From: Changhuang Liang <changhuang.liang@starfivetech.com>
To: Michael Turquette <mturquette@baylibre.com>,
Brian Masney <bmasney@redhat.com>,
Jerome Brunet <jbrunet+clk@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
Emil Renner Berthing <kernel@esmil.dk>,
Kees Cook <kees@kernel.org>,
"Gustavo A . R . Silva" <gustavoars@kernel.org>,
Richard Cochran <richardcochran@gmail.com>
Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-hardening@vger.kernel.org, netdev@vger.kernel.org,
Hal Feng <hal.feng@starfivetech.com>,
Changhuang Liang <changhuang.liang@starfivetech.com>
Subject: [PATCH v5 12/23] clk: starfive: Introduce idiv ops for inverted divider clocks
Date: Wed, 30 Sep 2026 05:43:06 -0700 [thread overview]
Message-ID: <20260930124317.5648-13-changhuang.liang@starfivetech.com> (raw)
In-Reply-To: <20260930124317.5648-1-changhuang.liang@starfivetech.com>
Some StarFive clocks only advertise the divider and invert capabilities
(via JH71X0_CLK_INVERT, without ENABLE). Add the JH71X0_IDIV() macro
to declare such clocks, and jh71x0_clk_idiv_ops, which combines the
divider rate operations with get_phase/set_phase.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/clk/starfive/clk-starfive-jh71x0.c | 12 ++++++++++++
drivers/clk/starfive/clk-starfive-jh71x0.h | 8 ++++++++
2 files changed, 20 insertions(+)
diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.c b/drivers/clk/starfive/clk-starfive-jh71x0.c
index bb7706ede1a6..1f98f1f8f0a5 100644
--- a/drivers/clk/starfive/clk-starfive-jh71x0.c
+++ b/drivers/clk/starfive/clk-starfive-jh71x0.c
@@ -302,6 +302,15 @@ static const struct clk_ops jh71x0_clk_inv_ops = {
.debug_init = jh71x0_clk_debug_init,
};
+static const struct clk_ops jh71x0_clk_idiv_ops = {
+ .get_phase = jh71x0_clk_get_phase,
+ .set_phase = jh71x0_clk_set_phase,
+ .recalc_rate = jh71x0_clk_recalc_rate,
+ .determine_rate = jh71x0_clk_determine_rate,
+ .set_rate = jh71x0_clk_set_rate,
+ .debug_init = jh71x0_clk_debug_init,
+};
+
const struct clk_ops *starfive_jh71x0_clk_ops(u32 max)
{
if (max & JH71X0_CLK_DIV_MASK) {
@@ -312,6 +321,9 @@ const struct clk_ops *starfive_jh71x0_clk_ops(u32 max)
}
if (max & JH71X0_CLK_ENABLE)
return &jh71x0_clk_gdiv_ops;
+ else if (max & JH71X0_CLK_INVERT)
+ return &jh71x0_clk_idiv_ops;
+
if (max == JH71X0_CLK_FRAC_MAX)
return &jh71x0_clk_fdiv_ops;
return &jh71x0_clk_div_ops;
diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.h b/drivers/clk/starfive/clk-starfive-jh71x0.h
index 2a1f0fb4cbb1..4cb3c2ef9525 100644
--- a/drivers/clk/starfive/clk-starfive-jh71x0.h
+++ b/drivers/clk/starfive/clk-starfive-jh71x0.h
@@ -104,6 +104,14 @@ struct jh71x0_clk_data {
.parents = { [0] = _parent }, \
}
+#define JH71X0_IDIV(_idx, _name, _flags, _max, _parent) \
+[_idx] = { \
+ .name = _name, \
+ .flags = _flags, \
+ .max = JH71X0_CLK_INVERT | (_max), \
+ .parents = { [0] = _parent }, \
+}
+
struct jh71x0_clk {
struct clk_hw hw;
unsigned int idx;
--
2.25.1
next prev parent reply other threads:[~2026-09-30 12:44 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-30 12:42 [PATCH v5 00/23] Add basic clocks and resets for JHB100 SoC Changhuang Liang
2026-09-30 12:42 ` [PATCH v5 01/23] clk: starfive: jh7110-sys: Fix memory leak in reset controller register Changhuang Liang
2026-09-30 12:42 ` [PATCH v5 02/23] clk: starfive: JH71x0: Move reset controller registration to jh71x0 common code Changhuang Liang
2026-09-30 12:42 ` [PATCH v5 03/23] reset: starfive: jh7110: Match auxiliary device names to jh71x0 clk driver Changhuang Liang
2026-09-30 12:42 ` [PATCH v5 04/23] clk: starfive: jh71x0: Add generic CRG probe helper Changhuang Liang
2026-09-30 12:42 ` [PATCH v5 05/23] dt-bindings: clock: Add StarFive JHB100 System-0 clock and reset generator Changhuang Liang
2026-09-30 12:43 ` [PATCH v5 06/23] clk: starfive: Add JHB100 System-0 clock generator driver Changhuang Liang
2026-09-30 12:43 ` [PATCH v5 07/23] dt-bindings: clock: Add StarFive JHB100 System-1 clock and reset generator Changhuang Liang
2026-09-30 12:43 ` [PATCH v5 08/23] clk: starfive: Add JHB100 System-1 clock generator driver Changhuang Liang
2026-09-30 12:43 ` [PATCH v5 09/23] dt-bindings: clock: Add StarFive JHB100 System-2 clock and reset generator Changhuang Liang
2026-09-30 12:43 ` [PATCH v5 10/23] clk: starfive: Add JHB100 System-2 clock generator driver Changhuang Liang
2026-09-30 12:43 ` [PATCH v5 11/23] dt-bindings: clock: Add StarFive JHB100 Peripheral-0 clock and reset generator Changhuang Liang
2026-09-30 12:43 ` Changhuang Liang [this message]
2026-09-30 12:43 ` [PATCH v5 13/23] clk: starfive: Expand the storage of clock parent index Changhuang Liang
2026-09-30 12:43 ` [PATCH v5 14/23] clk: starfive: Add StarFive JHB100 Peripheral-0 clock driver Changhuang Liang
2026-09-30 12:43 ` [PATCH v5 15/23] dt-bindings: clock: Add StarFive JHB100 Peripheral-1 clock and reset generator Changhuang Liang
2026-09-30 12:43 ` [PATCH v5 16/23] clk: starfive: Add StarFive JHB100 Peripheral-1 clock driver Changhuang Liang
2026-09-30 12:43 ` [PATCH v5 17/23] dt-bindings: clock: Add StarFive JHB100 Peripheral-2 clock and reset generator Changhuang Liang
2026-09-30 12:43 ` [PATCH v5 18/23] clk: starfive: Add StarFive JHB100 Peripheral-2 clock driver Changhuang Liang
2026-09-30 12:43 ` [PATCH v5 19/23] dt-bindings: clock: Add StarFive JHB100 Peripheral-3 clock and reset generator Changhuang Liang
2026-09-30 12:43 ` [PATCH v5 20/23] clk: starfive: Add StarFive JHB100 Peripheral-3 clock driver Changhuang Liang
2026-09-30 12:43 ` [PATCH v5 21/23] reset: starfive: jh71x0: Support discontiguous reset IDs Changhuang Liang
2026-09-30 12:43 ` [PATCH v5 22/23] reset: starfive: Add StarFive JHB100 reset driver Changhuang Liang
2026-09-30 12:43 ` [PATCH v5 23/23] riscv: dts: starfive: jhb100: Add clocks and resets nodes Changhuang Liang
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