From: Changhuang Liang <changhuang.liang@starfivetech.com>
To: Michael Turquette <mturquette@baylibre.com>,
Brian Masney <bmasney@redhat.com>,
Jerome Brunet <jbrunet+clk@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>,
Emil Renner Berthing <kernel@esmil.dk>,
Kees Cook <kees@kernel.org>,
"Gustavo A . R . Silva" <gustavoars@kernel.org>,
Richard Cochran <richardcochran@gmail.com>
Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-hardening@vger.kernel.org, netdev@vger.kernel.org,
Hal Feng <hal.feng@starfivetech.com>,
Changhuang Liang <changhuang.liang@starfivetech.com>
Subject: [PATCH v5 22/23] reset: starfive: Add StarFive JHB100 reset driver
Date: Wed, 30 Sep 2026 05:43:16 -0700 [thread overview]
Message-ID: <20260930124317.5648-23-changhuang.liang@starfivetech.com> (raw)
In-Reply-To: <20260930124317.5648-1-changhuang.liang@starfivetech.com>
Add auxiliary reset driver to support StarFive JHB100 SoC.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
MAINTAINERS | 6 +
drivers/reset/starfive/Kconfig | 9 +
drivers/reset/starfive/Makefile | 1 +
.../reset/starfive/reset-starfive-jhb100.c | 302 ++++++++++++++++++
4 files changed, 318 insertions(+)
create mode 100644 drivers/reset/starfive/reset-starfive-jhb100.c
diff --git a/MAINTAINERS b/MAINTAINERS
index d22078bcf488..60ced2810e0d 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -26236,6 +26236,12 @@ S: Supported
F: Documentation/devicetree/bindings/interrupt-controller/starfive,jhb100-intc.yaml
F: drivers/irqchip/irq-starfive-jhb100-intc.c
+STARFIVE JHB100 RESET CONTROLLER DRIVERS
+M: Changhuang Liang <changhuang.liang@starfivetech.com>
+S: Supported
+F: drivers/reset/starfive/reset-starfive-jhb1*
+F: include/dt-bindings/reset/starfive,jhb1*.h
+
STATIC BRANCH/CALL
M: Peter Zijlstra <peterz@infradead.org>
M: Josh Poimboeuf <jpoimboe@kernel.org>
diff --git a/drivers/reset/starfive/Kconfig b/drivers/reset/starfive/Kconfig
index d832339f61bc..84baefbaee14 100644
--- a/drivers/reset/starfive/Kconfig
+++ b/drivers/reset/starfive/Kconfig
@@ -19,3 +19,12 @@ config RESET_STARFIVE_JH7110
default ARCH_STARFIVE
help
This enables the reset controller driver for the StarFive JH7110 SoC.
+
+config RESET_STARFIVE_JHB100
+ bool "StarFive JHB100 Reset Driver"
+ depends on CLK_STARFIVE_JH71X0 || COMPILE_TEST
+ select AUXILIARY_BUS
+ select RESET_STARFIVE_JH71X0
+ default ARCH_STARFIVE
+ help
+ This enables the reset controller driver for the StarFive JHB100 SoC.
diff --git a/drivers/reset/starfive/Makefile b/drivers/reset/starfive/Makefile
index 7a44b66fb9d5..d781103355d3 100644
--- a/drivers/reset/starfive/Makefile
+++ b/drivers/reset/starfive/Makefile
@@ -3,3 +3,4 @@ obj-$(CONFIG_RESET_STARFIVE_JH71X0) += reset-starfive-jh71x0.o
obj-$(CONFIG_RESET_STARFIVE_JH7100) += reset-starfive-jh7100.o
obj-$(CONFIG_RESET_STARFIVE_JH7110) += reset-starfive-jh7110.o
+obj-$(CONFIG_RESET_STARFIVE_JHB100) += reset-starfive-jhb100.o
diff --git a/drivers/reset/starfive/reset-starfive-jhb100.c b/drivers/reset/starfive/reset-starfive-jhb100.c
new file mode 100644
index 000000000000..87a93149609a
--- /dev/null
+++ b/drivers/reset/starfive/reset-starfive-jhb100.c
@@ -0,0 +1,302 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Reset driver for the StarFive JHB100 SoC
+ *
+ * Copyright (C) 2024 StarFive Technology Co., Ltd.
+ *
+ * Author: Changhuang Liang <changhuang.liang@starfivetech.com>
+ */
+
+#include <dt-bindings/reset/starfive,jhb100-crg.h>
+#include <linux/auxiliary_bus.h>
+#include <soc/starfive/reset-starfive-jh71x0.h>
+
+#include "reset-starfive-jh71x0.h"
+
+#define NUM_RESETS(x) ((x) + 1)
+
+static const struct jh71x0_reset_map jhb100_sys0_map[] = {
+ { JHB100_SYS0RST_RESOURCE_ARB, 0 },
+ { JHB100_SYS0RST_SYS0_IOMUX_PRESETN, 3 },
+ { JHB100_SYS0RST_SYS0H_IOMUX_PRESETN, 4 },
+ { JHB100_SYS0RST_RST_ADAPTOR_TIMEOUT_RSTN, 5 },
+ { JHB100_SYS0RST_BMCPCIERP_RSTN_BUS, 14 },
+ { JHB100_SYS0RST_BMCPCIERP_RSTN_CRG, 15 },
+ { JHB100_SYS0RST_HOSTSS0_RSTN_BUS_ESPI, 16 },
+ { JHB100_SYS0RST_HOSTSS0_RSTN_BUS_PCIE, 17 },
+ { JHB100_SYS0RST_HOSTSS0_RSTN_CRG, 18 },
+ { JHB100_SYS0RST_BMCPERIPH2_RSTN_CRG, 19 },
+ { JHB100_SYS0RST_BMCPERIPH2_RSTN_BUS, 20 },
+ { JHB100_SYS0RST_VCE_RSTN_CRG, 21 },
+ { JHB100_SYS0RST_VCE_RSTN_BUS, 22 },
+ { JHB100_SYS0RST_BMCUSB_RSTN_BUS, 23 },
+ { JHB100_SYS0RST_BMCUSB_RSTN_CRG, 24 },
+};
+
+static const struct jh71x0_reset_info jhb100_sys0_info = {
+ .nr_resets = ARRAY_SIZE(jhb100_sys0_map),
+ .assert_offset = 0x12c,
+ .status_offset = 0x130,
+ .discontiguous = true,
+ .map = jhb100_sys0_map,
+};
+
+static const struct jh71x0_reset_map jhb100_sys1_map[] = {
+ { JHB100_SYS1RST_SYS1_IOMUX_PRESETN, 1 },
+ { JHB100_SYS1RST_MAIN_RSTN_CHIPTOP_SENSOR, 5 },
+ { JHB100_SYS1RST_VOUT_RSTN_HOST0, 8 },
+ { JHB100_SYS1RST_VOUT_RSTN_HOST1, 9 },
+ { JHB100_SYS1RST_HOSTSS1_RSTN_BUS_ESPI, 10 },
+ { JHB100_SYS1RST_HOSTSS1_RSTN_BUS_PCIE, 11 },
+ { JHB100_SYS1RST_HOSTSS1_RSTN_CRG, 12 },
+ { JHB100_SYS1RST_BMCPERIPH3_RSTN_CRG, 13 },
+ { JHB100_SYS1RST_BMCPERIPH3_RSTN_BUS, 14 },
+};
+
+static const struct jh71x0_reset_info jhb100_sys1_info = {
+ .nr_resets = ARRAY_SIZE(jhb100_sys1_map),
+ .assert_offset = 0x54,
+ .status_offset = 0x58,
+ .discontiguous = true,
+ .map = jhb100_sys1_map,
+};
+
+static const struct jh71x0_reset_map jhb100_sys2_map[] = {
+ { JHB100_SYS2RST_JTAG0_MST_WRAP_HRESETN, 2 },
+ { JHB100_SYS2RST_JTAG0_MST_WRAP_APB_PRESETN, 3 },
+ { JHB100_SYS2RST_JTAG1_MST_WRAP_HRESETN, 4 },
+ { JHB100_SYS2RST_JTAG1_MST_WRAP_APB_PRESETN, 5 },
+ { JHB100_SYS2RST_HUSBCMN_HOSTCMN_RSTN_BUS_NCNOC_INIT, 8 },
+ { JHB100_SYS2RST_HUSBCMN_RSTN_HOSTCMN_CRG, 9 },
+ { JHB100_SYS2RST_HUSBCMN_HOSTUSB0_RSTN_BUS_NCNOC_BMC_TARG, 10 },
+ { JHB100_SYS2RST_HUSBCMN_HOSTUSB0_RSTN_BUS_NCNOC_HOST_TARG, 11 },
+ { JHB100_SYS2RST_HUSBCMN_RSTN_BMC_CRG, 12 },
+ { JHB100_SYS2RST_HUSBCMN_RSTN_HOSTUSB0_CRG, 13 },
+ { JHB100_SYS2RST_HUSBCMN_HOSTUSB1_RSTN_BUS_NCNOC_BMC_TARG, 14 },
+ { JHB100_SYS2RST_HUSBCMN_HOSTUSB1_RSTN_BUS_NCNOC_HOST_TARG, 15 },
+ { JHB100_SYS2RST_HUSBCMN_RSTN_HOSTUSB1_CRG, 16 },
+ { JHB100_SYS2RST_BMCPERIPH1_RSTN_CRG, 17 },
+ { JHB100_SYS2RST_BMCPERIPH1_RSTN_BUS, 18 },
+ { JHB100_SYS2RST_BMCPERIPH0_RSTN_CRG, 19 },
+ { JHB100_SYS2RST_BMCPERIPH0_RSTN_BUS, 20 },
+ { JHB100_SYS2RST_GPU0_RSTN_CRG, 21 },
+ { JHB100_SYS2RST_GPU0_RSTN_BUS, 22 },
+ { JHB100_SYS2RST_GPU0_HOST_PCIE_RST_N, 23 },
+ { JHB100_SYS2RST_GPU1_RSTN_CRG, 24 },
+ { JHB100_SYS2RST_GPU1_RSTN_BUS, 25 },
+ { JHB100_SYS2RST_GPU1_HOST_PCIE_RST_N, 26 },
+};
+static const struct jh71x0_reset_info jhb100_sys2_info = {
+ .nr_resets = ARRAY_SIZE(jhb100_sys2_map),
+ .assert_offset = 0x88,
+ .status_offset = 0x8c,
+ .discontiguous = true,
+ .map = jhb100_sys2_map,
+};
+
+static const struct jh71x0_reset_map jhb100_per0_map[] = {
+ { JHB100_PER0RST_MAIN_RSTN_UART4, 1 },
+ { JHB100_PER0RST_MAIN_RSTN_UART5, 2 },
+ { JHB100_PER0RST_MAIN_RSTN_UART6, 3 },
+ { JHB100_PER0RST_MAIN_RSTN_UART7, 4 },
+ { JHB100_PER0RST_MAIN_RSTN_UART8, 5 },
+ { JHB100_PER0RST_MAIN_RSTN_UART9, 6 },
+ { JHB100_PER0RST_MAIN_RSTN_UART10, 7 },
+ { JHB100_PER0RST_MAIN_RSTN_UART11, 8 },
+ { JHB100_PER0RST_MAIN_RSTN_UART12, 9 },
+ { JHB100_PER0RST_MAIN_RSTN_UART13, 10 },
+ { JHB100_PER0RST_MAIN_RSTN_UART14, 11 },
+ { JHB100_PER0RST_MAIN_RSTN_I2C0, 12 },
+ { JHB100_PER0RST_MAIN_RSTN_I2C1, 13 },
+ { JHB100_PER0RST_MAIN_RSTN_I2C2, 14 },
+ { JHB100_PER0RST_MAIN_RSTN_I2C3, 15 },
+ { JHB100_PER0RST_MAIN_RSTN_I2C4, 16 },
+ { JHB100_PER0RST_MAIN_RSTN_I2C5, 17 },
+ { JHB100_PER0RST_MAIN_RSTN_I2C6, 18 },
+ { JHB100_PER0RST_MAIN_RSTN_I2C7, 19 },
+ { JHB100_PER0RST_MAIN_RSTN_I2C8, 20 },
+ { JHB100_PER0RST_MAIN_RSTN_I2C9, 21 },
+ { JHB100_PER0RST_MAIN_RSTN_I2C10, 22 },
+ { JHB100_PER0RST_MAIN_RSTN_I2C11, 23 },
+ { JHB100_PER0RST_MAIN_RSTN_I2C12, 24 },
+ { JHB100_PER0RST_MAIN_RSTN_I2C13, 25 },
+ { JHB100_PER0RST_MAIN_RSTN_I2C14, 26 },
+ { JHB100_PER0RST_MAIN_RSTN_I2C15, 27 },
+ { JHB100_PER0RST_MAIN_RSTN_I3C0, 28 },
+ { JHB100_PER0RST_MAIN_RSTN_I3C1, 29 },
+ { JHB100_PER0RST_MAIN_RSTN_I3C2, 30 },
+ { JHB100_PER0RST_MAIN_RSTN_I3C3, 31 },
+ { JHB100_PER0RST_MAIN_RSTN_I3C4, 32 },
+ { JHB100_PER0RST_MAIN_RSTN_I3C5, 33 },
+ { JHB100_PER0RST_MAIN_RSTN_I3C6, 34 },
+ { JHB100_PER0RST_MAIN_RSTN_I3C7, 35 },
+ { JHB100_PER0RST_MAIN_RSTN_I3C8, 36 },
+ { JHB100_PER0RST_MAIN_RSTN_I3C9, 37 },
+ { JHB100_PER0RST_MAIN_RSTN_I3C10, 38 },
+ { JHB100_PER0RST_MAIN_RSTN_I3C11, 39 },
+ { JHB100_PER0RST_MAIN_RSTN_I3C12, 40 },
+ { JHB100_PER0RST_MAIN_RSTN_I3C13, 41 },
+ { JHB100_PER0RST_MAIN_RSTN_I3C14, 42 },
+ { JHB100_PER0RST_MAIN_RSTN_I3C15, 43 },
+ { JHB100_PER0RST_MAIN_RSTN_WDT0, 44 },
+ { JHB100_PER0RST_MAIN_RSTN_WDT1, 45 },
+ { JHB100_PER0RST_MAIN_RSTN_WDT2, 46 },
+ { JHB100_PER0RST_MAIN_RSTN_WDT3, 47 },
+ { JHB100_PER0RST_MAIN_RSTN_WDT4, 48 },
+ { JHB100_PER0RST_MAIN_RSTN_DUALTIMER0, 49 },
+ { JHB100_PER0RST_MAIN_RSTN_DUALTIMER1, 50 },
+ { JHB100_PER0RST_MAIN_RSTN_DUALTIMER2, 51 },
+ { JHB100_PER0RST_MAIN_RSTN_TRNG, 52 },
+ { JHB100_PER0RST_MAIN_RSTN_DMAC0, 53 },
+ { JHB100_PER0RST_MAIN_RSTN_DMAC1, 54 },
+ { JHB100_PER0RST_MAIN_RSTN_DMAC2, 55 },
+ { JHB100_PER0RST_MAIN_RSTN_LTPI0, 56 },
+ { JHB100_PER0RST_MAIN_RSTN_LTPI1, 57 },
+ { JHB100_PER0RST_MAIN_RSTN_SOL4, 58 },
+ { JHB100_PER0RST_MAIN_RSTN_SOL5, 59 },
+ { JHB100_PER0RST_MAIN_RSTN_SOL6, 60 },
+ { JHB100_PER0RST_MAIN_RSTN_SOL7, 61 },
+ { JHB100_PER0RST_MAIN_RSTN_SOL8, 62 },
+ { JHB100_PER0RST_MAIN_RSTN_SOL9, 63 },
+ { JHB100_PER0RST_MAIN_RSTN_SOL10, 64 },
+ { JHB100_PER0RST_MAIN_RSTN_SOL11, 65 },
+ { JHB100_PER0RST_MAIN_RSTN_SOL12, 66 },
+ { JHB100_PER0RST_MAIN_RSTN_SOL13, 67 },
+ { JHB100_PER0RST_MAIN_RSTN_SOL14, 68 },
+ { JHB100_PER0RST_MAIN_RSTN_LDO0, 69 },
+ { JHB100_PER0RST_MAIN_RSTN_LDO1, 70 },
+ { JHB100_PER0RST_MAIN_RSTN_PERIPH0_SENSORS, 71 },
+ { JHB100_PER0RST_MAIN_RSTN_DMAC0_SENSORS, 72 },
+ { JHB100_PER0RST_SYSCON_PRESETN, 73 },
+ { JHB100_PER0RST_GPIO_IOMUX_PRESETN, 74 },
+ { JHB100_PER0RST_UART_MUX_REG_WRAP, 75 },
+};
+
+static const struct jh71x0_reset_info jhb100_per0_info = {
+ .nr_resets = ARRAY_SIZE(jhb100_per0_map),
+ .assert_offset = 0x554,
+ .status_offset = 0x560,
+ .discontiguous = true,
+ .map = jhb100_per0_map,
+};
+
+static const struct jh71x0_reset_map jhb100_per1_map[] = {
+ { JHB100_PER1RST_IOMUX_PRESETN, 0 },
+ { JHB100_PER1RST_SYSCON_PRESETN, 1 },
+ { JHB100_PER1RST_MAIN_RSTN_SFC0, 2 },
+ { JHB100_PER1RST_MAIN_RSTN_SFC1, 3 },
+ { JHB100_PER1RST_MAIN_RSTN_SFC2, 4 },
+ { JHB100_PER1RST_MAIN_RSTN_SPI0, 5 },
+ { JHB100_PER1RST_MAIN_RSTN_PERIPH1_SENSORS, 6 },
+ { JHB100_PER1RST_MAIN_RSTN_SGPIO0, 7 },
+ { JHB100_PER1RST_MAIN_RSTN_SGPIO1, 8 },
+ { JHB100_PER1RST_MAIN_RSTN_EMMC0, 9 },
+ { JHB100_PER1RST_MAIN_RSTN_UFS, 11 },
+ { JHB100_PER1RST_MAIN_RSTN_UFS_PHY, 12 },
+ { JHB100_PER1RST_MAIN_RSTN_DMAC_SFC0, 13 },
+ { JHB100_PER1RST_MAIN_RSTN_DMAC_SFC1, 14 },
+ { JHB100_PER1RST_MAIN_RSTN_DMAC_SFC2, 15 },
+ { JHB100_PER1RST_MAIN_RSTN_DMAC_SPI0, 16 },
+ { JHB100_PER1RST_MAIN_RSTN_PERIPH1_RAS, 17 },
+};
+
+static const struct jh71x0_reset_info jhb100_per1_info = {
+ .nr_resets = ARRAY_SIZE(jhb100_per1_map),
+ .assert_offset = 0x134,
+ .status_offset = 0x138,
+ .discontiguous = true,
+ .map = jhb100_per1_map,
+};
+
+static const struct jh71x0_reset_map jhb100_per2_map[] = {
+ { JHB100_PER2RST_IOMUX_PRESETN, 0 },
+ { JHB100_PER2RST_POK_IOMUX_PRESETN, 1 },
+ { JHB100_PER2RST_SYSREG_RSTN, 2 },
+ { JHB100_PER2RST_MAIN_RSTN_CAN0, 3 },
+ { JHB100_PER2RST_MAIN_RSTN_CAN1, 4 },
+ { JHB100_PER2RST_FAN_TACH_PRESETN, 5 },
+ { JHB100_PER2RST_MAIN_RSTN_GMAC2, 7 },
+ { JHB100_PER2RST_MAIN_RSTN_GMAC3, 8 },
+ { JHB100_PER2RST_MAIN_RSTN_DMAC_8CH, 9 },
+ { JHB100_PER2RST_MAIN_RSTN_RTC, 10 },
+ { JHB100_PER2RST_ADC0_PRESETN, 11 },
+ { JHB100_PER2RST_ADC0_IOMUX_PRESETN, 12 },
+ { JHB100_PER2RST_ADC1_PRESETN, 13 },
+ { JHB100_PER2RST_ADC1_IOMUX_PRESETN, 14 },
+ { JHB100_PER2RST_MAIN_RSTN_PERIPH2_SENSORS, 15 },
+};
+
+static const struct jh71x0_reset_info jhb100_per2_info = {
+ .nr_resets = ARRAY_SIZE(jhb100_per2_map),
+ .assert_offset = 0x11c,
+ .status_offset = 0x120,
+ .discontiguous = true,
+ .map = jhb100_per2_map,
+};
+
+static const struct jh71x0_reset_info jhb100_per3_info = {
+ .nr_resets = NUM_RESETS(JHB100_PER3RST_IOMUX_PRESETN),
+ .assert_offset = 0x98,
+ .status_offset = 0x9c,
+ .discontiguous = false,
+};
+
+static int jhb100_reset_probe(struct auxiliary_device *adev,
+ const struct auxiliary_device_id *id)
+{
+ const struct jh71x0_reset_info *info =
+ (const struct jh71x0_reset_info *)(id->driver_data);
+ struct jh71x0_reset_adev *rdev = to_jh71x0_reset_adev(adev);
+ void __iomem *base = rdev->base;
+
+ if (!info || !base)
+ return -ENODEV;
+
+ return reset_starfive_jh71x0_register_with_info(&adev->dev, adev->dev.parent->of_node,
+ base + info->assert_offset,
+ base + info->status_offset,
+ NULL, info, NULL);
+}
+
+static const struct auxiliary_device_id jhb100_reset_ids[] = {
+ {
+ .name = "clk_starfive_jh71x0.jhb100-r-sys0",
+ .driver_data = (kernel_ulong_t)&jhb100_sys0_info,
+ },
+ {
+ .name = "clk_starfive_jh71x0.jhb100-r-sys1",
+ .driver_data = (kernel_ulong_t)&jhb100_sys1_info,
+ },
+ {
+ .name = "clk_starfive_jh71x0.jhb100-r-sys2",
+ .driver_data = (kernel_ulong_t)&jhb100_sys2_info,
+ },
+ {
+ .name = "clk_starfive_jh71x0.jhb100-r-per0",
+ .driver_data = (kernel_ulong_t)&jhb100_per0_info,
+ },
+ {
+ .name = "clk_starfive_jh71x0.jhb100-r-per1",
+ .driver_data = (kernel_ulong_t)&jhb100_per1_info,
+ },
+ {
+ .name = "clk_starfive_jh71x0.jhb100-r-per2",
+ .driver_data = (kernel_ulong_t)&jhb100_per2_info,
+ },
+ {
+ .name = "clk_starfive_jh71x0.jhb100-r-per3",
+ .driver_data = (kernel_ulong_t)&jhb100_per3_info,
+ },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(auxiliary, jhb100_reset_ids);
+
+static struct auxiliary_driver jhb100_reset_driver = {
+ .probe = jhb100_reset_probe,
+ .id_table = jhb100_reset_ids,
+};
+module_auxiliary_driver(jhb100_reset_driver);
+
+MODULE_AUTHOR("Changhuang Liang <changhuang.liang@starfivetech.com>");
+MODULE_DESCRIPTION("StarFive JHB100 reset driver");
+MODULE_LICENSE("GPL");
--
2.25.1
next prev parent reply other threads:[~2026-09-30 12:44 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-30 12:42 [PATCH v5 00/23] Add basic clocks and resets for JHB100 SoC Changhuang Liang
2026-09-30 12:42 ` [PATCH v5 01/23] clk: starfive: jh7110-sys: Fix memory leak in reset controller register Changhuang Liang
2026-09-30 12:42 ` [PATCH v5 02/23] clk: starfive: JH71x0: Move reset controller registration to jh71x0 common code Changhuang Liang
2026-09-30 12:42 ` [PATCH v5 03/23] reset: starfive: jh7110: Match auxiliary device names to jh71x0 clk driver Changhuang Liang
2026-09-30 12:42 ` [PATCH v5 04/23] clk: starfive: jh71x0: Add generic CRG probe helper Changhuang Liang
2026-09-30 12:42 ` [PATCH v5 05/23] dt-bindings: clock: Add StarFive JHB100 System-0 clock and reset generator Changhuang Liang
2026-09-30 12:43 ` [PATCH v5 06/23] clk: starfive: Add JHB100 System-0 clock generator driver Changhuang Liang
2026-09-30 12:43 ` [PATCH v5 07/23] dt-bindings: clock: Add StarFive JHB100 System-1 clock and reset generator Changhuang Liang
2026-09-30 12:43 ` [PATCH v5 08/23] clk: starfive: Add JHB100 System-1 clock generator driver Changhuang Liang
2026-09-30 12:43 ` [PATCH v5 09/23] dt-bindings: clock: Add StarFive JHB100 System-2 clock and reset generator Changhuang Liang
2026-09-30 12:43 ` [PATCH v5 10/23] clk: starfive: Add JHB100 System-2 clock generator driver Changhuang Liang
2026-09-30 12:43 ` [PATCH v5 11/23] dt-bindings: clock: Add StarFive JHB100 Peripheral-0 clock and reset generator Changhuang Liang
2026-09-30 12:43 ` [PATCH v5 12/23] clk: starfive: Introduce idiv ops for inverted divider clocks Changhuang Liang
2026-09-30 12:43 ` [PATCH v5 13/23] clk: starfive: Expand the storage of clock parent index Changhuang Liang
2026-09-30 12:43 ` [PATCH v5 14/23] clk: starfive: Add StarFive JHB100 Peripheral-0 clock driver Changhuang Liang
2026-09-30 12:43 ` [PATCH v5 15/23] dt-bindings: clock: Add StarFive JHB100 Peripheral-1 clock and reset generator Changhuang Liang
2026-09-30 12:43 ` [PATCH v5 16/23] clk: starfive: Add StarFive JHB100 Peripheral-1 clock driver Changhuang Liang
2026-09-30 12:43 ` [PATCH v5 17/23] dt-bindings: clock: Add StarFive JHB100 Peripheral-2 clock and reset generator Changhuang Liang
2026-09-30 12:43 ` [PATCH v5 18/23] clk: starfive: Add StarFive JHB100 Peripheral-2 clock driver Changhuang Liang
2026-09-30 12:43 ` [PATCH v5 19/23] dt-bindings: clock: Add StarFive JHB100 Peripheral-3 clock and reset generator Changhuang Liang
2026-09-30 12:43 ` [PATCH v5 20/23] clk: starfive: Add StarFive JHB100 Peripheral-3 clock driver Changhuang Liang
2026-09-30 12:43 ` [PATCH v5 21/23] reset: starfive: jh71x0: Support discontiguous reset IDs Changhuang Liang
2026-09-30 12:43 ` Changhuang Liang [this message]
2026-09-30 12:43 ` [PATCH v5 23/23] riscv: dts: starfive: jhb100: Add clocks and resets nodes Changhuang Liang
2026-09-30 22:43 ` [PATCH v5 00/23] Add basic clocks and resets for JHB100 SoC Conor Dooley
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