From: Borislav Petkov <bp@alien8.de>
To: Paul Louvel <paul.louvel@bootlin.com>
Cc: Tony Luck <tony.luck@intel.com>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Magnus Damm <magnus.damm@gmail.com>,
linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
linux-edac@vger.kernel.org, devicetree@vger.kernel.org,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>,
Miquel Raynal <miquel.raynal@bootlin.com>,
Herve Codina <herve.codina@bootlin.com>,
Wolfram Sang <wsa+renesas@sang-engineering.com>
Subject: Re: [PATCH v5 1/3] dt-bindings: edac: cdns,ddr-edac: add Cadence DDR EDAC
Date: Mon, 5 Oct 2026 11:46:21 -0700 [thread overview]
Message-ID: <20261005184621.GCasPwfaQNE0q6zykP@fat_crate.local> (raw)
In-Reply-To: <20261005-paul-v7-3-rc1-edac-v5-1-140a0f124bc0@bootlin.com>
On Mon, Oct 05, 2026 at 02:49:22PM +0200, Paul Louvel wrote:
> Add the Cadence EDAC dt binding.
> The memory controller optionally supports ECC SECDED with DDR2/DDR3
> memory.
>
> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> Signed-off-by: Paul Louvel (Schneider Electric) <paul.louvel@bootlin.com>
> ---
> .../devicetree/bindings/edac/cdns,ddr-edac.yaml | 61 ++++++++++++++++++++++
> MAINTAINERS | 6 +++
> 2 files changed, 67 insertions(+)
Needs review by DT maintainers if it is going to go through the EDAC tree, see
output of:
./scripts/get_maintainer.pl -f Documentation/devicetree/bindings/edac/
--
Regards/Gruss,
Boris.
https://people.kernel.org/tglx/notes-about-netiquette
next prev parent reply other threads:[~2026-10-05 18:46 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-05 12:49 [PATCH v5 0/3] Add Renesas RZ/N1x EDAC driver Paul Louvel
2026-10-05 12:49 ` [PATCH v5 1/3] dt-bindings: edac: cdns,ddr-edac: add Cadence DDR EDAC Paul Louvel
2026-10-05 18:46 ` Borislav Petkov [this message]
2026-10-07 4:55 ` Paul Louvel
2026-10-06 15:53 ` Rob Herring (Arm)
2026-10-05 12:49 ` [PATCH v5 2/3] EDAC/cadence: Add Cadence DDR EDAC driver Paul Louvel
2026-10-07 2:11 ` Borislav Petkov
2026-10-07 4:52 ` Paul Louvel
2026-10-05 12:49 ` [PATCH v5 3/3] ARM: dts: renesas: r9a06g032: add EDAC node Paul Louvel
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