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From: "Paul Louvel" <paul.louvel@bootlin.com>
To: "Borislav Petkov" <bp@alien8.de>,
	"Paul Louvel" <paul.louvel@bootlin.com>
Cc: "Tony Luck" <tony.luck@intel.com>,
	"Rob Herring" <robh@kernel.org>,
	"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
	"Conor Dooley" <conor+dt@kernel.org>,
	"Geert Uytterhoeven" <geert+renesas@glider.be>,
	"Magnus Damm" <magnus.damm@gmail.com>,
	<linux-kernel@vger.kernel.org>,
	<linux-renesas-soc@vger.kernel.org>, <linux-edac@vger.kernel.org>,
	<devicetree@vger.kernel.org>,
	"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
	"Miquel Raynal" <miquel.raynal@bootlin.com>,
	"Herve Codina" <herve.codina@bootlin.com>,
	"Wolfram Sang" <wsa+renesas@sang-engineering.com>
Subject: Re: [PATCH v5 1/3] dt-bindings: edac: cdns,ddr-edac: add Cadence DDR EDAC
Date: Wed, 07 Oct 2026 06:55:09 +0200	[thread overview]
Message-ID: <DLYC6W4J0NRH.3T1EOLT37KM9S@bootlin.com> (raw)
In-Reply-To: <20261005184621.GCasPwfaQNE0q6zykP@fat_crate.local>

On Mon Oct 5, 2026 at 8:46 PM CEST, Borislav Petkov wrote:
> On Mon, Oct 05, 2026 at 02:49:22PM +0200, Paul Louvel wrote:
>> Add the Cadence EDAC dt binding.
>> The memory controller optionally supports ECC SECDED with DDR2/DDR3
>> memory.
>> 
>> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
>> Signed-off-by: Paul Louvel (Schneider Electric) <paul.louvel@bootlin.com>
>> ---
>>  .../devicetree/bindings/edac/cdns,ddr-edac.yaml    | 61 ++++++++++++++++++++++
>>  MAINTAINERS                                        |  6 +++
>>  2 files changed, 67 insertions(+)
>
> Needs review by DT maintainers if it is going to go through the EDAC tree, see
> output of:
>
> ./scripts/get_maintainer.pl -f Documentation/devicetree/bindings/edac/

ACK.
For some reason b4 did not included most of the people apart from Rob /
Krzysztof / Wolfram.

-- 
Paul Louvel, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com


  reply	other threads:[~2026-10-07  4:55 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-05 12:49 [PATCH v5 0/3] Add Renesas RZ/N1x EDAC driver Paul Louvel
2026-10-05 12:49 ` [PATCH v5 1/3] dt-bindings: edac: cdns,ddr-edac: add Cadence DDR EDAC Paul Louvel
2026-10-05 18:46   ` Borislav Petkov
2026-10-07  4:55     ` Paul Louvel [this message]
2026-10-06 15:53   ` Rob Herring (Arm)
2026-10-05 12:49 ` [PATCH v5 2/3] EDAC/cadence: Add Cadence DDR EDAC driver Paul Louvel
2026-10-07  2:11   ` Borislav Petkov
2026-10-07  4:52     ` Paul Louvel
2026-10-05 12:49 ` [PATCH v5 3/3] ARM: dts: renesas: r9a06g032: add EDAC node Paul Louvel

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