[PATCH RFC] dt-bindings: perf: riscv,pmu: Add interrupts-extended property

[PATCH RFC] dt-bindings: perf: riscv,pmu: Add interrupts-extended property

[Eric Lin]

The interrupts-extended property is used to specify the connection
between the PMU counter overflow interrupt and the corresponding CPU
local interrupt controller (riscv,cpu-intc).

This property also allows the software to associate a PMU node with a
specific CPU. To support future heterogeneous systems, where different
CPUs may support different PMU events, this property allows the driver
to identify the correct PMU capabilities for each hart.

Reviewed-by: Nick Hu <nick.hu@sifive.com>
Signed-off-by: Eric Lin <eric.lin@sifive.com>
---
 Documentation/devicetree/bindings/perf/riscv,pmu.yaml | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/Documentation/devicetree/bindings/perf/riscv,pmu.yaml b/Documentation/devicetree/bindings/perf/riscv,pmu.yaml
index d01c677ad3c7..13aceb3d42b9 100644
--- a/Documentation/devicetree/bindings/perf/riscv,pmu.yaml
+++ b/Documentation/devicetree/bindings/perf/riscv,pmu.yaml
@@ -34,6 +34,13 @@ properties:
   compatible:
     const: riscv,pmu
 
+  interrupts-extended:
+    minItems: 1
+    maxItems: 4095
+    description:
+      Specifies the interrupt-parent and local interrupt index for each CPU's
+      PMU counter overflow. Each item points to a riscv,cpu-intc node.
+
   riscv,event-to-mhpmevent:
     $ref: /schemas/types.yaml#/definitions/uint32-matrix
     description:
@@ -101,6 +108,7 @@ examples:
   - |
     pmu {
         compatible = "riscv,pmu";
+        interrupts-extended = <&cpu0_intc 13>;
         riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>;
         riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
                                       <0x00002 0x00002 0x00000004>,
@@ -127,6 +135,9 @@ examples:
      */
     pmu {
           compatible = "riscv,pmu";
+          interrupts-extended = <&cpu0_intc 13>,
+                                <&cpu1_intc 13>,<&cpu2_intc 13>,
+                                <&cpu3_intc 13>,<&cpu4_intc 13>;
           riscv,event-to-mhpmevent =
               /* SBI_PMU_HW_CACHE_REFERENCES -> Instruction or Data cache/ITIM busy */
               <0x00003 0x00000000 0x1801>,

---
base-commit: dc59e4fea9d83f03bad6bddf3fa2e52491777482
change-id: 20260701-pmu-dt-property-ff12b35fe0fc

Best regards,
--  
Eric Lin <eric.lin@sifive.com>

Re: [PATCH RFC] dt-bindings: perf: riscv,pmu: Add interrupts-extended property

[Conor Dooley]

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On Thu, Jul 02, 2026 at 05:04:31PM +0800, Eric Lin wrote:
> The interrupts-extended property is used to specify the connection
> between the PMU counter overflow interrupt and the corresponding CPU
> local interrupt controller (riscv,cpu-intc).
> 
> This property also allows the software to associate a PMU node with a
> specific CPU. To support future heterogeneous systems, where different
> CPUs may support different PMU events, this property allows the driver
> to identify the correct PMU capabilities for each hart.
> 
> Reviewed-by: Nick Hu <nick.hu@sifive.com>
> Signed-off-by: Eric Lin <eric.lin@sifive.com>

This has been sitting for ages, I was kinda waiting to see if there'd be
some feedback from the relevant maintainers (riscv pmu). Was there a
series sent to opensbi or elsewhere to implement support for these
devices?

Thanks,
Conor.

> ---
>  Documentation/devicetree/bindings/perf/riscv,pmu.yaml | 11 +++++++++++
>  1 file changed, 11 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/perf/riscv,pmu.yaml b/Documentation/devicetree/bindings/perf/riscv,pmu.yaml
> index d01c677ad3c7..13aceb3d42b9 100644
> --- a/Documentation/devicetree/bindings/perf/riscv,pmu.yaml
> +++ b/Documentation/devicetree/bindings/perf/riscv,pmu.yaml
> @@ -34,6 +34,13 @@ properties:
>    compatible:
>      const: riscv,pmu
>  
> +  interrupts-extended:
> +    minItems: 1
> +    maxItems: 4095
> +    description:
> +      Specifies the interrupt-parent and local interrupt index for each CPU's
> +      PMU counter overflow. Each item points to a riscv,cpu-intc node.
> +
>    riscv,event-to-mhpmevent:
>      $ref: /schemas/types.yaml#/definitions/uint32-matrix
>      description:
> @@ -101,6 +108,7 @@ examples:
>    - |
>      pmu {
>          compatible = "riscv,pmu";
> +        interrupts-extended = <&cpu0_intc 13>;
>          riscv,event-to-mhpmevent = <0x0000B 0x0000 0x0001>;
>          riscv,event-to-mhpmcounters = <0x00001 0x00001 0x00000001>,
>                                        <0x00002 0x00002 0x00000004>,
> @@ -127,6 +135,9 @@ examples:
>       */
>      pmu {
>            compatible = "riscv,pmu";
> +          interrupts-extended = <&cpu0_intc 13>,
> +                                <&cpu1_intc 13>,<&cpu2_intc 13>,
> +                                <&cpu3_intc 13>,<&cpu4_intc 13>;
>            riscv,event-to-mhpmevent =
>                /* SBI_PMU_HW_CACHE_REFERENCES -> Instruction or Data cache/ITIM busy */
>                <0x00003 0x00000000 0x1801>,
> 
> ---
> base-commit: dc59e4fea9d83f03bad6bddf3fa2e52491777482
> change-id: 20260701-pmu-dt-property-ff12b35fe0fc
> 
> Best regards,
> --  
> Eric Lin <eric.lin@sifive.com>
> 

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