* [PATCH v3 1/2] dt-bindings: arm: altera: add Agilex SoCDK multi-QSPI board
2026-10-08 8:10 [PATCH v3 0/2] arm64: dts: socfpga: agilex: add SoCDK multi-QSPI board genevieve.chan
@ 2026-10-08 8:10 ` genevieve.chan
2026-10-08 8:10 ` [PATCH v3 2/2] arm64: dts: socfpga: agilex: add " genevieve.chan
1 sibling, 0 replies; 4+ messages in thread
From: genevieve.chan @ 2026-10-08 8:10 UTC (permalink / raw)
To: Dinh Nguyen, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: devicetree, linux-kernel
From: Genevieve Chan <genevieve.chan@altera.com>
The Agilex SoCDK can be fitted with a multi-QSPI daughter card in
place of the default single-flash QSPI card. The multi-QSPI card
carries four Micron MT25QU02G flashes connected to the HPS QSPI
controller on chip selects 0-3.
The different flash population requires a separate board DTS, hence, add
a board compatible for it, following the existing SoCDK variants.
The board uses the Agilex SoC (marketed as Agilex 7 F-Series), so it
falls back to "intel,socfpga-agilex".
Signed-off-by: Genevieve Chan <genevieve.chan@altera.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
---
Changes in v3:
- Add Conor's Acked-by.
Changes in v2:
- Rename compatible from intel,socfpga-agilex7f-socdk-multiqspi to
intel,socfpga-agilex-socdk-multiqspi.
- Describe the hardware difference in the commit message.
Documentation/devicetree/bindings/arm/altera.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml
index 5fce1161210e..01f6323b9a6b 100644
--- a/Documentation/devicetree/bindings/arm/altera.yaml
+++ b/Documentation/devicetree/bindings/arm/altera.yaml
@@ -97,6 +97,7 @@ properties:
- intel,socfpga-agilex-n6000
- intel,socfpga-agilex-socdk
- intel,socfpga-agilex-socdk-emmc
+ - intel,socfpga-agilex-socdk-multiqspi
- const: intel,socfpga-agilex
- description: Agilex3 boards
--
2.43.7
^ permalink raw reply [flat|nested] 4+ messages in thread* [PATCH v3 2/2] arm64: dts: socfpga: agilex: add SoCDK multi-QSPI board
2026-10-08 8:10 [PATCH v3 0/2] arm64: dts: socfpga: agilex: add SoCDK multi-QSPI board genevieve.chan
2026-10-08 8:10 ` [PATCH v3 1/2] dt-bindings: arm: altera: add Agilex " genevieve.chan
@ 2026-10-08 8:10 ` genevieve.chan
2026-10-08 12:18 ` Dinh Nguyen
1 sibling, 1 reply; 4+ messages in thread
From: genevieve.chan @ 2026-10-08 8:10 UTC (permalink / raw)
To: Dinh Nguyen, Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: devicetree, linux-kernel
From: Genevieve Chan <genevieve.chan@altera.com>
Add a device tree for the Agilex SoCDK fitted with the multi-QSPI
daughter board. The daughter board replaces the single QSPI flash of
the default SoCDK with four Micron MT25QU02G flashes on chip selects
0-3, which allows the system to use up to 1 GiB of QSPI storage.
The board is otherwise identical to the SoCDK and builds on
socfpga_agilex.dtsi.
Signed-off-by: Genevieve Chan <genevieve.chan@altera.com>
---
Changes in v3:
- Reword subject to avoid repeating "Agilex".
- Move the DTS to arch/arm64/boot/dts/altera/, following the move of
the SoCFPGA device trees in for-next.
Changes in v2:
- Rename file, compatible and model to drop the "agilex7f" prefix.
- Reword commit message to describe the hardware.
arch/arm64/boot/dts/altera/Makefile | 1 +
.../altera/socfpga_agilex_socdk_multiqspi.dts | 213 ++++++++++++++++++
2 files changed, 214 insertions(+)
create mode 100644 arch/arm64/boot/dts/altera/socfpga_agilex_socdk_multiqspi.dts
diff --git a/arch/arm64/boot/dts/altera/Makefile b/arch/arm64/boot/dts/altera/Makefile
index 8f41349103b8..d38fe88a1cc8 100644
--- a/arch/arm64/boot/dts/altera/Makefile
+++ b/arch/arm64/boot/dts/altera/Makefile
@@ -2,6 +2,7 @@
dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_agilex_n6000.dtb \
socfpga_agilex_socdk.dtb \
socfpga_agilex_socdk_emmc.dtb \
+ socfpga_agilex_socdk_multiqspi.dtb \
socfpga_agilex_socdk_nand.dtb \
socfpga_agilex3_socdk.dtb \
socfpga_agilex5_socdk.dtb \
diff --git a/arch/arm64/boot/dts/altera/socfpga_agilex_socdk_multiqspi.dts b/arch/arm64/boot/dts/altera/socfpga_agilex_socdk_multiqspi.dts
new file mode 100644
index 000000000000..0bf087fa7553
--- /dev/null
+++ b/arch/arm64/boot/dts/altera/socfpga_agilex_socdk_multiqspi.dts
@@ -0,0 +1,213 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2026, Intel Corporation
+ */
+#include "socfpga_agilex.dtsi"
+
+/ {
+ model = "SoCFPGA Agilex SoCDK multi-QSPI daughter board";
+ compatible = "intel,socfpga-agilex-socdk-multiqspi", "intel,socfpga-agilex";
+
+ aliases {
+ serial0 = &uart0;
+ ethernet0 = &gmac0;
+ ethernet1 = &gmac1;
+ ethernet2 = &gmac2;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ leds {
+ compatible = "gpio-leds";
+ led0 {
+ label = "hps_led0";
+ gpios = <&portb 20 GPIO_ACTIVE_HIGH>;
+ };
+
+ led1 {
+ label = "hps_led1";
+ gpios = <&portb 19 GPIO_ACTIVE_HIGH>;
+ };
+
+ led2 {
+ label = "hps_led2";
+ gpios = <&portb 21 GPIO_ACTIVE_HIGH>;
+ };
+ };
+
+ memory@80000000 {
+ device_type = "memory";
+ /* We expect the bootloader to fill in the reg */
+ reg = <0 0x80000000 0 0>;
+ };
+};
+
+&gpio1 {
+ status = "okay";
+};
+
+&gmac0 {
+ status = "okay";
+ /* PHY delays are configured via skew properties */
+ phy-mode = "rgmii";
+ phy-handle = <&phy0>;
+
+ max-frame-size = <9000>;
+
+ mdio0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ phy0: ethernet-phy@4 {
+ reg = <4>;
+
+ txd0-skew-ps = <0>; /* -420ps */
+ txd1-skew-ps = <0>; /* -420ps */
+ txd2-skew-ps = <0>; /* -420ps */
+ txd3-skew-ps = <0>; /* -420ps */
+ rxd0-skew-ps = <420>; /* 0ps */
+ rxd1-skew-ps = <420>; /* 0ps */
+ rxd2-skew-ps = <420>; /* 0ps */
+ rxd3-skew-ps = <420>; /* 0ps */
+ txen-skew-ps = <0>; /* -420ps */
+ txc-skew-ps = <900>; /* 0ps */
+ rxdv-skew-ps = <420>; /* 0ps */
+ rxc-skew-ps = <1680>; /* 780ps */
+ };
+ };
+};
+
+&mmc {
+ status = "okay";
+ cap-sd-highspeed;
+ broken-cd;
+ bus-width = <4>;
+ clk-phase-sd-hs = <0>, <135>;
+};
+
+&osc1 {
+ clock-frequency = <25000000>;
+};
+
+&uart0 {
+ status = "okay";
+};
+
+&usb0 {
+ status = "okay";
+ disable-over-current;
+};
+
+&watchdog0 {
+ status = "okay";
+};
+
+&qspi {
+ status = "okay";
+
+ flash@0 {
+ compatible = "micron,mt25qu02g", "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <25000000>;
+
+ m25p,fast-read;
+ cdns,read-delay = <2>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ qspi_boot0: partition@0 {
+ label = "Boot and fpga data";
+ reg = <0x0 0x10000000>;
+ };
+ };
+ };
+
+ flash@1 {
+ compatible = "micron,mt25qu02g", "jedec,spi-nor";
+ reg = <1>;
+ spi-max-frequency = <25000000>;
+
+ m25p,fast-read;
+ cdns,read-delay = <2>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ qspi_boot1: partition@0 {
+ label = "Boot and fpga data";
+ reg = <0x0 0x10000000>;
+ };
+ };
+ };
+
+ flash@2 {
+ compatible = "micron,mt25qu02g", "jedec,spi-nor";
+ reg = <2>;
+ spi-max-frequency = <25000000>;
+
+ m25p,fast-read;
+ cdns,read-delay = <2>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ qspi_boot2: partition@0 {
+ label = "Boot and fpga data";
+ reg = <0x0 0x10000000>;
+ };
+ };
+ };
+
+ flash@3 {
+ compatible = "micron,mt25qu02g", "jedec,spi-nor";
+ reg = <3>;
+ spi-max-frequency = <25000000>;
+
+ m25p,fast-read;
+ cdns,read-delay = <2>;
+ cdns,tshsl-ns = <50>;
+ cdns,tsd2d-ns = <50>;
+ cdns,tchsh-ns = <4>;
+ cdns,tslch-ns = <4>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+
+ partitions {
+ compatible = "fixed-partitions";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ qspi_boot3: partition@0 {
+ label = "Boot and fpga data";
+ reg = <0x0 0x10000000>;
+ };
+ };
+ };
+};
--
2.43.7
^ permalink raw reply [flat|nested] 4+ messages in thread