From: fangyu.yu@linux.alibaba.com
To: tomasz.jeznach@linux.dev, joro@8bytes.org, will@kernel.org,
robin.murphy@arm.com, pjw@kernel.org, palmer@dabbelt.com,
aou@eecs.berkeley.edu, alex@ghiti.fr, jroedel@suse.de,
zong.li@sifive.com, andrew.jones@oss.qualcomm.com,
jgg@nvidia.com, jgg@ziepe.ca
Cc: fangyu.yu@linux.alibaba.com, guoren@kernel.org,
iommu@lists.linux.dev, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org
Subject: [RFC PATCH 2/3] iommu/riscv: Extract IRQ forwarding payload validation
Date: Thu, 8 Oct 2026 22:00:00 +0800 [thread overview]
Message-ID: <20261008140001.94508-3-fangyu.yu@linux.alibaba.com> (raw)
In-Reply-To: <20261008140001.94508-1-fangyu.yu@linux.alibaba.com>
From: Fangyu Yu <fangyu.yu@linux.alibaba.com>
Move the owner and MSI address mask/pattern checks from
riscv_iommu_ir_activate() into a separate helper so a second forwarding
backend can validate the same fields. No functional change.
Signed-off-by: Fangyu Yu <fangyu.yu@linux.alibaba.com>
---
drivers/iommu/riscv/iommu-ir.c | 22 ++++++++++++++++------
1 file changed, 16 insertions(+), 6 deletions(-)
diff --git a/drivers/iommu/riscv/iommu-ir.c b/drivers/iommu/riscv/iommu-ir.c
index b3f0a56475ed..b96baff9986d 100644
--- a/drivers/iommu/riscv/iommu-ir.c
+++ b/drivers/iommu/riscv/iommu-ir.c
@@ -104,15 +104,10 @@ static void riscv_iommu_ir_set_target(struct riscv_iommu_msipte *msipte,
}
}
-static int riscv_iommu_ir_activate(struct riscv_iommu_msi_table *msi_table,
- struct riscv_iommu_device *iommu,
- struct riscv_iommu_ir_vcpu_info *vcpu_info)
+static int riscv_iommu_ir_validate_vcpu_info(const struct riscv_iommu_ir_vcpu_info *vcpu_info)
{
u64 pattern = vcpu_info->msi_addr_pattern;
u64 mask = vcpu_info->msi_addr_mask;
- u64 required_caps = 0;
- size_t nr_ptes;
- int ret;
if (!vcpu_info->owner || (pattern & mask) ||
((pattern | mask) & ~RISCV_IOMMU_DC_MSI_ADDR_MASK))
@@ -129,6 +124,21 @@ static int riscv_iommu_ir_activate(struct riscv_iommu_msi_table *msi_table,
return -EINVAL;
}
+ return 0;
+}
+
+static int riscv_iommu_ir_activate(struct riscv_iommu_msi_table *msi_table,
+ struct riscv_iommu_device *iommu,
+ struct riscv_iommu_ir_vcpu_info *vcpu_info)
+{
+ u64 required_caps = 0;
+ size_t nr_ptes;
+ int ret;
+
+ ret = riscv_iommu_ir_validate_vcpu_info(vcpu_info);
+ if (ret)
+ return ret;
+
nr_ptes = riscv_iommu_ir_nr_ptes(vcpu_info);
ret = riscv_iommu_ir_validate_targets(vcpu_info, nr_ptes, &required_caps);
--
2.50.1
next prev parent reply other threads:[~2026-10-08 14:00 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-08 13:59 [RFC PATCH 0/3] iommu/riscv: Add irqbypass support without MSI page table fangyu.yu
2026-10-08 13:59 ` [RFC PATCH 1/3] iommu/riscv: Add guest IMSIC GPA mapping helpers fangyu.yu
2026-10-09 8:50 ` Gong Shuai
2026-10-08 14:00 ` fangyu.yu [this message]
2026-10-08 14:00 ` [RFC PATCH 3/3] iommu/riscv: Support IRQ forwarding without MSI page tables fangyu.yu
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