* [PATCH net-next v25 00/10] net: dsa: Add Airoha AN8855 support
@ 2026-10-09 16:10 Christian Marangi
2026-10-09 16:10 ` [PATCH net-next v25 01/10] dt-bindings: net: dsa: Document support for Airoha AN8855 DSA Switch Christian Marangi
` (9 more replies)
0 siblings, 10 replies; 18+ messages in thread
From: Christian Marangi @ 2026-10-09 16:10 UTC (permalink / raw)
To: Christian Marangi, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Vladimir Oltean, Matthias Brugger,
AngeloGioacchino Del Regno, Chester A. Unal, Daniel Golle,
Heiner Kallweit, Russell King, Simon Horman, Joris Vaisvila,
linux-arm-kernel, linux-mediatek, netdev, mfd, devicetree,
linux-kernel
This series add the initial support for the Airoha AN8855 Switch.
It's a 5 port Gigabit Switch with SGMII/HSGMII upstream port.
This is starting to get in the wild and there are already some router
having this switch chip.
MT7530 is generalized with reg fields to a shared library to
reduce code duplication and reuse all the logic for AN8855.
There is this special thing where PHY needs to be calibrated with values
from the switch efuse. (the thing have a whole cpu timer and MCU)
Given the double usage of PHY and Switch accessor, a special handling
is used with registering a mdio-regmap bus for each internal PHY.
From v8 Driver is now evaluated with Kernel selftest scripts for DSA:
Additional info about the test bridge_vlan_aware.sh.
It was discovered that the Airoha Switch (and probably the Mediatek one
that produce the same test results) hardcode checking for 802.1ad when
the port is configured in VLAN-Aware mode (aka Security mode).
In such mode, both 802.1q and 802.1ad TPID are checked, hence the
bridge_vlan_aware.sh test fails as packets with 802.1ad TPID are rejected
(in the case where a wrong VLAN ID is forwarded)
This was confirmed by Airoha and multiple try were done to try to
workaround this problem. No solution were found to this as ACL mechanism
can't work on receiving packets and the Switch doesn't support turning off
this.
The current driver is in use from 4 month on OpenWrt with all kind of
scenario confirming working in VLAN bridge. By tweaking the
bridge_vlan_aware.sh test with setting the TPID to 0x9100, the test
correctly pass as packets gets classified as untagged and the default PVID
applied. It's also confirmed that switch correctly parse the 802.1ad tag
and make the packet pass only when allowed by VLAN table rules.
Output local_termination.sh
TEST: lan2: Unicast IPv4 to primary MAC address [ OK ]
TEST: lan2: Unicast IPv4 to macvlan MAC address [ OK ]
TEST: lan2: Unicast IPv4 to unknown MAC address [ OK ]
TEST: lan2: Unicast IPv4 to unknown MAC address, promisc [ OK ]
TEST: lan2: Unicast IPv4 to unknown MAC address, allmulti [ OK ]
TEST: lan2: Multicast IPv4 to joined group [ OK ]
TEST: lan2: Multicast IPv4 to unknown group [XFAIL]
reception succeeded, but should have failed
TEST: lan2: Multicast IPv4 to unknown group, promisc [ OK ]
TEST: lan2: Multicast IPv4 to unknown group, allmulti [ OK ]
TEST: lan2: Multicast IPv6 to joined group [ OK ]
TEST: lan2: Multicast IPv6 to unknown group [XFAIL]
reception succeeded, but should have failed
TEST: lan2: Multicast IPv6 to unknown group, promisc [ OK ]
TEST: lan2: Multicast IPv6 to unknown group, allmulti [ OK ]
TEST: lan2: 1588v2 over L2 transport, Sync [ OK ]
TEST: lan2: 1588v2 over L2 transport, Follow-Up [ OK ]
TEST: lan2: 1588v2 over L2 transport, Peer Delay Request [ OK ]
TEST: lan2: 1588v2 over IPv4, Sync [FAIL]
reception failed
TEST: lan2: 1588v2 over IPv4, Follow-Up [FAIL]
reception failed
TEST: lan2: 1588v2 over IPv4, Peer Delay Request [FAIL]
reception failed
TEST: lan2: 1588v2 over IPv6, Sync [FAIL]
reception failed
TEST: lan2: 1588v2 over IPv6, Follow-Up [FAIL]
reception failed
TEST: lan2: 1588v2 over IPv6, Peer Delay Request [FAIL]
reception failed
TEST: vlan_filtering=0 bridge: Unicast IPv4 to primary MAC address [ OK ]
TEST: vlan_filtering=0 bridge: Unicast IPv4 to macvlan MAC address [ OK ]
TEST: vlan_filtering=0 bridge: Unicast IPv4 to unknown MAC address [ OK ]
TEST: vlan_filtering=0 bridge: Unicast IPv4 to unknown MAC address, promisc [ OK ]
TEST: vlan_filtering=0 bridge: Unicast IPv4 to unknown MAC address, allmulti [ OK ]
TEST: vlan_filtering=0 bridge: Multicast IPv4 to joined group [ OK ]
TEST: vlan_filtering=0 bridge: Multicast IPv4 to unknown group [XFAIL]
reception succeeded, but should have failed
TEST: vlan_filtering=0 bridge: Multicast IPv4 to unknown group, promisc [ OK ]
TEST: vlan_filtering=0 bridge: Multicast IPv4 to unknown group, allmulti [ OK ]
TEST: vlan_filtering=0 bridge: Multicast IPv6 to joined group [ OK ]
TEST: vlan_filtering=0 bridge: Multicast IPv6 to unknown group [XFAIL]
reception succeeded, but should have failed
TEST: vlan_filtering=0 bridge: Multicast IPv6 to unknown group, promisc [ OK ]
TEST: vlan_filtering=0 bridge: Multicast IPv6 to unknown group, allmulti [ OK ]
TEST: vlan_filtering=1 bridge: Unicast IPv4 to primary MAC address [ OK ]
TEST: vlan_filtering=1 bridge: Unicast IPv4 to macvlan MAC address [ OK ]
TEST: vlan_filtering=1 bridge: Unicast IPv4 to unknown MAC address [ OK ]
TEST: vlan_filtering=1 bridge: Unicast IPv4 to unknown MAC address, promisc [ OK ]
TEST: vlan_filtering=1 bridge: Unicast IPv4 to unknown MAC address, allmulti [ OK ]
TEST: vlan_filtering=1 bridge: Multicast IPv4 to joined group [ OK ]
TEST: vlan_filtering=1 bridge: Multicast IPv4 to unknown group [XFAIL]
reception succeeded, but should have failed
TEST: vlan_filtering=1 bridge: Multicast IPv4 to unknown group, promisc [ OK ]
TEST: vlan_filtering=1 bridge: Multicast IPv4 to unknown group, allmulti [ OK ]
TEST: vlan_filtering=1 bridge: Multicast IPv6 to joined group [ OK ]
TEST: vlan_filtering=1 bridge: Multicast IPv6 to unknown group [XFAIL]
reception succeeded, but should have failed
TEST: vlan_filtering=1 bridge: Multicast IPv6 to unknown group, promisc [ OK ]
TEST: vlan_filtering=1 bridge: Multicast IPv6 to unknown group, allmulti [ OK ]
TEST: VLAN upper: Unicast IPv4 to primary MAC address [ OK ]
TEST: VLAN upper: Unicast IPv4 to macvlan MAC address [ OK ]
TEST: VLAN upper: Unicast IPv4 to unknown MAC address [ OK ]
TEST: VLAN upper: Unicast IPv4 to unknown MAC address, promisc [ OK ]
TEST: VLAN upper: Unicast IPv4 to unknown MAC address, allmulti [ OK ]
TEST: VLAN upper: Multicast IPv4 to joined group [ OK ]
TEST: VLAN upper: Multicast IPv4 to unknown group [XFAIL]
reception succeeded, but should have failed
TEST: VLAN upper: Multicast IPv4 to unknown group, promisc [ OK ]
TEST: VLAN upper: Multicast IPv4 to unknown group, allmulti [ OK ]
TEST: VLAN upper: Multicast IPv6 to joined group [ OK ]
TEST: VLAN upper: Multicast IPv6 to unknown group [XFAIL]
reception succeeded, but should have failed
TEST: VLAN upper: Multicast IPv6 to unknown group, promisc [ OK ]
TEST: VLAN upper: Multicast IPv6 to unknown group, allmulti [ OK ]
TEST: VLAN upper: 1588v2 over L2 transport, Sync [ OK ]
TEST: VLAN upper: 1588v2 over L2 transport, Follow-Up [FAIL]
reception failed
TEST: VLAN upper: 1588v2 over L2 transport, Peer Delay Request [ OK ]
TEST: VLAN upper: 1588v2 over IPv4, Sync [FAIL]
reception failed
;TEST: VLAN upper: 1588v2 over IPv4, Follow-Up [FAIL]
reception failed
TEST: VLAN upper: 1588v2 over IPv4, Peer Delay Request [FAIL]
reception failed
TEST: VLAN upper: 1588v2 over IPv6, Sync [FAIL]
reception failed
TEST: VLAN upper: 1588v2 over IPv6, Follow-Up [FAIL]
reception failed
TEST: VLAN upper: 1588v2 over IPv6, Peer Delay Request [FAIL]
reception failed
TEST: VLAN over vlan_filtering=0 bridged port: Unicast IPv4 to primary MAC address [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: Unicast IPv4 to macvlan MAC address [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: Unicast IPv4 to unknown MAC address [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: Unicast IPv4 to unknown MAC address, promisc [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: Unicast IPv4 to unknown MAC address, allmulti [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: Multicast IPv4 to joined group [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: Multicast IPv4 to unknown group [XFAIL]
reception succeeded, but should have failed
TEST: VLAN over vlan_filtering=0 bridged port: Multicast IPv4 to unknown group, promisc [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: Multicast IPv4 to unknown group, allmulti [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: Multicast IPv6 to joined group [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: Multicast IPv6 to unknown group [XFAIL]
reception succeeded, but should have failed
TEST: VLAN over vlan_filtering=0 bridged port: Multicast IPv6 to unknown group, promisc [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: Multicast IPv6 to unknown group, allmulti [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: 1588v2 over L2 transport, Sync [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: 1588v2 over L2 transport, Follow-Up [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: 1588v2 over L2 transport, Peer Delay Request [ OK ]
TEST: VLAN over vlan_filtering=0 bridged port: 1588v2 over IPv4, Sync [FAIL]
reception failed
TEST: VLAN over vlan_filtering=0 bridged port: 1588v2 over IPv4, Follow-Up [FAIL]
reception failed
TEST: VLAN over vlan_filtering=0 bridged port: 1588v2 over IPv4, Peer Delay Request [FAIL]
reception failed
TEST: VLAN over vlan_filtering=0 bridged port: 1588v2 over IPv6, Sync [FAIL]
reception failed
TEST: VLAN over vlan_filtering=0 bridged port: 1588v2 over IPv6, Follow-Up [FAIL]
reception failed
TEST: VLAN over vlan_filtering=0 bridged port: 1588v2 over IPv6, Peer Delay Request [FAIL]
reception failed
TEST: VLAN over vlan_filtering=1 bridged port: Unicast IPv4 to primary MAC address [ OK ]
TEST: VLAN over vlan_filtering=1 bridged port: Unicast IPv4 to macvlan MAC address [ OK ]
TEST: VLAN over vlan_filtering=1 bridged port: Unicast IPv4 to unknown MAC address [FAIL]
reception succeeded, but should have failed
TEST: VLAN over vlan_filtering=1 bridged port: Unicast IPv4 to unknown MAC address, promisc [ OK ]
TEST: VLAN over vlan_filtering=1 bridged port: Unicast IPv4 to unknown MAC address, allmulti [FAIL]
reception succeeded, but should have failed
TEST: VLAN over vlan_filtering=1 bridged port: Multicast IPv4 to joined group [ OK ]
TEST: VLAN over vlan_filtering=1 bridged port: Multicast IPv4 to unknown group [XFAIL]
reception succeeded, but should have failed
TEST: VLAN over vlan_filtering=1 bridged port: Multicast IPv4 to unknown group, promisc [ OK ]
TEST: VLAN over vlan_filtering=1 bridged port: Multicast IPv4 to unknown group, allmulti [ OK ]
TEST: VLAN over vlan_filtering=1 bridged port: Multicast IPv6 to joined group [ OK ]
TEST: VLAN over vlan_filtering=1 bridged port: Multicast IPv6 to unknown group [XFAIL]
reception succeeded, but should have failed
TEST: VLAN over vlan_filtering=1 bridged port: Multicast IPv6 to unknown group, promisc [ OK ]
TEST: VLAN over vlan_filtering=1 bridged port: Multicast IPv6 to unknown group, allmulti [ OK ]
TEST: VLAN over vlan_filtering=1 bridged port: 1588v2 over L2 transport, Sync [ OK ]
TEST: VLAN over vlan_filtering=1 bridged port: 1588v2 over L2 transport, Follow-Up [ OK ]
TEST: VLAN over vlan_filtering=1 bridged port: 1588v2 over L2 transport, Peer Delay Request [ OK ]
TEST: VLAN over vlan_filtering=1 bridged port: 1588v2 over IPv4, Sync [FAIL]
reception failed
TEST: VLAN over vlan_filtering=1 bridged port: 1588v2 over IPv4, Follow-Up [FAIL]
reception failed
TEST: VLAN over vlan_filtering=1 bridged port: 1588v2 over IPv4, Peer Delay Request [FAIL]
reception failed
TEST: VLAN over vlan_filtering=1 bridged port: 1588v2 over IPv6, Sync [FAIL]
reception failed
TEST: VLAN over vlan_filtering=1 bridged port: 1588v2 over IPv6, Follow-Up [FAIL]
reception failed
TEST: VLAN over vlan_filtering=1 bridged port: 1588v2 over IPv6, Peer Delay Request [FAIL]
reception failed
TEST: VLAN over vlan_filtering=0 bridge: Unicast IPv4 to primary MAC address [ OK ]
TEST: VLAN over vlan_filtering=0 bridge: Unicast IPv4 to macvlan MAC address [ OK ]
TEST: VLAN over vlan_filtering=0 bridge: Unicast IPv4 to unknown MAC address [ OK ]
TEST: VLAN over vlan_filtering=0 bridge: Unicast IPv4 to unknown MAC address, promisc [ OK ]
TEST: VLAN over vlan_filtering=0 bridge: Unicast IPv4 to unknown MAC address, allmulti [ OK ]
TEST: VLAN over vlan_filtering=0 bridge: Multicast IPv4 to joined group [ OK ]
TEST: VLAN over vlan_filtering=0 bridge: Multicast IPv4 to unknown group [XFAIL]
reception succeeded, but should have failed
TEST: VLAN over vlan_filtering=0 bridge: Multicast IPv4 to unknown group, promisc [ OK ]
TEST: VLAN over vlan_filtering=0 bridge: Multicast IPv4 to unknown group, allmulti [ OK ]
TEST: VLAN over vlan_filtering=0 bridge: Multicast IPv6 to joined group [ OK ]
TEST: VLAN over vlan_filtering=0 bridge: Multicast IPv6 to unknown group [XFAIL]
reception succeeded, but should have failed
TEST: VLAN over vlan_filtering=0 bridge: Multicast IPv6 to unknown group, promisc [ OK ]
TEST: VLAN over vlan_filtering=0 bridge: Multicast IPv6 to unknown group, allmulti [ OK ]
TEST: VLAN over vlan_filtering=1 bridge: Unicast IPv4 to primary MAC address [ OK ]
TEST: VLAN over vlan_filtering=1 bridge: Unicast IPv4 to macvlan MAC address [ OK ]
TEST: VLAN over vlan_filtering=1 bridge: Unicast IPv4 to unknown MAC address [ OK ]
TEST: VLAN over vlan_filtering=1 bridge: Unicast IPv4 to unknown MAC address, promisc [ OK ]
TEST: VLAN over vlan_filtering=1 bridge: Unicast IPv4 to unknown MAC address, allmulti [ OK ]
TEST: VLAN over vlan_filtering=1 bridge: Multicast IPv4 to joined group [ OK ]
TEST: VLAN over vlan_filtering=1 bridge: Multicast IPv4 to unknown group [XFAIL]
reception succeeded, but should have failed
TEST: VLAN over vlan_filtering=1 bridge: Multicast IPv4 to unknown group, promisc [ OK ]
TEST: VLAN over vlan_filtering=1 bridge: Multicast IPv4 to unknown group, allmulti [ OK ]
TEST: VLAN over vlan_filtering=1 bridge: Multicast IPv6 to joined group [ OK ]
TEST: VLAN over vlan_filtering=1 bridge: Multicast IPv6 to unknown group [XFAIL]
reception succeeded, but should have failed
TEST: VLAN over vlan_filtering=1 bridge: Multicast IPv6 to unknown group, promisc [ OK ]
TEST: VLAN over vlan_filtering=1 bridge: Multicast IPv6 to unknown group, allmulti [ OK ]
Output bridge_vlan_unaware.sh
TEST: ping [ OK ]
TEST: ping6 [ OK ]
TEST: FDB learning [ OK ]
TEST: Unknown unicast flood [ OK ]
TEST: Unregistered multicast flood [ OK ]
Output bridge_vlan_aware.sh
TEST: ping [ OK ]
TEST: ping6 [ OK ]
TEST: FDB learning [ OK ]
TEST: Unknown unicast flood [ OK ]
TEST: Unregistered multicast flood [ OK ]
INFO: Add and delete a VLAN on bridge port lan2
TEST: ping [ OK ]
TEST: ping6 [ OK ]
TEST: Externally learned FDB entry - ageing & roaming [ OK ]
TEST: FDB entry in PVID for VLAN-tagged with other TPID [FAIL]
FDB entry was not learned when it should
TEST: Reception of VLAN with other TPID as untagged [FAIL]
Packet was not forwarded when it should
TEST: Reception of VLAN with other TPID as untagged (no PVID) [FAIL]
Packet was forwarded when should not
Changes v25:
- Address suggestion for MFD for sashiko
- Better handle port enable/disable
Changes v24:
- Add review tag by Andrew
- Fix missing multicast from generalize patch
- Add patch to move mediatek drivers to dedicated driver
- Zero out saved timer on LPI disable
- Correctl check regfiled on FDB read
- Fix MFD leaked of node
- Better handle MFD virtual mdio name
Changes v23:
- Add review by tag for DT patch
- Fix MFD fwnode handle release
- Better handle LPI handling for AN8855
- Add additional kconfig for AN8855
- Use shorter name for virtual phy bus
Changes v22:
- Improve MFD lock handling for phy bus
- Prevent devm crash on removal for MFD driver
- Address VAWD bug reported by bot
- Fix wrong msb for MIB for AN8855 driver
- Better handle kconfig dependency
- Read tx_lpi under lock
Changes v21:
- Rebase on top of net-next
- Drop megred patch from Daniel
- Address suggestion reported by bot for MFD driver
- Drop reset for MFD driver
- Reset FDB and VLAN data on writing
- Fix not correct PCR matrix in port enable
- Add ID_EN7528 fields
- Fix MAC address learning SA_DIS
- Fix MAC address FDB read swapped
- Fix mib reset logic
- Fix AN8855 missing regfiled
- Fix AN8855 ethtool stats access
- Improve tx lpi timer for AN8855
- Improve MFD Documentation patch
Changes v20:
- Address all the typo pointed out by bot
- Make documentation schema more consistent
- Address some concern for the mfd driver from bot
- Fix some conversion problem for the generalization patch
Changes v19:
- Rebase on top of net-next
- Rework with shared function from mt7530 driver
- Add dependency for mt7530 lock
- Fix some define typo for AN8855
Changes v18:
- Fix configurting typo
- Init ret in MFD driver
Changes v17:
- Drop nvmem patch (subset merged and present in linux-next)
- Fix wrong Documentation patch for MFD
- Address reviews for MFD driver
- Rework MTK tag to slipt for Airoha name
Changes v16:
- Rebase on top of net-next
- Drop PBUS implementation (Airoha said that it's not OK to use it)
- Convert to simple mdio-regmap and split regmap
- Fix typo for some define (AND8855 -> AN8855)
Changes v15:
- Rebase on top of net-next
- Drop regmap MDIO patch (in favor of PBUS)
- Implement MDIO PBUS and rework MDIO driver/MFD
- Reimplement EEE support
- Add some check for regmap from MFD
- Move to single regmap and add comments with all findings
Changes v14:
- Move MAITAINERS entry to dedicated commit (make it easier for cross
subsystem merge)
- Pack variables in trap function
- Add additional patch for reported difference from MTK tag
Changes v13:
- Reimplement tx_lpi OPs
- Rework mdio-regmap to internally encode/decode address
- Fix error in Documentation
- Drop ext-surge property (assume calibration with declared nvmem cell)
- Fix comments from Lee on MFD driver
- Improve print error and drop extra space in DSA driver
Changes v12:
- Update on top of net-next
- Add additional info on conver-letter about slefttests and HW limitation
- Introduce mdio-regmap generalization for multiple address
- Drop dev flags and define PHY calibration in PHY node directly
Changes v11:
- Address reviews from Christophe (spell mistake + dev_err_probe)
- Fix kconfig dependency for MFD driver (depends on MDIO_DEVICE instead of MDIO)
(indirectly fix link error for mdio APIs)
- Fix copy-paste error for MFD driver of_table
- Fix compilation error for PHY (move NVMEM to .config)
- Drop unneeded NVMEM node from MDIO example schema (from Andrew)
- Adapt MFD example schema to MDIO reg property restrictions
Changes v10:
- Entire rework to MFD + split to MDIO, EFUSE, SWITCH separate drivers
- Drop EEE OPs (while Russell finish RFC for EEE changes)
- Use new pcs_inpand OPs
- Drop AN restart function and move to pcs_config
- Enable assisted_learning and disable CPU learn (preparation for fdb_isolation)
- Move EFUSE read in Internal PHY driver to .config to handle EPROBE_DEFER
(needed now that NVMEM driver is register externally instead of internally to switch
node)
Changes v9:
- Error out on using 5G speed as currently not supported
- Add missing MAC_2500FD in phylink mac_capabilities
- Add comment and improve if condition for an8855_phylink_mac_config
Changes v8:
- Add port Fast Age support
- Add support for Port Isolation
- Use correct register for Learning Disable
- Add support for Ageing Time OP
- Set default PVID to 0 by default
- Add mdb OPs
- Add port change MTU
- Fix support for Upper VLAN
Changes v7:
- Fix devm_dsa_register_switch wrong export symbol
Changes v6:
- Drop standard MIB and handle with ethtool OPs (as requested by Jakub)
- Cosmetic: use bool instead of 0 or 1
Changes v5:
- Add devm_dsa_register_switch() patch
- Add Reviewed-by tag for DT patch
Changes v4:
- Set regmap readable_table static (mute compilation warning)
- Add support for port_bridge flags (LEARNING, FLOOD)
- Reset fdb struct in fdb_dump
- Drop support_asym_pause in port_enable
- Add define for get_phy_flags
- Fix bug for port not inititially part of a bridge
(in an8855_setup the port matrix was always cleared but
the CPU port was never initially added)
- Disable learning and flood for user port by default
- Set CPU port to flood and learning by default
- Correctly AND force duplex and flow control in an8855_phylink_mac_link_up
- Drop RGMII from pcs_config
- Check ret in "Disable AN if not in autoneg"
- Use devm_mutex_init
- Fix typo for AN8855_PORT_CHECK_MODE
- Better define AN8855_STP_LISTENING = AN8855_STP_BLOCKING
- Fix typo in AN8855_PHY_EN_DOWN_SHIFT
- Use paged helper for PHY
- Skip calibration in config_init if priv not defined
Changes v3:
- Out of RFC
- Switch PHY code to select_page API
- Better describe masks and bits in PHY driver for ADC register
- Drop raw values and use define for mii read/write
- Switch to absolute PHY address
- Replace raw values with mask and bits for pcs_config
- Fix typo for ext-surge property name
- Drop support for relocating Switch base PHY address on the bus
Changes v2:
- Drop mutex guard patch
- Drop guard usage in DSA driver
- Use __mdiobus_write/read
- Check return condition and return errors for mii read/write
- Fix wrong logic for EEE
- Fix link_down (don't force link down with autoneg)
- Fix forcing speed on sgmii autoneg
- Better document link speed for sgmii reg
- Use standard define for sgmii reg
- Imlement nvmem support to expose switch EFUSE
- Rework PHY calibration with the use of NVMEM producer/consumer
- Update DT with new NVMEM property
- Move aneg validation for 2500-basex in pcs_config
- Move r50Ohm table and function to PHY driver
Christian Marangi (10):
dt-bindings: net: dsa: Document support for Airoha AN8855 DSA Switch
dt-bindings: net: Document support for AN8855 Switch Internal PHY
dt-bindings: mfd: Document support for Airoha AN8855 Switch SoC
mfd: an8855: Add support for Airoha AN8855 Switch
net: phy: Add Airoha AN8855 Internal Switch Gigabit PHY
net: dsa: tag_mtk: add Airoha variant usage of this TAG
MAINTAINERS: add myself as maintainer for Airoha AN8855 Switch
net: dsa: move mediatek DSA driver in dedicated directory
net: dsa: mt7530: generalize and move common function to lib module
net: dsa: Add Airoha AN8855 5-Port Gigabit DSA Switch driver
.../bindings/mfd/airoha,an8855.yaml | 176 ++
.../bindings/net/airoha,an8855-phy.yaml | 83 +
.../net/dsa/airoha,an8855-switch.yaml | 86 +
MAINTAINERS | 22 +-
drivers/mfd/Kconfig | 14 +
drivers/mfd/Makefile | 1 +
drivers/mfd/airoha-an8855.c | 579 ++++++
drivers/net/dsa/Kconfig | 45 +-
drivers/net/dsa/Makefile | 5 +-
drivers/net/dsa/mediatek/Kconfig | 59 +
drivers/net/dsa/mediatek/Makefile | 7 +
drivers/net/dsa/mediatek/an8855.c | 1765 +++++++++++++++++
drivers/net/dsa/mediatek/an8855.h | 755 +++++++
drivers/net/dsa/mediatek/mt7530-lib.c | 1156 +++++++++++
drivers/net/dsa/mediatek/mt7530-lib.h | 413 ++++
drivers/net/dsa/{ => mediatek}/mt7530-mdio.c | 4 +
drivers/net/dsa/{ => mediatek}/mt7530-mmio.c | 4 +
drivers/net/dsa/{ => mediatek}/mt7530.c | 1366 +++----------
drivers/net/dsa/{ => mediatek}/mt7530.h | 256 +--
drivers/net/dsa/{ => mediatek}/mt7628.c | 0
drivers/net/phy/Kconfig | 6 +
drivers/net/phy/Makefile | 1 +
drivers/net/phy/air_an8855.c | 275 +++
include/net/dsa.h | 2 +
net/dsa/Kconfig | 11 +
net/dsa/Makefile | 2 +-
net/dsa/tag_mtk.c | 36 +-
27 files changed, 5832 insertions(+), 1297 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mfd/airoha,an8855.yaml
create mode 100644 Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml
create mode 100644 Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml
create mode 100644 drivers/mfd/airoha-an8855.c
create mode 100644 drivers/net/dsa/mediatek/Kconfig
create mode 100644 drivers/net/dsa/mediatek/Makefile
create mode 100644 drivers/net/dsa/mediatek/an8855.c
create mode 100644 drivers/net/dsa/mediatek/an8855.h
create mode 100644 drivers/net/dsa/mediatek/mt7530-lib.c
create mode 100644 drivers/net/dsa/mediatek/mt7530-lib.h
rename drivers/net/dsa/{ => mediatek}/mt7530-mdio.c (99%)
rename drivers/net/dsa/{ => mediatek}/mt7530-mmio.c (97%)
rename drivers/net/dsa/{ => mediatek}/mt7530.c (63%)
rename drivers/net/dsa/{ => mediatek}/mt7530.h (81%)
rename drivers/net/dsa/{ => mediatek}/mt7628.c (100%)
create mode 100644 drivers/net/phy/air_an8855.c
--
2.55.0
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH net-next v25 01/10] dt-bindings: net: dsa: Document support for Airoha AN8855 DSA Switch
2026-10-09 16:10 [PATCH net-next v25 00/10] net: dsa: Add Airoha AN8855 support Christian Marangi
@ 2026-10-09 16:10 ` Christian Marangi
2026-10-09 16:10 ` [PATCH net-next v25 02/10] dt-bindings: net: Document support for AN8855 Switch Internal PHY Christian Marangi
` (8 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: Christian Marangi @ 2026-10-09 16:10 UTC (permalink / raw)
To: Christian Marangi, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Vladimir Oltean, Matthias Brugger,
AngeloGioacchino Del Regno, Chester A. Unal, Daniel Golle,
Heiner Kallweit, Russell King, Simon Horman, Joris Vaisvila,
linux-arm-kernel, linux-mediatek, netdev, mfd, devicetree,
linux-kernel
Document support for Airoha AN8855 5-port Gigabit Switch.
It does expose the 5 Internal PHYs on the MDIO bus and each port
can access the Switch register space by configuring the PHY page.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
---
.../net/dsa/airoha,an8855-switch.yaml | 86 +++++++++++++++++++
1 file changed, 86 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml
diff --git a/Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml b/Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml
new file mode 100644
index 000000000000..5ad9b9e13983
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml
@@ -0,0 +1,86 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/dsa/airoha,an8855-switch.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha AN8855 Gigabit Switch
+
+maintainers:
+ - Christian Marangi <ansuelsmth@gmail.com>
+
+description: >
+ Airoha AN8855 is a 5-port Gigabit Switch.
+
+ It does expose the 5 Internal PHYs on the MDIO bus and each port
+ can access the Switch register space by configuring the PHY page.
+
+$ref: dsa.yaml#/$defs/ethernet-ports
+
+properties:
+ compatible:
+ const: airoha,an8855-switch
+
+required:
+ - compatible
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ ethernet-switch {
+ compatible = "airoha,an8855-switch";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan1";
+ phy-mode = "internal";
+ phy-handle = <&internal_phy1>;
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan2";
+ phy-mode = "internal";
+ phy-handle = <&internal_phy2>;
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "lan3";
+ phy-mode = "internal";
+ phy-handle = <&internal_phy3>;
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "lan4";
+ phy-mode = "internal";
+ phy-handle = <&internal_phy4>;
+ };
+
+ port@4 {
+ reg = <4>;
+ label = "wan";
+ phy-mode = "internal";
+ phy-handle = <&internal_phy5>;
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ phy-mode = "2500base-x";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ pause;
+ };
+ };
+ };
+ };
--
2.55.0
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH net-next v25 02/10] dt-bindings: net: Document support for AN8855 Switch Internal PHY
2026-10-09 16:10 [PATCH net-next v25 00/10] net: dsa: Add Airoha AN8855 support Christian Marangi
2026-10-09 16:10 ` [PATCH net-next v25 01/10] dt-bindings: net: dsa: Document support for Airoha AN8855 DSA Switch Christian Marangi
@ 2026-10-09 16:10 ` Christian Marangi
2026-10-10 16:19 ` netdev-bot+sashiko
2026-10-09 16:10 ` [PATCH net-next v25 03/10] dt-bindings: mfd: Document support for Airoha AN8855 Switch SoC Christian Marangi
` (7 subsequent siblings)
9 siblings, 1 reply; 18+ messages in thread
From: Christian Marangi @ 2026-10-09 16:10 UTC (permalink / raw)
To: Christian Marangi, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Vladimir Oltean, Matthias Brugger,
AngeloGioacchino Del Regno, Chester A. Unal, Daniel Golle,
Heiner Kallweit, Russell King, Simon Horman, Joris Vaisvila,
linux-arm-kernel, linux-mediatek, netdev, mfd, devicetree,
linux-kernel
Document support for AN8855 Switch Internal PHY.
Airoha AN8855 is a 5-port Gigabit Switch that expose the Internal
PHYs on the MDIO bus.
Each PHY might need to be calibrated to correctly work with the
use of the eFUSE provided by the Switch SoC. This can be enabled by
defining in the PHY node the NVMEM cell properties.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
---
.../bindings/net/airoha,an8855-phy.yaml | 83 +++++++++++++++++++
1 file changed, 83 insertions(+)
create mode 100644 Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml
diff --git a/Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml b/Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml
new file mode 100644
index 000000000000..d2f86116badf
--- /dev/null
+++ b/Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml
@@ -0,0 +1,83 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/net/airoha,an8855-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha AN8855 Switch Internal PHY
+
+maintainers:
+ - Christian Marangi <ansuelsmth@gmail.com>
+
+description: >
+ Airoha AN8855 is a 5-port Gigabit Switch that expose the Internal
+ PHYs on the MDIO bus.
+
+ Each PHY might need to be calibrated to correctly work with the
+ use of the eFUSE provided by the Switch SoC.
+
+allOf:
+ - $ref: ethernet-phy.yaml#
+
+select:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - ethernet-phy-idc0ff.0410
+ required:
+ - compatible
+
+properties:
+ reg:
+ maxItems: 1
+
+ nvmem-cells:
+ items:
+ - description: phandle to SoC eFUSE tx_a
+ - description: phandle to SoC eFUSE tx_b
+ - description: phandle to SoC eFUSE tx_c
+ - description: phandle to SoC eFUSE tx_d
+
+ nvmem-cell-names:
+ items:
+ - const: tx_a
+ - const: tx_b
+ - const: tx_c
+ - const: tx_d
+
+required:
+ - compatible
+ - reg
+
+dependentRequired:
+ nvmem-cells: [ nvmem-cell-names ]
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-phy@1 {
+ compatible = "ethernet-phy-idc0ff.0410",
+ "ethernet-phy-ieee802.3-c45";
+
+ reg = <1>;
+ };
+
+ ethernet-phy@2 {
+ compatible = "ethernet-phy-idc0ff.0410",
+ "ethernet-phy-ieee802.3-c45";
+
+ reg = <2>;
+
+ nvmem-cells = <&shift_sel_port0_tx_a>,
+ <&shift_sel_port0_tx_b>,
+ <&shift_sel_port0_tx_c>,
+ <&shift_sel_port0_tx_d>;
+ nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
+ };
+ };
--
2.55.0
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH net-next v25 03/10] dt-bindings: mfd: Document support for Airoha AN8855 Switch SoC
2026-10-09 16:10 [PATCH net-next v25 00/10] net: dsa: Add Airoha AN8855 support Christian Marangi
2026-10-09 16:10 ` [PATCH net-next v25 01/10] dt-bindings: net: dsa: Document support for Airoha AN8855 DSA Switch Christian Marangi
2026-10-09 16:10 ` [PATCH net-next v25 02/10] dt-bindings: net: Document support for AN8855 Switch Internal PHY Christian Marangi
@ 2026-10-09 16:10 ` Christian Marangi
2026-10-10 16:19 ` netdev-bot+sashiko
2026-10-09 16:10 ` [PATCH net-next v25 04/10] mfd: an8855: Add support for Airoha AN8855 Switch Christian Marangi
` (6 subsequent siblings)
9 siblings, 1 reply; 18+ messages in thread
From: Christian Marangi @ 2026-10-09 16:10 UTC (permalink / raw)
To: Christian Marangi, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Vladimir Oltean, Matthias Brugger,
AngeloGioacchino Del Regno, Chester A. Unal, Daniel Golle,
Heiner Kallweit, Russell King, Simon Horman, Joris Vaisvila,
linux-arm-kernel, linux-mediatek, netdev, mfd, devicetree,
linux-kernel
Document support for Airoha AN8855 Switch SoC. This SoC expose various
peripherals like an Ethernet Switch, a NVMEM provider and Ethernet PHYs.
It does also support i2c and timers but those are not currently
supported/used.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
---
.../bindings/mfd/airoha,an8855.yaml | 176 ++++++++++++++++++
1 file changed, 176 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/airoha,an8855.yaml
diff --git a/Documentation/devicetree/bindings/mfd/airoha,an8855.yaml b/Documentation/devicetree/bindings/mfd/airoha,an8855.yaml
new file mode 100644
index 000000000000..48127e956c96
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/airoha,an8855.yaml
@@ -0,0 +1,176 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/airoha,an8855.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Airoha AN8855 Switch SoC
+
+maintainers:
+ - Christian Marangi <ansuelsmth@gmail.com>
+
+description: >
+ Airoha AN8855 Switch is a SoC that expose various peripherals like an
+ Ethernet Switch, a NVMEM provider and Ethernet PHYs.
+
+ It does also support i2c and timers but those are not currently
+ supported/used.
+
+properties:
+ compatible:
+ const: airoha,an8855
+
+ reg:
+ maxItems: 1
+
+ reset-gpios:
+ maxItems: 1
+
+ efuse:
+ type: object
+ $ref: /schemas/nvmem/airoha,an8855-efuse.yaml
+ description: EFUSE exposed by the Airoha AN8855 SoC
+
+ ethernet-switch:
+ type: object
+ $ref: /schemas/net/dsa/airoha,an8855-switch.yaml
+ description: Switch exposed by the Airoha AN8855 SoC
+
+ mdio:
+ type: object
+ $ref: /schemas/net/mdio.yaml#
+ description: MDIO exposed by the Airoha AN8855 SoC
+ unevaluatedProperties: false
+
+required:
+ - compatible
+ - reg
+ - mdio
+ - ethernet-switch
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ soc@1 {
+ compatible = "airoha,an8855";
+ reg = <1>;
+
+ reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>;
+
+ efuse {
+ compatible = "airoha,an8855-efuse";
+
+ #nvmem-cell-cells = <0>;
+
+ nvmem-layout {
+ compatible = "fixed-layout";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ shift_sel_port0_tx_a: shift-sel-port0-tx-a@c {
+ reg = <0xc 0x4>;
+ };
+
+ shift_sel_port0_tx_b: shift-sel-port0-tx-b@10 {
+ reg = <0x10 0x4>;
+ };
+
+ shift_sel_port0_tx_c: shift-sel-port0-tx-c@14 {
+ reg = <0x14 0x4>;
+ };
+
+ shift_sel_port0_tx_d: shift-sel-port0-tx-d@18 {
+ reg = <0x18 0x4>;
+ };
+
+ shift_sel_port1_tx_a: shift-sel-port1-tx-a@1c {
+ reg = <0x1c 0x4>;
+ };
+
+ shift_sel_port1_tx_b: shift-sel-port1-tx-b@20 {
+ reg = <0x20 0x4>;
+ };
+
+ shift_sel_port1_tx_c: shift-sel-port1-tx-c@24 {
+ reg = <0x24 0x4>;
+ };
+
+ shift_sel_port1_tx_d: shift-sel-port1-tx-d@28 {
+ reg = <0x28 0x4>;
+ };
+ };
+ };
+
+ ethernet-switch {
+ compatible = "airoha,an8855-switch";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ label = "lan1";
+ phy-mode = "internal";
+ phy-handle = <&internal_phy1>;
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "lan2";
+ phy-mode = "internal";
+ phy-handle = <&internal_phy2>;
+ };
+
+ port@5 {
+ reg = <5>;
+ label = "cpu";
+ ethernet = <&gmac0>;
+ phy-mode = "2500base-x";
+
+ fixed-link {
+ speed = <2500>;
+ full-duplex;
+ pause;
+ };
+ };
+ };
+ };
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ internal_phy1: ethernet-phy@1 {
+ compatible = "ethernet-phy-idc0ff.0410",
+ "ethernet-phy-ieee802.3-c22";
+ reg = <1>;
+
+ nvmem-cells = <&shift_sel_port0_tx_a>,
+ <&shift_sel_port0_tx_b>,
+ <&shift_sel_port0_tx_c>,
+ <&shift_sel_port0_tx_d>;
+ nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
+ };
+
+ internal_phy2: ethernet-phy@2 {
+ compatible = "ethernet-phy-idc0ff.0410",
+ "ethernet-phy-ieee802.3-c22";
+ reg = <2>;
+
+ nvmem-cells = <&shift_sel_port1_tx_a>,
+ <&shift_sel_port1_tx_b>,
+ <&shift_sel_port1_tx_c>,
+ <&shift_sel_port1_tx_d>;
+ nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
+ };
+ };
+ };
+ };
--
2.55.0
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH net-next v25 04/10] mfd: an8855: Add support for Airoha AN8855 Switch
2026-10-09 16:10 [PATCH net-next v25 00/10] net: dsa: Add Airoha AN8855 support Christian Marangi
` (2 preceding siblings ...)
2026-10-09 16:10 ` [PATCH net-next v25 03/10] dt-bindings: mfd: Document support for Airoha AN8855 Switch SoC Christian Marangi
@ 2026-10-09 16:10 ` Christian Marangi
2026-10-10 16:19 ` netdev-bot+sashiko
2026-10-09 16:10 ` [PATCH net-next v25 05/10] net: phy: Add Airoha AN8855 Internal Switch Gigabit PHY Christian Marangi
` (5 subsequent siblings)
9 siblings, 1 reply; 18+ messages in thread
From: Christian Marangi @ 2026-10-09 16:10 UTC (permalink / raw)
To: Christian Marangi, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Vladimir Oltean, Matthias Brugger,
AngeloGioacchino Del Regno, Chester A. Unal, Daniel Golle,
Heiner Kallweit, Russell King, Simon Horman, Joris Vaisvila,
linux-arm-kernel, linux-mediatek, netdev, mfd, devicetree,
linux-kernel
Add support for Airoha AN8855 Switch that provide support for a DSA
switch and a NVMEM provider.
Also make use of the mdio-regmap driver and register a regmap for each
internal PHY of the switch.
This is needed to handle the double usage of the PHYs as both PHY and
Switch accessor.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/mfd/Kconfig | 14 +
drivers/mfd/Makefile | 1 +
drivers/mfd/airoha-an8855.c | 579 ++++++++++++++++++++++++++++++++++++
3 files changed, 594 insertions(+)
create mode 100644 drivers/mfd/airoha-an8855.c
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index e4fd4572472f..afbdcec0fce8 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -54,6 +54,20 @@ config MFD_ALTERA_SYSMGR
using regmap_mmio accesses for ARM32 parts and SMC calls to
EL3 for ARM64 parts.
+config MFD_AIROHA_AN8855
+ tristate "Airoha AN8855 Switch Core"
+ select MFD_CORE
+ select REGMAP
+ select PHYLIB
+ select MDIO_REGMAP
+ depends on NETDEVICES && OF
+ help
+ Support for the Airoha AN8855 Switch Core. This is an SoC
+ that provides various peripherals, to count, i2c, an Ethrnet
+ Switch, a CPU timer, GPIO, eFUSE.
+
+ Currently it provides a DSA switch and a NVMEM provider.
+
config MFD_ACT8945A
tristate "Active-semi ACT8945A"
select MFD_CORE
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 72d3944b0ad8..484127dba2ad 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_MFD_88PM860X) += 88pm860x.o
obj-$(CONFIG_MFD_88PM800) += 88pm800.o 88pm80x.o
obj-$(CONFIG_MFD_88PM805) += 88pm805.o 88pm80x.o
obj-$(CONFIG_MFD_88PM886_PMIC) += 88pm886.o
+obj-$(CONFIG_MFD_AIROHA_AN8855) += airoha-an8855.o
obj-$(CONFIG_MFD_ACT8945A) += act8945a.o
obj-$(CONFIG_MFD_SM501) += sm501.o
obj-$(CONFIG_ARCH_BCM2835) += bcm2835-pm.o
diff --git a/drivers/mfd/airoha-an8855.c b/drivers/mfd/airoha-an8855.c
new file mode 100644
index 000000000000..a2778511dfef
--- /dev/null
+++ b/drivers/mfd/airoha-an8855.c
@@ -0,0 +1,579 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Core driver for Airoha AN8855 Switch
+ *
+ * Copyright (C) 2024 Christian Marangi <ansuelsmth@gmail.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/fwnode_mdio.h>
+#include <linux/gpio/consumer.h>
+#include <linux/mfd/core.h>
+#include <linux/mdio.h>
+#include <linux/mdio/mdio-regmap.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/phy.h>
+#include <linux/regmap.h>
+
+/* Register for HW trap status */
+#define AN8855_HWTRAP 0x1000009c
+
+/*
+ * Register of the Switch ID
+ * (called Project ID in Documentation)
+ */
+#define AN8855_CREV 0x10005000
+#define AN8855_ID 0x8855 /* Switch ID */
+
+/* Register for GPHY Power Down
+ * Used to Toggle the Gigabit PHY power and enable them.
+ */
+#define AN8855_RG_GPHY_AFE_PWD 0x1028c840
+
+/* MII Registers */
+#define AN8855_PHY_SELECT_PAGE 0x1f
+#define AN8855_PHY_PAGE GENMASK(2, 0)
+#define AN8855_PHY_PAGE_STANDARD FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x0)
+#define AN8855_PHY_PAGE_EXTENDED_1 FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x1)
+#define AN8855_PHY_PAGE_EXTENDED_4 FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x4)
+
+/* MII Registers Page 4 */
+#define AN8855_PBUS_MODE 0x10
+#define AN8855_PBUS_MODE_ADDR_FIXED 0x0
+#define AN8855_PBUS_MODE_ADDR_INCR BIT(15)
+#define AN8855_PBUS_WR_ADDR_HIGH 0x11
+#define AN8855_PBUS_WR_ADDR_LOW 0x12
+#define AN8855_PBUS_WR_DATA_HIGH 0x13
+#define AN8855_PBUS_WR_DATA_LOW 0x14
+#define AN8855_PBUS_RD_ADDR_HIGH 0x15
+#define AN8855_PBUS_RD_ADDR_LOW 0x16
+#define AN8855_PBUS_RD_DATA_HIGH 0x17
+#define AN8855_PBUS_RD_DATA_LOW 0x18
+
+#define AN8855_MAX_PHY_PORT 5
+
+struct an8855_core {
+ struct mii_bus *bus;
+ struct mii_bus *phy_bus;
+ unsigned int switch_addr;
+ u16 current_page;
+};
+
+struct an8855_phy {
+ u8 addr;
+ struct an8855_core *core;
+};
+
+struct an8855_phy_bus {
+ struct mii_bus *bus;
+ struct fwnode_handle *node;
+ u8 addr;
+};
+
+static const struct mfd_cell an8855_cells[] = {
+ MFD_CELL_OF("an8855-efuse", NULL, NULL, 0, 0,
+ "airoha,an8855-efuse"),
+ MFD_CELL_OF("an8855-switch", NULL, NULL, 0, 0,
+ "airoha,an8855-switch"),
+};
+
+static int an8855_mii_set_page(struct an8855_core *priv, u8 addr,
+ u8 page) __must_hold(&priv->bus->mdio_lock)
+{
+ struct mii_bus *bus = priv->bus;
+ int ret;
+
+ ret = __mdiobus_write(bus, addr, AN8855_PHY_SELECT_PAGE, page);
+ if (ret) {
+ dev_err_ratelimited(&bus->dev, "failed to set mii page\n");
+ return ret;
+ }
+
+ /* Cache current page if next MII read/write is for Switch page */
+ priv->current_page = page;
+ return 0;
+}
+
+static int an8855_mii_read32(struct mii_bus *bus, u8 phy_id, u32 reg,
+ u32 *val) __must_hold(&bus->mdio_lock)
+{
+ int lo, hi, ret;
+
+ ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_MODE,
+ AN8855_PBUS_MODE_ADDR_FIXED);
+ if (ret)
+ goto err;
+
+ ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_RD_ADDR_HIGH,
+ upper_16_bits(reg));
+ if (ret)
+ goto err;
+
+ ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_RD_ADDR_LOW,
+ lower_16_bits(reg));
+ if (ret)
+ goto err;
+
+ hi = __mdiobus_read(bus, phy_id, AN8855_PBUS_RD_DATA_HIGH);
+ if (hi < 0) {
+ ret = hi;
+ goto err;
+ }
+
+ lo = __mdiobus_read(bus, phy_id, AN8855_PBUS_RD_DATA_LOW);
+ if (lo < 0) {
+ ret = lo;
+ goto err;
+ }
+
+ *val = ((u32)hi << 16) | lo;
+
+ return 0;
+err:
+ dev_err_ratelimited(&bus->dev, "failed to read register\n");
+ return ret;
+}
+
+/*
+ * Protect concurrent access to phy page if switch address also
+ * expose a PHY.
+ */
+static void an8855_regmap_lock(struct an8855_core *priv)
+{
+ if (priv->phy_bus)
+ mutex_lock(&priv->phy_bus->mdio_lock);
+ mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
+}
+
+static void an8855_regmap_unlock(struct an8855_core *priv)
+{
+ mutex_unlock(&priv->bus->mdio_lock);
+ if (priv->phy_bus)
+ mutex_unlock(&priv->phy_bus->mdio_lock);
+}
+
+static int an8855_regmap_read(void *ctx, uint32_t reg, uint32_t *val)
+{
+ struct an8855_core *priv = ctx;
+ struct mii_bus *bus = priv->bus;
+ u16 addr = priv->switch_addr;
+ int ret;
+
+ an8855_regmap_lock(priv);
+ ret = an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4);
+ if (ret < 0)
+ goto exit;
+
+ ret = an8855_mii_read32(bus, addr, reg, val);
+
+exit:
+ an8855_regmap_unlock(priv);
+
+ return ret < 0 ? ret : 0;
+}
+
+static int an8855_mii_write32(struct mii_bus *bus, u8 phy_id, u32 reg,
+ u32 val) __must_hold(&bus->mdio_lock)
+{
+ int ret;
+
+ ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_MODE,
+ AN8855_PBUS_MODE_ADDR_FIXED);
+ if (ret)
+ goto err;
+
+ ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_ADDR_HIGH,
+ upper_16_bits(reg));
+ if (ret)
+ goto err;
+ ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_ADDR_LOW,
+ lower_16_bits(reg));
+ if (ret)
+ goto err;
+
+ ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_DATA_HIGH,
+ upper_16_bits(val));
+ if (ret)
+ goto err;
+
+ ret = __mdiobus_write(bus, phy_id, AN8855_PBUS_WR_DATA_LOW,
+ lower_16_bits(val));
+ if (ret)
+ goto err;
+
+ return 0;
+err:
+ dev_err_ratelimited(&bus->dev,
+ "failed to write an8855 register\n");
+ return ret;
+}
+
+static int an8855_regmap_write(void *ctx, uint32_t reg, uint32_t val)
+{
+ struct an8855_core *priv = ctx;
+ struct mii_bus *bus = priv->bus;
+ u16 addr = priv->switch_addr;
+ int ret;
+
+ an8855_regmap_lock(priv);
+ ret = an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4);
+ if (ret)
+ goto exit;
+
+ ret = an8855_mii_write32(bus, addr, reg, val);
+
+exit:
+ an8855_regmap_unlock(priv);
+
+ return ret < 0 ? ret : 0;
+}
+
+static int an8855_regmap_update_bits(void *ctx, uint32_t reg, uint32_t mask,
+ uint32_t write_val)
+{
+ struct an8855_core *priv = ctx;
+ struct mii_bus *bus = priv->bus;
+ u16 addr = priv->switch_addr;
+ u32 val;
+ int ret;
+
+ an8855_regmap_lock(priv);
+ ret = an8855_mii_set_page(priv, addr, AN8855_PHY_PAGE_EXTENDED_4);
+ if (ret)
+ goto exit;
+
+ ret = an8855_mii_read32(bus, addr, reg, &val);
+ if (ret < 0)
+ goto exit;
+
+ val &= ~mask;
+ val |= write_val & mask;
+ ret = an8855_mii_write32(bus, addr, reg, val);
+
+exit:
+ an8855_regmap_unlock(priv);
+
+ return ret < 0 ? ret : 0;
+}
+
+static const struct regmap_range an8855_readable_ranges[] = {
+ regmap_reg_range(0x10000000, 0x10000fff), /* SCU */
+ regmap_reg_range(0x10001000, 0x10001fff), /* RBUS */
+ regmap_reg_range(0x10002000, 0x10002fff), /* MCU */
+ regmap_reg_range(0x10005000, 0x10005fff), /* SYS SCU */
+ regmap_reg_range(0x10007000, 0x10007fff), /* I2C Slave */
+ regmap_reg_range(0x10008000, 0x10008fff), /* I2C Master */
+ regmap_reg_range(0x10009000, 0x10009fff), /* PDMA */
+ regmap_reg_range(0x1000a100, 0x1000a2ff), /* General Purpose Timer */
+ regmap_reg_range(0x1000a200, 0x1000a2ff), /* GPU timer */
+ regmap_reg_range(0x1000a300, 0x1000a3ff), /* GPIO */
+ regmap_reg_range(0x1000a400, 0x1000a5ff), /* EFUSE */
+ regmap_reg_range(0x1000c000, 0x1000cfff), /* GDMP CSR */
+ regmap_reg_range(0x10010000, 0x1001ffff), /* GDMP SRAM */
+ regmap_reg_range(0x10200000, 0x10203fff), /* Switch - ARL Global */
+ regmap_reg_range(0x10204000, 0x10207fff), /* Switch - BMU */
+ regmap_reg_range(0x10208000, 0x1020bfff), /* Switch - ARL Port */
+ regmap_reg_range(0x1020c000, 0x1020cfff), /* Switch - SCH */
+ regmap_reg_range(0x10210000, 0x10213fff), /* Switch - MAC */
+ regmap_reg_range(0x10214000, 0x10217fff), /* Switch - MIB */
+ regmap_reg_range(0x10218000, 0x1021bfff), /* Switch - Port Control */
+ regmap_reg_range(0x1021c000, 0x1021ffff), /* Switch - TOP */
+ regmap_reg_range(0x10220000, 0x1022ffff), /* SerDes */
+ regmap_reg_range(0x10286000, 0x10286fff), /* RG Batcher */
+ regmap_reg_range(0x1028c000, 0x1028ffff), /* ETHER_SYS */
+ regmap_reg_range(0x30000000, 0x37ffffff), /* I2C EEPROM */
+ regmap_reg_range(0x38000000, 0x3fffffff), /* BOOT_ROM */
+ regmap_reg_range(0xa0000000, 0xbfffffff), /* GPHY */
+};
+
+static const struct regmap_access_table an8855_readable_table = {
+ .yes_ranges = an8855_readable_ranges,
+ .n_yes_ranges = ARRAY_SIZE(an8855_readable_ranges),
+};
+
+static const struct regmap_config an8855_regmap_config = {
+ .name = "switch",
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = 0xbfffffff,
+ .reg_read = an8855_regmap_read,
+ .reg_write = an8855_regmap_write,
+ .reg_update_bits = an8855_regmap_update_bits,
+ .disable_locking = true,
+ .rd_table = &an8855_readable_table,
+};
+
+static int an8855_regmap_phy_reset_page(struct an8855_core *priv,
+ int phy) __must_hold(&priv->bus->mdio_lock)
+{
+ /* Check PHY page only for addr shared with switch */
+ if (phy != priv->switch_addr)
+ return 0;
+
+ /* Don't restore page if it's not set to Switch page */
+ if (priv->current_page != AN8855_PHY_PAGE_EXTENDED_4)
+ return 0;
+
+ /*
+ * Restore page to 0, PHY might change page right after but that
+ * will be ignored as it won't be a switch page.
+ */
+ return an8855_mii_set_page(priv, phy, AN8855_PHY_PAGE_STANDARD);
+}
+
+static int an8855_regmap_phy_read(void *ctx, uint32_t reg, uint32_t *val)
+{
+ struct an8855_phy *priv = ctx;
+ struct an8855_core *core_priv;
+ u32 addr = priv->addr;
+ struct mii_bus *bus;
+ int ret;
+
+ core_priv = priv->core;
+ bus = core_priv->bus;
+
+ mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
+ ret = an8855_regmap_phy_reset_page(core_priv, addr);
+ if (ret)
+ goto exit;
+
+ ret = __mdiobus_read(bus, addr, reg);
+ if (ret >= 0)
+ *val = ret;
+
+exit:
+ mutex_unlock(&bus->mdio_lock);
+
+ return ret < 0 ? ret : 0;
+}
+
+static int an8855_regmap_phy_write(void *ctx, uint32_t reg, uint32_t val)
+{
+ struct an8855_phy *priv = ctx;
+ struct an8855_core *core_priv;
+ u32 addr = priv->addr;
+ struct mii_bus *bus;
+ int ret;
+
+ core_priv = priv->core;
+ bus = core_priv->bus;
+
+ mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
+ ret = an8855_regmap_phy_reset_page(core_priv, addr);
+ if (ret)
+ goto exit;
+
+ ret = __mdiobus_write(bus, addr, reg, val);
+
+exit:
+ mutex_unlock(&bus->mdio_lock);
+
+ return ret;
+}
+
+static const struct regmap_config an8855_phy_regmap_config = {
+ .reg_bits = 16,
+ .val_bits = 16,
+ .reg_read = an8855_regmap_phy_read,
+ .reg_write = an8855_regmap_phy_write,
+ .disable_locking = true,
+ .max_register = 0x1f,
+};
+
+static int an8855_read_switch_id(struct device *dev, struct regmap *regmap)
+{
+ u32 id;
+ int ret;
+
+ ret = regmap_read(regmap, AN8855_CREV, &id);
+ if (ret)
+ return ret;
+
+ if (id != AN8855_ID) {
+ dev_err(dev, "Detected Switch ID %x but %x was expected\n",
+ id, AN8855_ID);
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static int an8855_phy_bus_register(struct device *dev, struct an8855_core *priv,
+ struct device_node *phy_np,
+ struct an8855_phy_bus *phy_bus_info)
+{
+ struct mdio_regmap_config mrc = { };
+ struct an8855_phy *phy_priv;
+ struct regmap *regmap;
+ u32 addr, phy_offset;
+ struct mii_bus *bus;
+ int ret;
+
+ ret = of_property_read_u32(phy_np, "reg", &addr);
+ if (ret)
+ return ret;
+
+ phy_offset = addr - priv->switch_addr;
+ if (phy_offset >= AN8855_MAX_PHY_PORT)
+ return -EINVAL;
+
+ phy_priv = devm_kzalloc(dev, sizeof(*phy_priv), GFP_KERNEL);
+ if (!phy_priv)
+ return -ENOMEM;
+
+ phy_priv->addr = addr;
+ phy_priv->core = priv;
+
+ regmap = devm_regmap_init(dev, NULL, phy_priv, &an8855_phy_regmap_config);
+ if (IS_ERR(regmap))
+ return dev_err_probe(dev, PTR_ERR(regmap),
+ "phy%d regmap initialization failed\n",
+ addr);
+
+ mrc.regmap = regmap;
+ mrc.parent = dev;
+ mrc.valid_addr = addr;
+ snprintf(mrc.name, MII_BUS_ID_SIZE, "%s-phy%u", dev_name(dev), addr);
+
+ bus = devm_mdio_regmap_register(dev, &mrc);
+ if (IS_ERR(bus))
+ return PTR_ERR(bus);
+
+ if (addr == priv->switch_addr)
+ priv->phy_bus = bus;
+
+ phy_bus_info->bus = bus;
+ phy_bus_info->addr = addr;
+ phy_bus_info->node = fwnode_handle_get(of_fwnode_handle(phy_np));
+
+ return 0;
+}
+
+static int an8855_mdio_register(struct device *dev, struct an8855_core *priv,
+ struct an8855_phy_bus *phy_bus_infos)
+{
+ struct device_node *mdio_np;
+ int ret = 0;
+ int i = 0;
+
+ mdio_np = of_get_child_by_name(dev->of_node, "mdio");
+ if (!mdio_np)
+ return -ENODEV;
+
+ for_each_available_child_of_node_scoped(mdio_np, phy_np) {
+ if (i >= AN8855_MAX_PHY_PORT) {
+ ret = -EINVAL;
+ goto exit;
+ }
+
+ ret = an8855_phy_bus_register(dev, priv, phy_np,
+ &phy_bus_infos[i]);
+ if (ret)
+ goto exit;
+
+ i++;
+ }
+
+exit:
+ of_node_put(mdio_np);
+ if (ret) {
+ while (i--)
+ fwnode_handle_put(phy_bus_infos[i].node);
+
+ return ret;
+ }
+
+ return i;
+}
+
+static int an8855_core_probe(struct mdio_device *mdiodev)
+{
+ struct an8855_phy_bus phy_bus_infos[AN8855_MAX_PHY_PORT] = { };
+ struct device *dev = &mdiodev->dev;
+ struct an8855_core *priv;
+ struct regmap *regmap;
+ int num_phys;
+ int i, ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->bus = mdiodev->bus;
+ priv->switch_addr = mdiodev->addr;
+ /* No DMA for mdiobus, mute warning for DMA mask not set */
+ dev->dma_mask = &dev->coherent_dma_mask;
+
+ /* Register virtual MDIO for each PHY */
+ num_phys = an8855_mdio_register(dev, priv, phy_bus_infos);
+ if (num_phys < 0)
+ return num_phys;
+
+ regmap = devm_regmap_init(dev, NULL, priv, &an8855_regmap_config);
+ if (IS_ERR(regmap)) {
+ ret = PTR_ERR(regmap);
+ dev_err_probe(dev, ret, "regmap initialization failed\n");
+ goto err_put_fwnodes;
+ }
+
+ /* Reset PHY page for switch address */
+ mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
+ ret = an8855_mii_set_page(priv, priv->switch_addr,
+ AN8855_PHY_PAGE_STANDARD);
+ mutex_unlock(&priv->bus->mdio_lock);
+ if (ret)
+ goto err_put_fwnodes;
+
+ ret = an8855_read_switch_id(dev, regmap);
+ if (ret)
+ goto err_put_fwnodes;
+
+ /* Release global PHY power down */
+ ret = regmap_write(regmap, AN8855_RG_GPHY_AFE_PWD, 0x0);
+ if (ret)
+ goto err_put_fwnodes;
+
+ /* Register PHYs */
+ for (i = 0; i < num_phys; i++) {
+ ret = fwnode_mdiobus_register_phy(phy_bus_infos[i].bus,
+ phy_bus_infos[i].node,
+ phy_bus_infos[i].addr);
+ fwnode_handle_put(phy_bus_infos[i].node);
+ phy_bus_infos[i].node = NULL;
+
+ if (ret)
+ goto err_put_fwnodes;
+ }
+
+ return devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, an8855_cells,
+ ARRAY_SIZE(an8855_cells), NULL, 0,
+ NULL);
+
+err_put_fwnodes:
+ for (i = 0; i < num_phys; i++)
+ if (phy_bus_infos[i].node)
+ fwnode_handle_put(phy_bus_infos[i].node);
+
+ return ret;
+}
+
+static const struct of_device_id an8855_core_of_match[] = {
+ { .compatible = "airoha,an8855" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, an8855_core_of_match);
+
+static struct mdio_driver an8855_core_driver = {
+ .probe = an8855_core_probe,
+ .mdiodrv.driver = {
+ .name = "an8855",
+ .of_match_table = an8855_core_of_match,
+ },
+};
+mdio_module_driver(an8855_core_driver);
+
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
+MODULE_DESCRIPTION("Driver for Airoha AN8855");
+MODULE_LICENSE("GPL");
--
2.55.0
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH net-next v25 05/10] net: phy: Add Airoha AN8855 Internal Switch Gigabit PHY
2026-10-09 16:10 [PATCH net-next v25 00/10] net: dsa: Add Airoha AN8855 support Christian Marangi
` (3 preceding siblings ...)
2026-10-09 16:10 ` [PATCH net-next v25 04/10] mfd: an8855: Add support for Airoha AN8855 Switch Christian Marangi
@ 2026-10-09 16:10 ` Christian Marangi
2026-10-10 16:19 ` netdev-bot+sashiko
2026-10-09 16:10 ` [PATCH net-next v25 06/10] net: dsa: tag_mtk: add Airoha variant usage of this TAG Christian Marangi
` (4 subsequent siblings)
9 siblings, 1 reply; 18+ messages in thread
From: Christian Marangi @ 2026-10-09 16:10 UTC (permalink / raw)
To: Christian Marangi, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Vladimir Oltean, Matthias Brugger,
AngeloGioacchino Del Regno, Chester A. Unal, Daniel Golle,
Heiner Kallweit, Russell King, Simon Horman, Joris Vaisvila,
linux-arm-kernel, linux-mediatek, netdev, mfd, devicetree,
linux-kernel
Cc: Andrew Lunn
Add support for Airoha AN8855 Internal Switch Gigabit PHY.
This is a simple PHY driver to configure and calibrate the PHY for the
AN8855 Switch with the use of NVMEM cells.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
---
drivers/net/phy/Kconfig | 6 +
drivers/net/phy/Makefile | 1 +
drivers/net/phy/air_an8855.c | 275 +++++++++++++++++++++++++++++++++++
3 files changed, 282 insertions(+)
create mode 100644 drivers/net/phy/air_an8855.c
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index d3835597e379..eca2ce135c86 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -96,6 +96,12 @@ config AIR_AN8801_PHY
help
Currently supports the Airoha AN8801R PHY.
+config AIR_AN8855_PHY
+ tristate "Airoha AN8855 Internal Gigabit PHY"
+ depends on NVMEM || !NVMEM
+ help
+ Currently supports the internal Airoha AN8855 Switch PHY.
+
config AIR_EN8811H_PHY
tristate "Airoha EN8811H 2.5 Gigabit PHY"
select AIR_NET_PHYLIB
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 579066a638f0..d5c633db0742 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -31,6 +31,7 @@ obj-$(CONFIG_ADIN_PHY) += adin.o
obj-$(CONFIG_ADIN1100_PHY) += adin1100.o
obj-$(CONFIG_ADIN1140_PHY) += adin1140-phy.o
obj-$(CONFIG_AIR_AN8801_PHY) += air_an8801.o
+obj-$(CONFIG_AIR_AN8855_PHY) += air_an8855.o
obj-$(CONFIG_AIR_EN8811H_PHY) += air_en8811h.o
obj-$(CONFIG_AIR_NET_PHYLIB) += air_phy_lib.o
obj-$(CONFIG_AMD_PHY) += amd.o
diff --git a/drivers/net/phy/air_an8855.c b/drivers/net/phy/air_an8855.c
new file mode 100644
index 000000000000..bc22256fd5f9
--- /dev/null
+++ b/drivers/net/phy/air_an8855.c
@@ -0,0 +1,275 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2024 Christian Marangi <ansuelsmth@gmail.com>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/module.h>
+#include <linux/nvmem-consumer.h>
+#include <linux/of.h>
+#include <linux/phy.h>
+
+#define AN8855_PHY_SELECT_PAGE 0x1f
+#define AN8855_PHY_PAGE GENMASK(2, 0)
+#define AN8855_PHY_PAGE_STANDARD FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x0)
+#define AN8855_PHY_PAGE_EXTENDED_1 FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x1)
+
+/* MII Registers Page 1 */
+#define AN8855_PHY_EXT_REG_14 0x14
+#define AN8855_PHY_EN_DOWN_SHIFT BIT(4)
+
+/* R50 Calibration regs in MDIO_MMD_VEND1 */
+#define AN8855_PHY_R50OHM_RSEL_TX_AB 0x174
+#define AN8855_PHY_R50OHM_RSEL_TX_A_EN BIT(15)
+#define AN8855_PHY_R50OHM_RSEL_TX_A GENMASK(14, 8)
+#define AN8855_PHY_R50OHM_RSEL_TX_B_EN BIT(7)
+#define AN8855_PHY_R50OHM_RSEL_TX_B GENMASK(6, 0)
+#define AN8855_PHY_R50OHM_RSEL_TX_CD 0x175
+#define AN8855_PHY_R50OHM_RSEL_TX_C_EN BIT(15)
+#define AN8855_PHY_R50OHM_RSEL_TX_C GENMASK(14, 8)
+#define AN8855_PHY_R50OHM_RSEL_TX_D_EN BIT(7)
+#define AN8855_PHY_R50OHM_RSEL_TX_D GENMASK(6, 0)
+
+#define AN8855_SWITCH_EFUSE_R50O GENMASK(30, 24)
+
+/* PHY TX PAIR DELAY SELECT Register */
+#define AN8855_PHY_TX_PAIR_DLY_SEL_GBE 0x013
+#define AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_A_GBE GENMASK(14, 12)
+#define AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_B_GBE GENMASK(10, 8)
+#define AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_C_GBE GENMASK(6, 4)
+#define AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_D_GBE GENMASK(2, 0)
+/* PHY ADC Register */
+#define AN8855_PHY_RXADC_CTRL 0x0d8
+#define AN8855_PHY_RG_AD_SAMPLE_PHSEL_A BIT(12)
+#define AN8855_PHY_RG_AD_SAMPLE_PHSEL_B BIT(8)
+#define AN8855_PHY_RG_AD_SAMPLE_PHSEL_C BIT(4)
+#define AN8855_PHY_RG_AD_SAMPLE_PHSEL_D BIT(0)
+#define AN8855_PHY_RXADC_REV_0 0x0d9
+#define AN8855_PHY_RG_AD_RESERVE0_A GENMASK(15, 8)
+#define AN8855_PHY_RG_AD_RESERVE0_B GENMASK(7, 0)
+#define AN8855_PHY_RXADC_REV_1 0x0da
+#define AN8855_PHY_RG_AD_RESERVE0_C GENMASK(15, 8)
+#define AN8855_PHY_RG_AD_RESERVE0_D GENMASK(7, 0)
+
+#define AN8855_PHY_ID 0xc0ff0410
+
+struct air_an8855_priv {
+ bool needs_calibration;
+ u8 calibration_data[4];
+};
+
+static const u8 dsa_r50ohm_table[] = {
+ 127, 127, 127, 127, 127, 127, 127, 127, 127, 127,
+ 127, 127, 127, 127, 127, 127, 127, 126, 122, 117,
+ 112, 109, 104, 101, 97, 94, 90, 88, 84, 80,
+ 78, 74, 72, 68, 66, 64, 61, 58, 56, 53,
+ 51, 48, 47, 44, 42, 40, 38, 36, 34, 32,
+ 31, 28, 27, 24, 24, 22, 20, 18, 16, 16,
+ 14, 12, 11, 9
+};
+
+static int an8855_get_r50ohm_val(struct device *dev, const char *calib_name,
+ u8 *dest)
+{
+ u32 shift_sel, val;
+ int ret;
+ int i;
+
+ ret = nvmem_cell_read_u32(dev, calib_name, &val);
+ if (ret)
+ return ret;
+
+ shift_sel = FIELD_GET(AN8855_SWITCH_EFUSE_R50O, val);
+ for (i = 0; i < ARRAY_SIZE(dsa_r50ohm_table); i++)
+ if (dsa_r50ohm_table[i] == shift_sel)
+ break;
+
+ if (i < 8 || i >= ARRAY_SIZE(dsa_r50ohm_table))
+ *dest = dsa_r50ohm_table[25];
+ else
+ *dest = dsa_r50ohm_table[i - 8];
+
+ return 0;
+}
+
+static int an8855_probe(struct phy_device *phydev)
+{
+ struct device *dev = &phydev->mdio.dev;
+ struct air_an8855_priv *priv;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->needs_calibration = of_property_present(dev->of_node,
+ "nvmem-cells");
+
+ if (priv->needs_calibration) {
+ int ret;
+
+ ret = an8855_get_r50ohm_val(dev, "tx_a", &priv->calibration_data[0]);
+ if (ret)
+ return ret;
+
+ ret = an8855_get_r50ohm_val(dev, "tx_b", &priv->calibration_data[1]);
+ if (ret)
+ return ret;
+
+ ret = an8855_get_r50ohm_val(dev, "tx_c", &priv->calibration_data[2]);
+ if (ret)
+ return ret;
+
+ ret = an8855_get_r50ohm_val(dev, "tx_d", &priv->calibration_data[3]);
+ if (ret)
+ return ret;
+ }
+
+ phydev->priv = priv;
+
+ return 0;
+}
+
+static int an8855_get_downshift(struct phy_device *phydev, u8 *data)
+{
+ int val;
+
+ val = phy_read_paged(phydev, AN8855_PHY_PAGE_EXTENDED_1, AN8855_PHY_EXT_REG_14);
+ if (val < 0)
+ return val;
+
+ *data = val & AN8855_PHY_EN_DOWN_SHIFT ? DOWNSHIFT_DEV_DEFAULT_COUNT :
+ DOWNSHIFT_DEV_DISABLE;
+
+ return 0;
+}
+
+static int an8855_set_downshift(struct phy_device *phydev, u8 cnt)
+{
+ u16 ds = cnt != DOWNSHIFT_DEV_DISABLE ? AN8855_PHY_EN_DOWN_SHIFT : 0;
+
+ return phy_modify_paged(phydev, AN8855_PHY_PAGE_EXTENDED_1,
+ AN8855_PHY_EXT_REG_14, AN8855_PHY_EN_DOWN_SHIFT,
+ ds);
+}
+
+static int an8855_config_init(struct phy_device *phydev)
+{
+ struct air_an8855_priv *priv = phydev->priv;
+ int ret;
+
+ /* Enable HW auto downshift */
+ ret = an8855_set_downshift(phydev, DOWNSHIFT_DEV_DEFAULT_COUNT);
+ if (ret)
+ return ret;
+
+ if (priv->needs_calibration) {
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_R50OHM_RSEL_TX_AB,
+ AN8855_PHY_R50OHM_RSEL_TX_A_EN | AN8855_PHY_R50OHM_RSEL_TX_A |
+ AN8855_PHY_R50OHM_RSEL_TX_B_EN | AN8855_PHY_R50OHM_RSEL_TX_B,
+ AN8855_PHY_R50OHM_RSEL_TX_A_EN |
+ FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_A,
+ priv->calibration_data[0]) |
+ AN8855_PHY_R50OHM_RSEL_TX_B_EN |
+ FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_B,
+ priv->calibration_data[1]));
+ if (ret)
+ return ret;
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_R50OHM_RSEL_TX_CD,
+ AN8855_PHY_R50OHM_RSEL_TX_C_EN | AN8855_PHY_R50OHM_RSEL_TX_C |
+ AN8855_PHY_R50OHM_RSEL_TX_D_EN | AN8855_PHY_R50OHM_RSEL_TX_D,
+ AN8855_PHY_R50OHM_RSEL_TX_C_EN |
+ FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_C,
+ priv->calibration_data[2]) |
+ AN8855_PHY_R50OHM_RSEL_TX_D_EN |
+ FIELD_PREP(AN8855_PHY_R50OHM_RSEL_TX_D,
+ priv->calibration_data[3]));
+ if (ret)
+ return ret;
+ }
+
+ /* Apply values to reduce signal noise */
+ ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_TX_PAIR_DLY_SEL_GBE,
+ AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_A_GBE |
+ AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_C_GBE,
+ FIELD_PREP(AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_A_GBE, 0x4) |
+ FIELD_PREP(AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_C_GBE, 0x4));
+ if (ret)
+ return ret;
+ ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_RXADC_CTRL,
+ AN8855_PHY_RG_AD_SAMPLE_PHSEL_A |
+ AN8855_PHY_RG_AD_SAMPLE_PHSEL_C);
+ if (ret)
+ return ret;
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_RXADC_REV_0,
+ FIELD_PREP(AN8855_PHY_RG_AD_RESERVE0_A, 0x1));
+ if (ret)
+ return ret;
+ ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_RXADC_REV_1,
+ FIELD_PREP(AN8855_PHY_RG_AD_RESERVE0_C, 0x1));
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static int an8855_get_tunable(struct phy_device *phydev,
+ struct ethtool_tunable *tuna, void *data)
+{
+ switch (tuna->id) {
+ case ETHTOOL_PHY_DOWNSHIFT:
+ return an8855_get_downshift(phydev, data);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static int an8855_set_tunable(struct phy_device *phydev,
+ struct ethtool_tunable *tuna, const void *data)
+{
+ switch (tuna->id) {
+ case ETHTOOL_PHY_DOWNSHIFT:
+ return an8855_set_downshift(phydev, *(const u8 *)data);
+ default:
+ return -EOPNOTSUPP;
+ }
+}
+
+static int an8855_read_page(struct phy_device *phydev)
+{
+ return __phy_read(phydev, AN8855_PHY_SELECT_PAGE);
+}
+
+static int an8855_write_page(struct phy_device *phydev, int page)
+{
+ return __phy_write(phydev, AN8855_PHY_SELECT_PAGE, page);
+}
+
+static struct phy_driver an8855_driver[] = {
+{
+ PHY_ID_MATCH_EXACT(AN8855_PHY_ID),
+ .name = "Airoha AN8855 internal PHY",
+ /* PHY_GBIT_FEATURES */
+ .flags = PHY_IS_INTERNAL,
+ .probe = an8855_probe,
+ .config_init = an8855_config_init,
+ .soft_reset = genphy_soft_reset,
+ .get_tunable = an8855_get_tunable,
+ .set_tunable = an8855_set_tunable,
+ .suspend = genphy_suspend,
+ .resume = genphy_resume,
+ .read_page = an8855_read_page,
+ .write_page = an8855_write_page,
+}, };
+
+module_phy_driver(an8855_driver);
+
+static struct mdio_device_id __maybe_unused an8855_tbl[] = {
+ { PHY_ID_MATCH_EXACT(AN8855_PHY_ID) },
+ { }
+};
+
+MODULE_DEVICE_TABLE(mdio, an8855_tbl);
+
+MODULE_DESCRIPTION("Airoha AN8855 PHY driver");
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
+MODULE_LICENSE("GPL");
--
2.55.0
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH net-next v25 06/10] net: dsa: tag_mtk: add Airoha variant usage of this TAG
2026-10-09 16:10 [PATCH net-next v25 00/10] net: dsa: Add Airoha AN8855 support Christian Marangi
` (4 preceding siblings ...)
2026-10-09 16:10 ` [PATCH net-next v25 05/10] net: phy: Add Airoha AN8855 Internal Switch Gigabit PHY Christian Marangi
@ 2026-10-09 16:10 ` Christian Marangi
2026-10-10 16:19 ` netdev-bot+sashiko
2026-10-09 16:10 ` [PATCH net-next v25 07/10] MAINTAINERS: add myself as maintainer for Airoha AN8855 Switch Christian Marangi
` (3 subsequent siblings)
9 siblings, 1 reply; 18+ messages in thread
From: Christian Marangi @ 2026-10-09 16:10 UTC (permalink / raw)
To: Christian Marangi, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Vladimir Oltean, Matthias Brugger,
AngeloGioacchino Del Regno, Chester A. Unal, Daniel Golle,
Heiner Kallweit, Russell King, Simon Horman, Joris Vaisvila,
linux-arm-kernel, linux-mediatek, netdev, mfd, devicetree,
linux-kernel
Cc: Andrew Lunn
Add variant of the MTK TAG for Airoha Switch and comments about difference
between Airoha AN8855 and Mediatek tag bitmap.
Airoha AN8855 doesn't support controlling SA learning and Leaky VLAN
from tag. Although these bits are not used (and even not defined for
Leaky VLAN), it's worth to add comments for these difference to prevent
any kind of regression in the future if ever these bits will be used.
Rework the makefile, config and tag driver to better report to
external tool (like libpcap) the usage of this variant with a dedicated
"Airoha" name.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
---
include/net/dsa.h | 2 ++
net/dsa/Kconfig | 11 +++++++++++
net/dsa/Makefile | 2 +-
net/dsa/tag_mtk.c | 36 +++++++++++++++++++++++++++++++++---
4 files changed, 47 insertions(+), 4 deletions(-)
diff --git a/include/net/dsa.h b/include/net/dsa.h
index 5d12191b6f6f..9824c63ad50b 100644
--- a/include/net/dsa.h
+++ b/include/net/dsa.h
@@ -62,6 +62,7 @@ struct tc_action;
#define DSA_TAG_PROTO_KSZ8463_VALUE 34
#define DSA_TAG_PROTO_MT7628_VALUE 35
#define DSA_TAG_PROTO_KS8995_VALUE 36
+#define DSA_TAG_PROTO_AIROHA_VALUE 37
enum dsa_tag_protocol {
DSA_TAG_PROTO_NONE = DSA_TAG_PROTO_NONE_VALUE,
@@ -76,6 +77,7 @@ enum dsa_tag_protocol {
DSA_TAG_PROTO_KSZ9893 = DSA_TAG_PROTO_KSZ9893_VALUE,
DSA_TAG_PROTO_LAN9303 = DSA_TAG_PROTO_LAN9303_VALUE,
DSA_TAG_PROTO_MTK = DSA_TAG_PROTO_MTK_VALUE,
+ DSA_TAG_PROTO_AIROHA = DSA_TAG_PROTO_AIROHA_VALUE,
DSA_TAG_PROTO_QCA = DSA_TAG_PROTO_QCA_VALUE,
DSA_TAG_PROTO_TRAILER = DSA_TAG_PROTO_TRAILER_VALUE,
DSA_TAG_PROTO_8021Q = DSA_TAG_PROTO_8021Q_VALUE,
diff --git a/net/dsa/Kconfig b/net/dsa/Kconfig
index 4f44bf3ede23..28a249f04a43 100644
--- a/net/dsa/Kconfig
+++ b/net/dsa/Kconfig
@@ -24,6 +24,13 @@ config NET_DSA_TAG_NONE
Say Y or M if you want to enable support for switches which don't tag
frames over the CPU port.
+config NET_DSA_TAG_AIROHA
+ tristate "Tag driver for Airoha switches"
+ select NET_DSA_TAG_MTK_COMMON
+ help
+ Say Y or M if you want to enable support for tagging frames for
+ Airoha switches.
+
config NET_DSA_TAG_AR9331
tristate "Tag driver for Atheros AR9331 SoC with built-in switch"
help
@@ -104,8 +111,12 @@ config NET_DSA_TAG_MT7628
Say Y or M if you want to enable support for tagging frames for the
switch embedded in the MT7628 SoC.
+config NET_DSA_TAG_MTK_COMMON
+ tristate
+
config NET_DSA_TAG_MTK
tristate "Tag driver for Mediatek switches"
+ select NET_DSA_TAG_MTK_COMMON
help
Say Y or M if you want to enable support for tagging frames for
Mediatek switches.
diff --git a/net/dsa/Makefile b/net/dsa/Makefile
index 1f9cc30e9988..7ccaa528a989 100644
--- a/net/dsa/Makefile
+++ b/net/dsa/Makefile
@@ -29,7 +29,7 @@ obj-$(CONFIG_NET_DSA_TAG_KS8995) += tag_ks8995.o
obj-$(CONFIG_NET_DSA_TAG_KSZ) += tag_ksz.o
obj-$(CONFIG_NET_DSA_TAG_LAN9303) += tag_lan9303.o
obj-$(CONFIG_NET_DSA_TAG_MT7628) += tag_mt7628.o
-obj-$(CONFIG_NET_DSA_TAG_MTK) += tag_mtk.o
+obj-$(CONFIG_NET_DSA_TAG_MTK_COMMON) += tag_mtk.o
obj-$(CONFIG_NET_DSA_TAG_MXL_862XX) += tag_mxl862xx.o
obj-$(CONFIG_NET_DSA_TAG_MXL_GSW1XX) += tag_mxl-gsw1xx.o
obj-$(CONFIG_NET_DSA_TAG_NETC) += tag_netc.o
diff --git a/net/dsa/tag_mtk.c b/net/dsa/tag_mtk.c
index c7dc7731675e..f8087d768da6 100644
--- a/net/dsa/tag_mtk.c
+++ b/net/dsa/tag_mtk.c
@@ -11,6 +11,7 @@
#include "tag.h"
#define MTK_NAME "mtk"
+#define AIROHA_NAME "airoha"
#define MTK_HDR_LEN 4
#define MTK_HDR_XMIT_UNTAGGED 0
@@ -18,6 +19,9 @@
#define MTK_HDR_XMIT_TAGGED_TPID_88A8 2
#define MTK_HDR_RECV_SOURCE_PORT_MASK GENMASK(2, 0)
#define MTK_HDR_XMIT_DP_BIT_MASK GENMASK(5, 0)
+/* AN8855 doesn't support SA_DIS and Leaky VLAN
+ * control in tag as these bits doesn't exist.
+ */
#define MTK_HDR_XMIT_SA_DIS BIT(6)
static struct sk_buff *mtk_tag_xmit(struct sk_buff *skb,
@@ -99,6 +103,7 @@ static struct sk_buff *mtk_tag_rcv(struct sk_buff *skb, struct net_device *dev)
return skb;
}
+#if IS_ENABLED(CONFIG_NET_DSA_TAG_MTK)
static const struct dsa_device_ops mtk_netdev_ops = {
.name = MTK_NAME,
.proto = DSA_TAG_PROTO_MTK,
@@ -107,8 +112,33 @@ static const struct dsa_device_ops mtk_netdev_ops = {
.needed_headroom = MTK_HDR_LEN,
};
-MODULE_DESCRIPTION("DSA tag driver for Mediatek switches");
-MODULE_LICENSE("GPL");
+DSA_TAG_DRIVER(mtk_netdev_ops);
MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_MTK, MTK_NAME);
+#endif
-module_dsa_tag_driver(mtk_netdev_ops);
+#if IS_ENABLED(CONFIG_NET_DSA_TAG_AIROHA)
+static const struct dsa_device_ops airoha_netdev_ops = {
+ .name = AIROHA_NAME,
+ .proto = DSA_TAG_PROTO_AIROHA,
+ .xmit = mtk_tag_xmit,
+ .rcv = mtk_tag_rcv,
+ .needed_headroom = MTK_HDR_LEN,
+};
+
+DSA_TAG_DRIVER(airoha_netdev_ops);
+MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_AIROHA, AIROHA_NAME);
+#endif
+
+static struct dsa_tag_driver *dsa_tag_driver_array[] = {
+#if IS_ENABLED(CONFIG_NET_DSA_TAG_MTK)
+ &DSA_TAG_DRIVER_NAME(mtk_netdev_ops),
+#endif
+#if IS_ENABLED(CONFIG_NET_DSA_TAG_AIROHA)
+ &DSA_TAG_DRIVER_NAME(airoha_netdev_ops),
+#endif
+};
+
+module_dsa_tag_drivers(dsa_tag_driver_array);
+
+MODULE_DESCRIPTION("DSA tag driver for Mediatek switches");
+MODULE_LICENSE("GPL");
--
2.55.0
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH net-next v25 07/10] MAINTAINERS: add myself as maintainer for Airoha AN8855 Switch
2026-10-09 16:10 [PATCH net-next v25 00/10] net: dsa: Add Airoha AN8855 support Christian Marangi
` (5 preceding siblings ...)
2026-10-09 16:10 ` [PATCH net-next v25 06/10] net: dsa: tag_mtk: add Airoha variant usage of this TAG Christian Marangi
@ 2026-10-09 16:10 ` Christian Marangi
2026-10-09 16:10 ` [PATCH net-next v25 08/10] net: dsa: move mediatek DSA driver in dedicated directory Christian Marangi
` (2 subsequent siblings)
9 siblings, 0 replies; 18+ messages in thread
From: Christian Marangi @ 2026-10-09 16:10 UTC (permalink / raw)
To: Christian Marangi, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Vladimir Oltean, Matthias Brugger,
AngeloGioacchino Del Regno, Chester A. Unal, Daniel Golle,
Heiner Kallweit, Russell King, Simon Horman, Joris Vaisvila,
linux-arm-kernel, linux-mediatek, netdev, mfd, devicetree,
linux-kernel
Cc: Andrew Lunn
Add myself as maintainer for AN8855 DSA driver and all the related
subdriver (mfd, mdio, phy, nvmem)
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
---
MAINTAINERS | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 509b35b5a0e7..53dcff93f896 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -759,6 +759,22 @@ S: Maintained
F: Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml
F: drivers/net/ethernet/airoha/
+AIROHA AN8855 DSA DRIVER
+M: Christian Marangi <ansuelsmth@gmail.com>
+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
+L: linux-mediatek@lists.infradead.org (moderated for non-subscribers)
+L: netdev@vger.kernel.org
+S: Maintained
+F: Documentation/devicetree/bindings/mfd/airoha,an8855.yaml
+F: Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml
+F: Documentation/devicetree/bindings/net/dsa/airoha,an8855-switch.yaml
+F: Documentation/devicetree/bindings/nvmem/airoha,an8855-efuse.yaml
+F: drivers/mfd/airoha-an8855.c
+F: drivers/net/dsa/mediatek/an8855.c
+F: drivers/net/dsa/mediatek/an8855.h
+F: drivers/net/phy/air_an8855.c
+F: drivers/nvmem/an8855-efuse.c
+
AIROHA PCIE PHY DRIVER
M: Lorenzo Bianconi <lorenzo@kernel.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
--
2.55.0
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH net-next v25 08/10] net: dsa: move mediatek DSA driver in dedicated directory
2026-10-09 16:10 [PATCH net-next v25 00/10] net: dsa: Add Airoha AN8855 support Christian Marangi
` (6 preceding siblings ...)
2026-10-09 16:10 ` [PATCH net-next v25 07/10] MAINTAINERS: add myself as maintainer for Airoha AN8855 Switch Christian Marangi
@ 2026-10-09 16:10 ` Christian Marangi
2026-10-09 16:10 ` [PATCH net-next v25 09/10] net: dsa: mt7530: generalize and move common function to lib module Christian Marangi
2026-10-09 16:10 ` [PATCH net-next v25 10/10] net: dsa: Add Airoha AN8855 5-Port Gigabit DSA Switch driver Christian Marangi
9 siblings, 0 replies; 18+ messages in thread
From: Christian Marangi @ 2026-10-09 16:10 UTC (permalink / raw)
To: Christian Marangi, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Vladimir Oltean, Matthias Brugger,
AngeloGioacchino Del Regno, Chester A. Unal, Daniel Golle,
Heiner Kallweit, Russell King, Simon Horman, Joris Vaisvila,
linux-arm-kernel, linux-mediatek, netdev, mfd, devicetree,
linux-kernel
To tidy things up and better organize DSA drivers, move the Mediatek
related driver to the dedicated Vendor directory.
MAINTAINERS file is updated accordingly to reference the new location.
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
MAINTAINERS | 6 +--
drivers/net/dsa/Kconfig | 45 +-------------------
drivers/net/dsa/Makefile | 5 +--
drivers/net/dsa/mediatek/Kconfig | 45 ++++++++++++++++++++
drivers/net/dsa/mediatek/Makefile | 5 +++
drivers/net/dsa/{ => mediatek}/mt7530-mdio.c | 0
drivers/net/dsa/{ => mediatek}/mt7530-mmio.c | 0
drivers/net/dsa/{ => mediatek}/mt7530.c | 0
drivers/net/dsa/{ => mediatek}/mt7530.h | 0
drivers/net/dsa/{ => mediatek}/mt7628.c | 0
10 files changed, 55 insertions(+), 51 deletions(-)
create mode 100644 drivers/net/dsa/mediatek/Kconfig
create mode 100644 drivers/net/dsa/mediatek/Makefile
rename drivers/net/dsa/{ => mediatek}/mt7530-mdio.c (100%)
rename drivers/net/dsa/{ => mediatek}/mt7530-mmio.c (100%)
rename drivers/net/dsa/{ => mediatek}/mt7530.c (100%)
rename drivers/net/dsa/{ => mediatek}/mt7530.h (100%)
rename drivers/net/dsa/{ => mediatek}/mt7628.c (100%)
diff --git a/MAINTAINERS b/MAINTAINERS
index 53dcff93f896..e16c14ea38a1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -16841,9 +16841,9 @@ M: Chester A. Unal <chester.a.unal@arinc9.com>
M: Daniel Golle <daniel@makrotopia.org>
L: netdev@vger.kernel.org
S: Maintained
-F: drivers/net/dsa/mt7530-mdio.c
-F: drivers/net/dsa/mt7530-mmio.c
-F: drivers/net/dsa/mt7530.*
+F: drivers/net/dsa/mediatek/mt7530-mdio.c
+F: drivers/net/dsa/mediatek/mt7530-mmio.c
+F: drivers/net/dsa/mediatek/mt7530.*
F: net/dsa/tag_mtk.c
MEDIATEK T7XX 5G WWAN MODEM DRIVER
diff --git a/drivers/net/dsa/Kconfig b/drivers/net/dsa/Kconfig
index fe8cd5338fda..ffc26eb3e899 100644
--- a/drivers/net/dsa/Kconfig
+++ b/drivers/net/dsa/Kconfig
@@ -28,50 +28,7 @@ source "drivers/net/dsa/hirschmann/Kconfig"
source "drivers/net/dsa/lantiq/Kconfig"
-config NET_DSA_MT7530
- tristate "MediaTek MT7530 and MT7531 Ethernet switch support"
- select NET_DSA_TAG_MTK
- select REGMAP_IRQ
- imply NET_DSA_MT7530_MDIO
- imply NET_DSA_MT7530_MMIO
- help
- This enables support for the MediaTek MT7530 and MT7531 Ethernet
- switch chips. Multi-chip module MT7530 in MT7621AT, MT7621DAT,
- MT7621ST and MT7623AI SoCs, and built-in switch in MT7988 SoC are
- supported as well.
-
-config NET_DSA_MT7530_MDIO
- tristate "MediaTek MT7530 MDIO interface driver"
- depends on NET_DSA_MT7530
- select MEDIATEK_GE_PHY
- select PCS_MTK_LYNXI
- help
- This enables support for the MediaTek MT7530 and MT7531 switch
- chips which are connected via MDIO, as well as multi-chip
- module MT7530 which can be found in the MT7621AT, MT7621DAT,
- MT7621ST and MT7623AI SoCs.
-
-config NET_DSA_MT7530_MMIO
- tristate "MediaTek MT7530 MMIO interface driver"
- depends on NET_DSA_MT7530
- depends on HAS_IOMEM
- imply MEDIATEK_GE_SOC_PHY
- help
- This enables support for the built-in Ethernet switch found
- in the MediaTek MT7988 SoC.
- The switch is a similar design as MT7531, but the switch registers
- are directly mapped into the SoCs register space rather than being
- accessible via MDIO.
-
-config NET_DSA_MT7628
- tristate "MediaTek MT7628 Embedded Ethernet switch support"
- depends on HAS_IOMEM && (SOC_MT7620 || COMPILE_TEST)
- select NET_DSA_TAG_MT7628
- select MEDIATEK_FE_SOC_PHY
- select REGMAP_MMIO
- help
- This enables support for the built-in Ethernet switch found
- in the MT7628 SoC.
+source "drivers/net/dsa/mediatek/Kconfig"
config NET_DSA_MV88E6060
tristate "Marvell 88E6060 ethernet switch chip support"
diff --git a/drivers/net/dsa/Makefile b/drivers/net/dsa/Makefile
index 7e637d56b35c..ee4784a9839b 100644
--- a/drivers/net/dsa/Makefile
+++ b/drivers/net/dsa/Makefile
@@ -2,10 +2,6 @@
obj-$(CONFIG_NET_DSA_BCM_SF2) += bcm-sf2.o
bcm-sf2-objs := bcm_sf2.o bcm_sf2_cfp.o
obj-$(CONFIG_NET_DSA_LOOP) += dsa_loop.o
-obj-$(CONFIG_NET_DSA_MT7530) += mt7530.o
-obj-$(CONFIG_NET_DSA_MT7530_MDIO) += mt7530-mdio.o
-obj-$(CONFIG_NET_DSA_MT7530_MMIO) += mt7530-mmio.o
-obj-$(CONFIG_NET_DSA_MT7628) += mt7628.o
obj-$(CONFIG_NET_DSA_MV88E6060) += mv88e6060.o
obj-$(CONFIG_NET_DSA_RZN1_A5PSW) += rzn1_a5psw.o
obj-$(CONFIG_NET_DSA_SMSC_LAN9303) += lan9303-core.o
@@ -17,6 +13,7 @@ obj-$(CONFIG_NET_DSA_VITESSE_VSC73XX_SPI) += vitesse-vsc73xx-spi.o
obj-y += b53/
obj-y += hirschmann/
obj-y += lantiq/
+obj-y += mediatek/
obj-y += microchip/
obj-y += motorcomm/
obj-y += mv88e6xxx/
diff --git a/drivers/net/dsa/mediatek/Kconfig b/drivers/net/dsa/mediatek/Kconfig
new file mode 100644
index 000000000000..ef62481662fd
--- /dev/null
+++ b/drivers/net/dsa/mediatek/Kconfig
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: GPL-2.0-only
+config NET_DSA_MT7530
+ tristate "MediaTek MT7530 and MT7531 Ethernet switch support"
+ select NET_DSA_TAG_MTK
+ select REGMAP_IRQ
+ imply NET_DSA_MT7530_MDIO
+ imply NET_DSA_MT7530_MMIO
+ help
+ This enables support for the MediaTek MT7530 and MT7531 Ethernet
+ switch chips. Multi-chip module MT7530 in MT7621AT, MT7621DAT,
+ MT7621ST and MT7623AI SoCs, and built-in switch in MT7988 SoC are
+ supported as well.
+
+config NET_DSA_MT7530_MDIO
+ tristate "MediaTek MT7530 MDIO interface driver"
+ depends on NET_DSA_MT7530
+ select MEDIATEK_GE_PHY
+ select PCS_MTK_LYNXI
+ help
+ This enables support for the MediaTek MT7530 and MT7531 switch
+ chips which are connected via MDIO, as well as multi-chip
+ module MT7530 which can be found in the MT7621AT, MT7621DAT,
+ MT7621ST and MT7623AI SoCs.
+
+config NET_DSA_MT7530_MMIO
+ tristate "MediaTek MT7530 MMIO interface driver"
+ depends on NET_DSA_MT7530
+ depends on HAS_IOMEM
+ imply MEDIATEK_GE_SOC_PHY
+ help
+ This enables support for the built-in Ethernet switch found
+ in the MediaTek MT7988 SoC.
+ The switch is a similar design as MT7531, but the switch registers
+ are directly mapped into the SoCs register space rather than being
+ accessible via MDIO.
+
+config NET_DSA_MT7628
+ tristate "MediaTek MT7628 Embedded Ethernet switch support"
+ depends on HAS_IOMEM && (SOC_MT7620 || COMPILE_TEST)
+ select NET_DSA_TAG_MT7628
+ select MEDIATEK_FE_SOC_PHY
+ select REGMAP_MMIO
+ help
+ This enables support for the built-in Ethernet switch found
+ in the MT7628 SoC.
diff --git a/drivers/net/dsa/mediatek/Makefile b/drivers/net/dsa/mediatek/Makefile
new file mode 100644
index 000000000000..0ed6e11f292e
--- /dev/null
+++ b/drivers/net/dsa/mediatek/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_NET_DSA_MT7530) += mt7530.o
+obj-$(CONFIG_NET_DSA_MT7530_MDIO) += mt7530-mdio.o
+obj-$(CONFIG_NET_DSA_MT7530_MMIO) += mt7530-mmio.o
+obj-$(CONFIG_NET_DSA_MT7628) += mt7628.o
diff --git a/drivers/net/dsa/mt7530-mdio.c b/drivers/net/dsa/mediatek/mt7530-mdio.c
similarity index 100%
rename from drivers/net/dsa/mt7530-mdio.c
rename to drivers/net/dsa/mediatek/mt7530-mdio.c
diff --git a/drivers/net/dsa/mt7530-mmio.c b/drivers/net/dsa/mediatek/mt7530-mmio.c
similarity index 100%
rename from drivers/net/dsa/mt7530-mmio.c
rename to drivers/net/dsa/mediatek/mt7530-mmio.c
diff --git a/drivers/net/dsa/mt7530.c b/drivers/net/dsa/mediatek/mt7530.c
similarity index 100%
rename from drivers/net/dsa/mt7530.c
rename to drivers/net/dsa/mediatek/mt7530.c
diff --git a/drivers/net/dsa/mt7530.h b/drivers/net/dsa/mediatek/mt7530.h
similarity index 100%
rename from drivers/net/dsa/mt7530.h
rename to drivers/net/dsa/mediatek/mt7530.h
diff --git a/drivers/net/dsa/mt7628.c b/drivers/net/dsa/mediatek/mt7628.c
similarity index 100%
rename from drivers/net/dsa/mt7628.c
rename to drivers/net/dsa/mediatek/mt7628.c
--
2.55.0
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH net-next v25 09/10] net: dsa: mt7530: generalize and move common function to lib module
2026-10-09 16:10 [PATCH net-next v25 00/10] net: dsa: Add Airoha AN8855 support Christian Marangi
` (7 preceding siblings ...)
2026-10-09 16:10 ` [PATCH net-next v25 08/10] net: dsa: move mediatek DSA driver in dedicated directory Christian Marangi
@ 2026-10-09 16:10 ` Christian Marangi
2026-10-10 16:19 ` netdev-bot+sashiko
2026-10-09 16:10 ` [PATCH net-next v25 10/10] net: dsa: Add Airoha AN8855 5-Port Gigabit DSA Switch driver Christian Marangi
9 siblings, 1 reply; 18+ messages in thread
From: Christian Marangi @ 2026-10-09 16:10 UTC (permalink / raw)
To: Christian Marangi, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Vladimir Oltean, Matthias Brugger,
AngeloGioacchino Del Regno, Chester A. Unal, Daniel Golle,
Heiner Kallweit, Russell King, Simon Horman, Joris Vaisvila,
linux-arm-kernel, linux-mediatek, netdev, mfd, devicetree,
linux-kernel
Cc: Andrew Lunn
In preparation of support of DSA Switch from Airoha, create a mt7530
library module and move there all the common function.
Function are generalized to use the reg_field regmap API but still apply
the same exact logic. Every function is renamed to mt7530_lib prefix to
better identify it.
Minimum modification are needed to the register header and common enum and
macro are moved to the mt7530 library header to permit reuse.
A library struct is introduced with everything required for the common
functions.
The generalization and the introduction of reg_field regmap API have the
side effect of permitting to clean the mirror functions that required
special handling for MT7530 and MT7531 based switch that had different
registers. This is done by declaring a common MT7530 reg_field and a
specific one in the Switch match table.
No behaviour change is expected by this change as it's just a code move and
reimplementation.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/net/dsa/mediatek/Kconfig | 4 +
drivers/net/dsa/mediatek/Makefile | 1 +
drivers/net/dsa/mediatek/mt7530-lib.c | 1128 +++++++++++++++++++
drivers/net/dsa/mediatek/mt7530-lib.h | 391 +++++++
drivers/net/dsa/mediatek/mt7530-mdio.c | 4 +
drivers/net/dsa/mediatek/mt7530-mmio.c | 4 +
drivers/net/dsa/mediatek/mt7530.c | 1366 ++++++------------------
drivers/net/dsa/mediatek/mt7530.h | 256 ++---
8 files changed, 1912 insertions(+), 1242 deletions(-)
create mode 100644 drivers/net/dsa/mediatek/mt7530-lib.c
create mode 100644 drivers/net/dsa/mediatek/mt7530-lib.h
diff --git a/drivers/net/dsa/mediatek/Kconfig b/drivers/net/dsa/mediatek/Kconfig
index ef62481662fd..7b48300dca0c 100644
--- a/drivers/net/dsa/mediatek/Kconfig
+++ b/drivers/net/dsa/mediatek/Kconfig
@@ -1,6 +1,10 @@
# SPDX-License-Identifier: GPL-2.0-only
+config NET_DSA_MT7530_LIB
+ tristate
+
config NET_DSA_MT7530
tristate "MediaTek MT7530 and MT7531 Ethernet switch support"
+ select NET_DSA_MT7530_LIB
select NET_DSA_TAG_MTK
select REGMAP_IRQ
imply NET_DSA_MT7530_MDIO
diff --git a/drivers/net/dsa/mediatek/Makefile b/drivers/net/dsa/mediatek/Makefile
index 0ed6e11f292e..b2c0693dbb58 100644
--- a/drivers/net/dsa/mediatek/Makefile
+++ b/drivers/net/dsa/mediatek/Makefile
@@ -1,5 +1,6 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_NET_DSA_MT7530) += mt7530.o
+obj-$(CONFIG_NET_DSA_MT7530_LIB) += mt7530-lib.o
obj-$(CONFIG_NET_DSA_MT7530_MDIO) += mt7530-mdio.o
obj-$(CONFIG_NET_DSA_MT7530_MMIO) += mt7530-mmio.o
obj-$(CONFIG_NET_DSA_MT7628) += mt7628.o
diff --git a/drivers/net/dsa/mediatek/mt7530-lib.c b/drivers/net/dsa/mediatek/mt7530-lib.c
new file mode 100644
index 000000000000..098dd45d3ee9
--- /dev/null
+++ b/drivers/net/dsa/mediatek/mt7530-lib.c
@@ -0,0 +1,1128 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <linux/device.h>
+#include <linux/if_bridge.h>
+#include <linux/module.h>
+#include <linux/regmap.h>
+#include <net/dsa.h>
+
+#include "mt7530-lib.h"
+
+void mt7530_lib_mib_reset(struct mt7530_lib_priv *priv)
+{
+ regmap_field_write(priv->fields[MT7530_CCR_MIB_ENABLE], 0);
+ regmap_field_write(priv->fields[MT7530_CCR_RX_OCT_CNT_GOOD], 1);
+ regmap_field_write(priv->fields[MT7530_CCR_RX_OCT_CNT_BAD], 1);
+ regmap_field_write(priv->fields[MT7530_CCR_TX_OCT_CNT_GOOD], 1);
+ regmap_field_write(priv->fields[MT7530_CCR_TX_OCT_CNT_BAD], 1);
+ regmap_field_write(priv->fields[MT7530_CCR_MIB_ENABLE], 1);
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_mib_reset);
+
+/* In Clause 5 of IEEE Std 802-2014, two sublayers of the data link layer (DLL)
+ * of the Open Systems Interconnection basic reference model (OSI/RM) are
+ * described; the medium access control (MAC) and logical link control (LLC)
+ * sublayers. The MAC sublayer is the one facing the physical layer.
+ *
+ * In 8.2 of IEEE Std 802.1Q-2022, the Bridge architecture is described. A
+ * Bridge component comprises a MAC Relay Entity for interconnecting the Ports
+ * of the Bridge, at least two Ports, and higher layer entities with at least a
+ * Spanning Tree Protocol Entity included.
+ *
+ * Each Bridge Port also functions as an end station and shall provide the MAC
+ * Service to an LLC Entity. Each instance of the MAC Service is provided to a
+ * distinct LLC Entity that supports protocol identification, multiplexing, and
+ * demultiplexing, for protocol data unit (PDU) transmission and reception by
+ * one or more higher layer entities.
+ *
+ * It is described in 8.13.9 of IEEE Std 802.1Q-2022 that in a Bridge, the LLC
+ * Entity associated with each Bridge Port is modeled as being directly
+ * connected to the attached Local Area Network (LAN).
+ *
+ * On the switch with CPU port architecture, CPU port functions as Management
+ * Port, and the Management Port functionality is provided by software which
+ * functions as an end station. Software is connected to an IEEE 802 LAN that is
+ * wholly contained within the system that incorporates the Bridge. Software
+ * provides access to the LLC Entity associated with each Bridge Port by the
+ * value of the source port field on the special tag on the frame received by
+ * software.
+ *
+ * We call frames that carry control information to determine the active
+ * topology and current extent of each Virtual Local Area Network (VLAN), i.e.,
+ * spanning tree or Shortest Path Bridging (SPB) and Multiple VLAN Registration
+ * Protocol Data Units (MVRPDUs), and frames from other link constrained
+ * protocols, such as Extensible Authentication Protocol over LAN (EAPOL) and
+ * Link Layer Discovery Protocol (LLDP), link-local frames. They are not
+ * forwarded by a Bridge. Permanently configured entries in the filtering
+ * database (FDB) ensure that such frames are discarded by the Forwarding
+ * Process. In 8.6.3 of IEEE Std 802.1Q-2022, this is described in detail:
+ *
+ * Each of the reserved MAC addresses specified in Table 8-1
+ * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]) shall be
+ * permanently configured in the FDB in C-VLAN components and ERs.
+ *
+ * Each of the reserved MAC addresses specified in Table 8-2
+ * (01-80-C2-00-00-[01,02,03,04,05,06,07,08,09,0A,0E]) shall be permanently
+ * configured in the FDB in S-VLAN components.
+ *
+ * Each of the reserved MAC addresses specified in Table 8-3
+ * (01-80-C2-00-00-[01,02,04,0E]) shall be permanently configured in the FDB in
+ * TPMR components.
+ *
+ * The FDB entries for reserved MAC addresses shall specify filtering for all
+ * Bridge Ports and all VIDs. Management shall not provide the capability to
+ * modify or remove entries for reserved MAC addresses.
+ *
+ * The addresses in Table 8-1, Table 8-2, and Table 8-3 determine the scope of
+ * propagation of PDUs within a Bridged Network, as follows:
+ *
+ * The Nearest Bridge group address (01-80-C2-00-00-0E) is an address that no
+ * conformant Two-Port MAC Relay (TPMR) component, Service VLAN (S-VLAN)
+ * component, Customer VLAN (C-VLAN) component, or MAC Bridge can forward.
+ * PDUs transmitted using this destination address, or any other addresses
+ * that appear in Table 8-1, Table 8-2, and Table 8-3
+ * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]), can
+ * therefore travel no further than those stations that can be reached via a
+ * single individual LAN from the originating station.
+ *
+ * The Nearest non-TPMR Bridge group address (01-80-C2-00-00-03), is an
+ * address that no conformant S-VLAN component, C-VLAN component, or MAC
+ * Bridge can forward; however, this address is relayed by a TPMR component.
+ * PDUs using this destination address, or any of the other addresses that
+ * appear in both Table 8-1 and Table 8-2 but not in Table 8-3
+ * (01-80-C2-00-00-[00,03,05,06,07,08,09,0A,0B,0C,0D,0F]), will be relayed by
+ * any TPMRs but will propagate no further than the nearest S-VLAN component,
+ * C-VLAN component, or MAC Bridge.
+ *
+ * The Nearest Customer Bridge group address (01-80-C2-00-00-00) is an address
+ * that no conformant C-VLAN component, MAC Bridge can forward; however, it is
+ * relayed by TPMR components and S-VLAN components. PDUs using this
+ * destination address, or any of the other addresses that appear in Table 8-1
+ * but not in either Table 8-2 or Table 8-3 (01-80-C2-00-00-[00,0B,0C,0D,0F]),
+ * will be relayed by TPMR components and S-VLAN components but will propagate
+ * no further than the nearest C-VLAN component or MAC Bridge.
+ *
+ * Because the LLC Entity associated with each Bridge Port is provided via CPU
+ * port, we must not filter these frames but forward them to CPU port.
+ *
+ * In a Bridge, the transmission Port is majorly decided by ingress and egress
+ * rules, FDB, and spanning tree Port State functions of the Forwarding Process.
+ * For link-local frames, only CPU port should be designated as destination port
+ * in the FDB, and the other functions of the Forwarding Process must not
+ * interfere with the decision of the transmission Port. We call this process
+ * trapping frames to CPU port.
+ *
+ * Therefore, on the switch with CPU port architecture, link-local frames must
+ * be trapped to CPU port, and certain link-local frames received by a Port of a
+ * Bridge comprising a TPMR component or an S-VLAN component must be excluded
+ * from it.
+ *
+ * A Bridge of the switch with CPU port architecture cannot comprise a Two-Port
+ * MAC Relay (TPMR) component as a TPMR component supports only a subset of the
+ * functionality of a MAC Bridge. A Bridge comprising two Ports (Management Port
+ * doesn't count) of this architecture will either function as a standard MAC
+ * Bridge or a standard VLAN Bridge.
+ *
+ * Therefore, a Bridge of this architecture can only comprise S-VLAN components,
+ * C-VLAN components, or MAC Bridge components. Since there's no TPMR component,
+ * we don't need to relay PDUs using the destination addresses specified on the
+ * Nearest non-TPMR section, and the proportion of the Nearest Customer Bridge
+ * section where they must be relayed by TPMR components.
+ *
+ * One option to trap link-local frames to CPU port is to add static FDB entries
+ * with CPU port designated as destination port. However, because that
+ * Independent VLAN Learning (IVL) is being used on every VID, each entry only
+ * applies to a single VLAN Identifier (VID). For a Bridge comprising a MAC
+ * Bridge component or a C-VLAN component, there would have to be 16 times 4096
+ * entries. This switch intellectual property can only hold a maximum of 2048
+ * entries. Using this option, there also isn't a mechanism to prevent
+ * link-local frames from being discarded when the spanning tree Port State of
+ * the reception Port is discarding.
+ *
+ * The remaining option is to utilise the BPC, RGAC1, RGAC2, RGAC3, and RGAC4
+ * registers. Whilst this applies to every VID, it doesn't contain all of the
+ * reserved MAC addresses without affecting the remaining Standard Group MAC
+ * Addresses. The REV_UN frame tag utilised using the RGAC4 register covers the
+ * remaining 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] destination
+ * addresses. It also includes the 01-80-C2-00-00-22 to 01-80-C2-00-00-FF
+ * destination addresses which may be relayed by MAC Bridges or VLAN Bridges.
+ * The latter option provides better but not complete conformance.
+ *
+ * This switch intellectual property also does not provide a mechanism to trap
+ * link-local frames with specific destination addresses to CPU port by Bridge,
+ * to conform to the filtering rules for the distinct Bridge components.
+ *
+ * Therefore, regardless of the type of the Bridge component, link-local frames
+ * with these destination addresses will be trapped to CPU port:
+ *
+ * 01-80-C2-00-00-[00,01,02,03,0E]
+ *
+ * In a Bridge comprising a MAC Bridge component or a C-VLAN component:
+ *
+ * Link-local frames with these destination addresses won't be trapped to CPU
+ * port which won't conform to IEEE Std 802.1Q-2022:
+ *
+ * 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F]
+ *
+ * In a Bridge comprising an S-VLAN component:
+ *
+ * Link-local frames with these destination addresses will be trapped to CPU
+ * port which won't conform to IEEE Std 802.1Q-2022:
+ *
+ * 01-80-C2-00-00-00
+ *
+ * Link-local frames with these destination addresses won't be trapped to CPU
+ * port which won't conform to IEEE Std 802.1Q-2022:
+ *
+ * 01-80-C2-00-00-[04,05,06,07,08,09,0A]
+ *
+ * To trap link-local frames to CPU port as conformant as this switch
+ * intellectual property can allow, link-local frames are made to be regarded as
+ * Bridge Protocol Data Units (BPDUs). This is because this switch intellectual
+ * property only lets the frames regarded as BPDUs bypass the spanning tree Port
+ * State function of the Forwarding Process.
+ *
+ * The only remaining interference is the ingress rules. When the reception Port
+ * has no PVID assigned on software, VLAN-untagged frames won't be allowed in.
+ * There doesn't seem to be a mechanism on the switch intellectual property to
+ * have link-local frames bypass this function of the Forwarding Process.
+ */
+void mt7530_lib_trap_frames(struct mt7530_lib_priv *priv)
+{
+ /* Trap 802.1X PAE frames and BPDUs to the CPU port(s) and egress
+ * them with the EG_TAG attribute set to disabled (system default)
+ * so that any VLAN tags in the frame are not modified by the
+ * switch egress VLAN tag processing. This preserves VLAN tags
+ * for reception on VLAN sub-interfaces.
+ */
+ regmap_field_write(priv->fields[MT7530_BPDU_EG_TAG],
+ MT7530_VLAN_EG_DISABLED);
+ regmap_field_write(priv->fields[MT7530_BPDU_PORT_FW],
+ TO_CPU_FW_CPU_ONLY);
+ regmap_field_write(priv->fields[MT7530_PAE_BPDU_FR], 1);
+ regmap_field_write(priv->fields[MT7530_PAE_EG_TAG],
+ MT7530_VLAN_EG_DISABLED);
+ regmap_field_write(priv->fields[MT7530_PAE_PORT_FW],
+ TO_CPU_FW_CPU_ONLY);
+
+ /* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and
+ * egress them with EG_TAG disabled.
+ */
+ regmap_field_write(priv->fields[MT7530_R01_BPDU_FR], 1);
+ regmap_field_write(priv->fields[MT7530_R01_EG_TAG],
+ MT7530_VLAN_EG_DISABLED);
+ regmap_field_write(priv->fields[MT7530_R01_PORT_FW],
+ TO_CPU_FW_CPU_ONLY);
+ regmap_field_write(priv->fields[MT7530_R02_BPDU_FR], 1);
+ regmap_field_write(priv->fields[MT7530_R02_EG_TAG],
+ MT7530_VLAN_EG_DISABLED);
+ regmap_field_write(priv->fields[MT7530_R02_PORT_FW],
+ TO_CPU_FW_CPU_ONLY);
+
+ /* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and
+ * egress them with EG_TAG disabled.
+ */
+ regmap_field_write(priv->fields[MT7530_R03_BPDU_FR], 1);
+ regmap_field_write(priv->fields[MT7530_R03_EG_TAG],
+ MT7530_VLAN_EG_DISABLED);
+ regmap_field_write(priv->fields[MT7530_R03_PORT_FW],
+ TO_CPU_FW_CPU_ONLY);
+ regmap_field_write(priv->fields[MT7530_R0E_BPDU_FR], 1);
+ regmap_field_write(priv->fields[MT7530_R0E_EG_TAG],
+ MT7530_VLAN_EG_DISABLED);
+ regmap_field_write(priv->fields[MT7530_R0E_PORT_FW],
+ TO_CPU_FW_CPU_ONLY);
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_trap_frames);
+
+static void mt7530_update_port_member(struct mt7530_lib_priv *priv, int port,
+ const struct net_device *bridge_dev,
+ bool join) __must_hold(priv->reg_mutex)
+{
+ struct dsa_port *dp = dsa_to_port(priv->ds, port), *other_dp;
+ struct mt7530_port *p = &priv->ports[port], *other_p;
+ struct dsa_port *cpu_dp = dp->cpu_dp;
+ u32 port_bitmap = BIT(cpu_dp->index);
+ int other_port;
+ bool isolated;
+
+ dsa_switch_for_each_user_port(other_dp, priv->ds) {
+ other_port = other_dp->index;
+ other_p = &priv->ports[other_port];
+
+ if (dp == other_dp)
+ continue;
+
+ /* Add/remove this port to/from the port matrix of the other
+ * ports in the same bridge. If the port is disabled, port
+ * matrix is kept and not being setup until the port becomes
+ * enabled.
+ */
+ if (!dsa_port_offloads_bridge_dev(other_dp, bridge_dev))
+ continue;
+
+ isolated = p->isolated && other_p->isolated;
+
+ if (join && !isolated) {
+ other_p->pm |= BIT(port);
+ port_bitmap |= BIT(other_port);
+ } else {
+ other_p->pm &= ~BIT(port);
+ }
+
+ if (other_p->enable)
+ regmap_fields_write(priv->fields[MT7530_PCR_MATRIX],
+ other_port, other_p->pm);
+ }
+
+ /* Add/remove the all other ports to this port matrix. For !join
+ * (leaving the bridge), only the CPU port will remain in the port matrix
+ * of this port.
+ */
+ p->pm = port_bitmap;
+ if (priv->ports[port].enable)
+ regmap_fields_write(priv->fields[MT7530_PCR_MATRIX],
+ port, port_bitmap);
+}
+
+void mt7530_lib_read_port_stats(struct regmap_field *low,
+ struct regmap_field *high,
+ int port, uint64_t *data)
+{
+ u32 val = 0;
+
+ regmap_fields_read(low, port, &val);
+ *data = val;
+
+ if (high) {
+ val = 0;
+ regmap_fields_read(high, port, &val);
+ *data |= (u64)val << 32;
+ }
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_read_port_stats);
+
+void mt7530_lib_get_eth_mac_stats(struct mt7530_lib_priv *priv, int port,
+ struct ethtool_eth_mac_stats *mac_stats)
+{
+ /* MIB counter doesn't provide a FramesTransmittedOK but instead
+ * provide stats for Unicast, Broadcast and Multicast frames separately.
+ * To simulate a global frame counter, read Unicast and addition Multicast
+ * and Broadcast later
+ */
+ mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_TX_UNICAST], NULL, port,
+ &mac_stats->FramesTransmittedOK);
+
+ mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_TX_SINGLE_COLLISION], NULL, port,
+ &mac_stats->SingleCollisionFrames);
+
+ mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_TX_MULTIPLE_COLLISION], NULL, port,
+ &mac_stats->MultipleCollisionFrames);
+
+ mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_RX_UNICAST], NULL, port,
+ &mac_stats->FramesReceivedOK);
+
+ mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_TX_BYTES_LOW],
+ priv->fields[MT7530_MIB_TX_BYTES_HIGH], port,
+ &mac_stats->OctetsTransmittedOK);
+
+ mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_RX_ALIGN_ERR], NULL, port,
+ &mac_stats->AlignmentErrors);
+
+ mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_TX_DEFERRED], NULL, port,
+ &mac_stats->FramesWithDeferredXmissions);
+
+ mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_TX_LATE_COLLISION], NULL, port,
+ &mac_stats->LateCollisions);
+
+ mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_TX_EXCESSIVE_COLLISION], NULL, port,
+ &mac_stats->FramesAbortedDueToXSColls);
+
+ mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_RX_BYTES_LOW],
+ priv->fields[MT7530_MIB_RX_BYTES_HIGH], port,
+ &mac_stats->OctetsReceivedOK);
+
+ mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_TX_MULTICAST], NULL, port,
+ &mac_stats->MulticastFramesXmittedOK);
+ mac_stats->FramesTransmittedOK += mac_stats->MulticastFramesXmittedOK;
+ mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_TX_BROADCAST], NULL, port,
+ &mac_stats->BroadcastFramesXmittedOK);
+ mac_stats->FramesTransmittedOK += mac_stats->BroadcastFramesXmittedOK;
+
+ mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_RX_MULTICAST], NULL, port,
+ &mac_stats->MulticastFramesReceivedOK);
+ mac_stats->FramesReceivedOK += mac_stats->MulticastFramesReceivedOK;
+ mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_RX_BROADCAST], NULL, port,
+ &mac_stats->BroadcastFramesReceivedOK);
+ mac_stats->FramesReceivedOK += mac_stats->BroadcastFramesReceivedOK;
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_get_eth_mac_stats);
+
+void mt7530_lib_get_rmon_stats(struct mt7530_lib_priv *priv, int port,
+ struct ethtool_rmon_stats *rmon_stats,
+ const struct ethtool_rmon_hist_range **ranges,
+ const struct mt7530_rmon_hist *ranges_info)
+{
+ int i;
+
+ mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_RX_UNDER_SIZE_ERR], NULL, port,
+ &rmon_stats->undersize_pkts);
+ mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_RX_OVER_SZ_ERR], NULL, port,
+ &rmon_stats->oversize_pkts);
+ mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_RX_FRAG_ERR], NULL, port,
+ &rmon_stats->fragments);
+ mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_RX_JABBER_ERR], NULL, port,
+ &rmon_stats->jabbers);
+
+ for (i = 0; i < ranges_info->num_ranges; i++) {
+ unsigned int field = ranges_info->ranges_fields[i];
+ unsigned int field_tx = ranges_info->ranges_tx_fields[i];
+
+ mt7530_lib_read_port_stats(priv->fields[field], NULL, port,
+ &rmon_stats->hist[i]);
+ mt7530_lib_read_port_stats(priv->fields[field_tx], NULL, port,
+ &rmon_stats->hist_tx[i]);
+ }
+
+ *ranges = ranges_info->ranges;
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_get_rmon_stats);
+
+void mt7530_lib_get_eth_ctrl_stats(struct mt7530_lib_priv *priv, int port,
+ struct ethtool_eth_ctrl_stats *ctrl_stats)
+{
+ mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_TX_PAUSE], NULL, port,
+ &ctrl_stats->MACControlFramesTransmitted);
+ mt7530_lib_read_port_stats(priv->fields[MT7530_MIB_RX_PAUSE], NULL, port,
+ &ctrl_stats->MACControlFramesReceived);
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_get_eth_ctrl_stats);
+
+int mt7530_lib_fdb_cmd(struct mt7530_lib_priv *priv, enum mt7530_fdb_cmd cmd,
+ u32 mat, u32 *rsp)
+{
+ u32 val;
+ int ret;
+
+ ret = regmap_field_write(priv->fields[MT7530_ATC_MAT], mat);
+ if (ret)
+ return ret;
+
+ ret = regmap_field_write(priv->fields[MT7530_ATC_CMD], cmd);
+ if (ret)
+ return ret;
+
+ ret = regmap_field_write(priv->fields[MT7530_ATC_BUSY], 1);
+ if (ret)
+ return ret;
+
+ ret = regmap_field_read_poll_timeout(priv->fields[MT7530_ATC_BUSY],
+ val, !val, 20, 20000);
+ if (ret < 0) {
+ dev_err(priv->dev, "reset timeout\n");
+ return ret;
+ }
+
+ regmap_field_read(priv->fields[MT7530_ATC_INVALID], &val);
+ if (cmd == MT7530_FDB_READ && val)
+ return -EINVAL;
+
+ if (rsp)
+ regmap_field_read(priv->fields[__MT7530_ATC], rsp);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_fdb_cmd);
+
+static void mt7530_lib_fdb_write(struct mt7530_lib_priv *priv, u16 vid,
+ u8 port_mask, const u8 *mac,
+ u8 aging, u8 type)
+{
+ /* Clear ATWD registers from previous access */
+ regmap_field_write(priv->fields[__MT7530_ATWD1], 0);
+ regmap_field_write(priv->fields[__MT7530_ATWD2], 0);
+ regmap_field_write(priv->fields[__MT7530_ATWD3], 0);
+
+ regmap_field_write(priv->fields[MT7530_ATWD_CVID], vid);
+ regmap_field_write(priv->fields[MT7530_ATWD_IVL], 1);
+ regmap_field_write(priv->fields[MT7530_ATWD_FID], FID_BRIDGED);
+ regmap_field_write(priv->fields[MT7530_ATWD_AGE_TIMER], aging);
+ regmap_field_write(priv->fields[MT7530_ATWD_PORT_MAP], port_mask);
+ /* STATIC_ENT indicate that entry is static wouldn't
+ * be aged out and STATIC_EMP specified as erasing an
+ * entry
+ */
+ regmap_field_write(priv->fields[MT7530_ATWD_ENT_STATUS], type);
+ regmap_field_write(priv->fields[MT7530_ATWD_MAC_BYTE_5], mac[5]);
+ regmap_field_write(priv->fields[MT7530_ATWD_MAC_BYTE_4], mac[4]);
+ regmap_field_write(priv->fields[MT7530_ATWD_MAC_BYTE_3], mac[3]);
+ regmap_field_write(priv->fields[MT7530_ATWD_MAC_BYTE_2], mac[2]);
+ regmap_field_write(priv->fields[MT7530_ATWD_MAC_BYTE_1], mac[1]);
+ regmap_field_write(priv->fields[MT7530_ATWD_MAC_BYTE_0], mac[0]);
+}
+
+void mt7530_lib_fdb_read(struct mt7530_lib_priv *priv, struct mt7530_fdb *fdb)
+{
+ u32 val = 0;
+
+ regmap_field_read(priv->fields[MT7530_ATRD_CVID], &val);
+ fdb->vid = val;
+ regmap_field_read(priv->fields[MT7530_ATRD_AGE_TIMER], &val);
+ fdb->aging = val;
+ regmap_field_read(priv->fields[MT7530_ATRD_PORT_MAP], &val);
+ fdb->port_mask = val;
+ regmap_field_read(priv->fields[MT7530_ATRD_MAC_BYTE_5], &val);
+ fdb->mac[5] = val;
+ regmap_field_read(priv->fields[MT7530_ATRD_MAC_BYTE_4], &val);
+ fdb->mac[4] = val;
+ regmap_field_read(priv->fields[MT7530_ATRD_MAC_BYTE_3], &val);
+ fdb->mac[3] = val;
+ regmap_field_read(priv->fields[MT7530_ATRD_MAC_BYTE_2], &val);
+ fdb->mac[2] = val;
+ regmap_field_read(priv->fields[MT7530_ATRD_MAC_BYTE_1], &val);
+ fdb->mac[1] = val;
+ regmap_field_read(priv->fields[MT7530_ATRD_MAC_BYTE_0], &val);
+ fdb->mac[0] = val;
+ regmap_field_read(priv->fields[MT7530_ATRD_ENT_STATUS], &val);
+ fdb->noarp = val == STATIC_ENT;
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_fdb_read);
+
+void mt7530_lib_port_fast_age(struct mt7530_lib_priv *priv, int port)
+{
+ mutex_lock(priv->reg_mutex);
+
+ /* Flush all non-static MAC address entries */
+ mt7530_lib_fdb_cmd(priv, MT7530_FDB_FLUSH,
+ ATC_MAT_NON_STATIC_MAC, NULL);
+
+ mutex_unlock(priv->reg_mutex);
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_port_fast_age);
+
+int mt7530_lib_port_fdb_add(struct mt7530_lib_priv *priv, int port,
+ const unsigned char *addr, u16 vid,
+ struct dsa_db db)
+{
+ u8 port_mask = BIT(port);
+ int ret;
+
+ mutex_lock(priv->reg_mutex);
+ mt7530_lib_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
+ ret = mt7530_lib_fdb_cmd(priv, MT7530_FDB_WRITE,
+ ATC_MAT_MACTAB, NULL);
+ mutex_unlock(priv->reg_mutex);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_port_fdb_add);
+
+int mt7530_lib_port_fdb_del(struct mt7530_lib_priv *priv, int port,
+ const unsigned char *addr, u16 vid,
+ struct dsa_db db)
+{
+ u8 port_mask = BIT(port);
+ int ret;
+
+ mutex_lock(priv->reg_mutex);
+ mt7530_lib_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP);
+ ret = mt7530_lib_fdb_cmd(priv, MT7530_FDB_WRITE,
+ ATC_MAT_MACTAB, NULL);
+ mutex_unlock(priv->reg_mutex);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_port_fdb_del);
+
+int mt7530_lib_port_mdb_add(struct mt7530_lib_priv *priv, int port,
+ const struct switchdev_obj_port_mdb *mdb,
+ struct dsa_db db)
+{
+ const u8 *addr = mdb->addr;
+ u16 vid = mdb->vid;
+ u8 port_mask = 0;
+ u32 val;
+ int ret;
+
+ mutex_lock(priv->reg_mutex);
+
+ mt7530_lib_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP);
+ if (!mt7530_lib_fdb_cmd(priv, MT7530_FDB_READ,
+ ATC_MAT_MACTAB, NULL)) {
+ regmap_field_read(priv->fields[MT7530_ATRD_PORT_MAP],
+ &val);
+ port_mask = val;
+ }
+
+ port_mask |= BIT(port);
+ mt7530_lib_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
+ ret = mt7530_lib_fdb_cmd(priv, MT7530_FDB_WRITE,
+ ATC_MAT_MACTAB, NULL);
+
+ mutex_unlock(priv->reg_mutex);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_port_mdb_add);
+
+int mt7530_lib_port_mdb_del(struct mt7530_lib_priv *priv, int port,
+ const struct switchdev_obj_port_mdb *mdb,
+ struct dsa_db db)
+{
+ const u8 *addr = mdb->addr;
+ u16 vid = mdb->vid;
+ u8 port_mask = 0;
+ u32 val;
+ int ret;
+
+ mutex_lock(priv->reg_mutex);
+
+ mt7530_lib_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP);
+ if (!mt7530_lib_fdb_cmd(priv, MT7530_FDB_READ,
+ ATC_MAT_MACTAB, NULL)) {
+ regmap_field_read(priv->fields[MT7530_ATRD_PORT_MAP],
+ &val);
+ port_mask = val;
+ }
+
+ port_mask &= ~BIT(port);
+ mt7530_lib_fdb_write(priv, vid, port_mask, addr, -1,
+ port_mask ? STATIC_ENT : STATIC_EMP);
+ ret = mt7530_lib_fdb_cmd(priv, MT7530_FDB_WRITE,
+ ATC_MAT_MACTAB, NULL);
+
+ mutex_unlock(priv->reg_mutex);
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_port_mdb_del);
+
+int mt7530_lib_port_mirror_add(struct mt7530_lib_priv *priv, int port,
+ struct dsa_mall_mirror_tc_entry *mirror,
+ bool ingress, struct netlink_ext_ack *extack)
+{
+ u32 monitor_port, val = 0;
+ int ret;
+
+ /* Check for existent entry */
+ if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port))
+ return -EEXIST;
+
+ regmap_field_read(priv->fields[MT7530_MIRROR_EN], &val);
+ ret = regmap_field_read(priv->fields[MT7530_MIRROR_PORT], &monitor_port);
+ if (ret)
+ return ret;
+
+ /* MT7530 only supports one monitor port */
+ if (val && monitor_port != mirror->to_local_port)
+ return -EEXIST;
+
+ regmap_field_write(priv->fields[MT7530_MIRROR_PORT],
+ mirror->to_local_port);
+ regmap_field_write(priv->fields[MT7530_MIRROR_EN], 1);
+
+ if (ingress) {
+ regmap_fields_write(priv->fields[MT7530_PCR_PORT_RX_MIR], port, 1);
+ priv->mirror_rx |= BIT(port);
+ } else {
+ regmap_fields_write(priv->fields[MT7530_PCR_PORT_TX_MIR], port, 1);
+ priv->mirror_tx |= BIT(port);
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_port_mirror_add);
+
+void mt7530_lib_port_mirror_del(struct mt7530_lib_priv *priv, int port,
+ struct dsa_mall_mirror_tc_entry *mirror)
+{
+ if (mirror->ingress) {
+ regmap_fields_write(priv->fields[MT7530_PCR_PORT_RX_MIR], port, 0);
+ priv->mirror_rx &= ~BIT(port);
+ } else {
+ regmap_fields_write(priv->fields[MT7530_PCR_PORT_TX_MIR], port, 0);
+ priv->mirror_tx &= ~BIT(port);
+ }
+
+ if (!priv->mirror_rx && !priv->mirror_tx)
+ regmap_field_write(priv->fields[MT7530_MIRROR_EN], 0);
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_port_mirror_del);
+
+int mt7530_lib_port_change_mtu(struct mt7530_lib_priv *priv, int port, int new_mtu)
+{
+ int length;
+
+ /* When a new MTU is set, DSA always set the CPU port's MTU to the
+ * largest MTU of the user ports. Because the switch only has a global
+ * RX length register, only allowing CPU port here is enough.
+ */
+ if (!dsa_is_cpu_port(priv->ds, port))
+ return 0;
+
+ /* RX length also includes Ethernet header, MTK tag, and FCS length */
+ length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN;
+ if (length <= 1522) {
+ regmap_field_write(priv->fields[MT7530_GMACCR_MAX_RX_PKT_LEN],
+ MAX_RX_PKT_LEN_1522);
+ } else if (length <= 1536) {
+ regmap_field_write(priv->fields[MT7530_GMACCR_MAX_RX_PKT_LEN],
+ MAX_RX_PKT_LEN_1536);
+ } else if (length <= 1552) {
+ regmap_field_write(priv->fields[MT7530_GMACCR_MAX_RX_PKT_LEN],
+ MAX_RX_PKT_LEN_1552);
+ } else {
+ regmap_field_write(priv->fields[MT7530_GMACCR_MAX_RX_JUMBO],
+ DIV_ROUND_UP(length, 1024));
+ regmap_field_write(priv->fields[MT7530_GMACCR_MAX_RX_PKT_LEN],
+ MAX_RX_PKT_LEN_JUMBO);
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_port_change_mtu);
+
+void mt7530_lib_stp_state_set(struct mt7530_lib_priv *priv, int port, u8 state)
+{
+ u32 stp_state;
+
+ switch (state) {
+ case BR_STATE_DISABLED:
+ stp_state = MT7530_STP_DISABLED;
+ break;
+ case BR_STATE_BLOCKING:
+ stp_state = MT7530_STP_BLOCKING;
+ break;
+ case BR_STATE_LISTENING:
+ stp_state = MT7530_STP_LISTENING;
+ break;
+ case BR_STATE_LEARNING:
+ stp_state = MT7530_STP_LEARNING;
+ break;
+ case BR_STATE_FORWARDING:
+ default:
+ stp_state = MT7530_STP_FORWARDING;
+ break;
+ }
+
+ regmap_fields_update_bits(priv->fields[MT7530_SSP_FID_PST],
+ port, FID_PST_MASK(FID_BRIDGED),
+ FID_PST(FID_BRIDGED, stp_state));
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_stp_state_set);
+
+int mt7530_lib_port_bridge_flags(struct mt7530_lib_priv *priv, int port,
+ struct switchdev_brport_flags flags,
+ struct netlink_ext_ack *extack)
+{
+ struct dsa_switch *ds = priv->ds;
+
+ if (flags.mask & BR_LEARNING)
+ regmap_fields_write(priv->fields[MT7530_PSC_SA_DIS],
+ port, !(flags.val & BR_LEARNING));
+
+ if (flags.mask & BR_FLOOD)
+ regmap_field_update_bits(priv->fields[MT7530_UNU_FFP],
+ BIT(port),
+ flags.val & BR_FLOOD ? BIT(port) : 0);
+
+ if (flags.mask & BR_MCAST_FLOOD)
+ regmap_field_update_bits(priv->fields[MT7530_UNM_FFP],
+ BIT(port),
+ flags.val & BR_MCAST_FLOOD ? BIT(port) : 0);
+
+ if (flags.mask & BR_BCAST_FLOOD)
+ regmap_field_update_bits(priv->fields[MT7530_BC_FFP],
+ BIT(port),
+ flags.val & BR_BCAST_FLOOD ? BIT(port) : 0);
+
+ if (flags.mask & BR_ISOLATED) {
+ struct dsa_port *dp = dsa_to_port(ds, port);
+ struct net_device *bridge_dev = dsa_port_bridge_dev_get(dp);
+
+ priv->ports[port].isolated = !!(flags.val & BR_ISOLATED);
+
+ mutex_lock(priv->reg_mutex);
+ mt7530_update_port_member(priv, port, bridge_dev, true);
+ mutex_unlock(priv->reg_mutex);
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_port_bridge_flags);
+
+int mt7530_lib_port_bridge_join(struct mt7530_lib_priv *priv, int port,
+ struct dsa_bridge bridge, bool *tx_fwd_offload,
+ struct netlink_ext_ack *extack)
+{
+ mutex_lock(priv->reg_mutex);
+
+ mt7530_update_port_member(priv, port, bridge.dev, true);
+
+ /* Set to fallback mode for independent VLAN learning */
+ regmap_fields_write(priv->fields[MT7530_PCR_PORT_VLAN],
+ port, MT7530_PORT_FALLBACK_MODE);
+
+ mutex_unlock(priv->reg_mutex);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_port_bridge_join);
+
+void mt7530_lib_port_bridge_leave(struct mt7530_lib_priv *priv, int port,
+ struct dsa_bridge bridge)
+{
+ mutex_lock(priv->reg_mutex);
+
+ mt7530_update_port_member(priv, port, bridge.dev, false);
+
+ /* When a port is removed from the bridge, the port would be set up
+ * back to the default as is at initial boot which is a VLAN-unaware
+ * port.
+ */
+ regmap_fields_write(priv->fields[MT7530_PCR_PORT_VLAN],
+ port, MT7530_PORT_MATRIX_MODE);
+
+ mutex_unlock(priv->reg_mutex);
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_port_bridge_leave);
+
+static void mt7530_port_set_vlan_unaware(struct mt7530_lib_priv *priv, int port)
+{
+ struct dsa_switch *ds = priv->ds;
+ bool all_user_ports_removed = true;
+ int i;
+
+ /* This is called after .port_bridge_leave when leaving a VLAN-aware
+ * bridge. Don't set standalone ports to fallback mode.
+ */
+ if (dsa_port_bridge_dev_get(dsa_to_port(ds, port)))
+ regmap_fields_write(priv->fields[MT7530_PCR_PORT_VLAN],
+ port, MT7530_PORT_FALLBACK_MODE);
+
+ regmap_fields_write(priv->fields[MT7530_PVC_VLAN_ATTR],
+ port, MT7530_VLAN_TRANSPARENT);
+ regmap_fields_write(priv->fields[MT7530_PVC_EG_TAG],
+ port, MT7530_VLAN_EG_CONSISTENT);
+ regmap_fields_write(priv->fields[MT7530_PVC_ACC_FRM],
+ port, MT7530_VLAN_ACC_ALL);
+
+ regmap_fields_write(priv->fields[MT7530_PPBV1_G0_PORT_VID],
+ port, G0_PORT_VID_DEF);
+
+ for (i = 0; i < priv->ds->num_ports; i++) {
+ if (i == port)
+ continue;
+ if (dsa_is_user_port(ds, i) &&
+ dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
+ all_user_ports_removed = false;
+ break;
+ }
+ }
+
+ /* CPU port also does the same thing until all user ports belonging to
+ * the CPU port get out of VLAN filtering mode.
+ */
+ if (all_user_ports_removed) {
+ mutex_lock(priv->reg_mutex);
+ mt7530_lib_setup_vlan0(priv);
+ mutex_unlock(priv->reg_mutex);
+ }
+}
+
+static void mt7530_port_set_vlan_aware(struct mt7530_lib_priv *priv, int port)
+{
+ struct dsa_switch *ds = priv->ds;
+
+ /* Trapped into security mode allows packet forwarding through VLAN
+ * table lookup.
+ */
+ if (dsa_is_user_port(ds, port)) {
+ regmap_fields_write(priv->fields[MT7530_PCR_PORT_VLAN],
+ port, MT7530_PORT_SECURITY_MODE);
+ regmap_fields_write(priv->fields[MT7530_PPBV1_G0_PORT_VID],
+ port, priv->ports[port].pvid);
+
+ /* Only accept tagged frames if PVID is not set */
+ if (!priv->ports[port].pvid)
+ regmap_fields_write(priv->fields[MT7530_PVC_ACC_FRM],
+ port, MT7530_VLAN_ACC_TAGGED);
+
+ /* Set the port as a user port which is to be able to recognize
+ * VID from incoming packets before fetching entry within the
+ * VLAN table.
+ */
+ regmap_fields_write(priv->fields[MT7530_PVC_VLAN_ATTR],
+ port, MT7530_VLAN_USER);
+ regmap_fields_write(priv->fields[MT7530_PVC_EG_TAG],
+ port, MT7530_VLAN_EG_DISABLED);
+ } else {
+ /* Also set CPU ports to the "user" VLAN port attribute, to
+ * allow VLAN classification, but keep the EG_TAG attribute as
+ * "consistent" (i.o.w. don't change its value) for packets
+ * received by the switch from the CPU, so that tagged packets
+ * are forwarded to user ports as tagged, and untagged as
+ * untagged.
+ */
+ regmap_fields_write(priv->fields[MT7530_PVC_VLAN_ATTR],
+ port, MT7530_VLAN_USER);
+ }
+}
+
+int mt7530_lib_port_vlan_filtering(struct mt7530_lib_priv *priv, int port, bool vlan_filtering,
+ struct netlink_ext_ack *extack)
+{
+ struct dsa_switch *ds = priv->ds;
+ struct dsa_port *cpu_dp, *dp;
+
+ dp = dsa_to_port(ds, port);
+ cpu_dp = dp->cpu_dp;
+
+ if (vlan_filtering) {
+ /* The port is being kept as VLAN-unaware port when bridge is
+ * set up with vlan_filtering not being set, Otherwise, the
+ * port and the corresponding CPU port is required the setup
+ * for becoming a VLAN-aware port.
+ */
+ mt7530_port_set_vlan_aware(priv, port);
+ mt7530_port_set_vlan_aware(priv, cpu_dp->index);
+ } else {
+ mt7530_port_set_vlan_unaware(priv, port);
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_port_vlan_filtering);
+
+static int mt7530_vlan_cmd(struct mt7530_lib_priv *priv, enum mt7530_vlan_cmd cmd,
+ u16 vid)
+{
+ u32 val;
+ int ret;
+
+ ret = regmap_field_write(priv->fields[MT7530_VTCR_FUNC], cmd);
+ if (ret)
+ return ret;
+
+ ret = regmap_field_write(priv->fields[MT7530_VTCR_VID], vid);
+ if (ret)
+ return ret;
+
+ ret = regmap_field_write(priv->fields[MT7530_VTCR_BUSY], 1);
+ if (ret)
+ return ret;
+
+ ret = regmap_field_read_poll_timeout(priv->fields[MT7530_VTCR_BUSY],
+ val, !val, 20, 20000);
+ if (ret < 0) {
+ dev_err(priv->dev, "poll timeout\n");
+ return ret;
+ }
+
+ regmap_field_read(priv->fields[MT7530_VTCR_INVALID], &val);
+ if (val) {
+ dev_err(priv->dev, "read VTCR invalid\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static void mt7530_hw_vlan_add(struct mt7530_lib_priv *priv,
+ struct mt7530_hw_vlan_entry *entry)
+{
+ struct dsa_port *dp = dsa_to_port(priv->ds, entry->port);
+ u8 new_members;
+ u32 val;
+
+ new_members = entry->old_members | BIT(entry->port);
+
+ /* Validate the entry with independent learning, create egress tag per
+ * VLAN and joining the port as one of the port members.
+ */
+ regmap_field_write(priv->fields[MT7530_VAWD_IVL_MAC], 1);
+ regmap_field_write(priv->fields[MT7530_VAWD_VTAG_EN], 1);
+ regmap_field_write(priv->fields[MT7530_VAWD_PORT_MEM],
+ new_members);
+ regmap_field_write(priv->fields[MT7530_VAWD_FID],
+ FID_BRIDGED);
+ regmap_field_write(priv->fields[MT7530_VAWD_VLAN_VALID], 1);
+
+ /* Decide whether adding tag or not for those outgoing packets from the
+ * port inside the VLAN.
+ * CPU port is always taken as a tagged port for serving more than one
+ * VLANs across and also being applied with egress type stack mode for
+ * that VLAN tags would be appended after hardware special tag used as
+ * DSA tag.
+ */
+ if (dsa_port_is_cpu(dp))
+ val = MT7530_VLAN_EGRESS_STACK;
+ else if (entry->untagged)
+ val = MT7530_VLAN_EGRESS_UNTAG;
+ else
+ val = MT7530_VLAN_EGRESS_TAG;
+ regmap_field_update_bits(priv->fields[MT7530_VAWD_ETAG],
+ ETAG_CTRL_P_MASK(entry->port),
+ ETAG_CTRL_P(entry->port, val));
+}
+
+static void mt7530_hw_vlan_del(struct mt7530_lib_priv *priv,
+ struct mt7530_hw_vlan_entry *entry)
+{
+ u8 new_members;
+ u32 val;
+
+ new_members = entry->old_members & ~BIT(entry->port);
+
+ regmap_field_read(priv->fields[MT7530_VAWD_VLAN_VALID], &val);
+ if (!val) {
+ dev_err(priv->dev,
+ "Cannot be deleted due to invalid entry\n");
+ return;
+ }
+
+ if (new_members) {
+ regmap_field_write(priv->fields[MT7530_VAWD_IVL_MAC], 1);
+ regmap_field_write(priv->fields[MT7530_VAWD_VTAG_EN], 1);
+ regmap_field_write(priv->fields[MT7530_VAWD_PORT_MEM],
+ new_members);
+ regmap_field_write(priv->fields[MT7530_VAWD_VLAN_VALID], 1);
+ } else {
+ regmap_field_write(priv->fields[__MT7530_VAWD1], 0);
+ regmap_field_write(priv->fields[__MT7530_VAWD2], 0);
+ }
+}
+
+static void mt7530_hw_vlan_update(struct mt7530_lib_priv *priv, u16 vid,
+ struct mt7530_hw_vlan_entry *entry,
+ mt7530_vlan_op vlan_op)
+{
+ u32 val = 0;
+
+ /* Fetch entry */
+ mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid);
+
+ regmap_field_read(priv->fields[MT7530_VAWD_PORT_MEM], &val);
+ entry->old_members = val;
+
+ /* Manipulate entry */
+ vlan_op(priv, entry);
+
+ /* Flush result to hardware */
+ mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid);
+}
+
+int mt7530_lib_port_vlan_add(struct mt7530_lib_priv *priv, int port,
+ const struct switchdev_obj_port_vlan *vlan,
+ struct netlink_ext_ack *extack)
+{
+ bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
+ bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
+ struct mt7530_hw_vlan_entry new_entry;
+ struct dsa_switch *ds = priv->ds;
+
+ mutex_lock(priv->reg_mutex);
+
+ /* VID 0 is managed exclusively by mt7530_lib_setup_vlan0() for
+ * VLAN-unaware bridge operation. Don't let the bridge overwrite
+ * its EG_CON flag with VTAG_EN and corrupt PORT_MEM.
+ */
+ if (vlan->vid == 0)
+ goto skip_vlan_table;
+
+ mt7530_hw_vlan_entry_init(&new_entry, port, untagged);
+ mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add);
+
+skip_vlan_table:
+
+ if (pvid) {
+ priv->ports[port].pvid = vlan->vid;
+
+ /* Accept all frames if PVID is set */
+ regmap_fields_write(priv->fields[MT7530_PVC_ACC_FRM],
+ port, MT7530_VLAN_ACC_ALL);
+
+ /* Only configure PVID if VLAN filtering is enabled */
+ if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
+ regmap_fields_write(priv->fields[MT7530_PPBV1_G0_PORT_VID],
+ port, vlan->vid);
+ } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) {
+ /* This VLAN is overwritten without PVID, so unset it */
+ priv->ports[port].pvid = G0_PORT_VID_DEF;
+
+ /* Only accept tagged frames if the port is VLAN-aware */
+ if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
+ regmap_fields_write(priv->fields[MT7530_PVC_ACC_FRM],
+ port, MT7530_VLAN_ACC_TAGGED);
+
+ regmap_fields_write(priv->fields[MT7530_PPBV1_G0_PORT_VID],
+ port, G0_PORT_VID_DEF);
+ }
+
+ mutex_unlock(priv->reg_mutex);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_port_vlan_add);
+
+int mt7530_lib_port_vlan_del(struct mt7530_lib_priv *priv, int port,
+ const struct switchdev_obj_port_vlan *vlan)
+{
+ struct mt7530_hw_vlan_entry target_entry;
+ struct dsa_switch *ds = priv->ds;
+
+ mutex_lock(priv->reg_mutex);
+
+ /* VID 0 is managed exclusively by mt7530_lib_setup_vlan0(). */
+ if (vlan->vid == 0)
+ goto skip_vlan_table;
+
+ mt7530_hw_vlan_entry_init(&target_entry, port, 0);
+ mt7530_hw_vlan_update(priv, vlan->vid, &target_entry,
+ mt7530_hw_vlan_del);
+
+skip_vlan_table:
+ /* PVID is being restored to the default whenever the PVID port
+ * is being removed from the VLAN.
+ */
+ if (priv->ports[port].pvid == vlan->vid) {
+ priv->ports[port].pvid = G0_PORT_VID_DEF;
+
+ /* Only accept tagged frames if the port is VLAN-aware */
+ if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
+ regmap_fields_write(priv->fields[MT7530_PVC_ACC_FRM],
+ port, MT7530_VLAN_ACC_TAGGED);
+
+ regmap_fields_write(priv->fields[MT7530_PPBV1_G0_PORT_VID],
+ port, G0_PORT_VID_DEF);
+ }
+
+ mutex_unlock(priv->reg_mutex);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_port_vlan_del);
+
+int mt7530_lib_setup_vlan0(struct mt7530_lib_priv *priv)
+{
+ /* Clear VAWD registers from previous access */
+ regmap_field_write(priv->fields[__MT7530_VAWD1], 0);
+ regmap_field_write(priv->fields[__MT7530_VAWD2], 0);
+
+ regmap_field_write(priv->fields[MT7530_VAWD_IVL_MAC], 1);
+ regmap_field_write(priv->fields[MT7530_VAWD_VTAG_EN], 0);
+ regmap_field_write(priv->fields[MT7530_VAWD_EG_CON], 1);
+ regmap_field_write(priv->fields[MT7530_VAWD_PORT_MEM],
+ MT7530_ALL_MEMBERS);
+ regmap_field_write(priv->fields[MT7530_VAWD_FID],
+ FID_BRIDGED);
+ regmap_field_write(priv->fields[MT7530_VAWD_VLAN_VALID], 1);
+ regmap_field_write(priv->fields[__MT7530_VAWD2], 0);
+
+ return mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0);
+}
+EXPORT_SYMBOL_GPL(mt7530_lib_setup_vlan0);
+
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
+MODULE_DESCRIPTION("Library Driver for Mediatek MT7530 Based Switch");
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/dsa/mediatek/mt7530-lib.h b/drivers/net/dsa/mediatek/mt7530-lib.h
new file mode 100644
index 000000000000..da2ee781f7e6
--- /dev/null
+++ b/drivers/net/dsa/mediatek/mt7530-lib.h
@@ -0,0 +1,391 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef __MT7530_LIB_H
+#define __MT7530_LIB_H
+
+#define G0_PORT_VID_DEF 0
+#define MT7530_ALL_MEMBERS 0xff
+
+#define MTK_HDR_LEN 4
+#define MT7530_MAX_MTU (15 * 1024 - ETH_HLEN - ETH_FCS_LEN - MTK_HDR_LEN)
+
+/* MT7530_ATA1 */
+#define STATIC_EMP 0
+#define STATIC_ENT 3
+
+#define ATC_MAT_MACTAB 0
+#define ATC_MAT_NON_STATIC_MAC 4
+
+enum mt7530_fdb_cmd {
+ MT7530_FDB_READ = 0,
+ MT7530_FDB_WRITE = 1,
+ MT7530_FDB_FLUSH = 2,
+ MT7530_FDB_START = 4,
+ MT7530_FDB_NEXT = 5,
+};
+
+enum mt7530_max_rx_pkt_len {
+ MAX_RX_PKT_LEN_1522 = 0,
+ MAX_RX_PKT_LEN_1536 = 1,
+ MAX_RX_PKT_LEN_1552 = 2,
+ MAX_RX_PKT_LEN_JUMBO = 3,
+};
+
+#define FID_PST(fid, state) (((state) & 0x3) << ((fid) * 2))
+#define FID_PST_MASK(fid) FID_PST(fid, 0x3)
+
+enum mt7530_stp_state {
+ MT7530_STP_DISABLED = 0,
+ MT7530_STP_BLOCKING = 1,
+ MT7530_STP_LISTENING = 1,
+ MT7530_STP_LEARNING = 2,
+ MT7530_STP_FORWARDING = 3
+};
+
+/* Egress Tag Control */
+#define ETAG_CTRL_P(p, x) (((x) & 0x3) << ((p) << 1))
+#define ETAG_CTRL_P_MASK(p) ETAG_CTRL_P(p, 3)
+
+enum mt753x_to_cpu_fw {
+ TO_CPU_FW_SYSTEM_DEFAULT,
+ TO_CPU_FW_CPU_EXCLUDE = 4,
+ TO_CPU_FW_CPU_INCLUDE = 5,
+ TO_CPU_FW_CPU_ONLY = 6,
+ TO_CPU_FW_DROP = 7,
+};
+
+enum mt7530_port_mode {
+ /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */
+ MT7530_PORT_MATRIX_MODE = 0,
+
+ /* Fallback Mode: Forward received frames with ingress ports that do
+ * not belong to the VLAN member. Frames whose VID is not listed on
+ * the VLAN table are forwarded by the PCR_MATRIX members.
+ */
+ MT7530_PORT_FALLBACK_MODE = 1,
+
+ /* Security Mode: Discard any frame due to ingress membership
+ * violation or VID missed on the VLAN table.
+ */
+ MT7530_PORT_SECURITY_MODE = 3,
+};
+
+enum mt7530_vlan_port_acc_frm {
+ MT7530_VLAN_ACC_ALL = 0,
+ MT7530_VLAN_ACC_TAGGED = 1,
+ MT7530_VLAN_ACC_UNTAGGED = 2,
+};
+
+enum mt7530_vlan_port_eg_tag {
+ MT7530_VLAN_EG_DISABLED = 0,
+ MT7530_VLAN_EG_CONSISTENT = 1,
+ MT7530_VLAN_EG_UNTAGGED = 4,
+};
+
+enum mt7530_vlan_port_attr {
+ MT7530_VLAN_USER = 0,
+ MT7530_VLAN_TRANSPARENT = 3,
+};
+
+enum mt7530_fid {
+ FID_STANDALONE = 0,
+ FID_BRIDGED = 1,
+};
+
+enum mt7530_vlan_egress_attr {
+ MT7530_VLAN_EGRESS_UNTAG = 0,
+ MT7530_VLAN_EGRESS_TAG = 2,
+ MT7530_VLAN_EGRESS_STACK = 3,
+};
+
+enum mt7530_vlan_cmd {
+ /* Read/Write the specified VID entry from VAWD register based
+ * on VID.
+ */
+ MT7530_VTCR_RD_VID = 0,
+ MT7530_VTCR_WR_VID = 1,
+};
+
+enum mt7530_regmap_field {
+ MT7530_MIRROR_EN,
+ MT7530_MIRROR_PORT,
+
+ MT7530_UNU_FFP,
+ MT7530_UNM_FFP,
+ MT7530_BC_FFP,
+
+ MT7530_CCR_MIB_ENABLE,
+ MT7530_CCR_RX_OCT_CNT_GOOD,
+ MT7530_CCR_RX_OCT_CNT_BAD,
+ MT7530_CCR_TX_OCT_CNT_GOOD,
+ MT7530_CCR_TX_OCT_CNT_BAD,
+
+ MT7530_BPDU_EG_TAG,
+ MT7530_BPDU_PORT_FW,
+ MT7530_PAE_BPDU_FR,
+ MT7530_PAE_EG_TAG,
+ MT7530_PAE_PORT_FW,
+ MT7530_R01_BPDU_FR,
+ MT7530_R01_EG_TAG,
+ MT7530_R01_PORT_FW,
+ MT7530_R02_BPDU_FR,
+ MT7530_R02_EG_TAG,
+ MT7530_R02_PORT_FW,
+ MT7530_R03_BPDU_FR,
+ MT7530_R03_EG_TAG,
+ MT7530_R03_PORT_FW,
+ MT7530_R0E_BPDU_FR,
+ MT7530_R0E_EG_TAG,
+ MT7530_R0E_PORT_FW,
+
+ MT7530_VAWD_IVL_MAC,
+ MT7530_VAWD_EG_CON,
+ MT7530_VAWD_VTAG_EN,
+ MT7530_VAWD_PORT_MEM,
+ MT7530_VAWD_FID,
+ MT7530_VAWD_VLAN_VALID,
+ __MT7530_VAWD1,
+
+ MT7530_VAWD_ETAG,
+ __MT7530_VAWD2,
+
+ MT7530_VTCR_BUSY,
+ MT7530_VTCR_FUNC,
+ MT7530_VTCR_VID,
+ MT7530_VTCR_INVALID,
+
+ MT7530_ATWD_CVID,
+ MT7530_ATWD_IVL,
+ MT7530_ATWD_FID,
+ MT7530_ATWD_AGE_TIMER,
+ MT7530_ATWD_PORT_MAP,
+ MT7530_ATWD_ENT_STATUS,
+ MT7530_ATWD_MAC_BYTE_5,
+ MT7530_ATWD_MAC_BYTE_4,
+ MT7530_ATWD_MAC_BYTE_3,
+ MT7530_ATWD_MAC_BYTE_2,
+ MT7530_ATWD_MAC_BYTE_1,
+ MT7530_ATWD_MAC_BYTE_0,
+
+ __MT7530_ATWD1,
+ __MT7530_ATWD2,
+ __MT7530_ATWD3,
+
+ MT7530_ATRD_CVID,
+ MT7530_ATRD_AGE_TIMER,
+ MT7530_ATRD_PORT_MAP,
+ MT7530_ATRD_ENT_STATUS,
+ MT7530_ATRD_MAC_BYTE_5,
+ MT7530_ATRD_MAC_BYTE_4,
+ MT7530_ATRD_MAC_BYTE_3,
+ MT7530_ATRD_MAC_BYTE_2,
+ MT7530_ATRD_MAC_BYTE_1,
+ MT7530_ATRD_MAC_BYTE_0,
+
+ MT7530_ATC_BUSY,
+ MT7530_ATC_MAT,
+ MT7530_ATC_INVALID,
+ MT7530_ATC_CMD,
+ __MT7530_ATC,
+
+ MT7530_SSP_FID_PST,
+
+ MT7530_PCR_PORT_TX_MIR,
+ MT7530_PCR_PORT_RX_MIR,
+ MT7530_PCR_PORT_VLAN,
+ MT7530_PCR_MATRIX,
+
+ MT7530_PSC_SA_DIS,
+
+ MT7530_PVC_EG_TAG,
+ MT7530_PVC_VLAN_ATTR,
+ MT7530_PVC_ACC_FRM,
+
+ MT7530_PPBV1_G0_PORT_VID,
+
+ MT7530_GMACCR_MAX_RX_JUMBO,
+ MT7530_GMACCR_MAX_RX_PKT_LEN,
+
+ MT7530_MIB_TX_DROP,
+ MT7530_MIB_TX_CRC_ERR,
+ MT7530_MIB_TX_UNICAST,
+ MT7530_MIB_TX_MULTICAST,
+ MT7530_MIB_TX_BROADCAST,
+ MT7530_MIB_TX_COLLISION,
+ MT7530_MIB_TX_SINGLE_COLLISION,
+ MT7530_MIB_TX_MULTIPLE_COLLISION,
+ MT7530_MIB_TX_DEFERRED,
+ MT7530_MIB_TX_LATE_COLLISION,
+ MT7530_MIB_TX_EXCESSIVE_COLLISION,
+ MT7530_MIB_TX_PAUSE,
+ MT7530_MIB_TX_PKT_SZ_64,
+ MT7530_MIB_TX_PKT_SZ_65_TO_127,
+ MT7530_MIB_TX_PKT_SZ_128_TO_255,
+ MT7530_MIB_TX_PKT_SZ_256_TO_511,
+ MT7530_MIB_TX_PKT_SZ_512_TO_1023,
+ MT7530_MIB_TX_PKT_SZ_1024_TO_MAX,
+ MT7530_MIB_TX_BYTES_LOW,
+ MT7530_MIB_TX_BYTES_HIGH,
+ MT7530_MIB_RX_DROP,
+ MT7530_MIB_RX_FILTERING,
+ MT7530_MIB_RX_UNICAST,
+ MT7530_MIB_RX_MULTICAST,
+ MT7530_MIB_RX_BROADCAST,
+ MT7530_MIB_RX_ALIGN_ERR,
+ MT7530_MIB_RX_CRC_ERR,
+ MT7530_MIB_RX_UNDER_SIZE_ERR,
+ MT7530_MIB_RX_FRAG_ERR,
+ MT7530_MIB_RX_OVER_SZ_ERR,
+ MT7530_MIB_RX_JABBER_ERR,
+ MT7530_MIB_RX_PAUSE,
+ MT7530_MIB_RX_PKT_SZ_64,
+ MT7530_MIB_RX_PKT_SZ_65_TO_127,
+ MT7530_MIB_RX_PKT_SZ_128_TO_255,
+ MT7530_MIB_RX_PKT_SZ_256_TO_511,
+ MT7530_MIB_RX_PKT_SZ_512_TO_1023,
+ MT7530_MIB_RX_PKT_SZ_1024_TO_MAX,
+ MT7530_MIB_RX_BYTES_LOW,
+ MT7530_MIB_RX_BYTES_HIGH,
+ MT7530_MIB_RX_CTRL_DROP,
+ MT7530_MIB_RX_INGRESS_DROP,
+ MT7530_MIB_RX_ARL_DROP,
+
+ MT7530_FIELD_MAX,
+};
+
+struct mt7530_fdb {
+ u16 vid;
+ u8 port_mask;
+ u8 aging;
+ u8 mac[6];
+ bool noarp;
+};
+
+struct mt7530_hw_vlan_entry {
+ int port;
+ u8 old_members;
+ bool untagged;
+};
+
+static inline void mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry *e,
+ int port, bool untagged)
+{
+ e->port = port;
+ e->untagged = untagged;
+}
+
+#define MIB_DESC(_fl, _fh, _n) \
+ { \
+ .field_low = (_fl), \
+ .field_high = (_fh), \
+ .name = (_n), \
+ }
+
+struct mt7530_mib_desc {
+ int field_low;
+ int field_high;
+ const char *name;
+};
+
+struct mt7530_rmon_hist {
+ unsigned int *ranges_fields;
+ unsigned int *ranges_tx_fields;
+ const struct ethtool_rmon_hist_range *ranges;
+ unsigned int num_ranges;
+};
+
+struct mt7530_reg_field {
+ unsigned int id;
+ const struct reg_field field;
+};
+
+/* struct mt7530_port - This is the main data structure for holding the state
+ * of the port.
+ * @enable: The status used for show port is enabled or not.
+ * @pm: The matrix used to show all connections with the port.
+ * @pvid: The VLAN specified is to be considered a PVID at ingress. Any
+ * untagged frames will be assigned to the related VLAN.
+ * @sgmii_pcs: Pointer to PCS instance for SerDes ports
+ * @stats: Cached port statistics for MDIO-connected switches
+ */
+struct mt7530_port {
+ bool enable;
+ bool isolated;
+ u32 pm;
+ u16 pvid;
+ struct phylink_pcs *sgmii_pcs;
+ struct rtnl_link_stats64 stats;
+};
+
+struct mt7530_lib_priv {
+ struct device *dev;
+ struct dsa_switch *ds;
+ struct regmap *regmap;
+ struct regmap_field *fields[MT7530_FIELD_MAX];
+
+ u8 mirror_rx;
+ u8 mirror_tx;
+
+ struct mt7530_port *ports;
+ struct mutex *reg_mutex;
+};
+
+typedef void (*mt7530_vlan_op)(struct mt7530_lib_priv *,
+ struct mt7530_hw_vlan_entry *);
+
+void mt7530_lib_mib_reset(struct mt7530_lib_priv *priv);
+void mt7530_lib_trap_frames(struct mt7530_lib_priv *priv);
+
+void mt7530_lib_read_port_stats(struct regmap_field *low,
+ struct regmap_field *high,
+ int port, uint64_t *data);
+void mt7530_lib_get_eth_mac_stats(struct mt7530_lib_priv *priv, int port,
+ struct ethtool_eth_mac_stats *mac_stats);
+void mt7530_lib_get_rmon_stats(struct mt7530_lib_priv *priv, int port,
+ struct ethtool_rmon_stats *rmon_stats,
+ const struct ethtool_rmon_hist_range **ranges,
+ const struct mt7530_rmon_hist *ranges_info);
+void mt7530_lib_get_eth_ctrl_stats(struct mt7530_lib_priv *priv, int port,
+ struct ethtool_eth_ctrl_stats *ctrl_stats);
+int mt7530_lib_fdb_cmd(struct mt7530_lib_priv *priv, enum mt7530_fdb_cmd cmd,
+ u32 mat, u32 *rsp);
+void mt7530_lib_fdb_read(struct mt7530_lib_priv *priv, struct mt7530_fdb *fdb);
+void mt7530_lib_port_fast_age(struct mt7530_lib_priv *priv, int port);
+int mt7530_lib_port_fdb_add(struct mt7530_lib_priv *priv, int port,
+ const unsigned char *addr, u16 vid,
+ struct dsa_db db);
+int mt7530_lib_port_fdb_del(struct mt7530_lib_priv *priv, int port,
+ const unsigned char *addr, u16 vid,
+ struct dsa_db db);
+int mt7530_lib_port_mdb_add(struct mt7530_lib_priv *priv, int port,
+ const struct switchdev_obj_port_mdb *mdb,
+ struct dsa_db db);
+int mt7530_lib_port_mdb_del(struct mt7530_lib_priv *priv, int port,
+ const struct switchdev_obj_port_mdb *mdb,
+ struct dsa_db db);
+void mt7530_lib_port_mirror_del(struct mt7530_lib_priv *priv, int port,
+ struct dsa_mall_mirror_tc_entry *mirror);
+int mt7530_lib_port_mirror_add(struct mt7530_lib_priv *priv, int port,
+ struct dsa_mall_mirror_tc_entry *mirror,
+ bool ingress, struct netlink_ext_ack *extack);
+int mt7530_lib_port_change_mtu(struct mt7530_lib_priv *priv, int port, int new_mtu);
+void mt7530_lib_stp_state_set(struct mt7530_lib_priv *priv, int port, u8 state);
+int mt7530_lib_port_bridge_flags(struct mt7530_lib_priv *priv, int port,
+ struct switchdev_brport_flags flags,
+ struct netlink_ext_ack *extack);
+int mt7530_lib_port_bridge_join(struct mt7530_lib_priv *priv, int port,
+ struct dsa_bridge bridge, bool *tx_fwd_offload,
+ struct netlink_ext_ack *extack);
+void mt7530_lib_port_bridge_leave(struct mt7530_lib_priv *priv, int port,
+ struct dsa_bridge bridge);
+int mt7530_lib_port_vlan_filtering(struct mt7530_lib_priv *priv, int port, bool vlan_filtering,
+ struct netlink_ext_ack *extack);
+int mt7530_lib_port_vlan_add(struct mt7530_lib_priv *priv, int port,
+ const struct switchdev_obj_port_vlan *vlan,
+ struct netlink_ext_ack *extack);
+int mt7530_lib_port_vlan_del(struct mt7530_lib_priv *priv, int port,
+ const struct switchdev_obj_port_vlan *vlan);
+
+int mt7530_lib_setup_vlan0(struct mt7530_lib_priv *priv);
+
+#endif /* __MT7530_LIB_H */
+
diff --git a/drivers/net/dsa/mediatek/mt7530-mdio.c b/drivers/net/dsa/mediatek/mt7530-mdio.c
index 0be107dc6759..e823a9b1422f 100644
--- a/drivers/net/dsa/mediatek/mt7530-mdio.c
+++ b/drivers/net/dsa/mediatek/mt7530-mdio.c
@@ -218,6 +218,10 @@ mt7530_probe(struct mdio_device *mdiodev)
if (IS_ERR(priv->regmap))
return PTR_ERR(priv->regmap);
+ ret = mt7530_setup_lib_priv(priv);
+ if (ret)
+ return ret;
+
if (priv->id == ID_MT7531)
priv->create_sgmii = mt7531_create_sgmii;
diff --git a/drivers/net/dsa/mediatek/mt7530-mmio.c b/drivers/net/dsa/mediatek/mt7530-mmio.c
index cf3bdb23a2d5..2dcb2bb545b9 100644
--- a/drivers/net/dsa/mediatek/mt7530-mmio.c
+++ b/drivers/net/dsa/mediatek/mt7530-mmio.c
@@ -61,6 +61,10 @@ mt7988_probe(struct platform_device *pdev)
if (IS_ERR(priv->regmap))
return PTR_ERR(priv->regmap);
+ ret = mt7530_setup_lib_priv(priv);
+ if (ret)
+ return ret;
+
return dsa_register_switch(priv->ds);
}
diff --git a/drivers/net/dsa/mediatek/mt7530.c b/drivers/net/dsa/mediatek/mt7530.c
index 7781a63b4e6f..6087e5826780 100644
--- a/drivers/net/dsa/mediatek/mt7530.c
+++ b/drivers/net/dsa/mediatek/mt7530.c
@@ -24,10 +24,163 @@
#include <net/pkt_cls.h>
#include "mt7530.h"
+#include "mt7530-lib.h"
#define MT7530_STATS_POLL_INTERVAL (1 * HZ)
#define MT7530_STATS_RATE_LIMIT (HZ / 10)
+static const struct mt7530_reg_field mt753x_fields[] = {
+ { MT7530_BC_FFP, REG_FIELD(MT753X_MFC, 24, 31) },
+ { MT7530_UNM_FFP, REG_FIELD(MT753X_MFC, 16, 23) },
+ { MT7530_UNU_FFP, REG_FIELD(MT753X_MFC, 8, 15) },
+
+ { MT7530_CCR_MIB_ENABLE, REG_FIELD(MT7530_MIB_CCR, 31, 31) },
+ { MT7530_CCR_RX_OCT_CNT_GOOD, REG_FIELD(MT7530_MIB_CCR, 7, 7) },
+ { MT7530_CCR_RX_OCT_CNT_BAD, REG_FIELD(MT7530_MIB_CCR, 6, 6) },
+ { MT7530_CCR_TX_OCT_CNT_GOOD, REG_FIELD(MT7530_MIB_CCR, 5, 5) },
+ { MT7530_CCR_TX_OCT_CNT_BAD, REG_FIELD(MT7530_MIB_CCR, 4, 4) },
+
+ { MT7530_BPDU_EG_TAG, REG_FIELD(MT753X_BPC, 6, 8) },
+ { MT7530_BPDU_PORT_FW, REG_FIELD(MT753X_BPC, 0, 2) },
+ { MT7530_PAE_BPDU_FR, REG_FIELD(MT753X_BPC, 25, 25) },
+ { MT7530_PAE_EG_TAG, REG_FIELD(MT753X_BPC, 22, 24) },
+ { MT7530_PAE_PORT_FW, REG_FIELD(MT753X_BPC, 16, 18) },
+ { MT7530_R01_BPDU_FR, REG_FIELD(MT753X_RGAC1, 9, 9) },
+ { MT7530_R01_EG_TAG, REG_FIELD(MT753X_RGAC1, 6, 8) },
+ { MT7530_R01_PORT_FW, REG_FIELD(MT753X_RGAC1, 0, 2) },
+ { MT7530_R02_BPDU_FR, REG_FIELD(MT753X_RGAC1, 25, 25) },
+ { MT7530_R02_EG_TAG, REG_FIELD(MT753X_RGAC1, 22, 24) },
+ { MT7530_R02_PORT_FW, REG_FIELD(MT753X_RGAC1, 16, 18) },
+ { MT7530_R03_BPDU_FR, REG_FIELD(MT753X_RGAC2, 9, 9) },
+ { MT7530_R03_EG_TAG, REG_FIELD(MT753X_RGAC2, 6, 8) },
+ { MT7530_R03_PORT_FW, REG_FIELD(MT753X_RGAC2, 0, 2) },
+ { MT7530_R0E_BPDU_FR, REG_FIELD(MT753X_RGAC2, 25, 25) },
+ { MT7530_R0E_EG_TAG, REG_FIELD(MT753X_RGAC2, 22, 24) },
+ { MT7530_R0E_PORT_FW, REG_FIELD(MT753X_RGAC2, 16, 18) },
+
+ { MT7530_VAWD_IVL_MAC, REG_FIELD(MT7530_VAWD1, 30, 30) },
+ { MT7530_VAWD_EG_CON, REG_FIELD(MT7530_VAWD1, 29, 29) },
+ { MT7530_VAWD_VTAG_EN, REG_FIELD(MT7530_VAWD1, 28, 28) },
+ { MT7530_VAWD_PORT_MEM, REG_FIELD(MT7530_VAWD1, 16, 23) },
+ { MT7530_VAWD_FID, REG_FIELD(MT7530_VAWD1, 1, 3) },
+ { MT7530_VAWD_VLAN_VALID, REG_FIELD(MT7530_VAWD1, 0, 0) },
+ { __MT7530_VAWD1, REG_FIELD(MT7530_VAWD1, 0, 31) },
+
+ { MT7530_VAWD_ETAG, REG_FIELD(MT7530_VAWD2, 0, 15) },
+ { __MT7530_VAWD2, REG_FIELD(MT7530_VAWD2, 0, 31) },
+
+ { MT7530_VTCR_BUSY, REG_FIELD(MT7530_VTCR, 31, 31) },
+ { MT7530_VTCR_INVALID, REG_FIELD(MT7530_VTCR, 16, 16) },
+ { MT7530_VTCR_FUNC, REG_FIELD(MT7530_VTCR, 12, 15) },
+ { MT7530_VTCR_VID, REG_FIELD(MT7530_VTCR, 0, 11) },
+
+ { MT7530_ATWD_CVID, REG_FIELD(MT7530_ATA2, 0, 11), },
+ { MT7530_ATWD_IVL, REG_FIELD(MT7530_ATA2, 15, 15), },
+ { MT7530_ATWD_FID, REG_FIELD(MT7530_ATA2, 12, 14), },
+ { MT7530_ATWD_AGE_TIMER, REG_FIELD(MT7530_ATWD, 24, 31), },
+ { MT7530_ATWD_PORT_MAP, REG_FIELD(MT7530_ATWD, 4, 11), },
+ { MT7530_ATWD_ENT_STATUS, REG_FIELD(MT7530_ATWD, 2, 3), },
+ { MT7530_ATWD_MAC_BYTE_5, REG_FIELD(MT7530_ATA2, 16, 23), },
+ { MT7530_ATWD_MAC_BYTE_4, REG_FIELD(MT7530_ATA2, 24, 31), },
+ { MT7530_ATWD_MAC_BYTE_3, REG_FIELD(MT7530_ATA1, 0, 7), },
+ { MT7530_ATWD_MAC_BYTE_2, REG_FIELD(MT7530_ATA1, 8, 15), },
+ { MT7530_ATWD_MAC_BYTE_1, REG_FIELD(MT7530_ATA1, 16, 23), },
+ { MT7530_ATWD_MAC_BYTE_0, REG_FIELD(MT7530_ATA1, 24, 31), },
+
+ { __MT7530_ATWD1, REG_FIELD(MT7530_ATWD, 0, 31), },
+ { __MT7530_ATWD2, REG_FIELD(MT7530_ATA1, 0, 31), },
+ { __MT7530_ATWD3, REG_FIELD(MT7530_ATA2, 0, 31), },
+
+ { MT7530_ATRD_CVID, REG_FIELD(MT7530_TSRA2, 0, 11), },
+ { MT7530_ATRD_AGE_TIMER, REG_FIELD(MT7530_ATRD, 24, 31), },
+ { MT7530_ATRD_PORT_MAP, REG_FIELD(MT7530_ATRD, 4, 11), },
+ { MT7530_ATRD_ENT_STATUS, REG_FIELD(MT7530_ATRD, 2, 3), },
+ { MT7530_ATRD_MAC_BYTE_5, REG_FIELD(MT7530_TSRA2, 16, 23), },
+ { MT7530_ATRD_MAC_BYTE_4, REG_FIELD(MT7530_TSRA2, 24, 31), },
+ { MT7530_ATRD_MAC_BYTE_3, REG_FIELD(MT7530_TSRA1, 0, 7), },
+ { MT7530_ATRD_MAC_BYTE_2, REG_FIELD(MT7530_TSRA1, 8, 15), },
+ { MT7530_ATRD_MAC_BYTE_1, REG_FIELD(MT7530_TSRA1, 16, 23), },
+ { MT7530_ATRD_MAC_BYTE_0, REG_FIELD(MT7530_TSRA1, 24, 31), },
+
+ { MT7530_ATC_BUSY, REG_FIELD(MT7530_ATC, 15, 15), },
+ { MT7530_ATC_INVALID, REG_FIELD(MT7530_ATC, 12, 12), },
+ { MT7530_ATC_MAT, REG_FIELD(MT7530_ATC, 8, 11), },
+ { MT7530_ATC_CMD, REG_FIELD(MT7530_ATC, 0, 2), },
+ { __MT7530_ATC, REG_FIELD(MT7530_ATC, 0, 31), },
+
+ { MT7530_SSP_FID_PST, REG_FIELD_ID(MT7530_SSP, 0, 15, MT7530_NUM_PORTS, 0x100) },
+
+ { MT7530_PCR_PORT_TX_MIR, REG_FIELD_ID(MT7530_PCR, 9, 9, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_PCR_PORT_RX_MIR, REG_FIELD_ID(MT7530_PCR, 8, 8, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_PCR_PORT_VLAN, REG_FIELD_ID(MT7530_PCR, 0, 1, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_PCR_MATRIX, REG_FIELD_ID(MT7530_PCR, 16, 23, MT7530_NUM_PORTS, 0x100) },
+
+ { MT7530_PSC_SA_DIS, REG_FIELD_ID(MT7530_PSC, 4, 4, MT7530_NUM_PORTS, 0x100) },
+
+ { MT7530_PVC_EG_TAG, REG_FIELD_ID(MT7530_PVC, 8, 10, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_PVC_VLAN_ATTR, REG_FIELD_ID(MT7530_PVC, 6, 7, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_PVC_ACC_FRM, REG_FIELD_ID(MT7530_PVC, 0, 1, MT7530_NUM_PORTS, 0x100) },
+
+ { MT7530_PPBV1_G0_PORT_VID, REG_FIELD_ID(MT7530_PPBV1, 0, 11, MT7530_NUM_PORTS, 0x100) },
+
+ { MT7530_GMACCR_MAX_RX_JUMBO, REG_FIELD(MT7530_GMACCR, 2, 5) },
+ { MT7530_GMACCR_MAX_RX_PKT_LEN, REG_FIELD(MT7530_GMACCR, 0, 1) },
+
+ { MT7530_MIB_TX_DROP, REG_FIELD_ID(MT7530_PORT_MIB_TX_DROP, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_TX_CRC_ERR, REG_FIELD_ID(MT7530_PORT_MIB_TX_CRC_ERR, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_TX_UNICAST, REG_FIELD_ID(MT7530_PORT_MIB_TX_UNICAST, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_TX_MULTICAST, REG_FIELD_ID(MT7530_PORT_MIB_TX_MULTICAST, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_TX_BROADCAST, REG_FIELD_ID(MT7530_PORT_MIB_TX_BROADCAST, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_TX_COLLISION, REG_FIELD_ID(MT7530_PORT_MIB_TX_COLLISION, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_TX_SINGLE_COLLISION, REG_FIELD_ID(MT7530_PORT_MIB_TX_SINGLE_COLLISION, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_TX_MULTIPLE_COLLISION, REG_FIELD_ID(MT7530_PORT_MIB_TX_MULTIPLE_COLLISION, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_TX_DEFERRED, REG_FIELD_ID(MT7530_PORT_MIB_TX_DEFERRED, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_TX_LATE_COLLISION, REG_FIELD_ID(MT7530_PORT_MIB_TX_LATE_COLLISION, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_TX_EXCESSIVE_COLLISION, REG_FIELD_ID(MT7530_PORT_MIB_TX_EXCESSIVE_COLLISION, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_TX_PAUSE, REG_FIELD_ID(MT7530_PORT_MIB_TX_PAUSE, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_TX_PKT_SZ_64, REG_FIELD_ID(MT7530_PORT_MIB_TX_PKT_SZ_64, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_TX_PKT_SZ_65_TO_127, REG_FIELD_ID(MT7530_PORT_MIB_TX_PKT_SZ_65_TO_127, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_TX_PKT_SZ_128_TO_255, REG_FIELD_ID(MT7530_PORT_MIB_TX_PKT_SZ_128_TO_255, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_TX_PKT_SZ_256_TO_511, REG_FIELD_ID(MT7530_PORT_MIB_TX_PKT_SZ_256_TO_511, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_TX_PKT_SZ_512_TO_1023, REG_FIELD_ID(MT7530_PORT_MIB_TX_PKT_SZ_512_TO_1023, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_TX_PKT_SZ_1024_TO_MAX, REG_FIELD_ID(MT7530_PORT_MIB_TX_PKT_SZ_1024_TO_MAX, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_TX_BYTES_LOW, REG_FIELD_ID(MT7530_PORT_MIB_TX_BYTES_LOW, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_TX_BYTES_HIGH, REG_FIELD_ID(MT7530_PORT_MIB_TX_BYTES_HIGH, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_DROP, REG_FIELD_ID(MT7530_PORT_MIB_RX_DROP, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_FILTERING, REG_FIELD_ID(MT7530_PORT_MIB_RX_FILTERING, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_UNICAST, REG_FIELD_ID(MT7530_PORT_MIB_RX_UNICAST, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_MULTICAST, REG_FIELD_ID(MT7530_PORT_MIB_RX_MULTICAST, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_BROADCAST, REG_FIELD_ID(MT7530_PORT_MIB_RX_BROADCAST, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_ALIGN_ERR, REG_FIELD_ID(MT7530_PORT_MIB_RX_ALIGN_ERR, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_CRC_ERR, REG_FIELD_ID(MT7530_PORT_MIB_RX_CRC_ERR, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_UNDER_SIZE_ERR, REG_FIELD_ID(MT7530_PORT_MIB_RX_UNDER_SIZE_ERR, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_FRAG_ERR, REG_FIELD_ID(MT7530_PORT_MIB_RX_FRAG_ERR, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_OVER_SZ_ERR, REG_FIELD_ID(MT7530_PORT_MIB_RX_OVER_SZ_ERR, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_JABBER_ERR, REG_FIELD_ID(MT7530_PORT_MIB_RX_JABBER_ERR, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_PAUSE, REG_FIELD_ID(MT7530_PORT_MIB_RX_PAUSE, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_PKT_SZ_64, REG_FIELD_ID(MT7530_PORT_MIB_RX_PKT_SZ_64, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_PKT_SZ_65_TO_127, REG_FIELD_ID(MT7530_PORT_MIB_RX_PKT_SZ_65_TO_127, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_PKT_SZ_128_TO_255, REG_FIELD_ID(MT7530_PORT_MIB_RX_PKT_SZ_128_TO_255, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_PKT_SZ_256_TO_511, REG_FIELD_ID(MT7530_PORT_MIB_RX_PKT_SZ_256_TO_511, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_PKT_SZ_512_TO_1023, REG_FIELD_ID(MT7530_PORT_MIB_RX_PKT_SZ_512_TO_1023, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_PKT_SZ_1024_TO_MAX, REG_FIELD_ID(MT7530_PORT_MIB_RX_PKT_SZ_1024_TO_MAX, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_BYTES_LOW, REG_FIELD_ID(MT7530_PORT_MIB_RX_BYTES_LOW, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_BYTES_HIGH, REG_FIELD_ID(MT7530_PORT_MIB_RX_BYTES_HIGH, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_CTRL_DROP, REG_FIELD_ID(MT7530_PORT_MIB_RX_CTRL_DROP, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_INGRESS_DROP, REG_FIELD_ID(MT7530_PORT_MIB_RX_INGRESS_DROP, 0, 31, MT7530_NUM_PORTS, 0x100) },
+ { MT7530_MIB_RX_ARL_DROP, REG_FIELD_ID(MT7530_PORT_MIB_RX_ARL_DROP, 0, 31, MT7530_NUM_PORTS, 0x100) },
+};
+
+static const struct mt7530_reg_field mt7530_fields[] = {
+ { MT7530_MIRROR_EN, REG_FIELD(MT753X_MFC, 3, 3) },
+ { MT7530_MIRROR_PORT, REG_FIELD(MT753X_MFC, 0, 2) },
+};
+
+static const struct mt7530_reg_field mt7531_fields[] = {
+ { MT7530_MIRROR_EN, REG_FIELD(MT7531_CFC, 19, 19) },
+ { MT7530_MIRROR_PORT, REG_FIELD(MT7531_CFC, 16, 18) },
+};
+
static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs)
{
return container_of(pcs, struct mt753x_pcs, pcs);
@@ -35,15 +188,15 @@ static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs)
/* String, offset, and register size in bytes if different from 4 bytes */
static const struct mt7530_mib_desc mt7530_mib[] = {
- MIB_DESC(1, MT7530_PORT_MIB_TX_DROP, "TxDrop"),
- MIB_DESC(1, MT7530_PORT_MIB_TX_CRC_ERR, "TxCrcErr"),
- MIB_DESC(1, MT7530_PORT_MIB_TX_COLLISION, "TxCollision"),
- MIB_DESC(1, MT7530_PORT_MIB_RX_DROP, "RxDrop"),
- MIB_DESC(1, MT7530_PORT_MIB_RX_FILTERING, "RxFiltering"),
- MIB_DESC(1, MT7530_PORT_MIB_RX_CRC_ERR, "RxCrcErr"),
- MIB_DESC(1, MT7530_PORT_MIB_RX_CTRL_DROP, "RxCtrlDrop"),
- MIB_DESC(1, MT7530_PORT_MIB_RX_INGRESS_DROP, "RxIngressDrop"),
- MIB_DESC(1, MT7530_PORT_MIB_RX_ARL_DROP, "RxArlDrop"),
+ MIB_DESC(MT7530_MIB_TX_DROP, -1, "TxDrop"),
+ MIB_DESC(MT7530_MIB_TX_CRC_ERR, -1, "TxCrcErr"),
+ MIB_DESC(MT7530_MIB_TX_COLLISION, -1, "TxCollision"),
+ MIB_DESC(MT7530_MIB_RX_DROP, -1, "RxDrop"),
+ MIB_DESC(MT7530_MIB_RX_FILTERING, -1, "RxFiltering"),
+ MIB_DESC(MT7530_MIB_RX_CRC_ERR, -1, "RxCrcErr"),
+ MIB_DESC(MT7530_MIB_RX_CTRL_DROP, -1, "RxCtrlDrop"),
+ MIB_DESC(MT7530_MIB_RX_INGRESS_DROP, -1, "RxIngressDrop"),
+ MIB_DESC(MT7530_MIB_RX_ARL_DROP, -1, "RxArlDrop"),
};
static void
@@ -154,115 +307,11 @@ core_clear(struct mt7530_priv *priv, u32 reg, u32 val)
core_rmw(priv, reg, val, 0);
}
-static int
-mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)
-{
- u32 val;
- int ret;
-
- /* Set the command operating upon the MAC address entries */
- val = ATC_BUSY | ATC_MAT(0) | cmd;
- ret = regmap_write(priv->regmap, MT7530_ATC, val);
- if (ret)
- return ret;
-
- ret = regmap_read_poll_timeout(priv->regmap, MT7530_ATC, val,
- !(val & ATC_BUSY), 20, 20000);
- if (!ret)
- ret = regmap_read(priv->regmap, MT7530_ATC, &val);
-
- if (ret < 0) {
- dev_err(priv->dev, "reset timeout\n");
- return ret;
- }
-
- /* Additional sanity for read command if the specified
- * entry is invalid
- */
- if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID))
- return -EINVAL;
-
- if (rsp)
- *rsp = val;
-
- return 0;
-}
-
static void mt7530_port_fast_age(struct dsa_switch *ds, int port)
{
struct mt7530_priv *priv = ds->priv;
- u32 val;
- int ret;
-
- mutex_lock(&priv->reg_mutex);
-
- /* Flush all non-static MAC address entries */
- val = ATC_BUSY | ATC_MAT_NON_STATIC_MAC | MT7530_FDB_FLUSH;
- ret = regmap_write(priv->regmap, MT7530_ATC, val);
- if (!ret)
- ret = regmap_read_poll_timeout(priv->regmap, MT7530_ATC, val,
- !(val & ATC_BUSY), 20, 20000);
- if (ret < 0)
- dev_err(priv->dev, "fast age failed: %d\n", ret);
-
- mutex_unlock(&priv->reg_mutex);
-}
-
-static void
-mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb)
-{
- u32 reg[3];
- int i;
-
- /* Read from ARL table into an array */
- for (i = 0; i < 3; i++) {
- regmap_read(priv->regmap, MT7530_TSRA1 + (i * 4),
- ®[i]);
-
- dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n",
- __func__, __LINE__, i, reg[i]);
- }
- fdb->vid = FIELD_GET(CVID_MASK, reg[1]);
- fdb->aging = FIELD_GET(AGE_TIMER_MASK, reg[2]);
- fdb->port_mask = FIELD_GET(PORT_MAP_MASK, reg[2]);
- fdb->mac[0] = FIELD_GET(MAC_BYTE_0_MASK, reg[0]);
- fdb->mac[1] = FIELD_GET(MAC_BYTE_1_MASK, reg[0]);
- fdb->mac[2] = FIELD_GET(MAC_BYTE_2_MASK, reg[0]);
- fdb->mac[3] = FIELD_GET(MAC_BYTE_3_MASK, reg[0]);
- fdb->mac[4] = FIELD_GET(MAC_BYTE_4_MASK, reg[1]);
- fdb->mac[5] = FIELD_GET(MAC_BYTE_5_MASK, reg[1]);
- fdb->noarp = FIELD_GET(ENT_STATUS_MASK, reg[2]) == STATIC_ENT;
-}
-
-static void
-mt7530_fdb_write(struct mt7530_priv *priv, u16 vid,
- u8 port_mask, const u8 *mac,
- u8 aging, u8 type)
-{
- u32 reg[3] = { 0 };
- int i;
-
- reg[1] |= FIELD_PREP(CVID_MASK, vid);
- reg[1] |= ATA2_IVL;
- reg[1] |= ATA2_FID(FID_BRIDGED);
- reg[2] |= FIELD_PREP(AGE_TIMER_MASK, aging);
- reg[2] |= FIELD_PREP(PORT_MAP_MASK, port_mask);
- /* STATIC_ENT indicate that entry is static wouldn't
- * be aged out and STATIC_EMP specified as erasing an
- * entry
- */
- reg[2] |= FIELD_PREP(ENT_STATUS_MASK, type);
- reg[1] |= FIELD_PREP(MAC_BYTE_5_MASK, mac[5]);
- reg[1] |= FIELD_PREP(MAC_BYTE_4_MASK, mac[4]);
- reg[0] |= FIELD_PREP(MAC_BYTE_3_MASK, mac[3]);
- reg[0] |= FIELD_PREP(MAC_BYTE_2_MASK, mac[2]);
- reg[0] |= FIELD_PREP(MAC_BYTE_1_MASK, mac[1]);
- reg[0] |= FIELD_PREP(MAC_BYTE_0_MASK, mac[0]);
-
- /* Write array into the ARL table */
- for (i = 0; i < 3; i++)
- regmap_write(priv->regmap, MT7530_ATA1 + (i * 4), reg[i]);
+ mt7530_lib_port_fast_age(&priv->lib_priv, port);
}
/* Set up switch core clock for MT7530 */
@@ -449,15 +498,6 @@ mt7531_pll_setup(struct mt7530_priv *priv)
usleep_range(25, 35);
}
-static void
-mt7530_mib_reset(struct dsa_switch *ds)
-{
- struct mt7530_priv *priv = ds->priv;
-
- regmap_write(priv->regmap, MT7530_MIB_CCR, CCR_MIB_FLUSH);
- regmap_write(priv->regmap, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);
-}
-
static int mt7530_phy_read_c22(struct mt7530_priv *priv, int port, int regnum)
{
return mdiobus_read_nested(priv->bus, port, regnum);
@@ -702,34 +742,25 @@ mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset,
ethtool_puts(&data, mt7530_mib[i].name);
}
-static void
-mt7530_read_port_stats(struct mt7530_priv *priv, int port,
- u32 offset, u8 size, uint64_t *data)
-{
- u32 val, reg = MT7530_PORT_MIB_COUNTER(port) + offset;
-
- regmap_read(priv->regmap, reg, &val);
- *data = val;
-
- if (size == 2) {
- regmap_read(priv->regmap, reg + 4, &val);
- *data |= (u64)val << 32;
- }
-}
-
static void
mt7530_get_ethtool_stats(struct dsa_switch *ds, int port,
uint64_t *data)
{
struct mt7530_priv *priv = ds->priv;
const struct mt7530_mib_desc *mib;
+ struct mt7530_lib_priv *lib_priv;
int i;
+ lib_priv = &priv->lib_priv;
for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) {
+ struct regmap_field *high = NULL;
mib = &mt7530_mib[i];
- mt7530_read_port_stats(priv, port, mib->offset, mib->size,
- data + i);
+ if (mib->field_high != -1)
+ high = lib_priv->fields[mib->field_high];
+
+ mt7530_lib_read_port_stats(lib_priv->fields[mib->field_low],
+ high, port, data + i);
}
}
@@ -747,54 +778,7 @@ static void mt7530_get_eth_mac_stats(struct dsa_switch *ds, int port,
{
struct mt7530_priv *priv = ds->priv;
- /* MIB counter doesn't provide a FramesTransmittedOK but instead
- * provide stats for Unicast, Broadcast and Multicast frames separately.
- * To simulate a global frame counter, read Unicast and addition Multicast
- * and Broadcast later
- */
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_UNICAST, 1,
- &mac_stats->FramesTransmittedOK);
-
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_SINGLE_COLLISION, 1,
- &mac_stats->SingleCollisionFrames);
-
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_MULTIPLE_COLLISION, 1,
- &mac_stats->MultipleCollisionFrames);
-
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_UNICAST, 1,
- &mac_stats->FramesReceivedOK);
-
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BYTES, 2,
- &mac_stats->OctetsTransmittedOK);
-
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_ALIGN_ERR, 1,
- &mac_stats->AlignmentErrors);
-
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_DEFERRED, 1,
- &mac_stats->FramesWithDeferredXmissions);
-
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_LATE_COLLISION, 1,
- &mac_stats->LateCollisions);
-
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_EXCESSIVE_COLLISION, 1,
- &mac_stats->FramesAbortedDueToXSColls);
-
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BYTES, 2,
- &mac_stats->OctetsReceivedOK);
-
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_MULTICAST, 1,
- &mac_stats->MulticastFramesXmittedOK);
- mac_stats->FramesTransmittedOK += mac_stats->MulticastFramesXmittedOK;
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BROADCAST, 1,
- &mac_stats->BroadcastFramesXmittedOK);
- mac_stats->FramesTransmittedOK += mac_stats->BroadcastFramesXmittedOK;
-
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_MULTICAST, 1,
- &mac_stats->MulticastFramesReceivedOK);
- mac_stats->FramesReceivedOK += mac_stats->MulticastFramesReceivedOK;
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BROADCAST, 1,
- &mac_stats->BroadcastFramesReceivedOK);
- mac_stats->FramesReceivedOK += mac_stats->BroadcastFramesReceivedOK;
+ return mt7530_lib_get_eth_mac_stats(&priv->lib_priv, port, mac_stats);
}
static const struct ethtool_rmon_hist_range mt7530_rmon_ranges[] = {
@@ -807,53 +791,41 @@ static const struct ethtool_rmon_hist_range mt7530_rmon_ranges[] = {
{}
};
+static const struct mt7530_rmon_hist mt7530_rmon_hist_info = {
+ .ranges_fields = (unsigned int []){
+ MT7530_MIB_RX_PKT_SZ_64,
+ MT7530_MIB_RX_PKT_SZ_65_TO_127,
+ MT7530_MIB_RX_PKT_SZ_128_TO_255,
+ MT7530_MIB_RX_PKT_SZ_256_TO_511,
+ MT7530_MIB_RX_PKT_SZ_512_TO_1023,
+ MT7530_MIB_RX_PKT_SZ_1024_TO_MAX,
+ },
+ .ranges_tx_fields = (unsigned int []){
+ MT7530_MIB_TX_PKT_SZ_64,
+ MT7530_MIB_TX_PKT_SZ_65_TO_127,
+ MT7530_MIB_TX_PKT_SZ_128_TO_255,
+ MT7530_MIB_TX_PKT_SZ_256_TO_511,
+ MT7530_MIB_TX_PKT_SZ_512_TO_1023,
+ MT7530_MIB_TX_PKT_SZ_1024_TO_MAX,
+ },
+ .ranges = mt7530_rmon_ranges,
+ .num_ranges = ARRAY_SIZE(mt7530_rmon_ranges) - 1,
+};
+
static void mt7530_get_rmon_stats(struct dsa_switch *ds, int port,
struct ethtool_rmon_stats *rmon_stats,
const struct ethtool_rmon_hist_range **ranges)
{
struct mt7530_priv *priv = ds->priv;
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_UNDER_SIZE_ERR, 1,
- &rmon_stats->undersize_pkts);
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_OVER_SZ_ERR, 1,
- &rmon_stats->oversize_pkts);
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_FRAG_ERR, 1,
- &rmon_stats->fragments);
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_JABBER_ERR, 1,
- &rmon_stats->jabbers);
-
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_64, 1,
- &rmon_stats->hist[0]);
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_65_TO_127, 1,
- &rmon_stats->hist[1]);
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_128_TO_255, 1,
- &rmon_stats->hist[2]);
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_256_TO_511, 1,
- &rmon_stats->hist[3]);
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_512_TO_1023, 1,
- &rmon_stats->hist[4]);
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PKT_SZ_1024_TO_MAX, 1,
- &rmon_stats->hist[5]);
-
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_64, 1,
- &rmon_stats->hist_tx[0]);
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_65_TO_127, 1,
- &rmon_stats->hist_tx[1]);
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_128_TO_255, 1,
- &rmon_stats->hist_tx[2]);
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_256_TO_511, 1,
- &rmon_stats->hist_tx[3]);
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_512_TO_1023, 1,
- &rmon_stats->hist_tx[4]);
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PKT_SZ_1024_TO_MAX, 1,
- &rmon_stats->hist_tx[5]);
-
- *ranges = mt7530_rmon_ranges;
+ return mt7530_lib_get_rmon_stats(&priv->lib_priv, port, rmon_stats, ranges,
+ &mt7530_rmon_hist_info);
}
static void mt7530_read_port_stats64(struct mt7530_priv *priv, int port,
struct rtnl_link_stats64 *storage)
{
+ struct mt7530_lib_priv *lib_priv = &priv->lib_priv;
uint64_t data;
/* MIB counter doesn't provide a FramesTransmittedOK but instead
@@ -861,38 +833,40 @@ static void mt7530_read_port_stats64(struct mt7530_priv *priv, int port,
* To simulate a global frame counter, read Unicast and addition Multicast
* and Broadcast later
*/
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_UNICAST, 1,
- &storage->rx_packets);
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_MULTICAST, 1,
- &storage->multicast);
+ mt7530_lib_read_port_stats(lib_priv->fields[MT7530_MIB_RX_UNICAST],
+ NULL, port, &storage->rx_packets);
+ mt7530_lib_read_port_stats(lib_priv->fields[MT7530_MIB_RX_MULTICAST],
+ NULL, port, &storage->multicast);
storage->rx_packets += storage->multicast;
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BROADCAST, 1,
- &data);
+ mt7530_lib_read_port_stats(lib_priv->fields[MT7530_MIB_RX_BROADCAST],
+ NULL, port, &data);
storage->rx_packets += data;
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_UNICAST, 1,
- &storage->tx_packets);
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_MULTICAST, 1,
- &data);
+ mt7530_lib_read_port_stats(lib_priv->fields[MT7530_MIB_TX_UNICAST],
+ NULL, port, &storage->tx_packets);
+ mt7530_lib_read_port_stats(lib_priv->fields[MT7530_MIB_TX_MULTICAST],
+ NULL, port, &data);
storage->tx_packets += data;
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BROADCAST, 1,
- &data);
+ mt7530_lib_read_port_stats(lib_priv->fields[MT7530_MIB_TX_BROADCAST],
+ NULL, port, &data);
storage->tx_packets += data;
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_BYTES, 2,
- &storage->rx_bytes);
+ mt7530_lib_read_port_stats(lib_priv->fields[MT7530_MIB_RX_BYTES_LOW],
+ lib_priv->fields[MT7530_MIB_RX_BYTES_HIGH], port,
+ &storage->rx_bytes);
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_BYTES, 2,
- &storage->tx_bytes);
+ mt7530_lib_read_port_stats(lib_priv->fields[MT7530_MIB_TX_BYTES_LOW],
+ lib_priv->fields[MT7530_MIB_TX_BYTES_HIGH], port,
+ &storage->tx_bytes);
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_DROP, 1,
- &storage->rx_dropped);
+ mt7530_lib_read_port_stats(lib_priv->fields[MT7530_MIB_RX_DROP],
+ NULL, port, &storage->rx_dropped);
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_DROP, 1,
- &storage->tx_dropped);
+ mt7530_lib_read_port_stats(lib_priv->fields[MT7530_MIB_TX_DROP],
+ NULL, port, &storage->tx_dropped);
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_CRC_ERR, 1,
- &storage->rx_crc_errors);
+ mt7530_lib_read_port_stats(lib_priv->fields[MT7530_MIB_RX_CRC_ERR],
+ NULL, port, &storage->rx_crc_errors);
}
static void mt7530_stats_refresh(struct mt7530_priv *priv)
@@ -948,11 +922,7 @@ static void mt7530_get_eth_ctrl_stats(struct dsa_switch *ds, int port,
{
struct mt7530_priv *priv = ds->priv;
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_TX_PAUSE, 1,
- &ctrl_stats->MACControlFramesTransmitted);
-
- mt7530_read_port_stats(priv, port, MT7530_PORT_MIB_RX_PAUSE, 1,
- &ctrl_stats->MACControlFramesReceived);
+ mt7530_lib_get_eth_ctrl_stats(&priv->lib_priv, port, ctrl_stats);
}
static int
@@ -1073,214 +1043,6 @@ static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)
mutex_unlock(&priv->reg_mutex);
}
-/* In Clause 5 of IEEE Std 802-2014, two sublayers of the data link layer (DLL)
- * of the Open Systems Interconnection basic reference model (OSI/RM) are
- * described; the medium access control (MAC) and logical link control (LLC)
- * sublayers. The MAC sublayer is the one facing the physical layer.
- *
- * In 8.2 of IEEE Std 802.1Q-2022, the Bridge architecture is described. A
- * Bridge component comprises a MAC Relay Entity for interconnecting the Ports
- * of the Bridge, at least two Ports, and higher layer entities with at least a
- * Spanning Tree Protocol Entity included.
- *
- * Each Bridge Port also functions as an end station and shall provide the MAC
- * Service to an LLC Entity. Each instance of the MAC Service is provided to a
- * distinct LLC Entity that supports protocol identification, multiplexing, and
- * demultiplexing, for protocol data unit (PDU) transmission and reception by
- * one or more higher layer entities.
- *
- * It is described in 8.13.9 of IEEE Std 802.1Q-2022 that in a Bridge, the LLC
- * Entity associated with each Bridge Port is modeled as being directly
- * connected to the attached Local Area Network (LAN).
- *
- * On the switch with CPU port architecture, CPU port functions as Management
- * Port, and the Management Port functionality is provided by software which
- * functions as an end station. Software is connected to an IEEE 802 LAN that is
- * wholly contained within the system that incorporates the Bridge. Software
- * provides access to the LLC Entity associated with each Bridge Port by the
- * value of the source port field on the special tag on the frame received by
- * software.
- *
- * We call frames that carry control information to determine the active
- * topology and current extent of each Virtual Local Area Network (VLAN), i.e.,
- * spanning tree or Shortest Path Bridging (SPB) and Multiple VLAN Registration
- * Protocol Data Units (MVRPDUs), and frames from other link constrained
- * protocols, such as Extensible Authentication Protocol over LAN (EAPOL) and
- * Link Layer Discovery Protocol (LLDP), link-local frames. They are not
- * forwarded by a Bridge. Permanently configured entries in the filtering
- * database (FDB) ensure that such frames are discarded by the Forwarding
- * Process. In 8.6.3 of IEEE Std 802.1Q-2022, this is described in detail:
- *
- * Each of the reserved MAC addresses specified in Table 8-1
- * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]) shall be
- * permanently configured in the FDB in C-VLAN components and ERs.
- *
- * Each of the reserved MAC addresses specified in Table 8-2
- * (01-80-C2-00-00-[01,02,03,04,05,06,07,08,09,0A,0E]) shall be permanently
- * configured in the FDB in S-VLAN components.
- *
- * Each of the reserved MAC addresses specified in Table 8-3
- * (01-80-C2-00-00-[01,02,04,0E]) shall be permanently configured in the FDB in
- * TPMR components.
- *
- * The FDB entries for reserved MAC addresses shall specify filtering for all
- * Bridge Ports and all VIDs. Management shall not provide the capability to
- * modify or remove entries for reserved MAC addresses.
- *
- * The addresses in Table 8-1, Table 8-2, and Table 8-3 determine the scope of
- * propagation of PDUs within a Bridged Network, as follows:
- *
- * The Nearest Bridge group address (01-80-C2-00-00-0E) is an address that no
- * conformant Two-Port MAC Relay (TPMR) component, Service VLAN (S-VLAN)
- * component, Customer VLAN (C-VLAN) component, or MAC Bridge can forward.
- * PDUs transmitted using this destination address, or any other addresses
- * that appear in Table 8-1, Table 8-2, and Table 8-3
- * (01-80-C2-00-00-[00,01,02,03,04,05,06,07,08,09,0A,0B,0C,0D,0E,0F]), can
- * therefore travel no further than those stations that can be reached via a
- * single individual LAN from the originating station.
- *
- * The Nearest non-TPMR Bridge group address (01-80-C2-00-00-03), is an
- * address that no conformant S-VLAN component, C-VLAN component, or MAC
- * Bridge can forward; however, this address is relayed by a TPMR component.
- * PDUs using this destination address, or any of the other addresses that
- * appear in both Table 8-1 and Table 8-2 but not in Table 8-3
- * (01-80-C2-00-00-[00,03,05,06,07,08,09,0A,0B,0C,0D,0F]), will be relayed by
- * any TPMRs but will propagate no further than the nearest S-VLAN component,
- * C-VLAN component, or MAC Bridge.
- *
- * The Nearest Customer Bridge group address (01-80-C2-00-00-00) is an address
- * that no conformant C-VLAN component, MAC Bridge can forward; however, it is
- * relayed by TPMR components and S-VLAN components. PDUs using this
- * destination address, or any of the other addresses that appear in Table 8-1
- * but not in either Table 8-2 or Table 8-3 (01-80-C2-00-00-[00,0B,0C,0D,0F]),
- * will be relayed by TPMR components and S-VLAN components but will propagate
- * no further than the nearest C-VLAN component or MAC Bridge.
- *
- * Because the LLC Entity associated with each Bridge Port is provided via CPU
- * port, we must not filter these frames but forward them to CPU port.
- *
- * In a Bridge, the transmission Port is majorly decided by ingress and egress
- * rules, FDB, and spanning tree Port State functions of the Forwarding Process.
- * For link-local frames, only CPU port should be designated as destination port
- * in the FDB, and the other functions of the Forwarding Process must not
- * interfere with the decision of the transmission Port. We call this process
- * trapping frames to CPU port.
- *
- * Therefore, on the switch with CPU port architecture, link-local frames must
- * be trapped to CPU port, and certain link-local frames received by a Port of a
- * Bridge comprising a TPMR component or an S-VLAN component must be excluded
- * from it.
- *
- * A Bridge of the switch with CPU port architecture cannot comprise a Two-Port
- * MAC Relay (TPMR) component as a TPMR component supports only a subset of the
- * functionality of a MAC Bridge. A Bridge comprising two Ports (Management Port
- * doesn't count) of this architecture will either function as a standard MAC
- * Bridge or a standard VLAN Bridge.
- *
- * Therefore, a Bridge of this architecture can only comprise S-VLAN components,
- * C-VLAN components, or MAC Bridge components. Since there's no TPMR component,
- * we don't need to relay PDUs using the destination addresses specified on the
- * Nearest non-TPMR section, and the proportion of the Nearest Customer Bridge
- * section where they must be relayed by TPMR components.
- *
- * One option to trap link-local frames to CPU port is to add static FDB entries
- * with CPU port designated as destination port. However, because that
- * Independent VLAN Learning (IVL) is being used on every VID, each entry only
- * applies to a single VLAN Identifier (VID). For a Bridge comprising a MAC
- * Bridge component or a C-VLAN component, there would have to be 16 times 4096
- * entries. This switch intellectual property can only hold a maximum of 2048
- * entries. Using this option, there also isn't a mechanism to prevent
- * link-local frames from being discarded when the spanning tree Port State of
- * the reception Port is discarding.
- *
- * The remaining option is to utilise the BPC, RGAC1, RGAC2, RGAC3, and RGAC4
- * registers. Whilst this applies to every VID, it doesn't contain all of the
- * reserved MAC addresses without affecting the remaining Standard Group MAC
- * Addresses. The REV_UN frame tag utilised using the RGAC4 register covers the
- * remaining 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F] destination
- * addresses. It also includes the 01-80-C2-00-00-22 to 01-80-C2-00-00-FF
- * destination addresses which may be relayed by MAC Bridges or VLAN Bridges.
- * The latter option provides better but not complete conformance.
- *
- * This switch intellectual property also does not provide a mechanism to trap
- * link-local frames with specific destination addresses to CPU port by Bridge,
- * to conform to the filtering rules for the distinct Bridge components.
- *
- * Therefore, regardless of the type of the Bridge component, link-local frames
- * with these destination addresses will be trapped to CPU port:
- *
- * 01-80-C2-00-00-[00,01,02,03,0E]
- *
- * In a Bridge comprising a MAC Bridge component or a C-VLAN component:
- *
- * Link-local frames with these destination addresses won't be trapped to CPU
- * port which won't conform to IEEE Std 802.1Q-2022:
- *
- * 01-80-C2-00-00-[04,05,06,07,08,09,0A,0B,0C,0D,0F]
- *
- * In a Bridge comprising an S-VLAN component:
- *
- * Link-local frames with these destination addresses will be trapped to CPU
- * port which won't conform to IEEE Std 802.1Q-2022:
- *
- * 01-80-C2-00-00-00
- *
- * Link-local frames with these destination addresses won't be trapped to CPU
- * port which won't conform to IEEE Std 802.1Q-2022:
- *
- * 01-80-C2-00-00-[04,05,06,07,08,09,0A]
- *
- * To trap link-local frames to CPU port as conformant as this switch
- * intellectual property can allow, link-local frames are made to be regarded as
- * Bridge Protocol Data Units (BPDUs). This is because this switch intellectual
- * property only lets the frames regarded as BPDUs bypass the spanning tree Port
- * State function of the Forwarding Process.
- *
- * The only remaining interference is the ingress rules. When the reception Port
- * has no PVID assigned on software, VLAN-untagged frames won't be allowed in.
- * There doesn't seem to be a mechanism on the switch intellectual property to
- * have link-local frames bypass this function of the Forwarding Process.
- */
-static void
-mt753x_trap_frames(struct mt7530_priv *priv)
-{
- /* Trap 802.1X PAE frames and BPDUs to the CPU port(s) and egress
- * them with the EG_TAG attribute set to disabled (system default)
- * so that any VLAN tags in the frame are not modified by the
- * switch egress VLAN tag processing. This preserves VLAN tags
- * for reception on VLAN sub-interfaces.
- */
- regmap_update_bits(priv->regmap, MT753X_BPC,
- PAE_BPDU_FR | PAE_EG_TAG_MASK | PAE_PORT_FW_MASK |
- BPDU_EG_TAG_MASK | BPDU_PORT_FW_MASK,
- PAE_BPDU_FR | PAE_EG_TAG(MT7530_VLAN_EG_DISABLED) |
- PAE_PORT_FW(TO_CPU_FW_CPU_ONLY) |
- BPDU_EG_TAG(MT7530_VLAN_EG_DISABLED) |
- TO_CPU_FW_CPU_ONLY);
-
- /* Trap frames with :01 and :02 MAC DAs to the CPU port(s) and
- * egress them with EG_TAG disabled.
- */
- regmap_update_bits(priv->regmap, MT753X_RGAC1,
- R02_BPDU_FR | R02_EG_TAG_MASK | R02_PORT_FW_MASK |
- R01_BPDU_FR | R01_EG_TAG_MASK | R01_PORT_FW_MASK,
- R02_BPDU_FR | R02_EG_TAG(MT7530_VLAN_EG_DISABLED) |
- R02_PORT_FW(TO_CPU_FW_CPU_ONLY) | R01_BPDU_FR |
- R01_EG_TAG(MT7530_VLAN_EG_DISABLED) |
- TO_CPU_FW_CPU_ONLY);
-
- /* Trap frames with :03 and :0E MAC DAs to the CPU port(s) and
- * egress them with EG_TAG disabled.
- */
- regmap_update_bits(priv->regmap, MT753X_RGAC2,
- R0E_BPDU_FR | R0E_EG_TAG_MASK | R0E_PORT_FW_MASK |
- R03_BPDU_FR | R03_EG_TAG_MASK | R03_PORT_FW_MASK,
- R0E_BPDU_FR | R0E_EG_TAG(MT7530_VLAN_EG_DISABLED) |
- R0E_PORT_FW(TO_CPU_FW_CPU_ONLY) | R03_BPDU_FR |
- R03_EG_TAG(MT7530_VLAN_EG_DISABLED) |
- TO_CPU_FW_CPU_ONLY);
-}
-
static void
mt753x_cpu_port_enable(struct dsa_switch *ds, int port)
{
@@ -1329,11 +1091,11 @@ mt7530_port_enable(struct dsa_switch *ds, int port,
if (dsa_port_is_user(dp)) {
struct dsa_port *cpu_dp = dp->cpu_dp;
- priv->ports[port].pm |= PCR_MATRIX(BIT(cpu_dp->index));
+ priv->ports[port].pm |= BIT(cpu_dp->index);
}
priv->ports[port].enable = true;
regmap_update_bits(priv->regmap, MT7530_PCR_P(port), PCR_MATRIX_MASK,
- priv->ports[port].pm);
+ PCR_MATRIX(priv->ports[port].pm));
mutex_unlock(&priv->reg_mutex);
@@ -1378,36 +1140,8 @@ static int
mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
{
struct mt7530_priv *priv = ds->priv;
- int length;
- u32 val;
-
- /* When a new MTU is set, DSA always set the CPU port's MTU to the
- * largest MTU of the user ports. Because the switch only has a global
- * RX length register, only allowing CPU port here is enough.
- */
- if (!dsa_is_cpu_port(ds, port))
- return 0;
-
- regmap_read(priv->regmap, MT7530_GMACCR, &val);
- val &= ~MAX_RX_PKT_LEN_MASK;
-
- /* RX length also includes Ethernet header, MTK tag, and FCS length */
- length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN;
- if (length <= 1522) {
- val |= MAX_RX_PKT_LEN_1522;
- } else if (length <= 1536) {
- val |= MAX_RX_PKT_LEN_1536;
- } else if (length <= 1552) {
- val |= MAX_RX_PKT_LEN_1552;
- } else {
- val &= ~MAX_RX_JUMBO_MASK;
- val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024));
- val |= MAX_RX_PKT_LEN_JUMBO;
- }
-
- regmap_write(priv->regmap, MT7530_GMACCR, val);
- return 0;
+ return mt7530_lib_port_change_mtu(&priv->lib_priv, port, new_mtu);
}
static int
@@ -1420,81 +1154,8 @@ static void
mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state)
{
struct mt7530_priv *priv = ds->priv;
- u32 stp_state;
- switch (state) {
- case BR_STATE_DISABLED:
- stp_state = MT7530_STP_DISABLED;
- break;
- case BR_STATE_BLOCKING:
- stp_state = MT7530_STP_BLOCKING;
- break;
- case BR_STATE_LISTENING:
- stp_state = MT7530_STP_LISTENING;
- break;
- case BR_STATE_LEARNING:
- stp_state = MT7530_STP_LEARNING;
- break;
- case BR_STATE_FORWARDING:
- default:
- stp_state = MT7530_STP_FORWARDING;
- break;
- }
-
- regmap_update_bits(priv->regmap, MT7530_SSP_P(port),
- FID_PST_MASK(FID_BRIDGED),
- FID_PST(FID_BRIDGED, stp_state));
-}
-
-static void mt7530_update_port_member(struct mt7530_priv *priv, int port,
- const struct net_device *bridge_dev,
- bool join) __must_hold(&priv->reg_mutex)
-{
- struct dsa_port *dp = dsa_to_port(priv->ds, port), *other_dp;
- struct mt7530_port *p = &priv->ports[port], *other_p;
- struct dsa_port *cpu_dp = dp->cpu_dp;
- u32 port_bitmap = BIT(cpu_dp->index);
- int other_port;
- bool isolated;
-
- dsa_switch_for_each_user_port(other_dp, priv->ds) {
- other_port = other_dp->index;
- other_p = &priv->ports[other_port];
-
- if (dp == other_dp)
- continue;
-
- /* Add/remove this port to/from the port matrix of the other
- * ports in the same bridge. If the port is disabled, port
- * matrix is kept and not being setup until the port becomes
- * enabled.
- */
- if (!dsa_port_offloads_bridge_dev(other_dp, bridge_dev))
- continue;
-
- isolated = p->isolated && other_p->isolated;
-
- if (join && !isolated) {
- other_p->pm |= PCR_MATRIX(BIT(port));
- port_bitmap |= BIT(other_port);
- } else {
- other_p->pm &= ~PCR_MATRIX(BIT(port));
- }
-
- if (other_p->enable)
- regmap_update_bits(priv->regmap,
- MT7530_PCR_P(other_port),
- PCR_MATRIX_MASK, other_p->pm);
- }
-
- /* Add/remove the all other ports to this port matrix. For !join
- * (leaving the bridge), only the CPU port will remain in the port matrix
- * of this port.
- */
- p->pm = PCR_MATRIX(port_bitmap);
- if (priv->ports[port].enable)
- regmap_update_bits(priv->regmap, MT7530_PCR_P(port),
- PCR_MATRIX_MASK, p->pm);
+ mt7530_lib_stp_state_set(&priv->lib_priv, port, state);
}
static int
@@ -1516,37 +1177,8 @@ mt7530_port_bridge_flags(struct dsa_switch *ds, int port,
{
struct mt7530_priv *priv = ds->priv;
- if (flags.mask & BR_LEARNING)
- regmap_update_bits(priv->regmap, MT7530_PSC_P(port), SA_DIS,
- flags.val & BR_LEARNING ? 0 : SA_DIS);
-
- if (flags.mask & BR_FLOOD)
- regmap_update_bits(priv->regmap, MT753X_MFC,
- UNU_FFP(BIT(port)),
- flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0);
-
- if (flags.mask & BR_MCAST_FLOOD)
- regmap_update_bits(priv->regmap, MT753X_MFC,
- UNM_FFP(BIT(port)),
- flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0);
-
- if (flags.mask & BR_BCAST_FLOOD)
- regmap_update_bits(priv->regmap, MT753X_MFC,
- BC_FFP(BIT(port)),
- flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0);
-
- if (flags.mask & BR_ISOLATED) {
- struct dsa_port *dp = dsa_to_port(ds, port);
- struct net_device *bridge_dev = dsa_port_bridge_dev_get(dp);
-
- priv->ports[port].isolated = !!(flags.val & BR_ISOLATED);
-
- mutex_lock(&priv->reg_mutex);
- mt7530_update_port_member(priv, port, bridge_dev, true);
- mutex_unlock(&priv->reg_mutex);
- }
-
- return 0;
+ return mt7530_lib_port_bridge_flags(&priv->lib_priv, port, flags,
+ extack);
}
static int
@@ -1556,151 +1188,8 @@ mt7530_port_bridge_join(struct dsa_switch *ds, int port,
{
struct mt7530_priv *priv = ds->priv;
- mutex_lock(&priv->reg_mutex);
-
- mt7530_update_port_member(priv, port, bridge.dev, true);
-
- /* Set to fallback mode for independent VLAN learning */
- regmap_update_bits(priv->regmap, MT7530_PCR_P(port),
- PCR_PORT_VLAN_MASK, MT7530_PORT_FALLBACK_MODE);
-
- mutex_unlock(&priv->reg_mutex);
-
- return 0;
-}
-
-static int
-mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid)
-{
- u32 val;
- int ret;
-
- val = VTCR_BUSY | VTCR_FUNC(cmd) | VTCR_VID(vid);
- ret = regmap_write(priv->regmap, MT7530_VTCR, val);
- if (ret)
- return ret;
-
- ret = regmap_read_poll_timeout(priv->regmap, MT7530_VTCR, val,
- !(val & VTCR_BUSY), 20, 20000);
- if (!ret)
- ret = regmap_read(priv->regmap, MT7530_VTCR, &val);
-
- if (ret < 0) {
- dev_err(priv->dev, "poll timeout\n");
- return ret;
- }
-
- if (val & VTCR_INVALID) {
- dev_err(priv->dev, "read VTCR invalid\n");
- return -EINVAL;
- }
-
- return 0;
-}
-
-static int
-mt7530_setup_vlan0(struct mt7530_priv *priv)
-{
- u32 val;
-
- /* Validate the entry with independent learning, keep the original
- * ingress tag attribute.
- */
- val = IVL_MAC | EG_CON | PORT_MEM(MT7530_ALL_MEMBERS) | FID(FID_BRIDGED) |
- VLAN_VALID;
- regmap_write(priv->regmap, MT7530_VAWD1, val);
- regmap_write(priv->regmap, MT7530_VAWD2, 0);
-
- return mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0);
-}
-
-static void
-mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port)
-{
- struct mt7530_priv *priv = ds->priv;
- bool all_user_ports_removed = true;
- int i;
-
- /* This is called after .port_bridge_leave when leaving a VLAN-aware
- * bridge. Don't set standalone ports to fallback mode.
- */
- if (dsa_port_bridge_dev_get(dsa_to_port(ds, port)))
- regmap_update_bits(priv->regmap, MT7530_PCR_P(port),
- PCR_PORT_VLAN_MASK,
- MT7530_PORT_FALLBACK_MODE);
-
- regmap_update_bits(priv->regmap, MT7530_PVC_P(port),
- VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK,
- VLAN_ATTR(MT7530_VLAN_TRANSPARENT) |
- PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) |
- MT7530_VLAN_ACC_ALL);
-
- /* Set PVID to 0 */
- regmap_update_bits(priv->regmap, MT7530_PPBV1_P(port),
- G0_PORT_VID_MASK, G0_PORT_VID_DEF);
-
- for (i = 0; i < priv->ds->num_ports; i++) {
- if (i == port)
- continue;
- if (dsa_is_user_port(ds, i) &&
- dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
- all_user_ports_removed = false;
- break;
- }
- }
-
- /* CPU port also does the same thing until all user ports belonging to
- * the CPU port get out of VLAN filtering mode.
- */
- if (all_user_ports_removed) {
- mutex_lock(&priv->reg_mutex);
- mt7530_setup_vlan0(priv);
- mutex_unlock(&priv->reg_mutex);
- }
-}
-
-static void
-mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port)
-{
- struct mt7530_priv *priv = ds->priv;
-
- /* Trapped into security mode allows packet forwarding through VLAN
- * table lookup.
- */
- if (dsa_is_user_port(ds, port)) {
- regmap_update_bits(priv->regmap, MT7530_PCR_P(port),
- PCR_PORT_VLAN_MASK,
- MT7530_PORT_SECURITY_MODE);
- regmap_update_bits(priv->regmap, MT7530_PPBV1_P(port),
- G0_PORT_VID_MASK,
- G0_PORT_VID(priv->ports[port].pvid));
-
- /* Only accept tagged frames if PVID is not set */
- if (!priv->ports[port].pvid)
- regmap_update_bits(priv->regmap, MT7530_PVC_P(port),
- ACC_FRM_MASK,
- MT7530_VLAN_ACC_TAGGED);
-
- /* Set the port as a user port which is to be able to recognize
- * VID from incoming packets before fetching entry within the
- * VLAN table.
- */
- regmap_update_bits(priv->regmap, MT7530_PVC_P(port),
- VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
- VLAN_ATTR(MT7530_VLAN_USER) |
- PVC_EG_TAG(MT7530_VLAN_EG_DISABLED));
- } else {
- /* Also set CPU ports to the "user" VLAN port attribute, to
- * allow VLAN classification, but keep the EG_TAG attribute as
- * "consistent" (i.o.w. don't change its value) for packets
- * received by the switch from the CPU, so that tagged packets
- * are forwarded to user ports as tagged, and untagged as
- * untagged.
- */
- regmap_update_bits(priv->regmap, MT7530_PVC_P(port),
- VLAN_ATTR_MASK,
- VLAN_ATTR(MT7530_VLAN_USER));
- }
+ return mt7530_lib_port_bridge_join(&priv->lib_priv, port, bridge,
+ tx_fwd_offload, extack);
}
static void
@@ -1709,18 +1198,7 @@ mt7530_port_bridge_leave(struct dsa_switch *ds, int port,
{
struct mt7530_priv *priv = ds->priv;
- mutex_lock(&priv->reg_mutex);
-
- mt7530_update_port_member(priv, port, bridge.dev, false);
-
- /* When a port is removed from the bridge, the port would be set up
- * back to the default as is at initial boot which is a VLAN-unaware
- * port.
- */
- regmap_update_bits(priv->regmap, MT7530_PCR_P(port),
- PCR_PORT_VLAN_MASK, MT7530_PORT_MATRIX_MODE);
-
- mutex_unlock(&priv->reg_mutex);
+ return mt7530_lib_port_bridge_leave(&priv->lib_priv, port, bridge);
}
static int
@@ -1729,15 +1207,8 @@ mt7530_port_fdb_add(struct dsa_switch *ds, int port,
struct dsa_db db)
{
struct mt7530_priv *priv = ds->priv;
- int ret;
- u8 port_mask = BIT(port);
-
- mutex_lock(&priv->reg_mutex);
- mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
- ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
- mutex_unlock(&priv->reg_mutex);
- return ret;
+ return mt7530_lib_port_fdb_add(&priv->lib_priv, port, addr, vid, db);
}
static int
@@ -1746,15 +1217,8 @@ mt7530_port_fdb_del(struct dsa_switch *ds, int port,
struct dsa_db db)
{
struct mt7530_priv *priv = ds->priv;
- int ret;
- u8 port_mask = BIT(port);
- mutex_lock(&priv->reg_mutex);
- mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP);
- ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
- mutex_unlock(&priv->reg_mutex);
-
- return ret;
+ return mt7530_lib_port_fdb_del(&priv->lib_priv, port, addr, vid, db);
}
static int
@@ -1769,13 +1233,14 @@ mt7530_port_fdb_dump(struct dsa_switch *ds, int port,
mutex_lock(&priv->reg_mutex);
- ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp);
+ ret = mt7530_lib_fdb_cmd(&priv->lib_priv, MT7530_FDB_START,
+ ATC_MAT_MACTAB, &rsp);
if (ret < 0)
goto err;
do {
if (rsp & ATC_SRCH_HIT) {
- mt7530_fdb_read(priv, &_fdb);
+ mt7530_lib_fdb_read(&priv->lib_priv, &_fdb);
if (_fdb.port_mask & BIT(port)) {
ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp,
data);
@@ -1785,7 +1250,8 @@ mt7530_port_fdb_dump(struct dsa_switch *ds, int port,
}
} while (--cnt &&
!(rsp & ATC_SRCH_END) &&
- !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp));
+ !mt7530_lib_fdb_cmd(&priv->lib_priv, MT7530_FDB_NEXT,
+ ATC_MAT_MACTAB, &rsp));
err:
mutex_unlock(&priv->reg_mutex);
@@ -1798,27 +1264,8 @@ mt7530_port_mdb_add(struct dsa_switch *ds, int port,
struct dsa_db db)
{
struct mt7530_priv *priv = ds->priv;
- const u8 *addr = mdb->addr;
- u16 vid = mdb->vid;
- u8 port_mask = 0;
- u32 val;
- int ret;
-
- mutex_lock(&priv->reg_mutex);
-
- mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP);
- if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) {
- regmap_read(priv->regmap, MT7530_ATRD, &val);
- port_mask = FIELD_GET(PORT_MAP_MASK, val);
- }
-
- port_mask |= BIT(port);
- mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
- ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
-
- mutex_unlock(&priv->reg_mutex);
- return ret;
+ return mt7530_lib_port_mdb_add(&priv->lib_priv, port, mdb, db);
}
static int
@@ -1827,132 +1274,19 @@ mt7530_port_mdb_del(struct dsa_switch *ds, int port,
struct dsa_db db)
{
struct mt7530_priv *priv = ds->priv;
- const u8 *addr = mdb->addr;
- u16 vid = mdb->vid;
- u8 port_mask = 0;
- u32 val;
- int ret;
-
- mutex_lock(&priv->reg_mutex);
- mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP);
- if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) {
- regmap_read(priv->regmap, MT7530_ATRD, &val);
- port_mask = FIELD_GET(PORT_MAP_MASK, val);
- }
-
- port_mask &= ~BIT(port);
- mt7530_fdb_write(priv, vid, port_mask, addr, -1,
- port_mask ? STATIC_ENT : STATIC_EMP);
- ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
-
- mutex_unlock(&priv->reg_mutex);
-
- return ret;
+ return mt7530_lib_port_mdb_del(&priv->lib_priv, port, mdb, db);
}
static int
mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
struct netlink_ext_ack *extack)
{
- struct dsa_port *dp = dsa_to_port(ds, port);
- struct dsa_port *cpu_dp = dp->cpu_dp;
-
- if (vlan_filtering) {
- /* The port is being kept as VLAN-unaware port when bridge is
- * set up with vlan_filtering not being set, Otherwise, the
- * port and the corresponding CPU port is required the setup
- * for becoming a VLAN-aware port.
- */
- mt7530_port_set_vlan_aware(ds, port);
- mt7530_port_set_vlan_aware(ds, cpu_dp->index);
- } else {
- mt7530_port_set_vlan_unaware(ds, port);
- }
-
- return 0;
-}
-
-static void
-mt7530_hw_vlan_add(struct mt7530_priv *priv,
- struct mt7530_hw_vlan_entry *entry)
-{
- struct dsa_port *dp = dsa_to_port(priv->ds, entry->port);
- u8 new_members;
- u32 val;
-
- new_members = entry->old_members | BIT(entry->port);
-
- /* Validate the entry with independent learning, create egress tag per
- * VLAN and joining the port as one of the port members.
- */
- val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) |
- VLAN_VALID;
- regmap_write(priv->regmap, MT7530_VAWD1, val);
-
- /* Decide whether adding tag or not for those outgoing packets from the
- * port inside the VLAN.
- * CPU port is always taken as a tagged port for serving more than one
- * VLANs across and also being applied with egress type stack mode for
- * that VLAN tags would be appended after hardware special tag used as
- * DSA tag.
- */
- if (dsa_port_is_cpu(dp))
- val = MT7530_VLAN_EGRESS_STACK;
- else if (entry->untagged)
- val = MT7530_VLAN_EGRESS_UNTAG;
- else
- val = MT7530_VLAN_EGRESS_TAG;
- regmap_update_bits(priv->regmap, MT7530_VAWD2,
- ETAG_CTRL_P_MASK(entry->port),
- ETAG_CTRL_P(entry->port, val));
-}
-
-static void
-mt7530_hw_vlan_del(struct mt7530_priv *priv,
- struct mt7530_hw_vlan_entry *entry)
-{
- u8 new_members;
- u32 val;
-
- new_members = entry->old_members & ~BIT(entry->port);
-
- regmap_read(priv->regmap, MT7530_VAWD1, &val);
- if (!(val & VLAN_VALID)) {
- dev_err(priv->dev,
- "Cannot be deleted due to invalid entry\n");
- return;
- }
-
- if (new_members) {
- val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) |
- VLAN_VALID;
- regmap_write(priv->regmap, MT7530_VAWD1, val);
- } else {
- regmap_write(priv->regmap, MT7530_VAWD1, 0);
- regmap_write(priv->regmap, MT7530_VAWD2, 0);
- }
-}
-
-static void
-mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid,
- struct mt7530_hw_vlan_entry *entry,
- mt7530_vlan_op vlan_op)
-{
- u32 val;
-
- /* Fetch entry */
- mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid);
-
- regmap_read(priv->regmap, MT7530_VAWD1, &val);
-
- entry->old_members = FIELD_GET(PORT_MEM_MASK, val);
-
- /* Manipulate entry */
- vlan_op(priv, entry);
+ struct mt7530_priv *priv = ds->priv;
- /* Flush result to hardware */
- mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid);
+ return mt7530_lib_port_vlan_filtering(&priv->lib_priv, port,
+ vlan_filtering,
+ extack);
}
static int
@@ -1960,94 +1294,18 @@ mt7530_port_vlan_add(struct dsa_switch *ds, int port,
const struct switchdev_obj_port_vlan *vlan,
struct netlink_ext_ack *extack)
{
- bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
- bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
- struct mt7530_hw_vlan_entry new_entry;
struct mt7530_priv *priv = ds->priv;
- mutex_lock(&priv->reg_mutex);
-
- /* VID 0 is managed exclusively by mt7530_setup_vlan0() for
- * VLAN-unaware bridge operation. Don't let the bridge overwrite
- * its EG_CON flag with VTAG_EN and corrupt PORT_MEM.
- */
- if (vlan->vid == 0)
- goto skip_vlan_table;
-
- mt7530_hw_vlan_entry_init(&new_entry, port, untagged);
- mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add);
-
-skip_vlan_table:
-
- if (pvid) {
- priv->ports[port].pvid = vlan->vid;
-
- /* Accept all frames if PVID is set */
- regmap_update_bits(priv->regmap, MT7530_PVC_P(port),
- ACC_FRM_MASK, MT7530_VLAN_ACC_ALL);
-
- /* Only configure PVID if VLAN filtering is enabled */
- if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
- regmap_update_bits(priv->regmap, MT7530_PPBV1_P(port),
- G0_PORT_VID_MASK,
- G0_PORT_VID(vlan->vid));
- } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) {
- /* This VLAN is overwritten without PVID, so unset it */
- priv->ports[port].pvid = G0_PORT_VID_DEF;
-
- /* Only accept tagged frames if the port is VLAN-aware */
- if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
- regmap_update_bits(priv->regmap, MT7530_PVC_P(port),
- ACC_FRM_MASK,
- MT7530_VLAN_ACC_TAGGED);
-
- regmap_update_bits(priv->regmap, MT7530_PPBV1_P(port),
- G0_PORT_VID_MASK, G0_PORT_VID_DEF);
- }
-
- mutex_unlock(&priv->reg_mutex);
-
- return 0;
+ return mt7530_lib_port_vlan_add(&priv->lib_priv, port, vlan, extack);
}
static int
mt7530_port_vlan_del(struct dsa_switch *ds, int port,
const struct switchdev_obj_port_vlan *vlan)
{
- struct mt7530_hw_vlan_entry target_entry;
struct mt7530_priv *priv = ds->priv;
- mutex_lock(&priv->reg_mutex);
-
- /* VID 0 is managed exclusively by mt7530_setup_vlan0(). */
- if (vlan->vid == 0)
- goto skip_vlan_table;
-
- mt7530_hw_vlan_entry_init(&target_entry, port, 0);
- mt7530_hw_vlan_update(priv, vlan->vid, &target_entry,
- mt7530_hw_vlan_del);
-
-skip_vlan_table:
- /* PVID is being restored to the default whenever the PVID port
- * is being removed from the VLAN.
- */
- if (priv->ports[port].pvid == vlan->vid) {
- priv->ports[port].pvid = G0_PORT_VID_DEF;
-
- /* Only accept tagged frames if the port is VLAN-aware */
- if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
- regmap_update_bits(priv->regmap, MT7530_PVC_P(port),
- ACC_FRM_MASK,
- MT7530_VLAN_ACC_TAGGED);
-
- regmap_update_bits(priv->regmap, MT7530_PPBV1_P(port),
- G0_PORT_VID_MASK, G0_PORT_VID_DEF);
- }
-
-
- mutex_unlock(&priv->reg_mutex);
-
- return 0;
+ return mt7530_lib_port_vlan_del(&priv->lib_priv, port, vlan);
}
static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,
@@ -2055,60 +1313,16 @@ static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,
bool ingress, struct netlink_ext_ack *extack)
{
struct mt7530_priv *priv = ds->priv;
- int monitor_port;
- u32 val;
-
- /* Check for existent entry */
- if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port))
- return -EEXIST;
-
- regmap_read(priv->regmap, MT753X_MIRROR_REG(priv->id), &val);
-
- /* MT7530 only supports one monitor port */
- monitor_port = MT753X_MIRROR_PORT_GET(priv->id, val);
- if (val & MT753X_MIRROR_EN(priv->id) &&
- monitor_port != mirror->to_local_port)
- return -EEXIST;
-
- val |= MT753X_MIRROR_EN(priv->id);
- val &= ~MT753X_MIRROR_PORT_MASK(priv->id);
- val |= MT753X_MIRROR_PORT_SET(priv->id, mirror->to_local_port);
- regmap_write(priv->regmap, MT753X_MIRROR_REG(priv->id), val);
- regmap_read(priv->regmap, MT7530_PCR_P(port), &val);
- if (ingress) {
- val |= PORT_RX_MIR;
- priv->mirror_rx |= BIT(port);
- } else {
- val |= PORT_TX_MIR;
- priv->mirror_tx |= BIT(port);
- }
- regmap_write(priv->regmap, MT7530_PCR_P(port), val);
-
- return 0;
+ return mt7530_lib_port_mirror_add(&priv->lib_priv, port, mirror, ingress, extack);
}
static void mt753x_port_mirror_del(struct dsa_switch *ds, int port,
struct dsa_mall_mirror_tc_entry *mirror)
{
struct mt7530_priv *priv = ds->priv;
- u32 val;
- regmap_read(priv->regmap, MT7530_PCR_P(port), &val);
- if (mirror->ingress) {
- val &= ~PORT_RX_MIR;
- priv->mirror_rx &= ~BIT(port);
- } else {
- val &= ~PORT_TX_MIR;
- priv->mirror_tx &= ~BIT(port);
- }
- regmap_write(priv->regmap, MT7530_PCR_P(port), val);
-
- if (!priv->mirror_rx && !priv->mirror_tx) {
- regmap_read(priv->regmap, MT753X_MIRROR_REG(priv->id), &val);
- val &= ~MT753X_MIRROR_EN(priv->id);
- regmap_write(priv->regmap, MT753X_MIRROR_REG(priv->id), val);
- }
+ mt7530_lib_port_mirror_del(&priv->lib_priv, port, mirror);
}
static enum dsa_tag_protocol
@@ -2486,10 +1700,10 @@ mt7530_setup(struct dsa_switch *ds)
if ((val & MT7530_XTAL_MASK) == MT7530_XTAL_40MHZ)
mt7530_pll_setup(priv);
- mt753x_trap_frames(priv);
+ mt7530_lib_trap_frames(&priv->lib_priv);
/* Enable and reset MIB counters */
- mt7530_mib_reset(ds);
+ mt7530_lib_mib_reset(&priv->lib_priv);
for (i = 0; i < priv->ds->num_ports; i++) {
/* Clear link settings and enable force mode to force link down
@@ -2513,7 +1727,8 @@ mt7530_setup(struct dsa_switch *ds)
/* Set default PVID to 0 on all user ports */
regmap_update_bits(priv->regmap, MT7530_PPBV1_P(i),
- G0_PORT_VID_MASK, G0_PORT_VID_DEF);
+ G0_PORT_VID_MASK,
+ G0_PORT_VID(G0_PORT_VID_DEF));
}
/* Enable consistent egress tag */
regmap_update_bits(priv->regmap, MT7530_PVC_P(i),
@@ -2525,7 +1740,7 @@ mt7530_setup(struct dsa_switch *ds)
regmap_set_bits(priv->regmap, MT753X_AGC, LOCAL_EN);
/* Setup VLAN ID 0 for VLAN-unaware bridges */
- ret = mt7530_setup_vlan0(priv);
+ ret = mt7530_lib_setup_vlan0(&priv->lib_priv);
if (ret)
return ret;
@@ -2584,7 +1799,8 @@ mt7530_setup(struct dsa_switch *ds)
#endif /* CONFIG_GPIOLIB */
/* Flush the FDB table */
- ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
+ ret = mt7530_lib_fdb_cmd(&priv->lib_priv, MT7530_FDB_FLUSH,
+ ATC_MAT_MACTAB, NULL);
if (ret < 0)
return ret;
@@ -2603,10 +1819,10 @@ mt7531_setup_common(struct dsa_switch *ds)
ds->ageing_time_min = 2 * 1000;
ds->ageing_time_max = (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1) * 1000;
- mt753x_trap_frames(priv);
+ mt7530_lib_trap_frames(&priv->lib_priv);
/* Enable and reset MIB counters */
- mt7530_mib_reset(ds);
+ mt7530_lib_mib_reset(&priv->lib_priv);
/* Disable flooding on all ports */
regmap_clear_bits(priv->regmap, MT753X_MFC,
@@ -2637,7 +1853,8 @@ mt7531_setup_common(struct dsa_switch *ds)
/* Set default PVID to 0 on all user ports */
regmap_update_bits(priv->regmap, MT7530_PPBV1_P(i),
- G0_PORT_VID_MASK, G0_PORT_VID_DEF);
+ G0_PORT_VID_MASK,
+ G0_PORT_VID(G0_PORT_VID_DEF));
}
/* Enable consistent egress tag */
@@ -2655,12 +1872,13 @@ mt7531_setup_common(struct dsa_switch *ds)
CPORT_SW2FE_STAG_EN | CPORT_FE2SW_STAG_EN);
/* Flush the FDB table */
- ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
+ ret = mt7530_lib_fdb_cmd(&priv->lib_priv, MT7530_FDB_FLUSH,
+ ATC_MAT_MACTAB, NULL);
if (ret < 0)
return ret;
/* Setup VLAN ID 0 for VLAN-unaware bridges */
- return mt7530_setup_vlan0(priv);
+ return mt7530_lib_setup_vlan0(&priv->lib_priv);
}
static int
@@ -3275,11 +2493,12 @@ mt753x_port_change_conduit(struct dsa_switch *ds, int port,
mutex_lock(&priv->reg_mutex);
/* dp->cpu_dp still points to the old CPU port */
- priv->ports[port].pm &= ~PCR_MATRIX(BIT(dp->cpu_dp->index));
- priv->ports[port].pm |= PCR_MATRIX(BIT(new_cpu_dp->index));
+ priv->ports[port].pm &= ~BIT(dp->cpu_dp->index);
+ priv->ports[port].pm |= BIT(new_cpu_dp->index);
if (priv->ports[port].enable)
regmap_update_bits(priv->regmap, MT7530_PCR_P(port),
- PCR_MATRIX_MASK, priv->ports[port].pm);
+ PCR_MATRIX_MASK,
+ PCR_MATRIX(priv->ports[port].pm));
mutex_unlock(&priv->reg_mutex);
@@ -3450,6 +2669,8 @@ static const struct phylink_mac_ops mt753x_phylink_mac_ops = {
const struct mt753x_info mt753x_table[] = {
[ID_MT7621] = {
.id = ID_MT7621,
+ .reg_fields = mt7530_fields,
+ .num_reg_fields = ARRAY_SIZE(mt7530_fields),
.pcs_ops = &mt7530_pcs_ops,
.sw_setup = mt7530_setup,
.phy_read_c22 = mt7530_phy_read_c22,
@@ -3461,6 +2682,8 @@ const struct mt753x_info mt753x_table[] = {
},
[ID_MT7530] = {
.id = ID_MT7530,
+ .reg_fields = mt7530_fields,
+ .num_reg_fields = ARRAY_SIZE(mt7530_fields),
.pcs_ops = &mt7530_pcs_ops,
.sw_setup = mt7530_setup,
.phy_read_c22 = mt7530_phy_read_c22,
@@ -3472,6 +2695,8 @@ const struct mt753x_info mt753x_table[] = {
},
[ID_MT7531] = {
.id = ID_MT7531,
+ .reg_fields = mt7531_fields,
+ .num_reg_fields = ARRAY_SIZE(mt7531_fields),
.pcs_ops = &mt7530_pcs_ops,
.sw_setup = mt7531_setup,
.phy_read_c22 = mt7531_ind_c22_phy_read,
@@ -3483,6 +2708,8 @@ const struct mt753x_info mt753x_table[] = {
},
[ID_MT7988] = {
.id = ID_MT7988,
+ .reg_fields = mt7531_fields,
+ .num_reg_fields = ARRAY_SIZE(mt7531_fields),
.pcs_ops = &mt7530_pcs_ops,
.sw_setup = mt7988_setup,
.phy_read_c22 = mt7531_ind_c22_phy_read,
@@ -3493,6 +2720,8 @@ const struct mt753x_info mt753x_table[] = {
},
[ID_EN7581] = {
.id = ID_EN7581,
+ .reg_fields = mt7531_fields,
+ .num_reg_fields = ARRAY_SIZE(mt7531_fields),
.pcs_ops = &mt7530_pcs_ops,
.sw_setup = mt7988_setup,
.phy_read_c22 = mt7531_ind_c22_phy_read,
@@ -3503,6 +2732,8 @@ const struct mt753x_info mt753x_table[] = {
},
[ID_AN7583] = {
.id = ID_AN7583,
+ .reg_fields = mt7531_fields,
+ .num_reg_fields = ARRAY_SIZE(mt7531_fields),
.pcs_ops = &mt7530_pcs_ops,
.sw_setup = mt7988_setup,
.phy_read_c22 = mt7531_ind_c22_phy_read,
@@ -3513,6 +2744,8 @@ const struct mt753x_info mt753x_table[] = {
},
[ID_EN7528] = {
.id = ID_EN7528,
+ .reg_fields = mt7531_fields,
+ .num_reg_fields = ARRAY_SIZE(mt7531_fields),
.pcs_ops = &mt7530_pcs_ops,
.sw_setup = mt7988_setup,
.phy_read_c22 = mt7531_ind_c22_phy_read,
@@ -3567,6 +2800,47 @@ mt7530_remove_common(struct mt7530_priv *priv)
}
EXPORT_SYMBOL_GPL(mt7530_remove_common);
+int mt7530_setup_lib_priv(struct mt7530_priv *priv)
+{
+ struct mt7530_lib_priv *lib_priv = &priv->lib_priv;
+ int i;
+
+ lib_priv->dev = priv->dev;
+ lib_priv->ds = priv->ds;
+ lib_priv->regmap = priv->regmap;
+ lib_priv->ports = priv->ports;
+ lib_priv->reg_mutex = &priv->reg_mutex;
+
+ for (i = 0; i < ARRAY_SIZE(mt753x_fields); i++) {
+ const struct mt7530_reg_field *reg_field;
+ struct regmap_field *field;
+
+ reg_field = &mt753x_fields[i];
+ field = devm_regmap_field_alloc(priv->dev, priv->regmap,
+ reg_field->field);
+ if (IS_ERR(field))
+ return PTR_ERR(field);
+
+ lib_priv->fields[reg_field->id] = field;
+ }
+
+ for (i = 0; i < priv->info->num_reg_fields; i++) {
+ const struct mt7530_reg_field *reg_field;
+ struct regmap_field *field;
+
+ reg_field = &priv->info->reg_fields[i];
+ field = devm_regmap_field_alloc(priv->dev, priv->regmap,
+ reg_field->field);
+ if (IS_ERR(field))
+ return PTR_ERR(field);
+
+ lib_priv->fields[reg_field->id] = field;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(mt7530_setup_lib_priv);
+
MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch");
MODULE_LICENSE("GPL");
diff --git a/drivers/net/dsa/mediatek/mt7530.h b/drivers/net/dsa/mediatek/mt7530.h
index 2bbbe617b52e..50a12e10893d 100644
--- a/drivers/net/dsa/mediatek/mt7530.h
+++ b/drivers/net/dsa/mediatek/mt7530.h
@@ -7,14 +7,11 @@
#define __MT7530_H
#include <linux/bitfield.h>
+#include "mt7530-lib.h"
#define MT7530_NUM_PORTS 7
#define MT7530_NUM_PHYS 5
#define MT7530_NUM_FDB_RECORDS 2048
-#define MT7530_ALL_MEMBERS 0xff
-
-#define MTK_HDR_LEN 4
-#define MT7530_MAX_MTU (15 * 1024 - ETH_HLEN - ETH_FCS_LEN - MTK_HDR_LEN)
enum mt753x_id {
ID_MT7530 = 0,
@@ -135,18 +132,8 @@ enum mt753x_id {
#define R03_EG_TAG(x) FIELD_PREP(R03_EG_TAG_MASK, x)
#define R03_PORT_FW_MASK GENMASK(2, 0)
-enum mt753x_to_cpu_fw {
- TO_CPU_FW_SYSTEM_DEFAULT,
- TO_CPU_FW_CPU_EXCLUDE = 4,
- TO_CPU_FW_CPU_INCLUDE = 5,
- TO_CPU_FW_CPU_ONLY = 6,
- TO_CPU_FW_DROP = 7,
-};
-
/* Registers for address table access */
#define MT7530_ATA1 0x74
-#define STATIC_EMP 0
-#define STATIC_ENT 3
#define MT7530_ATA2 0x78
#define ATA2_IVL BIT(15)
#define ATA2_FID_MASK GENMASK(14, 12)
@@ -165,16 +152,6 @@ enum mt753x_to_cpu_fw {
#define ATC_INVALID BIT(12)
#define ATC_MAT_MASK GENMASK(11, 8)
#define ATC_MAT(x) FIELD_PREP(ATC_MAT_MASK, x)
-#define ATC_MAT_MACTAB ATC_MAT(0)
-#define ATC_MAT_NON_STATIC_MAC ATC_MAT(4)
-
-enum mt7530_fdb_cmd {
- MT7530_FDB_READ = 0,
- MT7530_FDB_WRITE = 1,
- MT7530_FDB_FLUSH = 2,
- MT7530_FDB_START = 4,
- MT7530_FDB_NEXT = 5,
-};
/* Registers for table search read address */
#define MT7530_TSRA1 0x84
@@ -202,14 +179,6 @@ enum mt7530_fdb_cmd {
#define VTCR_VID_MASK GENMASK(11, 0)
#define VTCR_VID(x) FIELD_PREP(VTCR_VID_MASK, x)
-enum mt7530_vlan_cmd {
- /* Read/Write the specified VID entry from VAWD register based
- * on VID.
- */
- MT7530_VTCR_RD_VID = 0,
- MT7530_VTCR_WR_VID = 1,
-};
-
/* Register for setup vlan and acl write data */
#define MT7530_VAWD1 0x94
#define PORT_STAG BIT(31)
@@ -228,21 +197,7 @@ enum mt7530_vlan_cmd {
/* VLAN Entry Valid */
#define VLAN_VALID BIT(0)
-enum mt7530_fid {
- FID_STANDALONE = 0,
- FID_BRIDGED = 1,
-};
-
#define MT7530_VAWD2 0x98
-/* Egress Tag Control */
-#define ETAG_CTRL_P(p, x) (((x) & 0x3) << ((p) << 1))
-#define ETAG_CTRL_P_MASK(p) ETAG_CTRL_P(p, 3)
-
-enum mt7530_vlan_egress_attr {
- MT7530_VLAN_EGRESS_UNTAG = 0,
- MT7530_VLAN_EGRESS_TAG = 2,
- MT7530_VLAN_EGRESS_STACK = 3,
-};
/* Register for address age control */
#define MT7530_AAC 0xa0
@@ -270,40 +225,16 @@ enum mt7530_vlan_egress_attr {
#define EGR_BC_CRC_IPG_PREAMBLE 0x18 /* crc + ipg + preamble */
/* Register for port STP state control */
-#define MT7530_SSP_P(x) (0x2000 + ((x) * 0x100))
-#define FID_PST(fid, state) (((state) & 0x3) << ((fid) * 2))
-#define FID_PST_MASK(fid) FID_PST(fid, 0x3)
-
-enum mt7530_stp_state {
- MT7530_STP_DISABLED = 0,
- MT7530_STP_BLOCKING = 1,
- MT7530_STP_LISTENING = 1,
- MT7530_STP_LEARNING = 2,
- MT7530_STP_FORWARDING = 3
-};
+#define MT7530_SSP 0x2000
+#define MT7530_SSP_P(x) (MT7530_SSP + ((x) * 0x100))
/* Register for port control */
-#define MT7530_PCR_P(x) (0x2004 + ((x) * 0x100))
+#define MT7530_PCR 0x2004
+#define MT7530_PCR_P(x) (MT7530_PCR + ((x) * 0x100))
#define PORT_TX_MIR BIT(9)
#define PORT_RX_MIR BIT(8)
#define PCR_PORT_VLAN_MASK GENMASK(1, 0)
-enum mt7530_port_mode {
- /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */
- MT7530_PORT_MATRIX_MODE = 0,
-
- /* Fallback Mode: Forward received frames with ingress ports that do
- * not belong to the VLAN member. Frames whose VID is not listed on
- * the VLAN table are forwarded by the PCR_MATRIX members.
- */
- MT7530_PORT_FALLBACK_MODE = 1,
-
- /* Security Mode: Discard any frame due to ingress membership
- * violation or VID missed on the VLAN table.
- */
- MT7530_PORT_SECURITY_MODE = 3,
-};
-
#define PCR_MATRIX_MASK GENMASK(23, 16)
#define PCR_MATRIX(x) FIELD_PREP(PCR_MATRIX_MASK, x)
#define PORT_PRI_MASK GENMASK(26, 24)
@@ -313,11 +244,13 @@ enum mt7530_port_mode {
#define PCR_MATRIX_CLR PCR_MATRIX(0)
/* Register for port security control */
-#define MT7530_PSC_P(x) (0x200c + ((x) * 0x100))
+#define MT7530_PSC 0x200c
+#define MT7530_PSC_P(x) (MT7530_PSC + ((x) * 0x100))
#define SA_DIS BIT(4)
/* Register for port vlan control */
-#define MT7530_PVC_P(x) (0x2010 + ((x) * 0x100))
+#define MT7530_PVC 0x2010
+#define MT7530_PVC_P(x) (MT7530_PVC + ((x) * 0x100))
#define PORT_SPEC_TAG BIT(5)
#define PVC_EG_TAG_MASK GENMASK(10, 8)
#define PVC_EG_TAG(x) FIELD_PREP(PVC_EG_TAG_MASK, x)
@@ -325,31 +258,14 @@ enum mt7530_port_mode {
#define VLAN_ATTR(x) FIELD_PREP(VLAN_ATTR_MASK, x)
#define ACC_FRM_MASK GENMASK(1, 0)
-enum mt7530_vlan_port_eg_tag {
- MT7530_VLAN_EG_DISABLED = 0,
- MT7530_VLAN_EG_CONSISTENT = 1,
- MT7530_VLAN_EG_UNTAGGED = 4,
-};
-
-enum mt7530_vlan_port_attr {
- MT7530_VLAN_USER = 0,
- MT7530_VLAN_TRANSPARENT = 3,
-};
-
-enum mt7530_vlan_port_acc_frm {
- MT7530_VLAN_ACC_ALL = 0,
- MT7530_VLAN_ACC_TAGGED = 1,
- MT7530_VLAN_ACC_UNTAGGED = 2,
-};
-
#define STAG_VPID_MASK GENMASK(31, 16)
#define STAG_VPID(x) FIELD_PREP(STAG_VPID_MASK, x)
/* Register for port port-and-protocol based vlan 1 control */
+#define MT7530_PPBV1 0x2014
#define MT7530_PPBV1_P(x) (0x2014 + ((x) * 0x100))
#define G0_PORT_VID_MASK GENMASK(11, 0)
#define G0_PORT_VID(x) FIELD_PREP(G0_PORT_VID_MASK, x)
-#define G0_PORT_VID_DEF G0_PORT_VID(0)
/* Register for port MAC control register */
#define MT753X_PMCR_P(x) (0x3000 + ((x) * 0x100))
@@ -427,55 +343,54 @@ enum mt7530_vlan_port_acc_frm {
#define MAX_RX_JUMBO_MASK GENMASK(5, 2)
#define MAX_RX_JUMBO(x) FIELD_PREP(MAX_RX_JUMBO_MASK, x)
#define MAX_RX_PKT_LEN_MASK GENMASK(1, 0)
-#define MAX_RX_PKT_LEN_1522 0x0
-#define MAX_RX_PKT_LEN_1536 0x1
-#define MAX_RX_PKT_LEN_1552 0x2
-#define MAX_RX_PKT_LEN_JUMBO 0x3
/* Register for MIB */
-#define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100)
+#define MT7530_MIB_COUNTER 0x4000
+#define MT7530_PORT_MIB_COUNTER(x) (MT7530_MIB_COUNTER + (x) * 0x100)
/* Each define is an offset of MT7530_PORT_MIB_COUNTER */
-#define MT7530_PORT_MIB_TX_DROP 0x00
-#define MT7530_PORT_MIB_TX_CRC_ERR 0x04
-#define MT7530_PORT_MIB_TX_UNICAST 0x08
-#define MT7530_PORT_MIB_TX_MULTICAST 0x0c
-#define MT7530_PORT_MIB_TX_BROADCAST 0x10
-#define MT7530_PORT_MIB_TX_COLLISION 0x14
-#define MT7530_PORT_MIB_TX_SINGLE_COLLISION 0x18
-#define MT7530_PORT_MIB_TX_MULTIPLE_COLLISION 0x1c
-#define MT7530_PORT_MIB_TX_DEFERRED 0x20
-#define MT7530_PORT_MIB_TX_LATE_COLLISION 0x24
-#define MT7530_PORT_MIB_TX_EXCESSIVE_COLLISION 0x28
-#define MT7530_PORT_MIB_TX_PAUSE 0x2c
-#define MT7530_PORT_MIB_TX_PKT_SZ_64 0x30
-#define MT7530_PORT_MIB_TX_PKT_SZ_65_TO_127 0x34
-#define MT7530_PORT_MIB_TX_PKT_SZ_128_TO_255 0x38
-#define MT7530_PORT_MIB_TX_PKT_SZ_256_TO_511 0x3c
-#define MT7530_PORT_MIB_TX_PKT_SZ_512_TO_1023 0x40
-#define MT7530_PORT_MIB_TX_PKT_SZ_1024_TO_MAX 0x44
-#define MT7530_PORT_MIB_TX_BYTES 0x48 /* 64 bytes */
-#define MT7530_PORT_MIB_RX_DROP 0x60
-#define MT7530_PORT_MIB_RX_FILTERING 0x64
-#define MT7530_PORT_MIB_RX_UNICAST 0x68
-#define MT7530_PORT_MIB_RX_MULTICAST 0x6c
-#define MT7530_PORT_MIB_RX_BROADCAST 0x70
-#define MT7530_PORT_MIB_RX_ALIGN_ERR 0x74
-#define MT7530_PORT_MIB_RX_CRC_ERR 0x78
-#define MT7530_PORT_MIB_RX_UNDER_SIZE_ERR 0x7c
-#define MT7530_PORT_MIB_RX_FRAG_ERR 0x80
-#define MT7530_PORT_MIB_RX_OVER_SZ_ERR 0x84
-#define MT7530_PORT_MIB_RX_JABBER_ERR 0x88
-#define MT7530_PORT_MIB_RX_PAUSE 0x8c
-#define MT7530_PORT_MIB_RX_PKT_SZ_64 0x90
-#define MT7530_PORT_MIB_RX_PKT_SZ_65_TO_127 0x94
-#define MT7530_PORT_MIB_RX_PKT_SZ_128_TO_255 0x98
-#define MT7530_PORT_MIB_RX_PKT_SZ_256_TO_511 0x9c
-#define MT7530_PORT_MIB_RX_PKT_SZ_512_TO_1023 0xa0
-#define MT7530_PORT_MIB_RX_PKT_SZ_1024_TO_MAX 0xa4
-#define MT7530_PORT_MIB_RX_BYTES 0xa8 /* 64 bytes */
-#define MT7530_PORT_MIB_RX_CTRL_DROP 0xb0
-#define MT7530_PORT_MIB_RX_INGRESS_DROP 0xb4
-#define MT7530_PORT_MIB_RX_ARL_DROP 0xb8
+#define MT7530_PORT_MIB_TX_DROP (MT7530_MIB_COUNTER + 0x00)
+#define MT7530_PORT_MIB_TX_CRC_ERR (MT7530_MIB_COUNTER + 0x04)
+#define MT7530_PORT_MIB_TX_UNICAST (MT7530_MIB_COUNTER + 0x08)
+#define MT7530_PORT_MIB_TX_MULTICAST (MT7530_MIB_COUNTER + 0x0c)
+#define MT7530_PORT_MIB_TX_BROADCAST (MT7530_MIB_COUNTER + 0x10)
+#define MT7530_PORT_MIB_TX_COLLISION (MT7530_MIB_COUNTER + 0x14)
+#define MT7530_PORT_MIB_TX_SINGLE_COLLISION (MT7530_MIB_COUNTER + 0x18)
+#define MT7530_PORT_MIB_TX_MULTIPLE_COLLISION (MT7530_MIB_COUNTER + 0x1c)
+#define MT7530_PORT_MIB_TX_DEFERRED (MT7530_MIB_COUNTER + 0x20)
+#define MT7530_PORT_MIB_TX_LATE_COLLISION (MT7530_MIB_COUNTER + 0x24)
+#define MT7530_PORT_MIB_TX_EXCESSIVE_COLLISION (MT7530_MIB_COUNTER + 0x28)
+#define MT7530_PORT_MIB_TX_PAUSE (MT7530_MIB_COUNTER + 0x2c)
+#define MT7530_PORT_MIB_TX_PKT_SZ_64 (MT7530_MIB_COUNTER + 0x30)
+#define MT7530_PORT_MIB_TX_PKT_SZ_65_TO_127 (MT7530_MIB_COUNTER + 0x34)
+#define MT7530_PORT_MIB_TX_PKT_SZ_128_TO_255 (MT7530_MIB_COUNTER + 0x38)
+#define MT7530_PORT_MIB_TX_PKT_SZ_256_TO_511 (MT7530_MIB_COUNTER + 0x3c)
+#define MT7530_PORT_MIB_TX_PKT_SZ_512_TO_1023 (MT7530_MIB_COUNTER + 0x40)
+#define MT7530_PORT_MIB_TX_PKT_SZ_1024_TO_MAX (MT7530_MIB_COUNTER + 0x44)
+#define MT7530_PORT_MIB_TX_BYTES_LOW (MT7530_MIB_COUNTER + 0x48) /* 64 bytes */
+#define MT7530_PORT_MIB_TX_BYTES_HIGH (MT7530_MIB_COUNTER + 0x4c)
+#define MT7530_PORT_MIB_RX_DROP (MT7530_MIB_COUNTER + 0x60)
+#define MT7530_PORT_MIB_RX_FILTERING (MT7530_MIB_COUNTER + 0x64)
+#define MT7530_PORT_MIB_RX_UNICAST (MT7530_MIB_COUNTER + 0x68)
+#define MT7530_PORT_MIB_RX_MULTICAST (MT7530_MIB_COUNTER + 0x6c)
+#define MT7530_PORT_MIB_RX_BROADCAST (MT7530_MIB_COUNTER + 0x70)
+#define MT7530_PORT_MIB_RX_ALIGN_ERR (MT7530_MIB_COUNTER + 0x74)
+#define MT7530_PORT_MIB_RX_CRC_ERR (MT7530_MIB_COUNTER + 0x78)
+#define MT7530_PORT_MIB_RX_UNDER_SIZE_ERR (MT7530_MIB_COUNTER + 0x7c)
+#define MT7530_PORT_MIB_RX_FRAG_ERR (MT7530_MIB_COUNTER + 0x80)
+#define MT7530_PORT_MIB_RX_OVER_SZ_ERR (MT7530_MIB_COUNTER + 0x84)
+#define MT7530_PORT_MIB_RX_JABBER_ERR (MT7530_MIB_COUNTER + 0x88)
+#define MT7530_PORT_MIB_RX_PAUSE (MT7530_MIB_COUNTER + 0x8c)
+#define MT7530_PORT_MIB_RX_PKT_SZ_64 (MT7530_MIB_COUNTER + 0x90)
+#define MT7530_PORT_MIB_RX_PKT_SZ_65_TO_127 (MT7530_MIB_COUNTER + 0x94)
+#define MT7530_PORT_MIB_RX_PKT_SZ_128_TO_255 (MT7530_MIB_COUNTER + 0x98)
+#define MT7530_PORT_MIB_RX_PKT_SZ_256_TO_511 (MT7530_MIB_COUNTER + 0x9c)
+#define MT7530_PORT_MIB_RX_PKT_SZ_512_TO_1023 (MT7530_MIB_COUNTER + 0xa0)
+#define MT7530_PORT_MIB_RX_PKT_SZ_1024_TO_MAX (MT7530_MIB_COUNTER + 0xa4)
+#define MT7530_PORT_MIB_RX_BYTES_LOW (MT7530_MIB_COUNTER + 0xa8) /* 64 bytes */
+#define MT7530_PORT_MIB_RX_BYTES_HIGH (MT7530_MIB_COUNTER + 0xac)
+#define MT7530_PORT_MIB_RX_CTRL_DROP (MT7530_MIB_COUNTER + 0xb0)
+#define MT7530_PORT_MIB_RX_INGRESS_DROP (MT7530_MIB_COUNTER + 0xb4)
+#define MT7530_PORT_MIB_RX_ARL_DROP (MT7530_MIB_COUNTER + 0xb8)
#define MT7530_MIB_CCR 0x4fe0
#define CCR_MIB_ENABLE BIT(31)
#define CCR_RX_OCT_CNT_GOOD BIT(7)
@@ -794,45 +709,6 @@ enum mt7531_xtal_fsel {
#define REG_GSWCK_EN BIT(0)
#define REG_TRGMIICK_EN BIT(1)
-#define MIB_DESC(_s, _o, _n) \
- { \
- .size = (_s), \
- .offset = (_o), \
- .name = (_n), \
- }
-
-struct mt7530_mib_desc {
- unsigned int size;
- unsigned int offset;
- const char *name;
-};
-
-struct mt7530_fdb {
- u16 vid;
- u8 port_mask;
- u8 aging;
- u8 mac[6];
- bool noarp;
-};
-
-/* struct mt7530_port - This is the main data structure for holding the state
- * of the port.
- * @enable: The status used for show port is enabled or not.
- * @pm: The matrix used to show all connections with the port.
- * @pvid: The VLAN specified is to be considered a PVID at ingress. Any
- * untagged frames will be assigned to the related VLAN.
- * @sgmii_pcs: Pointer to PCS instance for SerDes ports
- * @stats: Cached port statistics for MDIO-connected switches
- */
-struct mt7530_port {
- bool enable;
- bool isolated;
- u32 pm;
- u16 pvid;
- struct phylink_pcs *sgmii_pcs;
- struct rtnl_link_stats64 stats;
-};
-
/* Port 5 mode definitions of the MT7530 switch */
enum mt7530_p5_mode {
GMAC5,
@@ -864,6 +740,9 @@ struct mt753x_pcs {
struct mt753x_info {
enum mt753x_id id;
+ const struct mt7530_reg_field *reg_fields;
+ unsigned int num_reg_fields;
+
const struct phylink_pcs_ops *pcs_ops;
int (*sw_setup)(struct dsa_switch *ds);
@@ -921,8 +800,6 @@ struct mt7530_priv {
bool mcm;
enum mt7530_p5_mode p5_mode;
bool p5_sgmii;
- u8 mirror_rx;
- u8 mirror_tx;
struct mt7530_port ports[MT7530_NUM_PORTS];
struct mt753x_pcs pcs[MT7530_NUM_PORTS];
/* protect among processes for registers access*/
@@ -934,24 +811,10 @@ struct mt7530_priv {
spinlock_t stats_lock; /* protects cached stats counters */
struct delayed_work stats_work;
unsigned long stats_last;
-};
-struct mt7530_hw_vlan_entry {
- int port;
- u8 old_members;
- bool untagged;
+ struct mt7530_lib_priv lib_priv;
};
-static inline void mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry *e,
- int port, bool untagged)
-{
- e->port = port;
- e->untagged = untagged;
-}
-
-typedef void (*mt7530_vlan_op)(struct mt7530_priv *,
- struct mt7530_hw_vlan_entry *);
-
struct mt7530_hw_stats {
const char *string;
u16 reg;
@@ -960,6 +823,7 @@ struct mt7530_hw_stats {
int mt7530_probe_common(struct mt7530_priv *priv);
void mt7530_remove_common(struct mt7530_priv *priv);
+int mt7530_setup_lib_priv(struct mt7530_priv *priv);
extern const struct mt753x_info mt753x_table[];
--
2.55.0
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH net-next v25 10/10] net: dsa: Add Airoha AN8855 5-Port Gigabit DSA Switch driver
2026-10-09 16:10 [PATCH net-next v25 00/10] net: dsa: Add Airoha AN8855 support Christian Marangi
` (8 preceding siblings ...)
2026-10-09 16:10 ` [PATCH net-next v25 09/10] net: dsa: mt7530: generalize and move common function to lib module Christian Marangi
@ 2026-10-09 16:10 ` Christian Marangi
2026-10-10 16:19 ` netdev-bot+sashiko
9 siblings, 1 reply; 18+ messages in thread
From: Christian Marangi @ 2026-10-09 16:10 UTC (permalink / raw)
To: Christian Marangi, Lee Jones, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Andrew Lunn, David S. Miller, Eric Dumazet,
Jakub Kicinski, Paolo Abeni, Vladimir Oltean, Matthias Brugger,
AngeloGioacchino Del Regno, Chester A. Unal, Daniel Golle,
Heiner Kallweit, Russell King, Simon Horman, Joris Vaisvila,
linux-arm-kernel, linux-mediatek, netdev, mfd, devicetree,
linux-kernel
Cc: Andrew Lunn
Add Airoha AN8855 5-Port Gigabit DSA switch. Switch can support
10M, 100M, 1Gb, 2.5G and 5G Ethernet Speed but 5G is currently error out
as it's not currently supported as requires additional configuration for
the PCS.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
---
drivers/net/dsa/mediatek/Kconfig | 10 +
drivers/net/dsa/mediatek/Makefile | 1 +
drivers/net/dsa/mediatek/an8855.c | 1765 +++++++++++++++++++++++++
drivers/net/dsa/mediatek/an8855.h | 755 +++++++++++
drivers/net/dsa/mediatek/mt7530-lib.c | 68 +-
drivers/net/dsa/mediatek/mt7530-lib.h | 22 +
6 files changed, 2601 insertions(+), 20 deletions(-)
create mode 100644 drivers/net/dsa/mediatek/an8855.c
create mode 100644 drivers/net/dsa/mediatek/an8855.h
diff --git a/drivers/net/dsa/mediatek/Kconfig b/drivers/net/dsa/mediatek/Kconfig
index 7b48300dca0c..2799e78a8651 100644
--- a/drivers/net/dsa/mediatek/Kconfig
+++ b/drivers/net/dsa/mediatek/Kconfig
@@ -1,4 +1,14 @@
# SPDX-License-Identifier: GPL-2.0-only
+config NET_DSA_AN8855
+ tristate "Airoha AN8855 Ethernet switch support"
+ depends on MFD_AIROHA_AN8855 || COMPILE_TEST
+ depends on NET_DSA
+ select NET_DSA_MT7530_LIB
+ select NET_DSA_TAG_AIROHA
+ help
+ This enables support for the Ethernet switch inside the
+ Airoha AN8855 chip.
+
config NET_DSA_MT7530_LIB
tristate
diff --git a/drivers/net/dsa/mediatek/Makefile b/drivers/net/dsa/mediatek/Makefile
index b2c0693dbb58..60e5f5cd0901 100644
--- a/drivers/net/dsa/mediatek/Makefile
+++ b/drivers/net/dsa/mediatek/Makefile
@@ -1,4 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
+obj-$(CONFIG_NET_DSA_AN8855) += an8855.o
obj-$(CONFIG_NET_DSA_MT7530) += mt7530.o
obj-$(CONFIG_NET_DSA_MT7530_LIB) += mt7530-lib.o
obj-$(CONFIG_NET_DSA_MT7530_MDIO) += mt7530-mdio.o
diff --git a/drivers/net/dsa/mediatek/an8855.c b/drivers/net/dsa/mediatek/an8855.c
new file mode 100644
index 000000000000..22171cd885c7
--- /dev/null
+++ b/drivers/net/dsa/mediatek/an8855.c
@@ -0,0 +1,1765 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Airoha AN8855 DSA Switch driver
+ * Copyright (C) 2023 Min Yao <min.yao@airoha.com>
+ * Copyright (C) 2024 Christian Marangi <ansuelsmth@gmail.com>
+ */
+#include <linux/bitfield.h>
+#include <linux/ethtool.h>
+#include <linux/etherdevice.h>
+#include <linux/if_bridge.h>
+#include <linux/iopoll.h>
+#include <linux/netdevice.h>
+#include <linux/of_net.h>
+#include <linux/of_platform.h>
+#include <linux/phylink.h>
+#include <linux/platform_device.h>
+#include <linux/regmap.h>
+#include <net/dsa.h>
+
+#include "an8855.h"
+#include "mt7530-lib.h"
+
+static const struct mt7530_reg_field an8855_fields[] = {
+ { MT7530_BC_FFP, REG_FIELD(AN8855_BCF, 0, 7) },
+ { MT7530_UNM_FFP, REG_FIELD(AN8855_UNMF, 0, 7) },
+ { MT7530_UNU_FFP, REG_FIELD(AN8855_UNUF, 0, 7) },
+
+ { MT7530_CCR_MIB_ENABLE, REG_FIELD(AN8855_MIB_CCR, 31, 31) },
+ { MT7530_CCR_RX_OCT_CNT_GOOD, REG_FIELD(AN8855_MIB_CCR, 7, 7) },
+ { MT7530_CCR_RX_OCT_CNT_BAD, REG_FIELD(AN8855_MIB_CCR, 6, 6) },
+ { MT7530_CCR_TX_OCT_CNT_GOOD, REG_FIELD(AN8855_MIB_CCR, 5, 5) },
+ { MT7530_CCR_TX_OCT_CNT_BAD, REG_FIELD(AN8855_MIB_CCR, 4, 4) },
+
+ { MT7530_BPDU_EG_TAG, REG_FIELD(AN8855_BPC, 9, 11) },
+ { MT7530_BPDU_PORT_FW, REG_FIELD(AN8855_BPC, 0, 2) },
+ { MT7530_PAE_BPDU_FR, REG_FIELD(AN8855_PAC, 28, 28) },
+ { MT7530_PAE_EG_TAG, REG_FIELD(AN8855_PAC, 25, 27) },
+ { MT7530_PAE_PORT_FW, REG_FIELD(AN8855_PAC, 16, 18) },
+ { MT7530_R01_BPDU_FR, REG_FIELD(AN8855_RGAC1, 12, 12) },
+ { MT7530_R01_EG_TAG, REG_FIELD(AN8855_RGAC1, 9, 11) },
+ { MT7530_R01_PORT_FW, REG_FIELD(AN8855_RGAC1, 0, 2) },
+ { MT7530_R02_BPDU_FR, REG_FIELD(AN8855_RGAC1, 28, 28) },
+ { MT7530_R02_EG_TAG, REG_FIELD(AN8855_RGAC1, 25, 27) },
+ { MT7530_R02_PORT_FW, REG_FIELD(AN8855_RGAC1, 16, 18) },
+ { MT7530_R03_BPDU_FR, REG_FIELD(AN8855_RGAC2, 12, 12) },
+ { MT7530_R03_EG_TAG, REG_FIELD(AN8855_RGAC2, 9, 11) },
+ { MT7530_R03_PORT_FW, REG_FIELD(AN8855_RGAC2, 0, 2) },
+ { MT7530_R0E_BPDU_FR, REG_FIELD(AN8855_RGAC2, 28, 28) },
+ { MT7530_R0E_EG_TAG, REG_FIELD(AN8855_RGAC2, 25, 27) },
+ { MT7530_R0E_PORT_FW, REG_FIELD(AN8855_RGAC2, 16, 18) },
+
+ { MT7530_VAWD_IVL_MAC, REG_FIELD(AN8855_VAWD0, 5, 5) },
+ { MT7530_VAWD_EG_CON, REG_FIELD(AN8855_VAWD0, 11, 11) },
+ { MT7530_VAWD_VTAG_EN, REG_FIELD(AN8855_VAWD0, 10, 10) },
+ { MT7530_VAWD_PORT_MEM, REG_FIELD(AN8855_VAWD0, 26, 31) },
+ { MT7530_VAWD_FID, REG_FIELD(AN8855_VAWD0, 1, 4) },
+ { MT7530_VAWD_VLAN_VALID, REG_FIELD(AN8855_VAWD0, 0, 0) },
+ { __MT7530_VAWD1, REG_FIELD(AN8855_VAWD0, 0, 31) },
+
+ { MT7530_VAWD_ETAG, REG_FIELD(AN8855_VAWD0, 12, 23) },
+ { __MT7530_VAWD2, REG_FIELD(AN8855_VAWD1, 0, 31) },
+
+ { MT7530_VTCR_BUSY, REG_FIELD(AN8855_VTCR, 31, 31) },
+ { MT7530_VTCR_FUNC, REG_FIELD(AN8855_VTCR, 12, 15) },
+ { MT7530_VTCR_VID, REG_FIELD(AN8855_VTCR, 0, 11) },
+
+ { MT7530_ATWD_CVID, REG_FIELD(AN8855_ATWD, 16, 27), },
+ { MT7530_ATWD_IVL, REG_FIELD(AN8855_ATWD, 15, 15), },
+ { MT7530_ATWD_FID, REG_FIELD(AN8855_ATWD, 28, 31), },
+ { MT7530_ATWD_AGE_TIMER, REG_FIELD(AN8855_ATA2, 0, 8), },
+ { MT7530_ATWD_PORT_MAP, REG_FIELD(AN8855_ATWD2, 0, 7), },
+ { AN8855_ATWD_TYPE, REG_FIELD(AN8855_ATA2, 9, 9), },
+ { AN8855_ATWD_VLD, REG_FIELD(AN8855_ATWD, 0, 0), },
+ { MT7530_ATWD_MAC_BYTE_5, REG_FIELD(AN8855_ATA2, 16, 23), },
+ { MT7530_ATWD_MAC_BYTE_4, REG_FIELD(AN8855_ATA2, 24, 31), },
+ { MT7530_ATWD_MAC_BYTE_3, REG_FIELD(AN8855_ATA1, 0, 7), },
+ { MT7530_ATWD_MAC_BYTE_2, REG_FIELD(AN8855_ATA1, 8, 15), },
+ { MT7530_ATWD_MAC_BYTE_1, REG_FIELD(AN8855_ATA1, 16, 23), },
+ { MT7530_ATWD_MAC_BYTE_0, REG_FIELD(AN8855_ATA1, 24, 31), },
+
+ { __MT7530_ATWD1, REG_FIELD(AN8855_ATWD, 0, 31), },
+ { __MT7530_ATWD2, REG_FIELD(AN8855_ATWD2, 0, 31), },
+ { __MT7530_ATWD3, REG_FIELD(AN8855_ATA1, 0, 31), },
+ { __MT7530_ATWD4, REG_FIELD(AN8855_ATA2, 0, 31), },
+
+ { MT7530_ATRD_CVID, REG_FIELD(AN8855_ATRD0, 10, 21), },
+ { MT7530_ATRD_AGE_TIMER, REG_FIELD(AN8855_ATRD1, 3, 11), },
+ { MT7530_ATRD_PORT_MAP, REG_FIELD(AN8855_ATRD3, 0, 7), },
+ { AN8855_ATRD_ARP, REG_FIELD(AN8855_ATRD0, 1, 2), },
+ { MT7530_ATRD_MAC_BYTE_5, REG_FIELD(AN8855_ATRD1, 16, 23), },
+ { MT7530_ATRD_MAC_BYTE_4, REG_FIELD(AN8855_ATRD1, 24, 31), },
+ { MT7530_ATRD_MAC_BYTE_3, REG_FIELD(AN8855_ATRD2, 0, 7), },
+ { MT7530_ATRD_MAC_BYTE_2, REG_FIELD(AN8855_ATRD2, 8, 15), },
+ { MT7530_ATRD_MAC_BYTE_1, REG_FIELD(AN8855_ATRD2, 16, 23), },
+ { MT7530_ATRD_MAC_BYTE_0, REG_FIELD(AN8855_ATRD2, 24, 31), },
+
+ { MT7530_ATC_BUSY, REG_FIELD(AN8855_ATC, 31, 31), },
+ { MT7530_ATC_MAT, REG_FIELD(AN8855_ATC, 7, 11), },
+ { MT7530_ATC_CMD, REG_FIELD(AN8855_ATC, 0, 2), },
+ { __MT7530_ATC, REG_FIELD(AN8855_ATC, 0, 31), },
+
+ { MT7530_MIRROR_EN, REG_FIELD(AN8855_MIR, 7, 7) },
+ { MT7530_MIRROR_PORT, REG_FIELD(AN8855_MIR, 0, 4) },
+
+ { MT7530_SSP_FID_PST, REG_FIELD_ID(AN8855_SSP, 0, 15, AN8855_NUM_PORTS, 0x200) },
+
+ { MT7530_PCR_PORT_TX_MIR, REG_FIELD_ID(AN8855_PCR, 20, 20, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_PCR_PORT_RX_MIR, REG_FIELD_ID(AN8855_PCR, 16, 16, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_PCR_PORT_VLAN, REG_FIELD_ID(AN8855_PCR, 0, 1, AN8855_NUM_PORTS, 0x200) },
+
+ { MT7530_PCR_MATRIX, REG_FIELD_ID(AN8855_PORTMATRIX, 0, 5, AN8855_NUM_PORTS, 0x200) },
+
+ { MT7530_PSC_SA_DIS, REG_FIELD_ID(AN8855_PSC, 4, 4, AN8855_NUM_PORTS, 0x200) },
+
+ { MT7530_PVC_EG_TAG, REG_FIELD_ID(AN8855_PVC, 8, 10, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_PVC_VLAN_ATTR, REG_FIELD_ID(AN8855_PVC, 6, 7, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_PVC_ACC_FRM, REG_FIELD_ID(AN8855_PVC, 0, 1, AN8855_NUM_PORTS, 0x200) },
+
+ { MT7530_PPBV1_G0_PORT_VID, REG_FIELD_ID(AN8855_PPBV1, 0, 11, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_PVID_G0_PORT_VID, REG_FIELD_ID(AN8855_PVID, 0, 11, AN8855_NUM_PORTS, 0x200) },
+
+ { MT7530_GMACCR_MAX_RX_JUMBO, REG_FIELD(AN8855_GMACCR, 4, 7) },
+ { MT7530_GMACCR_MAX_RX_PKT_LEN, REG_FIELD(AN8855_GMACCR, 0, 1) },
+
+ { MT7530_MIB_TX_DROP, REG_FIELD_ID(AN8855_PORT_MIB_TX_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_CRC_ERR, REG_FIELD_ID(AN8855_PORT_MIB_TX_CRC_ERR, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_UNICAST, REG_FIELD_ID(AN8855_PORT_MIB_TX_UNICAST, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_MULTICAST, REG_FIELD_ID(AN8855_PORT_MIB_TX_MULTICAST, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_BROADCAST, REG_FIELD_ID(AN8855_PORT_MIB_TX_BROADCAST, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_COLLISION, REG_FIELD_ID(AN8855_PORT_MIB_TX_COLLISION, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_SINGLE_COLLISION, REG_FIELD_ID(AN8855_PORT_MIB_TX_SINGLE_COLLISION, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_MULTIPLE_COLLISION, REG_FIELD_ID(AN8855_PORT_MIB_TX_MULTIPLE_COLLISION, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_DEFERRED, REG_FIELD_ID(AN8855_PORT_MIB_TX_DEFERRED, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_LATE_COLLISION, REG_FIELD_ID(AN8855_PORT_MIB_TX_LATE_COLLISION, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_EXCESSIVE_COLLISION, REG_FIELD_ID(AN8855_PORT_MIB_TX_EXCESSIVE_COLLISION, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_PAUSE, REG_FIELD_ID(AN8855_PORT_MIB_TX_PAUSE, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_PKT_SZ_64, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_SZ_64, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_PKT_SZ_65_TO_127, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_SZ_65_TO_127, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_PKT_SZ_128_TO_255, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_SZ_128_TO_255, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_PKT_SZ_256_TO_511, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_SZ_256_TO_511, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_PKT_SZ_512_TO_1023, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_SZ_512_TO_1023, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_TX_PKT_SZ_1024_TO_1518, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_SZ_1024_TO_1518, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_TX_PKT_SZ_1519_TO_MAX, REG_FIELD_ID(AN8855_PORT_MIB_TX_PKT_SZ_1519_TO_MAX, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_BYTES_LOW, REG_FIELD_ID(AN8855_PORT_MIB_TX_BYTES_LOW, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_TX_BYTES_HIGH, REG_FIELD_ID(AN8855_PORT_MIB_TX_BYTES_HIGH, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_TX_OVERSIZE_DROP, REG_FIELD_ID(AN8855_PORT_MIB_TX_OVERSIZE_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_TX_BAD_PKT_BYTES_LOW, REG_FIELD_ID(AN8855_PORT_MIB_TX_BAD_PKT_BYTES_LOW, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_TX_BAD_PKT_BYTES_HIGH, REG_FIELD_ID(AN8855_PORT_MIB_TX_BAD_PKT_BYTES_HIGH, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_DROP, REG_FIELD_ID(AN8855_PORT_MIB_RX_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_FILTERING, REG_FIELD_ID(AN8855_PORT_MIB_RX_FILTERING, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_UNICAST, REG_FIELD_ID(AN8855_PORT_MIB_RX_UNICAST, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_MULTICAST, REG_FIELD_ID(AN8855_PORT_MIB_RX_MULTICAST, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_BROADCAST, REG_FIELD_ID(AN8855_PORT_MIB_RX_BROADCAST, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_ALIGN_ERR, REG_FIELD_ID(AN8855_PORT_MIB_RX_ALIGN_ERR, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_CRC_ERR, REG_FIELD_ID(AN8855_PORT_MIB_RX_CRC_ERR, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_UNDER_SIZE_ERR, REG_FIELD_ID(AN8855_PORT_MIB_RX_UNDER_SIZE_ERR, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_FRAG_ERR, REG_FIELD_ID(AN8855_PORT_MIB_RX_FRAG_ERR, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_OVER_SZ_ERR, REG_FIELD_ID(AN8855_PORT_MIB_RX_OVER_SZ_ERR, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_JABBER_ERR, REG_FIELD_ID(AN8855_PORT_MIB_RX_JABBER_ERR, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_PAUSE, REG_FIELD_ID(AN8855_PORT_MIB_RX_PAUSE, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_PKT_SZ_64, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_SZ_64, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_PKT_SZ_65_TO_127, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_SZ_65_TO_127, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_PKT_SZ_128_TO_255, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_SZ_128_TO_255, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_PKT_SZ_256_TO_511, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_SZ_256_TO_511, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_PKT_SZ_512_TO_1023, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_SZ_512_TO_1023, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_RX_PKT_SZ_1024_TO_1518, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_SZ_1024_TO_1518, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_RX_PKT_SZ_1519_TO_MAX, REG_FIELD_ID(AN8855_PORT_MIB_RX_PKT_SZ_1519_TO_MAX, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_BYTES_LOW, REG_FIELD_ID(AN8855_PORT_MIB_RX_BYTES_LOW, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_BYTES_HIGH, REG_FIELD_ID(AN8855_PORT_MIB_RX_BYTES_HIGH, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_CTRL_DROP, REG_FIELD_ID(AN8855_PORT_MIB_RX_CTRL_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_INGRESS_DROP, REG_FIELD_ID(AN8855_PORT_MIB_RX_INGRESS_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { MT7530_MIB_RX_ARL_DROP, REG_FIELD_ID(AN8855_PORT_MIB_RX_ARL_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_FLOW_CONTROL_DROP, REG_FIELD_ID(AN8855_PORT_MIB_FLOW_CONTROL_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_WRED_DROP, REG_FIELD_ID(AN8855_PORT_MIB_WRED_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_MIRROR_DROP, REG_FIELD_ID(AN8855_PORT_MIB_MIRROR_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_RX_BAD_PKT_BYTES_LOW, REG_FIELD_ID(AN8855_PORT_MIB_RX_BAD_PKT_BYTES_LOW, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_RX_BAD_PKT_BYTES_HIGH, REG_FIELD_ID(AN8855_PORT_MIB_RX_BAD_PKT_BYTES_HIGH, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_RXS_FLOW_SAMPLING_PKT_DROP, REG_FIELD_ID(AN8855_PORT_MIB_RXS_FLOW_SAMPLING_PKT_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_RXS_FLOW_TOTAL_PKT_DROP, REG_FIELD_ID(AN8855_PORT_MIB_RXS_FLOW_TOTAL_PKT_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+ { AN8855_MIB_PORT_CONTROL_DROP, REG_FIELD_ID(AN8855_PORT_MIB_PORT_CONTROL_DROP, 0, 31, AN8855_NUM_PORTS, 0x200) },
+};
+
+static const struct mt7530_mib_desc an8855_mib[] = {
+ MIB_DESC(MT7530_MIB_TX_DROP, -1, "TxDrop"),
+ MIB_DESC(MT7530_MIB_TX_CRC_ERR, -1, "TxCrcErr"),
+ MIB_DESC(MT7530_MIB_TX_COLLISION, -1, "TxCollision"),
+ MIB_DESC(AN8855_MIB_TX_OVERSIZE_DROP, -1, "TxOversizeDrop"),
+ MIB_DESC(AN8855_MIB_TX_BAD_PKT_BYTES_LOW,
+ AN8855_MIB_TX_BAD_PKT_BYTES_HIGH, "TxBadPktBytes"),
+ MIB_DESC(MT7530_MIB_RX_DROP, -1, "RxDrop"),
+ MIB_DESC(MT7530_MIB_RX_FILTERING, -1, "RxFiltering"),
+ MIB_DESC(MT7530_MIB_RX_CRC_ERR, -1, "RxCrcErr"),
+ MIB_DESC(MT7530_MIB_RX_CTRL_DROP, -1, "RxCtrlDrop"),
+ MIB_DESC(MT7530_MIB_RX_INGRESS_DROP, -1, "RxIngressDrop"),
+ MIB_DESC(MT7530_MIB_RX_ARL_DROP, -1, "RxArlDrop"),
+ MIB_DESC(AN8855_MIB_FLOW_CONTROL_DROP, -1, "FlowControlDrop"),
+ MIB_DESC(AN8855_MIB_WRED_DROP, -1, "WredDrop"),
+ MIB_DESC(AN8855_MIB_MIRROR_DROP, -1, "MirrorDrop"),
+ MIB_DESC(AN8855_MIB_RX_BAD_PKT_BYTES_LOW,
+ AN8855_MIB_RX_BAD_PKT_BYTES_HIGH, "RxBadPktBytes"),
+ MIB_DESC(AN8855_MIB_RXS_FLOW_SAMPLING_PKT_DROP, -1, "RxsFlowSamplingPktDrop"),
+ MIB_DESC(AN8855_MIB_RXS_FLOW_TOTAL_PKT_DROP, -1, "RxsFlowTotalPktDrop"),
+ MIB_DESC(AN8855_MIB_PORT_CONTROL_DROP, -1, "PortControlDrop"),
+};
+
+static void
+an8855_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
+{
+ struct dsa_port *dp = dsa_to_port(ds, port);
+ struct an8855_priv *priv = ds->priv;
+ bool learning = false;
+ int ret;
+
+ mt7530_lib_stp_state_set(&priv->lib_priv, port, state);
+
+ switch (state) {
+ case BR_STATE_LEARNING:
+ case BR_STATE_FORWARDING:
+ learning = dp->learning;
+ fallthrough;
+ default:
+ break;
+ }
+
+ ret = regmap_update_bits(priv->regmap, AN8855_PSC_P(port), AN8855_SA_DIS,
+ learning ? 0 : AN8855_SA_DIS);
+ if (ret)
+ dev_err(priv->ds->dev, "failed to update learn reg: %d\n", ret);
+}
+
+static void an8855_port_fast_age(struct dsa_switch *ds, int port)
+{
+ struct an8855_priv *priv = ds->priv;
+ int ret;
+
+ mutex_lock(&priv->reg_mutex);
+
+ /* Set to clean Dynamic entry */
+ ret = regmap_write(priv->regmap, AN8855_ATA2, AN8855_ATA2_TYPE);
+ if (ret) {
+ dev_err(priv->ds->dev, "failed to update ATA2 reg: %d\n", ret);
+ goto exit;
+ }
+
+ /* Set Port */
+ ret = regmap_write(priv->regmap, AN8855_ATWD2,
+ FIELD_PREP(AN8855_ATWD2_PORT, BIT(port)));
+ if (ret) {
+ dev_err(priv->ds->dev, "failed to update ATWD2 reg: %d\n", ret);
+ goto exit;
+ }
+
+ /* Flush Dynamic entry at port */
+ ret = mt7530_lib_fdb_cmd(&priv->lib_priv, MT7530_FDB_FLUSH,
+ AN8855_FDB_MAT_MAC_TYPE_PORT, NULL);
+ if (ret)
+ dev_err(priv->ds->dev, "failed to send FDB cmd: %d\n", ret);
+
+exit:
+ mutex_unlock(&priv->reg_mutex);
+}
+
+static int an8855_port_pre_bridge_flags(struct dsa_switch *ds, int port,
+ struct switchdev_brport_flags flags,
+ struct netlink_ext_ack *extack)
+{
+ if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD |
+ BR_BCAST_FLOOD | BR_ISOLATED))
+ return -EINVAL;
+
+ return 0;
+}
+
+static int an8855_port_bridge_flags(struct dsa_switch *ds, int port,
+ struct switchdev_brport_flags flags,
+ struct netlink_ext_ack *extack)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_port_bridge_flags(&priv->lib_priv, port, flags,
+ extack);
+}
+
+static int an8855_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
+{
+ struct an8855_priv *priv = ds->priv;
+ u32 age_count, age_unit, val;
+
+ /* Convert msec in AN8855_L2_AGING_MS_CONSTANT counter */
+ val = msecs / AN8855_L2_AGING_MS_CONSTANT;
+
+ /* Derive the count unit */
+ age_unit = DIV_ROUND_UP(val, FIELD_MAX(AN8855_AGE_CNT) + 1) - 1;
+ if (age_unit > FIELD_MAX(AN8855_AGE_UNIT))
+ age_unit = FIELD_MAX(AN8855_AGE_UNIT);
+
+ /* Get the count in unit, age_unit is always incremented by 1 internally */
+ age_count = DIV_ROUND_UP(val, age_unit + 1) - 1;
+
+ return regmap_update_bits(priv->regmap, AN8855_AAC,
+ AN8855_AGE_CNT | AN8855_AGE_UNIT,
+ FIELD_PREP(AN8855_AGE_CNT, age_count) |
+ FIELD_PREP(AN8855_AGE_UNIT, age_unit));
+}
+
+static int an8855_port_bridge_join(struct dsa_switch *ds, int port,
+ struct dsa_bridge bridge,
+ bool *tx_fwd_offload,
+ struct netlink_ext_ack *extack)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_port_bridge_join(&priv->lib_priv, port, bridge,
+ tx_fwd_offload, extack);
+}
+
+static void an8855_port_bridge_leave(struct dsa_switch *ds, int port,
+ struct dsa_bridge bridge)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_port_bridge_leave(&priv->lib_priv, port, bridge);
+}
+
+static int an8855_port_fdb_add(struct dsa_switch *ds, int port,
+ const unsigned char *addr, u16 vid,
+ struct dsa_db db)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_port_fdb_add(&priv->lib_priv, port, addr, vid, db);
+}
+
+static int an8855_port_fdb_del(struct dsa_switch *ds, int port,
+ const unsigned char *addr, u16 vid,
+ struct dsa_db db)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_port_fdb_del(&priv->lib_priv, port, addr, vid, db);
+}
+
+static int an8855_port_fdb_dump(struct dsa_switch *ds, int port,
+ dsa_fdb_dump_cb_t *cb, void *data)
+{
+ struct an8855_priv *priv = ds->priv;
+ int banks, count = 0;
+ u32 rsp;
+ int ret;
+ int i;
+
+ mutex_lock(&priv->reg_mutex);
+
+ /* Load search port */
+ ret = regmap_write(priv->regmap, AN8855_ATWD2,
+ FIELD_PREP(AN8855_ATWD2_PORT, BIT(port)));
+ if (ret)
+ goto exit;
+ ret = mt7530_lib_fdb_cmd(&priv->lib_priv, MT7530_FDB_START,
+ AN8855_FDB_MAT_MAC_PORT, &rsp);
+ if (ret < 0)
+ goto exit;
+
+ do {
+ /* From response get the number of banks to read, exit if 0 */
+ banks = FIELD_GET(AN8855_ATC_HIT, rsp);
+ if (!banks)
+ break;
+
+ /* Each banks have 4 entry */
+ for (i = 0; i < 4; i++) {
+ struct mt7530_fdb _fdb = { };
+
+ count++;
+
+ /* Check if bank is present */
+ if (!(banks & BIT(i)))
+ continue;
+
+ /* Select bank entry index */
+ ret = regmap_write(priv->regmap, AN8855_ATRDS,
+ FIELD_PREP(AN8855_ATRD_SEL, i));
+ if (ret)
+ break;
+ /* wait 1ms for the bank entry to be filled */
+ usleep_range(1000, 1500);
+ mt7530_lib_fdb_read(&priv->lib_priv, &_fdb);
+
+ ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, data);
+ if (ret < 0)
+ break;
+ }
+
+ /* Stop if reached max FDB number */
+ if (ret < 0 || count >= AN8855_NUM_FDB_RECORDS)
+ break;
+
+ /* Read next bank */
+ ret = mt7530_lib_fdb_cmd(&priv->lib_priv, MT7530_FDB_NEXT,
+ AN8855_FDB_MAT_MAC_PORT, &rsp);
+ if (ret < 0)
+ break;
+ } while (true);
+
+exit:
+ mutex_unlock(&priv->reg_mutex);
+ return ret;
+}
+
+static int an8855_port_vlan_filtering(struct dsa_switch *ds, int port,
+ bool vlan_filtering,
+ struct netlink_ext_ack *extack)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_port_vlan_filtering(&priv->lib_priv, port,
+ vlan_filtering,
+ extack);
+}
+
+static int an8855_port_vlan_add(struct dsa_switch *ds, int port,
+ const struct switchdev_obj_port_vlan *vlan,
+ struct netlink_ext_ack *extack)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_port_vlan_add(&priv->lib_priv, port, vlan, extack);
+}
+
+static int an8855_port_vlan_del(struct dsa_switch *ds, int port,
+ const struct switchdev_obj_port_vlan *vlan)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_port_vlan_del(&priv->lib_priv, port, vlan);
+}
+
+static int an8855_port_mdb_add(struct dsa_switch *ds, int port,
+ const struct switchdev_obj_port_mdb *mdb,
+ struct dsa_db db)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_port_mdb_add(&priv->lib_priv, port, mdb, db);
+}
+
+static int an8855_port_mdb_del(struct dsa_switch *ds, int port,
+ const struct switchdev_obj_port_mdb *mdb,
+ struct dsa_db db)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_port_mdb_del(&priv->lib_priv, port, mdb, db);
+}
+
+static int an8855_port_change_mtu(struct dsa_switch *ds, int port,
+ int new_mtu)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_port_change_mtu(&priv->lib_priv, port, new_mtu);
+}
+
+static int an8855_port_max_mtu(struct dsa_switch *ds, int port)
+{
+ return AN8855_MAX_MTU;
+}
+
+static void an8855_get_strings(struct dsa_switch *ds, int port,
+ u32 stringset, uint8_t *data)
+{
+ int i;
+
+ if (stringset != ETH_SS_STATS)
+ return;
+
+ for (i = 0; i < ARRAY_SIZE(an8855_mib); i++)
+ ethtool_puts(&data, an8855_mib[i].name);
+}
+
+static void an8855_get_ethtool_stats(struct dsa_switch *ds, int port,
+ uint64_t *data)
+{
+ struct an8855_priv *priv = ds->priv;
+ const struct mt7530_mib_desc *mib;
+ struct mt7530_lib_priv *lib_priv;
+ int i;
+
+ lib_priv = &priv->lib_priv;
+ for (i = 0; i < ARRAY_SIZE(an8855_mib); i++) {
+ struct regmap_field *high = NULL;
+
+ mib = &an8855_mib[i];
+ if (mib->field_high != -1)
+ high = lib_priv->fields[mib->field_high];
+
+ mt7530_lib_read_port_stats(lib_priv->fields[mib->field_low],
+ high, port, data + i);
+ }
+}
+
+static int an8855_get_sset_count(struct dsa_switch *ds, int port,
+ int sset)
+{
+ if (sset != ETH_SS_STATS)
+ return -EOPNOTSUPP;
+
+ return ARRAY_SIZE(an8855_mib);
+}
+
+static void an8855_get_eth_mac_stats(struct dsa_switch *ds, int port,
+ struct ethtool_eth_mac_stats *mac_stats)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_get_eth_mac_stats(&priv->lib_priv, port, mac_stats);
+}
+
+static const struct ethtool_rmon_hist_range an8855_rmon_ranges[] = {
+ { 0, 64 },
+ { 65, 127 },
+ { 128, 255 },
+ { 256, 511 },
+ { 512, 1023 },
+ { 1024, 1518 },
+ { 1519, AN8855_MAX_MTU },
+ {}
+};
+
+static const struct mt7530_rmon_hist an8855_rmon_hist_info = {
+ .ranges_fields = (unsigned int []){
+ MT7530_MIB_RX_PKT_SZ_64,
+ MT7530_MIB_RX_PKT_SZ_65_TO_127,
+ MT7530_MIB_RX_PKT_SZ_128_TO_255,
+ MT7530_MIB_RX_PKT_SZ_256_TO_511,
+ MT7530_MIB_RX_PKT_SZ_512_TO_1023,
+ AN8855_MIB_RX_PKT_SZ_1024_TO_1518,
+ AN8855_MIB_RX_PKT_SZ_1519_TO_MAX,
+ },
+ .ranges_tx_fields = (unsigned int []){
+ MT7530_MIB_TX_PKT_SZ_64,
+ MT7530_MIB_TX_PKT_SZ_65_TO_127,
+ MT7530_MIB_TX_PKT_SZ_128_TO_255,
+ MT7530_MIB_TX_PKT_SZ_256_TO_511,
+ MT7530_MIB_TX_PKT_SZ_512_TO_1023,
+ AN8855_MIB_TX_PKT_SZ_1024_TO_1518,
+ AN8855_MIB_TX_PKT_SZ_1519_TO_MAX,
+ },
+ .ranges = an8855_rmon_ranges,
+ .num_ranges = ARRAY_SIZE(an8855_rmon_ranges) - 1,
+};
+
+static void an8855_get_rmon_stats(struct dsa_switch *ds, int port,
+ struct ethtool_rmon_stats *rmon_stats,
+ const struct ethtool_rmon_hist_range **ranges)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_get_rmon_stats(&priv->lib_priv, port, rmon_stats, ranges,
+ &an8855_rmon_hist_info);
+}
+
+static void an8855_get_eth_ctrl_stats(struct dsa_switch *ds, int port,
+ struct ethtool_eth_ctrl_stats *ctrl_stats)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ mt7530_lib_get_eth_ctrl_stats(&priv->lib_priv, port, ctrl_stats);
+}
+
+static int an8855_port_mirror_add(struct dsa_switch *ds, int port,
+ struct dsa_mall_mirror_tc_entry *mirror,
+ bool ingress,
+ struct netlink_ext_ack *extack)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ return mt7530_lib_port_mirror_add(&priv->lib_priv, port, mirror, ingress, extack);
+}
+
+static void an8855_port_mirror_del(struct dsa_switch *ds, int port,
+ struct dsa_mall_mirror_tc_entry *mirror)
+{
+ struct an8855_priv *priv = ds->priv;
+
+ mt7530_lib_port_mirror_del(&priv->lib_priv, port, mirror);
+}
+
+static int an8855_port_enable(struct dsa_switch *ds, int port,
+ struct phy_device *phy)
+{
+ struct dsa_port *dp = dsa_to_port(ds, port);
+ struct an8855_priv *priv = ds->priv;
+ int ret;
+
+ mutex_lock(&priv->reg_mutex);
+
+ /* Allow the user port gets connected to the cpu port and also
+ * restore the port matrix if the port is the member of a certain
+ * bridge.
+ */
+ if (dsa_port_is_user(dp)) {
+ struct dsa_port *cpu_dp = dp->cpu_dp;
+
+ priv->ports[port].pm |= BIT(cpu_dp->index);
+ }
+ priv->ports[port].enable = true;
+ ret = regmap_fields_write(priv->lib_priv.fields[MT7530_PCR_MATRIX],
+ port, 0);
+ if (ret)
+ goto exit;
+
+ ret = regmap_set_bits(priv->regmap, AN8855_PMCR_P(port),
+ AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN);
+
+exit:
+ mutex_unlock(&priv->reg_mutex);
+
+ return ret;
+}
+
+static void an8855_port_disable(struct dsa_switch *ds, int port)
+{
+ struct an8855_priv *priv = ds->priv;
+ int ret;
+
+ mutex_lock(&priv->reg_mutex);
+ priv->ports[port].enable = false;
+ ret = regmap_fields_write(priv->lib_priv.fields[MT7530_PCR_MATRIX],
+ port, 0);
+ if (ret)
+ goto exit;
+
+ ret = regmap_clear_bits(priv->regmap, AN8855_PMCR_P(port),
+ AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN);
+exit:
+ mutex_unlock(&priv->reg_mutex);
+ if (ret)
+ dev_err(priv->ds->dev, "failed to disable port: %d\n", ret);
+}
+
+static int an8855_set_mac_eee(struct dsa_switch *ds, int port,
+ struct ethtool_keee *e)
+{
+ if (e->tx_lpi_timer > 0xFFF)
+ return -EINVAL;
+
+ return 0;
+}
+
+static enum dsa_tag_protocol an8855_get_tag_protocol(struct dsa_switch *ds,
+ int port,
+ enum dsa_tag_protocol mp)
+{
+ return DSA_TAG_PROTO_AIROHA;
+}
+
+static int an8855_setup(struct dsa_switch *ds)
+{
+ struct an8855_priv *priv = ds->priv;
+ struct dsa_port *dp;
+ int ret;
+
+ /* Enable and reset MIB counters */
+ mt7530_lib_mib_reset(&priv->lib_priv);
+
+ dsa_switch_for_each_user_port(dp, ds) {
+ /* Disable MAC by default on all user ports */
+ an8855_port_disable(ds, dp->index);
+
+ /* Individual user ports get connected to CPU port only */
+ ret = regmap_write(priv->regmap, AN8855_PORTMATRIX_P(dp->index),
+ FIELD_PREP(AN8855_PORTMATRIX_MASK, BIT(AN8855_CPU_PORT)));
+ if (ret)
+ return ret;
+
+ /* Disable Broadcast Forward on user ports */
+ ret = regmap_clear_bits(priv->regmap, AN8855_BCF, BIT(dp->index));
+ if (ret)
+ return ret;
+
+ /* Disable Unknown Unicast Forward on user ports */
+ ret = regmap_clear_bits(priv->regmap, AN8855_UNUF, BIT(dp->index));
+ if (ret)
+ return ret;
+
+ /* Disable Unknown Multicast Forward on user ports */
+ ret = regmap_clear_bits(priv->regmap, AN8855_UNMF, BIT(dp->index));
+ if (ret)
+ return ret;
+
+ ret = regmap_clear_bits(priv->regmap, AN8855_UNIPMF, BIT(dp->index));
+ if (ret)
+ return ret;
+
+ /* Set default PVID to on all user ports */
+ mt7530_port_set_pvid(&priv->lib_priv, dp->index, AN8855_PORT_VID_DEFAULT);
+ }
+
+ /* Enable Airoha header mode on the cpu port */
+ ret = regmap_write(priv->regmap, AN8855_PVC_P(AN8855_CPU_PORT),
+ AN8855_PORT_SPEC_REPLACE_MODE | AN8855_PORT_SPEC_TAG);
+ if (ret)
+ return ret;
+
+ /* Unknown multicast frame forwarding to the cpu port */
+ ret = regmap_write(priv->regmap, AN8855_UNMF, BIT(AN8855_CPU_PORT));
+ if (ret)
+ return ret;
+
+ /* Set CPU port number */
+ ret = regmap_update_bits(priv->regmap, AN8855_MFC,
+ AN8855_CPU_EN | AN8855_CPU_PORT_IDX,
+ AN8855_CPU_EN |
+ FIELD_PREP(AN8855_CPU_PORT_IDX, AN8855_CPU_PORT));
+ if (ret)
+ return ret;
+
+ /* CPU port gets connected to all user ports of
+ * the switch.
+ */
+ ret = regmap_write(priv->regmap, AN8855_PORTMATRIX_P(AN8855_CPU_PORT),
+ FIELD_PREP(AN8855_PORTMATRIX_MASK, dsa_user_ports(ds)));
+ if (ret)
+ return ret;
+
+ /* CPU port is set to fallback mode to let untagged
+ * frames pass through.
+ */
+ ret = regmap_update_bits(priv->regmap, AN8855_PCR_P(AN8855_CPU_PORT),
+ AN8855_PORT_VLAN,
+ FIELD_PREP(AN8855_PORT_VLAN, AN8855_PORT_FALLBACK_MODE));
+ if (ret)
+ return ret;
+
+ /* Enable Broadcast Forward on CPU port */
+ ret = regmap_set_bits(priv->regmap, AN8855_BCF, BIT(AN8855_CPU_PORT));
+ if (ret)
+ return ret;
+
+ /* Enable Unknown Unicast Forward on CPU port */
+ ret = regmap_set_bits(priv->regmap, AN8855_UNUF, BIT(AN8855_CPU_PORT));
+ if (ret)
+ return ret;
+
+ /* Enable Unknown Multicast Forward on CPU port */
+ ret = regmap_set_bits(priv->regmap, AN8855_UNMF, BIT(AN8855_CPU_PORT));
+ if (ret)
+ return ret;
+
+ ret = regmap_set_bits(priv->regmap, AN8855_UNIPMF, BIT(AN8855_CPU_PORT));
+ if (ret)
+ return ret;
+
+ /* Setup Trap special frame to CPU rules */
+ mt7530_lib_trap_frames(&priv->lib_priv);
+
+ dsa_switch_for_each_port(dp, ds) {
+ /* Disable Learning on all ports.
+ * Learning on CPU is disabled for fdb isolation and handled by
+ * assisted_learning_on_cpu_port.
+ */
+ ret = regmap_set_bits(priv->regmap, AN8855_PSC_P(dp->index),
+ AN8855_SA_DIS);
+ if (ret)
+ return ret;
+
+ /* Enable consistent egress tag (for VLAN unware VLAN-passthrough) */
+ ret = regmap_update_bits(priv->regmap, AN8855_PVC_P(dp->index),
+ AN8855_PVC_EG_TAG,
+ FIELD_PREP(AN8855_PVC_EG_TAG, AN8855_VLAN_EG_CONSISTENT));
+ if (ret)
+ return ret;
+ }
+
+ /* Setup VLAN for Default PVID */
+ ret = mt7530_lib_setup_vlan0(&priv->lib_priv);
+ if (ret)
+ return ret;
+
+ ret = regmap_clear_bits(priv->regmap, AN8855_CKGCR,
+ AN8855_CKG_LNKDN_GLB_STOP | AN8855_CKG_LNKDN_PORT_STOP);
+ if (ret)
+ return ret;
+
+ /* Flush the FDB table */
+ ret = mt7530_lib_fdb_cmd(&priv->lib_priv, MT7530_FDB_FLUSH,
+ AN8855_FDB_MAT_ALL, NULL);
+ if (ret < 0)
+ return ret;
+
+ /* Set min a max ageing value supported */
+ ds->ageing_time_min = AN8855_L2_AGING_MS_CONSTANT;
+ ds->ageing_time_max = FIELD_MAX(AN8855_AGE_CNT) *
+ FIELD_MAX(AN8855_AGE_UNIT) *
+ AN8855_L2_AGING_MS_CONSTANT;
+
+ /* User reported problem with WiFi roaming and
+ * ethernet port. Enabling assisted learning fix
+ * the issue.
+ */
+ ds->assisted_learning_on_cpu_port = true;
+
+ return 0;
+}
+
+static struct phylink_pcs *an8855_phylink_mac_select_pcs(struct phylink_config *config,
+ phy_interface_t interface)
+{
+ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct an8855_priv *priv = dp->ds->priv;
+
+ switch (interface) {
+ case PHY_INTERFACE_MODE_SGMII:
+ case PHY_INTERFACE_MODE_2500BASEX:
+ return &priv->pcs;
+ default:
+ return NULL;
+ }
+}
+
+static void an8855_phylink_mac_config(struct phylink_config *config,
+ unsigned int mode,
+ const struct phylink_link_state *state)
+{
+ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct dsa_switch *ds = dp->ds;
+ struct an8855_priv *priv;
+ int port = dp->index;
+
+ priv = ds->priv;
+
+ /* Nothing to configure for internal ports */
+ if (port != 5)
+ return;
+
+ mutex_lock(&priv->reg_mutex);
+ regmap_update_bits(priv->regmap, AN8855_PMCR_P(port),
+ AN8855_PMCR_IFG_XMIT | AN8855_PMCR_MAC_MODE |
+ AN8855_PMCR_BACKOFF_EN | AN8855_PMCR_BACKPR_EN,
+ FIELD_PREP(AN8855_PMCR_IFG_XMIT, 0x1) |
+ AN8855_PMCR_MAC_MODE | AN8855_PMCR_BACKOFF_EN |
+ AN8855_PMCR_BACKPR_EN);
+ mutex_unlock(&priv->reg_mutex);
+}
+
+static void an8855_phylink_get_caps(struct dsa_switch *ds, int port,
+ struct phylink_config *config)
+{
+ struct an8855_priv *priv = ds->priv;
+ u32 reg = 0;
+ int ret;
+
+ switch (port) {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 4:
+ __set_bit(PHY_INTERFACE_MODE_GMII,
+ config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_INTERNAL,
+ config->supported_interfaces);
+ break;
+ case 5:
+ phy_interface_set_rgmii(config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_SGMII,
+ config->supported_interfaces);
+ __set_bit(PHY_INTERFACE_MODE_2500BASEX,
+ config->supported_interfaces);
+ break;
+ }
+
+ config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
+ MAC_10 | MAC_100 | MAC_1000FD | MAC_2500FD;
+
+ ret = regmap_read(priv->regmap, AN8855_CKGCR, ®);
+ if (ret)
+ dev_err(ds->dev, "failed to read EEE LPI timer\n");
+
+ memcpy(config->lpi_interfaces, config->supported_interfaces,
+ sizeof(config->lpi_interfaces));
+ config->lpi_capabilities = MAC_100FD | MAC_1000FD;
+ /* Global LPI TXIDLE Threshold, default 60ms (unit 2us) */
+ config->lpi_timer_default = FIELD_GET(AN8855_LPI_TXIDLE_THD_MASK, reg) *
+ AN8855_TX_LPI_UNIT;
+
+ config->eee_enabled_default = true;
+}
+
+static void an8855_phylink_mac_link_down(struct phylink_config *config,
+ unsigned int mode,
+ phy_interface_t interface)
+{
+ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct an8855_priv *priv = dp->ds->priv;
+
+ mutex_lock(&priv->reg_mutex);
+
+ /* With autoneg just disable TX/RX else also force link down */
+ if (phylink_autoneg_inband(mode)) {
+ regmap_clear_bits(priv->regmap, AN8855_PMCR_P(dp->index),
+ AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN);
+ } else {
+ regmap_update_bits(priv->regmap, AN8855_PMCR_P(dp->index),
+ AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN |
+ AN8855_PMCR_FORCE_MODE | AN8855_PMCR_FORCE_LNK,
+ AN8855_PMCR_FORCE_MODE);
+ }
+
+ mutex_unlock(&priv->reg_mutex);
+}
+
+static void an8855_phylink_mac_link_up(struct phylink_config *config,
+ struct phy_device *phydev, unsigned int mode,
+ phy_interface_t interface, int speed,
+ int duplex, bool tx_pause, bool rx_pause)
+{
+ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct an8855_priv *priv = dp->ds->priv;
+ int port = dp->index;
+ u32 reg = 0;
+
+ mutex_lock(&priv->reg_mutex);
+
+ regmap_read(priv->regmap, AN8855_PMCR_P(port), ®);
+ if (phylink_autoneg_inband(mode)) {
+ reg &= ~AN8855_PMCR_FORCE_MODE;
+ } else {
+ reg |= AN8855_PMCR_FORCE_MODE | AN8855_PMCR_FORCE_LNK;
+
+ reg &= ~AN8855_PMCR_FORCE_SPEED;
+ switch (speed) {
+ case SPEED_10:
+ reg |= AN8855_PMCR_FORCE_SPEED_10;
+ break;
+ case SPEED_100:
+ reg |= AN8855_PMCR_FORCE_SPEED_100;
+ break;
+ case SPEED_1000:
+ reg |= AN8855_PMCR_FORCE_SPEED_1000;
+ break;
+ case SPEED_2500:
+ reg |= AN8855_PMCR_FORCE_SPEED_2500;
+ break;
+ case SPEED_5000:
+ dev_err(priv->ds->dev, "Missing support for 5G speed. Aborting...\n");
+ goto exit;
+ }
+
+ reg &= ~AN8855_PMCR_FORCE_FDX;
+ if (duplex == DUPLEX_FULL)
+ reg |= AN8855_PMCR_FORCE_FDX;
+
+ reg &= ~AN8855_PMCR_RX_FC_EN;
+ if (rx_pause || dsa_port_is_cpu(dp))
+ reg |= AN8855_PMCR_RX_FC_EN;
+
+ reg &= ~AN8855_PMCR_TX_FC_EN;
+ if (tx_pause || dsa_port_is_cpu(dp))
+ reg |= AN8855_PMCR_TX_FC_EN;
+ }
+
+ reg |= AN8855_PMCR_TX_EN | AN8855_PMCR_RX_EN;
+
+ regmap_write(priv->regmap, AN8855_PMCR_P(port), reg);
+
+exit:
+ mutex_unlock(&priv->reg_mutex);
+}
+
+static void an8855_phylink_mac_disable_tx_lpi(struct phylink_config *config)
+{
+ struct dsa_port *dp = dsa_phylink_to_port(config);
+ struct an8855_priv *priv = dp->ds->priv;
+ int port = dp->index;
+ int ret;
+
+ mutex_lock(&priv->reg_mutex);
+ priv->tx_lpi_timer_ports[port] = 0;
+ ret = regmap_clear_bits(priv->regmap, AN8855_PMCR_P(port),
+ AN8855_PMCR_FORCE_EEE1G |
+ AN8855_PMCR_FORCE_EEE100);
+ mutex_unlock(&priv->reg_mutex);
+ if (ret)
+ dev_err(dp->ds->dev, "failed to disable EEE for port %d\n",
+ port);
+
+ ret = regmap_clear_bits(priv->regmap, AN8855_PMEEECR_P(port),
+ AN8855_LPI_MODE_EN);
+ if (ret)
+ dev_err(dp->ds->dev, "failed to disable LPI for port %d\n",
+ port);
+}
+
+static int an8855_phylink_mac_enable_tx_lpi(struct phylink_config *config,
+ u32 timer, bool tx_clock_stop)
+{
+ struct an8855_priv *priv;
+ struct dsa_switch *ds;
+ struct dsa_port *dp;
+ int port;
+ u32 val;
+ int ret;
+
+ dp = dsa_phylink_to_port(config);
+ port = dp->index;
+ ds = dp->ds;
+ priv = ds->priv;
+
+ /* TX LPI timer is global, find the highest timer
+ * across all port.
+ * If requested timer is 0, set to enter LPI immediately
+ * for the single port.
+ */
+ if (timer) {
+ int i;
+
+ /* Save requested timer and search the highest one */
+ mutex_lock(&priv->reg_mutex);
+ priv->tx_lpi_timer_ports[port] = timer;
+ for (i = 0; i < AN8855_NUM_PORTS; i++) {
+ if (!priv->ports[i].enable)
+ continue;
+
+ if (i == port)
+ continue;
+
+ if (timer < priv->tx_lpi_timer_ports[i])
+ timer = priv->tx_lpi_timer_ports[i];
+ }
+
+ timer /= AN8855_TX_LPI_UNIT;
+ if (FIELD_FIT(AN8855_LPI_TXIDLE_THD_MASK, timer))
+ val = FIELD_PREP(AN8855_LPI_TXIDLE_THD_MASK, timer);
+ else
+ val = AN8855_LPI_TXIDLE_THD_MASK;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_CKGCR,
+ AN8855_LPI_TXIDLE_THD_MASK, val);
+ mutex_unlock(&priv->reg_mutex);
+ if (ret) {
+ dev_err(dp->ds->dev, "failed to set global LPI timer\n");
+ return ret;
+ }
+ } else {
+ ret = regmap_set_bits(priv->regmap, AN8855_PMEEECR_P(port),
+ AN8855_LPI_MODE_EN);
+ if (ret) {
+ dev_err(dp->ds->dev, "failed to enable LPI for port %d\n",
+ port);
+ return ret;
+ }
+ }
+
+ mutex_lock(&priv->reg_mutex);
+ ret = regmap_set_bits(priv->regmap, AN8855_PMCR_P(port),
+ AN8855_PMCR_FORCE_EEE1G |
+ AN8855_PMCR_FORCE_EEE100);
+ mutex_unlock(&priv->reg_mutex);
+ if (ret)
+ dev_err(dp->ds->dev, "failed to enable EEE for port %d\n",
+ port);
+
+ return ret;
+}
+
+static unsigned int an8855_pcs_inband_caps(struct phylink_pcs *pcs,
+ phy_interface_t interface)
+{
+ /* SGMII can be configured to use inband with AN result */
+ if (interface == PHY_INTERFACE_MODE_SGMII)
+ return LINK_INBAND_DISABLE | LINK_INBAND_ENABLE;
+
+ /* inband is not supported in 2500-baseX and must be disabled */
+ return LINK_INBAND_DISABLE;
+}
+
+static void an8855_pcs_get_state(struct phylink_pcs *pcs, unsigned int neg_mode,
+ struct phylink_link_state *state)
+{
+ struct an8855_priv *priv = container_of(pcs, struct an8855_priv, pcs);
+ u32 val;
+ int ret;
+
+ ret = regmap_read(priv->regmap, AN8855_PMSR_P(AN8855_CPU_PORT), &val);
+ if (ret < 0) {
+ state->link = false;
+ return;
+ }
+
+ state->link = !!(val & AN8855_PMSR_LNK);
+ state->an_complete = state->link;
+ state->duplex = (val & AN8855_PMSR_DPX) ? DUPLEX_FULL :
+ DUPLEX_HALF;
+
+ switch (val & AN8855_PMSR_SPEED) {
+ case AN8855_PMSR_SPEED_10:
+ state->speed = SPEED_10;
+ break;
+ case AN8855_PMSR_SPEED_100:
+ state->speed = SPEED_100;
+ break;
+ case AN8855_PMSR_SPEED_1000:
+ state->speed = SPEED_1000;
+ break;
+ case AN8855_PMSR_SPEED_2500:
+ state->speed = SPEED_2500;
+ break;
+ case AN8855_PMSR_SPEED_5000:
+ dev_err(priv->ds->dev, "Switch doesn't support 5G speed. Setting Unknown.\n");
+ fallthrough;
+ default:
+ state->speed = SPEED_UNKNOWN;
+ break;
+ }
+
+ if (val & AN8855_PMSR_RX_FC)
+ state->pause |= MLO_PAUSE_RX;
+ if (val & AN8855_PMSR_TX_FC)
+ state->pause |= MLO_PAUSE_TX;
+}
+
+static int an8855_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
+ phy_interface_t interface,
+ const unsigned long *advertising,
+ bool permit_pause_to_mac)
+{
+ struct an8855_priv *priv = container_of(pcs, struct an8855_priv, pcs);
+ u32 val;
+ int ret;
+
+ /* TX FIR - improve TX EYE */
+ ret = regmap_update_bits(priv->regmap, AN8855_INTF_CTRL_10,
+ AN8855_RG_DA_QP_TX_FIR_C2_SEL |
+ AN8855_RG_DA_QP_TX_FIR_C2_FORCE |
+ AN8855_RG_DA_QP_TX_FIR_C1_SEL |
+ AN8855_RG_DA_QP_TX_FIR_C1_FORCE,
+ AN8855_RG_DA_QP_TX_FIR_C2_SEL |
+ FIELD_PREP(AN8855_RG_DA_QP_TX_FIR_C2_FORCE, 0x4) |
+ AN8855_RG_DA_QP_TX_FIR_C1_SEL |
+ FIELD_PREP(AN8855_RG_DA_QP_TX_FIR_C1_FORCE, 0x0));
+ if (ret)
+ return ret;
+
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ val = 0x0;
+ else
+ val = 0xd;
+ ret = regmap_update_bits(priv->regmap, AN8855_INTF_CTRL_11,
+ AN8855_RG_DA_QP_TX_FIR_C0B_SEL |
+ AN8855_RG_DA_QP_TX_FIR_C0B_FORCE,
+ AN8855_RG_DA_QP_TX_FIR_C0B_SEL |
+ FIELD_PREP(AN8855_RG_DA_QP_TX_FIR_C0B_FORCE, val));
+ if (ret)
+ return ret;
+
+ /* RX CDR - improve RX Jitter Tolerance */
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ val = 0x5;
+ else
+ val = 0x6;
+ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_LPF_BOT_LIM,
+ AN8855_RG_QP_CDR_LPF_KP_GAIN |
+ AN8855_RG_QP_CDR_LPF_KI_GAIN,
+ FIELD_PREP(AN8855_RG_QP_CDR_LPF_KP_GAIN, val) |
+ FIELD_PREP(AN8855_RG_QP_CDR_LPF_KI_GAIN, val));
+ if (ret)
+ return ret;
+
+ /* PLL */
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ val = 0x1;
+ else
+ val = 0x0;
+ ret = regmap_update_bits(priv->regmap, AN8855_QP_DIG_MODE_CTRL_1,
+ AN8855_RG_TPHY_SPEED,
+ FIELD_PREP(AN8855_RG_TPHY_SPEED, val));
+ if (ret)
+ return ret;
+
+ /* PLL - LPF */
+ ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2,
+ AN8855_RG_DA_QP_PLL_RICO_SEL_INTF |
+ AN8855_RG_DA_QP_PLL_FBKSEL_INTF |
+ AN8855_RG_DA_QP_PLL_BR_INTF |
+ AN8855_RG_DA_QP_PLL_BPD_INTF |
+ AN8855_RG_DA_QP_PLL_BPA_INTF |
+ AN8855_RG_DA_QP_PLL_BC_INTF,
+ AN8855_RG_DA_QP_PLL_RICO_SEL_INTF |
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_FBKSEL_INTF, 0x0) |
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_BR_INTF, 0x3) |
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_BPD_INTF, 0x0) |
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_BPA_INTF, 0x5) |
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_BC_INTF, 0x1));
+ if (ret)
+ return ret;
+
+ /* PLL - ICO */
+ ret = regmap_set_bits(priv->regmap, AN8855_PLL_CTRL_4,
+ AN8855_RG_DA_QP_PLL_ICOLP_EN_INTF);
+ if (ret)
+ return ret;
+ ret = regmap_clear_bits(priv->regmap, AN8855_PLL_CTRL_2,
+ AN8855_RG_DA_QP_PLL_ICOIQ_EN_INTF);
+ if (ret)
+ return ret;
+
+ /* PLL - CHP */
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ val = 0x6;
+ else
+ val = 0x4;
+ ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2,
+ AN8855_RG_DA_QP_PLL_IR_INTF,
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_IR_INTF, val));
+ if (ret)
+ return ret;
+
+ /* PLL - PFD */
+ ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2,
+ AN8855_RG_DA_QP_PLL_PFD_OFFSET_EN_INTRF |
+ AN8855_RG_DA_QP_PLL_PFD_OFFSET_INTF |
+ AN8855_RG_DA_QP_PLL_KBAND_PREDIV_INTF,
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_PFD_OFFSET_INTF, 0x1) |
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_KBAND_PREDIV_INTF, 0x1));
+ if (ret)
+ return ret;
+
+ /* PLL - POSTDIV */
+ ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2,
+ AN8855_RG_DA_QP_PLL_POSTDIV_EN_INTF |
+ AN8855_RG_DA_QP_PLL_PHY_CK_EN_INTF |
+ AN8855_RG_DA_QP_PLL_PCK_SEL_INTF,
+ AN8855_RG_DA_QP_PLL_PCK_SEL_INTF);
+ if (ret)
+ return ret;
+
+ /* PLL - SDM */
+ ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2,
+ AN8855_RG_DA_QP_PLL_SDM_HREN_INTF,
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_SDM_HREN_INTF, 0x0));
+ if (ret)
+ return ret;
+ ret = regmap_clear_bits(priv->regmap, AN8855_PLL_CTRL_2,
+ AN8855_RG_DA_QP_PLL_SDM_IFM_INTF);
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_SS_LCPLL_PWCTL_SETTING_2,
+ AN8855_RG_NCPO_ANA_MSB,
+ FIELD_PREP(AN8855_RG_NCPO_ANA_MSB, 0x1));
+ if (ret)
+ return ret;
+
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ val = 0x7a000000;
+ else
+ val = 0x48000000;
+ ret = regmap_write(priv->regmap, AN8855_SS_LCPLL_TDC_FLT_2,
+ FIELD_PREP(AN8855_RG_LCPLL_NCPO_VALUE, val));
+ if (ret)
+ return ret;
+ ret = regmap_write(priv->regmap, AN8855_SS_LCPLL_TDC_PCW_1,
+ FIELD_PREP(AN8855_RG_LCPLL_PON_HRDDS_PCW_NCPO_GPON, val));
+ if (ret)
+ return ret;
+
+ ret = regmap_clear_bits(priv->regmap, AN8855_SS_LCPLL_TDC_FLT_5,
+ AN8855_RG_LCPLL_NCPO_CHG);
+ if (ret)
+ return ret;
+ ret = regmap_clear_bits(priv->regmap, AN8855_PLL_CK_CTRL_0,
+ AN8855_RG_DA_QP_PLL_SDM_DI_EN_INTF);
+ if (ret)
+ return ret;
+
+ /* PLL - SS */
+ ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_3,
+ AN8855_RG_DA_QP_PLL_SSC_DELTA_INTF,
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_SSC_DELTA_INTF, 0x0));
+ if (ret)
+ return ret;
+ ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_4,
+ AN8855_RG_DA_QP_PLL_SSC_DIR_DLY_INTF,
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_SSC_DIR_DLY_INTF, 0x0));
+ if (ret)
+ return ret;
+ ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_3,
+ AN8855_RG_DA_QP_PLL_SSC_PERIOD_INTF,
+ FIELD_PREP(AN8855_RG_DA_QP_PLL_SSC_PERIOD_INTF, 0x0));
+ if (ret)
+ return ret;
+
+ /* PLL - TDC */
+ ret = regmap_clear_bits(priv->regmap, AN8855_PLL_CK_CTRL_0,
+ AN8855_RG_DA_QP_PLL_TDC_TXCK_SEL_INTF);
+ if (ret)
+ return ret;
+
+ ret = regmap_set_bits(priv->regmap, AN8855_RG_QP_PLL_SDM_ORD,
+ AN8855_RG_QP_PLL_SSC_TRI_EN);
+ if (ret)
+ return ret;
+ ret = regmap_set_bits(priv->regmap, AN8855_RG_QP_PLL_SDM_ORD,
+ AN8855_RG_QP_PLL_SSC_PHASE_INI);
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_RX_DAC_EN,
+ AN8855_RG_QP_SIGDET_HF,
+ FIELD_PREP(AN8855_RG_QP_SIGDET_HF, 0x2));
+ if (ret)
+ return ret;
+
+ /* TCL Disable (only for Co-SIM) */
+ ret = regmap_clear_bits(priv->regmap, AN8855_PON_RXFEDIG_CTRL_0,
+ AN8855_RG_QP_EQ_RX500M_CK_SEL);
+ if (ret)
+ return ret;
+
+ /* TX Init */
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ val = 0x4;
+ else
+ val = 0x0;
+ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_TX_MODE,
+ AN8855_RG_QP_TX_RESERVE |
+ AN8855_RG_QP_TX_MODE_16B_EN,
+ FIELD_PREP(AN8855_RG_QP_TX_RESERVE, val));
+ if (ret)
+ return ret;
+
+ /* RX Control/Init */
+ ret = regmap_set_bits(priv->regmap, AN8855_RG_QP_RXAFE_RESERVE,
+ AN8855_RG_QP_CDR_PD_10B_EN);
+ if (ret)
+ return ret;
+
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ val = 0x1;
+ else
+ val = 0x2;
+ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_LPF_MJV_LIM,
+ AN8855_RG_QP_CDR_LPF_RATIO,
+ FIELD_PREP(AN8855_RG_QP_CDR_LPF_RATIO, val));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_LPF_SETVALUE,
+ AN8855_RG_QP_CDR_PR_BUF_IN_SR |
+ AN8855_RG_QP_CDR_PR_BETA_SEL,
+ FIELD_PREP(AN8855_RG_QP_CDR_PR_BUF_IN_SR, 0x6) |
+ FIELD_PREP(AN8855_RG_QP_CDR_PR_BETA_SEL, 0x1));
+ if (ret)
+ return ret;
+
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ val = 0xf;
+ else
+ val = 0xc;
+ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_PR_CKREF_DIV1,
+ AN8855_RG_QP_CDR_PR_DAC_BAND,
+ FIELD_PREP(AN8855_RG_QP_CDR_PR_DAC_BAND, val));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE,
+ AN8855_RG_QP_CDR_PR_KBAND_PCIE_MODE |
+ AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE_MASK,
+ FIELD_PREP(AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE_MASK, 0x19));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_FORCE_IBANDLPF_R_OFF,
+ AN8855_RG_QP_CDR_PHYCK_SEL |
+ AN8855_RG_QP_CDR_PHYCK_RSTB |
+ AN8855_RG_QP_CDR_PHYCK_DIV,
+ FIELD_PREP(AN8855_RG_QP_CDR_PHYCK_SEL, 0x2) |
+ FIELD_PREP(AN8855_RG_QP_CDR_PHYCK_DIV, 0x21));
+ if (ret)
+ return ret;
+
+ ret = regmap_clear_bits(priv->regmap, AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE,
+ AN8855_RG_QP_CDR_PR_XFICK_EN);
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RG_QP_CDR_PR_CKREF_DIV1,
+ AN8855_RG_QP_CDR_PR_KBAND_DIV,
+ FIELD_PREP(AN8855_RG_QP_CDR_PR_KBAND_DIV, 0x4));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_26,
+ AN8855_RG_QP_EQ_RETRAIN_ONLY_EN |
+ AN8855_RG_LINK_NE_EN |
+ AN8855_RG_LINK_ERRO_EN,
+ AN8855_RG_QP_EQ_RETRAIN_ONLY_EN |
+ AN8855_RG_LINK_ERRO_EN);
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RX_DLY_0,
+ AN8855_RG_QP_RX_SAOSC_EN_H_DLY |
+ AN8855_RG_QP_RX_PI_CAL_EN_H_DLY,
+ FIELD_PREP(AN8855_RG_QP_RX_SAOSC_EN_H_DLY, 0x3f) |
+ FIELD_PREP(AN8855_RG_QP_RX_PI_CAL_EN_H_DLY, 0x6f));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_42,
+ AN8855_RG_QP_EQ_EN_DLY,
+ FIELD_PREP(AN8855_RG_QP_EQ_EN_DLY, 0x150));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_2,
+ AN8855_RG_QP_RX_EQ_EN_H_DLY,
+ FIELD_PREP(AN8855_RG_QP_RX_EQ_EN_H_DLY, 0x150));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_PON_RXFEDIG_CTRL_9,
+ AN8855_RG_QP_EQ_LEQOSC_DLYCNT,
+ FIELD_PREP(AN8855_RG_QP_EQ_LEQOSC_DLYCNT, 0x1));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_8,
+ AN8855_RG_DA_QP_SAOSC_DONE_TIME |
+ AN8855_RG_DA_QP_LEQOS_EN_TIME,
+ FIELD_PREP(AN8855_RG_DA_QP_SAOSC_DONE_TIME, 0x200) |
+ FIELD_PREP(AN8855_RG_DA_QP_LEQOS_EN_TIME, 0xfff));
+ if (ret)
+ return ret;
+
+ /* Frequency meter */
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ val = 0x10;
+ else
+ val = 0x28;
+ ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_5,
+ AN8855_RG_FREDET_CHK_CYCLE,
+ FIELD_PREP(AN8855_RG_FREDET_CHK_CYCLE, val));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_6,
+ AN8855_RG_FREDET_GOLDEN_CYCLE,
+ FIELD_PREP(AN8855_RG_FREDET_GOLDEN_CYCLE, 0x64));
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_RX_CTRL_7,
+ AN8855_RG_FREDET_TOLERATE_CYCLE,
+ FIELD_PREP(AN8855_RG_FREDET_TOLERATE_CYCLE, 0x2710));
+ if (ret)
+ return ret;
+
+ ret = regmap_set_bits(priv->regmap, AN8855_PLL_CTRL_0,
+ AN8855_RG_PHYA_AUTO_INIT);
+ if (ret)
+ return ret;
+
+ /* PCS Init */
+ if (interface == PHY_INTERFACE_MODE_SGMII &&
+ neg_mode == PHYLINK_PCS_NEG_INBAND_DISABLED) {
+ ret = regmap_clear_bits(priv->regmap, AN8855_QP_DIG_MODE_CTRL_0,
+ AN8855_RG_SGMII_MODE | AN8855_RG_SGMII_AN_EN);
+ if (ret)
+ return ret;
+ }
+
+ ret = regmap_clear_bits(priv->regmap, AN8855_RG_HSGMII_PCS_CTROL_1,
+ AN8855_RG_TBI_10B_MODE);
+ if (ret)
+ return ret;
+
+ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ /* Set AN Ability - Interrupt */
+ ret = regmap_set_bits(priv->regmap, AN8855_SGMII_REG_AN_FORCE_CL37,
+ AN8855_RG_FORCE_AN_DONE);
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(priv->regmap, AN8855_SGMII_REG_AN_13,
+ AN8855_SGMII_REMOTE_FAULT_DIS |
+ AN8855_SGMII_IF_MODE,
+ AN8855_SGMII_REMOTE_FAULT_DIS |
+ FIELD_PREP(AN8855_SGMII_IF_MODE, 0xb));
+ if (ret)
+ return ret;
+ }
+
+ /* Rate Adaption - GMII path config. */
+ if (interface == PHY_INTERFACE_MODE_2500BASEX) {
+ ret = regmap_clear_bits(priv->regmap, AN8855_RATE_ADP_P0_CTRL_0,
+ AN8855_RG_P0_DIS_MII_MODE);
+ if (ret)
+ return ret;
+ } else {
+ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ ret = regmap_set_bits(priv->regmap, AN8855_MII_RA_AN_ENABLE,
+ AN8855_RG_P0_RA_AN_EN);
+ if (ret)
+ return ret;
+ } else {
+ ret = regmap_update_bits(priv->regmap, AN8855_RG_AN_SGMII_MODE_FORCE,
+ AN8855_RG_FORCE_CUR_SGMII_MODE |
+ AN8855_RG_FORCE_CUR_SGMII_SEL,
+ AN8855_RG_FORCE_CUR_SGMII_SEL);
+ if (ret)
+ return ret;
+
+ ret = regmap_clear_bits(priv->regmap, AN8855_RATE_ADP_P0_CTRL_0,
+ AN8855_RG_P0_MII_RA_RX_EN |
+ AN8855_RG_P0_MII_RA_TX_EN |
+ AN8855_RG_P0_MII_RA_RX_MODE |
+ AN8855_RG_P0_MII_RA_TX_MODE);
+ if (ret)
+ return ret;
+ }
+
+ ret = regmap_set_bits(priv->regmap, AN8855_RATE_ADP_P0_CTRL_0,
+ AN8855_RG_P0_MII_MODE);
+ if (ret)
+ return ret;
+ }
+
+ ret = regmap_set_bits(priv->regmap, AN8855_RG_RATE_ADAPT_CTRL_0,
+ AN8855_RG_RATE_ADAPT_RX_BYPASS |
+ AN8855_RG_RATE_ADAPT_TX_BYPASS |
+ AN8855_RG_RATE_ADAPT_RX_EN |
+ AN8855_RG_RATE_ADAPT_TX_EN);
+ if (ret)
+ return ret;
+
+ /* Disable AN if not in autoneg */
+ ret = regmap_update_bits(priv->regmap, AN8855_SGMII_REG_AN0, BMCR_ANENABLE,
+ neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED ? BMCR_ANENABLE :
+ 0);
+ if (ret)
+ return ret;
+
+ if (interface == PHY_INTERFACE_MODE_SGMII) {
+ /* Follow SDK init flow with restarting AN after AN enable */
+ if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ ret = regmap_set_bits(priv->regmap, AN8855_SGMII_REG_AN0,
+ BMCR_ANRESTART);
+ if (ret)
+ return ret;
+ } else {
+ ret = regmap_set_bits(priv->regmap, AN8855_PHY_RX_FORCE_CTRL_0,
+ AN8855_RG_FORCE_TXC_SEL);
+ if (ret)
+ return ret;
+ }
+ }
+
+ /* Force Speed with fixed-link or 2500base-x as doesn't support aneg */
+ if (interface == PHY_INTERFACE_MODE_2500BASEX ||
+ neg_mode != PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ if (interface == PHY_INTERFACE_MODE_2500BASEX)
+ val = AN8855_RG_LINK_MODE_P0_SPEED_2500;
+ else
+ val = AN8855_RG_LINK_MODE_P0_SPEED_1000;
+ ret = regmap_update_bits(priv->regmap, AN8855_SGMII_STS_CTRL_0,
+ AN8855_RG_LINK_MODE_P0 |
+ AN8855_RG_FORCE_SPD_MODE_P0,
+ val | AN8855_RG_FORCE_SPD_MODE_P0);
+ if (ret)
+ return ret;
+ }
+
+ /* bypass flow control to MAC */
+ ret = regmap_write(priv->regmap, AN8855_MSG_RX_LIK_STS_0,
+ AN8855_RG_DPX_STS_P3 | AN8855_RG_DPX_STS_P2 |
+ AN8855_RG_DPX_STS_P1 | AN8855_RG_TXFC_STS_P0 |
+ AN8855_RG_RXFC_STS_P0 | AN8855_RG_DPX_STS_P0);
+ if (ret)
+ return ret;
+ ret = regmap_write(priv->regmap, AN8855_MSG_RX_LIK_STS_2,
+ AN8855_RG_RXFC_AN_BYPASS_P3 |
+ AN8855_RG_RXFC_AN_BYPASS_P2 |
+ AN8855_RG_RXFC_AN_BYPASS_P1 |
+ AN8855_RG_TXFC_AN_BYPASS_P3 |
+ AN8855_RG_TXFC_AN_BYPASS_P2 |
+ AN8855_RG_TXFC_AN_BYPASS_P1 |
+ AN8855_RG_DPX_AN_BYPASS_P3 |
+ AN8855_RG_DPX_AN_BYPASS_P2 |
+ AN8855_RG_DPX_AN_BYPASS_P1 |
+ AN8855_RG_DPX_AN_BYPASS_P0);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static void an8855_pcs_an_restart(struct phylink_pcs *pcs)
+{
+}
+
+static const struct phylink_pcs_ops an8855_pcs_ops = {
+ .pcs_inband_caps = an8855_pcs_inband_caps,
+ .pcs_get_state = an8855_pcs_get_state,
+ .pcs_config = an8855_pcs_config,
+ .pcs_an_restart = an8855_pcs_an_restart,
+};
+
+static const struct phylink_mac_ops an8855_phylink_mac_ops = {
+ .mac_select_pcs = an8855_phylink_mac_select_pcs,
+ .mac_config = an8855_phylink_mac_config,
+ .mac_link_down = an8855_phylink_mac_link_down,
+ .mac_link_up = an8855_phylink_mac_link_up,
+ .mac_disable_tx_lpi = an8855_phylink_mac_disable_tx_lpi,
+ .mac_enable_tx_lpi = an8855_phylink_mac_enable_tx_lpi,
+};
+
+static const struct dsa_switch_ops an8855_switch_ops = {
+ .get_tag_protocol = an8855_get_tag_protocol,
+ .setup = an8855_setup,
+ .phylink_get_caps = an8855_phylink_get_caps,
+ .get_strings = an8855_get_strings,
+ .get_ethtool_stats = an8855_get_ethtool_stats,
+ .get_sset_count = an8855_get_sset_count,
+ .get_eth_mac_stats = an8855_get_eth_mac_stats,
+ .get_eth_ctrl_stats = an8855_get_eth_ctrl_stats,
+ .get_rmon_stats = an8855_get_rmon_stats,
+ .port_enable = an8855_port_enable,
+ .port_disable = an8855_port_disable,
+ .set_ageing_time = an8855_set_ageing_time,
+ .port_bridge_join = an8855_port_bridge_join,
+ .port_bridge_leave = an8855_port_bridge_leave,
+ .port_fast_age = an8855_port_fast_age,
+ .port_stp_state_set = an8855_port_stp_state_set,
+ .port_pre_bridge_flags = an8855_port_pre_bridge_flags,
+ .port_bridge_flags = an8855_port_bridge_flags,
+ .port_vlan_filtering = an8855_port_vlan_filtering,
+ .port_vlan_add = an8855_port_vlan_add,
+ .port_vlan_del = an8855_port_vlan_del,
+ .port_fdb_add = an8855_port_fdb_add,
+ .port_fdb_del = an8855_port_fdb_del,
+ .port_fdb_dump = an8855_port_fdb_dump,
+ .port_mdb_add = an8855_port_mdb_add,
+ .port_mdb_del = an8855_port_mdb_del,
+ .port_change_mtu = an8855_port_change_mtu,
+ .port_max_mtu = an8855_port_max_mtu,
+ .port_mirror_add = an8855_port_mirror_add,
+ .port_mirror_del = an8855_port_mirror_del,
+ .support_eee = dsa_supports_eee,
+ .set_mac_eee = an8855_set_mac_eee,
+};
+
+static int an8855_setup_lib_priv(struct an8855_priv *priv)
+{
+ struct mt7530_lib_priv *lib_priv = &priv->lib_priv;
+ int i;
+
+ lib_priv->dev = priv->ds->dev;
+ lib_priv->ds = priv->ds;
+ lib_priv->regmap = priv->regmap;
+ lib_priv->ports = priv->ports;
+ lib_priv->reg_mutex = &priv->reg_mutex;
+
+ for (i = 0; i < ARRAY_SIZE(an8855_fields); i++) {
+ const struct mt7530_reg_field *reg_field;
+ struct regmap_field *field;
+
+ reg_field = &an8855_fields[i];
+ field = devm_regmap_field_alloc(priv->ds->dev, priv->regmap,
+ reg_field->field);
+ if (IS_ERR(field))
+ return PTR_ERR(field);
+
+ lib_priv->fields[reg_field->id] = field;
+ }
+
+ return 0;
+}
+
+static int an8855_switch_probe(struct platform_device *pdev)
+{
+ struct an8855_priv *priv;
+ int ret;
+
+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ /* Get regmap from MFD */
+ priv->regmap = dev_get_regmap(pdev->dev.parent, NULL);
+ if (!priv->regmap)
+ return -ENOENT;
+
+ priv->ds = devm_kzalloc(&pdev->dev, sizeof(*priv->ds), GFP_KERNEL);
+ if (!priv->ds)
+ return -ENOMEM;
+
+ priv->ds->dev = &pdev->dev;
+ priv->ds->num_ports = AN8855_NUM_PORTS;
+ priv->ds->priv = priv;
+ priv->ds->ops = &an8855_switch_ops;
+ ret = devm_mutex_init(&pdev->dev, &priv->reg_mutex);
+ if (ret)
+ return ret;
+ priv->ds->phylink_mac_ops = &an8855_phylink_mac_ops;
+
+ priv->pcs.ops = &an8855_pcs_ops;
+ priv->pcs.poll = true;
+
+ ret = an8855_setup_lib_priv(priv);
+ if (ret)
+ return ret;
+
+ dev_set_drvdata(&pdev->dev, priv);
+
+ return dsa_register_switch(priv->ds);
+}
+
+static void an8855_switch_remove(struct platform_device *pdev)
+{
+ struct an8855_priv *priv = dev_get_drvdata(&pdev->dev);
+
+ if (!priv)
+ return;
+
+ dsa_unregister_switch(priv->ds);
+
+ dev_set_drvdata(&pdev->dev, NULL);
+}
+
+static void an8855_switch_shutdown(struct platform_device *pdev)
+{
+ struct an8855_priv *priv = dev_get_drvdata(&pdev->dev);
+
+ if (!priv)
+ return;
+
+ dsa_switch_shutdown(priv->ds);
+
+ dev_set_drvdata(&pdev->dev, NULL);
+}
+
+static const struct of_device_id an8855_switch_of_match[] = {
+ { .compatible = "airoha,an8855-switch" },
+ { /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, an8855_switch_of_match);
+
+static struct platform_driver an8855_switch_driver = {
+ .probe = an8855_switch_probe,
+ .remove = an8855_switch_remove,
+ .shutdown = an8855_switch_shutdown,
+ .driver = {
+ .name = "an8855-switch",
+ .of_match_table = an8855_switch_of_match,
+ },
+};
+module_platform_driver(an8855_switch_driver);
+
+MODULE_AUTHOR("Min Yao <min.yao@airoha.com>");
+MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
+MODULE_DESCRIPTION("Driver for Airoha AN8855 Switch");
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/dsa/mediatek/an8855.h b/drivers/net/dsa/mediatek/an8855.h
new file mode 100644
index 000000000000..85003e568450
--- /dev/null
+++ b/drivers/net/dsa/mediatek/an8855.h
@@ -0,0 +1,755 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2023 Min Yao <min.yao@airoha.com>
+ * Copyright (C) 2024 Christian Marangi <ansuelsmth@gmail.com>
+ */
+
+#ifndef __AN8855_H
+#define __AN8855_H
+
+#include <linux/bitfield.h>
+
+#include "mt7530-lib.h"
+
+#define AN8855_NUM_PORTS 6
+#define AN8855_CPU_PORT 5
+#define AN8855_NUM_FDB_RECORDS 2048
+#define AN8855_GPHY_SMI_ADDR_DEFAULT 1
+#define AN8855_PORT_VID_DEFAULT 0
+
+#define MTK_TAG_LEN 4
+#define AN8855_MAX_MTU (15360 - ETH_HLEN - ETH_FCS_LEN - MTK_TAG_LEN)
+
+#define AN8855_L2_AGING_MS_CONSTANT 1024
+
+#define AN8855_TX_LPI_UNIT 2 /* us */
+
+/* AN8855_SCU 0x10000000 */
+#define AN8855_RG_GPIO_LED_MODE 0x10000054
+#define AN8855_RG_GPIO_LED_SEL(i) (0x10000000 + (0x0058 + ((i) * 4)))
+#define AN8855_RG_INTB_MODE 0x10000080
+#define AN8855_RG_RGMII_TXCK_C 0x100001d0
+
+#define AN8855_PKG_SEL 0x10000094
+#define AN8855_PAG_SEL_AN8855H 0x2
+
+#define AN8855_RG_GPIO_L_INV 0x10000010
+#define AN8855_RG_GPIO_CTRL 0x1000a300
+#define AN8855_RG_GPIO_DATA 0x1000a304
+#define AN8855_RG_GPIO_OE 0x1000a314
+
+/* Register for system reset */
+#define AN8855_RST_CTRL 0x100050c0
+#define AN8855_SYS_CTRL_SYS_RST BIT(31)
+
+#define AN8855_INT_MASK 0x100050f0
+#define AN8855_INT_SYS BIT(15)
+
+#define AN8855_RG_CLK_CPU_ICG 0x10005034
+#define AN8855_MCU_ENABLE BIT(3)
+
+#define AN8855_RG_TIMER_CTL 0x1000a100
+#define AN8855_WDOG_ENABLE BIT(25)
+
+#define AN8855_RG_GDMP_RAM 0x10010000
+
+/* Registers to mac forward control for unknown frames */
+#define AN8855_MFC 0x10200010
+#define AN8855_CPU_EN BIT(15)
+#define AN8855_CPU_PORT_IDX GENMASK(12, 8)
+
+#define AN8855_PAC 0x10200024
+#define AN8855_TAG_PAE_MANG_FR BIT(30)
+#define AN8855_TAG_PAE_BPDU_FR BIT(28)
+#define AN8855_TAG_PAE_EG_TAG GENMASK(27, 25)
+#define AN8855_TAG_PAE_LKY_VLAN BIT(24)
+#define AN8855_TAG_PAE_PRI_HIGH BIT(23)
+#define AN8855_TAG_PAE_MIR GENMASK(20, 19)
+#define AN8855_TAG_PAE_PORT_FW GENMASK(18, 16)
+#define AN8855_PAE_MANG_FR BIT(14)
+#define AN8855_PAE_BPDU_FR BIT(12)
+#define AN8855_PAE_EG_TAG GENMASK(11, 9)
+#define AN8855_PAE_LKY_VLAN BIT(8)
+#define AN8855_PAE_PRI_HIGH BIT(7)
+#define AN8855_PAE_MIR GENMASK(4, 3)
+#define AN8855_PAE_PORT_FW GENMASK(2, 0)
+
+#define AN8855_RGAC1 0x10200028
+#define AN8855_R02_MANG_FR BIT(30)
+#define AN8855_R02_BPDU_FR BIT(28)
+#define AN8855_R02_EG_TAG GENMASK(27, 25)
+#define AN8855_R02_LKY_VLAN BIT(24)
+#define AN8855_R02_PRI_HIGH BIT(23)
+#define AN8855_R02_MIR GENMASK(20, 19)
+#define AN8855_R02_PORT_FW GENMASK(18, 16)
+#define AN8855_R01_MANG_FR BIT(14)
+#define AN8855_R01_BPDU_FR BIT(12)
+#define AN8855_R01_EG_TAG GENMASK(11, 9)
+#define AN8855_R01_LKY_VLAN BIT(8)
+#define AN8855_R01_PRI_HIGH BIT(7)
+#define AN8855_R01_MIR GENMASK(4, 3)
+#define AN8855_R01_PORT_FW GENMASK(2, 0)
+
+#define AN8855_RGAC2 0x1020002c
+#define AN8855_R0E_MANG_FR BIT(30)
+#define AN8855_R0E_BPDU_FR BIT(28)
+#define AN8855_R0E_EG_TAG GENMASK(27, 25)
+#define AN8855_R0E_LKY_VLAN BIT(24)
+#define AN8855_R0E_PRI_HIGH BIT(23)
+#define AN8855_R0E_MIR GENMASK(20, 19)
+#define AN8855_R0E_PORT_FW GENMASK(18, 16)
+#define AN8855_R03_MANG_FR BIT(14)
+#define AN8855_R03_BPDU_FR BIT(12)
+#define AN8855_R03_EG_TAG GENMASK(11, 9)
+#define AN8855_R03_LKY_VLAN BIT(8)
+#define AN8855_R03_PRI_HIGH BIT(7)
+#define AN8855_R03_MIR GENMASK(4, 3)
+#define AN8855_R03_PORT_FW GENMASK(2, 0)
+
+#define AN8855_AAC 0x102000a0
+#define AN8855_MAC_AUTO_FLUSH BIT(28)
+/* Control Address Table Age time.
+ * (AN8855_AGE_CNT + 1) * ( AN8855_AGE_UNIT + 1 ) * AN8855_L2_AGING_MS_CONSTANT
+ */
+#define AN8855_AGE_CNT GENMASK(20, 12)
+/* Value in seconds. Value is always incremented of 1 */
+#define AN8855_AGE_UNIT GENMASK(10, 0)
+
+/* Registers for ARL Unknown Unicast Forward control */
+#define AN8855_UNUF 0x102000b4
+
+/* Registers for ARL Unknown Multicast Forward control */
+#define AN8855_UNMF 0x102000b8
+
+/* Registers for ARL Broadcast forward control */
+#define AN8855_BCF 0x102000bc
+
+/* Registers for port address age disable */
+#define AN8855_AGDIS 0x102000c0
+
+/* Registers for mirror port control */
+#define AN8855_MIR 0x102000cc
+#define AN8855_MIRROR_EN BIT(7)
+#define AN8855_MIRROR_PORT GENMASK(4, 0)
+
+/* Registers for BPDU and PAE frame control*/
+#define AN8855_BPC 0x102000d0
+#define AN8855_BPDU_MANG_FR BIT(14)
+#define AN8855_BPDU_BPDU_FR BIT(12)
+#define AN8855_BPDU_EG_TAG GENMASK(11, 9)
+#define AN8855_BPDU_LKY_VLAN BIT(8)
+#define AN8855_BPDU_PRI_HIGH BIT(7)
+#define AN8855_BPDU_MIR GENMASK(4, 3)
+#define AN8855_BPDU_PORT_FW GENMASK(2, 0)
+
+/* Registers for IP Unknown Multicast Forward control */
+#define AN8855_UNIPMF 0x102000dc
+
+enum an8855_bpdu_port_fw {
+ AN8855_BPDU_FOLLOW_MFC = 0,
+ AN8855_BPDU_CPU_EXCLUDE = 4,
+ AN8855_BPDU_CPU_INCLUDE = 5,
+ AN8855_BPDU_CPU_ONLY = 6,
+ AN8855_BPDU_DROP = 7,
+};
+
+/* Register for address table control */
+#define AN8855_ATC 0x10200300
+#define AN8855_ATC_BUSY BIT(31)
+#define AN8855_ATC_HASH GENMASK(24, 16)
+#define AN8855_ATC_HIT GENMASK(15, 12)
+#define AN8855_ATC_MAT_MASK GENMASK(11, 7)
+#define AN8855_ATC_MAT(x) FIELD_PREP(AN8855_ATC_MAT_MASK, x)
+#define AN8855_ATC_SAT GENMASK(5, 4)
+#define AN8855_ATC_CMD GENMASK(2, 0)
+
+enum an8855_fdb_mat_cmds {
+ AN8855_FDB_MAT_ALL = 0,
+ AN8855_FDB_MAT_MAC, /* All MAC address */
+ AN8855_FDB_MAT_DYNAMIC_MAC, /* All Dynamic MAC address */
+ AN8855_FDB_MAT_STATIC_MAC, /* All Static Mac Address */
+ AN8855_FDB_MAT_DIP, /* All DIP/GA address */
+ AN8855_FDB_MAT_DIP_IPV4, /* All DIP/GA IPv4 address */
+ AN8855_FDB_MAT_DIP_IPV6, /* All DIP/GA IPv6 address */
+ AN8855_FDB_MAT_DIP_SIP, /* All DIP_SIP address */
+ AN8855_FDB_MAT_DIP_SIP_IPV4, /* All DIP_SIP IPv4 address */
+ AN8855_FDB_MAT_DIP_SIP_IPV6, /* All DIP_SIP IPv6 address */
+ AN8855_FDB_MAT_MAC_CVID, /* All MAC address with CVID */
+ AN8855_FDB_MAT_MAC_FID, /* All MAC address with Filter ID */
+ AN8855_FDB_MAT_MAC_PORT, /* All MAC address with port */
+ AN8855_FDB_MAT_DIP_SIP_DIP_IPV4, /* All DIP_SIP address with DIP_IPV4 */
+ AN8855_FDB_MAT_DIP_SIP_SIP_IPV4, /* All DIP_SIP address with SIP_IPV4 */
+ AN8855_FDB_MAT_DIP_SIP_DIP_IPV6, /* All DIP_SIP address with DIP_IPV6 */
+ AN8855_FDB_MAT_DIP_SIP_SIP_IPV6, /* All DIP_SIP address with SIP_IPV6 */
+ /* All MAC address with MAC type (dynamic or static) with CVID */
+ AN8855_FDB_MAT_MAC_TYPE_CVID,
+ /* All MAC address with MAC type (dynamic or static) with Filter ID */
+ AN8855_FDB_MAT_MAC_TYPE_FID,
+ /* All MAC address with MAC type (dynamic or static) with port */
+ AN8855_FDB_MAT_MAC_TYPE_PORT,
+};
+
+/* Registers for address table access */
+#define AN8855_ATA1 0x10200304
+#define AN8855_ATA1_MAC0 GENMASK(31, 24)
+#define AN8855_ATA1_MAC1 GENMASK(23, 16)
+#define AN8855_ATA1_MAC2 GENMASK(15, 8)
+#define AN8855_ATA1_MAC3 GENMASK(7, 0)
+#define AN8855_ATA2 0x10200308
+#define AN8855_ATA2_MAC4 GENMASK(31, 24)
+#define AN8855_ATA2_MAC5 GENMASK(23, 16)
+#define AN8855_ATA2_UNAUTH BIT(10)
+#define AN8855_ATA2_TYPE BIT(9) /* 1: dynamic, 0: static */
+#define AN8855_ATA2_AGE GENMASK(8, 0)
+
+/* Register for address table write data */
+#define AN8855_ATWD 0x10200324
+#define AN8855_ATWD_FID GENMASK(31, 28)
+#define AN8855_ATWD_VID GENMASK(27, 16)
+#define AN8855_ATWD_IVL BIT(15)
+#define AN8855_ATWD_EG_TAG GENMASK(14, 12)
+#define AN8855_ATWD_SA_MIR GENMASK(9, 8)
+#define AN8855_ATWD_SA_FWD GENMASK(7, 5)
+#define AN8855_ATWD_UPRI GENMASK(4, 2)
+#define AN8855_ATWD_LEAKY BIT(1)
+#define AN8855_ATWD_VLD_MASK BIT(0) /* vid LOAD */
+#define AN8855_ATWD2 0x10200328
+#define AN8855_ATWD2_PORT GENMASK(7, 0)
+
+/* Registers for table search read address */
+#define AN8855_ATRDS 0x10200330
+#define AN8855_ATRD_SEL GENMASK(1, 0)
+#define AN8855_ATRD0 0x10200334
+#define AN8855_ATRD0_FID GENMASK(28, 25)
+#define AN8855_ATRD0_VID GENMASK(21, 10)
+#define AN8855_ATRD0_IVL BIT(9)
+#define AN8855_ATRD0_TYPE GENMASK(4, 3)
+#define AN8855_ATRD0_ARP GENMASK(2, 1)
+#define AN8855_ATRD0_LIVE BIT(0)
+#define AN8855_ATRD1 0x10200338
+#define AN8855_ATRD1_MAC4 GENMASK(31, 24)
+#define AN8855_ATRD1_MAC5 GENMASK(23, 16)
+#define AN8855_ATRD1_AGING GENMASK(11, 3)
+#define AN8855_ATRD2 0x1020033c
+#define AN8855_ATRD2_MAC0 GENMASK(31, 24)
+#define AN8855_ATRD2_MAC1 GENMASK(23, 16)
+#define AN8855_ATRD2_MAC2 GENMASK(15, 8)
+#define AN8855_ATRD2_MAC3 GENMASK(7, 0)
+#define AN8855_ATRD3 0x10200340
+#define AN8855_ATRD3_PORTMASK GENMASK(7, 0)
+
+enum an8855_fdb_type {
+ AN8855_MAC_TB_TY_MAC = 0,
+ AN8855_MAC_TB_TY_DIP = 1,
+ AN8855_MAC_TB_TY_DIP_SIP = 2,
+};
+
+/* Register for vlan table control */
+#define AN8855_VTCR 0x10200600
+#define AN8855_VTCR_BUSY BIT(31)
+#define AN8855_VTCR_FUNC GENMASK(15, 12)
+#define AN8855_VTCR_VID GENMASK(11, 0)
+
+enum an8855_vlan_cmd {
+ /* Read/Write the specified VID entry from VAWD register based
+ * on VID.
+ */
+ AN8855_VTCR_RD_VID = 0,
+ AN8855_VTCR_WR_VID = 1,
+};
+
+/* Register for setup vlan write data */
+#define AN8855_VAWD0 0x10200604
+/* VLAN Member Control */
+#define AN8855_VA0_PORT GENMASK(31, 26)
+/* Egress Tag Control */
+#define AN8855_VA0_ETAG GENMASK(23, 12)
+#define AN8855_VA0_ETAG_PORT GENMASK(13, 12)
+#define AN8855_VA0_ETAG_PORT_SHIFT(port) ((port) * 2)
+#define AN8855_VA0_ETAG_PORT_MASK(port) (AN8855_VA0_ETAG_PORT << \
+ AN8855_VA0_ETAG_PORT_SHIFT(port))
+#define AN8855_VA0_ETAG_PORT_VAL(port, val) (FIELD_PREP(AN8855_VA0_ETAG_PORT, (val)) << \
+ AN8855_VA0_ETAG_PORT_SHIFT(port))
+#define AN8855_VA0_EG_CON BIT(11)
+#define AN8855_VA0_VTAG_EN BIT(10) /* Per VLAN Egress Tag Control */
+#define AN8855_VA0_IVL_MAC BIT(5) /* Independent VLAN Learning */
+#define AN8855_VA0_FID GENMASK(4, 1)
+#define AN8855_VA0_VLAN_VALID BIT(0) /* VLAN Entry Valid */
+#define AN8855_VAWD1 0x10200608
+#define AN8855_VA1_PORT_STAG BIT(1)
+
+enum an8855_fid {
+ AN8855_FID_STANDALONE = 0,
+ AN8855_FID_BRIDGED = 1,
+};
+
+/* Same register field of VAWD0 */
+#define AN8855_VARD0 0x10200618
+
+enum an8855_vlan_egress_attr {
+ AN8855_VLAN_EGRESS_UNTAG = 0,
+ AN8855_VLAN_EGRESS_TAG = 2,
+ AN8855_VLAN_EGRESS_STACK = 3,
+};
+
+/* Register for port STP state control */
+#define AN8855_SSP 0x10208000
+#define AN8855_SSP_P(x) (AN8855_SSP + ((x) * 0x200))
+/* Up to 16 FID supported, each with the same mask */
+#define AN8855_FID_PST GENMASK(1, 0)
+#define AN8855_FID_PST_SHIFT(fid) (2 * (fid))
+#define AN8855_FID_PST_MASK(fid) (AN8855_FID_PST << \
+ AN8855_FID_PST_SHIFT(fid))
+#define AN8855_FID_PST_VAL(fid, val) (FIELD_PREP(AN8855_FID_PST, (val)) << \
+ AN8855_FID_PST_SHIFT(fid))
+
+enum an8855_stp_state {
+ AN8855_STP_DISABLED = 0,
+ AN8855_STP_BLOCKING = 1,
+ AN8855_STP_LISTENING = AN8855_STP_BLOCKING,
+ AN8855_STP_LEARNING = 2,
+ AN8855_STP_FORWARDING = 3
+};
+
+/* Register for port control */
+#define AN8855_PCR 0x10208004
+#define AN8855_PCR_P(x) (AN8855_PCR + ((x) * 0x200))
+#define AN8855_EG_TAG GENMASK(29, 28)
+#define AN8855_PORT_PRI GENMASK(26, 24)
+#define AN8855_PORT_TX_MIR BIT(20)
+#define AN8855_PORT_RX_MIR BIT(16)
+#define AN8855_PORT_VLAN GENMASK(1, 0)
+
+enum an8855_port_mode {
+ /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */
+ AN8855_PORT_MATRIX_MODE = 0,
+
+ /* Fallback Mode: Forward received frames with ingress ports that do
+ * not belong to the VLAN member. Frames whose VID is not listed on
+ * the VLAN table are forwarded by the PCR_MATRIX members.
+ */
+ AN8855_PORT_FALLBACK_MODE = 1,
+
+ /* Check Mode: Forward received frames whose ingress do not
+ * belong to the VLAN member. Discard frames if VID ismiddes on the
+ * VLAN table.
+ */
+ AN8855_PORT_CHECK_MODE = 2,
+
+ /* Security Mode: Discard any frame due to ingress membership
+ * violation or VID missed on the VLAN table.
+ */
+ AN8855_PORT_SECURITY_MODE = 3,
+};
+
+/* Register for port security control */
+#define AN8855_PSC 0x1020800c
+#define AN8855_PSC_P(x) (AN8855_PSC + ((x) * 0x200))
+#define AN8855_SA_DIS BIT(4)
+
+/* Register for port vlan control */
+#define AN8855_PVC 0x10208010
+#define AN8855_PVC_P(x) (AN8855_PVC + ((x) * 0x200))
+#define AN8855_PORT_SPEC_REPLACE_MODE BIT(11)
+#define AN8855_PVC_EG_TAG GENMASK(10, 8)
+#define AN8855_VLAN_ATTR GENMASK(7, 6)
+#define AN8855_PORT_SPEC_TAG BIT(5)
+#define AN8855_ACC_FRM GENMASK(1, 0)
+
+enum an8855_vlan_port_eg_tag {
+ AN8855_VLAN_EG_DISABLED = 0,
+ AN8855_VLAN_EG_CONSISTENT = 1,
+ AN8855_VLAN_EG_UNTAGGED = 4,
+ AN8855_VLAN_EG_SWAP = 5,
+ AN8855_VLAN_EG_TAGGED = 6,
+ AN8855_VLAN_EG_STACK = 7,
+};
+
+enum an8855_vlan_port_attr {
+ AN8855_VLAN_USER = 0,
+ AN8855_VLAN_STACK = 1,
+ AN8855_VLAN_TRANSPARENT = 3,
+};
+
+enum an8855_vlan_port_acc_frm {
+ AN8855_VLAN_ACC_ALL = 0,
+ AN8855_VLAN_ACC_TAGGED = 1,
+ AN8855_VLAN_ACC_UNTAGGED = 2,
+};
+
+#define AN8855_PPBV1 0x10208014
+#define AN8855_PPBV1_P(x) (AN8855_PPBV1 + ((x) * 0x200))
+#define AN8855_PPBV_G0_PORT_VID GENMASK(11, 0)
+
+#define AN8855_PORTMATRIX 0x10208044
+#define AN8855_PORTMATRIX_P(x) (AN8855_PORTMATRIX + ((x) * 0x200))
+#define AN8855_PORTMATRIX_MASK GENMASK(5, 0)
+/* Port matrix without the CPU port that should never be removed */
+#define AN8855_USER_PORTMATRIX GENMASK(4, 0)
+
+/* Register for port PVID */
+#define AN8855_PVID 0x10208048
+#define AN8855_PVID_P(x) (AN8855_PVID + ((x) * 0x200))
+#define AN8855_G0_PORT_VID GENMASK(11, 0)
+
+/* Register for port MAC control register */
+#define AN8855_PMCR_P(x) (0x10210000 + ((x) * 0x200))
+#define AN8855_PMCR_FORCE_MODE BIT(31)
+#define AN8855_PMCR_FORCE_SPEED GENMASK(30, 28)
+#define AN8855_PMCR_FORCE_SPEED_5000 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x4)
+#define AN8855_PMCR_FORCE_SPEED_2500 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x3)
+#define AN8855_PMCR_FORCE_SPEED_1000 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x2)
+#define AN8855_PMCR_FORCE_SPEED_100 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x1)
+#define AN8855_PMCR_FORCE_SPEED_10 FIELD_PREP_CONST(AN8855_PMCR_FORCE_SPEED, 0x0)
+#define AN8855_PMCR_FORCE_FDX BIT(25)
+#define AN8855_PMCR_FORCE_LNK BIT(24)
+#define AN8855_PMCR_IFG_XMIT GENMASK(21, 20)
+#define AN8855_PMCR_EXT_PHY BIT(19)
+#define AN8855_PMCR_MAC_MODE BIT(18)
+#define AN8855_PMCR_TX_EN BIT(16)
+#define AN8855_PMCR_RX_EN BIT(15)
+#define AN8855_PMCR_BACKOFF_EN BIT(12)
+#define AN8855_PMCR_BACKPR_EN BIT(11)
+#define AN8855_PMCR_FORCE_EEE5G BIT(9)
+#define AN8855_PMCR_FORCE_EEE2P5G BIT(8)
+#define AN8855_PMCR_FORCE_EEE1G BIT(7)
+#define AN8855_PMCR_FORCE_EEE100 BIT(6)
+#define AN8855_PMCR_RX_FC_EN BIT(5)
+#define AN8855_PMCR_TX_FC_EN BIT(4)
+
+#define AN8855_PMSR_P(x) (0x10210010 + (x) * 0x200)
+#define AN8855_PMSR_SPEED GENMASK(30, 28)
+#define AN8855_PMSR_SPEED_5000 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x4)
+#define AN8855_PMSR_SPEED_2500 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x3)
+#define AN8855_PMSR_SPEED_1000 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x2)
+#define AN8855_PMSR_SPEED_100 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x1)
+#define AN8855_PMSR_SPEED_10 FIELD_PREP_CONST(AN8855_PMSR_SPEED, 0x0)
+#define AN8855_PMSR_DPX BIT(25)
+#define AN8855_PMSR_LNK BIT(24)
+#define AN8855_PMSR_EEE1G BIT(7)
+#define AN8855_PMSR_EEE100M BIT(6)
+#define AN8855_PMSR_RX_FC BIT(5)
+#define AN8855_PMSR_TX_FC BIT(4)
+
+#define AN8855_PMEEECR_P(x) (0x10210004 + (x) * 0x200)
+#define AN8855_LPI_MODE_EN BIT(31)
+#define AN8855_WAKEUP_TIME_2500 GENMASK(23, 16)
+#define AN8855_WAKEUP_TIME_1000 GENMASK(15, 8)
+#define AN8855_WAKEUP_TIME_100 GENMASK(7, 0)
+#define AN8855_PMEEECR2_P(x) (0x10210008 + (x) * 0x200)
+#define AN8855_WAKEUP_TIME_5000 GENMASK(7, 0)
+
+#define AN8855_GMACCR 0x10213e00
+#define AN8855_MAX_RX_JUMBO GENMASK(7, 4)
+/* 2K for 0x0, 0x1, 0x2 */
+#define AN8855_MAX_RX_JUMBO_2K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x0)
+#define AN8855_MAX_RX_JUMBO_3K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x3)
+#define AN8855_MAX_RX_JUMBO_4K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x4)
+#define AN8855_MAX_RX_JUMBO_5K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x5)
+#define AN8855_MAX_RX_JUMBO_6K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x6)
+#define AN8855_MAX_RX_JUMBO_7K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x7)
+#define AN8855_MAX_RX_JUMBO_8K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x8)
+#define AN8855_MAX_RX_JUMBO_9K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0x9)
+#define AN8855_MAX_RX_JUMBO_12K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0xa)
+#define AN8855_MAX_RX_JUMBO_15K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0xb)
+#define AN8855_MAX_RX_JUMBO_16K FIELD_PREP_CONST(AN8855_MAX_RX_JUMBO, 0xc)
+#define AN8855_MAX_RX_PKT_LEN GENMASK(1, 0)
+#define AN8855_MAX_RX_PKT_1518_1522 FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x0)
+#define AN8855_MAX_RX_PKT_1536 FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x1)
+#define AN8855_MAX_RX_PKT_1552 FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x2)
+#define AN8855_MAX_RX_PKT_JUMBO FIELD_PREP_CONST(AN8855_MAX_RX_PKT_LEN, 0x3)
+
+#define AN8855_CKGCR 0x10213e1c
+#define AN8855_LPI_TXIDLE_THD_MASK GENMASK(31, 14)
+#define AN8855_CKG_LNKDN_PORT_STOP BIT(1)
+#define AN8855_CKG_LNKDN_GLB_STOP BIT(0)
+
+/* Register for MIB */
+#define AN8855_MIB_COUNTER 0x10214000
+#define AN8855_PORT_MIB_COUNTER(x) (AN8855_MIB_COUNTER + (x) * 0x200)
+/* Each define is an offset of AN8855_PORT_MIB_COUNTER */
+#define AN8855_PORT_MIB_TX_DROP (AN8855_MIB_COUNTER + 0x00)
+#define AN8855_PORT_MIB_TX_CRC_ERR (AN8855_MIB_COUNTER + 0x04)
+#define AN8855_PORT_MIB_TX_UNICAST (AN8855_MIB_COUNTER + 0x08)
+#define AN8855_PORT_MIB_TX_MULTICAST (AN8855_MIB_COUNTER + 0x0c)
+#define AN8855_PORT_MIB_TX_BROADCAST (AN8855_MIB_COUNTER + 0x10)
+#define AN8855_PORT_MIB_TX_COLLISION (AN8855_MIB_COUNTER + 0x14)
+#define AN8855_PORT_MIB_TX_SINGLE_COLLISION (AN8855_MIB_COUNTER + 0x18)
+#define AN8855_PORT_MIB_TX_MULTIPLE_COLLISION (AN8855_MIB_COUNTER + 0x1c)
+#define AN8855_PORT_MIB_TX_DEFERRED (AN8855_MIB_COUNTER + 0x20)
+#define AN8855_PORT_MIB_TX_LATE_COLLISION (AN8855_MIB_COUNTER + 0x24)
+#define AN8855_PORT_MIB_TX_EXCESSIVE_COLLISION (AN8855_MIB_COUNTER + 0x28)
+#define AN8855_PORT_MIB_TX_PAUSE (AN8855_MIB_COUNTER + 0x2c)
+#define AN8855_PORT_MIB_TX_PKT_SZ_64 (AN8855_MIB_COUNTER + 0x30)
+#define AN8855_PORT_MIB_TX_PKT_SZ_65_TO_127 (AN8855_MIB_COUNTER + 0x34)
+#define AN8855_PORT_MIB_TX_PKT_SZ_128_TO_255 (AN8855_MIB_COUNTER + 0x38)
+#define AN8855_PORT_MIB_TX_PKT_SZ_256_TO_511 (AN8855_MIB_COUNTER + 0x3c)
+#define AN8855_PORT_MIB_TX_PKT_SZ_512_TO_1023 (AN8855_MIB_COUNTER + 0x40)
+#define AN8855_PORT_MIB_TX_PKT_SZ_1024_TO_1518 (AN8855_MIB_COUNTER + 0x44)
+#define AN8855_PORT_MIB_TX_PKT_SZ_1519_TO_MAX (AN8855_MIB_COUNTER + 0x48)
+#define AN8855_PORT_MIB_TX_BYTES_LOW (AN8855_MIB_COUNTER + 0x4c) /* 64 bytes */
+#define AN8855_PORT_MIB_TX_BYTES_HIGH (AN8855_MIB_COUNTER + 0x50)
+#define AN8855_PORT_MIB_TX_OVERSIZE_DROP (AN8855_MIB_COUNTER + 0x54)
+#define AN8855_PORT_MIB_TX_BAD_PKT_BYTES_LOW (AN8855_MIB_COUNTER + 0x58) /* 64 bytes */
+#define AN8855_PORT_MIB_TX_BAD_PKT_BYTES_HIGH (AN8855_MIB_COUNTER + 0x5c)
+#define AN8855_PORT_MIB_RX_DROP (AN8855_MIB_COUNTER + 0x80)
+#define AN8855_PORT_MIB_RX_FILTERING (AN8855_MIB_COUNTER + 0x84)
+#define AN8855_PORT_MIB_RX_UNICAST (AN8855_MIB_COUNTER + 0x88)
+#define AN8855_PORT_MIB_RX_MULTICAST (AN8855_MIB_COUNTER + 0x8c)
+#define AN8855_PORT_MIB_RX_BROADCAST (AN8855_MIB_COUNTER + 0x90)
+#define AN8855_PORT_MIB_RX_ALIGN_ERR (AN8855_MIB_COUNTER + 0x94)
+#define AN8855_PORT_MIB_RX_CRC_ERR (AN8855_MIB_COUNTER + 0x98)
+#define AN8855_PORT_MIB_RX_UNDER_SIZE_ERR (AN8855_MIB_COUNTER + 0x9c)
+#define AN8855_PORT_MIB_RX_FRAG_ERR (AN8855_MIB_COUNTER + 0xa0)
+#define AN8855_PORT_MIB_RX_OVER_SZ_ERR (AN8855_MIB_COUNTER + 0xa4)
+#define AN8855_PORT_MIB_RX_JABBER_ERR (AN8855_MIB_COUNTER + 0xa8)
+#define AN8855_PORT_MIB_RX_PAUSE (AN8855_MIB_COUNTER + 0xac)
+#define AN8855_PORT_MIB_RX_PKT_SZ_64 (AN8855_MIB_COUNTER + 0xb0)
+#define AN8855_PORT_MIB_RX_PKT_SZ_65_TO_127 (AN8855_MIB_COUNTER + 0xb4)
+#define AN8855_PORT_MIB_RX_PKT_SZ_128_TO_255 (AN8855_MIB_COUNTER + 0xb8)
+#define AN8855_PORT_MIB_RX_PKT_SZ_256_TO_511 (AN8855_MIB_COUNTER + 0xbc)
+#define AN8855_PORT_MIB_RX_PKT_SZ_512_TO_1023 (AN8855_MIB_COUNTER + 0xc0)
+#define AN8855_PORT_MIB_RX_PKT_SZ_1024_TO_1518 (AN8855_MIB_COUNTER + 0xc4)
+#define AN8855_PORT_MIB_RX_PKT_SZ_1519_TO_MAX (AN8855_MIB_COUNTER + 0xc8)
+#define AN8855_PORT_MIB_RX_BYTES_LOW (AN8855_MIB_COUNTER + 0xcc) /* 64 bytes */
+#define AN8855_PORT_MIB_RX_BYTES_HIGH (AN8855_MIB_COUNTER + 0xd0)
+#define AN8855_PORT_MIB_RX_CTRL_DROP (AN8855_MIB_COUNTER + 0xd4)
+#define AN8855_PORT_MIB_RX_INGRESS_DROP (AN8855_MIB_COUNTER + 0xd8)
+#define AN8855_PORT_MIB_RX_ARL_DROP (AN8855_MIB_COUNTER + 0xdc)
+#define AN8855_PORT_MIB_FLOW_CONTROL_DROP (AN8855_MIB_COUNTER + 0xe0)
+#define AN8855_PORT_MIB_WRED_DROP (AN8855_MIB_COUNTER + 0xe4)
+#define AN8855_PORT_MIB_MIRROR_DROP (AN8855_MIB_COUNTER + 0xe8)
+#define AN8855_PORT_MIB_RX_BAD_PKT_BYTES_LOW (AN8855_MIB_COUNTER + 0xec) /* 64 bytes */
+#define AN8855_PORT_MIB_RX_BAD_PKT_BYTES_HIGH (AN8855_MIB_COUNTER + 0xf0)
+#define AN8855_PORT_MIB_RXS_FLOW_SAMPLING_PKT_DROP (AN8855_MIB_COUNTER + 0xf4)
+#define AN8855_PORT_MIB_RXS_FLOW_TOTAL_PKT_DROP (AN8855_MIB_COUNTER + 0xf8)
+#define AN8855_PORT_MIB_PORT_CONTROL_DROP (AN8855_MIB_COUNTER + 0xfc)
+#define AN8855_MIB_CCR 0x10213e30
+#define AN8855_CCR_MIB_ENABLE BIT(31)
+#define AN8855_CCR_RX_OCT_CNT_GOOD BIT(7)
+#define AN8855_CCR_RX_OCT_CNT_BAD BIT(6)
+#define AN8855_CCR_TX_OCT_CNT_GOOD BIT(5)
+#define AN8855_CCR_TX_OCT_CNT_BAD BIT(4)
+#define AN8855_CCR_RX_OCT_CNT_GOOD_2 BIT(3)
+#define AN8855_CCR_RX_OCT_CNT_BAD_2 BIT(2)
+#define AN8855_CCR_TX_OCT_CNT_GOOD_2 BIT(1)
+#define AN8855_CCR_TX_OCT_CNT_BAD_2 BIT(0)
+#define AN8855_CCR_MIB_ACTIVATE (AN8855_CCR_MIB_ENABLE | \
+ AN8855_CCR_RX_OCT_CNT_GOOD | \
+ AN8855_CCR_RX_OCT_CNT_BAD | \
+ AN8855_CCR_TX_OCT_CNT_GOOD | \
+ AN8855_CCR_TX_OCT_CNT_BAD | \
+ AN8855_CCR_RX_OCT_CNT_BAD_2 | \
+ AN8855_CCR_TX_OCT_CNT_BAD_2)
+#define AN8855_MIB_CLR 0x10213e34
+#define AN8855_MIB_PORT6_CLR BIT(6)
+#define AN8855_MIB_PORT5_CLR BIT(5)
+#define AN8855_MIB_PORT4_CLR BIT(4)
+#define AN8855_MIB_PORT3_CLR BIT(3)
+#define AN8855_MIB_PORT2_CLR BIT(2)
+#define AN8855_MIB_PORT1_CLR BIT(1)
+#define AN8855_MIB_PORT0_CLR BIT(0)
+
+/* HSGMII/SGMII Configuration register */
+/* AN8855_HSGMII_AN_CSR_BASE 0x10220000 */
+#define AN8855_SGMII_REG_AN0 0x10220000
+/* AN8855_SGMII_AN_ENABLE BMCR_ANENABLE */
+/* AN8855_SGMII_AN_RESTART BMCR_ANRESTART */
+#define AN8855_SGMII_REG_AN_13 0x10220034
+#define AN8855_SGMII_REMOTE_FAULT_DIS BIT(8)
+#define AN8855_SGMII_IF_MODE GENMASK(5, 0)
+#define AN8855_SGMII_REG_AN_FORCE_CL37 0x10220060
+#define AN8855_RG_FORCE_AN_DONE BIT(0)
+
+/* AN8855_HSGMII_CSR_PCS_BASE 0x10220000 */
+#define AN8855_RG_HSGMII_PCS_CTROL_1 0x10220a00
+#define AN8855_RG_TBI_10B_MODE BIT(30)
+#define AN8855_RG_AN_SGMII_MODE_FORCE 0x10220a24
+#define AN8855_RG_FORCE_CUR_SGMII_MODE GENMASK(5, 4)
+#define AN8855_RG_FORCE_CUR_SGMII_SEL BIT(0)
+
+/* AN8855_MULTI_SGMII_CSR_BASE 0x10224000 */
+#define AN8855_SGMII_STS_CTRL_0 0x10224018
+#define AN8855_RG_LINK_MODE_P0 GENMASK(5, 4)
+#define AN8855_RG_LINK_MODE_P0_SPEED_2500 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x3)
+#define AN8855_RG_LINK_MODE_P0_SPEED_1000 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x2)
+#define AN8855_RG_LINK_MODE_P0_SPEED_100 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x1)
+#define AN8855_RG_LINK_MODE_P0_SPEED_10 FIELD_PREP_CONST(AN8855_RG_LINK_MODE_P0, 0x0)
+#define AN8855_RG_FORCE_SPD_MODE_P0 BIT(2)
+#define AN8855_MSG_RX_CTRL_0 0x10224100
+#define AN8855_MSG_RX_LIK_STS_0 0x10224514
+#define AN8855_RG_DPX_STS_P3 BIT(24)
+#define AN8855_RG_DPX_STS_P2 BIT(16)
+#define AN8855_RG_EEE1G_STS_P1 BIT(12)
+#define AN8855_RG_DPX_STS_P1 BIT(8)
+#define AN8855_RG_TXFC_STS_P0 BIT(2)
+#define AN8855_RG_RXFC_STS_P0 BIT(1)
+#define AN8855_RG_DPX_STS_P0 BIT(0)
+#define AN8855_MSG_RX_LIK_STS_2 0x1022451c
+#define AN8855_RG_RXFC_AN_BYPASS_P3 BIT(11)
+#define AN8855_RG_RXFC_AN_BYPASS_P2 BIT(10)
+#define AN8855_RG_RXFC_AN_BYPASS_P1 BIT(9)
+#define AN8855_RG_TXFC_AN_BYPASS_P3 BIT(7)
+#define AN8855_RG_TXFC_AN_BYPASS_P2 BIT(6)
+#define AN8855_RG_TXFC_AN_BYPASS_P1 BIT(5)
+#define AN8855_RG_DPX_AN_BYPASS_P3 BIT(3)
+#define AN8855_RG_DPX_AN_BYPASS_P2 BIT(2)
+#define AN8855_RG_DPX_AN_BYPASS_P1 BIT(1)
+#define AN8855_RG_DPX_AN_BYPASS_P0 BIT(0)
+#define AN8855_PHY_RX_FORCE_CTRL_0 0x10224520
+#define AN8855_RG_FORCE_TXC_SEL BIT(4)
+
+/* AN8855_XFI_CSR_PCS_BASE 0x10225000 */
+#define AN8855_RG_USXGMII_AN_CONTROL_0 0x10225bf8
+
+/* AN8855_MULTI_PHY_RA_CSR_BASE 0x10226000 */
+#define AN8855_RG_RATE_ADAPT_CTRL_0 0x10226000
+#define AN8855_RG_RATE_ADAPT_RX_BYPASS BIT(27)
+#define AN8855_RG_RATE_ADAPT_TX_BYPASS BIT(26)
+#define AN8855_RG_RATE_ADAPT_RX_EN BIT(4)
+#define AN8855_RG_RATE_ADAPT_TX_EN BIT(0)
+#define AN8855_RATE_ADP_P0_CTRL_0 0x10226100
+#define AN8855_RG_P0_DIS_MII_MODE BIT(31)
+#define AN8855_RG_P0_MII_MODE BIT(28)
+#define AN8855_RG_P0_MII_RA_RX_EN BIT(3)
+#define AN8855_RG_P0_MII_RA_TX_EN BIT(2)
+#define AN8855_RG_P0_MII_RA_RX_MODE BIT(1)
+#define AN8855_RG_P0_MII_RA_TX_MODE BIT(0)
+#define AN8855_MII_RA_AN_ENABLE 0x10226300
+#define AN8855_RG_P0_RA_AN_EN BIT(0)
+
+/* AN8855_QP_DIG_CSR_BASE 0x1022a000 */
+#define AN8855_QP_CK_RST_CTRL_4 0x1022a310
+#define AN8855_QP_DIG_MODE_CTRL_0 0x1022a324
+#define AN8855_RG_SGMII_MODE GENMASK(5, 4)
+#define AN8855_RG_SGMII_AN_EN BIT(0)
+#define AN8855_QP_DIG_MODE_CTRL_1 0x1022a330
+#define AN8855_RG_TPHY_SPEED GENMASK(3, 2)
+
+/* AN8855_SERDES_WRAPPER_BASE 0x1022c000 */
+#define AN8855_USGMII_CTRL_0 0x1022c000
+
+/* AN8855_QP_PMA_TOP_BASE 0x1022e000 */
+#define AN8855_PON_RXFEDIG_CTRL_0 0x1022e100
+#define AN8855_RG_QP_EQ_RX500M_CK_SEL BIT(12)
+#define AN8855_PON_RXFEDIG_CTRL_9 0x1022e124
+#define AN8855_RG_QP_EQ_LEQOSC_DLYCNT GENMASK(2, 0)
+
+#define AN8855_SS_LCPLL_PWCTL_SETTING_2 0x1022e208
+#define AN8855_RG_NCPO_ANA_MSB GENMASK(17, 16)
+#define AN8855_SS_LCPLL_TDC_FLT_2 0x1022e230
+#define AN8855_RG_LCPLL_NCPO_VALUE GENMASK(30, 0)
+#define AN8855_SS_LCPLL_TDC_FLT_5 0x1022e23c
+#define AN8855_RG_LCPLL_NCPO_CHG BIT(24)
+#define AN8855_SS_LCPLL_TDC_PCW_1 0x1022e248
+#define AN8855_RG_LCPLL_PON_HRDDS_PCW_NCPO_GPON GENMASK(30, 0)
+#define AN8855_INTF_CTRL_8 0x1022e320
+#define AN8855_INTF_CTRL_9 0x1022e324
+#define AN8855_INTF_CTRL_10 0x1022e328
+#define AN8855_RG_DA_QP_TX_FIR_C2_SEL BIT(29)
+#define AN8855_RG_DA_QP_TX_FIR_C2_FORCE GENMASK(28, 24)
+#define AN8855_RG_DA_QP_TX_FIR_C1_SEL BIT(21)
+#define AN8855_RG_DA_QP_TX_FIR_C1_FORCE GENMASK(20, 16)
+#define AN8855_INTF_CTRL_11 0x1022e32c
+#define AN8855_RG_DA_QP_TX_FIR_C0B_SEL BIT(6)
+#define AN8855_RG_DA_QP_TX_FIR_C0B_FORCE GENMASK(5, 0)
+#define AN8855_PLL_CTRL_0 0x1022e400
+#define AN8855_RG_PHYA_AUTO_INIT BIT(0)
+#define AN8855_PLL_CTRL_2 0x1022e408
+#define AN8855_RG_DA_QP_PLL_SDM_IFM_INTF BIT(30)
+#define AN8855_RG_DA_QP_PLL_RICO_SEL_INTF BIT(29)
+#define AN8855_RG_DA_QP_PLL_POSTDIV_EN_INTF BIT(28)
+#define AN8855_RG_DA_QP_PLL_PHY_CK_EN_INTF BIT(27)
+#define AN8855_RG_DA_QP_PLL_PFD_OFFSET_EN_INTRF BIT(26)
+#define AN8855_RG_DA_QP_PLL_PFD_OFFSET_INTF GENMASK(25, 24)
+#define AN8855_RG_DA_QP_PLL_PCK_SEL_INTF BIT(22)
+#define AN8855_RG_DA_QP_PLL_KBAND_PREDIV_INTF GENMASK(21, 20)
+#define AN8855_RG_DA_QP_PLL_IR_INTF GENMASK(19, 16)
+#define AN8855_RG_DA_QP_PLL_ICOIQ_EN_INTF BIT(14)
+#define AN8855_RG_DA_QP_PLL_FBKSEL_INTF GENMASK(13, 12)
+#define AN8855_RG_DA_QP_PLL_BR_INTF GENMASK(10, 8)
+#define AN8855_RG_DA_QP_PLL_BPD_INTF GENMASK(7, 6)
+#define AN8855_RG_DA_QP_PLL_BPA_INTF GENMASK(4, 2)
+#define AN8855_RG_DA_QP_PLL_BC_INTF GENMASK(1, 0)
+#define AN8855_PLL_CTRL_3 0x1022e40c
+#define AN8855_RG_DA_QP_PLL_SSC_PERIOD_INTF GENMASK(31, 16)
+#define AN8855_RG_DA_QP_PLL_SSC_DELTA_INTF GENMASK(15, 0)
+#define AN8855_PLL_CTRL_4 0x1022e410
+#define AN8855_RG_DA_QP_PLL_SDM_HREN_INTF GENMASK(4, 3)
+#define AN8855_RG_DA_QP_PLL_ICOLP_EN_INTF BIT(2)
+#define AN8855_RG_DA_QP_PLL_SSC_DIR_DLY_INTF GENMASK(1, 0)
+#define AN8855_PLL_CK_CTRL_0 0x1022e414
+#define AN8855_RG_DA_QP_PLL_TDC_TXCK_SEL_INTF BIT(9)
+#define AN8855_RG_DA_QP_PLL_SDM_DI_EN_INTF BIT(8)
+#define AN8855_RX_DLY_0 0x1022e614
+#define AN8855_RG_QP_RX_SAOSC_EN_H_DLY GENMASK(13, 8)
+#define AN8855_RG_QP_RX_PI_CAL_EN_H_DLY GENMASK(7, 0)
+#define AN8855_RX_CTRL_2 0x1022e630
+#define AN8855_RG_QP_RX_EQ_EN_H_DLY GENMASK(28, 16)
+#define AN8855_RX_CTRL_5 0x1022e63c
+#define AN8855_RG_FREDET_CHK_CYCLE GENMASK(29, 10)
+#define AN8855_RX_CTRL_6 0x1022e640
+#define AN8855_RG_FREDET_GOLDEN_CYCLE GENMASK(19, 0)
+#define AN8855_RX_CTRL_7 0x1022e644
+#define AN8855_RG_FREDET_TOLERATE_CYCLE GENMASK(19, 0)
+#define AN8855_RX_CTRL_8 0x1022e648
+#define AN8855_RG_DA_QP_SAOSC_DONE_TIME GENMASK(27, 16)
+#define AN8855_RG_DA_QP_LEQOS_EN_TIME GENMASK(14, 0)
+#define AN8855_RX_CTRL_26 0x1022e690
+#define AN8855_RG_QP_EQ_RETRAIN_ONLY_EN BIT(26)
+#define AN8855_RG_LINK_NE_EN BIT(24)
+#define AN8855_RG_LINK_ERRO_EN BIT(23)
+#define AN8855_RX_CTRL_42 0x1022e6d0
+#define AN8855_RG_QP_EQ_EN_DLY GENMASK(12, 0)
+
+/* AN8855_QP_ANA_CSR_BASE 0x1022f000 */
+#define AN8855_RG_QP_RX_DAC_EN 0x1022f000
+#define AN8855_RG_QP_SIGDET_HF GENMASK(17, 16)
+#define AN8855_RG_QP_RXAFE_RESERVE 0x1022f004
+#define AN8855_RG_QP_CDR_PD_10B_EN BIT(11)
+#define AN8855_RG_QP_CDR_LPF_BOT_LIM 0x1022f008
+#define AN8855_RG_QP_CDR_LPF_KP_GAIN GENMASK(26, 24)
+#define AN8855_RG_QP_CDR_LPF_KI_GAIN GENMASK(22, 20)
+#define AN8855_RG_QP_CDR_LPF_MJV_LIM 0x1022f00c
+#define AN8855_RG_QP_CDR_LPF_RATIO GENMASK(5, 4)
+#define AN8855_RG_QP_CDR_LPF_SETVALUE 0x1022f014
+#define AN8855_RG_QP_CDR_PR_BUF_IN_SR GENMASK(31, 29)
+#define AN8855_RG_QP_CDR_PR_BETA_SEL GENMASK(28, 25)
+#define AN8855_RG_QP_CDR_PR_CKREF_DIV1 0x1022f018
+#define AN8855_RG_QP_CDR_PR_KBAND_DIV GENMASK(26, 24)
+#define AN8855_RG_QP_CDR_PR_DAC_BAND GENMASK(12, 8)
+#define AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE 0x1022f01c
+#define AN8855_RG_QP_CDR_PR_XFICK_EN BIT(30)
+#define AN8855_RG_QP_CDR_PR_KBAND_PCIE_MODE BIT(6)
+#define AN8855_RG_QP_CDR_PR_KBAND_DIV_PCIE_MASK GENMASK(5, 0)
+#define AN8855_RG_QP_CDR_FORCE_IBANDLPF_R_OFF 0x1022f020
+#define AN8855_RG_QP_CDR_PHYCK_SEL GENMASK(17, 16)
+#define AN8855_RG_QP_CDR_PHYCK_RSTB BIT(13)
+#define AN8855_RG_QP_CDR_PHYCK_DIV GENMASK(12, 6)
+#define AN8855_RG_QP_TX_MODE 0x1022f028
+#define AN8855_RG_QP_TX_RESERVE GENMASK(31, 16)
+#define AN8855_RG_QP_TX_MODE_16B_EN BIT(0)
+#define AN8855_RG_QP_PLL_IPLL_DIG_PWR_SEL 0x1022f03c
+#define AN8855_RG_QP_PLL_SDM_ORD 0x1022f040
+#define AN8855_RG_QP_PLL_SSC_PHASE_INI BIT(4)
+#define AN8855_RG_QP_PLL_SSC_TRI_EN BIT(3)
+
+/* AN8855_ETHER_SYS_BASE 0x1028c800 */
+#define AN8855_RG_GPHY_AFE_PWD 0x1028c840
+#define AN8855_RG_GPHY_SMI_ADDR 0x1028c848
+
+struct an8855_priv {
+ struct dsa_switch *ds;
+ struct regmap *regmap;
+ /* Protect ATU or VLAN table access */
+ struct mutex reg_mutex;
+
+ struct phylink_pcs pcs;
+
+ struct mt7530_port ports[AN8855_NUM_PORTS];
+ u32 tx_lpi_timer_ports[AN8855_NUM_PORTS];
+
+ struct mt7530_lib_priv lib_priv;
+};
+
+#endif /* __AN8855_H */
diff --git a/drivers/net/dsa/mediatek/mt7530-lib.c b/drivers/net/dsa/mediatek/mt7530-lib.c
index 098dd45d3ee9..432576803332 100644
--- a/drivers/net/dsa/mediatek/mt7530-lib.c
+++ b/drivers/net/dsa/mediatek/mt7530-lib.c
@@ -423,9 +423,11 @@ int mt7530_lib_fdb_cmd(struct mt7530_lib_priv *priv, enum mt7530_fdb_cmd cmd,
return ret;
}
- regmap_field_read(priv->fields[MT7530_ATC_INVALID], &val);
- if (cmd == MT7530_FDB_READ && val)
- return -EINVAL;
+ if (priv->fields[MT7530_ATC_INVALID]) {
+ regmap_field_read(priv->fields[MT7530_ATC_INVALID], &val);
+ if (cmd == MT7530_FDB_READ && val)
+ return -EINVAL;
+ }
if (rsp)
regmap_field_read(priv->fields[__MT7530_ATC], rsp);
@@ -442,6 +444,8 @@ static void mt7530_lib_fdb_write(struct mt7530_lib_priv *priv, u16 vid,
regmap_field_write(priv->fields[__MT7530_ATWD1], 0);
regmap_field_write(priv->fields[__MT7530_ATWD2], 0);
regmap_field_write(priv->fields[__MT7530_ATWD3], 0);
+ if (priv->fields[__MT7530_ATWD4])
+ regmap_field_write(priv->fields[__MT7530_ATWD4], 0);
regmap_field_write(priv->fields[MT7530_ATWD_CVID], vid);
regmap_field_write(priv->fields[MT7530_ATWD_IVL], 1);
@@ -452,7 +456,17 @@ static void mt7530_lib_fdb_write(struct mt7530_lib_priv *priv, u16 vid,
* be aged out and STATIC_EMP specified as erasing an
* entry
*/
- regmap_field_write(priv->fields[MT7530_ATWD_ENT_STATUS], type);
+ if (priv->fields[MT7530_ATWD_ENT_STATUS])
+ regmap_field_write(priv->fields[MT7530_ATWD_ENT_STATUS], type);
+ if (priv->fields[AN8855_ATWD_TYPE]) {
+ /* Default to static entry (0) */
+ regmap_field_write(priv->fields[AN8855_ATWD_TYPE], 0);
+ }
+ if (priv->fields[AN8855_ATWD_VLD]) {
+ /* Load entry if STATIC_ENT */
+ regmap_field_write(priv->fields[AN8855_ATWD_VLD],
+ type == STATIC_ENT);
+ }
regmap_field_write(priv->fields[MT7530_ATWD_MAC_BYTE_5], mac[5]);
regmap_field_write(priv->fields[MT7530_ATWD_MAC_BYTE_4], mac[4]);
regmap_field_write(priv->fields[MT7530_ATWD_MAC_BYTE_3], mac[3]);
@@ -483,8 +497,14 @@ void mt7530_lib_fdb_read(struct mt7530_lib_priv *priv, struct mt7530_fdb *fdb)
fdb->mac[1] = val;
regmap_field_read(priv->fields[MT7530_ATRD_MAC_BYTE_0], &val);
fdb->mac[0] = val;
- regmap_field_read(priv->fields[MT7530_ATRD_ENT_STATUS], &val);
- fdb->noarp = val == STATIC_ENT;
+ if (priv->fields[MT7530_ATRD_ENT_STATUS]) {
+ regmap_field_read(priv->fields[MT7530_ATRD_ENT_STATUS], &val);
+ fdb->noarp = val == STATIC_ENT;
+ }
+ if (priv->fields[AN8855_ATRD_ARP]) {
+ regmap_field_read(priv->fields[AN8855_ATRD_ARP], &val);
+ fdb->noarp = !!val;
+ }
}
EXPORT_SYMBOL_GPL(mt7530_lib_fdb_read);
@@ -787,6 +807,17 @@ void mt7530_lib_port_bridge_leave(struct mt7530_lib_priv *priv, int port,
}
EXPORT_SYMBOL_GPL(mt7530_lib_port_bridge_leave);
+void mt7530_port_set_pvid(struct mt7530_lib_priv *priv, int port,
+ u16 pvid)
+{
+ regmap_fields_write(priv->fields[MT7530_PPBV1_G0_PORT_VID],
+ port, pvid);
+ if (priv->fields[AN8855_PVID_G0_PORT_VID])
+ regmap_fields_write(priv->fields[AN8855_PVID_G0_PORT_VID],
+ port, pvid);
+}
+EXPORT_SYMBOL_GPL(mt7530_port_set_pvid);
+
static void mt7530_port_set_vlan_unaware(struct mt7530_lib_priv *priv, int port)
{
struct dsa_switch *ds = priv->ds;
@@ -807,8 +838,7 @@ static void mt7530_port_set_vlan_unaware(struct mt7530_lib_priv *priv, int port)
regmap_fields_write(priv->fields[MT7530_PVC_ACC_FRM],
port, MT7530_VLAN_ACC_ALL);
- regmap_fields_write(priv->fields[MT7530_PPBV1_G0_PORT_VID],
- port, G0_PORT_VID_DEF);
+ mt7530_port_set_pvid(priv, port, G0_PORT_VID_DEF);
for (i = 0; i < priv->ds->num_ports; i++) {
if (i == port)
@@ -840,8 +870,7 @@ static void mt7530_port_set_vlan_aware(struct mt7530_lib_priv *priv, int port)
if (dsa_is_user_port(ds, port)) {
regmap_fields_write(priv->fields[MT7530_PCR_PORT_VLAN],
port, MT7530_PORT_SECURITY_MODE);
- regmap_fields_write(priv->fields[MT7530_PPBV1_G0_PORT_VID],
- port, priv->ports[port].pvid);
+ mt7530_port_set_pvid(priv, port, priv->ports[port].pvid);
/* Only accept tagged frames if PVID is not set */
if (!priv->ports[port].pvid)
@@ -919,10 +948,12 @@ static int mt7530_vlan_cmd(struct mt7530_lib_priv *priv, enum mt7530_vlan_cmd cm
return ret;
}
- regmap_field_read(priv->fields[MT7530_VTCR_INVALID], &val);
- if (val) {
- dev_err(priv->dev, "read VTCR invalid\n");
- return -EINVAL;
+ if (priv->fields[MT7530_VTCR_INVALID]) {
+ regmap_field_read(priv->fields[MT7530_VTCR_INVALID], &val);
+ if (val) {
+ dev_err(priv->dev, "read VTCR invalid\n");
+ return -EINVAL;
+ }
}
return 0;
@@ -1044,8 +1075,7 @@ int mt7530_lib_port_vlan_add(struct mt7530_lib_priv *priv, int port,
/* Only configure PVID if VLAN filtering is enabled */
if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port)))
- regmap_fields_write(priv->fields[MT7530_PPBV1_G0_PORT_VID],
- port, vlan->vid);
+ mt7530_port_set_pvid(priv, port, vlan->vid);
} else if (vlan->vid && priv->ports[port].pvid == vlan->vid) {
/* This VLAN is overwritten without PVID, so unset it */
priv->ports[port].pvid = G0_PORT_VID_DEF;
@@ -1055,8 +1085,7 @@ int mt7530_lib_port_vlan_add(struct mt7530_lib_priv *priv, int port,
regmap_fields_write(priv->fields[MT7530_PVC_ACC_FRM],
port, MT7530_VLAN_ACC_TAGGED);
- regmap_fields_write(priv->fields[MT7530_PPBV1_G0_PORT_VID],
- port, G0_PORT_VID_DEF);
+ mt7530_port_set_pvid(priv, port, G0_PORT_VID_DEF);
}
mutex_unlock(priv->reg_mutex);
@@ -1093,8 +1122,7 @@ int mt7530_lib_port_vlan_del(struct mt7530_lib_priv *priv, int port,
regmap_fields_write(priv->fields[MT7530_PVC_ACC_FRM],
port, MT7530_VLAN_ACC_TAGGED);
- regmap_fields_write(priv->fields[MT7530_PPBV1_G0_PORT_VID],
- port, G0_PORT_VID_DEF);
+ mt7530_port_set_pvid(priv, port, G0_PORT_VID_DEF);
}
mutex_unlock(priv->reg_mutex);
diff --git a/drivers/net/dsa/mediatek/mt7530-lib.h b/drivers/net/dsa/mediatek/mt7530-lib.h
index da2ee781f7e6..1465eb49f4cb 100644
--- a/drivers/net/dsa/mediatek/mt7530-lib.h
+++ b/drivers/net/dsa/mediatek/mt7530-lib.h
@@ -159,6 +159,8 @@ enum mt7530_regmap_field {
MT7530_ATWD_AGE_TIMER,
MT7530_ATWD_PORT_MAP,
MT7530_ATWD_ENT_STATUS,
+ AN8855_ATWD_TYPE,
+ AN8855_ATWD_VLD,
MT7530_ATWD_MAC_BYTE_5,
MT7530_ATWD_MAC_BYTE_4,
MT7530_ATWD_MAC_BYTE_3,
@@ -169,11 +171,13 @@ enum mt7530_regmap_field {
__MT7530_ATWD1,
__MT7530_ATWD2,
__MT7530_ATWD3,
+ __MT7530_ATWD4,
MT7530_ATRD_CVID,
MT7530_ATRD_AGE_TIMER,
MT7530_ATRD_PORT_MAP,
MT7530_ATRD_ENT_STATUS,
+ AN8855_ATRD_ARP,
MT7530_ATRD_MAC_BYTE_5,
MT7530_ATRD_MAC_BYTE_4,
MT7530_ATRD_MAC_BYTE_3,
@@ -201,6 +205,7 @@ enum mt7530_regmap_field {
MT7530_PVC_ACC_FRM,
MT7530_PPBV1_G0_PORT_VID,
+ AN8855_PVID_G0_PORT_VID,
MT7530_GMACCR_MAX_RX_JUMBO,
MT7530_GMACCR_MAX_RX_PKT_LEN,
@@ -223,8 +228,13 @@ enum mt7530_regmap_field {
MT7530_MIB_TX_PKT_SZ_256_TO_511,
MT7530_MIB_TX_PKT_SZ_512_TO_1023,
MT7530_MIB_TX_PKT_SZ_1024_TO_MAX,
+ AN8855_MIB_TX_PKT_SZ_1024_TO_1518,
+ AN8855_MIB_TX_PKT_SZ_1519_TO_MAX,
MT7530_MIB_TX_BYTES_LOW,
MT7530_MIB_TX_BYTES_HIGH,
+ AN8855_MIB_TX_OVERSIZE_DROP,
+ AN8855_MIB_TX_BAD_PKT_BYTES_LOW,
+ AN8855_MIB_TX_BAD_PKT_BYTES_HIGH,
MT7530_MIB_RX_DROP,
MT7530_MIB_RX_FILTERING,
MT7530_MIB_RX_UNICAST,
@@ -243,11 +253,21 @@ enum mt7530_regmap_field {
MT7530_MIB_RX_PKT_SZ_256_TO_511,
MT7530_MIB_RX_PKT_SZ_512_TO_1023,
MT7530_MIB_RX_PKT_SZ_1024_TO_MAX,
+ AN8855_MIB_RX_PKT_SZ_1024_TO_1518,
+ AN8855_MIB_RX_PKT_SZ_1519_TO_MAX,
MT7530_MIB_RX_BYTES_LOW,
MT7530_MIB_RX_BYTES_HIGH,
MT7530_MIB_RX_CTRL_DROP,
MT7530_MIB_RX_INGRESS_DROP,
MT7530_MIB_RX_ARL_DROP,
+ AN8855_MIB_FLOW_CONTROL_DROP,
+ AN8855_MIB_WRED_DROP,
+ AN8855_MIB_MIRROR_DROP,
+ AN8855_MIB_RX_BAD_PKT_BYTES_LOW,
+ AN8855_MIB_RX_BAD_PKT_BYTES_HIGH,
+ AN8855_MIB_RXS_FLOW_SAMPLING_PKT_DROP,
+ AN8855_MIB_RXS_FLOW_TOTAL_PKT_DROP,
+ AN8855_MIB_PORT_CONTROL_DROP,
MT7530_FIELD_MAX,
};
@@ -385,6 +405,8 @@ int mt7530_lib_port_vlan_add(struct mt7530_lib_priv *priv, int port,
int mt7530_lib_port_vlan_del(struct mt7530_lib_priv *priv, int port,
const struct switchdev_obj_port_vlan *vlan);
+void mt7530_port_set_pvid(struct mt7530_lib_priv *priv, int port,
+ u16 pvid);
int mt7530_lib_setup_vlan0(struct mt7530_lib_priv *priv);
#endif /* __MT7530_LIB_H */
--
2.55.0
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH net-next v25 02/10] dt-bindings: net: Document support for AN8855 Switch Internal PHY
2026-10-09 16:10 ` [PATCH net-next v25 02/10] dt-bindings: net: Document support for AN8855 Switch Internal PHY Christian Marangi
@ 2026-10-10 16:19 ` netdev-bot+sashiko
0 siblings, 0 replies; 18+ messages in thread
From: netdev-bot+sashiko @ 2026-10-10 16:19 UTC (permalink / raw)
To: ansuelsmth
Cc: lee, robh, krzk+dt, conor+dt, andrew+netdev, davem, edumazet,
kuba, pabeni, olteanv, matthias.bgg, angelogioacchino.delregno,
chester.a.unal, daniel, hkallweit1, linux, horms, joey,
linux-arm-kernel, linux-mediatek, netdev, mfd, devicetree,
linux-kernel, andrew
Thank you for your contribution! Sashiko AI review found 2 potential
issue(s) to consider.
Critical: 0 · High: 0 · Medium: 1 · Low: 1
If you believe none of the issues are legitimate, please reply to each
issue of Medium severity or higher and explain why the AI is wrong.
If any of them are legitimate and you plan to respin, please let patchwork
know by including "pw-bot: cr" as a separate line at the end of your reply
(one such reply per series is enough).
- [Medium] In the example of
Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml, both PHY…
- [Low] In the example of
Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml,…
--
dt-bindings: net: Document support for AN8855 Switch Internal PHY
This adds a YAML binding for the internal PHYs of the Airoha AN8855
5-port Gigabit Switch. These PHYs are exposed on the MDIO bus. The binding
also lets each PHY node reference the SoC eFUSE NVMEM cells (tx_a..tx_d)
used for calibration.
> diff --git a/Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml b/Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml
> new file mode 100644
> index 0000000000000..d2f86116badf4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml
> @@ -0,0 +1,83 @@
[ ... ]
> +examples:
> + - |
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + ethernet-phy@1 {
> + compatible = "ethernet-phy-idc0ff.0410",
> + "ethernet-phy-ieee802.3-c45";
[Severity: Medium]
Should this be "ethernet-phy-ieee802.3-c22" (or just the ID compatible)?
The same applies to ethernet-phy@2 below.
Later in the series, an8855_core_probe() in drivers/mfd/airoha-an8855.c
registers each internal PHY on a bus created by
devm_mdio_regmap_register(). That bus only provides C22 accessors:
drivers/net/mdio/mdio-regmap.c:devm_mdio_regmap_register() {
...
mii->read = mdio_regmap_read_c22;
mii->write = mdio_regmap_write_c22;
...
}
When the c45 compatible is present, fwnode_mdiobus_register_phy() ignores
the explicit c0ff.0410 ID and forces Clause 45 probing:
is_c45 = fwnode_device_is_compatible(child, "ethernet-phy-ieee802.3-c45");
if (is_c45 || fwnode_get_phy_id(child, &phy_id))
phy = get_phy_device(bus, addr, is_c45);
bus->read_c45 is NULL, so __mdiobus_c45_read() returns -EOPNOTSUPP. The
call chain is:
get_phy_device()->get_phy_c45_ids()->get_phy_c45_devs_in_pkg()
and get_phy_c45_ids() turns that error into -EIO. an8855_core_probe()
treats a fwnode_mdiobus_register_phy() failure as fatal
(goto err_put_fwnodes). So a DT copied from this example would make the
whole AN8855 MFD fail to probe, and neither the switch nor the eFUSE
device would be created.
The PHY driver later in the series (drivers/net/phy/air_an8855.c) also
uses C22 paged access, and the MFD binding in the same series
("dt-bindings: mfd: Document support for Airoha AN8855 Switch SoC") uses
"ethernet-phy-ieee802.3-c22" for these same PHYs. ethernet-phy.yaml
accepts both strings, so dt_binding_check won't flag the mismatch.
> +
> + reg = <1>;
> + };
> +
> + ethernet-phy@2 {
> + compatible = "ethernet-phy-idc0ff.0410",
> + "ethernet-phy-ieee802.3-c45";
> +
> + reg = <2>;
> +
> + nvmem-cells = <&shift_sel_port0_tx_a>,
> + <&shift_sel_port0_tx_b>,
> + <&shift_sel_port0_tx_c>,
> + <&shift_sel_port0_tx_d>;
[Severity: Low]
Is the PHY at reg 2 meant to use port 0's calibration cells here? In this
example ethernet-phy@1 has no cells and ethernet-phy@2 uses
shift_sel_port0_tx_*.
The MFD binding later in the series maps them differently:
ethernet-phy@1 (internal_phy1) uses shift_sel_port0_tx_*, ethernet-phy@2
(internal_phy2) uses shift_sel_port1_tx_*, port@0 is internal_phy1 and
port@1 is internal_phy2.
an8855_phy_bus_register() computes the port from the address:
phy_offset = addr - priv->switch_addr;
if (phy_offset >= AN8855_MAX_PHY_PORT)
return -EINVAL;
So when both reg 1 and reg 2 are present, the PHY at reg 2 can't be
port 0.
air_an8855.c reads tx_a..tx_d in an8855_probe() and writes them into the
VEND1 R50OHM_RSEL registers in an8855_config_init(). A DTS copied from this
example would put port 0's trim on a different PHY and leave the port 0 PHY
uncalibrated.
Would it make sense to match the MFD example, with port0 cells on
ethernet-phy@1 and port1 cells on ethernet-phy@2?
> + nvmem-cell-names = "tx_a", "tx_b", "tx_c", "tx_d";
> + };
> + };
--
Sashiko AI review · https://netdev-ai.bots.linux.dev/sashiko/#/patchset/20261009161102.38961-1-ansuelsmth%40gmail.com
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH net-next v25 03/10] dt-bindings: mfd: Document support for Airoha AN8855 Switch SoC
2026-10-09 16:10 ` [PATCH net-next v25 03/10] dt-bindings: mfd: Document support for Airoha AN8855 Switch SoC Christian Marangi
@ 2026-10-10 16:19 ` netdev-bot+sashiko
0 siblings, 0 replies; 18+ messages in thread
From: netdev-bot+sashiko @ 2026-10-10 16:19 UTC (permalink / raw)
To: ansuelsmth
Cc: lee, robh, krzk+dt, conor+dt, andrew+netdev, davem, edumazet,
kuba, pabeni, olteanv, matthias.bgg, angelogioacchino.delregno,
chester.a.unal, daniel, hkallweit1, linux, horms, joey,
linux-arm-kernel, linux-mediatek, netdev, mfd, devicetree,
linux-kernel, andrew
Thank you for your contribution! Sashiko AI review found 1 potential
issue(s) to consider.
Critical: 0 · High: 0 · Medium: 1 · Low: 0
If you believe none of the issues are legitimate, please reply to each
issue of Medium severity or higher and explain why the AI is wrong.
If any of them are legitimate and you plan to respin, please let patchwork
know by including "pw-bot: cr" as a separate line at the end of your reply
(one such reply per series is enough).
- [Medium] The two AN8855 binding examples disagree on how the internal
PHYs are accessed.
--
dt-bindings: mfd: Document support for Airoha AN8855 Switch SoC
This commit adds a YAML binding for the Airoha AN8855 Switch SoC. The SoC
exposes an Ethernet switch, an eFUSE NVMEM provider and internal Ethernet
PHYs. The example puts the internal PHYs on a nested mdio node.
> diff --git a/Documentation/devicetree/bindings/mfd/airoha,an8855.yaml b/Documentation/devicetree/bindings/mfd/airoha,an8855.yaml
> new file mode 100644
> index 0000000000000..48127e956c965
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/airoha,an8855.yaml
> @@ -0,0 +1,176 @@
[ ... ]
> + mdio {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + internal_phy1: ethernet-phy@1 {
> + compatible = "ethernet-phy-idc0ff.0410",
> + "ethernet-phy-ieee802.3-c22";
[Severity: Medium]
This example gives the internal PHYs the ethernet-phy-ieee802.3-c22
compatible. The PHY binding added earlier in this series uses the C45
compatible for the same PHY ID:
Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml:
ethernet-phy@1 {
compatible = "ethernet-phy-idc0ff.0410",
"ethernet-phy-ieee802.3-c45";
Which of the two is correct?
The PHY binding selects on ethernet-phy-idc0ff.0410, so it also applies
to the PHY nodes nested here. Its $ref to ethernet-phy.yaml accepts both
c22 and c45, which means dt_binding_check won't catch the mismatch.
Later in the series, the MFD driver puts each PHY on a bus created with
devm_mdio_regmap_register(). That bus only provides C22 accessors:
drivers/net/mdio/mdio-regmap.c:devm_mdio_regmap_register()
mii->read = mdio_regmap_read_c22;
mii->write = mdio_regmap_write_c22;
Would a board DT that copies the PHY binding example end up on this path?
an8855_core_probe()
fwnode_mdiobus_register_phy() /* is_c45 is true */
get_phy_device(bus, addr, true)
get_phy_c45_ids()
get_phy_c45_devs_in_pkg()
mdiobus_c45_read()
__mdiobus_c45_read() /* -EOPNOTSUPP, no read_c45 */
That error turns into -EIO. an8855_core_probe() then jumps to
err_put_fwnodes, so the switch, eFUSE and PHYs never get registered.
The switch binding says its registers are reached by configuring the PHY
page. That also points to C22 access.
Should the PHY binding example use ethernet-phy-ieee802.3-c22, or drop the
C45 compatible, so the two bindings agree?
--
Sashiko AI review · https://netdev-ai.bots.linux.dev/sashiko/#/patchset/20261009161102.38961-1-ansuelsmth%40gmail.com
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH net-next v25 04/10] mfd: an8855: Add support for Airoha AN8855 Switch
2026-10-09 16:10 ` [PATCH net-next v25 04/10] mfd: an8855: Add support for Airoha AN8855 Switch Christian Marangi
@ 2026-10-10 16:19 ` netdev-bot+sashiko
0 siblings, 0 replies; 18+ messages in thread
From: netdev-bot+sashiko @ 2026-10-10 16:19 UTC (permalink / raw)
To: ansuelsmth
Cc: lee, robh, krzk+dt, conor+dt, andrew+netdev, davem, edumazet,
kuba, pabeni, olteanv, matthias.bgg, angelogioacchino.delregno,
chester.a.unal, daniel, hkallweit1, linux, horms, joey,
linux-arm-kernel, linux-mediatek, netdev, mfd, devicetree,
linux-kernel, andrew
Thank you for your contribution! Sashiko AI review found 13 potential
issue(s) to consider.
Critical: 0 · High: 1 · Medium: 3 · Low: 9
If you believe none of the issues are legitimate, please reply to each
issue of Medium severity or higher and explain why the AI is wrong.
If any of them are legitimate and you plan to respin, please let patchwork
know by including "pw-bot: cr" as a separate line at the end of your reply
(one such reply per series is enough).
- [High] The MFD binding
(Documentation/devicetree/bindings/mfd/airoha,an8855.yaml) defines…
- [Medium] The commit message says the driver provides "a DSA switch and
a NVMEM provider", and so does the MFD_AIROHA_AN8855 help text.
- [Medium] The PHY binding added in this series
(Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml) shows…
- [Medium] an8855_phy_bus_register() checks the DT PHY `reg` only as an
offset from the switch address (`phy_offset = addr -…
- [Low] The patch leaves several loose ends: - AN8855_HWTRAP,
AN8855_PHY_PAGE_EXTENDED_1 and AN8855_PBUS_MODE_ADDR_INCR are defined…
- [Low] an8855_phy_bus_register() registers one unnamed 16-bit regmap per
internal PHY on the MFD parent device.
- [Low] In an8855_readable_ranges, the "General Purpose Timer" entry
covers 0x1000a100-0x1000a2ff.
- [Low] The MFD binding leaves `efuse` out of `required`, but
an8855_cells always adds the "an8855-efuse" cell with of_compatible…
- [Low] In an8855_phy_bus_register(), the u32 `addr` is printed with %d
in dev_err_probe(dev, ..., "phy%d regmap initialization failed\n",…
- [Low] an8855_phy_bus_register() builds each virtual MDIO bus id with
snprintf(mrc.name, MII_BUS_ID_SIZE, "%s-phy%u", dev_name(dev), addr)…
- [Low] an8855_regmap_phy_reset_page() always restores page 0
(AN8855_PHY_PAGE_STANDARD) after a switch access.
- [Low] an8855_mdio_register() mixes scope-based and goto-based cleanup.
- [Low] an8855_core_probe() writes 0 to AN8855_RG_GPHY_AFE_PWD, releasing
the analog front-end power-down for every internal GPHY at once,…
--
mfd: an8855: Add support for Airoha AN8855 Switch
This adds an MFD core driver for the Airoha AN8855 switch, which sits on an
MDIO bus. It exposes a 32-bit switch regmap and registers efuse and DSA
switch child cells. It also creates a virtual mdio-regmap bus, with its own
regmap, for each internal PHY, so that PHY and switch accesses sharing the
same MDIO address are serialized.
> diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
> index e4fd4572472f9..afbdcec0fce8f 100644
> --- a/drivers/mfd/Kconfig
> +++ b/drivers/mfd/Kconfig
> @@ -54,6 +54,20 @@ config MFD_ALTERA_SYSMGR
[ ... ]
> +config MFD_AIROHA_AN8855
> + tristate "Airoha AN8855 Switch Core"
> + select MFD_CORE
> + select REGMAP
> + select PHYLIB
> + select MDIO_REGMAP
> + depends on NETDEVICES && OF
> + help
> + Support for the Airoha AN8855 Switch Core. This is an SoC
> + that provides various peripherals, to count, i2c, an Ethrnet
> + Switch, a CPU timer, GPIO, eFUSE.
> +
> + Currently it provides a DSA switch and a NVMEM provider.
[Severity: Medium]
The commit message and this help text both say the driver provides "a DSA
switch and a NVMEM provider". The DSA and PHY parts arrive later in the
series, in "net: dsa: Add Airoha AN8855 5-Port Gigabit DSA Switch driver"
and "net: phy: Add Airoha AN8855 Internal Switch Gigabit PHY".
Can the NVMEM provider be enabled on real hardware, though? The driver for
the an8855-efuse cell can still only be built with COMPILE_TEST:
drivers/nvmem/Kconfig:
config NVMEM_AN8855_EFUSE
tristate "Airoha AN8855 eFuse support"
depends on COMPILE_TEST
No patch in the series relaxes this to something like
"depends on MFD_AIROHA_AN8855 || COMPILE_TEST", which is what
NET_DSA_AN8855 uses.
Once the series is applied, an8855_probe() in drivers/net/phy/air_an8855.c
calls nvmem_cell_read_u32() whenever the PHY node has nvmem-cells, as both
binding examples do. With no provider registered, that returns
-EPROBE_DEFER, or an error if NVMEM is disabled. The PHY driver then never
binds, and phy_attach_direct() falls back to genphy.
Wouldn't the R50 calibration and the vendor config_init (downshift and
noise-reduction settings) then never be applied?
> diff --git a/drivers/mfd/airoha-an8855.c b/drivers/mfd/airoha-an8855.c
> new file mode 100644
> index 0000000000000..a2778511dfefc
> --- /dev/null
> +++ b/drivers/mfd/airoha-an8855.c
> @@ -0,0 +1,579 @@
[ ... ]
> +#include <linux/gpio/consumer.h>
[ ... ]
> +/* Register for HW trap status */
> +#define AN8855_HWTRAP 0x1000009c
[ ... ]
> +#define AN8855_PHY_PAGE_EXTENDED_1 FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x1)
> +#define AN8855_PHY_PAGE_EXTENDED_4 FIELD_PREP_CONST(AN8855_PHY_PAGE, 0x4)
> +
> +/* MII Registers Page 4 */
> +#define AN8855_PBUS_MODE 0x10
> +#define AN8855_PBUS_MODE_ADDR_FIXED 0x0
> +#define AN8855_PBUS_MODE_ADDR_INCR BIT(15)
[ ... ]
> +struct an8855_core {
> + struct mii_bus *bus;
> + struct mii_bus *phy_bus;
> + unsigned int switch_addr;
> + u16 current_page;
> +};
[Severity: Low]
This isn't a bug, but there are a few leftovers here.
AN8855_HWTRAP, AN8855_PHY_PAGE_EXTENDED_1 and AN8855_PBUS_MODE_ADDR_INCR
are defined but never used. linux/gpio/consumer.h is included, but no GPIO
API is used.
The MFD_AIROHA_AN8855 help text has typos: "to count" and "Ethrnet".
The MFD guidelines also prefer naming the private data struct after the
device and calling the instance ddata, rather than using
struct an8855_core *priv.
[ ... ]
> +static const struct mfd_cell an8855_cells[] = {
> + MFD_CELL_OF("an8855-efuse", NULL, NULL, 0, 0,
> + "airoha,an8855-efuse"),
> + MFD_CELL_OF("an8855-switch", NULL, NULL, 0, 0,
> + "airoha,an8855-switch"),
> +};
[Severity: Low]
The airoha,an8855.yaml binding does not list efuse under required, but the
an8855-efuse cell is always added.
Take a DT that is valid under the binding but has no efuse node. In that
case mfd_add_device() prints "Failed to locate of_node" and registers the
platform device anyway. The efuse driver then binds by name and registers
an NVMEM device with no OF node, which no PHY can reference.
Should the efuse cell only be added when the node exists, or should efuse
be required in the binding?
[ ... ]
> +static const struct regmap_range an8855_readable_ranges[] = {
[ ... ]
> + regmap_reg_range(0x10009000, 0x10009fff), /* PDMA */
> + regmap_reg_range(0x1000a100, 0x1000a2ff), /* General Purpose Timer */
> + regmap_reg_range(0x1000a200, 0x1000a2ff), /* GPU timer */
[Severity: Low]
Should the General Purpose Timer range end at 0x1000a1ff? As written, it
fully contains the GPU timer range that follows.
Also, should "GPU timer" be "CPU timer"? That is what the Kconfig help
text calls it.
[ ... ]
> +static int an8855_regmap_phy_reset_page(struct an8855_core *priv,
> + int phy) __must_hold(&priv->bus->mdio_lock)
> +{
> + /* Check PHY page only for addr shared with switch */
> + if (phy != priv->switch_addr)
> + return 0;
> +
> + /* Don't restore page if it's not set to Switch page */
> + if (priv->current_page != AN8855_PHY_PAGE_EXTENDED_4)
> + return 0;
> +
> + /*
> + * Restore page to 0, PHY might change page right after but that
> + * will be ignored as it won't be a switch page.
> + */
> + return an8855_mii_set_page(priv, phy, AN8855_PHY_PAGE_STANDARD);
> +}
[Severity: Low]
This isn't a bug for in-kernel users, but this always restores page 0
after a switch access. PHY writes to register 0x1f that go through
an8855_regmap_phy_write() don't update priv->current_page. So if a switch
regmap access runs between two PHY accesses, the page the PHY selected is
lost.
In-kernel, phy_read_paged() and phy_modify_paged() in air_an8855.c hold
the virtual bus mdio_lock across the page select, the access and the
restore. an8855_regmap_lock() takes the same phy_bus->mdio_lock, so those
paths are serialized.
The remaining case is privileged userspace that selects a page with one
SIOCSMIIREG call and then accesses a register with a separate call. Is
that an acceptable limitation, and should the existing comment mention it?
[ ... ]
> +static int an8855_phy_bus_register(struct device *dev, struct an8855_core *priv,
> + struct device_node *phy_np,
> + struct an8855_phy_bus *phy_bus_info)
> +{
[ ... ]
> + ret = of_property_read_u32(phy_np, "reg", &addr);
> + if (ret)
> + return ret;
> +
> + phy_offset = addr - priv->switch_addr;
> + if (phy_offset >= AN8855_MAX_PHY_PORT)
> + return -EINVAL;
[Severity: Medium]
Should this also check that addr is below PHY_MAX_ADDR?
With the switch at MDIO address 28-31, a PHY child with reg 32-35 passes
this check. of_mdio_parse_addr() would normally reject that address. This
driver calls fwnode_mdiobus_register_phy() directly, so the address reaches
code that indexes PHY_MAX_ADDR-sized arrays in struct mii_bus:
an8855_core_probe()
fwnode_mdiobus_register_phy()
phy_device_create()
dev->irq = bus->irq[addr];
fwnode_mdiobus_phy_device_register()
mdio->irq[addr] = rc;
mdio->phy_ignore_ta_mask |= 1 << addr;
irq[32..35] overlaps reset_delay_us, reset_post_delay_us and reset_gpiod.
Also, "1 << addr" is undefined when addr is 32 or more.
Next, phy_device_register() fails with -EBUSY, because mdio_map[addr]
overlaps fields that are non-zero. The devres unwind then runs
mdiobus_unregister(), which passes bus->reset_gpiod to
gpiod_set_value_cansleep().
Could that dereference a corrupted reset_gpiod? Triggering this needs a DT
that breaks the reg maximum in mdio.yaml, but the core enforces this bound
at runtime on its own paths.
> +
> + phy_priv = devm_kzalloc(dev, sizeof(*phy_priv), GFP_KERNEL);
> + if (!phy_priv)
> + return -ENOMEM;
> +
> + phy_priv->addr = addr;
> + phy_priv->core = priv;
> +
> + regmap = devm_regmap_init(dev, NULL, phy_priv, &an8855_phy_regmap_config);
[Severity: Low]
This isn't a bug with the current probe order, but these unnamed PHY
regmaps are attached to the same device as the "switch" regmap.
an8855_efuse_probe(), and the DSA driver later in the series, both call
dev_get_regmap(dev->parent, NULL). That matches any regmap on the parent
and returns the most recently added one. The children get the switch
regmap only because an8855_core_probe() creates it after all the PHY
regmaps.
Would it be more robust for the children to look up "switch" by name, or
to give the PHY regmaps names?
> + if (IS_ERR(regmap))
> + return dev_err_probe(dev, PTR_ERR(regmap),
> + "phy%d regmap initialization failed\n",
> + addr);
[Severity: Low]
This isn't a bug, but addr is a u32 printed with %d here, while the
snprintf() below prints it with %u.
> +
> + mrc.regmap = regmap;
> + mrc.parent = dev;
> + mrc.valid_addr = addr;
> + snprintf(mrc.name, MII_BUS_ID_SIZE, "%s-phy%u", dev_name(dev), addr);
[Severity: Low]
Can this truncation drop the per-PHY suffix?
dev_name(dev) for this mdio_device is PHY_ID_FMT ("%s:%02x") applied to
the parent bus id, which can be up to 60 characters long. If the parent bus
id is 53 characters or longer, "-phyN", or at least its digit, gets cut
off.
devm_mdio_regmap_register() copies this name into mii->id, so every
virtual bus would get the same id and the second bus registration would
fail. Should the snprintf() return value be checked, or a shorter naming
scheme be used?
> +
> + bus = devm_mdio_regmap_register(dev, &mrc);
> + if (IS_ERR(bus))
> + return PTR_ERR(bus);
[Severity: Medium]
The PHY binding added in this series (airoha,an8855-phy.yaml) shows the
internal PHYs as:
compatible = "ethernet-phy-idc0ff.0410",
"ethernet-phy-ieee802.3-c45";
The MFD binding example uses "ethernet-phy-ieee802.3-c22" for the same
PHYs. The bus created here only sets mdio_regmap_read_c22() and
mdio_regmap_write_c22(), with no read_c45 or write_c45.
If a DT follows the PHY binding, wouldn't probe fail?
an8855_core_probe()
fwnode_mdiobus_register_phy() /* is_c45 set, PHY ID shortcut skipped */
get_phy_device(bus, addr, true)
get_phy_c45_ids()
mdiobus_c45_read() /* -EOPNOTSUPP without read_c45 */
get_phy_c45_ids() turns that into -EIO, and an8855_core_probe() jumps to
err_put_fwnodes. The switch, the efuse and all the PHYs then fail to
register.
Should the PHY binding example use c22, or should the driver handle the c45
compatible?
[ ... ]
> +static int an8855_mdio_register(struct device *dev, struct an8855_core *priv,
> + struct an8855_phy_bus *phy_bus_infos)
> +{
> + struct device_node *mdio_np;
> + int ret = 0;
> + int i = 0;
> +
> + mdio_np = of_get_child_by_name(dev->of_node, "mdio");
> + if (!mdio_np)
> + return -ENODEV;
> +
> + for_each_available_child_of_node_scoped(mdio_np, phy_np) {
> + if (i >= AN8855_MAX_PHY_PORT) {
> + ret = -EINVAL;
> + goto exit;
> + }
> +
> + ret = an8855_phy_bus_register(dev, priv, phy_np,
> + &phy_bus_infos[i]);
> + if (ret)
> + goto exit;
> +
> + i++;
> + }
> +
> +exit:
> + of_node_put(mdio_np);
[Severity: Low]
This isn't a bug as written, but this function mixes the scoped iterator
(phy_np is declared __free(device_node)) with goto-based cleanup.
include/linux/cleanup.h asks that the two not be mixed in one function.
Could mdio_np use __free(device_node), with the error paths returning
directly? Alternatively, the non-scoped iterator could be used with an
explicit of_node_put() on early exit.
[ ... ]
> +static int an8855_core_probe(struct mdio_device *mdiodev)
> +{
[ ... ]
> + /* Reset PHY page for switch address */
> + mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
> + ret = an8855_mii_set_page(priv, priv->switch_addr,
> + AN8855_PHY_PAGE_STANDARD);
> + mutex_unlock(&priv->bus->mdio_lock);
> + if (ret)
> + goto err_put_fwnodes;
> +
> + ret = an8855_read_switch_id(dev, regmap);
> + if (ret)
> + goto err_put_fwnodes;
[Severity: High]
Is the reset-gpios property from the airoha,an8855.yaml binding handled
anywhere? The binding example uses reset-gpios = <&pio 39 GPIO_ACTIVE_HIGH>.
an8855_core_probe() never requests or toggles that GPIO, and starts MDIO
traffic right here.
The MDIO core doesn't handle it either. mdiobus_register_device() only
calls mdio_device_register_reset() when MDIO_DEVICE_FLAG_PHY is set, and
the AN8855 core is a plain mdio_device.
If the bootloader leaves the switch in reset, wouldn't
an8855_read_switch_id() fail and leave the whole switch unusable? If reset
was released only just before probe, nothing waits for init to finish. In
both cases the chip never gets a clean hardware reset, so switch and PHY
state configured by the bootloader carries over.
The unused linux/gpio/consumer.h include and the unused AN8855_HWTRAP
("Register for HW trap status") define suggest a reset-and-wait sequence
was removed. Was that intended?
> +
> + /* Release global PHY power down */
> + ret = regmap_write(regmap, AN8855_RG_GPHY_AFE_PWD, 0x0);
> + if (ret)
> + goto err_put_fwnodes;
[Severity: Low]
This powers up the analog front end of every internal GPHY, including PHYs
that are not described in DT. Is anything expected to put them back into
power down?
If a later step fails, the err_put_fwnodes path only drops fwnode
references. There is no remove callback or devm action, and the DSA driver
later in the series never touches AN8855_RG_GPHY_AFE_PWD.
So after a failed probe or an unbind, the PHYs stay powered with no driver
managing them.
[ ... ]
--
Sashiko AI review · https://netdev-ai.bots.linux.dev/sashiko/#/patchset/20261009161102.38961-1-ansuelsmth%40gmail.com
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH net-next v25 05/10] net: phy: Add Airoha AN8855 Internal Switch Gigabit PHY
2026-10-09 16:10 ` [PATCH net-next v25 05/10] net: phy: Add Airoha AN8855 Internal Switch Gigabit PHY Christian Marangi
@ 2026-10-10 16:19 ` netdev-bot+sashiko
0 siblings, 0 replies; 18+ messages in thread
From: netdev-bot+sashiko @ 2026-10-10 16:19 UTC (permalink / raw)
To: ansuelsmth
Cc: lee, robh, krzk+dt, conor+dt, andrew+netdev, davem, edumazet,
kuba, pabeni, olteanv, matthias.bgg, angelogioacchino.delregno,
chester.a.unal, daniel, hkallweit1, linux, horms, joey,
linux-arm-kernel, linux-mediatek, netdev, mfd, devicetree,
linux-kernel, andrew
Thank you for your contribution! Sashiko AI review found 4 potential
issue(s) to consider.
Critical: 0 · High: 0 · Medium: 4 · Low: 0
If you believe none of the issues are legitimate, please reply to each
issue of Medium severity or higher and explain why the AI is wrong.
If any of them are legitimate and you plan to respin, please let patchwork
know by including "pw-bot: cr" as a separate line at the end of your reply
(one such reply per series is enough).
- [Medium] The commit says the driver calibrates the AN8855 PHY from
NVMEM cells, but the only provider of those cells cannot be enabled in…
- [Medium] The ETHTOOL_PHY_DOWNSHIFT tunable does not round-trip.
- [Medium] The PHY binding added in this series and the rest of the stack
disagree on Clause 22 vs Clause 45.
- [Medium] net: phy: air_an8855: phy_write_mmd clobbers adjacent reserved
fields
--
net: phy: Add Airoha AN8855 Internal Switch Gigabit PHY
This adds a PHY driver for the internal Gigabit PHYs in the Airoha AN8855
switch. At probe time it reads R50 calibration values from NVMEM cells. In
config_init it applies them together with some noise reduction settings,
and it also exposes the downshift tunable.
> diff --git a/drivers/net/phy/air_an8855.c b/drivers/net/phy/air_an8855.c
> new file mode 100644
> index 0000000000000..bc22256fd5f95
> --- /dev/null
> +++ b/drivers/net/phy/air_an8855.c
> @@ -0,0 +1,275 @@
[ ... ]
> +static int an8855_probe(struct phy_device *phydev)
> +{
> + struct device *dev = &phydev->mdio.dev;
> + struct air_an8855_priv *priv;
> +
> + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + if (!priv)
> + return -ENOMEM;
> +
> + priv->needs_calibration = of_property_present(dev->of_node,
> + "nvmem-cells");
> +
> + if (priv->needs_calibration) {
> + int ret;
> +
> + ret = an8855_get_r50ohm_val(dev, "tx_a", &priv->calibration_data[0]);
> + if (ret)
> + return ret;
[Severity: Medium]
Can this probe succeed on a kernel built without COMPILE_TEST when the DT
has nvmem-cells? The MFD binding example has them on every PHY.
The only provider of these cells is NVMEM_AN8855_EFUSE. In
drivers/nvmem/Kconfig it currently has:
config NVMEM_AN8855_EFUSE
...
depends on COMPILE_TEST
Commit 4796eaafd6a1 ("nvmem: an8855: drop an unused Kconfig symbol")
removed the MFD_AIROHA_AN8855 alternative because that symbol did not
exist yet.
This series adds MFD_AIROHA_AN8855 in "mfd: an8855: Add support for Airoha
AN8855 Switch". The "MFD_AIROHA_AN8855 ||" part of that dependency doesn't
seem to be added back anywhere in the series.
With NVMEM=y, an8855_get_r50ohm_val()->nvmem_cell_read_u32() ends up in
nvmem_device_match(). That never finds a provider and returns
-EPROBE_DEFER, so the probe defers forever.
With NVMEM=n, which the new "depends on NVMEM || !NVMEM" in
drivers/net/phy/Kconfig allows, the inline nvmem_cell_read_u32() stub
returns -EOPNOTSUPP and the probe fails.
Either way this driver never binds, and phy_attach_direct() falls back to
genphy when DSA attaches the port. Wouldn't that silently skip the R50
calibration, the noise reduction writes and the downshift enable in
an8855_config_init()?
Could the NVMEM_AN8855_EFUSE dependency on MFD_AIROHA_AN8855 be added back?
Separately, could the -EOPNOTSUPP case let the PHY run uncalibrated
instead of failing the probe?
[ ... ]
> +static int an8855_get_downshift(struct phy_device *phydev, u8 *data)
> +{
> + int val;
> +
> + val = phy_read_paged(phydev, AN8855_PHY_PAGE_EXTENDED_1, AN8855_PHY_EXT_REG_14);
> + if (val < 0)
> + return val;
> +
> + *data = val & AN8855_PHY_EN_DOWN_SHIFT ? DOWNSHIFT_DEV_DEFAULT_COUNT :
> + DOWNSHIFT_DEV_DISABLE;
> +
> + return 0;
> +}
> +
> +static int an8855_set_downshift(struct phy_device *phydev, u8 cnt)
> +{
> + u16 ds = cnt != DOWNSHIFT_DEV_DISABLE ? AN8855_PHY_EN_DOWN_SHIFT : 0;
[Severity: Medium]
Does the ETHTOOL_PHY_DOWNSHIFT tunable round-trip correctly?
In an8855_set_downshift(), any count from 1 to 255 returns success. The
requested count is dropped and only the enable bit is set. Counts the
hardware can't honour are never rejected. ethtool_phy_tunable_valid() in
net/ethtool/ioctl.c only checks len and type_id, so range checking is left
to the driver.
In an8855_get_downshift(), DOWNSHIFT_DEV_DEFAULT_COUNT (0xff) is reported
to userspace whenever the enable bit is set. That value is a request
sentinel, not a real retry count.
As a result, "ethtool --set-phy-tunable ethX downshift count 3" succeeds,
and a later get shows "Downshift count: 255".
Other drivers that use DOWNSHIFT_DEV_DEFAULT_COUNT (bcm-phy-lib.c,
bcm54140.c, marvell10g.c, microchip.c, mscc_main.c, qcom-phy-lib.c) map it
to a real count on set and reject counts they can't support. For example,
mv3310_set_downshift() does:
if (ds == DOWNSHIFT_DEV_DEFAULT_COUNT)
ds = 2;
None of them return 0xff from get.
[ ... ]
> +static int an8855_config_init(struct phy_device *phydev)
> +{
> + struct air_an8855_priv *priv = phydev->priv;
> + int ret;
[ ... ]
> + /* Apply values to reduce signal noise */
> + ret = phy_modify_mmd(phydev, MDIO_MMD_VEND1, AN8855_PHY_TX_PAIR_DLY_SEL_GBE,
> + AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_A_GBE |
> + AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_C_GBE,
> + FIELD_PREP(AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_A_GBE, 0x4) |
> + FIELD_PREP(AN8855_PHY_CR_DA_TX_PAIR_DELAY_SEL_C_GBE, 0x4));
[Severity: Medium]
Do these two writes clear the pair B and D fields?
The other noise reduction settings in an8855_config_init() only touch
pairs A and C. The TX pair delay uses phy_modify_mmd() and the RXADC
sample phase uses phy_set_bits_mmd(), so the B and D fields keep
their reset values.
The two RXADC reserve registers are handled differently.
phy_write_mmd() replaces the whole 16-bit register.
Writing FIELD_PREP(AN8855_PHY_RG_AD_RESERVE0_A, 0x1) to
AN8855_PHY_RXADC_REV_0 therefore also sets
AN8855_PHY_RG_AD_RESERVE0_B (bits 7:0) to 0. The write to
AN8855_PHY_RXADC_REV_1 does the same to AN8855_PHY_RG_AD_RESERVE0_D.
config_init runs from phy_init_hw() on every attach and resume, so
this is applied unconditionally. If the reset values of the B and D
fields are not zero, this would change the ADC tuning of pairs B and
D. That doesn't match how the other A/C-only writes in this block are
done.
Is clearing the B and D fields intended, for example because the
vendor code writes these registers as whole values? If so, could the
code say that? If not, should these be phy_modify_mmd() calls that
mask only AN8855_PHY_RG_AD_RESERVE0_A and
AN8855_PHY_RG_AD_RESERVE0_C, like the TX pair delay write above?
[Severity: Medium]
Several parts of this driver assume Clause 22 access:
- these MMD accesses, which go through C22-indirect access
- the register 0x1f paging in an8855_read_page() and an8855_write_page()
- genphy_soft_reset(), genphy_suspend() and genphy_resume()
Is the PHY binding added in this series consistent with that?
Both example nodes in
Documentation/devicetree/bindings/net/airoha,an8855-phy.yaml use:
compatible = "ethernet-phy-idc0ff.0410",
"ethernet-phy-ieee802.3-c45";
The MFD binding example in
Documentation/devicetree/bindings/mfd/airoha,an8855.yaml declares the same
PHY as "ethernet-phy-ieee802.3-c22".
The MDIO bus registered by an8855_core_probe() comes from
devm_mdio_regmap_register(), which only provides C22 accessors:
drivers/net/mdio/mdio-regmap.c:devm_mdio_regmap_register() {
...
mii->read = mdio_regmap_read_c22;
mii->write = mdio_regmap_write_c22;
...
}
If a DT follows the PHY binding example, the path would be:
an8855_core_probe()
fwnode_mdiobus_register_phy()
get_phy_device(bus, addr, true)
get_phy_c45_ids()
__mdiobus_c45_read() <- -EOPNOTSUPP, no read_c45
get_phy_c45_ids() turns this into -EIO, and the whole MFD probe fails.
Even if a phydev were created with is_c45 set, wouldn't every
phy_modify_mmd() and phy_write_mmd() in an8855_config_init() take the
unsupported C45 direct access path?
Should the PHY binding examples use "ethernet-phy-ieee802.3-c22" instead?
[ ... ]
--
Sashiko AI review · https://netdev-ai.bots.linux.dev/sashiko/#/patchset/20261009161102.38961-1-ansuelsmth%40gmail.com
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH net-next v25 06/10] net: dsa: tag_mtk: add Airoha variant usage of this TAG
2026-10-09 16:10 ` [PATCH net-next v25 06/10] net: dsa: tag_mtk: add Airoha variant usage of this TAG Christian Marangi
@ 2026-10-10 16:19 ` netdev-bot+sashiko
0 siblings, 0 replies; 18+ messages in thread
From: netdev-bot+sashiko @ 2026-10-10 16:19 UTC (permalink / raw)
To: ansuelsmth
Cc: lee, robh, krzk+dt, conor+dt, andrew+netdev, davem, edumazet,
kuba, pabeni, olteanv, matthias.bgg, angelogioacchino.delregno,
chester.a.unal, daniel, hkallweit1, linux, horms, joey,
linux-arm-kernel, linux-mediatek, netdev, mfd, devicetree,
linux-kernel, andrew
Thank you for your contribution! Sashiko AI review found 1 potential
issue(s) to consider.
Critical: 0 · High: 0 · Medium: 1 · Low: 0
If you believe none of the issues are legitimate, please reply to each
issue of Medium severity or higher and explain why the AI is wrong.
If any of them are legitimate and you plan to respin, please let patchwork
know by including "pw-bot: cr" as a separate line at the end of your reply
(one such reply per series is enough).
- [Medium] The patch adds DSA_TAG_PROTO_AIROHA as a second proto ID for
exactly the same wire format as DSA_TAG_PROTO_MTK.
--
net: dsa: tag_mtk: add Airoha variant usage of this TAG
This commit adds a DSA_TAG_PROTO_AIROHA tag protocol. It reuses the MTK
tag xmit/rcv handlers under a separate "airoha" name. The Kconfig is
split into NET_DSA_TAG_MTK and NET_DSA_TAG_AIROHA, and both select a
common NET_DSA_TAG_MTK_COMMON symbol that builds tag_mtk.o.
> diff --git a/net/dsa/tag_mtk.c b/net/dsa/tag_mtk.c
> index c7dc7731675ec..f8087d768da6d 100644
> --- a/net/dsa/tag_mtk.c
> +++ b/net/dsa/tag_mtk.c
[ ... ]
> @@ -107,8 +112,33 @@ static const struct dsa_device_ops mtk_netdev_ops = {
> .needed_headroom = MTK_HDR_LEN,
> };
>
> -MODULE_DESCRIPTION("DSA tag driver for Mediatek switches");
> -MODULE_LICENSE("GPL");
> +DSA_TAG_DRIVER(mtk_netdev_ops);
> MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_MTK, MTK_NAME);
> +#endif
>
> -module_dsa_tag_driver(mtk_netdev_ops);
> +#if IS_ENABLED(CONFIG_NET_DSA_TAG_AIROHA)
> +static const struct dsa_device_ops airoha_netdev_ops = {
> + .name = AIROHA_NAME,
> + .proto = DSA_TAG_PROTO_AIROHA,
> + .xmit = mtk_tag_xmit,
> + .rcv = mtk_tag_rcv,
> + .needed_headroom = MTK_HDR_LEN,
> +};
[Severity: Medium]
This adds a second proto ID for the same wire format as
DSA_TAG_PROTO_MTK. Several conduit drivers handle this tag format in
hardware, but they only check for DSA_TAG_PROTO_MTK. None of them are
updated here or later in the series.
Once an8855_get_tag_protocol() returns DSA_TAG_PROTO_AIROHA, will AN8855
switches behind these conduits lose that handling?
In drivers/net/ethernet/mediatek/mtk_ppe_offload.c:
mtk_flow_get_dsa_port() {
...
if (dp->cpu_dp->tag_ops->proto != DSA_TAG_PROTO_MTK)
return -ENODEV;
...
}
After the -ENODEV, *dev is still the DSA user netdev. That means
mtk_flow_set_output_device() fails every eth->netdev[] comparison and
returns -EOPNOTSUPP.
Would this reject nft flowtable hardware offload through AN8855 user
ports, even though mtk_foe_entry_set_dsa() would build the same tag?
In drivers/net/ethernet/mediatek/mtk_ppe.c, mtk_ppe_check_skb() skips
PPE binding for ETH_P_XDSA frames:
case htons(ETH_P_XDSA):
if (!netdev_uses_dsa(skb->dev) ||
skb->dev->dsa_ptr->tag_ops->proto != DSA_TAG_PROTO_MTK)
goto out;
In drivers/net/ethernet/mediatek/mtk_eth_soc.c, mtk_uses_dsa() would
return false:
return netdev_uses_dsa(dev) &&
dev->dsa_ptr->tag_ops->proto == DSA_TAG_PROTO_MTK;
On NETSYS v1, mtk_open() then takes the branch that clears
MTK_CDMP_STAG_EN. That turns off hardware special tag untagging and RX
VLAN offload.
In drivers/net/ethernet/airoha/airoha_eth.c, airoha_get_dsa_tag()
returns early:
if (dev->dsa_ptr->tag_ops->proto != DSA_TAG_PROTO_MTK)
return 0;
So the 4-byte special tag stays in the frame and is not moved into the
QDMA descriptor. That goes against the driver's own comment:
/* PPE module requires untagged DSA packets to work properly,
* so move DSA tag to DMA descriptor.
The RX side of that driver still turns on hardware special tag
stripping (GDM_STAG_EN_MASK in REG_GDM_INGRESS_CFG), based only on
netdev_uses_dsa(). TX and RX handling would then no longer match.
The DSA user netdev also inherits the conduit vlan_features
(AIROHA_HW_FEATURES). If the QDMA/FE cannot parse L3/L4 headers behind
an in-frame MTK tag, could CHECKSUM_PARTIAL or TSO frames end up with
bad checksums? I couldn't confirm that hardware behaviour from the code.
Should these conduit checks accept both DSA_TAG_PROTO_MTK and
DSA_TAG_PROTO_AIROHA, maybe through a shared helper? If not, is a
separate proto ID needed for an identical tag format?
> +
> +DSA_TAG_DRIVER(airoha_netdev_ops);
> +MODULE_ALIAS_DSA_TAG_DRIVER(DSA_TAG_PROTO_AIROHA, AIROHA_NAME);
> +#endif
[ ... ]
--
Sashiko AI review · https://netdev-ai.bots.linux.dev/sashiko/#/patchset/20261009161102.38961-1-ansuelsmth%40gmail.com
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH net-next v25 09/10] net: dsa: mt7530: generalize and move common function to lib module
2026-10-09 16:10 ` [PATCH net-next v25 09/10] net: dsa: mt7530: generalize and move common function to lib module Christian Marangi
@ 2026-10-10 16:19 ` netdev-bot+sashiko
0 siblings, 0 replies; 18+ messages in thread
From: netdev-bot+sashiko @ 2026-10-10 16:19 UTC (permalink / raw)
To: ansuelsmth
Cc: lee, robh, krzk+dt, conor+dt, andrew+netdev, davem, edumazet,
kuba, pabeni, olteanv, matthias.bgg, angelogioacchino.delregno,
chester.a.unal, daniel, hkallweit1, linux, horms, joey,
linux-arm-kernel, linux-mediatek, netdev, mfd, devicetree,
linux-kernel, andrew
Thank you for your contribution! Sashiko AI review found 8 potential
issue(s) to consider.
Critical: 0 · High: 2 · Medium: 4 (1) · Low: 2
If you believe none of the issues are legitimate, please reply to each
issue of Medium severity or higher and explain why the AI is wrong.
If any of them are legitimate and you plan to respin, please let patchwork
know by including "pw-bot: cr" as a separate line at the end of your reply
(one such reply per series is enough).
- [High] Name collision between the new enum constant and an old register
macro in drivers/net/dsa/mediatek/mt7530.c.
- [High] net: severe MDIO bus performance regression via sequential
regmap_field accesses
- [Medium] EN7528 port mirroring now programs the wrong register.
- [Medium] VLAN table entries written by
mt7530_hw_vlan_add()/mt7530_hw_vlan_del()…
- [Medium] Failed final status reads are treated as success.
- [Medium] The switch to regmap_field_read() introduces uninitialized
stack reads.
- [Low] mt7530_lib_mib_reset() replaces the two full writes to
MT7530_MIB_CCR (CCR_MIB_FLUSH = 0xF0, then CCR_MIB_ACTIVATE =…
- [Low] Two comments no longer match the definitions they describe.
Pre-existing issues:
- [Medium] This problem wasn't introduced by this patch, but
mt7530_port_fdb_dump() saves the callback's return value (for example…
--
net: dsa: mt7530: generalize and move common function to lib module
This moves the common MT7530 FDB, VLAN, bridge, mirror, MTU and MIB
helpers into a new mt7530-lib module. They are reimplemented on top of the
regmap_field API, and the per-chip mirror register layout is now
described by a reg_field table in mt753x_info. The commit message states
that no behaviour change is expected.
> diff --git a/drivers/net/dsa/mediatek/mt7530-lib.c b/drivers/net/dsa/mediatek/mt7530-lib.c
> new file mode 100644
> index 0000000000000..098dd45d3ee9f
> --- /dev/null
> +++ b/drivers/net/dsa/mediatek/mt7530-lib.c
> @@ -0,0 +1,1128 @@
[ ... ]
> +void mt7530_lib_mib_reset(struct mt7530_lib_priv *priv)
> +{
> + regmap_field_write(priv->fields[MT7530_CCR_MIB_ENABLE], 0);
> + regmap_field_write(priv->fields[MT7530_CCR_RX_OCT_CNT_GOOD], 1);
> + regmap_field_write(priv->fields[MT7530_CCR_RX_OCT_CNT_BAD], 1);
> + regmap_field_write(priv->fields[MT7530_CCR_TX_OCT_CNT_GOOD], 1);
> + regmap_field_write(priv->fields[MT7530_CCR_TX_OCT_CNT_BAD], 1);
> + regmap_field_write(priv->fields[MT7530_CCR_MIB_ENABLE], 1);
> +}
[Severity: Low]
Is this sequence equivalent to the old one? The removed
mt7530_mib_reset() wrote the whole register twice:
regmap_write(priv->regmap, MT7530_MIB_CCR, CCR_MIB_FLUSH);
regmap_write(priv->regmap, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);
regmap_field_write() is a read-modify-write that skips the bus write when
the value is unchanged. If MIB_ENABLE already reads as 0, the flush write
is never sent.
Bits 30:8 and 3:0 of MT7530_MIB_CCR are also no longer forced to 0, so
reset or bootloader values in those bits survive.
Could this change how the MIB counters get cleared and activated compared
with the old code? Separately, the MT7530_CCR_TX_OCT_CNT_GOOD write is
misrouted by the MT7530_MIRROR_EN collision described further down.
[ ... ]
> +int mt7530_lib_fdb_cmd(struct mt7530_lib_priv *priv, enum mt7530_fdb_cmd cmd,
> + u32 mat, u32 *rsp)
> +{
[Severity: High]
How much extra MDIO traffic does this add on MDIO-connected switches?
On MT7530 and MT7531, each 32-bit register access already costs
several MDIO frames. mt7530_regmap_read() and mt7530_regmap_write()
each issue a page select plus two 16-bit transfers.
The old mt7530_fdb_read() did three regmap_read() calls, on TSRA1,
TSRA2 and ATRD. This version does ten regmap_field_read() calls, and
each one is a separate bus read of one of those same three registers.
That is more than three times the bus traffic for every entry.
The write side is worse. regmap_field_write() goes through
regmap_update_bits_base(). These regmaps don't appear to have a
register cache, and the ARL registers are volatile anyway. So each
call is a bus read, followed by a write when the value differs.
mt7530_lib_fdb_write() does three clearing writes and then twelve
field writes. That is up to 15 reads and 15 writes, where
mt7530_fdb_write() did three plain regmap_write() calls.
mt7530_lib_fdb_cmd() likewise turns the single ATC write into three
read-modify-write cycles before the BUSY poll.
mt7530_port_fdb_dump() goes through this path once per entry, up to
MT7530_NUM_FDB_RECORDS times, while holding reg_mutex. Every
port_fdb_add/del and port_mdb_add/del also pays the expanded cost.
The VLAN paths do too: mt7530_hw_vlan_add(), mt7530_hw_vlan_del() and
mt7530_lib_setup_vlan0() now do one read-modify-write per field. The
old code built VAWD1 in software and wrote it once.
The result is a large increase in FDB dump and update latency. It also
adds a lot of MDIO bus load that the PHYs on the same bus have to
compete with. That doesn't seem to fit "No behaviour change is
expected".
Could the library build the full ATA1/ATA2/ATWD and VAWD1 values in
software and write each register once? On the read side, it could read
TSRA1/TSRA2/ATRD once and extract the fields from those values. The
per-chip layout could then be described with masks rather than
separate regmap_field accesses. Alternatively, were FDB dump times
measured on an MDIO-attached MT7531 before and after this change?
[ ... ]
> + ret = regmap_field_read_poll_timeout(priv->fields[MT7530_ATC_BUSY],
> + val, !val, 20, 20000);
> + if (ret < 0) {
> + dev_err(priv->dev, "reset timeout\n");
> + return ret;
> + }
> +
> + regmap_field_read(priv->fields[MT7530_ATC_INVALID], &val);
> + if (cmd == MT7530_FDB_READ && val)
> + return -EINVAL;
> +
> + if (rsp)
> + regmap_field_read(priv->fields[__MT7530_ATC], rsp);
> +
> + return 0;
> +}
[Severity: Medium]
What happens here if one of these final reads fails? After a successful
BUSY poll, val is 0. regmap_field_read() returns early on error without
touching its output:
ret = regmap_read(field->regmap, field->reg, ®_val);
if (ret != 0)
return ret;
A failed ATC_INVALID read therefore makes a failed FDB_READ look like a
valid hit. The unchecked rsp read leaves the caller's previous rsp in
place, so mt7530_port_fdb_dump() could act on stale ATC_SRCH_HIT or
ATC_SRCH_END bits.
mt7530_vlan_cmd() does the same with the MT7530_VTCR_INVALID read and
returns 0.
The removed helpers propagated these errors:
if (!ret)
ret = regmap_read(priv->regmap, MT7530_ATC, &val);
if (ret < 0) {
...
return ret;
}
Should the return values of these reads be checked?
[ ... ]
> +int mt7530_lib_port_mdb_add(struct mt7530_lib_priv *priv, int port,
> + const struct switchdev_obj_port_mdb *mdb,
> + struct dsa_db db)
> +{
> + const u8 *addr = mdb->addr;
> + u16 vid = mdb->vid;
> + u8 port_mask = 0;
> + u32 val;
> + int ret;
> +
> + mutex_lock(priv->reg_mutex);
> +
> + mt7530_lib_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP);
> + if (!mt7530_lib_fdb_cmd(priv, MT7530_FDB_READ,
> + ATC_MAT_MACTAB, NULL)) {
> + regmap_field_read(priv->fields[MT7530_ATRD_PORT_MAP],
> + &val);
> + port_mask = val;
> + }
[Severity: Medium]
Can val be used uninitialized here? regmap_field_read() reads into its own
temporary and does not assign *val when regmap_read() fails.
Before this patch, regmap_read() passed the caller's pointer straight down
to mt7530_regmap_read() in mt7530-mdio.c, which does:
/* Callers do not check for errors, keep the value deterministic */
*val = 0;
With the field API that zeroing only reaches the temporary inside
regmap_field_read(). On an MDIO read failure, an indeterminate port_mask
would then be written back into the ARL entry.
The same pattern appears in mt7530_lib_port_mdb_del() with
MT7530_ATRD_PORT_MAP. It also appears in mt7530_hw_vlan_del(), which
branches on an uninitialized val after reading MT7530_VAWD_VLAN_VALID.
[ ... ]
> +static void mt7530_hw_vlan_add(struct mt7530_lib_priv *priv,
> + struct mt7530_hw_vlan_entry *entry)
> +{
[ ... ]
> + regmap_field_write(priv->fields[MT7530_VAWD_IVL_MAC], 1);
> + regmap_field_write(priv->fields[MT7530_VAWD_VTAG_EN], 1);
> + regmap_field_write(priv->fields[MT7530_VAWD_PORT_MEM],
> + new_members);
> + regmap_field_write(priv->fields[MT7530_VAWD_FID],
> + FID_BRIDGED);
> + regmap_field_write(priv->fields[MT7530_VAWD_VLAN_VALID], 1);
[ ... ]
> + if (new_members) {
> + regmap_field_write(priv->fields[MT7530_VAWD_IVL_MAC], 1);
> + regmap_field_write(priv->fields[MT7530_VAWD_VTAG_EN], 1);
> + regmap_field_write(priv->fields[MT7530_VAWD_PORT_MEM],
> + new_members);
> + regmap_field_write(priv->fields[MT7530_VAWD_VLAN_VALID], 1);
> + } else {
[Severity: Medium]
Are these VLAN entries still fully defined? The old mt7530_hw_vlan_add()
wrote the whole register:
val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) |
VLAN_VALID;
regmap_write(priv->regmap, MT7530_VAWD1, val);
That cleared EG_CON (bit 29) and PORT_STAG (bit 31). The field
read-modify-writes here keep whatever RD_VID or an earlier access left in
VAWD1.
mt7530_hw_vlan_update() ignores the result of:
mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid);
If that command fails, VAWD1 can still hold the VID 0 entry staged by
mt7530_lib_setup_vlan0() with EG_CON set. Could the new VLAN then be
written with EG_CON=1, overriding the per-VLAN ETAG?
In mt7530_hw_vlan_del() with members remaining, the old code wrote VAWD1
without FID, which reset it to 0 (FID_STANDALONE). The new code keeps
FID_BRIDGED. Does that change which FID_PST STP state applies to the VLAN
after a member is removed?
Even if the new behaviour is preferable, it seems to differ from "No
behaviour change is expected".
[ ... ]
> diff --git a/drivers/net/dsa/mediatek/mt7530.c b/drivers/net/dsa/mediatek/mt7530.c
> index 7781a63b4e6fd..6087e5826780f 100644
> --- a/drivers/net/dsa/mediatek/mt7530.c
> +++ b/drivers/net/dsa/mediatek/mt7530.c
> @@ -24,10 +24,163 @@
> #include <net/pkt_cls.h>
>
> #include "mt7530.h"
> +#include "mt7530-lib.h"
[ ... ]
> +static const struct mt7530_reg_field mt7530_fields[] = {
> + { MT7530_MIRROR_EN, REG_FIELD(MT753X_MFC, 3, 3) },
> + { MT7530_MIRROR_PORT, REG_FIELD(MT753X_MFC, 0, 2) },
> +};
> +
> +static const struct mt7530_reg_field mt7531_fields[] = {
> + { MT7530_MIRROR_EN, REG_FIELD(MT7531_CFC, 19, 19) },
> + { MT7530_MIRROR_PORT, REG_FIELD(MT7531_CFC, 16, 18) },
> +};
[Severity: High]
Does MT7530_MIRROR_EN expand to the new enum value in these tables?
mt7530.h includes mt7530-lib.h but still keeps the old register macro:
#define MT7530_MIRROR_EN BIT(3)
In enum mt7530_regmap_field, MT7530_MIRROR_EN is 0 and
MT7530_CCR_TX_OCT_CNT_GOOD is 8. By the time these tables are compiled in
mt7530.c the macro is defined, so their id becomes BIT(3), which is 8.
mt7530_setup_lib_priv() then does:
lib_priv->fields[reg_field->id] = field;
That overwrites fields[MT7530_CCR_TX_OCT_CNT_GOOD] with the mirror enable
field and leaves fields[0] NULL. mt7530-lib.c does not include mt7530.h,
so MT7530_MIRROR_EN is 0 there.
Wouldn't this oops when a matchall mirror is offloaded?
mt753x_port_mirror_add()
mt7530_lib_port_mirror_add()
regmap_field_read(priv->fields[MT7530_MIRROR_EN], &val)
field->regmap on a NULL field
mt7530_lib_port_mirror_del() would hit the same NULL in
regmap_field_write().
Also, on every setup:
mt7530_setup() / mt7531_setup_common()
mt7530_lib_mib_reset()
regmap_field_write(priv->fields[MT7530_CCR_TX_OCT_CNT_GOOD], 1)
This now sets MFC bit 3 (or CFC bit 19), enabling the mirror engine at
boot, and MIB_CCR bit 5 is never set.
Would dropping or renaming the old MT7530_MIRROR_EN macro in mt7530.h
avoid this? The collision appears to still be present at the end of the
series.
[ ... ]
> @@ -35,15 +188,15 @@ static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs)
>
> /* String, offset, and register size in bytes if different from 4 bytes */
> static const struct mt7530_mib_desc mt7530_mib[] = {
[ ... ]
> + MIB_DESC(MT7530_MIB_TX_DROP, -1, "TxDrop"),
[Severity: Low]
This isn't a bug, but the comment above mt7530_mib[] still describes
offset and size. struct mt7530_mib_desc now holds field_low and
field_high regmap field indices.
In mt7530.h, "Each define is an offset of MT7530_PORT_MIB_COUNTER" no
longer holds either. The MT7530_PORT_MIB_* macros are now absolute port 0
addresses (MT7530_MIB_COUNTER + off), and the "64 bytes" notes now sit on
the *_BYTES_LOW halves.
Both comments are still present at the end of the series.
[ ... ]
> @@ -1769,13 +1233,14 @@ mt7530_port_fdb_dump(struct dsa_switch *ds, int port,
>
> mutex_lock(&priv->reg_mutex);
>
> - ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp);
> + ret = mt7530_lib_fdb_cmd(&priv->lib_priv, MT7530_FDB_START,
> + ATC_MAT_MACTAB, &rsp);
> if (ret < 0)
> goto err;
>
> do {
> if (rsp & ATC_SRCH_HIT) {
> - mt7530_fdb_read(priv, &_fdb);
> + mt7530_lib_fdb_read(&priv->lib_priv, &_fdb);
> if (_fdb.port_mask & BIT(port)) {
> ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp,
> data);
> @@ -1785,7 +1250,8 @@ mt7530_port_fdb_dump(struct dsa_switch *ds, int port,
> }
> } while (--cnt &&
> !(rsp & ATC_SRCH_END) &&
> - !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp));
> + !mt7530_lib_fdb_cmd(&priv->lib_priv, MT7530_FDB_NEXT,
> + ATC_MAT_MACTAB, &rsp));
> err:
> mutex_unlock(&priv->reg_mutex);
>
[Severity: Medium]
This is a pre-existing issue and was not introduced by this patch. The
function saves ret from cb() and breaks out of the loop, but always ends
with:
err:
mutex_unlock(&priv->reg_mutex);
return 0;
dsa_user_port_fdb_do_dump() returns -EMSGSIZE once the netlink skb is
full, and rtnl_fdb_dump() only keeps its continuation position for
-EMSGSIZE. Could the remaining FDB entries be silently dropped from a
multi-part bridge fdb show?
[ ... ]
> @@ -3513,6 +2744,8 @@ const struct mt753x_info mt753x_table[] = {
> },
> [ID_EN7528] = {
> .id = ID_EN7528,
> + .reg_fields = mt7531_fields,
> + .num_reg_fields = ARRAY_SIZE(mt7531_fields),
> .pcs_ops = &mt7530_pcs_ops,
> .sw_setup = mt7988_setup,
> .phy_read_c22 = mt7531_ind_c22_phy_read,
[Severity: Medium]
Should EN7528 use mt7530_fields here? The old MT753X_MIRROR_REG(),
MT753X_MIRROR_EN() and related macros in mt7530.h only selected
MT7531_CFC for ID_MT7531, ID_MT7988, ID_EN7581 and ID_AN7583. EN7528
therefore used MT753X_MFC, with enable at bit 3 and the monitor port in
bits 2:0.
With mt7531_fields, mt7530_lib_port_mirror_add() and
mt7530_lib_port_mirror_del() on EN7528 now read-modify-write MT7531_CFC
bit 19 and bits 18:16 instead.
The rest of the driver treats EN7528 as having the MT7530-style MFC
layout:
if (priv->id != ID_MT7530 && priv->id != ID_MT7621 &&
priv->id != ID_EN7528)
return;
That is from mt753x_conduit_state_change(). mt753x_cpu_port_enable() also
skips the MT7531_CFC CPU_PMAP setup for EN7528.
Does mirroring then silently stop working on EN7528, while bits get
written in a register this chip otherwise doesn't program? The
MT7530_MIRROR_EN collision above currently crashes earlier in this path,
but this mapping would remain once that is fixed. It is unchanged at the
end of the series.
[ ... ]
--
Sashiko AI review · https://netdev-ai.bots.linux.dev/sashiko/#/patchset/20261009161102.38961-1-ansuelsmth%40gmail.com
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH net-next v25 10/10] net: dsa: Add Airoha AN8855 5-Port Gigabit DSA Switch driver
2026-10-09 16:10 ` [PATCH net-next v25 10/10] net: dsa: Add Airoha AN8855 5-Port Gigabit DSA Switch driver Christian Marangi
@ 2026-10-10 16:19 ` netdev-bot+sashiko
0 siblings, 0 replies; 18+ messages in thread
From: netdev-bot+sashiko @ 2026-10-10 16:19 UTC (permalink / raw)
To: ansuelsmth
Cc: lee, robh, krzk+dt, conor+dt, andrew+netdev, davem, edumazet,
kuba, pabeni, olteanv, matthias.bgg, angelogioacchino.delregno,
chester.a.unal, daniel, hkallweit1, linux, horms, joey,
linux-arm-kernel, linux-mediatek, netdev, mfd, devicetree,
linux-kernel, andrew
Thank you for your contribution! Sashiko AI review found 15 potential
issue(s) to consider.
Critical: 0 · High: 2 · Medium: 9 · Low: 4
If you believe none of the issues are legitimate, please reply to each
issue of Medium severity or higher and explain why the AI is wrong.
If any of them are legitimate and you plan to respin, please let patchwork
know by including "pw-bot: cr" as a separate line at the end of your reply
(one such reply per series is enough).
- [High] an8855_port_enable() writes 0 to the port matrix instead of the
value it just computed.
- [High] On AN8855 the shared VLAN code reads table entries back from the
write-data register.
- [Medium] The patch makes the MT7530_ATC_INVALID check in
mt7530_lib_fdb_cmd() optional and gives AN8855 no replacement.
- [Medium] an8855_port_change_mtu() calls mt7530_lib_port_change_mtu()
directly.
- [Medium] an8855_set_mac_eee() rejects `tx_lpi_timer > 0xFFF`, a limit
copied from MT7530's 12-bit LPI_THRESH field.
- [Medium] The SGMII 'PCS Init' block in an8855_pcs_config() is dead
code.
- [Medium] an8855_port_fdb_dump() calls usleep_range(1000, 1500) for
every valid bank entry while it walks up to AN8855_NUM_FDB_RECORDS…
- [Medium] In an8855_pcs_config(), the 'PLL - SDM' step applies
AN8855_RG_DA_QP_PLL_SDM_HREN_INTF to AN8855_PLL_CTRL_2, but the header…
- [Medium] For SGMII without in-band negotiation, an8855_pcs_config()
always forces the PCS to 1000 Mb/s (AN8855_RG_LINK_MODE_P0_SPEED_1000…
- [Medium] The new driver adds `ethtool -S` strings for counters that
already have standard uAPIs.
- [Medium] net: dsa: an8855: missing mtu_enforcement_ingress flag allows
MTU violation
- [Low] NET_DSA_AN8855 is declared with `depends on MFD_AIROHA_AN8855 ||
COMPILE_TEST` and does not select REGMAP.
- [Low] The last RMON histogram bucket in an8855_rmon_ranges is { 1519,
AN8855_MAX_MTU }.
- [Low] an8855_phylink_mac_link_up() initialises `u32 reg = 0`, ignores
the return value of `regmap_read(priv->regmap, AN8855_PMCR_P(port),…
- [Low] an8855_port_fdb_dump() declares `u32 rsp;` without initialising
it and passes &rsp to mt7530_lib_fdb_cmd().
--
net: dsa: Add Airoha AN8855 5-Port Gigabit DSA Switch driver
This adds a DSA driver for the Airoha AN8855 5-port gigabit switch. It is
built on the shared mt7530-lib helpers and has an SGMII/2500BASE-X PCS for
the CPU port. mt7530-lib gains optional AN8855-specific regmap fields, and
its ATC/VTCR invalid checks become optional.
> diff --git a/drivers/net/dsa/mediatek/Kconfig b/drivers/net/dsa/mediatek/Kconfig
> index 7b48300dca0c5..2799e78a86517 100644
> --- a/drivers/net/dsa/mediatek/Kconfig
> +++ b/drivers/net/dsa/mediatek/Kconfig
> @@ -1,4 +1,14 @@
> # SPDX-License-Identifier: GPL-2.0-only
> +config NET_DSA_AN8855
> + tristate "Airoha AN8855 Ethernet switch support"
> + depends on MFD_AIROHA_AN8855 || COMPILE_TEST
> + depends on NET_DSA
> + select NET_DSA_MT7530_LIB
> + select NET_DSA_TAG_AIROHA
[Severity: Low]
Can REGMAP end up disabled with COMPILE_TEST=y and MFD_AIROHA_AN8855=n?
NET_DSA_MT7530_LIB is a bare tristate, and REGMAP normally comes in
because MFD_AIROHA_AN8855 selects it.
struct reg_field, REG_FIELD() and devm_regmap_field_alloc() are declared
only under CONFIG_REGMAP in include/linux/regmap.h, with no stubs. In
that configuration an8855.c and mt7530-lib.c would fail to build.
Should this also select REGMAP?
> diff --git a/drivers/net/dsa/mediatek/an8855.c b/drivers/net/dsa/mediatek/an8855.c
> new file mode 100644
> index 0000000000000..22171cd885c70
> --- /dev/null
> +++ b/drivers/net/dsa/mediatek/an8855.c
> @@ -0,0 +1,1765 @@
[ ... ]
> + { MT7530_VAWD_IVL_MAC, REG_FIELD(AN8855_VAWD0, 5, 5) },
> + { MT7530_VAWD_EG_CON, REG_FIELD(AN8855_VAWD0, 11, 11) },
> + { MT7530_VAWD_VTAG_EN, REG_FIELD(AN8855_VAWD0, 10, 10) },
> + { MT7530_VAWD_PORT_MEM, REG_FIELD(AN8855_VAWD0, 26, 31) },
> + { MT7530_VAWD_FID, REG_FIELD(AN8855_VAWD0, 1, 4) },
> + { MT7530_VAWD_VLAN_VALID, REG_FIELD(AN8855_VAWD0, 0, 0) },
> + { __MT7530_VAWD1, REG_FIELD(AN8855_VAWD0, 0, 31) },
> +
> + { MT7530_VAWD_ETAG, REG_FIELD(AN8855_VAWD0, 12, 23) },
[Severity: High]
After a VTCR read command, the shared VLAN code reads the entry back
through these fields:
- mt7530_hw_vlan_update() reads MT7530_VAWD_PORT_MEM for old_members.
- mt7530_hw_vlan_del() checks MT7530_VAWD_VLAN_VALID.
- mt7530_hw_vlan_add() does a read-modify-write of MT7530_VAWD_ETAG.
All of these map to AN8855_VAWD0, which is the write-data register.
an8855.h also defines a read-data register that nothing maps:
/* Same register field of VAWD0 */
#define AN8855_VARD0 0x10200618
If MT7530_VTCR_RD_VID returns its result in VARD0, does the VLAN code
read back whatever was last written to VAWD0 instead?
For example, mt7530_lib_setup_vlan0() leaves PORT_MEM =
MT7530_ALL_MEMBERS in VAWD0. A following bridge vlan add for another VID
could then start from all members. Could deletes also take the
invalid-entry path, or clear the wrong members?
> +static const struct mt7530_mib_desc an8855_mib[] = {
> + MIB_DESC(MT7530_MIB_TX_DROP, -1, "TxDrop"),
> + MIB_DESC(MT7530_MIB_TX_CRC_ERR, -1, "TxCrcErr"),
> + MIB_DESC(MT7530_MIB_TX_COLLISION, -1, "TxCollision"),
> + MIB_DESC(AN8855_MIB_TX_OVERSIZE_DROP, -1, "TxOversizeDrop"),
> + MIB_DESC(AN8855_MIB_TX_BAD_PKT_BYTES_LOW,
> + AN8855_MIB_TX_BAD_PKT_BYTES_HIGH, "TxBadPktBytes"),
> + MIB_DESC(MT7530_MIB_RX_DROP, -1, "RxDrop"),
> + MIB_DESC(MT7530_MIB_RX_FILTERING, -1, "RxFiltering"),
> + MIB_DESC(MT7530_MIB_RX_CRC_ERR, -1, "RxCrcErr"),
[Severity: Medium]
Several of these ethtool -S strings duplicate counters that already have
standard interfaces:
- "RxCrcErr" is FrameCheckSequenceErrors in ethtool_eth_mac_stats and
rx_crc_errors in rtnl_link_stats64.
- "TxCollision" is collisions.
- "RxDrop" and "TxDrop" are rx_dropped and tx_dropped.
an8855_switch_ops also has no .get_stats64. mt7530.c fills
rtnl_link_stats64 from the same field IDs in mt7530_get_stats64(). In
addition, mt7530_lib_get_eth_mac_stats() does not fill
FrameCheckSequenceErrors.
Could these be reported through the standard interfaces rather than as
driver-private strings?
[ ... ]
> +static int an8855_port_fdb_dump(struct dsa_switch *ds, int port,
> + dsa_fdb_dump_cb_t *cb, void *data)
> +{
> + struct an8855_priv *priv = ds->priv;
> + int banks, count = 0;
> + u32 rsp;
> + int ret;
> + int i;
> +
> + mutex_lock(&priv->reg_mutex);
> +
> + /* Load search port */
> + ret = regmap_write(priv->regmap, AN8855_ATWD2,
> + FIELD_PREP(AN8855_ATWD2_PORT, BIT(port)));
> + if (ret)
> + goto exit;
> + ret = mt7530_lib_fdb_cmd(&priv->lib_priv, MT7530_FDB_START,
> + AN8855_FDB_MAT_MAC_PORT, &rsp);
> + if (ret < 0)
> + goto exit;
> +
> + do {
> + /* From response get the number of banks to read, exit if 0 */
> + banks = FIELD_GET(AN8855_ATC_HIT, rsp);
[Severity: Low]
rsp is not initialised, and mt7530_lib_fdb_cmd() ignores the return value
of the response read:
if (rsp)
regmap_field_read(priv->fields[__MT7530_ATC], rsp);
return 0;
On a read error regmap_field_read() returns without writing *val. If that
read fails after a successful BUSY poll, does this FIELD_GET() work on an
indeterminate value?
> + if (!banks)
> + break;
> +
> + /* Each banks have 4 entry */
> + for (i = 0; i < 4; i++) {
> + struct mt7530_fdb _fdb = { };
> +
> + count++;
> +
> + /* Check if bank is present */
> + if (!(banks & BIT(i)))
> + continue;
> +
> + /* Select bank entry index */
> + ret = regmap_write(priv->regmap, AN8855_ATRDS,
> + FIELD_PREP(AN8855_ATRD_SEL, i));
> + if (ret)
> + break;
> + /* wait 1ms for the bank entry to be filled */
> + usleep_range(1000, 1500);
> + mt7530_lib_fdb_read(&priv->lib_priv, &_fdb);
[Severity: Medium]
This sleeps once per valid entry while walking up to
AN8855_NUM_FDB_RECORDS (2048) slots. Each MT7530_FDB_NEXT can also poll
ATC_BUSY for up to 20ms.
All of this runs under priv->reg_mutex and rtnl_lock, because the
PF_BRIDGE RTM_GETNEIGH dumpit (rtnl_fdb_dump) is not registered as
unlocked.
The dump needs no CAP_NET_ADMIN, and learning on bridged ports can fill
the table. Could one unprivileged bridge fdb show hold rtnl for seconds?
The walk also restarts from the beginning on every netlink continuation,
so the delay would repeat each time.
Is the per-entry 1ms sleep needed? The MT7530 dump does not have one.
[ ... ]
> +static int an8855_port_change_mtu(struct dsa_switch *ds, int port,
> + int new_mtu)
> +{
> + struct an8855_priv *priv = ds->priv;
> +
> + return mt7530_lib_port_change_mtu(&priv->lib_priv, port, new_mtu);
> +}
[Severity: Medium]
For jumbo frames, mt7530_lib_port_change_mtu() writes a linear KiB count:
regmap_field_write(priv->fields[MT7530_GMACCR_MAX_RX_JUMBO],
DIV_ROUND_UP(length, 1024));
The AN8855_MAX_RX_JUMBO_* defines in an8855.h describe a non-linear
encoding: 0x0-0x2 = 2K, 0x3-0x9 = 3K-9K, 0xa = 12K, 0xb = 15K,
0xc = 16K. AN8855_MAX_MTU allows frame lengths up to 15360.
With that encoding, frame lengths of 9217-12288 bytes would be written as
0xa-0xc (12K/15K/16K). Lengths of 12289-15360 bytes would be written as
0xd-0xf, which are not defined. Is that intended? None of the
AN8855_MAX_RX_JUMBO_* macros seem to be used.
[ ... ]
> +static const struct ethtool_rmon_hist_range an8855_rmon_ranges[] = {
> + { 0, 64 },
> + { 65, 127 },
> + { 128, 255 },
> + { 256, 511 },
> + { 512, 1023 },
> + { 1024, 1518 },
> + { 1519, AN8855_MAX_MTU },
> + {}
> +};
[Severity: Low]
AN8855_MAX_MTU is an L3 MTU: 15360 - ETH_HLEN - ETH_FCS_LEN -
MTK_TAG_LEN = 15338. ethtool_rmon_hist_range bounds are frame lengths.
Should the upper bound be the maximum frame length (15360) instead?
[ ... ]
> +static int an8855_port_enable(struct dsa_switch *ds, int port,
> + struct phy_device *phy)
> +{
> + struct dsa_port *dp = dsa_to_port(ds, port);
> + struct an8855_priv *priv = ds->priv;
> + int ret;
> +
> + mutex_lock(&priv->reg_mutex);
> +
> + /* Allow the user port gets connected to the cpu port and also
> + * restore the port matrix if the port is the member of a certain
> + * bridge.
> + */
> + if (dsa_port_is_user(dp)) {
> + struct dsa_port *cpu_dp = dp->cpu_dp;
> +
> + priv->ports[port].pm |= BIT(cpu_dp->index);
> + }
> + priv->ports[port].enable = true;
> + ret = regmap_fields_write(priv->lib_priv.fields[MT7530_PCR_MATRIX],
> + port, 0);
[Severity: High]
Should this write priv->ports[port].pm instead of 0? The pm value
computed just above is never used, so the port matrix is empty once the
port is enabled.
an8855_setup() sets AN8855_PORTMATRIX_P(user) to BIT(AN8855_CPU_PORT).
dsa_user_open()->dsa_port_enable_rt()->an8855_port_enable() then
overwrites it with 0.
Would a standalone user port then be unable to forward to the CPU port
until a bridge join or leave calls mt7530_update_port_member()?
The same would happen in two other cases:
- The CPU port's dsa_user_ports() matrix would be cleared when DSA
enables the CPU port.
- A port that was bridged before it came up would lose its membership,
because mt7530_update_port_member() skips the write for disabled ports.
For comparison, mt7530_port_enable() writes
PCR_MATRIX(priv->ports[port].pm) at this point.
[ ... ]
> +static int an8855_set_mac_eee(struct dsa_switch *ds, int port,
> + struct ethtool_keee *e)
> +{
> + if (e->tx_lpi_timer > 0xFFF)
> + return -EINVAL;
> +
> + return 0;
> +}
[Severity: Medium]
Should an8855_setup() also set ds->mtu_enforcement_ingress?
mt7530_lib_port_change_mtu() returns early for every port except the
CPU port, because GMACCR is a single global RX length limit. It relies
on DSA setting the CPU port MTU to the largest user port MTU, and
programs that value into the switch.
The per-port MTUs are therefore never enforced in hardware. Take two
user ports in the same bridge with different MTUs. The port with the
smaller MTU still accepts frames up to the largest configured MTU, so
its own setting is silently ignored on ingress.
ds->mtu_enforcement_ingress exists for switches that only have a
global MRU. With it set, DSA normalizes the MTU of all bridged ports
when one of them changes, so the global limit matches what every
bridged port is configured for. The MT7530 setup path sets it for this
reason.
This could be set next to assisted_learning_on_cpu_port. Or is there
something on AN8855 that enforces the per-port MTU that I am missing?
[Severity: Medium]
The 0xFFF limit matches MT7530's 12-bit LPI threshold. On AN8855 the
timer field is AN8855_LPI_TXIDLE_THD_MASK, GENMASK(31, 14), in 2us units,
and an8855_phylink_mac_enable_tx_lpi() already clamps the value to it.
an8855_phylink_get_caps() takes lpi_timer_default from CKGCR. Its comment
gives the default as 60ms, which is about 60000us.
The resulting call sequence is:
- phylink reports that default through get_eee.
- ethnl_set_eee() keeps it unless the user passes tx-timer.
- dsa_user_set_eee() then calls set_mac_eee() with it.
Would any ethtool --set-eee on a user port, including eee off, fail with
-EINVAL unless it also passes tx-timer <= 4095?
[ ... ]
> +static void an8855_phylink_mac_link_up(struct phylink_config *config,
> + struct phy_device *phydev, unsigned int mode,
> + phy_interface_t interface, int speed,
> + int duplex, bool tx_pause, bool rx_pause)
> +{
> + struct dsa_port *dp = dsa_phylink_to_port(config);
> + struct an8855_priv *priv = dp->ds->priv;
> + int port = dp->index;
> + u32 reg = 0;
> +
> + mutex_lock(&priv->reg_mutex);
> +
> + regmap_read(priv->regmap, AN8855_PMCR_P(port), ®);
[Severity: Low]
If this read fails, reg stays 0 and the later regmap_write() rebuilds
PMCR from zero. Would that clear MAC_MODE, IFG_XMIT, BACKOFF/BACKPR and
the EEE force bits set by mac_config and mac_enable_tx_lpi?
Should the read error be checked before the register is written back?
[ ... ]
> +static int an8855_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
> + phy_interface_t interface,
> + const unsigned long *advertising,
> + bool permit_pause_to_mac)
> +{
[ ... ]
> + /* PLL - SDM */
> + ret = regmap_update_bits(priv->regmap, AN8855_PLL_CTRL_2,
> + AN8855_RG_DA_QP_PLL_SDM_HREN_INTF,
> + FIELD_PREP(AN8855_RG_DA_QP_PLL_SDM_HREN_INTF, 0x0));
[Severity: Medium]
Is AN8855_PLL_CTRL_2 the right register here? an8855.h defines this field
in AN8855_PLL_CTRL_4:
#define AN8855_PLL_CTRL_4 0x1022e410
#define AN8855_RG_DA_QP_PLL_SDM_HREN_INTF GENMASK(4, 3)
In AN8855_PLL_CTRL_2, bits 4:2 are AN8855_RG_DA_QP_PLL_BPA_INTF, and the
earlier "PLL - LPF" step set that field to 0x5. Clearing bits 4:3 here
would change BPA to 0x1 and leave the real SDM_HREN field untouched.
[ ... ]
> + /* PCS Init */
> + if (interface == PHY_INTERFACE_MODE_SGMII &&
> + neg_mode == PHYLINK_PCS_NEG_INBAND_DISABLED) {
> + ret = regmap_clear_bits(priv->regmap, AN8855_QP_DIG_MODE_CTRL_0,
> + AN8855_RG_SGMII_MODE | AN8855_RG_SGMII_AN_EN);
[Severity: Medium]
Can this branch ever run? For SGMII, phylink_pcs_neg_mode() returns
either PHYLINK_PCS_NEG_INBAND_ENABLED or PHYLINK_PCS_NEG_OUTBAND.
INBAND_DISABLED only comes from the Base-X without a PHY case.
For SGMII fixed-link or PHY-managed links, SGMII_MODE and SGMII_AN_EN
would then stay at their reset or previous value. The other branches in
this function test neg_mode != PHYLINK_PCS_NEG_INBAND_ENABLED and set up
forced mode, so the PCS would end up configured inconsistently.
Should this condition also test neg_mode != PHYLINK_PCS_NEG_INBAND_ENABLED?
[ ... ]
> + /* Force Speed with fixed-link or 2500base-x as doesn't support aneg */
> + if (interface == PHY_INTERFACE_MODE_2500BASEX ||
> + neg_mode != PHYLINK_PCS_NEG_INBAND_ENABLED) {
> + if (interface == PHY_INTERFACE_MODE_2500BASEX)
> + val = AN8855_RG_LINK_MODE_P0_SPEED_2500;
> + else
> + val = AN8855_RG_LINK_MODE_P0_SPEED_1000;
[Severity: Medium]
For SGMII without in-band negotiation, this always forces the PCS to
1000.
an8855_phylink_get_caps() advertises MAC_10 | MAC_100 for port 5, and
an8855_phylink_mac_link_up() programs PMCR for 10 or 100. an8855_pcs_ops
has no .pcs_link_up to update the forced rate afterwards.
Would a 10/100 out-of-band SGMII link on port 5 run with the MAC and the
PCS at different rates?
[ ... ]
> diff --git a/drivers/net/dsa/mediatek/mt7530-lib.c b/drivers/net/dsa/mediatek/mt7530-lib.c
> index 098dd45d3ee9f..4325768033325 100644
> --- a/drivers/net/dsa/mediatek/mt7530-lib.c
> +++ b/drivers/net/dsa/mediatek/mt7530-lib.c
> @@ -423,9 +423,11 @@ int mt7530_lib_fdb_cmd(struct mt7530_lib_priv *priv, enum mt7530_fdb_cmd cmd,
> return ret;
> }
>
> - regmap_field_read(priv->fields[MT7530_ATC_INVALID], &val);
> - if (cmd == MT7530_FDB_READ && val)
> - return -EINVAL;
> + if (priv->fields[MT7530_ATC_INVALID]) {
> + regmap_field_read(priv->fields[MT7530_ATC_INVALID], &val);
> + if (cmd == MT7530_FDB_READ && val)
> + return -EINVAL;
> + }
[Severity: Medium]
an8855_fields[] has no MT7530_ATC_INVALID entry. On AN8855 an
MT7530_FDB_READ therefore returns 0 even when the lookup misses.
mt7530_lib_port_mdb_add() and mt7530_lib_port_mdb_del() treat 0 as
"entry exists":
if (!mt7530_lib_fdb_cmd(priv, MT7530_FDB_READ,
ATC_MAT_MACTAB, NULL)) {
regmap_field_read(priv->fields[MT7530_ATRD_PORT_MAP],
&val);
port_mask = val;
}
On a miss, could they merge whatever AN8855_ATRD3 still holds, for
example data left by the last an8855_port_fdb_dump()? That could program
a new group with ports that never joined it, or make mdb_del write a
STATIC_ENT for a group that does not exist.
The READ path also does not select the hit bank through AN8855_ATRDS, as
the fdb dump does.
AN8855 reports hits through AN8855_ATC_HIT. Should this check use that on
AN8855 instead?
The MT7530_VTCR_INVALID check in mt7530_vlan_cmd() was made optional in
the same way.
--
Sashiko AI review · https://netdev-ai.bots.linux.dev/sashiko/#/patchset/20261009161102.38961-1-ansuelsmth%40gmail.com
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2026-10-10 16:19 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2026-10-09 16:10 [PATCH net-next v25 00/10] net: dsa: Add Airoha AN8855 support Christian Marangi
2026-10-09 16:10 ` [PATCH net-next v25 01/10] dt-bindings: net: dsa: Document support for Airoha AN8855 DSA Switch Christian Marangi
2026-10-09 16:10 ` [PATCH net-next v25 02/10] dt-bindings: net: Document support for AN8855 Switch Internal PHY Christian Marangi
2026-10-10 16:19 ` netdev-bot+sashiko
2026-10-09 16:10 ` [PATCH net-next v25 03/10] dt-bindings: mfd: Document support for Airoha AN8855 Switch SoC Christian Marangi
2026-10-10 16:19 ` netdev-bot+sashiko
2026-10-09 16:10 ` [PATCH net-next v25 04/10] mfd: an8855: Add support for Airoha AN8855 Switch Christian Marangi
2026-10-10 16:19 ` netdev-bot+sashiko
2026-10-09 16:10 ` [PATCH net-next v25 05/10] net: phy: Add Airoha AN8855 Internal Switch Gigabit PHY Christian Marangi
2026-10-10 16:19 ` netdev-bot+sashiko
2026-10-09 16:10 ` [PATCH net-next v25 06/10] net: dsa: tag_mtk: add Airoha variant usage of this TAG Christian Marangi
2026-10-10 16:19 ` netdev-bot+sashiko
2026-10-09 16:10 ` [PATCH net-next v25 07/10] MAINTAINERS: add myself as maintainer for Airoha AN8855 Switch Christian Marangi
2026-10-09 16:10 ` [PATCH net-next v25 08/10] net: dsa: move mediatek DSA driver in dedicated directory Christian Marangi
2026-10-09 16:10 ` [PATCH net-next v25 09/10] net: dsa: mt7530: generalize and move common function to lib module Christian Marangi
2026-10-10 16:19 ` netdev-bot+sashiko
2026-10-09 16:10 ` [PATCH net-next v25 10/10] net: dsa: Add Airoha AN8855 5-Port Gigabit DSA Switch driver Christian Marangi
2026-10-10 16:19 ` netdev-bot+sashiko
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