* [PATCH v5 1/2] selftests/resctrl: Implement cl_flush() and sb() for aarch64
2026-10-12 7:47 [PATCH v5 0/2] selftests/resctrl: Fix resctrl selftests issues on aarch64 Richard Cheng
@ 2026-10-12 7:47 ` Richard Cheng
2026-10-12 7:47 ` [PATCH v5 2/2] selftests/resctrl: Recognise aarch64 as a vendor for L3_NONCONT_CAT Richard Cheng
1 sibling, 0 replies; 3+ messages in thread
From: Richard Cheng @ 2026-10-12 7:47 UTC (permalink / raw)
To: tony.luck, reinette.chatre, x86, shuah, fenghuay
Cc: Dave.Martin, james.morse, babu.moger, linux-kernel,
linux-kselftest, kaihengf, kobak, newtonl, kristinc,
Richard Cheng
cl_flush() and sb() compile to empty functions on aarch64, making
mem_flush() a silent no-op and leaving CMT/CAT tests operating on
unflushed state.
Add "dsb sy" for sb(), ARM requires a DSB whose access type covers both
loads and stores.
For cl_flush(), "dc civac" only reaches the Point of Coherency, on
ARM MPAM systems the SLC lies past the PoC and may be a NOP on coherent
platforms. Instead, dirty each cacheline with a store so that
mem_flush's full-buffer sweep evicts lines from the SLC via LRU
pressure.
Signed-off-by: Richard Cheng <icheng@nvidia.com>
---
tools/testing/selftests/resctrl/fill_buf.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/tools/testing/selftests/resctrl/fill_buf.c b/tools/testing/selftests/resctrl/fill_buf.c
index b9fa7968cd6e..eae0262fe265 100644
--- a/tools/testing/selftests/resctrl/fill_buf.c
+++ b/tools/testing/selftests/resctrl/fill_buf.c
@@ -27,6 +27,9 @@ static void sb(void)
#if defined(__i386) || defined(__x86_64)
asm volatile("sfence\n\t"
: : : "memory");
+#elif defined(__aarch64__)
+ asm volatile("dsb sy\n\t"
+ : : : "memory");
#endif
}
@@ -35,6 +38,14 @@ static void cl_flush(void *p)
#if defined(__i386) || defined(__x86_64)
asm volatile("clflush (%0)\n\t"
: : "r"(p) : "memory");
+#elif defined(__aarch64__)
+ /*
+ * Dirty the cache line with a store. As mem_flush() sweeps
+ * the full test buffer (sized larger than the SLC), cache pressure
+ * evicts lines from the SLC via LRU replacement.
+ */
+ asm volatile("strb wzr, [%0]\n\t"
+ : : "r"(p) : "memory");
#endif
}
--
2.43.0
^ permalink raw reply [flat|nested] 3+ messages in thread* [PATCH v5 2/2] selftests/resctrl: Recognise aarch64 as a vendor for L3_NONCONT_CAT
2026-10-12 7:47 [PATCH v5 0/2] selftests/resctrl: Fix resctrl selftests issues on aarch64 Richard Cheng
2026-10-12 7:47 ` [PATCH v5 1/2] selftests/resctrl: Implement cl_flush() and sb() for aarch64 Richard Cheng
@ 2026-10-12 7:47 ` Richard Cheng
1 sibling, 0 replies; 3+ messages in thread
From: Richard Cheng @ 2026-10-12 7:47 UTC (permalink / raw)
To: tony.luck, reinette.chatre, x86, shuah, fenghuay
Cc: Dave.Martin, james.morse, babu.moger, linux-kernel,
linux-kselftest, kaihengf, kobak, newtonl, kristinc,
Richard Cheng, Ilpo Järvinen
aarch64 has no vendor_id in /proc/cpuinfo, so detect_vendor() returns 0
and arch_supports_noncont_cat() falls through to "return false".
L3_NONCONT_CAT therefore spuriously fails on every ARM MPAM platform.
Define ARCH_ARM, short-circuit detect_vendor() to it on aarch64, and
add it to the AMD/Hygon always-supports early-out in
arch_supports_noncont_cat().
aarch64 has many implementers (ARM 0x41, NVIDIA 0x43, etc.), but MPAM
mandates non-contiguous CPBM uniformly, so per-implementer handling is
not needed here.
Reviewed-by: Ilpo Järvinen <ilpo.jarvinen@linux.intel.com>
Reviewed-by: Reinette Chatre <reinette.chatre@intel.com>
Signed-off-by: Richard Cheng <icheng@nvidia.com>
---
tools/testing/selftests/resctrl/cat_test.c | 9 ++++++--
tools/testing/selftests/resctrl/resctrl.h | 1 +
.../testing/selftests/resctrl/resctrl_tests.c | 21 +++++++++++++++++++
3 files changed, 29 insertions(+), 2 deletions(-)
diff --git a/tools/testing/selftests/resctrl/cat_test.c b/tools/testing/selftests/resctrl/cat_test.c
index 0a417267dd74..f4b02b3eedd7 100644
--- a/tools/testing/selftests/resctrl/cat_test.c
+++ b/tools/testing/selftests/resctrl/cat_test.c
@@ -271,8 +271,13 @@ static bool arch_supports_noncont_cat(const struct resctrl_test *test)
{
unsigned int vendor_id = get_vendor();
- /* AMD and Hygon always support non-contiguous CBM. */
- if (vendor_id == ARCH_AMD || vendor_id == ARCH_HYGON)
+ /*
+ * AMD and Hygon always support non-contiguous CBM. ARM/MPAM defines
+ * MPAMCFG_CPBM as a bitmap with no contiguity constraint per ARM
+ * DDI 0598.
+ */
+ if (vendor_id == ARCH_AMD || vendor_id == ARCH_HYGON ||
+ vendor_id == ARCH_ARM)
return true;
#if defined(__i386__) || defined(__x86_64__) /* arch */
diff --git a/tools/testing/selftests/resctrl/resctrl.h b/tools/testing/selftests/resctrl/resctrl.h
index a7556cdae0de..03b4500c1f7f 100644
--- a/tools/testing/selftests/resctrl/resctrl.h
+++ b/tools/testing/selftests/resctrl/resctrl.h
@@ -41,6 +41,7 @@
#define ARCH_INTEL BIT(0)
#define ARCH_AMD BIT(1)
#define ARCH_HYGON BIT(2)
+#define ARCH_ARM BIT(3)
#define END_OF_TESTS 1
diff --git a/tools/testing/selftests/resctrl/resctrl_tests.c b/tools/testing/selftests/resctrl/resctrl_tests.c
index dbcd5eea9fbc..cfece594a8c6 100644
--- a/tools/testing/selftests/resctrl/resctrl_tests.c
+++ b/tools/testing/selftests/resctrl/resctrl_tests.c
@@ -23,6 +23,15 @@ static struct resctrl_test *resctrl_tests[] = {
&l2_noncont_cat_test,
};
+static bool detect_aarch64(void)
+{
+#if defined(__aarch64__)
+ return true;
+#else
+ return false;
+#endif
+}
+
static unsigned int detect_vendor(void)
{
static unsigned int vendor_id;
@@ -34,6 +43,18 @@ static unsigned int detect_vendor(void)
if (initialized)
return vendor_id;
+ if (detect_aarch64()) {
+ /*
+ * aarch64 has no userspace vendor_id in /proc/cpuinfo.
+ * MPAM-capable ARM implementations follow ARM DDI 0598;
+ * treat all aarch64 builds as a single vendor for the
+ * purposes of resctrl selftests.
+ */
+ vendor_id = ARCH_ARM;
+ initialized = true;
+ return vendor_id;
+ }
+
inf = fopen("/proc/cpuinfo", "r");
if (!inf) {
vendor_id = 0;
--
2.43.0
^ permalink raw reply [flat|nested] 3+ messages in thread