From: Loic Poulain <loic.poulain@oss.qualcomm.com>
To: Robert Foss <rfoss@kernel.org>,
Andi Shyti <andi.shyti@kernel.org>,
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Cc: linux-i2c@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-kernel@vger.kernel.org,
Loic Poulain <loic.poulain@oss.qualcomm.com>
Subject: [PATCH v2 0/6] i2c: qcom-cci: Runtime capability detection and improved read/write
Date: Tue, 13 Oct 2026 12:30:24 +0200 [thread overview]
Message-ID: <20261013-cci-imp-v2-0-6873326b44a3@oss.qualcomm.com> (raw)
Improves the Qualcomm CCI I2C driver read/write in different ways:
- Capabilities (queue sizes, max transfer lengths, supported I2C mode)
are currently hardcoded per DT compatible string in a handful of
cci_data instances. Patch 4 replaces the static per-compatible
structs with a single version-sorted capability catalog resolved
at runtime from CCI_HW_VERSION.
- The driver only supported single-command writes, capped at 11 bytes
regardless of how much space the command queue actually has. Patches
2 and 5 factor out the write-command queueing into a reusable helper
and then add burst-write support, chunking longer writes
across the whole queue instead of a single command's payload.
- The FIFO read path hardcoded a fixed 12-byte limit unrelated to the
actual per-revision FIFO size, with a special-cased drain loop.
Patch 6 simplify the FIFO read/drain-loop and derive the read-side
limits from each revision's FIFO size
- Add burst-read support using threshold interrupts, allowing reads of
arbitrary size by draining the FIFO incrementally during the transfer.
Also add overflow and underflow IRQ reporting, as queue/fifo limits are
now derived from the hardware capabilities and exercised more
aggressively.
Support for unbounded write transfers using the threshold IRQ
mechanism is planned as a follow-up and not part of this series.
Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
---
Changes in v2:
- Split the HALT_ACK reset fix out into its own patch (Andi)
- Fix a typo in the "Detect capabilities from CCI_HW_VERSION" commit
message (Andi)
- Use GENMASK()/FIELD_GET() to decode the CCI_HW_VERSION fields (Konrad)
- Derive the number of masters from the DT i2c-bus subnodes instead of
encoding it per compatible string (Konrad)
- Add burst read support via RD_THRESHOLD/RD_PAUSE IRQs
- Link to v1: https://lore.kernel.org/r/20261004-cci-imp-v1-0-227d12cb4829@oss.qualcomm.com
---
Loic Poulain (6):
i2c: qcom-cci: Factor out write command queue programming
i2c: qcom-cci: Handle and report queue overflow/underflow interrupts
i2c: qcom-cci: Detect capabilities from CCI_HW_VERSION at runtime
i2c: qcom-cci: Add burst write support
i2c: qcom-cci: Extend i2c read limits based on CCI revision
i2c: qcom-cci: Add burst read support
drivers/i2c/busses/i2c-qcom-cci.c | 429 +++++++++++++++++++++++++++++---------
1 file changed, 325 insertions(+), 104 deletions(-)
---
base-commit: d6dc536a4c8bb99dd822bc349a9e801be7ea81c9
change-id: 20260929-cci-imp-8ba384309942
Best regards,
--
Loic Poulain <loic.poulain@oss.qualcomm.com>
next reply other threads:[~2026-10-13 10:30 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-13 10:30 Loic Poulain [this message]
2026-10-13 10:30 ` [PATCH v2 1/6] i2c: qcom-cci: Factor out write command queue programming Loic Poulain
2026-10-14 12:53 ` Bryan O'Donoghue
2026-10-14 13:18 ` Loic Poulain
2026-10-13 10:30 ` [PATCH v2 2/6] i2c: qcom-cci: Handle and report queue overflow/underflow interrupts Loic Poulain
2026-10-14 12:55 ` Bryan O'Donoghue
2026-10-13 10:30 ` [PATCH v2 3/6] i2c: qcom-cci: Detect capabilities from CCI_HW_VERSION at runtime Loic Poulain
2026-10-13 10:30 ` [PATCH v2 4/6] i2c: qcom-cci: Add burst write support Loic Poulain
2026-10-14 11:22 ` Konrad Dybcio
2026-10-13 10:30 ` [PATCH v2 5/6] i2c: qcom-cci: Extend i2c read limits based on CCI revision Loic Poulain
2026-10-13 10:30 ` [PATCH v2 6/6] i2c: qcom-cci: Add burst read support Loic Poulain
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