From: Changhuang Liang <changhuang.liang@starfivetech.com>
To: Brian Masney <bmasney@redhat.com>,
Jerome Brunet <jbrunet+clk@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Emil Renner Berthing <kernel@esmil.dk>
Cc: Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org,
Hal Feng <hal.feng@starfivetech.com>,
Changhuang Liang <changhuang.liang@starfivetech.com>
Subject: [PATCH v1 2/6] clk: starfive: jh71x0: Move reset controller registration to jh71x0 common code
Date: Tue, 13 Oct 2026 03:27:03 -0700 [thread overview]
Message-ID: <20261013102707.9207-3-changhuang.liang@starfivetech.com> (raw)
In-Reply-To: <20261013102707.9207-1-changhuang.liang@starfivetech.com>
jh7110_reset_controller_register() is only tied to the JH7110 system
clock driver by its location. Its logic is generic: hand the CRG
register base to the reset driver through an auxiliary device.
Move it to clk-starfive-jh71x0.c as jh71x0_reset_controller_register()
so that the clock drivers of other StarFive SoCs can reuse it, and make
CLK_STARFIVE_JH71X0 select AUXILIARY_BUS accordingly.
While at it, replace the open-coded auxiliary device allocation, init,
add and release handling with devm_auxiliary_device_create(), which
already implements all of it. The register base is now passed to the
reset driver as platform data of the auxiliary device, so struct
jh71x0_reset_adev and the embedded auxiliary device go away.
The auxiliary device ID is dropped: every CRG already uses a distinct
auxiliary device name, so the ID is not needed to keep the device names
unique, and it is always 0 now.
Since the helper now lives in clk-starfive-jh71x0.c, the auxiliary
device names are prefixed with "clk_starfive_jh71x0" instead of
"clk_starfive_jh7110_sys". Update the auxiliary_device_id table of the
JH7110 reset driver in the same patch to keep the tree bisectable.
Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
drivers/clk/starfive/Kconfig | 2 +-
.../clk/starfive/clk-starfive-jh7110-aon.c | 2 +-
.../clk/starfive/clk-starfive-jh7110-isp.c | 2 +-
.../clk/starfive/clk-starfive-jh7110-stg.c | 2 +-
.../clk/starfive/clk-starfive-jh7110-sys.c | 59 +------------------
.../clk/starfive/clk-starfive-jh7110-vout.c | 2 +-
drivers/clk/starfive/clk-starfive-jh7110.h | 4 --
drivers/clk/starfive/clk-starfive-jh71x0.c | 24 ++++++++
drivers/clk/starfive/clk-starfive-jh71x0.h | 2 +
.../reset/starfive/reset-starfive-jh7110.c | 19 +++---
include/soc/starfive/reset-starfive-jh71x0.h | 10 ++--
11 files changed, 45 insertions(+), 83 deletions(-)
diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig
index bd29358ffeec..51716655554f 100644
--- a/drivers/clk/starfive/Kconfig
+++ b/drivers/clk/starfive/Kconfig
@@ -2,6 +2,7 @@
config CLK_STARFIVE_JH71X0
bool
+ select AUXILIARY_BUS
config CLK_STARFIVE_JH7100
bool "StarFive JH7100 clock support"
@@ -32,7 +33,6 @@ config CLK_STARFIVE_JH7110_PLL
config CLK_STARFIVE_JH7110_SYS
bool "StarFive JH7110 system clock support"
depends on ARCH_STARFIVE || COMPILE_TEST
- select AUXILIARY_BUS
select CLK_STARFIVE_JH71X0
select RESET_STARFIVE_JH7110 if RESET_CONTROLLER
select CLK_STARFIVE_JH7110_PLL
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-aon.c b/drivers/clk/starfive/clk-starfive-jh7110-aon.c
index 6f67587f4335..66f1c56a7169 100644
--- a/drivers/clk/starfive/clk-starfive-jh7110-aon.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-aon.c
@@ -121,7 +121,7 @@ static int jh7110_aoncrg_probe(struct platform_device *pdev)
if (ret)
return ret;
- return jh7110_reset_controller_register(priv, "rst-aon", 1);
+ return jh71x0_reset_controller_register(priv, "rst-aon");
}
static const struct of_device_id jh7110_aoncrg_match[] = {
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-isp.c b/drivers/clk/starfive/clk-starfive-jh7110-isp.c
index c02c8b29a123..f8222d3c81ee 100644
--- a/drivers/clk/starfive/clk-starfive-jh7110-isp.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-isp.c
@@ -180,7 +180,7 @@ static int jh7110_ispcrg_probe(struct platform_device *pdev)
if (ret)
goto err_exit;
- ret = jh7110_reset_controller_register(priv, "rst-isp", 3);
+ ret = jh71x0_reset_controller_register(priv, "rst-isp");
if (ret)
goto err_exit;
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-stg.c b/drivers/clk/starfive/clk-starfive-jh7110-stg.c
index 2a5ad0e07d1d..5ae63e18aa4f 100644
--- a/drivers/clk/starfive/clk-starfive-jh7110-stg.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-stg.c
@@ -139,7 +139,7 @@ static int jh7110_stgcrg_probe(struct platform_device *pdev)
if (ret)
return ret;
- return jh7110_reset_controller_register(priv, "rst-stg", 2);
+ return jh71x0_reset_controller_register(priv, "rst-stg");
}
static const struct of_device_id jh7110_stgcrg_match[] = {
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-sys.c b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
index 1d460a03f936..6c5e9c54dfcd 100644
--- a/drivers/clk/starfive/clk-starfive-jh7110-sys.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-sys.c
@@ -6,15 +6,11 @@
* Copyright (C) 2022 StarFive Technology Co., Ltd.
*/
-#include <linux/auxiliary_bus.h>
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/platform_device.h>
-#include <linux/slab.h>
-
-#include <soc/starfive/reset-starfive-jh71x0.h>
#include <dt-bindings/clock/starfive,jh7110-crg.h>
@@ -323,59 +319,6 @@ static const struct jh71x0_clk_data jh7110_sysclk_data[] __initconst = {
JH7110_SYSCLK_OSC),
};
-static void jh7110_reset_unregister_adev(void *_adev)
-{
- struct auxiliary_device *adev = _adev;
-
- auxiliary_device_delete(adev);
- auxiliary_device_uninit(adev);
-}
-
-static void jh7110_reset_adev_release(struct device *dev)
-{
- struct auxiliary_device *adev = to_auxiliary_dev(dev);
- struct jh71x0_reset_adev *rdev = to_jh71x0_reset_adev(adev);
-
- kfree(rdev);
-}
-
-int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv,
- const char *adev_name,
- u32 adev_id)
-{
- struct jh71x0_reset_adev *rdev;
- struct auxiliary_device *adev;
- int ret;
-
- rdev = kzalloc_obj(*rdev);
- if (!rdev)
- return -ENOMEM;
-
- rdev->base = priv->base;
-
- adev = &rdev->adev;
- adev->name = adev_name;
- adev->dev.parent = priv->dev;
- adev->dev.release = jh7110_reset_adev_release;
- adev->id = adev_id;
-
- ret = auxiliary_device_init(adev);
- if (ret) {
- kfree(rdev);
- return ret;
- }
-
- ret = auxiliary_device_add(adev);
- if (ret) {
- auxiliary_device_uninit(adev);
- return ret;
- }
-
- return devm_add_action_or_reset(priv->dev,
- jh7110_reset_unregister_adev, adev);
-}
-EXPORT_SYMBOL_GPL(jh7110_reset_controller_register);
-
/*
* This clock notifier is called when the rate of PLL0 clock is to be changed.
* The cpu_root clock should save the current parent clock and switch its parent
@@ -525,7 +468,7 @@ static int __init jh7110_syscrg_probe(struct platform_device *pdev)
if (ret)
return ret;
- return jh7110_reset_controller_register(priv, "rst-sys", 0);
+ return jh71x0_reset_controller_register(priv, "rst-sys");
}
static const struct of_device_id jh7110_syscrg_match[] = {
diff --git a/drivers/clk/starfive/clk-starfive-jh7110-vout.c b/drivers/clk/starfive/clk-starfive-jh7110-vout.c
index aeba42cd3c44..14e5b8286671 100644
--- a/drivers/clk/starfive/clk-starfive-jh7110-vout.c
+++ b/drivers/clk/starfive/clk-starfive-jh7110-vout.c
@@ -189,7 +189,7 @@ static int jh7110_voutcrg_probe(struct platform_device *pdev)
if (ret)
goto err_exit;
- ret = jh7110_reset_controller_register(priv, "rst-vo", 4);
+ ret = jh71x0_reset_controller_register(priv, "rst-vo");
if (ret)
goto err_exit;
diff --git a/drivers/clk/starfive/clk-starfive-jh7110.h b/drivers/clk/starfive/clk-starfive-jh7110.h
index 0659adae4d76..55374ee24d4d 100644
--- a/drivers/clk/starfive/clk-starfive-jh7110.h
+++ b/drivers/clk/starfive/clk-starfive-jh7110.h
@@ -10,8 +10,4 @@ struct jh7110_top_sysclk {
int top_clks_num;
};
-int jh7110_reset_controller_register(struct jh71x0_clk_priv *priv,
- const char *adev_name,
- u32 adev_id);
-
#endif
diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.c b/drivers/clk/starfive/clk-starfive-jh71x0.c
index 80e9157347eb..37bab563c5e0 100644
--- a/drivers/clk/starfive/clk-starfive-jh71x0.c
+++ b/drivers/clk/starfive/clk-starfive-jh71x0.c
@@ -5,10 +5,12 @@
* Copyright (C) 2021-2022 Emil Renner Berthing <kernel@esmil.dk>
*/
+#include <linux/auxiliary_bus.h>
#include <linux/clk-provider.h>
#include <linux/debugfs.h>
#include <linux/device.h>
#include <linux/io.h>
+#include <soc/starfive/reset-starfive-jh71x0.h>
#include "clk-starfive-jh71x0.h"
@@ -337,3 +339,25 @@ struct clk_hw *jh71x0_clk_get(struct of_phandle_args *clkspec, void *data)
return ERR_PTR(-EINVAL);
}
EXPORT_SYMBOL_GPL(jh71x0_clk_get);
+
+int jh71x0_reset_controller_register(struct jh71x0_clk_priv *priv,
+ const char *adev_name)
+{
+ struct jh71x0_reset_adev *rdev;
+ struct auxiliary_device *adev;
+
+ rdev = devm_kzalloc(priv->dev, sizeof(*rdev), GFP_KERNEL);
+ if (!rdev)
+ return -ENOMEM;
+
+ rdev->base = priv->base;
+
+ adev = devm_auxiliary_device_create(priv->dev, adev_name, rdev);
+ if (!adev)
+ return dev_err_probe(priv->dev, -ENODEV,
+ "failed to create auxiliary device %s\n",
+ adev_name);
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(jh71x0_reset_controller_register);
diff --git a/drivers/clk/starfive/clk-starfive-jh71x0.h b/drivers/clk/starfive/clk-starfive-jh71x0.h
index 9d5dec1d5cd1..322a05157faf 100644
--- a/drivers/clk/starfive/clk-starfive-jh71x0.h
+++ b/drivers/clk/starfive/clk-starfive-jh71x0.h
@@ -123,5 +123,7 @@ struct jh71x0_clk_priv {
const struct clk_ops *starfive_jh71x0_clk_ops(u32 max);
struct clk_hw *jh71x0_clk_get(struct of_phandle_args *clkspec, void *data);
+int jh71x0_reset_controller_register(struct jh71x0_clk_priv *priv,
+ const char *adev_name);
#endif
diff --git a/drivers/reset/starfive/reset-starfive-jh7110.c b/drivers/reset/starfive/reset-starfive-jh7110.c
index 29a43f0f2ad6..30bf7282a919 100644
--- a/drivers/reset/starfive/reset-starfive-jh7110.c
+++ b/drivers/reset/starfive/reset-starfive-jh7110.c
@@ -53,15 +53,14 @@ static int jh7110_reset_probe(struct auxiliary_device *adev,
const struct auxiliary_device_id *id)
{
struct jh7110_reset_info *info = (struct jh7110_reset_info *)(id->driver_data);
- struct jh71x0_reset_adev *rdev = to_jh71x0_reset_adev(adev);
- void __iomem *base = rdev->base;
+ struct jh71x0_reset_adev *rdev = dev_get_platdata(&adev->dev);
- if (!info || !base)
+ if (!info || !rdev || !rdev->base)
return -ENODEV;
return reset_starfive_jh71x0_register(&adev->dev, adev->dev.parent->of_node,
- base + info->assert_offset,
- base + info->status_offset,
+ rdev->base + info->assert_offset,
+ rdev->base + info->status_offset,
NULL,
info->nr_resets,
NULL);
@@ -69,23 +68,23 @@ static int jh7110_reset_probe(struct auxiliary_device *adev,
static const struct auxiliary_device_id jh7110_reset_ids[] = {
{
- .name = "clk_starfive_jh7110_sys.rst-sys",
+ .name = "clk_starfive_jh71x0.rst-sys",
.driver_data = (kernel_ulong_t)&jh7110_sys_info,
},
{
- .name = "clk_starfive_jh7110_sys.rst-aon",
+ .name = "clk_starfive_jh71x0.rst-aon",
.driver_data = (kernel_ulong_t)&jh7110_aon_info,
},
{
- .name = "clk_starfive_jh7110_sys.rst-stg",
+ .name = "clk_starfive_jh71x0.rst-stg",
.driver_data = (kernel_ulong_t)&jh7110_stg_info,
},
{
- .name = "clk_starfive_jh7110_sys.rst-isp",
+ .name = "clk_starfive_jh71x0.rst-isp",
.driver_data = (kernel_ulong_t)&jh7110_isp_info,
},
{
- .name = "clk_starfive_jh7110_sys.rst-vo",
+ .name = "clk_starfive_jh71x0.rst-vo",
.driver_data = (kernel_ulong_t)&jh7110_vout_info,
},
{ /* sentinel */ }
diff --git a/include/soc/starfive/reset-starfive-jh71x0.h b/include/soc/starfive/reset-starfive-jh71x0.h
index 47b486ececc5..26a8532493a0 100644
--- a/include/soc/starfive/reset-starfive-jh71x0.h
+++ b/include/soc/starfive/reset-starfive-jh71x0.h
@@ -2,16 +2,14 @@
#ifndef __SOC_STARFIVE_RESET_JH71X0_H
#define __SOC_STARFIVE_RESET_JH71X0_H
-#include <linux/auxiliary_bus.h>
#include <linux/compiler_types.h>
-#include <linux/container_of.h>
+/*
+ * Platform data handed to the reset auxiliary device created by the
+ * StarFive JH71X0 clock drivers.
+ */
struct jh71x0_reset_adev {
void __iomem *base;
- struct auxiliary_device adev;
};
-#define to_jh71x0_reset_adev(_adev) \
- container_of((_adev), struct jh71x0_reset_adev, adev)
-
#endif
--
2.25.1
next prev parent reply other threads:[~2026-10-13 11:02 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-13 10:27 [PATCH v1 0/6] Add System-0 CRG for JHB100 SoC Changhuang Liang
2026-10-13 10:27 ` [PATCH v1 1/6] clk: starfive: jh7110-sys: Fix memory leak in reset controller register Changhuang Liang
2026-10-13 10:27 ` Changhuang Liang [this message]
2026-10-13 10:27 ` [PATCH v1 3/6] clk: starfive: jh71x0: Add generic CRG probe helper Changhuang Liang
2026-10-13 10:27 ` [PATCH v1 4/6] clk: starfive: Add JHB100 System-0 clock generator driver Changhuang Liang
2026-10-13 10:27 ` [PATCH v1 5/6] reset: starfive: jh71x0: Support discontiguous reset IDs Changhuang Liang
2026-10-13 10:27 ` [PATCH v1 6/6] reset: starfive: Add StarFive JHB100 System-0 reset driver Changhuang Liang
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