[PATCH v1 0/6] Add System-0 CRG for JHB100 SoC

[Changhuang Liang <changhuang.liang@starfivetech.com>]

The JHB100 SoC includes CRG (Clock and Reset Generator) for multiple
subsystems:

The JHB100 SoC is divided into multiple subsystems, and basically
each subsystem includes a CRG(Clock and Reset Generator):
 - sys0crg/sys1crg/sys2crg/
 - per0crg/per1crg/per2crg/per3crg/
 - voutcrg
 - vcecrg
 - gpu0crg/gpu1crg
 - cpucrg
 - usbcrg
 - host0crg/host1crg
 - pcierpcrg
 - husb0crg/husb1crg
 - husbcmncrg
 - husbd0crg/husbd1crg
 - npucrg

[1]: https://lore.kernel.org/all/20261008123338.11081-1-changhuang.liang@starfivetech.com/

This is a split of the previously sent large series [1].
The original series had too many patches, and there was a lot of
similar logic among the patches. To reduce the burden of repeating
similar comments and reviews, the original series of patches was
split up and a new series was established.

This series is based on the clk-next branch.

Changes since previous submission:
- Change RESET_STARFIVE_JHB100 from select to imply.
- Fix the external clock index to JH71X0_EXT_CLK_FLAG, and add
  JH71X0_EXT_CLK(_n) to define the external clock index.
- Remove CLK_IS_CRITICAL usage in sys0.
- Add a static_assert to check at compile time whether the internal
  clock and the external clock overlap in sys0.
- Remove 'power_domain" from 'struct jh71x0_crg_domain_info'.
- Register the reset device using devm_auxiliary_device_create().
- Obtain 'struct jh71x0_reset_adev *' via dev_get_platdata().
- Streamline the reset patch, keeping only the sys0 part.

Changhuang Liang (6):
  clk: starfive: jh7110-sys: Fix memory leak in reset controller
    register
  clk: starfive: jh71x0: Move reset controller registration to jh71x0
    common code
  clk: starfive: jh71x0: Add generic CRG probe helper
  clk: starfive: Add JHB100 System-0 clock generator driver
  reset: starfive: jh71x0: Support discontiguous reset IDs
  reset: starfive: Add StarFive JHB100 System-0 reset driver

 MAINTAINERS                                   |  13 ++
 drivers/clk/starfive/Kconfig                  |  12 +-
 drivers/clk/starfive/Makefile                 |   2 +
 .../clk/starfive/clk-starfive-jh7110-aon.c    |   2 +-
 .../clk/starfive/clk-starfive-jh7110-isp.c    |   2 +-
 .../clk/starfive/clk-starfive-jh7110-stg.c    |   2 +-
 .../clk/starfive/clk-starfive-jh7110-sys.c    |  57 +------
 .../clk/starfive/clk-starfive-jh7110-vout.c   |   2 +-
 drivers/clk/starfive/clk-starfive-jh7110.h    |   4 -
 drivers/clk/starfive/clk-starfive-jh71x0.c    | 120 +++++++++++++-
 drivers/clk/starfive/clk-starfive-jh71x0.h    |  23 +++
 .../clk/starfive/clk-starfive-jhb100-sys0.c   | 148 ++++++++++++++++++
 drivers/reset/starfive/Kconfig                |   9 ++
 drivers/reset/starfive/Makefile               |   1 +
 .../reset/starfive/reset-starfive-jh7110.c    |  19 ++-
 .../reset/starfive/reset-starfive-jh71x0.c    |  99 ++++++++++--
 .../reset/starfive/reset-starfive-jh71x0.h    |  19 +++
 .../reset/starfive/reset-starfive-jhb100.c    |  75 +++++++++
 include/soc/starfive/reset-starfive-jh71x0.h  |  10 +-
 19 files changed, 524 insertions(+), 95 deletions(-)
 create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-sys0.c
 create mode 100644 drivers/reset/starfive/reset-starfive-jhb100.c

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2.25.1