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From: George Neacsu via B4 Relay <devnull+geocausa.gmail.com@kernel.org>
To: Bryan O'Donoghue <bod@kernel.org>, Vinod Koul <vkoul@kernel.org>,
	 David Heidelberg <david@ixit.cz>
Cc: Neil Armstrong <neil.armstrong@linaro.org>,
	 Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>,
	 Loic Poulain <loic.poulain@oss.qualcomm.com>,
	 Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
	 Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>,
	 Vikram Sharma <vikram.sharma@oss.qualcomm.com>,
	 Suresh Vankadara <svankada@qti.qualcomm.com>,
	tjose@qti.qualcomm.com,
	 Mauro Carvalho Chehab <mchehab@kernel.org>,
	 Manivannan Sadhasivam <mani@kernel.org>,
	linux-phy@lists.infradead.org,  linux-media@vger.kernel.org,
	linux-arm-msm@vger.kernel.org,  linux-kernel@vger.kernel.org,
	Bryan O'Donoghue <bryan.odonoghue@linaro.org>,
	 George Neacsu <geocausa@gmail.com>
Subject: [PATCH RFC v2 0/4] phy: qcom-mipi-csi2: C-PHY for X1E80100
Date: Fri, 16 Oct 2026 11:57:47 +0100	[thread overview]
Message-ID: <20261016-x1e-cphy-rfc-v2-0-377654253193@gmail.com> (raw)

Hi Bryan, Vinod, David,

The Snapdragon Surface Pro 11's front camera, an IMX681, is on CSIPHY2
over one MIPI C-PHY trio. linux-next has the CSI2 PHY driver and the CAMSS
PHY API path, and C-PHY is the piece still missing for this camera. This
series adds the PHY side:

1. PHY_MODE_MIPI_CPHY and C-PHY configuration options in the generic PHY
   framework, because CAMSS had no way to ask the PHY for C-PHY;
2. C-PHY configuration helpers, the analogue of
   phy_mipi_dphy_get_default_config_for_hsclk();
3. a rename of the D-PHY init sequence in qcom-mipi-csi2;
4. C-PHY in qcom-mipi-csi2, with the X1E80100 sequence taken from
   Qualcomm's GPL-2.0 downstream header.

v2 is on next-20261015 and applies there on its own. The two CAMSS
patches from v1 (the CSID 680 PHY type select, and C-PHY in
csiphy_stream_on()) build on David's "media: camss: Add support for C-PHY
configuration on Qualcomm platforms" v9, which is not in linux-next yet,
so I have left them out and will send them on top of David's series:
https://lore.kernel.org/all/20260617-qcom-cphy-v9-0-83da8a8e4e44@ixit.cz/

Tested on the Surface Pro 11 (X1E80100) with David's v9 and those two
patches on top, through the upstream stack: CSI2 PHY nodes as in Bryan's
x1e80100 camera DT v7, and CAMSS in PHY API mode, with raw capture over
RDI:
- front IMX681 (Sergey's and Andre's v8 driver plus its C-PHY RFC) on
  CSIPHY2, one C-PHY trio at 2.4 Gsym/s: 3844x2640 at 30 fps, and the
  sensor's colour bars are byte-identical to the pattern captured with an
  out-of-tree driver. The settle count is now computed (28 at a 400 MHz
  timer), and any value from 6 to 48 gives the same frames;
- rear OV13858 on CSIPHY1, four D-PHY lanes: 29.9 fps with the same
  settle count as before the series.
The kernel was 7.1.5, with linux-next's CAMSS and CSI2 PHY built as
modules; the test build needed shims only for API differences.

Open question, from Nihal: the X1E table is Qualcomm's 2.5 Gsps one, and
downstream picks C-PHY settings by symbol rate. I would keep a single
table here and add selection by rate when a second rate is needed,
unless you would rather have the structure now.

Thanks,
George

---
Changes in v2:
- Rebase on next-20261015, PHY patches only; the CAMSS patches follow
  David's series (Bryan)
- phy: rename lanes to trios (Loic), make symbol_rate unsigned long long
  so 32-bit can hold rates above 4.29 Gsym/s, and keep Bryan's R-b for
  that patch
- phy: new patch with the C-PHY helpers (Bryan, Loic)
- qcom-mipi-csi2: new patch renaming init_seq/lane_array_size to
  dphy_init_seq/dphy_lane_array_size (Bryan)
- qcom-mipi-csi2: rename the C-PHY table to lane_regs_v2_1_2_cphy and
  shorten its comment (Konrad)
- qcom-mipi-csi2: no separate bus_type; the endpoint sets phy_mode and
  set_mode() checks against it (Nihal)
- qcom-mipi-csi2: if/else instead of the ternaries, one declaration per
  line, and lanes_enable() split into lane mask and polarity helpers
  instead of the goto (Bryan, Nihal)
- qcom-mipi-csi2: configure() uses the helpers and keeps the link
  frequency, so clocks scale as for D-PHY
- qcom-mipi-csi2: compute the C-PHY settle count instead of the fixed
  table value; blank lines between the per-trio blocks; fsleep() for the
  sequence delays (Nihal)
- qcom-mipi-csi2: drop the video-interfaces.h include, no longer needed
- Link to v1: https://lore.kernel.org/r/20261015-x1e-cphy-rfc-v1-0-1f3fa9af940a@gmail.com

---
George Neacsu (4):
      phy: Add MIPI C-PHY mode and configuration options
      phy: Add MIPI C-PHY configuration helpers
      phy: qcom-mipi-csi2: Rename the D-PHY init sequence
      phy: qcom-mipi-csi2: Add C-PHY support for X1E80100

 drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c | 220 ++++++++++++++++++---
 drivers/phy/qualcomm/phy-qcom-mipi-csi2-core.c     |  53 ++++-
 drivers/phy/qualcomm/phy-qcom-mipi-csi2.h          |   6 +-
 include/linux/phy/phy-mipi-cphy.h                  |  88 +++++++++
 include/linux/phy/phy.h                            |   5 +
 5 files changed, 339 insertions(+), 33 deletions(-)
---
base-commit: b810335a0699d1810683796b0e3ffe8827ddfe6c
change-id: 20261015-x1e-cphy-rfc-201860c8097f

Best regards,
-- 
George Neacsu <geocausa@gmail.com>



             reply	other threads:[~2026-10-16 10:57 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <K9h_NQSPlrzzoVDIqqNPGT6KDZNScVi2mlqy6yNs8VOOS_I4KXf0QLy4k3Cwo2qKhnfL_qUK5wnY4h6wX24L4A==@protonmail.internalid>
2026-10-16 10:57 ` George Neacsu via B4 Relay [this message]
2026-10-16 10:57   ` [PATCH RFC v2 1/4] phy: Add MIPI C-PHY mode and configuration options George Neacsu via B4 Relay
2026-10-16 11:35     ` Nihal Kumar Gupta
2026-10-16 14:16     ` Loic Poulain
2026-10-16 10:57   ` [PATCH RFC v2 2/4] phy: Add MIPI C-PHY configuration helpers George Neacsu via B4 Relay
2026-10-16 11:06     ` Bryan O'Donoghue
2026-10-16 10:57   ` [PATCH RFC v2 3/4] phy: qcom-mipi-csi2: Rename the D-PHY init sequence George Neacsu via B4 Relay
2026-10-16 11:07     ` Bryan O'Donoghue
2026-10-16 10:57   ` [PATCH RFC v2 4/4] phy: qcom-mipi-csi2: Add C-PHY support for X1E80100 George Neacsu via B4 Relay
2026-10-16 11:15     ` Bryan O'Donoghue
2026-10-16 11:35     ` Nihal Kumar Gupta
2026-10-16 12:05       ` Konrad Dybcio
2026-10-16 12:25         ` Nihal Kumar Gupta
2026-10-16 12:24     ` David Heidelberg
2026-10-16 11:02   ` [PATCH RFC v2 0/4] phy: qcom-mipi-csi2: C-PHY " Bryan O'Donoghue
2026-10-16 11:32     ` George Neacsu
2026-10-16 13:27       ` Bryan O'Donoghue
2026-10-16 14:55         ` George Neacsu

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