From: George Neacsu via B4 Relay <devnull+geocausa.gmail.com@kernel.org>
To: Bryan O'Donoghue <bod@kernel.org>, Vinod Koul <vkoul@kernel.org>,
David Heidelberg <david@ixit.cz>
Cc: Neil Armstrong <neil.armstrong@linaro.org>,
Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>,
Loic Poulain <loic.poulain@oss.qualcomm.com>,
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
Nihal Kumar Gupta <nihal.gupta@oss.qualcomm.com>,
Vikram Sharma <vikram.sharma@oss.qualcomm.com>,
Suresh Vankadara <svankada@qti.qualcomm.com>,
tjose@qti.qualcomm.com,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Manivannan Sadhasivam <mani@kernel.org>,
linux-phy@lists.infradead.org, linux-media@vger.kernel.org,
linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
George Neacsu <geocausa@gmail.com>
Subject: [PATCH RFC v2 3/4] phy: qcom-mipi-csi2: Rename the D-PHY init sequence
Date: Fri, 16 Oct 2026 11:57:50 +0100 [thread overview]
Message-ID: <20261016-x1e-cphy-rfc-v2-3-377654253193@gmail.com> (raw)
In-Reply-To: <20261016-x1e-cphy-rfc-v2-0-377654253193@gmail.com>
From: George Neacsu <geocausa@gmail.com>
The init sequence and its size describe the D-PHY mode only. Call them
dphy_init_seq and dphy_lane_array_size, so that a C-PHY sequence can sit
next to them under matching names.
No functional change.
Suggested-by: Bryan O'Donoghue <bod@kernel.org>
Assisted-by: Claude:claude-opus-5-5
Signed-off-by: George Neacsu <geocausa@gmail.com>
---
drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c | 8 ++++----
drivers/phy/qualcomm/phy-qcom-mipi-csi2.h | 4 ++--
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c
index 966d79c98..b2d4ec3e8 100644
--- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c
+++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2-3ph-dphy.c
@@ -246,8 +246,8 @@ phy_qcom_mipi_csi2_gen2_config_lanes(struct mipi_csi2phy_device *csi2phy,
u8 settle_cnt)
{
const struct mipi_csi2phy_device_regs *regs = csi2phy_dev_to_regs(csi2phy);
- const struct mipi_csi2phy_lane_regs *r = regs->init_seq;
- int i, array_size = regs->lane_array_size;
+ const struct mipi_csi2phy_lane_regs *r = regs->dphy_init_seq;
+ int i, array_size = regs->dphy_lane_array_size;
u32 val;
for (i = 0; i < array_size; i++, r++) {
@@ -372,8 +372,8 @@ static struct mipi_csi2_genpd x1e_genpds[] = {
const struct mipi_csi2phy_soc_cfg mipi_csi2_dphy_4nm_x1e = {
.ops = &phy_qcom_mipi_csi2_ops_3ph_1_0,
.reg_info = {
- .init_seq = lane_regs_x1e80100,
- .lane_array_size = ARRAY_SIZE(lane_regs_x1e80100),
+ .dphy_init_seq = lane_regs_x1e80100,
+ .dphy_lane_array_size = ARRAY_SIZE(lane_regs_x1e80100),
.common_regs_offset = 0x1000,
},
.supply_names = (const char **)x1e_supplies,
diff --git a/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h b/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h
index 7e55ae007..0d6031a4d 100644
--- a/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h
+++ b/drivers/phy/qualcomm/phy-qcom-mipi-csi2.h
@@ -48,8 +48,8 @@ struct mipi_csi2phy_lane_regs {
};
struct mipi_csi2phy_device_regs {
- const struct mipi_csi2phy_lane_regs *init_seq;
- const int lane_array_size;
+ const struct mipi_csi2phy_lane_regs *dphy_init_seq;
+ const int dphy_lane_array_size;
const u32 common_regs_offset;
};
--
2.53.0
next prev parent reply other threads:[~2026-10-16 10:57 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <K9h_NQSPlrzzoVDIqqNPGT6KDZNScVi2mlqy6yNs8VOOS_I4KXf0QLy4k3Cwo2qKhnfL_qUK5wnY4h6wX24L4A==@protonmail.internalid>
2026-10-16 10:57 ` [PATCH RFC v2 0/4] phy: qcom-mipi-csi2: C-PHY for X1E80100 George Neacsu via B4 Relay
2026-10-16 10:57 ` [PATCH RFC v2 1/4] phy: Add MIPI C-PHY mode and configuration options George Neacsu via B4 Relay
2026-10-16 11:35 ` Nihal Kumar Gupta
2026-10-16 14:16 ` Loic Poulain
2026-10-16 10:57 ` [PATCH RFC v2 2/4] phy: Add MIPI C-PHY configuration helpers George Neacsu via B4 Relay
2026-10-16 11:06 ` Bryan O'Donoghue
2026-10-16 10:57 ` George Neacsu via B4 Relay [this message]
2026-10-16 11:07 ` [PATCH RFC v2 3/4] phy: qcom-mipi-csi2: Rename the D-PHY init sequence Bryan O'Donoghue
2026-10-16 10:57 ` [PATCH RFC v2 4/4] phy: qcom-mipi-csi2: Add C-PHY support for X1E80100 George Neacsu via B4 Relay
2026-10-16 11:15 ` Bryan O'Donoghue
2026-10-16 11:35 ` Nihal Kumar Gupta
2026-10-16 12:05 ` Konrad Dybcio
2026-10-16 12:25 ` Nihal Kumar Gupta
2026-10-16 12:24 ` David Heidelberg
2026-10-16 11:02 ` [PATCH RFC v2 0/4] phy: qcom-mipi-csi2: C-PHY " Bryan O'Donoghue
2026-10-16 11:32 ` George Neacsu
2026-10-16 13:27 ` Bryan O'Donoghue
2026-10-16 14:55 ` George Neacsu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20261016-x1e-cphy-rfc-v2-3-377654253193@gmail.com \
--to=devnull+geocausa.gmail.com@kernel.org \
--cc=bod@kernel.org \
--cc=david@ixit.cz \
--cc=geocausa@gmail.com \
--cc=konrad.dybcio@oss.qualcomm.com \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-media@vger.kernel.org \
--cc=linux-phy@lists.infradead.org \
--cc=loic.poulain@oss.qualcomm.com \
--cc=mani@kernel.org \
--cc=mchehab@kernel.org \
--cc=neil.armstrong@linaro.org \
--cc=nihal.gupta@oss.qualcomm.com \
--cc=svankada@qti.qualcomm.com \
--cc=tjose@qti.qualcomm.com \
--cc=vikram.sharma@oss.qualcomm.com \
--cc=vkoul@kernel.org \
--cc=vladimir.zapolskiy@linaro.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®