From: Manikanta Maddireddy <mmaddireddy@nvidia.com>
To: <jingoohan1@gmail.com>, <mani@kernel.org>,
<lpieralisi@kernel.org>, <kwilczynski@kernel.org>,
<bhelgaas@google.com>, <linux-pci@vger.kernel.org>
Cc: <robh@kernel.org>, <thierry.reding@kernel.org>,
<jonathanh@nvidia.com>, <vidyas@nvidia.com>, <cassel@kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-tegra@vger.kernel.org>,
<mmaddireddy@nvidia.com>
Subject: [PATCH v2 3/5] PCI: dwc: Drop unused shift macros
Date: Fri, 16 Oct 2026 13:10:24 +0530 [thread overview]
Message-ID: <20261016074026.564302-4-mmaddireddy@nvidia.com> (raw)
In-Reply-To: <20261016074026.564302-1-mmaddireddy@nvidia.com>
Tegra no longer uses the DesignWare field shift macros after
converting the call sites to FIELD_PREP() and FIELD_MODIFY().
Remove the unused shift macros and the old narrow event-selector mask.
Add the complete event-selector field with the standard mask name, and
keep a temporary alias so existing users keep building until they are
converted.
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
---
drivers/pci/controller/dwc/pcie-designware.h | 10 ++--------
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index fa51c81f315c..cb1d1a98e61a 100644
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -85,9 +85,7 @@
/* Common Clock N_FTS */
#define PORT_AFAC_CC_N_FTS(n) FIELD_PREP(PORT_AFAC_CC_N_FTS_MASK, n)
#define PORT_AFAC_ENTER_ASPM BIT(30) /* ASPM L1 Entry Control */
-#define PORT_AFAC_L0S_ELS 24 /* L0s Entrance Latency shift */
#define PORT_AFAC_L0S_ELM GENMASK(26, 24) /* L0s Entrance Latency mask */
-#define PORT_AFAC_L1_ELS 27 /* L1 Entrance Latency shift */
#define PORT_AFAC_L1_ELM GENMASK(29, 27) /* L1 Entrance Latency mask */
#define PORT_LINK_CTRL 0x710 /* Port Link Control Register */
@@ -161,7 +159,6 @@
#define GEN3_CTRL_EQ_PHASE_2_3 BIT(9) /* Equalization Phase 2 and Phase 3 */
#define GEN3_CTRL_RXEQ_RGRDLESS_RXTS BIT(13)
#define GEN3_CTRL_GEN3_EQ_DISABLE BIT(16) /* Equalization Disable */
-#define GEN3_CTRL_RATE_SHADOW_SEL_SHIFT 24 /* Rate Shadow Select shift */
#define GEN3_CTRL_RATE_SHADOW_SEL_MASK GENMASK(25, 24) /* Rate Shadow Select mask */
#define GEN3_EQ_CTRL 0x8A8 /* Gen3 EQ Control */
@@ -279,17 +276,14 @@
#define RAS_DES_EVENT_COUNTER_CONTROL 0x8
#define EVENT_COUNTER_ALL_CLEAR 0x3
#define EVENT_COUNTER_ENABLE_ALL 0x7
-#define EVENT_COUNTER_ENABLE_SHIFT 2
#define EVENT_COUNTER_ENABLE_MASK GENMASK(4, 2)
-#define EVENT_COUNTER_EVENT_SEL_MASK GENMASK(7, 0)
-#define EVENT_COUNTER_EVENT_SEL_SHIFT 16
-#define EVENT_COUNTER_EVENT_SEL_FIELD_MASK GENMASK(23, 16)
+#define EVENT_COUNTER_EVENT_SEL_MASK GENMASK(23, 16)
+#define EVENT_COUNTER_EVENT_SEL_FIELD_MASK EVENT_COUNTER_EVENT_SEL_MASK
#define EVENT_COUNTER_EVENT_Tx_L0S 0x2
#define EVENT_COUNTER_EVENT_Rx_L0S 0x3
#define EVENT_COUNTER_EVENT_L1 0x5
#define EVENT_COUNTER_EVENT_L1_1 0x7
#define EVENT_COUNTER_EVENT_L1_2 0x8
-#define EVENT_COUNTER_GROUP_SEL_SHIFT 24
#define EVENT_COUNTER_GROUP_SEL_MASK GENMASK(27, 24)
#define EVENT_COUNTER_GROUP_5 0x5
--
2.34.1
next prev parent reply other threads:[~2026-10-16 7:41 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-16 7:40 [PATCH v2 0/5] PCI: dwc: Clean up RAS-DES and register field handling Manikanta Maddireddy
2026-10-16 7:40 ` [PATCH v2 1/5] PCI: dwc: Add RAS event counter field masks Manikanta Maddireddy
2026-10-16 7:40 ` [PATCH v2 2/5] PCI: tegra194: Use FIELD_*() for register fields Manikanta Maddireddy
2026-10-16 7:40 ` Manikanta Maddireddy [this message]
2026-10-16 7:40 ` [PATCH v2 4/5] PCI: tegra194: Use standard RAS event selector mask Manikanta Maddireddy
2026-10-16 7:40 ` [PATCH v2 5/5] PCI: dwc: Consolidate RAS-DES event counter fields Manikanta Maddireddy
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