[PATCH] clk: mediatek: mt7981: feed MSDC from emmc_208m, not emmc_400m

[PATCH] clk: mediatek: mt7981: feed MSDC from emmc_208m, not emmc_400m

[Brendon C.]

The MT7981B datasheet specifies the storage interface as "eMMC v4.5 @52
MHz 3.3V", MediaTek's SDK kernel parents CLK_INFRA_MSDC_CK from
emmc_208m, and both the SDK and U-Boot device trees hand the controller
CK_TOP_EMMC_208M as its "source" clock with max-frequency 52 MHz (52 =
208/4). Mainline parents the gate from emmc_400m instead. mtk-sd derives
its divider, the reported actual_clock and its data timeouts from that
source rate, so with a device tree asking for 26 MHz it programs CKDIV=4
and believes the bus runs at 25 MHz while the real bus clock is 13 MHz,
and every clock-derived timeout is sized for a bus twice as fast as the
real one.

On a GL.iNet GL-X3000 (Samsung 8GTF4R eMMC, 8-bit, 3.3 V, HS) this shows
up as msdc_track_cmd_data write data errors (host->error=0x4) on
roughly every 40 MB written, escalating under sustained multi-segment
writes to exhausted retries, "I/O error, dev mmcblk0", lost page writes
and a stopped f2fs overlay. Raw direct reads top out at 11 MB/s where
the vendor kernel reaches 23 MB/s on the same card.

With the correct parent the same device tree yields a real 26 MHz bus,
23 MB/s reads, and four rounds of a 1.4 GB mixed direct/buffered write
stress complete with zero retries and zero I/O errors, matching the
vendor firmware.

Signed-off-by: Brendon C. <bren@bren.win>
---
 drivers/clk/mediatek/clk-mt7981-infracfg.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/clk/mediatek/clk-mt7981-infracfg.c b/drivers/clk/mediatek/clk-mt7981-infracfg.c
index 68a102d..3d98bff 100644
--- a/drivers/clk/mediatek/clk-mt7981-infracfg.c
+++ b/drivers/clk/mediatek/clk-mt7981-infracfg.c
@@ -157,7 +157,7 @@ static const struct mtk_gate infra_clks[] = {
 	GATE_INFRA1(CLK_INFRA_SPI1_HCK_CK, "infra_spi1_hck", "infra_66m_mck",
 		    14),
 	GATE_INFRA1(CLK_INFRA_FRTC_CK, "infra_frtc", "cb_rtc_32k", 15),
-	GATE_INFRA1(CLK_INFRA_MSDC_CK, "infra_msdc", "emmc_400m", 16),
+	GATE_INFRA1(CLK_INFRA_MSDC_CK, "infra_msdc", "emmc_208m", 16),
 	GATE_INFRA1(CLK_INFRA_MSDC_HCK_CK, "infra_msdc_hck", "emmc_208m", 17),
 	GATE_INFRA1(CLK_INFRA_MSDC_133M_CK, "infra_msdc_133m", "sysaxi", 18),
 	GATE_INFRA1(CLK_INFRA_MSDC_66M_CK, "infra_msdc_66m", "sysaxi", 19),

base-commit: 58161ead29e50d70a317ea26b472e0c7508e69da
-- 
2.55.0

Re: [PATCH] clk: mediatek: mt7981: feed MSDC from emmc_208m, not emmc_400m

[Brendon C.]

Tested on a GL.iNet GL-X3000 only. The change is not board-specific:
every MT7981 board with eMMC or SD currently runs its bus at half the
rate its device tree requests and will get the requested rate with this
patch, matching MediaTek's SDK kernel and U-Boot. I do not have a
GL-XE3000, CMCC RAX3000M or Cudy TR3000 to confirm on; the test scripts
are in https://github.com/openwrt/openwrt/issues/25960 for anyone who
does.