[PATCH v2 0/4] arm64: dts: qcom: Set snps,resume-hs-terminations for M31 eUSB2 PHY platforms

[Peter Chen <peter.chen@oss.qualcomm.com>]

The DWC3 controllers on Qualcomm SoCs paired with the M31 eUSB2 PHY
need GUCTL1[10] (RESUME_OPMODE_HS_HOST) set for host-mode USB2 L2/L1
resume, as required by the HPG. Without it, a USB2 HS device cannot be
reset after it is runtime resumed: PORTSC.PR never clears
(PORTSC = 0xe11) and the hub driver fails with
"port_wait_reset: err = -16".

Set snps,resume-hs-terminations, which makes dwc3 core set GUCTL1[10],
on all platforms using the M31 eUSB2 PHY: Glymur, SM8750, Kaanapali
and Hawi.

Changes in v2:
- Apply the same fix to SM8750, Kaanapali and Hawi, which also use the
  M31 eUSB2 PHY (Konrad)
- Collect Reviewed-by tag from Konrad for the Glymur patch

v1: https://lore.kernel.org/all/20261016091336.2715717-1-peter.chen@oss.qualcomm.com/

Peter Chen (4):
  arm64: dts: qcom: glymur: Set snps,resume-hs-terminations for USB
    controllers
  arm64: dts: qcom: sm8750: Set snps,resume-hs-terminations for USB
    controller
  arm64: dts: qcom: kaanapali: Set snps,resume-hs-terminations for USB
    controller
  arm64: dts: qcom: hawi: Set snps,resume-hs-terminations for USB
    controller

 arch/arm64/boot/dts/qcom/glymur.dtsi    | 5 +++++
 arch/arm64/boot/dts/qcom/hawi.dtsi      | 1 +
 arch/arm64/boot/dts/qcom/kaanapali.dtsi | 1 +
 arch/arm64/boot/dts/qcom/sm8750.dtsi    | 1 +
 4 files changed, 8 insertions(+)

-- 
2.43.0