[PATCH v1 0/2] Add PWM support for JHB100 SoC

[PATCH v1 0/2] Add PWM support for JHB100 SoC

[Changhuang Liang]

The StarFive JHB100 PWM is based on the OpenCores PWM v1 controller
but with a modification: the polarity has been changed from inverted
to normal.

This series has been tested on the JHB100 EVB1 board.

This series depends on series:
https://lore.kernel.org/all/20261014110429.52762-1-hal.feng@starfivetech.com/

Changhuang Liang (2):
  dt-bindings: pwm: opencores: Add starfive,jhb100-pwm
  pwm: ocores: Add support for StarFive JHB100 PWM polarity

 .../bindings/pwm/opencores,pwm.yaml           | 12 ++++++----
 drivers/pwm/pwm-ocores.c                      | 24 ++++++++++++++++---
 2 files changed, 28 insertions(+), 8 deletions(-)

--
2.25.1

[PATCH v1 1/2] dt-bindings: pwm: opencores: Add starfive,jhb100-pwm

[Changhuang Liang]

Add a new compatible string "starfive,jhb100-pwm" for the PWM
controller found on the StarFive JHB100 SoC.

The StarFive JHB100 PWM is based on the OpenCores PWM v1 controller
but with a modification: the polarity has been changed from inverted
to normal. The generic opencores,pwm-v1 hardware only supports
inverted polarity, so the JHB100 variant cannot reuse the
"opencores,pwm-v1" fallback and must be described with a standalone
compatible string.

Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
 .../devicetree/bindings/pwm/opencores,pwm.yaml       | 12 +++++++-----
 1 file changed, 7 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml b/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml
index b15468f97b59..a7798310d350 100644
--- a/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml
+++ b/Documentation/devicetree/bindings/pwm/opencores,pwm.yaml
@@ -19,11 +19,13 @@ allOf:
 
 properties:
   compatible:
-    items:
-      - enum:
-          - starfive,jh7100-pwm
-          - starfive,jh7110-pwm
-      - const: opencores,pwm-v1
+    oneOf:
+      - items:
+          - enum:
+              - starfive,jh7100-pwm
+              - starfive,jh7110-pwm
+          - const: opencores,pwm-v1
+      - const: starfive,jhb100-pwm
 
   reg:
     maxItems: 1
-- 
2.25.1

[PATCH v1 2/2] pwm: ocores: Add support for StarFive JHB100 PWM polarity

[Changhuang Liang]

The StarFive JHB100 PWM is based on the OpenCores PWM v1 controller,
but its polarity has been changed from inverted to normal. The generic
opencores,pwm-v1 hardware only supports inverted polarity, so the
driver currently hardcodes PWM_POLARITY_INVERSED and rejects any other
polarity, which makes the JHB100 unusable.

Add a per-device OCPWM_FLAG_POLARITY_NORMAL flag to describe the
polarity capability of the hardware. Devices without this flag keep
the existing inverted-polarity behavior.

Use the flag in ocores_pwm_get_state() to report the polarity actually
supported by the device, and in ocores_pwm_apply() to validate the
requested polarity accordingly.

Finally, add the "starfive,jhb100-pwm" compatible with the normal
polarity flag set.

Signed-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>
---
 drivers/pwm/pwm-ocores.c | 24 +++++++++++++++++++++---
 1 file changed, 21 insertions(+), 3 deletions(-)

diff --git a/drivers/pwm/pwm-ocores.c b/drivers/pwm/pwm-ocores.c
index 4c7e87cb009f..1c69b856bd80 100644
--- a/drivers/pwm/pwm-ocores.c
+++ b/drivers/pwm/pwm-ocores.c
@@ -18,6 +18,7 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
+#include <linux/property.h>
 #include <linux/pwm.h>
 #include <linux/reset.h>
 
@@ -31,12 +32,15 @@
 
 #define OCPWM_NUM_SAVED_REGS	3
 
+#define OCPWM_FLAG_POLARITY_NORMAL	BIT(0)
+
 struct ocores_pwm_device {
 	void __iomem *base;
 	struct clk *clk;
 	unsigned long clk_rate;
 	struct reset_control *rst;
 	u32 saved_regs[OCPWM_NUM_SAVED_REGS];
+	unsigned long flags;
 };
 
 static int ocores_pwm_get_state(struct pwm_chip *chip,
@@ -60,7 +64,11 @@ static int ocores_pwm_get_state(struct pwm_chip *chip,
 	if (state->duty_cycle > state->period)
 		state->duty_cycle = state->period;
 
-	state->polarity = PWM_POLARITY_INVERSED;
+	if (ddata->flags & OCPWM_FLAG_POLARITY_NORMAL)
+		state->polarity = PWM_POLARITY_NORMAL;
+	else
+		state->polarity = PWM_POLARITY_INVERSED;
+
 	state->enabled = (ctrl_data & OCPWM_CTRL_EN) ? true : false;
 
 	pm_runtime_put(pwmchip_parent(chip));
@@ -85,8 +93,13 @@ static int ocores_pwm_apply(struct pwm_chip *chip,
 		return 0;
 	}
 
-	if (state->polarity != PWM_POLARITY_INVERSED)
-		return -EINVAL;
+	if (ddata->flags & OCPWM_FLAG_POLARITY_NORMAL) {
+		if (state->polarity != PWM_POLARITY_NORMAL)
+			return -EINVAL;
+	} else {
+		if (state->polarity != PWM_POLARITY_INVERSED)
+			return -EINVAL;
+	}
 
 	period_data = mul_u64_u32_div(state->period, ddata->clk_rate, NSEC_PER_SEC);
 	if (period_data > U32_MAX)
@@ -218,6 +231,7 @@ static int ocores_pwm_probe(struct platform_device *pdev)
 
 	chip->ops = &ocores_pwm_ops;
 	ddata = pwmchip_get_drvdata(chip);
+	ddata->flags = (unsigned long)device_get_match_data(dev);
 
 	ddata->base = devm_platform_ioremap_resource(pdev, 0);
 	if (IS_ERR(ddata->base))
@@ -279,6 +293,10 @@ static int ocores_pwm_probe(struct platform_device *pdev)
 
 static const struct of_device_id ocores_pwm_of_match[] = {
 	{ .compatible = "opencores,pwm-v1" },
+	{
+		.compatible = "starfive,jhb100-pwm",
+		.data = (void *)OCPWM_FLAG_POLARITY_NORMAL
+	},
 	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, ocores_pwm_of_match);
-- 
2.25.1