[PATCH] media: synopsys: dw-mipi-csi2rx: Fix DPHY testclr reset sequence

[PATCH] media: synopsys: dw-mipi-csi2rx: Fix DPHY testclr reset sequence

[Guoniu Zhou]

The Synopsys DPHY datasheet recommends applying a testclr pulse at
first power-up to reset the PHY configuration to its default values
before any test control register is programmed.

The existing code deasserts testclr first and then asserts it, which
is the reverse of the sequence recommended by the DPHY documentation.

Generate the required TESTCLR pulse by asserting TESTCLR, waiting
for the required pulse width, and then deasserting it.

Fixes: ec40b431f0ab ("media: synopsys: csi2rx: add i.MX93 support")
Signed-off-by: Guoniu Zhou <guoniu.zhou@oss.nxp.com>
---
 drivers/media/platform/synopsys/dw-mipi-csi2rx.c | 13 +++++++++----
 1 file changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/media/platform/synopsys/dw-mipi-csi2rx.c b/drivers/media/platform/synopsys/dw-mipi-csi2rx.c
index b7247d597c9c..b9f7ba25bd3b 100644
--- a/drivers/media/platform/synopsys/dw-mipi-csi2rx.c
+++ b/drivers/media/platform/synopsys/dw-mipi-csi2rx.c
@@ -830,18 +830,23 @@ static void imx93_csi2rx_dphy_assert_reset(struct dw_mipi_csi2rx_device *csi2)
 {
 	u32 val;
 
-	/* Release Synopsys DPHY test codes from reset */
+	/* Put PHY in shutdown mode for configuration */
 	dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_DPHY_RSTZ, 0);
 	dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_PHY_SHUTDOWNZ, 0);
 
+	/*
+	 * Apply testclr pulse to load analog programmability defaults
+	 * and release the test interface for configuration.
+	 */
 	val = dw_mipi_csi2rx_read(csi2, DW_MIPI_CSI2RX_PHY_TST_CTRL0);
-	val &= ~DPHY_TEST_CTRL0_TEST_CLR;
+	val |= DPHY_TEST_CTRL0_TEST_CLR;
 	dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_PHY_TST_CTRL0, val);
 
-	val = dw_mipi_csi2rx_read(csi2, DW_MIPI_CSI2RX_PHY_TST_CTRL0);
 	/* Wait for at least 15ns */
 	ndelay(15);
-	val |= DPHY_TEST_CTRL0_TEST_CLR;
+
+	val = dw_mipi_csi2rx_read(csi2, DW_MIPI_CSI2RX_PHY_TST_CTRL0);
+	val &= ~DPHY_TEST_CTRL0_TEST_CLR;
 	dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_PHY_TST_CTRL0, val);
 }
 

---
base-commit: d7e7bca7169873b46e857c025c10f3336c1258d8
change-id: 20261020-dw-csi2rx-6225697f45bb

Best regards,
-- 
Guoniu Zhou <guoniu.zhou@oss.nxp.com>

Re: [PATCH] media: synopsys: dw-mipi-csi2rx: Fix DPHY testclr reset sequence

[Michael Riesch]

Hi Guoniu,

Thanks for the patch.

On 10/20/26 05:04, Guoniu Zhou wrote:
> The Synopsys DPHY datasheet recommends applying a testclr pulse at
> first power-up to reset the PHY configuration to its default values
> before any test control register is programmed.
> 
> The existing code deasserts testclr first and then asserts it, which
> is the reverse of the sequence recommended by the DPHY documentation.
> 
> Generate the required TESTCLR pulse by asserting TESTCLR, waiting
> for the required pulse width, and then deasserting it.
> 
> Fixes: ec40b431f0ab ("media: synopsys: csi2rx: add i.MX93 support")
> Signed-off-by: Guoniu Zhou <guoniu.zhou@oss.nxp.com>

Acked-by: Michael Riesch <michael.riesch@collabora.com>

Best regards,
Michael

> ---
>  drivers/media/platform/synopsys/dw-mipi-csi2rx.c | 13 +++++++++----
>  1 file changed, 9 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/media/platform/synopsys/dw-mipi-csi2rx.c b/drivers/media/platform/synopsys/dw-mipi-csi2rx.c
> index b7247d597c9c..b9f7ba25bd3b 100644
> --- a/drivers/media/platform/synopsys/dw-mipi-csi2rx.c
> +++ b/drivers/media/platform/synopsys/dw-mipi-csi2rx.c
> @@ -830,18 +830,23 @@ static void imx93_csi2rx_dphy_assert_reset(struct dw_mipi_csi2rx_device *csi2)
>  {
>  	u32 val;
>  
> -	/* Release Synopsys DPHY test codes from reset */
> +	/* Put PHY in shutdown mode for configuration */
>  	dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_DPHY_RSTZ, 0);
>  	dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_PHY_SHUTDOWNZ, 0);
>  
> +	/*
> +	 * Apply testclr pulse to load analog programmability defaults
> +	 * and release the test interface for configuration.
> +	 */
>  	val = dw_mipi_csi2rx_read(csi2, DW_MIPI_CSI2RX_PHY_TST_CTRL0);
> -	val &= ~DPHY_TEST_CTRL0_TEST_CLR;
> +	val |= DPHY_TEST_CTRL0_TEST_CLR;
>  	dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_PHY_TST_CTRL0, val);
>  
> -	val = dw_mipi_csi2rx_read(csi2, DW_MIPI_CSI2RX_PHY_TST_CTRL0);
>  	/* Wait for at least 15ns */
>  	ndelay(15);
> -	val |= DPHY_TEST_CTRL0_TEST_CLR;
> +
> +	val = dw_mipi_csi2rx_read(csi2, DW_MIPI_CSI2RX_PHY_TST_CTRL0);
> +	val &= ~DPHY_TEST_CTRL0_TEST_CLR;
>  	dw_mipi_csi2rx_write(csi2, DW_MIPI_CSI2RX_PHY_TST_CTRL0, val);
>  }
>  
> 
> ---
> base-commit: d7e7bca7169873b46e857c025c10f3336c1258d8
> change-id: 20261020-dw-csi2rx-6225697f45bb
> 
> Best regards,