From: Xi Zhang via B4 Relay <devnull+xz.ca.cn.gmail.com@kernel.org>
To: Rob Clark <robin.clark@oss.qualcomm.com>,
Dmitry Baryshkov <lumag@kernel.org>,
Abhinav Kumar <abhinav.kumar@linux.dev>,
Jessica Zhang <jesszhan0024@gmail.com>,
Sean Paul <sean@poorly.run>,
Marijn Suijten <marijn.suijten@somainline.org>,
David Airlie <airlied@gmail.com>,
Simona Vetter <simona@ffwll.ch>
Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org,
Xi Zhang <xz.ca.cn@gmail.com>
Subject: [PATCH v2 4/6] drm/msm/dpu: Match setup_dither cleanup to the way it was set up
Date: Mon, 26 Oct 2026 17:25:45 -0300 [thread overview]
Message-ID: <20261026-msm-dpu-res-clean-v2-4-3d864435186e@gmail.com> (raw)
In-Reply-To: <20261026-msm-dpu-res-clean-v2-0-3d864435186e@gmail.com>
From: Xi Zhang <xz.ca.cn@gmail.com>
Cleanup hw_pp->ops.setup_dither with NULL for all PINGPONGs,
matching the way it was setup during enable.
Signed-off-by: Xi Zhang <xz.ca.cn@gmail.com>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index d967deb34c77..acea64ebd24e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1320,7 +1320,7 @@ static void _dpu_encoder_virt_enable_helper(struct drm_encoder *drm_enc)
if (dpu_enc->disp_info.intf_type == INTF_DSI &&
!WARN_ON(dpu_enc->num_phys_encs == 0)) {
unsigned bpc = dpu_enc->connector->display_info.bpc;
- for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
+ for (i = 0; i < ARRAY_SIZE(dpu_enc->hw_pp); i++) {
if (!dpu_enc->hw_pp[i])
continue;
_dpu_encoder_setup_dither(dpu_enc->hw_pp[i], bpc);
@@ -2306,8 +2306,10 @@ void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc)
}
}
- if (phys_enc->hw_pp && phys_enc->hw_pp->ops.setup_dither)
- phys_enc->hw_pp->ops.setup_dither(phys_enc->hw_pp, NULL);
+ if (dpu_enc->disp_info.intf_type == INTF_DSI)
+ for (i = 0; i < ARRAY_SIZE(dpu_enc->hw_pp); i++)
+ if (dpu_enc->hw_pp[i] && dpu_enc->hw_pp[i]->ops.setup_dither)
+ dpu_enc->hw_pp[i]->ops.setup_dither(dpu_enc->hw_pp[i], NULL);
if (dpu_enc->cwb_mask)
dpu_encoder_helper_phys_setup_cwb(phys_enc, false);
--
2.55.0
next prev parent reply other threads:[~2026-10-26 20:26 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-26 20:25 [PATCH v2 0/6] drm/msm/dpu: various dpu resource allocation/release mismatch fix Xi Zhang via B4 Relay
2026-10-26 20:25 ` [PATCH v2 1/6] drm/msm/dpu: reset unassigned resource slots to NULL on topology update Xi Zhang via B4 Relay
2026-10-26 23:04 ` Val Packett
2026-10-26 23:55 ` Xi Zhang
2026-10-26 20:25 ` [PATCH v2 2/6] drm/msm/dpu: save LMs in encoder mode_set for cleanup use later Xi Zhang via B4 Relay
2026-10-26 20:25 ` [PATCH v2 3/6] drm/msm/dpu: use common helper cleanup function in cmd mode disable Xi Zhang via B4 Relay
2026-10-26 20:25 ` Xi Zhang via B4 Relay [this message]
2026-10-26 20:25 ` [PATCH v2 5/6] drm/msm: force mode_changed on color_mgmt_changed, not just ctm Xi Zhang via B4 Relay
2026-10-26 23:15 ` Val Packett
2026-10-26 20:25 ` [PATCH v2 6/6] drm/msm/dpu: reset DSC_CMN_MAIN_CNF in dsc disable Xi Zhang via B4 Relay
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