From: Xi Zhang via B4 Relay <devnull+xz.ca.cn.gmail.com@kernel.org>
To: Rob Clark <robin.clark@oss.qualcomm.com>,
Dmitry Baryshkov <lumag@kernel.org>,
Abhinav Kumar <abhinav.kumar@linux.dev>,
Jessica Zhang <jesszhan0024@gmail.com>,
Sean Paul <sean@poorly.run>,
Marijn Suijten <marijn.suijten@somainline.org>,
David Airlie <airlied@gmail.com>,
Simona Vetter <simona@ffwll.ch>
Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org,
Xi Zhang <xz.ca.cn@gmail.com>
Subject: [PATCH v2 3/6] drm/msm/dpu: use common helper cleanup function in cmd mode disable
Date: Mon, 26 Oct 2026 17:25:44 -0300 [thread overview]
Message-ID: <20261026-msm-dpu-res-clean-v2-3-3d864435186e@gmail.com> (raw)
In-Reply-To: <20261026-msm-dpu-res-clean-v2-0-3d864435186e@gmail.com>
From: Xi Zhang <xz.ca.cn@gmail.com>
cmd mode encoder previously did not clean up dsc, or LMs during
disable.
Change to use the common dpu_encoder_helper_phys_cleanup function
for cmd mode disable.
Also do not set intf_cfg.mode_3d during disable:
dpu_encoder_helper_get_3d_blend_mode accesses drm_encoder->crtc->state
directly so intf_cfg.mode_3d weren't set to expected value for disable.
intf_cfg.mode_3d is also ignored by ctl->ops.reset_intf_cfg.
Signed-off-by: Xi Zhang <xz.ca.cn@gmail.com>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 10 +---------
2 files changed, 3 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 81b983ecffbb..d967deb34c77 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -2335,8 +2335,8 @@ void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc)
dpu_enc->dsc = NULL;
}
- intf_cfg.stream_sel = 0; /* Don't care value for video mode */
- intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
+ intf_cfg.stream_sel = 0; /* Ignored by reset_intf_cfg */
+ intf_cfg.mode_3d = 0; /* Ignored by reset_intf_cfg */
intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc);
intf_cfg.cwb = dpu_enc->cwb_mask;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index 45079ee59cf6..111f9dd5e053 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -538,7 +538,6 @@ static void dpu_encoder_phys_cmd_disable(struct dpu_encoder_phys *phys_enc)
{
struct dpu_encoder_phys_cmd *cmd_enc =
to_dpu_encoder_phys_cmd(phys_enc);
- struct dpu_hw_ctl *ctl;
if (phys_enc->enable_state == DPU_ENC_DISABLED) {
DPU_ERROR_CMDENC(cmd_enc, "already disabled\n");
@@ -566,14 +565,7 @@ static void dpu_encoder_phys_cmd_disable(struct dpu_encoder_phys *phys_enc)
phys_enc->hw_pp->ops.disable_tearcheck(phys_enc->hw_pp);
}
- if (phys_enc->hw_intf->ops.bind_pingpong_blk) {
- phys_enc->hw_intf->ops.bind_pingpong_blk(
- phys_enc->hw_intf,
- PINGPONG_NONE);
-
- ctl = phys_enc->hw_ctl;
- ctl->ops.update_pending_flush_intf(ctl, phys_enc->hw_intf->idx);
- }
+ dpu_encoder_helper_phys_cleanup(phys_enc);
phys_enc->enable_state = DPU_ENC_DISABLED;
}
--
2.55.0
next prev parent reply other threads:[~2026-10-26 20:26 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-26 20:25 [PATCH v2 0/6] drm/msm/dpu: various dpu resource allocation/release mismatch fix Xi Zhang via B4 Relay
2026-10-26 20:25 ` [PATCH v2 1/6] drm/msm/dpu: reset unassigned resource slots to NULL on topology update Xi Zhang via B4 Relay
2026-10-26 23:04 ` Val Packett
2026-10-26 23:55 ` Xi Zhang
2026-10-26 20:25 ` [PATCH v2 2/6] drm/msm/dpu: save LMs in encoder mode_set for cleanup use later Xi Zhang via B4 Relay
2026-10-26 20:25 ` Xi Zhang via B4 Relay [this message]
2026-10-26 20:25 ` [PATCH v2 4/6] drm/msm/dpu: Match setup_dither cleanup to the way it was set up Xi Zhang via B4 Relay
2026-10-26 20:25 ` [PATCH v2 5/6] drm/msm: force mode_changed on color_mgmt_changed, not just ctm Xi Zhang via B4 Relay
2026-10-26 23:15 ` Val Packett
2026-10-26 20:25 ` [PATCH v2 6/6] drm/msm/dpu: reset DSC_CMN_MAIN_CNF in dsc disable Xi Zhang via B4 Relay
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20261026-msm-dpu-res-clean-v2-3-3d864435186e@gmail.com \
--to=devnull+xz.ca.cn.gmail.com@kernel.org \
--cc=abhinav.kumar@linux.dev \
--cc=airlied@gmail.com \
--cc=dri-devel@lists.freedesktop.org \
--cc=freedreno@lists.freedesktop.org \
--cc=jesszhan0024@gmail.com \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=lumag@kernel.org \
--cc=marijn.suijten@somainline.org \
--cc=robin.clark@oss.qualcomm.com \
--cc=sean@poorly.run \
--cc=simona@ffwll.ch \
--cc=xz.ca.cn@gmail.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®