* [PATCH v2 2/4] dt-bindings: clocks: qcom,gcc-ipq8074: Allow CMN PLL bias clocks
2026-10-26 12:08 [PATCH v2 1/4] clk: qcom: ipq-cmn-pll: Correct IPQ8074 NSS NoC rate Robert Marko
@ 2026-10-26 12:08 ` Robert Marko
2026-10-26 12:08 ` [PATCH v2 3/4] clk: qcom: gcc-ipq8074: Align CMN PLL inputs with binding Robert Marko
2026-10-26 12:08 ` [PATCH v2 4/4] arm64: dts: qcom: ipq8074: Add CMN PLL Robert Marko
2 siblings, 0 replies; 4+ messages in thread
From: Robert Marko @ 2026-10-26 12:08 UTC (permalink / raw)
To: andersson, abelvesa, sboyd, bmasney+clk, jbrunet+clk, robh,
krzk+dt, conor+dt, konradybcio, taniya.das, ansuelsmth, john,
linux-arm-msm, linux-clk, devicetree, linux-kernel
Cc: Robert Marko
CMN PLL in IPQ8074 provides 2 fixed clocks to the GCC clock controller.
In order to describe this in DTS, allow passing them as the inputs to GCC.
This has a benefit that it avoids doing a global matching by name.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
Changes in v2:
- Keep the existing four-clock form valid with minItems: 4.
- Drop the _clk suffix from the new GCC input names.
- Correct the NSS NoC bias clock description to 461.5 MHz.
.../devicetree/bindings/clock/qcom,gcc-ipq8074.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml
index 00d7df75b3d6..1c9854a5c572 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-ipq8074.yaml
@@ -24,18 +24,24 @@ properties:
const: qcom,gcc-ipq8074
clocks:
+ minItems: 4
items:
- description: board XO clock
- description: sleep clock
- description: Gen3 QMP PCIe PHY PIPE clock
- description: Gen2 QMP PCIe PHY PIPE clock
+ - description: 300 MHz bias clock from CMN PLL
+ - description: 461.5 MHz NSS NoC bias clock from CMN PLL
clock-names:
+ minItems: 4
items:
- const: xo
- const: sleep_clk
- const: pcie0_pipe
- const: pcie1_pipe
+ - const: bias_pll_cc
+ - const: bias_pll_nss_noc
required:
- compatible
--
2.56.0
^ permalink raw reply [flat|nested] 4+ messages in thread* [PATCH v2 3/4] clk: qcom: gcc-ipq8074: Align CMN PLL inputs with binding
2026-10-26 12:08 [PATCH v2 1/4] clk: qcom: ipq-cmn-pll: Correct IPQ8074 NSS NoC rate Robert Marko
2026-10-26 12:08 ` [PATCH v2 2/4] dt-bindings: clocks: qcom,gcc-ipq8074: Allow CMN PLL bias clocks Robert Marko
@ 2026-10-26 12:08 ` Robert Marko
2026-10-26 12:08 ` [PATCH v2 4/4] arm64: dts: qcom: ipq8074: Add CMN PLL Robert Marko
2 siblings, 0 replies; 4+ messages in thread
From: Robert Marko @ 2026-10-26 12:08 UTC (permalink / raw)
To: andersson, abelvesa, sboyd, bmasney+clk, jbrunet+clk, robh,
krzk+dt, conor+dt, konradybcio, taniya.das, ansuelsmth, john,
linux-arm-msm, linux-clk, devicetree, linux-kernel
Cc: Robert Marko
The GCC binding names the CMN PLL inputs bias_pll_cc and
bias_pll_nss_noc. Use those names as fw_name so GCC resolves the
clocks through DT references.
Keep the existing .name values as fallbacks for older device trees
without these optional inputs.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
Changes in v2:
- New patch to align GCC parent lookups with the binding input names.
drivers/clk/qcom/gcc-ipq8074.c | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/qcom/gcc-ipq8074.c b/drivers/clk/qcom/gcc-ipq8074.c
index 1329ea28d703..68c080d49154 100644
--- a/drivers/clk/qcom/gcc-ipq8074.c
+++ b/drivers/clk/qcom/gcc-ipq8074.c
@@ -1132,7 +1132,7 @@ static const struct freq_tbl ftbl_nss_noc_bfdcd_clk_src[] = {
static const struct clk_parent_data gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
{ .fw_name = "xo", .name = "xo" },
- { .fw_name = "bias_pll_nss_noc_clk", .name = "bias_pll_nss_noc_clk" },
+ { .fw_name = "bias_pll_nss_noc", .name = "bias_pll_nss_noc_clk" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll2.clkr.hw },
};
@@ -1357,7 +1357,7 @@ static const struct freq_tbl ftbl_nss_ppe_clk_src[] = {
static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
{ .fw_name = "xo", .name = "xo" },
- { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
+ { .fw_name = "bias_pll_cc", .name = "bias_pll_cc_clk" },
{ .hw = &gpll0.clkr.hw },
{ .hw = &gpll4.clkr.hw },
{ .hw = &nss_crypto_pll.clkr.hw },
@@ -1411,7 +1411,7 @@ static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
{ .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
{ .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
- { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
+ { .fw_name = "bias_pll_cc", .name = "bias_pll_cc_clk" },
};
static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
@@ -1463,7 +1463,7 @@ static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
{ .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
{ .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
- { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
+ { .fw_name = "bias_pll_cc", .name = "bias_pll_cc_clk" },
};
static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
@@ -1704,7 +1704,7 @@ static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bia
{ .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
{ .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
- { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
+ { .fw_name = "bias_pll_cc", .name = "bias_pll_cc_clk" },
};
static const struct parent_map
@@ -1774,7 +1774,7 @@ static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bia
{ .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
{ .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
- { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
+ { .fw_name = "bias_pll_cc", .name = "bias_pll_cc_clk" },
};
static const struct parent_map
@@ -1842,7 +1842,7 @@ static const struct clk_parent_data gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
{ .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
{ .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
- { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
+ { .fw_name = "bias_pll_cc", .name = "bias_pll_cc_clk" },
};
static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
@@ -1907,7 +1907,7 @@ static const struct clk_parent_data gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
{ .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
{ .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
{ .hw = &ubi32_pll.clkr.hw },
- { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
+ { .fw_name = "bias_pll_cc", .name = "bias_pll_cc_clk" },
};
static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {
--
2.56.0
^ permalink raw reply [flat|nested] 4+ messages in thread* [PATCH v2 4/4] arm64: dts: qcom: ipq8074: Add CMN PLL
2026-10-26 12:08 [PATCH v2 1/4] clk: qcom: ipq-cmn-pll: Correct IPQ8074 NSS NoC rate Robert Marko
2026-10-26 12:08 ` [PATCH v2 2/4] dt-bindings: clocks: qcom,gcc-ipq8074: Allow CMN PLL bias clocks Robert Marko
2026-10-26 12:08 ` [PATCH v2 3/4] clk: qcom: gcc-ipq8074: Align CMN PLL inputs with binding Robert Marko
@ 2026-10-26 12:08 ` Robert Marko
2 siblings, 0 replies; 4+ messages in thread
From: Robert Marko @ 2026-10-26 12:08 UTC (permalink / raw)
To: andersson, abelvesa, sboyd, bmasney+clk, jbrunet+clk, robh,
krzk+dt, conor+dt, konradybcio, taniya.das, ansuelsmth, john,
linux-arm-msm, linux-clk, devicetree, linux-kernel
Cc: Robert Marko
Add the CMN PLL node, it will be used to feed the required fixed clocks
to networking subsystem.
CMN PLL provides bias_pll_cc and bias_pll_nss_noc to GCC.
Signed-off-by: Robert Marko <robimarko@gmail.com>
---
Changes in v2:
- Drop the _clk suffix from the GCC CMN PLL input names.
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 27 +++++++++++++++++++++++++--
1 file changed, 25 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 75a5ae30d966..b08efc959379 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -5,6 +5,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-ipq8074.h>
+#include <dt-bindings/clock/qcom,ipq8074-cmn-pll.h>
/ {
#address-cells = <2>;
@@ -15,6 +16,12 @@ / {
interrupt-parent = <&intc>;
clocks {
+ ref_48mhz_clk: ref-48mhz-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <48000000>;
+ #clock-cells = <0>;
+ };
+
sleep_clk: sleep_clk {
compatible = "fixed-clock";
clock-frequency = <32768>;
@@ -257,6 +264,18 @@ mdio: mdio@90000 {
status = "disabled";
};
+ cmn_pll: clock-controller@9b000 {
+ compatible = "qcom,ipq8074-cmn-pll";
+ reg = <0x0009b000 0x800>;
+ clocks = <&ref_48mhz_clk>,
+ <&gcc GCC_CMN_12GPLL_AHB_CLK>,
+ <&gcc GCC_CMN_12GPLL_SYS_CLK>;
+ clock-names = "ref", "ahb", "sys";
+ #clock-cells = <1>;
+ assigned-clocks = <&cmn_pll IPQ8074_CMN_PLL_CLK>;
+ assigned-clock-rates-u64 = /bits/ 64 <12000000000>;
+ };
+
qfprom: efuse@a4000 {
compatible = "qcom,ipq8074-qfprom", "qcom,qfprom";
reg = <0x000a4000 0x2000>;
@@ -369,11 +388,15 @@ gcc: clock-controller@1800000 {
clocks = <&xo>,
<&sleep_clk>,
<&pcie_qmp0>,
- <&pcie_qmp1>;
+ <&pcie_qmp1>,
+ <&cmn_pll IPQ8074_BIAS_PLL_CC_CLK>,
+ <&cmn_pll IPQ8074_BIAS_PLL_NSS_NOC_CLK>;
clock-names = "xo",
"sleep_clk",
"pcie0_pipe",
- "pcie1_pipe";
+ "pcie1_pipe",
+ "bias_pll_cc",
+ "bias_pll_nss_noc";
#clock-cells = <1>;
#power-domain-cells = <1>;
#reset-cells = <1>;
--
2.56.0
^ permalink raw reply [flat|nested] 4+ messages in thread