[PATCH] arm64: dts: st: Update gpio-line-names on STM32MP23xx DHCOS SoM

[PATCH] arm64: dts: st: Update gpio-line-names on STM32MP23xx DHCOS SoM

[Marek Vasut]

Adjust gpio-line-names to match both STM32MP23xx and STM32MP25xx DHCOS
SoM pads respectively in their matching SoM DTs.

Fixes: 6642d6a47901 ("arm64: dts: st: Add support for DH electronics STM32MP23xx/STM32MP25xx DHCOS SoM and Breakout Board and DHSBC")
Signed-off-by: Marek Vasut <marex@nabladev.com>
---
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Christoph Niedermaier <cniedermaier@dh-electronics.com>
Cc: Conor Dooley <conor+dt@kernel.org>
Cc: Krzysztof Kozlowski <krzk+dt@kernel.org>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: kernel@dh-electronics.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-stm32@st-md-mailman.stormreply.com
---
 .../boot/dts/st/stm32mp23xx-dhcos-som.dtsi    | 54 +++++++++++++++++++
 .../boot/dts/st/stm32mp25xx-dhcos-som.dtsi    | 47 ++++++++++++++++
 .../boot/dts/st/stm32mp2xxx-dhcos-som.dtsi    | 45 ----------------
 3 files changed, 101 insertions(+), 45 deletions(-)

diff --git a/arch/arm64/boot/dts/st/stm32mp23xx-dhcos-som.dtsi b/arch/arm64/boot/dts/st/stm32mp23xx-dhcos-som.dtsi
index 5d4624c3200ad..7a95f56bf857f 100644
--- a/arch/arm64/boot/dts/st/stm32mp23xx-dhcos-som.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp23xx-dhcos-som.dtsi
@@ -20,6 +20,60 @@ aliases {
 	};
 };
 
+&gpioa {
+	gpio-line-names = "", "", "", "",
+			  "", "", "", "",
+			  "", "", "", "",
+			  "DHCOS-C", "", "", "";
+};
+
+&gpiod {
+	gpio-line-names = "", "DHCOS-K", "DHCOS-J", "",
+			  "", "", "", "",
+			  "", "", "", "",
+			  "", "", "", "";
+};
+
+&gpiof {
+	gpio-line-names = "", "", "", "",
+			  "", "", "", "",
+			  "", "", "", "DHCOS-E",
+			  "DHCOS-N", "", "", "DHCOS_RAM-CODE_2";
+};
+
+&gpiog {
+	gpio-line-names = "", "", "", "",
+			  "", "", "", "DHCOS-P",
+			  "DHCOS-O", "DHCOS_RAM-CODE_0", "DHCOS_RAM-CODE_1", "",
+			  "", "", "DHCOS-F", "DHCOS_HW-CODE_0";
+};
+
+&gpioh {
+	gpio-line-names = "", "", "DHCOS-I", "",
+			  "", "DHCOS-H", "DHCOS-L", "",
+			  "DHCOS-G", "", "", "",
+			  "", "", "", "";
+};
+
+&gpioi {
+	gpio-line-names = "DHCOS_HW-CODE_1", "DHCOS_HW-CODE_2", "", "",
+			  "", "DHCOS-M", "", "",
+			  "", "", "", "DHCOS-D",
+			  "", "", "", "";
+};
+
+&ioexp {
+	gpio-line-names =
+		"#ETH1_RST_P0_0", "#ETH0_RST_P0_1",
+		"BT_REG_ON_P0_2", "WL_REG_ON_P0_3",
+		"USB1_PWR_EN_P0_4", "USB1_PWR_STAT_P0_5",
+		"USB0_PWR_EN_P0_6", "USB0_PWR_STAT_P0_7",
+		"SDIO0_CD_P1_0", "USB0_SS_SEL_P1_1",
+		"#PCIe_RST_1_2", "#PCIe_Wake_P1_3",
+		"#QSPI_RST_P1_4", "#CSI0_PWDN_P1_5",
+		"#CSI0_RST_P1_6", "#PCIE_CLKREQ_GPIO_Q_P1_7";
+};
+
 &rv3032 {
 	interrupts-extended = <&gpiod 10 IRQ_TYPE_EDGE_FALLING>;
 };
diff --git a/arch/arm64/boot/dts/st/stm32mp25xx-dhcos-som.dtsi b/arch/arm64/boot/dts/st/stm32mp25xx-dhcos-som.dtsi
index 23c25ea086445..3f3bdef05ce4e 100644
--- a/arch/arm64/boot/dts/st/stm32mp25xx-dhcos-som.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp25xx-dhcos-som.dtsi
@@ -20,6 +20,53 @@ aliases {
 	};
 };
 
+&gpioa {
+	gpio-line-names = "", "DHCOS-M", "DHCOS-K", "DHCOS-L",
+			  "DHCOS-E", "DHCOS-J", "", "",
+			  "DHCOS-D", "", "", "",
+			  "", "", "", "";
+};
+
+&gpiof {
+	gpio-line-names = "", "", "", "",
+			  "", "", "", "",
+			  "", "", "", "",
+			  "", "", "", "DHCOS_RAM-CODE_2";
+};
+
+&gpiog {
+	gpio-line-names = "", "", "", "",
+			  "", "", "", "",
+			  "", "DHCOS_RAM-CODE_0", "DHCOS_RAM-CODE_1", "",
+			  "", "", "DHCOS-F", "DHCOS_HW-CODE_0";
+};
+
+&gpioh {
+	gpio-line-names = "", "", "DHCOS-I", "DHCOS-N",
+			  "", "", "DHCOS-O", "DHCOS-H",
+			  "DHCOS-G", "", "", "",
+			  "", "", "", "";
+};
+
+&gpioi {
+	gpio-line-names = "DHCOS_HW-CODE_1", "DHCOS_HW-CODE_2", "", "",
+			  "", "", "", "",
+			  "", "DHCOS-C", "", "",
+			  "", "", "", "";
+};
+
+&ioexp {
+	gpio-line-names =
+		"#ETH1_RST_P0_0", "#ETH0_RST_P0_1",
+		"BT_REG_ON_P0_2", "WL_REG_ON_P0_3",
+		"USB1_PWR_EN_P0_4", "USB1_PWR_STAT_P0_5",
+		"USB0_PWR_EN_P0_6", "USB0_PWR_STAT_P0_7",
+		"SDIO0_CD_P1_0", "USB0_SS_SEL_P1_1",
+		"#PCIe_RST_1_2", "#PCIe_Wake_P1_3",
+		"#QSPI_RST_P1_4", "#CSI0_PWDN_P1_5",
+		"#CSI0_RST_P1_6", "#ETH3_RST_P1_7";
+};
+
 &rv3032 {
 	interrupts-extended = <&gpioi 10 IRQ_TYPE_EDGE_FALLING>;
 };
diff --git a/arch/arm64/boot/dts/st/stm32mp2xxx-dhcos-som.dtsi b/arch/arm64/boot/dts/st/stm32mp2xxx-dhcos-som.dtsi
index bcf63e2ea9898..6febdbfe83649 100644
--- a/arch/arm64/boot/dts/st/stm32mp2xxx-dhcos-som.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp2xxx-dhcos-som.dtsi
@@ -218,41 +218,6 @@ &arm_wdt {
 	status = "okay";
 };
 
-&gpioa {
-	gpio-line-names = "", "DHCOS-M", "DHCOS-K", "DHCOS-L",
-			  "DHCOS-E", "DHCOS-J", "", "",
-			  "DHCOS-D", "", "", "",
-			  "", "", "", "";
-};
-
-&gpiof {
-	gpio-line-names = "", "", "", "",
-			  "", "", "", "",
-			  "", "", "", "",
-			  "", "", "", "DHCOS_RAM-CODE_2";
-};
-
-&gpiog {
-	gpio-line-names = "", "", "", "",
-			  "", "", "", "",
-			  "", "DHCOS_RAM-CODE_0", "DHCOS_RAM-CODE_1", "",
-			  "", "", "DHCOS-F", "DHCOS_HW-CODE_0";
-};
-
-&gpioh {
-	gpio-line-names = "", "", "DHCOS-I", "DHCOS-N",
-			  "", "", "DHCOS-O", "DHCOS-H",
-			  "DHCOS-G", "", "", "",
-			  "", "", "", "";
-};
-
-&gpioi {
-	gpio-line-names = "DHCOS_HW-CODE_1", "DHCOS_HW-CODE_2", "", "",
-			  "", "", "", "",
-			  "", "DHCOS-C", "", "",
-			  "", "", "", "";
-};
-
 &gpioz {
 	gpio-line-names = "", "", "DHCOS-A", "DHCOS-B",
 			  "", "", "", "",
@@ -278,16 +243,6 @@ ioexp: gpio@20 {
 		interrupt-controller;
 		#interrupt-cells = <2>;
 		wakeup-source;
-
-		gpio-line-names =
-			"#ETH1_RST_P0_0", "#ETH0_RST_P0_1",
-			"BT_REG_ON_P0_2", "WL_REG_ON_P0_3",
-			"USB1_PWR_EN_P0_4", "USB1_PWR_STAT_P0_5",
-			"USB0_PWR_EN_P0_6", "USB0_PWR_STAT_P0_7",
-			"SDIO0_CD_P1_0", "USB0_SS_SEL_P1_1",
-			"#PCIe_RST_1_2", "#PCIe_Wake_P1_3",
-			"#QSPI_RST_P1_4", "#CSI0_PWDN_P1_5",
-			"#CSI0_RST_P1_6", "#ETH3_RST_P1_7";
 	};
 
 	eeprom0: eeprom@50 {
-- 
2.53.0