From: Tony Luck <tony.luck@intel.com>
To: Fenghua Yu <fenghuay@nvidia.com>,
Reinette Chatre <reinette.chatre@intel.com>,
Maciej Wieczor-Retman <maciej.wieczor-retman@intel.com>,
Peter Newman <peternewman@google.com>,
James Morse <james.morse@arm.com>,
Babu Moger <babu.moger@amd.com>,
Drew Fustini <dfustini@baylibre.com>,
Dave Martin <Dave.Martin@arm.com>, Chen Yu <yu.c.chen@intel.com>
Cc: x86@kernel.org, linux-kernel@vger.kernel.org,
patches@lists.linux.dev, Tony Luck <tony.luck@intel.com>
Subject: [RFC PATCH 0/8] arm,x86,fs/resctrl: Support asymmetric L2 cache allocation
Date: Mon, 26 Oct 2026 14:57:10 -0700 [thread overview]
Message-ID: <20261026215718.16810-1-tony.luck@intel.com> (raw)
RFC patch series built on top of Reinette's multiple control series[1]
The goal is to support L2 cache allocation on hybrid Intel CPUs such as
Panther Lake[2] where the P-core and E-core CPUs have different number
of supported bits for L2 cache bit mask controls. N.B. it is assumned
that the only point of asymmetry is the cache bit mask length. Other
parameters must be the same (but code doesn't check).
Overall approach is to add the per-L2 cache bitmask length to the domain
and use that everywhere instead of using a single value from the control.
Patch 1 changes the format of the per-control "max" file and should be
merged back into Reinette's multi-control series so this file can have
a consistent format from first upstream introduction.
Patches 2-5 are enumeration and preperation.
Patch 6 introduces, initializes, and uses the per-domain cache bit mask
length field (arm/MPAM change needs careful scrutiny).
Patch 7 enables asymmetric L2 for x86 CPUs that enumerate it. N.B. it
renammes the resource from "L2" to "L2A" to avoid user interface issues
with tools that expect L2 cache allocation to be symmetric.
Patch 8 suppresses creation of the "cbm_mask" file for asymmetric caches.
[1] git://git.kernel.org/pub/scm/linux/kernel/git/reinette/linux.git resctrl/controls_rfc_v2.4
[2] Typical desktop/laptop CPUs do not enumerate RDT L2 cache allocation.
This feature is found on SKUs intended for industrial applications.
Tony Luck (8):
fs/resctrl: Change UI of "max" file (merge back into earlier patches)
x86/resctrl: Add L2CAT quirk for Intel Panther Lake
x86/cpuid: Add and use defines for Intel RDT enumeration leaves
x86/resctrl: Add X86_FEATURE bits for asymmetric L2
x86/resctrl: Refactor rdt_get_cache_alloc_cfg()
arm,x86,fs/resctrl: Prepare for asymmetric caches
x86/resctrl: Check for and enable asymmetric L2 cache allocation
fs/resctrl: Suppress creation of cbm_mask info file on asymmetric
systems
Documentation/filesystems/resctrl.rst | 9 +++-
include/linux/resctrl.h | 12 ++++-
arch/x86/include/asm/cpufeatures.h | 3 ++
arch/x86/include/asm/cpuid/types.h | 4 ++
fs/resctrl/internal.h | 2 +
arch/x86/kernel/cpu/cpuid-deps.c | 2 +
arch/x86/kernel/cpu/resctrl/core.c | 64 +++++++++++++++++++++-----
arch/x86/kernel/cpu/resctrl/rdtgroup.c | 2 +-
arch/x86/kernel/cpu/scattered.c | 3 ++
drivers/resctrl/mpam_resctrl.c | 19 +++++---
fs/resctrl/ctrlmondata.c | 9 ++--
fs/resctrl/pseudo_lock.c | 2 +-
fs/resctrl/rdtgroup.c | 61 +++++++++++++++---------
13 files changed, 145 insertions(+), 47 deletions(-)
--
2.56.0
next reply other threads:[~2026-10-26 21:57 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-26 21:57 Tony Luck [this message]
2026-10-26 21:57 ` [RFC PATCH 1/8] fs/resctrl: Change UI of "max" file (merge back into earlier patches) Tony Luck
2026-10-26 21:57 ` [RFC PATCH 2/8] x86/resctrl: Add L2CAT quirk for Intel Panther Lake Tony Luck
2026-10-26 21:57 ` [RFC PATCH 3/8] x86/cpuid: Add and use defines for Intel RDT enumeration leaves Tony Luck
2026-10-26 21:57 ` [RFC PATCH 4/8] x86/resctrl: Add X86_FEATURE bits for asymmetric L2 Tony Luck
2026-10-26 21:57 ` [RFC PATCH 5/8] x86/resctrl: Refactor rdt_get_cache_alloc_cfg() Tony Luck
2026-10-26 21:57 ` [RFC PATCH 6/8] arm,x86,fs/resctrl: Prepare for asymmetric caches Tony Luck
2026-10-26 21:57 ` [RFC PATCH 7/8] x86/resctrl: Check for and enable asymmetric L2 cache allocation Tony Luck
2026-10-26 21:57 ` [RFC PATCH 8/8] fs/resctrl: Suppress creation of cbm_mask info file on asymmetric systems Tony Luck
2026-10-26 22:30 ` [RFC PATCH 0/8] arm,x86,fs/resctrl: Support asymmetric L2 cache allocation Reinette Chatre
2026-10-27 17:41 ` Luck, Tony
2026-10-27 18:30 ` Reinette Chatre
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20261026215718.16810-1-tony.luck@intel.com \
--to=tony.luck@intel.com \
--cc=Dave.Martin@arm.com \
--cc=babu.moger@amd.com \
--cc=dfustini@baylibre.com \
--cc=fenghuay@nvidia.com \
--cc=james.morse@arm.com \
--cc=linux-kernel@vger.kernel.org \
--cc=maciej.wieczor-retman@intel.com \
--cc=patches@lists.linux.dev \
--cc=peternewman@google.com \
--cc=reinette.chatre@intel.com \
--cc=x86@kernel.org \
--cc=yu.c.chen@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®