Re: [RFC PATCH 0/8] arm,x86,fs/resctrl: Support asymmetric L2 cache allocation

[Reinette Chatre <reinette.chatre@intel.com>]

Hi Tony,

On 10/26/26 2:57 PM, Tony Luck wrote:
> RFC patch series built on top of Reinette's multiple control series[1]
> 
> The goal is to support L2 cache allocation on hybrid Intel CPUs such as
> Panther Lake[2] where the P-core and E-core CPUs have different number
> of supported bits for L2 cache bit mask controls. N.B. it is assumned
> that the only point of asymmetry is the cache bit mask length. Other
> parameters must be the same (but code doesn't check).
> 
> Overall approach is to add the per-L2 cache bitmask length to the domain
> and use that everywhere instead of using a single value from the control.
> 
> Patch 1 changes the format of the per-control "max" file and should be
> merged back into Reinette's multi-control series so this file can have
> a consistent format from first upstream introduction.
> 
> Patches 2-5 are enumeration and preperation.
> 
> Patch 6 introduces, initializes, and uses the per-domain cache bit mask
> length field (arm/MPAM change needs careful scrutiny).
> 
> Patch 7 enables asymmetric L2 for x86 CPUs that enumerate it. N.B. it
> renammes the resource from "L2" to "L2A" to avoid user interface issues
> with tools that expect L2 cache allocation to be symmetric.

I did a quick scan and it seems to ignore the the distinction between a resource
and control as highlighted the previous time you brought up this work. Specifically,
please see:

	https://lore.kernel.org/lkml/eaeb4259-46d6-4656-8354-669ad32654b5@intel.com/

Also, why does patch #1 drop the 0x prefix from new control interface when displaying hex
values to user space? This is a significant change for which patch #1 does not provide
a motivation.

Reinette