From: Krzysztof Kozlowski <krzk@kernel.org>
To: Cunhao Lu <1579567540@qq.com>
Cc: Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney+clk@redhat.com>,
Jerome Brunet <jbrunet+clk@baylibre.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Heiko Stuebner <heiko@sntech.de>,
Philipp Zabel <p.zabel@pengutronix.de>,
Elaine Zhang <zhangqing@rock-chips.com>,
Richard Cochran <richardcochran@gmail.com>,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org,
linux-kernel@vger.kernel.org, netdev@vger.kernel.org
Subject: Re: [PATCH v4 1/4] dt-bindings: clock: rockchip: Add RK3572 CRU
Date: Tue, 27 Oct 2026 19:31:39 +0100 [thread overview]
Message-ID: <20261027-amiable-dazzling-kelpie-cef3ab@quoll> (raw)
In-Reply-To: <20261027-add-board-ok3572-c-clk-v4-1-d4152b4fedaa@qq.com>
On Tue, Oct 27, 2026 at 06:04:28PM +0800, Cunhao Lu wrote:
> From: Elaine Zhang <zhangqing@rock-chips.com>
>
> The RK3572 CRU uses the PMU0 GRF for the AUPLL reference mux.
> Describe the controller and define its clock and reset IDs.
>
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
>
> - Documented the xin24m input.
> - Made the PMU0 GRF phandle required.
> - Updated the example.
> - Closed the reset ID gap while preserving each named reset's register
> mapping.
> - Removed CLK_NR_CLKS from the clock binding.
>
> Signed-off-by: Cunhao Lu <1579567540@qq.com>
Same comments as in other places. I probably responded to older version.
Best regards,
Krzysztof
next prev parent reply other threads:[~2026-10-27 18:31 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-27 10:04 [PATCH v4 0/4] clk: rockchip: Add RK3572 clock and reset support Cunhao Lu via B4 Relay
2026-10-27 10:04 ` [PATCH v4 1/4] dt-bindings: clock: rockchip: Add RK3572 CRU Cunhao Lu via B4 Relay
2026-10-27 18:31 ` Krzysztof Kozlowski [this message]
2026-10-27 10:04 ` [PATCH v4 2/4] clk: rockchip: Add internal support for 24-bit fractional dividers Cunhao Lu via B4 Relay
2026-10-27 10:11 ` Shawn Lin
2026-10-27 10:41 ` Cunhao Lu
2026-10-27 10:56 ` Heiko Stübner
2026-10-27 11:31 ` Cunhao Lu
2026-10-27 10:04 ` [PATCH v4 3/4] clk: rockchip: Add composite clock macro with mux table Cunhao Lu via B4 Relay
2026-10-27 10:04 ` [PATCH v4 4/4] clk: rockchip: Add RK3572 clock and reset support Cunhao Lu via B4 Relay
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