From: Taniya Das <taniya.das@oss.qualcomm.com>
To: Bjorn Andersson <andersson@kernel.org>,
Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney+clk@redhat.com>,
Jerome Brunet <jbrunet+clk@baylibre.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Shawn Guo <shengchao.guo@oss.qualcomm.com>,
Abel Vesa <abelvesa@kernel.org>,
Satya Priya Kakitapalli <quic_skakitap@quicinc.com>,
Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Cc: Ajit Pandey <ajit.pandey@oss.qualcomm.com>,
Imran Shaik <imran.shaik@oss.qualcomm.com>,
Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
Taniya Das <taniya.das@oss.qualcomm.com>,
stable@vger.kernel.org,
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>,
Abel Vesa <abel.vesa@oss.qualcomm.com>,
Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Subject: [PATCH v3 0/4] clk: qcom: Add Nord DPRX clock controller support
Date: Tue, 27 Oct 2026 23:38:25 +0530 [thread overview]
Message-ID: <20261027-nords_dprx-v3-0-5d98b2c6c263@oss.qualcomm.com> (raw)
Add support for the DisplayPort Receiver (DPRX) clock controllers found
on Qualcomm Nord devices. There are two identical DPRX clock controller
instances (DPRX0 and DPRX1), each providing clocks for the DPRX core,
audio, AHB and video memory paths, along with their core PLLs.
The DPRX PLLs are ZONDA_OLE instances whose PLL_ALPHA_VAL register has
been widened to 28 bits to carry the fractional word at a finer
resolution. The alpha-PLL core must support that width for the DPRX PLLs
to lock to and report the correct rate.
The series is organized as follows:
- Patch 1 fixes Zonda PLL L-value rounding.
- Patch 2 adds alpha-PLL support for a 28-bit ALPHA_VAL width.
- Patch 3 documents the Nord DPRX clock controller DT bindings.
- Patch 4 adds the two DPRX clock controller drivers.
Changes in v3:
- Add a separate fix for Zonda PLL L-value rounding.
- Add runtime PM support and use masked divider register updates.
- Use the preferred items form for the power-domains binding property.
- Link to v2: https://lore.kernel.org/r/20260924-nords_dprx-v2-0-fa4364e087ef@oss.qualcomm.com
Changes in v2:
- Address review comments: remove unused definitions and includes, rewrap the
alpha-width ternary, and clarify that DPRXCC provides clocks and resets.
- Add RB-by tag [Abel]
- Link to v1: https://lore.kernel.org/r/20260907-nords_dprx-v1-0-d472af3f01b1@oss.qualcomm.com
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
---
Taniya Das (4):
clk: qcom: clk-alpha-pll: fix Zonda L value rounding
clk: qcom: clk-alpha-pll: support a 28-bit ALPHA_VAL width
dt-bindings: clock: qcom: document the Nord DPRX Clock Controller
clk: qcom: dprxcc: Add Nord DPRX clock controller support
.../bindings/clock/qcom,nord-dprxcc.yaml | 67 ++++
drivers/clk/qcom/Kconfig | 11 +
drivers/clk/qcom/Makefile | 1 +
drivers/clk/qcom/clk-alpha-pll.c | 10 +-
drivers/clk/qcom/clk-alpha-pll.h | 3 +
drivers/clk/qcom/dprxcc0-nord.c | 441 +++++++++++++++++++++
drivers/clk/qcom/dprxcc1-nord.c | 440 ++++++++++++++++++++
include/dt-bindings/clock/qcom,nord-dprxcc.h | 27 ++
8 files changed, 995 insertions(+), 5 deletions(-)
---
base-commit: f1ac44c32cba88ad65dcecd4a279661d14e93651
change-id: 20260903-nords_dprx-4903d7acc841
Best regards,
--
Taniya Das <taniya.das@oss.qualcomm.com>
next reply other threads:[~2026-10-27 18:08 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-27 18:08 Taniya Das [this message]
2026-10-27 18:08 ` [PATCH v3 1/4] clk: qcom: clk-alpha-pll: fix Zonda L value rounding Taniya Das
2026-10-28 13:01 ` Konrad Dybcio
2026-10-27 18:08 ` [PATCH v3 2/4] clk: qcom: clk-alpha-pll: support a 28-bit ALPHA_VAL width Taniya Das
2026-10-27 18:08 ` [PATCH v3 3/4] dt-bindings: clock: qcom: document the Nord DPRX Clock Controller Taniya Das
2026-10-27 18:08 ` [PATCH v3 4/4] clk: qcom: dprxcc: Add Nord DPRX clock controller support Taniya Das
2026-10-28 13:05 ` Konrad Dybcio
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