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From: Krzysztof Kozlowski <krzk@kernel.org>
To: Diogo Ivo <diogo.ivo.sx@renesas.com>
Cc: Wolfram Sang <wsa+renesas@sang-engineering.com>,
	 Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>,
	Alexandre Belloni <alexandre.belloni@bootlin.com>,
	 Frank Li <Frank.Li@nxp.com>, Rob Herring <robh@kernel.org>,
	 Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	 Geert Uytterhoeven <geert+renesas@glider.be>,
	Magnus Damm <magnus.damm@gmail.com>,
	 Stephen Boyd <sboyd@kernel.org>,
	Brian Masney <bmasney+clk@redhat.com>,
	 Jerome Brunet <jbrunet+clk@baylibre.com>,
	Linus Walleij <linusw@kernel.org>,
	linux-i3c@lists.infradead.org,  linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org,
	 linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org
Subject: Re: [PATCH v2 3/7] dt-bindings: i3c: renesas,i3c: Add RZ/G3L support
Date: Wed, 28 Oct 2026 12:30:30 +0100	[thread overview]
Message-ID: <20261028-ecstatic-fluffy-lizard-9a5da6@quoll> (raw)
In-Reply-To: <20261026-divo-ssgrlpcsrc-2966-i3c-v2-3-2e76b87209bb@renesas.com>

On Mon, Oct 26, 2026 at 11:35:46AM +0000, Diogo Ivo wrote:
> Add device tree binding support for I3C on the Renesas RZ/G3L
> (R9A08G046) SoC.
> 
> The I3C IP on the RZ/G3L is a subset of the one on the RZ/G3S, as the
> RZ/G3L has no HDR Exit Pattern detection interrupt. The resources are
> consumed by name (the tclk clock, the presetn and tresetn resets and
> seven of the named interrupts), all of which the RZ/G3L provides, so
> software can match and bind a RZ/G3L node through the RZ/G3S
> compatible. Add the RZ/G3L-specific "renesas,r9a08g046-i3c" compatible
> with a fallback to the RZ/G3S "renesas,r9a08g045-i3c" compatible.
> 
> The RZ/G3L is not compatible with the RZ/G3E, which has no input analog
> filters and supports high-speed mode (up to 3.4 Mbps).
> 
> Split the clock and interrupt constraints into separate if/else blocks
> so that RZ/G3L nodes inherit the 2-clock limit from the RZ/G3S fallback
> while being constrained to 16 interrupts alongside the RZ/G3E.
> 
> Signed-off-by: Diogo Ivo <diogo.ivo.sx@renesas.com>
> ---
> Changes in v2:
> - Describe the RZ/G3L by a SoC-specific compatible with a fallback to
>   the renesas,r9a08g045-i3c compatible of the RZ/G3S, instead of a
>   plain compatible, and drop the corresponding driver patch.
> - Split the clock and interrupt constraints into separate if/else
>   blocks to handle the RZ/G3S fallback on RZ/G3L nodes.
> - Explain in the commit message why the RZ/G3L is not made compatible
>   with the RZ/G3E.
> ---
>  .../devicetree/bindings/i3c/renesas,i3c.yaml       | 27 ++++++++++++++--------
>  1 file changed, 18 insertions(+), 9 deletions(-)

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof


  reply	other threads:[~2026-10-28 11:30 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-26 11:35 [PATCH v2 0/7] i3c: renesas: " Diogo Ivo
2026-10-26 11:35 ` [PATCH v2 1/7] i3c: renesas: Fix zero I2C SCL rate on pure I3C buses Diogo Ivo
2026-10-26 20:24   ` Frank Li
2026-10-26 11:35 ` [PATCH v2 2/7] i3c: renesas: Drop comma after OF match table sentinel Diogo Ivo
2026-10-26 11:35 ` [PATCH v2 3/7] dt-bindings: i3c: renesas,i3c: Add RZ/G3L support Diogo Ivo
2026-10-28 11:30   ` Krzysztof Kozlowski [this message]
2026-10-26 11:35 ` [PATCH v2 4/7] clk: renesas: r9a08g046: Add I3C clocks and resets Diogo Ivo
2026-10-26 11:35 ` [PATCH v2 5/7] pinctrl: renesas: rzg2l: Split SoC-specific masks in struct rzg2l_register_masks Diogo Ivo
2026-10-26 11:35 ` [PATCH v2 6/7] pinctrl: renesas: rzg2l: Add RZ/G3L support for selecting I3C power source Diogo Ivo
2026-10-26 11:35 ` [PATCH v2 7/7] arm64: dts: renesas: r9a08g046: Add I3C support Diogo Ivo

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