[PATCH v2 0/7] i3c: renesas: Add RZ/G3L support

[PATCH v2 0/7] i3c: renesas: Add RZ/G3L support

[Diogo Ivo]

Hi,

this series adds I3C support for the Renesas RZ/G3L (R9A08G046) SoC and
enables the controller on the RZ/G3L SMARC EVK.

It starts with a driver fix, which is independently applicable and
marked for stable: on a pure I3C bus, the I3C core leaves the I2C SCL
rate at zero, and the driver used to derive a zero-width open-drain SCL
from it. It now falls back to the 1 MHz FM+ limit instead. There is also
a small cosmetic patch removing a comma after the sentinel in the
compatible table, for consistency.

The rest of the series adds the DT bindings, the CPG clocks and resets,
and the SoC and board device tree support for RZ/G3L. The driver only
consumes resources that are common to the RZ/G3L and the RZ/G3S
(R9A08G045) (the tclk clock, the presetn and tresetn resets and seven
named interrupts), so no driver changes are needed: the RZ/G3L is
described by the SoC-specific renesas,r9a08g046-i3c compatible with a
fallback to the renesas,r9a08g045-i3c compatible of the RZ/G3S, which
the driver already matches.

The board enablement is guarded by the SW_I3C_EN switch, as the pins
are shared with RIIC3 and the audio codec behind it.

The I3C I/O voltage can be set to 1.2V or 1.8V on the board through
the SYS.3 (I3C_IOVS) switch. As software needs to tell the pin
controller which voltage is in effect, the series also adds pin
controller support for the I3C power source on RZ/G3L together with the
matching board device tree configuration.

Signed-off-by: Diogo Ivo <diogo.ivo.sx@renesas.com>
---
Changes in v2:
- Drop the "i3c: renesas: Add RZ/G3L support" patch and express the
  compatibility of the RZ/G3L with a fallback to the
  renesas,r9a08g045-i3c compatible in the bindings and in the DTS, as
  suggested by Krzysztof.
- Split the clock and interrupt constraints in the bindings into
  separate if/else blocks to handle the RZ/G3S fallback on RZ/G3L
  nodes.
- Sort the &i3c and i3c_pins nodes alphabetically in
  r9a08g046l48-smarc.dts.
- Link to v1: https://patch.msgid.link/20261020-divo-ssgrlpcsrc-2966-i3c-v1-0-30a47f25e515@renesas.com

---
Diogo Ivo (7):
      i3c: renesas: Fix zero I2C SCL rate on pure I3C buses
      i3c: renesas: Drop comma after OF match table sentinel
      dt-bindings: i3c: renesas,i3c: Add RZ/G3L support
      clk: renesas: r9a08g046: Add I3C clocks and resets
      pinctrl: renesas: rzg2l: Split SoC-specific masks in struct rzg2l_register_masks
      pinctrl: renesas: rzg2l: Add RZ/G3L support for selecting I3C power source
      arm64: dts: renesas: r9a08g046: Add I3C support

 .../devicetree/bindings/i3c/renesas,i3c.yaml       | 27 +++++++++++------
 arch/arm64/boot/dts/renesas/r9a08g046.dtsi         | 35 ++++++++++++++++++++++
 arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts | 21 +++++++++++++
 arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi   |  4 +++
 drivers/clk/renesas/r9a08g046-cpg.c                |  7 +++++
 drivers/i3c/master/renesas-i3c.c                   | 12 ++++++--
 drivers/pinctrl/renesas/pinctrl-rzg2l.c            | 25 ++++++++--------
 7 files changed, 107 insertions(+), 24 deletions(-)
---
base-commit: 5d13f5297a1bd1fdff5fab7efcdbc9bfe407e457
change-id: 20261020-divo-ssgrlpcsrc-2966-i3c-bca85b48f943

Best regards,
--  
Diogo Ivo <diogo.ivo.sx@renesas.com>

[PATCH v2 1/7] i3c: renesas: Fix zero I2C SCL rate on pure I3C buses

[Diogo Ivo]

On a pure I3C bus there are no I2C devices, so the I3C core leaves
bus->scl_rate.i2c at zero if i2c-scl-hz is not specified in DT.
Deriving i2c_total_ticks from that zero rate programs a zero-width
open-drain SCL into the STDBR open-drain fields, which are still used
in pure I3C mode for example in DAA.

Fall back to the 1 MHz FM+ limit instead, the fastest rate an I2C
device could have, so that a sane open-drain timing is programmed.

Fixes: d028219a9f14 ("i3c: master: Add basic driver for the Renesas I3C controller")
Cc: stable@vger.kernel.org
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Diogo Ivo <diogo.ivo.sx@renesas.com>
---
Changes in v2:
 - Substituted if/else with ternary operator
 - Picked up R-b from Wolfram Sang
---
 drivers/i3c/master/renesas-i3c.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/i3c/master/renesas-i3c.c b/drivers/i3c/master/renesas-i3c.c
index 8b264f72e55c..78d0a2c4a19e 100644
--- a/drivers/i3c/master/renesas-i3c.c
+++ b/drivers/i3c/master/renesas-i3c.c
@@ -579,7 +579,15 @@ static int renesas_i3c_bus_init(struct i3c_master_controller *m)
 	if (!i3c->rate)
 		return -EINVAL;
 
-	i2c_total_ticks = DIV_ROUND_UP(i3c->rate, bus->scl_rate.i2c);
+	/*
+	 * A pure I3C bus has no I2C devices, so the I3C core leaves
+	 * scl_rate.i2c at zero if not explicitly defined in DT. The
+	 * open-drain SCL fields of STDBR, which are used for the DAA
+	 * pending read, are derived from it though, so fall back to
+	 * the 1 MHz FM+ limit instead of programming a zero-width clock.
+	 */
+	i2c_total_ticks = DIV_ROUND_UP(i3c->rate,
+				       bus->scl_rate.i2c ?: I3C_BUS_I2C_FM_PLUS_SCL_MAX_RATE);
 	i3c_total_ticks = DIV_ROUND_UP(i3c->rate, bus->scl_rate.i3c);
 
 	i2c_parse_fw_timings(&m->dev, &t, true);

-- 
2.56.0

Re: [PATCH v2 1/7] i3c: renesas: Fix zero I2C SCL rate on pure I3C buses

[Frank Li]

On Mon, Oct 26, 2026 at 11:35:44AM +0000, Diogo Ivo wrote:
> On a pure I3C bus there are no I2C devices, so the I3C core leaves
> bus->scl_rate.i2c at zero if i2c-scl-hz is not specified in DT.
> Deriving i2c_total_ticks from that zero rate programs a zero-width
> open-drain SCL into the STDBR open-drain fields, which are still used
> in pure I3C mode for example in DAA.
>
> Fall back to the 1 MHz FM+ limit instead, the fastest rate an I2C
> device could have, so that a sane open-drain timing is programmed.
>
> Fixes: d028219a9f14 ("i3c: master: Add basic driver for the Renesas I3C controller")
> Cc: stable@vger.kernel.org
> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
> Signed-off-by: Diogo Ivo <diogo.ivo.sx@renesas.com>
> ---

Reviewed-by: Frank Li <Frank.Li@nxp.com>

> Changes in v2:
>  - Substituted if/else with ternary operator
>  - Picked up R-b from Wolfram Sang
> ---
>  drivers/i3c/master/renesas-i3c.c | 10 +++++++++-
>  1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/i3c/master/renesas-i3c.c b/drivers/i3c/master/renesas-i3c.c
> index 8b264f72e55c..78d0a2c4a19e 100644
> --- a/drivers/i3c/master/renesas-i3c.c
> +++ b/drivers/i3c/master/renesas-i3c.c
> @@ -579,7 +579,15 @@ static int renesas_i3c_bus_init(struct i3c_master_controller *m)
>  	if (!i3c->rate)
>  		return -EINVAL;
>
> -	i2c_total_ticks = DIV_ROUND_UP(i3c->rate, bus->scl_rate.i2c);
> +	/*
> +	 * A pure I3C bus has no I2C devices, so the I3C core leaves
> +	 * scl_rate.i2c at zero if not explicitly defined in DT. The
> +	 * open-drain SCL fields of STDBR, which are used for the DAA
> +	 * pending read, are derived from it though, so fall back to
> +	 * the 1 MHz FM+ limit instead of programming a zero-width clock.
> +	 */
> +	i2c_total_ticks = DIV_ROUND_UP(i3c->rate,
> +				       bus->scl_rate.i2c ?: I3C_BUS_I2C_FM_PLUS_SCL_MAX_RATE);
>  	i3c_total_ticks = DIV_ROUND_UP(i3c->rate, bus->scl_rate.i3c);
>
>  	i2c_parse_fw_timings(&m->dev, &t, true);
>
> --
> 2.56.0
>

[PATCH v2 2/7] i3c: renesas: Drop comma after OF match table sentinel

[Diogo Ivo]

Drop the unnecessary terminator comma on the compatible table.
No functional changes intended.

Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Diogo Ivo <diogo.ivo.sx@renesas.com>
---
Changes in v2:
 - Picked up R-b from Wolfram Sang and Frank Li
---
 drivers/i3c/master/renesas-i3c.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/i3c/master/renesas-i3c.c b/drivers/i3c/master/renesas-i3c.c
index 78d0a2c4a19e..fe4e557e5b9c 100644
--- a/drivers/i3c/master/renesas-i3c.c
+++ b/drivers/i3c/master/renesas-i3c.c
@@ -1623,7 +1623,7 @@ static const struct dev_pm_ops renesas_i3c_pm_ops = {
 static const struct of_device_id renesas_i3c_of_ids[] = {
 	{ .compatible = "renesas,r9a08g045-i3c" },
 	{ .compatible = "renesas,r9a09g047-i3c" },
-	{ /* sentinel */ },
+	{ /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, renesas_i3c_of_ids);
 

-- 
2.56.0

[PATCH v2 3/7] dt-bindings: i3c: renesas,i3c: Add RZ/G3L support

[Diogo Ivo]

Add device tree binding support for I3C on the Renesas RZ/G3L
(R9A08G046) SoC.

The I3C IP on the RZ/G3L is a subset of the one on the RZ/G3S, as the
RZ/G3L has no HDR Exit Pattern detection interrupt. The resources are
consumed by name (the tclk clock, the presetn and tresetn resets and
seven of the named interrupts), all of which the RZ/G3L provides, so
software can match and bind a RZ/G3L node through the RZ/G3S
compatible. Add the RZ/G3L-specific "renesas,r9a08g046-i3c" compatible
with a fallback to the RZ/G3S "renesas,r9a08g045-i3c" compatible.

The RZ/G3L is not compatible with the RZ/G3E, which has no input analog
filters and supports high-speed mode (up to 3.4 Mbps).

Split the clock and interrupt constraints into separate if/else blocks
so that RZ/G3L nodes inherit the 2-clock limit from the RZ/G3S fallback
while being constrained to 16 interrupts alongside the RZ/G3E.

Signed-off-by: Diogo Ivo <diogo.ivo.sx@renesas.com>
---
Changes in v2:
- Describe the RZ/G3L by a SoC-specific compatible with a fallback to
  the renesas,r9a08g045-i3c compatible of the RZ/G3S, instead of a
  plain compatible, and drop the corresponding driver patch.
- Split the clock and interrupt constraints into separate if/else
  blocks to handle the RZ/G3S fallback on RZ/G3L nodes.
- Explain in the commit message why the RZ/G3L is not made compatible
  with the RZ/G3E.
---
 .../devicetree/bindings/i3c/renesas,i3c.yaml       | 27 ++++++++++++++--------
 1 file changed, 18 insertions(+), 9 deletions(-)

diff --git a/Documentation/devicetree/bindings/i3c/renesas,i3c.yaml b/Documentation/devicetree/bindings/i3c/renesas,i3c.yaml
index a20d875086d4..9f69766df07c 100644
--- a/Documentation/devicetree/bindings/i3c/renesas,i3c.yaml
+++ b/Documentation/devicetree/bindings/i3c/renesas,i3c.yaml
@@ -17,6 +17,9 @@ properties:
           - enum:
               - renesas,r9a08g045-i3c # RZ/G3S
               - renesas,r9a09g047-i3c # RZ/G3E
+      - items:
+          - const: renesas,r9a08g046-i3c # RZ/G3L
+          - const: renesas,r9a08g045-i3c
       - items:
           - enum:
               - renesas,r9a09g056-i3c # RZ/V2N
@@ -120,26 +123,32 @@ allOf:
           maxItems: 2
         clock-names:
           maxItems: 2
-        interrupts:
-          minItems: 17
-        interrupt-names:
-          minItems: 17
+    else:
+      properties:
+        clocks:
+          minItems: 3
+        clock-names:
+          minItems: 3
 
   - if:
       properties:
         compatible:
           contains:
-            const: renesas,r9a09g047-i3c
+            enum:
+              - renesas,r9a08g046-i3c
+              - renesas,r9a09g047-i3c
     then:
       properties:
-        clocks:
-          minItems: 3
-        clock-names:
-          minItems: 3
         interrupts:
           maxItems: 16
         interrupt-names:
           maxItems: 16
+    else:
+      properties:
+        interrupts:
+          minItems: 17
+        interrupt-names:
+          minItems: 17
 
 unevaluatedProperties: false
 

-- 
2.56.0

Re: [PATCH v2 3/7] dt-bindings: i3c: renesas,i3c: Add RZ/G3L support

[Krzysztof Kozlowski]

On Mon, Oct 26, 2026 at 11:35:46AM +0000, Diogo Ivo wrote:
> Add device tree binding support for I3C on the Renesas RZ/G3L
> (R9A08G046) SoC.
> 
> The I3C IP on the RZ/G3L is a subset of the one on the RZ/G3S, as the
> RZ/G3L has no HDR Exit Pattern detection interrupt. The resources are
> consumed by name (the tclk clock, the presetn and tresetn resets and
> seven of the named interrupts), all of which the RZ/G3L provides, so
> software can match and bind a RZ/G3L node through the RZ/G3S
> compatible. Add the RZ/G3L-specific "renesas,r9a08g046-i3c" compatible
> with a fallback to the RZ/G3S "renesas,r9a08g045-i3c" compatible.
> 
> The RZ/G3L is not compatible with the RZ/G3E, which has no input analog
> filters and supports high-speed mode (up to 3.4 Mbps).
> 
> Split the clock and interrupt constraints into separate if/else blocks
> so that RZ/G3L nodes inherit the 2-clock limit from the RZ/G3S fallback
> while being constrained to 16 interrupts alongside the RZ/G3E.
> 
> Signed-off-by: Diogo Ivo <diogo.ivo.sx@renesas.com>
> ---
> Changes in v2:
> - Describe the RZ/G3L by a SoC-specific compatible with a fallback to
>   the renesas,r9a08g045-i3c compatible of the RZ/G3S, instead of a
>   plain compatible, and drop the corresponding driver patch.
> - Split the clock and interrupt constraints into separate if/else
>   blocks to handle the RZ/G3S fallback on RZ/G3L nodes.
> - Explain in the commit message why the RZ/G3L is not made compatible
>   with the RZ/G3E.
> ---
>  .../devicetree/bindings/i3c/renesas,i3c.yaml       | 27 ++++++++++++++--------
>  1 file changed, 18 insertions(+), 9 deletions(-)

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>

Best regards,
Krzysztof

[PATCH v2 4/7] clk: renesas: r9a08g046: Add I3C clocks and resets

[Diogo Ivo]

Add the P5 fixed clock, the module clocks for the I3C Bus Interface
(pclk, tclk), along with the corresponding module resets (presetn,
tresetn) on the RZ/G3L (R9A08G046) SoC.

Signed-off-by: Diogo Ivo <diogo.ivo.sx@renesas.com>
---
Changes in v2:
 - No changes
---
 drivers/clk/renesas/r9a08g046-cpg.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/clk/renesas/r9a08g046-cpg.c b/drivers/clk/renesas/r9a08g046-cpg.c
index b58057db9c4d..3833f88125ea 100644
--- a/drivers/clk/renesas/r9a08g046-cpg.c
+++ b/drivers/clk/renesas/r9a08g046-cpg.c
@@ -340,6 +340,7 @@ static const struct cpg_core_clk r9a08g046_core_clks[] __initconst = {
 		    dtable_4_128, 0, 0, 0, NULL),
 	DEF_FIXED("P4", R9A08G046_CLK_P4, CLK_PLL2_DIV2, 1, 5),
 	DEF_FIXED(".p4_div2", CLK_P4_DIV2, R9A08G046_CLK_P4, 1, 2),
+	DEF_FIXED("P5", R9A08G046_CLK_P5, CLK_PLL2_DIV2, 1, 4),
 	DEF_FIXED("P8", R9A08G046_CLK_P8, CLK_PLL3_DIV2, 1, 8),
 	DEF_G3S_DIV("P13", R9A08G046_CLK_P13, CLK_SEL_RSCI0, G3L_DIV_RSCI0, G3L_DIV_RSCI0_STS,
 		    dtable_2_16, 0, 100000000UL, 0, NULL),
@@ -581,6 +582,10 @@ static const struct rzg2l_mod_clk r9a08g046_mod_clks[] = {
 					MSTOP(BUS_PERI_COM, BIT(10))),
 	DEF_MOD("pci_clk_pmu",		R9A08G046_PCI_CLK_PMU, R9A08G046_CLK_P1, 0x608, 2,
 					MSTOP(BUS_PERI_COM, BIT(10))),
+	DEF_MOD("i3c_pclk",		R9A08G046_I3C_PCLK, R9A08G046_CLK_P20, 0x610, 0,
+					MSTOP(BUS_MCPU3, BIT(10))),
+	DEF_MOD("i3c_tclk",		R9A08G046_I3C_TCLK, R9A08G046_CLK_P5, 0x610, 1,
+					MSTOP(BUS_MCPU3, BIT(10))),
 	DEF_MOD("rsci0_pclk",		R9A08G046_RSCI0_PCLK, R9A08G046_CLK_P0, 0x618, 0,
 					MSTOP(BUS_MCPU2, BIT(7))),
 	DEF_MOD("rsci1_pclk",		R9A08G046_RSCI1_PCLK, R9A08G046_CLK_P0, 0x618, 1,
@@ -662,6 +667,8 @@ static const struct rzg2l_reset r9a08g046_resets[] = {
 	DEF_RST(R9A08G046_ADC1_ADRST_N, 0x8a8, 3),
 	DEF_RST(R9A08G046_TSU_PRESETN, 0x8ac, 0),
 	DEF_RST(R9A08G046_PCI_ARESETN, 0x908, 0),
+	DEF_RST(R9A08G046_I3C_PRESETN, 0x910, 0),
+	DEF_RST(R9A08G046_I3C_TRESETN, 0x910, 1),
 	DEF_RST(R9A08G046_RSCI0_PRESETN, 0x918, 0),
 	DEF_RST(R9A08G046_RSCI1_PRESETN, 0x918, 1),
 	DEF_RST(R9A08G046_RSCI2_PRESETN, 0x918, 2),

-- 
2.56.0

[PATCH v2 5/7] pinctrl: renesas: rzg2l: Split SoC-specific masks in struct rzg2l_register_masks

[Diogo Ivo]

struct rzg2l_register_masks declares the masks of the OTHER_POC register
of RZ/G3L and of the I3C_SET_POC register of RZ/G3S in two branches of an
anonymous union. As both branches share the same storage, initializing both
other_poc_pvdd1833_oth_awo_poc and i3c_set_poc on RZ/G3L would have the
designated initializers override each other, ending up with the I3C_SET_POC
value in the PVDD1833_OTH_AWO_POC mask.

Split the union into a common area, for masks shared by multiple SoCs, and
per-SoC areas: the RZ/G3S and RZ/G3L I3C_SET_POC mask moves to the common
area, and the RZ/G3L OTHER_POC masks stay in a dedicated RZ/G3L area. This
way every mask gets its own member, and new SoCs can be described by
adding their own struct (possibly inside a union).

The existing RZ/G3S data only initializes i3c_set_poc, so it is not
affected by this change.

Signed-off-by: Diogo Ivo <diogo.ivo.sx@renesas.com>
---
Changes in v2:
 - No changes
---
 drivers/pinctrl/renesas/pinctrl-rzg2l.c | 20 ++++++++------------
 1 file changed, 8 insertions(+), 12 deletions(-)

diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 9bf3743dc1ce..f73d273df362 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -278,18 +278,14 @@ struct rzg2l_register_offsets {
  * @i3c_set_poc: I3C_SET_POC mask
  */
 struct rzg2l_register_masks {
-	union {
-		/* RZ/G3L masks */
-		struct {
-			u8 other_poc_pvdd1833_oth_awo_poc;
-			u8 other_poc_pvdd1833_oth_iso_poc;
-			u8 other_poc_wdtovf_n_poc;
-		};
-
-		/* RZ/G3S masks */
-		struct {
-			u8 i3c_set_poc;
-		};
+	/* Masks common to multiple SoCs */
+	u8 i3c_set_poc; /* RZ/G3S, RZ/G3L */
+
+	/* RZ/G3L masks */
+	struct {
+		u8 other_poc_pvdd1833_oth_awo_poc;
+		u8 other_poc_pvdd1833_oth_iso_poc;
+		u8 other_poc_wdtovf_n_poc;
 	};
 };
 

-- 
2.56.0

[PATCH v2 6/7] pinctrl: renesas: rzg2l: Add RZ/G3L support for selecting I3C power source

[Diogo Ivo]

The Renesas RZ/G3L I3C pins can be powered at either 1.8V or 1.2V.  The
pin controller provides a register to select between these two options.
On RZ/G3L the I3C signals are multiplexed on the P2 port pins.  Update
the Renesas RZ/G2L pin controller driver to allow selecting the I3C
power source on RZ/G3L SoC.

Signed-off-by: Diogo Ivo <diogo.ivo.sx@renesas.com>
---
Changes in v2:
 - No changes
---
 drivers/pinctrl/renesas/pinctrl-rzg2l.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index f73d273df362..192da9f9a55d 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -2431,7 +2431,8 @@ static const char * const rzg3l_gpio_names[] = {
 static const u64 r9a08g046_gpio_configs[] = {
 	0x0,
 	0x0,
-	RZG2L_GPIO_PORT_PACK(2, 0x22, PIN_CFG_NF | PIN_CFG_IEN),	/* P2 */
+	RZG2L_GPIO_PORT_PACK(2, 0x22, PIN_CFG_NF | PIN_CFG_IEN |
+				      PIN_CFG_IO_VMC_I3C),		/* P2 */
 	RZG2L_GPIO_PORT_PACK(7, 0x23, RZG3L_MPXED_PIN_FUNCS_POC(A, AWO)), /* P3 */
 	0x0,
 	RZG2L_GPIO_PORT_PACK(7, 0x25, RZG3L_MPXED_PIN_FUNCS_POC(A, ISO)), /* P5 */
@@ -3933,10 +3934,12 @@ static const struct rzg2l_hwcfg rzg3l_hwcfg = {
 		.sd_ch = 0x3004,
 		.sd_ch2 = 0x3024,
 		.eth_poc = 0x3010,
+		.i3c_set = 0x301c,
 		.oen = 0x3018,
 		.other_poc = 0x3028,
 	},
 	.masks = {
+		.i3c_set_poc = BIT(2),
 		.other_poc_pvdd1833_oth_awo_poc = BIT(0),
 		.other_poc_pvdd1833_oth_iso_poc = BIT(1),
 		.other_poc_wdtovf_n_poc = BIT(2),

-- 
2.56.0

[PATCH v2 7/7] arm64: dts: renesas: r9a08g046: Add I3C support

[Diogo Ivo]

Add the I3C Bus Interface node to the RZ/G3L (R9A08G046) SoC DTSI and
enable it on the RZ/G3L SMARC EVK, together with the required pin
control.

The driver only consumes resources that are common to the RZ/G3L and
the RZ/G3S (R9A08G045), so the node uses the SoC-specific
renesas,r9a08g046-i3c compatible with a fallback to the
renesas,r9a08g045-i3c compatible of the RZ/G3S, following the bindings.

The I3C pins are shared with RIIC3, so the controller is only enabled
when the SW_I3C_EN switch is on.

The I3C I/O voltage can be set to 1.2V or 1.8V on the board through
the SYS.3 (I3C_IOVS) switch, so configure the pin controller for the
selected voltage through the power-source property.

Signed-off-by: Diogo Ivo <diogo.ivo.sx@renesas.com>
---
Changes in v2:
 - Declare compatible with G3S fallback
 - Sort the &i3c and i3c_pins nodes alphabetically in
   r9a08g046l48-smarc.dts
---
 arch/arm64/boot/dts/renesas/r9a08g046.dtsi         | 35 ++++++++++++++++++++++
 arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts | 21 +++++++++++++
 arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi   |  4 +++
 3 files changed, 60 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
index f33d5d7468ff..fccfe8d7faf5 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a08g046.dtsi
@@ -620,6 +620,41 @@ canfd: can@100c0000 {
 			/* placeholder */
 		};
 
+		i3c: i3c@100e0000 {
+			compatible = "renesas,r9a08g046-i3c", "renesas,r9a08g045-i3c";
+			reg = <0 0x100e0000 0 0x1000>;
+			interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 361 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 362 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 363 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
+				     <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "ierr", "terr", "abort", "resp",
+					  "cmd", "ibi", "rx", "tx", "rcv",
+					  "st", "sp", "tend", "nack", "al",
+					  "tmo", "wu";
+			clocks = <&cpg CPG_MOD R9A08G046_I3C_PCLK>,
+				 <&cpg CPG_MOD R9A08G046_I3C_TCLK>;
+			clock-names = "pclk", "tclk";
+			resets = <&cpg R9A08G046_I3C_PRESETN>,
+				 <&cpg R9A08G046_I3C_TRESETN>;
+			reset-names = "presetn", "tresetn";
+			power-domains = <&cpg>;
+			#address-cells = <3>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		ssi0: ssi@100e4000 {
 			compatible = "renesas,r9a08g046-ssi", "renesas,rz-ssi";
 			reg = <0 0x100e4000 0 0x400>;
diff --git a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
index 68d7b579e352..a713d63b4510 100644
--- a/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
+++ b/arch/arm64/boot/dts/renesas/r9a08g046l48-smarc.dts
@@ -13,6 +13,7 @@
 #define SW_DPI_EN		0
 #define SW_GPIO4		1
 #define SW_I3C_EN		0
+#define SW_I3C_IOVS		0
 #define SW_SER0_PMOD		1
 
 #define PMOD_GPIO4		0
@@ -120,6 +121,16 @@ da7212: codec@1a {
 };
 #endif
 
+#if SW_I3C_EN
+&i3c {
+	pinctrl-0 = <&i3c_pins>;
+	pinctrl-names = "default";
+	i2c-scl-hz = <400000>;
+	i3c-scl-hz = <12500000>;
+	status = "okay";
+};
+#endif
+
 &keys {
 #if !RZ_BOOT_MODE3 || !SW_GPIO4 || PMOD_GPIO4
 	/delete-node/ key-1;
@@ -163,6 +174,16 @@ i2c3_pins: i2c3 {
 			 <RZG3L_PORT_PINMUX(2, 1, 4)>; /* RIIC3_SDA */
 	};
 
+	i3c_pins: i3c {
+		pinmux = <RZG3L_PORT_PINMUX(2, 0, 2)>, /* I3C_SCL */
+			 <RZG3L_PORT_PINMUX(2, 1, 2)>; /* I3C_SDA */
+#if SW_I3C_IOVS
+		power-source = <1800>;
+#else
+		power-source = <1200>;
+#endif
+	};
+
 	pcie-clkreq-n-hog {
 		gpio-hog;
 		gpios = <RZG3L_GPIO(G, 6) GPIO_ACTIVE_HIGH>;
diff --git a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
index 91b2d0d43104..5959e62ad7ed 100644
--- a/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
+++ b/arch/arm64/boot/dts/renesas/rzg3l-smarc-som.dtsi
@@ -13,6 +13,10 @@
  *      0 - SMARC_I2C_GP is enabled
  *      1 - I3C is enabled
  *
+ * Switch position SYS.3, Macro SW_I3C_IOVS:
+ *      0 - I3C voltage is 1.2V (when SW_I3C_EN == 1)
+ *      1 - I3C voltage is 1.8V
+ *
  * Switch position SYS.4, Macro SW_SD2_EN:
  *      0 - Select I2S0
  *      1 - Select SD2

-- 
2.56.0