[PATCH v2 0/4] Add Tegra238 BPMP support and fix stale EMC clock rate

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* [PATCH v2 0/4] Add Tegra238 BPMP support and fix stale EMC clock rate
@ 2026-10-28 15:49 Johnny Liu
  2026-10-28 15:49 ` [PATCH v2 1/4] dt-bindings: firmware: tegra186-bpmp: Add Tegra238 BPMP Johnny Liu
                   ` (3 more replies)
  0 siblings, 4 replies; 5+ messages in thread
From: Johnny Liu @ 2026-10-28 15:49 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Thierry Reding,
	Jonathan Hunter, Prashant Gaikwad, Stephen Boyd, Brian Masney,
	Jerome Brunet, Douglas Anderson, Aniruddha Rao, devicetree,
	linux-tegra, linux-kernel, linux-clk
  Cc: Johnny Liu

EMC clock scaling is handled by the BPMP firmware without kernel
involvement, so clk_get_rate() on the EMC clock can return a stale value
cached by the common clock framework. This series makes the EMC clock
rate uncached on Tegra234, Tegra238 and Tegra264, and adds the pieces
needed to identify the EMC clock on each of these chips.

The EMC clock ID differs per chip (TEGRA234_CLK_EMC=31,
TEGRA238_CLK_EMC=43, TEGRA264_CLK_EMC=290), while the
"nvidia,tegra186-bpmp" fallback compatible and the tegra186_soc data are
shared across several chips. To avoid detecting the chip at runtime, the
EMC clock ID is carried in per-SoC BPMP data selected by the device tree
compatible.

Patch 1 adds the "nvidia,tegra238-bpmp" compatible to the binding,
together with the Tegra238 clock ID header. Patch 2 adds dedicated SoC
data for Tegra234, Tegra238 and Tegra264, selected by their specific
compatibles, and builds the BPMP driver for CONFIG_ARCH_TEGRA_238_SOC.
Patch 3 adds an emc_clk_id field to struct tegra_bpmp_soc and sets it
using the TEGRA*_CLK_EMC clock ID macros. Patch 4 then sets
CLK_GET_RATE_NOCACHE on the clock matching that ID.

The series touches both the clock and the firmware code. Patch 4 depends
on patch 3, which in turn depends on patch 1, so I would suggest taking
the whole series through the Tegra tree with an Acked-by from the clock
maintainers.

Changes in v2:
- Squash "dt-bindings: clock: Add Tegra238 BPMP clock IDs" into
  "dt-bindings: firmware: tegra186-bpmp: Add Tegra238 compatible".
- Reword the binding commit message to state that the Tegra238 SoC is
  fully compatible with the Tegra186 BPMP.

v1: https://lore.kernel.org/all/20261028084900.1047287-1-johnliu@nvidia.com/

Johnny Liu (4):
  dt-bindings: firmware: tegra186-bpmp: Add Tegra238 BPMP
  firmware: tegra: bpmp: Add Tegra238 support
  firmware: tegra: bpmp: Add per-SoC EMC clock ID
  clk: tegra: bpmp: Do not cache the EMC clock rate

 .../firmware/nvidia,tegra186-bpmp.yaml        |   1 +
 drivers/clk/tegra/clk-bpmp.c                  |   3 +
 drivers/firmware/tegra/Makefile               |   1 +
 drivers/firmware/tegra/bpmp.c                 |  61 ++--
 include/dt-bindings/clock/nvidia,tegra238.h   | 279 ++++++++++++++++++
 include/soc/tegra/bpmp.h                      |   1 +
 6 files changed, 329 insertions(+), 17 deletions(-)
 create mode 100644 include/dt-bindings/clock/nvidia,tegra238.h

-- 
2.43.0

^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH v2 1/4] dt-bindings: firmware: tegra186-bpmp: Add Tegra238 BPMP
  2026-10-28 15:49 [PATCH v2 0/4] Add Tegra238 BPMP support and fix stale EMC clock rate Johnny Liu
@ 2026-10-28 15:49 ` Johnny Liu
  2026-10-28 15:49 ` [PATCH v2 2/4] firmware: tegra: bpmp: Add Tegra238 support Johnny Liu
                   ` (2 subsequent siblings)
  3 siblings, 0 replies; 5+ messages in thread
From: Johnny Liu @ 2026-10-28 15:49 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Thierry Reding,
	Jonathan Hunter, Prashant Gaikwad, Stephen Boyd, Brian Masney,
	Jerome Brunet, Douglas Anderson, Aniruddha Rao, devicetree,
	linux-tegra, linux-kernel, linux-clk
  Cc: Johnny Liu

The Tegra238 SoC is fully compatible with the Tegra186 BPMP.

Add the clock IDs exposed by the BPMP firmware on Tegra238.

Signed-off-by: Johnny Liu <johnliu@nvidia.com>
---
 .../firmware/nvidia,tegra186-bpmp.yaml        |   1 +
 include/dt-bindings/clock/nvidia,tegra238.h   | 279 ++++++++++++++++++
 2 files changed, 280 insertions(+)
 create mode 100644 include/dt-bindings/clock/nvidia,tegra238.h

diff --git a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml
index 3c44fe607e12..4011fdf4a54d 100644
--- a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml
+++ b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml
@@ -70,6 +70,7 @@ properties:
           - enum:
               - nvidia,tegra194-bpmp
               - nvidia,tegra234-bpmp
+              - nvidia,tegra238-bpmp
               - nvidia,tegra264-bpmp
           - const: nvidia,tegra186-bpmp
       - const: nvidia,tegra186-bpmp
diff --git a/include/dt-bindings/clock/nvidia,tegra238.h b/include/dt-bindings/clock/nvidia,tegra238.h
new file mode 100644
index 000000000000..31313302d9ef
--- /dev/null
+++ b/include/dt-bindings/clock/nvidia,tegra238.h
@@ -0,0 +1,279 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/* Copyright (c) 2026, NVIDIA CORPORATION. All rights reserved. */
+
+#ifndef DT_BINDINGS_CLOCK_NVIDIA_TEGRA238_H
+#define DT_BINDINGS_CLOCK_NVIDIA_TEGRA238_H
+
+#define TEGRA238_CLK_ACLK				1
+#define TEGRA238_CLK_ACTMON				2
+#define TEGRA238_CLK_ADSP				3
+#define TEGRA238_CLK_ADSPNEON				4
+#define TEGRA238_CLK_AHUB				5
+#define TEGRA238_CLK_AON_APB				6
+#define TEGRA238_CLK_AON_CPU_NIC			7
+#define TEGRA238_CLK_AON_I2C_SLOW			8
+#define TEGRA238_CLK_AON_NIC				9
+#define TEGRA238_CLK_AON_TOUCH				10
+#define TEGRA238_CLK_APB2APE				11
+#define TEGRA238_CLK_APE				12
+#define TEGRA238_CLK_AUD_MCLK				13
+#define TEGRA238_CLK_AXI_CBB				14
+#define TEGRA238_CLK_AZA_2XBIT				15
+#define TEGRA238_CLK_AZA_BIT				16
+#define TEGRA238_CLK_BPMP_CPU				17
+#define TEGRA238_CLK_BPMP_CPU_NIC			18
+#define TEGRA238_CLK_CLK_32K				19
+#define TEGRA238_CLK_CLK_M				20
+#define TEGRA238_CLK_CSITE				21
+#define TEGRA238_CLK_DBGAPB				22
+#define TEGRA238_CLK_DISP				23
+#define TEGRA238_CLK_DISPHUBPLL				24
+#define TEGRA238_CLK_DISPPLL				25
+#define TEGRA238_CLK_DISP_ROOT				26
+#define TEGRA238_CLK_DMIC1				27
+#define TEGRA238_CLK_DMIC3				28
+#define TEGRA238_CLK_DMIC4				29
+#define TEGRA238_CLK_DMIC5				30
+#define TEGRA238_CLK_DPAUX				31
+#define TEGRA238_CLK_DP_LINK_REF			32
+#define TEGRA238_CLK_DSC				33
+#define TEGRA238_CLK_DSIPLL_CLKOUTA			34
+#define TEGRA238_CLK_DSIPLL_CLKOUTPN			35
+#define TEGRA238_CLK_DSIPLL_VCO				36
+#define TEGRA238_CLK_DSI_CORE				37
+#define TEGRA238_CLK_DSI_LP				38
+#define TEGRA238_CLK_DSI_PAD_INPUT			39
+#define TEGRA238_CLK_DSI_PIXEL				40
+#define TEGRA238_CLK_DSPK1				41
+#define TEGRA238_CLK_DSPK2				42
+#define TEGRA238_CLK_EMC				43
+#define TEGRA238_CLK_EMCHUB				44
+#define TEGRA238_CLK_EMCSA_EMC				45
+#define TEGRA238_CLK_EMCSA_MC				46
+#define TEGRA238_CLK_EMCSA_MPLL				47
+#define TEGRA238_CLK_EMCSB_EMC				48
+#define TEGRA238_CLK_EMCSB_MC				49
+#define TEGRA238_CLK_EMCSB_MPLL				50
+#define TEGRA238_CLK_EXTPERIPH1				51
+#define TEGRA238_CLK_EXTPERIPH2				52
+#define TEGRA238_CLK_EXTPERIPH3				53
+#define TEGRA238_CLK_EXTPERIPH4				54
+#define TEGRA238_CLK_FDE				55
+#define TEGRA238_CLK_FR_SE				56
+#define TEGRA238_CLK_FR_SEU1				57
+#define TEGRA238_CLK_FUSE				58
+#define TEGRA238_CLK_FUSE_BURN				59
+#define TEGRA238_CLK_FUSE_SERIAL			60
+#define TEGRA238_CLK_GPC0CLK				61
+#define TEGRA238_CLK_GPU_PWR				62
+#define TEGRA238_CLK_HOST1X				63
+#define TEGRA238_CLK_HUB				64
+#define TEGRA238_CLK_HUB_ROOT				65
+#define TEGRA238_CLK_I2C1				66
+#define TEGRA238_CLK_I2C2				67
+#define TEGRA238_CLK_I2C3				68
+#define TEGRA238_CLK_I2C4				69
+#define TEGRA238_CLK_I2C5				70
+#define TEGRA238_CLK_I2C6				71
+#define TEGRA238_CLK_I2C7				72
+#define TEGRA238_CLK_I2C8				73
+#define TEGRA238_CLK_I2C9				74
+#define TEGRA238_CLK_I2C_SLOW				75
+#define TEGRA238_CLK_I2S1				76
+#define TEGRA238_CLK_I2S1_SYNC_INPUT			77
+#define TEGRA238_CLK_I2S2				78
+#define TEGRA238_CLK_I2S2_SYNC_INPUT			79
+#define TEGRA238_CLK_I2S3				80
+#define TEGRA238_CLK_I2S3_SYNC_INPUT			81
+#define TEGRA238_CLK_I2S4				82
+#define TEGRA238_CLK_I2S4_SYNC_INPUT			83
+#define TEGRA238_CLK_I2S5				84
+#define TEGRA238_CLK_I2S5_SYNC_INPUT			85
+#define TEGRA238_CLK_I2S6				86
+#define TEGRA238_CLK_I2S6_SYNC_INPUT			87
+#define TEGRA238_CLK_JTAG_INTFC_PRE_CG			88
+#define TEGRA238_CLK_LA					89
+#define TEGRA238_CLK_LINKA_SYM_CLKOUT			90
+#define TEGRA238_CLK_LINKF_SYM_CLKOUT			91
+#define TEGRA238_CLK_MAUD				92
+#define TEGRA238_CLK_MCHUB				93
+#define TEGRA238_CLK_MIPI_CAL				94
+#define TEGRA238_CLK_MPHY_CORE_PLL_FIXED		95
+#define TEGRA238_CLK_MPHY_FORCE_LS_MODE			96
+#define TEGRA238_CLK_MPHY_L0_RX_ANA			97
+#define TEGRA238_CLK_MPHY_L0_RX_HS_SYMB_DIV		98
+#define TEGRA238_CLK_MPHY_L0_RX_LS_BIT			99
+#define TEGRA238_CLK_MPHY_L0_RX_LS_BIT_DIV		100
+#define TEGRA238_CLK_MPHY_L0_RX_LS_SYMB_DIV		101
+#define TEGRA238_CLK_MPHY_L0_RX_MUX_SYMB_DIV		102
+#define TEGRA238_CLK_MPHY_L0_RX_SYMB			103
+#define TEGRA238_CLK_MPHY_L0_TX_2X_SYMB			104
+#define TEGRA238_CLK_MPHY_L0_TX_HS_SYMB_DIV		105
+#define TEGRA238_CLK_MPHY_L0_TX_LS_3XBIT		106
+#define TEGRA238_CLK_MPHY_L0_TX_LS_3XBIT_DIV		107
+#define TEGRA238_CLK_MPHY_L0_TX_LS_SYMB_DIV		108
+#define TEGRA238_CLK_MPHY_L0_TX_MUX_SYMB_DIV		109
+#define TEGRA238_CLK_MPHY_L0_TX_PRE_SYMB		110
+#define TEGRA238_CLK_MPHY_L0_TX_SYMB			111
+#define TEGRA238_CLK_MPHY_L1_RX_ANA			112
+#define TEGRA238_CLK_MPHY_TX_1MHZ_REF			113
+#define TEGRA238_CLK_MSS_ENCRYPT			114
+#define TEGRA238_CLK_NAFLL_BPMP				115
+#define TEGRA238_CLK_NAFLL_CLUSTER0_CORE		116
+#define TEGRA238_CLK_NAFLL_CLUSTER0_DSU			117
+#define TEGRA238_CLK_NAFLL_FDE				118
+#define TEGRA238_CLK_NAFLL_GPC0				119
+#define TEGRA238_CLK_NAFLL_NVDEC			120
+#define TEGRA238_CLK_NAFLL_NVENC			121
+#define TEGRA238_CLK_NAFLL_OFA				122
+#define TEGRA238_CLK_NAFLL_SE				123
+#define TEGRA238_CLK_NAFLL_SEU1				124
+#define TEGRA238_CLK_NAFLL_TSEC				125
+#define TEGRA238_CLK_NAFLL_VIC				126
+#define TEGRA238_CLK_NVDEC				127
+#define TEGRA238_CLK_NVDISPLAY_P0			128
+#define TEGRA238_CLK_NVDISPLAY_P1			129
+#define TEGRA238_CLK_NVENC				130
+#define TEGRA238_CLK_OFA				131
+#define TEGRA238_CLK_OSC				132
+#define TEGRA238_CLK_PEX0_C0_CORE			133
+#define TEGRA238_CLK_PEX0_C1_CORE			134
+#define TEGRA238_CLK_PEX0_C2_CORE			135
+#define TEGRA238_CLK_PEX0_C3_CORE			136
+#define TEGRA238_CLK_PEX_SATA_USB_RX_BYP		137
+#define TEGRA238_CLK_PEX_USB_PAD_PLL0_MGMT		138
+#define TEGRA238_CLK_PEX_USB_PAD_PLL1_MGMT		139
+#define TEGRA238_CLK_PEX_USB_PAD_PLL2_MGMT		140
+#define TEGRA238_CLK_PEX_USB_PAD_PLL3_MGMT		141
+#define TEGRA238_CLK_PLLA				142
+#define TEGRA238_CLK_PLLA1				143
+#define TEGRA238_CLK_PLLA1_OUT1				144
+#define TEGRA238_CLK_PLLAON				145
+#define TEGRA238_CLK_PLLA_DISP				146
+#define TEGRA238_CLK_PLLA_DISPHUB			147
+#define TEGRA238_CLK_PLLA_DIV2				148
+#define TEGRA238_CLK_PLLA_OUT0				149
+#define TEGRA238_CLK_PLLC				150
+#define TEGRA238_CLK_PLLC2				151
+#define TEGRA238_CLK_PLLC4				152
+#define TEGRA238_CLK_PLLC4_MUXED			153
+#define TEGRA238_CLK_PLLC4_OUT1				154
+#define TEGRA238_CLK_PLLC4_OUT2				155
+#define TEGRA238_CLK_PLLC4_VCO_DIV2			156
+#define TEGRA238_CLK_PLLE				157
+#define TEGRA238_CLK_PLLE_HPS				158
+#define TEGRA238_CLK_PLLHUB				159
+#define TEGRA238_CLK_PLLP				160
+#define TEGRA238_CLK_PLLP_AUDIO				161
+#define TEGRA238_CLK_PLLP_DIV17				162
+#define TEGRA238_CLK_PLLP_OUT0				163
+#define TEGRA238_CLK_PLLP_OUT_JTAG			164
+#define TEGRA238_CLK_PLLREFE_VCOOUT			165
+#define TEGRA238_CLK_PLLREFE_VCOOUT_GATED		166
+#define TEGRA238_CLK_PPC				167
+#define TEGRA238_CLK_PRE_SF0				168
+#define TEGRA238_CLK_PRE_SOR0				169
+#define TEGRA238_CLK_PRE_SOR0_REF			170
+#define TEGRA238_CLK_PRE_SOR1				171
+#define TEGRA238_CLK_PRE_SOR1_REF			172
+#define TEGRA238_CLK_PWM1				173
+#define TEGRA238_CLK_PWM2				174
+#define TEGRA238_CLK_PWM3				175
+#define TEGRA238_CLK_PWM4				176
+#define TEGRA238_CLK_PWM5				177
+#define TEGRA238_CLK_PWM6				178
+#define TEGRA238_CLK_PWM7				179
+#define TEGRA238_CLK_PWM8				180
+#define TEGRA238_CLK_QSPI0_2X_PM			181
+#define TEGRA238_CLK_QSPI0_PM				182
+#define TEGRA238_CLK_RG0				183
+#define TEGRA238_CLK_RG1				184
+#define TEGRA238_CLK_SDMMC1				185
+#define TEGRA238_CLK_SDMMC4				186
+#define TEGRA238_CLK_SDMMC4_AXICIF			187
+#define TEGRA238_CLK_SDMMC_LEGACY_TM			188
+#define TEGRA238_CLK_SE					189
+#define TEGRA238_CLK_SEU1				190
+#define TEGRA238_CLK_SF0				191
+#define TEGRA238_CLK_SF0_POSTMUX			192
+#define TEGRA238_CLK_SF1				193
+#define TEGRA238_CLK_SF1_POSTMUX			194
+#define TEGRA238_CLK_SOC_THERM				195
+#define TEGRA238_CLK_SOR0				196
+#define TEGRA238_CLK_SOR0_PAD_CLKOUT			197
+#define TEGRA238_CLK_SOR0_PLL_REF			198
+#define TEGRA238_CLK_SOR0_REF				199
+#define TEGRA238_CLK_SOR1				200
+#define TEGRA238_CLK_SOR1_PAD_CLKOUT			201
+#define TEGRA238_CLK_SOR1_PLL_REF			202
+#define TEGRA238_CLK_SOR1_REF				203
+#define TEGRA238_CLK_SOR_SAFE				204
+#define TEGRA238_CLK_SPI1				205
+#define TEGRA238_CLK_SPI2				206
+#define TEGRA238_CLK_SPI3				207
+#define TEGRA238_CLK_SPI4				208
+#define TEGRA238_CLK_SPI5				209
+#define TEGRA238_CLK_SPPLL0_CLKOUTA			210
+#define TEGRA238_CLK_SPPLL0_CLKOUTB			211
+#define TEGRA238_CLK_SPPLL0_CLKOUTPN			212
+#define TEGRA238_CLK_SPPLL0_DIV10			213
+#define TEGRA238_CLK_SPPLL0_DIV25			214
+#define TEGRA238_CLK_SPPLL0_DIV27PN			215
+#define TEGRA238_CLK_SPPLL0_VCO				216
+#define TEGRA238_CLK_SPPLL1_CLKOUTPN			217
+#define TEGRA238_CLK_SPPLL1_DIV27PN			218
+#define TEGRA238_CLK_SPPLL1_VCO				219
+#define TEGRA238_CLK_SYNC_DMIC1				220
+#define TEGRA238_CLK_SYNC_DMIC3				221
+#define TEGRA238_CLK_SYNC_DMIC4				222
+#define TEGRA238_CLK_SYNC_DSPK1				223
+#define TEGRA238_CLK_SYNC_DSPK2				224
+#define TEGRA238_CLK_SYNC_I2S1				225
+#define TEGRA238_CLK_SYNC_I2S2				226
+#define TEGRA238_CLK_SYNC_I2S3				227
+#define TEGRA238_CLK_SYNC_I2S4				228
+#define TEGRA238_CLK_SYNC_I2S5				229
+#define TEGRA238_CLK_SYNC_I2S6				230
+#define TEGRA238_CLK_TACH0				231
+#define TEGRA238_CLK_TACH1				232
+#define TEGRA238_CLK_TSC				233
+#define TEGRA238_CLK_TSC_REF				234
+#define TEGRA238_CLK_TSEC				235
+#define TEGRA238_CLK_TSEC_PKA				236
+#define TEGRA238_CLK_TSENSE				237
+#define TEGRA238_CLK_UARTA				238
+#define TEGRA238_CLK_UARTB				239
+#define TEGRA238_CLK_UARTC				240
+#define TEGRA238_CLK_UARTD				241
+#define TEGRA238_CLK_UARTE				242
+#define TEGRA238_CLK_UARTF				243
+#define TEGRA238_CLK_UARTG				244
+#define TEGRA238_CLK_UARTH				245
+#define TEGRA238_CLK_UART_FST_MIPI_CAL			246
+#define TEGRA238_CLK_UFSDEV_REF				247
+#define TEGRA238_CLK_UFSHC				248
+#define TEGRA238_CLK_UPHY_PLL3				249
+#define TEGRA238_CLK_USB2_TRK				250
+#define TEGRA238_CLK_UTMIPLL_CLKOUT48			251
+#define TEGRA238_CLK_UTMIPLL_CLKOUT480			252
+#define TEGRA238_CLK_UTMIP_PLL				253
+#define TEGRA238_CLK_VIC				254
+#define TEGRA238_CLK_VPLL0				255
+#define TEGRA238_CLK_VPLL0_REF				256
+#define TEGRA238_CLK_VPLL1				257
+#define TEGRA238_CLK_XUSB_CORE_DEV			258
+#define TEGRA238_CLK_XUSB_CORE_HOST			259
+#define TEGRA238_CLK_XUSB_CORE_MUX			260
+#define TEGRA238_CLK_XUSB_CORE_SS			261
+#define TEGRA238_CLK_XUSB_FALCON			262
+#define TEGRA238_CLK_XUSB_FALCON_HOST			263
+#define TEGRA238_CLK_XUSB_FALCON_SS			264
+#define TEGRA238_CLK_XUSB_FS				265
+#define TEGRA238_CLK_XUSB_FS_DEV			266
+#define TEGRA238_CLK_XUSB_FS_HOST			267
+#define TEGRA238_CLK_XUSB_HS_HSICP			268
+#define TEGRA238_CLK_XUSB_SS				269
+#define TEGRA238_CLK_XUSB_SS_DEV			270
+#define TEGRA238_CLK_XUSB_SS_SUPERSPEED			271
+
+#endif /* DT_BINDINGS_CLOCK_NVIDIA_TEGRA238_H */
-- 
2.43.0


^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH v2 2/4] firmware: tegra: bpmp: Add Tegra238 support
  2026-10-28 15:49 [PATCH v2 0/4] Add Tegra238 BPMP support and fix stale EMC clock rate Johnny Liu
  2026-10-28 15:49 ` [PATCH v2 1/4] dt-bindings: firmware: tegra186-bpmp: Add Tegra238 BPMP Johnny Liu
@ 2026-10-28 15:49 ` Johnny Liu
  2026-10-28 15:49 ` [PATCH v2 3/4] firmware: tegra: bpmp: Add per-SoC EMC clock ID Johnny Liu
  2026-10-28 15:50 ` [PATCH v2 4/4] clk: tegra: bpmp: Do not cache the EMC clock rate Johnny Liu
  3 siblings, 0 replies; 5+ messages in thread
From: Johnny Liu @ 2026-10-28 15:49 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Thierry Reding,
	Jonathan Hunter, Prashant Gaikwad, Stephen Boyd, Brian Masney,
	Jerome Brunet, Douglas Anderson, Aniruddha Rao, devicetree,
	linux-tegra, linux-kernel, linux-clk
  Cc: Johnny Liu

The "nvidia,tegra186-bpmp" compatible and tegra186_soc data are shared by
Tegra186, Tegra194, Tegra234 and Tegra264. Tegra238 has its own BPMP
compatible, so give Tegra234, Tegra238 and Tegra264 dedicated SoC data
selected through their specific compatibles, built on top of a common
TEGRA186_BPMP_SOC_COMMON initializer. This allows chip specific
properties to be described in the SoC data. Tegra186 and Tegra194 keep
using tegra186_soc.

Also build bpmp-tegra186.o and the shared match table for
CONFIG_ARCH_TEGRA_238_SOC, so that a Tegra238-only configuration binds
the driver.

Signed-off-by: Johnny Liu <johnliu@nvidia.com>
---
 drivers/firmware/tegra/Makefile |  1 +
 drivers/firmware/tegra/bpmp.c   | 54 ++++++++++++++++++++++-----------
 2 files changed, 38 insertions(+), 17 deletions(-)

diff --git a/drivers/firmware/tegra/Makefile b/drivers/firmware/tegra/Makefile
index 97f7a5db9d0a..21e87f3afffe 100644
--- a/drivers/firmware/tegra/Makefile
+++ b/drivers/firmware/tegra/Makefile
@@ -4,6 +4,7 @@ tegra-bpmp-$(CONFIG_ARCH_TEGRA_210_SOC)	+= bpmp-tegra210.o
 tegra-bpmp-$(CONFIG_ARCH_TEGRA_186_SOC)	+= bpmp-tegra186.o
 tegra-bpmp-$(CONFIG_ARCH_TEGRA_194_SOC)	+= bpmp-tegra186.o
 tegra-bpmp-$(CONFIG_ARCH_TEGRA_234_SOC)	+= bpmp-tegra186.o
+tegra-bpmp-$(CONFIG_ARCH_TEGRA_238_SOC)	+= bpmp-tegra186.o
 tegra-bpmp-$(CONFIG_ARCH_TEGRA_264_SOC)	+= bpmp-tegra186.o
 tegra-bpmp-$(CONFIG_DEBUG_FS)	+= bpmp-debugfs.o
 tegra-bpmp-$(CONFIG_SYSFS)	+= bpmp-sysfs.o
diff --git a/drivers/firmware/tegra/bpmp.c b/drivers/firmware/tegra/bpmp.c
index d3508e98e338..beeb385870f5 100644
--- a/drivers/firmware/tegra/bpmp.c
+++ b/drivers/firmware/tegra/bpmp.c
@@ -1131,25 +1131,41 @@ static const struct dev_pm_ops tegra_bpmp_pm_ops = {
 #if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC) || \
     IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \
     IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC) || \
+    IS_ENABLED(CONFIG_ARCH_TEGRA_238_SOC) || \
     IS_ENABLED(CONFIG_ARCH_TEGRA_264_SOC)
+#define TEGRA186_BPMP_SOC_COMMON					\
+	.channels = {							\
+		.cpu_tx = {						\
+			.offset = 3,					\
+			.timeout = 60 * USEC_PER_SEC,			\
+		},							\
+		.thread = {						\
+			.offset = 0,					\
+			.count = 3,					\
+			.timeout = 600 * USEC_PER_SEC,			\
+		},							\
+		.cpu_rx = {						\
+			.offset = 13,					\
+			.timeout = 0,					\
+		},							\
+	},								\
+	.ops = &tegra186_bpmp_ops,					\
+	.num_resets = 193
+
 static const struct tegra_bpmp_soc tegra186_soc = {
-	.channels = {
-		.cpu_tx = {
-			.offset = 3,
-			.timeout = 60 * USEC_PER_SEC,
-		},
-		.thread = {
-			.offset = 0,
-			.count = 3,
-			.timeout = 600 * USEC_PER_SEC,
-		},
-		.cpu_rx = {
-			.offset = 13,
-			.timeout = 0,
-		},
-	},
-	.ops = &tegra186_bpmp_ops,
-	.num_resets = 193,
+	TEGRA186_BPMP_SOC_COMMON,
+};
+
+static const struct tegra_bpmp_soc tegra234_soc = {
+	TEGRA186_BPMP_SOC_COMMON,
+};
+
+static const struct tegra_bpmp_soc tegra238_soc = {
+	TEGRA186_BPMP_SOC_COMMON,
+};
+
+static const struct tegra_bpmp_soc tegra264_soc = {
+	TEGRA186_BPMP_SOC_COMMON,
 };
 #endif
 
@@ -1180,8 +1196,12 @@ static const struct of_device_id tegra_bpmp_match[] = {
 #if IS_ENABLED(CONFIG_ARCH_TEGRA_186_SOC) || \
     IS_ENABLED(CONFIG_ARCH_TEGRA_194_SOC) || \
     IS_ENABLED(CONFIG_ARCH_TEGRA_234_SOC) || \
+    IS_ENABLED(CONFIG_ARCH_TEGRA_238_SOC) || \
     IS_ENABLED(CONFIG_ARCH_TEGRA_264_SOC)
 	{ .compatible = "nvidia,tegra186-bpmp", .data = &tegra186_soc },
+	{ .compatible = "nvidia,tegra234-bpmp", .data = &tegra234_soc },
+	{ .compatible = "nvidia,tegra238-bpmp", .data = &tegra238_soc },
+	{ .compatible = "nvidia,tegra264-bpmp", .data = &tegra264_soc },
 #endif
 #if IS_ENABLED(CONFIG_ARCH_TEGRA_210_SOC)
 	{ .compatible = "nvidia,tegra210-bpmp", .data = &tegra210_soc },
-- 
2.43.0


^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH v2 3/4] firmware: tegra: bpmp: Add per-SoC EMC clock ID
  2026-10-28 15:49 [PATCH v2 0/4] Add Tegra238 BPMP support and fix stale EMC clock rate Johnny Liu
  2026-10-28 15:49 ` [PATCH v2 1/4] dt-bindings: firmware: tegra186-bpmp: Add Tegra238 BPMP Johnny Liu
  2026-10-28 15:49 ` [PATCH v2 2/4] firmware: tegra: bpmp: Add Tegra238 support Johnny Liu
@ 2026-10-28 15:49 ` Johnny Liu
  2026-10-28 15:50 ` [PATCH v2 4/4] clk: tegra: bpmp: Do not cache the EMC clock rate Johnny Liu
  3 siblings, 0 replies; 5+ messages in thread
From: Johnny Liu @ 2026-10-28 15:49 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Thierry Reding,
	Jonathan Hunter, Prashant Gaikwad, Stephen Boyd, Brian Masney,
	Jerome Brunet, Douglas Anderson, Aniruddha Rao, devicetree,
	linux-tegra, linux-kernel, linux-clk
  Cc: Johnny Liu

The EMC clock ID differs per chip (TEGRA234_CLK_EMC=31,
TEGRA238_CLK_EMC=43, TEGRA264_CLK_EMC=290).

Add an emc_clk_id field to struct tegra_bpmp_soc and set it for
Tegra234, Tegra238 and Tegra264. Tegra186 and Tegra194 have no EMC clock
ID and leave it unset.

Signed-off-by: Johnny Liu <johnliu@nvidia.com>
---
 drivers/firmware/tegra/bpmp.c | 7 +++++++
 include/soc/tegra/bpmp.h      | 1 +
 2 files changed, 8 insertions(+)

diff --git a/drivers/firmware/tegra/bpmp.c b/drivers/firmware/tegra/bpmp.c
index beeb385870f5..06da888535dc 100644
--- a/drivers/firmware/tegra/bpmp.c
+++ b/drivers/firmware/tegra/bpmp.c
@@ -21,6 +21,10 @@
 #include <soc/tegra/bpmp-abi.h>
 #include <soc/tegra/ivc.h>
 
+#include <dt-bindings/clock/nvidia,tegra238.h>
+#include <dt-bindings/clock/nvidia,tegra264.h>
+#include <dt-bindings/clock/tegra234-clock.h>
+
 #include "bpmp-private.h"
 
 #define MSG_ACK		BIT(0)
@@ -1158,14 +1162,17 @@ static const struct tegra_bpmp_soc tegra186_soc = {
 
 static const struct tegra_bpmp_soc tegra234_soc = {
 	TEGRA186_BPMP_SOC_COMMON,
+	.emc_clk_id = TEGRA234_CLK_EMC,
 };
 
 static const struct tegra_bpmp_soc tegra238_soc = {
 	TEGRA186_BPMP_SOC_COMMON,
+	.emc_clk_id = TEGRA238_CLK_EMC,
 };
 
 static const struct tegra_bpmp_soc tegra264_soc = {
 	TEGRA186_BPMP_SOC_COMMON,
+	.emc_clk_id = TEGRA264_CLK_EMC,
 };
 #endif
 
diff --git a/include/soc/tegra/bpmp.h b/include/soc/tegra/bpmp.h
index f55db918ccb1..40e2db8e69cc 100644
--- a/include/soc/tegra/bpmp.h
+++ b/include/soc/tegra/bpmp.h
@@ -31,6 +31,7 @@ struct tegra_bpmp_soc {
 	const struct tegra_bpmp_ops *ops;
 	const struct tegra_bpmp_mbwt_soc *mbwt;
 	unsigned int num_resets;
+	unsigned int emc_clk_id;
 };
 
 struct tegra_bpmp_mb_data {
-- 
2.43.0


^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH v2 4/4] clk: tegra: bpmp: Do not cache the EMC clock rate
  2026-10-28 15:49 [PATCH v2 0/4] Add Tegra238 BPMP support and fix stale EMC clock rate Johnny Liu
                   ` (2 preceding siblings ...)
  2026-10-28 15:49 ` [PATCH v2 3/4] firmware: tegra: bpmp: Add per-SoC EMC clock ID Johnny Liu
@ 2026-10-28 15:50 ` Johnny Liu
  3 siblings, 0 replies; 5+ messages in thread
From: Johnny Liu @ 2026-10-28 15:50 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Thierry Reding,
	Jonathan Hunter, Prashant Gaikwad, Stephen Boyd, Brian Masney,
	Jerome Brunet, Douglas Anderson, Aniruddha Rao, devicetree,
	linux-tegra, linux-kernel, linux-clk
  Cc: Johnny Liu

EMC clock scaling is managed by the BPMP itself without kernel
involvement. When the rate changes on the BPMP side, clk_get_rate() on
the kernel side returns the stale value cached by the common clock
framework instead of the rate programmed by the BPMP.

Set CLK_GET_RATE_NOCACHE on the EMC clock, identified by the per-SoC
emc_clk_id from the BPMP SoC data, so that rate queries are forwarded to
the BPMP.

Signed-off-by: Johnny Liu <johnliu@nvidia.com>
---
 drivers/clk/tegra/clk-bpmp.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/drivers/clk/tegra/clk-bpmp.c b/drivers/clk/tegra/clk-bpmp.c
index 067a8555c4e7..ddbc528cf93a 100644
--- a/drivers/clk/tegra/clk-bpmp.c
+++ b/drivers/clk/tegra/clk-bpmp.c
@@ -588,6 +588,9 @@ tegra_bpmp_clk_register(struct tegra_bpmp *bpmp,
 
 	init.parent_names = parents;
 
+	if (bpmp->soc->emc_clk_id && info->id == bpmp->soc->emc_clk_id)
+		init.flags = CLK_GET_RATE_NOCACHE;
+
 	err = devm_clk_hw_register(bpmp->dev, &clk->hw);
 
 	kfree(parents);
-- 
2.43.0


^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2026-10-28 16:06 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2026-10-28 15:49 [PATCH v2 0/4] Add Tegra238 BPMP support and fix stale EMC clock rate Johnny Liu
2026-10-28 15:49 ` [PATCH v2 1/4] dt-bindings: firmware: tegra186-bpmp: Add Tegra238 BPMP Johnny Liu
2026-10-28 15:49 ` [PATCH v2 2/4] firmware: tegra: bpmp: Add Tegra238 support Johnny Liu
2026-10-28 15:49 ` [PATCH v2 3/4] firmware: tegra: bpmp: Add per-SoC EMC clock ID Johnny Liu
2026-10-28 15:50 ` [PATCH v2 4/4] clk: tegra: bpmp: Do not cache the EMC clock rate Johnny Liu

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