[for-next 1/1] RDMA/ionic: Use a linear QID space when udma_shift is zero

[Abhijit Gangurde <abhijit.gangurde@amd.com>]

Firmware reports udma_shift as the log2 of the number of queues in
a queue group. A value of zero means the queues are not striped
across two UDMAs, so the QID space is linear and the device has one UDMA.

The interleaved bitid/qid transform treats bit 0 as the UDMA selector
when the group shift is zero. QID 1 then becomes bitid
1 << half_qid_shift, and freeing that QID releases the wrong allocator
index. Skip the transform and select one UDMA so QP and CQ allocation
uses the QID directly.

Fixes: e8521822c733 ("RDMA/ionic: Register device ops for control path")
Reported-by: Keith Lucas <keith.lucas@oracle.com>
Link: https://lore.kernel.org/r/20261021161651.4020222-1-haakon.bugge@oracle.com
Cc: stable@vger.kernel.org # 6.18
Signed-off-by: Abhijit Gangurde <abhijit.gangurde@amd.com>
---
 drivers/infiniband/hw/ionic/ionic_lif_cfg.c |  2 +-
 drivers/infiniband/hw/ionic/ionic_res.h     | 23 ++++++++++++++-------
 2 files changed, 17 insertions(+), 8 deletions(-)

diff --git a/drivers/infiniband/hw/ionic/ionic_lif_cfg.c b/drivers/infiniband/hw/ionic/ionic_lif_cfg.c
index 66cee57442e7..a3ee86b56037 100644
--- a/drivers/infiniband/hw/ionic/ionic_lif_cfg.c
+++ b/drivers/infiniband/hw/ionic/ionic_lif_cfg.c
@@ -84,7 +84,7 @@ void ionic_fill_lif_cfg(struct ionic_lif *lif, struct ionic_lif_cfg *cfg)
 	cfg->cq_qtype = ident->rdma.cq_qtype.qtype;
 	cfg->eq_qtype = ident->rdma.eq_qtype.qtype;
 	cfg->udma_qgrp_shift = ident->rdma.udma_shift;
-	cfg->udma_count = 2;
+	cfg->udma_count = cfg->udma_qgrp_shift ? 2 : 1;
 
 	cfg->max_stride = ident->rdma.max_stride;
 	cfg->rcq_sign_bit = ident->rdma.rcq_sign_bit;
diff --git a/drivers/infiniband/hw/ionic/ionic_res.h b/drivers/infiniband/hw/ionic/ionic_res.h
index 46c8c584bd9a..c480865dced5 100644
--- a/drivers/infiniband/hw/ionic/ionic_res.h
+++ b/drivers/infiniband/hw/ionic/ionic_res.h
@@ -125,10 +125,14 @@ static inline void ionic_resid_put(struct ionic_resid_bits *resid, int id)
 static inline u32 ionic_bitid_to_qid(u32 bitid, u8 qgrp_shift,
 				     u8 half_qid_shift)
 {
-	u32 udma_bit =
-		(bitid & BIT(half_qid_shift)) >> (half_qid_shift - qgrp_shift);
-	u32 grp_bits = (bitid & GENMASK(half_qid_shift - 1, qgrp_shift)) << 1;
-	u32 idx_bits = bitid & (BIT(qgrp_shift) - 1);
+	u32 udma_bit, grp_bits, idx_bits;
+
+	if (!qgrp_shift)
+		return bitid;
+
+	udma_bit = (bitid & BIT(half_qid_shift)) >> (half_qid_shift - qgrp_shift);
+	grp_bits = (bitid & GENMASK(half_qid_shift - 1, qgrp_shift)) << 1;
+	idx_bits = bitid & (BIT(qgrp_shift) - 1);
 
 	return grp_bits | udma_bit | idx_bits;
 }
@@ -145,9 +149,14 @@ static inline u32 ionic_bitid_to_qid(u32 bitid, u8 qgrp_shift,
  */
 static inline u32 ionic_qid_to_bitid(u32 qid, u8 qgrp_shift, u8 half_qid_shift)
 {
-	u32 udma_bit = (qid & BIT(qgrp_shift)) << (half_qid_shift - qgrp_shift);
-	u32 grp_bits = (qid & GENMASK(half_qid_shift, qgrp_shift + 1)) >> 1;
-	u32 idx_bits = qid & (BIT(qgrp_shift) - 1);
+	u32 udma_bit, grp_bits, idx_bits;
+
+	if (!qgrp_shift)
+		return qid;
+
+	udma_bit = (qid & BIT(qgrp_shift)) << (half_qid_shift - qgrp_shift);
+	grp_bits = (qid & GENMASK(half_qid_shift, qgrp_shift + 1)) >> 1;
+	idx_bits = qid & (BIT(qgrp_shift) - 1);
 
 	return udma_bit | grp_bits | idx_bits;
 }
-- 
2.43.0