From: Chunyan Zhang <chunyan.zhang@linux.spacemit.com>
To: Yixun Lan <dlan@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Paul Walmsley <pjw@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Alexandre Ghiti <alex@ghiti.fr>
Cc: spacemit@lists.linux.dev, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org,
Chunyan Zhang <zhang.lyra@gmail.com>,
Troy Mitchell <troy.mitchell@linux.spacemit.com>,
linux-kernel@vger.kernel.org
Subject: [PATCH] riscv: dts: spacemit: k3: add USB3 port A (DRD) nodes
Date: Fri, 30 Oct 2026 17:40:24 +0800 [thread overview]
Message-ID: <20261030094024.3226356-1-chunyan.zhang@linux.spacemit.com> (raw)
Describe the DWC3 controller and its USB 2.0 PHY for USB3 port A
of the K3 SoC.
Only the U2 lane is described: Port A's SuperSpeed PHY has no driver
yet, so the port runs at high-speed (maximum-speed = "high-speed").
Enable USB3 port A with dr_mode = "peripheral", so it can be used as
a USB device.
Signed-off-by: Chunyan Zhang <chunyan.zhang@linux.spacemit.com>
---
arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 9 ++++++
arch/riscv/boot/dts/spacemit/k3.dtsi | 30 ++++++++++++++++++++
2 files changed, 39 insertions(+)
diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
index b084a35aa00e..74d4fdf9e405 100644
--- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
+++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts
@@ -323,6 +323,15 @@ &usb2_phy {
status = "okay";
};
+&usb3a_u2phy {
+ status = "okay";
+};
+
+&usb3a {
+ dr_mode = "peripheral";
+ status = "okay";
+};
+
&usb3d_u2phy {
status = "okay";
};
diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi
index c3f2dce0969c..220dfe29bb78 100644
--- a/arch/riscv/boot/dts/spacemit/k3.dtsi
+++ b/arch/riscv/boot/dts/spacemit/k3.dtsi
@@ -630,6 +630,36 @@ gmac2_axi_setup: stmmac-axi-config {
};
};
+ usb3a: usb@cad00000 {
+ compatible = "spacemit,k3-dwc3";
+ reg = <0x0 0xcad00000 0x0 0x10000>;
+ interrupts = <118 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-parent = <&saplic>;
+ clocks = <&syscon_apmu CLK_APMU_USB3_PORTA_BUS>;
+ clock-names = "usbdrd30";
+ resets = <&syscon_apmu RESET_APMU_USB3_A_AHB>,
+ <&syscon_apmu RESET_APMU_USB3_A_VCC>,
+ <&syscon_apmu RESET_APMU_USB3_A_PHY>;
+ reset-names = "ahb", "vcc", "phy";
+ phys = <&usb3a_u2phy>;
+ phy-names = "usb2-phy";
+ phy_type = "utmi";
+ snps,dis_enblslpm_quirk;
+ snps,dis_u2_susphy_quirk;
+ snps,dis-del-phy-power-chg-quirk;
+ snps,dis-tx-ipgap-linecheck-quirk;
+ maximum-speed = "high-speed";
+ status = "disabled";
+ };
+
+ usb3a_u2phy: phy@cad20000 {
+ compatible = "spacemit,k3-usb2-phy";
+ reg = <0x0 0xcad20000 0x0 0x200>;
+ clocks = <&syscon_apmu CLK_APMU_USB3_PORTA_BUS>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
pdma: dma-controller@d4000000 {
compatible = "spacemit,k3-pdma";
reg = <0x0 0xd4000000 0x0 0x4000>;
--
2.34.1
reply other threads:[~2026-10-30 9:41 UTC|newest]
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