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* [PATCH 00/23] Subject: [PATCH net-next 00/23] net/hpe: add HPE Slingshot NIC drivers
@ 2026-10-30 20:58 Doug Ledford
  2026-10-30 20:58 ` [PATCH 01/23] net: hpe: ss1: add the Cassini headers Doug Ledford
                   ` (23 more replies)
  0 siblings, 24 replies; 25+ messages in thread
From: Doug Ledford @ 2026-10-30 20:58 UTC (permalink / raw)
  To: Slingshot Open Source Team, Nathan Chancellor, Nicolas Schier,
	Richard Cochran, Andrew Lunn, David S. Miller, Eric Dumazet,
	Jakub Kicinski, Paolo Abeni, Sumit Semwal, Christian König,
	Guenter Roeck
  Cc: linux-kernel, netdev, linux-kbuild, Doug Ledford, Sandeep Bhoot,
	Iraimani P, Mamila Santosh

To: Slingshot Open Source Team <slingshot-os-team@groups.ext.hpe.com>
To: Nathan Chancellor <nathan@kernel.org>
To: Nicolas Schier <nsc@kernel.org>
To: Richard Cochran <richardcochran@gmail.com>
To: Andrew Lunn <andrew+netdev@lunn.ch>
To: "David S. Miller" <davem@davemloft.net>
To: Eric Dumazet <edumazet@kernel.org>
To: Jakub Kicinski <kuba@kernel.org>
To: Paolo Abeni <pabeni@redhat.com>
To: Sumit Semwal <sumit.semwal@linaro.org>
To: Christian König <christian.koenig@amd.com>
To: Guenter Roeck <linux@roeck-us.net>
Cc: linux-kernel@vger.kernel.org
Cc: netdev@vger.kernel.org
Cc: linux-kbuild@vger.kernel.org

This series adds the Linux drivers for the HPE Slingshot Cassini network
interface controller, the NIC used in HPE Slingshot high-performance
computing systems (Cassini 1 with 200 Gb/s links and Cassini 2 with
400 Gb/s links).

The hardware is reached through three layered drivers:

 - cxi-sbl (Slingshot Base Link): SerDes, PML, link state machine and
   media handling for 200 Gb/s links (patches 2-8)
 - cxi-sl (Slingshot Link): the link layer for 400 Gb/s links, with its
   control layer, media and cable handling and sysfs interface
   (patches 9-15)
 - cxi-ss1 (Cassini core): the PCI driver that owns the device, its
   address translation, event and command queues, communication
   profiles, resource groups, QoS and services, plus cxi-eth, an
   Ethernet personality on top of it (patches 1 and 16-22)

Patch 23 adds Kconfig, Makefile and MAINTAINERS. Until that patch the
new driver sources are not compiled; only the new UAPI headers are
built, by the UAPI header test.

The core driver exposes an in-kernel CXI interface (cxi.h) to client
drivers through the auxiliary bus. The Ethernet personality in this
series is one such client; the RDMA driver is another.

Series size
-----------

We know this is longer than the usual netdev limit of about 15
patches. The three drivers depend on each other: cxi-ss1 selects
cxi-sbl or cxi-sl at run time according to the NIC generation, and a
single Kconfig/Makefile patch enables all three. Posting only part of
them would add code that cannot be built or used. Within the series,
each patch adds one layer so that it can be reviewed on its own. If
you would prefer a different split, for example the two link drivers
first and the core driver after them, please tell us and we will
restructure V2.

Driver Structure
----------------

The main reason for sending this patchset now, given that there are
still a few issues unresolved and over 16,000 checkpatch warnings for
line length (we're working through the tools that generate these
files to fix that up) is to get input on several overall design issues:

1) We are an Ethernet driver structured over a Portals 4.0 API
hardware device.  That means that our Ethernet implementation
is complex, much like combined Ethernet/RoCE devices.  We have
chosen, as a design decision, to keep the driver mostly in one
place and the RDMA portion of the driver is just a thin layer
that routes things like memory registrations and what not to our
Ethernet driver core.  In addition, the Ethernet support needs
many of those same things anyway, and the driver's RDMA aspect
uses a plain socket connection to the fabric manager in order
to get the configuration it needs to run.

It is possible that the driver could be re-architected to be an RDMA
driver first, and just provide a thin shim layer in the net/ethernet
area instead.

This would be considerable work, and very likely result in the sl
and sbl drivers still belonging more in the netdev area (or maybe
the phy subsystem, but I think these drivers are more than your
generic phy) so we didn't pre-emptively undertake that task.

In addition, moving entirely over to the RDMA subsystem would invert
the normal order of bring up between shared ethernet/RDMA devices.
One of our engineers opined that such a suggestion would be anathema
to the netdev community.

2) Our sysfs usage.  We have extensive elements that we populate
in sysfs related to the hardware.  Initial comments were that we
were likely over-using/abusing sysfs, so we have already removed
the sysfs telemetry support we used to have, reducing our sysfs
elements by 1,925 items (those items are now accessed via the
RDMA stack's hw counters support).  There are still a significant
number of sysfs elements exported, especially from the sl driver.

Dependencies
------------

This series has no dependencies and applies to net-next.

Two later submissions to linux-rdma depend on it:

 - "RDMA/cxi: add the HPE Cassini verbs driver" (kernel, linux-rdma),
   which also depends on the UET RDMA core series
   [PATCH rdma-next v2 00/13] RDMA/core: Ultra Ethernet transport verbs
   https://lore.kernel.org/linux-rdma/20261019-uet-ib-core-v2-0-8bd654f25370@broadcom.com/T/#t
 - the cxiverbs rdma-core provider (rdma-core pull request), which also
   depends on the UET rdma-core series
   libibverbs: Ultra Ethernet reliable unconnected verbs
   https://github.com/linux-rdma/rdma-core/pull/1829

Known open issues
-----------------

Every patch with a known unresolved issue says so in its commit
message. In summary:

 - SR-IOV: patches 1, 16, 17, 19, 20, 21 and 22 carry virtual-function
   code from an older, incomplete version of the Cassini SR-IOV support.
   V2 will include the updated SR-IOV implementation, so please ignore
   issues in the VF paths for now. Specific known VF issues are listed
   in patches 17 and 19.
 - Patch 11 (SL core link state machines):
   sl_core_hw_pcs_keep_all_lanes_active_set() is an empty hook with a
   TODO. It belongs to graceful lane-degrade support, which SL does not
   implement yet.
 - Patch 14 (SL sysfs): about 378 SL attributes (and 23 in cxi-ss1) have
   no Documentation/ABI entries yet. We are working with the hardware
   engineers to decide which attributes are stable interfaces and which
   belong in debugfs; the documentation will be in V2.
 - Patch 17 (datapath, open hardware question): DMAC transfers are
   bounded, and the engine is disabled and its interrupt drained before
   the completion descriptor is read. We are confirming with the
   hardware engineers that clearing C_PI_CFG_DMAC ENABLE guarantees no
   further host writes. Current callers keep their DMA buffers for the
   lifetime of the device.

checkpatch
----------

checkpatch --strict (100 columns) still reports issues in most patches;
each patch lists its own types and counts. Most come from the generated
hardware headers in patches 1 and 9 (for example, 19058 LEADING_SPACE
warnings in patch 9 alone) and from long lines. This code is also
maintained in internal HPE repositories, from which the generated
headers come, so the remaining fixes need coordination with those
repositories and will be made in V2. The 25 remaining ERRORs are
SPACING, CODE_INDENT, COMPLEX_MACRO and FLEXIBLE_ARRAY in the header
patches 1, 2, 9 and 16.  Those issues will be addressed by humans
with actual thought and coordinated between the internal repos and
this submission.

Some UAPI headers in this series (for example sbl-abi.h) also have
copies in out-of-tree HPE packages; those copies will be synchronized
with this series over time.

Review and testing
------------------

Before posting, the series was reviewed with the Sashiko AI code
review tool and checkpatch. All valid findings are fixed, except the
open items listed above.

Tool use: GitHub Copilot, an AI coding assistant, was used under our
direction to write many of the review fixes, to fold them into these
patches, to write commit messages and to run the build and hardware
tests. Every change was reviewed by the submitter, who takes
responsibility for it as for any other patch.

 - every patch builds incrementally, without compiler warnings, with an
   x86_64 configuration that enables these drivers and the UAPI header
   test
 - with exactly this series, the cxiverbs series and the rdma-core
   provider, booted on two Cassini 2 x86_64 nodes, the complete stack
   passed a full test matrix on both nodes: module identity and
   signatures, link bring-up and a 60-second link-stability check,
   the rdma-core Python suite (434 tests; tests that need features
   this device lacks are skipped), resource and VNI isolation tests
   in default and indexed addressing modes, including wrong-VNI
   rejection, privileged and unprivileged CSR access tests, and 36
   two-node ping-pong and RMA traffic cases (polling and event modes)
   in each direction, 72 in total. Native NIC resource accounting was
   identical before and after the traffic, and the kernel logs had no
   WARN, BUG or oops reports and no module load errors.
 - targeted user space models of the functions changed by the review
   fixes pass under AddressSanitizer and UndefinedBehaviorSanitizer.

Co-developed by Sandeep Bhoot, Mamila Santosh and Iraimani P, as shown
by the trailers on each patch.

Doug Ledford (23):
  net: hpe: ss1: add the Cassini headers
  net: hpe: sbl: add the Slingshot Base Link headers
  net: hpe: sbl: add the core instance and configuration layer
  net: hpe: sbl: add the SerDes layer
  net: hpe: sbl: add the PML link layer
  net: hpe: sbl: add link state management
  net: hpe: sbl: add the SBM serial bus layer
  net: hpe: sbl: add media, FEC and counter support
  net: hpe: sl: add the Slingshot Link headers
  net: hpe: sl: add the module entry points
  net: hpe: sl: add the core link state machines
  net: hpe: sl: add the control layer
  net: hpe: sl: add media and cable handling
  net: hpe: sl: add the sysfs interface
  net: hpe: sl: add the NIC binding and logging helpers
  net: hpe: ss1: add the Cassini core device layer
  net: hpe: ss1: add the datapath and memory translation layers
  net: hpe: ss1: add the link layer glue
  net: hpe: ss1: add SR-IOV support
  net: hpe: ss1: add the CXI core interfaces
  net: hpe: ss1: add resource groups, QoS and services
  net: hpe: ss1: add the Ethernet personality
  net: hpe: wire up the Slingshot NIC drivers

 416 files changed, 185139 insertions(+)

Signed-off-by: Doug Ledford <doug.ledford@hpe.com>
---
Doug Ledford (23):
      net: hpe: ss1: add the Cassini headers
      net: hpe: sbl: add the Slingshot Base Link headers
      net: hpe: sbl: add the core instance and configuration layer
      net: hpe: sbl: add the SerDes layer
      net: hpe: sbl: add the PML link layer
      net: hpe: sbl: add link state management
      net: hpe: sbl: add the SBM serial bus layer
      net: hpe: sbl: add media, FEC and counter support
      net: hpe: sl: add the Slingshot Link headers
      net: hpe: sl: add the module entry points
      net: hpe: sl: add the core link state machines
      net: hpe: sl: add the control layer
      net: hpe: sl: add media and cable handling
      net: hpe: sl: add the sysfs interface
      net: hpe: sl: add the NIC binding and logging helpers
      net: hpe: ss1: add the Cassini core device layer
      net: hpe: ss1: add the datapath and memory translation layers
      net: hpe: ss1: add the link layer glue
      net: hpe: ss1: add SR-IOV support
      net: hpe: ss1: add the CXI core interfaces
      net: hpe: ss1: add resource groups, QoS and services
      net: hpe: ss1: add the Ethernet personality
      net: hpe: wire up the Slingshot NIC drivers

 MAINTAINERS                                        |     7 +
 drivers/net/ethernet/Kconfig                       |     1 +
 drivers/net/ethernet/Makefile                      |     1 +
 drivers/net/ethernet/hpe/Kconfig                   |    26 +
 drivers/net/ethernet/hpe/Makefile                  |     8 +
 drivers/net/ethernet/hpe/sbl/Kconfig               |    15 +
 drivers/net/ethernet/hpe/sbl/Makefile              |    21 +
 drivers/net/ethernet/hpe/sbl/sbl_config_list.h     |    61 +
 drivers/net/ethernet/hpe/sbl/sbl_constants.h       |   352 +
 drivers/net/ethernet/hpe/sbl/sbl_counters.c        |   137 +
 drivers/net/ethernet/hpe/sbl/sbl_debug.c           |   167 +
 drivers/net/ethernet/hpe/sbl/sbl_fec.c             |   971 ++
 drivers/net/ethernet/hpe/sbl/sbl_fec_nic.c         |    36 +
 drivers/net/ethernet/hpe/sbl/sbl_inst.c            |   529 +
 drivers/net/ethernet/hpe/sbl/sbl_inst_nic.c        |    70 +
 drivers/net/ethernet/hpe/sbl/sbl_internal.c        |    23 +
 drivers/net/ethernet/hpe/sbl/sbl_internal.h        |   279 +
 drivers/net/ethernet/hpe/sbl/sbl_link.c            |  1739 +++
 drivers/net/ethernet/hpe/sbl/sbl_link.h            |    44 +
 drivers/net/ethernet/hpe/sbl/sbl_link_an.c         |  1010 ++
 drivers/net/ethernet/hpe/sbl/sbl_link_an_nic.c     |   111 +
 drivers/net/ethernet/hpe/sbl/sbl_link_nic.c        |   196 +
 drivers/net/ethernet/hpe/sbl/sbl_media.c           |   482 +
 drivers/net/ethernet/hpe/sbl/sbl_media_nic.c       |    47 +
 drivers/net/ethernet/hpe/sbl/sbl_misc.c            |   505 +
 drivers/net/ethernet/hpe/sbl/sbl_module_nic.c      |   132 +
 drivers/net/ethernet/hpe/sbl/sbl_platform.h        |    35 +
 drivers/net/ethernet/hpe/sbl/sbl_pml.c             |   787 +
 drivers/net/ethernet/hpe/sbl/sbl_pml_fn.h          |   132 +
 drivers/net/ethernet/hpe/sbl/sbl_pml_llr.c         |   736 +
 drivers/net/ethernet/hpe/sbl/sbl_pml_llr_nic.c     |    34 +
 drivers/net/ethernet/hpe/sbl/sbl_pml_mac.c         |   220 +
 drivers/net/ethernet/hpe/sbl/sbl_pml_pcs.c         |  1085 ++
 drivers/net/ethernet/hpe/sbl/sbl_pml_pcs_nic.c     |    53 +
 drivers/net/ethernet/hpe/sbl/sbl_pml_serdes_op.c   |   145 +
 drivers/net/ethernet/hpe/sbl/sbl_sbm.h             |    73 +
 drivers/net/ethernet/hpe/sbl/sbl_sbm_serdes.c      |  1114 ++
 drivers/net/ethernet/hpe/sbl/sbl_sbm_serdes.h      |   152 +
 drivers/net/ethernet/hpe/sbl/sbl_sbm_serdes_nic.c  |   138 +
 drivers/net/ethernet/hpe/sbl/sbl_serdes.c          |  1117 ++
 drivers/net/ethernet/hpe/sbl/sbl_serdes.h          |    94 +
 drivers/net/ethernet/hpe/sbl/sbl_serdes_fn.c       |  4310 ++++++
 drivers/net/ethernet/hpe/sbl/sbl_serdes_fn.h       |   151 +
 drivers/net/ethernet/hpe/sbl/sbl_serdes_map.h      |    10 +
 drivers/net/ethernet/hpe/sbl/sbl_test.c            |   406 +
 drivers/net/ethernet/hpe/sbl/sbl_timers.c          |   228 +
 drivers/net/ethernet/hpe/sl/Kconfig                |    15 +
 drivers/net/ethernet/hpe/sl/Makefile               |   140 +
 .../net/ethernet/hpe/sl/core/base/sl_core_log.h    |    70 +
 .../ethernet/hpe/sl/core/base/sl_core_timer_link.c |   109 +
 .../ethernet/hpe/sl/core/base/sl_core_timer_link.h |    41 +
 .../ethernet/hpe/sl/core/base/sl_core_timer_llr.c  |    84 +
 .../ethernet/hpe/sl/core/base/sl_core_timer_llr.h  |    37 +
 .../ethernet/hpe/sl/core/base/sl_core_work_link.h  |    41 +
 .../ethernet/hpe/sl/core/base/sl_core_work_llr.h   |    19 +
 .../hpe/sl/core/data/nic/sl_core_data_link.c       |    11 +
 .../hpe/sl/core/data/nic/sl_core_data_mac.c        |    11 +
 .../ethernet/hpe/sl/core/data/sl_core_data_ldev.c  |   122 +
 .../ethernet/hpe/sl/core/data/sl_core_data_ldev.h  |    19 +
 .../ethernet/hpe/sl/core/data/sl_core_data_lgrp.c  |   351 +
 .../ethernet/hpe/sl/core/data/sl_core_data_lgrp.h  |    26 +
 .../hpe/sl/core/data/sl_core_data_lgrp_trace.c     |    50 +
 .../hpe/sl/core/data/sl_core_data_lgrp_trace.h     |    13 +
 .../ethernet/hpe/sl/core/data/sl_core_data_link.c  |  1343 ++
 .../ethernet/hpe/sl/core/data/sl_core_data_link.h  |    91 +
 .../ethernet/hpe/sl/core/data/sl_core_data_llr.c   |   526 +
 .../ethernet/hpe/sl/core/data/sl_core_data_llr.h   |    49 +
 .../ethernet/hpe/sl/core/data/sl_core_data_mac.c   |   273 +
 .../ethernet/hpe/sl/core/data/sl_core_data_mac.h   |    24 +
 .../ethernet/hpe/sl/core/hw/nic/sl_core_hw_an.c    |    26 +
 .../ethernet/hpe/sl/core/hw/nic/sl_core_hw_fec.c   |   113 +
 .../hpe/sl/core/hw/nic/sl_core_hw_intr_flgs.h      |    70 +
 .../hpe/sl/core/hw/nic/sl_core_hw_intr_flgs_llr.h  |    37 +
 .../ethernet/hpe/sl/core/hw/nic/sl_core_hw_llr.c   |    44 +
 .../ethernet/hpe/sl/core/hw/nic/sl_core_hw_mac.c   |    32 +
 .../ethernet/hpe/sl/core/hw/nic/sl_core_hw_pcs.c   |    14 +
 .../sl/core/hw/nic/sl_core_hw_serdes_firmware.h    |    11 +
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_an.c    |   602 +
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_an.h    |   112 +
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_an_lp.c |   254 +
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_an_lp.h |    23 +
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_an_up.c |   270 +
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_an_up.h |    15 +
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_fec.h   |    23 +
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_intr.c  |   222 +
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_intr.h  |    52 +
 .../ethernet/hpe/sl/core/hw/sl_core_hw_intr_llr.c  |   181 +
 .../ethernet/hpe/sl/core/hw/sl_core_hw_intr_llr.h  |    48 +
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_io.h    |   308 +
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_link.c  |  2172 +++
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_link.h  |    35 +
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_llr.c   |   905 ++
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_llr.h   |    38 +
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_mac.c   |   172 +
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_mac.h   |    20 +
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_pcs.c   |   365 +
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_pcs.h   |    25 +
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_pmi.c   |    54 +
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_pmi.h   |    43 +
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_reset.c |    67 +
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_reset.h |    13 +
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_sbus.c  |   125 +
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_sbus.h  |    52 +
 .../ethernet/hpe/sl/core/hw/sl_core_hw_sbus_pmi.c  |   112 +
 .../ethernet/hpe/sl/core/hw/sl_core_hw_sbus_pmi.h  |    28 +
 .../ethernet/hpe/sl/core/hw/sl_core_hw_serdes.c    |   212 +
 .../ethernet/hpe/sl/core/hw/sl_core_hw_serdes.h    |    23 +
 .../hpe/sl/core/hw/sl_core_hw_serdes_addrs.h       |    87 +
 .../hpe/sl/core/hw/sl_core_hw_serdes_condor.h      |    12 +
 .../hpe/sl/core/hw/sl_core_hw_serdes_core.c        |   439 +
 .../hpe/sl/core/hw/sl_core_hw_serdes_core.h        |    12 +
 .../ethernet/hpe/sl/core/hw/sl_core_hw_serdes_fw.c |   191 +
 .../ethernet/hpe/sl/core/hw/sl_core_hw_serdes_fw.h |    15 +
 .../hpe/sl/core/hw/sl_core_hw_serdes_lane.c        |  1085 ++
 .../hpe/sl/core/hw/sl_core_hw_serdes_lane.h        |   125 +
 .../hpe/sl/core/hw/sl_core_hw_serdes_lane_rx.c     |   241 +
 .../hpe/sl/core/hw/sl_core_hw_serdes_lane_tx.c     |   394 +
 .../hpe/sl/core/hw/sl_core_hw_serdes_link.c        |   349 +
 .../hpe/sl/core/hw/sl_core_hw_serdes_link.h        |    13 +
 .../hpe/sl/core/hw/sl_core_hw_serdes_osprey.h      |    89 +
 .../ethernet/hpe/sl/core/hw/sl_core_hw_settings.h  |    40 +
 .../ethernet/hpe/sl/core/hw/sl_core_hw_uc_ram.c    |    84 +
 .../ethernet/hpe/sl/core/hw/sl_core_hw_uc_ram.h    |    28 +
 drivers/net/ethernet/hpe/sl/core/hw/ucode/octet.h  |  9605 ++++++++++++
 drivers/net/ethernet/hpe/sl/core/hw/ucode/quad.h   |  9410 ++++++++++++
 drivers/net/ethernet/hpe/sl/core/sl_core_ldev.c    |   192 +
 drivers/net/ethernet/hpe/sl/core/sl_core_ldev.h    |    73 +
 drivers/net/ethernet/hpe/sl/core/sl_core_lgrp.c    |   659 +
 drivers/net/ethernet/hpe/sl/core/sl_core_lgrp.h    |   214 +
 drivers/net/ethernet/hpe/sl/core/sl_core_link.c    |   623 +
 drivers/net/ethernet/hpe/sl/core/sl_core_link.h    |   534 +
 drivers/net/ethernet/hpe/sl/core/sl_core_link_an.c |   166 +
 drivers/net/ethernet/hpe/sl/core/sl_core_link_an.h |    31 +
 .../net/ethernet/hpe/sl/core/sl_core_link_fec.c    |   233 +
 .../net/ethernet/hpe/sl/core/sl_core_link_fec.h    |    45 +
 drivers/net/ethernet/hpe/sl/core/sl_core_llr.c     |   350 +
 drivers/net/ethernet/hpe/sl/core/sl_core_llr.h     |   138 +
 drivers/net/ethernet/hpe/sl/core/sl_core_mac.c     |   183 +
 drivers/net/ethernet/hpe/sl/core/sl_core_mac.h     |    62 +
 drivers/net/ethernet/hpe/sl/core/sl_core_str.c     |   283 +
 drivers/net/ethernet/hpe/sl/core/sl_core_str.h     |    28 +
 .../net/ethernet/hpe/sl/ctrl/base/sl_ctrl_log.h    |    34 +
 .../ethernet/hpe/sl/ctrl/data/sl_ctrl_data_lgrp.c  |   164 +
 .../ethernet/hpe/sl/ctrl/data/sl_ctrl_data_lgrp.h  |    20 +
 .../hpe/sl/ctrl/data/sl_ctrl_data_lgrp_trace.c     |    50 +
 .../hpe/sl/ctrl/data/sl_ctrl_data_lgrp_trace.h     |    13 +
 .../ethernet/hpe/sl/ctrl/data/sl_ctrl_data_link.c  |   424 +
 .../ethernet/hpe/sl/ctrl/data/sl_ctrl_data_link.h  |    48 +
 .../ethernet/hpe/sl/ctrl/data/sl_ctrl_data_llr.c   |    64 +
 .../ethernet/hpe/sl/ctrl/data/sl_ctrl_data_llr.h   |    15 +
 drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_ldev.c    |   290 +
 drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_ldev.h    |    91 +
 drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_lgrp.c    |   351 +
 drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_lgrp.h    |    93 +
 .../net/ethernet/hpe/sl/ctrl/sl_ctrl_lgrp_notif.c  |   258 +
 .../net/ethernet/hpe/sl/ctrl/sl_ctrl_lgrp_notif.h  |    40 +
 drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_link.c    |  1230 ++
 drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_link.h    |   161 +
 .../ethernet/hpe/sl/ctrl/sl_ctrl_link_counters.c   |   388 +
 .../ethernet/hpe/sl/ctrl/sl_ctrl_link_counters.h   |   125 +
 .../net/ethernet/hpe/sl/ctrl/sl_ctrl_link_fec.c    |   202 +
 .../net/ethernet/hpe/sl/ctrl/sl_ctrl_link_fec.h    |    33 +
 .../ethernet/hpe/sl/ctrl/sl_ctrl_link_fec_priv.c   |   539 +
 .../ethernet/hpe/sl/ctrl/sl_ctrl_link_fec_priv.h   |    94 +
 .../net/ethernet/hpe/sl/ctrl/sl_ctrl_link_priv.c   |   865 ++
 .../net/ethernet/hpe/sl/ctrl/sl_ctrl_link_priv.h   |    47 +
 drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_llr.c     |   630 +
 drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_llr.h     |    69 +
 .../ethernet/hpe/sl/ctrl/sl_ctrl_llr_counters.c    |   136 +
 .../ethernet/hpe/sl/ctrl/sl_ctrl_llr_counters.h    |    57 +
 drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_mac.c     |   536 +
 drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_mac.h     |    57 +
 .../ethernet/hpe/sl/ctrl/sl_ctrl_mac_counters.c    |    56 +
 .../ethernet/hpe/sl/ctrl/sl_ctrl_mac_counters.h    |    43 +
 .../ethernet/hpe/sl/ctrl/sl_ctrl_media_counters.c  |   157 +
 .../ethernet/hpe/sl/ctrl/sl_ctrl_media_counters.h  |    53 +
 drivers/net/ethernet/hpe/sl/log/sl_log.c           |   566 +
 drivers/net/ethernet/hpe/sl/log/sl_log.h           |    67 +
 .../ethernet/hpe/sl/media/base/sl_media_eeprom.c   |   611 +
 .../ethernet/hpe/sl/media/base/sl_media_eeprom.h   |    16 +
 .../net/ethernet/hpe/sl/media/base/sl_media_log.h  |    36 +
 .../net/ethernet/hpe/sl/media/base/sl_media_work.h |    13 +
 .../hpe/sl/media/data/nic/sl_media_data_jack.c     |   496 +
 .../hpe/sl/media/data/nic/sl_media_data_jack_emu.c |    38 +
 .../hpe/sl/media/data/nic/sl_media_data_ldev.c     |    30 +
 .../hpe/sl/media/data/sl_media_data_cable_db.h     |  6896 +++++++++
 .../hpe/sl/media/data/sl_media_data_cable_db_ops.c |   111 +
 .../hpe/sl/media/data/sl_media_data_cable_db_ops.h |    13 +
 .../hpe/sl/media/data/sl_media_data_jack.c         |   344 +
 .../hpe/sl/media/data/sl_media_data_jack.h         |    92 +
 .../hpe/sl/media/data/sl_media_data_ldev.c         |   115 +
 .../hpe/sl/media/data/sl_media_data_ldev.h         |    20 +
 .../hpe/sl/media/data/sl_media_data_lgrp.c         |   127 +
 .../hpe/sl/media/data/sl_media_data_lgrp.h         |    20 +
 .../hpe/sl/media/data/sl_media_data_lgrp_trace.c   |    31 +
 .../hpe/sl/media/data/sl_media_data_lgrp_trace.h   |    12 +
 .../net/ethernet/hpe/sl/media/nic/sl_media_io.c    |    63 +
 .../net/ethernet/hpe/sl/media/nic/sl_media_jack.c  |   315 +
 .../net/ethernet/hpe/sl/media/nic/sl_media_ldev.c  |    13 +
 drivers/net/ethernet/hpe/sl/media/sl_media_io.h    |    17 +
 drivers/net/ethernet/hpe/sl/media/sl_media_jack.c  |  1067 ++
 drivers/net/ethernet/hpe/sl/media/sl_media_jack.h  |   319 +
 drivers/net/ethernet/hpe/sl/media/sl_media_ldev.c  |    22 +
 drivers/net/ethernet/hpe/sl/media/sl_media_ldev.h  |    33 +
 drivers/net/ethernet/hpe/sl/media/sl_media_lgrp.c  |   498 +
 drivers/net/ethernet/hpe/sl/media/sl_media_lgrp.h  |    99 +
 drivers/net/ethernet/hpe/sl/nic/sl_asic.h          |    35 +
 drivers/net/ethernet/hpe/sl/nic/sl_asic_csrs.h     |   215 +
 drivers/net/ethernet/hpe/sl/nic/sl_ldev.c          |   147 +
 drivers/net/ethernet/hpe/sl/nic/sl_media.c         |    53 +
 drivers/net/ethernet/hpe/sl/sl.h                   |    14 +
 drivers/net/ethernet/hpe/sl/sl_fec.c               |    68 +
 drivers/net/ethernet/hpe/sl/sl_ldev.c              |   133 +
 drivers/net/ethernet/hpe/sl/sl_ldev.h              |    25 +
 drivers/net/ethernet/hpe/sl/sl_lgrp.c              |   409 +
 drivers/net/ethernet/hpe/sl/sl_lgrp.h              |    21 +
 drivers/net/ethernet/hpe/sl/sl_link.c              |   632 +
 drivers/net/ethernet/hpe/sl/sl_link.h              |    22 +
 drivers/net/ethernet/hpe/sl/sl_llr.c               |   289 +
 drivers/net/ethernet/hpe/sl/sl_llr.h               |    20 +
 drivers/net/ethernet/hpe/sl/sl_mac.c               |   220 +
 drivers/net/ethernet/hpe/sl/sl_mac.h               |    20 +
 drivers/net/ethernet/hpe/sl/sl_media.c             |   356 +
 drivers/net/ethernet/hpe/sl/sl_media_nic.c         |    23 +
 drivers/net/ethernet/hpe/sl/sl_module.c            |   129 +
 drivers/net/ethernet/hpe/sl/sl_module.h            |    14 +
 drivers/net/ethernet/hpe/sl/sl_platform.h          |    16 +
 drivers/net/ethernet/hpe/sl/sl_test_common.h       |   105 +
 drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs.h       |   116 +
 drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_ldev.c  |   410 +
 drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_lgrp.c  |    98 +
 .../ethernet/hpe/sl/sysfs/sl_sysfs_lgrp_config.c   |   438 +
 .../ethernet/hpe/sl/sysfs/sl_sysfs_lgrp_policy.c   |    53 +
 drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link.c  |   830 ++
 .../net/ethernet/hpe/sl/sysfs/sl_sysfs_link_caps.c |   303 +
 .../ethernet/hpe/sl/sysfs/sl_sysfs_link_config.c   |   388 +
 .../ethernet/hpe/sl/sysfs/sl_sysfs_link_counters.c |  1498 ++
 .../ethernet/hpe/sl/sysfs/sl_sysfs_link_degrade.c  |   336 +
 .../net/ethernet/hpe/sl/sysfs/sl_sysfs_link_fec.c  |   148 +
 .../net/ethernet/hpe/sl/sysfs/sl_sysfs_link_fec.h  |    12 +
 .../hpe/sl/sysfs/sl_sysfs_link_fec_current.c       |   336 +
 .../hpe/sl/sysfs/sl_sysfs_link_fec_current.h       |    12 +
 .../ethernet/hpe/sl/sysfs/sl_sysfs_link_fec_down.c |   316 +
 .../ethernet/hpe/sl/sysfs/sl_sysfs_link_fec_down.h |    12 +
 .../hpe/sl/sysfs/sl_sysfs_link_fec_mon_check.c     |   195 +
 .../hpe/sl/sysfs/sl_sysfs_link_fec_mon_check.h     |    12 +
 .../ethernet/hpe/sl/sysfs/sl_sysfs_link_fec_up.c   |   299 +
 .../ethernet/hpe/sl/sysfs/sl_sysfs_link_fec_up.h   |    12 +
 .../hpe/sl/sysfs/sl_sysfs_link_fec_up_check.c      |   137 +
 .../hpe/sl/sysfs/sl_sysfs_link_fec_up_check.h      |    12 +
 .../ethernet/hpe/sl/sysfs/sl_sysfs_link_pml_rec.c  |   193 +
 .../ethernet/hpe/sl/sysfs/sl_sysfs_link_policy.c   |   261 +
 drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_llr.c   |   221 +
 .../ethernet/hpe/sl/sysfs/sl_sysfs_llr_config.c    |   140 +
 .../ethernet/hpe/sl/sysfs/sl_sysfs_llr_counters.c  |   397 +
 .../ethernet/hpe/sl/sysfs/sl_sysfs_llr_loop_time.c |   221 +
 .../ethernet/hpe/sl/sysfs/sl_sysfs_llr_policy.c    |    74 +
 drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_mac.c   |   192 +
 .../ethernet/hpe/sl/sysfs/sl_sysfs_mac_counters.c  |   339 +
 drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_media.c |  1274 ++
 .../hpe/sl/sysfs/sl_sysfs_media_counters.c         |   599 +
 drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_pmi.c   |    80 +
 .../net/ethernet/hpe/sl/sysfs/sl_sysfs_pmi_rd.c    |   197 +
 .../net/ethernet/hpe/sl/sysfs/sl_sysfs_pmi_wr.c    |   220 +
 drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_sbus.c  |    89 +
 .../net/ethernet/hpe/sl/sysfs/sl_sysfs_sbus_pmi.c  |    80 +
 .../ethernet/hpe/sl/sysfs/sl_sysfs_sbus_pmi_rd.c   |   244 +
 .../ethernet/hpe/sl/sysfs/sl_sysfs_sbus_pmi_wr.c   |   244 +
 .../net/ethernet/hpe/sl/sysfs/sl_sysfs_sbus_rd.c   |   197 +
 .../net/ethernet/hpe/sl/sysfs/sl_sysfs_sbus_rst.c  |   105 +
 .../net/ethernet/hpe/sl/sysfs/sl_sysfs_sbus_wr.c   |   197 +
 .../net/ethernet/hpe/sl/sysfs/sl_sysfs_serdes.c    |   302 +
 .../ethernet/hpe/sl/sysfs/sl_sysfs_serdes_eye.c    |   197 +
 .../ethernet/hpe/sl/sysfs/sl_sysfs_serdes_eye.h    |    12 +
 .../ethernet/hpe/sl/sysfs/sl_sysfs_serdes_lol.c    |   141 +
 .../ethernet/hpe/sl/sysfs/sl_sysfs_serdes_lol.h    |    12 +
 .../ethernet/hpe/sl/sysfs/sl_sysfs_serdes_los.c    |   142 +
 .../ethernet/hpe/sl/sysfs/sl_sysfs_serdes_los.h    |    12 +
 .../hpe/sl/sysfs/sl_sysfs_serdes_settings.c        |   506 +
 .../hpe/sl/sysfs/sl_sysfs_serdes_settings.h        |    12 +
 .../ethernet/hpe/sl/sysfs/sl_sysfs_serdes_state.c  |   121 +
 .../ethernet/hpe/sl/sysfs/sl_sysfs_serdes_state.h  |    12 +
 .../hpe/sl/sysfs/sl_sysfs_serdes_swizzle.c         |   126 +
 .../hpe/sl/sysfs/sl_sysfs_serdes_swizzle.h         |    14 +
 drivers/net/ethernet/hpe/ss1/Kconfig               |    35 +
 drivers/net/ethernet/hpe/ss1/Makefile              |    28 +
 drivers/net/ethernet/hpe/ss1/cass_ats.c            |   299 +
 drivers/net/ethernet/hpe/ss1/cass_ats_inval.c      |    79 +
 drivers/net/ethernet/hpe/ss1/cass_atu.c            |  2072 +++
 drivers/net/ethernet/hpe/ss1/cass_cable.c          |   702 +
 drivers/net/ethernet/hpe/ss1/cass_cable.h          |   157 +
 drivers/net/ethernet/hpe/ss1/cass_core.c           |  1564 ++
 drivers/net/ethernet/hpe/ss1/cass_core.h           |  1472 ++
 drivers/net/ethernet/hpe/ss1/cass_cpt.c            |   585 +
 drivers/net/ethernet/hpe/ss1/cass_cq.c             |  1243 ++
 drivers/net/ethernet/hpe/ss1/cass_ct.c             |   639 +
 drivers/net/ethernet/hpe/ss1/cass_dev_info.c       |    60 +
 drivers/net/ethernet/hpe/ss1/cass_dma_buf.c        |   256 +
 drivers/net/ethernet/hpe/ss1/cass_dmac.c           |   597 +
 drivers/net/ethernet/hpe/ss1/cass_eq.c             |  1518 ++
 drivers/net/ethernet/hpe/ss1/cass_errors.c         |  1155 ++
 drivers/net/ethernet/hpe/ss1/cass_eth.c            |   702 +
 drivers/net/ethernet/hpe/ss1/cass_hmm.c            |   320 +
 drivers/net/ethernet/hpe/ss1/cass_hni.c            |   370 +
 drivers/net/ethernet/hpe/ss1/cass_irq.c            |   210 +
 drivers/net/ethernet/hpe/ss1/cass_ixe.c            |   348 +
 drivers/net/ethernet/hpe/ss1/cass_link.c           |   192 +
 drivers/net/ethernet/hpe/ss1/cass_link_misc.c      |   159 +
 drivers/net/ethernet/hpe/ss1/cass_lmon.c           |   573 +
 drivers/net/ethernet/hpe/ss1/cass_lni.c            |   404 +
 drivers/net/ethernet/hpe/ss1/cass_nta.c            |  1996 +++
 drivers/net/ethernet/hpe/ss1/cass_odp_decouple.c   |   599 +
 drivers/net/ethernet/hpe/ss1/cass_p2p.c            |   321 +
 drivers/net/ethernet/hpe/ss1/cass_p2p.h            |    69 +
 drivers/net/ethernet/hpe/ss1/cass_pcie_mon.c       |   288 +
 drivers/net/ethernet/hpe/ss1/cass_phy.c            |   224 +
 drivers/net/ethernet/hpe/ss1/cass_port_misc.c      |    68 +
 drivers/net/ethernet/hpe/ss1/cass_pt.c             |  1255 ++
 drivers/net/ethernet/hpe/ss1/cass_ptp.c            |   304 +
 drivers/net/ethernet/hpe/ss1/cass_rgid.c           |   293 +
 drivers/net/ethernet/hpe/ss1/cass_rgroup.c         |   281 +
 drivers/net/ethernet/hpe/ss1/cass_rgroup.h         |    30 +
 drivers/net/ethernet/hpe/ss1/cass_rmu.c            |   376 +
 drivers/net/ethernet/hpe/ss1/cass_rmu_eth.c        |  1017 ++
 drivers/net/ethernet/hpe/ss1/cass_rx_tx_profile.c  |   104 +
 drivers/net/ethernet/hpe/ss1/cass_rx_tx_profile.h  |    15 +
 drivers/net/ethernet/hpe/ss1/cass_sbl.c            |  1706 +++
 drivers/net/ethernet/hpe/ss1/cass_sbl.h            |   581 +
 drivers/net/ethernet/hpe/ss1/cass_sbus.c           |   172 +
 drivers/net/ethernet/hpe/ss1/cass_sl.c             |  1524 ++
 drivers/net/ethernet/hpe/ss1/cass_sl.h             |    95 +
 drivers/net/ethernet/hpe/ss1/cass_sl_io.c          |   368 +
 drivers/net/ethernet/hpe/ss1/cass_sl_io.h          |    19 +
 drivers/net/ethernet/hpe/ss1/cass_sriov.c          |  1274 ++
 drivers/net/ethernet/hpe/ss1/cass_ss1_debugfs.c    |   824 +
 drivers/net/ethernet/hpe/ss1/cass_ss1_debugfs.h    |    86 +
 drivers/net/ethernet/hpe/ss1/cass_svc.c            |  2011 +++
 drivers/net/ethernet/hpe/ss1/cass_sysfs.c          |   849 ++
 drivers/net/ethernet/hpe/ss1/cass_tc.c             |  2780 ++++
 drivers/net/ethernet/hpe/ss1/cass_telem.c          |   309 +
 drivers/net/ethernet/hpe/ss1/cass_telem_tables.h   |  3874 +++++
 drivers/net/ethernet/hpe/ss1/cass_trace.h          |    60 +
 drivers/net/ethernet/hpe/ss1/cass_uc.c             |  1933 +++
 drivers/net/ethernet/hpe/ss1/cass_vf.c             |    58 +
 drivers/net/ethernet/hpe/ss1/cass_vf.h             |    59 +
 drivers/net/ethernet/hpe/ss1/cass_vf_notif.c       |    51 +
 drivers/net/ethernet/hpe/ss1/cass_vf_notif.h       |    34 +
 drivers/net/ethernet/hpe/ss1/cuc_cxi.h             |   370 +
 drivers/net/ethernet/hpe/ss1/cxi_ac_entry_list.c   |   499 +
 drivers/net/ethernet/hpe/ss1/cxi_ac_entry_list.h   |    20 +
 drivers/net/ethernet/hpe/ss1/cxi_aux_dev.c         |   137 +
 drivers/net/ethernet/hpe/ss1/cxi_aux_dev.h         |    14 +
 drivers/net/ethernet/hpe/ss1/cxi_config.c          |  2990 ++++
 drivers/net/ethernet/hpe/ss1/cxi_config.h          |   234 +
 drivers/net/ethernet/hpe/ss1/cxi_configuration.h   |   332 +
 drivers/net/ethernet/hpe/ss1/cxi_core.c            |   281 +
 drivers/net/ethernet/hpe/ss1/cxi_core.h            |   434 +
 drivers/net/ethernet/hpe/ss1/cxi_eth.c             |   443 +
 drivers/net/ethernet/hpe/ss1/cxi_eth.h             |   352 +
 drivers/net/ethernet/hpe/ss1/cxi_eth_debugfs.c     |   206 +
 drivers/net/ethernet/hpe/ss1/cxi_eth_debugfs.h     |    26 +
 drivers/net/ethernet/hpe/ss1/cxi_eth_ioctl.c       |    44 +
 drivers/net/ethernet/hpe/ss1/cxi_eth_ops.c         |  2367 +++
 drivers/net/ethernet/hpe/ss1/cxi_ethtool.c         |   916 ++
 drivers/net/ethernet/hpe/ss1/cxi_ethtool.h         |    26 +
 drivers/net/ethernet/hpe/ss1/cxi_ethtool_names.h   |   110 +
 drivers/net/ethernet/hpe/ss1/cxi_internal.h        |    39 +
 drivers/net/ethernet/hpe/ss1/cxi_link.c            |   227 +
 drivers/net/ethernet/hpe/ss1/cxi_link.h            |    65 +
 drivers/net/ethernet/hpe/ss1/cxi_qos_profiles.c    |   722 +
 drivers/net/ethernet/hpe/ss1/cxi_qos_profiles.h    |   149 +
 drivers/net/ethernet/hpe/ss1/cxi_rgroup.c          |  1791 +++
 drivers/net/ethernet/hpe/ss1/cxi_rgroup.h          |    68 +
 drivers/net/ethernet/hpe/ss1/cxi_rx_profile.c      |   833 ++
 drivers/net/ethernet/hpe/ss1/cxi_rxtx_profile.c    |   418 +
 drivers/net/ethernet/hpe/ss1/cxi_rxtx_profile.h    |   135 +
 .../net/ethernet/hpe/ss1/cxi_rxtx_profile_list.c   |   249 +
 .../net/ethernet/hpe/ss1/cxi_rxtx_profile_list.h   |    53 +
 drivers/net/ethernet/hpe/ss1/cxi_tx_profile.c      |   819 +
 drivers/net/ethernet/hpe/ss1/cxi_vf_cmd.h          |    52 +
 drivers/net/ethernet/hpe/ss1/pldm_cxi.h            |   374 +
 include/linux/hpe/cxi/cassini_cntr_defs.h          |  2888 ++++
 include/linux/hpe/cxi/cassini_csr_defaults.h       |   703 +
 include/linux/hpe/cxi/cassini_error_defs.h         |  9091 +++++++++++
 include/linux/hpe/cxi/cxi.h                        |   611 +
 include/linux/hpe/cxi/cxi_defs.h                   |  1506 ++
 include/linux/hpe/cxi/cxi_prov_hw.h                |  1875 +++
 include/linux/hpe/cxi/driver.h                     |   102 +
 include/linux/hpe/cxi/libcassini.h                 |  1252 ++
 include/linux/hpe/sbl/sbl.h                        |   436 +
 include/linux/hpe/sbl/sbl_an.h                     |   174 +
 include/linux/hpe/sbl/sbl_csr_common.h             |    63 +
 include/linux/hpe/sbl/sbl_fec.h                    |    88 +
 include/linux/hpe/sbl/sbl_kconfig.h                |    33 +
 include/linux/hpe/sbl/sbl_mb.h                     |    77 +
 include/linux/hpe/sbl/sbl_platform.h               |    35 +
 include/linux/hpe/sbl/sbl_pml.h                    |  1081 ++
 include/linux/hpe/sbl/sbl_test.h                   |    20 +
 include/linux/hpe/sl/sl_fec.h                      |    39 +
 include/linux/hpe/sl/sl_ldev.h                     |   140 +
 include/linux/hpe/sl/sl_lgrp.h                     |   213 +
 include/linux/hpe/sl/sl_link.h                     |   244 +
 include/linux/hpe/sl/sl_llr.h                      |    84 +
 include/linux/hpe/sl/sl_mac.h                      |    32 +
 include/linux/hpe/sl/sl_media.h                    |   191 +
 include/uapi/ethernet/cassini_user_defs.h          | 14936 +++++++++++++++++++
 include/uapi/ethernet/sbl-abi.h                    |   648 +
 include/uapi/ethernet/sbl_cassini.h                |    21 +
 include/uapi/ethernet/sbl_counters.h               |   152 +
 include/uapi/ethernet/sbl_platform_config.h        |    13 +
 include/uapi/ethernet/sbl_sbm_constants.h          |   330 +
 include/uapi/ethernet/sbl_serdes.h                 |   390 +
 include/uapi/ethernet/sbl_serdes_defaults.h        |    66 +
 include/uapi/ethernet/sbl_serdes_map.h             |    41 +
 include/uapi/ethernet/sbl_serdes_map_init.h        |    65 +
 usr/include/Makefile                               |     5 +
 416 files changed, 185137 insertions(+)
---
base-commit: 734bef548a96e8774d6eef5dfa2026c6edc4e80b
change-id: 20261029-cxi-netdev-submission-673053a5d05e

Best regards,
--  
Doug Ledford <doug.ledford@hpe.com>


^ permalink raw reply	[flat|nested] 25+ messages in thread
* [PATCH 01/23] net: hpe: ss1: add the Cassini headers
  2026-10-30 20:58 [PATCH 00/23] Subject: [PATCH net-next 00/23] net/hpe: add HPE Slingshot NIC drivers Doug Ledford
@ 2026-10-30 20:58 ` Doug Ledford
  2026-10-30 20:58 ` [PATCH 02/23] net: hpe: sbl: add the Slingshot Base Link headers Doug Ledford
                   ` (22 subsequent siblings)
  23 siblings, 0 replies; 25+ messages in thread
From: Doug Ledford @ 2026-10-30 20:58 UTC (permalink / raw)
  To: Slingshot Open Source Team, Nathan Chancellor, Nicolas Schier,
	Richard Cochran, Andrew Lunn, David S. Miller, Eric Dumazet,
	Jakub Kicinski, Paolo Abeni, Sumit Semwal, Christian König,
	Guenter Roeck
  Cc: linux-kernel, netdev, linux-kbuild, Doug Ledford, Sandeep Bhoot

Start the Cassini core driver (cxi-ss1) with its headers: the register
and counter definitions, error definitions, telemetry item tables, and
the CXI interface (cxi.h, cxi_prov_hw.h, libcassini.h) through which
client drivers use the NIC.

The cassini_* headers are generated from the hardware description and
are not meant to be edited by hand, so they carry the generator's
formatting.  cassini_user_defs.h is shared byte-for-byte with the user
space libraries and is therefore under include/uapi/ethernet.  It
provides inline accessors that need errno.h, string.h and size_t,
which a standalone UAPI header cannot assume, so this patch excludes
it from the UAPI header self-test.

All fixed-width types use the kernel names (u8..u64) as the headers
are consumed from kernel code.

The Kconfig and Makefile hookup for this driver is deliberately the
last patch of the driver group, so that every earlier patch adds
sources without changing what the tree builds.

Known limitation, deferred to V2: this patch carries SR-IOV
virtual-function code (VF-to-PF mailbox requests, mailbox opcodes or VF
resource handling) from an older, incomplete version of the Cassini
SR-IOV support. V2 of this series will include the updated SR-IOV
implementation, so issues in the VF paths should be ignored for now.

checkpatch --strict (100 columns) still reports the following in this
patch. They need coordination with the internal repositories this code
is maintained in and will be fixed in V2:
- ERROR: SPACING (5), FLEXIBLE_ARRAY (3), COMPLEX_MACRO (2), CODE_INDENT
  (1)
- WARNING: LONG_LINE (89), BLOCK_COMMENT_STYLE (10), LEADING_SPACE (5),
  SPDX_LICENSE_TAG (4), VOLATILE (2), BRACES (1),
  PREFER_DEFINED_ATTRIBUTE_MACRO (1), SPACING (1), UNSPECIFIED_INT (1)
- CHECK: ASSIGNMENT_CONTINUATIONS (1426), PARENTHESIS_ALIGNMENT (27),
  BIT_MACRO (17), LINE_SPACING (15), MACRO_ARG_REUSE (8), CAMELCASE (2),
  UNCOMMENTED_DEFINITION (2)

Co-developed-by: Sandeep Bhoot <sandeep.bhoot@hpe.com>
Signed-off-by: Sandeep Bhoot <sandeep.bhoot@hpe.com>
Signed-off-by: Doug Ledford <doug.ledford@hpe.com>
---
 include/linux/hpe/cxi/cassini_cntr_defs.h    |  2888 +++++
 include/linux/hpe/cxi/cassini_csr_defaults.h |   703 ++
 include/linux/hpe/cxi/cassini_error_defs.h   |  9091 +++++++++++++++
 include/linux/hpe/cxi/cxi.h                  |   611 +
 include/linux/hpe/cxi/cxi_defs.h             |  1506 +++
 include/linux/hpe/cxi/cxi_prov_hw.h          |  1875 ++++
 include/linux/hpe/cxi/driver.h               |   102 +
 include/linux/hpe/cxi/libcassini.h           |  1252 +++
 include/uapi/ethernet/cassini_user_defs.h    | 14936 +++++++++++++++++++++++++
 usr/include/Makefile                         |     5 +
 10 files changed, 32969 insertions(+)

diff --git a/include/linux/hpe/cxi/cassini_cntr_defs.h b/include/linux/hpe/cxi/cassini_cntr_defs.h
new file mode 100644
index 000000000000..60a81adfff0f
--- /dev/null
+++ b/include/linux/hpe/cxi/cassini_cntr_defs.h
@@ -0,0 +1,2888 @@
+// SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+/*
+* Copyright 2018-2021,2024 Hewlett Packard Enterprise Development LP
+*
+* This file is for temporary backwards compatibility with the libcxi API
+* for cassini telemetry/counters.  That backwards compatibility will be
+* removed in a future release.	This file was previously generated and
+* released as part of "cassini-headers".
+*/
+
+#ifndef __CASSINI_CNTR_DEFS_H
+#define __CASSINI_CNTR_DEFS_H
+
+#define C1_CNTR_COUNT 1426
+#define C1_CNTR_SIZE 2528
+
+/*
+ * C_CNTR_ENTRY() - Compute counter array entry.
+ *
+ * Several counters are presented as arrays. Use C_CNTR_ARRAY() to compute
+ * an array entry dynamically. For example, the following lines are equivalent:
+ *    C_CNTR_ENTRY(C_CNTR_CQ_NUM_TXQ_CMD_READ_0, 3),
+ *    C_CNTR_CQ_NUM_TXQ_CMD_READ_3
+ */
+#define C_CNTR_ENTRY(base, id) ((base) + (id))
+
+#define C_CNTR_TYPE_GROUP_OFFSET_PI_IPD 96
+#define C_CNTR_TYPE_GROUP_OFFSET_MB	224
+#define C_CNTR_TYPE_GROUP_OFFSET_CQ	480
+#define C_CNTR_TYPE_GROUP_OFFSET_LPE	992
+#define C_CNTR_TYPE_GROUP_OFFSET_HNI	1504
+
+enum c_cntr_type {
+	C_CNTR_PI_IPD_PRI_RTRGT_TLPS
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +   0),
+	C_CNTR_PI_IPD_PRI_RTRGT_MWR_TLPS
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +   1),
+	C_CNTR_PI_IPD_PRI_RTRGT_MRD_TLPS
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +   2),
+	C_CNTR_PI_IPD_PRI_RTRGT_MSG_TLPS
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +   3),
+	C_CNTR_PI_IPD_PRI_RTRGT_MSGD_TLPS
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +   4),
+	C_CNTR_PI_IPD_PRI_RTRGT_TLPS_ABORTED
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +   5),
+	C_CNTR_PI_IPD_PRI_RTRGT_BLOCKED_ON_MB
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +   6),
+	C_CNTR_PI_IPD_PRI_RTRGT_BLOCKED_ON_RARB
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +   7),
+	C_CNTR_PI_IPD_PRI_RTRGT_HDR_PARITY_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +   8),
+	C_CNTR_PI_IPD_PRI_RTRGT_DATA_PARITY_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +   9),
+	C_CNTR_PI_IPD_PRI_RBYP_TLPS
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  10),
+	C_CNTR_PI_IPD_PRI_RBYP_TLPS_ABORTED
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  11),
+	C_CNTR_PI_IPD_PRI_RBYP_HDR_PARITY_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  12),
+	C_CNTR_PI_IPD_PRI_RBYP_DATA_PARITY_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  13),
+	C_CNTR_PI_IPD_PTI_TARB_XALI_POSTED_TLPS
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  14),
+	C_CNTR_PI_IPD_PTI_TARB_XALI_NON_POSTED_TLPS
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  15),
+	C_CNTR_PI_IPD_PTI_MSIXC_XALI_POSTED_TLPS
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  16),
+	C_CNTR_PI_IPD_PTI_DBG_XALI_POSTED_TLPS
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  17),
+	C_CNTR_PI_IPD_PTI_DBG_XALI_NON_POSTED_TLPS
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  18),
+	C_CNTR_PI_IPD_PTI_DMAC_XALI_POSTED_TLPS
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  19),
+	C_CNTR_PI_IPD_PTI_TARB_P_FIFO_COR_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  20),
+	C_CNTR_PI_IPD_PTI_TARB_P_FIFO_UCOR_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  21),
+	C_CNTR_PI_IPD_PTI_TARB_NP_FIFO_COR_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  22),
+	C_CNTR_PI_IPD_PTI_TARB_NP_FIFO_UCOR_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  23),
+	C_CNTR_PI_IPD_PTI_TARB_BLOCKED_ON_PH_CRD
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  24),
+	C_CNTR_PI_IPD_PTI_TARB_BLOCKED_ON_PD_CRD
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  25),
+	C_CNTR_PI_IPD_PTI_TARB_BLOCKED_ON_NPH_CRD
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  26),
+	C_CNTR_PI_IPD_PTI_TARB_BLOCKED_ON_NPD_CRD
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  27),
+	C_CNTR_PI_IPD_PTI_TARB_BLOCKED_ON_TAG
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  28),
+	C_CNTR_PI_IPD_PTI_DMAC_BLOCKED_ON_PH_CRD
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  29),
+	C_CNTR_PI_IPD_PTI_DMAC_BLOCKED_ON_PD_CRD
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  30),
+	C_CNTR_PI_IPD_PTI_MSIXC_BLOCKED_ON_PH_CRD
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  31),
+	C_CNTR_PI_IPD_PTI_MSIXC_BLOCKED_ON_PD_CRD
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  32),
+	C_CNTR_PI_IPD_PTI_DBG_BLOCKED_ON_PH_CRD
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  33),
+	C_CNTR_PI_IPD_PTI_DBG_BLOCKED_ON_PD_CRD
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  34),
+	C_CNTR_PI_IPD_PTI_DBG_BLOCKED_ON_NPH_CRD
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  35),
+	C_CNTR_PI_IPD_PTI_DBG_BLOCKED_ON_TAG
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  36),
+	C_CNTR_PI_IPD_PTI_TARB_CMPL_TO
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  37),
+	C_CNTR_PI_IPD_PTI_TARB_CMPL_TO_FIFO_COR_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  38),
+	C_CNTR_PI_IPD_PTI_TARB_CMPL_TO_FIFO_UCOR_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  39),
+	C_CNTR_PI_IPD_MSIXC_OOB_IRQS_SENT
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  40),
+	C_CNTR_PI_IPD_MSIXC_OOB_LEGACY_IRQS_SENT
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  41),
+	C_CNTR_PI_IPD_MSIXC_OOB_IRQS_DISCARDED
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  42),
+	C_CNTR_PI_IPD_MSIXC_OOB_IRQ_PBAS
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  43),
+	C_CNTR_PI_IPD_MSIXC_IB_IRQS_SENT
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  44),
+	C_CNTR_PI_IPD_MSIXC_IB_LEGACY_IRQS_SENT
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  45),
+	C_CNTR_PI_IPD_MSIXC_IB_IRQS_DISCARDED
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  46),
+	C_CNTR_PI_IPD_MSIXC_IB_IRQ_PBAS
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  47),
+	C_CNTR_PI_IPD_MSIXC_PBA_COR_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  48),
+	C_CNTR_PI_IPD_MSIXC_PBA_UCOR_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  49),
+	C_CNTR_PI_IPD_MSIXC_TABLE_COR_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  50),
+	C_CNTR_PI_IPD_MSIXC_TABLE_UCOR_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  51),
+	C_CNTR_PI_IPD_PTI_MSIXC_FIFO_COR_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  52),
+	C_CNTR_PI_IPD_PTI_MSIXC_FIFO_UCOR_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  53),
+	C_CNTR_PI_IPD_MSIXC_PTI_FIFO_COR_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  54),
+	C_CNTR_PI_IPD_MSIXC_PTI_FIFO_UCOR_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  55),
+	C_CNTR_PI_IPD_DMAC_P_FIFO_COR_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  56),
+	C_CNTR_PI_IPD_DMAC_P_FIFO_UCOR_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  57),
+	C_CNTR_PI_IPD_DBIC_DBI_REQUESTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  58),
+	C_CNTR_PI_IPD_DBIC_DBI_ACKS
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  59),
+	C_CNTR_PI_IPD_IPD_TRIGGER_EVENTS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  60),
+	C_CNTR_PI_IPD_IPD_TRIGGER_EVENTS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_PI_IPD +  61),
+	C_CNTR_MB_CRMC_RING_SBE_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +   0),
+	C_CNTR_MB_CRMC_RING_SBE_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +   1),
+	C_CNTR_MB_CRMC_RING_SBE_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +   2),
+	C_CNTR_MB_CRMC_RING_MBE_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +   3),
+	C_CNTR_MB_CRMC_RING_MBE_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +   4),
+	C_CNTR_MB_CRMC_RING_MBE_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +   5),
+	C_CNTR_MB_CRMC_WR_ERROR_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +   6),
+	C_CNTR_MB_CRMC_WR_ERROR_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +   7),
+	C_CNTR_MB_CRMC_WR_ERROR_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +   8),
+	C_CNTR_MB_CRMC_AXI_WR_REQUESTS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +   9),
+	C_CNTR_MB_CRMC_AXI_WR_REQUESTS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  10),
+	C_CNTR_MB_CRMC_AXI_WR_REQUESTS_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  11),
+	C_CNTR_MB_CRMC_RING_WR_REQUESTS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  12),
+	C_CNTR_MB_CRMC_RING_WR_REQUESTS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  13),
+	C_CNTR_MB_CRMC_RING_WR_REQUESTS_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  14),
+	C_CNTR_MB_CRMC_RD_ERROR_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  15),
+	C_CNTR_MB_CRMC_RD_ERROR_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  16),
+	C_CNTR_MB_CRMC_RD_ERROR_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  17),
+	C_CNTR_MB_CRMC_AXI_RD_REQUESTS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  18),
+	C_CNTR_MB_CRMC_AXI_RD_REQUESTS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  19),
+	C_CNTR_MB_CRMC_AXI_RD_REQUESTS_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  20),
+	C_CNTR_MB_CRMC_RING_RD_REQUESTS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  21),
+	C_CNTR_MB_CRMC_RING_RD_REQUESTS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  22),
+	C_CNTR_MB_CRMC_RING_RD_REQUESTS_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  23),
+	C_CNTR_MB_JAI_AXI_WR_REQUESTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  24),
+	C_CNTR_MB_JAI_AXI_RD_REQUESTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  25),
+	C_CNTR_MB_MB_LSA0_TRIGGER_EVENTS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  26),
+	C_CNTR_MB_MB_LSA0_TRIGGER_EVENTS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  27),
+	C_CNTR_MB_IXE_LSA0_TRIGGER_EVENTS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  28),
+	C_CNTR_MB_IXE_LSA0_TRIGGER_EVENTS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  29),
+	C_CNTR_MB_CQ_LSA0_TRIGGER_EVENTS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  30),
+	C_CNTR_MB_CQ_LSA0_TRIGGER_EVENTS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  31),
+	C_CNTR_MB_EE_LSA0_TRIGGER_EVENTS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  32),
+	C_CNTR_MB_EE_LSA0_TRIGGER_EVENTS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  33),
+	C_CNTR_MB_MB_LSA1_TRIGGER_EVENTS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  34),
+	C_CNTR_MB_MB_LSA1_TRIGGER_EVENTS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  35),
+	C_CNTR_MB_IXE_LSA1_TRIGGER_EVENTS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  36),
+	C_CNTR_MB_IXE_LSA1_TRIGGER_EVENTS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  37),
+	C_CNTR_MB_CQ_LSA1_TRIGGER_EVENTS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  38),
+	C_CNTR_MB_CQ_LSA1_TRIGGER_EVENTS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  39),
+	C_CNTR_MB_EE_LSA1_TRIGGER_EVENTS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  40),
+	C_CNTR_MB_EE_LSA1_TRIGGER_EVENTS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  41),
+	C_CNTR_MB_CMC_AXI_WR_REQUESTS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  42),
+	C_CNTR_MB_CMC_AXI_WR_REQUESTS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  43),
+	C_CNTR_MB_CMC_AXI_WR_REQUESTS_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  44),
+	C_CNTR_MB_CMC_AXI_WR_REQUESTS_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  45),
+	C_CNTR_MB_CMC_AXI_RD_REQUESTS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  46),
+	C_CNTR_MB_CMC_AXI_RD_REQUESTS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  47),
+	C_CNTR_MB_CMC_AXI_RD_REQUESTS_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  48),
+	C_CNTR_MB_CMC_AXI_RD_REQUESTS_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  49),
+	C_CNTR_PI_PRI_MB_RTRGT_TLPS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  64),
+	C_CNTR_PI_PRI_MB_RTRGT_MWR_TLPS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  65),
+	C_CNTR_PI_PRI_MB_RTRGT_MRD_TLPS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  66),
+	C_CNTR_PI_PRI_MB_RTRGT_TLP_DISCARDS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  67),
+	C_CNTR_PI_PRI_MB_RTRGT_POSTED_TLP_DISCARDS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  68),
+	C_CNTR_PI_PRI_MB_RTRGT_NON_POSTED_TLP_DISCARDS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  69),
+	C_CNTR_PI_PRI_MB_RTRGT_POSTED_TLP_PARTIAL_DISCARDS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  70),
+	C_CNTR_PI_PRI_MB_RTRGT_FIFO_COR_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  71),
+	C_CNTR_PI_PRI_MB_RTRGT_FIFO_UCOR_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  72),
+	C_CNTR_PI_PRI_MB_XALI_CMPL_TLPS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  73),
+	C_CNTR_PI_PRI_MB_XALI_CMPL_CA_TLPS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  74),
+	C_CNTR_PI_PRI_MB_XALI_CMPL_UR_TLPS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  75),
+	C_CNTR_PI_PRI_MB_AXI_WR_REQUESTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  76),
+	C_CNTR_PI_PRI_MB_AXI_RD_REQUESTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  77),
+	C_CNTR_PI_PRI_MB_AXI_WR_RSP_DECERRS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  78),
+	C_CNTR_PI_PRI_MB_AXI_WR_RSP_SLVERRS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  79),
+	C_CNTR_PI_PRI_MB_AXI_RD_RSP_DECERRS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  80),
+	C_CNTR_PI_PRI_MB_AXI_RD_RSP_SLVERRS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  81),
+	C_CNTR_PI_PRI_MB_AXI_RD_RSP_PARERRS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  82),
+	C_CNTR_PI_PRI_RARB_RTRGT_TLPS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  83),
+	C_CNTR_PI_PRI_RARB_RTRGT_MWR_TLPS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  84),
+	C_CNTR_PI_PRI_RARB_RTRGT_MSG_TLPS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  85),
+	C_CNTR_PI_PRI_RARB_RTRGT_MSGD_TLPS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  86),
+	C_CNTR_PI_PRI_RARB_RTRGT_TLP_DISCARDS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  87),
+	C_CNTR_PI_PRI_RARB_RTRGT_FIFO_COR_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  88),
+	C_CNTR_PI_PRI_RARB_RTRGT_FIFO_UCOR_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  89),
+	C_CNTR_PI_PRI_RARB_RBYP_TLPS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  90),
+	C_CNTR_PI_PRI_RARB_RBYP_TLP_DISCARDS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  91),
+	C_CNTR_PI_PRI_RARB_RBYP_FIFO_COR_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  92),
+	C_CNTR_PI_PRI_RARB_RBYP_FIFO_UCOR_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  93),
+	C_CNTR_PI_PRI_RARB_SRIOVT_COR_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  94),
+	C_CNTR_PI_PRI_RARB_SRIOVT_UCOR_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  95),
+	C_CNTR_PI_PTI_TARB_PKTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  96),
+	C_CNTR_PI_PTI_TARB_PKT_DISCARDS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  97),
+	C_CNTR_PI_PTI_TARB_RARB_CA_PKTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  98),
+	C_CNTR_PI_PTI_TARB_MWR_PKTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   +  99),
+	C_CNTR_PI_PTI_TARB_MRD_PKTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 100),
+	C_CNTR_PI_PTI_TARB_FLUSH_PKTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 101),
+	C_CNTR_PI_PTI_TARB_IRQ_PKTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 102),
+	C_CNTR_PI_PTI_TARB_TRANSLATION_PKTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 103),
+	C_CNTR_PI_PTI_TARB_INV_RSP_PKTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 104),
+	C_CNTR_PI_PTI_TARB_PG_REQ_PKTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 105),
+	C_CNTR_PI_PTI_TARB_AMO_PKTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 106),
+	C_CNTR_PI_PTI_TARB_FETCHING_AMO_PKTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 107),
+	C_CNTR_PI_PTI_TARB_HDR_COR_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 108),
+	C_CNTR_PI_PTI_TARB_HDR_UCOR_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 109),
+	C_CNTR_PI_PTI_TARB_DATA_COR_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 110),
+	C_CNTR_PI_PTI_TARB_DATA_UCOR_ERROR
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 111),
+	C_CNTR_PI_PTI_TARB_ACXT_COR_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 112),
+	C_CNTR_PI_PTI_TARB_ACXT_UCOR_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 113),
+	C_CNTR_PI_DMAC_AXI_RD_REQUESTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 119),
+	C_CNTR_PI_DMAC_AXI_RD_RSP_DECERRS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 120),
+	C_CNTR_PI_DMAC_AXI_RD_RSP_SLVERRS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 121),
+	C_CNTR_PI_DMAC_AXI_RD_RSP_PARERRS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 122),
+	C_CNTR_PI_DMAC_PAYLOAD_MWR_TLPS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 123),
+	C_CNTR_PI_DMAC_CE_MWR_TLPS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 124),
+	C_CNTR_PI_DMAC_IRQS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 125),
+	C_CNTR_PI_DMAC_DESC_COR_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 126),
+	C_CNTR_PI_DMAC_DESC_UCOR_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 127),
+	C_CNTR_ATU_MEM_COR_ERR_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 128),
+	C_CNTR_ATU_MEM_UCOR_ERR_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 129),
+	C_CNTR_ATU_CACHE_MISS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 130),
+	C_CNTR_ATU_CACHE_MISS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 131),
+	C_CNTR_ATU_CACHE_MISS_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 132),
+	C_CNTR_ATU_CACHE_MISS_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 133),
+	C_CNTR_ATU_CACHE_HIT_BASE_PAGE_SIZE_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 134),
+	C_CNTR_ATU_CACHE_HIT_BASE_PAGE_SIZE_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 135),
+	C_CNTR_ATU_CACHE_HIT_BASE_PAGE_SIZE_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 136),
+	C_CNTR_ATU_CACHE_HIT_BASE_PAGE_SIZE_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 137),
+	C_CNTR_ATU_CACHE_HIT_DERIVATIVE1_PAGE_SIZE_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 138),
+	C_CNTR_ATU_CACHE_HIT_DERIVATIVE1_PAGE_SIZE_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 139),
+	C_CNTR_ATU_CACHE_HIT_DERIVATIVE1_PAGE_SIZE_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 140),
+	C_CNTR_ATU_CACHE_HIT_DERIVATIVE1_PAGE_SIZE_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 141),
+	C_CNTR_ATU_CACHE_HIT_DERIVATIVE2_PAGE_SIZE_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 142),
+	C_CNTR_ATU_CACHE_HIT_DERIVATIVE2_PAGE_SIZE_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 143),
+	C_CNTR_ATU_CACHE_HIT_DERIVATIVE2_PAGE_SIZE_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 144),
+	C_CNTR_ATU_CACHE_HIT_DERIVATIVE2_PAGE_SIZE_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 145),
+	C_CNTR_ATU_CACHE_MISS_OXE
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 146),
+	C_CNTR_ATU_CACHE_MISS_IXE
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 147),
+	C_CNTR_ATU_CACHE_MISS_EE
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 148),
+	C_CNTR_ATU_ATS_TRANS_LATENCY_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 149),
+	C_CNTR_ATU_ATS_TRANS_LATENCY_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 150),
+	C_CNTR_ATU_ATS_TRANS_LATENCY_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 151),
+	C_CNTR_ATU_ATS_TRANS_LATENCY_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 152),
+	C_CNTR_ATU_NTA_TRANS_LATENCY_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 153),
+	C_CNTR_ATU_NTA_TRANS_LATENCY_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 154),
+	C_CNTR_ATU_NTA_TRANS_LATENCY_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 155),
+	C_CNTR_ATU_NTA_TRANS_LATENCY_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 156),
+	C_CNTR_ATU_CLIENT_REQ_OXE
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 157),
+	C_CNTR_ATU_CLIENT_REQ_IXE
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 158),
+	C_CNTR_ATU_CLIENT_REQ_EE
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 159),
+	C_CNTR_ATU_FILTERED_REQUESTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 160),
+	C_CNTR_ATU_ATS_PRS_ODP_LATENCY_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 161),
+	C_CNTR_ATU_ATS_PRS_ODP_LATENCY_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 162),
+	C_CNTR_ATU_ATS_PRS_ODP_LATENCY_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 163),
+	C_CNTR_ATU_ATS_PRS_ODP_LATENCY_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 164),
+	C_CNTR_ATU_NIC_PRI_ODP_LATENCY_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 165),
+	C_CNTR_ATU_NIC_PRI_ODP_LATENCY_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 166),
+	C_CNTR_ATU_NIC_PRI_ODP_LATENCY_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 167),
+	C_CNTR_ATU_NIC_PRI_ODP_LATENCY_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 168),
+	C_CNTR_ATU_ODP_REQUESTS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 169),
+	C_CNTR_ATU_ODP_REQUESTS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 170),
+	C_CNTR_ATU_ODP_REQUESTS_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 171),
+	C_CNTR_ATU_ODP_REQUESTS_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 172),
+	C_CNTR_ATU_CLIENT_RSP_NOT_OK_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 173),
+	C_CNTR_ATU_CLIENT_RSP_NOT_OK_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 174),
+	C_CNTR_ATU_CLIENT_RSP_NOT_OK_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 175),
+	C_CNTR_ATU_CLIENT_RSP_NOT_OK_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 176),
+	C_CNTR_ATU_CACHE_EVICTIONS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 177),
+	C_CNTR_ATU_ATS_INVAL_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 178),
+	C_CNTR_ATU_IMPLICIT_FLR_INVAL_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 179),
+	C_CNTR_ATU_IMPLICIT_ATS_EN_INVAL_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 180),
+	C_CNTR_ATU_ATUCQ_INVAL_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 181),
+	C_CNTR_ATU_PCIE_UNSUCCESS_CMPL
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 182),
+	C_CNTR_ATU_ATS_TRANS_ERR
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 183),
+	C_CNTR_ATU_PCIE_ERR_POISONED
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 184),
+	C_CNTR_ATU_ATS_DYNAMIC_STATE_CHANGE_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 185),
+	C_CNTR_ATU_AT_STALL_CCP
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 186),
+	C_CNTR_ATU_AT_STALL_NO_PTID
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 187),
+	C_CNTR_ATU_AT_STALL_NP_CDTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 188),
+	C_CNTR_ATU_AT_STALL_TARB_ARB
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 189),
+	C_CNTR_ATU_INVAL_STALL_ARB
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 190),
+	C_CNTR_ATU_INVAL_STALL_CMPL_WAIT
+			= (C_CNTR_TYPE_GROUP_OFFSET_MB	   + 191),
+	C_CNTR_CQ_SUCCESS_TX_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +   0),
+	C_CNTR_CQ_SUCCESS_TGT_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +   1),
+	C_CNTR_CQ_FAIL_TX_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +   2),
+	C_CNTR_CQ_FAIL_TGT_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +   3),
+	C_CNTR_CQ_MEM_COR_ERR_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +   4),
+	C_CNTR_CQ_MEM_UCOR_ERR_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +   5),
+	C_CNTR_CQ_RARB_LL_ERR_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +   6),
+	C_CNTR_CQ_RARB_ERR_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +   7),
+	C_CNTR_CQ_WR_PTR_UPDT_ERR_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +   8),
+	C_CNTR_CQ_NUM_TXQ_CMD_READS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  12),
+	C_CNTR_CQ_NUM_TXQ_CMD_READS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  13),
+	C_CNTR_CQ_NUM_TXQ_CMD_READS_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  14),
+	C_CNTR_CQ_NUM_TXQ_CMD_READS_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  15),
+	C_CNTR_CQ_NUM_TGQ_CMD_READS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  16),
+	C_CNTR_CQ_NUM_TGQ_CMD_READS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  17),
+	C_CNTR_CQ_NUM_TGQ_CMD_READS_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  18),
+	C_CNTR_CQ_NUM_TGQ_CMD_READS_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  19),
+	C_CNTR_CQ_NUM_TOU_CMD_READS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  20),
+	C_CNTR_CQ_NUM_TOU_CMD_READS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  21),
+	C_CNTR_CQ_NUM_TOU_CMD_READS_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  22),
+	C_CNTR_CQ_NUM_TOU_CMD_READS_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  23),
+	C_CNTR_CQ_TX_WAITING_ON_READ_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  24),
+	C_CNTR_CQ_TX_WAITING_ON_READ_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  25),
+	C_CNTR_CQ_TX_WAITING_ON_READ_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  26),
+	C_CNTR_CQ_TX_WAITING_ON_READ_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  27),
+	C_CNTR_CQ_TGT_WAITING_ON_READ_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  28),
+	C_CNTR_CQ_TGT_WAITING_ON_READ_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  29),
+	C_CNTR_CQ_TGT_WAITING_ON_READ_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  30),
+	C_CNTR_CQ_TGT_WAITING_ON_READ_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  31),
+	C_CNTR_CQ_NUM_TX_CMD_ALIGN_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  32),
+	C_CNTR_CQ_NUM_TX_CMD_OP_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  33),
+	C_CNTR_CQ_NUM_TX_CMD_ARG_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  34),
+	C_CNTR_CQ_NUM_TX_CMD_PERM_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  35),
+	C_CNTR_CQ_NUM_TGT_CMD_ARG_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  36),
+	C_CNTR_CQ_NUM_TGT_CMD_PERM_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  37),
+	C_CNTR_CQ_CQ_OXE_NUM_FLITS
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  38),
+	C_CNTR_CQ_CQ_OXE_NUM_STALLS
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  39),
+	C_CNTR_CQ_CQ_OXE_NUM_IDLES
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  40),
+	C_CNTR_CQ_CQ_TOU_NUM_FLITS
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  41),
+	C_CNTR_CQ_CQ_TOU_NUM_STALLS
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  42),
+	C_CNTR_CQ_CQ_TOU_NUM_IDLES
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  43),
+	C_CNTR_CQ_NUM_IDC_CMDS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  44),
+	C_CNTR_CQ_NUM_IDC_CMDS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  45),
+	C_CNTR_CQ_NUM_IDC_CMDS_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  46),
+	C_CNTR_CQ_NUM_IDC_CMDS_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  47),
+	C_CNTR_CQ_NUM_DMA_CMDS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  48),
+	C_CNTR_CQ_NUM_DMA_CMDS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  49),
+	C_CNTR_CQ_NUM_DMA_CMDS_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  50),
+	C_CNTR_CQ_NUM_DMA_CMDS_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  51),
+	C_CNTR_CQ_NUM_CQ_CMDS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  52),
+	C_CNTR_CQ_NUM_CQ_CMDS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  53),
+	C_CNTR_CQ_NUM_CQ_CMDS_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  54),
+	C_CNTR_CQ_NUM_CQ_CMDS_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  55),
+	C_CNTR_CQ_NUM_LL_CMDS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  56),
+	C_CNTR_CQ_NUM_LL_CMDS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  57),
+	C_CNTR_CQ_NUM_LL_CMDS_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  58),
+	C_CNTR_CQ_NUM_LL_CMDS_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  59),
+	C_CNTR_CQ_NUM_TGT_CMDS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  60),
+	C_CNTR_CQ_NUM_TGT_CMDS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  61),
+	C_CNTR_CQ_NUM_TGT_CMDS_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  62),
+	C_CNTR_CQ_NUM_TGT_CMDS_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  63),
+	C_CNTR_CQ_DMA_CMD_COUNTS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  64),
+	C_CNTR_CQ_DMA_CMD_COUNTS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  65),
+	C_CNTR_CQ_DMA_CMD_COUNTS_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  66),
+	C_CNTR_CQ_DMA_CMD_COUNTS_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  67),
+	C_CNTR_CQ_DMA_CMD_COUNTS_4
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  68),
+	C_CNTR_CQ_DMA_CMD_COUNTS_5
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  69),
+	C_CNTR_CQ_DMA_CMD_COUNTS_6
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  70),
+	C_CNTR_CQ_DMA_CMD_COUNTS_7
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  71),
+	C_CNTR_CQ_DMA_CMD_COUNTS_8
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  72),
+	C_CNTR_CQ_DMA_CMD_COUNTS_9
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  73),
+	C_CNTR_CQ_DMA_CMD_COUNTS_10
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  74),
+	C_CNTR_CQ_DMA_CMD_COUNTS_11
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  75),
+	C_CNTR_CQ_DMA_CMD_COUNTS_12
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  76),
+	C_CNTR_CQ_DMA_CMD_COUNTS_13
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  77),
+	C_CNTR_CQ_DMA_CMD_COUNTS_14
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  78),
+	C_CNTR_CQ_DMA_CMD_COUNTS_15
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  79),
+	C_CNTR_CQ_CQ_CMD_COUNTS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  80),
+	C_CNTR_CQ_CQ_CMD_COUNTS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  81),
+	C_CNTR_CQ_CQ_CMD_COUNTS_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  82),
+	C_CNTR_CQ_CQ_CMD_COUNTS_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  83),
+	C_CNTR_CQ_CQ_CMD_COUNTS_4
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  84),
+	C_CNTR_CQ_CQ_CMD_COUNTS_5
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  85),
+	C_CNTR_CQ_CQ_CMD_COUNTS_6
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  86),
+	C_CNTR_CQ_CQ_CMD_COUNTS_7
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  87),
+	C_CNTR_CQ_CQ_CMD_COUNTS_8
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  88),
+	C_CNTR_CQ_CQ_CMD_COUNTS_9
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  89),
+	C_CNTR_CQ_CQ_CMD_COUNTS_10
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  90),
+	C_CNTR_CQ_CQ_CMD_COUNTS_11
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  91),
+	C_CNTR_CQ_CQ_CMD_COUNTS_12
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  92),
+	C_CNTR_CQ_CQ_CMD_COUNTS_13
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  93),
+	C_CNTR_CQ_CQ_CMD_COUNTS_14
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  94),
+	C_CNTR_CQ_CQ_CMD_COUNTS_15
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  95),
+	C_CNTR_CQ_CYCLES_BLOCKED_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  96),
+	C_CNTR_CQ_CYCLES_BLOCKED_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  97),
+	C_CNTR_CQ_CYCLES_BLOCKED_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  98),
+	C_CNTR_CQ_CYCLES_BLOCKED_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   +  99),
+	C_CNTR_CQ_NUM_LL_OPS_SUCCESSFUL_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 112),
+	C_CNTR_CQ_NUM_LL_OPS_SUCCESSFUL_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 113),
+	C_CNTR_CQ_NUM_LL_OPS_SUCCESSFUL_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 114),
+	C_CNTR_CQ_NUM_LL_OPS_SUCCESSFUL_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 115),
+	C_CNTR_CQ_NUM_LL_OPS_REJECTED_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 116),
+	C_CNTR_CQ_NUM_LL_OPS_REJECTED_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 117),
+	C_CNTR_CQ_NUM_LL_OPS_REJECTED_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 118),
+	C_CNTR_CQ_NUM_LL_OPS_REJECTED_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 119),
+	C_CNTR_CQ_NUM_LL_OPS_SPLIT_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 120),
+	C_CNTR_CQ_NUM_LL_OPS_SPLIT_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 121),
+	C_CNTR_CQ_NUM_LL_OPS_SPLIT_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 122),
+	C_CNTR_CQ_NUM_LL_OPS_SPLIT_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 123),
+	C_CNTR_CQ_NUM_LL_OPS_RECEIVED_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 124),
+	C_CNTR_CQ_NUM_LL_OPS_RECEIVED_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 125),
+	C_CNTR_CQ_NUM_LL_OPS_RECEIVED_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 126),
+	C_CNTR_CQ_NUM_LL_OPS_RECEIVED_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 127),
+	C_CNTR_TOU_SUCCESS_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 128),
+	C_CNTR_TOU_FAIL_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 129),
+	C_CNTR_TOU_CQ_TOU_NUM_CMDS
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 132),
+	C_CNTR_TOU_CQ_TOU_NUM_STALLS
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 133),
+	C_CNTR_TOU_TOU_OXE_NUM_FLITS
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 134),
+	C_CNTR_TOU_TOU_OXE_NUM_STALLS
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 135),
+	C_CNTR_TOU_TOU_OXE_NUM_IDLES
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 136),
+	C_CNTR_TOU_LIST_REBUILD_CYCLES
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 137),
+	C_CNTR_TOU_CMD_FIFO_FULL_CYCLES
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 138),
+	C_CNTR_TOU_NUM_DOORBELL_WRITES
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 146),
+	C_CNTR_TOU_NUM_CT_UPDATES
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 147),
+	C_CNTR_TOU_NUM_TRIG_CMDS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 148),
+	C_CNTR_TOU_NUM_TRIG_CMDS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 149),
+	C_CNTR_TOU_NUM_TRIG_CMDS_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 150),
+	C_CNTR_TOU_NUM_TRIG_CMDS_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 151),
+	C_CNTR_TOU_NUM_LIST_REBUILDS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 152),
+	C_CNTR_TOU_NUM_LIST_REBUILDS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 153),
+	C_CNTR_TOU_NUM_LIST_REBUILDS_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 154),
+	C_CNTR_TOU_NUM_LIST_REBUILDS_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 155),
+	C_CNTR_TOU_CT_CMD_COUNTS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 156),
+	C_CNTR_TOU_CT_CMD_COUNTS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 157),
+	C_CNTR_TOU_CT_CMD_COUNTS_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 158),
+	C_CNTR_TOU_CT_CMD_COUNTS_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 159),
+	C_CNTR_TOU_CT_CMD_COUNTS_4
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 160),
+	C_CNTR_TOU_CT_CMD_COUNTS_5
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 161),
+	C_CNTR_TOU_CT_CMD_COUNTS_6
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 162),
+	C_CNTR_TOU_CT_CMD_COUNTS_7
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 163),
+	C_CNTR_TOU_CT_CMD_COUNTS_8
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 164),
+	C_CNTR_TOU_CT_CMD_COUNTS_9
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 165),
+	C_CNTR_TOU_CT_CMD_COUNTS_10
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 166),
+	C_CNTR_TOU_CT_CMD_COUNTS_11
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 167),
+	C_CNTR_TOU_CT_CMD_COUNTS_12
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 168),
+	C_CNTR_TOU_CT_CMD_COUNTS_13
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 169),
+	C_CNTR_TOU_CT_CMD_COUNTS_14
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 170),
+	C_CNTR_TOU_CT_CMD_COUNTS_15
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 171),
+	C_CNTR_PCT_MEM_COR_ERR_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 192),
+	C_CNTR_PCT_MEM_UCOR_ERR_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 193),
+	C_CNTR_PCT_REQ_ORDERED
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 194),
+	C_CNTR_PCT_REQ_UNORDERED
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 195),
+	C_CNTR_PCT_REQ_NO_RESPONSE
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 196),
+	C_CNTR_PCT_ETH_PACKETS
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 197),
+	C_CNTR_PCT_OPTIP_PACKETS
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 198),
+	C_CNTR_PCT_PTLS_RESPONSE
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 199),
+	C_CNTR_PCT_RESPONSES_RECEIVED
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 200),
+	C_CNTR_PCT_HRP_RESPONSES_RECEIVED
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 201),
+	C_CNTR_PCT_HRP_RSP_DISCARD_RECEIVED
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 202),
+	C_CNTR_PCT_HRP_RSP_ERR_RECEIVED
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 203),
+	C_CNTR_PCT_CONN_SCT_OPEN
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 204),
+	C_CNTR_PCT_CONN_TCT_OPEN
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 205),
+	C_CNTR_PCT_MST_HIT_ON_SOM
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 206),
+	C_CNTR_PCT_TRS_HIT_ON_REQ
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 207),
+	C_CNTR_PCT_CLS_REQ_MISS_TCT
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 208),
+	C_CNTR_PCT_CLEAR_SENT
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 209),
+	C_CNTR_PCT_CLOSE_SENT
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 210),
+	C_CNTR_PCT_ACCEL_CLOSE
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 211),
+	C_CNTR_PCT_CLEAR_CLOSE_DROP
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 212),
+	C_CNTR_PCT_REQ_SRC_ERROR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 213),
+	C_CNTR_PCT_BAD_SEQ_NACKS
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 214),
+	C_CNTR_PCT_NO_TCT_NACKS
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 215),
+	C_CNTR_PCT_NO_MST_NACKS
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 216),
+	C_CNTR_PCT_NO_TRS_NACKS
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 217),
+	C_CNTR_PCT_NO_MATCHING_TCT
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 218),
+	C_CNTR_PCT_RESOURCE_BUSY
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 219),
+	C_CNTR_PCT_ERR_NO_MATCHING_TRS
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 220),
+	C_CNTR_PCT_ERR_NO_MATCHING_MST
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 221),
+	C_CNTR_PCT_SPT_TIMEOUTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 222),
+	C_CNTR_PCT_SCT_TIMEOUTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 223),
+	C_CNTR_PCT_TCT_TIMEOUTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 224),
+	C_CNTR_PCT_RETRY_SRB_REQUESTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 225),
+	C_CNTR_PCT_RETRY_TRS_PUT
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 226),
+	C_CNTR_PCT_RETRY_MST_GET
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 227),
+	C_CNTR_PCT_CLR_CLS_STALLS
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 228),
+	C_CNTR_PCT_CLOSE_RSP_DROPS
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 229),
+	C_CNTR_PCT_TRS_RSP_NACK_DROPS
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 230),
+	C_CNTR_PCT_REQ_BLOCKED_CLOSING
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 231),
+	C_CNTR_PCT_REQ_BLOCKED_CLEARING
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 232),
+	C_CNTR_PCT_REQ_BLOCKED_RETRY
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 233),
+	C_CNTR_PCT_RSP_ERR_RCVD
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 234),
+	C_CNTR_PCT_RSP_DROPPED_TIMEOUT
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 235),
+	C_CNTR_PCT_RSP_DROPPED_TRY
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 236),
+	C_CNTR_PCT_RSP_DROPPED_CLS_TRY
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 237),
+	C_CNTR_PCT_RSP_DROPPED_INACTIVE
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 238),
+	C_CNTR_PCT_PCT_HNI_FLITS
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 239),
+	C_CNTR_PCT_PCT_HNI_STALLS
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 240),
+	C_CNTR_PCT_PCT_EE_EVENTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 241),
+	C_CNTR_PCT_PCT_EE_STALLS
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 242),
+	C_CNTR_PCT_PCT_CQ_NOTIFICATIONS
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 243),
+	C_CNTR_PCT_PCT_CQ_STALLS
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 244),
+	C_CNTR_PCT_PCT_MST_CMD0
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 245),
+	C_CNTR_PCT_PCT_MST_STALLS0
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 246),
+	C_CNTR_PCT_PCT_MST_CMD1
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 247),
+	C_CNTR_PCT_PCT_MST_STALLS1
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 248),
+	C_CNTR_PCT_SCT_STALL_STATE
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 249),
+	C_CNTR_PCT_TGT_CLS_ABORT
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 250),
+	C_CNTR_PCT_CLS_REQ_BAD_SEQNO_DROPS
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 251),
+	C_CNTR_PCT_REQ_TCT_TMOUT_DROPS
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 252),
+	C_CNTR_PCT_TRS_REPLAY_PEND_DROPS
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 253),
+	C_CNTR_PCT_REQ_RSP_LATENCY_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 256),
+	C_CNTR_PCT_REQ_RSP_LATENCY_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 257),
+	C_CNTR_PCT_REQ_RSP_LATENCY_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 258),
+	C_CNTR_PCT_REQ_RSP_LATENCY_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 259),
+	C_CNTR_PCT_REQ_RSP_LATENCY_4
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 260),
+	C_CNTR_PCT_REQ_RSP_LATENCY_5
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 261),
+	C_CNTR_PCT_REQ_RSP_LATENCY_6
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 262),
+	C_CNTR_PCT_REQ_RSP_LATENCY_7
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 263),
+	C_CNTR_PCT_REQ_RSP_LATENCY_8
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 264),
+	C_CNTR_PCT_REQ_RSP_LATENCY_9
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 265),
+	C_CNTR_PCT_REQ_RSP_LATENCY_10
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 266),
+	C_CNTR_PCT_REQ_RSP_LATENCY_11
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 267),
+	C_CNTR_PCT_REQ_RSP_LATENCY_12
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 268),
+	C_CNTR_PCT_REQ_RSP_LATENCY_13
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 269),
+	C_CNTR_PCT_REQ_RSP_LATENCY_14
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 270),
+	C_CNTR_PCT_REQ_RSP_LATENCY_15
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 271),
+	C_CNTR_PCT_REQ_RSP_LATENCY_16
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 272),
+	C_CNTR_PCT_REQ_RSP_LATENCY_17
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 273),
+	C_CNTR_PCT_REQ_RSP_LATENCY_18
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 274),
+	C_CNTR_PCT_REQ_RSP_LATENCY_19
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 275),
+	C_CNTR_PCT_REQ_RSP_LATENCY_20
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 276),
+	C_CNTR_PCT_REQ_RSP_LATENCY_21
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 277),
+	C_CNTR_PCT_REQ_RSP_LATENCY_22
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 278),
+	C_CNTR_PCT_REQ_RSP_LATENCY_23
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 279),
+	C_CNTR_PCT_REQ_RSP_LATENCY_24
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 280),
+	C_CNTR_PCT_REQ_RSP_LATENCY_25
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 281),
+	C_CNTR_PCT_REQ_RSP_LATENCY_26
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 282),
+	C_CNTR_PCT_REQ_RSP_LATENCY_27
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 283),
+	C_CNTR_PCT_REQ_RSP_LATENCY_28
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 284),
+	C_CNTR_PCT_REQ_RSP_LATENCY_29
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 285),
+	C_CNTR_PCT_REQ_RSP_LATENCY_30
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 286),
+	C_CNTR_PCT_REQ_RSP_LATENCY_31
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 287),
+	C_CNTR_PCT_HOST_ACCESS_LATENCY_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 288),
+	C_CNTR_PCT_HOST_ACCESS_LATENCY_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 289),
+	C_CNTR_PCT_HOST_ACCESS_LATENCY_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 290),
+	C_CNTR_PCT_HOST_ACCESS_LATENCY_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 291),
+	C_CNTR_PCT_HOST_ACCESS_LATENCY_4
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 292),
+	C_CNTR_PCT_HOST_ACCESS_LATENCY_5
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 293),
+	C_CNTR_PCT_HOST_ACCESS_LATENCY_6
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 294),
+	C_CNTR_PCT_HOST_ACCESS_LATENCY_7
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 295),
+	C_CNTR_PCT_HOST_ACCESS_LATENCY_8
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 296),
+	C_CNTR_PCT_HOST_ACCESS_LATENCY_9
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 297),
+	C_CNTR_PCT_HOST_ACCESS_LATENCY_10
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 298),
+	C_CNTR_PCT_HOST_ACCESS_LATENCY_11
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 299),
+	C_CNTR_PCT_HOST_ACCESS_LATENCY_12
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 300),
+	C_CNTR_PCT_HOST_ACCESS_LATENCY_13
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 301),
+	C_CNTR_PCT_HOST_ACCESS_LATENCY_14
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 302),
+	C_CNTR_PCT_HOST_ACCESS_LATENCY_15
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 303),
+	C_CNTR_EE_EVENTS_ENQUEUED_CNTR_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 320),
+	C_CNTR_EE_EVENTS_ENQUEUED_CNTR_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 321),
+	C_CNTR_EE_EVENTS_ENQUEUED_CNTR_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 322),
+	C_CNTR_EE_EVENTS_ENQUEUED_CNTR_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 323),
+	C_CNTR_EE_EVENTS_DROPPED_RSRVN_CNTR_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 324),
+	C_CNTR_EE_EVENTS_DROPPED_RSRVN_CNTR_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 325),
+	C_CNTR_EE_EVENTS_DROPPED_RSRVN_CNTR_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 326),
+	C_CNTR_EE_EVENTS_DROPPED_RSRVN_CNTR_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 327),
+	C_CNTR_EE_EVENTS_DROPPED_FC_SC_CNTR_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 328),
+	C_CNTR_EE_EVENTS_DROPPED_FC_SC_CNTR_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 329),
+	C_CNTR_EE_EVENTS_DROPPED_FC_SC_CNTR_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 330),
+	C_CNTR_EE_EVENTS_DROPPED_FC_SC_CNTR_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 331),
+	C_CNTR_EE_EVENTS_DROPPED_ORDINARY_CNTR_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 332),
+	C_CNTR_EE_EVENTS_DROPPED_ORDINARY_CNTR_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 333),
+	C_CNTR_EE_EVENTS_DROPPED_ORDINARY_CNTR_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 334),
+	C_CNTR_EE_EVENTS_DROPPED_ORDINARY_CNTR_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 335),
+	C_CNTR_EE_EQ_STATUS_UPDATE_CNTR_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 336),
+	C_CNTR_EE_EQ_STATUS_UPDATE_CNTR_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 337),
+	C_CNTR_EE_EQ_STATUS_UPDATE_CNTR_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 338),
+	C_CNTR_EE_EQ_STATUS_UPDATE_CNTR_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 339),
+	C_CNTR_EE_CBS_WRITTEN_CNTR_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 340),
+	C_CNTR_EE_CBS_WRITTEN_CNTR_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 341),
+	C_CNTR_EE_CBS_WRITTEN_CNTR_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 342),
+	C_CNTR_EE_CBS_WRITTEN_CNTR_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 343),
+	C_CNTR_EE_PARTIAL_CBS_WRITTEN_CNTR_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 344),
+	C_CNTR_EE_PARTIAL_CBS_WRITTEN_CNTR_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 345),
+	C_CNTR_EE_PARTIAL_CBS_WRITTEN_CNTR_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 346),
+	C_CNTR_EE_PARTIAL_CBS_WRITTEN_CNTR_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 347),
+	C_CNTR_EE_EXPIRED_CBS_WRITTEN_CNTR_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 348),
+	C_CNTR_EE_EXPIRED_CBS_WRITTEN_CNTR_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 349),
+	C_CNTR_EE_EXPIRED_CBS_WRITTEN_CNTR_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 350),
+	C_CNTR_EE_EXPIRED_CBS_WRITTEN_CNTR_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 351),
+	C_CNTR_EE_EQ_BUFFER_SWITCH_CNTR_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 352),
+	C_CNTR_EE_EQ_BUFFER_SWITCH_CNTR_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 353),
+	C_CNTR_EE_EQ_BUFFER_SWITCH_CNTR_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 354),
+	C_CNTR_EE_EQ_BUFFER_SWITCH_CNTR_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 355),
+	C_CNTR_EE_DEFERRED_EQ_SWITCH_CNTR_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 356),
+	C_CNTR_EE_DEFERRED_EQ_SWITCH_CNTR_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 357),
+	C_CNTR_EE_DEFERRED_EQ_SWITCH_CNTR_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 358),
+	C_CNTR_EE_DEFERRED_EQ_SWITCH_CNTR_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 359),
+	C_CNTR_EE_ADDR_TRANS_PREFETCH_CNTR_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 360),
+	C_CNTR_EE_ADDR_TRANS_PREFETCH_CNTR_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 361),
+	C_CNTR_EE_ADDR_TRANS_PREFETCH_CNTR_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 362),
+	C_CNTR_EE_ADDR_TRANS_PREFETCH_CNTR_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 363),
+	C_CNTR_EE_EQ_SW_STATE_WR_CNTR_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 364),
+	C_CNTR_EE_EQ_SW_STATE_WR_CNTR_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 365),
+	C_CNTR_EE_EQ_SW_STATE_WR_CNTR_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 366),
+	C_CNTR_EE_EQ_SW_STATE_WR_CNTR_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 367),
+	C_CNTR_EE_LPE_EVENT_REQ_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 368),
+	C_CNTR_EE_LPE_FE_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 369),
+	C_CNTR_EE_LPE_DD_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 370),
+	C_CNTR_EE_LPE_CE_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 371),
+	C_CNTR_EE_LPE_FE_STALL_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 372),
+	C_CNTR_EE_LPE_CE_STALL_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 373),
+	C_CNTR_EE_IXE_EVENT_REQ_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 374),
+	C_CNTR_EE_IXE_FE_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 375),
+	C_CNTR_EE_IXE_DD_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 376),
+	C_CNTR_EE_IXE_CE_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 377),
+	C_CNTR_EE_IXE_FE_STALL_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 378),
+	C_CNTR_EE_IXE_CE_STALL_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 379),
+	C_CNTR_EE_MST_EVENT_REQ_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 380),
+	C_CNTR_EE_MST_FE_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 381),
+	C_CNTR_EE_MST_DD_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 382),
+	C_CNTR_EE_MST_CE_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 383),
+	C_CNTR_EE_MST_FE_STALL_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 384),
+	C_CNTR_EE_MST_CE_STALL_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 385),
+	C_CNTR_EE_PCT_EVENT_REQ_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 386),
+	C_CNTR_EE_PCT_FE_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 387),
+	C_CNTR_EE_PCT_DD_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 388),
+	C_CNTR_EE_PCT_CE_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 389),
+	C_CNTR_EE_PCT_FE_STALL_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 390),
+	C_CNTR_EE_PCT_CE_STALL_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 391),
+	C_CNTR_EE_HNI_EVENT_REQ_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 392),
+	C_CNTR_EE_HNI_FE_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 393),
+	C_CNTR_EE_HNI_FE_STALL_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 394),
+	C_CNTR_EE_CQ_EVENT_REQ_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 395),
+	C_CNTR_EE_CQ_FE_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 396),
+	C_CNTR_EE_CQ_FE_STALL_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 397),
+	C_CNTR_EE_TS_FE_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 398),
+	C_CNTR_EE_TS_FE_STALL_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 399),
+	C_CNTR_EE_FE_ARB_OUT_EVENT_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 400),
+	C_CNTR_EE_FE_ARB_OUT_STALL_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 401),
+	C_CNTR_EE_CE_ARB_OUT_EVENT_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 402),
+	C_CNTR_EE_CE_ARB_OUT_STALL_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 403),
+	C_CNTR_EE_LPE_QUERY_EQ_NONE_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 404),
+	C_CNTR_EE_EQS_LPE_QUERY_REQ_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 405),
+	C_CNTR_EE_EQS_CSR_REQ_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 406),
+	C_CNTR_EE_EQS_CSR_STALL_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 407),
+	C_CNTR_EE_EQS_HWS_INIT_REQ_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 408),
+	C_CNTR_EE_EQS_HWS_INIT_STALL_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 409),
+	C_CNTR_EE_EQS_EXPIRED_CB_REQ_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 410),
+	C_CNTR_EE_EQS_EXPIRED_CB_STALL_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 411),
+	C_CNTR_EE_EQS_STS_UPDT_REQ_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 412),
+	C_CNTR_EE_EQS_STS_UPDT_STALL_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 413),
+	C_CNTR_EE_EQS_SWS_WR_REQ_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 414),
+	C_CNTR_EE_EQS_SWS_WR_STALL_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 415),
+	C_CNTR_EE_EQS_EVENT_REQ_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 416),
+	C_CNTR_EE_EQS_EVENT_STALL_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 417),
+	C_CNTR_EE_EQS_ARB_OUT_REQ_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 418),
+	C_CNTR_EE_EQS_FREE_CB_STALL_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 419),
+	C_CNTR_EE_ADDR_TRANS_REQ_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 420),
+	C_CNTR_EE_TARB_WR_REQ_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 421),
+	C_CNTR_EE_TARB_IRQ_REQ_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 422),
+	C_CNTR_EE_TARB_STALL_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 423),
+	C_CNTR_EE_EVENT_PUT_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 424),
+	C_CNTR_EE_EVENT_GET_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 425),
+	C_CNTR_EE_EVENT_ATOMIC_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 426),
+	C_CNTR_EE_EVENT_FETCH_ATOMIC_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 427),
+	C_CNTR_EE_EVENT_PUT_OVERFLOW_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 428),
+	C_CNTR_EE_EVENT_GET_OVERFLOW_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 429),
+	C_CNTR_EE_EVENT_ATOMIC_OVERFLOW_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 430),
+	C_CNTR_EE_EVENT_FETCH_ATOMIC_OVERFLOW_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 431),
+	C_CNTR_EE_EVENT_SEND_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 432),
+	C_CNTR_EE_EVENT_ACK_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 433),
+	C_CNTR_EE_EVENT_REPLY_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 434),
+	C_CNTR_EE_EVENT_LINK_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 435),
+	C_CNTR_EE_EVENT_SEARCH_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 436),
+	C_CNTR_EE_EVENT_STATE_CHANGE_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 437),
+	C_CNTR_EE_EVENT_UNLINK_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 438),
+	C_CNTR_EE_EVENT_RENDEZVOUS_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 439),
+	C_CNTR_EE_EVENT_ETHERNET_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 440),
+	C_CNTR_EE_EVENT_COMMAND_FAILURE_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 441),
+	C_CNTR_EE_EVENT_TRIGGERED_OP_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 442),
+	C_CNTR_EE_EVENT_ETHERNET_FGFC_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 443),
+	C_CNTR_EE_EVENT_PCT_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 444),
+	C_CNTR_EE_EVENT_MATCH_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 445),
+	C_CNTR_EE_EVENT_ERROR_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 452),
+	C_CNTR_EE_EVENT_TIMESTAMP_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 453),
+	C_CNTR_EE_EVENT_EQ_SWITCH_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 454),
+	C_CNTR_EE_EVENT_NULL_EVENT_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 455),
+	C_CNTR_EE_MEM_COR_ERR_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 456),
+	C_CNTR_EE_MEM_UCOR_ERR_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 457),
+	C_CNTR_EE_EQ_DSABLD_EVENT_ERR_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 458),
+	C_CNTR_EE_EQ_DSABLD_SWS_ERR_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 459),
+	C_CNTR_EE_EQ_DSABLD_LPEQ_ERR_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 460),
+	C_CNTR_EE_EQ_RSRVN_UFLW_ERR_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 461),
+	C_CNTR_EE_UNXPCTD_TRNSLTN_RSP_ERR_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 462),
+	C_CNTR_EE_RARB_HW_ERR_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 463),
+	C_CNTR_EE_RARB_SW_ERR_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 464),
+	C_CNTR_EE_TARB_ERR_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 465),
+	C_CNTR_EE_EQ_STATE_UCOR_ERR_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_CQ	   + 466),
+	C_CNTR_LPE_SUCCESS_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +   0),
+	C_CNTR_LPE_FAIL_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +   1),
+	C_CNTR_LPE_MEM_COR_ERR_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +   2),
+	C_CNTR_LPE_MEM_UCOR_ERR_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +   3),
+	C_CNTR_LPE_PUT_CMDS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +   5),
+	C_CNTR_LPE_RENDEZVOUS_PUT_CMDS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +   6),
+	C_CNTR_LPE_GET_CMDS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +   7),
+	C_CNTR_LPE_AMO_CMDS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +   8),
+	C_CNTR_LPE_FAMO_CMDS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +   9),
+	C_CNTR_LPE_ERR_ENTRY_NOT_FOUND_ETHERNET
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  15),
+	C_CNTR_LPE_ERR_PT_DISABLED_EQ_FULL
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  16),
+	C_CNTR_LPE_ERR_PT_DISABLED_REQ_EMPTY
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  17),
+	C_CNTR_LPE_ERR_PT_DISABLED_CANT_ALLOC_UNEXPECTED
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  18),
+	C_CNTR_LPE_ERR_PT_DISABLED_NO_MATCH_IN_OVERFLOW
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  19),
+	C_CNTR_LPE_ERR_EQ_DISABLED
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  20),
+	C_CNTR_LPE_ERR_OP_VIOLATION
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  21),
+	C_CNTR_LPE_ERR_ENTRY_NOT_FOUND_UNLINK_FAILED
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  22),
+	C_CNTR_LPE_ERR_ENTRY_NOT_FOUND_EQ_FULL
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  23),
+	C_CNTR_LPE_ERR_ENTRY_NOT_FOUND_REQ_EMPTY
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  24),
+	C_CNTR_LPE_ERR_ENTRY_NOT_FOUND_NO_MATCH_IN_OVERFLOW
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  25),
+	C_CNTR_LPE_ERR_ENTRY_NOT_FOUND_CANT_ALLOC_UNEXPECTED
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  26),
+	C_CNTR_LPE_ERR_INVALID_ENDPOINT
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  27),
+	C_CNTR_LPE_ERR_NO_SPACE_APPEND
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  28),
+	C_CNTR_LPE_ERR_NO_SPACE_NET
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  29),
+	C_CNTR_LPE_ERR_SEARCH_NO_MATCH
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  30),
+	C_CNTR_LPE_ERR_SETSTATE_NO_MATCH
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  31),
+	C_CNTR_LPE_ERR_SRC_ERROR
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  32),
+	C_CNTR_LPE_ERR_PTLTE_SW_MANAGED
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  33),
+	C_CNTR_LPE_ERR_ILLEGAL_OP
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  34),
+	C_CNTR_LPE_ERR_RESTRICTED_UNICAST
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  35),
+	C_CNTR_LPE_EVENT_PUT_OVERFLOW
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  41),
+	C_CNTR_LPE_EVENT_GET_OVERFLOW
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  43),
+	C_CNTR_LPE_EVENT_ATOMIC_OVERFLOW
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  45),
+	C_CNTR_LPE_PLEC_FREES_CSR
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  46),
+	C_CNTR_LPE_EVENT_FETCH_ATOMIC_OVERFLOW
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  47),
+	C_CNTR_LPE_EVENT_SEARCH
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  48),
+	C_CNTR_LPE_EVENT_RENDEZVOUS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  49),
+	C_CNTR_LPE_EVENT_LINK
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  50),
+	C_CNTR_LPE_EVENT_UNLINK
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  51),
+	C_CNTR_LPE_EVENT_STATECHANGE
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  52),
+	C_CNTR_LPE_PLEC_ALLOCS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  53),
+	C_CNTR_LPE_PLEC_FREES
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  54),
+	C_CNTR_LPE_PLEC_HITS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  55),
+	C_CNTR_LPE_CYC_NO_RDY_CDTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  56),
+	C_CNTR_LPE_CYC_RRQ_BLOCKED_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  57),
+	C_CNTR_LPE_CYC_RRQ_BLOCKED_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  58),
+	C_CNTR_LPE_CYC_RRQ_BLOCKED_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  59),
+	C_CNTR_LPE_CYC_RRQ_BLOCKED_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  60),
+	C_CNTR_LPE_CYC_BLOCKED_LOSSLESS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  61),
+	C_CNTR_LPE_CYC_BLOCKED_IXE_PUT
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  62),
+	C_CNTR_LPE_CYC_BLOCKED_IXE_GET
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  63),
+	C_CNTR_LPE_SEARCH_CMDS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  64),
+	C_CNTR_LPE_SEARCH_SUCCESS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  65),
+	C_CNTR_LPE_SEARCH_FAIL
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  66),
+	C_CNTR_LPE_SEARCH_DELETE_CMDS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  67),
+	C_CNTR_LPE_SEARCH_DELETE_SUCCESS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  68),
+	C_CNTR_LPE_SEARCH_DELETE_FAIL
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  69),
+	C_CNTR_LPE_UNLINK_CMDS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  70),
+	C_CNTR_LPE_UNLINK_SUCCESS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  71),
+	C_CNTR_LPE_NET_MATCH_REQUESTS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  72),
+	C_CNTR_LPE_NET_MATCH_REQUESTS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  73),
+	C_CNTR_LPE_NET_MATCH_REQUESTS_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  74),
+	C_CNTR_LPE_NET_MATCH_REQUESTS_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  75),
+	C_CNTR_LPE_NET_MATCH_SUCCESS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  76),
+	C_CNTR_LPE_NET_MATCH_SUCCESS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  77),
+	C_CNTR_LPE_NET_MATCH_SUCCESS_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  78),
+	C_CNTR_LPE_NET_MATCH_SUCCESS_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  79),
+	C_CNTR_LPE_NET_MATCH_USEONCE_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  80),
+	C_CNTR_LPE_NET_MATCH_USEONCE_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  81),
+	C_CNTR_LPE_NET_MATCH_USEONCE_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  82),
+	C_CNTR_LPE_NET_MATCH_USEONCE_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  83),
+	C_CNTR_LPE_NET_MATCH_LOCAL_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  84),
+	C_CNTR_LPE_NET_MATCH_LOCAL_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  85),
+	C_CNTR_LPE_NET_MATCH_LOCAL_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  86),
+	C_CNTR_LPE_NET_MATCH_LOCAL_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  87),
+	C_CNTR_LPE_NET_MATCH_PRIORITY_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  88),
+	C_CNTR_LPE_NET_MATCH_PRIORITY_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  89),
+	C_CNTR_LPE_NET_MATCH_PRIORITY_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  90),
+	C_CNTR_LPE_NET_MATCH_PRIORITY_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  91),
+	C_CNTR_LPE_NET_MATCH_OVERFLOW_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  92),
+	C_CNTR_LPE_NET_MATCH_OVERFLOW_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  93),
+	C_CNTR_LPE_NET_MATCH_OVERFLOW_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  94),
+	C_CNTR_LPE_NET_MATCH_OVERFLOW_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  95),
+	C_CNTR_LPE_NET_MATCH_REQUEST_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  96),
+	C_CNTR_LPE_NET_MATCH_REQUEST_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  97),
+	C_CNTR_LPE_NET_MATCH_REQUEST_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  98),
+	C_CNTR_LPE_NET_MATCH_REQUEST_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   +  99),
+	C_CNTR_LPE_APPEND_CMDS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 100),
+	C_CNTR_LPE_APPEND_CMDS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 101),
+	C_CNTR_LPE_APPEND_CMDS_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 102),
+	C_CNTR_LPE_APPEND_CMDS_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 103),
+	C_CNTR_LPE_APPEND_SUCCESS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 104),
+	C_CNTR_LPE_APPEND_SUCCESS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 105),
+	C_CNTR_LPE_APPEND_SUCCESS_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 106),
+	C_CNTR_LPE_APPEND_SUCCESS_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 107),
+	C_CNTR_LPE_SETSTATE_CMDS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 108),
+	C_CNTR_LPE_SETSTATE_CMDS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 109),
+	C_CNTR_LPE_SETSTATE_CMDS_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 110),
+	C_CNTR_LPE_SETSTATE_CMDS_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 111),
+	C_CNTR_LPE_SETSTATE_SUCCESS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 112),
+	C_CNTR_LPE_SETSTATE_SUCCESS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 113),
+	C_CNTR_LPE_SETSTATE_SUCCESS_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 114),
+	C_CNTR_LPE_SETSTATE_SUCCESS_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 115),
+	C_CNTR_LPE_SEARCH_NID_ANY_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 116),
+	C_CNTR_LPE_SEARCH_NID_ANY_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 117),
+	C_CNTR_LPE_SEARCH_NID_ANY_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 118),
+	C_CNTR_LPE_SEARCH_NID_ANY_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 119),
+	C_CNTR_LPE_SEARCH_PID_ANY_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 120),
+	C_CNTR_LPE_SEARCH_PID_ANY_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 121),
+	C_CNTR_LPE_SEARCH_PID_ANY_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 122),
+	C_CNTR_LPE_SEARCH_PID_ANY_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 123),
+	C_CNTR_LPE_SEARCH_RANK_ANY_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 124),
+	C_CNTR_LPE_SEARCH_RANK_ANY_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 125),
+	C_CNTR_LPE_SEARCH_RANK_ANY_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 126),
+	C_CNTR_LPE_SEARCH_RANK_ANY_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 127),
+	C_CNTR_LPE_RNDZV_PUTS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 128),
+	C_CNTR_LPE_RNDZV_PUTS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 129),
+	C_CNTR_LPE_RNDZV_PUTS_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 130),
+	C_CNTR_LPE_RNDZV_PUTS_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 131),
+	C_CNTR_LPE_RNDZV_PUTS_OFFLOADED_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 132),
+	C_CNTR_LPE_RNDZV_PUTS_OFFLOADED_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 133),
+	C_CNTR_LPE_RNDZV_PUTS_OFFLOADED_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 134),
+	C_CNTR_LPE_RNDZV_PUTS_OFFLOADED_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 135),
+	C_CNTR_LPE_NUM_TRUNCATED_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 136),
+	C_CNTR_LPE_NUM_TRUNCATED_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 137),
+	C_CNTR_LPE_NUM_TRUNCATED_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 138),
+	C_CNTR_LPE_NUM_TRUNCATED_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 139),
+	C_CNTR_LPE_UNEXPECTED_GET_AMO_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 140),
+	C_CNTR_LPE_UNEXPECTED_GET_AMO_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 141),
+	C_CNTR_LPE_UNEXPECTED_GET_AMO_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 142),
+	C_CNTR_LPE_UNEXPECTED_GET_AMO_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 143),
+	C_CNTR_IXE_MEM_COR_ERR_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 160),
+	C_CNTR_IXE_MEM_UCOR_ERR_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 161),
+	C_CNTR_IXE_PORT_DFA_MISMATCH
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 164),
+	C_CNTR_IXE_HDR_CHECKSUM_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 165),
+	C_CNTR_IXE_IPV4_CHECKSUM_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 166),
+	C_CNTR_IXE_HRP_REQ_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 167),
+	C_CNTR_IXE_IP_OPTIONS_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 168),
+	C_CNTR_IXE_GET_LEN_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 169),
+	C_CNTR_IXE_ROCE_ICRC_ERROR
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 170),
+	C_CNTR_IXE_PARSER_PAR_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 171),
+	C_CNTR_IXE_PBUF_RD_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 172),
+	C_CNTR_IXE_HDR_ECC_ERRORS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 173),
+	C_CNTR_IXE_RX_UDP_PKT
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 176),
+	C_CNTR_IXE_RX_TCP_PKT
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 177),
+	C_CNTR_IXE_RX_IPV4_PKT
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 178),
+	C_CNTR_IXE_RX_IPV6_PKT
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 179),
+	C_CNTR_IXE_RX_ROCE_PKT
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 180),
+	C_CNTR_IXE_RX_PTL_GEN_PKT
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 181),
+	C_CNTR_IXE_RX_PTL_SML_PKT
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 182),
+	C_CNTR_IXE_RX_PTL_UNRESTRICTED_PKT
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 183),
+	C_CNTR_IXE_RX_PTL_SMALLMSG_PKT
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 184),
+	C_CNTR_IXE_RX_PTL_CONTINUATION_PKT
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 185),
+	C_CNTR_IXE_RX_PTL_RESTRICTED_PKT
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 186),
+	C_CNTR_IXE_RX_PTL_CONNMGMT_PKT
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 187),
+	C_CNTR_IXE_RX_PTL_RESPONSE_PKT
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 188),
+	C_CNTR_IXE_RX_UNRECOGNIZED_PKT
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 189),
+	C_CNTR_IXE_RX_PTL_SML_AMO_PKT
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 190),
+	C_CNTR_IXE_RX_PTL_MSGS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 191),
+	C_CNTR_IXE_RX_PTL_MULTI_MSGS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 192),
+	C_CNTR_IXE_RX_PTL_MR_MSGS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 193),
+	C_CNTR_IXE_RX_PKT_DROP_PCT
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 194),
+	C_CNTR_IXE_RX_PKT_DROP_RMU_NORSP
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 195),
+	C_CNTR_IXE_RX_PKT_DROP_RMU_WRSP
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 196),
+	C_CNTR_IXE_RX_PKT_DROP_IXE_PARSER
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 197),
+	C_CNTR_IXE_RX_PKT_IPV4_OPTIONS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 198),
+	C_CNTR_IXE_RX_PKT_IPV6_OPTIONS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 199),
+	C_CNTR_IXE_RX_ETH_SEG
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 200),
+	C_CNTR_IXE_RX_ROCE_SEG
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 201),
+	C_CNTR_IXE_RX_ROCE_SPSEG
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 202),
+	C_CNTR_IXE_POOL_ECN_PKTS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 224),
+	C_CNTR_IXE_POOL_ECN_PKTS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 225),
+	C_CNTR_IXE_POOL_ECN_PKTS_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 226),
+	C_CNTR_IXE_POOL_ECN_PKTS_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 227),
+	C_CNTR_IXE_POOL_NO_ECN_PKTS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 228),
+	C_CNTR_IXE_POOL_NO_ECN_PKTS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 229),
+	C_CNTR_IXE_POOL_NO_ECN_PKTS_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 230),
+	C_CNTR_IXE_POOL_NO_ECN_PKTS_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 231),
+	C_CNTR_IXE_TC_REQ_ECN_PKTS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 232),
+	C_CNTR_IXE_TC_REQ_ECN_PKTS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 233),
+	C_CNTR_IXE_TC_REQ_ECN_PKTS_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 234),
+	C_CNTR_IXE_TC_REQ_ECN_PKTS_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 235),
+	C_CNTR_IXE_TC_REQ_ECN_PKTS_4
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 236),
+	C_CNTR_IXE_TC_REQ_ECN_PKTS_5
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 237),
+	C_CNTR_IXE_TC_REQ_ECN_PKTS_6
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 238),
+	C_CNTR_IXE_TC_REQ_ECN_PKTS_7
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 239),
+	C_CNTR_IXE_TC_REQ_NO_ECN_PKTS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 240),
+	C_CNTR_IXE_TC_REQ_NO_ECN_PKTS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 241),
+	C_CNTR_IXE_TC_REQ_NO_ECN_PKTS_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 242),
+	C_CNTR_IXE_TC_REQ_NO_ECN_PKTS_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 243),
+	C_CNTR_IXE_TC_REQ_NO_ECN_PKTS_4
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 244),
+	C_CNTR_IXE_TC_REQ_NO_ECN_PKTS_5
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 245),
+	C_CNTR_IXE_TC_REQ_NO_ECN_PKTS_6
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 246),
+	C_CNTR_IXE_TC_REQ_NO_ECN_PKTS_7
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 247),
+	C_CNTR_IXE_TC_RSP_ECN_PKTS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 248),
+	C_CNTR_IXE_TC_RSP_ECN_PKTS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 249),
+	C_CNTR_IXE_TC_RSP_ECN_PKTS_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 250),
+	C_CNTR_IXE_TC_RSP_ECN_PKTS_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 251),
+	C_CNTR_IXE_TC_RSP_ECN_PKTS_4
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 252),
+	C_CNTR_IXE_TC_RSP_ECN_PKTS_5
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 253),
+	C_CNTR_IXE_TC_RSP_ECN_PKTS_6
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 254),
+	C_CNTR_IXE_TC_RSP_ECN_PKTS_7
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 255),
+	C_CNTR_IXE_TC_RSP_NO_ECN_PKTS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 256),
+	C_CNTR_IXE_TC_RSP_NO_ECN_PKTS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 257),
+	C_CNTR_IXE_TC_RSP_NO_ECN_PKTS_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 258),
+	C_CNTR_IXE_TC_RSP_NO_ECN_PKTS_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 259),
+	C_CNTR_IXE_TC_RSP_NO_ECN_PKTS_4
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 260),
+	C_CNTR_IXE_TC_RSP_NO_ECN_PKTS_5
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 261),
+	C_CNTR_IXE_TC_RSP_NO_ECN_PKTS_6
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 262),
+	C_CNTR_IXE_TC_RSP_NO_ECN_PKTS_7
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 263),
+	C_CNTR_IXE_DISP_LPE_PUTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 264),
+	C_CNTR_IXE_DISP_LPE_PUTS_OK
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 265),
+	C_CNTR_IXE_DISP_LPE_AMOS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 266),
+	C_CNTR_IXE_DISP_LPE_AMOS_OK
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 267),
+	C_CNTR_IXE_DISP_MST_PUTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 268),
+	C_CNTR_IXE_DISP_MST_PUTS_OK
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 269),
+	C_CNTR_IXE_DISP_LPE_GETS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 270),
+	C_CNTR_IXE_DISP_LPE_GETS_OK
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 271),
+	C_CNTR_IXE_DISP_MST_GETS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 272),
+	C_CNTR_IXE_DISP_MST_GETS_OK
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 273),
+	C_CNTR_IXE_DISP_RPU_RESPS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 274),
+	C_CNTR_IXE_DISP_RPU_ERR_REQS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 275),
+	C_CNTR_IXE_DISP_DMAWR_REQS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 276),
+	C_CNTR_IXE_DISP_DMAWR_RESPS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 277),
+	C_CNTR_IXE_DISP_DMAWR_RESPS_OK
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 278),
+	C_CNTR_IXE_DISP_OXE_RESPS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 279),
+	C_CNTR_IXE_DISP_PCT_GETCOMP
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 280),
+	C_CNTR_IXE_DISP_ATU_REQS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 281),
+	C_CNTR_IXE_DISP_ATU_RESPS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 282),
+	C_CNTR_IXE_DISP_ATU_RESPS_OK
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 283),
+	C_CNTR_IXE_DISP_ETH_EVENTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 284),
+	C_CNTR_IXE_DISP_PUT_EVENTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 285),
+	C_CNTR_IXE_DISP_AMO_EVENTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 286),
+	C_CNTR_IXE_DISP_WR_CONFLICTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 287),
+	C_CNTR_IXE_DISP_AMO_CONFLICTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 288),
+	C_CNTR_IXE_DISP_STALL_CONFLICT
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 289),
+	C_CNTR_IXE_DISP_STALL_RESP_FIFO
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 290),
+	C_CNTR_IXE_DISP_STALL_ERR_FIFO
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 291),
+	C_CNTR_IXE_DISP_STALL_ATU_CDT
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 292),
+	C_CNTR_IXE_DISP_STALL_ATU_FIFO
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 293),
+	C_CNTR_IXE_DISP_STALL_GCOMP_FIFO
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 294),
+	C_CNTR_IXE_DISP_STALL_MDID_CDTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 295),
+	C_CNTR_IXE_DISP_STALL_MST_MATCH_FIFO
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 296),
+	C_CNTR_IXE_DISP_STALL_GRR_ID
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 297),
+	C_CNTR_IXE_DISP_STALL_PUT_RESP
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 298),
+	C_CNTR_IXE_DISP_ATU_FLUSH_REQS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 299),
+	C_CNTR_IXE_DMAWR_STALL_P_CDT
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 304),
+	C_CNTR_IXE_DMAWR_STALL_NP_CDT
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 305),
+	C_CNTR_IXE_DMAWR_STALL_NP_REQ_CNT
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 306),
+	C_CNTR_IXE_DMAWR_STALL_FTCH_AMO_CNT
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 307),
+	C_CNTR_IXE_DMAWR_P_PASS_NP_CNT
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 308),
+	C_CNTR_IXE_DMAWR_WRITE_REQS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 309),
+	C_CNTR_IXE_DMAWR_NIC_AMO_REQS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 310),
+	C_CNTR_IXE_DMAWR_CPU_AMO_REQS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 311),
+	C_CNTR_IXE_DMAWR_CPU_FTCH_AMO_REQS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 312),
+	C_CNTR_IXE_DMAWR_FLUSH_REQS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 313),
+	C_CNTR_IXE_DMAWR_REQ_NO_WRITE_REQS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 314),
+	C_CNTR_IXE_DMAWR_AMO_EX_INVALID
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 315),
+	C_CNTR_IXE_DMAWR_AMO_EX_OVERFLOW
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 316),
+	C_CNTR_IXE_DMAWR_AMO_EX_UNDERFLOW
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 317),
+	C_CNTR_IXE_DMAWR_AMO_EX_INEXACT
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 318),
+	C_CNTR_IXE_DMAWR_AMO_MISALIGNED
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 319),
+	C_CNTR_IXE_DMAWR_AMO_INVALID_OP
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 320),
+	C_CNTR_IXE_DMAWR_AMO_LEN_ERR
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 321),
+	C_CNTR_IXE_DMAWR_PCIE_UNSUCCESS_CMPL
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 322),
+	C_CNTR_IXE_DMAWR_PCIE_ERR_POISONED
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 323),
+	C_CNTR_RMU_PTL_SUCCESS_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 328),
+	C_CNTR_RMU_ENET_SUCCESS_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 329),
+	C_CNTR_RMU_MEM_COR_ERR_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 330),
+	C_CNTR_RMU_MEM_UCOR_ERR_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 331),
+	C_CNTR_RMU_PTL_INVLD_DFA_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 332),
+	C_CNTR_RMU_PTL_INVLD_VNI_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 333),
+	C_CNTR_RMU_PTL_NO_PTLTE_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 334),
+	C_CNTR_RMU_ENET_FRAME_REJECTED_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 335),
+	C_CNTR_RMU_ENET_PTLTE_SET_CTRL_ERR_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 336),
+	C_CNTR_PARBS_TARB_CQ_POSTED_PKTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 344),
+	C_CNTR_PARBS_TARB_CQ_NON_POSTED_PKTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 345),
+	C_CNTR_PARBS_TARB_CQ_SBE_CNT
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 346),
+	C_CNTR_PARBS_TARB_CQ_MBE_CNT
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 347),
+	C_CNTR_PARBS_TARB_EE_POSTED_PKTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 348),
+	C_CNTR_PARBS_TARB_EE_SBE_CNT
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 349),
+	C_CNTR_PARBS_TARB_EE_MBE_CNT
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 350),
+	C_CNTR_PARBS_TARB_IXE_POSTED_PKTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 351),
+	C_CNTR_PARBS_TARB_IXE_NON_POSTED_PKTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 352),
+	C_CNTR_PARBS_TARB_IXE_SBE_CNT
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 353),
+	C_CNTR_PARBS_TARB_IXE_MBE_CNT
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 354),
+	C_CNTR_PARBS_TARB_OXE_NON_POSTED_PKTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 355),
+	C_CNTR_PARBS_TARB_OXE_SBE_CNT
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 356),
+	C_CNTR_PARBS_TARB_OXE_MBE_CNT
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 357),
+	C_CNTR_PARBS_TARB_ATU_POSTED_PKTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 358),
+	C_CNTR_PARBS_TARB_ATU_NON_POSTED_PKTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 359),
+	C_CNTR_PARBS_TARB_ATU_SBE_CNT
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 360),
+	C_CNTR_PARBS_TARB_ATU_MBE_CNT
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 361),
+	C_CNTR_PARBS_TARB_PI_POSTED_PKTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 362),
+	C_CNTR_PARBS_TARB_PI_NON_POSTED_PKTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 363),
+	C_CNTR_PARBS_TARB_PI_POSTED_BLOCKED_CNT
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 364),
+	C_CNTR_PARBS_TARB_PI_NON_POSTED_BLOCKED_CNT
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 365),
+	C_CNTR_PARBS_TARB_CQ_POSTED_FIFO_SBE
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 366),
+	C_CNTR_PARBS_TARB_CQ_NON_POSTED_FIFO_SBE
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 367),
+	C_CNTR_PARBS_TARB_EE_POSTED_FIFO_SBE
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 368),
+	C_CNTR_PARBS_TARB_IXE_POSTED_FIFO_SBE
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 369),
+	C_CNTR_PARBS_TARB_IXE_NON_POSTED_FIFO_SBE
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 370),
+	C_CNTR_PARBS_TARB_OXE_NON_POSTED_FIFO_SBE
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 371),
+	C_CNTR_PARBS_TARB_ATU_POSTED_FIFO_SBE
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 372),
+	C_CNTR_PARBS_TARB_ATU_NON_POSTED_FIFO_SBE
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 373),
+	C_CNTR_PARBS_TARB_CQ_POSTED_FIFO_MBE
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 374),
+	C_CNTR_PARBS_TARB_CQ_NON_POSTED_FIFO_MBE
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 375),
+	C_CNTR_PARBS_TARB_EE_POSTED_FIFO_MBE
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 376),
+	C_CNTR_PARBS_TARB_IXE_POSTED_FIFO_MBE
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 377),
+	C_CNTR_PARBS_TARB_IXE_NON_POSTED_FIFO_MBE
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 378),
+	C_CNTR_PARBS_TARB_OXE_NON_POSTED_FIFO_MBE
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 379),
+	C_CNTR_PARBS_TARB_ATU_POSTED_FIFO_MBE
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 380),
+	C_CNTR_PARBS_TARB_ATU_NON_POSTED_FIFO_MBE
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 381),
+	C_CNTR_PARBS_RARB_PI_POSTED_PKTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 392),
+	C_CNTR_PARBS_RARB_PI_COMPLETION_PKTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 393),
+	C_CNTR_PARBS_RARB_PI_SBE_CNT
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 394),
+	C_CNTR_PARBS_RARB_PI_MBE_CNT
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 395),
+	C_CNTR_PARBS_RARB_CQ_POSTED_PKTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 396),
+	C_CNTR_PARBS_RARB_CQ_COMPLETION_PKTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 397),
+	C_CNTR_PARBS_RARB_EE_POSTED_PKTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 398),
+	C_CNTR_PARBS_RARB_IXE_POSTED_PKTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 399),
+	C_CNTR_PARBS_RARB_IXE_COMPLETION_PKTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 400),
+	C_CNTR_PARBS_RARB_OXE_COMPLETION_PKTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 401),
+	C_CNTR_PARBS_RARB_ATU_POSTED_PKTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 402),
+	C_CNTR_PARBS_RARB_ATU_COMPLETION_PKTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 403),
+	C_CNTR_MST_MEM_COR_ERR_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 408),
+	C_CNTR_MST_MEM_UCOR_ERR_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 409),
+	C_CNTR_MST_ALLOCATIONS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 410),
+	C_CNTR_MST_REQUESTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 411),
+	C_CNTR_MST_STALLED_WAITING_FOR_LPE
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 412),
+	C_CNTR_MST_STALLED_WAITING_GET_CRDTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 413),
+	C_CNTR_MST_STALLED_WAITING_PUT_CRDTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 414),
+	C_CNTR_MST_STALLED_WAITING_EE_CRDTS
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 415),
+	C_CNTR_MST_ERR_CANCELLED
+			= (C_CNTR_TYPE_GROUP_OFFSET_LPE	   + 424),
+	C_CNTR_HNI_COR_ECC_ERR_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +   0),
+	C_CNTR_HNI_UCOR_ECC_ERR_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +   1),
+	C_CNTR_HNI_TX_STALL_LLR
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +   2),
+	C_CNTR_HNI_RX_STALL_IXE_FIFO
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +   4),
+	C_CNTR_HNI_RX_STALL_IXE_PKTBUF_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +   8),
+	C_CNTR_HNI_RX_STALL_IXE_PKTBUF_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +   9),
+	C_CNTR_HNI_RX_STALL_IXE_PKTBUF_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  10),
+	C_CNTR_HNI_RX_STALL_IXE_PKTBUF_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  11),
+	C_CNTR_HNI_RX_STALL_IXE_PKTBUF_4
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  12),
+	C_CNTR_HNI_RX_STALL_IXE_PKTBUF_5
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  13),
+	C_CNTR_HNI_RX_STALL_IXE_PKTBUF_6
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  14),
+	C_CNTR_HNI_RX_STALL_IXE_PKTBUF_7
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  15),
+	C_CNTR_HNI_PFC_FIFO_OFLW_CNTR_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  16),
+	C_CNTR_HNI_PFC_FIFO_OFLW_CNTR_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  17),
+	C_CNTR_HNI_PFC_FIFO_OFLW_CNTR_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  18),
+	C_CNTR_HNI_PFC_FIFO_OFLW_CNTR_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  19),
+	C_CNTR_HNI_PFC_FIFO_OFLW_CNTR_4
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  20),
+	C_CNTR_HNI_PFC_FIFO_OFLW_CNTR_5
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  21),
+	C_CNTR_HNI_PFC_FIFO_OFLW_CNTR_6
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  22),
+	C_CNTR_HNI_PFC_FIFO_OFLW_CNTR_7
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  23),
+	C_CNTR_HNI_DISCARD_CNTR_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  24),
+	C_CNTR_HNI_DISCARD_CNTR_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  25),
+	C_CNTR_HNI_DISCARD_CNTR_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  26),
+	C_CNTR_HNI_DISCARD_CNTR_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  27),
+	C_CNTR_HNI_DISCARD_CNTR_4
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  28),
+	C_CNTR_HNI_DISCARD_CNTR_5
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  29),
+	C_CNTR_HNI_DISCARD_CNTR_6
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  30),
+	C_CNTR_HNI_DISCARD_CNTR_7
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  31),
+	C_CNTR_HNI_TX_OK_IEEE
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  32),
+	C_CNTR_HNI_TX_OK_OPT
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  33),
+	C_CNTR_HNI_TX_POISONED_IEEE
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  34),
+	C_CNTR_HNI_TX_POISONED_OPT
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  35),
+	C_CNTR_HNI_TX_OK_BROADCAST
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  36),
+	C_CNTR_HNI_TX_OK_MULTICAST
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  37),
+	C_CNTR_HNI_TX_OK_TAGGED
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  38),
+	C_CNTR_HNI_TX_OK_27
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  39),
+	C_CNTR_HNI_TX_OK_35
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  40),
+	C_CNTR_HNI_TX_OK_36_TO_63
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  41),
+	C_CNTR_HNI_TX_OK_64
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  42),
+	C_CNTR_HNI_TX_OK_65_TO_127
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  43),
+	C_CNTR_HNI_TX_OK_128_TO_255
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  44),
+	C_CNTR_HNI_TX_OK_256_TO_511
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  45),
+	C_CNTR_HNI_TX_OK_512_TO_1023
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  46),
+	C_CNTR_HNI_TX_OK_1024_TO_2047
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  47),
+	C_CNTR_HNI_TX_OK_2048_TO_4095
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  48),
+	C_CNTR_HNI_TX_OK_4096_TO_8191
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  49),
+	C_CNTR_HNI_TX_OK_8192_TO_MAX
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  50),
+	C_CNTR_HNI_RX_OK_IEEE
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  51),
+	C_CNTR_HNI_RX_OK_OPT
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  52),
+	C_CNTR_HNI_RX_BAD_IEEE
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  53),
+	C_CNTR_HNI_RX_BAD_OPT
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  54),
+	C_CNTR_HNI_RX_OK_BROADCAST
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  55),
+	C_CNTR_HNI_RX_OK_MULTICAST
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  56),
+	C_CNTR_HNI_RX_OK_MAC_CONTROL
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  57),
+	C_CNTR_HNI_RX_OK_BAD_OP_CODE
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  58),
+	C_CNTR_HNI_RX_OK_FLOW_CONTROL
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  59),
+	C_CNTR_HNI_RX_OK_TAGGED
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  60),
+	C_CNTR_HNI_RX_OK_LEN_TYPE_ERROR
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  61),
+	C_CNTR_HNI_RX_OK_TOO_LONG
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  62),
+	C_CNTR_HNI_RX_OK_UNDERSIZE
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  63),
+	C_CNTR_HNI_RX_FRAGMENT
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  64),
+	C_CNTR_HNI_RX_JABBER
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  65),
+	C_CNTR_HNI_RX_OK_27
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  66),
+	C_CNTR_HNI_RX_OK_35
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  67),
+	C_CNTR_HNI_RX_OK_36_TO_63
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  68),
+	C_CNTR_HNI_RX_OK_64
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  69),
+	C_CNTR_HNI_RX_OK_65_TO_127
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  70),
+	C_CNTR_HNI_RX_OK_128_TO_255
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  71),
+	C_CNTR_HNI_RX_OK_256_TO_511
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  72),
+	C_CNTR_HNI_RX_OK_512_TO_1023
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  73),
+	C_CNTR_HNI_RX_OK_1024_TO_2047
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  74),
+	C_CNTR_HNI_RX_OK_2048_TO_4095
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  75),
+	C_CNTR_HNI_RX_OK_4096_TO_8191
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  76),
+	C_CNTR_HNI_RX_OK_8192_TO_MAX
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  77),
+	C_CNTR_HNI_HRP_ACK
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  78),
+	C_CNTR_HNI_HRP_RESP
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  79),
+	C_CNTR_HNI_FGFC_PORT
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  80),
+	C_CNTR_HNI_FGFC_L2
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  81),
+	C_CNTR_HNI_FGFC_IPV4
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  82),
+	C_CNTR_HNI_FGFC_IPV6
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  83),
+	C_CNTR_HNI_FGFC_MATCH
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  84),
+	C_CNTR_HNI_FGFC_EVENT_XON
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  85),
+	C_CNTR_HNI_FGFC_EVENT_XOFF
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  86),
+	C_CNTR_HNI_FGFC_DISCARD
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  87),
+	C_CNTR_HNI_PAUSE_RECV_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  88),
+	C_CNTR_HNI_PAUSE_RECV_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  89),
+	C_CNTR_HNI_PAUSE_RECV_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  90),
+	C_CNTR_HNI_PAUSE_RECV_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  91),
+	C_CNTR_HNI_PAUSE_RECV_4
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  92),
+	C_CNTR_HNI_PAUSE_RECV_5
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  93),
+	C_CNTR_HNI_PAUSE_RECV_6
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  94),
+	C_CNTR_HNI_PAUSE_RECV_7
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  95),
+	C_CNTR_HNI_PAUSE_XOFF_SENT_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  96),
+	C_CNTR_HNI_PAUSE_XOFF_SENT_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  97),
+	C_CNTR_HNI_PAUSE_XOFF_SENT_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  98),
+	C_CNTR_HNI_PAUSE_XOFF_SENT_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   +  99),
+	C_CNTR_HNI_PAUSE_XOFF_SENT_4
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 100),
+	C_CNTR_HNI_PAUSE_XOFF_SENT_5
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 101),
+	C_CNTR_HNI_PAUSE_XOFF_SENT_6
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 102),
+	C_CNTR_HNI_PAUSE_XOFF_SENT_7
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 103),
+	C_CNTR_HNI_RX_PAUSED_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 104),
+	C_CNTR_HNI_RX_PAUSED_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 105),
+	C_CNTR_HNI_RX_PAUSED_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 106),
+	C_CNTR_HNI_RX_PAUSED_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 107),
+	C_CNTR_HNI_RX_PAUSED_4
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 108),
+	C_CNTR_HNI_RX_PAUSED_5
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 109),
+	C_CNTR_HNI_RX_PAUSED_6
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 110),
+	C_CNTR_HNI_RX_PAUSED_7
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 111),
+	C_CNTR_HNI_TX_PAUSED_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 112),
+	C_CNTR_HNI_TX_PAUSED_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 113),
+	C_CNTR_HNI_TX_PAUSED_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 114),
+	C_CNTR_HNI_TX_PAUSED_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 115),
+	C_CNTR_HNI_TX_PAUSED_4
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 116),
+	C_CNTR_HNI_TX_PAUSED_5
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 117),
+	C_CNTR_HNI_TX_PAUSED_6
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 118),
+	C_CNTR_HNI_TX_PAUSED_7
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 119),
+	C_CNTR_HNI_RX_PAUSED_STD
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 120),
+	C_CNTR_HNI_PAUSE_SENT
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 121),
+	C_CNTR_HNI_PAUSE_REFRESH
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 122),
+	C_CNTR_HNI_TX_STD_PADDED
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 124),
+	C_CNTR_HNI_TX_OPT_PADDED
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 125),
+	C_CNTR_HNI_TX_STD_SIZE_ERR
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 126),
+	C_CNTR_HNI_TX_OPT_SIZE_ERR
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 127),
+	C_CNTR_HNI_PKTS_SENT_BY_TC_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 128),
+	C_CNTR_HNI_PKTS_SENT_BY_TC_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 129),
+	C_CNTR_HNI_PKTS_SENT_BY_TC_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 130),
+	C_CNTR_HNI_PKTS_SENT_BY_TC_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 131),
+	C_CNTR_HNI_PKTS_SENT_BY_TC_4
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 132),
+	C_CNTR_HNI_PKTS_SENT_BY_TC_5
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 133),
+	C_CNTR_HNI_PKTS_SENT_BY_TC_6
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 134),
+	C_CNTR_HNI_PKTS_SENT_BY_TC_7
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 135),
+	C_CNTR_HNI_PKTS_RECV_BY_TC_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 136),
+	C_CNTR_HNI_PKTS_RECV_BY_TC_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 137),
+	C_CNTR_HNI_PKTS_RECV_BY_TC_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 138),
+	C_CNTR_HNI_PKTS_RECV_BY_TC_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 139),
+	C_CNTR_HNI_PKTS_RECV_BY_TC_4
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 140),
+	C_CNTR_HNI_PKTS_RECV_BY_TC_5
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 141),
+	C_CNTR_HNI_PKTS_RECV_BY_TC_6
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 142),
+	C_CNTR_HNI_PKTS_RECV_BY_TC_7
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 143),
+	C_CNTR_HNI_MULTICAST_PKTS_SENT_BY_TC_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 144),
+	C_CNTR_HNI_MULTICAST_PKTS_SENT_BY_TC_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 145),
+	C_CNTR_HNI_MULTICAST_PKTS_SENT_BY_TC_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 146),
+	C_CNTR_HNI_MULTICAST_PKTS_SENT_BY_TC_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 147),
+	C_CNTR_HNI_MULTICAST_PKTS_SENT_BY_TC_4
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 148),
+	C_CNTR_HNI_MULTICAST_PKTS_SENT_BY_TC_5
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 149),
+	C_CNTR_HNI_MULTICAST_PKTS_SENT_BY_TC_6
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 150),
+	C_CNTR_HNI_MULTICAST_PKTS_SENT_BY_TC_7
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 151),
+	C_CNTR_HNI_MULTICAST_PKTS_RECV_BY_TC_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 152),
+	C_CNTR_HNI_MULTICAST_PKTS_RECV_BY_TC_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 153),
+	C_CNTR_HNI_MULTICAST_PKTS_RECV_BY_TC_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 154),
+	C_CNTR_HNI_MULTICAST_PKTS_RECV_BY_TC_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 155),
+	C_CNTR_HNI_MULTICAST_PKTS_RECV_BY_TC_4
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 156),
+	C_CNTR_HNI_MULTICAST_PKTS_RECV_BY_TC_5
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 157),
+	C_CNTR_HNI_MULTICAST_PKTS_RECV_BY_TC_6
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 158),
+	C_CNTR_HNI_MULTICAST_PKTS_RECV_BY_TC_7
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 159),
+	C1_CNTR_HNI_PCS_PML_MBE_ERROR_CNT
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 160),
+	C1_CNTR_HNI_PCS_PML_SBE_ERROR_CNT
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 161),
+	C1_CNTR_HNI_PCS_CORRECTED_CW
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 162),
+	C1_CNTR_HNI_PCS_UNCORRECTED_CW
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 163),
+	C1_CNTR_HNI_PCS_GOOD_CW
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 164),
+	C1_CNTR_HNI_PCS_FECL_ERRORS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 165),
+	C1_CNTR_HNI_PCS_FECL_ERRORS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 166),
+	C1_CNTR_HNI_PCS_FECL_ERRORS_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 167),
+	C1_CNTR_HNI_PCS_FECL_ERRORS_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 168),
+	C1_CNTR_HNI_PCS_FECL_ERRORS_4
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 169),
+	C1_CNTR_HNI_PCS_FECL_ERRORS_5
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 170),
+	C1_CNTR_HNI_PCS_FECL_ERRORS_6
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 171),
+	C1_CNTR_HNI_PCS_FECL_ERRORS_7
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 172),
+	C1_CNTR_HNI_MAC_RX_ILLEGAL_SIZE
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 173),
+	C1_CNTR_HNI_MAC_RX_FRAGMENT
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 174),
+	C1_CNTR_HNI_MAC_RX_PREAMBLE_ERROR
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 175),
+	C1_CNTR_HNI_LLR_TX_LOOP_TIME_REQ_CTL_FR
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 176),
+	C1_CNTR_HNI_LLR_TX_LOOP_TIME_RSP_CTL_FR
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 177),
+	C1_CNTR_HNI_LLR_TX_INIT_CTL_OS
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 178),
+	C1_CNTR_HNI_LLR_TX_INIT_ECHO_CTL_OS
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 179),
+	C1_CNTR_HNI_LLR_TX_ACK_CTL_OS
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 180),
+	C1_CNTR_HNI_LLR_TX_NACK_CTL_OS
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 181),
+	C1_CNTR_HNI_LLR_TX_DISCARD
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 182),
+	C1_CNTR_HNI_LLR_TX_OK_LOSSY
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 183),
+	C1_CNTR_HNI_LLR_TX_OK_LOSSLESS
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 184),
+	C1_CNTR_HNI_LLR_TX_OK_LOSSLESS_RPT
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 185),
+	C1_CNTR_HNI_LLR_TX_POISONED_LOSSY
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 186),
+	C1_CNTR_HNI_LLR_TX_POISONED_LOSSLESS
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 187),
+	C1_CNTR_HNI_LLR_TX_POISONED_LOSSLESS_RPT
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 188),
+	C1_CNTR_HNI_LLR_TX_OK_BYPASS
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 189),
+	C1_CNTR_HNI_LLR_TX_REPLAY_EVENT
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 190),
+	C1_CNTR_HNI_LLR_RX_LOOP_TIME_REQ_CTL_FR
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 191),
+	C1_CNTR_HNI_LLR_RX_LOOP_TIME_RSP_CTL_FR
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 192),
+	C1_CNTR_HNI_LLR_RX_BAD_CTL_FR
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 193),
+	C1_CNTR_HNI_LLR_RX_INIT_CTL_OS
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 194),
+	C1_CNTR_HNI_LLR_RX_INIT_ECHO_CTL_OS
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 195),
+	C1_CNTR_HNI_LLR_RX_ACK_CTL_OS
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 196),
+	C1_CNTR_HNI_LLR_RX_NACK_CTL_OS
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 197),
+	C1_CNTR_HNI_LLR_RX_ACK_NACK_SEQ_ERR
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 198),
+	C1_CNTR_HNI_LLR_RX_OK_LOSSY
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 199),
+	C1_CNTR_HNI_LLR_RX_POISONED_LOSSY
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 200),
+	C1_CNTR_HNI_LLR_RX_BAD_LOSSY
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 201),
+	C1_CNTR_HNI_LLR_RX_OK_LOSSLESS
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 202),
+	C1_CNTR_HNI_LLR_RX_POISONED_LOSSLESS
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 203),
+	C1_CNTR_HNI_LLR_RX_BAD_LOSSLESS
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 204),
+	C1_CNTR_HNI_LLR_RX_EXPECTED_SEQ_GOOD
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 205),
+	C1_CNTR_HNI_LLR_RX_EXPECTED_SEQ_POISONED
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 206),
+	C1_CNTR_HNI_LLR_RX_EXPECTED_SEQ_BAD
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 207),
+	C1_CNTR_HNI_LLR_RX_UNEXPECTED_SEQ
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 208),
+	C1_CNTR_HNI_LLR_RX_DUPLICATE_SEQ
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 209),
+	C1_CNTR_HNI_LLR_RX_REPLAY_EVENT
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 210),
+	C1_CNTR_OXE_MEM_COR_ERR_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 211),
+	C1_CNTR_OXE_MEM_UCOR_ERR_CNTR
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 212),
+	C1_CNTR_OXE_ERR_NO_TRANSLATION
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 213),
+	C1_CNTR_OXE_ERR_INVALID_AC
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 214),
+	C1_CNTR_OXE_ERR_PAGE_PERM
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 215),
+	C1_CNTR_OXE_ERR_TA_ERROR
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 216),
+	C1_CNTR_OXE_ERR_PAGE_REQ
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 217),
+	C1_CNTR_OXE_ERR_PCI_EP
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 218),
+	C1_CNTR_OXE_ERR_PCI_CMPL
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 219),
+	C1_CNTR_OXE_STALL_PCT_BC_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 221),
+	C1_CNTR_OXE_STALL_PCT_BC_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 222),
+	C1_CNTR_OXE_STALL_PCT_BC_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 223),
+	C1_CNTR_OXE_STALL_PCT_BC_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 224),
+	C1_CNTR_OXE_STALL_PCT_BC_4
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 225),
+	C1_CNTR_OXE_STALL_PCT_BC_5
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 226),
+	C1_CNTR_OXE_STALL_PCT_BC_6
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 227),
+	C1_CNTR_OXE_STALL_PCT_BC_7
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 228),
+	C1_CNTR_OXE_STALL_PCT_BC_8
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 229),
+	C1_CNTR_OXE_STALL_PCT_BC_9
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 230),
+	C1_CNTR_OXE_STALL_PBUF_BC_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 231),
+	C1_CNTR_OXE_STALL_PBUF_BC_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 232),
+	C1_CNTR_OXE_STALL_PBUF_BC_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 233),
+	C1_CNTR_OXE_STALL_PBUF_BC_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 234),
+	C1_CNTR_OXE_STALL_PBUF_BC_4
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 235),
+	C1_CNTR_OXE_STALL_PBUF_BC_5
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 236),
+	C1_CNTR_OXE_STALL_PBUF_BC_6
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 237),
+	C1_CNTR_OXE_STALL_PBUF_BC_7
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 238),
+	C1_CNTR_OXE_STALL_PBUF_BC_8
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 239),
+	C1_CNTR_OXE_STALL_PBUF_BC_9
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 240),
+	C1_CNTR_OXE_STALL_TS_NO_OUT_CRD_TSC_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 241),
+	C1_CNTR_OXE_STALL_TS_NO_OUT_CRD_TSC_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 242),
+	C1_CNTR_OXE_STALL_TS_NO_OUT_CRD_TSC_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 243),
+	C1_CNTR_OXE_STALL_TS_NO_OUT_CRD_TSC_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 244),
+	C1_CNTR_OXE_STALL_TS_NO_OUT_CRD_TSC_4
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 245),
+	C1_CNTR_OXE_STALL_TS_NO_OUT_CRD_TSC_5
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 246),
+	C1_CNTR_OXE_STALL_TS_NO_OUT_CRD_TSC_6
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 247),
+	C1_CNTR_OXE_STALL_TS_NO_OUT_CRD_TSC_7
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 248),
+	C1_CNTR_OXE_STALL_TS_NO_OUT_CRD_TSC_8
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 249),
+	C1_CNTR_OXE_STALL_TS_NO_OUT_CRD_TSC_9
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 250),
+	C1_CNTR_OXE_STALL_TS_NO_IN_CRD_TSC_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 251),
+	C1_CNTR_OXE_STALL_TS_NO_IN_CRD_TSC_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 252),
+	C1_CNTR_OXE_STALL_TS_NO_IN_CRD_TSC_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 253),
+	C1_CNTR_OXE_STALL_TS_NO_IN_CRD_TSC_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 254),
+	C1_CNTR_OXE_STALL_TS_NO_IN_CRD_TSC_4
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 255),
+	C1_CNTR_OXE_STALL_TS_NO_IN_CRD_TSC_5
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 256),
+	C1_CNTR_OXE_STALL_TS_NO_IN_CRD_TSC_6
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 257),
+	C1_CNTR_OXE_STALL_TS_NO_IN_CRD_TSC_7
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 258),
+	C1_CNTR_OXE_STALL_TS_NO_IN_CRD_TSC_8
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 259),
+	C1_CNTR_OXE_STALL_TS_NO_IN_CRD_TSC_9
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 260),
+	C1_CNTR_OXE_STALL_WITH_NO_PCI_TAG
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 261),
+	C1_CNTR_OXE_STALL_WITH_NO_ATU_TAG
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 262),
+	C1_CNTR_OXE_STALL_STFWD_EOP
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 263),
+	C1_CNTR_OXE_STALL_PCIE_SCOREBOARD
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 264),
+	C1_CNTR_OXE_STALL_WR_CONFLICT_PKT_BUFF_BNK_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 265),
+	C1_CNTR_OXE_STALL_WR_CONFLICT_PKT_BUFF_BNK_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 266),
+	C1_CNTR_OXE_STALL_WR_CONFLICT_PKT_BUFF_BNK_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 267),
+	C1_CNTR_OXE_STALL_WR_CONFLICT_PKT_BUFF_BNK_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 268),
+	C1_CNTR_OXE_STALL_IDC_NO_BUFF_BC_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 269),
+	C1_CNTR_OXE_STALL_IDC_NO_BUFF_BC_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 270),
+	C1_CNTR_OXE_STALL_IDC_NO_BUFF_BC_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 271),
+	C1_CNTR_OXE_STALL_IDC_NO_BUFF_BC_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 272),
+	C1_CNTR_OXE_STALL_IDC_NO_BUFF_BC_4
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 273),
+	C1_CNTR_OXE_STALL_IDC_NO_BUFF_BC_5
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 274),
+	C1_CNTR_OXE_STALL_IDC_NO_BUFF_BC_6
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 275),
+	C1_CNTR_OXE_STALL_IDC_NO_BUFF_BC_7
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 276),
+	C1_CNTR_OXE_STALL_IDC_NO_BUFF_BC_8
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 277),
+	C1_CNTR_OXE_STALL_IDC_NO_BUFF_BC_9
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 278),
+	C1_CNTR_OXE_STALL_IDC_CMD_NO_DEQ
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 279),
+	C1_CNTR_OXE_STALL_NON_IDC_CMD_NO_DEQ
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 280),
+	C1_CNTR_OXE_STALL_FGFC_BLK_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 281),
+	C1_CNTR_OXE_STALL_FGFC_BLK_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 282),
+	C1_CNTR_OXE_STALL_FGFC_BLK_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 283),
+	C1_CNTR_OXE_STALL_FGFC_BLK_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 284),
+	C1_CNTR_OXE_STALL_FGFC_CNTRL_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 285),
+	C1_CNTR_OXE_STALL_FGFC_CNTRL_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 286),
+	C1_CNTR_OXE_STALL_FGFC_CNTRL_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 287),
+	C1_CNTR_OXE_STALL_FGFC_CNTRL_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 288),
+	C1_CNTR_OXE_STALL_FGFC_START_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 289),
+	C1_CNTR_OXE_STALL_FGFC_START_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 290),
+	C1_CNTR_OXE_STALL_FGFC_START_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 291),
+	C1_CNTR_OXE_STALL_FGFC_START_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 292),
+	C1_CNTR_OXE_STALL_FGFC_END_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 293),
+	C1_CNTR_OXE_STALL_FGFC_END_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 294),
+	C1_CNTR_OXE_STALL_FGFC_END_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 295),
+	C1_CNTR_OXE_STALL_FGFC_END_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 296),
+	C1_CNTR_OXE_STALL_HDR_ARB
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 297),
+	C1_CNTR_OXE_STALL_IOI_LAST_ORDERED
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 298),
+	C1_CNTR_OXE_IGNORE_ERRS
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 302),
+	C1_CNTR_OXE_IOI_DMA
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 303),
+	C1_CNTR_OXE_IOI_PKTS_ORDERED
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 304),
+	C1_CNTR_OXE_IOI_PKTS_UNORDERED
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 305),
+	C1_CNTR_OXE_PTL_TX_PUT_MSGS_TSC_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 306),
+	C1_CNTR_OXE_PTL_TX_PUT_MSGS_TSC_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 307),
+	C1_CNTR_OXE_PTL_TX_PUT_MSGS_TSC_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 308),
+	C1_CNTR_OXE_PTL_TX_PUT_MSGS_TSC_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 309),
+	C1_CNTR_OXE_PTL_TX_PUT_MSGS_TSC_4
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 310),
+	C1_CNTR_OXE_PTL_TX_PUT_MSGS_TSC_5
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 311),
+	C1_CNTR_OXE_PTL_TX_PUT_MSGS_TSC_6
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 312),
+	C1_CNTR_OXE_PTL_TX_PUT_MSGS_TSC_7
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 313),
+	C1_CNTR_OXE_PTL_TX_PUT_MSGS_TSC_8
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 314),
+	C1_CNTR_OXE_PTL_TX_PUT_MSGS_TSC_9
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 315),
+	C1_CNTR_OXE_PTL_TX_GET_MSGS_TSC_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 316),
+	C1_CNTR_OXE_PTL_TX_GET_MSGS_TSC_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 317),
+	C1_CNTR_OXE_PTL_TX_GET_MSGS_TSC_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 318),
+	C1_CNTR_OXE_PTL_TX_GET_MSGS_TSC_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 319),
+	C1_CNTR_OXE_PTL_TX_GET_MSGS_TSC_4
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 320),
+	C1_CNTR_OXE_PTL_TX_GET_MSGS_TSC_5
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 321),
+	C1_CNTR_OXE_PTL_TX_GET_MSGS_TSC_6
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 322),
+	C1_CNTR_OXE_PTL_TX_GET_MSGS_TSC_7
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 323),
+	C1_CNTR_OXE_PTL_TX_GET_MSGS_TSC_8
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 324),
+	C1_CNTR_OXE_PTL_TX_GET_MSGS_TSC_9
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 325),
+	C1_CNTR_OXE_PTL_TX_PUT_PKTS_TSC_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 326),
+	C1_CNTR_OXE_PTL_TX_PUT_PKTS_TSC_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 327),
+	C1_CNTR_OXE_PTL_TX_PUT_PKTS_TSC_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 328),
+	C1_CNTR_OXE_PTL_TX_PUT_PKTS_TSC_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 329),
+	C1_CNTR_OXE_PTL_TX_PUT_PKTS_TSC_4
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 330),
+	C1_CNTR_OXE_PTL_TX_PUT_PKTS_TSC_5
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 331),
+	C1_CNTR_OXE_PTL_TX_PUT_PKTS_TSC_6
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 332),
+	C1_CNTR_OXE_PTL_TX_PUT_PKTS_TSC_7
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 333),
+	C1_CNTR_OXE_PTL_TX_PUT_PKTS_TSC_8
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 334),
+	C1_CNTR_OXE_PTL_TX_PUT_PKTS_TSC_9
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 335),
+	C1_CNTR_OXE_PTL_TX_MR_MSGS
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 336),
+	C1_CNTR_OXE_NUM_HRP_CMDS
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 337),
+	C1_CNTR_OXE_CHANNEL_IDLE
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 338),
+	C1_CNTR_OXE_MCU_MEAS_0
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 339),
+	C1_CNTR_OXE_MCU_MEAS_1
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 340),
+	C1_CNTR_OXE_MCU_MEAS_2
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 341),
+	C1_CNTR_OXE_MCU_MEAS_3
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 342),
+	C1_CNTR_OXE_MCU_MEAS_4
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 343),
+	C1_CNTR_OXE_MCU_MEAS_5
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 344),
+	C1_CNTR_OXE_MCU_MEAS_6
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 345),
+	C1_CNTR_OXE_MCU_MEAS_7
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 346),
+	C1_CNTR_OXE_MCU_MEAS_8
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 347),
+	C1_CNTR_OXE_MCU_MEAS_9
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 348),
+	C1_CNTR_OXE_MCU_MEAS_10
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 349),
+	C1_CNTR_OXE_MCU_MEAS_11
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 350),
+	C1_CNTR_OXE_MCU_MEAS_12
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 351),
+	C1_CNTR_OXE_MCU_MEAS_13
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 352),
+	C1_CNTR_OXE_MCU_MEAS_14
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 353),
+	C1_CNTR_OXE_MCU_MEAS_15
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 354),
+	C1_CNTR_OXE_MCU_MEAS_16
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 355),
+	C1_CNTR_OXE_MCU_MEAS_17
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 356),
+	C1_CNTR_OXE_MCU_MEAS_18
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 357),
+	C1_CNTR_OXE_MCU_MEAS_19
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 358),
+	C1_CNTR_OXE_MCU_MEAS_20
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 359),
+	C1_CNTR_OXE_MCU_MEAS_21
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 360),
+	C1_CNTR_OXE_MCU_MEAS_22
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 361),
+	C1_CNTR_OXE_MCU_MEAS_23
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 362),
+	C1_CNTR_OXE_MCU_MEAS_24
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 363),
+	C1_CNTR_OXE_MCU_MEAS_25
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 364),
+	C1_CNTR_OXE_MCU_MEAS_26
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 365),
+	C1_CNTR_OXE_MCU_MEAS_27
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 366),
+	C1_CNTR_OXE_MCU_MEAS_28
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 367),
+	C1_CNTR_OXE_MCU_MEAS_29
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 368),
+	C1_CNTR_OXE_MCU_MEAS_30
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 369),
+	C1_CNTR_OXE_MCU_MEAS_31
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 370),
+	C1_CNTR_OXE_MCU_MEAS_32
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 371),
+	C1_CNTR_OXE_MCU_MEAS_33
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 372),
+	C1_CNTR_OXE_MCU_MEAS_34
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 373),
+	C1_CNTR_OXE_MCU_MEAS_35
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 374),
+	C1_CNTR_OXE_MCU_MEAS_36
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 375),
+	C1_CNTR_OXE_MCU_MEAS_37
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 376),
+	C1_CNTR_OXE_MCU_MEAS_38
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 377),
+	C1_CNTR_OXE_MCU_MEAS_39
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 378),
+	C1_CNTR_OXE_MCU_MEAS_40
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 379),
+	C1_CNTR_OXE_MCU_MEAS_41
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 380),
+	C1_CNTR_OXE_MCU_MEAS_42
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 381),
+	C1_CNTR_OXE_MCU_MEAS_43
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 382),
+	C1_CNTR_OXE_MCU_MEAS_44
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 383),
+	C1_CNTR_OXE_MCU_MEAS_45
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 384),
+	C1_CNTR_OXE_MCU_MEAS_46
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 385),
+	C1_CNTR_OXE_MCU_MEAS_47
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 386),
+	C1_CNTR_OXE_MCU_MEAS_48
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 387),
+	C1_CNTR_OXE_MCU_MEAS_49
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 388),
+	C1_CNTR_OXE_MCU_MEAS_50
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 389),
+	C1_CNTR_OXE_MCU_MEAS_51
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 390),
+	C1_CNTR_OXE_MCU_MEAS_52
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 391),
+	C1_CNTR_OXE_MCU_MEAS_53
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 392),
+	C1_CNTR_OXE_MCU_MEAS_54
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 393),
+	C1_CNTR_OXE_MCU_MEAS_55
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 394),
+	C1_CNTR_OXE_MCU_MEAS_56
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 395),
+	C1_CNTR_OXE_MCU_MEAS_57
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 396),
+	C1_CNTR_OXE_MCU_MEAS_58
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 397),
+	C1_CNTR_OXE_MCU_MEAS_59
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 398),
+	C1_CNTR_OXE_MCU_MEAS_60
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 399),
+	C1_CNTR_OXE_MCU_MEAS_61
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 400),
+	C1_CNTR_OXE_MCU_MEAS_62
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 401),
+	C1_CNTR_OXE_MCU_MEAS_63
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 402),
+	C1_CNTR_OXE_MCU_MEAS_64
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 403),
+	C1_CNTR_OXE_MCU_MEAS_65
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 404),
+	C1_CNTR_OXE_MCU_MEAS_66
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 405),
+	C1_CNTR_OXE_MCU_MEAS_67
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 406),
+	C1_CNTR_OXE_MCU_MEAS_68
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 407),
+	C1_CNTR_OXE_MCU_MEAS_69
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 408),
+	C1_CNTR_OXE_MCU_MEAS_70
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 409),
+	C1_CNTR_OXE_MCU_MEAS_71
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 410),
+	C1_CNTR_OXE_MCU_MEAS_72
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 411),
+	C1_CNTR_OXE_MCU_MEAS_73
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 412),
+	C1_CNTR_OXE_MCU_MEAS_74
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 413),
+	C1_CNTR_OXE_MCU_MEAS_75
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 414),
+	C1_CNTR_OXE_MCU_MEAS_76
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 415),
+	C1_CNTR_OXE_MCU_MEAS_77
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 416),
+	C1_CNTR_OXE_MCU_MEAS_78
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 417),
+	C1_CNTR_OXE_MCU_MEAS_79
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 418),
+	C1_CNTR_OXE_MCU_MEAS_80
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 419),
+	C1_CNTR_OXE_MCU_MEAS_81
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 420),
+	C1_CNTR_OXE_MCU_MEAS_82
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 421),
+	C1_CNTR_OXE_MCU_MEAS_83
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 422),
+	C1_CNTR_OXE_MCU_MEAS_84
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 423),
+	C1_CNTR_OXE_MCU_MEAS_85
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 424),
+	C1_CNTR_OXE_MCU_MEAS_86
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 425),
+	C1_CNTR_OXE_MCU_MEAS_87
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 426),
+	C1_CNTR_OXE_MCU_MEAS_88
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 427),
+	C1_CNTR_OXE_MCU_MEAS_89
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 428),
+	C1_CNTR_OXE_MCU_MEAS_90
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 429),
+	C1_CNTR_OXE_MCU_MEAS_91
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 430),
+	C1_CNTR_OXE_MCU_MEAS_92
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 431),
+	C1_CNTR_OXE_MCU_MEAS_93
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 432),
+	C1_CNTR_OXE_MCU_MEAS_94
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 433),
+	C1_CNTR_OXE_MCU_MEAS_95
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 434),
+	C1_CNTR_OXE_PRF_SET0_ST_READY
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 435),
+	C1_CNTR_OXE_PRF_SET0_ST_PCT_IDX_WAIT
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 436),
+	C1_CNTR_OXE_PRF_SET0_ST_PKTBUF_REQ
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 437),
+	C1_CNTR_OXE_PRF_SET0_ST_PKTBUF_GNT
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 438),
+	C1_CNTR_OXE_PRF_SET0_ST_HEADER
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 439),
+	C1_CNTR_OXE_PRF_SET0_ST_DMA_MDR
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 440),
+	C1_CNTR_OXE_PRF_SET0_ST_DMA_UPD
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 441),
+	C1_CNTR_OXE_PRF_SET0_PKTBUF_NA
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 442),
+	C1_CNTR_OXE_PRF_SET0_SPT_NA
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 443),
+	C1_CNTR_OXE_PRF_SET0_SMT_NA
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 444),
+	C1_CNTR_OXE_PRF_SET0_SRB_NA
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 445),
+	C1_CNTR_OXE_PRF_SET0_TS_SELECT
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 446),
+	C1_CNTR_OXE_PRF_SET0_OCC_HIST_BIN0
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 447),
+	C1_CNTR_OXE_PRF_SET0_OCC_HIST_BIN1
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 448),
+	C1_CNTR_OXE_PRF_SET0_OCC_HIST_BIN2
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 449),
+	C1_CNTR_OXE_PRF_SET0_OCC_HIST_BIN3
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 450),
+	C1_CNTR_OXE_PRF_SET1_ST_READY
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 451),
+	C1_CNTR_OXE_PRF_SET1_ST_PCT_IDX_WAIT
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 452),
+	C1_CNTR_OXE_PRF_SET1_ST_PKTBUF_REQ
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 453),
+	C1_CNTR_OXE_PRF_SET1_ST_PKTBUF_GNT
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 454),
+	C1_CNTR_OXE_PRF_SET1_ST_HEADER
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 455),
+	C1_CNTR_OXE_PRF_SET1_ST_DMA_MDR
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 456),
+	C1_CNTR_OXE_PRF_SET1_ST_DMA_UPD
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 457),
+	C1_CNTR_OXE_PRF_SET1_PKTBUF_NA
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 458),
+	C1_CNTR_OXE_PRF_SET1_SPT_NA
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 459),
+	C1_CNTR_OXE_PRF_SET1_SMT_NA
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 460),
+	C1_CNTR_OXE_PRF_SET1_SRB_NA
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 461),
+	C1_CNTR_OXE_PRF_SET1_TS_SELECT
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 462),
+	C1_CNTR_OXE_PRF_SET1_OCC_HIST_BIN0
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 463),
+	C1_CNTR_OXE_PRF_SET1_OCC_HIST_BIN1
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 464),
+	C1_CNTR_OXE_PRF_SET1_OCC_HIST_BIN2
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 465),
+	C1_CNTR_OXE_PRF_SET1_OCC_HIST_BIN3
+			= (C_CNTR_TYPE_GROUP_OFFSET_HNI	   + 466),
+};
+
+#endif
diff --git a/include/linux/hpe/cxi/cassini_csr_defaults.h b/include/linux/hpe/cxi/cassini_csr_defaults.h
new file mode 100644
index 000000000000..075bda4001da
--- /dev/null
+++ b/include/linux/hpe/cxi/cassini_csr_defaults.h
@@ -0,0 +1,703 @@
+/* SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause */
+/* Non-zero default values for Cassini CSR fields
+ * Copyright 2018-2020 Hewlett Packard Enterprise Development LP
+ *
+ * This file is generated with find-csr-defaults.py - Do not modify.
+ */
+
+#ifndef __CASSINI_HW_DEFAULTS_H
+#define __CASSINI_HW_DEFAULTS_H
+
+#define C_ATU_DBG_CFG_LSA_SEL_IDX__SELECT_IDX 0xf
+#define C_ATU_ERR_IRQA_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_ATU_ERR_IRQB_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_ATU_EXT_ERR_IRQA_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_ATU_EXT_ERR_IRQB_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_ATU_CFG_ATS__INVAL_BATCH_MODE 0x1
+#define C_ATU_CFG_ATS__NUM_XLATIONS_REQ 0x3
+#define C_ATU_CFG_ATS__INVAL_PROCESS_INTERVAL 0x1a
+#define C_ATU_CFG_PTID_POOL__SIZE 0x20
+#define C_ATU_CFG_ATS_DYNAMIC__PHW 0x100
+#define C_ATU_CFG_ATS_DYNAMIC__AHW 0x80
+#define C_ATU_CFG_ATS_DYNAMIC__ALW 0x20
+#define C_ATU_CFG_TARB_CDTS__POSTED_LIMIT 0x10
+#define C_ATU_CFG_TARB_CDTS__NON_POSTED_LIMIT 0x10
+#define C_ATU_CFG_ANCHOR_CHK__INTRVL 0x3e8
+#define C_ATU_CFG_XLATION_HIST__NTA_BIN1_MIN 0x10
+#define C_ATU_CFG_XLATION_HIST__NTA_BIN2_MIN 0x20
+#define C_ATU_CFG_XLATION_HIST__NTA_BIN3_MIN 0x30
+#define C_ATU_CFG_XLATION_HIST__ATS_BIN1_MIN 0x10
+#define C_ATU_CFG_XLATION_HIST__ATS_BIN2_MIN 0x20
+#define C_ATU_CFG_XLATION_HIST__ATS_BIN3_MIN 0x30
+#define C_ATU_CFG_XLATION_HIST__CNTR_INC 0x7
+#define C_ATU_CFG_ODP_HIST__NIC_PRI_BIN1_MIN 0x10
+#define C_ATU_CFG_ODP_HIST__NIC_PRI_BIN2_MIN 0x20
+#define C_ATU_CFG_ODP_HIST__NIC_PRI_BIN3_MIN 0x30
+#define C_ATU_CFG_ODP_HIST__ATS_PRS_BIN1_MIN 0x10
+#define C_ATU_CFG_ODP_HIST__ATS_PRS_BIN2_MIN 0x20
+#define C_ATU_CFG_ODP_HIST__ATS_PRS_BIN3_MIN 0x30
+#define C_ATU_CFG_ODP_HIST__CNTR_INC 0x7
+#define C1_ATU_CFG_ODP_DECOUPLE__FLUSH_REQ_DELAY 0x80
+#define C1_ATU_CFG_ODP_DECOUPLE__ENABLE 0x1
+#define C2_ATU_CFG_ODP_DECOUPLE__FLUSH_REQ_DELAY 0x3ff
+#define C2_ATU_CFG_ODP_DECOUPLE__ENABLE 0x1
+#define C2_ATU_CFG_ODP_DECOUPLE__WAIT_NO_TRIGGER 0x1
+#define C2_ATU_CFG_ODP_DECOUPLE__IP_ALL_CLIENT 0x1
+#define C2_ATU_CFG_ODP_DECOUPLE__TCAM_MASK 0x3
+#define C_ATU_STS_CMDPROC__ATUCQ_IDLE 0x1
+#define C_ATU_STS_CMDPROC__INBOUND_WAIT_IDLE 0x1
+#define C_ATU_STS_ODPQ__ODPQ_SPACE 0x8
+#define C_ATU_STS_TARB_CDTS__POSTED_AVAIL 0x1
+#define C_ATU_STS_TARB_CDTS__NON_POSTED_AVAIL 0x1
+#define C_ATU_STS_ATS_INVALQ__STATE_WAIT_TRIG 0x1
+#define C_ATU_STS_ODP_DECOUPLE__PREVIOUS_EPOCH 0x1
+#define C_CQ_DBG_CFG_LSA_SEL_IDX__SELECT_IDX 0x3f
+#define C_CQ_ERR_IRQA_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_CQ_ERR_IRQB_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_CQ_EXT_ERR_IRQA_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_CQ_EXT_ERR_IRQB_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_CQ_CFG_MEM_RD_THRESH__MAX_OUTSTANDING_REQ 0x1ff
+#define C_CQ_CFG_TLE_POOL__NUM_RESERVED 0x8
+#define C_CQ_CFG_TLE_POOL__MAX_ALLOC 0x200
+#define C_CQ_CFG_STS_TLE_SHARED__NUM_SHARED 0x7e0
+#define C_CQ_CFG_CREDIT_LIMITS__LPE_CMD_CREDITS 0x200
+#define C_CQ_CFG_CREDIT_LIMITS__LPE_RCV_FIFO_CREDITS 0xc
+#define C_CQ_CFG_CREDIT_LIMITS__EE_EVENT_CREDITS 0x10
+#define C_CQ_CFG_CREDIT_LIMITS__TOU_FQ_CREDITS 0x40
+#define C_CQ_CFG_CREDIT_LIMITS__TARB_P_CREDITS 0x10
+#define C_CQ_CFG_CREDIT_LIMITS__TARB_NP_CREDITS 0x10
+#define C_CQ_CFG_CREDIT_LIMITS__PREFETCH_TOU_CREDITS 0x10
+#define C_CQ_CFG_CREDIT_LIMITS__TOU_WB_CREDITS 0x10
+#define C_CQ_CFG_CREDIT_LIMITS__TOU_EVENT_CREDITS 0x4
+#define C_CQ_CFG_CREDIT_LIMITS__TGQ_CMD_FAIL_EVENT_CREDITS 0x4
+#define C_CQ_CFG_CREDIT_LIMITS__TXQ_CMD_FAIL_EVENT_CREDITS 0xc
+#define C_CQ_CFG_CREDIT_LIMITS__TOU_CMD_FAIL_EVENT_CREDITS 0x4
+#define C_CQ_CFG_CREDIT_LIMITS__FQ_TOT_CREDITS 0x100
+#define C_CQ_TXQ_WRPTR_TABLE__MEM_Q_WR_PTR 0x4
+#define C_CQ_TXQ_RDPTR_TABLE__MEM_Q_RD_PTR 0x4
+#define C_CQ_TXQ_PREPTR_TABLE__MEM_Q_PRE_PTR 0x4
+#define C_CQ_TGQ_WRPTR_TABLE__MEM_Q_WR_PTR 0x4
+#define C_CQ_TGQ_RDPTR_TABLE__MEM_Q_RD_PTR 0x4
+#define C_CQ_TGQ_PREPTR_TABLE__MEM_Q_PRE_PTR 0x4
+#define C_CQ_CFG_CQ_POLICY__POLICY_0_SHIFT 0x4
+#define C_CQ_CFG_CQ_POLICY__POLICY_1_SHIFT 0x4
+#define C_CQ_CFG_CQ_POLICY__POLICY_2_SHIFT 0x4
+#define C_CQ_CFG_CQ_POLICY__POLICY_3_SHIFT 0x4
+#define C_CQ_CFG_FQ_THRESH_TABLE__THRESH 0x400000
+#define C_CQ_CFG_OCU_HASH_MASK__DFA 0xfffff000
+#define C_CQ_CFG_OCU_HASH_MASK__VNI 0xffff
+#define C_CQ_CFG_OCU_HASH_MASK__DSCP 0x3f
+#define C_CQ_CFG_OCUSET_FQ_TABLE__FQ_COUNT 0x1
+#define C_CQ_CFG_FQ_RESRV__MAX_ALLOC 0x100
+#define C_CQ_CFG_FQ_POLICY__FQ_1_ACTIVE 0x80
+#define C_CQ_CFG_FQ_POLICY__FQ_2_ACTIVE 0x55
+#define C_CQ_CFG_FQ_POLICY__FQ_3_ACTIVE 0x40
+#define C_CQ_CFG_FQ_POLICY__FQ_4_ACTIVE 0x33
+#define C_CQ_CFG_FQ_POLICY__FQ_5_ACTIVE 0x2a
+#define C_CQ_CFG_FQ_POLICY__FQ_6_ACTIVE 0x24
+#define C_CQ_CFG_FQ_POLICY__FQ_7_ACTIVE 0x20
+#define C_CQ_CFG_FQ_POLICY__FQ_8_ACTIVE 0x20
+#define C_CQ_CFG_FQ_LOAD__PUT_HDR_LEN 0x40
+#define C_CQ_CFG_FQ_LOAD__GET_HDR_LEN 0x40
+#define C_CQ_DBG_TRIG_OPS_QUEUE_ST__EMPTY 0x1
+#define C_CQ_DBG_PFQ_QUEUE_ST__EMPTY 0x1
+#define C_CQ_DBG_TXFQ_QUEUE_ST__EMPTY 0x1
+#define C_CQ_DBG_TUPFQ_QUEUE_ST__EMPTY 0x1
+#define C_CQ_DBG_TUFQ_QUEUE_ST__EMPTY 0x1
+#define C_CQ_DBG_CFG_LSA_TRIG_CMN__TRIG_RESET 0x1
+#define C_EE_DBG_CFG_LSA_SEL_IDX__SELECT_IDX 0x1f
+#define C_EE_ERR_IRQA_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_EE_ERR_IRQB_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_EE_EXT_ERR_IRQA_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_EE_EXT_ERR_IRQB_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_EE_CFG_CREDIT_LIMITS__CQ_CT_CREDITS 0x40
+#define C_EE_CFG_CREDIT_LIMITS__TARB_CREDITS 0x10
+#define C_EE_CFG_MAX_ECBS_LIMIT__MAX_ECBS 0x100
+#define C_EE_CFG_LATENCY_MONITOR__GRANULARITY 0x32
+#define C_EE_CFG_LATENCY_MONITOR__LT_LIMIT 0x1ff
+#define C_EE_CFG_LATENCY_MONITOR__GRANULARITY_A 0x32
+#define C_EE_CFG_LATENCY_MONITOR__LT_LIMIT_A 0x1ff
+#define C_EE_CFG_LATENCY_MONITOR__GRANULARITY_B 0x32
+#define C_EE_CFG_LATENCY_MONITOR__LT_LIMIT_B 0x1ff
+#define C_EE_CFG_LATENCY_MONITOR__THRESH_A 0x100
+#define C_EE_CFG_LATENCY_MONITOR__THRESH_B 0x100
+#define C_EE_CFG_EVENT_OVERRIDES__PCT_SET_CT_SEND 0x1
+#define C_EE_CFG_EVENT_OVERRIDES__PCT_SET_CT_ACK 0x1
+#define C_EE_CFG_EVENT_OVERRIDES__PCT_SET_CT_REPLY 0x1
+#define C_EE_CFG_EVENT_OVERRIDES__LPE_SET_CT_COMM 0x1
+#define C_EE_CFG_EVENT_OVERRIDES__LPE_SET_CT_OVERFLOW 0x1
+#define C_EE_CFG_EVENT_OVERRIDES__IXE_SET_CT_COMM 0x1
+#define C_EE_CFG_EVENT_OVERRIDES__IXE_COUNT_ENET 0x1
+#define C_EE_CFG_EVENT_OVERRIDES__MST_SET_CT_COMM 0x1
+#define C_EE_STS_INIT_DONE__WARM_RESET 0x1
+#define C_EE_DBG_CFG_LSA_TRIG_CMN__TRIG_RESET 0x1
+#define C_HNI_DBG_CFG_LSA_SEL_IDX__SELECT_IDX 0xf
+#define C_HNI_ERR_IRQA_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_HNI_ERR_IRQB_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_HNI_CFG_CDT__IXE_CDTS 0x20
+#define C_HNI_CFG_CDT__HRP_CDTS 0x10
+#define C_HNI_CFG_CDT__LLR_CDTS 0x8
+#define C_HNI_CFG_CDT__EE_CDTS 0x10
+#define C_HNI_CFG_CDT__IXE_PBUF_SIZE 0x800
+#define C_HNI_CFG_FGFC_DMAC__DMAC 0x180c200000e
+#define C_HNI_CFG_FGFC_HDR__ETHER_TYPE 0x88b7
+#define C_HNI_CFG_FGFC_HDR__OUI_PROTOCOL_ID 0xeab
+#define C_HNI_CFG_FGFC__L2_TYPE 0x1
+#define C_HNI_CFG_FGFC__IPV4_TYPE 0x2
+#define C_HNI_CFG_FGFC__IPV6_TYPE 0x3
+#define C_HNI_CFG_FGFC__PORTALS_EN 0x1
+#define C_HNI_CFG_FGFC__L2_EN 0x1
+#define C_HNI_CFG_FGFC__IPV4_EN 0x1
+#define C_HNI_CFG_FGFC__IPV6_EN 0x1
+#define C_HNI_CFG_FGFC__CACHE_EN 0x1
+#define C_HNI_CFG_HRP_HDR__PORTALS_PROTOCOL 0x77
+#define C_HNI_CFG_HRP_HDR__PKT_TYPE 0x71
+#define C_HNI_CFG_TXTS_L2_MATCH__DMAC 0x180c200000e
+#define C_HNI_CFG_TXTS_L2_MATCH__ETHERTYPE 0x88f7
+#define C_HNI_CFG_RXTS_L2_MATCH__DMAC 0x180c200000e
+#define C_HNI_CFG_RXTS_L2_MATCH__ETHERTYPE 0x88f7
+#define C_HNI_CFG_PAUSE_QUANTA__SUB_VALUE 0x7d000
+#define C_HNI_CFG_PAUSE_QUANTA__SUB_PERIOD 0x14
+#define C_HNI_CFG_PAUSE_TIMING__PAUSE_PERIOD 0xffff
+#define C_HNI_CFG_PAUSE_TIMING__PAUSE_REPEAT_PERIOD 0xf000
+#define C_HNI_CFG_PAUSE_DMAC__DMAC 0x180c2000001
+#define C_HNI_CFG_PAUSE_TX_CTRL__MAC_CNTL_OPCODE 0x1
+#define C_HNI_CFG_PAUSE_TX_CTRL__MAC_CNTL_TYPE 0x8808
+#define C_HNI_CFG_PORT_PKT__VS_VERSION 0x3
+#define C_HNI_CFG_PORT_PKT__PORTALS_PROTOCOL 0x77
+#define C_HNI_CFG_MAX_SIZES__MAX_STD_SIZE 0x2800
+#define C_HNI_CFG_MAX_SIZES__MAX_OPT_SIZE 0x2800
+#define C_HNI_CFG_MAX_SIZES__MAX_PORTALS_SIZE 0x2800
+#define C_HNI_CFG_TX_SIZE__PAD_SIZE_OPT 0x10
+#define C_HNI_CFG_TX_SIZE__PAD_SIZE_STD 0x40
+#define C_HNI_CFG_TX_SIZE__MIN_SIZE_OPT 0x10
+#define C_HNI_CFG_TX_SIZE__MIN_SIZE_STD 0x20
+#define C_HNI_CFG_TX_SIZE__MAX_SIZE_OPT 0x251c
+#define C_HNI_CFG_TX_SIZE__MAX_SIZE_STD 0x251c
+#define C_HNI_CFG_PBUF__STATIC_RSVD 0x80
+#define C_HNI_CFG_PBUF__MTU 0x50
+#define C_HNI_CFG_SEND__SBR 0x1
+#define C_HNI_UC_SBR_INTR__SEND_SBR 0x1
+#define C_HNI_PML_DBG_CFG_LSA_SEL_IDX__SELECT_IDX 0x1f
+#define C1_HNI_PML_ERR_IRQA_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define SS2_PORT_PML_ERR_IRQA_MSK__ERR_IRQ_MSK_W0 0xffffffffffffffff
+#define SS2_PORT_PML_ERR_IRQA_MSK__ERR_IRQ_MSK_W1 0xffffffffffffffff
+#define SS2_PORT_PML_ERR_IRQA_MSK__ERR_IRQ_MSK_W2 0xffffffffffffffff
+#define SS2_PORT_PML_ERR_IRQA_MSK__ERR_IRQ_MSK_W3 0xffffffffffffffff
+#define C1_HNI_PML_ERR_IRQB_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define SS2_PORT_PML_ERR_IRQB_MSK__ERR_IRQ_MSK_W0 0xffffffffffffffff
+#define SS2_PORT_PML_ERR_IRQB_MSK__ERR_IRQ_MSK_W1 0xffffffffffffffff
+#define SS2_PORT_PML_ERR_IRQB_MSK__ERR_IRQ_MSK_W2 0xffffffffffffffff
+#define SS2_PORT_PML_ERR_IRQB_MSK__ERR_IRQ_MSK_W3 0xffffffffffffffff
+#define C_HNI_PML_CFG_GENERAL__CLOCK_PERIOD_PS 0x3e8
+#define C1_HNI_PML_CFG_SERDES_CORE_INTERRUPT__SET_INTERRUPT_DELAY 0x4
+#define C1_HNI_PML_CFG_SERDES_CORE_INTERRUPT__CLEAR_INTERRUPT_DELAY 0x4
+#define C1_HNI_PML_CFG_SERDES_CORE_INTERRUPT__CAPTURE_INTERRUPT_DATA_DELAY 0x4
+#define SS2_PORT_PML_CFG_PCS__PCS_MODE 0x4
+#define C1_HNI_PML_CFG_PCS_AUTONEG__RESET 0x1
+#define SS2_PORT_PML_CFG_PCS_AUTONEG__RESET 0x1
+#define C1_HNI_PML_CFG_PCS_AUTONEG_TIMERS__BREAK_LINK_TIMER_MAX 0x42c1d80
+#define C1_HNI_PML_CFG_PCS_AUTONEG_TIMERS__LINK_FAIL_INHIBIT_TIMER_MAX 0x1e19b040
+#define SS2_PORT_PML_CFG_PCS_AUTONEG_TIMERS__BREAK_LINK_TIMER_MAX 0x42c1d80
+#define SS2_PORT_PML_CFG_PCS_AUTONEG_TIMERS__LINK_FAIL_INHIBIT_TIMER_MAX 0x1e19b040
+#define C1_HNI_PML_CFG_PCS_AMS__AM_SPACING 0x6
+#define C1_HNI_PML_CFG_PCS_AMS__RAM_SPACING 0x6
+#define SS2_PORT_PML_CFG_PCS_AMS__AM_SPACING 0xc
+#define SS2_PORT_PML_CFG_PCS_AMS__RAM_SPACING 0x6
+#define C1_HNI_PML_CFG_TX_PCS__LANE_1_SOURCE 0x1
+#define C1_HNI_PML_CFG_TX_PCS__LANE_2_SOURCE 0x2
+#define C1_HNI_PML_CFG_TX_PCS__LANE_3_SOURCE 0x3
+#define C1_HNI_PML_CFG_TX_PCS__GEARBOX_CREDITS 0x8
+#define C1_HNI_PML_CFG_TX_PCS__CDC_READY_LEVEL 0x8
+#define SS2_PORT_PML_CFG_TX_PCS__LANE_1_SOURCE 0x1
+#define SS2_PORT_PML_CFG_TX_PCS__LANE_2_SOURCE 0x2
+#define SS2_PORT_PML_CFG_TX_PCS__LANE_3_SOURCE 0x3
+#define SS2_PORT_PML_CFG_TX_PCS__CDC_READY_LEVEL 0x8
+#define C1_HNI_PML_CFG_RX_PCS__RS_MODE 0x5
+#define C1_HNI_PML_CFG_RX_PCS__HEALTH_BAD_SENSITIVITY 0x2
+#define SS2_PORT_PML_CFG_RX_PCS__CW_GAP_544 0x6
+#define SS2_PORT_PML_CFG_RX_PCS__CW_GAP_LL 0x4
+#define SS2_PORT_PML_CFG_RX_PCS__CW_GAP_ONE_FEC 0x3
+#define SS2_PORT_PML_CFG_RX_PCS__HEALTH_BAD_SENSITIVITY 0x2
+#define SS2_PORT_PML_CFG_RX_PCS__LANE_1_SOURCE 0x1
+#define SS2_PORT_PML_CFG_RX_PCS__LANE_2_SOURCE 0x2
+#define SS2_PORT_PML_CFG_RX_PCS__LANE_3_SOURCE 0x3
+#define SS2_PORT_PML_CFG_RX_PCS__SIGNAL_DETECT_ENN 0xf
+#define SS2_PORT_PML_CFG_RX_PCS__RX_LOCK_ENN 0xf
+#define SS2_PORT_PML_CFG_RX_PCS__RX_CLK_VLD_ENN 0xf
+#define C1_HNI_PML_CFG_TX_MAC__PCS_CREDITS 0x8
+#define C1_HNI_PML_CFG_TX_MAC__IFG_MODE 0x1
+#define C1_HNI_PML_CFG_TX_MAC__VS_VERSION 0x3
+#define C1_HNI_PML_CFG_TX_MAC__NON_PORTALS_SOF_WINDOW 0x7
+#define C1_HNI_PML_CFG_TX_MAC__NON_PORTALS_MAX_SOF 0x3
+#define C1_HNI_PML_CFG_TX_MAC__ANY_FRAME_SOF_WINDOW_0 0x1
+#define C1_HNI_PML_CFG_TX_MAC__ANY_FRAME_MAX_SOF_0 0x1
+#define C1_HNI_PML_CFG_TX_MAC__ANY_FRAME_SOF_WINDOW_1 0x1
+#define C1_HNI_PML_CFG_TX_MAC__ANY_FRAME_MAX_SOF_1 0x1
+#define C1_HNI_PML_CFG_TX_MAC__PORTALS_PROTOCOL 0x77
+#define SS2_PORT_PML_CFG_TX_MAC__IFG_MODE 0x1
+#define SS2_PORT_PML_CFG_TX_MAC__MAC_PAD_IDLE_THRESH 0x9
+#define SS2_PORT_PML_CFG_TX_MAC__IEEE_IFG_ADJUSTMENT 0x3
+#define SS2_PORT_PML_CFG_TX_MAC__VS_VERSION 0x3
+#define SS2_PORT_PML_CFG_TX_MAC__ST_PROTOCOL 0x77
+#define C1_HNI_PML_CFG_LLR__MAC_IF_CREDITS 0x8
+#define C1_HNI_PML_CFG_LLR__LINK_DOWN_BEHAVIOR 0x1
+#define C1_HNI_PML_CFG_LLR__SIZE 0x3
+#define C1_HNI_PML_CFG_LLR__FILTER_CTL_FRAMES 0x1
+#define C1_HNI_PML_CFG_LLR__FILTER_LOSSLESS_WHEN_OFF 0x1
+#define SS2_PORT_PML_CFG_LLR__SIZE 0x1
+#define C1_HNI_PML_CFG_LLR_CF_DMAC__CTL_FRAME_DMAC 0x180c200000e
+#define SS2_PORT_PML_CFG_LLR_CF_DMAC__CTL_FRAME_DMAC 0x180c200000e
+#define C1_HNI_PML_CFG_LLR_CF_ETYPE__CTL_FRAME_ETHERTYPE 0x88b6
+#define SS2_PORT_PML_CFG_LLR_CF_ETYPE__CTL_FRAME_ETHERTYPE 0x88b6
+#define C1_HNI_PML_CFG_LLR_CF_RATES__LOOP_TIMING_PERIOD 0x157c
+#define C1_HNI_PML_CFG_LLR_CF_RATES__INIT_CTL_OS_PERIOD 0x3
+#define SS2_PORT_PML_CFG_LLR_CF_RATES__LOOP_TIMING_PERIOD 0x157c
+#define SS2_PORT_PML_CFG_LLR_CF_RATES__INIT_CTL_OS_PERIOD 0x3
+#define C1_HNI_PML_CFG_LLR_SM__REPLAY_TIMER_MAX 0x3c8c
+#define C1_HNI_PML_CFG_LLR_SM__REPLAY_CT_MAX 0xff
+#define C1_HNI_PML_CFG_LLR_SM__RETRY_THRESHOLD 0x2
+#define SS2_PORT_PML_CFG_LLR_SM__REPLAY_TIMER_MAX 0x3c8c
+#define SS2_PORT_PML_CFG_LLR_SM__REPLAY_CT_MAX 0xff
+#define SS2_PORT_PML_CFG_LLR_SM__RETRY_THRESHOLD 0x2
+#define C1_HNI_PML_CFG_LLR_CAPACITY__MAX_SEQ 0x800
+#define C1_HNI_PML_CFG_LLR_CAPACITY__MAX_DATA 0x800
+#define SS2_PORT_PML_CFG_LLR_CAPACITY__MAX_SEQ 0x800
+#define SS2_PORT_PML_CFG_LLR_CAPACITY__MAX_DATA 0x800
+#define C1_HNI_PML_CFG_LLR_TIMEOUTS__PCS_LINK_DN_TIMER_MAX 0x3b9aca00
+#define C1_HNI_PML_CFG_LLR_TIMEOUTS__DATA_AGE_TIMER_MAX 0xee6b2800
+#define SS2_PORT_PML_CFG_LLR_TIMEOUTS__PCS_LINK_DN_TIMER_MAX 0x3b9aca00
+#define SS2_PORT_PML_CFG_LLR_TIMEOUTS__DATA_AGE_TIMER_MAX 0xee6b2800
+#define C1_HNI_PML_CFG_LLR_FGFC_0__FGFC_DMAC 0x180c200000e
+#define C1_HNI_PML_CFG_LLR_FGFC_0__FGFC_EXTENDED_ETHERTYPE_MASK 0x7f
+#define SS2_PORT_PML_CFG_LLR_FGFC_0__FGFC_DMAC 0x180c200000e
+#define SS2_PORT_PML_CFG_LLR_FGFC_0__FGFC_EXTENDED_ETHERTYPE_MASK 0x7f
+#define C1_HNI_PML_CFG_LLR_FGFC_1__FGFC_EXTENDED_ETHERTYPE 0x88b7000eab000000
+#define SS2_PORT_PML_CFG_LLR_FGFC_1__FGFC_EXTENDED_ETHERTYPE 0x88b7000eab000000
+#define SS2_PORT_PML_DBG_RX_SERDES_CLKS__RX_0_PPM_DELTA 0x101
+#define SS2_PORT_PML_DBG_RX_SERDES_CLKS__RX_1_PPM_DELTA 0x101
+#define SS2_PORT_PML_DBG_RX_SERDES_CLKS__RX_2_PPM_DELTA 0x101
+#define SS2_PORT_PML_DBG_RX_SERDES_CLKS__RX_3_PPM_DELTA 0x101
+#define C1_HNI_PML_DBG_PCS__TX_SCRAMBLER_EN 0x1
+#define C1_HNI_PML_DBG_PCS__RX_DESCRAMBLER_EN 0x1
+#define C1_HNI_PML_DBG_PCS__FORCE_BAD_BIP 0x1f
+#define SS2_PORT_PML_DBG_PCS__TX_SCRAMBLER_EN 0x1
+#define SS2_PORT_PML_DBG_PCS__RX_DESCRAMBLER_EN 0x1
+#define SS2_PORT_PML_DBG_PCS__FORCE_BAD_BIP 0x1f
+#define C_IXE_DBG_CFG_LSA_SEL_IDX__SELECT_IDX 0x3f
+#define C_IXE_ERR_IRQA_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_IXE_ERR_IRQB_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_IXE_EXT_ERR_IRQA_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_IXE_EXT_ERR_IRQB_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_IXE_CFG_DSCP_WRQ_MAP__MASK0 0x1fffff
+#define C_IXE_CFG_DSCP_WRQ_MAP__MASK1 0x55555
+#define C_IXE_CFG_TC_FQ_MAP__PUT_RESP_MASK 0xffffff
+#define C_IXE_CFG_TC_FQ_MAP__GET_REQ_MASK 0xffffff
+#define C_IXE_CFG_OP_VNI_REMAP__VNI_MASK 0xffff
+#define C_IXE_CFG_OP_VNI_REMAP__FLUSH_ONLY_EOM 0x1
+#define C_IXE_CFG_DISP_CDT_LIM__MST_MATCH_CDTS 0x20
+#define C_IXE_CFG_DISP_CDT_LIM__WRQ_FF_CDTS 0x3
+#define C_IXE_CFG_DISP_CDT_LIM__ATU_REQ_CDTS 0x4
+#define C_IXE_CFG_DISP_CDT_LIM__RPU_ERR_CDTS 0x5
+#define C_IXE_CFG_DISP_CDT_LIM__RPU_RESP_CDTS 0x5
+#define C_IXE_CFG_DISP_CDT_LIM__PCT_GCOMP_CDTS 0x20
+#define C_IXE_CFG_DISP_CDT_LIM__PUT_RESP_CDTS 0x200
+#define C_IXE_CFG_DISP_CDT_LIM__PUT_ATU_CDTS 0x100
+#define C_IXE_CFG_DISP_CDT_LIM__EE_CDTS 0x10
+#define C_IXE_CFG_AMO_OFFLOAD_CODE_1OP__OP_MIN_CODE 0x1
+#define C_IXE_CFG_AMO_OFFLOAD_CODE_1OP__OP_MAX_CODE 0x2
+#define C_IXE_CFG_AMO_OFFLOAD_CODE_1OP__OP_SUM_CODE 0x3
+#define C_IXE_CFG_AMO_OFFLOAD_CODE_1OP__OP_LOR_CODE 0x4
+#define C_IXE_CFG_AMO_OFFLOAD_CODE_1OP__OP_LAND_CODE 0x5
+#define C_IXE_CFG_AMO_OFFLOAD_CODE_1OP__OP_BOR_CODE 0x6
+#define C_IXE_CFG_AMO_OFFLOAD_CODE_1OP__OP_BAND_CODE 0x7
+#define C_IXE_CFG_AMO_OFFLOAD_CODE_1OP__OP_LXOR_CODE 0x8
+#define C_IXE_CFG_AMO_OFFLOAD_CODE_1OP__OP_BXOR_CODE 0x9
+#define C_IXE_CFG_AMO_OFFLOAD_CODE_1OP__OP_SWAP_CODE 0xa
+#define C_IXE_CFG_AMO_OFFLOAD_CODE_2OP__OP_CSWAP_EQ_CODE 0x1
+#define C_IXE_CFG_AMO_OFFLOAD_CODE_2OP__OP_CSWAP_NE_CODE 0x2
+#define C_IXE_CFG_AMO_OFFLOAD_CODE_2OP__OP_CSWAP_LE_CODE 0x3
+#define C_IXE_CFG_AMO_OFFLOAD_CODE_2OP__OP_CSWAP_LT_CODE 0x4
+#define C_IXE_CFG_AMO_OFFLOAD_CODE_2OP__OP_CSWAP_GE_CODE 0x5
+#define C_IXE_CFG_AMO_OFFLOAD_CODE_2OP__OP_CSWAP_GT_CODE 0x6
+#define C_IXE_CFG_AMO_OFFLOAD_CODE_2OP__OP_AXOR_CODE 0x7
+#define C_IXE_CFG_AMO_OFFLOAD__FIRST_DW_BE_32BIT 0xf
+#define C_IXE_CFG_AMO_OFFLOAD__FIRST_DW_BE_64BIT 0xf
+#define C_IXE_CFG_AMO_OFFLOAD__LAST_DW_BE_64BIT 0xf
+#define C_IXE_CFG_DMAWR__FLAG_DATA 0xffffffff
+#define C_IXE_CFG_DMAWR_CDT__FTCH_AMO_LIMIT 0x100
+#define C_IXE_CFG_DMAWR_CDT__NP_REQ_LIMIT 0x100
+#define C_IXE_CFG_DMAWR_CDT__NP_LIMIT 0x10
+#define C_IXE_CFG_DMAWR_CDT__P_LIMIT 0x20
+#define C_IXE_CFG_PORT_PKT__VS_VERSION 0x3
+#define C_IXE_CFG_PORT_PKT__PORTALS_PROTOCOL 0x77
+#define C_IXE_CFG_PARSER__IPV4_FLOWLAB_TYPE 0x8f
+#define C_IXE_CFG_PARSER__IPV6_FRAG_TYPE 0x2c
+#define C_IXE_CFG_PARSER__UDP_TYPE 0x11
+#define C_IXE_CFG_PARSER__TCP_TYPE 0x6
+#define C_IXE_CFG_PARSER__ETH_SEGMENT 0x1f
+#define C_IXE_CFG_PARSER__RPU_WRDISP_CDT 0x8
+#define C_IXE_CFG_ROCE__UDP_DSTPORT_BTH 0x12b7
+#define C_IXE_CFG_BTH_OPCODE__LEN_0 0x3
+#define C_IXE_CFG_BTH_OPCODE__LEN_1 0x3
+#define C_IXE_CFG_BTH_OPCODE__LEN_2 0x3
+#define C_IXE_CFG_BTH_OPCODE__LEN_3 0x3
+#define C_IXE_CFG_BTH_OPCODE__LEN_4 0x3
+#define C_IXE_CFG_BTH_OPCODE__LEN_5 0x3
+#define C_IXE_CFG_BTH_OPCODE__LEN_6 0x3
+#define C_IXE_CFG_BTH_OPCODE__LEN_7 0x3
+#define C_IXE_CFG_BTH_OPCODE__LEN_8 0x3
+#define C_IXE_CFG_BTH_OPCODE__LEN_9 0x3
+#define C_IXE_CFG_BTH_OPCODE__LEN_10 0x3
+#define C_IXE_CFG_BTH_OPCODE__LEN_11 0x3
+#define C_IXE_CFG_BTH_OPCODE__LEN_12 0x3
+#define C_IXE_CFG_BTH_OPCODE__LEN_13 0x3
+#define C_IXE_CFG_BTH_OPCODE__LEN_14 0x3
+#define C_IXE_CFG_BTH_OPCODE__LEN_15 0x3
+#define C_IXE_STS_TARB_CDTS__FTCH_AMO_AVAIL 0x1
+#define C_IXE_STS_TARB_CDTS__NP_REQ_AVAIL 0x1
+#define C_IXE_STS_TARB_CDTS__NP_AVAIL 0x1
+#define C_IXE_STS_TARB_CDTS__P_AVAIL 0x1
+#define C_IXE_DBG_RDFQ_QUEUE_ST__EMPTY 0x1
+#define C_IXE_DBG_WRQ_QUEUE_ST__EMPTY 0x1
+#define C_IXE_DBG_RPU_QUEUE_ST__EMPTY 0x1
+#define C_IXE_DBG_CFG_LSA_TRIG_CMN__TRIG_RESET 0x1
+#define C_LPE_DBG_CFG_LSA_SEL_IDX__SELECT_IDX 0x1f
+#define C_LPE_ERR_IRQA_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_LPE_ERR_IRQB_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_LPE_CFG_TC_ARB_QUANTA__ARB_QUANTA 0x64
+#define C_LPE_CFG_TC_ARB_WEIGHTS__TC0_WEIGHT 0x1
+#define C_LPE_CFG_TC_ARB_WEIGHTS__TC1_WEIGHT 0x1
+#define C_LPE_CFG_TC_ARB_WEIGHTS__TC2_WEIGHT 0x1
+#define C_LPE_CFG_TC_ARB_WEIGHTS__TC3_WEIGHT 0x1
+#define C_LPE_CFG_TC_ARB_WEIGHTS__TC4_WEIGHT 0x1
+#define C_LPE_CFG_TC_ARB_WEIGHTS__TC5_WEIGHT 0x1
+#define C_LPE_CFG_TC_ARB_WEIGHTS__TC6_WEIGHT 0x1
+#define C_LPE_CFG_TC_ARB_WEIGHTS__TC7_WEIGHT 0x1
+#define C_LPE_CFG_FQ_TC_MAP__BASE1 0x1
+#define C_LPE_CFG_FQ_TC_MAP__BASE2 0x2
+#define C_LPE_CFG_FQ_TC_MAP__BASE3 0x3
+#define C_LPE_CFG_FQ_TC_MAP__BASE4 0x4
+#define C_LPE_CFG_FQ_TC_MAP__BASE5 0x5
+#define C_LPE_CFG_FQ_TC_MAP__BASE6 0x6
+#define C_LPE_CFG_FQ_TC_MAP__BASE7 0x7
+#define C_LPE_CFG_CDT_LIMITS__IXEMRQ_WC_CDTS 0x8
+#define C_LPE_CFG_CDT_LIMITS__CQMRQ_WC_CDTS 0x8
+#define C_LPE_CFG_CDT_LIMITS__RDY_PLE_CDTS 0xc
+#define C_LPE_CFG_CDT_LIMITS__EVENT_CDTS 0x10
+#define C_LPE_CFG_CDT_LIMITS__IXE_PUT_CDTS 0x8
+#define C_LPE_CFG_CDT_LIMITS__IXE_GET_CDTS 0x8
+#define C_LPE_CFG_CDT_LIMITS__IXE_MST_CDTS 0x8
+#define C_LPE_CFG_CDT_LIMITS__RRQ_CDTS 0x7
+#define C_LPE_CFG_INITIATOR_CTRL__PID_BITS 0x8
+#define C_LPE_CFG_ETHERNET_THRESHOLD__THRESHOLD 0x5dc
+#define C_LPE_CFG_MIN_FREE_SHFT__MIN_FREE_SHFT 0x6
+#define C_LPE_CFG_MATCHER_EN__PE0_MATCHER_EN 0xff
+#define C_LPE_CFG_MATCHER_EN__PE1_MATCHER_EN 0xff
+#define C_LPE_CFG_MATCHER_EN__PE2_MATCHER_EN 0xff
+#define C_LPE_CFG_MATCHER_EN__PE3_MATCHER_EN 0xff
+#define C1_LPE_CFG_GET_FQ_HASH__HASH0 0x55249
+#define C1_LPE_CFG_GET_FQ_HASH__HASH1 0xaa492
+#define C1_LPE_CFG_GET_FQ_HASH__HASH2 0x924
+#define C_LPE_CFG_PE_LE_POOLS__MAX_ALLOC 0x400
+#define C_LPE_CFG_PE_LE_SHARED__NUM_SHARED 0x4000
+#define C_LPE_CFG_PE_LE_SHARED__NUM_TOTAL 0x4000
+#define C_LPE_STS_PE_FREE_MASK__FREE_MASK 0xffffffffffffffff
+#define C_LPE_CFG_PTL_TABLE__EN_SW_HW_ST_CHNG 0x1
+#define C_LPE_DBG_IXEMRQ_QUEUE_ST__EMPTY 0x1
+#define C_LPE_DBG_CQMRQ_QUEUE_ST__EMPTY 0x1
+#define C_LPE_DBG_GETFQ_QUEUE_ST__EMPTY 0x1
+#define C_LPE_DBG_PETCQ_QUEUE_ST__EMPTY 0x1
+#define C_MB_ERR_IRQA_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_MB_ERR_IRQB_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_MB_EXT_ERR_IRQA_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_MB_EXT_ERR_IRQB_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_MB_CFG_MISC__NIC_WARM_RST0 0x1
+#define C_MB_CFG_MISC__NIC_WARM_RST1 0x1
+#define C_MB_CFG_MISC__NIC_WARM_RST2 0x1
+#define C_MB_CFG_MISC__NIC_WARM_RST3 0x1
+#define C_MB_CFG_MISC__NIC_WARM_RST4 0x1
+#define C_MB_CFG_MISC__NIC_WARM_RST5 0x1
+#define C_MB_CFG_MISC__NIC_WARM_RST6 0x1
+#define C_MB_CFG_MISC__NIC_WARM_RST7 0x1
+#define C_MB_CFG_MISC__NIC_WARM_RST8 0x1
+#define C_MB_CFG_MISC__NIC_WARM_RST9 0x1
+#define C_MB_STS_REV__REV 0x2
+#define C_MB_STS_REV__DEVICE_ID 0x501
+#define C_MB_STS_REV__VENDOR_ID 0x17db
+#define C1_MB_CFG_RSTC__PCIE_REF_CLK_SEL 0x1
+#define C2_MB_CFG_RSTC__PCIE_REF_CLK_SEL 0x1
+#define C_MB_CFG_CRMC__RING_TIMEOUT 0xff
+#define C_MB_CFG_RTC__RTC_ETC_SEC_CHANGE_MASK 0x2
+#define C_MB_CFG_RTC__ETC_NS_LOCK_RESOLUTION 0x2
+#define C_MB_CFG_RTC_INC__NANOSECONDS 0x1
+#define C_MB_DBG_CFG_LSA_TRIG_CMN__TRIG_RESET 0x1
+#define C1_MB_DBG_CFG_LSA_CAP__CAP_RESET 0x1
+#define C2_MB_DBG_CFG_LSA_CAP__CAP_RESET 0x1
+#define C_MB_CFG_FLASH_INTERFACE__SPI_PAGE_CMD 0x13
+#define C_MB_CFG_FLASH_INTERFACE__SPI_PAGE_SIZE 0x1
+#define C_MB_CFG_FLASH_INTERFACE__SPI_PAGE_ADDR_WIDTH 0x2
+#define C_MB_CFG_FLASH_INTERFACE__SPI_STATUS_CMD 0xf
+#define C_MB_CFG_FLASH_INTERFACE__SPI_STATUS_ADDR 0xc0
+#define C_MB_CFG_FLASH_INTERFACE__SPI_READ_CMD 0x3
+#define C_MB_CFG_FLASH_INTERFACE__SPI_READ_ADDR_WIDTH 0x2
+#define C_MB_CFG_FLASH_INTERFACE__SPI_READ_DUMMY_CNT 0x8
+#define C_MB_CFG_FLASH_INTERFACE__SPI_CLK_FREQ 0x7
+#define C_MB_CFG_FLASH_INTERFACE__DRIVE_IO3 0x1
+#define C_MB_CFG_FLASH_CSR_INIT_P1__INIT_ENABLE 0x1
+#define C_MB_CFG_FLASH_CSR_INIT_P1__SIZE 0xf
+#define C_MB_CFG_FLASH_CSR_INIT_P2__ADDRESS 0x100
+#define C_MB_CFG_FLASH_CSR_INIT_P2__EXIT_ON_SPI_ERROR 0x1
+#define C_MB_CFG_FLASH_CSR_INIT_P2__SIZE 0xf
+#define C_MB_CFG_FLASH_PCIE_SERDES__ADDRESS 0x1000
+#define C_MB_CFG_FLASH_PCIE_SERDES__EXIT_ON_SPI_ERROR 0x1
+#define C_MB_CFG_FLASH_PCIE_SERDES__SIZE 0x5fff
+#define C_MB_CFG_FLASH_EXP_ROM__ADDRESS 0x1000000
+#define C_MB_CFG_FLASH_PAGE0__PREFETCH_SIZE 0xf
+#define C_MB_CFG_FLASH_PAGE1__PREFETCH_SIZE 0xf
+#define C_MST_DBG_CFG_LSA_SEL_IDX__SELECT_IDX 0x7
+#define C_MST_ERR_IRQA_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_MST_ERR_IRQB_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_MST_CFG_CRDT_LIMITS__GET_Q_DEPTH 0x8
+#define C_MST_CFG_CRDT_LIMITS__PUT_Q_DEPTH 0x8
+#define C_MST_CFG_CRDT_LIMITS__EE_Q_DEPTH 0x10
+#define C_MST_CFG_CRDT_LIMITS__REQ_FIFO_DEPTH 0x4
+#define C_MST_DBG_REQ_FIFO_HALT__HALT_FIFO_MASK 0xffffffff
+#define C_OXE_DBG_CFG_LSA_SEL_IDX__SELECT_IDX 0xff
+#define C_OXE_ERR_IRQA_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_OXE_ERR_IRQB_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_OXE_CFG_CDT__PCT_FLIT_CDTS 0x10
+#define C_OXE_CFG_CDT__PCT_REQ_CDTS 0x10
+#define C_OXE_CFG_CDT__OUT_FLIT_CDTS 0xb0
+#define C_OXE_CFG_CDT__OUT_PKT_CDTS 0x40
+#define C_OXE_CFG_CDT__OUT_FLIT_THRESHOLD 0xb0
+#define C_OXE_CFG_FAB_PARAM__VER 0x3
+#define C_OXE_CFG_FAB_PARAM__TTL 0x5a
+#define C_OXE_CFG_FAB_PARAM__PROTOCOL 0x77
+#define C_OXE_CFG_FAB_PARAM__MIN_REQ_SIZE 0x3c
+#define C_OXE_CFG_FAB_PARAM__MIN_RSP_SIZE 0x3c
+#define C_OXE_CFG_FAB_SFA__NID 0x555aa
+#define C_OXE_CFG_RESPONSE_LEN__PUT_HDR_LEN 0x28
+#define C_OXE_CFG_RESPONSE_LEN__HRP_HDR_LEN 0x4
+#define C_OXE_CFG_RESPONSE_LEN__GET_HDR_LEN 0x28
+#define C_OXE_CFG_RESPONSE_LEN__PAYLOAD_SCALE 0x1
+#define C_OXE_CFG_PAUSE_QUANTA__SUB_VALUE 0x7d000
+#define C_OXE_CFG_PAUSE_QUANTA__SUB_PERIOD 0x14
+#define C_OXE_CFG_FGFC__EXTRA_BYTES 0x4
+#define C_OXE_CFG_FGFC__ROUND_POS 0x4
+#define C_OXE_CFG_FGFC__CDT_ADJ 0x843
+#define C_OXE_CFG_FGFC__CDT_LIMIT 0xffffff
+#define C_OXE_CFG_PCT_CDT__SPT_CDT_LIMIT 0x7ff
+#define C_OXE_CFG_PCT_CDT__SMT_CDT_LIMIT 0x100
+#define C_OXE_CFG_PCT_CDT__SCT_CDT_LIMIT 0x1000
+#define C_OXE_CFG_PCT_CDT__SRB_CDT_LIMIT 0x7ff
+#define C_OXE_CFG_IDC_PRIORITY_LIMIT__OCC_BLIMIT 0x80
+#define C_OXE_CFG_IDC_PRIORITY_LIMIT__OCC_CLIMIT 0x80
+#define C_OXE_CFG_BUF_BC_PARAM__BC_RESERV_BUF_CDT 0x28
+#define C_OXE_CFG_BUF_BC_PARAM__BC_MAX_MTU 0x28
+#define C_OXE_CFG_PCT_BC_CDT__SPT_CDT_RSVD 0x4
+#define C_OXE_CFG_PCT_BC_CDT__SMT_CDT_RSVD 0x4
+#define C_OXE_CFG_PCT_BC_CDT__SCT_CDT_RSVD 0x4
+#define C_OXE_CFG_PCT_BC_CDT__SRB_CDT_RSVD 0x10
+#define C_OXE_CFG_BUF_SH_CDT__BUF_SH_CDT 0x270
+#define C_OXE_CFG_BUF_SH_CDT__BUF_SH_BC_CDT 0x270
+#define C_OXE_CFG_BUF_SH_CDT__BUF_SH_BC_IDC_CDT 0x80
+#define C_OXE_CFG_MCU_PRIORITY_LIMIT__OCC_BLIMIT 0x80
+#define C_OXE_CFG_MCU_PRIORITY_LIMIT__OCC_CLIMIT 0x80
+#define C_OXE_CFG_MEM_RD_THRESH__MAX_PCIE_REQ 0x200
+#define C_OXE_CFG_MEM_RD_THRESH__MAX_AT_REQ 0x100
+#define C_OXE_CFG_ARB_MFS_OUT__MFS0 0x42
+#define C_OXE_CFG_ARB_MFS_OUT__MFS1 0x120
+#define C_OXE_CFG_ARB_MFS_OUT__MFS2 0x30
+#define C_OXE_CFG_ARB_MFS_IN__MFS0 0x42
+#define C_OXE_CFG_ARB_MFS_IN__MFS1 0x120
+#define C_OXE_CFG_ARB_MFS_IN__MFS2 0x30
+#define C_OXE_CFG_OUTSTANDING_LIMIT__PUT_LIMIT 0x7ff
+#define C_OXE_CFG_OUTSTANDING_LIMIT__GET_LIMIT 0x7ff
+#define C_OXE_CFG_OUTSTANDING_LIMIT__IOI_ORD_LIMIT 0x7ff
+#define C_OXE_CFG_OUTSTANDING_LIMIT__IOI_UNORD_LIMIT 0x1fff
+#define C_OXE_CFG_ARB_LEAF__PARENT 0x7
+#define C_OXE_CFG_ARB_LEAF__ENABLE_IN 0x1
+#define C_PARBS_DBG_CFG_LSA_SEL_IDX__SELECT_IDX 0x1f
+#define C_PARBS_ERR_IRQA_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_PARBS_ERR_IRQB_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_PARBS_EXT_ERR_IRQA_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_PARBS_EXT_ERR_IRQB_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_PARBS_CFG_CREDIT_LIMITS__TARB_PI_POSTED_CREDITS 0x1f
+#define C_PARBS_CFG_CREDIT_LIMITS__TARB_PI_NON_POSTED_CREDITS 0x1f
+#define C_PCT_DBG_CFG_LSA_SEL_IDX__SELECT_IDX 0xf
+#define C_PCT_ERR_IRQA_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_PCT_ERR_IRQB_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_PCT_EXT_ERR_IRQA_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_PCT_EXT_ERR_IRQB_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_PCT_ERR_SHUTDN_MSK__ERR_SHUTDN_MSK 0xffffffffffffffff
+#define C_PCT_EXT_ERR_SHUTDN_MSK__ERR_SHUTDN_MSK 0xffffffffffffffff
+#define C_PCT_CFG_PKT_MISC__SM_FAB_HDR 0x3
+#define C_PCT_CFG_PKT_MISC__PTL_PROTO 0x77
+#define C_PCT_CFG_TIMING__STALL_CTR 0x4
+#define C_PCT_CFG_TIMING__SPT_TIMEOUT_EPOCH_SEL 0x10
+#define C_PCT_CFG_TIMING__SCT_IDLE_EPOCH_SEL 0x14
+#define C_PCT_CFG_TIMING__SCT_CLOSE_EPOCH_SEL 0x10
+#define C_PCT_CFG_TIMING__TCT_TIMEOUT_EPOCH_SEL 0x18
+#define C_PCT_CFG_PKTO_FIFO_LIMITS__MST_EVNT_LIMIT 0x20
+#define C_PCT_CFG_PKTO_FIFO_LIMITS__TRS_LIMIT 0x10
+#define C_PCT_CFG_PKTO_FIFO_LIMITS__SPT_CDT_ACK_LIMIT 0x8
+#define C_PCT_CFG_PKTO_FIFO_LIMITS__EE_LIMIT 0x10
+#define C_PCT_CFG_PKTO_FIFO_LIMITS__CQ_LIMIT 0x10
+#define C_PCT_CFG_PKTO_FIFO_LIMITS__SRB_LIMIT 0xc
+#define C_PCT_CFG_PKTO_FIFO_LIMITS__PCT_HNI_LIMIT 0x10
+#define C_PCT_CFG_PKTO_FIFO_LIMITS__PIGGYBACK_CLR_LIMIT 0x4
+#define C_PCT_CFG_PKTO_FIFO_LIMITS__SMT_CDT_ACK_LIMIT 0x8
+#define C1_PCT_CFG_IXE_REQ_FIFO_LIMITS__IXE_REQ_CLR_LIMIT 0x20
+#define C1_PCT_CFG_IXE_REQ_FIFO_LIMITS__IXE_REQ_CLR1_LIMIT 0x4
+#define C1_PCT_CFG_IXE_REQ_FIFO_LIMITS__IXE_REQ_CLR2_LIMIT 0x4
+#define C1_PCT_CFG_IXE_REQ_FIFO_LIMITS__IXE_REQ_RSP_LIMIT 0x10
+#define C2_PCT_CFG_IXE_REQ_FIFO_LIMITS__IXE_REQ_CLR_LIMIT 0x20
+#define C2_PCT_CFG_IXE_REQ_FIFO_LIMITS__IXE_REQ_CLR1_LIMIT 0x4
+#define C2_PCT_CFG_IXE_REQ_FIFO_LIMITS__IXE_REQ_CLR2_LIMIT 0x4
+#define C2_PCT_CFG_IXE_REQ_FIFO_LIMITS__NACK_TRS_RSP_LIMIT 0x8
+#define C_PCT_CFG_IXE_GCOMP_FIFO_LIMITS__EE_LIMIT 0x10
+#define C_PCT_CFG_IXE_GCOMP_FIFO_LIMITS__CQ_LIMIT 0x10
+#define C_PCT_CFG_IXE_GCOMP_FIFO_LIMITS__CLR_LIMIT 0x8
+#define C_PCT_CFG_IXE_GCOMP_FIFO_LIMITS__SMT_CDT_ACK_LIMIT 0x8
+#define C_PCT_CFG_IXE_GCOMP_FIFO_LIMITS__SPT_CDT_ACK_LIMIT 0x8
+#define C_PCT_CFG_EE_CQ_FIFO_LIMIT__EE_CQ_LIMIT 0x10
+#define C_PCT_CFG_TBL_FIFO_LIMITS__SCT_TBL_CLS_LIMIT 0x8
+#define C_PCT_CFG_TBL_FIFO_LIMITS__SCT_TBL_EE_LIMIT 0x10
+#define C_PCT_CFG_TBL_FIFO_LIMITS__SPT_TBL_EE_LIMIT 0x10
+#define C_PCT_CFG_TBL_FIFO_LIMITS__TCT_TBL_EE_LIMIT 0x10
+#define C_PCT_CFG_IXE_RSP_FIFO_LIMITS__CLR_LIMIT 0x8
+#define C_PCT_CFG_IXE_RSP_FIFO_LIMITS__EE_LIMIT 0x10
+#define C_PCT_CFG_IXE_RSP_FIFO_LIMITS__CQ_LIMIT 0x10
+#define C_PCT_CFG_IXE_RSP_FIFO_LIMITS__SRB_DEALLOC_LIMIT 0x10
+#define C_PCT_CFG_IXE_RSP_FIFO_LIMITS__SMT_CDT_ACK_LIMIT 0x8
+#define C_PCT_CFG_IXE_RSP_FIFO_LIMITS__SPT_CDT_ACK_LIMIT 0x8
+#define C_PCT_CFG_IXE_RSP_FIFO_LIMITS__SCT_CDT_ACK_LIMIT 0x8
+#define C_PCT_CFG_SRC_CLS_REQ_FIFO_LIMIT__SRC_CLS_REQ_LIMIT 0x8
+#define C_PCT_CFG_TGT_CLR_REQ_FIFO_LIMIT__TGT_CLR_REQ_LIMIT 0x20
+#define C_PCT_CFG_TGT_CLR_REQ_FIFO_LIMIT__MST_DEALLOC_FIFO_LIMIT 0x8
+#define C1_PCT_CFG_TGT_CLS_RSP_FIFO_LIMIT__TGT_CLS_RSP_LIMIT 0x10
+#define C2_PCT_CFG_TGT_CLS_RSP_FIFO_LIMIT__TGT_CLS_RSP_LIMIT 0x8
+#define C1_PCT_CFG_CLS_REQ_GEN_FIFO_LIMIT__CLS_REQ_GEN_LIMIT 0x40
+#define C1_PCT_CFG_CLS_REQ_GEN_FIFO_LIMIT__SPT_CDT_ACK_LIMIT 0x8
+#define C2_PCT_CFG_CLS_REQ_GEN_FIFO_LIMIT__CLS_REQ_GEN_LIMIT 0x40
+#define C2_PCT_CFG_CLS_REQ_GEN_FIFO_LIMIT__CLS_RSP_GEN_LIMIT 0x40
+#define C2_PCT_CFG_CLS_REQ_GEN_FIFO_LIMIT__NACK_TRS_RSP_GEN_LIMIT 0x40
+#define C2_PCT_CFG_CLS_REQ_GEN_FIFO_LIMIT__SPT_CDT_ACK_LIMIT 0x8
+#define C1_PCT_CFG_TRS_TC_DED_LIMIT__DED_LIMIT 0x40
+#define C2_PCT_CFG_TRS_TC_DED_LIMIT__DED_LIMIT 0x200
+#define C1_PCT_CFG_TRS_TC_MAX_LIMIT__MAX_LIMIT 0x640
+#define C2_PCT_CFG_TRS_TC_MAX_LIMIT__MAX_LIMIT 0x1900
+#define C1_PCT_CFG_TRS_CRDT_LIMITS__TOTAL_LIMIT 0x800
+#define C1_PCT_CFG_TRS_CRDT_LIMITS__SHARED_LIMIT 0x600
+#define C2_PCT_CFG_TRS_CRDT_LIMITS__TOTAL_LIMIT 0x2000
+#define C2_PCT_CFG_TRS_CRDT_LIMITS__SHARED_LIMIT 0x1000
+#define C_PCT_CFG_MST_TC_DED_LIMIT__DED_LIMIT 0x40
+#define C_PCT_CFG_MST_TC_MAX_LIMIT__MAX_LIMIT 0x640
+#define C_PCT_CFG_MST_CRDT_LIMITS__TOTAL_LIMIT 0x800
+#define C_PCT_CFG_MST_CRDT_LIMITS__SHARED_LIMIT 0x600
+#define C_PCT_CFG_TCT_TC_DED_LIMIT__DED_LIMIT 0x100
+#define C_PCT_CFG_TCT_TC_MAX_LIMIT__MAX_LIMIT 0x1900
+#define C_PCT_CFG_TCT_CRDT_LIMITS__TOTAL_LIMIT 0x2000
+#define C_PCT_CFG_TCT_CRDT_LIMITS__SHARED_LIMIT 0x1800
+#define C_PCT_CFG_CONN_LOAD_SETUP__SCALED_FABRIC_RTT 0x4
+#define C_PCT_CFG_CONN_LOAD_SETUP__SHARED_FREE_SNAP_INTRVL 0x80
+#define C_PCT_CFG_CONN_LOAD_SETUP__LOAD_METRIC_ADJUST 0x6
+#define C1_PCT_CFG_SCT_MISC_SETUP__VNI_MASK 0xffff
+#define C2_PCT_CFG_SCT_MISC_SETUP__VNI_MASK 0xffff
+#define C_PCT_CFG_SCT_TAG_DFA_MASK__DSCP0_DFA_MASK 0xfff
+#define C_PCT_CFG_SCT_TAG_DFA_MASK__DSCP1_DFA_MASK 0xfff
+#define C_PCT_CFG_SCT_TAG_DFA_MASK__DSCP2_DFA_MASK 0xfff
+#define C_PCT_CFG_SCT_TAG_DFA_MASK__DSCP3_DFA_MASK 0xfff
+#define C_PCT_CFG_SW_RETRY_SRC_CLS_REQ__CLOSE_NOT_CLEAR 0x1
+#define C_PCT_CFG_MEM_SETUP__CAM_CHK_INTRVL 0x400
+#define C_PCT_CFG_NET_HIST__CLOCK_SHIFT 0x7
+#define C_PCT_CFG_NET_HIST__B_SHIFT 0x4
+#define C_PCT_CFG_NET_HIST__M_SHIFT 0x2
+#define C_PCT_CFG_NET_HIST__IML_SHIFT 0x3
+#define C_PCT_CFG_NET_HIST__IL_SHIFT 0x14
+#define C_PCT_CFG_HOST_HIST__CLOCK_SHIFT 0x6
+#define C_PCT_CFG_HOST_HIST__B_SHIFT 0x2
+#define C_PCT_CFG_HOST_HIST__M_SHIFT 0x1
+#define C_PCT_CFG_HOST_HIST__IML_SHIFT 0x3
+#define C_PCT_CFG_HOST_HIST__IL_SHIFT 0x14
+#define C_PI_DBG_CFG_LSA_SEL_IDX__SELECT_IDX 0x1f
+#define C_PI_ERR_IRQA_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_PI_ERR_IRQB_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_PI_EXT_ERR_IRQA_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_PI_EXT_ERR_IRQB_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_PI_CFG_PRI__MB_XLAT_DISCARD_ON_RTRGT_HDR_PAR_ERR 0x1
+#define C_PI_CFG_PRI__MB_XLAT_DISCARD_ON_RTRGT_DATA_PAR_ERR 0x1
+#define C_PI_CFG_PRI__RARB_XLAT_DISCARD_ON_RTRGT_HDR_PAR_ERR 0x1
+#define C_PI_CFG_PRI__RARB_XLAT_DISCARD_ON_RTRGT_DATA_PAR_ERR 0x1
+#define C_PI_CFG_PRI__RARB_XLAT_DISCARD_ON_RBYP_HDR_PAR_ERR 0x1
+#define C_PI_CFG_PRI__RARB_XLAT_DISCARD_ON_RBYP_DATA_PAR_ERR 0x1
+#define C_PI_IPD_DBG_CFG_IP_LSA_SEL_IDX__SELECT_IDX 0x1f
+#define C_PI_IPD_ERR_IRQA_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_PI_IPD_ERR_IRQB_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_PI_IPD_EXT_ERR_IRQA_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_PI_IPD_EXT_ERR_IRQB_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_PI_IPD_DBG_CFG_IP__APP_LTSSM_ENABLE 0x1
+#define C_PI_IPD_DBG_CFG_IP__APP_READY_ENTR_L23 0x1
+#define C_PI_IPD_CFG_VF_PF_IRQ_MASK__MASK 0xffffffffffffffff
+#define C_PI_IPD_DBG_CFG_LSA_TRIG_CMN__TRIG_RESET 0x1
+#define C1_PI_IPD_DBG_CFG_LSA_CAP__CAP_RESET 0x1
+#define C2_PI_IPD_DBG_CFG_LSA_CAP__CAP_RESET 0x1
+#define C_PI_IPD_CFG_MSIX_TABLE__VECTOR_CTL_MASK 0x1
+#define C_PI_IPD_CFG_VF_MSIX_TABLE__VECTOR_CTL_MASK 0x1
+#define C_RMU_DBG_CFG_LSA_SEL_IDX__SELECT_IDX 0x7
+#define C_RMU_ERR_IRQA_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_RMU_ERR_IRQB_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C_RMU_CFG_VNI_LIST_CHK__INTRVL 0x3e8
+#define C_RMU_CFG_PORTAL_LIST_CHK__INTRVL 0x3e8
+#define C_RMU_CFG_PTLTE_SET_LIST_CHK__INTRVL 0x3e8
+#define C_RMU_CFG_HASH_KEY__KEY_WD_0 0xce956a40459716af
+#define C_RMU_CFG_HASH_KEY__KEY_WD_1 0x20f0df941e6531b7
+#define C_RMU_CFG_HASH_KEY__KEY_WD_2 0x2a248008c8e231a5
+#define C_RMU_CFG_HASH_KEY__KEY_WD_3 0x987b221364fdc00b
+#define C_RMU_CFG_HASH_KEY__KEY_WD_4 0xfc10b4febad088a5
+#define C_RMU_CFG_HASH_KEY__KEY_WD_5 0x32e00ed6
+#define C_RMU_STS_INIT_DONE__WARM_RESET 0x1
+#define C2_HNI_EXT_ERR_IRQA_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C2_HNI_EXT_ERR_IRQB_MSK__ERR_IRQ_MSK 0xffffffffffffffff
+#define C2_HNI_CFG_FSM__TIMEOUT 0xfff
+#define SS2_PORT_PML_DBG_CFG_LSA_SEL_IDX__SELECT_IDX 0x1f
+#define SS2_PORT_PML_CFG_GENERAL__CLOCK_PERIOD_PS 0x3e8
+#define SS2_PORT_PML_CFG_PORT_GROUP__PG_CFG 0x3
+#define SS2_PORT_PML_CFG_PORT_GROUP__LINK_FUNCTION 0x7
+#define SS2_PORT_PML_CFG_TX_PCS_SUBPORT__GEARBOX_CREDITS 0x8
+#define SS2_PORT_PML_CFG_RX_PCS_SUBPORT__RS_MODE 0x5
+#define SS2_PORT_PML_CFG_TX_MAC_SUBPORT__PCS_CREDITS 0x8
+#define SS2_PORT_PML_CFG_TX_MAC_SUBPORT__MAC_CDT_INIT_VAL 0x40
+#define SS2_PORT_PML_CFG_TX_MAC_SUBPORT__MAC_CDT_THRESH 0xf
+#define SS2_PORT_PML_CFG_LLR_SUBPORT__FILTER_CTL_FRAMES 0x1
+#define SS2_PORT_PML_CFG_LLR_SUBPORT__FILTER_LOSSLESS_WHEN_OFF 0x1
+#define SS2_PORT_PML_CFG_LLR_SUBPORT__MAC_IF_CREDITS 0x8
+#define SS2_PORT_PML_CFG_LLR_SUBPORT__LINK_DOWN_BEHAVIOR 0x1
+#define SS2_PORT_PML_CFG_SERDES_RX__PMD_LN_RX_H_PWRDN 0x1
+#define SS2_PORT_PML_CFG_SERDES_TX__PMD_TX_DISABLE 0x1
+#define SS2_PORT_PML_CFG_SERDES_TX__PMD_LN_TX_H_PWRDN 0x1
+#define SS2_PORT_PML_DBG_FEC__DISABLE_UCE 0x1
+#define C2_IXE_CFG_DISP_ORD__WR_ATOMIC_OP 0x1
+#define C2_IXE_STS_PARSER_SEG_CNT__PKT_CNT 0x3fffffffffff
+#define C2_LPE_CFG_GET_FQ_HASH0__HASH 0xc9cf5d93
+#define C2_LPE_CFG_GET_FQ_HASH1__HASH 0xfa53fa76
+#define C2_LPE_CFG_GET_FQ_HASH2__HASH 0x5eb5335c
+#define C2_LPE_CFG_GET_FQ_DFA_MASK__DSCP0_DFA_MASK 0xfff
+#define C2_LPE_CFG_GET_FQ_DFA_MASK__DSCP1_DFA_MASK 0xfff
+#define C2_LPE_CFG_GET_FQ_DFA_MASK__DSCP2_DFA_MASK 0xfff
+#define C2_LPE_CFG_GET_FQ_DFA_MASK__DSCP3_DFA_MASK 0xfff
+#define C2_MB_CFG_FLASH_NOR_INTERFACE__RDY_BYPASS_CMD_MODE 0xff
+#define C2_MB_CFG_FLASH_NOR_INTERFACE__SPI_READ_CMD 0x3
+#define C2_MB_CFG_FLASH_NOR_INTERFACE__SPI_READ_ADDR_WIDTH 0x3
+#define C2_MB_CFG_FLASH_NOR_INTERFACE__SPI_CLK_FREQ 0x7
+#define C2_MB_CFG_FLASH_NOR_INTERFACE__DRIVE_IO3 0x1
+#define C2_OXE_CFG_SPT_BC_LIMIT__LIMIT 0x7ff
+#define C2_PI_CFG_PHY_PIPE_CONFIG__PIPE_CONFIG_IN 0x4000008
+#define C2_PI_CFG_PHY_PIPE_CONFIG__PIPE_CONFIG2_IN 0x3001
+#define C2_PI_CFG_PHY_SERDES_CONFIG__CONFIG_63_0 0x1008504618043242
+#define C2_PI_CFG_PHY_SERDES_CONFIG__CONFIG_127_64 0x4031a20207d69
+#define C2_PI_CFG_PHY_SERDES_CONFIG__CONFIG_191_128 0x6902250460103242
+#define C2_PI_CFG_PHY_SERDES_CONFIG__CONFIG_255_192 0x421500a192007d
+
+#endif
diff --git a/include/linux/hpe/cxi/cassini_error_defs.h b/include/linux/hpe/cxi/cassini_error_defs.h
new file mode 100644
index 000000000000..72f8d3237138
--- /dev/null
+++ b/include/linux/hpe/cxi/cassini_error_defs.h
@@ -0,0 +1,9091 @@
+/* SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause */
+/*
+ * Cassini error CSRs helpers
+ * Copyright 2019-2020 Hewlett Packard Enterprise Development LP
+ *
+ * This file is generated. Do not modify.
+ */
+
+#ifndef __CASSINI_ERROR_DEFS_H
+#define __CASSINI_ERROR_DEFS_H
+
+#define C_MAX_CSR_ERR_INFO 3
+#define C_MAX_CSR_CNTRS 3
+struct flg_err_info {
+	unsigned int bit;
+	unsigned int num_bits;
+	const char *bit_name;
+	enum c_error_class ec;
+	struct {
+		unsigned int offset;
+		unsigned int size;
+		const char *name;
+	} err_info[C_MAX_CSR_ERR_INFO];
+	struct {
+		unsigned int offset;
+		const char *name;
+		enum {
+			C_ERR_INDEX_NONE,	/* no indexing */
+			C_ERR_INDEX_MATCH,	/* indexed counter by bit number */
+		} index;
+	} cntr[C_MAX_CSR_CNTRS];
+};
+
+static const struct flg_err_info atu_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "crnc_ring_sync_error", C_EC_UNCOR_NS},
+	{2, 1, "crnc_ring_ecc_sbe", C_EC_COR},
+	{3, 1, "crnc_ring_ecc_mbe", C_EC_UNCOR_NS},
+	{4, 1, "crnc_ring_cmd_unknown", C_EC_UNCOR_NS},
+	{5, 1, "crnc_csr_cmd_unknown", C_EC_UNCOR_NS},
+	{6, 1, "crnc_csr_cmd_incomplete", C_EC_UNCOR_NS},
+	{7, 1, "crnc_buf_ecc_sbe", C_EC_COR},
+	{8, 1, "crnc_buf_ecc_mbe", C_EC_UNCOR_NS},
+	{32, 1, "fifo_err", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_FIFO, C_ATU_ERR_INFO_FIFO_SIZE,
+	   "C_ATU_ERR_INFO_FIFO"},
+	  },
+	 {},
+	 },
+	{33, 1, "page_perm_err", C_EC_BADCON_S,
+	 {{C_ATU_ERR_INFO_PAGE_PERM, C_ATU_ERR_INFO_PAGE_PERM_SIZE,
+	   "C_ATU_ERR_INFO_PAGE_PERM"},
+	  },
+	 {{0x10020568, "client_rsp_not_ok", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{34, 1, "ats_trans_err", C_EC_BADCON_S,
+	 {{C_ATU_ERR_INFO_ATS_TRANS, C_ATU_ERR_INFO_ATS_TRANS_SIZE,
+	   "C_ATU_ERR_INFO_ATS_TRANS"},
+	  {C_ATU_STS_ATS_VF_DISABLED, C_ATU_STS_ATS_VF_DISABLED_SIZE,
+	   "C_ATU_STS_ATS_VF_DISABLED"},
+	  {C_ATU_STS_ATS_PF_DISABLED, C_ATU_STS_ATS_PF_DISABLED_SIZE,
+	   "C_ATU_STS_ATS_PF_DISABLED"},
+	  },
+	 {{0x100205B8, "ats_trans_err", C_ERR_INDEX_NONE},
+	  {0x10020568, "client_rsp_not_ok", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{35, 1, "pcie_unsuccess_cmpl", C_EC_BADCON_S,
+	 {{C_ATU_ERR_INFO_PCIE_UC, C_ATU_ERR_INFO_PCIE_UC_SIZE,
+	   "C_ATU_ERR_INFO_PCIE_UC"},
+	  },
+	 {{0x100205B0, "pcie_unsuccess_cmpl", C_ERR_INDEX_NONE},
+	  {0x10020568, "client_rsp_not_ok", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{36, 1, "pcie_error_poisoned", C_EC_UNCOR_S,
+	 {{C_ATU_ERR_INFO_PCIE_EP, C_ATU_ERR_INFO_PCIE_EP_SIZE,
+	   "C_ATU_ERR_INFO_PCIE_EP"},
+	  },
+	 {{0x100205C0, "pcie_err_poisoned", C_ERR_INDEX_NONE},
+	  {0x10020568, "client_rsp_not_ok", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{37, 1, "ats_page_req_err", C_EC_BADCON_S,
+	 {{C_ATU_ERR_INFO_ATS_PAGE_REQ, C_ATU_ERR_INFO_ATS_PAGE_REQ_SIZE,
+	   "C_ATU_ERR_INFO_ATS_PAGE_REQ"},
+	  },
+	 {{0x10020568, "client_rsp_not_ok", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{38, 1, "no_translation", C_EC_BADCON_S,
+	 {{C_ATU_ERR_INFO_TRANSLATION, C_ATU_ERR_INFO_TRANSLATION_SIZE,
+	   "C_ATU_ERR_INFO_TRANSLATION"},
+	  },
+	 {{0x10020568, "client_rsp_not_ok", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{39, 1, "invalid_ac", C_EC_BADCON_S,
+	 {{C_ATU_ERR_INFO_AC, C_ATU_ERR_INFO_AC_SIZE, "C_ATU_ERR_INFO_AC"},
+	  },
+	 {{0x10020568, "client_rsp_not_ok", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{40, 1, "prb_expired", C_EC_BADCON_S,
+	 {{C_ATU_ERR_INFO_PRB_EXPIRED, C_ATU_ERR_INFO_PRB_EXPIRED_SIZE,
+	   "C_ATU_ERR_INFO_PRB_EXPIRED"},
+	  },
+	 {},
+	 },
+	{41, 1, "nta_pte_align_err", C_EC_BADCON_S,
+	 {{C_ATU_ERR_INFO_NTA_PTE_ALIGN, C_ATU_ERR_INFO_NTA_PTE_ALIGN_SIZE,
+	   "C_ATU_ERR_INFO_NTA_PTE_ALIGN"},
+	  },
+	 {{0x10020568, "client_rsp_not_ok", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{42, 1, "ats_odp_config_err", C_EC_BADCON_S,
+	 {{C_ATU_ERR_INFO_ATS_ODP_CONFIG, C_ATU_ERR_INFO_ATS_ODP_CONFIG_SIZE,
+	   "C_ATU_ERR_INFO_ATS_ODP_CONFIG"},
+	  },
+	 {{0x10020568, "client_rsp_not_ok", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{43, 1, "addr_out_of_range", C_EC_BADCON_S,
+	 {{C_ATU_ERR_INFO_ADDR_OUT_OF_RANGE,
+	   C_ATU_ERR_INFO_ADDR_OUT_OF_RANGE_SIZE,
+	   "C_ATU_ERR_INFO_ADDR_OUT_OF_RANGE"},
+	  },
+	 {{0x10020568, "client_rsp_not_ok", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{44, 1, "ats_page_size_config_err", C_EC_BADCON_S,
+	 {{C_ATU_ERR_INFO_ATS_PAGE_SIZE_CONFIG,
+	   C_ATU_ERR_INFO_ATS_PAGE_SIZE_CONFIG_SIZE,
+	   "C_ATU_ERR_INFO_ATS_PAGE_SIZE_CONFIG"},
+	  },
+	 {},
+	 },
+	{45, 1, "ats_page_size_err", C_EC_BADCON_S,
+	 {{C_ATU_ERR_INFO_ATS_PAGE_SIZE, C_ATU_ERR_INFO_ATS_PAGE_SIZE_SIZE,
+	   "C_ATU_ERR_INFO_ATS_PAGE_SIZE"},
+	  },
+	 {{0x10020568, "client_rsp_not_ok", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{46, 1, "p_tarb_cdt_uflow", C_EC_CRIT},
+	{47, 1, "np_tarb_cdt_uflow", C_EC_CRIT},
+	{48, 1, "ee_odp_req_err", C_EC_BADCON_S,
+	 {{C_ATU_ERR_INFO_EE_ODP_REQ, C_ATU_ERR_INFO_EE_ODP_REQ_SIZE,
+	   "C_ATU_ERR_INFO_EE_ODP_REQ"},
+	  },
+	 {{0x10020568, "client_rsp_not_ok", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{49, 1, "ats_fn_disabled_err", C_EC_BADCON_S,
+	 {{C_ATU_ERR_INFO_ATS_FN_DISABLED, C_ATU_ERR_INFO_ATS_FN_DISABLED_SIZE,
+	   "C_ATU_ERR_INFO_ATS_FN_DISABLED"},
+	  },
+	 {},
+	 },
+	{50, 1, "rarb_hw_err", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_RARB, C_ATU_ERR_INFO_RARB_SIZE,
+	   "C_ATU_ERR_INFO_RARB"},
+	  },
+	 {},
+	 },
+	{51, 1, "epoch_cnt_err", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_EPOCH_CNT, C_ATU_ERR_INFO_EPOCH_CNT_SIZE,
+	   "C_ATU_ERR_INFO_EPOCH_CNT"},
+	  },
+	 {},
+	 },
+	{52, 1, "rspq_cmpl_err", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_RSPQ_CMPL, C_ATU_ERR_INFO_RSPQ_CMPL_SIZE,
+	   "C_ATU_ERR_INFO_RSPQ_CMPL"},
+	  },
+	 {{0x10020568, "client_rsp_not_ok", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{53, 1, "odp_unexp_idx_err", C_EC_BADCON_S,
+	 {{C_ATU_ERR_INFO_ODP_UNEXP_IDX, C_ATU_ERR_INFO_ODP_UNEXP_IDX_SIZE,
+	   "C_ATU_ERR_INFO_ODP_UNEXP_IDX"},
+	  },
+	 {},
+	 },
+	{54, 1, "in_progress_cnt_err", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_IN_PROGRESS_CNT, C_ATU_ERR_INFO_IN_PROGRESS_CNT_SIZE,
+	   "C_ATU_ERR_INFO_IN_PROGRESS_CNT"},
+	  },
+	 {},
+	 },
+	{64, 1}
+};
+
+static const struct flg_err_info atu_ext_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "ac_mem_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{2, 1, "otb_mem_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{3, 1, "tag_mem_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{4, 1, "ingress_bus_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{5, 1, "data_mem_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{6, 1, "chain_tail_mem_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{7, 1, "chain_next_mem_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{8, 1, "missq_mem_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{9, 1, "uniqq_mem_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{10, 1, "chain_mem_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{11, 1, "pointer_mem_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{12, 1, "replayq_mem_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{13, 1, "retryq_mem_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{14, 1, "prb_mem_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{15, 1, "invalq_mem_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{16, 1, "rspinfoq_mem_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{17, 1, "cmpldata_mem_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{18, 1, "atucq_mem_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{19, 1, "ats_prq_mem_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{20, 1, "rarb_hdr_bus_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{21, 1, "rarb_data_bus_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{22, 1, "odpq_mem_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{33, 1, "ac_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{34, 1, "otb_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{35, 1, "tag_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{36, 1, "ingress_bus_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{37, 1, "data_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{38, 1, "chain_tail_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{39, 1, "chain_next_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{40, 1, "missq_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{41, 1, "uniqq_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{42, 1, "chain_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{43, 1, "pointer_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{44, 1, "replayq_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{45, 1, "retryq_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{46, 1, "prb_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{47, 1, "invalq_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{48, 1, "rspinfoq_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{49, 1, "cmpldata_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{50, 1, "atucq_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{51, 1, "ats_prq_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{52, 1, "rarb_hdr_bus_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{53, 1, "rarb_data_bus_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{54, 1, "odpq_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{56, 1, "anchor_vld_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{57, 1, "anchor_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{64, 1}
+};
+
+static const struct flg_err_info cq_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "crnc_ring_sync_error", C_EC_UNCOR_NS},
+	{2, 1, "crnc_ring_ecc_sbe", C_EC_COR},
+	{3, 1, "crnc_ring_ecc_mbe", C_EC_UNCOR_NS},
+	{4, 1, "crnc_ring_cmd_unknown", C_EC_UNCOR_NS},
+	{5, 1, "crnc_csr_cmd_unknown", C_EC_UNCOR_NS},
+	{6, 1, "crnc_csr_cmd_incomplete", C_EC_UNCOR_NS},
+	{7, 1, "crnc_buf_ecc_sbe", C_EC_COR},
+	{8, 1, "crnc_buf_ecc_mbe", C_EC_UNCOR_NS},
+	{16, 1, "fifo_err", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_FIFO_ERR, C_CQ_ERR_INFO_FIFO_ERR_SIZE,
+	   "C_CQ_ERR_INFO_FIFO_ERR"},
+	  },
+	 {},
+	 },
+	{17, 1, "credit_uflw", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_CC, C_CQ_ERR_INFO_CC_SIZE, "C_CQ_ERR_INFO_CC"},
+	  },
+	 {},
+	 },
+	{18, 1, "c_state_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{19, 1, "rarb_hdr_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{20, 1, "rarb_data_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{21, 1, "event_ram_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{22, 1, "ll_state_mem_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{23, 1, "ll_status_mem_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{24, 1, "c_state_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{25, 1, "rarb_hdr_ucor", C_EC_CRIT,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{26, 1, "rarb_data_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{27, 1, "event_ram_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{28, 1, "ll_state_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{29, 1, "ll_status_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{30, 1, "ll_nempty_vectr_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{31, 1, "ll_full_vectr_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{32, 1, "event_cnt_ovf", C_EC_INFO},
+	{33, 1, "tle_oversubscribed", C_EC_BADCON_NS},
+	{34, 1, "rarb_bad_xactn_err", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_RARB, C_CQ_ERR_INFO_RARB_SIZE, "C_CQ_ERR_INFO_RARB"},
+	  },
+	 {{0x100038, "rarb_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{35, 1, "rarb_cmpltn_err", C_EC_CRIT,
+	 {{C_CQ_ERR_INFO_RARB, C_CQ_ERR_INFO_RARB_SIZE, "C_CQ_ERR_INFO_RARB"},
+	  },
+	 {{0x100038, "rarb_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{36, 1, "rarb_tou_wr_hw_err", C_EC_UNCOR_S,
+	 {{C_CQ_ERR_INFO_RARB, C_CQ_ERR_INFO_RARB_SIZE, "C_CQ_ERR_INFO_RARB"},
+	  },
+	 {{0x100038, "rarb_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{37, 1, "rarb_ll_wr_hw_err", C_EC_UNCOR_S,
+	 {{C_CQ_ERR_INFO_RARB_LL, C_CQ_ERR_INFO_RARB_LL_SIZE,
+	   "C_CQ_ERR_INFO_RARB_LL"},
+	  },
+	 {{0x100030, "rarb_ll_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{38, 1, "rarb_invld_wr_sw_err", C_EC_BADCON_NS,
+	 {{C_CQ_ERR_INFO_RARB, C_CQ_ERR_INFO_RARB_SIZE, "C_CQ_ERR_INFO_RARB"},
+	  },
+	 {{0x100038, "rarb_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{39, 1, "rarb_tou_wr_sw_err", C_EC_BADCON_S,
+	 {{C_CQ_ERR_INFO_RARB, C_CQ_ERR_INFO_RARB_SIZE, "C_CQ_ERR_INFO_RARB"},
+	  },
+	 {{0x100038, "rarb_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{40, 1, "rarb_ll_wr_sw_err", C_EC_BADCON_S,
+	 {{C_CQ_ERR_INFO_RARB_LL, C_CQ_ERR_INFO_RARB_LL_SIZE,
+	   "C_CQ_ERR_INFO_RARB_LL"},
+	  },
+	 {{0x100030, "rarb_ll_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{41, 1, "msg_cnt_uflw", C_EC_BADCON_S,
+	 {{C_CQ_ERR_INFO_OCU_MAP, C_CQ_ERR_INFO_OCU_MAP_SIZE,
+	   "C_CQ_ERR_INFO_OCU_MAP"},
+	  },
+	 {},
+	 },
+	{42, 1, "fq_load_uflw", C_EC_BADCON_S,
+	 {{C_CQ_ERR_INFO_OCU_MAP, C_CQ_ERR_INFO_OCU_MAP_SIZE,
+	   "C_CQ_ERR_INFO_OCU_MAP"},
+	  },
+	 {},
+	 },
+	{43, 1, "wr_ptr_updt_err", C_EC_BADCON_S,
+	 {{C_CQ_ERR_INFO_WR_PTR_UPDT, C_CQ_ERR_INFO_WR_PTR_UPDT_SIZE,
+	   "C_CQ_ERR_INFO_WR_PTR_UPDT"},
+	  },
+	 {{0x100040, "wr_ptr_updt_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{44, 1, "ard_ptr_update_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{45, 1, "tx_fqu_free_list_ovf", C_EC_BADCON_S},
+	{46, 1, "tou_fqu_free_list_ovf", C_EC_BADCON_S},
+	{64, 1}
+};
+
+static const struct flg_err_info cq_ext_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "remap_array_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{2, 1, "cprof_table_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{3, 1, "ac_remap_array_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{4, 1, "tou_fq_cmd_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{5, 1, "cq_fq_cmd_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{6, 1, "tou_fid_list_ptrs_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{7, 1, "cq_fid_list_ptrs_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{8, 1, "ll_buf_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{9, 1, "tx_ptr_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{10, 1, "tx_base_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{11, 1, "tx_ocuset_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{12, 1, "tg_ptr_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{13, 1, "tg_base_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{14, 1, "pfq_bufs_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{15, 1, "pfq_bufs_info_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{16, 1, "pfq_ptrs_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{17, 1, "target_pfq_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{18, 1, "tu_pfq_bufs_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{19, 1, "tu_pfq_info_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{20, 1, "tu_pfq_list_ptrs_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{21, 1, "ct_table_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{22, 1, "ee_table_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{23, 1, "ptlte_table_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{24, 1, "ct_events_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{25, 1, "thresh_table_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{26, 1, "trig_ct_field_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{27, 1, "trig_list_nodes_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{28, 1, "tou_ll_reorder_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{29, 1, "tou_cmd_ptrs_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{30, 1, "in_fifo_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{31, 1, "wb_addr_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{33, 1, "remap_array_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{34, 1, "cprof_table_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{35, 1, "ac_remap_array_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{36, 1, "tou_fq_cmd_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{37, 1, "cq_fq_cmd_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{38, 1, "tou_fid_list_ptrs_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{39, 1, "cq_fid_list_ptrs_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{40, 1, "ll_buf_ucor", C_EC_TRNSNT_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{41, 1, "tx_ptr_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{42, 1, "tx_base_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{43, 1, "tx_ocuset_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{44, 1, "tg_ptr_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{45, 1, "tg_base_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{46, 1, "pfq_bufs_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{47, 1, "pfq_bufs_info_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{48, 1, "pfq_ptrs_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{49, 1, "target_pfq_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{50, 1, "tu_pfq_bufs_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{51, 1, "tu_pfq_info_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{52, 1, "tu_pfq_list_ptrs_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{53, 1, "ct_table_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{54, 1, "ee_table_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{55, 1, "ptlte_table_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{56, 1, "ct_events_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{57, 1, "thresh_table_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{58, 1, "trig_ct_field_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{59, 1, "trig_list_nodes_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{60, 1, "tou_ll_reorder_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{61, 1, "tou_cmd_ptrs_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{62, 1, "in_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{63, 1, "wb_addr_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{64, 1}
+};
+
+static const struct flg_err_info ee_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "crnc_ring_sync_error", C_EC_UNCOR_NS},
+	{2, 1, "crnc_ring_ecc_sbe", C_EC_COR},
+	{3, 1, "crnc_ring_ecc_mbe", C_EC_UNCOR_NS},
+	{4, 1, "crnc_ring_cmd_unknown", C_EC_UNCOR_NS},
+	{5, 1, "crnc_csr_cmd_unknown", C_EC_UNCOR_NS},
+	{6, 1, "crnc_csr_cmd_incomplete", C_EC_UNCOR_NS},
+	{7, 1, "crnc_buf_ecc_sbe", C_EC_COR},
+	{8, 1, "crnc_buf_ecc_mbe", C_EC_UNCOR_NS},
+	{32, 1, "eq_ovflw_rsrvn", C_EC_BADCON_S,
+	 {{C_EE_ERR_INFO_EQ_CFG, C_EE_ERR_INFO_EQ_CFG_SIZE,
+	   "C_EE_ERR_INFO_EQ_CFG"},
+	  },
+	 {},
+	 },
+	{33, 1, "eq_ovflw_fc_sc", C_EC_BADCON_S,
+	 {{C_EE_ERR_INFO_EQ_CFG, C_EE_ERR_INFO_EQ_CFG_SIZE,
+	   "C_EE_ERR_INFO_EQ_CFG"},
+	  },
+	 {},
+	 },
+	{34, 1, "eq_ovflw_ordinary", C_EC_BADCON_S,
+	 {{C_EE_ERR_INFO_EQ_CFG, C_EE_ERR_INFO_EQ_CFG_SIZE,
+	   "C_EE_ERR_INFO_EQ_CFG"},
+	  },
+	 {},
+	 },
+	{35, 1, "eq_dsabld_event", C_EC_BADCON_NS,
+	 {{C_EE_ERR_INFO_EQ_CFG, C_EE_ERR_INFO_EQ_CFG_SIZE,
+	   "C_EE_ERR_INFO_EQ_CFG"},
+	  },
+	 {{0x100E50, "eq_dsabld_event_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{36, 1, "eq_dsabld_sw_state_wr", C_EC_BADCON_NS,
+	 {{C_EE_ERR_INFO_EQ_CFG, C_EE_ERR_INFO_EQ_CFG_SIZE,
+	   "C_EE_ERR_INFO_EQ_CFG"},
+	  },
+	 {{0x100E58, "eq_dsabld_sws_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{37, 1, "eq_dsabld_lpe_query", C_EC_BADCON_NS,
+	 {{C_EE_ERR_INFO_EQ_CFG, C_EE_ERR_INFO_EQ_CFG_SIZE,
+	   "C_EE_ERR_INFO_EQ_CFG"},
+	  },
+	 {{0x100E60, "eq_dsabld_lpeq_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{38, 1, "eq_rsrvn_uflw", C_EC_CRIT,
+	 {{C_EE_ERR_INFO_RSRVN_UFLW, C_EE_ERR_INFO_RSRVN_UFLW_SIZE,
+	   "C_EE_ERR_INFO_RSRVN_UFLW"},
+	  },
+	 {{0x100E68, "eq_rsrvn_uflw_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{39, 1, "unxpctd_trnsltn_rsp", C_EC_CRIT,
+	 {{C_EE_ERR_INFO_TRNSLTN, C_EE_ERR_INFO_TRNSLTN_SIZE,
+	   "C_EE_ERR_INFO_TRNSLTN"},
+	  },
+	 {{0x100E70, "unxpctd_trnsltn_rsp_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{40, 1, "rarb_hw_err", C_EC_UNCOR_NS,
+	 {{C_EE_ERR_INFO_RARB, C_EE_ERR_INFO_RARB_SIZE, "C_EE_ERR_INFO_RARB"},
+	  },
+	 {{0x100E78, "rarb_hw_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{41, 1, "rarb_sw_err", C_EC_BADCON_NS,
+	 {{C_EE_ERR_INFO_RARB, C_EE_ERR_INFO_RARB_SIZE, "C_EE_ERR_INFO_RARB"},
+	  },
+	 {{0x100E80, "rarb_sw_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{42, 1, "tarb_err", C_EC_UNCOR_NS,
+	 {{C_EE_ERR_INFO_TARB, C_EE_ERR_INFO_TARB_SIZE, "C_EE_ERR_INFO_TARB"},
+	  },
+	 {{0x100E88, "tarb_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{43, 1, "eq_state_ucor", C_EC_UNCOR_NS,
+	 {{C_EE_ERR_INFO_EQ_UCOR, C_EE_ERR_INFO_EQ_UCOR_SIZE,
+	   "C_EE_ERR_INFO_EQ_UCOR"},
+	  },
+	 {{0x100E90, "eq_state_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{48, 1, "unxpctd_cq_cdt", C_EC_CRIT},
+	{49, 1, "unxpctd_tarb_cdt", C_EC_CRIT},
+	{50, 1, "eq_state_updt_urun", C_EC_CRIT},
+	{51, 1, "eq_state_updt_orun", C_EC_CRIT},
+	{64, 1}
+};
+
+static const struct flg_err_info ee_ext_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "leo_mem_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{2, 1, "pts_mem_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{3, 1, "ixe_bus_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{4, 1, "lpe_bus_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{5, 1, "mst_bus_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{6, 1, "pct_bus_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{7, 1, "hni_bus_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{8, 1, "cq_bus_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{9, 1, "eqd_mem_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{10, 1, "eqsws_mem_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{11, 1, "eqhws_mem_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{12, 1, "ecbsb_mem_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{13, 1, "ecb_mem_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{14, 1, "rarb_hdr_bus_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{15, 1, "rarb_data_bus_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{16, 1, "acb_vect_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{17, 1, "eqswupd_vect_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{18, 1, "lm_cbeq_mem_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{19, 1, "lm_state_vect_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{20, 1, "trnrsp_mem_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{21, 1, "trnrsp_bus_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{22, 1, "rlscb_vect_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{23, 1, "trncb_vect_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{26, 1, "leo_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{27, 1, "pts_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{28, 1, "ixe_bus_ucor", C_EC_UNCOR_NS,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{29, 1, "lpe_bus_ucor", C_EC_UNCOR_NS,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{30, 1, "mst_bus_ucor", C_EC_UNCOR_NS,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{31, 1, "pct_bus_ucor", C_EC_UNCOR_NS,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{32, 1, "hni_bus_ucor", C_EC_UNCOR_NS,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{33, 1, "cq_bus_ucor", C_EC_UNCOR_NS,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{34, 1, "eqd_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{35, 1, "eqsws_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{36, 1, "eqhws_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{37, 1, "ecbsb_mem_ucor", C_EC_CRIT,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{38, 1, "ecb_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{39, 1, "rarb_hdr_bus_ucor", C_EC_UNCOR_NS,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{40, 1, "rarb_data_bus_ucor", C_EC_UNCOR_NS,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{41, 1, "acb_vect_ucor", C_EC_CRIT,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{42, 1, "lm_cbeq_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{43, 1, "trnrsp_mem_ucor", C_EC_CRIT,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{44, 1, "trnrsp_bus_ucor", C_EC_UNCOR_NS,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{45, 1, "rlscb_vect_ucor", C_EC_CRIT,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{46, 1, "trncb_vect_ucor", C_EC_CRIT,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{49, 1, "ixe_to_ee_urun", C_EC_CRIT},
+	{50, 1, "ixe_to_ee_orun", C_EC_CRIT},
+	{51, 1, "lpe_to_ee_urun", C_EC_CRIT},
+	{52, 1, "lpe_to_ee_orun", C_EC_CRIT},
+	{53, 1, "mst_to_ee_urun", C_EC_CRIT},
+	{54, 1, "mst_to_ee_orun", C_EC_CRIT},
+	{55, 1, "pct_to_ee_urun", C_EC_CRIT},
+	{56, 1, "pct_to_ee_orun", C_EC_CRIT},
+	{57, 1, "hni_to_ee_urun", C_EC_CRIT},
+	{58, 1, "hni_to_ee_orun", C_EC_CRIT},
+	{59, 1, "cq_to_ee_urun", C_EC_CRIT},
+	{60, 1, "cq_to_ee_orun", C_EC_CRIT},
+	{64, 1}
+};
+
+static const struct flg_err_info hni_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "crnc_ring_sync_error", C_EC_UNCOR_NS},
+	{2, 1, "crnc_ring_ecc_sbe", C_EC_COR},
+	{3, 1, "crnc_ring_ecc_mbe", C_EC_UNCOR_NS},
+	{4, 1, "crnc_ring_cmd_unknown", C_EC_UNCOR_NS},
+	{5, 1, "crnc_csr_cmd_unknown", C_EC_UNCOR_NS},
+	{6, 1, "crnc_csr_cmd_incomplete", C_EC_UNCOR_NS},
+	{7, 1, "crnc_buf_ecc_sbe", C_EC_COR},
+	{8, 1, "crnc_buf_ecc_mbe", C_EC_UNCOR_NS},
+	{10, 1, "event_cnt_ovf", C_EC_INFO},
+	{11, 1, "llr_flit_cor", C_EC_COR,
+	 {{C1_HNI_ERR_INFO_ECC, C1_HNI_ERR_INFO_ECC_SIZE,
+	   "C1_HNI_ERR_INFO_ECC"},
+	  },
+	 {{0x1002000, "cor_ecc_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{12, 1, "rx_stat_fifo_cor", C_EC_COR,
+	 {{C1_HNI_ERR_INFO_ECC, C1_HNI_ERR_INFO_ECC_SIZE,
+	   "C1_HNI_ERR_INFO_ECC"},
+	  },
+	 {{0x1002000, "cor_ecc_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{13, 1, "rx_pkt_fifo_cor", C_EC_COR,
+	 {{C1_HNI_ERR_INFO_ECC, C1_HNI_ERR_INFO_ECC_SIZE,
+	   "C1_HNI_ERR_INFO_ECC"},
+	  },
+	 {{0x1002000, "cor_ecc_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{14, 1, "timestamp_cor", C_EC_COR,
+	 {{C1_HNI_ERR_INFO_ECC, C1_HNI_ERR_INFO_ECC_SIZE,
+	   "C1_HNI_ERR_INFO_ECC"},
+	  },
+	 {{0x1002000, "cor_ecc_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{15, 1, "hrp_fifo_cor", C_EC_COR,
+	 {{C1_HNI_ERR_INFO_ECC, C1_HNI_ERR_INFO_ECC_SIZE,
+	   "C1_HNI_ERR_INFO_ECC"},
+	  },
+	 {{0x1002000, "cor_ecc_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{16, 1, "fgfc_fifo_cor", C_EC_COR,
+	 {{C1_HNI_ERR_INFO_ECC, C1_HNI_ERR_INFO_ECC_SIZE,
+	   "C1_HNI_ERR_INFO_ECC"},
+	  },
+	 {{0x1002000, "cor_ecc_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{17, 1, "tx_flit_cor", C_EC_COR,
+	 {{C1_HNI_ERR_INFO_ECC, C1_HNI_ERR_INFO_ECC_SIZE,
+	   "C1_HNI_ERR_INFO_ECC"},
+	  },
+	 {{0x1002000, "cor_ecc_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{18, 1, "event_ram_cor", C_EC_COR,
+	 {{C1_HNI_ERR_INFO_ECC, C1_HNI_ERR_INFO_ECC_SIZE,
+	   "C1_HNI_ERR_INFO_ECC"},
+	  },
+	 {{0x1002000, "cor_ecc_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{19, 1, "llr_flit_ucor", C_EC_UNCOR_NS,
+	 {{C1_HNI_ERR_INFO_ECC, C1_HNI_ERR_INFO_ECC_SIZE,
+	   "C1_HNI_ERR_INFO_ECC"},
+	  },
+	 {{0x1002008, "ucor_ecc_err_cntr", C_ERR_INDEX_NONE},
+	  {0x10021A8, "rx_bad_ieee", C_ERR_INDEX_NONE},
+	  {0x10021B0, "rx_bad_opt", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{20, 1, "rx_stat_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C1_HNI_ERR_INFO_ECC, C1_HNI_ERR_INFO_ECC_SIZE,
+	   "C1_HNI_ERR_INFO_ECC"},
+	  },
+	 {{0x1002008, "ucor_ecc_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{21, 1, "rx_pkt_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C1_HNI_ERR_INFO_ECC, C1_HNI_ERR_INFO_ECC_SIZE,
+	   "C1_HNI_ERR_INFO_ECC"},
+	  },
+	 {{0x1002008, "ucor_ecc_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{22, 1, "timestamp_ucor", C_EC_UNCOR_NS,
+	 {{C1_HNI_ERR_INFO_ECC, C1_HNI_ERR_INFO_ECC_SIZE,
+	   "C1_HNI_ERR_INFO_ECC"},
+	  },
+	 {{0x1002008, "ucor_ecc_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{23, 1, "hrp_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C1_HNI_ERR_INFO_ECC, C1_HNI_ERR_INFO_ECC_SIZE,
+	   "C1_HNI_ERR_INFO_ECC"},
+	  },
+	 {{0x1002008, "ucor_ecc_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{24, 1, "fgfc_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C1_HNI_ERR_INFO_ECC, C1_HNI_ERR_INFO_ECC_SIZE,
+	   "C1_HNI_ERR_INFO_ECC"},
+	  },
+	 {{0x1002008, "ucor_ecc_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{25, 1, "tx_flit_ucor", C_EC_UNCOR_NS,
+	 {{C1_HNI_ERR_INFO_ECC, C1_HNI_ERR_INFO_ECC_SIZE,
+	   "C1_HNI_ERR_INFO_ECC"},
+	  },
+	 {{0x1002008, "ucor_ecc_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{26, 1, "event_ram_ucor", C_EC_UNCOR_NS,
+	 {{C1_HNI_ERR_INFO_ECC, C1_HNI_ERR_INFO_ECC_SIZE,
+	   "C1_HNI_ERR_INFO_ECC"},
+	  },
+	 {{0x1002008, "ucor_ecc_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{27, 1, "fifo_err", C_EC_UNCOR_NS,
+	 {{C1_HNI_ERR_INFO_FIFO, C1_HNI_ERR_INFO_FIFO_SIZE,
+	   "C1_HNI_ERR_INFO_FIFO"},
+	  },
+	 {},
+	 },
+	{28, 1, "llr_chksum_bad", C_EC_UNCOR_NS, {},
+	 {{0x10021B0, "rx_bad_opt", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{29, 1, "llr_fcs_bad", C_EC_UNCOR_NS, {},
+	 {{0x10021A8, "rx_bad_ieee", C_ERR_INDEX_NONE},
+	  {0x10021B0, "rx_bad_opt", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{30, 1, "llr_ctrl_perr", C_EC_UNCOR_NS, {},
+	 {{0x10021A8, "rx_bad_ieee", C_ERR_INDEX_NONE},
+	  {0x10021B0, "rx_bad_opt", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{31, 1, "llr_exceed_mfs", C_EC_UNCOR_NS, {},
+	 {{0x10021F0, "rx_ok_too_long", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{32, 1, "llr_eopb", C_EC_UNCOR_NS, {},
+	 {{0x10021A8, "rx_bad_ieee", C_ERR_INDEX_NONE},
+	  {0x10021B0, "rx_bad_opt", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{33, 1, "rx_ctrl_perr", C_EC_CRIT},
+	{34, 1, "pause_timeout", C_EC_BADCON_NS,
+	 {{C_HNI_STS_PAUSE_TIMEOUT, C_HNI_STS_PAUSE_TIMEOUT_SIZE,
+	   "C_HNI_STS_PAUSE_TIMEOUT"},
+	  },
+	 {},
+	 },
+	{35, 1, "fgfc_err", C_EC_UNCOR_NS,
+	 {{C1_HNI_ERR_INFO_FGFC, C1_HNI_ERR_INFO_FGFC_SIZE,
+	   "C1_HNI_ERR_INFO_FGFC"},
+	  },
+	 {},
+	 },
+	{36, 1, "credit_uflw", C_EC_UNCOR_NS,
+	 {{C1_HNI_ERR_INFO_CC, C1_HNI_ERR_INFO_CC_SIZE, "C1_HNI_ERR_INFO_CC"},
+	  },
+	 {},
+	 },
+	{37, 1, "tx_ctrl_perr", C_EC_UNCOR_NS},
+	{38, 1, "tx_size_err", C_EC_UNCOR_NS,
+	 {{C1_HNI_ERR_INFO_SIZE_ERR, C1_HNI_ERR_INFO_SIZE_ERR_SIZE,
+	   "C1_HNI_ERR_INFO_SIZE_ERR"},
+	  },
+	 {{0x10023F0, "tx_std_size_err", C_ERR_INDEX_NONE},
+	  {0x10023F8, "tx_opt_size_err", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{39, 1, "rx_pause_err", C_EC_BADCON_NS},
+	{40, 8, "pfc_fifo_oflw", C_EC_CRIT, {},
+	 {{0x1002080, "pfc_fifo_oflw_cntr", C_ERR_INDEX_MATCH},
+	  },
+	 },
+	{48, 8, "discard_err", C_EC_UNCOR_NS,
+	 {{C1_HNI_ERR_INFO_DISCARD, C1_HNI_ERR_INFO_DISCARD_SIZE,
+	   "C1_HNI_ERR_INFO_DISCARD"},
+	  },
+	 {{0x10020C0, "discard_cntr", C_ERR_INDEX_MATCH},
+	  },
+	 },
+	{56, 8, "disable_err", C_EC_UNCOR_NS},
+	{64, 1}
+};
+
+static const struct flg_err_info ixe_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "crnc_ring_sync_error", C_EC_UNCOR_NS},
+	{2, 1, "crnc_ring_ecc_sbe", C_EC_COR},
+	{3, 1, "crnc_ring_ecc_mbe", C_EC_UNCOR_NS},
+	{4, 1, "crnc_ring_cmd_unknown", C_EC_UNCOR_NS},
+	{5, 1, "crnc_csr_cmd_unknown", C_EC_UNCOR_NS},
+	{6, 1, "crnc_csr_cmd_incomplete", C_EC_UNCOR_NS},
+	{7, 1, "crnc_buf_ecc_sbe", C_EC_COR},
+	{8, 1, "crnc_buf_ecc_mbe", C_EC_UNCOR_NS},
+	{32, 1, "pafa_perr", C_EC_UNCOR_NS},
+	{33, 1, "fifo_err", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_FIFO_ERR, C_IXE_ERR_INFO_FIFO_ERR_SIZE,
+	   "C_IXE_ERR_INFO_FIFO_ERR"},
+	  },
+	 {},
+	 },
+	{34, 1, "credit_uflw", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_CC, C_IXE_ERR_INFO_CC_SIZE, "C_IXE_ERR_INFO_CC"},
+	  },
+	 {},
+	 },
+	{35, 1, "pcie_unsuccess_cmpl", C_EC_BADCON_S,
+	 {{C_IXE_ERR_INFO_PCIE_UC, C_IXE_ERR_INFO_PCIE_UC_SIZE,
+	   "C_IXE_ERR_INFO_PCIE_UC"},
+	  },
+	 {{0x9870A10, "dmawr_pcie_unsuccess_cmpl", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{36, 1, "pcie_error_poisoned", C_EC_UNCOR_S,
+	 {{C_IXE_ERR_INFO_PCIE_EP, C_IXE_ERR_INFO_PCIE_EP_SIZE,
+	   "C_IXE_ERR_INFO_PCIE_EP"},
+	  },
+	 {{0x9870A18, "dmawr_pcie_err_poisoned", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{37, 1, "port_dfa_mismatch", C_EC_UNCOR_NS, {},
+	 {{0x9870520, "port_dfa_mismatch", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{38, 1, "port_discard_trig", C_EC_INFO,
+	 {{C_IXE_CFG_DISCARD, C_IXE_CFG_DISCARD_SIZE, "C_IXE_CFG_DISCARD"},
+	  },
+	 {},
+	 },
+	{39, 1, "hdr_checksum_err", C_EC_TRNSNT_NS, {},
+	 {{0x9870528, "hdr_checksum_errors", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{40, 1, "hdr_ecc_err", C_EC_TRNSNT_NS, {},
+	 {{0x9870568, "hdr_ecc_errors", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{41, 1, "get_len_err", C_EC_TRNSNT_NS, {},
+	 {{0x9870548, "get_len_errors", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{42, 1, "ipv4_checksum_err", C_EC_TRNSNT_NS,
+	 {{C_IXE_ERR_INFO_ETH_PARSE, C_IXE_ERR_INFO_ETH_PARSE_SIZE,
+	   "C_IXE_ERR_INFO_ETH_PARSE"},
+	  },
+	 {{0x9870530, "ipv4_checksum_errors", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{43, 1, "ipv4_options_err", C_EC_TRNSNT_NS,
+	 {{C_IXE_ERR_INFO_ETH_PARSE, C_IXE_ERR_INFO_ETH_PARSE_SIZE,
+	   "C_IXE_ERR_INFO_ETH_PARSE"},
+	  },
+	 {{0x9870540, "ip_options_errors", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{44, 1, "ipv6_options_err", C_EC_TRNSNT_NS,
+	 {{C_IXE_ERR_INFO_ETH_PARSE, C_IXE_ERR_INFO_ETH_PARSE_SIZE,
+	   "C_IXE_ERR_INFO_ETH_PARSE"},
+	  },
+	 {{0x9870540, "ip_options_errors", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{45, 1, "hrp_req_err", C_EC_TRNSNT_NS, {},
+	 {{0x9870538, "hrp_req_errors", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{46, 1, "parser_disable", C_EC_CRIT},
+	{47, 1, "pbuf_pkt_perr", C_EC_DEGRD_NS, {},
+	 {{0x9870558, "parser_par_errors", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{48, 1, "pbuf_rd_err", C_EC_DEGRD_NS, {},
+	 {{0x9870560, "pbuf_rd_errors", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{49, 1, "pkt_flit_fifo_perr", C_EC_TRNSNT_NS, {},
+	 {{0x9870558, "parser_par_errors", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{50, 1, "amo_align_err", C_EC_BADCON_S,
+	 {{C_IXE_ERR_INFO_AMO_OP, C_IXE_ERR_INFO_AMO_OP_SIZE,
+	   "C_IXE_ERR_INFO_AMO_OP"},
+	  },
+	 {{0x98709F8, "dmawr_amo_misaligned", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{51, 1, "amo_op_err", C_EC_BADCON_S,
+	 {{C_IXE_ERR_INFO_AMO_OP, C_IXE_ERR_INFO_AMO_OP_SIZE,
+	   "C_IXE_ERR_INFO_AMO_OP"},
+	  },
+	 {{0x9870A00, "dmawr_amo_invalid_op", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{52, 1, "amo_fp_inexact", C_EC_INFO,
+	 {{C_IXE_ERR_INFO_FP_INEXACT, C_IXE_ERR_INFO_FP_INEXACT_SIZE,
+	   "C_IXE_ERR_INFO_FP_INEXACT"},
+	  },
+	 {{0x98709F0, "dmawr_amo_ex_inexact", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{53, 1, "amo_fp_overflow", C_EC_INFO,
+	 {{C_IXE_ERR_INFO_FP_OVERFLOW, C_IXE_ERR_INFO_FP_OVERFLOW_SIZE,
+	   "C_IXE_ERR_INFO_FP_OVERFLOW"},
+	  },
+	 {{0x98709E0, "dmawr_amo_ex_overflow", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{54, 1, "amo_fp_underflow", C_EC_INFO,
+	 {{C_IXE_ERR_INFO_FP_UNDERFLOW, C_IXE_ERR_INFO_FP_UNDERFLOW_SIZE,
+	   "C_IXE_ERR_INFO_FP_UNDERFLOW"},
+	  },
+	 {{0x98709E8, "dmawr_amo_ex_underflow", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{55, 1, "amo_fp_invalid", C_EC_INFO,
+	 {{C_IXE_ERR_INFO_FP_INVALID, C_IXE_ERR_INFO_FP_INVALID_SIZE,
+	   "C_IXE_ERR_INFO_FP_INVALID"},
+	  },
+	 {{0x98709D8, "dmawr_amo_ex_invalid", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{56, 1, "rarb_hw_err", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_RARB, C_IXE_ERR_INFO_RARB_SIZE,
+	   "C_IXE_ERR_INFO_RARB"},
+	  },
+	 {},
+	 },
+	{57, 1, "amo_length_err", C_EC_BADCON_S,
+	 {{C_IXE_ERR_INFO_AMO_LENGTH, C_IXE_ERR_INFO_AMO_LENGTH_SIZE,
+	   "C_IXE_ERR_INFO_AMO_LENGTH"},
+	  },
+	 {{0x9870A08, "dmawr_amo_len_err", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{58, 1, "pbuf_overflow", C_EC_CRIT},
+	{64, 1}
+};
+
+static const struct flg_err_info ixe_ext_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "flop_fifo_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{2, 1, "put_resp_mem_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{3, 1, "get_req_mem_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{4, 1, "rdfq_list_mem_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{5, 1, "wr_md_mem_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{6, 1, "event_fifo_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{7, 1, "wr_ev_mem_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{8, 1, "pkt_flit_fifo_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{9, 1, "pbuf_list_mem_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{10, 1, "pbuf_sb_mem_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{11, 1, "atu_resp_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{12, 1, "rdoq_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{13, 1, "ingressq_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{14, 1, "info_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{15, 1, "cmd_info_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{16, 1, "sideband_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{17, 1, "p_cmd_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{18, 1, "np_cmd_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{19, 1, "amo_info_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{20, 1, "addr_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{21, 1, "rd_buf_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{22, 1, "ack_rd_buf_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{23, 1, "hni_flit_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{24, 1, "rpu_list_mem_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{25, 1, "rpu_st_mem_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{26, 1, "rarb_hdr_bus_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{27, 1, "rarb_data_bus_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{28, 1, "pbuf_flit_mem_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{33, 1, "flop_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{34, 1, "put_resp_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{35, 1, "get_req_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{36, 1, "rdfq_list_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{37, 1, "wr_md_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{38, 1, "event_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{39, 1, "wr_ev_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{40, 1, "pkt_flit_fifo_ucor", C_EC_TRNSNT_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{41, 1, "pbuf_list_mem_ucor", C_EC_TRNSNT_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{42, 1, "pbuf_sb_mem_ucor", C_EC_TRNSNT_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{43, 1, "atu_resp_ucor", C_EC_TRNSNT_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{44, 1, "rdoq_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{45, 1, "ingressq_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{46, 1, "info_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{47, 1, "cmd_info_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{48, 1, "sideband_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{49, 1, "p_cmd_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{50, 1, "np_cmd_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{51, 1, "amo_info_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{52, 1, "addr_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{53, 1, "rd_buf_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{54, 1, "ack_rd_buf_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{55, 1, "hni_flit_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{56, 1, "rpu_list_mem_ucor", C_EC_CRIT,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{57, 1, "rpu_st_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{58, 1, "rarb_hdr_bus_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{59, 1, "rarb_data_bus_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{60, 1, "pbuf_flit_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{64, 1}
+};
+
+static const struct flg_err_info lpe_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "crnc_ring_sync_error", C_EC_UNCOR_NS},
+	{2, 1, "crnc_ring_ecc_sbe", C_EC_COR},
+	{3, 1, "crnc_ring_ecc_mbe", C_EC_UNCOR_NS},
+	{4, 1, "crnc_ring_cmd_unknown", C_EC_UNCOR_NS},
+	{5, 1, "crnc_csr_cmd_unknown", C_EC_UNCOR_NS},
+	{6, 1, "crnc_csr_cmd_incomplete", C_EC_UNCOR_NS},
+	{7, 1, "crnc_buf_ecc_sbe", C_EC_COR},
+	{8, 1, "crnc_buf_ecc_mbe", C_EC_UNCOR_NS},
+	{9, 1, "event_cnt_ovf", C_EC_INFO},
+	{10, 1, "le_oversubscribed", C_EC_BADCON_NS},
+	{12, 1, "illegal_op", C_EC_BADCON_NS,
+	 {{C_LPE_ERR_INFO_NET_HDR, C_LPE_ERR_INFO_NET_HDR_SIZE,
+	   "C_LPE_ERR_INFO_NET_HDR"},
+	  },
+	 {},
+	 },
+	{13, 1, "src_error", C_EC_BADCON_NS,
+	 {{C_LPE_ERR_INFO_NET_HDR, C_LPE_ERR_INFO_NET_HDR_SIZE,
+	   "C_LPE_ERR_INFO_NET_HDR"},
+	  },
+	 {},
+	 },
+	{14, 1, "delayed", C_EC_BADCON_NS,
+	 {{C_LPE_ERR_INFO_NET_HDR, C_LPE_ERR_INFO_NET_HDR_SIZE,
+	   "C_LPE_ERR_INFO_NET_HDR"},
+	  },
+	 {},
+	 },
+	{15, 1, "restricted_unicast", C_EC_BADCON_NS,
+	 {{C_LPE_ERR_INFO_NET_HDR, C_LPE_ERR_INFO_NET_HDR_SIZE,
+	   "C_LPE_ERR_INFO_NET_HDR"},
+	  },
+	 {},
+	 },
+	{16, 1, "no_space", C_EC_BADCON_NS,
+	 {{C_LPE_ERR_INFO_NET_HDR, C_LPE_ERR_INFO_NET_HDR_SIZE,
+	   "C_LPE_ERR_INFO_NET_HDR"},
+	  },
+	 {},
+	 },
+	{17, 1, "invalid_endpoint", C_EC_BADCON_NS,
+	 {{C_LPE_ERR_INFO_NET_HDR, C_LPE_ERR_INFO_NET_HDR_SIZE,
+	   "C_LPE_ERR_INFO_NET_HDR"},
+	  },
+	 {},
+	 },
+	{18, 1, "entry_not_found", C_EC_BADCON_NS,
+	 {{C_LPE_ERR_INFO_NET_HDR, C_LPE_ERR_INFO_NET_HDR_SIZE,
+	   "C_LPE_ERR_INFO_NET_HDR"},
+	  },
+	 {},
+	 },
+	{19, 1, "op_violation", C_EC_BADCON_NS,
+	 {{C_LPE_ERR_INFO_NET_HDR, C_LPE_ERR_INFO_NET_HDR_SIZE,
+	   "C_LPE_ERR_INFO_NET_HDR"},
+	  },
+	 {},
+	 },
+	{20, 1, "eq_disabled", C_EC_BADCON_NS,
+	 {{C_LPE_ERR_INFO_NET_HDR, C_LPE_ERR_INFO_NET_HDR_SIZE,
+	   "C_LPE_ERR_INFO_NET_HDR"},
+	  },
+	 {},
+	 },
+	{21, 1, "pt_disabled_fc", C_EC_BADCON_NS,
+	 {{C_LPE_ERR_INFO_NET_HDR, C_LPE_ERR_INFO_NET_HDR_SIZE,
+	   "C_LPE_ERR_INFO_NET_HDR"},
+	  },
+	 {},
+	 },
+	{22, 1, "pt_disabled_dis", C_EC_BADCON_NS,
+	 {{C_LPE_ERR_INFO_NET_HDR, C_LPE_ERR_INFO_NET_HDR_SIZE,
+	   "C_LPE_ERR_INFO_NET_HDR"},
+	  },
+	 {},
+	 },
+	{23, 1, "pt_disabled_rst", C_EC_BADCON_NS,
+	 {{C_LPE_ERR_INFO_NET_HDR, C_LPE_ERR_INFO_NET_HDR_SIZE,
+	   "C_LPE_ERR_INFO_NET_HDR"},
+	  },
+	 {},
+	 },
+	{24, 1, "illegal_cq_op", C_EC_BADCON_NS},
+	{25, 1, "fifo_err", C_EC_UNCOR_NS},
+	{26, 1, "cq_fifo_overrun", C_EC_UNCOR_NS},
+	{27, 1, "cdt_cnt_uflow", C_EC_UNCOR_NS,
+	 {{C_LPE_ERR_INFO_CDT_CNT_UFLOW, C_LPE_ERR_INFO_CDT_CNT_UFLOW_SIZE,
+	   "C_LPE_ERR_INFO_CDT_CNT_UFLOW"},
+	  },
+	 {},
+	 },
+	{28, 1, "mrr_mem_cor", C_EC_COR,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{29, 1, "free_list_mem_cor", C_EC_COR,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{30, 1, "event_ram_cor", C_EC_COR,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{31, 1, "plec_mem_cor", C_EC_COR,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{32, 1, "ptlte_mem_cor", C_EC_COR,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{33, 1, "ixemrq_front_mem_cor", C_EC_COR,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{34, 1, "ixemrq_back_mem_cor", C_EC_COR,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{35, 1, "ixemrq_list_mem_cor", C_EC_COR,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{36, 1, "petcq_list_mem_cor", C_EC_COR,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{37, 1, "list_entry_mem_cor", C_EC_COR,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{38, 1, "cqmrq_front_mem_cor", C_EC_COR,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{39, 1, "cqmrq_back_mem_cor", C_EC_COR,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{40, 1, "cqmrq_list_mem_cor", C_EC_COR,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{41, 1, "rget_ram_mem_cor", C_EC_COR,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{42, 1, "rrq_fifo_cor", C_EC_COR,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{43, 1, "cq_fifo_cor", C_EC_COR,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{45, 1, "rdy_pleq_cor", C_EC_COR,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{46, 1, "mrr_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{47, 1, "free_list_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{48, 1, "event_ram_ucor", C_EC_UNCOR_NS,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{49, 1, "plec_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{50, 1, "ptlte_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{51, 1, "ixemrq_front_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{52, 1, "ixemrq_back_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{53, 1, "ixemrq_list_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{54, 1, "petcq_list_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{55, 1, "list_entry_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{56, 1, "cqmrq_front_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{57, 1, "cqmrq_back_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{58, 1, "cqmrq_list_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{59, 1, "rget_ram_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{60, 1, "rrq_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{61, 1, "cq_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{63, 1, "rdy_pleq_ucor", C_EC_UNCOR_NS,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{64, 1}
+};
+
+static const struct flg_err_info mb_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "crnc_ring_sync_error", C_EC_UNCOR_NS},
+	{2, 1, "crnc_ring_ecc_sbe", C_EC_COR},
+	{3, 1, "crnc_ring_ecc_mbe", C_EC_UNCOR_NS},
+	{4, 1, "crnc_ring_cmd_unknown", C_EC_UNCOR_NS},
+	{5, 1, "crnc_csr_cmd_unknown", C_EC_UNCOR_NS},
+	{6, 1, "crnc_csr_cmd_incomplete", C_EC_UNCOR_NS},
+	{7, 1, "crnc_buf_ecc_sbe", C_EC_COR},
+	{8, 1, "crnc_buf_ecc_mbe", C_EC_UNCOR_NS},
+	{16, 1, "crmc_ring_sync_error", C_EC_UNCOR_NS,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{17, 1, "crmc_ring_ecc_sbe", C_EC_COR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{18, 1, "crmc_ring_ecc_mbe", C_EC_UNCOR_NS,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{19, 1, "crmc_ring_cmd_unknown", C_EC_UNCOR_NS,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{20, 1, "crmc_wr_error", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{21, 1, "crmc_wr_addr_invalid", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{22, 1, "crmc_wr_cmd_invalid", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{23, 1, "crmc_wr_be_invalid", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{24, 1, "crmc_wr_cor_error", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{25, 1, "crmc_wr_uncor_error", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{26, 1, "crmc_wr_burst_error", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{27, 1, "crmc_wr_mcast_nack", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{28, 1, "crmc_wr_rsvd_error", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{29, 1, "crmc_wr_wrapped", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{30, 1, "crmc_wr_timeout", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{31, 1, "crmc_wr_axi_req_error", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{32, 1, "crmc_wr_axi_ring_error", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{33, 1, "crmc_wr_axi_wstrb_error", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{34, 1, "crmc_wr_axi_parity_error", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{35, 1, "crmc_rd_error", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{36, 1, "crmc_rd_addr_invalid", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{37, 1, "crmc_rd_cmd_invalid", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{38, 1, "crmc_rd_be_invalid", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{39, 1, "crmc_rd_cor_error", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{40, 1, "crmc_rd_uncor_error", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{41, 1, "crmc_rd_burst_error", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{42, 1, "crmc_rd_mcast_nack", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{43, 1, "crmc_rd_rsvd_error", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{44, 1, "crmc_rd_wrapped", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{45, 1, "crmc_rd_timeout", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{46, 1, "crmc_rd_axi_req_error", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{47, 1, "crmc_rd_axi_ring_error", C_EC_SFTWR},
+	{48, 4, "cmc_wr_error", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CMC_WR, C_MB_ERR_INFO_CMC_WR_SIZE,
+	   "C_MB_ERR_INFO_CMC_WR"},
+	  },
+	 {},
+	 },
+	{52, 4, "cmc_rd_error", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CMC_RD, C_MB_ERR_INFO_CMC_RD_SIZE,
+	   "C_MB_ERR_INFO_CMC_RD"},
+	  },
+	 {},
+	 },
+	{56, 1, "event_cnt_ovf", C_EC_INFO},
+	{57, 1, "event_ram_cor", C_EC_COR,
+	 {{C_MB_ERR_INFO_MEM, C_MB_ERR_INFO_MEM_SIZE, "C_MB_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{58, 1, "event_ram_ucor", C_EC_UNCOR_NS,
+	 {{C_MB_ERR_INFO_MEM, C_MB_ERR_INFO_MEM_SIZE, "C_MB_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{59, 1, "flash_cache0_cor", C_EC_COR,
+	 {{C_MB_ERR_INFO_MEM, C_MB_ERR_INFO_MEM_SIZE, "C_MB_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{60, 1, "flash_cache0_ucor", C_EC_UNCOR_NS,
+	 {{C_MB_ERR_INFO_MEM, C_MB_ERR_INFO_MEM_SIZE, "C_MB_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{61, 1, "flash_cache1_cor", C_EC_COR,
+	 {{C_MB_ERR_INFO_MEM, C_MB_ERR_INFO_MEM_SIZE, "C_MB_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{62, 1, "flash_cache1_ucor", C_EC_UNCOR_NS,
+	 {{C_MB_ERR_INFO_MEM, C_MB_ERR_INFO_MEM_SIZE, "C_MB_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{63, 1, "spi_ecc_error", C_EC_UNCOR_NS,
+	 {{C_MB_ERR_INFO_SPI, C_MB_ERR_INFO_SPI_SIZE, "C_MB_ERR_INFO_SPI"},
+	  },
+	 {},
+	 },
+	{64, 1}
+};
+
+static const struct flg_err_info mb_ext_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "jai_axi_cadr_unexpected_cmd", C_EC_SFTWR},
+	{2, 1, "jai_axi_cadr_unknown_cmd", C_EC_SFTWR},
+	{3, 1, "jai_axi_wr_decerr", C_EC_SFTWR},
+	{4, 1, "jai_axi_wr_slverr", C_EC_SFTWR},
+	{5, 1, "jai_axi_rd_decerr", C_EC_SFTWR},
+	{6, 1, "jai_axi_rd_slverr", C_EC_SFTWR},
+	{7, 1, "jai_axi_rd_parity_error", C_EC_SFTWR},
+	{8, 1, "flm_csr_init_p1_spi_err", C_EC_CRIT},
+	{9, 1, "flm_csr_init_p2_spi_err", C_EC_CRIT},
+	{10, 1, "flm_csr_init_p1_fail", C_EC_CRIT},
+	{11, 1, "flm_csr_init_p2_fail", C_EC_CRIT},
+	{12, 1, "flm_csr_init_p1_abort", C_EC_CRIT},
+	{13, 1, "flm_csr_init_p2_abort", C_EC_CRIT},
+	{14, 1, "flm_csr_init_p1_len_err", C_EC_CRIT},
+	{15, 1, "flm_csr_init_p2_len_err", C_EC_CRIT},
+	{16, 1, "flm_csr_init_p1_cont_err", C_EC_CRIT},
+	{17, 1, "flm_csr_init_p2_cont_err", C_EC_CRIT},
+	{18, 1, "flm_csr_init_p1_axi_decerr", C_EC_CRIT},
+	{19, 1, "flm_csr_init_p2_axi_decerr", C_EC_CRIT},
+	{20, 1, "flm_csr_init_p1_axi_slverr", C_EC_CRIT},
+	{21, 1, "flm_csr_init_p2_axi_slverr", C_EC_CRIT},
+	{22, 1, "flm_serdes_rom_load_spi_err", C_EC_CRIT},
+	{23, 1, "flm_serdes_rom_load_error", C_EC_CRIT},
+	{24, 1, "flm_serdes_rom_load_abort", C_EC_CRIT},
+	{25, 1, "flm_serdes_rom_load_fail", C_EC_CRIT},
+	{26, 1, "flm_hg_spi_error", C_EC_CRIT},
+	{27, 1, "flm_hg_addr_error", C_EC_CRIT},
+	{28, 1, "flm_sbus_wr_error", C_EC_CRIT},
+	{29, 1, "flm_sbus_rd_error", C_EC_CRIT},
+	{64, 1}
+};
+
+static const struct flg_err_info mst_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "crnc_ring_sync_error", C_EC_UNCOR_NS},
+	{2, 1, "crnc_ring_ecc_sbe", C_EC_COR},
+	{3, 1, "crnc_ring_ecc_mbe", C_EC_UNCOR_NS},
+	{4, 1, "crnc_ring_cmd_unknown", C_EC_UNCOR_NS},
+	{5, 1, "crnc_csr_cmd_unknown", C_EC_UNCOR_NS},
+	{6, 1, "crnc_csr_cmd_incomplete", C_EC_UNCOR_NS},
+	{7, 1, "crnc_buf_ecc_sbe", C_EC_COR},
+	{8, 1, "crnc_buf_ecc_mbe", C_EC_UNCOR_NS},
+	{32, 1, "lnk_list_ptrs_cor", C_EC_COR,
+	 {{C_MST_ERR_INFO_MEM, C_MST_ERR_INFO_MEM_SIZE, "C_MST_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{33, 1, "lnk_list_ptrs_ucor", C_EC_CRIT,
+	 {{C_MST_ERR_INFO_MEM, C_MST_ERR_INFO_MEM_SIZE, "C_MST_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{36, 1, "req_fifo_unrun", C_EC_CRIT},
+	{37, 1, "req_fifo_ovrun", C_EC_CRIT},
+	{38, 1, "req_fifo_crdt_unflw", C_EC_CRIT},
+	{44, 1, "match_crdt_unflw_get", C_EC_CRIT},
+	{45, 1, "match_crdt_unflw_put", C_EC_CRIT},
+	{46, 1, "evnt_fifo_cor", C_EC_COR,
+	 {{C_MST_ERR_INFO_MEM, C_MST_ERR_INFO_MEM_SIZE, "C_MST_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{47, 1, "evnt_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C_MST_ERR_INFO_MEM, C_MST_ERR_INFO_MEM_SIZE, "C_MST_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{48, 1, "evnt_fifo_unrun", C_EC_CRIT},
+	{49, 1, "evnt_fifo_ovrun", C_EC_CRIT},
+	{50, 1, "ee_crdt_unflw", C_EC_CRIT},
+	{51, 1, "req_fifo_cor", C_EC_COR,
+	 {{C_MST_ERR_INFO_MEM, C_MST_ERR_INFO_MEM_SIZE, "C_MST_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{52, 1, "req_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C_MST_ERR_INFO_MEM, C_MST_ERR_INFO_MEM_SIZE, "C_MST_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{53, 1, "mst_table_cor", C_EC_COR,
+	 {{C_MST_ERR_INFO_MEM, C_MST_ERR_INFO_MEM_SIZE, "C_MST_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{54, 1, "mst_table_ucor", C_EC_UNCOR_NS,
+	 {{C_MST_ERR_INFO_MEM, C_MST_ERR_INFO_MEM_SIZE, "C_MST_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{55, 1, "ll_data_ram_cor", C_EC_COR,
+	 {{C_MST_ERR_INFO_MEM, C_MST_ERR_INFO_MEM_SIZE, "C_MST_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{56, 1, "ll_data_ram_ucor", C_EC_UNCOR_NS,
+	 {{C_MST_ERR_INFO_MEM, C_MST_ERR_INFO_MEM_SIZE, "C_MST_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{64, 1}
+};
+
+static const struct flg_err_info oxe_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "crnc_ring_sync_error", C_EC_UNCOR_NS},
+	{2, 1, "crnc_ring_ecc_sbe", C_EC_COR},
+	{3, 1, "crnc_ring_ecc_mbe", C_EC_UNCOR_NS},
+	{4, 1, "crnc_ring_cmd_unknown", C_EC_UNCOR_NS},
+	{5, 1, "crnc_csr_cmd_unknown", C_EC_UNCOR_NS},
+	{6, 1, "crnc_csr_cmd_incomplete", C_EC_UNCOR_NS},
+	{7, 1, "crnc_buf_ecc_sbe", C_EC_COR},
+	{8, 1, "crnc_buf_ecc_mbe", C_EC_UNCOR_NS},
+	{16, 1, "cells_mem_cor", C_EC_COR,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002698, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{17, 1, "pkl_mem_cor", C_EC_COR,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002698, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{18, 1, "pct_sb_mcu_mem_cor", C_EC_COR,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002698, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{19, 1, "pct_sb_sct_mem_cor", C_EC_COR,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002698, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{20, 1, "dmu_mem_cor", C_EC_COR,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002698, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{21, 1, "rec_mem_cor", C_EC_COR,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002698, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{22, 1, "atreq_mem_cor", C_EC_COR,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002698, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{23, 1, "atrsp_mem_cor", C_EC_COR,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002698, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{24, 1, "tso_flit_cor", C_EC_COR,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002698, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{25, 1, "sb_fifo_cor", C_EC_COR,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002698, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{26, 1, "rarb_hdr_cor", C_EC_COR,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002698, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{27, 1, "rarb_data_cor", C_EC_COR,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002698, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{28, 1, "at_resp_bus_cor", C_EC_COR,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002698, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{29, 1, "ixe_cmd_cor", C_EC_COR,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002698, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{30, 1, "lpe_cmd_cor", C_EC_COR,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002698, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{31, 1, "tou_cmd_cor", C_EC_COR,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002698, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{32, 1, "cq_cmd_cor", C_EC_COR,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002698, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{33, 1, "cells_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x10026A0, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{34, 1, "pkl_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x10026A0, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{35, 1, "pct_sb_mcu_mem_ucor", C_EC_CRIT,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x10026A0, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{36, 1, "pct_sb_sct_mem_ucor", C_EC_CRIT,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x10026A0, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{37, 1, "dmu_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x10026A0, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{38, 1, "rec_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x10026A0, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{39, 1, "atreq_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x10026A0, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{40, 1, "atrsp_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x10026A0, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{41, 1, "tso_flit_ucor", C_EC_UNCOR_NS,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x10026A0, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{42, 1, "sb_fifo_ucor", C_EC_CRIT,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x10026A0, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{43, 1, "rarb_hdr_ucor", C_EC_UNCOR_NS,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  {C_OXE_ERR_INFO_RARB, C_OXE_ERR_INFO_RARB_SIZE,
+	   "C_OXE_ERR_INFO_RARB"},
+	  },
+	 {{0x10026A0, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{44, 1, "rarb_data_ucor", C_EC_UNCOR_NS,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  {C_OXE_ERR_INFO_RARB, C_OXE_ERR_INFO_RARB_SIZE,
+	   "C_OXE_ERR_INFO_RARB"},
+	  },
+	 {{0x10026A0, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{45, 1, "at_resp_bus_ucor", C_EC_UNCOR_NS,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x10026A0, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{46, 1, "ixe_cmd_ucor", C_EC_CRIT,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x10026A0, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{47, 1, "lpe_cmd_ucor", C_EC_CRIT,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x10026A0, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{48, 1, "tou_cmd_ucor", C_EC_CRIT,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x10026A0, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{49, 1, "cq_cmd_ucor", C_EC_CRIT,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x10026A0, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{50, 1, "fifo_err", C_EC_UNCOR_NS,
+	 {{C_OXE_ERR_INFO_FIFO_ERR, C_OXE_ERR_INFO_FIFO_ERR_SIZE,
+	   "C_OXE_ERR_INFO_FIFO_ERR"},
+	  },
+	 {},
+	 },
+	{51, 1, "credit_uflw", C_EC_UNCOR_NS,
+	 {{C_OXE_ERR_INFO_CC, C_OXE_ERR_INFO_CC_SIZE, "C_OXE_ERR_INFO_CC"},
+	  },
+	 {},
+	 },
+	{52, 1, "spt_ignore_err", C_EC_BADCON_NS,
+	 {{C_OXE_ERR_INFO_IGNORE_ERR, C_OXE_ERR_INFO_IGNORE_ERR_SIZE,
+	   "C_OXE_ERR_INFO_IGNORE_ERR"},
+	  },
+	 {{0x1002970, "ignore_errs", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{53, 1, "smt_ignore_err", C_EC_BADCON_NS,
+	 {{C_OXE_ERR_INFO_IGNORE_ERR, C_OXE_ERR_INFO_IGNORE_ERR_SIZE,
+	   "C_OXE_ERR_INFO_IGNORE_ERR"},
+	  },
+	 {{0x1002970, "ignore_errs", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{54, 1, "sct_ignore_err", C_EC_BADCON_NS,
+	 {{C_OXE_ERR_INFO_IGNORE_ERR, C_OXE_ERR_INFO_IGNORE_ERR_SIZE,
+	   "C_OXE_ERR_INFO_IGNORE_ERR"},
+	  },
+	 {{0x1002970, "ignore_errs", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{55, 1, "srb_ignore_err", C_EC_BADCON_NS,
+	 {{C_OXE_ERR_INFO_IGNORE_ERR, C_OXE_ERR_INFO_IGNORE_ERR_SIZE,
+	   "C_OXE_ERR_INFO_IGNORE_ERR"},
+	  },
+	 {{0x1002970, "ignore_errs", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{56, 1, "cmd_unexpected", C_EC_UNCOR_NS,
+	 {{C_OXE_ERR_INFO_UNEXPCTD, C_OXE_ERR_INFO_UNEXPCTD_SIZE,
+	   "C_OXE_ERR_INFO_UNEXPCTD"},
+	  },
+	 {},
+	 },
+	{57, 1, "rarb_hw_err", C_EC_UNCOR_NS,
+	 {{C_OXE_ERR_INFO_RARB, C_OXE_ERR_INFO_RARB_SIZE,
+	   "C_OXE_ERR_INFO_RARB"},
+	  },
+	 {},
+	 },
+	{58, 1, "pcie_unsuccess_cmpl", C_EC_UNCOR_NS,
+	 {{C_OXE_ERR_INFO_PCIE_UC, C_OXE_ERR_INFO_PCIE_UC_SIZE,
+	   "C_OXE_ERR_INFO_PCIE_UC"},
+	  },
+	 {},
+	 },
+	{59, 1, "pcie_error_poisoned", C_EC_UNCOR_NS,
+	 {{C_OXE_ERR_INFO_PCIE_EP, C_OXE_ERR_INFO_PCIE_EP_SIZE,
+	   "C_OXE_ERR_INFO_PCIE_EP"},
+	  },
+	 {},
+	 },
+	{60, 1, "at_overrun_err", C_EC_UNCOR_NS},
+	{61, 1, "mdr_pipe_ucor", C_EC_UNCOR_NS,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x10026A0, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{62, 1, "cell_xlate_parity_err", C_EC_UNCOR_NS,
+	 {{C_OXE_ERR_INFO_CELL_XLATE, C_OXE_ERR_INFO_CELL_XLATE_SIZE,
+	   "C_OXE_ERR_INFO_CELL_XLATE"},
+	  },
+	 {},
+	 },
+	{64, 1}
+};
+
+static const struct flg_err_info parbs_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "crnc_ring_sync_error", C_EC_UNCOR_NS},
+	{2, 1, "crnc_ring_ecc_sbe", C_EC_COR},
+	{3, 1, "crnc_ring_ecc_mbe", C_EC_UNCOR_NS},
+	{4, 1, "crnc_ring_cmd_unknown", C_EC_UNCOR_NS},
+	{5, 1, "crnc_csr_cmd_unknown", C_EC_UNCOR_NS},
+	{6, 1, "crnc_csr_cmd_incomplete", C_EC_UNCOR_NS},
+	{7, 1, "crnc_buf_ecc_sbe", C_EC_COR},
+	{8, 1, "crnc_buf_ecc_mbe", C_EC_UNCOR_NS},
+	{16, 1, "cq_tarb_hdr_cor", C_EC_COR,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{17, 1, "cq_tarb_hdr_ucor", C_EC_UNCOR_NS,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{18, 1, "cq_tarb_data_cor", C_EC_COR,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{19, 1, "cq_tarb_data_ucor", C_EC_UNCOR_NS,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{20, 1, "ee_tarb_hdr_cor", C_EC_COR,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{21, 1, "ee_tarb_hdr_ucor", C_EC_UNCOR_NS,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{22, 1, "ee_tarb_data_cor", C_EC_COR,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{23, 1, "ee_tarb_data_ucor", C_EC_UNCOR_NS,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{24, 1, "ixe_tarb_hdr_cor", C_EC_COR,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{25, 1, "ixe_tarb_hdr_ucor", C_EC_UNCOR_NS,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{26, 1, "ixe_tarb_data_cor", C_EC_COR,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{27, 1, "ixe_tarb_data_ucor", C_EC_UNCOR_NS,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{28, 1, "oxe_tarb_hdr_cor", C_EC_COR,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{29, 1, "oxe_tarb_hdr_ucor", C_EC_UNCOR_NS,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{30, 1, "atu_tarb_hdr_cor", C_EC_COR,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{31, 1, "atu_tarb_hdr_ucor", C_EC_UNCOR_NS,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{32, 1, "atu_tarb_data_cor", C_EC_COR,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{33, 1, "atu_tarb_data_ucor", C_EC_UNCOR_NS,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{34, 1, "tarb_pi_hdr_cor", C_EC_COR,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{35, 1, "tarb_pi_hdr_ucor", C_EC_UNCOR_NS,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{36, 1, "tarb_pi_data_cor", C_EC_COR,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{37, 1, "tarb_pi_data_ucor", C_EC_UNCOR_NS,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{38, 1, "cq_p_fifo_overrun", C_EC_UNCOR_NS},
+	{39, 1, "cq_p_fifo_underrun", C_EC_UNCOR_NS},
+	{40, 1, "cq_np_fifo_overrun", C_EC_UNCOR_NS},
+	{41, 1, "cq_np_fifo_underrun", C_EC_UNCOR_NS},
+	{42, 1, "ee_p_fifo_overrun", C_EC_UNCOR_NS},
+	{43, 1, "ee_p_fifo_underrun", C_EC_UNCOR_NS},
+	{44, 1, "ixe_p_fifo_overrun", C_EC_UNCOR_NS},
+	{45, 1, "ixe_p_fifo_underrun", C_EC_UNCOR_NS},
+	{46, 1, "ixe_np_fifo_overrun", C_EC_UNCOR_NS},
+	{47, 1, "ixe_np_fifo_underrun", C_EC_UNCOR_NS},
+	{48, 1, "oxe_np_fifo_overrun", C_EC_UNCOR_NS},
+	{49, 1, "oxe_np_fifo_underrun", C_EC_UNCOR_NS},
+	{50, 1, "atu_p_fifo_overrun", C_EC_UNCOR_NS},
+	{51, 1, "atu_p_fifo_underrun", C_EC_UNCOR_NS},
+	{52, 1, "atu_np_fifo_overrun", C_EC_UNCOR_NS},
+	{53, 1, "atu_np_fifo_underrun", C_EC_UNCOR_NS},
+	{54, 1, "ord_p_fifo_overrun", C_EC_UNCOR_NS},
+	{55, 1, "ord_p_fifo_underrun", C_EC_UNCOR_NS},
+	{56, 1, "ord_np_fifo_overrun", C_EC_UNCOR_NS},
+	{57, 1, "ord_np_fifo_underrun", C_EC_UNCOR_NS},
+	{58, 1, "ord_np_cnt_overrun", C_EC_UNCOR_NS},
+	{59, 1, "ord_np_cnt_underrun", C_EC_UNCOR_NS},
+	{60, 1, "tarb_pi_p_cdt_underflow", C_EC_UNCOR_NS},
+	{61, 1, "tarb_pi_np_cdt_underflow", C_EC_UNCOR_NS},
+	{64, 1}
+};
+
+static const struct flg_err_info parbs_ext_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "pi_rarb_hdr_cor", C_EC_COR,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{2, 1, "pi_rarb_hdr_ucor", C_EC_UNCOR_NS,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{3, 1, "pi_rarb_data_cor", C_EC_COR,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{4, 1, "pi_rarb_data_ucor", C_EC_UNCOR_NS,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{64, 1}
+};
+
+static const struct flg_err_info pct_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "crnc_ring_sync_error", C_EC_UNCOR_NS},
+	{2, 1, "crnc_ring_ecc_sbe", C_EC_COR},
+	{3, 1, "crnc_ring_ecc_mbe", C_EC_UNCOR_NS},
+	{4, 1, "crnc_ring_cmd_unknown", C_EC_UNCOR_NS},
+	{5, 1, "crnc_csr_cmd_unknown", C_EC_UNCOR_NS},
+	{6, 1, "crnc_csr_cmd_incomplete", C_EC_UNCOR_NS},
+	{7, 1, "crnc_buf_ecc_sbe", C_EC_COR},
+	{8, 1, "crnc_buf_ecc_mbe", C_EC_UNCOR_NS},
+	{9, 1, "srb_alloc_dup", C_EC_UNCOR_NS},
+	{10, 1, "srb_dealloc_dup", C_EC_UNCOR_NS},
+	{12, 1, "flop_fifo_cor", C_EC_COR,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100600, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{13, 1, "mst_cam_free_cor", C_EC_COR,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100600, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{14, 1, "sct_cam_free_cor", C_EC_COR,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100600, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{15, 1, "tct_cam_free_cor", C_EC_COR,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100600, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{16, 1, "trs_cam_free_cor", C_EC_COR,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100600, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{17, 1, "sct_tbl_cor", C_EC_COR,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100600, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{18, 1, "smt_tbl_cor", C_EC_COR,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100600, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{19, 1, "spt_tbl_cor", C_EC_COR,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100600, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{20, 1, "tct_tbl_cor", C_EC_COR,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100600, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{21, 1, "trs_tbl_cor", C_EC_COR,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100600, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{22, 1, "req_redo_cor", C_EC_COR,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100600, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{23, 1, "cls_clr_req_gen_cor", C_EC_COR,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100600, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{24, 1, "srb_nlist_ram_cor", C_EC_COR,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100600, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{25, 1, "srb_data_ram_cor", C_EC_COR,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100600, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{26, 1, "flop_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100608, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{27, 1, "mst_cam_free_ucor", C_EC_UNCOR_NS,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100608, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{28, 1, "sct_cam_free_ucor", C_EC_UNCOR_NS,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100608, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{29, 1, "tct_cam_free_ucor", C_EC_UNCOR_NS,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100608, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{30, 1, "trs_cam_free_ucor", C_EC_UNCOR_NS,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100608, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{31, 1, "sct_tbl_ucor", C_EC_UNCOR_NS,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100608, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{32, 1, "smt_tbl_ucor", C_EC_UNCOR_NS,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100608, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{33, 1, "spt_tbl_ucor", C_EC_UNCOR_NS,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100608, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{34, 1, "tct_tbl_ucor", C_EC_UNCOR_NS,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100608, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{35, 1, "trs_tbl_ucor", C_EC_UNCOR_NS,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100608, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{36, 1, "req_redo_ucor", C_EC_UNCOR_NS,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100608, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{37, 1, "cls_clr_req_gen_ucor", C_EC_UNCOR_NS,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100608, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{38, 1, "srb_nlist_ram_ucor", C_EC_UNCOR_NS,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100608, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{39, 1, "srb_data_ram_ucor", C_EC_UNCOR_NS,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100608, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{40, 1, "mst_cam_ucor", C_EC_UNCOR_NS,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100608, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{41, 1, "sct_cam_ucor", C_EC_UNCOR_NS,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100608, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{42, 1, "tct_cam_ucor", C_EC_UNCOR_NS,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100608, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{43, 1, "trs_cam_ucor", C_EC_UNCOR_NS,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100608, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{44, 1, "fifo_err", C_EC_UNCOR_NS,
+	 {{C_PCT_ERR_INFO_FIFO, C_PCT_ERR_INFO_FIFO_SIZE,
+	   "C_PCT_ERR_INFO_FIFO"},
+	  },
+	 {},
+	 },
+	{45, 1, "credit_uflw", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_CC, C_PCT_ERR_INFO_CC_SIZE, "C_PCT_ERR_INFO_CC"},
+	  },
+	 {},
+	 },
+	{64, 1}
+};
+
+static const struct flg_err_info pct_ext_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "sct_tbl_dealloc", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{2, 1, "sct_tbl_alloc", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{3, 1, "sct_tbl_rd_misc_unused", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{4, 1, "sct_tbl_wr_misc_unused", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{5, 1, "sct_tbl_rd_ram_unused", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{6, 1, "sct_tbl_wr_ram_unused", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{7, 1, "smt_tbl_dealloc", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{8, 1, "smt_tbl_alloc", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{9, 1, "smt_tbl_rd_ram_unused", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{10, 1, "smt_tbl_wr_ram_unused", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{11, 1, "spt_tbl_dealloc", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{12, 1, "spt_tbl_alloc", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{13, 1, "spt_tbl_rd_misc_unused", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{14, 1, "spt_tbl_wr_misc_unused", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{15, 1, "spt_tbl_rd_ram_unused", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{16, 1, "spt_tbl_wr_ram_unused", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{17, 1, "spt_tbl_set_wrong_status", C_EC_CRIT},
+	{18, 1, "tct_tbl_dealloc", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{19, 1, "tct_tbl_alloc", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{20, 1, "tct_tbl_rd_misc_unused", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{21, 1, "tct_tbl_rd_ram_unused", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{22, 1, "tct_tbl_wr_ram_unused", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{23, 1, "trs_tbl_dealloc", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{24, 1, "trs_tbl_alloc", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{25, 1, "trs_tbl_rd_ram_unused", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{26, 1, "trs_tbl_wr_ram_unused", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{27, 1, "oxe_sct_miss_on_mid", C_EC_CRIT},
+	{28, 1, "oxe_failed_sct_alloc", C_EC_CRIT},
+	{29, 1, "oxe_illegal_req", C_EC_CRIT},
+	{30, 1, "oxe_new_conn_not_som", C_EC_CRIT},
+	{31, 1, "oxe_invalid_smt_not_som", C_EC_CRIT},
+	{32, 1, "oxe_illegal_access2_fsm", C_EC_CRIT},
+	{33, 1, "oxe_smt_req_cnt_exceed", C_EC_CRIT},
+	{34, 1, "oxe_sct_req_cnt_exceed", C_EC_CRIT},
+	{35, 1, "ixe_req_tct_not_in_use", C_EC_CRIT},
+	{36, 1, "ixe_req_tct_miss_unordered_mid", C_EC_CRIT},
+	{37, 1, "ixe_req_mst_missing", C_EC_CRIT},
+	{38, 1, "ixe_req_clr_out_of_range", C_EC_CRIT},
+	{39, 1, "ixe_rsp_spt_not_in_use", C_EC_CRIT},
+	{40, 1, "ixe_rsp_spt_status_not_pend", C_EC_CRIT},
+	{41, 1, "ixe_rsp_smt_pend_cnt_exceed", C_EC_CRIT},
+	{42, 1, "ixe_rsp_sct_pend_cnt_exceed", C_EC_CRIT},
+	{43, 1, "ixe_rsp_smt_invalid", C_EC_CRIT},
+	{44, 1, "ixe_rsp_spt_not_get_vld", C_EC_CRIT},
+	{45, 1, "ixe_rsp_cls_not_pend", C_EC_CRIT},
+	{46, 1, "ixe_gcomp_spt_not_in_use", C_EC_CRIT},
+	{47, 1, "ixe_gcomp_not_get_ack_rcvd", C_EC_CRIT},
+	{48, 1, "ixe_gcomp_smt_pend_cnt_exceed", C_EC_CRIT},
+	{49, 1, "ixe_gcomp_sct_pend_cnt_exceed", C_EC_CRIT},
+	{50, 1, "ixe_gcomp_smt_invalid", C_EC_CRIT},
+	{51, 1, "ixe_gcomp_spt_not_get_vld", C_EC_CRIT},
+	{52, 1, "src_cls_spt_wrong_sct", C_EC_CRIT},
+	{53, 1, "src_cls_spt_not_used", C_EC_CRIT},
+	{54, 1, "src_cls_spt_not_opcomp", C_EC_CRIT},
+	{55, 1, "src_cls_bad_close", C_EC_CRIT},
+	{56, 1, "pkto_illegal_req", C_EC_CRIT},
+	{57, 1, "pkto_illegal_pkttype", C_EC_CRIT},
+	{58, 1, "pkto_head_fsm", C_EC_CRIT},
+	{59, 1, "srb_wr_rd_same_cycle", C_EC_CRIT},
+	{60, 1, "sct_miss_unrestricted_mid", C_EC_CRIT},
+	{61, 1, "mbe_in_ctrls", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{62, 1, "sct_cam_err", C_EC_CRIT},
+	{63, 1, "mst_cam_err", C_EC_CRIT},
+	{64, 1}
+};
+
+static const struct flg_err_info pi_ipd_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "crnc_ring_sync_error", C_EC_UNCOR_NS},
+	{2, 1, "crnc_ring_ecc_sbe", C_EC_COR},
+	{3, 1, "crnc_ring_ecc_mbe", C_EC_UNCOR_NS},
+	{4, 1, "crnc_ring_cmd_unknown", C_EC_UNCOR_NS},
+	{5, 1, "crnc_csr_cmd_unknown", C_EC_UNCOR_NS},
+	{6, 1, "crnc_csr_cmd_incomplete", C_EC_UNCOR_NS},
+	{7, 1, "crnc_buf_ecc_sbe", C_EC_COR},
+	{8, 1, "crnc_buf_ecc_mbe", C_EC_UNCOR_NS},
+	{16, 1, "event_cnt_ovf", C_EC_INFO},
+	{17, 1, "event_ram_cor", C_EC_COR,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{18, 1, "event_ram_ucor", C_EC_UNCOR_NS,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{19, 1, "msix_table_cor", C_EC_COR,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{20, 1, "msix_table_ucor", C_EC_UNCOR_NS,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{21, 1, "msix_pba_cor", C_EC_COR,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{22, 1, "msix_pba_ucor", C_EC_UNCOR_NS,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{23, 4, "pti_tarb_xlat_p_fifo_cor", C_EC_COR,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{27, 4, "pti_tarb_xlat_p_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{31, 3, "pti_tarb_xlat_np_fifo_cor", C_EC_COR,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{34, 3, "pti_tarb_xlat_np_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{37, 1, "pti_tarb_xlat_tbuf_cor", C_EC_COR,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{38, 1, "pti_tarb_xlat_tbuf_ucor", C_EC_UNCOR_NS,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{39, 1, "pti_tarb_xlat_cpl_to_fifo_cor", C_EC_COR,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{40, 1, "pti_tarb_xlat_cpl_to_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{41, 4, "pri_mb_xlat_comp_fifo_cor", C_EC_COR,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{45, 4, "pri_mb_xlat_comp_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{49, 1, "pti_msixc_fifo_cor", C_EC_COR,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{50, 1, "pti_msixc_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{51, 1, "msixc_pti_fifo_cor", C_EC_COR,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{52, 1, "msixc_pti_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{53, 4, "dmac_p_fifo_cor", C_EC_COR,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{57, 4, "dmac_p_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{64, 1}
+};
+
+static const struct flg_err_info pi_ipd_ext_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 3, "ip_app_parity_errs", C_EC_CRIT},
+	{4, 1, "ip_radm_qoverflow", C_EC_CRIT},
+	{5, 1, "ip_radm_msg_unlock", C_EC_INFO},
+	{6, 1, "ip_radm_pm_turnoff", C_EC_INFO},
+	{7, 1, "ip_wake", C_EC_INFO},
+	{8, 1, "ip_cfg_uncor_internal_err_sts", C_EC_UNCOR_NS},
+	{9, 1, "ip_cfg_corrected_internal_err_sts", C_EC_COR},
+	{10, 1, "ip_cfg_rcvr_overflow_err_sts", C_EC_CRIT},
+	{11, 1, "ip_cfg_fc_protocol_err_sts", C_EC_CRIT},
+	{12, 1, "ip_cfg_mlf_tlp_err_sts", C_EC_INFO},
+	{13, 1, "ip_cfg_surprise_down_er_sts", C_EC_INFO},
+	{14, 1, "ip_cfg_dl_protocol_err_sts", C_EC_CRIT},
+	{15, 1, "ip_cfg_ecrc_err_sts", C_EC_CRIT},
+	{16, 1, "ip_cfg_replay_number_rollover_err_sts", C_EC_INFO},
+	{17, 1, "ip_cfg_replay_timer_timeout_err_sts", C_EC_CRIT},
+	{18, 1, "ip_cfg_bad_dllp_err_sts", C_EC_CRIT},
+	{19, 1, "ip_cfg_bad_tlp_err_sts", C_EC_CRIT},
+	{20, 1, "ip_cfg_rcvr_err_sts", C_EC_CRIT},
+	{26, 1, "pti_tarb_xlat_xali_ph_crd_warn", C_EC_INFO},
+	{27, 1, "pti_tarb_xlat_xali_pd_crd_warn", C_EC_INFO},
+	{28, 1, "pti_tarb_xlat_xali_nph_crd_warn", C_EC_INFO},
+	{29, 1, "pti_tarb_xlat_xali_npd_crd_warn", C_EC_INFO},
+	{30, 1, "pti_tarb_xlat_ten_bit_tag_msb_error", C_EC_CRIT},
+	{31, 1, "pti_tarb_xlat_p_fifo_underrun", C_EC_CRIT},
+	{32, 1, "pti_tarb_xlat_np_fifo_underrun", C_EC_CRIT},
+	{33, 1, "pti_tarb_xlat_ord_fifo_underrun", C_EC_CRIT},
+	{34, 1, "pti_tarb_xlat_cpl_to_fifo_overrun", C_EC_CRIT},
+	{35, 1, "pti_tarb_xlat_cpl_to_fifo_underrun", C_EC_CRIT},
+	{36, 1, "pti_tarb_xlat_pti_pri_cpl_to_fifo_overrun", C_EC_CRIT},
+	{37, 1, "pti_tarb_xlat_ord_np_cnt_overrun", C_EC_CRIT},
+	{38, 1, "pti_tarb_xlat_ord_np_cnt_underrun", C_EC_CRIT},
+	{39, 1, "pri_rtrgt_hdr_parity_error", C_EC_CRIT},
+	{40, 1, "pri_rtrgt_data_parity_error", C_EC_CRIT},
+	{41, 1, "pri_rtrgt_abort", C_EC_CRIT},
+	{42, 1, "pri_rbyp_hdr_parity_error", C_EC_CRIT},
+	{43, 1, "pri_rbyp_data_parity_error", C_EC_CRIT},
+	{44, 1, "pri_rbyp_abort", C_EC_CRIT},
+	{45, 1, "pri_rarb_xlat_rtrgt_fifo_overrun", C_EC_CRIT},
+	{46, 1, "pri_rarb_xlat_rtrgt_rdy_fifo_overrun", C_EC_CRIT},
+	{47, 1, "pri_rarb_xlat_rbyp_fifo_overrun", C_EC_CRIT},
+	{48, 1, "pri_rarb_xlat_rbyp_rdy_fifo_overrun", C_EC_CRIT},
+	{49, 1, "pri_mb_xlat_rtrgt_fifo_overrun", C_EC_CRIT},
+	{50, 1, "pri_mb_xlat_rtrgt_rdy_fifo_overrun", C_EC_CRIT},
+	{51, 1, "pri_mb_xlat_comp_fifo_underrun", C_EC_CRIT},
+	{52, 1, "msixc_pti_fifo_overrun", C_EC_CRIT},
+	{53, 1, "msixc_pti_fifo_underrun", C_EC_CRIT},
+	{54, 1, "pti_msixc_fifo_overrun", C_EC_CRIT},
+	{55, 1, "pti_msixc_fifo_underrun", C_EC_CRIT},
+	{56, 1, "msix_disabled_error", C_EC_INFO},
+	{57, 1, "msix_hg_vf_size_error", C_EC_INFO},
+	{58, 1, "msix_pti_idx_error", C_EC_INFO},
+	{59, 1, "dmac_bme_error", C_EC_INFO},
+	{64, 1}
+};
+
+static const struct flg_err_info pi_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "crnc_ring_sync_error", C_EC_UNCOR_NS},
+	{2, 1, "crnc_ring_ecc_sbe", C_EC_COR},
+	{3, 1, "crnc_ring_ecc_mbe", C_EC_UNCOR_NS},
+	{4, 1, "crnc_ring_cmd_unknown", C_EC_UNCOR_NS},
+	{5, 1, "crnc_csr_cmd_unknown", C_EC_UNCOR_NS},
+	{6, 1, "crnc_csr_cmd_incomplete", C_EC_UNCOR_NS},
+	{7, 1, "crnc_buf_ecc_sbe", C_EC_COR},
+	{8, 1, "crnc_buf_ecc_mbe", C_EC_UNCOR_NS},
+	{16, 1, "acxt_cor", C_EC_COR,
+	 {{C_PI_ERR_INFO_MEM, C_PI_ERR_INFO_MEM_SIZE, "C_PI_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{17, 1, "acxt_ucor", C_EC_UNCOR_NS,
+	 {{C_PI_ERR_INFO_MEM, C_PI_ERR_INFO_MEM_SIZE, "C_PI_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{18, 1, "sriovt_cor", C_EC_COR,
+	 {{C_PI_ERR_INFO_MEM, C_PI_ERR_INFO_MEM_SIZE, "C_PI_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{19, 1, "sriovt_ucor", C_EC_UNCOR_NS,
+	 {{C_PI_ERR_INFO_MEM, C_PI_ERR_INFO_MEM_SIZE, "C_PI_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{20, 1, "dmac_desc_cor", C_EC_COR,
+	 {{C_PI_ERR_INFO_MEM, C_PI_ERR_INFO_MEM_SIZE, "C_PI_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{21, 1, "dmac_desc_ucor", C_EC_UNCOR_NS,
+	 {{C_PI_ERR_INFO_MEM, C_PI_ERR_INFO_MEM_SIZE, "C_PI_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{22, 4, "pri_mb_xlat_rtrgt_fifo_cor", C_EC_COR,
+	 {{C_PI_ERR_INFO_MEM, C_PI_ERR_INFO_MEM_SIZE, "C_PI_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{26, 4, "pri_mb_xlat_rtrgt_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C_PI_ERR_INFO_MEM, C_PI_ERR_INFO_MEM_SIZE, "C_PI_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{30, 4, "pri_rarb_xlat_rtrgt_fifo_cor", C_EC_COR,
+	 {{C_PI_ERR_INFO_MEM, C_PI_ERR_INFO_MEM_SIZE, "C_PI_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{34, 4, "pri_rarb_xlat_rtrgt_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C_PI_ERR_INFO_MEM, C_PI_ERR_INFO_MEM_SIZE, "C_PI_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{38, 4, "pri_rarb_xlat_rbyp_fifo_cor", C_EC_COR,
+	 {{C_PI_ERR_INFO_MEM, C_PI_ERR_INFO_MEM_SIZE, "C_PI_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{42, 4, "pri_rarb_xlat_rbyp_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C_PI_ERR_INFO_MEM, C_PI_ERR_INFO_MEM_SIZE, "C_PI_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{46, 1, "pti_tarb_xlat_pipe0_hdr_cor", C_EC_COR,
+	 {{C_PI_ERR_INFO_MEM, C_PI_ERR_INFO_MEM_SIZE, "C_PI_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{47, 1, "pti_tarb_xlat_pipe0_hdr_ucor", C_EC_UNCOR_NS,
+	 {{C_PI_ERR_INFO_MEM, C_PI_ERR_INFO_MEM_SIZE, "C_PI_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{48, 1, "pti_tarb_xlat_pipe3_hdr_cor", C_EC_COR,
+	 {{C_PI_ERR_INFO_MEM, C_PI_ERR_INFO_MEM_SIZE, "C_PI_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{49, 1, "pti_tarb_xlat_pipe3_hdr_ucor", C_EC_UNCOR_NS,
+	 {{C_PI_ERR_INFO_MEM, C_PI_ERR_INFO_MEM_SIZE, "C_PI_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{50, 1, "pti_tarb_xlat_pipe3_data_cor", C_EC_COR,
+	 {{C_PI_ERR_INFO_MEM, C_PI_ERR_INFO_MEM_SIZE, "C_PI_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{51, 1, "pti_tarb_xlat_pipe3_data_ucor", C_EC_UNCOR_NS,
+	 {{C_PI_ERR_INFO_MEM, C_PI_ERR_INFO_MEM_SIZE, "C_PI_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{52, 1, "pti_tarb_xlat_unexpected_dv", C_EC_CRIT,
+	 {{C_PI_ERR_INFO_TARB, C_PI_ERR_INFO_TARB_SIZE, "C_PI_ERR_INFO_TARB"},
+	  },
+	 {},
+	 },
+	{53, 1, "pti_tarb_xlat_ac_en_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_TARB, C_PI_ERR_INFO_TARB_SIZE, "C_PI_ERR_INFO_TARB"},
+	  },
+	 {},
+	 },
+	{54, 1, "pti_tarb_xlat_cfg_vf_en_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_TARB, C_PI_ERR_INFO_TARB_SIZE, "C_PI_ERR_INFO_TARB"},
+	  },
+	 {},
+	 },
+	{55, 1, "pti_tarb_xlat_cfg_vf_num_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_TARB, C_PI_ERR_INFO_TARB_SIZE, "C_PI_ERR_INFO_TARB"},
+	  },
+	 {},
+	 },
+	{56, 1, "pti_tarb_xlat_cfg_vf_bme_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_TARB, C_PI_ERR_INFO_TARB_SIZE, "C_PI_ERR_INFO_TARB"},
+	  },
+	 {},
+	 },
+	{57, 1, "pti_tarb_xlat_cfg_bme_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_TARB, C_PI_ERR_INFO_TARB_SIZE, "C_PI_ERR_INFO_TARB"},
+	  },
+	 {},
+	 },
+	{58, 1, "pti_tarb_xlat_cfg_amo_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_TARB, C_PI_ERR_INFO_TARB_SIZE, "C_PI_ERR_INFO_TARB"},
+	  },
+	 {},
+	 },
+	{62, 2, "uc_attention", C_EC_SFTWR},
+	{64, 1}
+};
+
+static const struct flg_err_info pi_ext_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "pri_mb_xlat_rtrgt_abort_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{2, 1, "pri_mb_xlat_rtrgt_hdr_parity_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{3, 1, "pri_mb_xlat_rtrgt_data_parity_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{4, 1, "pri_mb_xlat_axi_wr_decerr", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{5, 1, "pri_mb_xlat_axi_wr_slverr", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{6, 1, "pri_mb_xlat_axi_rd_decerr", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{7, 1, "pri_mb_xlat_axi_rd_slverr", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{8, 1, "pri_mb_xlat_axi_rd_parity_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{9, 1, "pri_mb_xlat_msg_tlp_discard", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{10, 1, "pri_mb_xlat_unexpected_np_tlp", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{11, 1, "pri_mb_xlat_unexpected_tlp", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{12, 1, "pri_mb_xlat_pf_addr_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{13, 1, "pri_mb_xlat_vf_addr_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{14, 1, "pri_mb_xlat_rom_wr_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{15, 1, "pri_mb_xlat_partial_discard", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{16, 1, "pri_mb_xlat_rtrgt_fifo_underrun", C_EC_CRIT,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{17, 1, "pri_mb_xlat_rtrgt_rdy_fifo_underrun", C_EC_CRIT,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{18, 1, "pri_mb_xlat_comp_fifo_overrun", C_EC_CRIT,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{19, 1, "pri_mb_xlat_comp_ca", C_EC_CRIT,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{20, 1, "pri_mb_xlat_comp_ur", C_EC_CRIT,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{21, 1, "pri_rarb_xlat_rtrgt_abort_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{22, 1, "pri_rarb_xlat_rtrgt_hdr_parity_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{23, 1, "pri_rarb_xlat_rtrgt_data_parity_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{24, 1, "pri_rarb_xlat_rtrgt_unexpected_tlp", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{25, 1, "pri_rarb_xlat_rtrgt_unexpected_msg", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{26, 1, "pri_rarb_xlat_rtrgt_vf_addr_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{27, 1, "pri_rarb_xlat_rtrgt_vf_en_num_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{28, 1, "pri_rarb_xlat_rtrgt_vf_en_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{29, 1, "pri_rarb_xlat_rtrgt_inv_req_vf_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{30, 1, "pri_rarb_xlat_rtrgt_inv_req_dev_id_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{31, 1, "pri_rarb_xlat_rtrgt_prgr_vf_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{32, 1, "pri_rarb_xlat_rtrgt_prgr_dev_id_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{33, 1, "pri_rarb_xlat_rtrgt_fifo_underrun", C_EC_CRIT,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{34, 1, "pri_rarb_xlat_rtrgt_rdy_fifo_underrun", C_EC_CRIT,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{35, 1, "pri_rarb_xlat_rbyp_abort_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RBYP, C_PI_ERR_INFO_RBYP_SIZE, "C_PI_ERR_INFO_RBYP"},
+	  },
+	 {},
+	 },
+	{36, 1, "pri_rarb_xlat_rbyp_hdr_parity_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RBYP, C_PI_ERR_INFO_RBYP_SIZE, "C_PI_ERR_INFO_RBYP"},
+	  },
+	 {},
+	 },
+	{37, 1, "pri_rarb_xlat_rbyp_data_parity_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RBYP, C_PI_ERR_INFO_RBYP_SIZE, "C_PI_ERR_INFO_RBYP"},
+	  },
+	 {},
+	 },
+	{38, 1, "pri_rarb_xlat_rbyp_tag_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RBYP, C_PI_ERR_INFO_RBYP_SIZE, "C_PI_ERR_INFO_RBYP"},
+	  },
+	 {},
+	 },
+	{39, 1, "pri_rarb_xlat_rbyp_unexpected_tlp_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RBYP, C_PI_ERR_INFO_RBYP_SIZE, "C_PI_ERR_INFO_RBYP"},
+	  },
+	 {},
+	 },
+	{40, 1, "pri_rarb_xlat_rbyp_fifo_underrun", C_EC_CRIT,
+	 {{C_PI_ERR_INFO_RBYP, C_PI_ERR_INFO_RBYP_SIZE, "C_PI_ERR_INFO_RBYP"},
+	  },
+	 {},
+	 },
+	{41, 1, "pri_rarb_xlat_rbyp_rdy_fifo_underrun", C_EC_CRIT,
+	 {{C_PI_ERR_INFO_RBYP, C_PI_ERR_INFO_RBYP_SIZE, "C_PI_ERR_INFO_RBYP"},
+	  },
+	 {},
+	 },
+	{42, 1, "pti_tarb_xlat_p_fifo_overrun", C_EC_CRIT,
+	 {{C_PI_ERR_INFO_TARB, C_PI_ERR_INFO_TARB_SIZE, "C_PI_ERR_INFO_TARB"},
+	  },
+	 {},
+	 },
+	{43, 1, "pti_tarb_xlat_np_fifo_overrun", C_EC_CRIT,
+	 {{C_PI_ERR_INFO_TARB, C_PI_ERR_INFO_TARB_SIZE, "C_PI_ERR_INFO_TARB"},
+	  },
+	 {},
+	 },
+	{44, 1, "pti_tarb_xlat_ord_fifo_overrun", C_EC_CRIT,
+	 {{C_PI_ERR_INFO_TARB, C_PI_ERR_INFO_TARB_SIZE, "C_PI_ERR_INFO_TARB"},
+	  },
+	 {},
+	 },
+	{45, 1, "pti_tarb_xlat_np_err_fifo_overrun", C_EC_CRIT,
+	 {{C_PI_ERR_INFO_TARB, C_PI_ERR_INFO_TARB_SIZE, "C_PI_ERR_INFO_TARB"},
+	  },
+	 {},
+	 },
+	{46, 1, "pti_tarb_xlat_np_err_fifo_underrun", C_EC_CRIT},
+	{47, 1, "pti_tarb_xlat_pti_pri_cpl_to_fifo_underrun", C_EC_CRIT},
+	{48, 1, "dmac_axi_rd_decerr", C_EC_INFO,
+	 {{C_PI_ERR_INFO_DMAC, C_PI_ERR_INFO_DMAC_SIZE, "C_PI_ERR_INFO_DMAC"},
+	  },
+	 {},
+	 },
+	{49, 1, "dmac_axi_rd_slverr", C_EC_INFO,
+	 {{C_PI_ERR_INFO_DMAC, C_PI_ERR_INFO_DMAC_SIZE, "C_PI_ERR_INFO_DMAC"},
+	  },
+	 {},
+	 },
+	{50, 1, "dmac_axi_rd_parity_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_DMAC, C_PI_ERR_INFO_DMAC_SIZE, "C_PI_ERR_INFO_DMAC"},
+	  },
+	 {},
+	 },
+	{64, 1}
+};
+
+static const struct flg_err_info hni_pml_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "crnc_ring_sync_error", C_EC_UNCOR_NS},
+	{2, 1, "crnc_ring_ecc_sbe", C_EC_COR},
+	{3, 1, "crnc_ring_ecc_mbe", C_EC_UNCOR_NS},
+	{4, 1, "crnc_ring_cmd_unknown", C_EC_UNCOR_NS},
+	{5, 1, "crnc_csr_cmd_unknown", C_EC_UNCOR_NS},
+	{6, 1, "crnc_csr_cmd_incomplete", C_EC_UNCOR_NS},
+	{7, 1, "crnc_buf_ecc_sbe", C_EC_COR},
+	{8, 1, "crnc_buf_ecc_mbe", C_EC_UNCOR_NS},
+	{31, 1, "mac_rx_frame_err", C_EC_TRNSNT_NS,
+	 {{C1_HNI_PML_ERR_INFO_MAC_RX_DP, C1_HNI_PML_ERR_INFO_MAC_RX_DP_SIZE,
+	   "C1_HNI_PML_ERR_INFO_MAC_RX_DP"},
+	  },
+	 {},
+	 },
+	{32, 1, "autoneg_page_received", C_EC_TRNSNT_NS},
+	{33, 1, "autoneg_complete", C_EC_TRNSNT_NS},
+	{34, 1, "autoneg_failed", C_EC_TRNSNT_NS},
+	{35, 1, "pcs_tx_dp_err", C_EC_TRNSNT_NS,
+	 {{C1_HNI_PML_ERR_INFO_PCS_TX_DP, C1_HNI_PML_ERR_INFO_PCS_TX_DP_SIZE,
+	   "C1_HNI_PML_ERR_INFO_PCS_TX_DP"},
+	  },
+	 {},
+	 },
+	{36, 1, "pcs_rx_dp_err", C_EC_TRNSNT_NS,
+	 {{C1_HNI_PML_ERR_INFO_PCS_RX_DP, C1_HNI_PML_ERR_INFO_PCS_RX_DP_SIZE,
+	   "C1_HNI_PML_ERR_INFO_PCS_RX_DP"},
+	  },
+	 {},
+	 },
+	{37, 1, "pcs_rx_deskew_overflow", C_EC_TRNSNT_NS},
+	{38, 1, "pcs_rx_deskew_pe", C_EC_TRNSNT_NS,
+	 {{C1_HNI_PML_ERR_INFO_PCS_RX_DESKEW_PES,
+	   C1_HNI_PML_ERR_INFO_PCS_RX_DESKEW_PES_SIZE,
+	   "C1_HNI_PML_ERR_INFO_PCS_RX_DESKEW_PES"},
+	  },
+	 {},
+	 },
+	{39, 1, "pcs_fec_mem0_sbe", C_EC_COR,
+	 {{C1_HNI_PML_ERR_INFO_MEM, C1_HNI_PML_ERR_INFO_MEM_SIZE,
+	   "C1_HNI_PML_ERR_INFO_MEM"},
+	  },
+	 {{0x1002508, "pml_sbe_error_cnt", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{40, 1, "pcs_fec_mem0_mbe", C_EC_UNCOR_NS,
+	 {{C1_HNI_PML_ERR_INFO_MEM, C1_HNI_PML_ERR_INFO_MEM_SIZE,
+	   "C1_HNI_PML_ERR_INFO_MEM"},
+	  },
+	 {{0x1002500, "pml_mbe_error_cnt", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{41, 1, "pcs_fec_mem1_sbe", C_EC_COR,
+	 {{C1_HNI_PML_ERR_INFO_MEM, C1_HNI_PML_ERR_INFO_MEM_SIZE,
+	   "C1_HNI_PML_ERR_INFO_MEM"},
+	  },
+	 {{0x1002508, "pml_sbe_error_cnt", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{42, 1, "pcs_fec_mem1_mbe", C_EC_UNCOR_NS,
+	 {{C1_HNI_PML_ERR_INFO_MEM, C1_HNI_PML_ERR_INFO_MEM_SIZE,
+	   "C1_HNI_PML_ERR_INFO_MEM"},
+	  },
+	 {{0x1002500, "pml_mbe_error_cnt", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{43, 1, "pcs_tx_degrade", C_EC_TRNSNT_NS},
+	{44, 1, "pcs_rx_degrade", C_EC_TRNSNT_NS},
+	{45, 1, "pcs_rx_degrade_failure", C_EC_TRNSNT_NS},
+	{46, 1, "pcs_tx_degrade_failure", C_EC_TRNSNT_NS},
+	{47, 1, "pcs_hi_ser", C_EC_TRNSNT_NS},
+	{48, 1, "pcs_link_down", C_EC_TRNSNT_NS},
+	{49, 1, "mac_tx_dp_err", C_EC_UNCOR_NS,
+	 {{C1_HNI_PML_ERR_INFO_MAC_TX_DP, C1_HNI_PML_ERR_INFO_MAC_TX_DP_SIZE,
+	   "C1_HNI_PML_ERR_INFO_MAC_TX_DP"},
+	  },
+	 {},
+	 },
+	{50, 1, "mac_rx_dp_err", C_EC_TRNSNT_NS,
+	 {{C1_HNI_PML_ERR_INFO_MAC_RX_DP, C1_HNI_PML_ERR_INFO_MAC_RX_DP_SIZE,
+	   "C1_HNI_PML_ERR_INFO_MAC_RX_DP"},
+	  },
+	 {},
+	 },
+	{51, 1, "llr_tx_dp_sbe", C_EC_COR,
+	 {{C1_HNI_PML_ERR_INFO_LLR_TX_DP, C1_HNI_PML_ERR_INFO_LLR_TX_DP_SIZE,
+	   "C1_HNI_PML_ERR_INFO_LLR_TX_DP"},
+	  },
+	 {},
+	 },
+	{52, 1, "llr_tx_dp_mbe", C_EC_UNCOR_NS,
+	 {{C1_HNI_PML_ERR_INFO_LLR_TX_DP, C1_HNI_PML_ERR_INFO_LLR_TX_DP_SIZE,
+	   "C1_HNI_PML_ERR_INFO_LLR_TX_DP"},
+	  },
+	 {},
+	 },
+	{53, 1, "llr_tx_dp_err", C_EC_UNCOR_NS,
+	 {{C1_HNI_PML_ERR_INFO_LLR_TX_DP, C1_HNI_PML_ERR_INFO_LLR_TX_DP_SIZE,
+	   "C1_HNI_PML_ERR_INFO_LLR_TX_DP"},
+	  },
+	 {},
+	 },
+	{54, 1, "llr_seq_mem_sbe", C_EC_COR,
+	 {{C1_HNI_PML_ERR_INFO_MEM, C1_HNI_PML_ERR_INFO_MEM_SIZE,
+	   "C1_HNI_PML_ERR_INFO_MEM"},
+	  },
+	 {{0x1002508, "pml_sbe_error_cnt", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{55, 1, "llr_seq_mem_mbe", C_EC_UNCOR_NS,
+	 {{C1_HNI_PML_ERR_INFO_MEM, C1_HNI_PML_ERR_INFO_MEM_SIZE,
+	   "C1_HNI_PML_ERR_INFO_MEM"},
+	  },
+	 {{0x1002500, "pml_mbe_error_cnt", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{56, 1, "llr_replay_mem_sbe", C_EC_COR,
+	 {{C1_HNI_PML_ERR_INFO_MEM, C1_HNI_PML_ERR_INFO_MEM_SIZE,
+	   "C1_HNI_PML_ERR_INFO_MEM"},
+	  },
+	 {{0x1002508, "pml_sbe_error_cnt", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{57, 1, "llr_replay_mem_mbe", C_EC_UNCOR_NS,
+	 {{C1_HNI_PML_ERR_INFO_MEM, C1_HNI_PML_ERR_INFO_MEM_SIZE,
+	   "C1_HNI_PML_ERR_INFO_MEM"},
+	  },
+	 {{0x1002500, "pml_mbe_error_cnt", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{58, 1, "llr_ack_nack_error", C_EC_TRNSNT_NS},
+	{59, 1, "llr_ack_nack_seq_err", C_EC_TRNSNT_NS},
+	{60, 1, "llr_replay_at_max", C_EC_TRNSNT_NS},
+	{61, 1, "pcs_lanes_locked", C_EC_INFO},
+	{62, 1, "pcs_aligned", C_EC_INFO},
+	{63, 1, "pcs_ready", C_EC_INFO},
+	{64, 1}
+};
+
+static const struct flg_err_info rmu_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "crnc_ring_sync_error", C_EC_UNCOR_NS},
+	{2, 1, "crnc_ring_ecc_sbe", C_EC_COR},
+	{3, 1, "crnc_ring_ecc_mbe", C_EC_UNCOR_NS},
+	{4, 1, "crnc_ring_cmd_unknown", C_EC_UNCOR_NS},
+	{5, 1, "crnc_csr_cmd_unknown", C_EC_UNCOR_NS},
+	{6, 1, "crnc_csr_cmd_incomplete", C_EC_UNCOR_NS},
+	{7, 1, "crnc_buf_ecc_sbe", C_EC_COR},
+	{8, 1, "crnc_buf_ecc_mbe", C_EC_UNCOR_NS},
+	{32, 1, "ptl_idx_mem_cor", C_EC_COR,
+	 {{C_RMU_ERR_INFO_MEM, C_RMU_ERR_INFO_MEM_SIZE, "C_RMU_ERR_INFO_MEM"},
+	  },
+	 {{0x9870A50, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{33, 1, "ptlte_set_ctrl_mem_cor", C_EC_COR,
+	 {{C_RMU_ERR_INFO_MEM, C_RMU_ERR_INFO_MEM_SIZE, "C_RMU_ERR_INFO_MEM"},
+	  },
+	 {{0x9870A50, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{34, 1, "ptl_idx_indir_mem_cor", C_EC_COR,
+	 {{C_RMU_ERR_INFO_MEM, C_RMU_ERR_INFO_MEM_SIZE, "C_RMU_ERR_INFO_MEM"},
+	  },
+	 {{0x9870A50, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{36, 1, "vni_list_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_RMU_ERR_INFO_MEM, C_RMU_ERR_INFO_MEM_SIZE, "C_RMU_ERR_INFO_MEM"},
+	  },
+	 {{0x9870A58, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{37, 1, "vni_list_vld_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_RMU_ERR_INFO_MEM, C_RMU_ERR_INFO_MEM_SIZE, "C_RMU_ERR_INFO_MEM"},
+	  },
+	 {{0x9870A58, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{38, 1, "ptl_list_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_RMU_ERR_INFO_MEM, C_RMU_ERR_INFO_MEM_SIZE, "C_RMU_ERR_INFO_MEM"},
+	  },
+	 {{0x9870A58, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{39, 1, "ptl_list_vld_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_RMU_ERR_INFO_MEM, C_RMU_ERR_INFO_MEM_SIZE, "C_RMU_ERR_INFO_MEM"},
+	  },
+	 {{0x9870A58, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{40, 1, "ptl_idx_mem_ucor", C_EC_UNCOR_S,
+	 {{C_RMU_ERR_INFO_MEM, C_RMU_ERR_INFO_MEM_SIZE, "C_RMU_ERR_INFO_MEM"},
+	  },
+	 {{0x9870A58, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{41, 1, "ptlte_set_list_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_RMU_ERR_INFO_MEM, C_RMU_ERR_INFO_MEM_SIZE, "C_RMU_ERR_INFO_MEM"},
+	  },
+	 {{0x9870A58, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{42, 1, "ptlte_set_list_vld_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_RMU_ERR_INFO_MEM, C_RMU_ERR_INFO_MEM_SIZE, "C_RMU_ERR_INFO_MEM"},
+	  },
+	 {{0x9870A58, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{43, 1, "ptlte_set_ctrl_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_RMU_ERR_INFO_MEM, C_RMU_ERR_INFO_MEM_SIZE, "C_RMU_ERR_INFO_MEM"},
+	  },
+	 {{0x9870A58, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{44, 1, "ptl_idx_indir_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_RMU_ERR_INFO_MEM, C_RMU_ERR_INFO_MEM_SIZE, "C_RMU_ERR_INFO_MEM"},
+	  },
+	 {{0x9870A58, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{48, 1, "ptl_invld_dfa", C_EC_BADCON_S,
+	 {{C_RMU_ERR_INFO_PTL_INVLD_DFA, C_RMU_ERR_INFO_PTL_INVLD_DFA_SIZE,
+	   "C_RMU_ERR_INFO_PTL_INVLD_DFA"},
+	  },
+	 {{0x9870A60, "ptl_invld_dfa_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{49, 1, "ptl_invld_vni", C_EC_BADCON_S,
+	 {{C_RMU_ERR_INFO_PTL_INVLD_VNI, C_RMU_ERR_INFO_PTL_INVLD_VNI_SIZE,
+	   "C_RMU_ERR_INFO_PTL_INVLD_VNI"},
+	  },
+	 {{0x9870A68, "ptl_invld_vni_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{50, 1, "ptl_no_ptlte", C_EC_BADCON_S,
+	 {{C_RMU_ERR_INFO_PTL_NO_PTLTE, C_RMU_ERR_INFO_PTL_NO_PTLTE_SIZE,
+	   "C_RMU_ERR_INFO_PTL_NO_PTLTE"},
+	  },
+	 {{0x9870A70, "ptl_no_ptlte_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{51, 1, "enet_frame_rejected", C_EC_BADCON_NS,
+	 {{C_RMU_ERR_INFO_ENET_NO_PTLTE_SET,
+	   C_RMU_ERR_INFO_ENET_NO_PTLTE_SET_SIZE,
+	   "C_RMU_ERR_INFO_ENET_NO_PTLTE_SET"},
+	  },
+	 {{0x9870A78, "enet_frame_rejected_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{52, 1, "enet_ptlte_set_ctrl_err", C_EC_BADCON_NS,
+	 {{C_RMU_ERR_INFO_ENET_BAD_PTLTE_SET_CTRL,
+	   C_RMU_ERR_INFO_ENET_BAD_PTLTE_SET_CTRL_SIZE,
+	   "C_RMU_ERR_INFO_ENET_BAD_PTLTE_SET_CTRL"},
+	  },
+	 {{0x9870A80, "enet_ptlte_set_ctrl_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{64, 1}
+};
+
+static const struct flg_err_info c2_atu_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "crnc_ring_sync_error", C_EC_UNCOR_NS},
+	{2, 1, "crnc_ring_ecc_sbe", C_EC_COR},
+	{3, 1, "crnc_ring_ecc_mbe", C_EC_UNCOR_NS},
+	{4, 1, "crnc_ring_cmd_unknown", C_EC_UNCOR_NS},
+	{5, 1, "crnc_csr_cmd_unknown", C_EC_UNCOR_NS},
+	{6, 1, "crnc_csr_cmd_incomplete", C_EC_UNCOR_NS},
+	{7, 1, "crnc_buf_ecc_sbe", C_EC_COR},
+	{8, 1, "crnc_buf_ecc_mbe", C_EC_UNCOR_NS},
+	{32, 1, "fifo_err", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_FIFO, C_ATU_ERR_INFO_FIFO_SIZE,
+	   "C_ATU_ERR_INFO_FIFO"},
+	  },
+	 {},
+	 },
+	{33, 1, "page_perm_err", C_EC_BADCON_S,
+	 {{C_ATU_ERR_INFO_PAGE_PERM, C_ATU_ERR_INFO_PAGE_PERM_SIZE,
+	   "C_ATU_ERR_INFO_PAGE_PERM"},
+	  },
+	 {{0x10020568, "client_rsp_not_ok", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{34, 1, "ats_trans_err", C_EC_BADCON_S,
+	 {{C_ATU_ERR_INFO_ATS_TRANS, C_ATU_ERR_INFO_ATS_TRANS_SIZE,
+	   "C_ATU_ERR_INFO_ATS_TRANS"},
+	  {C_ATU_STS_ATS_VF_DISABLED, C_ATU_STS_ATS_VF_DISABLED_SIZE,
+	   "C_ATU_STS_ATS_VF_DISABLED"},
+	  {C_ATU_STS_ATS_PF_DISABLED, C_ATU_STS_ATS_PF_DISABLED_SIZE,
+	   "C_ATU_STS_ATS_PF_DISABLED"},
+	  },
+	 {{0x100205B8, "ats_trans_err", C_ERR_INDEX_NONE},
+	  {0x10020568, "client_rsp_not_ok", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{35, 1, "pcie_unsuccess_cmpl", C_EC_BADCON_S,
+	 {{C_ATU_ERR_INFO_PCIE_UC, C_ATU_ERR_INFO_PCIE_UC_SIZE,
+	   "C_ATU_ERR_INFO_PCIE_UC"},
+	  },
+	 {{0x100205B0, "pcie_unsuccess_cmpl", C_ERR_INDEX_NONE},
+	  {0x10020568, "client_rsp_not_ok", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{36, 1, "pcie_error_poisoned", C_EC_UNCOR_S,
+	 {{C_ATU_ERR_INFO_PCIE_EP, C_ATU_ERR_INFO_PCIE_EP_SIZE,
+	   "C_ATU_ERR_INFO_PCIE_EP"},
+	  },
+	 {{0x100205C0, "pcie_err_poisoned", C_ERR_INDEX_NONE},
+	  {0x10020568, "client_rsp_not_ok", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{37, 1, "ats_page_req_err", C_EC_BADCON_S,
+	 {{C_ATU_ERR_INFO_ATS_PAGE_REQ, C_ATU_ERR_INFO_ATS_PAGE_REQ_SIZE,
+	   "C_ATU_ERR_INFO_ATS_PAGE_REQ"},
+	  },
+	 {{0x10020568, "client_rsp_not_ok", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{38, 1, "no_translation", C_EC_BADCON_S,
+	 {{C_ATU_ERR_INFO_TRANSLATION, C_ATU_ERR_INFO_TRANSLATION_SIZE,
+	   "C_ATU_ERR_INFO_TRANSLATION"},
+	  },
+	 {{0x10020568, "client_rsp_not_ok", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{39, 1, "invalid_ac", C_EC_BADCON_S,
+	 {{C_ATU_ERR_INFO_AC, C_ATU_ERR_INFO_AC_SIZE, "C_ATU_ERR_INFO_AC"},
+	  },
+	 {{0x10020568, "client_rsp_not_ok", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{40, 1, "prb_expired", C_EC_BADCON_S,
+	 {{C_ATU_ERR_INFO_PRB_EXPIRED, C_ATU_ERR_INFO_PRB_EXPIRED_SIZE,
+	   "C_ATU_ERR_INFO_PRB_EXPIRED"},
+	  },
+	 {},
+	 },
+	{41, 1, "nta_pte_align_err", C_EC_BADCON_S,
+	 {{C_ATU_ERR_INFO_NTA_PTE_ALIGN, C_ATU_ERR_INFO_NTA_PTE_ALIGN_SIZE,
+	   "C_ATU_ERR_INFO_NTA_PTE_ALIGN"},
+	  },
+	 {{0x10020568, "client_rsp_not_ok", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{42, 1, "ats_odp_config_err", C_EC_BADCON_S,
+	 {{C_ATU_ERR_INFO_ATS_ODP_CONFIG, C_ATU_ERR_INFO_ATS_ODP_CONFIG_SIZE,
+	   "C_ATU_ERR_INFO_ATS_ODP_CONFIG"},
+	  },
+	 {{0x10020568, "client_rsp_not_ok", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{43, 1, "addr_out_of_range", C_EC_BADCON_S,
+	 {{C_ATU_ERR_INFO_ADDR_OUT_OF_RANGE,
+	   C_ATU_ERR_INFO_ADDR_OUT_OF_RANGE_SIZE,
+	   "C_ATU_ERR_INFO_ADDR_OUT_OF_RANGE"},
+	  },
+	 {{0x10020568, "client_rsp_not_ok", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{44, 1, "ats_page_size_config_err", C_EC_BADCON_S,
+	 {{C_ATU_ERR_INFO_ATS_PAGE_SIZE_CONFIG,
+	   C_ATU_ERR_INFO_ATS_PAGE_SIZE_CONFIG_SIZE,
+	   "C_ATU_ERR_INFO_ATS_PAGE_SIZE_CONFIG"},
+	  },
+	 {},
+	 },
+	{45, 1, "ats_page_size_err", C_EC_BADCON_S,
+	 {{C_ATU_ERR_INFO_ATS_PAGE_SIZE, C_ATU_ERR_INFO_ATS_PAGE_SIZE_SIZE,
+	   "C_ATU_ERR_INFO_ATS_PAGE_SIZE"},
+	  },
+	 {{0x10020568, "client_rsp_not_ok", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{46, 1, "p_tarb_cdt_uflow", C_EC_CRIT},
+	{47, 1, "np_tarb_cdt_uflow", C_EC_CRIT},
+	{48, 1, "ee_odp_req_err", C_EC_BADCON_S,
+	 {{C_ATU_ERR_INFO_EE_ODP_REQ, C_ATU_ERR_INFO_EE_ODP_REQ_SIZE,
+	   "C_ATU_ERR_INFO_EE_ODP_REQ"},
+	  },
+	 {{0x10020568, "client_rsp_not_ok", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{49, 1, "ats_fn_disabled_err", C_EC_BADCON_S,
+	 {{C_ATU_ERR_INFO_ATS_FN_DISABLED, C_ATU_ERR_INFO_ATS_FN_DISABLED_SIZE,
+	   "C_ATU_ERR_INFO_ATS_FN_DISABLED"},
+	  },
+	 {},
+	 },
+	{50, 1, "rarb_hw_err", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_RARB, C_ATU_ERR_INFO_RARB_SIZE,
+	   "C_ATU_ERR_INFO_RARB"},
+	  },
+	 {},
+	 },
+	{51, 1, "epoch_cnt_err", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_EPOCH_CNT, C_ATU_ERR_INFO_EPOCH_CNT_SIZE,
+	   "C_ATU_ERR_INFO_EPOCH_CNT"},
+	  },
+	 {},
+	 },
+	{52, 1, "rspq_cmpl_err", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_RSPQ_CMPL, C_ATU_ERR_INFO_RSPQ_CMPL_SIZE,
+	   "C_ATU_ERR_INFO_RSPQ_CMPL"},
+	  },
+	 {{0x10020568, "client_rsp_not_ok", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{53, 1, "odp_unexp_idx_err", C_EC_BADCON_S,
+	 {{C_ATU_ERR_INFO_ODP_UNEXP_IDX, C_ATU_ERR_INFO_ODP_UNEXP_IDX_SIZE,
+	   "C_ATU_ERR_INFO_ODP_UNEXP_IDX"},
+	  },
+	 {},
+	 },
+	{54, 1, "in_progress_cnt_err", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_IN_PROGRESS_CNT, C_ATU_ERR_INFO_IN_PROGRESS_CNT_SIZE,
+	   "C_ATU_ERR_INFO_IN_PROGRESS_CNT"},
+	  },
+	 {},
+	 },
+	{64, 1}
+};
+
+static const struct flg_err_info c2_atu_ext_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "ac_mem_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{2, 1, "otb_mem_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{3, 1, "tag_mem_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{4, 1, "ingress_bus_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{5, 1, "data_mem_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{6, 1, "chain_tail_mem_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{7, 1, "chain_next_mem_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{8, 1, "missq_mem_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{9, 1, "uniqq_mem_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{10, 1, "chain_mem_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{11, 1, "pointer_mem_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{12, 1, "replayq_mem_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{13, 1, "retryq_mem_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{14, 1, "prb_mem_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{15, 1, "invalq_mem_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{16, 1, "rspinfoq_mem_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{17, 1, "cmpldata_mem_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{18, 1, "atucq_mem_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{19, 1, "ats_prq_mem_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{20, 1, "rarb_hdr_bus_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{21, 1, "rarb_data_bus_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{22, 1, "odpq_mem_cor", C_EC_COR,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020400, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{33, 1, "ac_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{34, 1, "otb_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{35, 1, "tag_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{36, 1, "ingress_bus_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{37, 1, "data_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{38, 1, "chain_tail_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{39, 1, "chain_next_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{40, 1, "missq_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{41, 1, "uniqq_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{42, 1, "chain_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{43, 1, "pointer_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{44, 1, "replayq_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{45, 1, "retryq_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{46, 1, "prb_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{47, 1, "invalq_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{48, 1, "rspinfoq_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{49, 1, "cmpldata_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{50, 1, "atucq_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{51, 1, "ats_prq_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{52, 1, "rarb_hdr_bus_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{53, 1, "rarb_data_bus_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{54, 1, "odpq_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{56, 1, "anchor_vld_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{57, 1, "anchor_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_ATU_ERR_INFO_MEM, C_ATU_ERR_INFO_MEM_SIZE, "C_ATU_ERR_INFO_MEM"},
+	  },
+	 {{0x10020408, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{64, 1}
+};
+
+static const struct flg_err_info c2_cq_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "crnc_ring_sync_error", C_EC_UNCOR_NS},
+	{2, 1, "crnc_ring_ecc_sbe", C_EC_COR},
+	{3, 1, "crnc_ring_ecc_mbe", C_EC_UNCOR_NS},
+	{4, 1, "crnc_ring_cmd_unknown", C_EC_UNCOR_NS},
+	{5, 1, "crnc_csr_cmd_unknown", C_EC_UNCOR_NS},
+	{6, 1, "crnc_csr_cmd_incomplete", C_EC_UNCOR_NS},
+	{7, 1, "crnc_buf_ecc_sbe", C_EC_COR},
+	{8, 1, "crnc_buf_ecc_mbe", C_EC_UNCOR_NS},
+	{16, 1, "fifo_err", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_FIFO_ERR, C_CQ_ERR_INFO_FIFO_ERR_SIZE,
+	   "C_CQ_ERR_INFO_FIFO_ERR"},
+	  },
+	 {},
+	 },
+	{17, 1, "credit_uflw", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_CC, C_CQ_ERR_INFO_CC_SIZE, "C_CQ_ERR_INFO_CC"},
+	  },
+	 {},
+	 },
+	{18, 1, "c_state_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{19, 1, "rarb_hdr_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{20, 1, "rarb_data_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{21, 1, "event_ram_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{22, 1, "ll_state_mem_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{23, 1, "ll_status_mem_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{24, 1, "c_state_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{25, 1, "rarb_hdr_ucor", C_EC_CRIT,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{26, 1, "rarb_data_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{27, 1, "event_ram_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{28, 1, "ll_state_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{29, 1, "ll_status_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{30, 1, "ll_nempty_vectr_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{31, 1, "ll_full_vectr_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{32, 1, "event_cnt_ovf", C_EC_INFO},
+	{33, 1, "tle_oversubscribed", C_EC_BADCON_NS},
+	{34, 1, "rarb_bad_xactn_err", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_RARB, C_CQ_ERR_INFO_RARB_SIZE, "C_CQ_ERR_INFO_RARB"},
+	  },
+	 {{0x100038, "rarb_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{35, 1, "rarb_cmpltn_err", C_EC_CRIT,
+	 {{C_CQ_ERR_INFO_RARB, C_CQ_ERR_INFO_RARB_SIZE, "C_CQ_ERR_INFO_RARB"},
+	  },
+	 {{0x100038, "rarb_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{36, 1, "rarb_tou_wr_hw_err", C_EC_UNCOR_S,
+	 {{C_CQ_ERR_INFO_RARB, C_CQ_ERR_INFO_RARB_SIZE, "C_CQ_ERR_INFO_RARB"},
+	  },
+	 {{0x100038, "rarb_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{37, 1, "rarb_ll_wr_hw_err", C_EC_UNCOR_S,
+	 {{C_CQ_ERR_INFO_RARB_LL, C_CQ_ERR_INFO_RARB_LL_SIZE,
+	   "C_CQ_ERR_INFO_RARB_LL"},
+	  },
+	 {{0x100030, "rarb_ll_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{38, 1, "rarb_invld_wr_sw_err", C_EC_BADCON_NS,
+	 {{C_CQ_ERR_INFO_RARB, C_CQ_ERR_INFO_RARB_SIZE, "C_CQ_ERR_INFO_RARB"},
+	  },
+	 {{0x100038, "rarb_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{39, 1, "rarb_tou_wr_sw_err", C_EC_BADCON_S,
+	 {{C_CQ_ERR_INFO_RARB, C_CQ_ERR_INFO_RARB_SIZE, "C_CQ_ERR_INFO_RARB"},
+	  },
+	 {{0x100038, "rarb_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{40, 1, "rarb_ll_wr_sw_err", C_EC_BADCON_S,
+	 {{C_CQ_ERR_INFO_RARB_LL, C_CQ_ERR_INFO_RARB_LL_SIZE,
+	   "C_CQ_ERR_INFO_RARB_LL"},
+	  },
+	 {{0x100030, "rarb_ll_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{41, 1, "msg_cnt_uflw", C_EC_BADCON_S,
+	 {{C_CQ_ERR_INFO_OCU_MAP, C_CQ_ERR_INFO_OCU_MAP_SIZE,
+	   "C_CQ_ERR_INFO_OCU_MAP"},
+	  },
+	 {},
+	 },
+	{42, 1, "fq_load_uflw", C_EC_BADCON_S,
+	 {{C_CQ_ERR_INFO_OCU_MAP, C_CQ_ERR_INFO_OCU_MAP_SIZE,
+	   "C_CQ_ERR_INFO_OCU_MAP"},
+	  },
+	 {},
+	 },
+	{43, 1, "wr_ptr_updt_err", C_EC_BADCON_S,
+	 {{C_CQ_ERR_INFO_WR_PTR_UPDT, C_CQ_ERR_INFO_WR_PTR_UPDT_SIZE,
+	   "C_CQ_ERR_INFO_WR_PTR_UPDT"},
+	  },
+	 {{0x100040, "wr_ptr_updt_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{44, 1, "ard_ptr_update_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{45, 1, "tx_fqu_free_list_ovf", C_EC_BADCON_S},
+	{46, 1, "tou_fqu_free_list_ovf", C_EC_BADCON_S},
+	{64, 1}
+};
+
+static const struct flg_err_info c2_cq_ext_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "remap_array_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{2, 1, "cprof_table_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{3, 1, "ac_remap_array_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{4, 1, "tou_fq_cmd_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{5, 1, "cq_fq_cmd_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{6, 1, "tou_fid_list_ptrs_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{7, 1, "cq_fid_list_ptrs_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{8, 1, "ll_buf_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{9, 1, "tx_ptr_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{10, 1, "tx_base_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{11, 1, "tx_ocuset_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{12, 1, "tg_ptr_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{13, 1, "tg_base_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{14, 1, "pfq_bufs_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{15, 1, "pfq_bufs_info_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{16, 1, "pfq_ptrs_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{17, 1, "target_pfq_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{18, 1, "tu_pfq_bufs_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{19, 1, "tu_pfq_info_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{20, 1, "tu_pfq_list_ptrs_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{21, 1, "ct_table_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{22, 1, "ee_table_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{23, 1, "ptlte_table_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{24, 1, "ct_events_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{25, 1, "thresh_table_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{26, 1, "trig_ct_field_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{27, 1, "trig_list_nodes_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{28, 1, "tou_ll_reorder_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{29, 1, "tou_cmd_ptrs_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{30, 1, "in_fifo_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{31, 1, "wb_addr_cor", C_EC_COR,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100020, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{33, 1, "remap_array_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{34, 1, "cprof_table_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{35, 1, "ac_remap_array_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{36, 1, "tou_fq_cmd_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{37, 1, "cq_fq_cmd_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{38, 1, "tou_fid_list_ptrs_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{39, 1, "cq_fid_list_ptrs_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{40, 1, "ll_buf_ucor", C_EC_TRNSNT_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{41, 1, "tx_ptr_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{42, 1, "tx_base_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{43, 1, "tx_ocuset_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{44, 1, "tg_ptr_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{45, 1, "tg_base_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{46, 1, "pfq_bufs_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{47, 1, "pfq_bufs_info_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{48, 1, "pfq_ptrs_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{49, 1, "target_pfq_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{50, 1, "tu_pfq_bufs_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{51, 1, "tu_pfq_info_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{52, 1, "tu_pfq_list_ptrs_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{53, 1, "ct_table_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{54, 1, "ee_table_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{55, 1, "ptlte_table_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{56, 1, "ct_events_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{57, 1, "thresh_table_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{58, 1, "trig_ct_field_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{59, 1, "trig_list_nodes_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{60, 1, "tou_ll_reorder_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{61, 1, "tou_cmd_ptrs_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{62, 1, "in_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{63, 1, "wb_addr_ucor", C_EC_UNCOR_NS,
+	 {{C_CQ_ERR_INFO_MEM, C_CQ_ERR_INFO_MEM_SIZE, "C_CQ_ERR_INFO_MEM"},
+	  },
+	 {{0x100028, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{64, 1}
+};
+
+static const struct flg_err_info c2_ee_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "crnc_ring_sync_error", C_EC_UNCOR_NS},
+	{2, 1, "crnc_ring_ecc_sbe", C_EC_COR},
+	{3, 1, "crnc_ring_ecc_mbe", C_EC_UNCOR_NS},
+	{4, 1, "crnc_ring_cmd_unknown", C_EC_UNCOR_NS},
+	{5, 1, "crnc_csr_cmd_unknown", C_EC_UNCOR_NS},
+	{6, 1, "crnc_csr_cmd_incomplete", C_EC_UNCOR_NS},
+	{7, 1, "crnc_buf_ecc_sbe", C_EC_COR},
+	{8, 1, "crnc_buf_ecc_mbe", C_EC_UNCOR_NS},
+	{32, 1, "eq_ovflw_rsrvn", C_EC_BADCON_S,
+	 {{C_EE_ERR_INFO_EQ_CFG, C_EE_ERR_INFO_EQ_CFG_SIZE,
+	   "C_EE_ERR_INFO_EQ_CFG"},
+	  },
+	 {},
+	 },
+	{33, 1, "eq_ovflw_fc_sc", C_EC_BADCON_S,
+	 {{C_EE_ERR_INFO_EQ_CFG, C_EE_ERR_INFO_EQ_CFG_SIZE,
+	   "C_EE_ERR_INFO_EQ_CFG"},
+	  },
+	 {},
+	 },
+	{34, 1, "eq_ovflw_ordinary", C_EC_BADCON_S,
+	 {{C_EE_ERR_INFO_EQ_CFG, C_EE_ERR_INFO_EQ_CFG_SIZE,
+	   "C_EE_ERR_INFO_EQ_CFG"},
+	  },
+	 {},
+	 },
+	{35, 1, "eq_dsabld_event", C_EC_BADCON_NS,
+	 {{C_EE_ERR_INFO_EQ_CFG, C_EE_ERR_INFO_EQ_CFG_SIZE,
+	   "C_EE_ERR_INFO_EQ_CFG"},
+	  },
+	 {{0x100E50, "eq_dsabld_event_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{36, 1, "eq_dsabld_sw_state_wr", C_EC_BADCON_NS,
+	 {{C_EE_ERR_INFO_EQ_CFG, C_EE_ERR_INFO_EQ_CFG_SIZE,
+	   "C_EE_ERR_INFO_EQ_CFG"},
+	  },
+	 {{0x100E58, "eq_dsabld_sws_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{37, 1, "eq_dsabld_lpe_query", C_EC_BADCON_NS,
+	 {{C_EE_ERR_INFO_EQ_CFG, C_EE_ERR_INFO_EQ_CFG_SIZE,
+	   "C_EE_ERR_INFO_EQ_CFG"},
+	  },
+	 {{0x100E60, "eq_dsabld_lpeq_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{38, 1, "eq_rsrvn_uflw", C_EC_CRIT,
+	 {{C_EE_ERR_INFO_RSRVN_UFLW, C_EE_ERR_INFO_RSRVN_UFLW_SIZE,
+	   "C_EE_ERR_INFO_RSRVN_UFLW"},
+	  },
+	 {{0x100E68, "eq_rsrvn_uflw_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{39, 1, "unxpctd_trnsltn_rsp", C_EC_CRIT,
+	 {{C_EE_ERR_INFO_TRNSLTN, C_EE_ERR_INFO_TRNSLTN_SIZE,
+	   "C_EE_ERR_INFO_TRNSLTN"},
+	  },
+	 {{0x100E70, "unxpctd_trnsltn_rsp_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{40, 1, "rarb_hw_err", C_EC_UNCOR_NS,
+	 {{C_EE_ERR_INFO_RARB, C_EE_ERR_INFO_RARB_SIZE, "C_EE_ERR_INFO_RARB"},
+	  },
+	 {{0x100E78, "rarb_hw_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{41, 1, "rarb_sw_err", C_EC_BADCON_NS,
+	 {{C_EE_ERR_INFO_RARB, C_EE_ERR_INFO_RARB_SIZE, "C_EE_ERR_INFO_RARB"},
+	  },
+	 {{0x100E80, "rarb_sw_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{42, 1, "tarb_err", C_EC_UNCOR_NS,
+	 {{C_EE_ERR_INFO_TARB, C_EE_ERR_INFO_TARB_SIZE, "C_EE_ERR_INFO_TARB"},
+	  },
+	 {{0x100E88, "tarb_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{43, 1, "eq_state_ucor", C_EC_UNCOR_NS,
+	 {{C_EE_ERR_INFO_EQ_UCOR, C_EE_ERR_INFO_EQ_UCOR_SIZE,
+	   "C_EE_ERR_INFO_EQ_UCOR"},
+	  },
+	 {{0x100E90, "eq_state_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{48, 1, "unxpctd_cq_cdt", C_EC_CRIT},
+	{49, 1, "unxpctd_tarb_cdt", C_EC_CRIT},
+	{50, 1, "eq_state_updt_urun", C_EC_CRIT},
+	{51, 1, "eq_state_updt_orun", C_EC_CRIT},
+	{64, 1}
+};
+
+static const struct flg_err_info c2_ee_ext_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "leo_mem_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{2, 1, "pts_mem_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{3, 1, "ixe_bus_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{4, 1, "lpe_bus_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{5, 1, "mst_bus_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{6, 1, "pct_bus_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{7, 1, "hni_bus_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{8, 1, "cq_bus_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{9, 1, "eqd_mem_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{10, 1, "eqsws_mem_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{11, 1, "eqhws_mem_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{12, 1, "ecbsb_mem_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{13, 1, "ecb_mem_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{14, 1, "rarb_hdr_bus_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{15, 1, "rarb_data_bus_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{16, 1, "acb_vect_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{17, 1, "eqswupd_vect_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{18, 1, "lm_cbeq_mem_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{19, 1, "lm_state_vect_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{20, 1, "trnrsp_mem_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{21, 1, "trnrsp_bus_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{22, 1, "rlscb_vect_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{23, 1, "trncb_vect_cor", C_EC_COR,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E40, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{26, 1, "leo_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{27, 1, "pts_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{28, 1, "ixe_bus_ucor", C_EC_UNCOR_NS,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{29, 1, "lpe_bus_ucor", C_EC_UNCOR_NS,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{30, 1, "mst_bus_ucor", C_EC_UNCOR_NS,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{31, 1, "pct_bus_ucor", C_EC_UNCOR_NS,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{32, 1, "hni_bus_ucor", C_EC_UNCOR_NS,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{33, 1, "cq_bus_ucor", C_EC_UNCOR_NS,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{34, 1, "eqd_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{35, 1, "eqsws_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{36, 1, "eqhws_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{37, 1, "ecbsb_mem_ucor", C_EC_CRIT,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{38, 1, "ecb_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{39, 1, "rarb_hdr_bus_ucor", C_EC_UNCOR_NS,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{40, 1, "rarb_data_bus_ucor", C_EC_UNCOR_NS,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{41, 1, "acb_vect_ucor", C_EC_CRIT,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{42, 1, "lm_cbeq_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{43, 1, "trnrsp_mem_ucor", C_EC_CRIT,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{44, 1, "trnrsp_bus_ucor", C_EC_UNCOR_NS,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{45, 1, "rlscb_vect_ucor", C_EC_CRIT,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{46, 1, "trncb_vect_ucor", C_EC_CRIT,
+	 {{C_EE_ERR_INFO_MEM, C_EE_ERR_INFO_MEM_SIZE, "C_EE_ERR_INFO_MEM"},
+	  },
+	 {{0x100E48, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{49, 1, "ixe_to_ee_urun", C_EC_CRIT},
+	{50, 1, "ixe_to_ee_orun", C_EC_CRIT},
+	{51, 1, "lpe_to_ee_urun", C_EC_CRIT},
+	{52, 1, "lpe_to_ee_orun", C_EC_CRIT},
+	{53, 1, "mst_to_ee_urun", C_EC_CRIT},
+	{54, 1, "mst_to_ee_orun", C_EC_CRIT},
+	{55, 1, "pct_to_ee_urun", C_EC_CRIT},
+	{56, 1, "pct_to_ee_orun", C_EC_CRIT},
+	{57, 1, "hni_to_ee_urun", C_EC_CRIT},
+	{58, 1, "hni_to_ee_orun", C_EC_CRIT},
+	{59, 1, "cq_to_ee_urun", C_EC_CRIT},
+	{60, 1, "cq_to_ee_orun", C_EC_CRIT},
+	{64, 1}
+};
+
+static const struct flg_err_info c2_hni_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "crnc_ring_sync_error", C_EC_UNCOR_NS},
+	{2, 1, "crnc_ring_ecc_sbe", C_EC_COR},
+	{3, 1, "crnc_ring_ecc_mbe", C_EC_UNCOR_NS},
+	{4, 1, "crnc_ring_cmd_unknown", C_EC_UNCOR_NS},
+	{5, 1, "crnc_csr_cmd_unknown", C_EC_UNCOR_NS},
+	{6, 1, "crnc_csr_cmd_incomplete", C_EC_UNCOR_NS},
+	{7, 1, "crnc_buf_ecc_sbe", C_EC_COR},
+	{8, 1, "crnc_buf_ecc_mbe", C_EC_UNCOR_NS},
+	{10, 1, "event_cnt_ovf", C_EC_INFO},
+	{11, 1, "llr_flit_cor", C_EC_COR,
+	 {{C2_HNI_ERR_INFO_ECC, C2_HNI_ERR_INFO_ECC_SIZE,
+	   "C2_HNI_ERR_INFO_ECC"},
+	  },
+	 {{0x1002000, "cor_ecc_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{12, 1, "rx_stat_fifo_cor", C_EC_COR,
+	 {{C2_HNI_ERR_INFO_ECC, C2_HNI_ERR_INFO_ECC_SIZE,
+	   "C2_HNI_ERR_INFO_ECC"},
+	  },
+	 {{0x1002000, "cor_ecc_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{13, 1, "rx_pkt_fifo_cor", C_EC_COR,
+	 {{C2_HNI_ERR_INFO_ECC, C2_HNI_ERR_INFO_ECC_SIZE,
+	   "C2_HNI_ERR_INFO_ECC"},
+	  },
+	 {{0x1002000, "cor_ecc_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{14, 1, "timestamp_cor", C_EC_COR,
+	 {{C2_HNI_ERR_INFO_ECC, C2_HNI_ERR_INFO_ECC_SIZE,
+	   "C2_HNI_ERR_INFO_ECC"},
+	  },
+	 {{0x1002000, "cor_ecc_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{15, 1, "hrp_fifo_cor", C_EC_COR,
+	 {{C2_HNI_ERR_INFO_ECC, C2_HNI_ERR_INFO_ECC_SIZE,
+	   "C2_HNI_ERR_INFO_ECC"},
+	  },
+	 {{0x1002000, "cor_ecc_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{16, 1, "fgfc_fifo_cor", C_EC_COR,
+	 {{C2_HNI_ERR_INFO_ECC, C2_HNI_ERR_INFO_ECC_SIZE,
+	   "C2_HNI_ERR_INFO_ECC"},
+	  },
+	 {{0x1002000, "cor_ecc_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{17, 1, "tx_flit_cor", C_EC_COR,
+	 {{C2_HNI_ERR_INFO_ECC, C2_HNI_ERR_INFO_ECC_SIZE,
+	   "C2_HNI_ERR_INFO_ECC"},
+	  },
+	 {{0x1002000, "cor_ecc_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{18, 1, "event_ram_cor", C_EC_COR,
+	 {{C2_HNI_ERR_INFO_ECC, C2_HNI_ERR_INFO_ECC_SIZE,
+	   "C2_HNI_ERR_INFO_ECC"},
+	  },
+	 {{0x1002000, "cor_ecc_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{19, 1, "ixe_flit_cor", C_EC_COR,
+	 {{C2_HNI_ERR_INFO_ECC, C2_HNI_ERR_INFO_ECC_SIZE,
+	   "C2_HNI_ERR_INFO_ECC"},
+	  },
+	 {{0x1002000, "cor_ecc_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{20, 1, "llr_flit_ucor", C_EC_UNCOR_NS,
+	 {{C2_HNI_ERR_INFO_ECC, C2_HNI_ERR_INFO_ECC_SIZE,
+	   "C2_HNI_ERR_INFO_ECC"},
+	  },
+	 {{0x1002008, "ucor_ecc_err_cntr", C_ERR_INDEX_NONE},
+	  {0x10021A8, "rx_bad_ieee", C_ERR_INDEX_NONE},
+	  {0x10021B0, "rx_bad_opt", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{21, 1, "rx_stat_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C2_HNI_ERR_INFO_ECC, C2_HNI_ERR_INFO_ECC_SIZE,
+	   "C2_HNI_ERR_INFO_ECC"},
+	  },
+	 {{0x1002008, "ucor_ecc_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{22, 1, "rx_pkt_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C2_HNI_ERR_INFO_ECC, C2_HNI_ERR_INFO_ECC_SIZE,
+	   "C2_HNI_ERR_INFO_ECC"},
+	  },
+	 {{0x1002008, "ucor_ecc_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{23, 1, "timestamp_ucor", C_EC_UNCOR_NS,
+	 {{C2_HNI_ERR_INFO_ECC, C2_HNI_ERR_INFO_ECC_SIZE,
+	   "C2_HNI_ERR_INFO_ECC"},
+	  },
+	 {{0x1002008, "ucor_ecc_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{24, 1, "hrp_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C2_HNI_ERR_INFO_ECC, C2_HNI_ERR_INFO_ECC_SIZE,
+	   "C2_HNI_ERR_INFO_ECC"},
+	  },
+	 {{0x1002008, "ucor_ecc_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{25, 1, "fgfc_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C2_HNI_ERR_INFO_ECC, C2_HNI_ERR_INFO_ECC_SIZE,
+	   "C2_HNI_ERR_INFO_ECC"},
+	  },
+	 {{0x1002008, "ucor_ecc_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{26, 1, "tx_flit_ucor", C_EC_UNCOR_NS,
+	 {{C2_HNI_ERR_INFO_ECC, C2_HNI_ERR_INFO_ECC_SIZE,
+	   "C2_HNI_ERR_INFO_ECC"},
+	  },
+	 {{0x1002008, "ucor_ecc_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{27, 1, "event_ram_ucor", C_EC_UNCOR_NS,
+	 {{C2_HNI_ERR_INFO_ECC, C2_HNI_ERR_INFO_ECC_SIZE,
+	   "C2_HNI_ERR_INFO_ECC"},
+	  },
+	 {{0x1002008, "ucor_ecc_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{28, 1, "ixe_flit_ucor", C_EC_UNCOR_NS,
+	 {{C2_HNI_ERR_INFO_ECC, C2_HNI_ERR_INFO_ECC_SIZE,
+	   "C2_HNI_ERR_INFO_ECC"},
+	  },
+	 {{0x1002008, "ucor_ecc_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{29, 1, "fifo_err", C_EC_UNCOR_NS,
+	 {{C2_HNI_ERR_INFO_FIFO, C2_HNI_ERR_INFO_FIFO_SIZE,
+	   "C2_HNI_ERR_INFO_FIFO"},
+	  },
+	 {},
+	 },
+	{30, 1, "llr_chksum_bad", C_EC_UNCOR_NS, {},
+	 {{0x10021B0, "rx_bad_opt", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{31, 1, "llr_fcs_bad", C_EC_UNCOR_NS, {},
+	 {{0x10021A8, "rx_bad_ieee", C_ERR_INDEX_NONE},
+	  {0x10021B0, "rx_bad_opt", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{32, 1, "llr_ctrl_perr", C_EC_UNCOR_NS, {},
+	 {{0x10021A8, "rx_bad_ieee", C_ERR_INDEX_NONE},
+	  {0x10021B0, "rx_bad_opt", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{33, 1, "llr_exceed_mfs", C_EC_UNCOR_NS, {},
+	 {{0x10021F0, "rx_ok_too_long", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{34, 1, "llr_eopb", C_EC_UNCOR_NS, {},
+	 {{0x10021A8, "rx_bad_ieee", C_ERR_INDEX_NONE},
+	  {0x10021B0, "rx_bad_opt", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{35, 1, "pause_timeout", C_EC_BADCON_NS,
+	 {{C_HNI_STS_PAUSE_TIMEOUT, C_HNI_STS_PAUSE_TIMEOUT_SIZE,
+	   "C_HNI_STS_PAUSE_TIMEOUT"},
+	  },
+	 {},
+	 },
+	{36, 1, "fgfc_err", C_EC_UNCOR_NS,
+	 {{C2_HNI_ERR_INFO_FGFC, C2_HNI_ERR_INFO_FGFC_SIZE,
+	   "C2_HNI_ERR_INFO_FGFC"},
+	  },
+	 {},
+	 },
+	{37, 1, "credit_uflw", C_EC_UNCOR_NS,
+	 {{C2_HNI_ERR_INFO_CC, C2_HNI_ERR_INFO_CC_SIZE, "C2_HNI_ERR_INFO_CC"},
+	  },
+	 {},
+	 },
+	{38, 1, "tx_size_err", C_EC_UNCOR_NS,
+	 {{C2_HNI_ERR_INFO_SIZE_ERR, C2_HNI_ERR_INFO_SIZE_ERR_SIZE,
+	   "C2_HNI_ERR_INFO_SIZE_ERR"},
+	  },
+	 {{0x10023F0, "tx_std_size_err", C_ERR_INDEX_NONE},
+	  {0x10023F8, "tx_opt_size_err", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{39, 1, "rx_pause_err", C_EC_BADCON_NS},
+	{40, 8, "pfc_fifo_oflw", C_EC_CRIT, {},
+	 {{0x1002080, "pfc_fifo_oflw_cntr", C_ERR_INDEX_MATCH},
+	  },
+	 },
+	{48, 8, "discard_err", C_EC_UNCOR_NS,
+	 {{C2_HNI_ERR_INFO_DISCARD, C2_HNI_ERR_INFO_DISCARD_SIZE,
+	   "C2_HNI_ERR_INFO_DISCARD"},
+	  },
+	 {{0x10020C0, "discard_cntr", C_ERR_INDEX_MATCH},
+	  },
+	 },
+	{56, 8, "disable_err", C_EC_UNCOR_NS},
+	{64, 1}
+};
+
+static const struct flg_err_info c2_hni_ext_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "pmi_err", C_EC_BADCON_NS,
+	 {{C2_HNI_EXT_ERR_INFO_PMI, C2_HNI_EXT_ERR_INFO_PMI_SIZE,
+	   "C2_HNI_EXT_ERR_INFO_PMI"},
+	  },
+	 {},
+	 },
+	{2, 1, "fsm_err", C_EC_BADCON_NS,
+	 {{C2_HNI_EXT_ERR_INFO_FSM, C2_HNI_EXT_ERR_INFO_FSM_SIZE,
+	   "C2_HNI_EXT_ERR_INFO_FSM"},
+	  },
+	 {},
+	 },
+	{3, 1, "pmi_ack", C_EC_INFO},
+	{4, 1, "rx_ctrl_perr", C_EC_CRIT},
+	{5, 1, "tx_ctrl_perr", C_EC_UNCOR_NS},
+	{64, 1}
+};
+
+static const struct flg_err_info c2_ixe_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "crnc_ring_sync_error", C_EC_UNCOR_NS},
+	{2, 1, "crnc_ring_ecc_sbe", C_EC_COR},
+	{3, 1, "crnc_ring_ecc_mbe", C_EC_UNCOR_NS},
+	{4, 1, "crnc_ring_cmd_unknown", C_EC_UNCOR_NS},
+	{5, 1, "crnc_csr_cmd_unknown", C_EC_UNCOR_NS},
+	{6, 1, "crnc_csr_cmd_incomplete", C_EC_UNCOR_NS},
+	{7, 1, "crnc_buf_ecc_sbe", C_EC_COR},
+	{8, 1, "crnc_buf_ecc_mbe", C_EC_UNCOR_NS},
+	{32, 1, "pafa_perr", C_EC_UNCOR_NS},
+	{33, 1, "fifo_err", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_FIFO_ERR, C_IXE_ERR_INFO_FIFO_ERR_SIZE,
+	   "C_IXE_ERR_INFO_FIFO_ERR"},
+	  },
+	 {},
+	 },
+	{34, 1, "credit_uflw", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_CC, C_IXE_ERR_INFO_CC_SIZE, "C_IXE_ERR_INFO_CC"},
+	  },
+	 {},
+	 },
+	{35, 1, "pcie_unsuccess_cmpl", C_EC_BADCON_S,
+	 {{C_IXE_ERR_INFO_PCIE_UC, C_IXE_ERR_INFO_PCIE_UC_SIZE,
+	   "C_IXE_ERR_INFO_PCIE_UC"},
+	  },
+	 {{0x9870A10, "dmawr_pcie_unsuccess_cmpl", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{36, 1, "pcie_error_poisoned", C_EC_UNCOR_S,
+	 {{C_IXE_ERR_INFO_PCIE_EP, C_IXE_ERR_INFO_PCIE_EP_SIZE,
+	   "C_IXE_ERR_INFO_PCIE_EP"},
+	  },
+	 {{0x9870A18, "dmawr_pcie_err_poisoned", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{37, 1, "port_dfa_mismatch", C_EC_UNCOR_NS, {},
+	 {{0x9870520, "port_dfa_mismatch", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{38, 1, "port_discard_trig", C_EC_INFO,
+	 {{C_IXE_CFG_DISCARD, C_IXE_CFG_DISCARD_SIZE, "C_IXE_CFG_DISCARD"},
+	  },
+	 {},
+	 },
+	{39, 1, "hdr_checksum_err", C_EC_TRNSNT_NS, {},
+	 {{0x9870528, "hdr_checksum_errors", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{40, 1, "hdr_ecc_err", C_EC_TRNSNT_NS, {},
+	 {{0x9870568, "hdr_ecc_errors", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{41, 1, "get_len_err", C_EC_TRNSNT_NS, {},
+	 {{0x9870548, "get_len_errors", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{42, 1, "ipv4_checksum_err", C_EC_TRNSNT_NS,
+	 {{C_IXE_ERR_INFO_ETH_PARSE, C_IXE_ERR_INFO_ETH_PARSE_SIZE,
+	   "C_IXE_ERR_INFO_ETH_PARSE"},
+	  },
+	 {{0x9870530, "ipv4_checksum_errors", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{43, 1, "ipv4_options_err", C_EC_TRNSNT_NS,
+	 {{C_IXE_ERR_INFO_ETH_PARSE, C_IXE_ERR_INFO_ETH_PARSE_SIZE,
+	   "C_IXE_ERR_INFO_ETH_PARSE"},
+	  },
+	 {{0x9870540, "ip_options_errors", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{44, 1, "ipv6_options_err", C_EC_TRNSNT_NS,
+	 {{C_IXE_ERR_INFO_ETH_PARSE, C_IXE_ERR_INFO_ETH_PARSE_SIZE,
+	   "C_IXE_ERR_INFO_ETH_PARSE"},
+	  },
+	 {{0x9870540, "ip_options_errors", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{45, 1, "hrp_req_err", C_EC_TRNSNT_NS, {},
+	 {{0x9870538, "hrp_req_errors", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{46, 1, "parser_disable", C_EC_CRIT},
+	{47, 1, "pbuf_pkt_perr", C_EC_DEGRD_NS, {},
+	 {{0x9870558, "parser_par_errors", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{48, 1, "pbuf_rd_err", C_EC_DEGRD_NS, {},
+	 {{0x9870560, "pbuf_rd_errors", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{49, 1, "pkt_flit_fifo_perr", C_EC_TRNSNT_NS, {},
+	 {{0x9870558, "parser_par_errors", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{50, 1, "amo_align_err", C_EC_BADCON_S,
+	 {{C_IXE_ERR_INFO_AMO_OP, C_IXE_ERR_INFO_AMO_OP_SIZE,
+	   "C_IXE_ERR_INFO_AMO_OP"},
+	  },
+	 {{0x98709F8, "dmawr_amo_misaligned", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{51, 1, "amo_op_err", C_EC_BADCON_S,
+	 {{C_IXE_ERR_INFO_AMO_OP, C_IXE_ERR_INFO_AMO_OP_SIZE,
+	   "C_IXE_ERR_INFO_AMO_OP"},
+	  },
+	 {{0x9870A00, "dmawr_amo_invalid_op", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{52, 1, "amo_fp_inexact", C_EC_INFO,
+	 {{C_IXE_ERR_INFO_FP_INEXACT, C_IXE_ERR_INFO_FP_INEXACT_SIZE,
+	   "C_IXE_ERR_INFO_FP_INEXACT"},
+	  },
+	 {{0x98709F0, "dmawr_amo_ex_inexact", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{53, 1, "amo_fp_overflow", C_EC_INFO,
+	 {{C_IXE_ERR_INFO_FP_OVERFLOW, C_IXE_ERR_INFO_FP_OVERFLOW_SIZE,
+	   "C_IXE_ERR_INFO_FP_OVERFLOW"},
+	  },
+	 {{0x98709E0, "dmawr_amo_ex_overflow", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{54, 1, "amo_fp_underflow", C_EC_INFO,
+	 {{C_IXE_ERR_INFO_FP_UNDERFLOW, C_IXE_ERR_INFO_FP_UNDERFLOW_SIZE,
+	   "C_IXE_ERR_INFO_FP_UNDERFLOW"},
+	  },
+	 {{0x98709E8, "dmawr_amo_ex_underflow", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{55, 1, "amo_fp_invalid", C_EC_INFO,
+	 {{C_IXE_ERR_INFO_FP_INVALID, C_IXE_ERR_INFO_FP_INVALID_SIZE,
+	   "C_IXE_ERR_INFO_FP_INVALID"},
+	  },
+	 {{0x98709D8, "dmawr_amo_ex_invalid", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{56, 1, "rarb_hw_err", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_RARB, C_IXE_ERR_INFO_RARB_SIZE,
+	   "C_IXE_ERR_INFO_RARB"},
+	  },
+	 {},
+	 },
+	{57, 1, "amo_length_err", C_EC_BADCON_S,
+	 {{C_IXE_ERR_INFO_AMO_LENGTH, C_IXE_ERR_INFO_AMO_LENGTH_SIZE,
+	   "C_IXE_ERR_INFO_AMO_LENGTH"},
+	  },
+	 {{0x9870A08, "dmawr_amo_len_err", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{58, 1, "pbuf_overflow", C_EC_CRIT},
+	{64, 1}
+};
+
+static const struct flg_err_info c2_ixe_ext_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "flop_fifo_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{2, 1, "put_resp_mem_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{3, 1, "get_req_mem_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{4, 1, "rdfq_list_mem_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{5, 1, "wr_md_mem_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{6, 1, "event_fifo_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{7, 1, "wr_ev_mem_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{8, 1, "pkt_flit_fifo_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{9, 1, "pbuf_list_mem_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{10, 1, "pbuf_sb_mem_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{11, 1, "atu_resp_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{12, 1, "rdoq_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{13, 1, "ingressq_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{14, 1, "info_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{15, 1, "cmd_info_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{16, 1, "sideband_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{17, 1, "p_cmd_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{18, 1, "np_cmd_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{19, 1, "amo_info_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{20, 1, "addr_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{21, 1, "rd_buf_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{22, 1, "ack_rd_buf_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{23, 1, "hni_flit_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{24, 1, "rpu_list_mem_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{25, 1, "rpu_st_mem_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{26, 1, "rarb_hdr_bus_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{27, 1, "rarb_data_bus_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{28, 1, "pbuf_flit_mem_cor", C_EC_COR,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870500, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{33, 1, "flop_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{34, 1, "put_resp_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{35, 1, "get_req_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{36, 1, "rdfq_list_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{37, 1, "wr_md_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{38, 1, "event_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{39, 1, "wr_ev_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{40, 1, "pkt_flit_fifo_ucor", C_EC_TRNSNT_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{41, 1, "pbuf_list_mem_ucor", C_EC_TRNSNT_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{42, 1, "pbuf_sb_mem_ucor", C_EC_TRNSNT_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{43, 1, "atu_resp_ucor", C_EC_TRNSNT_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{44, 1, "rdoq_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{45, 1, "ingressq_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{46, 1, "info_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{47, 1, "cmd_info_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{48, 1, "sideband_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{49, 1, "p_cmd_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{50, 1, "np_cmd_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{51, 1, "amo_info_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{52, 1, "addr_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{53, 1, "rd_buf_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{54, 1, "ack_rd_buf_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{55, 1, "hni_flit_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{56, 1, "rpu_list_mem_ucor", C_EC_CRIT,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{57, 1, "rpu_st_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{58, 1, "rarb_hdr_bus_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{59, 1, "rarb_data_bus_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{60, 1, "pbuf_flit_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_IXE_ERR_INFO_MEM, C_IXE_ERR_INFO_MEM_SIZE, "C_IXE_ERR_INFO_MEM"},
+	  },
+	 {{0x9870508, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{64, 1}
+};
+
+static const struct flg_err_info c2_lpe_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "crnc_ring_sync_error", C_EC_UNCOR_NS},
+	{2, 1, "crnc_ring_ecc_sbe", C_EC_COR},
+	{3, 1, "crnc_ring_ecc_mbe", C_EC_UNCOR_NS},
+	{4, 1, "crnc_ring_cmd_unknown", C_EC_UNCOR_NS},
+	{5, 1, "crnc_csr_cmd_unknown", C_EC_UNCOR_NS},
+	{6, 1, "crnc_csr_cmd_incomplete", C_EC_UNCOR_NS},
+	{7, 1, "crnc_buf_ecc_sbe", C_EC_COR},
+	{8, 1, "crnc_buf_ecc_mbe", C_EC_UNCOR_NS},
+	{9, 1, "event_cnt_ovf", C_EC_INFO},
+	{10, 1, "le_oversubscribed", C_EC_BADCON_NS},
+	{12, 1, "illegal_op", C_EC_BADCON_NS,
+	 {{C_LPE_ERR_INFO_NET_HDR, C_LPE_ERR_INFO_NET_HDR_SIZE,
+	   "C_LPE_ERR_INFO_NET_HDR"},
+	  },
+	 {},
+	 },
+	{13, 1, "src_error", C_EC_BADCON_NS,
+	 {{C_LPE_ERR_INFO_NET_HDR, C_LPE_ERR_INFO_NET_HDR_SIZE,
+	   "C_LPE_ERR_INFO_NET_HDR"},
+	  },
+	 {},
+	 },
+	{14, 1, "delayed", C_EC_BADCON_NS,
+	 {{C_LPE_ERR_INFO_NET_HDR, C_LPE_ERR_INFO_NET_HDR_SIZE,
+	   "C_LPE_ERR_INFO_NET_HDR"},
+	  },
+	 {},
+	 },
+	{15, 1, "restricted_unicast", C_EC_BADCON_NS,
+	 {{C_LPE_ERR_INFO_NET_HDR, C_LPE_ERR_INFO_NET_HDR_SIZE,
+	   "C_LPE_ERR_INFO_NET_HDR"},
+	  },
+	 {},
+	 },
+	{16, 1, "no_space", C_EC_BADCON_NS,
+	 {{C_LPE_ERR_INFO_NET_HDR, C_LPE_ERR_INFO_NET_HDR_SIZE,
+	   "C_LPE_ERR_INFO_NET_HDR"},
+	  },
+	 {},
+	 },
+	{17, 1, "invalid_endpoint", C_EC_BADCON_NS,
+	 {{C_LPE_ERR_INFO_NET_HDR, C_LPE_ERR_INFO_NET_HDR_SIZE,
+	   "C_LPE_ERR_INFO_NET_HDR"},
+	  },
+	 {},
+	 },
+	{18, 1, "entry_not_found", C_EC_BADCON_NS,
+	 {{C_LPE_ERR_INFO_NET_HDR, C_LPE_ERR_INFO_NET_HDR_SIZE,
+	   "C_LPE_ERR_INFO_NET_HDR"},
+	  },
+	 {},
+	 },
+	{19, 1, "op_violation", C_EC_BADCON_NS,
+	 {{C_LPE_ERR_INFO_NET_HDR, C_LPE_ERR_INFO_NET_HDR_SIZE,
+	   "C_LPE_ERR_INFO_NET_HDR"},
+	  },
+	 {},
+	 },
+	{20, 1, "eq_disabled", C_EC_BADCON_NS,
+	 {{C_LPE_ERR_INFO_NET_HDR, C_LPE_ERR_INFO_NET_HDR_SIZE,
+	   "C_LPE_ERR_INFO_NET_HDR"},
+	  },
+	 {},
+	 },
+	{21, 1, "pt_disabled_fc", C_EC_BADCON_NS,
+	 {{C_LPE_ERR_INFO_NET_HDR, C_LPE_ERR_INFO_NET_HDR_SIZE,
+	   "C_LPE_ERR_INFO_NET_HDR"},
+	  },
+	 {},
+	 },
+	{22, 1, "pt_disabled_dis", C_EC_BADCON_NS,
+	 {{C_LPE_ERR_INFO_NET_HDR, C_LPE_ERR_INFO_NET_HDR_SIZE,
+	   "C_LPE_ERR_INFO_NET_HDR"},
+	  },
+	 {},
+	 },
+	{23, 1, "pt_disabled_rst", C_EC_BADCON_NS,
+	 {{C_LPE_ERR_INFO_NET_HDR, C_LPE_ERR_INFO_NET_HDR_SIZE,
+	   "C_LPE_ERR_INFO_NET_HDR"},
+	  },
+	 {},
+	 },
+	{24, 1, "illegal_cq_op", C_EC_BADCON_NS},
+	{25, 1, "fifo_err", C_EC_UNCOR_NS},
+	{26, 1, "cq_fifo_overrun", C_EC_UNCOR_NS},
+	{27, 1, "cdt_cnt_uflow", C_EC_UNCOR_NS,
+	 {{C_LPE_ERR_INFO_CDT_CNT_UFLOW, C_LPE_ERR_INFO_CDT_CNT_UFLOW_SIZE,
+	   "C_LPE_ERR_INFO_CDT_CNT_UFLOW"},
+	  },
+	 {},
+	 },
+	{28, 1, "mrr_mem_cor", C_EC_COR,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{29, 1, "free_list_mem_cor", C_EC_COR,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{30, 1, "event_ram_cor", C_EC_COR,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{31, 1, "plec_mem_cor", C_EC_COR,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{32, 1, "ptlte_mem_cor", C_EC_COR,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{33, 1, "ixemrq_front_mem_cor", C_EC_COR,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{34, 1, "ixemrq_back_mem_cor", C_EC_COR,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{35, 1, "ixemrq_list_mem_cor", C_EC_COR,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{36, 1, "petcq_list_mem_cor", C_EC_COR,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{37, 1, "list_entry_mem_cor", C_EC_COR,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{38, 1, "cqmrq_front_mem_cor", C_EC_COR,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{39, 1, "cqmrq_back_mem_cor", C_EC_COR,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{40, 1, "cqmrq_list_mem_cor", C_EC_COR,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{41, 1, "rget_ram_mem_cor", C_EC_COR,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{42, 1, "rrq_fifo_cor", C_EC_COR,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{43, 1, "cq_fifo_cor", C_EC_COR,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{45, 1, "rdy_pleq_cor", C_EC_COR,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{46, 1, "mrr_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{47, 1, "free_list_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{48, 1, "event_ram_ucor", C_EC_UNCOR_NS,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{49, 1, "plec_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{50, 1, "ptlte_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{51, 1, "ixemrq_front_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{52, 1, "ixemrq_back_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{53, 1, "ixemrq_list_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{54, 1, "petcq_list_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{55, 1, "list_entry_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{56, 1, "cqmrq_front_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{57, 1, "cqmrq_back_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{58, 1, "cqmrq_list_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{59, 1, "rget_ram_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{60, 1, "rrq_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{61, 1, "cq_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{63, 1, "rdy_pleq_ucor", C_EC_UNCOR_NS,
+	 {{C_LPE_ERR_INFO_MEM, C_LPE_ERR_INFO_MEM_SIZE, "C_LPE_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{64, 1}
+};
+
+static const struct flg_err_info c2_mb_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "crnc_ring_sync_error", C_EC_UNCOR_NS},
+	{2, 1, "crnc_ring_ecc_sbe", C_EC_COR},
+	{3, 1, "crnc_ring_ecc_mbe", C_EC_UNCOR_NS},
+	{4, 1, "crnc_ring_cmd_unknown", C_EC_UNCOR_NS},
+	{5, 1, "crnc_csr_cmd_unknown", C_EC_UNCOR_NS},
+	{6, 1, "crnc_csr_cmd_incomplete", C_EC_UNCOR_NS},
+	{7, 1, "crnc_buf_ecc_sbe", C_EC_COR},
+	{8, 1, "crnc_buf_ecc_mbe", C_EC_UNCOR_NS},
+	{16, 1, "crmc_ring_sync_error", C_EC_UNCOR_NS,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{17, 1, "crmc_ring_ecc_sbe", C_EC_COR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{18, 1, "crmc_ring_ecc_mbe", C_EC_UNCOR_NS,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{19, 1, "crmc_ring_cmd_unknown", C_EC_UNCOR_NS,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{20, 1, "crmc_wr_error", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{21, 1, "crmc_wr_addr_invalid", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{22, 1, "crmc_wr_cmd_invalid", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{23, 1, "crmc_wr_be_invalid", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{24, 1, "crmc_wr_cor_error", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{25, 1, "crmc_wr_uncor_error", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{26, 1, "crmc_wr_burst_error", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{27, 1, "crmc_wr_mcast_nack", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{28, 1, "crmc_wr_rsvd_error", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{29, 1, "crmc_wr_wrapped", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{30, 1, "crmc_wr_timeout", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{31, 1, "crmc_wr_axi_req_error", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{32, 1, "crmc_wr_axi_ring_error", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{33, 1, "crmc_wr_axi_wstrb_error", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{34, 1, "crmc_wr_axi_parity_error", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{35, 1, "crmc_rd_error", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{36, 1, "crmc_rd_addr_invalid", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{37, 1, "crmc_rd_cmd_invalid", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{38, 1, "crmc_rd_be_invalid", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{39, 1, "crmc_rd_cor_error", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{40, 1, "crmc_rd_uncor_error", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{41, 1, "crmc_rd_burst_error", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{42, 1, "crmc_rd_mcast_nack", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{43, 1, "crmc_rd_rsvd_error", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{44, 1, "crmc_rd_wrapped", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{45, 1, "crmc_rd_timeout", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{46, 1, "crmc_rd_axi_req_error", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CRMC, C_MB_ERR_INFO_CRMC_SIZE, "C_MB_ERR_INFO_CRMC"},
+	  },
+	 {},
+	 },
+	{47, 1, "crmc_rd_axi_ring_error", C_EC_SFTWR},
+	{48, 4, "cmc_wr_error", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CMC_WR, C_MB_ERR_INFO_CMC_WR_SIZE,
+	   "C_MB_ERR_INFO_CMC_WR"},
+	  },
+	 {},
+	 },
+	{52, 4, "cmc_rd_error", C_EC_SFTWR,
+	 {{C_MB_ERR_INFO_CMC_RD, C_MB_ERR_INFO_CMC_RD_SIZE,
+	   "C_MB_ERR_INFO_CMC_RD"},
+	  },
+	 {},
+	 },
+	{56, 1, "event_cnt_ovf", C_EC_INFO},
+	{57, 1, "event_ram_cor", C_EC_COR,
+	 {{C_MB_ERR_INFO_MEM, C_MB_ERR_INFO_MEM_SIZE, "C_MB_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{58, 1, "event_ram_ucor", C_EC_UNCOR_NS,
+	 {{C_MB_ERR_INFO_MEM, C_MB_ERR_INFO_MEM_SIZE, "C_MB_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{59, 1, "flash_cache0_cor", C_EC_COR,
+	 {{C_MB_ERR_INFO_MEM, C_MB_ERR_INFO_MEM_SIZE, "C_MB_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{60, 1, "flash_cache0_ucor", C_EC_UNCOR_NS,
+	 {{C_MB_ERR_INFO_MEM, C_MB_ERR_INFO_MEM_SIZE, "C_MB_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{61, 1, "flash_cache1_cor", C_EC_COR,
+	 {{C_MB_ERR_INFO_MEM, C_MB_ERR_INFO_MEM_SIZE, "C_MB_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{62, 1, "flash_cache1_ucor", C_EC_UNCOR_NS,
+	 {{C_MB_ERR_INFO_MEM, C_MB_ERR_INFO_MEM_SIZE, "C_MB_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{63, 1, "spi_ecc_error", C_EC_UNCOR_NS,
+	 {{C_MB_ERR_INFO_SPI, C_MB_ERR_INFO_SPI_SIZE, "C_MB_ERR_INFO_SPI"},
+	  },
+	 {},
+	 },
+	{64, 1}
+};
+
+static const struct flg_err_info c2_mb_ext_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "jai_axi_cadr_unexpected_cmd", C_EC_SFTWR},
+	{2, 1, "jai_axi_cadr_unknown_cmd", C_EC_SFTWR},
+	{3, 1, "jai_axi_wr_decerr", C_EC_SFTWR},
+	{4, 1, "jai_axi_wr_slverr", C_EC_SFTWR},
+	{5, 1, "jai_axi_rd_decerr", C_EC_SFTWR},
+	{6, 1, "jai_axi_rd_slverr", C_EC_SFTWR},
+	{7, 1, "jai_axi_rd_parity_error", C_EC_SFTWR},
+	{8, 1, "flm_csr_init_p1_spi_err", C_EC_CRIT},
+	{9, 1, "flm_csr_init_p2_spi_err", C_EC_CRIT},
+	{10, 1, "flm_csr_init_p1_fail", C_EC_CRIT},
+	{11, 1, "flm_csr_init_p2_fail", C_EC_CRIT},
+	{12, 1, "flm_csr_init_p1_abort", C_EC_CRIT},
+	{13, 1, "flm_csr_init_p2_abort", C_EC_CRIT},
+	{14, 1, "flm_csr_init_p1_len_err", C_EC_CRIT},
+	{15, 1, "flm_csr_init_p2_len_err", C_EC_CRIT},
+	{16, 1, "flm_csr_init_p1_cont_err", C_EC_CRIT},
+	{17, 1, "flm_csr_init_p2_cont_err", C_EC_CRIT},
+	{18, 1, "flm_csr_init_p1_axi_decerr", C_EC_CRIT},
+	{19, 1, "flm_csr_init_p2_axi_decerr", C_EC_CRIT},
+	{20, 1, "flm_csr_init_p1_axi_slverr", C_EC_CRIT},
+	{21, 1, "flm_csr_init_p2_axi_slverr", C_EC_CRIT},
+	{22, 1, "flm_serdes_rom_load_spi_err", C_EC_CRIT},
+	{23, 1, "flm_serdes_rom_load_error", C_EC_CRIT},
+	{24, 1, "flm_serdes_rom_load_abort", C_EC_CRIT},
+	{25, 1, "flm_serdes_rom_load_fail", C_EC_CRIT},
+	{26, 1, "flm_hg_spi_error", C_EC_CRIT},
+	{27, 1, "flm_hg_addr_error", C_EC_CRIT},
+	{28, 1, "flm_sbus_wr_error", C_EC_CRIT},
+	{29, 1, "flm_sbus_rd_error", C_EC_CRIT},
+	{64, 1}
+};
+
+static const struct flg_err_info c2_mst_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "crnc_ring_sync_error", C_EC_UNCOR_NS},
+	{2, 1, "crnc_ring_ecc_sbe", C_EC_COR},
+	{3, 1, "crnc_ring_ecc_mbe", C_EC_UNCOR_NS},
+	{4, 1, "crnc_ring_cmd_unknown", C_EC_UNCOR_NS},
+	{5, 1, "crnc_csr_cmd_unknown", C_EC_UNCOR_NS},
+	{6, 1, "crnc_csr_cmd_incomplete", C_EC_UNCOR_NS},
+	{7, 1, "crnc_buf_ecc_sbe", C_EC_COR},
+	{8, 1, "crnc_buf_ecc_mbe", C_EC_UNCOR_NS},
+	{32, 1, "lnk_list_ptrs_cor", C_EC_COR,
+	 {{C_MST_ERR_INFO_MEM, C_MST_ERR_INFO_MEM_SIZE, "C_MST_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{33, 1, "lnk_list_ptrs_ucor", C_EC_CRIT,
+	 {{C_MST_ERR_INFO_MEM, C_MST_ERR_INFO_MEM_SIZE, "C_MST_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{36, 1, "req_fifo_unrun", C_EC_CRIT},
+	{37, 1, "req_fifo_ovrun", C_EC_CRIT},
+	{38, 1, "req_fifo_crdt_unflw", C_EC_CRIT},
+	{44, 1, "match_crdt_unflw_get", C_EC_CRIT},
+	{45, 1, "match_crdt_unflw_put", C_EC_CRIT},
+	{46, 1, "evnt_fifo_cor", C_EC_COR,
+	 {{C_MST_ERR_INFO_MEM, C_MST_ERR_INFO_MEM_SIZE, "C_MST_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{47, 1, "evnt_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C_MST_ERR_INFO_MEM, C_MST_ERR_INFO_MEM_SIZE, "C_MST_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{48, 1, "evnt_fifo_unrun", C_EC_CRIT},
+	{49, 1, "evnt_fifo_ovrun", C_EC_CRIT},
+	{50, 1, "ee_crdt_unflw", C_EC_CRIT},
+	{51, 1, "req_fifo_cor", C_EC_COR,
+	 {{C_MST_ERR_INFO_MEM, C_MST_ERR_INFO_MEM_SIZE, "C_MST_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{52, 1, "req_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C_MST_ERR_INFO_MEM, C_MST_ERR_INFO_MEM_SIZE, "C_MST_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{53, 1, "mst_table_cor", C_EC_COR,
+	 {{C_MST_ERR_INFO_MEM, C_MST_ERR_INFO_MEM_SIZE, "C_MST_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{54, 1, "mst_table_ucor", C_EC_UNCOR_NS,
+	 {{C_MST_ERR_INFO_MEM, C_MST_ERR_INFO_MEM_SIZE, "C_MST_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{55, 1, "ll_data_ram_cor", C_EC_COR,
+	 {{C_MST_ERR_INFO_MEM, C_MST_ERR_INFO_MEM_SIZE, "C_MST_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{56, 1, "ll_data_ram_ucor", C_EC_UNCOR_NS,
+	 {{C_MST_ERR_INFO_MEM, C_MST_ERR_INFO_MEM_SIZE, "C_MST_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{64, 1}
+};
+
+static const struct flg_err_info c2_oxe_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "crnc_ring_sync_error", C_EC_UNCOR_NS},
+	{2, 1, "crnc_ring_ecc_sbe", C_EC_COR},
+	{3, 1, "crnc_ring_ecc_mbe", C_EC_UNCOR_NS},
+	{4, 1, "crnc_ring_cmd_unknown", C_EC_UNCOR_NS},
+	{5, 1, "crnc_csr_cmd_unknown", C_EC_UNCOR_NS},
+	{6, 1, "crnc_csr_cmd_incomplete", C_EC_UNCOR_NS},
+	{7, 1, "crnc_buf_ecc_sbe", C_EC_COR},
+	{8, 1, "crnc_buf_ecc_mbe", C_EC_UNCOR_NS},
+	{14, 1, "spt_cdt_err", C_EC_CRIT,
+	 {{C2_OXE_ERR_INFO_SPT_CDT_ERR, C2_OXE_ERR_INFO_SPT_CDT_ERR_SIZE,
+	   "C2_OXE_ERR_INFO_SPT_CDT_ERR"},
+	  },
+	 {{0x1002A48, "spt_cdt_errs", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{15, 1, "smt_cdt_err", C_EC_CRIT,
+	 {{C2_OXE_ERR_INFO_SMT_CDT_ERR, C2_OXE_ERR_INFO_SMT_CDT_ERR_SIZE,
+	   "C2_OXE_ERR_INFO_SMT_CDT_ERR"},
+	  },
+	 {{0x1002A50, "smt_cdt_errs", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{16, 1, "cells_mem_cor", C_EC_COR,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002788, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{17, 1, "pkl_mem_cor", C_EC_COR,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002788, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{18, 1, "pct_sb_mcu_mem_cor", C_EC_COR,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002788, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{19, 1, "pct_sb_sct_mem_cor", C_EC_COR,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002788, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{20, 1, "dmu_mem_cor", C_EC_COR,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002788, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{21, 1, "rec_mem_cor", C_EC_COR,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002788, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{22, 1, "atreq_mem_cor", C_EC_COR,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002788, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{23, 1, "atrsp_mem_cor", C_EC_COR,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002788, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{24, 1, "tso_flit_cor", C_EC_COR,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002788, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{25, 1, "sb_fifo_cor", C_EC_COR,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002788, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{26, 1, "rarb_hdr_cor", C_EC_COR,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002788, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{27, 1, "rarb_data_cor", C_EC_COR,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002788, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{28, 1, "at_resp_bus_cor", C_EC_COR,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002788, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{29, 1, "ixe_cmd_cor", C_EC_COR,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002788, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{30, 1, "lpe_cmd_cor", C_EC_COR,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002788, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{31, 1, "tou_cmd_cor", C_EC_COR,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002788, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{32, 1, "cq_cmd_cor", C_EC_COR,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002788, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{33, 1, "cells_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002790, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{34, 1, "pkl_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002790, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{35, 1, "pct_sb_mcu_mem_ucor", C_EC_CRIT,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002790, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{36, 1, "pct_sb_sct_mem_ucor", C_EC_CRIT,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002790, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{37, 1, "dmu_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002790, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{38, 1, "rec_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002790, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{39, 1, "atreq_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002790, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{40, 1, "atrsp_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002790, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{41, 1, "tso_flit_ucor", C_EC_UNCOR_NS,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002790, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{42, 1, "sb_fifo_ucor", C_EC_CRIT,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002790, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{43, 1, "rarb_hdr_ucor", C_EC_UNCOR_NS,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  {C_OXE_ERR_INFO_RARB, C_OXE_ERR_INFO_RARB_SIZE,
+	   "C_OXE_ERR_INFO_RARB"},
+	  },
+	 {{0x1002790, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{44, 1, "rarb_data_ucor", C_EC_UNCOR_NS,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  {C_OXE_ERR_INFO_RARB, C_OXE_ERR_INFO_RARB_SIZE,
+	   "C_OXE_ERR_INFO_RARB"},
+	  },
+	 {{0x1002790, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{45, 1, "at_resp_bus_ucor", C_EC_UNCOR_NS,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002790, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{46, 1, "ixe_cmd_ucor", C_EC_CRIT,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002790, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{47, 1, "lpe_cmd_ucor", C_EC_CRIT,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002790, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{48, 1, "tou_cmd_ucor", C_EC_CRIT,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002790, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{49, 1, "cq_cmd_ucor", C_EC_CRIT,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002790, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{50, 1, "fifo_err", C_EC_UNCOR_NS,
+	 {{C_OXE_ERR_INFO_FIFO_ERR, C_OXE_ERR_INFO_FIFO_ERR_SIZE,
+	   "C_OXE_ERR_INFO_FIFO_ERR"},
+	  },
+	 {},
+	 },
+	{51, 1, "credit_uflw", C_EC_UNCOR_NS,
+	 {{C_OXE_ERR_INFO_CC, C_OXE_ERR_INFO_CC_SIZE, "C_OXE_ERR_INFO_CC"},
+	  },
+	 {},
+	 },
+	{52, 1, "spt_ignore_err", C_EC_BADCON_NS,
+	 {{C_OXE_ERR_INFO_IGNORE_ERR, C_OXE_ERR_INFO_IGNORE_ERR_SIZE,
+	   "C_OXE_ERR_INFO_IGNORE_ERR"},
+	  },
+	 {{0x1002A60, "ignore_errs", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{53, 1, "smt_ignore_err", C_EC_BADCON_NS,
+	 {{C_OXE_ERR_INFO_IGNORE_ERR, C_OXE_ERR_INFO_IGNORE_ERR_SIZE,
+	   "C_OXE_ERR_INFO_IGNORE_ERR"},
+	  },
+	 {{0x1002A60, "ignore_errs", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{54, 1, "sct_ignore_err", C_EC_BADCON_NS,
+	 {{C_OXE_ERR_INFO_IGNORE_ERR, C_OXE_ERR_INFO_IGNORE_ERR_SIZE,
+	   "C_OXE_ERR_INFO_IGNORE_ERR"},
+	  },
+	 {{0x1002A60, "ignore_errs", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{55, 1, "srb_ignore_err", C_EC_BADCON_NS,
+	 {{C_OXE_ERR_INFO_IGNORE_ERR, C_OXE_ERR_INFO_IGNORE_ERR_SIZE,
+	   "C_OXE_ERR_INFO_IGNORE_ERR"},
+	  },
+	 {{0x1002A60, "ignore_errs", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{56, 1, "cmd_unexpected", C_EC_UNCOR_NS,
+	 {{C_OXE_ERR_INFO_UNEXPCTD, C_OXE_ERR_INFO_UNEXPCTD_SIZE,
+	   "C_OXE_ERR_INFO_UNEXPCTD"},
+	  },
+	 {},
+	 },
+	{57, 1, "rarb_hw_err", C_EC_UNCOR_NS,
+	 {{C_OXE_ERR_INFO_RARB, C_OXE_ERR_INFO_RARB_SIZE,
+	   "C_OXE_ERR_INFO_RARB"},
+	  },
+	 {},
+	 },
+	{58, 1, "pcie_unsuccess_cmpl", C_EC_UNCOR_NS,
+	 {{C_OXE_ERR_INFO_PCIE_UC, C_OXE_ERR_INFO_PCIE_UC_SIZE,
+	   "C_OXE_ERR_INFO_PCIE_UC"},
+	  },
+	 {},
+	 },
+	{59, 1, "pcie_error_poisoned", C_EC_UNCOR_NS,
+	 {{C_OXE_ERR_INFO_PCIE_EP, C_OXE_ERR_INFO_PCIE_EP_SIZE,
+	   "C_OXE_ERR_INFO_PCIE_EP"},
+	  },
+	 {},
+	 },
+	{60, 1, "at_overrun_err", C_EC_UNCOR_NS},
+	{61, 1, "mdr_pipe_ucor", C_EC_UNCOR_NS,
+	 {{C_OXE_ERR_INFO_MEM, C_OXE_ERR_INFO_MEM_SIZE, "C_OXE_ERR_INFO_MEM"},
+	  },
+	 {{0x1002790, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{62, 1, "cell_xlate_parity_err", C_EC_UNCOR_NS,
+	 {{C_OXE_ERR_INFO_CELL_XLATE, C_OXE_ERR_INFO_CELL_XLATE_SIZE,
+	   "C_OXE_ERR_INFO_CELL_XLATE"},
+	  },
+	 {},
+	 },
+	{64, 1}
+};
+
+static const struct flg_err_info c2_parbs_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "crnc_ring_sync_error", C_EC_UNCOR_NS},
+	{2, 1, "crnc_ring_ecc_sbe", C_EC_COR},
+	{3, 1, "crnc_ring_ecc_mbe", C_EC_UNCOR_NS},
+	{4, 1, "crnc_ring_cmd_unknown", C_EC_UNCOR_NS},
+	{5, 1, "crnc_csr_cmd_unknown", C_EC_UNCOR_NS},
+	{6, 1, "crnc_csr_cmd_incomplete", C_EC_UNCOR_NS},
+	{7, 1, "crnc_buf_ecc_sbe", C_EC_COR},
+	{8, 1, "crnc_buf_ecc_mbe", C_EC_UNCOR_NS},
+	{16, 1, "cq_tarb_hdr_cor", C_EC_COR,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{17, 1, "cq_tarb_hdr_ucor", C_EC_UNCOR_NS,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{18, 1, "cq_tarb_data_cor", C_EC_COR,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{19, 1, "cq_tarb_data_ucor", C_EC_UNCOR_NS,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{20, 1, "ee_tarb_hdr_cor", C_EC_COR,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{21, 1, "ee_tarb_hdr_ucor", C_EC_UNCOR_NS,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{22, 1, "ee_tarb_data_cor", C_EC_COR,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{23, 1, "ee_tarb_data_ucor", C_EC_UNCOR_NS,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{24, 1, "ixe_tarb_hdr_cor", C_EC_COR,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{25, 1, "ixe_tarb_hdr_ucor", C_EC_UNCOR_NS,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{26, 1, "ixe_tarb_data_cor", C_EC_COR,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{27, 1, "ixe_tarb_data_ucor", C_EC_UNCOR_NS,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{28, 1, "oxe_tarb_hdr_cor", C_EC_COR,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{29, 1, "oxe_tarb_hdr_ucor", C_EC_UNCOR_NS,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{30, 1, "atu_tarb_hdr_cor", C_EC_COR,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{31, 1, "atu_tarb_hdr_ucor", C_EC_UNCOR_NS,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{32, 1, "atu_tarb_data_cor", C_EC_COR,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{33, 1, "atu_tarb_data_ucor", C_EC_UNCOR_NS,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{34, 1, "tarb_pi_hdr_cor", C_EC_COR,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{35, 1, "tarb_pi_hdr_ucor", C_EC_UNCOR_NS,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{36, 1, "tarb_pi_data_cor", C_EC_COR,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{37, 1, "tarb_pi_data_ucor", C_EC_UNCOR_NS,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{38, 1, "cq_p_fifo_overrun", C_EC_UNCOR_NS},
+	{39, 1, "cq_p_fifo_underrun", C_EC_UNCOR_NS},
+	{40, 1, "cq_np_fifo_overrun", C_EC_UNCOR_NS},
+	{41, 1, "cq_np_fifo_underrun", C_EC_UNCOR_NS},
+	{42, 1, "ee_p_fifo_overrun", C_EC_UNCOR_NS},
+	{43, 1, "ee_p_fifo_underrun", C_EC_UNCOR_NS},
+	{44, 1, "ixe_p_fifo_overrun", C_EC_UNCOR_NS},
+	{45, 1, "ixe_p_fifo_underrun", C_EC_UNCOR_NS},
+	{46, 1, "ixe_np_fifo_overrun", C_EC_UNCOR_NS},
+	{47, 1, "ixe_np_fifo_underrun", C_EC_UNCOR_NS},
+	{48, 1, "oxe_np_fifo_overrun", C_EC_UNCOR_NS},
+	{49, 1, "oxe_np_fifo_underrun", C_EC_UNCOR_NS},
+	{50, 1, "atu_p_fifo_overrun", C_EC_UNCOR_NS},
+	{51, 1, "atu_p_fifo_underrun", C_EC_UNCOR_NS},
+	{52, 1, "atu_np_fifo_overrun", C_EC_UNCOR_NS},
+	{53, 1, "atu_np_fifo_underrun", C_EC_UNCOR_NS},
+	{54, 1, "ord_p_fifo_overrun", C_EC_UNCOR_NS},
+	{55, 1, "ord_p_fifo_underrun", C_EC_UNCOR_NS},
+	{56, 1, "ord_np_fifo_overrun", C_EC_UNCOR_NS},
+	{57, 1, "ord_np_fifo_underrun", C_EC_UNCOR_NS},
+	{58, 1, "ord_np_cnt_overrun", C_EC_UNCOR_NS},
+	{59, 1, "ord_np_cnt_underrun", C_EC_UNCOR_NS},
+	{60, 1, "tarb_pi_p_cdt_underflow", C_EC_UNCOR_NS},
+	{61, 1, "tarb_pi_np_cdt_underflow", C_EC_UNCOR_NS},
+	{64, 1}
+};
+
+static const struct flg_err_info c2_parbs_ext_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "pi_rarb_hdr_cor", C_EC_COR,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{2, 1, "pi_rarb_hdr_ucor", C_EC_UNCOR_NS,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{3, 1, "pi_rarb_data_cor", C_EC_COR,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{4, 1, "pi_rarb_data_ucor", C_EC_UNCOR_NS,
+	 {{C_PARBS_ERR_INFO_MEM, C_PARBS_ERR_INFO_MEM_SIZE,
+	   "C_PARBS_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{64, 1}
+};
+
+static const struct flg_err_info c2_pct_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "crnc_ring_sync_error", C_EC_UNCOR_NS},
+	{2, 1, "crnc_ring_ecc_sbe", C_EC_COR},
+	{3, 1, "crnc_ring_ecc_mbe", C_EC_UNCOR_NS},
+	{4, 1, "crnc_ring_cmd_unknown", C_EC_UNCOR_NS},
+	{5, 1, "crnc_csr_cmd_unknown", C_EC_UNCOR_NS},
+	{6, 1, "crnc_csr_cmd_incomplete", C_EC_UNCOR_NS},
+	{7, 1, "crnc_buf_ecc_sbe", C_EC_COR},
+	{8, 1, "crnc_buf_ecc_mbe", C_EC_UNCOR_NS},
+	{9, 1, "srb_alloc_dup", C_EC_UNCOR_NS},
+	{10, 1, "srb_dealloc_dup", C_EC_UNCOR_NS},
+	{12, 1, "flop_fifo_cor", C_EC_COR,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100600, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{13, 1, "mst_cam_free_cor", C_EC_COR,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100600, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{14, 1, "sct_cam_free_cor", C_EC_COR,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100600, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{15, 1, "tct_cam_free_cor", C_EC_COR,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100600, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{16, 1, "trs_cam_free_cor", C_EC_COR,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100600, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{17, 1, "sct_tbl_cor", C_EC_COR,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100600, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{18, 1, "smt_tbl_cor", C_EC_COR,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100600, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{19, 1, "spt_tbl_cor", C_EC_COR,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100600, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{20, 1, "tct_tbl_cor", C_EC_COR,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100600, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{21, 1, "trs_tbl_cor", C_EC_COR,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100600, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{22, 1, "req_redo_cor", C_EC_COR,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100600, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{23, 1, "cls_clr_req_gen_cor", C_EC_COR,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100600, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{24, 1, "srb_nlist_ram_cor", C_EC_COR,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100600, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{25, 1, "srb_data_ram_cor", C_EC_COR,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100600, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{26, 1, "cls_rsp_gen_cor", C_EC_COR,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100600, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{27, 1, "nack_trs_rsp_gen_cor", C_EC_COR,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100600, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{28, 1, "flop_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100608, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{29, 1, "mst_cam_free_ucor", C_EC_UNCOR_NS,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100608, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{30, 1, "sct_cam_free_ucor", C_EC_UNCOR_NS,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100608, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{31, 1, "tct_cam_free_ucor", C_EC_UNCOR_NS,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100608, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{32, 1, "trs_cam_free_ucor", C_EC_UNCOR_NS,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100608, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{33, 1, "sct_tbl_ucor", C_EC_UNCOR_NS,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100608, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{34, 1, "smt_tbl_ucor", C_EC_UNCOR_NS,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100608, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{35, 1, "spt_tbl_ucor", C_EC_UNCOR_NS,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100608, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{36, 1, "tct_tbl_ucor", C_EC_UNCOR_NS,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100608, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{37, 1, "trs_tbl_ucor", C_EC_UNCOR_NS,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100608, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{38, 1, "req_redo_ucor", C_EC_UNCOR_NS,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100608, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{39, 1, "cls_clr_req_gen_ucor", C_EC_UNCOR_NS,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100608, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{40, 1, "srb_nlist_ram_ucor", C_EC_UNCOR_NS,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100608, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{41, 1, "srb_data_ram_ucor", C_EC_UNCOR_NS,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100608, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{42, 1, "mst_cam_ucor", C_EC_UNCOR_NS,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100608, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{43, 1, "sct_cam_ucor", C_EC_UNCOR_NS,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100608, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{44, 1, "tct_cam_ucor", C_EC_UNCOR_NS,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100608, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{45, 1, "trs_cam_ucor", C_EC_UNCOR_NS,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100608, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{46, 1, "nack_trs_rsp_gen_ucor", C_EC_UNCOR_NS,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100608, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{47, 1, "cls_rsp_gen_ucor", C_EC_UNCOR_NS,
+	 {{C_PCT_ERR_INFO_MEM, C_PCT_ERR_INFO_MEM_SIZE, "C_PCT_ERR_INFO_MEM"},
+	  },
+	 {{0x100608, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{48, 1, "fifo_err", C_EC_UNCOR_NS,
+	 {{C_PCT_ERR_INFO_FIFO, C_PCT_ERR_INFO_FIFO_SIZE,
+	   "C_PCT_ERR_INFO_FIFO"},
+	  },
+	 {},
+	 },
+	{49, 1, "credit_uflw", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_CC, C_PCT_ERR_INFO_CC_SIZE, "C_PCT_ERR_INFO_CC"},
+	  },
+	 {},
+	 },
+	{64, 1}
+};
+
+static const struct flg_err_info c2_pct_ext_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "sct_tbl_dealloc", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{2, 1, "sct_tbl_alloc", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{3, 1, "sct_tbl_rd_misc_unused", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{4, 1, "sct_tbl_wr_misc_unused", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{5, 1, "sct_tbl_rd_ram_unused", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{6, 1, "sct_tbl_wr_ram_unused", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{7, 1, "smt_tbl_dealloc", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{8, 1, "smt_tbl_alloc", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{9, 1, "smt_tbl_rd_ram_unused", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{10, 1, "smt_tbl_wr_ram_unused", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{11, 1, "spt_tbl_dealloc", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{12, 1, "spt_tbl_alloc", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{13, 1, "spt_tbl_rd_misc_unused", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{14, 1, "spt_tbl_wr_misc_unused", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{15, 1, "spt_tbl_rd_ram_unused", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{16, 1, "spt_tbl_wr_ram_unused", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{17, 1, "spt_tbl_set_wrong_status", C_EC_CRIT},
+	{18, 1, "tct_tbl_dealloc", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{19, 1, "tct_tbl_alloc", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{20, 1, "tct_tbl_rd_misc_unused", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{21, 1, "tct_tbl_rd_ram_unused", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{22, 1, "tct_tbl_wr_ram_unused", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{23, 1, "trs_tbl_dealloc", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{24, 1, "trs_tbl_alloc", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{25, 1, "trs_tbl_rd_ram_unused", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{26, 1, "trs_tbl_wr_ram_unused", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{27, 1, "oxe_sct_miss_on_mid", C_EC_CRIT},
+	{28, 1, "oxe_failed_sct_alloc", C_EC_CRIT},
+	{29, 1, "oxe_illegal_req", C_EC_CRIT},
+	{30, 1, "oxe_new_conn_not_som", C_EC_CRIT},
+	{31, 1, "oxe_invalid_smt_not_som", C_EC_CRIT},
+	{32, 1, "oxe_illegal_access2_fsm", C_EC_CRIT},
+	{33, 1, "oxe_smt_req_cnt_exceed", C_EC_CRIT},
+	{34, 1, "oxe_sct_req_cnt_exceed", C_EC_CRIT},
+	{35, 1, "ixe_req_tct_not_in_use", C_EC_CRIT},
+	{36, 1, "ixe_req_tct_miss_unordered_mid", C_EC_INFO},
+	{37, 1, "ixe_req_mst_missing", C_EC_INFO},
+	{38, 1, "ixe_req_clr_out_of_range", C_EC_CRIT},
+	{39, 1, "ixe_rsp_spt_not_in_use", C_EC_CRIT},
+	{40, 1, "ixe_rsp_spt_status_not_pend", C_EC_CRIT},
+	{41, 1, "ixe_rsp_smt_pend_cnt_exceed", C_EC_CRIT},
+	{42, 1, "ixe_rsp_sct_pend_cnt_exceed", C_EC_CRIT},
+	{43, 1, "ixe_rsp_smt_invalid", C_EC_CRIT},
+	{44, 1, "ixe_rsp_spt_not_get_vld", C_EC_CRIT},
+	{45, 1, "ixe_rsp_cls_not_pend", C_EC_CRIT},
+	{46, 1, "ixe_gcomp_spt_not_in_use", C_EC_CRIT},
+	{47, 1, "ixe_gcomp_not_get_ack_rcvd", C_EC_CRIT},
+	{48, 1, "ixe_gcomp_smt_pend_cnt_exceed", C_EC_CRIT},
+	{49, 1, "ixe_gcomp_sct_pend_cnt_exceed", C_EC_CRIT},
+	{50, 1, "ixe_gcomp_smt_invalid", C_EC_CRIT},
+	{51, 1, "ixe_gcomp_spt_not_get_vld", C_EC_CRIT},
+	{52, 1, "src_cls_spt_wrong_sct", C_EC_CRIT},
+	{53, 1, "src_cls_spt_not_used", C_EC_CRIT},
+	{54, 1, "src_cls_spt_not_opcomp", C_EC_CRIT},
+	{55, 1, "src_cls_bad_close", C_EC_CRIT},
+	{56, 1, "pkto_illegal_req", C_EC_CRIT},
+	{57, 1, "pkto_illegal_pkttype", C_EC_CRIT},
+	{58, 1, "pkto_head_fsm", C_EC_CRIT},
+	{59, 1, "srb_wr_rd_same_cycle", C_EC_CRIT},
+	{60, 1, "sct_miss_unrestricted_mid", C_EC_CRIT},
+	{61, 1, "mbe_in_ctrls", C_EC_CRIT,
+	 {{C_PCT_ERR_INFO_EXT, C_PCT_ERR_INFO_EXT_SIZE, "C_PCT_ERR_INFO_EXT"},
+	  },
+	 {},
+	 },
+	{62, 1, "sct_cam_err", C_EC_CRIT},
+	{63, 1, "mst_cam_err", C_EC_CRIT},
+	{64, 1}
+};
+
+static const struct flg_err_info c2_pi_ipd_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "crnc_ring_sync_error", C_EC_UNCOR_NS},
+	{2, 1, "crnc_ring_ecc_sbe", C_EC_COR},
+	{3, 1, "crnc_ring_ecc_mbe", C_EC_UNCOR_NS},
+	{4, 1, "crnc_ring_cmd_unknown", C_EC_UNCOR_NS},
+	{5, 1, "crnc_csr_cmd_unknown", C_EC_UNCOR_NS},
+	{6, 1, "crnc_csr_cmd_incomplete", C_EC_UNCOR_NS},
+	{7, 1, "crnc_buf_ecc_sbe", C_EC_COR},
+	{8, 1, "crnc_buf_ecc_mbe", C_EC_UNCOR_NS},
+	{16, 1, "event_cnt_ovf", C_EC_INFO},
+	{17, 1, "event_ram_cor", C_EC_COR,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{18, 1, "event_ram_ucor", C_EC_UNCOR_NS,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{19, 1, "msix_table_cor", C_EC_COR,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{20, 1, "msix_table_ucor", C_EC_UNCOR_NS,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{21, 1, "msix_pba_cor", C_EC_COR,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{22, 1, "msix_pba_ucor", C_EC_UNCOR_NS,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{23, 4, "pti_tarb_xlat_p_fifo_cor", C_EC_COR,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{27, 4, "pti_tarb_xlat_p_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{31, 3, "pti_tarb_xlat_np_fifo_cor", C_EC_COR,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{34, 3, "pti_tarb_xlat_np_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{37, 1, "pti_tarb_xlat_tbuf_cor", C_EC_COR,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{38, 1, "pti_tarb_xlat_tbuf_ucor", C_EC_UNCOR_NS,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{39, 1, "pti_tarb_xlat_cpl_to_fifo_cor", C_EC_COR,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{40, 1, "pti_tarb_xlat_cpl_to_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{41, 4, "pri_mb_xlat_comp_fifo_cor", C_EC_COR,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{45, 4, "pri_mb_xlat_comp_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{49, 1, "pti_msixc_fifo_cor", C_EC_COR,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{50, 1, "pti_msixc_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{51, 1, "msixc_pti_fifo_cor", C_EC_COR,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{52, 1, "msixc_pti_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{53, 4, "dmac_p_fifo_cor", C_EC_COR,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{57, 4, "dmac_p_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C_PI_IPD_ERR_INFO_MEM, C_PI_IPD_ERR_INFO_MEM_SIZE,
+	   "C_PI_IPD_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{64, 1}
+};
+
+static const struct flg_err_info c2_pi_ipd_ext_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 3, "ip_app_parity_errs", C_EC_CRIT},
+	{4, 1, "ip_radm_qoverflow", C_EC_CRIT},
+	{5, 1, "ip_radm_msg_unlock", C_EC_INFO},
+	{6, 1, "ip_radm_pm_turnoff", C_EC_INFO},
+	{7, 1, "ip_wake", C_EC_INFO},
+	{8, 1, "ip_cfg_uncor_internal_err_sts", C_EC_UNCOR_NS},
+	{9, 1, "ip_cfg_corrected_internal_err_sts", C_EC_COR},
+	{10, 1, "ip_cfg_rcvr_overflow_err_sts", C_EC_CRIT},
+	{11, 1, "ip_cfg_fc_protocol_err_sts", C_EC_CRIT},
+	{12, 1, "ip_cfg_mlf_tlp_err_sts", C_EC_INFO},
+	{13, 1, "ip_cfg_surprise_down_er_sts", C_EC_INFO},
+	{14, 1, "ip_cfg_dl_protocol_err_sts", C_EC_CRIT},
+	{15, 1, "ip_cfg_ecrc_err_sts", C_EC_CRIT},
+	{16, 1, "ip_cfg_replay_number_rollover_err_sts", C_EC_INFO},
+	{17, 1, "ip_cfg_replay_timer_timeout_err_sts", C_EC_CRIT},
+	{18, 1, "ip_cfg_bad_dllp_err_sts", C_EC_CRIT},
+	{19, 1, "ip_cfg_bad_tlp_err_sts", C_EC_CRIT},
+	{20, 1, "ip_cfg_rcvr_err_sts", C_EC_CRIT},
+	{26, 1, "pti_tarb_xlat_xali_ph_crd_warn", C_EC_INFO},
+	{27, 1, "pti_tarb_xlat_xali_pd_crd_warn", C_EC_INFO},
+	{28, 1, "pti_tarb_xlat_xali_nph_crd_warn", C_EC_INFO},
+	{29, 1, "pti_tarb_xlat_xali_npd_crd_warn", C_EC_INFO},
+	{30, 1, "pti_tarb_xlat_ten_bit_tag_msb_error", C_EC_CRIT},
+	{31, 1, "pti_tarb_xlat_p_fifo_underrun", C_EC_CRIT},
+	{32, 1, "pti_tarb_xlat_np_fifo_underrun", C_EC_CRIT},
+	{33, 1, "pti_tarb_xlat_ord_fifo_underrun", C_EC_CRIT},
+	{34, 1, "pti_tarb_xlat_cpl_to_fifo_overrun", C_EC_CRIT},
+	{35, 1, "pti_tarb_xlat_cpl_to_fifo_underrun", C_EC_CRIT},
+	{36, 1, "pti_tarb_xlat_pti_pri_cpl_to_fifo_overrun", C_EC_CRIT},
+	{37, 1, "pti_tarb_xlat_ord_np_cnt_overrun", C_EC_CRIT},
+	{38, 1, "pti_tarb_xlat_ord_np_cnt_underrun", C_EC_CRIT},
+	{39, 1, "pri_rtrgt_hdr_parity_error", C_EC_CRIT},
+	{40, 1, "pri_rtrgt_data_parity_error", C_EC_CRIT},
+	{41, 1, "pri_rtrgt_abort", C_EC_CRIT},
+	{42, 1, "pri_rbyp_hdr_parity_error", C_EC_CRIT},
+	{43, 1, "pri_rbyp_data_parity_error", C_EC_CRIT},
+	{44, 1, "pri_rbyp_abort", C_EC_CRIT},
+	{45, 1, "pri_rarb_xlat_rtrgt_fifo_overrun", C_EC_CRIT},
+	{46, 1, "pri_rarb_xlat_rtrgt_rdy_fifo_overrun", C_EC_CRIT},
+	{47, 1, "pri_rarb_xlat_rbyp_fifo_overrun", C_EC_CRIT},
+	{48, 1, "pri_rarb_xlat_rbyp_rdy_fifo_overrun", C_EC_CRIT},
+	{49, 1, "pri_mb_xlat_rtrgt_fifo_overrun", C_EC_CRIT},
+	{50, 1, "pri_mb_xlat_rtrgt_rdy_fifo_overrun", C_EC_CRIT},
+	{51, 1, "pri_mb_xlat_comp_fifo_underrun", C_EC_CRIT},
+	{52, 1, "msixc_pti_fifo_overrun", C_EC_CRIT},
+	{53, 1, "msixc_pti_fifo_underrun", C_EC_CRIT},
+	{54, 1, "pti_msixc_fifo_overrun", C_EC_CRIT},
+	{55, 1, "pti_msixc_fifo_underrun", C_EC_CRIT},
+	{56, 1, "msix_disabled_error", C_EC_INFO},
+	{57, 1, "msix_hg_vf_size_error", C_EC_INFO},
+	{58, 1, "msix_pti_idx_error", C_EC_INFO},
+	{59, 1, "dmac_bme_error", C_EC_INFO},
+	{64, 1}
+};
+
+static const struct flg_err_info c2_pi_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "crnc_ring_sync_error", C_EC_UNCOR_NS},
+	{2, 1, "crnc_ring_ecc_sbe", C_EC_COR},
+	{3, 1, "crnc_ring_ecc_mbe", C_EC_UNCOR_NS},
+	{4, 1, "crnc_ring_cmd_unknown", C_EC_UNCOR_NS},
+	{5, 1, "crnc_csr_cmd_unknown", C_EC_UNCOR_NS},
+	{6, 1, "crnc_csr_cmd_incomplete", C_EC_UNCOR_NS},
+	{7, 1, "crnc_buf_ecc_sbe", C_EC_COR},
+	{8, 1, "crnc_buf_ecc_mbe", C_EC_UNCOR_NS},
+	{16, 1, "acxt_cor", C_EC_COR,
+	 {{C_PI_ERR_INFO_MEM, C_PI_ERR_INFO_MEM_SIZE, "C_PI_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{17, 1, "acxt_ucor", C_EC_UNCOR_NS,
+	 {{C_PI_ERR_INFO_MEM, C_PI_ERR_INFO_MEM_SIZE, "C_PI_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{18, 1, "sriovt_cor", C_EC_COR,
+	 {{C_PI_ERR_INFO_MEM, C_PI_ERR_INFO_MEM_SIZE, "C_PI_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{19, 1, "sriovt_ucor", C_EC_UNCOR_NS,
+	 {{C_PI_ERR_INFO_MEM, C_PI_ERR_INFO_MEM_SIZE, "C_PI_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{20, 1, "dmac_desc_cor", C_EC_COR,
+	 {{C_PI_ERR_INFO_MEM, C_PI_ERR_INFO_MEM_SIZE, "C_PI_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{21, 1, "dmac_desc_ucor", C_EC_UNCOR_NS,
+	 {{C_PI_ERR_INFO_MEM, C_PI_ERR_INFO_MEM_SIZE, "C_PI_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{22, 4, "pri_mb_xlat_rtrgt_fifo_cor", C_EC_COR,
+	 {{C_PI_ERR_INFO_MEM, C_PI_ERR_INFO_MEM_SIZE, "C_PI_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{26, 4, "pri_mb_xlat_rtrgt_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C_PI_ERR_INFO_MEM, C_PI_ERR_INFO_MEM_SIZE, "C_PI_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{30, 4, "pri_rarb_xlat_rtrgt_fifo_cor", C_EC_COR,
+	 {{C_PI_ERR_INFO_MEM, C_PI_ERR_INFO_MEM_SIZE, "C_PI_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{34, 4, "pri_rarb_xlat_rtrgt_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C_PI_ERR_INFO_MEM, C_PI_ERR_INFO_MEM_SIZE, "C_PI_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{38, 4, "pri_rarb_xlat_rbyp_fifo_cor", C_EC_COR,
+	 {{C_PI_ERR_INFO_MEM, C_PI_ERR_INFO_MEM_SIZE, "C_PI_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{42, 4, "pri_rarb_xlat_rbyp_fifo_ucor", C_EC_UNCOR_NS,
+	 {{C_PI_ERR_INFO_MEM, C_PI_ERR_INFO_MEM_SIZE, "C_PI_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{46, 1, "pti_tarb_xlat_pipe0_hdr_cor", C_EC_COR,
+	 {{C_PI_ERR_INFO_MEM, C_PI_ERR_INFO_MEM_SIZE, "C_PI_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{47, 1, "pti_tarb_xlat_pipe0_hdr_ucor", C_EC_UNCOR_NS,
+	 {{C_PI_ERR_INFO_MEM, C_PI_ERR_INFO_MEM_SIZE, "C_PI_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{48, 1, "pti_tarb_xlat_pipe3_hdr_cor", C_EC_COR,
+	 {{C_PI_ERR_INFO_MEM, C_PI_ERR_INFO_MEM_SIZE, "C_PI_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{49, 1, "pti_tarb_xlat_pipe3_hdr_ucor", C_EC_UNCOR_NS,
+	 {{C_PI_ERR_INFO_MEM, C_PI_ERR_INFO_MEM_SIZE, "C_PI_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{50, 1, "pti_tarb_xlat_pipe3_data_cor", C_EC_COR,
+	 {{C_PI_ERR_INFO_MEM, C_PI_ERR_INFO_MEM_SIZE, "C_PI_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{51, 1, "pti_tarb_xlat_pipe3_data_ucor", C_EC_UNCOR_NS,
+	 {{C_PI_ERR_INFO_MEM, C_PI_ERR_INFO_MEM_SIZE, "C_PI_ERR_INFO_MEM"},
+	  },
+	 {},
+	 },
+	{52, 1, "pti_tarb_xlat_unexpected_dv", C_EC_CRIT,
+	 {{C_PI_ERR_INFO_TARB, C_PI_ERR_INFO_TARB_SIZE, "C_PI_ERR_INFO_TARB"},
+	  },
+	 {},
+	 },
+	{53, 1, "pti_tarb_xlat_ac_en_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_TARB, C_PI_ERR_INFO_TARB_SIZE, "C_PI_ERR_INFO_TARB"},
+	  },
+	 {},
+	 },
+	{54, 1, "pti_tarb_xlat_cfg_vf_en_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_TARB, C_PI_ERR_INFO_TARB_SIZE, "C_PI_ERR_INFO_TARB"},
+	  },
+	 {},
+	 },
+	{55, 1, "pti_tarb_xlat_cfg_vf_num_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_TARB, C_PI_ERR_INFO_TARB_SIZE, "C_PI_ERR_INFO_TARB"},
+	  },
+	 {},
+	 },
+	{56, 1, "pti_tarb_xlat_cfg_vf_bme_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_TARB, C_PI_ERR_INFO_TARB_SIZE, "C_PI_ERR_INFO_TARB"},
+	  },
+	 {},
+	 },
+	{57, 1, "pti_tarb_xlat_cfg_bme_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_TARB, C_PI_ERR_INFO_TARB_SIZE, "C_PI_ERR_INFO_TARB"},
+	  },
+	 {},
+	 },
+	{58, 1, "pti_tarb_xlat_cfg_amo_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_TARB, C_PI_ERR_INFO_TARB_SIZE, "C_PI_ERR_INFO_TARB"},
+	  },
+	 {},
+	 },
+	{62, 2, "uc_attention", C_EC_SFTWR},
+	{64, 1}
+};
+
+static const struct flg_err_info c2_pi_ext_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "pri_mb_xlat_rtrgt_abort_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{2, 1, "pri_mb_xlat_rtrgt_hdr_parity_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{3, 1, "pri_mb_xlat_rtrgt_data_parity_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{4, 1, "pri_mb_xlat_axi_wr_decerr", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{5, 1, "pri_mb_xlat_axi_wr_slverr", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{6, 1, "pri_mb_xlat_axi_rd_decerr", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{7, 1, "pri_mb_xlat_axi_rd_slverr", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{8, 1, "pri_mb_xlat_axi_rd_parity_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{9, 1, "pri_mb_xlat_msg_tlp_discard", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{10, 1, "pri_mb_xlat_unexpected_np_tlp", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{11, 1, "pri_mb_xlat_unexpected_tlp", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{12, 1, "pri_mb_xlat_pf_addr_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{13, 1, "pri_mb_xlat_vf_addr_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{14, 1, "pri_mb_xlat_rom_wr_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{15, 1, "pri_mb_xlat_partial_discard", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{16, 1, "pri_mb_xlat_rtrgt_fifo_underrun", C_EC_CRIT,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{17, 1, "pri_mb_xlat_rtrgt_rdy_fifo_underrun", C_EC_CRIT,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{18, 1, "pri_mb_xlat_comp_fifo_overrun", C_EC_CRIT,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{19, 1, "pri_mb_xlat_comp_ca", C_EC_CRIT,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{20, 1, "pri_mb_xlat_comp_ur", C_EC_CRIT,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{21, 1, "pri_rarb_xlat_rtrgt_abort_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{22, 1, "pri_rarb_xlat_rtrgt_hdr_parity_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{23, 1, "pri_rarb_xlat_rtrgt_data_parity_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{24, 1, "pri_rarb_xlat_rtrgt_unexpected_tlp", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{25, 1, "pri_rarb_xlat_rtrgt_unexpected_msg", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{26, 1, "pri_rarb_xlat_rtrgt_vf_addr_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{27, 1, "pri_rarb_xlat_rtrgt_vf_en_num_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{28, 1, "pri_rarb_xlat_rtrgt_vf_en_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{29, 1, "pri_rarb_xlat_rtrgt_inv_req_vf_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{30, 1, "pri_rarb_xlat_rtrgt_inv_req_dev_id_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{31, 1, "pri_rarb_xlat_rtrgt_prgr_vf_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{32, 1, "pri_rarb_xlat_rtrgt_prgr_dev_id_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{33, 1, "pri_rarb_xlat_rtrgt_fifo_underrun", C_EC_CRIT,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{34, 1, "pri_rarb_xlat_rtrgt_rdy_fifo_underrun", C_EC_CRIT,
+	 {{C_PI_ERR_INFO_RTRGT, C_PI_ERR_INFO_RTRGT_SIZE,
+	   "C_PI_ERR_INFO_RTRGT"},
+	  },
+	 {},
+	 },
+	{35, 1, "pri_rarb_xlat_rbyp_abort_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RBYP, C_PI_ERR_INFO_RBYP_SIZE, "C_PI_ERR_INFO_RBYP"},
+	  },
+	 {},
+	 },
+	{36, 1, "pri_rarb_xlat_rbyp_hdr_parity_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RBYP, C_PI_ERR_INFO_RBYP_SIZE, "C_PI_ERR_INFO_RBYP"},
+	  },
+	 {},
+	 },
+	{37, 1, "pri_rarb_xlat_rbyp_data_parity_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RBYP, C_PI_ERR_INFO_RBYP_SIZE, "C_PI_ERR_INFO_RBYP"},
+	  },
+	 {},
+	 },
+	{38, 1, "pri_rarb_xlat_rbyp_tag_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RBYP, C_PI_ERR_INFO_RBYP_SIZE, "C_PI_ERR_INFO_RBYP"},
+	  },
+	 {},
+	 },
+	{39, 1, "pri_rarb_xlat_rbyp_unexpected_tlp_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_RBYP, C_PI_ERR_INFO_RBYP_SIZE, "C_PI_ERR_INFO_RBYP"},
+	  },
+	 {},
+	 },
+	{40, 1, "pri_rarb_xlat_rbyp_fifo_underrun", C_EC_CRIT,
+	 {{C_PI_ERR_INFO_RBYP, C_PI_ERR_INFO_RBYP_SIZE, "C_PI_ERR_INFO_RBYP"},
+	  },
+	 {},
+	 },
+	{41, 1, "pri_rarb_xlat_rbyp_rdy_fifo_underrun", C_EC_CRIT,
+	 {{C_PI_ERR_INFO_RBYP, C_PI_ERR_INFO_RBYP_SIZE, "C_PI_ERR_INFO_RBYP"},
+	  },
+	 {},
+	 },
+	{42, 1, "pti_tarb_xlat_p_fifo_overrun", C_EC_CRIT,
+	 {{C_PI_ERR_INFO_TARB, C_PI_ERR_INFO_TARB_SIZE, "C_PI_ERR_INFO_TARB"},
+	  },
+	 {},
+	 },
+	{43, 1, "pti_tarb_xlat_np_fifo_overrun", C_EC_CRIT,
+	 {{C_PI_ERR_INFO_TARB, C_PI_ERR_INFO_TARB_SIZE, "C_PI_ERR_INFO_TARB"},
+	  },
+	 {},
+	 },
+	{44, 1, "pti_tarb_xlat_ord_fifo_overrun", C_EC_CRIT,
+	 {{C_PI_ERR_INFO_TARB, C_PI_ERR_INFO_TARB_SIZE, "C_PI_ERR_INFO_TARB"},
+	  },
+	 {},
+	 },
+	{45, 1, "pti_tarb_xlat_np_err_fifo_overrun", C_EC_CRIT,
+	 {{C_PI_ERR_INFO_TARB, C_PI_ERR_INFO_TARB_SIZE, "C_PI_ERR_INFO_TARB"},
+	  },
+	 {},
+	 },
+	{46, 1, "pti_tarb_xlat_np_err_fifo_underrun", C_EC_CRIT},
+	{47, 1, "pti_tarb_xlat_pti_pri_cpl_to_fifo_underrun", C_EC_CRIT},
+	{48, 1, "dmac_axi_rd_decerr", C_EC_INFO,
+	 {{C_PI_ERR_INFO_DMAC, C_PI_ERR_INFO_DMAC_SIZE, "C_PI_ERR_INFO_DMAC"},
+	  },
+	 {},
+	 },
+	{49, 1, "dmac_axi_rd_slverr", C_EC_INFO,
+	 {{C_PI_ERR_INFO_DMAC, C_PI_ERR_INFO_DMAC_SIZE, "C_PI_ERR_INFO_DMAC"},
+	  },
+	 {},
+	 },
+	{50, 1, "dmac_axi_rd_parity_error", C_EC_INFO,
+	 {{C_PI_ERR_INFO_DMAC, C_PI_ERR_INFO_DMAC_SIZE, "C_PI_ERR_INFO_DMAC"},
+	  },
+	 {},
+	 },
+	{51, 1, "ahb_overwrite", C_EC_SFTWR,
+	 {{C2_PI_ERR_INFO_AHB, C2_PI_ERR_INFO_AHB_SIZE, "C2_PI_ERR_INFO_AHB"},
+	  },
+	 {},
+	 },
+	{52, 1, "ahb_resp_err", C_EC_SFTWR,
+	 {{C2_PI_ERR_INFO_AHB, C2_PI_ERR_INFO_AHB_SIZE, "C2_PI_ERR_INFO_AHB"},
+	  },
+	 {},
+	 },
+	{64, 1}
+};
+
+static const struct flg_err_info ss2_port_pml_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "crnc_ring_sync_error", C_EC_UNCOR_NS},
+	{2, 1, "crnc_ring_ecc_sbe", C_EC_COR},
+	{3, 1, "crnc_ring_ecc_mbe", C_EC_UNCOR_NS},
+	{4, 1, "crnc_ring_cmd_unknown", C_EC_UNCOR_NS},
+	{5, 1, "crnc_csr_cmd_unknown", C_EC_UNCOR_NS},
+	{6, 1, "crnc_csr_cmd_incomplete", C_EC_UNCOR_NS},
+	{7, 1, "crnc_buf_ecc_sbe", C_EC_COR},
+	{8, 1, "crnc_buf_ecc_mbe", C_EC_UNCOR_NS},
+	{9, 1, "csrc_ring_sync_error", C_EC_UNCOR_NS},
+	{10, 1, "csrc_ring_ecc_sbe", C_EC_COR},
+	{11, 1, "csrc_ring_ecc_mbe", C_EC_UNCOR_NS},
+	{12, 1, "csrc_ring_cmd_unknown", C_EC_UNCOR_NS},
+	{13, 1, "csrc_sring_sync_error", C_EC_UNCOR_NS},
+	{14, 1, "csrc_sring_ecc_sbe", C_EC_COR},
+	{15, 1, "csrc_sring_ecc_mbe", C_EC_UNCOR_NS},
+	{16, 1, "csrc_sring_cmd_unknown", C_EC_UNCOR_NS},
+	{17, 1, "csrc_buf_ecc_sbe", C_EC_COR},
+	{18, 1, "csrc_buf_ecc_mbe", C_EC_UNCOR_NS},
+	{32, 1, "pcs_tx_dp_err", C_EC_TRNSNT_NS,
+	 {{SS2_PORT_PML_ERR_INFO_PCS_TX_DP,
+	   SS2_PORT_PML_ERR_INFO_PCS_TX_DP_SIZE,
+	   "SS2_PORT_PML_ERR_INFO_PCS_TX_DP"},
+	  },
+	 {},
+	 },
+	{33, 1, "pcs_rx_dp_err", C_EC_TRNSNT_NS,
+	 {{SS2_PORT_PML_ERR_INFO_PCS_RX_DP,
+	   SS2_PORT_PML_ERR_INFO_PCS_RX_DP_SIZE,
+	   "SS2_PORT_PML_ERR_INFO_PCS_RX_DP"},
+	  },
+	 {},
+	 },
+	{34, 1, "pcs_rx_deskew_overflow", C_EC_TRNSNT_NS,
+	 {{SS2_PORT_PML_ERR_INFO_PCS_RX_DESKEW,
+	   SS2_PORT_PML_ERR_INFO_PCS_RX_DESKEW_SIZE,
+	   "SS2_PORT_PML_ERR_INFO_PCS_RX_DESKEW"},
+	  },
+	 {},
+	 },
+	{35, 1, "pcs_rx_deskew_pe", C_EC_UNCOR_NS,
+	 {{SS2_PORT_PML_ERR_INFO_PCS_RX_DESKEW_PES,
+	   SS2_PORT_PML_ERR_INFO_PCS_RX_DESKEW_PES_SIZE,
+	   "SS2_PORT_PML_ERR_INFO_PCS_RX_DESKEW_PES"},
+	  },
+	 {},
+	 },
+	{36, 1, "pcs_fec0_mem_sbe", C_EC_COR,
+	 {{SS2_PORT_PML_ERR_INFO_EDC_COR, SS2_PORT_PML_ERR_INFO_EDC_COR_SIZE,
+	   "SS2_PORT_PML_ERR_INFO_EDC_COR"},
+	  },
+	 {},
+	 },
+	{37, 1, "pcs_fec0_mem_mbe", C_EC_UNCOR_NS,
+	 {{SS2_PORT_PML_ERR_INFO_EDC_UCOR, SS2_PORT_PML_ERR_INFO_EDC_UCOR_SIZE,
+	   "SS2_PORT_PML_ERR_INFO_EDC_UCOR"},
+	  },
+	 {},
+	 },
+	{38, 1, "pcs_fec1_mem_sbe", C_EC_COR,
+	 {{SS2_PORT_PML_ERR_INFO_EDC_COR, SS2_PORT_PML_ERR_INFO_EDC_COR_SIZE,
+	   "SS2_PORT_PML_ERR_INFO_EDC_COR"},
+	  },
+	 {},
+	 },
+	{39, 1, "pcs_fec1_mem_mbe", C_EC_UNCOR_NS,
+	 {{SS2_PORT_PML_ERR_INFO_EDC_UCOR, SS2_PORT_PML_ERR_INFO_EDC_UCOR_SIZE,
+	   "SS2_PORT_PML_ERR_INFO_EDC_UCOR"},
+	  },
+	 {},
+	 },
+	{40, 1, "mac_tx_dp_err", C_EC_TRNSNT_NS,
+	 {{SS2_PORT_PML_ERR_INFO_MAC_TX_DP,
+	   SS2_PORT_PML_ERR_INFO_MAC_TX_DP_SIZE,
+	   "SS2_PORT_PML_ERR_INFO_MAC_TX_DP"},
+	  },
+	 {},
+	 },
+	{41, 1, "mac_rx_dp_err", C_EC_TRNSNT_NS,
+	 {{SS2_PORT_PML_ERR_INFO_MAC_RX_DP,
+	   SS2_PORT_PML_ERR_INFO_MAC_RX_DP_SIZE,
+	   "SS2_PORT_PML_ERR_INFO_MAC_RX_DP"},
+	  },
+	 {},
+	 },
+	{42, 1, "llr_tx_dp_sbe", C_EC_COR,
+	 {{SS2_PORT_PML_ERR_INFO_LLR_TX_DP_SBE,
+	   SS2_PORT_PML_ERR_INFO_LLR_TX_DP_SBE_SIZE,
+	   "SS2_PORT_PML_ERR_INFO_LLR_TX_DP_SBE"},
+	  },
+	 {},
+	 },
+	{43, 1, "llr_tx_dp_mbe", C_EC_UNCOR_NS,
+	 {{SS2_PORT_PML_ERR_INFO_LLR_TX_DP_MBE,
+	   SS2_PORT_PML_ERR_INFO_LLR_TX_DP_MBE_SIZE,
+	   "SS2_PORT_PML_ERR_INFO_LLR_TX_DP_MBE"},
+	  },
+	 {},
+	 },
+	{44, 1, "llr_tx_dp_err", C_EC_TRNSNT_NS,
+	 {{SS2_PORT_PML_ERR_INFO_LLR_TX_DP,
+	   SS2_PORT_PML_ERR_INFO_LLR_TX_DP_SIZE,
+	   "SS2_PORT_PML_ERR_INFO_LLR_TX_DP"},
+	  },
+	 {},
+	 },
+	{45, 1, "llr_rx_dp_err", C_EC_TRNSNT_NS},
+	{46, 1, "llr_seq_mem_sbe", C_EC_COR,
+	 {{SS2_PORT_PML_ERR_INFO_EDC_COR, SS2_PORT_PML_ERR_INFO_EDC_COR_SIZE,
+	   "SS2_PORT_PML_ERR_INFO_EDC_COR"},
+	  },
+	 {},
+	 },
+	{47, 1, "llr_seq_mem_mbe", C_EC_UNCOR_NS,
+	 {{SS2_PORT_PML_ERR_INFO_EDC_UCOR, SS2_PORT_PML_ERR_INFO_EDC_UCOR_SIZE,
+	   "SS2_PORT_PML_ERR_INFO_EDC_UCOR"},
+	  },
+	 {},
+	 },
+	{48, 1, "llr_replay_mem_sbe", C_EC_COR,
+	 {{SS2_PORT_PML_ERR_INFO_EDC_COR, SS2_PORT_PML_ERR_INFO_EDC_COR_SIZE,
+	   "SS2_PORT_PML_ERR_INFO_EDC_COR"},
+	  },
+	 {},
+	 },
+	{49, 1, "llr_replay_mem_mbe", C_EC_UNCOR_NS,
+	 {{SS2_PORT_PML_ERR_INFO_EDC_UCOR, SS2_PORT_PML_ERR_INFO_EDC_UCOR_SIZE,
+	   "SS2_PORT_PML_ERR_INFO_EDC_UCOR"},
+	  },
+	 {},
+	 },
+	{50, 1, "event_mem_sbe", C_EC_COR,
+	 {{SS2_PORT_PML_ERR_INFO_EDC_COR, SS2_PORT_PML_ERR_INFO_EDC_COR_SIZE,
+	   "SS2_PORT_PML_ERR_INFO_EDC_COR"},
+	  },
+	 {},
+	 },
+	{51, 1, "event_mem_mbe", C_EC_UNCOR_NS,
+	 {{SS2_PORT_PML_ERR_INFO_EDC_UCOR, SS2_PORT_PML_ERR_INFO_EDC_UCOR_SIZE,
+	   "SS2_PORT_PML_ERR_INFO_EDC_UCOR"},
+	  },
+	 {},
+	 },
+	{52, 1, "mac_rx_fcs32_err_0", C_EC_TRNSNT_NS},
+	{53, 1, "mac_rx_fcs32_err_1", C_EC_TRNSNT_NS},
+	{54, 1, "mac_rx_fcs32_err_2", C_EC_TRNSNT_NS},
+	{55, 1, "mac_rx_fcs32_err_3", C_EC_TRNSNT_NS},
+	{56, 1, "mac_rx_framing_err_0", C_EC_TRNSNT_NS},
+	{57, 1, "mac_rx_framing_err_1", C_EC_TRNSNT_NS},
+	{58, 1, "mac_rx_framing_err_2", C_EC_TRNSNT_NS},
+	{59, 1, "mac_rx_framing_err_3", C_EC_TRNSNT_NS},
+	{60, 1, "mac_rx_preamble_err_0", C_EC_TRNSNT_NS},
+	{61, 1, "mac_rx_preamble_err_1", C_EC_TRNSNT_NS},
+	{62, 1, "mac_rx_preamble_err_2", C_EC_TRNSNT_NS},
+	{63, 1, "mac_rx_preamble_err_3", C_EC_TRNSNT_NS},
+	{64, 1, "pcs_link_down_0", C_EC_TRNSNT_NS},
+	{65, 1, "pcs_link_down_1", C_EC_TRNSNT_NS},
+	{66, 1, "pcs_link_down_2", C_EC_TRNSNT_NS},
+	{67, 1, "pcs_link_down_3", C_EC_TRNSNT_NS},
+	{68, 1, "pcs_link_down_lf_0", C_EC_TRNSNT_NS},
+	{69, 1, "pcs_link_down_lf_1", C_EC_TRNSNT_NS},
+	{70, 1, "pcs_link_down_lf_2", C_EC_TRNSNT_NS},
+	{71, 1, "pcs_link_down_lf_3", C_EC_TRNSNT_NS},
+	{72, 1, "pcs_link_down_rf_0", C_EC_TRNSNT_NS},
+	{73, 1, "pcs_link_down_rf_1", C_EC_TRNSNT_NS},
+	{74, 1, "pcs_link_down_rf_2", C_EC_TRNSNT_NS},
+	{75, 1, "pcs_link_down_rf_3", C_EC_TRNSNT_NS},
+	{76, 1, "pcs_hi_ser_0", C_EC_TRNSNT_NS},
+	{77, 1, "pcs_hi_ser_1", C_EC_TRNSNT_NS},
+	{78, 1, "pcs_hi_ser_2", C_EC_TRNSNT_NS},
+	{79, 1, "pcs_hi_ser_3", C_EC_TRNSNT_NS},
+	{80, 1, "pcs_tx_degrade", C_EC_DEGRD_NS},
+	{81, 1, "pcs_rx_degrade", C_EC_DEGRD_NS},
+	{82, 1, "pcs_rx_degrade_failure", C_EC_UNCOR_NS},
+	{83, 1, "pcs_tx_degrade_failure", C_EC_UNCOR_NS},
+	{92, 1, "autoneg_failed_0", C_EC_TRNSNT_NS},
+	{93, 1, "autoneg_failed_1", C_EC_TRNSNT_NS},
+	{94, 1, "autoneg_failed_2", C_EC_TRNSNT_NS},
+	{95, 1, "autoneg_failed_3", C_EC_TRNSNT_NS},
+	{96, 1, "llr_ack_nack_error_0", C_EC_TRNSNT_NS},
+	{97, 1, "llr_ack_nack_error_1", C_EC_TRNSNT_NS},
+	{98, 1, "llr_ack_nack_error_2", C_EC_TRNSNT_NS},
+	{99, 1, "llr_ack_nack_error_3", C_EC_TRNSNT_NS},
+	{100, 1, "llr_ack_nack_seq_err_0", C_EC_TRNSNT_NS},
+	{101, 1, "llr_ack_nack_seq_err_1", C_EC_TRNSNT_NS},
+	{102, 1, "llr_ack_nack_seq_err_2", C_EC_TRNSNT_NS},
+	{103, 1, "llr_ack_nack_seq_err_3", C_EC_TRNSNT_NS},
+	{104, 1, "llr_replay_at_max_0", C_EC_TRNSNT_NS},
+	{105, 1, "llr_replay_at_max_1", C_EC_TRNSNT_NS},
+	{106, 1, "llr_replay_at_max_2", C_EC_TRNSNT_NS},
+	{107, 1, "llr_replay_at_max_3", C_EC_TRNSNT_NS},
+	{108, 1, "llr_expected_frame_bad_0", C_EC_TRNSNT_NS},
+	{109, 1, "llr_expected_frame_bad_1", C_EC_TRNSNT_NS},
+	{110, 1, "llr_expected_frame_bad_2", C_EC_TRNSNT_NS},
+	{111, 1, "llr_expected_frame_bad_3", C_EC_TRNSNT_NS},
+	{112, 1, "llr_duplicate_frame_0", C_EC_TRNSNT_NS},
+	{113, 1, "llr_duplicate_frame_1", C_EC_TRNSNT_NS},
+	{114, 1, "llr_duplicate_frame_2", C_EC_TRNSNT_NS},
+	{115, 1, "llr_duplicate_frame_3", C_EC_TRNSNT_NS},
+	{116, 1, "llr_unexpected_frame_0", C_EC_TRNSNT_NS},
+	{117, 1, "llr_unexpected_frame_1", C_EC_TRNSNT_NS},
+	{118, 1, "llr_unexpected_frame_2", C_EC_TRNSNT_NS},
+	{119, 1, "llr_unexpected_frame_3", C_EC_TRNSNT_NS},
+	{120, 1, "llr_loop_time_fail_0", C_EC_TRNSNT_NS},
+	{121, 1, "llr_loop_time_fail_1", C_EC_TRNSNT_NS},
+	{122, 1, "llr_loop_time_fail_2", C_EC_TRNSNT_NS},
+	{123, 1, "llr_loop_time_fail_3", C_EC_TRNSNT_NS},
+	{124, 1, "llr_init_fail_0", C_EC_TRNSNT_NS},
+	{125, 1, "llr_init_fail_1", C_EC_TRNSNT_NS},
+	{126, 1, "llr_init_fail_2", C_EC_TRNSNT_NS},
+	{127, 1, "llr_init_fail_3", C_EC_TRNSNT_NS},
+	{128, 1, "llr_starved_0", C_EC_TRNSNT_NS},
+	{129, 1, "llr_starved_1", C_EC_TRNSNT_NS},
+	{130, 1, "llr_starved_2", C_EC_TRNSNT_NS},
+	{131, 1, "llr_starved_3", C_EC_TRNSNT_NS},
+	{132, 1, "llr_max_starvation_limit_0", C_EC_TRNSNT_NS},
+	{133, 1, "llr_max_starvation_limit_1", C_EC_TRNSNT_NS},
+	{134, 1, "llr_max_starvation_limit_2", C_EC_TRNSNT_NS},
+	{135, 1, "llr_max_starvation_limit_3", C_EC_TRNSNT_NS},
+	{192, 1, "pcs_lanes_locked_0", C_EC_INFO},
+	{193, 1, "pcs_lanes_locked_1", C_EC_INFO},
+	{194, 1, "pcs_lanes_locked_2", C_EC_INFO},
+	{195, 1, "pcs_lanes_locked_3", C_EC_INFO},
+	{196, 1, "pcs_aligned_0", C_EC_INFO},
+	{197, 1, "pcs_aligned_1", C_EC_INFO},
+	{198, 1, "pcs_aligned_2", C_EC_INFO},
+	{199, 1, "pcs_aligned_3", C_EC_INFO},
+	{200, 1, "pcs_link_up_0", C_EC_INFO},
+	{201, 1, "pcs_link_up_1", C_EC_INFO},
+	{202, 1, "pcs_link_up_2", C_EC_INFO},
+	{203, 1, "pcs_link_up_3", C_EC_INFO},
+	{204, 1, "pcs_rx_degrade_rdy", C_EC_INFO},
+	{205, 1, "pcs_lp_degrade_rdy", C_EC_INFO},
+	{208, 1, "autoneg_page_received_0", C_EC_INFO},
+	{209, 1, "autoneg_page_received_1", C_EC_INFO},
+	{210, 1, "autoneg_page_received_2", C_EC_INFO},
+	{211, 1, "autoneg_page_received_3", C_EC_INFO},
+	{212, 1, "autoneg_complete_0", C_EC_INFO},
+	{213, 1, "autoneg_complete_1", C_EC_INFO},
+	{214, 1, "autoneg_complete_2", C_EC_INFO},
+	{215, 1, "autoneg_complete_3", C_EC_INFO},
+	{216, 1, "llr_loop_time_0", C_EC_INFO},
+	{217, 1, "llr_loop_time_1", C_EC_INFO},
+	{218, 1, "llr_loop_time_2", C_EC_INFO},
+	{219, 1, "llr_loop_time_3", C_EC_INFO},
+	{220, 1, "time_stamp_valid_0", C_EC_INFO},
+	{221, 1, "time_stamp_valid_1", C_EC_INFO},
+	{222, 1, "time_stamp_valid_2", C_EC_INFO},
+	{223, 1, "time_stamp_valid_3", C_EC_INFO},
+	{224, 1, "fec_err_vector_valid", C_EC_INFO},
+	{225, 1, "llr_init_complete_0", C_EC_INFO},
+	{226, 1, "llr_init_complete_1", C_EC_INFO},
+	{227, 1, "llr_init_complete_2", C_EC_INFO},
+	{228, 1, "llr_init_complete_3", C_EC_INFO},
+	{229, 1, "event_cnt_ovf", C_EC_INFO},
+	{230, 1, "rx_signal_ok_0", C_EC_INFO},
+	{231, 1, "rx_signal_ok_1", C_EC_INFO},
+	{232, 1, "rx_signal_ok_2", C_EC_INFO},
+	{233, 1, "rx_signal_ok_3", C_EC_INFO},
+	{256, 1}
+};
+
+static const struct flg_err_info c2_rmu_err_info[] = {
+	{0, 1, "sw_diag", C_EC_SFTWR},
+	{1, 1, "crnc_ring_sync_error", C_EC_UNCOR_NS},
+	{2, 1, "crnc_ring_ecc_sbe", C_EC_COR},
+	{3, 1, "crnc_ring_ecc_mbe", C_EC_UNCOR_NS},
+	{4, 1, "crnc_ring_cmd_unknown", C_EC_UNCOR_NS},
+	{5, 1, "crnc_csr_cmd_unknown", C_EC_UNCOR_NS},
+	{6, 1, "crnc_csr_cmd_incomplete", C_EC_UNCOR_NS},
+	{7, 1, "crnc_buf_ecc_sbe", C_EC_COR},
+	{8, 1, "crnc_buf_ecc_mbe", C_EC_UNCOR_NS},
+	{32, 1, "ptl_idx_mem_cor", C_EC_COR,
+	 {{C_RMU_ERR_INFO_MEM, C_RMU_ERR_INFO_MEM_SIZE, "C_RMU_ERR_INFO_MEM"},
+	  },
+	 {{0x9870A50, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{33, 1, "ptlte_set_ctrl_mem_cor", C_EC_COR,
+	 {{C_RMU_ERR_INFO_MEM, C_RMU_ERR_INFO_MEM_SIZE, "C_RMU_ERR_INFO_MEM"},
+	  },
+	 {{0x9870A50, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{34, 1, "ptl_idx_indir_mem_cor", C_EC_COR,
+	 {{C_RMU_ERR_INFO_MEM, C_RMU_ERR_INFO_MEM_SIZE, "C_RMU_ERR_INFO_MEM"},
+	  },
+	 {{0x9870A50, "mem_cor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{36, 1, "vni_list_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_RMU_ERR_INFO_MEM, C_RMU_ERR_INFO_MEM_SIZE, "C_RMU_ERR_INFO_MEM"},
+	  },
+	 {{0x9870A58, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{37, 1, "vni_list_vld_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_RMU_ERR_INFO_MEM, C_RMU_ERR_INFO_MEM_SIZE, "C_RMU_ERR_INFO_MEM"},
+	  },
+	 {{0x9870A58, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{38, 1, "ptl_list_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_RMU_ERR_INFO_MEM, C_RMU_ERR_INFO_MEM_SIZE, "C_RMU_ERR_INFO_MEM"},
+	  },
+	 {{0x9870A58, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{39, 1, "ptl_list_vld_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_RMU_ERR_INFO_MEM, C_RMU_ERR_INFO_MEM_SIZE, "C_RMU_ERR_INFO_MEM"},
+	  },
+	 {{0x9870A58, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{40, 1, "ptl_idx_mem_ucor", C_EC_UNCOR_S,
+	 {{C_RMU_ERR_INFO_MEM, C_RMU_ERR_INFO_MEM_SIZE, "C_RMU_ERR_INFO_MEM"},
+	  },
+	 {{0x9870A58, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{41, 1, "ptlte_set_list_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_RMU_ERR_INFO_MEM, C_RMU_ERR_INFO_MEM_SIZE, "C_RMU_ERR_INFO_MEM"},
+	  },
+	 {{0x9870A58, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{42, 1, "ptlte_set_list_vld_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_RMU_ERR_INFO_MEM, C_RMU_ERR_INFO_MEM_SIZE, "C_RMU_ERR_INFO_MEM"},
+	  },
+	 {{0x9870A58, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{43, 1, "ptlte_set_ctrl_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_RMU_ERR_INFO_MEM, C_RMU_ERR_INFO_MEM_SIZE, "C_RMU_ERR_INFO_MEM"},
+	  },
+	 {{0x9870A58, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{44, 1, "ptl_idx_indir_mem_ucor", C_EC_UNCOR_NS,
+	 {{C_RMU_ERR_INFO_MEM, C_RMU_ERR_INFO_MEM_SIZE, "C_RMU_ERR_INFO_MEM"},
+	  },
+	 {{0x9870A58, "mem_ucor_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{48, 1, "ptl_invld_dfa", C_EC_BADCON_S,
+	 {{C_RMU_ERR_INFO_PTL_INVLD_DFA, C_RMU_ERR_INFO_PTL_INVLD_DFA_SIZE,
+	   "C_RMU_ERR_INFO_PTL_INVLD_DFA"},
+	  },
+	 {{0x9870A60, "ptl_invld_dfa_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{49, 1, "ptl_invld_vni", C_EC_BADCON_S,
+	 {{C_RMU_ERR_INFO_PTL_INVLD_VNI, C_RMU_ERR_INFO_PTL_INVLD_VNI_SIZE,
+	   "C_RMU_ERR_INFO_PTL_INVLD_VNI"},
+	  },
+	 {{0x9870A68, "ptl_invld_vni_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{50, 1, "ptl_no_ptlte", C_EC_BADCON_S,
+	 {{C_RMU_ERR_INFO_PTL_NO_PTLTE, C_RMU_ERR_INFO_PTL_NO_PTLTE_SIZE,
+	   "C_RMU_ERR_INFO_PTL_NO_PTLTE"},
+	  },
+	 {{0x9870A70, "ptl_no_ptlte_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{51, 1, "enet_frame_rejected", C_EC_BADCON_NS,
+	 {{C_RMU_ERR_INFO_ENET_NO_PTLTE_SET,
+	   C_RMU_ERR_INFO_ENET_NO_PTLTE_SET_SIZE,
+	   "C_RMU_ERR_INFO_ENET_NO_PTLTE_SET"},
+	  },
+	 {{0x9870A78, "enet_frame_rejected_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{52, 1, "enet_ptlte_set_ctrl_err", C_EC_BADCON_NS,
+	 {{C_RMU_ERR_INFO_ENET_BAD_PTLTE_SET_CTRL,
+	   C_RMU_ERR_INFO_ENET_BAD_PTLTE_SET_CTRL_SIZE,
+	   "C_RMU_ERR_INFO_ENET_BAD_PTLTE_SET_CTRL"},
+	  },
+	 {{0x9870A80, "enet_ptlte_set_ctrl_err_cntr", C_ERR_INDEX_NONE},
+	  },
+	 },
+	{64, 1}
+};
+
+#endif
diff --git a/include/linux/hpe/cxi/cxi.h b/include/linux/hpe/cxi/cxi.h
new file mode 100644
index 000000000000..c951e92028af
--- /dev/null
+++ b/include/linux/hpe/cxi/cxi.h
@@ -0,0 +1,611 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2021-2022, 2024-2026 Hewlett Packard Enterprise Development LP */
+
+/* Public definitions for the CXI subsystem */
+
+#ifndef _LINUX_CXI_H
+#define _LINUX_CXI_H
+
+#include <linux/list.h>
+#include <linux/ktime.h>
+#include <linux/uio.h>
+#include <linux/firmware.h>
+#include <uapi/linux/ethtool.h>
+#include <uapi/linux/if.h>
+#include <uapi/linux/net_tstamp.h>
+
+#include "cxi_prov_hw.h"
+#include "cxi_defs.h"
+
+#define TRANSACTION_TYPE 0xF
+#define CXI_INVALID_NID 0xFFFFFFFF
+/**
+ * struct cxi_dev - A CXI device
+ *
+ * This represents a CXI PCI device, which can either be the physical
+ * device (PF), or a virtual device (VF). Such a device is needed to
+ * use most CXI APIs.
+ */
+struct cxi_dev {
+	/* Device name. eg cxi0. */
+	char name[30];
+
+	/* Device number */
+	unsigned int cxi_num;
+
+	/* Main Ethernet device linked to this device. Used for
+	 * logging.
+	 */
+	char eth_name[IFNAMSIZ];
+
+	/* MAC address assigned to the device */
+	u8 mac_addr[ETH_ALEN];
+
+	/* PCP to be used for untagged Ethernet frames. */
+	u8 untagged_eth_pcp;
+
+	/* Link to the core's device list */
+	struct list_head dev_list;
+
+	/* Whether this device is a PF or a passthrough PF, or a VF. */
+	bool is_physfn;
+
+	struct pci_dev *pdev;
+
+	struct cxi_properties_info prop;
+
+	/* System info (mix or homogeneous) */
+	enum system_type_identifier system_type_identifier;
+
+	struct cxi_ib_dev *cxi_ibdev;
+};
+
+struct cxi_lni {
+	unsigned int id;
+	unsigned int rgid;
+};
+
+struct cxi_md;
+
+struct cxi_pte {
+	/* Portal index */
+	unsigned int id;
+};
+
+struct cxi_domain {
+	unsigned int id;
+	unsigned int vni;
+	unsigned int pid;
+};
+
+struct cxi_rmu_eth {
+	unsigned int id;
+};
+
+struct cxi_ac {
+	int acid;
+	int lac;
+};
+
+enum cxi_async_event {
+	CXI_EVENT_CABLE_INSERTED = 1,
+	CXI_EVENT_CABLE_REMOVED,
+	CXI_EVENT_LINK_UP,
+	CXI_EVENT_LINK_DOWN,
+
+	/* The MAC address of the device has being set or
+	 * updated. This changes the NID, which some users care
+	 * about. When getting this event they can retrieve the new
+	 * NID.
+	 */
+	CXI_EVENT_NID_CHANGED,
+};
+
+/* Resources used by an Ethernet device. */
+struct cxi_eth_res {
+	/* Track which Set List entries are used by this Ethernet
+	 * device. The size matches C_RMU_CFG_PTLTE_SET_LIST_ENTRIES.
+	 */
+	unsigned long sl[BITS_TO_LONGS(128)];
+
+	/* The default catch-all portal table entry. If a packet
+	 * doesn't hash, or no hash are defined, this is where it will
+	 * go to.
+	 */
+	unsigned int ptn_def;
+
+	/* Portal for ptp */
+	unsigned int ptn_ptp;
+
+	/* Number of RSS queues */
+	unsigned int rss_queues;
+
+	/* Number of entries in the indirection table */
+	unsigned int rss_indir_size;
+
+	/* Hashing function(s) used. The same hash is used for all Set
+	 * List entries for that device.
+	 */
+	unsigned int portal_index_indir_base;
+	u32 hash_types_enabled; /* or'ed C_RSS_HASH_TYPES_ENABLED_T */
+	unsigned int ptn_rss[CXI_ETH_MAX_RSS_QUEUES];
+	u32 indir_table[CXI_ETH_MAX_INDIR_ENTRIES];
+};
+
+#define PTP_L2_MAC 0x011B19000000ULL
+#define PTP_L2_ETHERTYPE 0x88f7
+
+/* Access Control Entries */
+typedef unsigned int __bitwise cxi_ac_typeset_t;
+enum cxi_ac_type {
+	CXI_AC_UID  = (__force cxi_ac_typeset_t)BIT(0),
+	CXI_AC_GID  = (__force cxi_ac_typeset_t)BIT(1),
+	CXI_AC_OPEN = (__force cxi_ac_typeset_t)BIT(2),
+	CXI_AC_NETNS = (__force cxi_ac_typeset_t)BIT(3),
+};
+
+/* Common parts of RX and TX Profiles */
+#define CXI_VNI_NAME_LEN    64
+#define MAX_PID_BITS 9
+#define DEFAULT_PID_BITS MAX_PID_BITS
+
+union cxi_ac_data {
+	uid_t     uid;
+	gid_t     gid;
+	unsigned int netns;
+};
+
+struct cxi_ac_entry_list {
+	struct cxi_ac_entry *open_entry;
+	struct {
+		struct xarray       xarray;
+	} uid;
+	struct {
+		struct xarray       xarray;
+	} gid;
+	struct {
+		struct xarray       xarray;
+	} netns;
+
+	struct {
+		struct xarray       xarray;
+	} id;
+};
+
+struct cxi_rxtx_vni_attr {
+	u16         match;
+	u16         ignore;
+	char        name[CXI_VNI_NAME_LEN];
+};
+
+struct cxi_rxtx_profile_state {
+	bool       enable;
+	refcount_t refcount;
+};
+
+struct cxi_rxtx_profile {
+	unsigned int                   id;
+	struct cxi_rxtx_vni_attr       vni_attr;
+	struct cxi_rxtx_profile_state  state;
+	struct cxi_ac_entry_list       ac_entry_list;
+};
+
+/* RX Profile */
+
+/* Struct to hold HW configuration */
+struct cxi_rx_config {
+	struct cxi_dev *device;
+	int rmu_index;
+	DECLARE_BITMAP(pid_table, 1 << MAX_PID_BITS);
+	spinlock_t pid_lock;
+};
+
+/* Struct for creation and listing */
+struct cxi_rx_attr {
+	struct cxi_rxtx_vni_attr        vni_attr;
+	/* TODO: other RX specific attributes */
+};
+
+struct cxi_rx_profile {
+	struct cxi_rxtx_profile         profile_common;
+	struct cxi_rx_config            config;
+	/* TODO: other RX parameters */
+};
+
+/* TX Profile */
+
+struct cxi_tx_config {
+	bool exclusive_cp;
+	struct cass_dev *hw;
+	struct idr cass_cp_table;
+	DECLARE_BITMAP(tc_table, CXI_TC_MAX);
+	spinlock_t lock;
+};
+
+/* Struct for creation and listing */
+struct cxi_tx_attr {
+	struct cxi_rxtx_vni_attr vni_attr;
+};
+
+struct cxi_tx_profile {
+	struct cxi_rxtx_profile         profile_common;
+	struct cxi_tx_config            config;
+};
+
+struct cxi_rx_profile *cxi_dev_alloc_rx_profile(struct cxi_dev *dev,
+					const struct cxi_rx_attr *rx_attr);
+struct cxi_tx_profile *cxi_dev_alloc_tx_profile(struct cxi_dev *dev,
+					const struct cxi_tx_attr *tx_attr);
+int cxi_rx_profile_dec_refcount(struct cxi_dev *dev,
+				struct cxi_rx_profile *rx_profile);
+int cxi_tx_profile_dec_refcount(struct cxi_dev *dev,
+				struct cxi_tx_profile *tx_profile,
+				bool list_remove);
+struct cxi_rx_profile *cxi_dev_get_rx_profile(struct cxi_dev *dev,
+					      unsigned int vni);
+struct cxi_tx_profile *cxi_dev_get_tx_profile(struct cxi_dev *dev,
+					      unsigned int vni);
+int cxi_tx_profile_set_tc(struct cxi_tx_profile *tx_profile, int tc, bool set);
+int cxi_rx_profile_add_ac_entry(struct cxi_rx_profile *rx_profile,
+				enum cxi_ac_type type, uid_t uid, gid_t gid,
+				unsigned int netns, unsigned int *ac_entry_id);
+int cxi_tx_profile_add_ac_entry(struct cxi_tx_profile *tx_profile,
+				enum cxi_ac_type type, uid_t uid, gid_t gid,
+				unsigned int netns, unsigned int *ac_entry_id);
+void cxi_tx_profile_remove_ac_entries(struct cxi_tx_profile *tx_profile);
+int cxi_dev_set_rx_profile_attr(struct cxi_dev *dev,
+				struct cxi_rx_profile *rx_profile,
+				const struct cxi_rx_attr *rx_attr);
+int cxi_dev_set_tx_profile_attr(struct cxi_dev *dev,
+				struct cxi_tx_profile *tx_profile,
+				const struct cxi_tx_attr *tx_attr);
+int cxi_rx_profile_enable(struct cxi_dev *dev,
+			   struct cxi_rx_profile *rx_profile);
+void cxi_rx_profile_disable(struct cxi_dev *dev,
+			   struct cxi_rx_profile *rx_profile);
+int cxi_tx_profile_enable(struct cxi_dev *dev,
+			   struct cxi_tx_profile *tx_profile);
+void cxi_tx_profile_disable(struct cxi_dev *dev,
+			   struct cxi_tx_profile *tx_profile);
+bool cxi_rx_profile_is_enabled(const struct cxi_rx_profile *rx_profile);
+bool cxi_tx_profile_is_enabled(const struct cxi_tx_profile *tx_profile);
+bool cxi_tx_profile_exclusive_cp(struct cxi_tx_profile *tx_profile);
+int cxi_tx_profile_set_exclusive_cp(struct cxi_tx_profile *tx_profile,
+				    bool exclusive_cp);
+int cxi_rx_profile_get_info(struct cxi_dev *dev,
+			    struct cxi_rx_profile *rx_profile,
+			    struct cxi_rx_attr *rx_attr,
+			    struct cxi_rxtx_profile_state *state);
+int cxi_tx_profile_get_info(struct cxi_dev *dev,
+			    struct cxi_tx_profile *tx_profile,
+			    struct cxi_tx_attr *tx_attr,
+			    struct cxi_rxtx_profile_state *state);
+int cxi_svc_set_netns(struct cxi_dev *dev, unsigned int svc_id, unsigned int netns);
+int cxi_svc_get_netns(struct cxi_dev *dev, unsigned int svc_id,
+		      unsigned int *netns);
+
+/* Rgroup */
+struct cxi_rgroup;
+struct cxi_rgroup_attr;
+
+struct cxi_resource_limits {
+	size_t     reserved;
+	size_t     max;
+	size_t     in_use;
+};
+
+enum cxi_resource_type {
+	CXI_RESOURCE_PTLTE  = 1,
+	CXI_RESOURCE_TXQ,
+	CXI_RESOURCE_TGQ,
+	CXI_RESOURCE_EQ,
+	CXI_RESOURCE_CT,
+	CXI_RESOURCE_PE0_LE,
+	CXI_RESOURCE_PE1_LE,
+	CXI_RESOURCE_PE2_LE,
+	CXI_RESOURCE_PE3_LE,
+	CXI_RESOURCE_TLE,
+	CXI_RESOURCE_AC,
+	CXI_RESOURCE_MAX,
+};
+
+void cxi_rgroup_enable(struct cxi_rgroup *rgroup);
+void cxi_rgroup_disable(struct cxi_rgroup *rgroup);
+bool cxi_rgroup_is_enabled(struct cxi_rgroup *rgroup);
+void cxi_rgroup_ac_entry_list_destroy(struct cxi_rgroup *rgroup);
+
+unsigned int cxi_rgroup_id(const struct cxi_rgroup *rgroup);
+char *cxi_rgroup_name(struct cxi_rgroup *rgroup);
+bool cxi_rgroup_system_service(const struct cxi_rgroup *rgroup);
+unsigned int cxi_rgroup_cntr_pool_id(const struct cxi_rgroup *rgroup);
+unsigned int cxi_rgroup_lnis_per_rgid(const struct cxi_rgroup *rgroup);
+int cxi_rgroup_refcount(const struct cxi_rgroup *rgroup);
+int cxi_rgroup_le_pool_id(const struct cxi_rgroup *rgroup, int index);
+int cxi_rgroup_tle_pool_id(const struct cxi_rgroup *rgroup);
+int cxi_rgroup_set_lnis_per_rgid(struct cxi_rgroup *rgroup, int lnis_per_rgid);
+void cxi_rgroup_set_lnis_per_rgid_compat(struct cxi_rgroup *rgroup,
+				     int lnis_per_rgid);
+int cxi_rgroup_set_cntr_pool_id(struct cxi_rgroup *rgroup, int cntr_pool_id);
+int cxi_rgroup_set_system_service(struct cxi_rgroup *rgroup, bool system_service);
+int cxi_rgroup_set_name(struct cxi_rgroup *rgroup, char *name);
+struct cxi_rgroup *cxi_dev_alloc_rgroup(struct cxi_dev *dev,
+					const struct cxi_rgroup_attr *attr);
+int cxi_rgroup_dec_refcount(struct cxi_rgroup *rgroup);
+int cxi_rgroup_add_resource(struct cxi_rgroup *rgroup,
+			    enum cxi_resource_type resource_type,
+			    const struct cxi_resource_limits *limits);
+int cxi_rgroup_add_ac_entry(struct cxi_rgroup *rgroup,
+			    enum cxi_ac_type type,
+			    const union cxi_ac_data *data,
+			    unsigned int *ac_entry_id);
+int cxi_rgroup_update_ac_entry(struct cxi_rgroup *rgroup,
+			       enum cxi_ac_type type,
+			       const union cxi_ac_data *data,
+			       unsigned int *ac_entry_id);
+
+struct cxi_ct *cxi_ct_alloc(struct cxi_lni *lni, struct c_ct_writeback *wb,
+			    bool is_user);
+int cxi_ct_wb_update(struct cxi_ct *ct, struct c_ct_writeback *wb);
+void cxi_ct_free(struct cxi_ct *ct);
+int cxi_ct_user_info(struct cxi_ct *ct, phys_addr_t *csr_addr,
+		     size_t *csr_size);
+
+struct cxi_lni *cxi_lni_alloc(struct cxi_dev *dev, unsigned int svc_id);
+int cxi_lni_free(struct cxi_lni *lni);
+
+struct cxi_cp *cxi_trig_cp_alloc(struct cxi_lni *lni, unsigned int vni_pcp,
+				 unsigned int tc,
+				 enum cxi_traffic_class_type tc_type,
+				 enum cxi_trig_cp cp_type);
+struct cxi_cp *cxi_cp_alloc(struct cxi_lni *lni, unsigned int vni_pcp,
+			    unsigned int tc,
+			    enum cxi_traffic_class_type tc_type);
+void cxi_cp_free(struct cxi_cp *cp);
+
+int cxi_cp_modify(struct cxi_cp *cp, unsigned int vni_pcp);
+
+int cxi_domain_reserve(struct cxi_lni *lni, unsigned int vni, unsigned int pid,
+		       unsigned int count);
+struct cxi_domain *cxi_domain_alloc(struct cxi_lni *lni, unsigned int vni,
+				    unsigned int pid);
+void cxi_domain_free(struct cxi_domain *domain);
+
+struct cxi_md *cxi_map(struct cxi_lni *lni, uintptr_t va, size_t len,
+		       u32 flags, const struct cxi_md_hints *hints);
+struct cxi_md *cxi_map_iov(struct cxi_lni *lni, const struct iov_iter *iter,
+			   u32 flags);
+struct cxi_md *cxi_map_sgtable(struct cxi_lni *lni, struct sg_table *sgt,
+			       u32 flags);
+int cxi_update_sgtable(struct cxi_md *md, struct sg_table *sgt);
+int cxi_unmap(struct cxi_md *md);
+int cxi_update_md(struct cxi_md *md, uintptr_t va, size_t len, u32 flags);
+int cxi_phys_lac_alloc(struct cxi_lni *lni);
+void cxi_phys_lac_free(struct cxi_lni *lni, int lac);
+int cxi_clear_md(struct cxi_md *md);
+int cxi_update_iov(struct cxi_md *md, const struct iov_iter *iter);
+
+struct cxi_eq *cxi_eq_alloc(struct cxi_lni *lni, const struct cxi_md *md,
+			    const struct cxi_eq_attr *attr,
+			    void (*event_cb)(void *cb_data),
+			    void *event_cb_data,
+			    void (*status_cb)(void *cb_data),
+			    void *status_cb_data);
+int cxi_eq_adjust_reserved_fc(struct cxi_eq *eq, int value);
+int cxi_eq_user_info(struct cxi_eq *evtq,
+		     phys_addr_t *csr_addr, size_t *csr_size);
+int cxi_eq_free(struct cxi_eq *evtq);
+
+int cxi_eq_resize(struct cxi_eq *evtq, void *queue, size_t queue_len,
+		  struct cxi_md *queue_md);
+int cxi_eq_resize_complete(struct cxi_eq *evtq);
+struct cxi_cq *cxi_cq_alloc(struct cxi_lni *lni, struct cxi_eq *evtq,
+			    const struct cxi_cq_alloc_opts *opts,
+			    int numa_node);
+struct cxi_cq *cxi_cq_alloc_buf(struct cxi_lni *lni, struct cxi_eq *evtq,
+				const struct cxi_cq_alloc_opts_buf *opts,
+				int numa_node);
+int cxi_cq_user_info(struct cxi_cq *cmdq,
+		     size_t *cmds_size, struct page **cmds_pages,
+		     phys_addr_t *wp_addr, size_t *wp_addr_size);
+void cxi_cq_free(struct cxi_cq *cmdq);
+unsigned int cxi_cq_ack_counter(struct cxi_cq *cq);
+
+struct cxi_pte *cxi_pte_alloc(struct cxi_lni *lni, struct cxi_eq *evtq,
+			      const struct cxi_pt_alloc_opts *opts);
+void cxi_pte_free(struct cxi_pte *pt);
+int cxi_pte_map(struct cxi_pte *pt, struct cxi_domain *domain,
+		unsigned int pid_offset, bool is_multicast,
+		unsigned int *pt_index);
+int cxi_pte_unmap(struct cxi_pte *pt, struct cxi_domain *domain, int pt_index);
+void cxi_pte_le_invalidate(struct cxi_pte *pt, unsigned int buffer_id,
+			   enum c_ptl_list list);
+int cxi_pte_status(struct cxi_pte *pte, struct cxi_pte_status *status);
+int cxi_pte_transition_sm(struct cxi_pte *pt, unsigned int drop_count);
+int cxi_inbound_wait(struct cxi_dev *cdev);
+
+int cxi_svc_alloc(struct cxi_dev *dev, const struct cxi_svc_desc *svc,
+		  struct cxi_svc_fail_info *fail_info, char *name);
+int cxi_svc_destroy(struct cxi_dev *dev, unsigned int svc_id);
+int cxi_svc_list_get(struct cxi_dev *dev, int count,
+		     struct cxi_svc_desc *svc_list);
+int cxi_svc_update(struct cxi_dev *dev, const struct cxi_svc_desc *svc);
+int cxi_svc_set_lpr(struct cxi_dev *dev, unsigned int svc_id,
+		    unsigned int lnis_per_rgid);
+int cxi_svc_get_lpr(struct cxi_dev *dev, unsigned int svc_id);
+int cxi_svc_get(struct cxi_dev *dev, unsigned int svc_id,
+		struct cxi_svc_desc *svc_desc);
+int cxi_svc_rsrc_list_get(struct cxi_dev *dev, int count,
+			  struct cxi_rsrc_use *rsrc_list);
+int cxi_svc_rsrc_get(struct cxi_dev *dev, unsigned int svc_id,
+		     struct cxi_rsrc_use *rsrc_use);
+int cxi_svc_set_exclusive_cp(struct cxi_dev *dev, unsigned int svc_id,
+			     bool exclusive_cp);
+int cxi_svc_get_exclusive_cp(struct cxi_dev *dev, unsigned int svc_id);
+int cxi_svc_enable(struct cxi_dev *dev, unsigned int svc_id, bool enable);
+int cxi_svc_set_vni_range(struct cxi_dev *dev, unsigned int svc_id,
+			  unsigned int vni_min, unsigned int vni_max);
+int cxi_svc_get_vni_range(struct cxi_dev *dev, unsigned int svc_id,
+			  unsigned int *vni_min, unsigned int *vni_max);
+int cxi_tc_cfg(struct cxi_dev *dev, unsigned int tc,
+	       enum cxi_traffic_class_type tc_type);
+int cxi_tc_validate(struct cxi_dev *dev, unsigned int tc,
+		    enum cxi_traffic_class_type tc_type);
+int cxi_tc_clear(struct cxi_dev *dev, unsigned int tc,
+		 enum cxi_traffic_class_type tc_type);
+struct cxi_tc_info {
+	u32 tc;
+	u32 tc_type;
+	u32 res_req_dscp;
+	u32 unres_req_dscp;
+	u32 res_rsp_dscp;
+	u32 unres_rsp_dscp;
+	u32 req_pcp;
+	u32 rsp_pcp;
+	u32 ocuset;
+	u32 cq_tc;
+	u32 req_bc;
+};
+int cxi_tc_list(struct cxi_dev *dev, struct cxi_tc_info *entries,
+		unsigned int max_entries, unsigned int *count);
+int cxi_job_tc_bind(struct cxi_dev *dev, unsigned int job_id,
+		    unsigned int svc_id, unsigned int tc,
+		    enum cxi_traffic_class_type tc_type, bool create_tc,
+		    const struct cxi_rsrc_limits *limits,
+		    unsigned int *bound_svc_id, bool *created_tc);
+int cxi_get_tc_req_pcp(struct cxi_dev *dev, unsigned int tc);
+int cxi_dev_info_get(struct cxi_dev *dev,
+		     struct cxi_dev_info_use *devinfo);
+
+struct cxi_client {
+	/* Add and remove devices callback */
+	int (*add)(struct cxi_dev *dev);
+	void (*remove)(struct cxi_dev *dev);
+
+	/* Asynchronous events handler */
+	void (*async_event)(struct cxi_dev *cxi_dev,
+			    enum cxi_async_event event);
+
+	/* For the core */
+	struct list_head list;
+};
+int cxi_register_client(struct cxi_client *client);
+void cxi_unregister_client(struct cxi_client *client);
+void cxi_set_nid(struct cxi_dev *dev, u32 nid);
+void cxi_set_nid_from_mac(struct cxi_dev *cdev, const u8 *addr);
+
+typedef int (*cxi_msg_relay_t)(void *data, unsigned int vf_num,
+			       const void *req, size_t req_len, uid_t uid, gid_t gid,
+			       void *rsp, size_t *rsp_len);
+int cxi_register_msg_relay(struct cxi_dev *cdev, cxi_msg_relay_t msg_relay,
+			   void *msg_relay_data);
+int cxi_unregister_msg_relay(struct cxi_dev *cdev);
+int cxi_send_msg_to_pf(struct cxi_dev *cdev, const void *req,
+		       size_t req_len, void *rsp, size_t *rsp_len);
+int cxi_send_msg_to_vf(struct cxi_dev *cdev, int vf_num, const void *req,
+		       size_t req_len, void *rsp, size_t *rsp_len);
+
+int cxi_set_max_eth_rxsize(struct cxi_dev *cdev, unsigned int max_std_size);
+int cxi_get_max_eth_rxsize(struct cxi_dev *cdev);
+int cxi_eth_add_mac(struct cxi_dev *cdev, struct cxi_eth_res *res,
+		    u64 mac_addr, bool is_ptp);
+int cxi_eth_set_promiscuous(struct cxi_dev *cdev, struct cxi_eth_res *res);
+int cxi_eth_set_all_multi(struct cxi_dev *cdev, struct cxi_eth_res *res);
+void cxi_eth_set_list_invalidate_all(struct cxi_dev *cdev,
+				     struct cxi_eth_res *res);
+void cxi_eth_set_indir_table(struct cxi_dev *cdev, struct cxi_eth_res *res);
+void cxi_eth_clear_indir_table(struct cxi_dev *cdev, struct cxi_eth_res *res);
+void cxi_eth_get_hash_key(struct cxi_dev *cdev, u8 *key);
+
+/* RMU Ethernet API */
+struct cxi_rmu_eth *cxi_rmu_eth_alloc(struct cxi_dev *cdev);
+
+void cxi_rmu_eth_free(struct cxi_rmu_eth *rmu_eth);
+
+int cxi_rmu_eth_add_mac_filter(struct cxi_rmu_eth *rmu_eth, unsigned int idx,
+			       u64 mac_addr, struct cxi_pte *pte, bool use_rss);
+int cxi_rmu_eth_add_all_mcast_filter(struct cxi_rmu_eth *rmu_eth, unsigned int idx,
+				     struct cxi_pte *pte, bool use_rss);
+int cxi_rmu_eth_add_promiscuous_filter(struct cxi_rmu_eth *rmu_eth, unsigned int idx,
+				       struct cxi_pte *pte, bool use_rss);
+int cxi_rmu_eth_remove_filter(struct cxi_rmu_eth *rmu_eth, unsigned int idx);
+int cxi_rmu_eth_set_rss_queues(struct cxi_rmu_eth *rmu_eth, unsigned int num_queues,
+			       struct cxi_pte **ptes, u32 hash_types);
+int cxi_rmu_eth_set_indir_table(struct cxi_rmu_eth *rmu_eth, const u8 *indir_table,
+				unsigned int indir_size);
+void cxi_rmu_eth_get_hash_key(struct cxi_dev *cdev, u8 *key);
+
+/* Ethernet utility functions */
+void cxi_eth_get_pause(struct cxi_dev *cdev, struct ethtool_pauseparam *pause);
+void cxi_eth_set_pause(struct cxi_dev *cdev, const struct ethtool_pauseparam *pause);
+int cxi_eth_cfg_timestamp(struct cxi_dev *cdev,
+			  struct hwtstamp_config *config);
+int cxi_eth_get_tx_timestamp(struct cxi_dev *cdev,
+			     struct skb_shared_hwtstamps *tstamps);
+void cxi_set_ethernet_threshold(struct cxi_dev *cdev, unsigned int threshold);
+void cxi_set_roce_rcv_seg(struct cxi_dev *cdev, bool enable);
+void cxi_set_eth_name(struct cxi_dev *cdev, const char *name);
+
+void cxi_get_csrs_range(struct cxi_dev *cdev, phys_addr_t *base, size_t *len);
+
+struct cxi_eth_info {
+	/* The size at which an Ethernet packet is segmented. Each
+	 * segment of the packet will be this size.
+	 */
+	unsigned int max_segment_size;
+
+	/* The device's min_free_shift setting */
+	unsigned int min_free_shift;
+
+	/* Default MAC address, as programmed in the uC */
+	u8 default_mac_addr[ETH_ALEN];
+
+	/* Current copy of the QSFP eeprom, with its length. If length
+	 * is 0, the data is not valid.
+	 */
+	u8 qsfp_eeprom[ETH_MODULE_SFF_8436_LEN];
+	unsigned int qsfp_eeprom_len;
+
+	/* Firmware version, as returned by the uC for FW_QSPI_BLOB. */
+	char fw_version[16];
+
+	/* Expansion ROM version, as returned by the uC for FW_OPROM. */
+	char erom_version[16];
+
+	int ptp_clock_index;
+};
+void cxi_eth_devinfo(struct cxi_dev *cdev, struct cxi_eth_info *eth_info);
+int cxi_get_qsfp_data(struct cxi_dev *cdev, u32 offset, u32 len, u32 page, u8 *data);
+
+int cxi_program_firmware(struct cxi_dev *cdev, const struct firmware *fw);
+
+int cxi_sbus_op(struct cxi_dev *cdev, const struct cxi_sbus_op_params *params,
+		u32 *rsp_data, u8 *result_code, u8 *overrun);
+int cxi_sbus_op_reset(struct cxi_dev *cdev);
+int cxi_serdes_op(struct cxi_dev *cdev, u64 serdes_sel, u64 op, u64 data,
+		  int timeout, unsigned int flags, u16 *result);
+
+bool cxi_is_link_up(struct cxi_dev *cdev);
+void cxi_sbl_disable_pml_recovery(struct cxi_dev *cdev, bool disable);
+
+int cxi_dmac_desc_set_alloc(struct cxi_dev *cdev, u16 num_descs,
+			    const char *name);
+int cxi_dmac_desc_set_reserve(struct cxi_dev *cdev, u16 num_descs,
+			      u16 desc_idx, const char *name);
+int cxi_dmac_desc_set_free(struct cxi_dev *cdev, int set_id);
+int cxi_dmac_desc_set_reset(struct cxi_dev *cdev, int set_id);
+int cxi_dmac_desc_set_add(struct cxi_dev *cdev, int set_id, dma_addr_t dst,
+			  u32 src, size_t len);
+int cxi_dmac_xfer(struct cxi_dev *cdev, int set_id);
+
+int cxi_telem_get_selected(struct cxi_dev *cdev, const unsigned int *items,
+			   u64 *data, unsigned int count);
+int cxi_telem_read(struct cxi_dev *cdev, const u64 *items, u64 *values,
+		   u64 *timestamps, unsigned int count);
+
+bool cxi_retry_handler_running(struct cxi_dev *cdev);
+
+void cxi_set_led_beacon(struct cxi_dev *cdev, bool state);
+
+int cxi_get_lpe_append_credits(unsigned int lpe_cdt_thresh_id);
+
+#endif	/* _LINUX_CXI_H */
diff --git a/include/linux/hpe/cxi/cxi_defs.h b/include/linux/hpe/cxi/cxi_defs.h
new file mode 100644
index 000000000000..f163ec0ecb41
--- /dev/null
+++ b/include/linux/hpe/cxi/cxi_defs.h
@@ -0,0 +1,1506 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/* Copyright 2021, 2024-2026 Hewlett Packard Enterprise Development LP */
+
+#ifndef __UAPI_CXI_ABI_H
+#define __UAPI_CXI_ABI_H
+
+#include <linux/types.h>
+#include <uapi/ethernet/cassini_user_defs.h>
+
+/* Information for mmap */
+struct cxi_mminfo {
+    u64 offset;
+    u64 size;
+};
+
+enum cxi_command_opcode {
+		CXI_OP_INVALID,
+
+		CXI_OP_LNI_ALLOC,
+		CXI_OP_LNI_FREE,
+		CXI_OP_DOMAIN_RESERVE,
+		CXI_OP_DOMAIN_ALLOC,
+		CXI_OP_DOMAIN_FREE,
+		CXI_OP_CP_ALLOC,
+		CXI_OP_CP_FREE,
+		CXI_OP_CQ_ALLOC,
+		CXI_OP_CQ_FREE,
+		CXI_OP_CQ_ACK_COUNTER,
+		CXI_OP_ATU_MAP,
+		CXI_OP_ATU_UNMAP,
+		CXI_OP_EQ_ALLOC,
+		CXI_OP_EQ_FREE,
+		CXI_OP_EQ_RESIZE,
+		CXI_OP_EQ_RESIZE_COMPLETE,
+		CXI_OP_PTE_ALLOC,
+		CXI_OP_PTE_FREE,
+		CXI_OP_PTE_MAP,
+		CXI_OP_PTE_UNMAP,
+		CXI_OP_PTE_LE_INVALIDATE,
+		CXI_OP_PTE_STATUS,
+		CXI_OP_WAIT_ALLOC,
+		CXI_OP_WAIT_FREE,
+		CXI_OP_CT_ALLOC,
+		CXI_OP_CT_FREE,
+		CXI_OP_SVC_LIST_GET,
+		CXI_OP_SVC_ALLOC,
+		CXI_OP_SVC_DESTROY,
+		CXI_OP_MAP_CSRS,
+		CXI_OP_SBUS_OP_RESET,
+		CXI_OP_SBUS_OP,
+		CXI_OP_SERDES_OP,
+		CXI_OP_GET_DEV_PROPERTIES,
+		_OBSOLETED_CXI_OP_MAP_TELEMETRY,
+		_OBSOLETED_CXI_OP_UNMAP_TELEMETRY,
+		CXI_OP_EQ_ADJUST_RESERVED_FC,
+		CXI_OP_CT_WB_UPDATE,
+		_OBSOLETED_CXI_OP_RESERVE_CNTR_POOL_ID,
+		_OBSOLETED_CXI_OP_RELEASE_CNTR_POOL_ID,
+		_OBSOLETED_CXI_OP_GET_TELEMETRY_REFRESH_INTERVAL,
+		_OBSOLETED_CXI_OP_SET_TELEMETRY_REFRESH_INTERVAL,
+		CXI_OP_INBOUND_WAIT,
+		CXI_OP_SVC_UPDATE,
+		CXI_OP_SVC_GET,
+		_OBSOLETED_CXI_OP_START_TELEMETRY,
+		_OBSOLETED_CXI_OP_STOP_TELEMETRY,
+		CXI_OP_PTE_TRANSITION_SM,
+		CXI_OP_SVC_RSRC_LIST_GET,
+		CXI_OP_SVC_RSRC_GET,
+		CXI_OP_ATU_UPDATE_MD,
+		CXI_OP_DEV_INFO_GET,
+
+		CXI_OP_SVC_SET_LPR,
+		CXI_OP_SVC_GET_LPR,
+
+		CXI_OP_DEV_ALLOC_RX_PROFILE,
+		CXI_OP_DEV_GET_RX_PROFILE_IDS,
+
+		CXI_OP_RX_PROFILE_RELEASE,
+		CXI_OP_RX_PROFILE_REVOKE,
+		CXI_OP_RX_PROFILE_GET_INFO,
+
+		CXI_OP_RX_PROFILE_ADD_AC_ENTRY,
+		CXI_OP_RX_PROFILE_REMOVE_AC_ENTRY,
+		CXI_OP_RX_PROFILE_GET_AC_ENTRY_IDS,
+		CXI_OP_RX_PROFILE_GET_AC_ENTRY_DATA_BY_ID,
+		CXI_OP_RX_PROFILE_GET_AC_ENTRY_ID_BY_DATA,
+		CXI_OP_RX_PROFILE_GET_AC_ENTRY_ID_BY_USER,
+
+		CXI_OP_DEV_ALLOC_TX_PROFILE,
+		CXI_OP_DEV_GET_TX_PROFILE_IDS,
+
+		CXI_OP_TX_PROFILE_RELEASE,
+		CXI_OP_TX_PROFILE_REVOKE,
+		CXI_OP_TX_PROFILE_GET_INFO,
+
+		CXI_OP_TX_PROFILE_ADD_AC_ENTRY,
+		CXI_OP_TX_PROFILE_REMOVE_AC_ENTRY,
+		CXI_OP_TX_PROFILE_GET_AC_ENTRY_IDS,
+		CXI_OP_TX_PROFILE_GET_AC_ENTRY_DATA_BY_ID,
+		CXI_OP_TX_PROFILE_GET_AC_ENTRY_ID_BY_DATA,
+		CXI_OP_TX_PROFILE_GET_AC_ENTRY_ID_BY_USER,
+
+		CXI_OP_CP_MODIFY,
+		CXI_OP_SVC_SET_EXCLUSIVE_CP,
+		CXI_OP_SVC_GET_EXCLUSIVE_CP,
+		CXI_OP_SVC_ENABLE,
+		CXI_OP_SVC_SET_VNI_RANGE,
+		CXI_OP_SVC_GET_VNI_RANGE,
+
+		CXI_OP_TRIG_CP_ALLOC,
+
+		CXI_OP_SVC_SET_NETNS,
+		CXI_OP_SVC_GET_NETNS,
+		CXI_OP_CQ_ALLOC_BUF,
+
+
+		CXI_OP_VF_GET_TOKEN,
+		CXI_OP_PHYS_LAC_ALLOC,
+		CXI_OP_PHYS_LAC_FREE,
+		CXI_OP_ATU_MAP_SGT,
+		CXI_OP_ETH_DEV_INFO_GET,
+		CXI_OP_ETH_TC_REQ_PCP_GET,
+		CXI_OP_ETH_PAUSE_GET,
+		CXI_OP_ETH_MAX_RXSIZE_GET,
+		CXI_OP_ETH_LINK_STATE_GET,
+		CXI_OP_RMU_ETH_ALLOC,
+		CXI_OP_RMU_ETH_FREE,
+		CXI_OP_RMU_ETH_HASH_KEY_GET,
+		CXI_OP_RMU_ETH_ADD_MAC_FILTER,
+		CXI_OP_RMU_ETH_REMOVE_FILTER,
+		CXI_OP_RMU_ETH_ADD_PROMISC_FILTER,
+		CXI_OP_RMU_ETH_SET_RSS_QUEUES,
+		CXI_OP_RMU_ETH_SET_INDIR_TABLE,
+		CXI_OP_RMU_ETH_ADD_ALL_MCAST_FILTER,
+
+		CXI_OP_MAX,
+};
+
+struct cxi_common_cmd {
+	enum cxi_command_opcode op;
+	void __user *resp;
+};
+
+struct cxi_lni_alloc_cmd {
+	enum cxi_command_opcode op;
+	void __user  *resp;
+	u32 svc_id;
+};
+
+struct cxi_lni_alloc_resp {
+	u32 lni;
+};
+
+struct cxi_lni_free_cmd {
+	enum cxi_command_opcode op;
+	u32 lni;
+};
+
+struct cxi_rmu_eth_alloc_cmd {
+	enum cxi_command_opcode op;
+	void __user  *resp;
+};
+
+struct cxi_rmu_eth_alloc_resp {
+	u32 rmu_eth;
+	u32 id;
+};
+
+struct cxi_rmu_eth_free_cmd {
+	enum cxi_command_opcode op;
+	void __user  *resp;
+	u32 rmu_eth;
+};
+
+struct cxi_rmu_eth_hash_key_get_cmd {
+	enum cxi_command_opcode op;
+	void __user *resp;
+};
+
+/* Size of RSS key in bytes, rounded up from 351 bits */
+#define CXI_ETH_HASH_KEY_SIZE 44
+
+struct cxi_rmu_eth_get_hash_key_resp {
+	u8 key[CXI_ETH_HASH_KEY_SIZE];
+};
+
+struct cxi_rmu_eth_add_mac_filter_cmd {
+	enum cxi_command_opcode op;
+	void __user  *resp;
+	u32 rmu_eth;
+	u32 idx;
+	u32 pte;
+	u64 mac_addr;
+	bool use_rss;
+};
+
+struct cxi_rmu_eth_add_promisc_filter_cmd {
+	enum cxi_command_opcode op;
+	void __user  *resp;
+	u32 rmu_eth;
+	u32 idx;
+	u32 pte;
+	bool use_rss;
+};
+
+struct cxi_rmu_eth_add_all_mcast_filter_cmd {
+	enum cxi_command_opcode op;
+	void __user  *resp;
+	u32 rmu_eth;
+	u32 idx;
+	u32 pte;
+	bool use_rss;
+};
+
+struct cxi_rmu_eth_remove_filter_cmd {
+	enum cxi_command_opcode op;
+	void __user  *resp;
+	u32 rmu_eth;
+	u32 idx;
+};
+
+#define CXI_ETH_MAX_RSS_QUEUES 64
+
+struct cxi_rmu_eth_set_rss_queues_cmd {
+	enum cxi_command_opcode op;
+	void __user  *resp;
+	u32 rmu_eth;
+	u32 num_queues;
+	u32 ptes[CXI_ETH_MAX_RSS_QUEUES];
+	u32 hash_types;
+};
+
+#define CXI_ETH_MAX_INDIR_ENTRIES 64
+
+struct cxi_rmu_eth_set_indir_table_cmd {
+	enum cxi_command_opcode op;
+	void __user  *resp;
+	u32 rmu_eth;
+	u32 indir_size;
+	u8 indir_table[CXI_ETH_MAX_INDIR_ENTRIES];
+};
+
+struct cxi_domain_reserve_cmd {
+	enum cxi_command_opcode op;
+	void __user  *resp;
+
+	u32 lni;
+	u32 vni;
+	u32 pid;
+	u32 count;
+};
+
+struct cxi_domain_reserve_resp {
+	u32 pid;
+};
+
+struct cxi_domain_alloc_cmd {
+	enum cxi_command_opcode op;
+	void __user  *resp;
+
+	u32 lni;
+	u32 vni;
+	u32 pid;
+};
+
+struct cxi_domain_alloc_resp {
+	u32 domain;
+	u32 vni;
+	u32 pid;
+};
+
+struct cxi_domain_free_cmd {
+	enum cxi_command_opcode op;
+	u32 domain;
+};
+
+struct cxi_ct_alloc_cmd {
+	enum cxi_command_opcode op;
+	void __user *resp;
+
+	/* LNI to associate with the counting event. */
+	u32 lni;
+
+	/* User writeback buffer used by counting event. */
+	struct c_ct_writeback __user *wb;
+};
+
+struct cxi_ct_wb_update_cmd {
+	enum cxi_command_opcode op;
+	u32 ctn;
+
+	/* User writeback buffer used by counting event. */
+	struct c_ct_writeback __user *wb;
+};
+
+struct cxi_ct_alloc_resp {
+	/* Allocated counting event number. */
+	u32 ctn;
+	struct cxi_mminfo doorbell;
+};
+
+struct cxi_ct_free_cmd {
+	enum cxi_command_opcode op;
+	u32 ctn;
+};
+
+enum cxi_traffic_class {
+	/* HRP traffic classes. */
+	CXI_TC_DEDICATED_ACCESS,
+	CXI_TC_LOW_LATENCY,
+	CXI_TC_BULK_DATA,
+	CXI_TC_BEST_EFFORT,
+
+	/* Ethernet specific traffic class. */
+	CXI_TC_ETH,
+	CXI_TC_MAX,
+};
+
+enum cxi_eth_traffic_class {
+	CXI_ETH_TC1 = CXI_TC_MAX,
+	CXI_ETH_SHARED,
+	CXI_ETH_TC2,
+};
+
+enum cxi_traffic_class_type {
+	CXI_TC_TYPE_DEFAULT,
+	CXI_TC_TYPE_HRP,
+	CXI_TC_TYPE_RESTRICTED,
+	CXI_TC_TYPE_COLL_LEAF,
+	CXI_TC_TYPE_MAX,
+};
+
+/* Helper structure for mapping multicast addresses to a PtlTE */
+union cxi_pte_map_offset {
+	struct {
+		u32 mcast_id:C_DFA_MULTICAST_ID_BITS;
+		u32 mcast_pte_index:C_DFA_INDEX_EXT_BITS;
+	};
+	u32 uintval;
+};
+
+/* CXI CQ status update policies. Policies are listed from most aggressive to
+ * least.
+ *
+ * CXI_CQ_UPDATE_ALWAYS: Update when the hardware read pointer advances.
+ * CXI_CQ_UPDATE_HIGH_FREQ_EMPTY: Update at a high frequency and when the CQ is
+ * empty.
+ * CXI_CQ_UPDATE_LOW_FREQ_EMPTY: Update at a low frequency and when the CQ is
+ * empty.
+ * CXI_CQ_UPDATE_LOW_FREQ: Update at a low frequency.
+ */
+enum cxi_cq_update_policy {
+	CXI_CQ_UPDATE_ALWAYS,
+	CXI_CQ_UPDATE_HIGH_FREQ_EMPTY,
+	CXI_CQ_UPDATE_LOW_FREQ_EMPTY,
+	CXI_CQ_UPDATE_LOW_FREQ,
+};
+
+struct cxi_tc_cfg_cmd {
+	enum cxi_command_opcode op;
+	void __user *resp;
+
+	/* TC Label (Key) */
+	u32 tc;
+
+	/* Restricted packet HRP */
+	bool hrp;
+
+	/* Restricted DSCP */
+	u32 rdscp;
+
+	/* Unrestricted DSCP */
+	u32 udscp;
+
+	/* OCU SET Index */
+	u32 ocu_set_idx;
+
+	/* CQ specific TC value. */
+	u32 cq_tc;
+};
+
+struct cxi_tc_cfg_resp {
+	/* Traffic Class ID */
+	u32 id;
+};
+
+struct cxi_tc_clear_cmd {
+	enum cxi_command_opcode op;
+
+	/* Traffic Class ID */
+	u32 id;
+};
+
+struct cxi_cp_alloc_cmd {
+	enum cxi_command_opcode op;
+	void __user *resp;
+
+	/* LNI to associate with the CP. */
+	u32 lni;
+
+	/* VNI to associate with the CP. */
+	u32 vni;
+
+	/* Traffic class to associate with the CP. */
+	enum cxi_traffic_class tc;
+
+	/* Traffic class type to associated with the CP. */
+	enum cxi_traffic_class_type tc_type;
+};
+
+enum cxi_trig_cp {
+	TRIG_LCID,
+	NON_TRIG_LCID,
+	ANY_LCID,
+};
+
+struct cxi_trig_cp_alloc_cmd {
+	enum cxi_command_opcode op;
+	void __user *resp;
+
+	/* LNI to associate with the CP. */
+	u32 lni;
+
+	/* VNI to associate with the CP. */
+	u32 vni;
+
+	/* Traffic class to associate with the CP. */
+	enum cxi_traffic_class tc;
+
+	/* Traffic class type to associated with the CP. */
+	enum cxi_traffic_class_type tc_type;
+
+	/* This CP is for cmdq of triggered, non-triggered or any cmdq. */
+	enum cxi_trig_cp cp_type;
+};
+
+struct cxi_cp_alloc_resp {
+	u32 cp_hndl;
+	u32 lcid;
+};
+
+struct cxi_cp_free_cmd {
+	enum cxi_command_opcode op;
+	u32 cp_hndl;
+};
+
+struct cxi_cp_modify_cmd {
+	enum cxi_command_opcode op;
+	u32 cp_hndl;
+
+	/* VNI to associate with the CP. */
+	u32 vni;
+};
+
+#define CXI_MAX_CQ_COUNT (1 << 16)
+
+enum {
+	/* CQ is allocated for the current user process. Driver use only. */
+	CXI_CQ_USER = (1 << 0),
+
+	/* Whether this is a transmit or target CQ */
+	CXI_CQ_IS_TX = (1 << 1),
+
+	/* Whether that CQ can send RAW ethernet packets. For TX CQ in
+	 * privileged clients only.
+	 */
+	CXI_CQ_TX_ETHERNET = (1 << 2),
+
+	/* If set, the TX queue is reserved for triggered commands. */
+	CXI_CQ_TX_WITH_TRIG_CMDS= (1 << 3),
+};
+
+struct cxi_cq_alloc_opts {
+	/* Requested number of 64-byte entries in the command
+	 * queue. Up to CXI_MAX_CQ_COUNT.
+	 */
+	u32 count;
+
+	/* CQ status update policy. */
+	enum cxi_cq_update_policy policy;
+
+	/* Statistics counter pool for the CQ. */
+	u32 stat_cnt_pool;
+
+	/* Flags controlling CQ behavior (See CXI_CQ_*). */
+	u32 flags;
+
+	/* Initial Local Communication ID, for transmit CQ only. */
+	u32 lcid;
+
+	/* Index of one of the 4 LPE credits defined in the CXI driver
+	 * by the tg_threshold module parameter. Must be 0 to 3, with
+	 * 0 being the default.
+	 */
+	u32 lpe_cdt_thresh_id;
+};
+
+#define INVALID_DMABUF_FD (-1)
+struct cxi_cq_alloc_opts_buf {
+	struct cxi_cq_alloc_opts opts;
+
+	/* Pointer to an optional user buffer. */
+	void __user *buf;
+
+	/* If set, buf is allocated in host mem. Otherwise, device mem. */
+	bool is_host_mem;
+
+	/* dmabuf file descriptor. INVALID_DMABUF_FD if not dmabuf. */
+	s32 dmabuf_fd;
+
+	u64 dmabuf_offset;
+};
+
+struct cxi_cq_alloc_cmd {
+	enum cxi_command_opcode op;
+	void  __user *resp;
+
+	u32 lni;  /* LNI to associate with the event queue */
+
+	/* EQ handle to report CQ errors to. May be set to C_EQ_NONE. */
+	u32 eq;
+
+	struct cxi_cq_alloc_opts opts;
+};
+
+struct cxi_cq_alloc_buf_cmd {
+	enum cxi_command_opcode op;
+	void  __user *resp;
+
+	u32 lni;  /* LNI to associate with the event queue */
+
+	/* EQ handle to report CQ errors to. May be set to C_EQ_NONE. */
+	u32 eq;
+
+	struct cxi_cq_alloc_opts_buf opts;
+};
+
+struct cxi_cq_alloc_resp {
+	u32 cq;
+
+	/* Number of 64 bytes entries in the queue */
+	u32 count;
+
+	/* mmap info for the array of commands and the write pointer
+	 * for that CQ
+	 */
+	struct cxi_mminfo cmds;
+	struct cxi_mminfo wp_addr;
+};
+
+struct cxi_cq_free_cmd {
+	enum cxi_command_opcode op;
+	u32 cq;
+};
+
+struct cxi_cq_ack_counter_resp {
+	u32 ack_counter;
+};
+
+struct cxi_cq_ack_counter_cmd {
+	enum cxi_command_opcode op;
+	void  __user *resp;
+	u32 cq;
+};
+
+enum cxi_atu_map_flags {
+	CXI_MAP_PIN       = (1 << 0),
+	CXI_MAP_ATS       = (1 << 1),
+	CXI_MAP_WRITE     = (1 << 2),
+	CXI_MAP_READ      = (1 << 3),
+	CXI_MAP_FAULT     = (1 << 4),
+	CXI_MAP_NOCACHE   = (1 << 5),
+	CXI_MAP_USER_ADDR = (1 << 6),
+	CXI_MAP_ATS_PT    = (1 << 7),
+	CXI_MAP_ATS_DYN   = (1 << 8),
+	CXI_MAP_DEVICE    = (1 << 9),
+	CXI_MAP_UNUSED    = (1 << 10),
+	CXI_MAP_ALLOC_MD  = (1 << 11),
+	CXI_MAP_PREFETCH  = (1 << 12),
+};
+
+/* PTE allocation options */
+struct cxi_pt_alloc_opts {
+	u64 en_event_match         :  1;
+	u64 clr_remote_offset      :  1;
+	u64 en_flowctrl            :  1;
+	u64 use_long_event         :  1;
+	u64 lossless               :  1;
+	u64 en_restricted_unicast_lm :  1;
+	u64 use_logical            :  1;
+	u64 is_matching            :  1;
+	u64 do_space_check         :  1;
+	u64 en_align_lm            :  1;
+	u64 en_sw_hw_st_chng       :  1;
+	u64 ethernet               :  1;
+	u64 signal_invalid         :  1;
+	u64 signal_underflow       :  1;
+	u64 signal_overflow        :  1;
+	u64 signal_inexact         :  1;
+	u64 en_match_on_vni        :  1;
+};
+
+/* CXI Memory Descriptor */
+struct cxi_md {
+	u64      iova;       /* aligned IO virtual address */
+	u64      va;         /* aligned virtual address */
+	size_t   len;        /* aligned length */
+	u8       lac;        /* logical address context */
+	s32    page_shift; /* base page size */
+	s32    huge_shift; /* huge page size */
+	u32      id;
+};
+
+/**
+ * struct cxi_cp - Communication profile.
+ *
+ * @vni_pcp: Virtual Network Identifier or PCP
+ * @tc: Best practice traffic class
+ * @hrp: Restricted packet HRP enable
+ * @lcid: Communication profile LCID
+ */
+struct cxi_cp {
+	union {
+		u32 vni;	/* Deprecated */
+		u32 vni_pcp;
+	};
+	enum cxi_traffic_class tc;
+	enum cxi_traffic_class_type tc_type;
+	u32 lcid;
+};
+
+struct cxi_md_hints {
+	s32 page_shift; /* base page size */
+	s32 huge_shift; /* huge page size */
+	s32 ptg_mode;
+	bool ptg_mode_valid;
+	s32 dmabuf_fd;
+	u64 dmabuf_offset;
+	bool dmabuf_valid;
+};
+
+#define CXI_VA_TO_IOVA(_md, _va) \
+		((_md)->iova + ((u64)(_va) - (_md)->va))
+#define CXI_IOVA_TO_VA(_md, _iova) \
+		((_md)->va + ((u64)(_iova) - (_md)->iova))
+#define CXI_MD_CONTAINS(_md, _va, _len) \
+		((_va) >= (void *)(_md)->va && \
+		 (_va) + (_len) <= (void *)(_md)->va + (_md)->len)
+
+struct cxi_atu_map_cmd {
+	enum cxi_command_opcode op;
+	void __user *resp;
+
+	u32 lni;
+	u64 va;
+	u64 len;
+	u32 flags;
+
+	struct cxi_md_hints hints;
+};
+
+#define CXI_ATU_SGT_MAX_ENTRIES 1400
+
+struct cxi_sgt_entry {
+	u64 dma_addr;
+	u32 dma_len;
+	u32 offset;
+};
+
+struct cxi_atu_map_sgt_cmd {
+	enum cxi_command_opcode op;
+	void __user *resp;
+
+	u32 lni;
+	u32 flags;
+	u32 nents;
+	struct cxi_sgt_entry sge[CXI_ATU_SGT_MAX_ENTRIES];
+};
+
+struct cxi_atu_map_sgt_resp {
+	u32 id;
+	struct cxi_md md;
+};
+
+struct cxi_atu_map_resp {
+	u32 id;
+	struct cxi_md md;
+};
+
+struct cxi_atu_unmap_cmd {
+	enum cxi_command_opcode op;
+
+	u32 id;
+};
+
+struct cxi_atu_update_md_cmd {
+	enum cxi_command_opcode op;
+
+	u32 id;
+	u64 va;
+	u64 len;
+	u32 flags;
+};
+
+enum {
+	/* EQ is allocated for the current user process. Driver use only. */
+	CXI_EQ_USER = (1 << 0),
+
+	/* Configure the EQ buffer for passthrough (no address translation).
+	 * When using passthrough, the queue buffer provided must be backed by
+	 * contiguous physical pages and the MD is ignored. When using
+	 * passthrough, physical pages backing the queue buffer are pinned.
+	 * Using passthrough can alleviate IOMMU cache pressure and eliminate
+	 * translation overhead for event writes.
+	 *
+	 * Kernel threads must use kmalloc'ed addresses. User processes have
+	 * limited visibility into how virtual addresses are mapped. Using a
+	 * single-page sized queue is one way to guarantee that a process'
+	 * queue buffer is contiguous. A mapped hugepage may be used to support
+	 * passthrough with large queue buffers.
+	 */
+	CXI_EQ_PASSTHROUGH = (1 << 1),
+
+	/* Force all initiator events to use the long event format. */
+	CXI_EQ_INIT_LONG = (1 << 2),
+
+	/* Force all target events to use the long event format. */
+	CXI_EQ_TGT_LONG = (1 << 3),
+
+	/* By default, an EQ generates a status write-back when one or more
+	 * events are dropped. Disable status write-backs when events are
+	 * dropped.
+	 */
+	CXI_EQ_DROP_STATUS_DISABLE = (1 << 4),
+
+	/* Enable EQ timestamp events. Timestamp events are periodically
+	 * inserted into event queues, providing a means to bound the time
+	 * interval during which other events arrive in the queue.
+	 */
+	CXI_EQ_TIMESTAMP_EVENTS = (1 << 5),
+
+	/* Disable EQ event combining. */
+	CXI_EQ_EC_DISABLE = (1 << 6),
+
+	/* EQ is to be registered with the PCT block */
+	CXI_EQ_REGISTER_PCT = (1 << 7),
+};
+
+struct cxi_eq_attr {
+	/* Pointer to the event queue buffer. */
+	void *queue;
+
+	/* Length of the event queue buffer. */
+	size_t queue_len;
+
+	/* Flags controlling EQ behavior (See CXI_EQ_*). */
+	u64 flags;
+
+	/* An EQ may be configured to generate a status write-back when the
+	 * event queue reaches a defined fill level. Status information lets
+	 * applications better understand the current condition of the EQ.
+	 *
+	 * An EQ may have up to four fill level status update thresholds
+	 * enabled. The first threshold is defined as a base percentage.
+	 * Subsequent thresholds are defined as the base percentage minus the
+	 * Nth multiple of a percentage delta.  Given a base of 95 and delta of
+	 * 15, the four thresholds are: 95%, 80%, 65% and 50% filled.
+	 *
+	 * Each EQ may specify the number of enabled thresholds, N, where only
+	 * thresholds 0-(N-1) are enabled.  For N of 2, an EQ will trigger a
+	 * fill level status update when it becomes 80% and 95% filled.
+	 */
+
+	/* Status threshold base percentage. */
+	u32 status_thresh_base;
+
+	/* Status threshold percentage delta. */
+	u32 status_thresh_delta;
+
+	/* Count of enabled status thresholds. */
+	u32 status_thresh_count;
+
+	/* EQ event combining buffer expiration delay in nanoseconds. Specify
+	 * 0 to use the default delay. Provide the CXI_EQ_EC_DISABLE flag to
+	 * disable event combining.
+	 */
+	u32 ec_delay;
+
+	/* CPU affinity hs32 used for interrupt generation. */
+	u32 cpu_affinity;
+
+	/* Number of event slots which cannot be used by LPE for incoming
+	 * messages.
+	 */
+	u32 reserved_slots;
+};
+
+#define CXI_MD_NONE 0
+#define CXI_WAIT_NONE 0
+
+struct cxi_eq_alloc_cmd {
+	enum cxi_command_opcode op;
+	void  __user *resp;
+
+	u32 lni; /* LNI to associate with the event queue */
+
+	 /* Memory Descriptor covering event queue buffer. CXI_MD_NONE
+	  * for none.
+	  */
+	u32 queue_md;
+
+	/* Event wait object handle. CXI_WAIT_NONE for none. */
+	u32 event_wait;
+
+	/* Status update wait object handle. CXI_WAIT_NONE for none. */
+	u32 status_wait;
+
+	struct cxi_eq_attr attr;
+};
+
+struct cxi_eq_alloc_resp {
+	u32 eq; /* event queue handle */
+	struct cxi_mminfo csr; /* mmap info for the event queue CSRs */
+};
+
+struct cxi_eq_free_cmd {
+	enum cxi_command_opcode op;
+	u32 eq; /* event queue handle to free */
+};
+
+struct cxi_eq_resize_cmd {
+	enum cxi_command_opcode op;
+
+	/* EQ to resize */
+	u32 eq_hndl;
+
+	/* Pointer to the new event queue buffer. */
+	void *queue;
+
+	/* New event queue buffer length in bytes. */
+	size_t queue_len;
+
+	/* Memory Descriptor covering the new event queue buffer. */
+	u32 queue_md;
+};
+
+struct cxi_eq_resize_complete_cmd {
+	enum cxi_command_opcode op;
+
+	u32 eq_hndl; /* EQ to resize */
+};
+
+/* PtlTE operations */
+struct cxi_pte_alloc_cmd {
+	enum cxi_command_opcode op;
+	void __user *resp;
+
+	u32 lni_hndl;
+	u32 evtq_hndl;
+	struct cxi_pt_alloc_opts opts;
+};
+
+struct cxi_pte_alloc_resp {
+	u32 pte_number;
+};
+
+struct cxi_pte_free_cmd {
+	enum cxi_command_opcode op;
+	void __user *resp;
+
+	u32 pte_number;
+};
+
+struct cxi_pte_map_cmd {
+	enum cxi_command_opcode op;
+	void __user *resp;
+
+	u32 pte_number;
+	u32 domain_hndl;
+	u32 pid_offset;
+	bool is_multicast;
+};
+
+struct cxi_pte_map_resp {
+	u32 pte_index;
+};
+
+struct cxi_pte_unmap_cmd {
+	enum cxi_command_opcode op;
+	void __user *resp;
+
+	u32 pte_index;
+};
+
+struct cxi_pte_le_invalidate_cmd {
+	enum cxi_command_opcode op;
+	u32 pte_index;
+	u32 buffer_id;
+	enum c_ptl_list list;
+};
+
+struct cxi_pte_status {
+	u32 drop_count;
+	u8 state;
+	u16 les_reserved;
+	u16 les_allocated;
+	u16 les_max;
+
+	u64 __user *ule_offsets;
+	u16 ule_count;
+};
+
+struct cxi_pte_status_cmd {
+	enum cxi_command_opcode op;
+	void __user *resp;
+
+	u32 pte_index;
+};
+
+struct cxi_pte_status_resp {
+	struct cxi_pte_status status;
+};
+
+struct cxi_pte_transition_sm_cmd {
+	enum cxi_command_opcode op;
+	void __user *resp;
+
+	u32 pte_index;
+	u32 drop_count;
+};
+
+struct cxi_wait_alloc_cmd {
+	enum cxi_command_opcode op;
+	void __user *resp;
+
+	u32 lni;
+
+};
+
+struct cxi_wait_alloc_resp {
+	u32 client_id;
+	u32 wait;
+};
+
+struct cxi_wait_free_cmd {
+	enum cxi_command_opcode op;
+	void __user *resp;
+
+	u32 wait;
+};
+
+struct cxi_map_csrs_cmd {
+	enum cxi_command_opcode op;
+	void  __user *resp;
+};
+
+struct cxi_map_csrs_resp {
+	struct cxi_mminfo csr; /* mmap info for the CSRs */
+};
+
+enum cxi_rsrc_type {
+	CXI_RSRC_TYPE_PTE,
+	CXI_RSRC_TYPE_TXQ,
+	CXI_RSRC_TYPE_TGQ,
+	CXI_RSRC_TYPE_EQ,
+	CXI_RSRC_TYPE_CT,
+	CXI_RSRC_TYPE_LE,
+	CXI_RSRC_TYPE_TLE,
+	CXI_RSRC_TYPE_AC,
+
+	CXI_RSRC_TYPE_MAX,
+};
+
+struct cxi_limits {
+	u16 max;
+	u16 res;
+};
+
+struct cxi_rsrc_limits {
+	union {
+		struct {
+			struct cxi_limits ptes;
+			struct cxi_limits txqs;
+			struct cxi_limits tgqs;
+			struct cxi_limits eqs;
+			struct cxi_limits cts;
+			struct cxi_limits les;
+			struct cxi_limits tles;
+			struct cxi_limits acs;
+		};
+		struct cxi_limits type[CXI_RSRC_TYPE_MAX];
+	};
+};
+
+struct cxi_rsrc_use {
+	/* SVC_ID = 0 is not a valid svc_id. But will be used to indicate total
+	 * resources used on the device
+	 */
+	u32 svc_id;
+	u32 tle_pool_id;
+	u16 in_use[CXI_RSRC_TYPE_MAX];
+};
+
+enum cxi_svc_member_type {
+	CXI_SVC_MEMBER_IGNORE,
+	CXI_SVC_MEMBER_UID,
+	CXI_SVC_MEMBER_GID,
+	CXI_SVC_MEMBER_NET_NS,
+	CXI_SVC_MEMBER_MAX,
+};
+
+struct cxi_svc_fail_info {
+	/* If a reservation was requested for a CXI_RSRC_TYPE_X and allocation
+	 * failed, its entry in this array will reflect how many of said
+	 * resource were actually available to reserve.
+	 */
+	u16 rsrc_avail[CXI_RSRC_TYPE_MAX];
+
+	/* True if relevant pool ids were requested, but none were available. */
+	bool no_le_pools;
+	bool no_tle_pools;
+	bool no_cntr_pools;
+};
+
+#define CXI_SVC_MAX_MEMBERS 2
+#define CXI_SVC_MAX_VNIS 4
+#define CXI_DEFAULT_SVC_ID 1
+
+struct cxi_svc_desc {
+	u8
+		/* Limit access to member processes */
+		restricted_members:1,
+
+		/* Limit access to defined VNIs */
+		restricted_vnis:1,
+
+		/* Limit access to defined TCs */
+		restricted_tcs:1,
+
+		/* Limit access to resources */
+		resource_limits:1,
+
+		/* Whether a service should be enabled.
+		 * Services are enabled by default upon creation.
+		 */
+		enable:1,
+
+		/* Differentiates system and user services */
+		is_system_svc:1,
+
+		/* Counter Pool ID */
+		cntr_pool_id:2;
+
+	/* How many VNIs provided by the user are valid.
+	 * Must be non-zero if restricted_vnis is true.
+	 */
+	u8 num_vld_vnis;
+
+	/* VNIs allowed by this service */
+	u16 vnis[CXI_SVC_MAX_VNIS];
+
+	bool tcs[CXI_TC_MAX];
+
+	struct {
+		union cxi_svc_member {
+			__kernel_uid_t  uid;
+			__kernel_gid_t  gid;
+		} svc_member;
+		enum cxi_svc_member_type type;
+	} members[CXI_SVC_MAX_MEMBERS];
+
+	struct cxi_rsrc_limits limits;
+
+	u32 svc_id;
+};
+
+struct cxi_svc_rsrc_list_get_cmd {
+	enum cxi_command_opcode op;
+	void __user *resp;
+
+	u32 count;
+	struct cxi_rsrc_use *rsrc_list;
+};
+
+struct cxi_svc_rsrc_list_get_resp {
+	u32 count;
+};
+
+struct cxi_svc_rsrc_get_cmd {
+	enum cxi_command_opcode op;
+	void __user *resp;
+
+	u32 svc_id;
+};
+
+struct cxi_svc_rsrc_get_resp {
+	struct cxi_rsrc_use rsrcs;
+};
+
+struct cxi_svc_list_get_cmd {
+	enum cxi_command_opcode op;
+	void __user *resp;
+
+	u32 count;
+	struct cxi_svc_desc *svc_list;
+};
+
+struct cxi_svc_list_get_resp {
+	u32 count;
+};
+
+struct cxi_svc_get_cmd {
+	enum cxi_command_opcode op;
+	void __user *resp;
+
+	u32 svc_id;
+};
+
+struct cxi_svc_get_resp {
+	struct cxi_svc_desc svc_desc;
+};
+
+struct cxi_svc_alloc_cmd {
+	enum cxi_command_opcode op;
+	void __user *resp;
+
+	struct cxi_svc_desc svc_desc;
+};
+
+struct cxi_svc_alloc_resp {
+	u32 svc_id;
+	struct cxi_svc_fail_info fail_info;
+};
+
+struct cxi_svc_destroy_cmd {
+	enum cxi_command_opcode op;
+	u32 svc_id;
+};
+
+struct cxi_svc_update_cmd {
+	enum cxi_command_opcode op;
+	void __user *resp;
+
+	struct cxi_svc_desc svc_desc;
+};
+
+struct cxi_svc_enable_cmd {
+	enum cxi_command_opcode op;
+	void __user *resp;
+	u32 svc_id;
+	bool enable;
+};
+
+struct cxi_svc_lpr_cmd {
+	enum cxi_command_opcode op;
+	void __user *resp;
+	u32 svc_id;
+	u32 lnis_per_rgid;
+};
+
+struct cxi_svc_set_exclusive_cp_cmd {
+	enum cxi_command_opcode op;
+	u32 svc_id;
+	bool exclusive_cp;
+};
+
+struct cxi_svc_get_exclusive_cp_cmd {
+	enum cxi_command_opcode op;
+	void __user *resp;
+	u32 svc_id;
+};
+
+struct cxi_svc_get_value_resp {
+	u32 value;
+};
+
+struct cxi_svc_vni_range_cmd {
+	enum cxi_command_opcode op;
+	void __user *resp;
+	u32 svc_id;
+	u32 vni_min;
+	u32 vni_max;
+};
+
+struct cxi_svc_set_netns_cmd {
+	enum cxi_command_opcode op;
+	u32 svc_id;
+	u32 netns;
+};
+
+struct cxi_svc_get_netns_cmd {
+	enum cxi_command_opcode op;
+	void __user *resp;
+	u32 svc_id;
+};
+
+struct cxi_svc_get_vni_range_resp {
+	u32 vni_min;
+	u32 vni_max;
+};
+
+struct cxi_svc_update_resp {
+	struct cxi_svc_fail_info fail_info;
+};
+
+struct cxi_inbound_wait_cmd {
+	enum cxi_command_opcode op;
+};
+
+struct cxi_svc_get_exclusive_cp_resp {
+	bool exclusive_cp;
+};
+
+/**
+ * struct cxi_sbus_op_params - SBus operation parameters
+ *
+ * @req_data: Data for request
+ * @data_addr: Data address within the SBus Receiver
+ * @rx_addr: Address of destination SBus Receiver
+ * @command: Command for request
+ * @delay: time to wait after issuing the command, 0 to 100, in us
+ * @timeout: timeout for the whole command, 1 to 5000, in ms
+ * @poll_interval: polling interval for result, 1 to 1000, in ms
+ */
+struct cxi_sbus_op_params {
+	u32 req_data;
+	u8 data_addr;
+	u8 rx_addr;
+	u8 command;
+	u32 delay;
+	u32 timeout;
+	u32 poll_interval;
+};
+
+struct cxi_sbus_op_cmd {
+	enum cxi_command_opcode op;
+	void __user *resp;
+
+	struct cxi_sbus_op_params params;
+};
+
+struct cxi_sbus_op_resp {
+	u32 rsp_data;
+	u8 result_code;
+	u8 overrun;
+};
+
+struct cxi_sbus_op_reset_cmd {
+	enum cxi_command_opcode op;
+	void __user *resp;
+};
+
+/**
+ * struct cxi_serdes_op_cmd - SERDES operation parameters
+ *
+ * @serdes_sel:
+ * @serdes_op:
+ * @data:
+ * @timeout: non-zero timeout for the whole command, in ms
+ * @flags:
+ */
+struct cxi_serdes_op_cmd {
+	enum cxi_command_opcode op;
+	void __user *resp;
+
+	u64 serdes_sel;
+	u64 serdes_op;
+	u64 data;
+	s32 timeout;
+	u32 flags;
+};
+
+struct cxi_serdes_op_resp {
+	u16 result;
+};
+
+/* Versions and revisions of the chip */
+enum cassini_version {
+	CASSINI_1 = 0x10,
+	CASSINI_2 = 0x20,
+
+	CASSINI_1_0 = (CASSINI_1 | 0x01),
+	CASSINI_1_1 = (CASSINI_1 | 0x02),
+
+	CASSINI_2_0 = (CASSINI_2 | 0x01),
+};
+
+/* System info to determine if a system is mixed (C1 & C2)
+ * or homogeneous (only C1 or only C2).
+ */
+enum system_type_identifier {
+	CASSINI_MIX = 0,
+	CASSINI_1_ONLY = 1,
+	CASSINI_2_ONLY = 2,
+};
+
+struct cxi_properties_info {
+	/* Physical NIC Address of the device. */
+	union {
+		u32 nic_addr; /* obsolete */
+		u32 nid;
+	};
+
+	/* NID explicitly configured by user */
+	bool nid_configured;
+
+	/* Width of PID field */
+	u32 pid_bits;
+
+	/* Count of PIDs per VNI */
+	u32 pid_count;
+
+	/* Granularity of device PID space. */
+	u32 pid_granule;
+
+	/* min_free shift value */
+	u32 min_free_shift;
+
+	/* Source PTE index for offloaded rendezvous Gets */
+	u32 rdzv_get_idx;
+
+	/* Device resource limit info */
+	struct cxi_rsrc_limits rsrcs;
+
+	u32 device_rev;
+	u32 device_proto;
+	u32 device_platform;
+
+	/* Hardware version (1.0, 1.1, 2.0, ...) */
+	enum cassini_version cassini_version;
+
+	/* Rendezvous get hardware enable state */
+	bool rdzv_get_en;
+
+	/* NIC AMO operation opcode being remapped to PCIe fetch add. */
+	s32 amo_remap_to_pcie_fadd;
+	u32 vni_matching;
+};
+
+struct cxi_get_dev_properties_cmd {
+	enum cxi_command_opcode op;
+	void __user *resp;
+};
+
+struct cxi_eq_adjust_reserved_fc_cmd {
+	enum cxi_command_opcode op;
+	void __user *resp;
+	u32 eq_hndl;
+	s32 value;
+};
+
+struct cxi_eq_adjust_reserved_fc_resp {
+	s32 reserved_fc;
+};
+
+struct cxi_dev_info_use {
+	u32 nid;
+	u32 pid_bits;
+	u32 pid_count;
+	u32 pid_granule;
+	u32 min_free_shift;
+	u32 rdzv_get_idx;
+	u32 vendor_id;
+	u32 device_id;
+	u32 device_rev;
+	u32 device_proto;
+	u32 device_platform;
+	u32 pct_eq;
+	s32 uc_nic;
+
+	size_t link_mtu;
+	u64 link_speed;
+	u8 link_state;
+	u16 num_ptes;
+	u16 num_txqs;
+	u16 num_tgqs;
+	u16 num_eqs;
+	u16 num_cts;
+	u16 num_acs;
+	u16 num_tles;
+	u16 num_les;
+
+	char fru_description[16];
+
+	enum cassini_version cassini_version;
+
+	enum system_type_identifier system_type_identifier;
+};
+
+struct cxi_dev_info_get_cmd {
+	enum cxi_command_opcode op;
+	void __user *resp;
+};
+
+struct cxi_dev_info_get_resp {
+	struct cxi_dev_info_use devinfo;
+};
+
+struct cxi_eth_dev_info_get_cmd {
+	enum cxi_command_opcode op;
+	void __user *resp;
+	size_t buf_size;  /* Size of buffer provided by caller */
+};
+
+struct cxi_eth_tc_req_pcp_get_cmd {
+	enum cxi_command_opcode op;
+	void __user *resp;
+	u32 tc;  /* Traffic class to query */
+};
+
+struct cxi_get_tc_req_pcp_resp {
+	s32 req_pcp;  /* Request PCP for the TC, or -1 if not active */
+};
+
+struct cxi_eth_pause_get_cmd {
+	enum cxi_command_opcode op;
+	void __user *resp;
+};
+
+struct cxi_eth_get_pause_resp {
+	u32 tx_pause;  /* TX pause enabled */
+	u32 rx_pause;  /* RX pause enabled */
+};
+
+struct cxi_eth_max_rxsize_get_cmd {
+	enum cxi_command_opcode op;
+	void __user *resp;
+};
+
+struct cxi_eth_get_max_rxsize_resp {
+	u32 max_rxsize;  /* Current max RX frame size, excluding headers */
+};
+
+struct cxi_eth_link_state_get_cmd {
+	enum cxi_command_opcode op;
+	void __user *resp;
+};
+
+struct cxi_eth_get_link_state_resp {
+	u8 link_up;  /* Non-zero if the link is up */
+};
+
+struct cxi_phys_lac_alloc_cmd {
+	enum cxi_command_opcode op;
+	void __user *resp;
+	u32 lni;
+};
+
+struct cxi_phys_lac_alloc_resp {
+	u32 lac;
+};
+
+struct cxi_phys_lac_free_cmd {
+	enum cxi_command_opcode op;
+	u32 lni;
+	u32 lac;
+};
+
+struct cxi_vf_get_token_cmd {
+	enum cxi_command_opcode op;
+	void __user *resp;
+};
+
+struct cxi_vf_get_token_resp {
+	u32 token;
+};
+
+#define CXIERR_GENL_FAMILY_NAME "cxierr"
+#define CXIERR_GENL_VERSION	1
+#define CXIERR_GENL_MCAST_GROUP_NAME "cxierr_mc_group"
+
+enum {
+	CXIERR_ERR_UNSPEC,
+	CXIERR_ERR_MSG,
+};
+
+enum cxierr_nldev_attr {
+	CXIERR_GENL_ATTR_UNSPEC, /* always first */
+
+	CXIERR_GENL_ATTR_DEV_NUM,
+	CXIERR_GENL_ATTR_CSR_FLG,
+	CXIERR_GENL_ATTR_BIT,
+
+	CXIERR_GENL_ATTR_MAX	/* always last */
+};
+
+/* Expose driver default PCT Timings that will be
+ * referenced by the Retry Handler
+ */
+#define C1_DEFAULT_SPT_TIMEOUT_EPOCH 30
+#define C1_DEFAULT_SCT_IDLE_EPOCH 15
+#define C1_DEFAULT_SCT_CLOSE_EPOCH 30
+#define C1_DEFAULT_TCT_TIMEOUT_EPOCH 35
+
+/* Check whether Cassini is of a specific revision or version.
+ *
+ * For instance, CASSINI_1_0 will match only for Cassini 1.0, while
+ * CASSINI_1 will match both Cassini 1.0 and 1.1.
+ */
+static inline bool cassini_version(const struct cxi_properties_info *prop,
+				   enum cassini_version version)
+{
+	return (prop->cassini_version & version) == version;
+}
+
+#endif	/* __UAPI_CXI_ABI_H */
diff --git a/include/linux/hpe/cxi/cxi_prov_hw.h b/include/linux/hpe/cxi/cxi_prov_hw.h
new file mode 100644
index 000000000000..b2b8a9d146fc
--- /dev/null
+++ b/include/linux/hpe/cxi/cxi_prov_hw.h
@@ -0,0 +1,1875 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * Copyright 2018-2020 Cray Inc. All rights reserved
+ *
+ * CXI event queue and command queue definitions and accessors.
+ */
+
+#ifndef __CXI_PROV_HW
+#define __CXI_PROV_HW
+
+/*
+ * wp_fence() - Fence operation used before advancing the command queue write
+ * pointer. This ensures that all commands are write visible before hardware
+ * processing the write pointer update.
+ *
+ * wc_fence() - Fence operation used to ensuring ordering between writes to
+ * write combining buffers.
+ */
+
+#if defined(__aarch64__)
+
+#define aarch64_dmb(opt) asm volatile ("dmb " #opt ::: "memory")
+
+
+#define sfence() aarch64_dmb(oshst)
+
+/* Data memory barrier with outer shareability is enough to ensure write
+ * ordering between host memory command writes and write pointer doorbell
+ * writes.
+ */
+#define wp_fence() aarch64_dmb(oshst)
+
+
+/* Data memory barrier with outer shareability is enough writes to device memory
+ * gather regions (i.e. write combined regions) are ordered with respect to
+ * subsequent device memory gather region writes.
+ */
+#define wc_fence() aarch64_dmb(oshst)
+
+#elif defined(__x86_64__)
+
+#define sfence() __asm__ __volatile__  ( "sfence" ::: "memory" )
+#define wp_fence() sfence()
+#define wc_fence() sfence()
+
+#else
+#error "Unsupported CPU architecture"
+#endif
+
+#include <uapi/ethernet/cassini_user_defs.h>
+
+static const u8 amo_size[16] = {1, 1, 2, 2, 4, 4, 8, 8, 4, 8, 8, 16, 16};
+
+/*
+ * Padding needed for a command given the command size and
+ * position. eg. a command of size 3 (256 bytes), with a wr_ptr at
+ * pos % 8 = 2 needs pad_slots[2][3] = 6 32-bytes block.
+ */
+static const u32 __cxi_pad_slots[8][4] = {
+	{0, 0, 0, 0},
+	{0, 1, 3, 7},
+	{0, 0, 2, 6},
+	{0, 1, 1, 5},
+	{0, 0, 0, 4},
+	{0, 1, 3, 3},
+	{0, 0, 2, 2},
+	{0, 1, 1, 1}
+};
+
+/*
+ * Number of 32-bytes slots needed for a command
+ */
+static const u32 __cxi_cmd_slots[4] = {
+	1, 2, 4, 8
+};
+
+/*
+ * Return the command size to fit a certain payload. 32 bytes or less
+ * return 0 (C_CMD_SIZE_32B), 33 to 64 returns 1 (C_CMD_SIZE_64B), ...
+ */
+static inline enum c_cmd_size __cxi_cmd_size(u32 size)
+{
+	if (size <= 16)
+		return C_CMD_SIZE_32B;
+	else
+		return (enum c_cmd_size)
+			(8 * sizeof(u64) -
+			 __builtin_clzll((size - 1)) - 5);
+}
+
+/*
+ * Note.
+ *
+ * The hardware command granularity is 64 bytes (a slot). However the
+ * hardware also support 32 bytes commands. If a command is 32 bytes,
+ * there will always be a second 32 bytes command in that 64 bytes
+ * slot, and may be a NoOp.
+ */
+
+struct cxi_cmd32 {
+	u8 pad[32];
+};
+
+#define C_CQ_CMD_SIZE 64
+#define C_CQ_FIRST_WR_PTR 4
+#define C_CQ_FIRST_WR_PTR_32 (2 * C_CQ_FIRST_WR_PTR)
+
+#define LL_OFFSET(wp32) ((((wp32) / 2) & 0x0f) * 64)
+
+struct cxi_cmd64 {
+	u8 pad[C_CQ_CMD_SIZE];
+};
+
+union c_cmdu {
+	u8                 u8;
+	struct c_cmd		command;
+	struct c_cstate_cmd	c_state;
+	struct c_idc_hdr	idc_hdr;
+	struct c_idc_eth_cmd	idc_eth;
+	struct c_idc_put_cmd	idc_put;
+	struct c_idc_amo_cmd	idc_amo;
+	struct c_idc_msg_hdr	idc_msg;
+	struct c_nomatch_dma_cmd nomatch_dma;
+	struct c_full_dma_cmd	full_dma;
+	struct c_dma_amo_cmd	dma_amo;
+	struct c_dma_eth_cmd	dma_eth;
+	struct c_ct_cmd		ct;
+	struct c_cq_cmd		cq;
+	struct c_target_cmd	target;
+	struct c_set_state_cmd	set_state;
+};
+
+/* User command queue */
+struct cxi_cq {
+	/* Command queue size */
+	u32 size;
+
+	/* Memory mapped write pointer location */
+	u64 *wp_addr;
+
+	/* Low-latency write regions. */
+	u8 *ll_64;
+	u8 *ll_128a;
+	u8 *ll_128u;
+
+	/* CQ status and commands buffer. CQ status occupies the first 8 32-byte
+	 * slots. Commands start after.
+	 */
+	union {
+		struct cxi_cmd32 *cmds32;
+		volatile struct c_cq_status *status;
+	};
+	u64 rp32;
+
+	/* CQ index. Transmit CQs use 0 to 1023, and target CQs use
+	 * 1024 to 1535. Use cxi_cq_get_cqn() to retrieve the CQ
+	 * number, going from 0 to 1023, or 0 to 512 respectively. */
+	u32 idx;
+
+	/* 32-bytes internal write pointer */
+	u32 size32;
+	u64 wp32;
+	u64 hw_wp32;
+};
+
+#define C_EE_CFG_ECB_SIZE 64
+union c_event {
+	/* Use as event header, to access event_size and event_type
+	 * only */
+	struct c_event_cmd_fail hdr;
+
+	struct c_event_initiator_short	init_short;
+	struct c_event_initiator_long	init_long;
+	struct c_event_trig_op_short	trig_short;
+	struct c_event_trig_op_long	trig_long;
+	struct c_event_cmd_fail		cmd_fail;
+	struct c_event_target_long	tgt_long;
+	struct c_event_target_short	tgt_short;
+	struct c_event_target_enet	enet;
+	struct c_event_enet_fgfc	enet_fgfc;
+	struct c_event_timestamp	timestamp;
+	struct c_event_eq_switch	eq_switch;
+	struct c_event_pct              pct;
+};
+
+#define C_LE_EVENT_CT_BYTES		(1 << 0)
+#define C_LE_EVENT_CT_OVERFLOW		(1 << 1)
+#define C_LE_EVENT_CT_COMM		(1 << 2)
+#define C_LE_EVENT_UNLINK_DISABLE	(1 << 3)
+#define C_LE_EVENT_SUCCESS_DISABLE	(1 << 4)
+#define C_LE_EVENT_COMM_DISABLE		(1 << 5)
+#define C_LE_EVENT_LINK_DISABLE		(1 << 6)
+#define C_LE_UNRESTRICTED_END_RO	(1 << 7)
+#define C_LE_UNRESTRICTED_BODY_RO	(1 << 8)
+#define C_LE_UNEXPECTED_HDR_DISABLE	(1 << 9)
+#define C_LE_USE_ONCE			(1 << 10)
+#define C_LE_NO_TRUNCATE		(1 << 11)
+#define C_LE_MANAGE_LOCAL		(1 << 12)
+#define C_LE_OP_GET			(1 << 13)
+#define C_LE_OP_PUT			(1 << 14)
+#define C_LE_RESTART_SEQ		(1 << 15)
+
+static inline void cxi_target_cmd_setopts(struct c_target_cmd *cmd,
+				          u32 flags)
+{
+	if (flags & C_LE_EVENT_CT_BYTES)
+		cmd->event_ct_bytes = 1;
+	if (flags & C_LE_EVENT_CT_OVERFLOW)
+		cmd->event_ct_overflow = 1;
+	if (flags & C_LE_EVENT_CT_COMM)
+		cmd->event_ct_comm = 1;
+	if (flags & C_LE_EVENT_UNLINK_DISABLE)
+		cmd->event_unlink_disable = 1;
+	if (flags & C_LE_EVENT_SUCCESS_DISABLE)
+		cmd->event_success_disable = 1;
+	if (flags & C_LE_EVENT_COMM_DISABLE)
+		cmd->event_comm_disable = 1;
+	if (flags & C_LE_EVENT_LINK_DISABLE)
+		cmd->event_link_disable = 1;
+	if (flags & C_LE_UNRESTRICTED_END_RO)
+		cmd->unrestricted_end_ro = 1;
+	if (flags & C_LE_UNRESTRICTED_BODY_RO)
+		cmd->unrestricted_body_ro = 1;
+	if (flags & C_LE_USE_ONCE)
+		cmd->use_once = 1;
+	if (flags & C_LE_NO_TRUNCATE)
+		cmd->no_truncate = 1;
+	if (flags & C_LE_MANAGE_LOCAL)
+		cmd->manage_local = 1;
+	if (flags & C_LE_OP_GET)
+		cmd->op_get = 1;
+	if (flags & C_LE_OP_PUT)
+		cmd->op_put = 1;
+	if (flags & C_LE_RESTART_SEQ)
+		cmd->restart_seq = 1;
+}
+
+static inline s32 cxi_init_event_rc(const union c_event *event)
+{
+	if (event->hdr.event_size == C_EVENT_SIZE_16_BYTE)
+		return event->init_short.return_code;
+	return event->init_long.return_code;
+}
+
+static inline s32 cxi_tgt_event_rc(const union c_event *event)
+{
+	if (event->hdr.event_size == C_EVENT_SIZE_32_BYTE)
+		return event->tgt_short.return_code;
+	return event->tgt_long.return_code;
+}
+
+static inline s32 cxi_event_rc(const union c_event *event)
+{
+	switch(event->hdr.event_type) {
+	case C_EVENT_PUT:
+	case C_EVENT_GET:
+	case C_EVENT_ATOMIC:
+	case C_EVENT_FETCH_ATOMIC:
+	case C_EVENT_PUT_OVERFLOW:
+	case C_EVENT_GET_OVERFLOW:
+	case C_EVENT_ATOMIC_OVERFLOW:
+	case C_EVENT_FETCH_ATOMIC_OVERFLOW:
+	case C_EVENT_LINK:
+	case C_EVENT_SEARCH:
+	case C_EVENT_STATE_CHANGE:
+	case C_EVENT_UNLINK:
+	case C_EVENT_RENDEZVOUS:
+	case C_EVENT_MATCH:
+		return cxi_tgt_event_rc(event);
+
+	case C_EVENT_SEND:
+	case C_EVENT_ACK:
+	case C_EVENT_REPLY:
+		return cxi_init_event_rc(event);
+
+	case C_EVENT_ETHERNET:
+		return event->enet.return_code;
+	case C_EVENT_COMMAND_FAILURE:
+		return event->cmd_fail.return_code;
+	case C_EVENT_TRIGGERED_OP:
+		if (event->hdr.event_size == C_EVENT_SIZE_16_BYTE) {
+			return event->trig_short.return_code;
+		} else {
+			return event->trig_long.return_code;
+		}
+	case C_EVENT_ETHERNET_FGFC:
+		return event->enet_fgfc.return_code;
+	case C_EVENT_PCT:
+		return event->pct.return_code;
+	case C_EVENT_ERROR:
+		return C_RC_NO_EVENT;
+	case C_EVENT_TIMESTAMP:
+		return event->timestamp.return_code;
+	case C_EVENT_EQ_SWITCH:
+		return event->eq_switch.return_code;
+	case C_EVENT_NULL_EVENT:
+		return C_RC_NO_EVENT;
+	}
+
+	return C_RC_NO_EVENT;
+}
+
+/* Generate match_id. match_id is present in LEs, DMA commands and EQ events.
+ * The highest 'pid_bits' bits are used to hold a PID value. The remaining,
+ * low-order 32-'pid_bits' bits are used to store an Endpoint ID. When using a
+ * PtlTE configured for logical matching, the Endpoint ID represents a logical
+ * rank ID. Otherwise, the Endpoint ID contains a 20 bit physical NIC ID.
+ */
+#define CXI_MATCH_ID(pid_bits, pid, ep) \
+	((((pid) & ((1U << (pid_bits)) - 1)) << (32U - (pid_bits))) | \
+	 ((ep) & ((1U << (32 - (pid_bits))) - 1)))
+#define CXI_MATCH_ID_ANY CXI_MATCH_ID(C_DFA_PID_BITS_MAX, C_PID_ANY, C_RANK_ANY)
+
+#define CXI_MATCH_ID_PID(pid_bits, match_id) ((match_id) >> (32 - (pid_bits)))
+#define CXI_MATCH_ID_EP(pid_bits, match_id) \
+	((match_id) & ((1U << (32 - (pid_bits))) - 1))
+
+/**
+ * struct cxi_rdzv_match_bits - Match bits used for Rendezvous Get.
+ * @match_bits: Match bits mirrored from the Rendezvous Put operation
+ * @transaction_type: Rendezvous transaction type, must match device
+ * configuration
+ * @rendezvous_id: Rendezvous ID used for Rendezvous Put operation
+ *
+ * The 64-bit rendezvous match bits value has two uses.
+ * 1. Rendezvous Put Initiator: Match bits used in a source buffer LE linked to
+ *    the rendezvous source PtlTE.
+ * 2. Rendezvous Put Target: Match bits used in a SW issued Get.
+ */
+struct cxi_rdzv_match_bits {
+	union {
+		struct {
+			u64 rendezvous_id		: 8;
+			u64 transaction_type	: 4;
+			u64 unused			: 36;
+			u64 match_bits		: 16;
+		};
+		u64 raw;
+	};
+};
+
+/**
+ * struct cxi_rdzv_user_ptr - User pointer format for Rendezvous Get events.
+ * @src_nid: Source fabric address NID of the Rendezvous Put
+ * @src_pid: Source fabric address PID of the Rendezvous Put
+ * @ptlte_index: PltTE index the target LE was appended on
+ * @rendezvous_id: Rendezvous ID from the Rendezvous Put
+ * @buffer_id: Buffer ID of the target LE from the Rendezvous Put
+ *
+ * The user_ptr field in a Reply event for a Hardware issued Rendezvous Get is
+ * formatted using this structure.
+ */
+struct cxi_rdzv_user_ptr {
+	union {
+		struct {
+			u64 src_nid	: 20;
+			u64 src_pid	: 9;
+			u64 ptlte_index	: 11;
+			u64 rendezvous_id	: 8;
+			u64 buffer_id	: 16;
+		};
+		u64 raw;
+	};
+};
+
+#define CT_INC_SUCCESS_OFFSET 0
+#define CT_INC_FAILURE_OFFSET 64
+#define CT_RESET_SUCCESS_OFFSET 128
+#define CT_RESET_FAILURE_OFFSET 192
+#define CT_SUCCESS_MASK ((1ULL << C_CT_SUCCESS_BITS) - 1)
+#define CT_FAILURE_MASK ((1ULL << C_CT_FAILURE_BITS) - 1)
+
+/* User counter */
+struct cxi_ct {
+	/* Memory mapped doorbell. */
+	u64 *doorbell;
+
+	/* The allocated CT number, which will be used in commands. */
+	u32 ctn;
+
+	/* Writeback buffer backpoint for CT owner. */
+	struct c_ct_writeback *wb;
+};
+
+/* Hardware reserves two event slots: one for detecting EQ overrun and the first
+ * slot for providing EQ status writeback.
+ */
+#define C_EQ_RESERVED_EVENT_SLOTS 2U
+
+/* User event queue */
+struct cxi_eq {
+	/* Event queue byte size */
+	u32 byte_size;
+
+	/* EQ software state, which includes the read pointer. Keep a
+	 * local copy and update the fields as needed before copying
+	 * it to the adapter. */
+	union c_ee_cfg_eq_sw_state sw_state;
+	u64 *sw_state_addr;
+
+	/* Cached status write-back timestamp. */
+	u64 last_ts_sec;
+	u64 last_ts_ns;
+
+	/* Current read offset */
+	u32 rd_offset;
+
+	/* Previous read offset - before last call to
+	 * cxi_eq_ack_events() */
+	u32 prev_rd_offset;
+
+	/* The allocated EQ number, which will be used in commands. */
+	u32 eqn;
+
+	/* Backpointer for the owner of the EQ. */
+	void *context;
+
+	union {
+		/* Ring buffer for events */
+		u8 *events;
+
+		/* EQ status write-back pointer. Updated when the number of free
+		 * events crosses a configurable threshold, or when events are
+		 * dropped. */
+		struct c_eq_status *status;
+	};
+};
+
+/* Check to see if command queue is empty. */
+static inline bool cxi_cq_empty(struct cxi_cq *cq)
+{
+	u64 wp = cq->wp32 / 2;
+
+	return wp == cq->status->rd_ptr;
+}
+
+/*
+ * Advance the internal write pointer for the given command
+ * size. cmd_size is 0, 1, 2 or 3 (C_CMD_SIZE_XXX).
+ * If the write pointer wraps, set wp32 to the first valid offset for a command.
+ * The start of the queue is used by Cassini to return status.
+ */
+static inline void __cxi_cq_advance_wp(struct cxi_cq *cq,
+				       enum c_cmd_size cmd_size)
+{
+	cq->wp32 = (cq->wp32 + (1 << cmd_size));
+	if (cq->wp32 >= cq->size32)
+		cq->wp32 = C_CQ_FIRST_WR_PTR_32;
+}
+
+/*
+ * Return the number of usable slots in the queue using the cached read
+ * pointer. Remove 1 full 64-bytes slot to prevent queue overrun (wr_ptr ==
+ * rd_ptr). Remove 4 full slots because the start of the queue is used by
+ * Cassini to return rd_ptr and status.
+ */
+static inline s32 __cxi_cq_free_slots_check(const struct cxi_cq *cq)
+{
+	if (cq->wp32 >= cq->rp32)
+		return cq->size32 - cq->wp32 + cq->rp32 - 2 -
+				C_CQ_FIRST_WR_PTR_32;
+	else
+		return cq->rp32 - cq->wp32 - 2;
+}
+
+/*
+ * Return the number of usable slots in the queue.
+ *
+ * Cassini regularly writes the read pointer to host memory. Avoid accessing
+ * the read pointer to reduce expensive loads from memory.
+ */
+static inline s32 __cxi_cq_free_slots(struct cxi_cq *cq)
+{
+	s32 slots = __cxi_cq_free_slots_check(cq);
+
+	if (slots < 16) {
+		cq->rp32 = cq->status->rd_ptr * 2;
+		slots = __cxi_cq_free_slots_check(cq);
+	}
+
+	return slots;
+}
+
+/**
+ * cxi_cq_update_wp() - Update the real write pointer.
+ *
+ * This lets the rest of the software manage the ring buffer as
+ * 64-bytes slots, while internally it's managed as 32 bytes slots.
+ *
+ * If the internal write pointer is odd, add a NoOp to pad to a 64
+ * bytes block.
+ *
+ * Users should not call this function. Instead, they should use
+ * cxi_cq_ll_ring() or cxi_cq_ring().
+ */
+static inline void cxi_cq_update_wp(struct cxi_cq *cq)
+{
+	if (cq->wp32 & 1) {
+		struct cxi_cmd32 *cmd = &cq->cmds32[cq->wp32];
+
+		/* Command opcode and DFA must be cleared */
+		memset(cmd->pad, 0, sizeof(u64));
+		__cxi_cq_advance_wp(cq, C_CMD_SIZE_32B);
+	}
+
+	/* Ensure commands are in memory. */
+	wp_fence();
+}
+
+/**
+ * cxi_memcpy_aligned() - Copy to 64-bit aligned buffer.
+ *
+ * dest and n must be 64-bit aligned.
+ */
+static inline void cxi_memcpy_aligned(void *dest, const void *src, size_t n)
+{
+	size_t i;
+
+	for (i = 0; i < n / 8; i++)
+		((u64 *)dest)[i] = ((u64 *)src)[i];
+}
+
+/**
+ * __cxi_cq_inc_hw_wp32() - Increment software's mirror of the hardware write
+ * pointer by count amount of 32-byte chunks. Count must not exceed CQ size.
+ */
+static inline void __cxi_cq_inc_hw_wp32(struct cxi_cq *cq, u32 count)
+{
+	cq->hw_wp32 += count;
+	if (cq->hw_wp32 == cq->size32)
+		cq->hw_wp32 = C_CQ_FIRST_WR_PTR_32;
+}
+
+/**
+ * cxi_cq_ll_write64() - Write commands to 64-byte low-latency region.
+ *
+ * Note: Users should not call this function.
+ */
+static inline void cxi_cq_ll_write64(struct cxi_cq *cq)
+{
+	struct cxi_cmd64 *ll =
+		(struct cxi_cmd64 *)(cq->ll_64 + LL_OFFSET(cq->hw_wp32));
+
+	cxi_memcpy_aligned(ll, &cq->cmds32[cq->hw_wp32],
+			   sizeof(struct cxi_cmd64));
+
+	__cxi_cq_inc_hw_wp32(cq, 2);
+}
+
+/**
+ * cxi_cq_ll_write128_aligned() - Write commands to 128-byte aligned
+ * low-latency region. The CQ hardware write pointer must be aligned to a
+ * 128-byte boundary (i.e. hw_wp32 % 8 == 0, 4).
+ *
+ * Note: Users should not call this function.
+ */
+static inline void cxi_cq_ll_write128_aligned(struct cxi_cq *cq)
+{
+	struct cxi_cmd64 *ll =
+		(struct cxi_cmd64 *)(cq->ll_128a + LL_OFFSET(cq->hw_wp32));
+
+	cxi_memcpy_aligned(ll, &cq->cmds32[cq->hw_wp32],
+			   sizeof(struct cxi_cmd64) * 2);
+
+	__cxi_cq_inc_hw_wp32(cq, 4);
+}
+
+/**
+ * cxi_cq_ll_write128_unaligned() - Write commands to 128-byte unaligned
+ * low-latency region. The CQ hardware write pointer must be unaligned to a
+ * 128-byte boundary (i.e. hw_wp32 % 8 == 2, 6).
+ *
+ * Note: Users should not call this function.
+ */
+static inline void cxi_cq_ll_write128_unaligned(struct cxi_cq *cq)
+{
+	struct cxi_cmd64 *ll;
+
+	/*
+	 * These two 32-byte slots MUST be NOOPs. Thus, skip over them in the
+	 * command queue since hardware will skip the corresponding 64-byte
+	 * slot.
+	 */
+	__cxi_cq_inc_hw_wp32(cq, 2);
+
+	ll = (struct cxi_cmd64 *)(cq->ll_128u + LL_OFFSET(cq->hw_wp32));
+
+	cxi_memcpy_aligned(ll, &cq->cmds32[cq->hw_wp32],
+			   sizeof(struct cxi_cmd64) * 2);
+
+	__cxi_cq_inc_hw_wp32(cq, 4);
+}
+
+/**
+ * cxi_cq_ring() - Update the CQ write pointer and ring the CQ to
+ * execute the new posted commands.
+ *
+ * After posting one or more commands, the user would call this
+ * function to let the new work start.
+ *
+ * @cq: the command queue
+ */
+static inline void cxi_cq_ring(struct cxi_cq *cq)
+{
+	u64 wr_ptr;
+
+	if (cq->wp32 == cq->hw_wp32)
+		return;
+
+	cxi_cq_update_wp(cq);
+
+	cq->hw_wp32 = cq->wp32;
+	wr_ptr = cq->wp32 / 2;
+	*cq->wp_addr = wr_ptr;
+	wc_fence();
+}
+
+/**
+ * cxi_cq_ll_ring() - Commit outstanding commands to hardware using the
+ * low-latency write mechanism. This function will account for the alignment of
+ * the CQ hardware write pointer to ensure that the proper low-latency region
+ * is written to. This function guarantees that all commands are committed to
+ * HW. A standard doorbell ring may be used to accomplish that.
+ *
+ * Note: 256-byte commands cannot use the low-latency region. A standard
+ * doorbell ring is used to commit incompatible commands.
+ */
+static inline void cxi_cq_ll_ring(struct cxi_cq *cq)
+{
+	const struct c_cmd *cmd;
+	s32 cmd32_count;
+
+	if (cq->wp32 == cq->hw_wp32)
+		return;
+
+	cmd = (struct c_cmd *)&cq->cmds32[cq->hw_wp32];
+	if (cmd->cmd_size == C_CMD_SIZE_256B) {
+		cxi_cq_ring(cq);
+		return;
+	}
+
+	/* Align CQ to 64-byte boundary. */
+	cxi_cq_update_wp(cq);
+
+	cmd32_count = cq->wp32 - cq->hw_wp32;
+	if (cmd32_count < 0)
+		cmd32_count = cq->size32 - cq->hw_wp32;
+
+	/*
+	 * Identify the low-latency region to be written based on the CQ
+	 * hardware write pointer alignment.
+	 */
+	if (cmd32_count == 2) {
+		cxi_cq_ll_write64(cq);
+	} else if (cq->hw_wp32 % 4) {
+		cmd = (struct c_cmd *)&cq->cmds32[cq->hw_wp32];
+
+		if (cmd->opcode == C_CMD_NOOP) {
+			cmd = (struct c_cmd *)&cq->cmds32[cq->hw_wp32 + 2];
+
+			if (cmd->cmd_size == C_CMD_SIZE_256B) {
+				cxi_cq_ring(cq);
+				return;
+			}
+
+			cxi_cq_ll_write128_unaligned(cq);
+		} else {
+			cxi_cq_ll_write64(cq);
+		}
+	} else {
+		cxi_cq_ll_write128_aligned(cq);
+	}
+
+	/* Flush WC buffers. */
+	wc_fence();
+
+	/* Perform a doorbell ring if there are more commands ready. */
+	if (cq->wp32 != cq->hw_wp32)
+		cxi_cq_ring(cq);
+}
+
+/**
+ * cxi_cq_align_for_cmd() - Prepare command queue for new command
+ *
+ * Check whether the command queue has enough space for cmd_size
+ * 32-bytes blocks. For the current implementation we must ensure that
+ * 1 64-bytes block (ie. 2 32 bytes blocks) is always free to avoid
+ * queue wrap around. If the command doesn't align with the current
+ * block, prepend one or more NoOp for padding.
+ */
+static inline s32 cxi_cq_align_for_cmd(struct cxi_cq *cq,
+				       enum c_cmd_size cmd_size)
+{
+	const u32 pad_slots =
+		__cxi_pad_slots[cq->wp32 % 8][cmd_size];
+	const u32 cmd_slots = __cxi_cmd_slots[cmd_size];
+
+	/* Space available in the queue */
+	if (__cxi_cq_free_slots(cq) < (s32)(cmd_slots + pad_slots))
+		return -ENOSPC;
+
+	if (pad_slots) {
+		struct cxi_cmd32 *cmd = &cq->cmds32[cq->wp32];
+		u32 i;
+
+		for (i = 0; i < pad_slots; i++, cmd++) {
+			/* Command opcode and DFA must be cleared */
+			memset(cmd->pad, 0, 8);
+		}
+
+		cq->wp32 += pad_slots;
+		if (cq->wp32 >= cq->size32)
+			cq->wp32 = C_CQ_FIRST_WR_PTR_32;
+	}
+
+	return 0;
+}
+
+/**
+ * cxi_cq_get_cqn() - Return the CQ number
+ *
+ * From the allocated CQ index, return its number, which ranges from 0
+ * to 1023 for transmit CQs, and 0 to 511 for target CQs.
+ *
+ * @cq: the command queue
+ */
+static inline u32 cxi_cq_get_cqn(const struct cxi_cq *cq)
+{
+	if (cq->idx >= C_NUM_TRANSMIT_CQS)
+		return cq->idx - C_NUM_TRANSMIT_CQS;
+	else
+		return cq->idx;
+}
+
+/**
+ * cxi_cq_align_for_ct128_cmd() - Prepare command queue for new CT command
+ *
+ * For CT commands, the NoOp must be of type C_CMD_TYPE_CT. Commands
+ * on these queues are also only 64 or 128 bytes. Only called for 128
+ * bytes commands, as 64 bytes commands will never need padding.
+*/
+static inline s32 cxi_cq_align_for_ct128_cmd(struct cxi_cq *cq)
+{
+	const enum c_cmd_size cmd_size = C_CMD_SIZE_128B;
+	const u32 pad_slots =
+		__cxi_pad_slots[cq->wp32 % 8][cmd_size];
+	const s32 cmd_slots = __cxi_cmd_slots[cmd_size];
+
+	/* Space available in the queue */
+	if (__cxi_cq_free_slots(cq) < (s32)(cmd_slots + pad_slots))
+		return -ENOSPC;
+
+	/* A triggger TXQ only accepts 64-byte or 128-byte commands. If padding
+	 * is required for a 128-byte command, it only needs to be padded with a
+	 * single 64-byte command.
+	 */
+	if (pad_slots) {
+		struct c_cmd *cmd = (struct c_cmd *)&cq->cmds32[cq->wp32];
+
+		/* Command opcode and DFA must be cleared */
+		memset(cmd, 0, 8);
+		cmd->cmd_type = C_CMD_TYPE_CT;
+		cmd->cmd_size = C_CMD_SIZE_64B;
+		cmd->opcode = C_CMD_CT_NOOP;
+
+		cq->wp32 += pad_slots;
+		if (cq->wp32 >= cq->size32)
+			cq->wp32 = C_CQ_FIRST_WR_PTR_32;
+	}
+
+	return 0;
+}
+
+/**
+ * cxi_cq_emit_cq_cmd() - Emit a NOOP or FENCE CQ command
+ *
+ * opcode is either C_CMD_CQ_NOOP or C_CMD_CQ_FENCE.
+ */
+static inline s32 __attribute__((warn_unused_result))
+cxi_cq_emit_cq_cmd(struct cxi_cq *cq, u32 opcode)
+{
+	struct c_cq_cmd *cmd;
+	s32 rc;
+	const enum c_cmd_size cmd_size = C_CMD_SIZE_64B;
+
+	rc = cxi_cq_align_for_cmd(cq, cmd_size);
+	if (rc)
+		return rc;
+
+	cmd = (struct c_cq_cmd *)&cq->cmds32[cq->wp32];
+
+	/* Command opcode and DFA must be cleared */
+	memset(cmd, 0, 8);
+	cmd->command.cmd_type = C_CMD_TYPE_CQ;
+	cmd->command.cmd_size = cmd_size;
+	cmd->command.opcode = opcode;
+
+	__cxi_cq_advance_wp(cq, cmd_size);
+
+	return 0;
+}
+
+/**
+ * cxi_cq_emit_cq_lcid() - Emit an LCID CQ command
+ *
+ * The LCID command must be prepared differently than the NOOP and
+ * FENCE commands; it must be 128-bytes aligned, and padded with a NOP
+ * command after it.
+ */
+static inline s32 __attribute__((warn_unused_result))
+cxi_cq_emit_cq_lcid(struct cxi_cq *cq, u8 lcid)
+{
+	struct c_cq_cmd *cmd;
+	s32 rc;
+	const enum c_cmd_size cmd_size = C_CMD_SIZE_64B;
+
+	rc = cxi_cq_align_for_cmd(cq, C_CMD_SIZE_128B);
+	if (rc)
+		return rc;
+
+	cmd = (struct c_cq_cmd *)&cq->cmds32[cq->wp32];
+
+	/* Command opcode and DFA must be cleared */
+	memset(cmd, 0, 8);
+	cmd->command.cmd_type = C_CMD_TYPE_CQ;
+	cmd->command.cmd_size = cmd_size;
+	cmd->command.opcode = C_CMD_CQ_LCID;
+	cmd->lcid = lcid;
+
+	__cxi_cq_advance_wp(cq, cmd_size);
+
+	rc = cxi_cq_emit_cq_cmd(cq, C_CMD_CQ_NOOP);
+	if (rc)
+		return -ENOSPC;	/* not possible */
+
+	return 0;
+}
+
+/**
+ * cxi_cq_emit_cmd() - Emit the given command.
+ *
+ * The command may use 1 to 4 slots. Padding will be added if needed.
+ */
+static inline s32
+cxi_cq_emit_cmd(struct cxi_cq *cq, const union c_cmdu *cmd_in,
+		size_t cmd_length)
+{
+	struct c_cmd *cmd;
+	const enum c_cmd_size cmd_size = __cxi_cmd_size(cmd_length);
+	s32 rc;
+
+	rc = cxi_cq_align_for_cmd(cq, cmd_size);
+	if (rc)
+		return rc;
+
+	cmd = (struct c_cmd *)&cq->cmds32[cq->wp32];
+	memcpy(cmd, cmd_in, cmd_length);
+	cmd->cmd_size = cmd_size;
+
+	__cxi_cq_advance_wp(cq, cmd_size);
+
+	return 0;
+}
+
+/**
+ * cxi_cq_emit_c_state() - Emit an IDC C_STATE command.
+ *
+ * the command uses 1 slot. Padding will be added if needed.
+ */
+static inline s32
+cxi_cq_emit_c_state(struct cxi_cq *cq, const struct c_cstate_cmd *cmd_in)
+{
+	struct c_cstate_cmd *cmd;
+	s32 rc;
+
+	rc = cxi_cq_align_for_cmd(cq, C_CMD_SIZE_32B);
+	if (rc)
+		return -ENOSPC;
+
+	cmd = (struct c_cstate_cmd *)&cq->cmds32[cq->wp32];
+
+	*cmd = *cmd_in;
+
+	cmd->command.cmd_type = C_CMD_TYPE_IDC;
+	cmd->command.cmd_size = C_CMD_SIZE_32B;	/* Always 32 bytes */
+	cmd->command.opcode = C_CMD_CSTATE;
+	cmd->length = sizeof(struct c_cstate_cmd);
+
+	__cxi_cq_advance_wp(cq, C_CMD_SIZE_32B);
+
+	return 0;
+}
+
+/**
+ * cxi_cq_emit_idc_put() - Emit an IDC PUT command.
+ *
+ * May use 1 to 4 slots. Padding will be added if needed.
+ */
+static inline s32
+cxi_cq_emit_idc_put(struct cxi_cq *cq, const struct c_idc_put_cmd *cmd_in,
+		    const void *payload, size_t payload_length)
+{
+	struct c_idc_put_cmd *cmd;
+	const enum c_cmd_size cmd_size = __cxi_cmd_size(16 + payload_length);
+	s32 rc;
+
+	rc = cxi_cq_align_for_cmd(cq, cmd_size);
+	if (rc)
+		return rc;
+
+	cmd = (struct c_idc_put_cmd *)&cq->cmds32[cq->wp32];
+
+	*cmd = *cmd_in;
+
+	cmd->idc_header.command.cmd_size = cmd_size;
+	cmd->idc_header.command.cmd_type = C_CMD_TYPE_IDC;
+	cmd->idc_header.command.opcode = C_CMD_PUT;
+
+	memcpy(cmd->data, payload, payload_length);
+
+	/* account for header */
+	cmd->idc_header.length = sizeof(cmd->idc_header) + payload_length;
+
+	__cxi_cq_advance_wp(cq, cmd_size);
+
+	return 0;
+}
+
+/**
+ * cxi_cq_emit_idc_msg() - Emit an IDC small message command.
+ *
+ * May use 1 to 4 slots. Padding will be added if needed.
+ *
+ * May return -EINVAL if payload_length is greater than
+ * C_MAX_IDC_PAYLOAD_UNR
+ */
+static inline s32
+cxi_cq_emit_idc_msg(struct cxi_cq *cq, const struct c_idc_msg_hdr *cmd_in,
+		    const void *payload, size_t payload_length)
+{
+	struct c_idc_msg_hdr *cmd;
+	enum c_cmd_size cmd_size =
+		__cxi_cmd_size(sizeof(struct c_idc_msg_hdr) + payload_length);
+	s32 rc;
+
+	if (payload_length > C_MAX_IDC_PAYLOAD_UNR)
+		return -EINVAL;
+	if (cmd_size == C_CMD_SIZE_32B)
+		cmd_size = C_CMD_SIZE_64B;	/* Minimum size is 64B */
+
+	rc = cxi_cq_align_for_cmd(cq, cmd_size);
+	if (rc)
+		return rc;
+
+	cmd = (struct c_idc_msg_hdr *)&cq->cmds32[cq->wp32];
+
+	*cmd = *cmd_in;
+
+	cmd->command.cmd_size = cmd_size;
+	cmd->command.cmd_type = C_CMD_TYPE_IDC;
+	cmd->command.opcode = C_CMD_SMALL_MESSAGE;
+
+	memcpy(cmd->data, payload, payload_length);
+
+	/* account for header */
+	cmd->length = sizeof(struct c_idc_msg_hdr) + payload_length;
+
+	__cxi_cq_advance_wp(cq, cmd_size);
+
+	return 0;
+}
+
+/**
+ * cxi_cq_emit_idc_eth() - Emit an IDC Ethernet command.
+ *
+ * May use 1 to 4 slots. Padding will be added if needed.
+ */
+static inline s32
+cxi_cq_emit_idc_eth(struct cxi_cq *cq, const struct c_idc_eth_cmd *cmd_in,
+		    const void *payload, size_t payload_length)
+{
+	struct c_idc_eth_cmd *cmd;
+	const u64 len = sizeof(struct c_idc_eth_cmd) + payload_length;
+	const enum c_cmd_size cmd_size = __cxi_cmd_size(len);
+	s32 rc;
+
+	rc = cxi_cq_align_for_cmd(cq, cmd_size);
+	if (rc)
+		return rc;
+
+	cmd = (struct c_idc_eth_cmd *)&cq->cmds32[cq->wp32];
+
+	*cmd = *cmd_in;
+
+	cmd->command.cmd_size = cmd_size;
+	cmd->command.cmd_type = C_CMD_TYPE_IDC;
+	cmd->command.opcode = C_CMD_ETHERNET_TX;
+
+	memcpy(cmd->data, payload, payload_length);
+
+	cmd->length = len;
+
+	__cxi_cq_advance_wp(cq, cmd_size);
+
+	return 0;
+}
+
+/**
+ * cxi_cq_emit_idc_amo() - Emit an IDC AMO command.
+ *
+ * If possible, emit the AMO with a small_amo request.
+ */
+static inline s32
+cxi_cq_emit_idc_amo(struct cxi_cq *cq, const struct c_idc_amo_cmd *cmd_in,
+		    bool fetching)
+{
+	s32 rc;
+	enum c_cmd_size cmd_size;
+
+	if (cmd_in->atomic_type == C_AMO_TYPE_DOUBLE_COMPLEX_T ||
+	    cmd_in->atomic_op == C_AMO_OP_CSWAP ||
+	    cmd_in->atomic_op == C_AMO_OP_AXOR ||
+	    fetching) {
+		struct c_idc_amo_cmd *cmd;
+
+		cmd_size = C_CMD_SIZE_64B;
+
+		rc = cxi_cq_align_for_cmd(cq, cmd_size);
+		if (rc)
+			return rc;
+
+		cmd = (struct c_idc_amo_cmd *)&cq->cmds32[cq->wp32];
+
+		*cmd = *cmd_in;
+
+		cmd->idc_header.command.cmd_size = cmd_size;
+		cmd->idc_header.command.cmd_type = C_CMD_TYPE_IDC;
+		cmd->idc_header.command.opcode =
+			fetching ? C_CMD_FETCHING_ATOMIC : C_CMD_ATOMIC;
+
+		/* Large AMOs always have a length of 64 bytes. */
+		cmd->idc_header.length = sizeof(*cmd);
+	} else {
+		struct c_idc_put_cmd *cmd;
+		struct c_small_amo_payload *payload;
+
+		cmd_size = C_CMD_SIZE_32B;
+
+		rc = cxi_cq_align_for_cmd(cq, cmd_size);
+		if (rc)
+			return rc;
+
+		cmd = (struct c_idc_put_cmd *)&cq->cmds32[cq->wp32];
+		payload = (struct c_small_amo_payload *)cmd->data;
+
+		cmd->idc_header = cmd_in->idc_header;
+
+		cmd->idc_header.command.cmd_size = cmd_size;
+		cmd->idc_header.command.cmd_type = C_CMD_TYPE_IDC;
+		cmd->idc_header.command.opcode = C_CMD_ATOMIC;
+
+		/* Small AMOs always have a length of 32 bytes. */
+		cmd->idc_header.length = 32;
+
+		payload->amo_op = cmd_in->atomic_op;
+		payload->amo_type = cmd_in->atomic_type;
+		payload->op1_word1 = cmd_in->op1_word1;
+	}
+
+	__cxi_cq_advance_wp(cq, cmd_size);
+
+	return 0;
+}
+
+/**
+ * cxi_cq_emit_dma_amo() - Emit a DMA AMO command.
+ *
+ * Uses 2 slots. Padding will be added if needed.
+ */
+static inline s32
+cxi_cq_emit_dma_amo(struct cxi_cq *cq, struct c_dma_amo_cmd *cmd_in,
+		    bool fetching)
+{
+	struct c_dma_amo_cmd *cmd;
+	const enum c_cmd_size cmd_size = C_CMD_SIZE_128B;
+	s32 rc;
+
+	rc = cxi_cq_align_for_cmd(cq, cmd_size);
+	if (rc)
+		return rc;
+
+	cmd = (struct c_dma_amo_cmd *)&cq->cmds32[cq->wp32];
+
+	*cmd = *cmd_in;
+
+	cmd->command.cmd_size = cmd_size;
+	cmd->command.cmd_type = C_CMD_TYPE_DMA;
+	cmd->command.opcode =
+		fetching ? C_CMD_FETCHING_ATOMIC : C_CMD_ATOMIC;
+	cmd->request_len = amo_size[cmd->atomic_type];
+
+	__cxi_cq_advance_wp(cq, cmd_size);
+
+	return 0;
+}
+
+/**
+ * cxi_cq_emit_dma_eth() - Emit a DMA ethernet command.
+ */
+static inline s32
+cxi_cq_emit_dma_eth(struct cxi_cq *cq, const struct c_dma_eth_cmd *cmd_in)
+{
+	const enum c_cmd_size cmd_size = C_CMD_SIZE_128B;
+	struct c_dma_eth_cmd *cmd;
+	u32 total_len = 0;
+	s32 rc;
+	s32 i;
+
+	rc = cxi_cq_align_for_cmd(cq, cmd_size);
+	if (rc)
+		return rc;
+
+	cmd = (struct c_dma_eth_cmd *)&cq->cmds32[cq->wp32];
+
+	*cmd = *cmd_in;
+
+	cmd->command.cmd_type = C_CMD_TYPE_DMA;
+	cmd->command.cmd_size = cmd_size;
+	cmd->command.opcode = C_CMD_ETHERNET_TX;
+
+	for (i = 0; i < cmd_in->num_segments; i++)
+		total_len += cmd_in->len[i];
+	cmd->total_len = total_len;
+
+	__cxi_cq_advance_wp(cq, cmd_size);
+
+	return 0;
+}
+
+/**
+ * cxi_cq_emit_dma() - Emit a non restricted DMA command.
+ */
+static inline s32
+cxi_cq_emit_dma(struct cxi_cq *cq, struct c_full_dma_cmd *cmd_in)
+{
+	struct c_full_dma_cmd *cmd;
+	s32 rc;
+	const enum c_cmd_size cmd_size = C_CMD_SIZE_64B;
+
+	rc = cxi_cq_align_for_cmd(cq, cmd_size);
+	if (rc)
+		return rc;
+
+	cmd = (struct c_full_dma_cmd *)&cq->cmds32[cq->wp32];
+
+	*cmd = *cmd_in;
+
+	cmd->command.cmd_type = C_CMD_TYPE_DMA;
+	cmd->command.cmd_size = cmd_size;
+
+	__cxi_cq_advance_wp(cq, cmd_size);
+
+	return 0;
+}
+
+/**
+ * cxi_cq_emit_nomatch_dma() - Emit a non-matching DMA command.
+ *
+ * This command is used to target a non-matching PtlTE where remote target
+ * events are not needed (restricted send option bit is always set). Valid
+ * command operations are CMD_NOMATCH_GET and CMD_NOMATCH_PUT.
+ *
+ * Note: With this command, only errors will be generated on the EQ. Use
+ * cxi_cq_emit_dma() with the restricted bit set if per transaction success
+ * events are needed.
+ */
+static inline s32
+cxi_cq_emit_nomatch_dma(struct cxi_cq *cq, struct c_nomatch_dma_cmd *cmd_in)
+{
+	struct c_nomatch_dma_cmd *cmd;
+	s32 rc;
+	const enum c_cmd_size cmd_size = C_CMD_SIZE_32B;
+
+	rc = cxi_cq_align_for_cmd(cq, cmd_size);
+	if (rc)
+		return rc;
+
+	cmd = (struct c_nomatch_dma_cmd *)&cq->cmds32[cq->wp32];
+
+	*cmd = *cmd_in;
+
+	cmd->command.cmd_type = C_CMD_TYPE_DMA;
+	cmd->command.cmd_size = cmd_size;
+	cmd->restricted = 1;
+
+	__cxi_cq_advance_wp(cq, cmd_size);
+
+	return 0;
+}
+
+/**
+ * cxi_cq_emit_target() - Emit a target command.
+ *
+ * All the target commands (c_target_cmd and c_set_state) are 64
+ * bytes.
+ */
+static inline s32
+cxi_cq_emit_target(struct cxi_cq *cq, const void *cmd_in)
+{
+	const enum c_cmd_size cmd_size = C_CMD_SIZE_64B;
+	struct c_target_cmd *cmd;
+
+	/* Space available in the queue */
+	if (__cxi_cq_free_slots(cq) < (int)__cxi_cmd_slots[cmd_size])
+		return -ENOSPC;
+
+	cmd = (struct c_target_cmd *)&cq->cmds32[cq->wp32];
+
+	memcpy(cmd, cmd_in, sizeof(*cmd));
+
+	cmd->command.cmd_type = C_CMD_TYPE_CQ;
+	cmd->command.cmd_size = cmd_size;
+
+	__cxi_cq_advance_wp(cq, cmd_size);
+
+	return 0;
+}
+
+/**
+ * cxi_cq_emit_ct() - Emit a counting event (CT) command without embedded data.
+ *
+ * This function can also be used for trigger event, trigger inc, and trigger
+ * set.
+ */
+static inline s32
+cxi_cq_emit_ct(struct cxi_cq *cq, u32 opcode,
+	       const struct c_ct_cmd *cmd_in)
+{
+	const enum c_cmd_size cmd_size = C_CMD_SIZE_64B;
+	struct c_ct_cmd *cmd;
+
+	/* Space available in the queue */
+	if (__cxi_cq_free_slots(cq) < (int)__cxi_cmd_slots[cmd_size])
+		return -ENOSPC;
+
+	cmd = (struct c_ct_cmd *)&cq->cmds32[cq->wp32];
+
+	*cmd = *cmd_in;
+
+	cmd->command.cmd_type = C_CMD_TYPE_CT;
+	cmd->command.cmd_size = cmd_size;
+	cmd->command.opcode = opcode;
+
+	__cxi_cq_advance_wp(cq, cmd_size);
+
+	return 0;
+}
+
+/**
+ * cxi_cq_emit_trig_full_dma() - Emit a triggered full DMA command.
+ *
+ * Trigger command with embedded data is always 128 bytes.
+ */
+static inline s32
+cxi_cq_emit_trig_full_dma(struct cxi_cq *cq,
+			  const struct c_ct_cmd *cmd_in,
+			  const struct c_full_dma_cmd *dma_in)
+{
+	const enum c_cmd_size cmd_size = C_CMD_SIZE_128B;
+	struct c_ct_cmd *cmd;
+	struct c_full_dma_cmd *dma;
+	s32 rc;
+
+	rc = cxi_cq_align_for_ct128_cmd(cq);
+	if (rc)
+		return rc;
+
+	cmd = (struct c_ct_cmd *)&cq->cmds32[cq->wp32];
+	dma = (struct c_full_dma_cmd *)cmd->embedded_dma;
+
+	*cmd = *cmd_in;
+	*dma = *dma_in;
+
+	cmd->command.cmd_type = C_CMD_TYPE_CT;
+	cmd->command.cmd_size = cmd_size;
+	cmd->command.opcode = C_CMD_CT_TRIG_DMA;
+
+	dma->command.cmd_type = C_CMD_TYPE_DMA;
+	dma->command.cmd_size = C_CMD_SIZE_64B;
+
+	__cxi_cq_advance_wp(cq, cmd_size);
+
+	return 0;
+}
+
+/**
+ * cxi_cq_emit_trig_nomatch_dma() - Emit a triggered nomatch DMA command.
+ *
+ * Trigger command with embedded data is always 128 bytes.
+ */
+static inline s32
+cxi_cq_emit_trig_nomatch_dma(struct cxi_cq *cq,
+			     const struct c_ct_cmd *cmd_in,
+			     const struct c_nomatch_dma_cmd *dma_in)
+{
+	const enum c_cmd_size cmd_size = C_CMD_SIZE_128B;
+	struct c_ct_cmd *cmd;
+	struct c_nomatch_dma_cmd *dma;
+	s32 rc;
+
+	rc = cxi_cq_align_for_ct128_cmd(cq);
+	if (rc)
+		return rc;
+
+	cmd = (struct c_ct_cmd *)&cq->cmds32[cq->wp32];
+	dma = (struct c_nomatch_dma_cmd *)cmd->embedded_dma;
+
+	*cmd = *cmd_in;
+	*dma = *dma_in;
+
+	cmd->command.cmd_type = C_CMD_TYPE_CT;
+	cmd->command.cmd_size = cmd_size;
+	cmd->command.opcode = C_CMD_CT_TRIG_DMA;
+
+	dma->command.cmd_type = C_CMD_TYPE_DMA;
+	dma->command.cmd_size = C_CMD_SIZE_32B;
+	dma->restricted = 1;
+
+	__cxi_cq_advance_wp(cq, cmd_size);
+
+	return 0;
+}
+
+/**
+ * cxi_cq_emit_trig_dma_amo() Emit a triggered DMA AMO command.
+ *
+ * Trigger command with embedded data is always 128 bytes.
+ */
+static inline s32
+cxi_cq_emit_trig_dma_amo(struct cxi_cq *cq,
+			 const struct c_ct_cmd *cmd_in,
+			 const struct c_dma_amo_cmd *amo_in,
+			 bool fetching)
+{
+	const enum c_cmd_size cmd_size = C_CMD_SIZE_128B;
+	struct c_ct_cmd *cmd;
+	struct c_dma_amo_cmd *amo;
+	s32 rc;
+
+	rc = cxi_cq_align_for_ct128_cmd(cq);
+	if (rc)
+		return rc;
+
+	cmd = (struct c_ct_cmd *)&cq->cmds32[cq->wp32];
+	amo = (struct c_dma_amo_cmd *)cmd->embedded_dma;
+
+	*cmd = *cmd_in;
+	*amo = *amo_in;
+
+	cmd->command.cmd_type = C_CMD_TYPE_CT;
+	cmd->command.cmd_size = cmd_size;
+	cmd->command.opcode = C_CMD_CT_TRIG_DMA;
+
+	amo->command.cmd_type = C_CMD_TYPE_DMA;
+	amo->command.cmd_size = C_CMD_SIZE_128B;
+	amo->command.opcode =
+		fetching ? C_CMD_FETCHING_ATOMIC : C_CMD_ATOMIC;
+	amo->request_len = amo_size[amo->atomic_type];
+
+	__cxi_cq_advance_wp(cq, cmd_size);
+
+	return 0;
+}
+
+/**
+ * cxi_cq_init() - Initialize a command queue
+ * @cq: The command queue
+ * @cmds: The commands memory
+ * @count: Count (size) of command queue
+ * @launch_addr: The CQ launch address
+ * @cqn: Command queue number
+ */
+static inline void cxi_cq_init(struct cxi_cq *cq, struct cxi_cmd64 *cmds,
+			       u32 count, void *launch_addr,
+			       u32 idx)
+{
+	struct c_cmdq *la = (struct c_cmdq *)launch_addr;
+
+	cq->size = count;
+	cq->size32 = 2 * count;
+	cq->wp32 = C_CQ_FIRST_WR_PTR_32;
+	cq->hw_wp32 = cq->wp32;
+	cq->rp32 = cq->wp32;
+
+	/* Setting status pointer sets the commands pointer. */
+	if (cmds) {
+		cq->status = (struct c_cq_status *)&cmds[0];
+		cq->status->rd_ptr = C_CQ_FIRST_WR_PTR;
+		cq->status->return_code = C_RC_OK;
+	}
+
+	if (launch_addr) {
+		cq->wp_addr = (u64 *)launch_addr;
+		cq->ll_64 = (u8 *)la->ll_wr64a0123;
+		cq->ll_128a = (u8 *)la->ll_wr128a02;
+		cq->ll_128u = (u8 *)la->ll_wr128a13;
+	}
+	cq->idx = idx;
+}
+
+/**
+ * cxi_eq_empty() - Check if event queue is empty
+ */
+static inline bool cxi_eq_empty(struct cxi_eq *eq)
+{
+	u32 rd_offset = eq->rd_offset;
+	const union c_event *event = (union c_event *)(eq->events + rd_offset);
+
+	if (event->hdr.event_size == C_EVENT_SIZE_NO_EVENT)
+		return true;
+	else
+		return false;
+}
+
+/**
+ * cxi_eq_peek_event() - Get the next event on an event queue without advancing
+ *                       the software read pointer.
+ *
+ * Returns a pointer in the event queue.
+ */
+static inline const union c_event *cxi_eq_peek_event(struct cxi_eq *eq)
+{
+	u32 rd_offset = eq->rd_offset;
+	const volatile union c_event *event;
+	s32 rc_offset;
+
+again:
+	event = (union c_event *)(eq->events + rd_offset);
+
+	/* No event */
+	if (event->hdr.event_size == C_EVENT_SIZE_NO_EVENT)
+		return NULL;
+
+	/* Ensure the event has fully arrived by checking the return
+	 * code is not C_RC_NO_EVENT (0). The return_code is 6 bits in
+	 * the last byte of the event (so either offset 15, 31 or
+	 * 63). */
+	rc_offset = (8 << event->hdr.event_size) - 1;
+	if (((((u8 *)event)[rc_offset]) & 0x3f) == C_RC_NO_EVENT)
+		return NULL;
+
+	if (event->hdr.event_type == C_EVENT_NULL_EVENT) {
+		/* Consume the event and move to the next one */
+		rd_offset += (8 << event->hdr.event_size);
+		if (rd_offset >= eq->byte_size)
+			rd_offset = C_EE_CFG_ECB_SIZE;
+		eq->rd_offset = rd_offset;
+
+		goto again;
+	}
+
+	return (const union c_event *)event;
+}
+
+/**
+ * cxi_eq_next_event() - Advance the event queue to the next event.
+ */
+static inline void cxi_eq_next_event(struct cxi_eq *eq)
+{
+	const union c_event *event;
+	u32 rd_offset = eq->rd_offset;
+
+	event = (union c_event *)(eq->events + rd_offset);
+	rd_offset = eq->rd_offset + (8 << event->hdr.event_size);
+	if (rd_offset >= eq->byte_size)
+		rd_offset = C_EE_CFG_ECB_SIZE;
+	eq->rd_offset = rd_offset;
+}
+
+/**
+ * cxi_eq_get_event() - Get the next event on an event queue.
+ *
+ * Returns a pointer in the event queue. The event must be processed
+ * before calling cxi_eq_ack_events().
+ */
+static inline const union c_event *cxi_eq_get_event(struct cxi_eq *eq)
+{
+	const union c_event *event;
+
+	event = cxi_eq_peek_event(eq);
+	if (!event)
+		return NULL;
+
+	cxi_eq_next_event(eq);
+
+	return event;
+}
+
+/**
+ * cxi_eq_move_rp() - Move the EQ read pointer
+ * @eq: The EQ to have read pointer moved.
+ *
+ * There should be no need to call this function. Use cxi_eq_ack_events().
+ *
+ * Return: Updated read pointer
+ */
+static inline u64 cxi_eq_move_rp(struct cxi_eq *eq)
+{
+	u32 rd_offset = eq->rd_offset;
+	u32 prev_rd_offset = eq->prev_rd_offset;
+	u64 rd_ptr = rd_offset / C_EE_CFG_ECB_SIZE;
+	u8 *p = &eq->events[prev_rd_offset];
+
+	if (prev_rd_offset < rd_offset) {
+		memset(p, 0, rd_offset - prev_rd_offset);
+	} else if (prev_rd_offset > rd_offset) {
+		memset(p, 0, eq->byte_size - prev_rd_offset);
+		memset(eq->events + C_EE_CFG_ECB_SIZE, 0,
+		       rd_offset - C_EE_CFG_ECB_SIZE);
+	}
+	eq->prev_rd_offset = rd_offset;
+
+	return rd_ptr;
+}
+
+/**
+ * cxi_eq_ack_events() - Acknowledge consumed events in the event queue
+ *
+ * All events returned through cxi_eq_get_event() are cleared and the
+ * producer read pointer is advanced. These events must therefore be
+ * processed before calling this function.
+ *
+ * An application doesn't need to call this function after each event;
+ * it may process several events before.
+ */
+static inline void cxi_eq_ack_events(struct cxi_eq *eq)
+{
+	eq->sw_state.rd_ptr = cxi_eq_move_rp(eq);
+
+	*eq->sw_state_addr = eq->sw_state.qw;
+}
+
+/**
+ * cxi_eq_get_status() - Query for an event queue status update.
+ *
+ * Cassini updates event queue status when:
+ *
+ * -The number of free 64-byte events slots remaining in the queue crosses a
+ *  software configured threshold.
+ * -An event is dropped due to the event queue being full.
+ *
+ * Status fields of interest to providers are:
+ * -thld_sts: Asserted if the update was due to a fill threshold being crossed.
+ * -thld_id: Indicates the ID of the fill level threshold crossed (if thld_sts
+ *           is asserted).
+ * -unackd_dropped_event: Indicates that one or more events have been dropped
+ *                        since the last status update.
+ * -event_slots_free: The number of 64-byte event slots that were unused in the
+ *                    event queue buffer when the event queue status was updated.
+ * -timestamp_ns: The nanoseconds field of the real-time when the event queue
+ *                status was last updated.
+ * -timestamp_sec: The seconds field of the real-time when the event queue
+ *                 status was last updated.
+ *
+ * @eq: The event queue to query.
+ * @status: On success, contains a copy of the status update.
+ *
+ * Returns non-zero if a new event queue status update is available.
+ */
+static inline s32 cxi_eq_get_status(struct cxi_eq *eq,
+				    struct c_eq_status *status)
+{
+	struct c_eq_status status_cpy;
+	s32 tries = 100;
+
+	/* Fast path: return 0 if the last status looks old. */
+	if (eq->last_ts_ns == eq->status->timestamp_ns_cpy &&
+	    eq->last_ts_sec == eq->status->timestamp_sec_cpy)
+		return 0;
+
+	/* Read the entire status update. A status update may not be written
+	 * atomically on all architectures.  Re-read the full status until a
+	 * valid update is read.
+	 */
+	do {
+		memcpy(&status_cpy, eq->status, sizeof(status_cpy));
+
+		if (status_cpy.timestamp_ns == status_cpy.timestamp_ns_cpy &&
+		    status_cpy.timestamp_sec == status_cpy.timestamp_sec_cpy)
+			break;
+	} while (--tries);
+
+	/* Return 0 if a full status update was unavailable. */
+	if (!tries)
+		return 0;
+
+	/* Keep a record that we read this status update in software and return
+	 * the update.
+	 */
+	eq->last_ts_sec = status_cpy.timestamp_sec;
+	eq->last_ts_ns = status_cpy.timestamp_ns;
+
+	*status = status_cpy;
+	return 1;
+}
+
+/**
+ * cxi_eq_status_fill_level() - Return status update fill level.
+ *
+ * @eq: The EQ which generated the status update.
+ * @status: Pointer to a status update.
+ *
+ * Returns the fill level (as a percentage) reported by the provided status
+ * update. Valid only if status->thld_sts is set.
+ */
+static inline u32 cxi_eq_status_fill_level(struct cxi_eq *eq,
+						    struct c_eq_status *status)
+{
+	return 100 - status->event_slots_free * 100 /
+			(eq->byte_size / C_EE_CFG_ECB_SIZE);
+}
+
+/**
+ * cxi_eq_get_drops() - Return non-zero if new events have been dropped.
+ *
+ * When there is insufficient space in the EQ for events to be delivered, new
+ * events are dropped. In this case the NIC performs an EQ status write-back
+ * indicating events were dropped. All subsequent status write-backs will
+ * indicate that events were dropped until drops are acknowledged.
+ *
+ * After observing that events were dropped, a user should recover space in the
+ * EQ and then acknowledge the dropped events using cxi_eq_ack_drops(). After
+ * this call, subsequent EQ status write-backs will not indicate that events
+ * were dropped until new events are dropped.
+ */
+static inline s32 cxi_eq_get_drops(struct cxi_eq *eq)
+{
+	return eq->status->unackd_dropped_event;
+}
+
+/**
+ * cxi_eq_ack_drops() - Acknowledge dropped events in the event queue
+ */
+static inline void cxi_eq_ack_drops(struct cxi_eq *eq)
+{
+	eq->status->unackd_dropped_event = 0;
+	eq->sw_state.event_drop_seq_no = eq->status->event_drop_seq_no;
+	cxi_eq_ack_events(eq);
+}
+
+/**
+ * cxi_eq_int_enable() - Unmask EQ event interrupts
+ */
+static inline void cxi_eq_int_enable(struct cxi_eq *eq)
+{
+	eq->sw_state.event_int_disable = 0;
+	cxi_eq_ack_events(eq);
+}
+
+/**
+ * cxi_eq_int_disable() - Mask EQ event interrupts
+ */
+static inline void cxi_eq_int_disable(struct cxi_eq *eq)
+{
+	eq->sw_state.event_int_disable = 1;
+	cxi_eq_ack_events(eq);
+}
+
+/**
+ * cxi_eq_sts_int_enable() - Unmask EQ status update interrupts
+ */
+static inline void cxi_eq_sts_int_enable(struct cxi_eq *eq)
+{
+	eq->sw_state.eq_sts_int_disable = 0;
+	cxi_eq_ack_events(eq);
+}
+
+/**
+ * cxi_eq_sts_int_disable() - Mask EQ status update interrupts
+ */
+static inline void cxi_eq_sts_int_disable(struct cxi_eq *eq)
+{
+	eq->sw_state.eq_sts_int_disable = 1;
+	cxi_eq_ack_events(eq);
+}
+
+/**
+ * cxi_eq_init() - Initialize an event queue
+ * @eq: The event queue to initialize
+ * @events: The events buffer
+ * @size: Size in bytes of the events buffer
+ * @eqn: The EQ number to use in commands
+ * @sw_state_addr: Software state CSR address
+ */
+static inline void cxi_eq_init(struct cxi_eq *eq, u8 *events,
+			       u32 size, u32 eqn,
+			       u64 *sw_state_addr)
+{
+	eq->events = events;
+	eq->rd_offset = C_EE_CFG_ECB_SIZE;
+	eq->prev_rd_offset = C_EE_CFG_ECB_SIZE;
+	eq->byte_size = size;
+	eq->sw_state_addr = sw_state_addr;
+	eq->eqn = eqn;
+}
+
+#define CXI_MASK(n) ((1 << (n)) - 1)
+
+#define	CXI_MCAST_FA_FORMAT	0x1ff
+#define	CXI_MCAST_FA_ACTION	0x7
+#define CXI_DFA_EP_WIDTH	12
+#define CXI_DFA_EXT_WIDTH	5
+#define CXI_EP_WIDTH		(CXI_DFA_EP_WIDTH + CXI_DFA_EXT_WIDTH)
+#define CXI_DFA_EP_MASK		CXI_MASK(CXI_DFA_EP_WIDTH)
+#define CXI_DFA_EXT_MASK	CXI_MASK(CXI_DFA_EXT_WIDTH)
+
+/**
+ * cxi_build_dfa_ep() - Build 12 bit DFA EP Index.
+ * @pid: The DFA PID value.
+ * @pid_width: The DFA PID width.
+ * @idx: The DFA PTE index.
+ */
+static inline u32 cxi_build_dfa_ep(u32 pid, u32 pid_width,
+					u32 idx)
+{
+	return ((idx >> CXI_DFA_EXT_WIDTH) << pid_width) + pid;
+}
+
+/**
+ * cxi_build_dfa_ext() - Return 5 bit DFA extension.
+ * @idx: The DFA PTE index.
+ */
+static inline u32 cxi_build_dfa_ext(u32 idx)
+{
+	return idx & CXI_DFA_EXT_MASK;
+}
+
+/**
+ * cxi_dfa_ep() - Return 12 bit DFA EP.
+ * @dfa: The DFA to parse.
+ */
+static inline u32 cxi_dfa_ep(u32 dfa)
+{
+	return dfa & CXI_DFA_EP_MASK;
+}
+
+/**
+ * cxi_dfa_pid() - Return variable width DFA PID.
+ * @dfa: The DFA to parse.
+ */
+static inline u32 cxi_dfa_pid(u32 dfa, u32 pid_width)
+{
+	return dfa & CXI_MASK(pid_width);
+}
+
+/**
+ * cxi_dfa_nid() - Return 20 bit DFA NID.
+ * @dfa: The DFA to parse.
+ */
+static inline u32 cxi_dfa_nid(u32 dfa)
+{
+	return dfa >> CXI_DFA_EP_WIDTH;
+}
+
+/**
+ * cxi_dfa_to_init() - Convert 32 bit DFA to initiator ID.
+ * @dfa: The DFA to convert.
+ * @pid_width: The DFA PID width.
+ */
+static inline u32 cxi_dfa_to_init(u32 dfa, u32 pid_width)
+{
+	return CXI_MATCH_ID(pid_width,
+			    cxi_dfa_pid(dfa, pid_width),
+			    cxi_dfa_nid(dfa));
+}
+
+/**
+ * cxi_build_dfa() - Build a destination fabric address
+ * @nic_addr: Destination NIC address
+ * @pid: VNI partition
+ * @pid_granule: VNI partition granule
+ * @idx: Index into the VNI partition
+ * @dfa: Destination fabric address to be set
+ * @dfa_ext: DFA extension to be set
+ */
+static inline void cxi_build_dfa(u32 nic_addr, u32 pid,
+				 u32 pid_width, u32 idx,
+				 union c_fab_addr *dfa, u8 *dfa_ext)
+{
+	dfa->unicast.nid = nic_addr;
+	dfa->unicast.endpoint_defined = cxi_build_dfa_ep(pid, pid_width, idx);
+	*dfa_ext = cxi_build_dfa_ext(idx);
+}
+
+/**
+ * cxi_build_mcast_dfa() - Build a destination multicast fabric address
+ *
+ * @mcast_id: Destination multicast address
+ * @red_id: Reduction ID value
+ * @idx_ext: Multicast index extension
+ * @dfa: Destination fabric address to be set
+ * @dfa_ext: DFA extension to be set
+ */
+static inline void cxi_build_mcast_dfa(u32 mcast_id, u32 red_id,
+				       u32 idx_ext,
+				       union c_fab_addr *dfa, u8 *dfa_ext)
+{
+	memset(dfa, 0, sizeof(*dfa));
+	dfa->multicast.format = CXI_MCAST_FA_FORMAT;
+	dfa->multicast.reduction_id = red_id;
+	dfa->multicast.multicast_id = mcast_id;
+	dfa->multicast.action = CXI_MCAST_FA_ACTION;
+
+	*dfa_ext = cxi_build_dfa_ext(idx_ext);
+}
+
+/**
+ * cxi_ct_init() - Initialize a counter
+ * @ct: Counter to initialize
+ * @wb: Writeback buffer
+ * @doorbell_addr: Doorbell address
+ */
+static inline void cxi_ct_init(struct cxi_ct *ct, struct c_ct_writeback *wb,
+			       u32 ctn, u64 *doorbell_addr)
+{
+	ct->wb = wb;
+	ct->ctn = ctn;
+	ct->doorbell = doorbell_addr;
+}
+
+/**
+ * cxi_ct_inc_success() - Increment counter success value
+ * @ct: Counter
+ * @value: Value
+ *
+ * Note: Value is constrained to 48 bits.
+ */
+static inline void cxi_ct_inc_success(struct cxi_ct *ct, u64 value)
+{
+	ct->doorbell[CT_INC_SUCCESS_OFFSET / sizeof(u64)] =
+		value & CT_SUCCESS_MASK;
+}
+
+/**
+ * cxi_ct_inc_failure() - Increment counter failure value
+ * @ct: Counter
+ * @value: Value
+ *
+ * Note: Value is constrained to 7 bits.
+ */
+static inline void cxi_ct_inc_failure(struct cxi_ct *ct, u8 value)
+{
+	ct->doorbell[CT_INC_FAILURE_OFFSET / sizeof(u64)] =
+		value & CT_FAILURE_MASK;
+}
+
+/**
+ * cxi_ct_reset_success() - Reset success counter to zero.
+ * @ct: Counting event to be reset.
+ */
+static inline void cxi_ct_reset_success(struct cxi_ct *ct)
+{
+	ct->doorbell[CT_RESET_SUCCESS_OFFSET / sizeof(u64)] = 0;
+}
+
+/**
+ * cxi_ct_reset_failure() - Reset failure counter to zero.
+ * @ct: Counting event to be reset.
+ */
+static inline void cxi_ct_reset_failure(struct cxi_ct *ct)
+{
+	ct->doorbell[CT_RESET_FAILURE_OFFSET / sizeof(u64)] = 0;
+}
+
+#endif	/* __CXI_PROV_HW */
diff --git a/include/linux/hpe/cxi/driver.h b/include/linux/hpe/cxi/driver.h
new file mode 100644
index 000000000000..36cf0ba22081
--- /dev/null
+++ b/include/linux/hpe/cxi/driver.h
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause*/
+/*
+* Copyright 2026 Hewlett Packard Enterprise Development LP
+*/
+
+#ifndef __DRIVER_H__
+#define __DRIVER_H__
+#include <linux/auxiliary_bus.h>
+#include <linux/notifier.h>
+#include <linux/hpe/cxi/cxi.h>
+#include <linux/hpe/cxi/cxi_defs.h>
+
+struct cxi_adev {
+	struct auxiliary_device adev;
+	struct device *dev;
+	struct pci_dev *pdev;
+	void   *cxi_dev;
+	struct blocking_notifier_head nid_notifier;
+
+	struct cxi_lni *(*lni_alloc)(struct cxi_dev *cdev, unsigned int job_id);
+	int (*lni_free)(struct cxi_lni *lni);
+	int (*pid_alloc)(struct cxi_lni *lni);
+	void (*pid_free)(struct cxi_lni *lni, unsigned int pid);
+	void (*query_device)(void *cassdev);
+	struct cxi_md *(*cxi_map)(struct cxi_lni *lni, uintptr_t va, size_t len,
+			u32 flags, const struct cxi_md_hints *hints);
+	int (*dev_info_get)(struct cxi_dev *cdev, struct cxi_dev_info_use *info);
+	bool (*is_link_up)(struct cxi_dev *cdev);
+	int (*svc_get)(struct cxi_dev *cdev, unsigned int svc_id,
+			struct cxi_svc_desc *svc_desc);
+	int (*svc_rsrc_get)(struct cxi_dev *cdev, unsigned int svc_id,
+			    struct cxi_rsrc_use *use);
+	int (*svc_alloc)(struct cxi_dev *cdev,
+			 const struct cxi_svc_desc *svc_desc,
+			 struct cxi_svc_fail_info *fail_info, char *name);
+	int (*svc_destroy)(struct cxi_dev *cdev, unsigned int svc_id);
+	int (*svc_enable)(struct cxi_dev *cdev, unsigned int svc_id, bool enable);
+	int (*svc_set_vni_range)(struct cxi_dev *cdev, unsigned int svc_id,
+				 unsigned int first, unsigned int last);
+	int (*svc_get_vni_range)(struct cxi_dev *cdev, unsigned int svc_id,
+				 unsigned int *first, unsigned int *last);
+	int (*tc_cfg)(struct cxi_dev *cdev, unsigned int tc,
+		      enum cxi_traffic_class_type type);
+	int (*job_tc_bind)(struct cxi_dev *cdev, unsigned int job_id,
+			   unsigned int svc_id, unsigned int tc,
+			   enum cxi_traffic_class_type tc_type, bool create_tc,
+			   const struct cxi_rsrc_limits *limits,
+			   unsigned int *bound_svc_id, bool *created_tc);
+	int (*tc_clear)(struct cxi_dev *cdev, unsigned int tc,
+			 enum cxi_traffic_class_type tc_type);
+	int (*tc_list)(struct cxi_dev *cdev, struct cxi_tc_info *entries,
+			unsigned int max_entries, unsigned int *count);
+	int(*domain_reserve)(struct cxi_lni *lni, unsigned int vni,
+			unsigned int pid, unsigned int count);
+	struct cxi_domain *(*domain_alloc)(struct cxi_lni *lni,
+			unsigned int vni,
+			unsigned int pid);
+	void (*domain_free)(struct cxi_domain *domain);
+	struct cxi_cp *(*cp_alloc)(struct cxi_lni *lni,
+			unsigned int vni_pcp,
+			unsigned int tc,
+			enum cxi_traffic_class_type tc_type);
+	void (*cp_free)(struct cxi_cp *cp);
+	struct cxi_cq *(*cq_alloc)(struct cxi_lni *lni, struct cxi_eq *evtq,
+			const struct cxi_cq_alloc_opts *opts,
+			int numa_node);
+	void (*cq_free)(struct cxi_cq *cmdq);
+	struct cxi_pte *(*cxi_pte_alloc)(struct cxi_lni *lni, struct cxi_eq *evtq,
+			const struct cxi_pt_alloc_opts *opts);
+	void (*cxi_pte_free)(struct cxi_pte *pte);
+	int (*cq_user_info)(struct cxi_cq *cmdq, size_t *cmds_size,
+			struct page **cmds_pages,
+			phys_addr_t *wp_addr,
+			size_t *wp_addr_size);
+	struct cxi_eq *(*eq_alloc)(struct cxi_lni *lni, const struct cxi_md *md,
+			const struct cxi_eq_attr *attr,
+			void (*event_cb)(void *cb_data),
+			void *event_cb_data,
+			void (*status_cb)(void *cb_data),
+			void *status_cb_data);
+
+	int (*eq_free)(struct cxi_eq *evtq);
+	const union c_event *(*eq_get_event)(struct cxi_eq *eq);
+	void (*eq_next_event)(struct cxi_eq *eq);
+	struct cxi_ct *(*ct_alloc)(struct cxi_lni *lni,
+			struct c_ct_writeback *wb, bool is_user);
+	void (*ct_free)(struct cxi_ct *ct);
+
+	int (*clear_md)(struct cxi_md *md);
+	int (*eq_user_info)(struct cxi_eq *evtq,
+			phys_addr_t *csr_addr, size_t *csr_size);
+	int (*ct_user_info)(struct cxi_ct *ct,
+			phys_addr_t *doorbell_addr, size_t *doorbell_size);
+	int (*pte_unmap)(struct cxi_pte *pt,
+			struct cxi_domain *domain, int pt_index);
+	int (*pte_map)(struct cxi_pte *pt, struct cxi_domain *domain,
+			unsigned int pid_offset, bool is_multicast,
+			unsigned int *pt_index);
+	int (*cxi_unmap)(struct cxi_md *md);
+	u8 *(*get_mac_addr)(struct cxi_dev *dev);
+};
+#endif
diff --git a/include/linux/hpe/cxi/libcassini.h b/include/linux/hpe/cxi/libcassini.h
new file mode 100644
index 000000000000..8ea70a85b00b
--- /dev/null
+++ b/include/linux/hpe/cxi/libcassini.h
@@ -0,0 +1,1252 @@
+// SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
+/*
+ * Copyright 2018 Cray Inc. All rights reserved
+ *
+ * Cassini hardware definitions and accessors. This is the header to
+ * include Cassini hardware support.
+ *
+ * This header is only for entities that control the hardware (the
+ * kernel core driver, a bios driver, ...) Applications only include
+ * cxi_prov_hw.h.
+ */
+
+#ifndef __CXI_CASSINI_H
+#define __CXI_CASSINI_H
+
+#ifndef __KERNEL__
+#include <stdbool.h>
+#endif
+
+#include <uapi/ethernet/cassini_user_defs.h>
+#include "cxi_prov_hw.h"
+
+/**
+ * cass_write() - Write to the adapter in 64-bits words
+ *
+ * Modify a control status register (CSR) on BAR0.
+ *
+ * @hw: the device
+ * @offset: offset of the CSR in the region
+ * @data_in: buffer with the data to write
+ * @len: length to write, in bytes. Must be a multiple of 8.
+ */
+static inline void cass_write(struct cass_dev *hw, u64 offset,
+			      const void *data_in, size_t len)
+{
+	void __iomem *base = cass_csr(hw, offset);
+	const u64 *data = data_in;
+	int i;
+
+	len /= sizeof(u64);
+
+	for (i = 0; i < len; i++, base += sizeof(u64))
+		writeq(data[i], base);
+}
+
+/**
+ * cass_read() - Read from the adapter in 64-bits words
+ *
+ * Read a CSR on BAR0.
+ *
+ * @hw: the device
+ * @offset: offset of the CSR in the region
+ * @data_out: buffer to store the result
+ * @len: length to read, in bytes. Must be a multiple of 8.
+ */
+static inline void cass_read(struct cass_dev *hw, u64 offset, void *data_out, size_t len)
+{
+	void __iomem *base = cass_csr(hw, offset);
+	u64 *data = data_out;
+	int i;
+
+	len /= sizeof(u64);
+
+	for (i = 0; i < len; i++, base += sizeof(u64))
+		data[i] = readq(base);
+}
+
+/* Assume that shadow CSRs are at same offset across all blocks. This
+ * is not true for IXE and SS2_PORT_PML, but shadow CSRs are not used
+ * for these.
+ */
+#define SHADOW_OFFSET C_ATU_MSC_SHADOW_OFFSET
+#define SHADOW_ACTION_OFFSET C_ATU_MSC_SHADOW_ACTION_OFFSET
+
+struct hni_data4_full_amo {
+	struct c_port_unrestricted_hdr full;
+	struct c_port_amo_payload payload;
+} __attribute__((packed));
+
+/* IPV4 and generic Portals header. */
+struct hni_header4 {
+	struct c_port_fab_hdr hdr;
+	union {
+		struct c_pkt_type		pkt_type;
+		struct c_port_unrestricted_hdr	full;
+		struct c_port_small_msg_hdr	small_msg;
+		struct c_port_continuation_hdr	cont;
+		struct c_port_restricted_hdr	restricted;
+		struct hni_data4_full_amo	full_amo;
+	};
+};
+
+/* Small packet format. */
+struct hni_header_vs {
+	struct c_port_fab_vs_hdr	hdr;
+	struct c_pkt_type		pkt_type;
+	/* May need to expand union */
+	union {
+		struct c_port_restricted_hdr	req;
+	};
+};
+
+/* IPV6 header. */
+struct hni_header6 {
+	u32	version  : 4;
+	u32	tc       : 8;
+	u32	flowLab  :20;	/* Flow Label */
+	u16	length;		/* Payload length */
+	u8		nextHead;	/* Next Header */
+	u8		hopLimit;
+	u32	srcIP[4];
+	u32	dstIP[4];
+};
+
+struct hni_ver {
+    u8 unused : 4;
+    u8 ver    : 4;
+};
+
+union hni_header {
+    struct hni_ver      ver;
+	struct hni_header4   h4;
+	struct hni_header_vs vs;
+	struct hni_header6   h6;
+};
+
+/**
+ * cass_flush_pci() - Flush the PCI bus for the device
+ *
+ * Since PCI bus writes are posted asynchronously, force them to reach
+ * the device. This is needed when some resources are allocated or
+ * freed. Any CSR read is good.
+ */
+static inline void cass_flush_pci(struct cass_dev *dev)
+{
+	union c_mb_sts_rev rev;
+
+	cass_read(dev, C_MB_STS_REV, &rev, sizeof(rev));
+}
+
+/**
+ * cass_shadow_write_prepare() - copy the CSR data to the shadow region.
+ *
+ * This is called before cass_shadow_write_do() to prepare the shadow
+ * write. It is useful when the same data must be copied to many CSRs
+ * through the shadow region. Otherwise it is easier to use
+ * cass_shadow_write().
+ */
+static inline void
+cass_shadow_write_prepare(struct cass_dev *dev, unsigned int block_base,
+			  const void *csr_value,
+			  unsigned int csr_length)
+{
+	cass_write(dev, block_base + SHADOW_OFFSET, csr_value, csr_length);
+}
+
+/**
+ * cass_shadow_write_do() - Perform a shadow write
+ *
+ * Ring the corresponding CSR. cass_shadow_write_prepare() must be
+ * called first to prepare the data to write to the CSR.
+ */
+static inline void
+cass_shadow_write_do(struct cass_dev *dev, unsigned int block_base,
+		     unsigned int addr_offset)
+{
+	union c_msc_shadow_action shadow = {
+		.write = 1,
+		.addr_offset = addr_offset
+	};
+
+	cass_write(dev, block_base + SHADOW_ACTION_OFFSET, &shadow,
+		   sizeof(shadow));
+}
+
+/**
+ * cass_shadow_write() - Perform a shadow write
+ */
+static inline void
+cass_shadow_write(struct cass_dev *dev, unsigned int block_base,
+		  unsigned int addr_offset, const void *csr_value,
+		  unsigned int csr_length)
+{
+	cass_shadow_write_prepare(dev, block_base, csr_value, csr_length);
+	cass_shadow_write_do(dev, block_base, addr_offset);
+}
+
+/**
+ * cass_shadow_read() - Perform a shadow read
+ */
+static inline void
+cass_shadow_read(struct cass_dev *dev, unsigned int block_base,
+		 unsigned int addr_offset, void *csr_value,
+		 unsigned int csr_length)
+{
+	union c_msc_shadow_action shadow = {
+		.write = 0,
+		.addr_offset = addr_offset
+	};
+
+	cass_write(dev, block_base + SHADOW_ACTION_OFFSET, &shadow,
+		   sizeof(shadow));
+
+	cass_read(dev, block_base + SHADOW_OFFSET, csr_value, csr_length);
+}
+
+/**
+ * cass_tx_cq_init() - Configure a transmit CQ
+ */
+static inline void cass_tx_cq_init(struct cass_dev *dev, struct cxi_cq *cq,
+				   unsigned int cq_num,
+				   const union c_cq_txq_tc_table *tc,
+				   const union c_cq_txq_base_table *cfg)
+{
+	const union c_cq_txq_wrptr_table wrptr = {
+		.mem_q_wr_ptr = C_CQ_FIRST_WR_PTR,
+	};
+
+	cass_write(dev, C_CQ_TXQ_TC_TABLE(cq_num), tc, sizeof(*tc));
+	cass_write(dev, C_CQ_TXQ_WRPTR_TABLE(cq_num), &wrptr, sizeof(wrptr));
+
+	cass_shadow_write(dev, C_CQ_BASE, C_CQ_TXQ_BASE_TABLE(cq_num),
+			  cfg, sizeof(*cfg));
+}
+
+/**
+ * cass_tgt_cq_init() - Configure a target CQ
+ */
+static inline void
+cass_tgt_cq_init(struct cass_dev *dev, struct cxi_cq *cq,
+		 unsigned int cq_num, const union c_cq_tgq_table *cfg)
+{
+	const union c_cq_tgq_wrptr_table wrptr = {
+		.mem_q_wr_ptr = C_CQ_FIRST_WR_PTR,
+	};
+
+	cass_write(dev, C_CQ_TGQ_WRPTR_TABLE(cq_num), &wrptr, sizeof(wrptr));
+
+	cass_shadow_write(dev, C_CQ_BASE, C_CQ_TGQ_TABLE(cq_num),
+			  cfg, sizeof(*cfg));
+}
+
+/**
+ * cass_tx_cq_enable() - Enable a transmit CQ
+ */
+static inline void
+cass_tx_cq_enable(struct cass_dev *dev, unsigned int cq_num)
+{
+	const union c_cq_txq_enable cfg = {
+		.txq_enable = 1,
+	};
+
+	cass_write(dev, C_CQ_TXQ_ENABLE(cq_num), &cfg, sizeof(cfg));
+
+	cass_flush_pci(dev);
+}
+
+/**
+ * cass_tgt_cq_enable() - Enable a target CQ
+ */
+static inline void
+cass_tgt_cq_enable(struct cass_dev *dev, unsigned int cq_num)
+{
+	const union c_cq_tgq_enable cfg = {
+		.tgq_enable = 1,
+	};
+
+	cass_write(dev, C_CQ_TGQ_ENABLE(cq_num), &cfg, sizeof(cfg));
+
+	cass_flush_pci(dev);
+}
+
+/**
+ * cass_tx_cq_disable() - Disable a transmit CQ
+ */
+static inline void
+cass_tx_cq_disable(struct cass_dev *dev, unsigned int cq_num)
+{
+	const union c_cq_txq_enable cfg = {
+			.drain = 1,
+	};
+
+	cass_write(dev, C_CQ_TXQ_ENABLE(cq_num), &cfg, sizeof(cfg));
+
+	cass_flush_pci(dev);
+}
+
+/**
+ * cass_tgt_cq_disable() - Disable a target CQ
+ */
+static inline void
+cass_tgt_cq_disable(struct cass_dev *dev, unsigned int cq_num)
+{
+	const union c_cq_tgq_enable cfg = {
+		.drain = 1,
+	};
+
+	cass_write(dev, C_CQ_TGQ_ENABLE(cq_num), &cfg, sizeof(cfg));
+
+	cass_flush_pci(dev);
+}
+
+/**
+ * cass_eq_set_event_format() - Set default event size
+ *
+ * Tell Cassini to use short or large events for the EQ. By default,
+ * Cassini will use short event format if possible.
+ *
+ * Since the CSR accessed is shared by 32 EQs, access to this function
+ * must be serialized.
+ *
+ * @initr_use_long: If set, always use long format initiator events
+ * @trgt_use_long: If set, always use long format target events
+ */
+static inline void cass_eq_set_event_format(struct cass_dev *dev,
+					    unsigned int eq_num,
+					    bool initr_use_long,
+					    bool trgt_use_long)
+{
+	unsigned int index = eq_num / 32;
+	unsigned int offset = eq_num % 32 * 2;
+	u64 mask = 0b11UL << offset;
+	union c_ee_cfg_long_evnt_ovr_table ovr;
+
+	cass_read(dev, C_EE_CFG_LONG_EVNT_OVR_TABLE(index),
+		  &ovr.qw, sizeof(ovr));
+
+	ovr.qw &= ~mask;
+	mask = (u64)(trgt_use_long << 1 | initr_use_long) << offset;
+	ovr.qw |= mask;
+
+	cass_write(dev, C_EE_CFG_LONG_EVNT_OVR_TABLE(index),
+		   &ovr.qw, sizeof(ovr));
+}
+
+/**
+ * cass_eq_set_periodic_timestamp() - Enable/disable timestamp event generation
+ *
+ * Since the CSR accessed is shared by 64 EQs, access to this function
+ * must be serialized.
+ *
+ * @dev: the Cassini device
+ * @eq_num: the EQ index
+ * @enable: whether to enable or disable the timestamp event generation
+ */
+static inline void cass_eq_set_periodic_timestamp(struct cass_dev *dev,
+						  unsigned int eq_num,
+						  bool enable)
+{
+	u64 mask = 1ULL << (eq_num & 0x3f);
+	union c_ee_cfg_periodic_tstamp_table cfg_periodic_tstamp;
+
+	cass_read(dev, C_EE_CFG_PERIODIC_TSTAMP_TABLE(eq_num / 64),
+		  &cfg_periodic_tstamp, sizeof(cfg_periodic_tstamp));
+
+	if (enable)
+		cfg_periodic_tstamp.n63_n0_enable_periodic_tstamp |= mask;
+	else
+		cfg_periodic_tstamp.n63_n0_enable_periodic_tstamp &= ~mask;
+
+	cass_write(dev, C_EE_CFG_PERIODIC_TSTAMP_TABLE(eq_num / 64),
+		   &cfg_periodic_tstamp, sizeof(cfg_periodic_tstamp));
+}
+
+/**
+ * cass_eq_init() - Initializes an event queue.
+ *
+ * @dev: Cassini device
+ * @eq_num: Event queue number
+ * @rgid: Resource group ID to assign the EQ to
+ * @cfg: Event queue initial configuration
+ * @initr_use_long: If true, always use long format for initiator events
+ * @trgt_use_long: If true, always use long format for initiator events
+ *
+ * Caller must ensure that C_EE_CFG_INIT_EQ_HW_STATE is ready to be
+ * used by checking its pending bit beforehand.
+ */
+static inline void cass_eq_init(struct cass_dev *dev, unsigned int eq_num,
+				u8 rgid, union c_ee_cfg_eq_descriptor *cfg,
+				bool initr_use_long, bool trgt_use_long)
+{
+	static const union c_ee_cfg_eq_sw_state sw_state = {};
+	const union c_ee_cfg_init_eq_hw_state hw_state = {
+		.eq_handle = eq_num
+	};
+	const union c_cq_cfg_eq_rgid_table cfg_rgid = { .rgid = rgid };
+	u64 csr;
+
+	cass_write(dev, C_CQ_CFG_EQ_RGID_TABLE(eq_num),
+		   &cfg_rgid, sizeof(cfg_rgid));
+
+	csr = C_EE_CFG_EQ_SW_STATE(eq_num);
+	cass_write(dev, csr, &sw_state, sizeof(sw_state));
+
+	csr = C_EE_CFG_INIT_EQ_HW_STATE;
+	cass_write(dev, csr, &hw_state, sizeof(hw_state));
+
+	/* Initialize the event queue descriptor */
+	cass_shadow_write(dev, C_EE_BASE, C_EE_CFG_EQ_DESCRIPTOR(eq_num),
+			  cfg, sizeof(*cfg));
+
+	cass_eq_set_event_format(dev, eq_num, initr_use_long, trgt_use_long);
+	cass_eq_set_periodic_timestamp(dev, eq_num, false);
+
+	cass_flush_pci(dev);
+}
+
+/**
+ * cass_eq_clear() - Clear the event queue configuration.
+ *
+ * Note: cass_eq_init() must be called before cass_eq_clear().
+ */
+static inline void cass_eq_clear(struct cass_dev *dev, struct cxi_eq *evtq)
+{
+	static const union c_ee_cfg_eq_descriptor cfg = {};
+	static const union c_cq_cfg_eq_rgid_table cfg_rgid = {
+		.rgid = C_RESERVED_RGID
+	};
+
+	cass_shadow_write(dev, C_EE_BASE, C_EE_CFG_EQ_DESCRIPTOR(evtq->eqn),
+			  &cfg, sizeof(cfg));
+
+	cass_write(dev, C_CQ_CFG_EQ_RGID_TABLE(evtq->eqn),
+		   &cfg_rgid, sizeof(cfg_rgid));
+
+	cass_flush_pci(dev);
+}
+
+/**
+ * cass_read_lpe_reserve_pool() - Get reserved entries in PE's pool
+ *
+ * pe is 0 to 3, pool is 0 to 15.
+ */
+static inline void
+cass_read_lpe_reserve_pool(struct cass_dev *dev, unsigned int pe,
+			   unsigned int pool,
+			   union c_lpe_cfg_pe_le_pools *alloc)
+{
+	u64 csr;
+
+	csr = C_LPE_CFG_PE_LE_POOLS(pe * (C_LPE_CFG_PE_LE_POOLS_ENTRIES / C_PE_COUNT) + pool);
+
+	cass_read(dev, csr, alloc, sizeof(*alloc));
+}
+
+/**
+ * cass_config_lpe_reserve_pool() - Reserve some entries in a PE's pool.
+ *
+ * Reserve some entries in pool 'pool' for Process Engine 'pe'.
+ * Return 0 if the adapter accepted the new setting, or a negative
+ * errno on error.
+ *
+ * pe is 0 to 3, pool is 0 to 15.
+ */
+static inline int
+cass_config_lpe_reserve_pool(struct cass_dev *dev, unsigned int pe,
+			     unsigned int pool,
+			     const union c_lpe_cfg_pe_le_pools *alloc)
+{
+	u64 csr;
+	union c_lpe_cfg_pe_le_pools alloc_check = {};
+
+	csr = C_LPE_CFG_PE_LE_POOLS(pe * (C_LPE_CFG_PE_LE_POOLS_ENTRIES / C_PE_COUNT) + pool);
+
+	cass_write(dev, csr, alloc, sizeof(*alloc));
+
+	/* Check the write was successful, as the spec recommends. */
+	cass_read(dev, csr, &alloc_check, sizeof(alloc_check));
+
+	if (alloc_check.num_reserved == alloc->num_reserved &&
+	    alloc_check.max_alloc == alloc->max_alloc) {
+		return 0;
+	} else {
+		return -EINVAL;
+	}
+}
+
+/**
+ * cass_lpe_reserve_pool_sts() - Get the number of used entries in a PE pool.
+ *
+ * pe is 0 to 3, pool is 0 to 15.
+ */
+static inline void
+cass_lpe_reserve_pool_sts(struct cass_dev *dev, unsigned int pe,
+			  unsigned int pool,
+			  union c_lpe_sts_pe_le_alloc *query)
+{
+	u64 csr;
+
+	csr = C_LPE_STS_PE_LE_ALLOC(pe * (C_LPE_STS_PE_LE_ALLOC_ENTRIES / C_PE_COUNT) + pool);
+	cass_read(dev, csr, query, sizeof(*query));
+}
+
+/**
+ * cass_read_lpe_shared_pool() - Get the number of shared list entries in a PE.
+ *
+ * pe is 0 to 3.
+ */
+static inline void
+cass_read_lpe_shared_pool(struct cass_dev *dev, unsigned int pe,
+			  union c_lpe_cfg_pe_le_shared *shared)
+{
+	u64 csr;
+
+	csr = C_LPE_CFG_PE_LE_SHARED(pe);
+
+	cass_read(dev, csr, shared, sizeof(*shared));
+}
+
+/**
+ * cass_config_lpe_shared_pool() - Configure the shared list entries in a PE.
+ *
+ * pe is 0 to 3.
+ */
+static inline int
+cass_config_lpe_shared_pool(struct cass_dev *dev, unsigned int pe,
+			    union c_lpe_cfg_pe_le_shared *shared)
+{
+	union c_lpe_cfg_pe_le_shared shared_check = {};
+	u64 csr;
+
+	csr = C_LPE_CFG_PE_LE_SHARED(pe);
+
+	cass_write(dev, csr, shared, sizeof(*shared));
+
+	/* Check the write was successful, as the spec recommends. */
+	cass_read(dev, csr, &shared_check, sizeof(shared_check));
+
+	if (shared_check.num_total == shared->num_total &&
+	    shared_check.num_shared == shared->num_shared) {
+		return 0;
+	} else {
+		return -EINVAL;
+	}
+}
+
+/**
+ * cass_read_le_state() - Read a list entry (LE) state
+ *
+ * Since this function uses C_LPE_MSC_SHADOW, its access must be
+ * serialized.
+ */
+static inline void cass_read_le_state(struct cass_dev *dev, unsigned int le_idx,
+				      union c_lpe_sts_list_entries *le_sts)
+{
+	cass_shadow_read(dev, C_LPE_BASE, C_LPE_STS_LIST_ENTRIES_OFFSET(le_idx),
+			 le_sts, sizeof(*le_sts));
+}
+
+/**
+ * cass_read_pte() - Read a Table Entry (PtlTE)
+ *
+ * Since this function uses C_LPE_MSC_SHADOW, its access must be
+ * serialized.
+ */
+static inline void cass_read_pte(struct cass_dev *dev, unsigned int pte_num,
+				 union c_lpe_cfg_ptl_table *ptl_table)
+{
+	cass_shadow_read(dev, C_LPE_BASE, C_LPE_CFG_PTL_TABLE_OFFSET(pte_num),
+			 ptl_table, sizeof(*ptl_table));
+}
+
+/**
+ * cass_config_pte() - Configure a Table Entry (PtlTE)
+ *
+ * Since this function uses C_LPE_MSC_SHADOW, its access must be
+ * serialized.
+ */
+static inline void cass_config_pte(struct cass_dev *dev, unsigned int pte_num,
+				   const union c_lpe_cfg_ptl_table *ptl_table)
+{
+	cass_shadow_write(dev, C_LPE_BASE, C_LPE_CFG_PTL_TABLE_OFFSET(pte_num),
+			  ptl_table, sizeof(*ptl_table));
+}
+
+/**
+ * cass_config_ac() - Configure an Address Context entry (AC)
+ *
+ * Since this function uses C_ATU_MSC_SHADOW, its access must be
+ * serialized.
+ */
+static inline void cass_config_ac(struct cass_dev *dev, unsigned int ac_num,
+				  const union c_atu_cfg_ac_table *atu_ac)
+{
+	cass_shadow_write(dev, C_ATU_BASE, C_ATU_CFG_AC_TABLE_OFFSET(ac_num),
+			  atu_ac, sizeof(*atu_ac));
+}
+
+/**
+ * cass_config_pi_acxt() - Configure a PI Address Context entry (AC)
+ */
+static inline void cass_config_pi_acxt(struct cass_dev *dev,
+				       unsigned int ac_num,
+				       const union c_pi_cfg_acxt *pi_acxt)
+{
+	cass_write(dev, C_PI_CFG_ACXT(ac_num), pi_acxt, sizeof(*pi_acxt));
+}
+
+/**
+ * cass_invalidate_vni_list() - Invalidate a VNI list entry.
+ */
+static inline void cass_invalidate_vni_list(struct cass_dev *dev,
+					    unsigned int idx)
+{
+	const union c_rmu_cfg_vni_list_invalidate
+		rmu_cfg_vni_list_invalidate = {
+		.invalidate = 1
+	};
+
+	cass_write(dev, C_RMU_CFG_VNI_LIST_INVALIDATE(idx),
+		   &rmu_cfg_vni_list_invalidate,
+		   sizeof(rmu_cfg_vni_list_invalidate));
+}
+
+/**
+ * cass_config_matching_vni_list() - Configure a VNI entry in the VNI list.
+ *
+ * The VNI is returned with cass_invalidate_vni_list().
+ *
+ * The X and Y CSRs are used to configure the VNI value for which the
+ * VNI List entry matches. If an exact match is required, the value to be
+ * matched is written to the X CSR array entry and the one's complement
+ * of the value to be matched is written to the Y CSR array entry.
+ *
+ * If any bits of the value are to be ignored when checking for a match,
+ * those bits are written with the value 0 in both the X and Y CSR array entries.
+ * X and Y of the same bit position should not both be written to the value 1;
+ * doing so leads to increased power consumption. However, it is acceptable
+ * for X and Y of the same bit position to both be 1 while the entry is in the
+ * invalid state and is being transitioned to a new value.
+ */
+static inline void cass_config_matching_vni_list(struct cass_dev *dev,
+						 unsigned int idx,
+						 unsigned int vni,
+						 unsigned int ignore)
+{
+	union c_rmu_cfg_vni_list rmu_cfg_vni_list;
+
+	/* Invalidate first */
+	cass_invalidate_vni_list(dev, idx);
+
+	/* Remove the ignore bits from the VNI. */
+	vni &= ~ignore;
+
+	rmu_cfg_vni_list.vni = vni;
+	cass_write(dev, C_RMU_CFG_VNI_LIST_X(idx),
+		   &rmu_cfg_vni_list, sizeof(rmu_cfg_vni_list));
+
+	rmu_cfg_vni_list.vni = ~vni & ~ignore;
+	cass_write(dev, C_RMU_CFG_VNI_LIST_Y(idx),
+		   &rmu_cfg_vni_list, sizeof(rmu_cfg_vni_list));
+}
+
+/**
+ * cass_config_vni_list() - Configure a VNI entry in the VNI list.
+ *
+ * Only exact matches are currently supported. The VNI is returned
+ * with cass_invalidate_vni_list().
+ */
+static inline void cass_config_vni_list(struct cass_dev *dev,
+					unsigned int idx,
+					unsigned int vni)
+{
+	cass_config_matching_vni_list(dev, idx, vni, 0);
+}
+
+/**
+ * cass_config_portal_index_table() - Set a portal index table entry.
+ *
+ * The corresponding entry must be invalidated first. Since each CSR
+ * addresses 4 different portal entries, and only one is changed,
+ * serialization must be ensured.
+ *
+ * @dev: Cassini device
+ * @plist_idx: portal list index
+ * @phys_ptn: portal number allocated on device
+ */
+static inline void
+cass_config_portal_index_table(struct cass_dev *dev, unsigned int plist_idx,
+			       unsigned int phys_ptn)
+{
+	union c_rmu_cfg_portal_index_table portal_index_table = {};
+	const unsigned int idx =
+		plist_idx / C_RMU_CFG_PORTAL_INDEX_TABLE_ARRAY_SIZE;
+	const unsigned int offset =
+		plist_idx % C_RMU_CFG_PORTAL_INDEX_TABLE_ARRAY_SIZE;
+
+	/* Read, modify, write */
+	cass_read(dev, C_RMU_CFG_PORTAL_INDEX_TABLE(idx),
+		  &portal_index_table, sizeof(portal_index_table));
+
+	portal_index_table.e[offset].phys_portal_table_idx = phys_ptn;
+
+	cass_write(dev, C_RMU_CFG_PORTAL_INDEX_TABLE(idx),
+		   &portal_index_table, sizeof(portal_index_table));
+}
+
+/**
+ * cass_invalidate_portal_list() - Invalidate a Portal list entry
+ */
+static inline void cass_invalidate_portal_list(struct cass_dev *dev,
+					       unsigned int idx)
+{
+	const union c_rmu_cfg_portal_list_invalidate
+		rmu_cfg_portal_list_invalidate = {
+		.invalidate = 1
+	};
+
+	cass_write(dev, C_RMU_CFG_PORTAL_LIST_INVALIDATE(idx),
+		   &rmu_cfg_portal_list_invalidate,
+		   sizeof(rmu_cfg_portal_list_invalidate));
+}
+
+/**
+ * cass_config_portal_list() - Configure a Portal list entry in the
+ * portals list, and its corresponding entry in the RMU portal index
+ * table.
+ *
+ * Only exact matches are supported.
+ *
+ * Since each portal index table CSR addresses 4 different portal
+ * entries, and only one is changed, serialization must be ensured.
+ *
+ * @dev: Cassini device
+ * @plist_idx: portal list index
+ * @phys_ptn: portal number allocated on device
+ * @cfg: pointer to the portal list configuration
+ */
+static inline void
+cass_config_portal_list(struct cass_dev *dev, unsigned int plist_idx,
+			unsigned int phys_ptn,
+			const union c_rmu_cfg_portal_list *cfg)
+{
+	union c_rmu_cfg_portal_list cfg_y;
+
+	/* Invalidate first */
+	cass_invalidate_portal_list(dev, plist_idx);
+
+	cass_config_portal_index_table(dev, plist_idx, phys_ptn);
+
+	/* Activate the portal list */
+	cass_write(dev, C_RMU_CFG_PORTAL_LIST_X(plist_idx), cfg, sizeof(*cfg));
+
+	cfg_y = *cfg;
+	cfg_y.index_ext = ~cfg->index_ext;
+	cfg_y.multicast_id = ~cfg->multicast_id;
+	cfg_y.is_multicast = ~cfg->is_multicast;
+	cfg_y.vni_list_idx = ~cfg->vni_list_idx;
+	cass_write(dev, C_RMU_CFG_PORTAL_LIST_Y(plist_idx),
+		   &cfg_y, sizeof(cfg_y));
+}
+
+/**
+ * cass_invalidate_set_list() - Invalidate a Set List entry.
+ *
+ * @dev: Cassini device
+ * @set_list_idx: Set List and Set Ctrl indexes
+ */
+static inline void cass_invalidate_set_list(struct cass_dev *dev,
+					    unsigned int set_list_idx)
+{
+	static const union c_rmu_cfg_ptlte_set_list_invalidate
+		rmu_cfg_ptlte_set_list_invalidate = { .invalidate = 1 };
+
+	cass_write(dev, C_RMU_CFG_PTLTE_SET_LIST_INVALIDATE(set_list_idx),
+		   &rmu_cfg_ptlte_set_list_invalidate,
+		   sizeof(rmu_cfg_ptlte_set_list_invalidate));
+}
+
+/**
+ * cass_config_set_ctrl() - Configure a Set Ctrl entry
+ *
+ * @dev: Cassini device
+ * @set_list_idx: Set Ctrl indexes
+ */
+static inline void
+cass_config_set_ctrl(struct cass_dev *dev,
+		     unsigned int set_list_idx,
+		     const struct c_rmu_cfg_ptlte_set_ctrl_table_entry *entry)
+{
+	unsigned int set_ctrl_idx = set_list_idx /
+		C_RMU_CFG_PTLTE_SET_CTRL_TABLE_ARRAY_SIZE;
+	unsigned int set_ctrl_entry = set_list_idx %
+		C_RMU_CFG_PTLTE_SET_CTRL_TABLE_ARRAY_SIZE;
+	union c_rmu_cfg_ptlte_set_ctrl_table set_ctrl;
+
+	cass_read(dev, C_RMU_CFG_PTLTE_SET_CTRL_TABLE(set_ctrl_idx),
+		  &set_ctrl, sizeof(set_ctrl));
+
+	set_ctrl.e[set_ctrl_entry] = *entry;
+
+	cass_write(dev, C_RMU_CFG_PTLTE_SET_CTRL_TABLE(set_ctrl_idx),
+		   &set_ctrl, sizeof(set_ctrl));
+}
+
+/**
+ * cass_config_indir_entry() - Configure an indirection table
+ *
+ * @dev: Cassini device
+ * @indir_idx: Index in the indirection table
+ * @ptlte_idx: Portal table entry to direct to
+ */
+static inline void cass_config_indir_entry(struct cass_dev *dev,
+					   unsigned int indir_idx,
+					   unsigned int ptlte_idx)
+{
+	union c_rmu_cfg_portal_index_indir_table indir_table;
+	unsigned int indir_table_idx = indir_idx /
+		C_RMU_CFG_PORTAL_INDEX_INDIR_TABLE_ARRAY_SIZE;
+	unsigned int indir_table_entry = indir_idx %
+		C_RMU_CFG_PORTAL_INDEX_INDIR_TABLE_ARRAY_SIZE;
+
+	cass_read(dev, C_RMU_CFG_PORTAL_INDEX_INDIR_TABLE(indir_table_idx),
+		  &indir_table, sizeof(indir_table));
+
+	indir_table.e[indir_table_entry].phys_portal_table_idx = ptlte_idx;
+
+	cass_write(dev, C_RMU_CFG_PORTAL_INDEX_INDIR_TABLE(indir_table_idx),
+		   &indir_table, sizeof(indir_table));
+}
+
+/**
+ * cass_config_set_list() - Configure a Set List entry
+ *
+ * Each Ethernet device needs a default entry to catch packets that do
+ * not hash to anything. Program the Set List, Set Ctrl and
+ * indirection entries.
+ *
+ * @dev: Cassini device
+ * @set_list_idx: Set List and Set Ctrl indexes
+ * @ptlte_idx: Portal table entry
+ * @cfg: how to program the set list
+ * @cfg_mask: valid bits for @cfg
+ *
+ * Since this function uses C_RMU_MSC_SHADOW, its access must be
+ * serialized.
+ */
+static inline void
+cass_config_set_list(struct cass_dev *dev, unsigned int set_list_idx,
+		     unsigned int ptlte_idx,
+		     const union c_rmu_cfg_ptlte_set_list *cfg,
+		     const union c_rmu_cfg_ptlte_set_list *cfg_mask)
+{
+	static const struct c_rmu_cfg_ptlte_set_ctrl_table_entry set_ctrl = {};
+
+	/* Invalidate set list first */
+	cass_invalidate_set_list(dev, set_list_idx);
+
+	/* Clear the control table access */
+	cass_config_set_ctrl(dev, set_list_idx, &set_ctrl);
+
+	/* Modify the indirection table with the physical PtlTE. */
+	cass_config_indir_entry(dev, 2048 + set_list_idx, ptlte_idx);
+
+	/* Enable the set list */
+	cass_write(dev, C_RMU_CFG_PTLTE_SET_LIST_X(set_list_idx),
+		   cfg, sizeof(*cfg));
+
+	cass_shadow_write(dev, C_RMU_BASE,
+			  C_RMU_CFG_PTLTE_SET_LIST_Y_OFFSET(set_list_idx),
+			  cfg_mask, sizeof(*cfg_mask));
+}
+
+/**
+ * cass_ct_enable() - Configure and enable a counting event.
+ *
+ * @dev: Cassini device
+ * @ctn: Counter number
+ * @rgid: Resource group ID to assign the CT to
+ * @wb: Writeback buffer
+ * @wb_addr: Address for writeback counter (physical or virtual)
+ * @wb_ac: Address context for @wb_addr
+ * @ct_mmio: Base address of CT doorbell memory
+ * @ct: User counter structure to initialize
+ */
+static inline void
+cass_ct_enable(struct cass_dev *dev, unsigned int ctn, u8 rgid,
+	       u64 wb_addr, u16 wb_ac)
+{
+	static const union c_cq_cfg_ct_enable enable = { .ct_enable = 1, };
+	const union c_cq_cfg_ct_rgid_table cfg = { .rgid = rgid };
+	const union c_cq_cfg_ct_wb_mem_addr mem = {
+		.wb_mem_addr = wb_addr >> 3,
+		.wb_mem_context = wb_ac,
+	};
+
+	cass_write(dev, C_CQ_CFG_CT_RGID_TABLE(ctn), &cfg, sizeof(cfg));
+	cass_write(dev, C_CQ_CFG_CT_ENABLE(ctn), &enable, sizeof(enable));
+
+	/* Enable the writeback area (if it exists) after enabling the
+	 * CT. Cassini is triggering a writeback during reset which
+	 * the driver doesn't want to deal with.
+	 */
+	cass_write(dev, C_CQ_CFG_CT_WB_MEM_ADDR(ctn), &mem, sizeof(mem));
+
+	cass_flush_pci(dev);
+}
+
+/**
+ * cass_ct_disable() - Disable a counting event (CT).
+ *
+ * @dev: Cassini device
+ * @ctn: Counter number
+ */
+static inline void cass_ct_disable(struct cass_dev *dev, unsigned int ctn)
+{
+	static const union c_cq_cfg_ct_enable enable = {};
+	static const union c_cq_cfg_ct_rgid_table cfg = {};
+	static const union c_cq_cfg_ct_wb_mem_addr mem = {};
+
+	cass_write(dev, C_CQ_CFG_CT_WB_MEM_ADDR(ctn), &mem, sizeof(mem));
+	cass_write(dev, C_CQ_CFG_CT_ENABLE(ctn), &enable, sizeof(enable));
+	cass_write(dev, C_CQ_CFG_CT_RGID_TABLE(ctn), &cfg, sizeof(cfg));
+
+	cass_flush_pci(dev);
+}
+
+/**
+ * cass_assign_ptlte_to_rgid() - Assign a portal entry to a resource group.
+ *
+ * @dev: Cassini device
+ * @pte: The portal table entry
+ * @rgid: Resource group ID
+ */
+static inline void cass_assign_ptlte_to_rgid(struct cass_dev *dev,
+					     unsigned int pte, u8 rgid)
+{
+	union c_cq_cfg_ptlte_rgid_table cfg = { .rgid = rgid };
+
+	cass_write(dev, C_CQ_CFG_PTLTE_RGID_TABLE(pte), &cfg, sizeof(cfg));
+}
+
+/**
+ * cass_set_cp_table() - Set a communication profile table entry.
+ *
+ * @dev: Cassini device
+ * @cid: Communication profile ID
+ * @cfg: Desired configuration
+ */
+static inline void cass_set_cp_table(struct cass_dev *dev, u8 cid,
+				     const union c_cq_cfg_cp_table *cfg)
+{
+	cass_write(dev, C_CQ_CFG_CP_TABLE(cid), cfg, sizeof(*cfg));
+}
+
+/**
+ * cass_set_cp_fl_table() - Set a communication profile flow table entry.
+ *
+ * @dev: Cassini device
+ * @cid: Communication profile ID
+ * @cfg: Desired configuration
+ */
+static inline void cass_set_cp_fl_table(struct cass_dev *dev, u8 cid,
+					const union c_cq_cfg_cp_fl_table *cfg)
+{
+	cass_write(dev, C_CQ_CFG_CP_FL_TABLE(cid), cfg, sizeof(*cfg));
+}
+
+/**
+ * cass_set_pfq_tc_map() - Map prefetch queue to traffic class.
+ *
+ * @dev: Cassini device
+ * @pfq_id: Prefetch queue ID
+ * @cfg: Desired configuration
+ */
+static inline void cass_set_pfq_tc_map(struct cass_dev *dev, u8 pfq_id,
+				       const union c_cq_cfg_pfq_tc_map *cfg)
+{
+	cass_write(dev, C_CQ_CFG_PFQ_TC_MAP(pfq_id), cfg, sizeof(*cfg));
+}
+
+/**
+ * cass_set_acid() - Set an ACID for an RGID
+ *
+ * There are 8 ACIDs per RGID.
+ *
+ * @dev: Cassini device
+ * @rgid: Resource group ID
+ * @lac:  Index in the RGID. 0 to 7.
+ * @acid: The ACID to store in the RGID
+ */
+static inline void cass_set_acid(struct cass_dev *dev, u8 rgid,
+				 unsigned int lac, u16 acid)
+{
+	const union c_cq_cfg_ac_array cfg = { .ac = acid };
+
+	cass_write(dev, C_CQ_CFG_AC_ARRAY(rgid * C_NUM_LACS + lac),
+		   &cfg, sizeof(cfg));
+
+	cass_flush_pci(dev);
+}
+
+/**
+ * cass_set_cid() - Set a CID for an RGID
+ *
+ * There are 16 CIDs in a RGID.
+ *
+ * @dev: Cassini device
+ * @rgid: Resource group ID
+ * @lcid_idx: Index in the RGID. 0 to 15.
+ * @cid: The CID to store in the RGID
+ */
+static inline void cass_set_cid(struct cass_dev *dev, u8 rgid,
+				unsigned int lcid_idx, u8 cid)
+{
+	union c_cq_cfg_cid_array cfg = { .cid = cid };
+
+	cass_write(dev, C_CQ_CFG_CID_ARRAY(rgid * 16 + lcid_idx),
+		   &cfg, sizeof(cfg));
+}
+
+/**
+ * cass_set_vf_pf_ints() - Enable or disable a VF interrupt on the host
+ *
+ * Part of the PF/VF communication. This allows the given VF to
+ * generate interrupt 31 on the host to signify a message is
+ * ready. This is called by the owner of the PF.
+ *
+ * @dev: Cassini device
+ * @vf_num: which VF interrupt to set
+ * @enable: whether to enable or disable the VF interrupt
+ */
+static inline void cass_set_vf_pf_int(struct cass_dev *dev,
+				      unsigned int vf_num,
+				      bool enable)
+{
+	union c_pi_ipd_cfg_vf_pf_irq_mask cfg_vf_pf_irq_mask;
+
+	cass_read(dev , C_PI_IPD_CFG_VF_PF_IRQ_MASK, &cfg_vf_pf_irq_mask,
+		  sizeof(cfg_vf_pf_irq_mask));
+	if (enable)
+		cfg_vf_pf_irq_mask.mask &= ~(1 << vf_num);
+	else
+		cfg_vf_pf_irq_mask.mask |= (1 << vf_num);
+	cass_write(dev, C_PI_IPD_CFG_VF_PF_IRQ_MASK, &cfg_vf_pf_irq_mask,
+		   sizeof(cfg_vf_pf_irq_mask));
+}
+
+/**
+ * cass_clear_vf_pf_int() - Clear a pending VF interrupt
+ *
+ * Called by the owner of the PF after processing an interrupt from a
+ * VF.
+ *
+ * @dev: Cassini device
+ * @vf_num: which VF interrupt to clear
+ */
+static inline void cass_clear_vf_pf_int(struct cass_dev *dev,
+					unsigned int vf_num)
+{
+	union c_pi_ipd_cfg_vf_pf_irq_clr cfg_vf_pf_irq_clr = {
+		.clr = (1 << vf_num),
+	};
+
+	cass_write(dev, C_PI_IPD_CFG_VF_PF_IRQ_CLR,
+		   &cfg_vf_pf_irq_clr, sizeof(cfg_vf_pf_irq_clr));
+}
+
+/**
+ * cass_config_sriovt() - Configure access to a resource from a VF
+ *
+ * @dev: Cassini device
+ * @enable: whether to enable or disable the access from the VF
+ * @vf_num: which VF owns that resource (if enabled)
+ * @res_index: resource index
+ *
+ * The resource index is either:
+ *   -    0 + a transmit CQ id
+ *   - 1024 + a target CQ id
+ *   - 2048 + a CT id
+ *   - 4096 + an EQ id
+ */
+static inline void cass_config_sriovt(struct cass_dev *dev,
+				      bool enable,
+				      unsigned int vf_num,
+				      unsigned res_index)
+{
+	const union c_pi_cfg_sriovt cfg_sriovt = {
+		.vf_en = enable,
+		.vf_num = vf_num,
+	};
+
+	cass_write(dev, C_PI_CFG_SRIOVT(res_index),
+		   &cfg_sriovt, sizeof(cfg_sriovt));
+}
+
+/* Initializes simple structures that are 8 bytes wide. */
+#define CASS_INIT_SIMPLE_TABLE(up, lo) {			\
+	unsigned int i;						\
+	const union lo lo = {};					\
+	_Static_assert(sizeof(lo) == 8, "Invalid size");	\
+	for (i = 0; i < up ## _ENTRIES; i++)			\
+		cass_write(dev, up(i), &lo, sizeof(lo));	\
+	}
+
+/*
+ * Initializes simple structures that are larger than 8 bytes. Shadow
+ * memory must be used.
+ */
+#define CASS_INIT_SHADOW_TABLE(up, lo, block_base) {		\
+	unsigned int i;						\
+	const union lo lo = {};					\
+	_Static_assert(sizeof(lo) > 8, "Invalid size");			\
+	cass_shadow_write_prepare(dev, block_base, &lo, sizeof(lo));	\
+	for (i = 0; i < up ## _ENTRIES; i++)			\
+		cass_shadow_write_do(dev, block_base, up ## _OFFSET(i));\
+	}
+
+/**
+ * cass_init() - Mandatory initialization of a Cassini chip
+ *
+ * Used after a power on or a reset.
+ */
+static inline void cass_init(struct cass_dev *dev)
+{
+	unsigned int i;
+	static const union {
+		union c_rmu_cfg_portal_list rmu_cfg_portal_list;
+		union c_rmu_cfg_ptlte_set_list rmu_cfg_ptlte_set_list;
+		union c_cq_cfg_tg_thresh cq_cfg_tg_thresh;
+		union c_lpe_cfg_get_ctrl lpe_cfg_get_ctrl;
+	} u = {};
+	static const union c_rmu_cfg_ptlte_set_list rmu_cfg_ptlte_set_list_mask = {
+		.qw = { 0xfffffffffffffffULL, 0xfffffffffffffffULL,
+			0xfffffffffffffffULL, 0xfffffffffffffffULL }
+	};
+	static const union c_ee_cfg_latency_monitor cfg_latency_monitor = {
+		.thresh_a      = 128,
+		.thresh_b      = 196,
+		.lt_limit      = 100,
+		.lt_limit_a    =  40,
+		.lt_limit_b    =  20,
+		.granularity   =  50,
+		.granularity_a =  20,
+		.granularity_b =  10,
+		.hysteresis_a  = 100,
+		.hysteresis_b  = 150,
+	};
+	union c_ee_cfg_timestamp_freq cfg_timestamp_freq = {.clk_divider = 1000};
+	union c_cq_cfg_ct_wb_mem_addr cfg_ct_wb_mem_addr;
+	union c_mb_sts_rev rev;
+
+	/*
+	 * All CSRs that are accessible through the shadow space must
+	 * be initialized.
+	 *
+	 */
+
+	CASS_INIT_SIMPLE_TABLE(C_RMU_CFG_PORTAL_INDEX_TABLE,
+			       c_rmu_cfg_portal_index_table);
+	CASS_INIT_SIMPLE_TABLE(C_RMU_CFG_PTLTE_SET_CTRL_TABLE,
+			       c_rmu_cfg_ptlte_set_ctrl_table);
+	CASS_INIT_SIMPLE_TABLE(C_RMU_CFG_PORTAL_INDEX_INDIR_TABLE,
+			       c_rmu_cfg_portal_index_indir_table);
+
+	for (i = 0; i < C_RMU_CFG_PTLTE_SET_LIST_ENTRIES; i++) {
+		cass_config_set_list(dev, i, 0, &u.rmu_cfg_ptlte_set_list,
+					   &rmu_cfg_ptlte_set_list_mask);
+		cass_invalidate_set_list(dev, i);
+	}
+
+	for (i = 0; i < C_RMU_CFG_VNI_LIST_ENTRIES; i++) {
+		cass_config_matching_vni_list(dev, i, 0, 0);
+		cass_invalidate_vni_list(dev, i);
+	}
+
+	for (i = 0; i < C_RMU_CFG_PORTAL_LIST_ENTRIES; i++) {
+		cass_config_portal_list(dev, i, 0, &u.rmu_cfg_portal_list);
+		cass_invalidate_portal_list(dev, i);
+	}
+
+	CASS_INIT_SHADOW_TABLE(C_ATU_CFG_AC_TABLE,
+			       c_atu_cfg_ac_table, C_ATU_BASE);
+	CASS_INIT_SIMPLE_TABLE(C_ATU_CFG_CQ_TABLE, c_atu_cfg_cq_table);
+
+	CASS_INIT_SIMPLE_TABLE(C_CQ_CFG_CP_TABLE, c_cq_cfg_cp_table);
+	CASS_INIT_SIMPLE_TABLE(C_CQ_CFG_CT_WB_MEM_ADDR, c_cq_cfg_ct_wb_mem_addr);
+
+	CASS_INIT_SHADOW_TABLE(C_CQ_TXQ_BASE_TABLE, c_cq_txq_base_table,
+			       C_CQ_BASE);
+	CASS_INIT_SHADOW_TABLE(C_CQ_TGQ_TABLE, c_cq_tgq_table, C_CQ_BASE);
+	CASS_INIT_SIMPLE_TABLE(C_CQ_CFG_CID_ARRAY, c_cq_cfg_cid_array);
+	CASS_INIT_SIMPLE_TABLE(C_CQ_CFG_CT_RGID_TABLE, c_cq_cfg_ct_rgid_table);
+	CASS_INIT_SIMPLE_TABLE(C_CQ_CFG_EQ_RGID_TABLE, c_cq_cfg_eq_rgid_table);
+	CASS_INIT_SIMPLE_TABLE(C_CQ_CFG_AC_ARRAY, c_cq_cfg_ac_array);
+	CASS_INIT_SIMPLE_TABLE(C_CQ_CFG_PTLTE_RGID_TABLE, c_cq_cfg_ptlte_rgid_table);
+
+	CASS_INIT_SHADOW_TABLE(C_LPE_CFG_PTL_TABLE, c_lpe_cfg_ptl_table,
+			       C_LPE_BASE);
+	CASS_INIT_SHADOW_TABLE(C_LPE_DBG_MRR, c_lpe_dbg_mrr, C_LPE_BASE);
+	CASS_INIT_SHADOW_TABLE(C_LPE_DBG_RGET_RAM, c_lpe_dbg_rget_ram, C_LPE_BASE);
+	CASS_INIT_SHADOW_TABLE(C_LPE_STS_LIST_ENTRIES, c_lpe_sts_list_entries,
+			       C_LPE_BASE);
+	cass_write(dev, C_LPE_CFG_GET_CTRL, &u.lpe_cfg_get_ctrl,
+		   sizeof(u.lpe_cfg_get_ctrl));
+
+	CASS_INIT_SHADOW_TABLE(C_EE_CFG_EQ_DESCRIPTOR,
+			       c_ee_cfg_eq_descriptor, C_EE_BASE);
+	CASS_INIT_SIMPLE_TABLE(C_EE_CFG_LONG_EVNT_OVR_TABLE,
+			       c_ee_cfg_long_evnt_ovr_table);
+	CASS_INIT_SIMPLE_TABLE(C_EE_CFG_PERIODIC_TSTAMP_TABLE,
+			       c_ee_cfg_periodic_tstamp_table);
+	CASS_INIT_SIMPLE_TABLE(C_EE_DBG_ECB_SIDEBAND, c_ee_dbg_ecb_sideband);
+	CASS_INIT_SHADOW_TABLE(C_EE_DBG_ECB, c_ee_dbg_ecb, C_EE_BASE);
+	CASS_INIT_SIMPLE_TABLE(C_EE_DBG_TRNSLTN_RSP, c_ee_dbg_trnsltn_rsp);
+	CASS_INIT_SIMPLE_TABLE(C_EE_CFG_EQ_SW_STATE, c_ee_cfg_eq_sw_state);
+	CASS_INIT_SHADOW_TABLE(C_EE_CFG_STS_EQ_HW_STATE,
+			       c_ee_cfg_sts_eq_hw_state, C_EE_BASE);
+	cass_write(dev, C_EE_CFG_LATENCY_MONITOR, &cfg_latency_monitor,
+		   sizeof(cfg_latency_monitor));
+	cass_write(dev, C_EE_CFG_TIMESTAMP_FREQ, &cfg_timestamp_freq,
+		   sizeof(cfg_timestamp_freq));
+
+	CASS_INIT_SIMPLE_TABLE(C_PCT_CFG_SCT_RAM0, c_pct_cfg_sct_ram0);
+	CASS_INIT_SIMPLE_TABLE(C_PCT_CFG_SCT_RAM1, c_pct_cfg_sct_ram1);
+	CASS_INIT_SIMPLE_TABLE(C_PCT_CFG_SCT_RAM2, c_pct_cfg_sct_ram2);
+	CASS_INIT_SIMPLE_TABLE(C_PCT_CFG_SCT_RAM3, c_pct_cfg_sct_ram3);
+	CASS_INIT_SIMPLE_TABLE(C_PCT_CFG_SCT_RAM4, c_pct_cfg_sct_ram4);
+	CASS_INIT_SIMPLE_TABLE(C_PCT_CFG_SMT_RAM0, c_pct_cfg_smt_ram0);
+	CASS_INIT_SIMPLE_TABLE(C_PCT_CFG_SMT_RAM1, c_pct_cfg_smt_ram1);
+	CASS_INIT_SHADOW_TABLE(C_PCT_CFG_SPT_RAM0, c_pct_cfg_spt_ram0, C_PCT_BASE);
+	CASS_INIT_SIMPLE_TABLE(C_PCT_CFG_SPT_RAM1, c_pct_cfg_spt_ram1);
+	CASS_INIT_SIMPLE_TABLE(C_PCT_CFG_SPT_RAM2, c_pct_cfg_spt_ram2);
+	CASS_INIT_SIMPLE_TABLE(C_PCT_CFG_TCT_RAM, c_pct_cfg_tct_ram);
+
+	cass_read(dev, C_MB_STS_REV, &rev, sizeof(rev));
+
+	if (rev.vendor_id == 0x17db && rev.device_id == 0x501) {
+		/* See Cassini ERRATA-3248. CTs can be disabled due to a bug
+		 * unless C_CQ_CFG_CT_WB_MEM_ADDR has been read once.
+		 * Must read back one CT MEM ADDR. */
+		cass_read(dev, C_CQ_CFG_CT_WB_MEM_ADDR(0), &cfg_ct_wb_mem_addr,
+			  sizeof(cfg_ct_wb_mem_addr));
+
+		CASS_INIT_SIMPLE_TABLE(C1_PCT_CFG_TRS_RAM0,
+				       c_pct_cfg_trs_ram0);
+		CASS_INIT_SHADOW_TABLE(C1_PCT_CFG_TRS_RAM1,
+				       c_pct_cfg_trs_ram1, C_PCT_BASE);
+	} else {
+		CASS_INIT_SIMPLE_TABLE(C2_PCT_CFG_TRS_RAM0,
+				       c_pct_cfg_trs_ram0);
+		CASS_INIT_SHADOW_TABLE(C2_PCT_CFG_TRS_RAM1,
+				       c_pct_cfg_trs_ram1, C_PCT_BASE);
+	}
+
+	CASS_INIT_SHADOW_TABLE(C_MST_DBG_MST_TABLE, c_mst_dbg_mst_table, C_MST_BASE);
+}
+
+#undef CASS_INIT_SIMPLE_TABLE
+#undef CASS_INIT_SHADOW_TABLE
+
+#endif	/* __CXI_CASSINI_H */
diff --git a/include/uapi/ethernet/cassini_user_defs.h b/include/uapi/ethernet/cassini_user_defs.h
new file mode 100644
index 000000000000..8d890bdad65f
--- /dev/null
+++ b/include/uapi/ethernet/cassini_user_defs.h
@@ -0,0 +1,14936 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/*
+ * Cassini hardware definitions
+ * Copyright 2018-2021 Hewlett Packard Enterprise Development LP
+ *
+ * This file is generated. Do not modify.
+ */
+
+#ifndef __CASSINI_USER_DEFS_H
+#define __CASSINI_USER_DEFS_H
+
+#include <asm/byteorder.h>
+
+#ifndef __LITTLE_ENDIAN
+# __LITTLE_ENDIAN
+#error "Non-little endian builds not supported"
+#endif
+
+
+#ifndef __KERNEL__
+#include <endian.h>
+
+/* Provide fallback implementations if endian.h functions aren't available */
+#ifndef be64toh
+#define be64toh(x) __builtin_bswap64(x)
+#endif
+#ifndef htobe64
+#define htobe64(x) __builtin_bswap64(x)
+#endif
+#ifndef be32toh
+#define be32toh(x) __builtin_bswap32(x)
+#endif
+#ifndef htobe32
+#define htobe32(x) __builtin_bswap32(x)
+#endif
+#ifndef be16toh
+#define be16toh(x) __builtin_bswap16(x)
+#endif
+#ifndef htobe16
+#define htobe16(x) __builtin_bswap16(x)
+#endif
+
+#define be64_to_cpu be64toh
+#define be32_to_cpu be32toh
+#define be16_to_cpu be16toh
+#define cpu_to_be64 htobe64
+#define cpu_to_be32 htobe32
+#define cpu_to_be16 htobe16
+#endif
+
+#define C_CQ_BASE 0x00000000
+#define C_PCT_BASE 0x00800000
+#define C_HNI_BASE 0x01000000
+#define C_HNI_PML_BASE 0x01800000
+#define C_RMU_BASE 0x02000000
+#define C_IXE_BASE 0x02800000
+#define C_ATU_BASE 0x08000000
+#define C_EE_BASE 0x08800000
+#define C_PARBS_BASE 0x09000000
+#define C_LPE_BASE 0x09800000
+#define C_MST_BASE 0x0a000000
+#define C_OXE_BASE 0x0a800000
+#define C_MB_BASE 0x10000000
+#define C_PI_BASE 0x10800000
+#define C_PI_IPD_BASE 0x11000000
+#define C_MEMORG_CSR 0x40000000u
+#define C_MEMORG_CSR_SIZE 0x28000000u
+#define C_MEMORG_CQ_LAUNCH 0x00000000u
+#define C_MEMORG_CQ_LAUNCH_SIZE 0x08000000u
+#define C_MEMORG_CQ_TOU 0x08000000u
+#define C_MEMORG_EE 0x10000000u
+#define C_CQ_LAUNCH_TXQ_BASE (C_MEMORG_CQ_LAUNCH + 0x00000000)
+#define C_CQ_LAUNCH_TGT_BASE (C_MEMORG_CQ_LAUNCH + 0x04000000)
+#define C_CQ_LAUNCH_PAGE_SIZE 0x10000
+#define C_TOU_LAUNCH_PAGE_SIZE 0x10000
+#define C_EE_SW_STATE_PAGE_SIZE 0x10000
+#define C_NUM_CTS 2048
+#define C_CT_NONE 0
+#define C_AC_NONE 0
+#define C_CID_NONE 0
+#define C_NUM_EQS 2048
+#define C_EQ_NONE 0
+#define C_NUM_ACS 1024
+#define C_NUM_PTLTES 2048
+#define C_NUM_TRANSMIT_CQS 1024
+#define C_NUM_TARGET_CQS 512
+#define C_NID_ANY 1048575
+#define NICSIM_CONFIG_DUMP 0x27fff008
+#define NICSIM_CONFIG_LOG 0x27fff010
+#define NICSIM_CONFIG_STATE 0x27fff018
+#define NICSIM_NIC_ID 0x27fff060
+#define C_PLATFORM_ASIC 0
+#define C_PLATFORM_NETSIM 1
+#define C_PLATFORM_Z1 2
+#define C_PLATFORM_FPGA 3
+#define C_MST_TABLE_SIMPLE_OFFSET 16
+#define C_PE_COUNT 4
+#define C_COMM_PROF_PER_CQ 16
+#define C_DFA_PID_BITS_MIN 6
+#define C_DFA_PID_BITS_MAX 9
+#define C_PID_ANY ((1 << C_DFA_PID_BITS_MAX) - 1)
+#define C_RANK_ANY ((1 << (32 - C_DFA_PID_BITS_MAX)) - 1)
+#define C_DFA_NIC_BITS 20
+#define C_DFA_MULTICAST_ID_BITS 13
+#define C_DFA_INDEX_EXT_BITS 5
+#define C_CT_SUCCESS_BITS 48
+#define C_CT_FAILURE_BITS 7
+#define C_DFA_ENDPOINT_DEFINED_BITS 12
+#define C_DFA_ENDPOINT_BITS (C_DFA_ENDPOINT_DEFINED_BITS + C_DFA_INDEX_EXT_BITS)
+#define C_NUM_RGIDS 256
+#define C_RESERVED_RGID 0
+#define C_OXE_CQ_MCU_START 0
+#define C_OXE_CQ_MCU_COUNT 48
+#define C_OXE_LPE_MCU_START (C_OXE_CQ_MCU_START + C_OXE_CQ_MCU_COUNT)
+#define C_OXE_LPE_MCU_COUNT 16
+#define C_OXE_IXE_MCU_START (C_OXE_LPE_MCU_START + C_OXE_LPE_MCU_COUNT)
+#define C_OXE_IXE_MCU_COUNT 24
+#define C_OXE_TOU_MCU_START (C_OXE_IXE_MCU_START + C_OXE_IXE_MCU_COUNT)
+#define C_OXE_TOU_MCU_COUNT 8
+#define C_OXE_MCU_COUNT (C_OXE_CQ_MCU_COUNT + C_OXE_IXE_MCU_COUNT + C_OXE_LPE_MCU_COUNT + C_OXE_TOU_MCU_COUNT)
+#define C_NUM_LACS 8
+#define C_NUM_TLES 2048
+#define C_NUM_VFS 64
+#define C_MAX_IDC_PAYLOAD_RES 224
+#define C_MAX_IDC_PAYLOAD_UNR 192
+#define C_ATU_PRB_ENTRIES 512
+
+enum c_rsp_status {
+	C_RSP_PEND = 0,
+	C_RSP_NACK_RCVD = 1,
+	C_RSP_GET_ACK_RCVD = 2,
+	C_RSP_OP_COMP = 3,
+};
+
+enum c_sct_status {
+	C_SCT_NOT_USED = 0,
+	C_SCT_NORMAL = 1,
+	C_SCT_STALL = 2,
+	C_SCT_CLEAR_PEND = 3,
+	C_SCT_CLOSE_PEND = 4,
+	C_SCT_CLOSE_TIMEOUT = 5,
+	C_SCT_CLOSE_COMP = 6,
+	C_SCT_RETRY = 7,
+};
+
+enum c_port_v4_pkt_type {
+	C_V4_PKT_UNRESTRICTED = 0,
+	C_V4_PKT_SMALLMSG = 1,
+	C_V4_PKT_CONTINUATION = 2,
+	C_V4_PKT_CONN_MGMT = 3,
+	C_V4_PKT_RESTRICTED = 4,
+	C_RESERVED5 = 5,
+	C_RESERVED6 = 6,
+	C_V4_PKT_HRP_ACK = 7,
+};
+
+enum c_port_vs_pkt_type {
+	C_VS_PKT_PUT64 = 0,
+	C_VS_PKT_GET64 = 1,
+	C_VS_PKT_PUT32 = 2,
+	C_VS_PKT_GET32 = 3,
+	C_VS_PKT_AMO64 = 4,
+	C_VS_PKT_FAMO64 = 5,
+	C_VS_PKT_AMO32 = 6,
+	C_VS_PKT_FAMO32 = 7,
+};
+
+enum c_port_rsp_pkt_type {
+	C_RSP_PKT_ANY = 0,
+	C_RSP_PKT_32B = 1,
+};
+
+enum c_format {
+	C_PKT_FORMAT_OPT = 0,
+	C_PKT_FORMAT_STD = 1,
+};
+
+enum c_checksum_ctrl {
+	C_CHECKSUM_CTRL_NONE = 0,
+	C_CHECKSUM_CTRL_ROCE = 1,
+	C_CHECKSUM_CTRL_UDP = 2,
+	C_CHECKSUM_CTRL_TCP = 3,
+};
+
+enum c_cmd_size {
+	C_CMD_SIZE_32B = 0,
+	C_CMD_SIZE_64B = 1,
+	C_CMD_SIZE_128B = 2,
+	C_CMD_SIZE_256B = 3,
+};
+
+enum c_ptl_list {
+	C_PTL_LIST_PRIORITY = 0,
+	C_PTL_LIST_OVERFLOW = 1,
+	C_PTL_LIST_REQUEST = 2,
+	C_PTL_LIST_UNEXPECTED = 3,
+};
+
+enum c_atomic_op {
+	C_AMO_OP_MIN = 0,
+	C_AMO_OP_MAX = 1,
+	C_AMO_OP_SUM = 2,
+	C_AMO_OP_LOR = 4,
+	C_AMO_OP_LAND = 5,
+	C_AMO_OP_BOR = 6,
+	C_AMO_OP_BAND = 7,
+	C_AMO_OP_LXOR = 8,
+	C_AMO_OP_BXOR = 9,
+	C_AMO_OP_SWAP = 10,
+	C_AMO_OP_CSWAP = 11,
+	C_AMO_OP_AXOR = 12,
+};
+
+enum c_cswap_op {
+	C_AMO_OP_CSWAP_EQ = 0,
+	C_AMO_OP_CSWAP_NE = 1,
+	C_AMO_OP_CSWAP_LE = 2,
+	C_AMO_OP_CSWAP_LT = 3,
+	C_AMO_OP_CSWAP_GE = 4,
+	C_AMO_OP_CSWAP_GT = 5,
+};
+
+enum c_atomic_type {
+	C_AMO_TYPE_INT8_T = 0,
+	C_AMO_TYPE_UINT8_T = 1,
+	C_AMO_TYPE_INT16_T = 2,
+	C_AMO_TYPE_UINT16_T = 3,
+	C_AMO_TYPE_INT32_T = 4,
+	C_AMO_TYPE_UINT32_T = 5,
+	C_AMO_TYPE_INT64_T = 6,
+	C_AMO_TYPE_UINT64_T = 7,
+	C_AMO_TYPE_FLOAT_T = 8,
+	C_AMO_TYPE_FLOAT_COMPLEX_T = 9,
+	C_AMO_TYPE_DOUBLE_T = 10,
+	C_AMO_TYPE_DOUBLE_COMPLEX_T = 11,
+	C_AMO_TYPE_UINT128_T = 12,
+};
+
+enum c_ptlte_state {
+	C_PTLTE_RESET = 0,
+	C_PTLTE_DISABLED = 1,
+	C_PTLTE_ENABLED = 2,
+	C_PTLTE_SOFTWARE_MANAGED = 3,
+	C_PTLTE_ETHERNET = 4,
+};
+
+enum c_cmd_type {
+	C_CMD_TYPE_IDC = 0,
+	C_CMD_TYPE_DMA = 1,
+	C_CMD_TYPE_CT = 2,
+	C_CMD_TYPE_CQ = 3,
+};
+
+enum c_dma_op {
+	C_CMD_NOOP = 0,
+	C_CMD_PUT = 1,
+	C_CMD_GET = 2,
+	C_CMD_RENDEZVOUS_PUT = 3,
+	C_CMD_ATOMIC = 4,
+	C_CMD_FETCHING_ATOMIC = 5,
+	C_CMD_ETHERNET_TX = 6,
+	C_CMD_SMALL_MESSAGE = 7,
+	C_CMD_NOMATCH_PUT = 8,
+	C_CMD_NOMATCH_GET = 9,
+	C_CMD_CSTATE = 10,
+	C_CMD_CLOSE = 11,
+	C_CMD_CLEAR = 12,
+	C_CMD_REDUCTION = 13,
+};
+
+enum c_ct_op {
+	C_CMD_CT_NOOP = 0,
+	C_CMD_CT_SET = 1,
+	C_CMD_CT_GET = 2,
+	C_CMD_CT_INC = 3,
+	C_CMD_CT_CANCEL = 4,
+	C_CMD_CT_TRIG_DMA = 5,
+	C_CMD_CT_TRIG_SET = 6,
+	C_CMD_CT_TRIG_INC = 7,
+	C_CMD_CT_TRIG_EVENT = 8,
+};
+
+enum c_cq_op {
+	C_CMD_CQ_NOOP = 0,
+	C_CMD_CQ_FENCE = 1,
+	C_CMD_CQ_LCID = 2,
+};
+
+enum c_tgt_op {
+	C_CMD_TGT_APPEND = 8,
+	C_CMD_TGT_SEARCH = 9,
+	C_CMD_TGT_SEARCH_AND_DELETE = 10,
+	C_CMD_TGT_UNLINK = 11,
+	C_CMD_TGT_SETSTATE = 12,
+};
+
+enum c_event_size {
+	C_EVENT_SIZE_NO_EVENT = 0,
+	C_EVENT_SIZE_16_BYTE = 1,
+	C_EVENT_SIZE_32_BYTE = 2,
+	C_EVENT_SIZE_64_BYTE = 3,
+};
+
+enum c_event_type {
+	C_EVENT_PUT = 0,
+	C_EVENT_GET = 1,
+	C_EVENT_ATOMIC = 2,
+	C_EVENT_FETCH_ATOMIC = 3,
+	C_EVENT_PUT_OVERFLOW = 4,
+	C_EVENT_GET_OVERFLOW = 5,
+	C_EVENT_ATOMIC_OVERFLOW = 6,
+	C_EVENT_FETCH_ATOMIC_OVERFLOW = 7,
+	C_EVENT_SEND = 8,
+	C_EVENT_ACK = 9,
+	C_EVENT_REPLY = 10,
+	C_EVENT_LINK = 11,
+	C_EVENT_SEARCH = 12,
+	C_EVENT_STATE_CHANGE = 13,
+	C_EVENT_UNLINK = 14,
+	C_EVENT_RENDEZVOUS = 15,
+	C_EVENT_ETHERNET = 16,
+	C_EVENT_COMMAND_FAILURE = 17,
+	C_EVENT_TRIGGERED_OP = 18,
+	C_EVENT_ETHERNET_FGFC = 19,
+	C_EVENT_PCT = 20,
+	C_EVENT_MATCH = 21,
+	C_EVENT_ERROR = 28,
+	C_EVENT_TIMESTAMP = 29,
+	C_EVENT_EQ_SWITCH = 30,
+	C_EVENT_NULL_EVENT = 31,
+};
+
+enum c_return_code {
+	C_RC_NO_EVENT = 0,
+	C_RC_OK = 1,
+	C_RC_UNDELIVERABLE = 2,
+	C_RC_PT_DISABLED = 3,
+	C_RC_DROPPED = 4,
+	C_RC_PERM_VIOLATION = 5,
+	C_RC_OP_VIOLATION = 6,
+	C_RC_NO_MATCH = 8,
+	C_RC_UNCOR = 9,
+	C_RC_UNCOR_TRNSNT = 10,
+	C_RC_NO_SPACE = 16,
+	C_RC_ENTRY_NOT_FOUND = 18,
+	C_RC_NO_TARGET_CONN = 19,
+	C_RC_NO_TARGET_MST = 20,
+	C_RC_NO_TARGET_TRS = 21,
+	C_RC_SEQUENCE_ERROR = 22,
+	C_RC_NO_MATCHING_CONN = 23,
+	C_RC_INVALID_DFA_FORMAT = 24,
+	C_RC_VNI_NOT_FOUND = 25,
+	C_RC_PTLTE_NOT_FOUND = 26,
+	C_RC_PTLTE_SW_MANAGED = 27,
+	C_RC_SRC_ERROR = 28,
+	C_RC_MST_CANCELLED = 29,
+	C_RC_HRP_CONFIG_ERROR = 30,
+	C_RC_HRP_RSP_ERROR = 31,
+	C_RC_HRP_RSP_DISCARD = 32,
+	C_RC_INVALID_AC = 33,
+	C_RC_PAGE_PERM_ERROR = 34,
+	C_RC_ATS_ERROR = 35,
+	C_RC_NO_TRANSLATION = 36,
+	C_RC_PAGE_REQ_ERROR = 37,
+	C_RC_PCIE_ERROR_POISONED = 38,
+	C_RC_PCIE_UNSUCCESS_CMPL = 39,
+	C_RC_AMO_INVAL_OP_ERROR = 40,
+	C_RC_AMO_ALIGN_ERROR = 41,
+	C_RC_AMO_FP_INVALID = 42,
+	C_RC_AMO_FP_UNDERFLOW = 43,
+	C_RC_AMO_FP_OVERFLOW = 44,
+	C_RC_AMO_FP_INEXACT = 45,
+	C_RC_ILLEGAL_OP = 46,
+	C_RC_INVALID_ENDPOINT = 47,
+	C_RC_RESTRICTED_UNICAST = 48,
+	C_RC_CMD_ALIGN_ERROR = 49,
+	C_RC_CMD_INVALID_ARG = 50,
+	C_RC_INVALID_EVENT = 51,
+	C_RC_ADDR_OUT_OF_RANGE = 52,
+	C_RC_CONN_CLOSED = 53,
+	C_RC_CANCELED = 54,
+	C_RC_NO_MATCHING_TRS = 55,
+	C_RC_NO_MATCHING_MST = 56,
+	C_RC_DELAYED = 57,
+	C_RC_AMO_LENGTH_ERROR = 58,
+	C_RC_PKTBUF_ERROR = 59,
+	C_RC_RESOURCE_BUSY = 60,
+	C_RC_FLUSH_TRANSLATION = 61,
+	C_RC_TRS_PEND_RSP = 62,
+};
+
+enum c_rss_hash_type {
+	C_RSS_HASH_NONE = 0,
+	C_RSS_HASH_IPV4 = 1,
+	C_RSS_HASH_IPV4_TCP = 2,
+	C_RSS_HASH_IPV4_UDP = 3,
+	C_RSS_HASH_IPV4_PROTOCOL = 4,
+	C_RSS_HASH_IPV4_PROTOCOL_TCP = 5,
+	C_RSS_HASH_IPV4_PROTOCOL_UDP = 6,
+	C_RSS_HASH_IPV4_PROTOCOL_UDP_ROCE = 7,
+	C_RSS_HASH_IPV4_FLOW_LABEL = 8,
+	C_RSS_HASH_IPV6 = 9,
+	C_RSS_HASH_IPV6_TCP = 10,
+	C_RSS_HASH_IPV6_UDP = 11,
+	C_RSS_HASH_IPV6_PROTOCOL = 12,
+	C_RSS_HASH_IPV6_PROTOCOL_TCP = 13,
+	C_RSS_HASH_IPV6_PROTOCOL_UDP = 14,
+	C_RSS_HASH_IPV6_PROTOCOL_UDP_ROCE = 15,
+	C_RSS_HASH_IPV6_FLOW_LABEL = 16,
+};
+
+enum c_sc_reason {
+	C_SC_FC_EQ_FULL = 0,
+	C_SC_FC_NO_MATCH = 1,
+	C_SC_FC_UNEXPECTED_FAIL = 2,
+	C_SC_FC_REQUEST_FULL = 3,
+	C_SC_SM_UNEXPECTED_FAIL = 4,
+	C_SC_SM_APPEND_FAIL = 5,
+	C_SC_DIS_UNCOR = 6,
+};
+
+enum c_pct_event_type {
+	C_PCT_REQUEST_NACK = 0,
+	C_PCT_REQUEST_TIMEOUT = 1,
+	C_PCT_SCT_TIMEOUT = 2,
+	C_PCT_TCT_TIMEOUT = 3,
+	C_PCT_ACCEL_CLOSE_COMPLETE = 4,
+	C_PCT_RETRY_COMPLETE = 5,
+};
+
+enum c_error_class {
+	C_EC_SFTWR = 0,
+	C_EC_INFO = 1,
+	C_EC_TRS_NS = 2,
+	C_EC_TRS_S = 3,
+	C_EC_TRNSNT_NS = 4,
+	C_EC_TRNSNT_S = 5,
+	C_EC_BADCON_NS = 6,
+	C_EC_BADCON_S = 7,
+	C_EC_DEGRD_NS = 8,
+	C_EC_COR = 9,
+	C_EC_UNCOR_NS = 10,
+	C_EC_UNCOR_S = 11,
+	C_EC_CRIT = 12,
+};
+
+enum c_odp_status {
+	C_ATU_ODP_SUCCESS = 0,
+	C_ATU_ODP_FAILURE = 1,
+};
+
+enum c_ta_mode {
+	C_ATU_ATS_MODE = 0,
+	C_ATU_NTA_MODE = 1,
+	C_ATU_ATS_DYNAMIC_MODE = 2,
+	C_ATU_PASSTHROUGH_MODE = 3,
+};
+
+enum c_ptg_mode {
+	C_ATU_PTG_MODE_SGL = 0,
+	C_ATU_PTG_MODE_DBL_A = 1,
+	C_ATU_PTG_MODE_DBL_B = 2,
+	C_ATU_PTG_MODE_DBL_C = 3,
+	C_ATU_PTG_MODE_TPL_A = 4,
+	C_ATU_PTG_MODE_TPL_B = 5,
+};
+
+enum c_odp_mode {
+	C_ATU_ODP_MODE_ATS_PRS = 0,
+	C_ATU_ODP_MODE_NIC_PRI = 1,
+};
+
+enum c_atucq_cmd {
+	C_ATU_NOP = 0,
+	C_ATU_INVALIDATE_PAGES = 1,
+	C_ATU_COMPLETION_WAIT = 2,
+	C_ATU_RESERVED = 3,
+};
+
+enum c_enet_frame_type {
+	C_RMU_ENET_802_3 = 1,
+	C_RMU_ENET_OPT_IPV4 = 2,
+	C_RMU_ENET_OPT_IPV6 = 3,
+};
+
+enum c_msix_ints {
+	C_PF_TO_VF_MSIX_INT = 0,
+	C_PI_IPD_IRQA_MSIX_INT = 0,
+	C_PI_IRQA_MSIX_INT = 1,
+	C_MB_IRQA_MSIX_INT = 2,
+	C_CQ_IRQA_MSIX_INT = 3,
+	C_PCT_IRQA_MSIX_INT = 4,
+	C_HNI_IRQA_MSIX_INT = 5,
+	C_HNI_PML_IRQA_MSIX_INT = 6,
+	C_RMU_IRQA_MSIX_INT = 7,
+	C_IXE_IRQA_MSIX_INT = 8,
+	C_ATU_IRQA_MSIX_INT = 9,
+	C_EE_IRQA_MSIX_INT = 10,
+	C_PARBS_IRQA_MSIX_INT = 11,
+	C_LPE_IRQA_MSIX_INT = 12,
+	C_MST_IRQA_MSIX_INT = 13,
+	C_OXE_IRQA_MSIX_INT = 14,
+	C_PI_IPD_IRQB_MSIX_INT = 15,
+	C_PI_IRQB_MSIX_INT = 16,
+	C_MB_IRQB_MSIX_INT = 17,
+	C_CQ_IRQB_MSIX_INT = 18,
+	C_PCT_IRQB_MSIX_INT = 19,
+	C_HNI_IRQB_MSIX_INT = 20,
+	C_HNI_PML_IRQB_MSIX_INT = 21,
+	C_RMU_IRQB_MSIX_INT = 22,
+	C_IXE_IRQB_MSIX_INT = 23,
+	C_ATU_IRQB_MSIX_INT = 24,
+	C_EE_IRQB_MSIX_INT = 25,
+	C_PARBS_IRQB_MSIX_INT = 26,
+	C_LPE_IRQB_MSIX_INT = 27,
+	C_MST_IRQB_MSIX_INT = 28,
+	C_OXE_IRQB_MSIX_INT = 29,
+	C_PI_DMAC_MSIX_INT = 30,
+	C_PI_IPD_VF_PF_MSIX_INT = 31,
+	C_FIRST_AVAIL_MSIX_INT = 32,
+};
+
+enum c_pi_err_flg_bit {
+	C_PI_ERR_FLG__UC_ATTENTION_0 = 62,
+	C_PI_ERR_FLG__UC_ATTENTION_1 = 63,
+};
+
+enum c_pct_bitmask {
+	C_PCT_CFG_SRB_RETRY_GRP_CTRL__GRP_LOADED_MSK = 0x1,
+	C_PCT_CFG_SRB_RETRY_GRP_CTRL__GRP_ACTIVE_MSK = 0x2,
+	C_PCT_CFG_SW_SIM_SRC_RSP__LOADED_MSK = 0x1000000000000,
+	C_PCT_CFG_SW_RETRY_SRC_CLS_REQ__LOADED_MSK = 0x10000,
+	C_PCT_CFG_SW_SIM_TGT_CLS_REQ__LOADED_MSK = 0x10000,
+};
+
+enum c2_link_dn_behavior {
+	C2_HNI_PML_LD_DISCARD = 0,
+	C2_HNI_PML_LD_BLOCK = 1,
+	C2_HNI_PML_LD_BEST_EFFORT = 2,
+};
+
+enum c2_llr_state {
+	C2_HNI_PML_OFF_LLR = 0,
+	C2_HNI_PML_INIT = 1,
+	C2_HNI_PML_ADVANCE = 2,
+	C2_HNI_PML_HALT = 3,
+	C2_HNI_PML_REPLAY = 4,
+	C2_HNI_PML_DISCARD = 5,
+	C2_HNI_PML_MONITOR = 6,
+};
+
+enum c2_link_function {
+	C2_LF_ETH_ACC = 0,
+	C2_LF_ETH_TRUNK = 1,
+	C2_LF_C3_R2 = 2,
+	C2_LF_C2_R2 = 3,
+	C2_LF_C1_R2 = 4,
+	C2_LF_C3_R1 = 5,
+	C2_LF_R1_R2 = 6,
+	C2_LF_R2_R2_FAB_NRML = 7,
+	C2_LF_R2_R2_FAB_TRANS = 8,
+	C2_LF_R2_R2_FAB_TO_FAB = 9,
+	C2_LF_R2_R2_FAB_RTR = 10,
+	C2_LF_C2_R1 = 11,
+};
+
+struct c_fa_anon {
+	__u8 action      :  3;
+	__u32: 20;
+	__u16 fa_format  :  9;
+};
+
+struct c_fa_unicast {
+	__u16 endpoint_defined  : 12;
+	__u32 nid               : 20;
+};
+
+struct c_fa_multicast {
+	__u8 action         :  3;
+	__u16 multicast_id  : 13;
+	__u8:  2;
+	__u8 reduction_id   :  3;
+	__u8:  2;
+	__u16 format        :  9;
+};
+
+union c_fab_addr {
+	struct c_fa_multicast multicast;
+	struct c_fa_unicast unicast;
+	struct c_fa_anon anon;
+};
+
+struct c_process {
+	__u32 process;
+};
+
+struct c_hdr_data {
+	__u64 hdr_data;
+};
+
+struct c_padded_ct_success {
+	__u64 value      : 48;
+	__u16 unused_0;
+};
+
+struct c_padded_ct_failure {
+	__u8 value  :  7;
+	__u64: 57;
+};
+
+struct c_tct_idx {
+	__u16 tct_idx  : 13;
+	__u8:  3;
+};
+
+#ifdef __LITTLE_ENDIAN
+struct c_pkt_type {
+	__u8 opcode        :  4;
+	__u8 ver_pkt_type  :  3;
+	__u8 req_not_rsp   :  1;
+};
+#else
+struct c_pkt_type {
+	__u8 req_not_rsp   :  1;
+	__u8 ver_pkt_type  :  3;
+	__u8 opcode        :  4;
+};
+#endif
+
+struct c_ts {
+	__u32 ns   : 30;
+	__u8 rsvd  :  2;
+	__u64 sec  : 48;
+} __attribute__((packed));
+
+struct c_padded_sct_idx {
+	__u16 sct_idx  : 12;
+	__u8:  1;
+	__u8:  3;
+};
+
+union c_conn_idx {
+	struct c_tct_idx tct_idx;
+	struct c_padded_sct_idx padded_sct_idx;
+};
+
+struct c_ule_entry {
+	__u32: 17;
+	__u8 restricted          :  1;
+	__u8 tc                  :  3;
+	__u8 use_offset_for_get  :  1;
+	__u16 rendezvous_id      :  8;
+	__u16 vni                : 16;
+	__u16 dscp               :  6;
+	__u32 sfa_nid            : 20;
+	__u64 hdr_data           : 64;
+	__u64 match_bits         : 64;
+	__u32 initiator          : 32;
+	__u64 start_or_offset    : 57;
+	__u32 mlength            : 32;
+	__u32 request_len        : 32;
+	__u8 opcode              :  4;
+	__u8 src_error           :  1;
+	__u16 addr               : 14;
+	__u8 vld                 :  1;
+	__u16: 11;
+} __attribute__((packed));
+
+struct c_amo_payload {
+	__u8 amo_op       :  4;
+	__u8:  4;
+	__u8 amo_type     :  4;
+	__u8:  4;
+	__u8 cswap_op     :  3;
+	__u8:  5;
+	__u64: 40;
+	__u64 op1_word1;
+	__u64 op1_word2;
+	__u64 op2_word1;
+	__u64 op2_word2;
+};
+
+struct c_small_amo_payload {
+	__u8 amo_op       :  4;
+	__u8:  4;
+	__u8 amo_type     :  4;
+	__u8:  4;
+	__u64: 48;
+	__u64 op1_word1;
+};
+
+struct c_page_table_entry {
+	__u8:  6;
+	__u64 ptr  : 51;
+	__u8 r     :  1;
+	__u8 w     :  1;
+	__u8 leaf  :  1;
+	__u8 p     :  1;
+	__u8:  3;
+};
+
+struct c_page_request_entry {
+	__u64 addr   : 45;
+	__u16 index  :  9;
+	__u16 acid   : 10;
+} __attribute__((packed));
+
+struct c_cmd {
+	__u8 cmd_type  :  2;
+	__u8 cmd_size  :  2;
+	__u8 opcode    :  4;
+};
+
+struct c_cmdq {
+	__u16 wr_ptr;
+	__u16 unused_0[511];
+	__u64 ll_wr64a0123[128];
+	__u64 ll_wr128a02[128];
+	__u64 ll_wr128a13[128];
+};
+
+struct c_cq_status {
+	__u16 rd_ptr;
+	__u16 num_write_cmds_rejected;
+	__u8 fail_command;
+	__u8 unused_0;
+	__u8 return_code                :  6;
+	__u16:  7;
+	__u8 fail_loc_32                :  1;
+	__u8 fail_ll                    :  1;
+	__u8 ll_disabled                :  1;
+};
+
+struct c_idc_hdr {
+	struct c_cmd command;
+	__u8 length;
+	__u16 unused_0;
+	union c_fab_addr dfa;
+	__u64 remote_offset  : 56;
+	__u8 unused_1;
+};
+
+struct c_idc_amo_cmd {
+	struct c_idc_hdr idc_header;
+	__u64 local_addr           : 57;
+	__u8:  7;
+	__u8 atomic_op             :  4;
+	__u8:  4;
+	__u8 atomic_type           :  4;
+	__u8:  4;
+	__u8 cswap_op              :  3;
+	__u8:  5;
+	__u64: 40;
+	__u64 op1_word1;
+	__u64 op1_word2;
+	__u64 op2_word1;
+	__u64 op2_word2;
+};
+
+struct c_idc_msg_hdr {
+	struct c_cmd command;
+	__u8 length;
+	__u16 unused_0;
+	union c_fab_addr dfa;
+	__u64 match_bits;
+	__u64 header_data;
+	__u64 user_ptr;
+	__u8 data[0];
+};
+
+struct c_cstate_cmd {
+	struct c_cmd command;
+	__u8 length;
+	__u8 write_lac              :  3;
+	__u8 event_send_disable     :  1;
+	__u8 event_success_disable  :  1;
+	__u8 event_ct_send          :  1;
+	__u8 event_ct_reply         :  1;
+	__u8 event_ct_ack           :  1;
+	__u8 event_ct_bytes         :  1;
+	__u8 get_with_local_flag    :  1;
+	__u8 restricted             :  1;
+	__u8 reduction              :  1;
+	__u8 flush                  :  1;
+	__u8 use_offset_for_get     :  1;
+	__u8:  1;
+	__u8:  1;
+	__u32 initiator;
+	__u8 index_ext              :  5;
+	__u8:  3;
+	__u64: 56;
+	__u64 user_ptr;
+	__u32 unused_0;
+	__u16 ct                    : 11;
+	__u8:  5;
+	__u16 eq                    : 11;
+	__u8:  5;
+};
+
+struct c_idc_eth_cmd {
+	struct c_cmd command;
+	__u8 length;
+	__u8 flow_hash;
+	__u8 checksum_ctrl     :  2;
+	__u8:  2;
+	__u8 fmt               :  1;
+	__u8:  3;
+	__u16 checksum_start   : 10;
+	__u8:  2;
+	__u16 checksum_offset  :  6;
+	__u16: 14;
+	__u64 unused_0;
+	__u8 data[0];
+} __attribute__((packed));
+
+struct c_dma_eth_cmd {
+	struct c_cmd command;
+	__u8 read_lac               :  3;
+	__u8:  4;
+	__u8 fmt                    :  1;
+	__u8 flow_hash;
+	__u8 checksum_ctrl          :  2;
+	__u8:  3;
+	__u8 num_segments           :  3;
+	__u16 checksum_start        : 10;
+	__u8:  2;
+	__u16 checksum_offset       :  6;
+	__u16: 14;
+	__u64 user_ptr;
+	__u16 len[7];
+	__u16 unused_0;
+	__u64 addr[7];
+	__u16 total_len;
+	__u8 event_send_disable     :  1;
+	__u8 event_success_disable  :  1;
+	__u8 event_ct_send          :  1;
+	__u8 event_ct_reply         :  1;
+	__u8 event_ct_ack           :  1;
+	__u8 event_ct_bytes         :  1;
+	__u8 get_with_local_flag    :  1;
+	__u8 restricted             :  1;
+	__u8 reduction              :  1;
+	__u8 flush                  :  1;
+	__u8 use_offset_for_get     :  1;
+	__u8:  1;
+	__u8:  1;
+	__u8:  3;
+	__u16 ct                    : 11;
+	__u8:  5;
+	__u16 eq                    : 11;
+	__u8:  5;
+} __attribute__((packed));
+
+struct c_nomatch_dma_cmd {
+	struct c_cmd command;
+	__u8 index_ext              :  5;
+	__u8:  3;
+	__u8 lac                    :  3;
+	__u8 event_send_disable     :  1;
+	__u8 event_success_disable  :  1;
+	__u8 event_ct_send          :  1;
+	__u8 event_ct_reply         :  1;
+	__u8 event_ct_ack           :  1;
+	__u8 event_ct_bytes         :  1;
+	__u8 get_with_local_flag    :  1;
+	__u8 restricted             :  1;
+	__u8 reduction              :  1;
+	__u8 flush                  :  1;
+	__u8 use_offset_for_get     :  1;
+	__u8:  1;
+	__u8:  1;
+	union c_fab_addr dfa;
+	__u64 remote_offset         : 56;
+	__u8 unused_0;
+	__u64 local_addr            : 57;
+	__u8:  7;
+	__u32 request_len;
+	__u16 ct                    : 11;
+	__u8:  5;
+	__u16 eq                    : 11;
+	__u8:  5;
+};
+
+struct c_full_dma_cmd {
+	struct c_cmd command;
+	__u8 index_ext              :  5;
+	__u8:  3;
+	__u8 lac                    :  3;
+	__u8 event_send_disable     :  1;
+	__u8 event_success_disable  :  1;
+	__u8 event_ct_send          :  1;
+	__u8 event_ct_reply         :  1;
+	__u8 event_ct_ack           :  1;
+	__u8 event_ct_bytes         :  1;
+	__u8 get_with_local_flag    :  1;
+	__u8 restricted             :  1;
+	__u8 reduction              :  1;
+	__u8 flush                  :  1;
+	__u8 use_offset_for_get     :  1;
+	__u8:  1;
+	__u8:  1;
+	union c_fab_addr dfa;
+	__u64 remote_offset         : 56;
+	__u8 unused_0;
+	__u64 local_addr            : 57;
+	__u8:  7;
+	__u32 request_len;
+	__u16 ct                    : 11;
+	__u8:  5;
+	__u16 eq                    : 11;
+	__u8:  5;
+	__u32 eager_length          : 20;
+	__u8:  4;
+	__u8 rendezvous_id;
+	__u32 initiator;
+	__u64 match_bits;
+	__u64 header_data;
+	__u64 user_ptr;
+};
+
+struct c_dma_amo_cmd {
+	struct c_cmd command;
+	__u8 index_ext              :  5;
+	__u8:  3;
+	__u8 lac                    :  3;
+	__u8 event_send_disable     :  1;
+	__u8 event_success_disable  :  1;
+	__u8 event_ct_send          :  1;
+	__u8 event_ct_reply         :  1;
+	__u8 event_ct_ack           :  1;
+	__u8 event_ct_bytes         :  1;
+	__u8 get_with_local_flag    :  1;
+	__u8 restricted             :  1;
+	__u8 reduction              :  1;
+	__u8 flush                  :  1;
+	__u8 use_offset_for_get     :  1;
+	__u8:  1;
+	__u8:  1;
+	union c_fab_addr dfa;
+	__u64 remote_offset         : 56;
+	__u8 unused_0;
+	__u64 local_read_addr       : 57;
+	__u8:  7;
+	__u32 request_len;
+	__u16 ct                    : 11;
+	__u8:  5;
+	__u16 eq                    : 11;
+	__u8:  5;
+	__u32 unused_1;
+	__u32 initiator;
+	__u64 match_bits;
+	__u64 header_data;
+	__u64 user_ptr;
+	__u64 local_write_addr      : 57;
+	__u8:  7;
+	__u8 atomic_op              :  4;
+	__u8:  4;
+	__u8 atomic_type            :  4;
+	__u8:  4;
+	__u8 cswap_op               :  3;
+	__u8:  5;
+	__u8 unused_2;
+	__u8 write_lac              :  3;
+	__u32: 29;
+	__u64 op2_word1;
+	__u64 op2_word2;
+};
+
+struct c_ct_cmd {
+	struct c_cmd command;
+	__u8 unused_0;
+	__u16 ct               : 11;
+	__u8:  5;
+	__u16 trig_ct          : 11;
+	__u8:  5;
+	__u16 eq               : 11;
+	__u8:  5;
+	__u64 ct_success       : 48;
+	__u8 ct_failure        :  7;
+	__u16:  7;
+	__u8 set_ct_success    :  1;
+	__u8 set_ct_failure    :  1;
+	__u64 threshold        : 48;
+	__u16 unused_1;
+	__u8 embedded_dma[0];
+} __attribute__((packed));
+
+struct c_cq_cmd {
+	struct c_cmd command;
+	__u32: 24;
+	__u8 lcid           :  4;
+	__u8:  4;
+	__u32: 24;
+	__u64 unused_0;
+	__u64 unused_1;
+	__u64 unused_2;
+	__u64 unused_3;
+	__u64 unused_4;
+	__u64 unused_5;
+	__u64 unused_6;
+};
+
+struct c_target_cmd {
+	struct c_cmd command;
+	__u8 ptl_list                :  2;
+	__u8:  6;
+	__u16 ptlte_index            : 11;
+	__u8:  5;
+	__u8 event_ct_bytes          :  1;
+	__u8 event_ct_overflow       :  1;
+	__u8 event_ct_comm           :  1;
+	__u8 event_unlink_disable    :  1;
+	__u8 event_success_disable   :  1;
+	__u8 event_comm_disable      :  1;
+	__u8 event_link_disable      :  1;
+	__u8 unrestricted_end_ro     :  1;
+	__u8 unrestricted_body_ro    :  1;
+	__u8 unexpected_hdr_disable  :  1;
+	__u8 use_once                :  1;
+	__u8 no_truncate             :  1;
+	__u8 manage_local            :  1;
+	__u8 op_get                  :  1;
+	__u8 op_put                  :  1;
+	__u8:  1;
+	__u16 ct                     : 11;
+	__u8:  5;
+	__u16 buffer_id;
+	__u8 lac                     :  3;
+	__u8:  5;
+	__u8 restart_seq             :  1;
+	__u8:  7;
+	__u32 unused_0;
+	__u64 start                  : 57;
+	__u8:  7;
+	__u64 length                 : 56;
+	__u8 unused_1;
+	__u32 min_free               : 24;
+	__u8 unused_2;
+	__u32 match_id;
+	__u64 match_bits;
+	__u64 ignore_bits;
+	__u64 unused_3;
+};
+
+struct c_set_state_cmd {
+	struct c_cmd command;
+	__u8 ptlte_state    :  3;
+	__u8:  5;
+	__u16 ptlte_index   : 11;
+	__u8:  5;
+	__u32 unused_0;
+	__u64 current_addr  : 57;
+	__u8:  7;
+	__u32 drop_count    : 24;
+	__u8 unused_1;
+	__u32 unused_2;
+	__u64 unused_3;
+	__u64 unused_4;
+	__u64 unused_5;
+	__u64 unused_6;
+	__u64 unused_7;
+};
+
+struct c_eq_status {
+	__u32 timestamp_ns_cpy     : 30;
+	__u64: 34;
+	__u64 timestamp_sec_cpy    : 48;
+	__u8 thld_sts              :  1;
+	__u8:  3;
+	__u8 thld_id               :  2;
+	__u8:  2;
+	__u8 unackd_dropped_event  :  1;
+	__u8:  3;
+	__u8 event_drop_seq_no     :  1;
+	__u8:  3;
+	__u32 event_slots_free     : 26;
+	__u8:  6;
+	__u32 event_slots_rsrvd    : 26;
+	__u8:  6;
+	__u32 wr_ptr               : 26;
+	__u8:  6;
+	__u8 using_buffer_b        :  1;
+	__u32: 31;
+	__u64 unused_0;
+	__u64 unused_1;
+	__u32 unused_2;
+	__u32 timestamp_ns         : 30;
+	__u8:  2;
+	__u64 timestamp_sec        : 48;
+	__u16 unused_3;
+};
+
+struct c_event_initiator_short {
+	__u64 user_ptr;
+	__u32 mlength;
+	__u8 ptl_list     :  2;
+	__u8:  2;
+	__u8 rendezvous   :  1;
+	__u8 retry        :  1;
+	__u8 tgt_error    :  1;
+	__u16:  9;
+	__u8 event_size   :  2;
+	__u8 event_type   :  5;
+	__u8:  1;
+	__u8 return_code  :  6;
+	__u8:  2;
+};
+
+struct c_event_initiator_long {
+	__u64 user_ptr;
+	__u32 mlength;
+	__u8 ptl_list        :  2;
+	__u8:  2;
+	__u8 rendezvous      :  1;
+	__u8 retry           :  1;
+	__u8 tgt_error       :  1;
+	__u16:  9;
+	__u8 event_size      :  2;
+	__u8 event_type      :  5;
+	__u8:  1;
+	__u8 unused_0;
+	__u32 timestamp_ns   : 30;
+	__u64: 34;
+	__u64 timestamp_sec  : 48;
+	__u8 unused_1;
+	__u8 return_code     :  6;
+	__u8:  2;
+};
+
+struct c_event_trig_op_short {
+	__u64 threshold   : 48;
+	__u16 unused_0;
+	__u16 ct_handle   : 11;
+	__u64: 37;
+	__u8 event_size   :  2;
+	__u8 event_type   :  5;
+	__u8:  1;
+	__u8 return_code  :  6;
+	__u8:  2;
+};
+
+struct c_event_trig_op_long {
+	__u64 threshold      : 48;
+	__u16 unused_0;
+	__u16 ct_handle      : 11;
+	__u64: 37;
+	__u8 event_size      :  2;
+	__u8 event_type      :  5;
+	__u8:  1;
+	__u8 unused_1;
+	__u32 timestamp_ns   : 30;
+	__u64: 34;
+	__u64 timestamp_sec  : 48;
+	__u8 unused_2;
+	__u8 return_code     :  6;
+	__u8:  2;
+};
+
+struct c_event_cmd_fail {
+	__u16 cq_id              : 10;
+	__u8 is_target           :  1;
+	__u8:  5;
+	__u16 fail_loc;
+	struct c_cmd fail_command;
+	__u32: 24;
+	__u64: 48;
+	__u8 event_size          :  2;
+	__u8 event_type          :  5;
+	__u8:  1;
+	__u8 return_code         :  6;
+	__u8:  2;
+};
+
+struct c_state_chg_fields {
+	__u8 ptlte_state  :  3;
+	__u8:  5;
+	__u8 sc_reason    :  4;
+	__u8:  4;
+	__u8 sc_nic_auto  :  1;
+	__u16: 15;
+};
+
+union c_tgt_ol_initiator {
+	struct c_process initiator;
+	struct c_state_chg_fields state_change;
+};
+
+struct c_event_target_long {
+	__u64 header_data;
+	union c_tgt_ol_initiator initiator;
+	__u16 ptlte_index                 : 11;
+	__u8:  5;
+	__u8 event_size                   :  2;
+	__u8 event_type                   :  5;
+	__u8:  1;
+	__u8 ptl_list                     :  2;
+	__u8 rendezvous                   :  1;
+	__u8 get_issued                   :  1;
+	__u8 auto_unlinked                :  1;
+	__u8:  3;
+	__u64 match_bits;
+	__u16 buffer_id;
+	__u16 vni;
+	__u32 timestamp_ns                : 30;
+	__u8 timestamp_sec_low            :  2;
+	__u32 mlength;
+	__u32 rlength;
+	__u64 remote_offset               : 56;
+	__u8 unused_0;
+	__u64 start                       : 57;
+	__u8:  7;
+	__u16 lpe_stat_1;
+	__u16 lpe_stat_2;
+	__u8 atomic_type                  :  4;
+	__u8 atomic_op                    :  4;
+	__u8 cswap_op                     :  3;
+	__u8:  5;
+	__u8 rendezvous_id;
+	__u8 return_code                  :  6;
+	__u8:  2;
+};
+
+struct c_event_target_short {
+	__u64 header_data;
+	__u32 initiator;
+	__u16 ptlte_index   : 11;
+	__u8:  5;
+	__u8 event_size     :  2;
+	__u8 event_type     :  5;
+	__u8:  1;
+	__u8 ptl_list       :  2;
+	__u8:  2;
+	__u8 auto_unlinked  :  1;
+	__u8:  3;
+	__u64 match_bits;
+	__u16 buffer_id;
+	__u16 vni;
+	__u32 length        : 20;
+	__u8:  4;
+	__u8 return_code    :  6;
+	__u8:  2;
+};
+
+struct c_event_target_enet {
+	__u16 checksum;
+	__u64 pkt_cnt          : 46;
+	__u8 seg_cnt           :  2;
+	__u32 rss_hash_value;
+	__u16 ptlte_index      : 11;
+	__u8:  5;
+	__u8 event_size        :  2;
+	__u8 event_type        :  5;
+	__u8:  1;
+	__u8 ptl_list          :  2;
+	__u8:  2;
+	__u8 auto_unlinked     :  1;
+	__u8:  3;
+	__u64 start            : 57;
+	__u8:  7;
+	__u16 buffer_id;
+	__u8 rss_hash_type     :  5;
+	__u8:  3;
+	__u8 more_frags        :  1;
+	__u8:  1;
+	__u8 is_roce           :  1;
+	__u8 roce_icrc_ok      :  1;
+	__u8 timestamp         :  1;
+	__u8 fmt               :  1;
+	__u8 parser_err        :  1;
+	__u8:  1;
+	__u16 length;
+	__u8 unused_0;
+	__u8 return_code       :  6;
+	__u8:  2;
+};
+
+struct c_event_enet_fgfc {
+	__u32 identifier;
+	__u32 unused_0;
+	__u8 fgfc_type     :  2;
+	__u8:  6;
+	__u8 xoff          :  1;
+	__u8:  7;
+	__u8 srcip_tag     :  2;
+	__u8:  6;
+	__u8 unused_1;
+	__u16 credits;
+	__u8 event_size    :  2;
+	__u8 event_type    :  5;
+	__u8:  1;
+	__u8 return_code   :  6;
+	__u8:  2;
+};
+
+struct c_event_pct {
+	union c_fab_addr dfa;
+	__u16 seq_num            : 12;
+	__u8:  4;
+	__u16 unused_0;
+	__u8 pct_event_type      :  3;
+	__u8:  5;
+	__u8 unused_1;
+	__u16 spt_idx            : 11;
+	__u8:  5;
+	union c_conn_idx conn_idx;
+	__u8 event_size          :  2;
+	__u8 event_type          :  5;
+	__u8:  1;
+	__u8 return_code         :  6;
+	__u8:  2;
+};
+
+struct c_event_timestamp {
+	__u32 timestamp_ns   : 30;
+	__u64: 34;
+	__u64 timestamp_sec  : 48;
+	__u8 event_size      :  2;
+	__u8 event_type      :  5;
+	__u8:  1;
+	__u8 return_code     :  6;
+	__u8:  2;
+};
+
+struct c_event_eq_switch {
+	__u64 unused_0;
+	__u64: 48;
+	__u8 event_size   :  2;
+	__u8 event_type   :  5;
+	__u8:  1;
+	__u8 return_code  :  6;
+	__u8:  2;
+};
+
+struct c_cq_cntrs {
+	__u64 success_tx_cntr;
+	__u64 success_tgt_cntr;
+	__u64 fail_tx_cntr;
+	__u64 fail_tgt_cntr;
+	__u64 mem_cor_err_cntr;
+	__u64 mem_ucor_err_cntr;
+	__u64 rarb_ll_err_cntr;
+	__u64 rarb_err_cntr;
+	__u64 wr_ptr_updt_err_cntr;
+	__u64 cntr0[3];
+	__u64 num_txq_cmd_reads[4];
+	__u64 num_tgq_cmd_reads[4];
+	__u64 num_tou_cmd_reads[4];
+	__u64 tx_waiting_on_read[4];
+	__u64 tgt_waiting_on_read[4];
+	__u64 num_tx_cmd_align_errors;
+	__u64 num_tx_cmd_op_errors;
+	__u64 num_tx_cmd_arg_errors;
+	__u64 num_tx_cmd_perm_errors;
+	__u64 num_tgt_cmd_arg_errors;
+	__u64 num_tgt_cmd_perm_errors;
+	__u64 cq_oxe_num_flits;
+	__u64 cq_oxe_num_stalls;
+	__u64 cq_oxe_num_idles;
+	__u64 cq_tou_num_flits;
+	__u64 cq_tou_num_stalls;
+	__u64 cq_tou_num_idles;
+	__u64 num_idc_cmds[4];
+	__u64 num_dma_cmds[4];
+	__u64 num_cq_cmds[4];
+	__u64 num_ll_cmds[4];
+	__u64 num_tgt_cmds[4];
+	__u64 dma_cmd_counts[16];
+	__u64 cq_cmd_counts[16];
+	__u64 cycles_blocked[4];
+	__u64 cntr2[12];
+	__u64 num_ll_ops_successful[4];
+	__u64 num_ll_ops_rejected[4];
+	__u64 num_ll_ops_split[4];
+	__u64 num_ll_ops_received[4];
+};
+
+struct c_tou_cntrs {
+	__u64 success_cntr;
+	__u64 fail_cntr;
+	__u64 cntr0[2];
+	__u64 cq_tou_num_cmds;
+	__u64 cq_tou_num_stalls;
+	__u64 tou_oxe_num_flits;
+	__u64 tou_oxe_num_stalls;
+	__u64 tou_oxe_num_idles;
+	__u64 list_rebuild_cycles;
+	__u64 cmd_fifo_full_cycles;
+	__u64 cntr1[7];
+	__u64 num_doorbell_writes;
+	__u64 num_ct_updates;
+	__u64 num_trig_cmds[4];
+	__u64 num_list_rebuilds[4];
+	__u64 ct_cmd_counts[16];
+	__u64 cntr2[20];
+};
+
+struct c1_oxe_cntrs {
+	__u64 mem_cor_err_cntr;
+	__u64 mem_ucor_err_cntr;
+	__u64 err_no_translation;
+	__u64 err_invalid_ac;
+	__u64 err_page_perm;
+	__u64 err_ta_error;
+	__u64 err_page_req;
+	__u64 err_pci_ep;
+	__u64 err_pci_cmpl;
+	__u64 rsvd0;
+	__u64 stall_pct_bc[10];
+	__u64 stall_pbuf_bc[10];
+	__u64 stall_ts_no_out_crd_tsc[10];
+	__u64 stall_ts_no_in_crd_tsc[10];
+	__u64 stall_with_no_pci_tag;
+	__u64 stall_with_no_atu_tag;
+	__u64 stall_stfwd_eop;
+	__u64 stall_pcie_scoreboard;
+	__u64 stall_wr_conflict_pkt_buff_bnk[4];
+	__u64 stall_idc_no_buff_bc[10];
+	__u64 stall_idc_cmd_no_deq;
+	__u64 stall_non_idc_cmd_no_deq;
+	__u64 stall_fgfc_blk[4];
+	__u64 stall_fgfc_cntrl[4];
+	__u64 stall_fgfc_start[4];
+	__u64 stall_fgfc_end[4];
+	__u64 stall_hdr_arb;
+	__u64 stall_ioi_last_ordered;
+	__u64 rsvd1[3];
+	__u64 ignore_errs;
+	__u64 ioi_dma;
+	__u64 ioi_pkts_ordered;
+	__u64 ioi_pkts_unordered;
+	__u64 ptl_tx_put_msgs_tsc[10];
+	__u64 ptl_tx_get_msgs_tsc[10];
+	__u64 ptl_tx_put_pkts_tsc[10];
+	__u64 ptl_tx_mr_msgs;
+	__u64 num_hrp_cmds;
+	__u64 channel_idle;
+	__u64 mcu_meas[96];
+	__u64 prf_set0_st_ready;
+	__u64 prf_set0_st_pct_idx_wait;
+	__u64 prf_set0_st_pktbuf_req;
+	__u64 prf_set0_st_pktbuf_gnt;
+	__u64 prf_set0_st_header;
+	__u64 prf_set0_st_dma_mdr;
+	__u64 prf_set0_st_dma_upd;
+	__u64 prf_set0_pktbuf_na;
+	__u64 prf_set0_spt_na;
+	__u64 prf_set0_smt_na;
+	__u64 prf_set0_srb_na;
+	__u64 prf_set0_ts_select;
+	__u64 prf_set0_occ_hist_bin0;
+	__u64 prf_set0_occ_hist_bin1;
+	__u64 prf_set0_occ_hist_bin2;
+	__u64 prf_set0_occ_hist_bin3;
+	__u64 prf_set1_st_ready;
+	__u64 prf_set1_st_pct_idx_wait;
+	__u64 prf_set1_st_pktbuf_req;
+	__u64 prf_set1_st_pktbuf_gnt;
+	__u64 prf_set1_st_header;
+	__u64 prf_set1_st_dma_mdr;
+	__u64 prf_set1_st_dma_upd;
+	__u64 prf_set1_pktbuf_na;
+	__u64 prf_set1_spt_na;
+	__u64 prf_set1_smt_na;
+	__u64 prf_set1_srb_na;
+	__u64 prf_set1_ts_select;
+	__u64 prf_set1_occ_hist_bin0;
+	__u64 prf_set1_occ_hist_bin1;
+	__u64 prf_set1_occ_hist_bin2;
+	__u64 prf_set1_occ_hist_bin3;
+};
+
+struct c2_oxe_cntrs {
+	__u64 mem_cor_err_cntr;
+	__u64 mem_ucor_err_cntr;
+	__u64 err_no_translation;
+	__u64 err_invalid_ac;
+	__u64 err_page_perm;
+	__u64 err_ta_error;
+	__u64 err_page_req;
+	__u64 err_pci_ep;
+	__u64 err_pci_cmpl;
+	__u64 rsvd0;
+	__u64 stall_pct_bc[10];
+	__u64 stall_pbuf_bc[10];
+	__u64 stall_ts_no_out_crd_tsc[10];
+	__u64 stall_ts_no_in_crd_tsc[10];
+	__u64 stall_with_no_pci_tag;
+	__u64 stall_with_no_atu_tag;
+	__u64 stall_stfwd_eop;
+	__u64 stall_pcie_scoreboard;
+	__u64 stall_wr_conflict_pkt_buff_bnk[4];
+	__u64 stall_idc_no_buff_bc[10];
+	__u64 stall_idc_cmd_no_deq;
+	__u64 stall_non_idc_cmd_no_deq;
+	__u64 stall_fgfc_blk[4];
+	__u64 stall_fgfc_cntrl[4];
+	__u64 stall_fgfc_start[4];
+	__u64 stall_fgfc_end[4];
+	__u64 stall_hdr_arb;
+	__u64 stall_ioi_last_ordered;
+	__u64 spt_cdt_errs;
+	__u64 smt_cdt_errs;
+	__u64 rsvd1;
+	__u64 ignore_errs;
+	__u64 ioi_dma;
+	__u64 ioi_pkts_ordered;
+	__u64 ioi_pkts_unordered;
+	__u64 ptl_tx_put_msgs_tsc[10];
+	__u64 ptl_tx_get_msgs_tsc[10];
+	__u64 ptl_tx_put_pkts_tsc[10];
+	__u64 ptl_tx_mr_msgs;
+	__u64 num_hrp_cmds;
+	__u64 channel_idle;
+	__u64 mcu_meas[96];
+	__u64 prf_set0_st_ready;
+	__u64 prf_set0_st_pct_idx_wait;
+	__u64 prf_set0_st_pktbuf_req;
+	__u64 prf_set0_st_pktbuf_gnt;
+	__u64 prf_set0_st_header;
+	__u64 prf_set0_st_dma_mdr;
+	__u64 prf_set0_st_dma_upd;
+	__u64 prf_set0_pktbuf_na;
+	__u64 prf_set0_spt_na;
+	__u64 prf_set0_smt_na;
+	__u64 prf_set0_srb_na;
+	__u64 prf_set0_ts_select;
+	__u64 prf_set0_occ_hist_bin0;
+	__u64 prf_set0_occ_hist_bin1;
+	__u64 prf_set0_occ_hist_bin2;
+	__u64 prf_set0_occ_hist_bin3;
+	__u64 prf_set1_st_ready;
+	__u64 prf_set1_st_pct_idx_wait;
+	__u64 prf_set1_st_pktbuf_req;
+	__u64 prf_set1_st_pktbuf_gnt;
+	__u64 prf_set1_st_header;
+	__u64 prf_set1_st_dma_mdr;
+	__u64 prf_set1_st_dma_upd;
+	__u64 prf_set1_pktbuf_na;
+	__u64 prf_set1_spt_na;
+	__u64 prf_set1_smt_na;
+	__u64 prf_set1_srb_na;
+	__u64 prf_set1_ts_select;
+	__u64 prf_set1_occ_hist_bin0;
+	__u64 prf_set1_occ_hist_bin1;
+	__u64 prf_set1_occ_hist_bin2;
+	__u64 prf_set1_occ_hist_bin3;
+};
+
+struct c_ixe_cntrs {
+	__u64 mem_cor_err_cntr;
+	__u64 mem_ucor_err_cntr;
+	__u64 cntr1[2];
+	__u64 port_dfa_mismatch;
+	__u64 hdr_checksum_errors;
+	__u64 ipv4_checksum_errors;
+	__u64 hrp_req_errors;
+	__u64 ip_options_errors;
+	__u64 get_len_errors;
+	__u64 roce_icrc_error;
+	__u64 parser_par_errors;
+	__u64 pbuf_rd_errors;
+	__u64 hdr_ecc_errors;
+	__u64 cntr2[2];
+	__u64 rx_udp_pkt;
+	__u64 rx_tcp_pkt;
+	__u64 rx_ipv4_pkt;
+	__u64 rx_ipv6_pkt;
+	__u64 rx_roce_pkt;
+	__u64 rx_ptl_gen_pkt;
+	__u64 rx_ptl_sml_pkt;
+	__u64 rx_ptl_unrestricted_pkt;
+	__u64 rx_ptl_smallmsg_pkt;
+	__u64 rx_ptl_continuation_pkt;
+	__u64 rx_ptl_restricted_pkt;
+	__u64 rx_ptl_connmgmt_pkt;
+	__u64 rx_ptl_response_pkt;
+	__u64 rx_unrecognized_pkt;
+	__u64 rx_ptl_sml_amo_pkt;
+	__u64 rx_ptl_msgs;
+	__u64 rx_ptl_multi_msgs;
+	__u64 rx_ptl_mr_msgs;
+	__u64 rx_pkt_drop_pct;
+	__u64 rx_pkt_drop_rmu_norsp;
+	__u64 rx_pkt_drop_rmu_wrsp;
+	__u64 rx_pkt_drop_ixe_parser;
+	__u64 rx_pkt_ipv4_options;
+	__u64 rx_pkt_ipv6_options;
+	__u64 rx_eth_seg;
+	__u64 rx_roce_seg;
+	__u64 rx_roce_spseg;
+	__u64 cntr3[21];
+	__u64 pool_ecn_pkts[4];
+	__u64 pool_no_ecn_pkts[4];
+	__u64 tc_req_ecn_pkts[8];
+	__u64 tc_req_no_ecn_pkts[8];
+	__u64 tc_rsp_ecn_pkts[8];
+	__u64 tc_rsp_no_ecn_pkts[8];
+	__u64 disp_lpe_puts;
+	__u64 disp_lpe_puts_ok;
+	__u64 disp_lpe_amos;
+	__u64 disp_lpe_amos_ok;
+	__u64 disp_mst_puts;
+	__u64 disp_mst_puts_ok;
+	__u64 disp_lpe_gets;
+	__u64 disp_lpe_gets_ok;
+	__u64 disp_mst_gets;
+	__u64 disp_mst_gets_ok;
+	__u64 disp_rpu_resps;
+	__u64 disp_rpu_err_reqs;
+	__u64 disp_dmawr_reqs;
+	__u64 disp_dmawr_resps;
+	__u64 disp_dmawr_resps_ok;
+	__u64 disp_oxe_resps;
+	__u64 disp_pct_getcomp;
+	__u64 disp_atu_reqs;
+	__u64 disp_atu_resps;
+	__u64 disp_atu_resps_ok;
+	__u64 disp_eth_events;
+	__u64 disp_put_events;
+	__u64 disp_amo_events;
+	__u64 disp_wr_conflicts;
+	__u64 disp_amo_conflicts;
+	__u64 disp_stall_conflict;
+	__u64 disp_stall_resp_fifo;
+	__u64 disp_stall_err_fifo;
+	__u64 disp_stall_atu_cdt;
+	__u64 disp_stall_atu_fifo;
+	__u64 disp_stall_gcomp_fifo;
+	__u64 disp_stall_mdid_cdts;
+	__u64 disp_stall_mst_match_fifo;
+	__u64 disp_stall_grr_id;
+	__u64 disp_stall_put_resp;
+	__u64 disp_atu_flush_reqs;
+	__u64 cntr4[4];
+	__u64 dmawr_stall_p_cdt;
+	__u64 dmawr_stall_np_cdt;
+	__u64 dmawr_stall_np_req_cnt;
+	__u64 dmawr_stall_ftch_amo_cnt;
+	__u64 dmawr_p_pass_np_cnt;
+	__u64 dmawr_write_reqs;
+	__u64 dmawr_nic_amo_reqs;
+	__u64 dmawr_cpu_amo_reqs;
+	__u64 dmawr_cpu_ftch_amo_reqs;
+	__u64 dmawr_flush_reqs;
+	__u64 dmawr_req_no_write_reqs;
+	__u64 dmawr_amo_ex_invalid;
+	__u64 dmawr_amo_ex_overflow;
+	__u64 dmawr_amo_ex_underflow;
+	__u64 dmawr_amo_ex_inexact;
+	__u64 dmawr_amo_misaligned;
+	__u64 dmawr_amo_invalid_op;
+	__u64 dmawr_amo_len_err;
+	__u64 dmawr_pcie_unsuccess_cmpl;
+	__u64 dmawr_pcie_err_poisoned;
+	__u64 cntr5[4];
+};
+
+struct c_pct_cntrs {
+	__u64 mem_cor_err_cntr;
+	__u64 mem_ucor_err_cntr;
+	__u64 req_ordered;
+	__u64 req_unordered;
+	__u64 req_no_response;
+	__u64 eth_packets;
+	__u64 optip_packets;
+	__u64 ptls_response;
+	__u64 responses_received;
+	__u64 hrp_responses_received;
+	__u64 hrp_rsp_discard_received;
+	__u64 hrp_rsp_err_received;
+	__u64 conn_sct_open;
+	__u64 conn_tct_open;
+	__u64 mst_hit_on_som;
+	__u64 trs_hit_on_req;
+	__u64 cls_req_miss_tct;
+	__u64 clear_sent;
+	__u64 close_sent;
+	__u64 accel_close;
+	__u64 clear_close_drop;
+	__u64 req_src_error;
+	__u64 bad_seq_nacks;
+	__u64 no_tct_nacks;
+	__u64 no_mst_nacks;
+	__u64 no_trs_nacks;
+	__u64 no_matching_tct;
+	__u64 resource_busy;
+	__u64 err_no_matching_trs;
+	__u64 err_no_matching_mst;
+	__u64 spt_timeouts;
+	__u64 sct_timeouts;
+	__u64 tct_timeouts;
+	__u64 retry_srb_requests;
+	__u64 retry_trs_put;
+	__u64 retry_mst_get;
+	__u64 clr_cls_stalls;
+	__u64 close_rsp_drops;
+	__u64 trs_rsp_nack_drops;
+	__u64 req_blocked_closing;
+	__u64 req_blocked_clearing;
+	__u64 req_blocked_retry;
+	__u64 rsp_err_rcvd;
+	__u64 rsp_dropped_timeout;
+	__u64 rsp_dropped_try;
+	__u64 rsp_dropped_cls_try;
+	__u64 rsp_dropped_inactive;
+	__u64 pct_hni_flits;
+	__u64 pct_hni_stalls;
+	__u64 pct_ee_events;
+	__u64 pct_ee_stalls;
+	__u64 pct_cq_notifications;
+	__u64 pct_cq_stalls;
+	__u64 pct_mst_cmd0;
+	__u64 pct_mst_stalls0;
+	__u64 pct_mst_cmd1;
+	__u64 pct_mst_stalls1;
+	__u64 sct_stall_state;
+	__u64 tgt_cls_abort;
+	__u64 cls_req_bad_seqno_drops;
+	__u64 req_tct_tmout_drops;
+	__u64 trs_replay_pend_drops;
+	__u64 cntr_rsvd_1[2];
+	__u64 req_rsp_latency[32];
+	__u64 host_access_latency[16];
+	__u64 cntr_rsvd_2[16];
+};
+
+struct c_rmu_cntrs {
+	__u64 ptl_success_cntr;
+	__u64 enet_success_cntr;
+	__u64 mem_cor_err_cntr;
+	__u64 mem_ucor_err_cntr;
+	__u64 ptl_invld_dfa_cntr;
+	__u64 ptl_invld_vni_cntr;
+	__u64 ptl_no_ptlte_cntr;
+	__u64 enet_frame_rejected_cntr;
+	__u64 enet_ptlte_set_ctrl_err_cntr;
+	__u64 cntr_rsvd[7];
+};
+
+struct c_lpe_cntrs {
+	__u64 success_cntr;
+	__u64 fail_cntr;
+	__u64 mem_cor_err_cntr;
+	__u64 mem_ucor_err_cntr;
+	__u64 cntr0;
+	__u64 put_cmds;
+	__u64 rendezvous_put_cmds;
+	__u64 get_cmds;
+	__u64 amo_cmds;
+	__u64 famo_cmds;
+	__u64 cntr1[5];
+	__u64 err_entry_not_found_ethernet;
+	__u64 err_pt_disabled_eq_full;
+	__u64 err_pt_disabled_req_empty;
+	__u64 err_pt_disabled_cant_alloc_unexpected;
+	__u64 err_pt_disabled_no_match_in_overflow;
+	__u64 err_eq_disabled;
+	__u64 err_op_violation;
+	__u64 err_entry_not_found_unlink_failed;
+	__u64 err_entry_not_found_eq_full;
+	__u64 err_entry_not_found_req_empty;
+	__u64 err_entry_not_found_no_match_in_overflow;
+	__u64 err_entry_not_found_cant_alloc_unexpected;
+	__u64 err_invalid_endpoint;
+	__u64 err_no_space_append;
+	__u64 err_no_space_net;
+	__u64 err_search_no_match;
+	__u64 err_setstate_no_match;
+	__u64 err_src_error;
+	__u64 err_ptlte_sw_managed;
+	__u64 err_illegal_op;
+	__u64 err_restricted_unicast;
+	__u64 cntr2[5];
+	__u64 event_put_overflow;
+	__u64 cntr3;
+	__u64 event_get_overflow;
+	__u64 cntr4;
+	__u64 event_atomic_overflow;
+	__u64 plec_frees_csr;
+	__u64 event_fetch_atomic_overflow;
+	__u64 event_search;
+	__u64 event_rendezvous;
+	__u64 event_link;
+	__u64 event_unlink;
+	__u64 event_statechange;
+	__u64 plec_allocs;
+	__u64 plec_frees;
+	__u64 plec_hits;
+	__u64 cyc_no_rdy_cdts;
+	__u64 cyc_rrq_blocked[4];
+	__u64 cyc_blocked_lossless;
+	__u64 cyc_blocked_ixe_put;
+	__u64 cyc_blocked_ixe_get;
+	__u64 search_cmds;
+	__u64 search_success;
+	__u64 search_fail;
+	__u64 search_delete_cmds;
+	__u64 search_delete_success;
+	__u64 search_delete_fail;
+	__u64 unlink_cmds;
+	__u64 unlink_success;
+	__u64 net_match_requests[4];
+	__u64 net_match_success[4];
+	__u64 net_match_useonce[4];
+	__u64 net_match_local[4];
+	__u64 net_match_priority[4];
+	__u64 net_match_overflow[4];
+	__u64 net_match_request[4];
+	__u64 append_cmds[4];
+	__u64 append_success[4];
+	__u64 setstate_cmds[4];
+	__u64 setstate_success[4];
+	__u64 search_nid_any[4];
+	__u64 search_pid_any[4];
+	__u64 search_rank_any[4];
+	__u64 rndzv_puts[4];
+	__u64 rndzv_puts_offloaded[4];
+	__u64 num_truncated[4];
+	__u64 unexpected_get_amo[4];
+	__u64 cntr_rsvd[16];
+};
+
+struct c_mst_cntrs {
+	__u64 mem_cor_err_cntr;
+	__u64 mem_ucor_err_cntr;
+	__u64 allocations;
+	__u64 requests;
+	__u64 stalled_waiting_for_lpe;
+	__u64 stalled_waiting_get_crdts;
+	__u64 stalled_waiting_put_crdts;
+	__u64 stalled_waiting_ee_crdts;
+	__u64 cntr1[8];
+	__u64 err_cancelled;
+	__u64 cntr2[15];
+};
+
+struct c_ee_cntrs {
+	__u64 events_enqueued_cntr[4];
+	__u64 events_dropped_rsrvn_cntr[4];
+	__u64 events_dropped_fc_sc_cntr[4];
+	__u64 events_dropped_ordinary_cntr[4];
+	__u64 eq_status_update_cntr[4];
+	__u64 cbs_written_cntr[4];
+	__u64 partial_cbs_written_cntr[4];
+	__u64 expired_cbs_written_cntr[4];
+	__u64 eq_buffer_switch_cntr[4];
+	__u64 deferred_eq_switch_cntr[4];
+	__u64 addr_trans_prefetch_cntr[4];
+	__u64 eq_sw_state_wr_cntr[4];
+	__u64 lpe_event_req_cntr;
+	__u64 lpe_fe_cntr;
+	__u64 lpe_dd_cntr;
+	__u64 lpe_ce_cntr;
+	__u64 lpe_fe_stall_cntr;
+	__u64 lpe_ce_stall_cntr;
+	__u64 ixe_event_req_cntr;
+	__u64 ixe_fe_cntr;
+	__u64 ixe_dd_cntr;
+	__u64 ixe_ce_cntr;
+	__u64 ixe_fe_stall_cntr;
+	__u64 ixe_ce_stall_cntr;
+	__u64 mst_event_req_cntr;
+	__u64 mst_fe_cntr;
+	__u64 mst_dd_cntr;
+	__u64 mst_ce_cntr;
+	__u64 mst_fe_stall_cntr;
+	__u64 mst_ce_stall_cntr;
+	__u64 pct_event_req_cntr;
+	__u64 pct_fe_cntr;
+	__u64 pct_dd_cntr;
+	__u64 pct_ce_cntr;
+	__u64 pct_fe_stall_cntr;
+	__u64 pct_ce_stall_cntr;
+	__u64 hni_event_req_cntr;
+	__u64 hni_fe_cntr;
+	__u64 hni_fe_stall_cntr;
+	__u64 cq_event_req_cntr;
+	__u64 cq_fe_cntr;
+	__u64 cq_fe_stall_cntr;
+	__u64 ts_fe_cntr;
+	__u64 ts_fe_stall_cntr;
+	__u64 fe_arb_out_event_cntr;
+	__u64 fe_arb_out_stall_cntr;
+	__u64 ce_arb_out_event_cntr;
+	__u64 ce_arb_out_stall_cntr;
+	__u64 lpe_query_eq_none_cntr;
+	__u64 eqs_lpe_query_req_cntr;
+	__u64 eqs_csr_req_cntr;
+	__u64 eqs_csr_stall_cntr;
+	__u64 eqs_hws_init_req_cntr;
+	__u64 eqs_hws_init_stall_cntr;
+	__u64 eqs_expired_cb_req_cntr;
+	__u64 eqs_expired_cb_stall_cntr;
+	__u64 eqs_sts_updt_req_cntr;
+	__u64 eqs_sts_updt_stall_cntr;
+	__u64 eqs_sws_wr_req_cntr;
+	__u64 eqs_sws_wr_stall_cntr;
+	__u64 eqs_event_req_cntr;
+	__u64 eqs_event_stall_cntr;
+	__u64 eqs_arb_out_req_cntr;
+	__u64 eqs_free_cb_stall_cntr;
+	__u64 addr_trans_req_cntr;
+	__u64 tarb_wr_req_cntr;
+	__u64 tarb_irq_req_cntr;
+	__u64 tarb_stall_cntr;
+	__u64 event_type_cntr[32];
+	__u64 mem_cor_err_cntr;
+	__u64 mem_ucor_err_cntr;
+	__u64 eq_dsabld_event_err_cntr;
+	__u64 eq_dsabld_sws_err_cntr;
+	__u64 eq_dsabld_lpeq_err_cntr;
+	__u64 eq_rsrvn_uflw_err_cntr;
+	__u64 unxpctd_trnsltn_rsp_err_cntr;
+	__u64 rarb_hw_err_cntr;
+	__u64 rarb_sw_err_cntr;
+	__u64 tarb_err_cntr;
+	__u64 eq_state_ucor_err_cntr;
+	__u64 cntr_rsvd[13];
+};
+
+struct c_atu_cntrs {
+	__u64 mem_cor_err_cntr;
+	__u64 mem_ucor_err_cntr;
+	__u64 cache_miss[4];
+	__u64 cache_hit_base_page_size[4];
+	__u64 cache_hit_derivative1_page_size[4];
+	__u64 cache_hit_derivative2_page_size[4];
+	__u64 cache_miss_oxe;
+	__u64 cache_miss_ixe;
+	__u64 cache_miss_ee;
+	__u64 ats_trans_latency[4];
+	__u64 nta_trans_latency[4];
+	__u64 client_req_oxe;
+	__u64 client_req_ixe;
+	__u64 client_req_ee;
+	__u64 filtered_requests;
+	__u64 ats_prs_odp_latency[4];
+	__u64 nic_pri_odp_latency[4];
+	__u64 odp_requests[4];
+	__u64 client_rsp_not_ok[4];
+	__u64 cache_evictions;
+	__u64 ats_inval_cntr;
+	__u64 implicit_flr_inval_cntr;
+	__u64 implicit_ats_en_inval_cntr;
+	__u64 atucq_inval_cntr;
+	__u64 pcie_unsuccess_cmpl;
+	__u64 ats_trans_err;
+	__u64 pcie_err_poisoned;
+	__u64 ats_dynamic_state_change_cntr;
+	__u64 at_stall_ccp;
+	__u64 at_stall_no_ptid;
+	__u64 at_stall_np_cdts;
+	__u64 at_stall_tarb_arb;
+	__u64 inval_stall_arb;
+	__u64 inval_stall_cmpl_wait;
+};
+
+struct c_parbs_cntrs {
+	__u64 tarb_cq_posted_pkts;
+	__u64 tarb_cq_non_posted_pkts;
+	__u64 tarb_cq_sbe_cnt;
+	__u64 tarb_cq_mbe_cnt;
+	__u64 tarb_ee_posted_pkts;
+	__u64 tarb_ee_sbe_cnt;
+	__u64 tarb_ee_mbe_cnt;
+	__u64 tarb_ixe_posted_pkts;
+	__u64 tarb_ixe_non_posted_pkts;
+	__u64 tarb_ixe_sbe_cnt;
+	__u64 tarb_ixe_mbe_cnt;
+	__u64 tarb_oxe_non_posted_pkts;
+	__u64 tarb_oxe_sbe_cnt;
+	__u64 tarb_oxe_mbe_cnt;
+	__u64 tarb_atu_posted_pkts;
+	__u64 tarb_atu_non_posted_pkts;
+	__u64 tarb_atu_sbe_cnt;
+	__u64 tarb_atu_mbe_cnt;
+	__u64 tarb_pi_posted_pkts;
+	__u64 tarb_pi_non_posted_pkts;
+	__u64 tarb_pi_posted_blocked_cnt;
+	__u64 tarb_pi_non_posted_blocked_cnt;
+	__u64 tarb_cq_posted_fifo_sbe;
+	__u64 tarb_cq_non_posted_fifo_sbe;
+	__u64 tarb_ee_posted_fifo_sbe;
+	__u64 tarb_ixe_posted_fifo_sbe;
+	__u64 tarb_ixe_non_posted_fifo_sbe;
+	__u64 tarb_oxe_non_posted_fifo_sbe;
+	__u64 tarb_atu_posted_fifo_sbe;
+	__u64 tarb_atu_non_posted_fifo_sbe;
+	__u64 tarb_cq_posted_fifo_mbe;
+	__u64 tarb_cq_non_posted_fifo_mbe;
+	__u64 tarb_ee_posted_fifo_mbe;
+	__u64 tarb_ixe_posted_fifo_mbe;
+	__u64 tarb_ixe_non_posted_fifo_mbe;
+	__u64 tarb_oxe_non_posted_fifo_mbe;
+	__u64 tarb_atu_posted_fifo_mbe;
+	__u64 tarb_atu_non_posted_fifo_mbe;
+	__u64 tarb_reserved_cnts[10];
+	__u64 rarb_pi_posted_pkts;
+	__u64 rarb_pi_completion_pkts;
+	__u64 rarb_pi_sbe_cnt;
+	__u64 rarb_pi_mbe_cnt;
+	__u64 rarb_cq_posted_pkts;
+	__u64 rarb_cq_completion_pkts;
+	__u64 rarb_ee_posted_pkts;
+	__u64 rarb_ixe_posted_pkts;
+	__u64 rarb_ixe_completion_pkts;
+	__u64 rarb_oxe_completion_pkts;
+	__u64 rarb_atu_posted_pkts;
+	__u64 rarb_atu_completion_pkts;
+	__u64 rarb_reserved_cnts[4];
+};
+
+struct c_pi_cntrs {
+	__u64 pri_mb_rtrgt_tlps;
+	__u64 pri_mb_rtrgt_mwr_tlps;
+	__u64 pri_mb_rtrgt_mrd_tlps;
+	__u64 pri_mb_rtrgt_tlp_discards;
+	__u64 pri_mb_rtrgt_posted_tlp_discards;
+	__u64 pri_mb_rtrgt_non_posted_tlp_discards;
+	__u64 pri_mb_rtrgt_posted_tlp_partial_discards;
+	__u64 pri_mb_rtrgt_fifo_cor_errors;
+	__u64 pri_mb_rtrgt_fifo_ucor_errors;
+	__u64 pri_mb_xali_cmpl_tlps;
+	__u64 pri_mb_xali_cmpl_ca_tlps;
+	__u64 pri_mb_xali_cmpl_ur_tlps;
+	__u64 pri_mb_axi_wr_requests;
+	__u64 pri_mb_axi_rd_requests;
+	__u64 pri_mb_axi_wr_rsp_decerrs;
+	__u64 pri_mb_axi_wr_rsp_slverrs;
+	__u64 pri_mb_axi_rd_rsp_decerrs;
+	__u64 pri_mb_axi_rd_rsp_slverrs;
+	__u64 pri_mb_axi_rd_rsp_parerrs;
+	__u64 pri_rarb_rtrgt_tlps;
+	__u64 pri_rarb_rtrgt_mwr_tlps;
+	__u64 pri_rarb_rtrgt_msg_tlps;
+	__u64 pri_rarb_rtrgt_msgd_tlps;
+	__u64 pri_rarb_rtrgt_tlp_discards;
+	__u64 pri_rarb_rtrgt_fifo_cor_errors;
+	__u64 pri_rarb_rtrgt_fifo_ucor_errors;
+	__u64 pri_rarb_rbyp_tlps;
+	__u64 pri_rarb_rbyp_tlp_discards;
+	__u64 pri_rarb_rbyp_fifo_cor_errors;
+	__u64 pri_rarb_rbyp_fifo_ucor_errors;
+	__u64 pri_rarb_sriovt_cor_errors;
+	__u64 pri_rarb_sriovt_ucor_errors;
+	__u64 pti_tarb_pkts;
+	__u64 pti_tarb_pkt_discards;
+	__u64 pti_tarb_rarb_ca_pkts;
+	__u64 pti_tarb_mwr_pkts;
+	__u64 pti_tarb_mrd_pkts;
+	__u64 pti_tarb_flush_pkts;
+	__u64 pti_tarb_irq_pkts;
+	__u64 pti_tarb_translation_pkts;
+	__u64 pti_tarb_inv_rsp_pkts;
+	__u64 pti_tarb_pg_req_pkts;
+	__u64 pti_tarb_amo_pkts;
+	__u64 pti_tarb_fetching_amo_pkts;
+	__u64 pti_tarb_hdr_cor_errors;
+	__u64 pti_tarb_hdr_ucor_errors;
+	__u64 pti_tarb_data_cor_errors;
+	__u64 pti_tarb_data_ucor_error;
+	__u64 pti_tarb_acxt_cor_errors;
+	__u64 pti_tarb_acxt_ucor_errors;
+	__u64 pti_tarb_reserved[5];
+	__u64 dmac_axi_rd_requests;
+	__u64 dmac_axi_rd_rsp_decerrs;
+	__u64 dmac_axi_rd_rsp_slverrs;
+	__u64 dmac_axi_rd_rsp_parerrs;
+	__u64 dmac_payload_mwr_tlps;
+	__u64 dmac_ce_mwr_tlps;
+	__u64 dmac_irqs;
+	__u64 dmac_desc_cor_errors;
+	__u64 dmac_desc_ucor_errors;
+};
+
+struct c_pi_ipd_cntrs {
+	__u64 pri_rtrgt_tlps;
+	__u64 pri_rtrgt_mwr_tlps;
+	__u64 pri_rtrgt_mrd_tlps;
+	__u64 pri_rtrgt_msg_tlps;
+	__u64 pri_rtrgt_msgd_tlps;
+	__u64 pri_rtrgt_tlps_aborted;
+	__u64 pri_rtrgt_blocked_on_mb;
+	__u64 pri_rtrgt_blocked_on_rarb;
+	__u64 pri_rtrgt_hdr_parity_errors;
+	__u64 pri_rtrgt_data_parity_errors;
+	__u64 pri_rbyp_tlps;
+	__u64 pri_rbyp_tlps_aborted;
+	__u64 pri_rbyp_hdr_parity_errors;
+	__u64 pri_rbyp_data_parity_errors;
+	__u64 pti_tarb_xali_posted_tlps;
+	__u64 pti_tarb_xali_non_posted_tlps;
+	__u64 pti_msixc_xali_posted_tlps;
+	__u64 pti_dbg_xali_posted_tlps;
+	__u64 pti_dbg_xali_non_posted_tlps;
+	__u64 pti_dmac_xali_posted_tlps;
+	__u64 pti_tarb_p_fifo_cor_errors;
+	__u64 pti_tarb_p_fifo_ucor_errors;
+	__u64 pti_tarb_np_fifo_cor_errors;
+	__u64 pti_tarb_np_fifo_ucor_errors;
+	__u64 pti_tarb_blocked_on_ph_crd;
+	__u64 pti_tarb_blocked_on_pd_crd;
+	__u64 pti_tarb_blocked_on_nph_crd;
+	__u64 pti_tarb_blocked_on_npd_crd;
+	__u64 pti_tarb_blocked_on_tag;
+	__u64 pti_dmac_blocked_on_ph_crd;
+	__u64 pti_dmac_blocked_on_pd_crd;
+	__u64 pti_msixc_blocked_on_ph_crd;
+	__u64 pti_msixc_blocked_on_pd_crd;
+	__u64 pti_dbg_blocked_on_ph_crd;
+	__u64 pti_dbg_blocked_on_pd_crd;
+	__u64 pti_dbg_blocked_on_nph_crd;
+	__u64 pti_dbg_blocked_on_tag;
+	__u64 pti_tarb_cmpl_to;
+	__u64 pti_tarb_cmpl_to_fifo_cor_errors;
+	__u64 pti_tarb_cmpl_to_fifo_ucor_errors;
+	__u64 msixc_oob_irqs_sent;
+	__u64 msixc_oob_legacy_irqs_sent;
+	__u64 msixc_oob_irqs_discarded;
+	__u64 msixc_oob_irq_pbas;
+	__u64 msixc_ib_irqs_sent;
+	__u64 msixc_ib_legacy_irqs_sent;
+	__u64 msixc_ib_irqs_discarded;
+	__u64 msixc_ib_irq_pbas;
+	__u64 msixc_pba_cor_errors;
+	__u64 msixc_pba_ucor_errors;
+	__u64 msixc_table_cor_errors;
+	__u64 msixc_table_ucor_errors;
+	__u64 pti_msixc_fifo_cor_errors;
+	__u64 pti_msixc_fifo_ucor_errors;
+	__u64 msixc_pti_fifo_cor_errors;
+	__u64 msixc_pti_fifo_ucor_errors;
+	__u64 dmac_p_fifo_cor_errors;
+	__u64 dmac_p_fifo_ucor_errors;
+	__u64 dbic_dbi_requests;
+	__u64 dbic_dbi_acks;
+	__u64 ipd_trigger_events[2];
+	__u64 ipd_cnts_reserved[66];
+};
+
+struct c_mb_cntrs {
+	__u64 crmc_ring_sbe[3];
+	__u64 crmc_ring_mbe[3];
+	__u64 crmc_wr_error[3];
+	__u64 crmc_axi_wr_requests[3];
+	__u64 crmc_ring_wr_requests[3];
+	__u64 crmc_rd_error[3];
+	__u64 crmc_axi_rd_requests[3];
+	__u64 crmc_ring_rd_requests[3];
+	__u64 jai_axi_wr_requests;
+	__u64 jai_axi_rd_requests;
+	__u64 mb_lsa0_trigger_events[2];
+	__u64 ixe_lsa0_trigger_events[2];
+	__u64 cq_lsa0_trigger_events[2];
+	__u64 ee_lsa0_trigger_events[2];
+	__u64 mb_lsa1_trigger_events[2];
+	__u64 ixe_lsa1_trigger_events[2];
+	__u64 cq_lsa1_trigger_events[2];
+	__u64 ee_lsa1_trigger_events[2];
+	__u64 cmc_axi_wr_requests[4];
+	__u64 cmc_axi_rd_requests[4];
+	__u64 mb_todo_cntrs[14];
+};
+
+#ifdef __LITTLE_ENDIAN
+struct c_port_fab_hdr {
+	__u8 ihl            :  4;
+	__u8 ver            :  4;
+	__u8 ecn            :  2;
+	__u8 dscp           :  6;
+	__u16 tl;
+	__u16 vni;
+	__u8 spt_idx_hi     :  6;
+	__u8:  2;
+	__u8 try_           :  3;
+	__u8 spt_idx_low    :  5;
+	__u8 ttl;
+	__u8 protocol;
+	__u16 hdr_chksum;
+	union c_fab_addr sfa;
+	union c_fab_addr dfa;
+} __attribute__((packed));
+#else
+struct c_port_fab_hdr {
+	__u8 ver            :  4;
+	__u8 ihl            :  4;
+	__u8 dscp           :  6;
+	__u8 ecn            :  2;
+	__u16 tl;
+	__u16 vni;
+	__u8:  2;
+	__u16 spt_idx       : 11;
+	__u8 try_           :  3;
+	__u8 ttl;
+	__u8 protocol;
+	__u16 hdr_chksum;
+	union c_fab_addr sfa;
+	union c_fab_addr dfa;
+} __attribute__((packed));
+#endif
+
+static inline void c_port_fab_hdr_set_tl(struct c_port_fab_hdr *p, __u16 tl)
+{
+	p->tl = cpu_to_be16(tl);
+}
+
+static inline __u16 c_port_fab_hdr_get_tl(const struct c_port_fab_hdr *p)
+{
+	return be16_to_cpu(p->tl);
+}
+
+static inline void c_port_fab_hdr_set_vni(struct c_port_fab_hdr *p, __u16 vni)
+{
+	p->vni = cpu_to_be16(vni);
+}
+
+static inline __u16 c_port_fab_hdr_get_vni(const struct c_port_fab_hdr *p)
+{
+	return be16_to_cpu(p->vni);
+}
+
+static inline void c_port_fab_hdr_set_spt_idx(struct c_port_fab_hdr *p, __u16 spt_idx)
+{
+#ifdef __LITTLE_ENDIAN
+	p->spt_idx_low = spt_idx;
+	p->spt_idx_hi = spt_idx >> 5;
+#else
+	p->spt_idx = spt_idx;
+#endif
+}
+
+static inline __u16 c_port_fab_hdr_get_spt_idx(const struct c_port_fab_hdr *p)
+{
+#ifdef __LITTLE_ENDIAN
+	return (__u16)p->spt_idx_low | (__u16)p->spt_idx_hi << 5;
+#else
+	return p->spt_idx;
+#endif
+}
+
+static inline void c_port_fab_hdr_set_hdr_chksum(struct c_port_fab_hdr *p, __u16 hdr_chksum)
+{
+	p->hdr_chksum = cpu_to_be16(hdr_chksum);
+}
+
+static inline __u16 c_port_fab_hdr_get_hdr_chksum(const struct c_port_fab_hdr *p)
+{
+	return be16_to_cpu(p->hdr_chksum);
+}
+
+#ifdef __LITTLE_ENDIAN
+struct c_port_fab_vs_hdr {
+	__u8 dscp_hi        :  4;
+	__u8 ver            :  4;
+	__u8:  2;
+	__u8:  4;
+	__u8 dscp_low       :  2;
+	__u8 spt_idx_hi;
+	__u8:  2;
+	__u8 try_           :  3;
+	__u8 spt_idx_low    :  3;
+	__u16 vni;
+	union c_fab_addr sfa;
+	union c_fab_addr dfa;
+} __attribute__((packed));
+#else
+struct c_port_fab_vs_hdr {
+	__u8 ver            :  4;
+	__u16 dscp          :  6;
+	__u8:  4;
+	__u8:  2;
+	__u16 spt_idx       : 11;
+	__u8 try_           :  3;
+	__u8:  2;
+	__u16 vni;
+	union c_fab_addr sfa;
+	union c_fab_addr dfa;
+} __attribute__((packed));
+#endif
+
+static inline void c_port_fab_vs_hdr_set_dscp(struct c_port_fab_vs_hdr *p, __u8 dscp)
+{
+#ifdef __LITTLE_ENDIAN
+	p->dscp_low = dscp;
+	p->dscp_hi = dscp >> 2;
+#else
+	p->dscp = dscp;
+#endif
+}
+
+static inline __u8 c_port_fab_vs_hdr_get_dscp(const struct c_port_fab_vs_hdr *p)
+{
+#ifdef __LITTLE_ENDIAN
+	return (__u8)p->dscp_low | (__u8)p->dscp_hi << 2;
+#else
+	return p->dscp;
+#endif
+}
+
+static inline void c_port_fab_vs_hdr_set_spt_idx(struct c_port_fab_vs_hdr *p, __u16 spt_idx)
+{
+#ifdef __LITTLE_ENDIAN
+	p->spt_idx_low = spt_idx;
+	p->spt_idx_hi = spt_idx >> 3;
+#else
+	p->spt_idx = spt_idx;
+#endif
+}
+
+static inline __u16 c_port_fab_vs_hdr_get_spt_idx(const struct c_port_fab_vs_hdr *p)
+{
+#ifdef __LITTLE_ENDIAN
+	return (__u16)p->spt_idx_low | (__u16)p->spt_idx_hi << 3;
+#else
+	return p->spt_idx;
+#endif
+}
+
+static inline void c_port_fab_vs_hdr_set_vni(struct c_port_fab_vs_hdr *p, __u16 vni)
+{
+	p->vni = cpu_to_be16(vni);
+}
+
+static inline __u16 c_port_fab_vs_hdr_get_vni(const struct c_port_fab_vs_hdr *p)
+{
+	return be16_to_cpu(p->vni);
+}
+
+#ifdef __LITTLE_ENDIAN
+struct c_port_unrestricted_hdr {
+	__u8 opcode              :  4;
+	__u8 ver_pkt_type        :  3;
+	__u8 req_not_rsp         :  1;
+	__u8 index_ext           :  5;
+	__u8 pktid_ext           :  2;
+	__u8 flush               :  1;
+	__u64 remote_offset      : 56;
+	__u8 msg_id;
+	__u8 seq_num_hi;
+	__u8 clr_seq_num_hi      :  4;
+	__u8 seq_num_low         :  4;
+	__u8 clr_seq_num_low;
+	__u8 sct_idx_hi;
+	__u8 rendezvous_id_hi    :  4;
+	__u8 sct_idx_low         :  4;
+	__u8:  2;
+	__u8 use_offset_for_get  :  1;
+	__u8 src_error           :  1;
+	__u8 rendezvous_id_low   :  4;
+	__u32 request_len;
+	__u32 initiator;
+	__u64 match_bits;
+	__u64 header_data;
+	__u8 eg_len_hi;
+	__u8 eg_len_mid;
+	__u8:  4;
+	__u8 eg_len_low          :  4;
+} __attribute__((packed));
+#else
+struct c_port_unrestricted_hdr {
+	__u8 req_not_rsp         :  1;
+	__u8 ver_pkt_type        :  3;
+	__u8 opcode              :  4;
+	__u8 flush               :  1;
+	__u8 pktid_ext           :  2;
+	__u8 index_ext           :  5;
+	__u64 remote_offset      : 56;
+	__u8 msg_id;
+	__u16 seq_num            : 12;
+	__u16 clr_seq_num        : 12;
+	__u16 sct_idx            : 12;
+	__u16 rendezvous_id      :  8;
+	__u8 src_error           :  1;
+	__u8 use_offset_for_get  :  1;
+	__u8:  2;
+	__u32 request_len;
+	__u32 initiator;
+	__u64 match_bits;
+	__u64 header_data;
+	__u32 eg_len             : 20;
+	__u8:  4;
+} __attribute__((packed));
+#endif
+
+static inline void c_port_unrestricted_hdr_set_remote_offset(struct c_port_unrestricted_hdr *p, __u64 remote_offset)
+{
+	p->remote_offset = cpu_to_be64(remote_offset << 8);
+}
+
+static inline __u64 c_port_unrestricted_hdr_get_remote_offset(const struct c_port_unrestricted_hdr *p)
+{
+	return be64_to_cpu(p->remote_offset) >> 8;
+}
+
+static inline void c_port_unrestricted_hdr_set_seq_num(struct c_port_unrestricted_hdr *p, __u16 seq_num)
+{
+#ifdef __LITTLE_ENDIAN
+	p->seq_num_low = seq_num;
+	p->seq_num_hi = seq_num >> 4;
+#else
+	p->seq_num = seq_num;
+#endif
+}
+
+static inline __u16 c_port_unrestricted_hdr_get_seq_num(const struct c_port_unrestricted_hdr *p)
+{
+#ifdef __LITTLE_ENDIAN
+	return (__u16)p->seq_num_low | (__u16)p->seq_num_hi << 4;
+#else
+	return p->seq_num;
+#endif
+}
+
+static inline void c_port_unrestricted_hdr_set_clr_seq_num(struct c_port_unrestricted_hdr *p, __u16 clr_seq_num)
+{
+#ifdef __LITTLE_ENDIAN
+	p->clr_seq_num_low = clr_seq_num;
+	p->clr_seq_num_hi = clr_seq_num >> 8;
+#else
+	p->clr_seq_num = clr_seq_num;
+#endif
+}
+
+static inline __u16 c_port_unrestricted_hdr_get_clr_seq_num(const struct c_port_unrestricted_hdr *p)
+{
+#ifdef __LITTLE_ENDIAN
+	return (__u16)p->clr_seq_num_low | (__u16)p->clr_seq_num_hi << 8;
+#else
+	return p->clr_seq_num;
+#endif
+}
+
+static inline void c_port_unrestricted_hdr_set_sct_idx(struct c_port_unrestricted_hdr *p, __u16 sct_idx)
+{
+#ifdef __LITTLE_ENDIAN
+	p->sct_idx_low = sct_idx;
+	p->sct_idx_hi = sct_idx >> 4;
+#else
+	p->sct_idx = sct_idx;
+#endif
+}
+
+static inline __u16 c_port_unrestricted_hdr_get_sct_idx(const struct c_port_unrestricted_hdr *p)
+{
+#ifdef __LITTLE_ENDIAN
+	return (__u16)p->sct_idx_low | (__u16)p->sct_idx_hi << 4;
+#else
+	return p->sct_idx;
+#endif
+}
+
+static inline void c_port_unrestricted_hdr_set_rendezvous_id(struct c_port_unrestricted_hdr *p, __u8 rendezvous_id)
+{
+#ifdef __LITTLE_ENDIAN
+	p->rendezvous_id_low = rendezvous_id;
+	p->rendezvous_id_hi = rendezvous_id >> 4;
+#else
+	p->rendezvous_id = rendezvous_id;
+#endif
+}
+
+static inline __u8 c_port_unrestricted_hdr_get_rendezvous_id(const struct c_port_unrestricted_hdr *p)
+{
+#ifdef __LITTLE_ENDIAN
+	return (__u8)p->rendezvous_id_low | (__u8)p->rendezvous_id_hi << 4;
+#else
+	return p->rendezvous_id;
+#endif
+}
+
+static inline void c_port_unrestricted_hdr_set_request_len(struct c_port_unrestricted_hdr *p, __u32 request_len)
+{
+	p->request_len = cpu_to_be32(request_len);
+}
+
+static inline __u32 c_port_unrestricted_hdr_get_request_len(const struct c_port_unrestricted_hdr *p)
+{
+	return be32_to_cpu(p->request_len);
+}
+
+static inline void c_port_unrestricted_hdr_set_initiator(struct c_port_unrestricted_hdr *p, __u32 initiator)
+{
+	p->initiator = cpu_to_be32(initiator);
+}
+
+static inline __u32 c_port_unrestricted_hdr_get_initiator(const struct c_port_unrestricted_hdr *p)
+{
+	return be32_to_cpu(p->initiator);
+}
+
+static inline void c_port_unrestricted_hdr_set_match_bits(struct c_port_unrestricted_hdr *p, __u64 match_bits)
+{
+	p->match_bits = cpu_to_be64(match_bits);
+}
+
+static inline __u64 c_port_unrestricted_hdr_get_match_bits(const struct c_port_unrestricted_hdr *p)
+{
+	return be64_to_cpu(p->match_bits);
+}
+
+static inline void c_port_unrestricted_hdr_set_header_data(struct c_port_unrestricted_hdr *p, __u64 header_data)
+{
+	p->header_data = cpu_to_be64(header_data);
+}
+
+static inline __u64 c_port_unrestricted_hdr_get_header_data(const struct c_port_unrestricted_hdr *p)
+{
+	return be64_to_cpu(p->header_data);
+}
+
+static inline void c_port_unrestricted_hdr_set_eg_len(struct c_port_unrestricted_hdr *p, __u32 eg_len)
+{
+#ifdef __LITTLE_ENDIAN
+	p->eg_len_low = eg_len;
+	p->eg_len_mid = eg_len >> 4;
+	p->eg_len_hi = eg_len >> 12;
+#else
+	p->eg_len = eg_len;
+#endif
+}
+
+static inline __u32 c_port_unrestricted_hdr_get_eg_len(const struct c_port_unrestricted_hdr *p)
+{
+#ifdef __LITTLE_ENDIAN
+	return (__u32)p->eg_len_low | (__u32)p->eg_len_mid << 4 | (__u32)p->eg_len_hi << 12;
+#else
+	return p->eg_len;
+#endif
+}
+
+#ifdef __LITTLE_ENDIAN
+struct c_port_small_msg_hdr {
+	__u8 opcode            :  4;
+	__u8 ver_pkt_type      :  3;
+	__u8 req_not_rsp       :  1;
+	__u8 index_ext         :  5;
+	__u8 pktid_ext         :  2;
+	__u8 flush             :  1;
+	__u64 header_data      : 64;
+	__u8 seq_num_hi;
+	__u8 clr_seq_num_hi    :  4;
+	__u8 seq_num_low       :  4;
+	__u8 clr_seq_num_low;
+	__u8 sct_idx_hi;
+	__u8 request_len_hi    :  4;
+	__u8 sct_idx_low       :  4;
+	__u8 request_len_low;
+	__u32 initiator;
+	__u64 match_bits       : 64;
+	__u8:  7;
+	__u8 src_error         :  1;
+} __attribute__((packed));
+#else
+struct c_port_small_msg_hdr {
+	__u8 req_not_rsp   :  1;
+	__u8 ver_pkt_type  :  3;
+	__u8 opcode        :  4;
+	__u8 flush         :  1;
+	__u8 pktid_ext     :  2;
+	__u8 index_ext     :  5;
+	__u64 header_data  : 64;
+	__u16 seq_num      : 12;
+	__u16 clr_seq_num  : 12;
+	__u16 sct_idx      : 12;
+	__u16 request_len  : 12;
+	__u32 initiator;
+	__u64 match_bits   : 64;
+	__u8 src_error     :  1;
+	__u8:  7;
+} __attribute__((packed));
+#endif
+
+static inline void c_port_small_msg_hdr_set_header_data(struct c_port_small_msg_hdr *p, __u64 header_data)
+{
+	p->header_data = cpu_to_be64(header_data);
+}
+
+static inline __u64 c_port_small_msg_hdr_get_header_data(const struct c_port_small_msg_hdr *p)
+{
+	return be64_to_cpu(p->header_data);
+}
+
+static inline void c_port_small_msg_hdr_set_seq_num(struct c_port_small_msg_hdr *p, __u16 seq_num)
+{
+#ifdef __LITTLE_ENDIAN
+	p->seq_num_low = seq_num;
+	p->seq_num_hi = seq_num >> 4;
+#else
+	p->seq_num = seq_num;
+#endif
+}
+
+static inline __u16 c_port_small_msg_hdr_get_seq_num(const struct c_port_small_msg_hdr *p)
+{
+#ifdef __LITTLE_ENDIAN
+	return (__u16)p->seq_num_low | (__u16)p->seq_num_hi << 4;
+#else
+	return p->seq_num;
+#endif
+}
+
+static inline void c_port_small_msg_hdr_set_clr_seq_num(struct c_port_small_msg_hdr *p, __u16 clr_seq_num)
+{
+#ifdef __LITTLE_ENDIAN
+	p->clr_seq_num_low = clr_seq_num;
+	p->clr_seq_num_hi = clr_seq_num >> 8;
+#else
+	p->clr_seq_num = clr_seq_num;
+#endif
+}
+
+static inline __u16 c_port_small_msg_hdr_get_clr_seq_num(const struct c_port_small_msg_hdr *p)
+{
+#ifdef __LITTLE_ENDIAN
+	return (__u16)p->clr_seq_num_low | (__u16)p->clr_seq_num_hi << 8;
+#else
+	return p->clr_seq_num;
+#endif
+}
+
+static inline void c_port_small_msg_hdr_set_sct_idx(struct c_port_small_msg_hdr *p, __u16 sct_idx)
+{
+#ifdef __LITTLE_ENDIAN
+	p->sct_idx_low = sct_idx;
+	p->sct_idx_hi = sct_idx >> 4;
+#else
+	p->sct_idx = sct_idx;
+#endif
+}
+
+static inline __u16 c_port_small_msg_hdr_get_sct_idx(const struct c_port_small_msg_hdr *p)
+{
+#ifdef __LITTLE_ENDIAN
+	return (__u16)p->sct_idx_low | (__u16)p->sct_idx_hi << 4;
+#else
+	return p->sct_idx;
+#endif
+}
+
+static inline void c_port_small_msg_hdr_set_request_len(struct c_port_small_msg_hdr *p, __u16 request_len)
+{
+#ifdef __LITTLE_ENDIAN
+	p->request_len_low = request_len;
+	p->request_len_hi = request_len >> 8;
+#else
+	p->request_len = request_len;
+#endif
+}
+
+static inline __u16 c_port_small_msg_hdr_get_request_len(const struct c_port_small_msg_hdr *p)
+{
+#ifdef __LITTLE_ENDIAN
+	return (__u16)p->request_len_low | (__u16)p->request_len_hi << 8;
+#else
+	return p->request_len;
+#endif
+}
+
+static inline void c_port_small_msg_hdr_set_initiator(struct c_port_small_msg_hdr *p, __u32 initiator)
+{
+	p->initiator = cpu_to_be32(initiator);
+}
+
+static inline __u32 c_port_small_msg_hdr_get_initiator(const struct c_port_small_msg_hdr *p)
+{
+	return be32_to_cpu(p->initiator);
+}
+
+static inline void c_port_small_msg_hdr_set_match_bits(struct c_port_small_msg_hdr *p, __u64 match_bits)
+{
+	p->match_bits = cpu_to_be64(match_bits);
+}
+
+static inline __u64 c_port_small_msg_hdr_get_match_bits(const struct c_port_small_msg_hdr *p)
+{
+	return be64_to_cpu(p->match_bits);
+}
+
+#ifdef __LITTLE_ENDIAN
+struct c_port_continuation_hdr {
+	__u8 opcode             :  4;
+	__u8 ver_pkt_type       :  3;
+	__u8 req_not_rsp        :  1;
+	__u8:  2;
+	__u8 src_error          :  1;
+	__u8 pkt_ordered        :  1;
+	__u8 eom                :  1;
+	__u8 pktid_ext          :  2;
+	__u8 flush              :  1;
+	__u32 offset            : 32;
+	__u8 msg_id;
+	__u8 seq_num_hi;
+	__u8 clr_seq_num_hi     :  4;
+	__u8 seq_num_low        :  4;
+	__u8 clr_seq_num_low;
+	__u8 sct_idx_hi;
+	__u8 pkt_xfer_len_hi    :  4;
+	__u8 sct_idx_low        :  4;
+	__u8 pkt_xfer_len_low;
+} __attribute__((packed));
+#else
+struct c_port_continuation_hdr {
+	__u8 req_not_rsp    :  1;
+	__u8 ver_pkt_type   :  3;
+	__u8 opcode         :  4;
+	__u8 flush          :  1;
+	__u8 pktid_ext      :  2;
+	__u8 eom            :  1;
+	__u8 pkt_ordered    :  1;
+	__u8 src_error      :  1;
+	__u8:  2;
+	__u32 offset        : 32;
+	__u8 msg_id;
+	__u16 seq_num       : 12;
+	__u16 clr_seq_num   : 12;
+	__u16 sct_idx       : 12;
+	__u16 pkt_xfer_len  : 12;
+} __attribute__((packed));
+#endif
+
+static inline void c_port_continuation_hdr_set_offset(struct c_port_continuation_hdr *p, __u32 offset)
+{
+	p->offset = cpu_to_be32(offset);
+}
+
+static inline __u32 c_port_continuation_hdr_get_offset(const struct c_port_continuation_hdr *p)
+{
+	return be32_to_cpu(p->offset);
+}
+
+static inline void c_port_continuation_hdr_set_seq_num(struct c_port_continuation_hdr *p, __u16 seq_num)
+{
+#ifdef __LITTLE_ENDIAN
+	p->seq_num_low = seq_num;
+	p->seq_num_hi = seq_num >> 4;
+#else
+	p->seq_num = seq_num;
+#endif
+}
+
+static inline __u16 c_port_continuation_hdr_get_seq_num(const struct c_port_continuation_hdr *p)
+{
+#ifdef __LITTLE_ENDIAN
+	return (__u16)p->seq_num_low | (__u16)p->seq_num_hi << 4;
+#else
+	return p->seq_num;
+#endif
+}
+
+static inline void c_port_continuation_hdr_set_clr_seq_num(struct c_port_continuation_hdr *p, __u16 clr_seq_num)
+{
+#ifdef __LITTLE_ENDIAN
+	p->clr_seq_num_low = clr_seq_num;
+	p->clr_seq_num_hi = clr_seq_num >> 8;
+#else
+	p->clr_seq_num = clr_seq_num;
+#endif
+}
+
+static inline __u16 c_port_continuation_hdr_get_clr_seq_num(const struct c_port_continuation_hdr *p)
+{
+#ifdef __LITTLE_ENDIAN
+	return (__u16)p->clr_seq_num_low | (__u16)p->clr_seq_num_hi << 8;
+#else
+	return p->clr_seq_num;
+#endif
+}
+
+static inline void c_port_continuation_hdr_set_sct_idx(struct c_port_continuation_hdr *p, __u16 sct_idx)
+{
+#ifdef __LITTLE_ENDIAN
+	p->sct_idx_low = sct_idx;
+	p->sct_idx_hi = sct_idx >> 4;
+#else
+	p->sct_idx = sct_idx;
+#endif
+}
+
+static inline __u16 c_port_continuation_hdr_get_sct_idx(const struct c_port_continuation_hdr *p)
+{
+#ifdef __LITTLE_ENDIAN
+	return (__u16)p->sct_idx_low | (__u16)p->sct_idx_hi << 4;
+#else
+	return p->sct_idx;
+#endif
+}
+
+static inline void c_port_continuation_hdr_set_pkt_xfer_len(struct c_port_continuation_hdr *p, __u16 pkt_xfer_len)
+{
+#ifdef __LITTLE_ENDIAN
+	p->pkt_xfer_len_low = pkt_xfer_len;
+	p->pkt_xfer_len_hi = pkt_xfer_len >> 8;
+#else
+	p->pkt_xfer_len = pkt_xfer_len;
+#endif
+}
+
+static inline __u16 c_port_continuation_hdr_get_pkt_xfer_len(const struct c_port_continuation_hdr *p)
+{
+#ifdef __LITTLE_ENDIAN
+	return (__u16)p->pkt_xfer_len_low | (__u16)p->pkt_xfer_len_hi << 8;
+#else
+	return p->pkt_xfer_len;
+#endif
+}
+
+#ifdef __LITTLE_ENDIAN
+struct c_port_restricted_hdr {
+	__u8 opcode            :  4;
+	__u8 ver_pkt_type      :  3;
+	__u8 req_not_rsp       :  1;
+	__u8 index_ext         :  5;
+	__u8 pktid_ext         :  2;
+	__u8 flush             :  1;
+	__u64 remote_offset    : 56;
+	__u8 request_len_hi    :  4;
+	__u8 src_error         :  1;
+	__u8:  3;
+	__u8 request_len_low;
+} __attribute__((packed));
+#else
+struct c_port_restricted_hdr {
+	__u8 req_not_rsp     :  1;
+	__u8 ver_pkt_type    :  3;
+	__u8 opcode          :  4;
+	__u8 flush           :  1;
+	__u8 pktid_ext       :  2;
+	__u8 index_ext       :  5;
+	__u64 remote_offset  : 56;
+	__u8:  3;
+	__u8 src_error       :  1;
+	__u16 request_len    : 12;
+} __attribute__((packed));
+#endif
+
+static inline void c_port_restricted_hdr_set_remote_offset(struct c_port_restricted_hdr *p, __u64 remote_offset)
+{
+	p->remote_offset = cpu_to_be64(remote_offset << 8);
+}
+
+static inline __u64 c_port_restricted_hdr_get_remote_offset(const struct c_port_restricted_hdr *p)
+{
+	return be64_to_cpu(p->remote_offset) >> 8;
+}
+
+static inline void c_port_restricted_hdr_set_request_len(struct c_port_restricted_hdr *p, __u16 request_len)
+{
+#ifdef __LITTLE_ENDIAN
+	p->request_len_low = request_len;
+	p->request_len_hi = request_len >> 8;
+#else
+	p->request_len = request_len;
+#endif
+}
+
+static inline __u16 c_port_restricted_hdr_get_request_len(const struct c_port_restricted_hdr *p)
+{
+#ifdef __LITTLE_ENDIAN
+	return (__u16)p->request_len_low | (__u16)p->request_len_hi << 8;
+#else
+	return p->request_len;
+#endif
+}
+
+#ifdef __LITTLE_ENDIAN
+struct c_port_amo_payload {
+	__u8 amo_op          :  4;
+	__u8:  4;
+	__u8 amo_type        :  4;
+	__u8:  4;
+	__u8 cswap_op        :  3;
+	__u8:  5;
+	__u64: 40;
+	__u64 op1_word1_le;
+	__u64 op1_word2_le;
+	__u64 op2_word1_le;
+	__u64 op2_word2_le;
+} __attribute__((packed));
+#else
+struct c_port_amo_payload {
+	__u8:  4;
+	__u8 amo_op          :  4;
+	__u8:  4;
+	__u8 amo_type        :  4;
+	__u8:  5;
+	__u8 cswap_op        :  3;
+	__u64: 40;
+	__u64 op1_word1_le;
+	__u64 op1_word2_le;
+	__u64 op2_word1_le;
+	__u64 op2_word2_le;
+} __attribute__((packed));
+#endif
+
+static inline void c_port_amo_payload_set_op1_word1_le(struct c_port_amo_payload *p, __u64 op1_word1_le)
+{
+	p->op1_word1_le = cpu_to_be64(op1_word1_le);
+}
+
+static inline __u64 c_port_amo_payload_get_op1_word1_le(const struct c_port_amo_payload *p)
+{
+	return be64_to_cpu(p->op1_word1_le);
+}
+
+static inline void c_port_amo_payload_set_op1_word2_le(struct c_port_amo_payload *p, __u64 op1_word2_le)
+{
+	p->op1_word2_le = cpu_to_be64(op1_word2_le);
+}
+
+static inline __u64 c_port_amo_payload_get_op1_word2_le(const struct c_port_amo_payload *p)
+{
+	return be64_to_cpu(p->op1_word2_le);
+}
+
+static inline void c_port_amo_payload_set_op2_word1_le(struct c_port_amo_payload *p, __u64 op2_word1_le)
+{
+	p->op2_word1_le = cpu_to_be64(op2_word1_le);
+}
+
+static inline __u64 c_port_amo_payload_get_op2_word1_le(const struct c_port_amo_payload *p)
+{
+	return be64_to_cpu(p->op2_word1_le);
+}
+
+static inline void c_port_amo_payload_set_op2_word2_le(struct c_port_amo_payload *p, __u64 op2_word2_le)
+{
+	p->op2_word2_le = cpu_to_be64(op2_word2_le);
+}
+
+static inline __u64 c_port_amo_payload_get_op2_word2_le(const struct c_port_amo_payload *p)
+{
+	return be64_to_cpu(p->op2_word2_le);
+}
+
+struct c_hni_cntrs {
+	__u64 cor_ecc_err_cntr;
+	__u64 ucor_ecc_err_cntr;
+	__u64 tx_stall_llr;
+	__u64 cntr0;
+	__u64 rx_stall_ixe_fifo;
+	__u64 cntr1[3];
+	__u64 rx_stall_ixe_pktbuf[8];
+	__u64 pfc_fifo_oflw_cntr[8];
+	__u64 discard_cntr[8];
+	__u64 tx_ok_ieee;
+	__u64 tx_ok_opt;
+	__u64 tx_poisoned_ieee;
+	__u64 tx_poisoned_opt;
+	__u64 tx_ok_broadcast;
+	__u64 tx_ok_multicast;
+	__u64 tx_ok_tagged;
+	__u64 tx_ok_27;
+	__u64 tx_ok_35;
+	__u64 tx_ok_36_to_63;
+	__u64 tx_ok_64;
+	__u64 tx_ok_65_to_127;
+	__u64 tx_ok_128_to_255;
+	__u64 tx_ok_256_to_511;
+	__u64 tx_ok_512_to_1023;
+	__u64 tx_ok_1024_to_2047;
+	__u64 tx_ok_2048_to_4095;
+	__u64 tx_ok_4096_to_8191;
+	__u64 tx_ok_8192_to_max;
+	__u64 rx_ok_ieee;
+	__u64 rx_ok_opt;
+	__u64 rx_bad_ieee;
+	__u64 rx_bad_opt;
+	__u64 rx_ok_broadcast;
+	__u64 rx_ok_multicast;
+	__u64 rx_ok_mac_control;
+	__u64 rx_ok_bad_op_code;
+	__u64 rx_ok_flow_control;
+	__u64 rx_ok_tagged;
+	__u64 rx_ok_len_type_error;
+	__u64 rx_ok_too_long;
+	__u64 rx_ok_undersize;
+	__u64 rx_fragment;
+	__u64 rx_jabber;
+	__u64 rx_ok_27;
+	__u64 rx_ok_35;
+	__u64 rx_ok_36_to_63;
+	__u64 rx_ok_64;
+	__u64 rx_ok_65_to_127;
+	__u64 rx_ok_128_to_255;
+	__u64 rx_ok_256_to_511;
+	__u64 rx_ok_512_to_1023;
+	__u64 rx_ok_1024_to_2047;
+	__u64 rx_ok_2048_to_4095;
+	__u64 rx_ok_4096_to_8191;
+	__u64 rx_ok_8192_to_max;
+	__u64 hrp_ack;
+	__u64 hrp_resp;
+	__u64 fgfc_port;
+	__u64 fgfc_l2;
+	__u64 fgfc_ipv4;
+	__u64 fgfc_ipv6;
+	__u64 fgfc_match;
+	__u64 fgfc_event_xon;
+	__u64 fgfc_event_xoff;
+	__u64 fgfc_discard;
+	__u64 pause_recv[8];
+	__u64 pause_xoff_sent[8];
+	__u64 rx_paused[8];
+	__u64 tx_paused[8];
+	__u64 rx_paused_std;
+	__u64 pause_sent;
+	__u64 pause_refresh;
+	__u64 cntr2;
+	__u64 tx_std_padded;
+	__u64 tx_opt_padded;
+	__u64 tx_std_size_err;
+	__u64 tx_opt_size_err;
+	__u64 pkts_sent_by_tc[8];
+	__u64 pkts_recv_by_tc[8];
+	__u64 multicast_pkts_sent_by_tc[8];
+	__u64 multicast_pkts_recv_by_tc[8];
+};
+
+struct c1_hni_pcs_cntrs {
+	__u64 pml_mbe_error_cnt;
+	__u64 pml_sbe_error_cnt;
+	__u64 corrected_cw;
+	__u64 uncorrected_cw;
+	__u64 good_cw;
+	__u64 fecl_errors[8];
+};
+
+struct c2_hni_pcs_cntrs {
+	__u64 pml_mbe_error_cnt;
+	__u64 pml_sbe_error_cnt;
+	__u64 corrected_cw;
+	__u64 uncorrected_cw;
+	__u64 good_cw;
+	__u64 fecl_errors[16];
+	__u64 corrected_cw_bin[15];
+};
+
+struct c1_hni_mac_cntrs {
+	__u64 rx_illegal_size;
+	__u64 rx_fragment;
+	__u64 rx_preamble_error;
+};
+
+struct c2_hni_mac_cntrs {
+	__u64 rx_illegal_size;
+	__u64 rx_fragment;
+	__u64 rx_preamble_error;
+	__u64 tx_ifg_adjustment_sync;
+};
+
+struct c1_hni_llr_cntrs {
+	__u64 tx_loop_time_req_ctl_fr;
+	__u64 tx_loop_time_rsp_ctl_fr;
+	__u64 tx_init_ctl_os;
+	__u64 tx_init_echo_ctl_os;
+	__u64 tx_ack_ctl_os;
+	__u64 tx_nack_ctl_os;
+	__u64 tx_discard;
+	__u64 tx_ok_lossy;
+	__u64 tx_ok_lossless;
+	__u64 tx_ok_lossless_rpt;
+	__u64 tx_poisoned_lossy;
+	__u64 tx_poisoned_lossless;
+	__u64 tx_poisoned_lossless_rpt;
+	__u64 tx_ok_bypass;
+	__u64 tx_replay_event;
+	__u64 rx_loop_time_req_ctl_fr;
+	__u64 rx_loop_time_rsp_ctl_fr;
+	__u64 rx_bad_ctl_fr;
+	__u64 rx_init_ctl_os;
+	__u64 rx_init_echo_ctl_os;
+	__u64 rx_ack_ctl_os;
+	__u64 rx_nack_ctl_os;
+	__u64 rx_ack_nack_seq_err;
+	__u64 rx_ok_lossy;
+	__u64 rx_poisoned_lossy;
+	__u64 rx_bad_lossy;
+	__u64 rx_ok_lossless;
+	__u64 rx_poisoned_lossless;
+	__u64 rx_bad_lossless;
+	__u64 rx_expected_seq_good;
+	__u64 rx_expected_seq_poisoned;
+	__u64 rx_expected_seq_bad;
+	__u64 rx_unexpected_seq;
+	__u64 rx_duplicate_seq;
+	__u64 rx_replay_event;
+};
+
+struct c2_hni_llr_cntrs {
+	__u64 tx_loop_time_req_ctl_fr;
+	__u64 tx_loop_time_rsp_ctl_fr;
+	__u64 tx_init_ctl_os;
+	__u64 tx_init_echo_ctl_os;
+	__u64 tx_ack_ctl_os;
+	__u64 tx_nack_ctl_os;
+	__u64 tx_discard;
+	__u64 tx_ok_lossy;
+	__u64 tx_ok_lossless;
+	__u64 tx_ok_lossless_rpt;
+	__u64 tx_poisoned_lossy;
+	__u64 tx_poisoned_lossless;
+	__u64 tx_poisoned_lossless_rpt;
+	__u64 tx_bad_lossy;
+	__u64 tx_bad_lossless;
+	__u64 tx_bad_lossless_rpt;
+	__u64 tx_ok_bypass;
+	__u64 tx_replay_event;
+	__u64 tx_llr_blocked;
+	__u64 tx_llr_unblocked;
+	__u64 rx_loop_time_req_ctl_fr;
+	__u64 rx_loop_time_rsp_ctl_fr;
+	__u64 rx_bad_ctl_fr;
+	__u64 rx_init_ctl_os;
+	__u64 rx_init_echo_ctl_os;
+	__u64 rx_ack_ctl_os;
+	__u64 rx_nack_ctl_os;
+	__u64 rx_ack_nack_seq_err;
+	__u64 rx_ok_lossy;
+	__u64 rx_poisoned_lossy;
+	__u64 rx_bad_lossy;
+	__u64 rx_ok_lossless;
+	__u64 rx_poisoned_lossless;
+	__u64 rx_bad_lossless;
+	__u64 rx_expected_seq_good;
+	__u64 rx_expected_seq_poisoned;
+	__u64 rx_expected_seq_bad;
+	__u64 rx_unexpected_seq;
+	__u64 rx_duplicate_seq;
+	__u64 rx_replay_event;
+	__u64 rx_ack_nack_error;
+};
+
+struct c_pi_dmac_cdesc {
+	__u8 done    :  1;
+	__u8 status  :  2;
+	__u64: 61;
+};
+
+struct c_idc_put_cmd {
+	struct c_idc_hdr idc_header;
+	__u8 data[0];
+};
+
+struct c_list_entry_simple {
+	__u64: 38;
+	__u16 addr  : 14;
+	__u8 vld    :  1;
+	__u16: 11;
+} __attribute__((packed));
+
+struct c_mst_table_simple {
+	__u16 portal_index  : 11;
+	__u8:  1;
+	__u8 ptl_list       :  2;
+	__u8:  2;
+	__u16 buffer_id;
+	__u32 initiator;
+};
+
+struct c_ct_writeback {
+	__u64 ct_success   : 48;
+	__u8 ct_failure    :  7;
+	__u16 unused       :  8;
+	__u8 ct_writeback  :  1;
+};
+#define C_ATU_CFG_CRNC_OFFSET	0x00000000
+#define C_ATU_CFG_CRNC	(C_ATU_BASE + C_ATU_CFG_CRNC_OFFSET)
+#define C_ATU_CFG_CRNC_SIZE	0x00000008
+
+union c_atu_cfg_crnc {
+	__u64 qw;
+	struct {
+		__u64 csr_timeout   :  8;
+		__u64 mcast_id      : 10;
+		__u64: 1;
+		__u64 mcast_enable  :  1;
+		__u64 mcast_mask    : 10;
+		__u64: 34;
+	};
+};
+
+#define C_ATU_MSC_SHADOW_ACTION_OFFSET	0x00000038
+#define C_ATU_MSC_SHADOW_ACTION	(C_ATU_BASE + C_ATU_MSC_SHADOW_ACTION_OFFSET)
+#define C_ATU_MSC_SHADOW_ACTION_SIZE	0x00000008
+
+union c_msc_shadow_action {
+	__u64 qw;
+	struct {
+		__u64 addr_offset  : 23;
+		__u64: 8;
+		__u64 write        :  1;
+		__u64: 32;
+	};
+};
+
+#define C_ATU_MSC_SHADOW_OFFSET	0x00000040
+#define C_ATU_MSC_SHADOW	(C_ATU_BASE + C_ATU_MSC_SHADOW_OFFSET)
+#define C_ATU_MSC_SHADOW_SIZE	0x00000020
+
+union c_atu_msc_shadow {
+	__u64 qw[4];
+};
+
+#define C_ATU_ERR_ELAPSED_TIME_OFFSET	0x00000100
+#define C_ATU_ERR_ELAPSED_TIME	(C_ATU_BASE + C_ATU_ERR_ELAPSED_TIME_OFFSET)
+#define C_ATU_ERR_ELAPSED_TIME_SIZE	0x00000008
+
+union c_atu_err_elapsed_time {
+	__u64 qw;
+	struct {
+		__u64 nanoseconds  : 30;
+		__u64 seconds      : 34;
+	};
+};
+
+#define C_ATU_ERR_FLG_OFFSET	0x00000108
+#define C_ATU_ERR_FLG	(C_ATU_BASE + C_ATU_ERR_FLG_OFFSET)
+#define C_ATU_ERR_FLG_SIZE	0x00000008
+
+union c_atu_err_flg {
+	__u64 qw;
+	struct {
+		__u64 sw_diag                   :  1;
+		__u64 crnc_ring_sync_error      :  1;
+		__u64 crnc_ring_ecc_sbe         :  1;
+		__u64 crnc_ring_ecc_mbe         :  1;
+		__u64 crnc_ring_cmd_unknown     :  1;
+		__u64 crnc_csr_cmd_unknown      :  1;
+		__u64 crnc_csr_cmd_incomplete   :  1;
+		__u64 crnc_buf_ecc_sbe          :  1;
+		__u64 crnc_buf_ecc_mbe          :  1;
+		__u64: 23;
+		__u64 fifo_err                  :  1;
+		__u64 page_perm_err             :  1;
+		__u64 ats_trans_err             :  1;
+		__u64 pcie_unsuccess_cmpl       :  1;
+		__u64 pcie_error_poisoned       :  1;
+		__u64 ats_page_req_err          :  1;
+		__u64 no_translation            :  1;
+		__u64 invalid_ac                :  1;
+		__u64 prb_expired               :  1;
+		__u64 nta_pte_align_err         :  1;
+		__u64 ats_odp_config_err        :  1;
+		__u64 addr_out_of_range         :  1;
+		__u64 ats_page_size_config_err  :  1;
+		__u64 ats_page_size_err         :  1;
+		__u64 p_tarb_cdt_uflow          :  1;
+		__u64 np_tarb_cdt_uflow         :  1;
+		__u64 ee_odp_req_err            :  1;
+		__u64 ats_fn_disabled_err       :  1;
+		__u64 rarb_hw_err               :  1;
+		__u64 epoch_cnt_err             :  1;
+		__u64 rspq_cmpl_err             :  1;
+		__u64 odp_unexp_idx_err         :  1;
+		__u64 in_progress_cnt_err       :  1;
+		__u64: 9;
+	};
+};
+
+#define C_ATU_ERR_FIRST_FLG_OFFSET	0x00000110
+#define C_ATU_ERR_FIRST_FLG	(C_ATU_BASE + C_ATU_ERR_FIRST_FLG_OFFSET)
+#define C_ATU_ERR_FIRST_FLG_SIZE	0x00000008
+#define C_ATU_ERR_FIRST_FLG_TS_OFFSET	0x00000118
+#define C_ATU_ERR_FIRST_FLG_TS	(C_ATU_BASE + C_ATU_ERR_FIRST_FLG_TS_OFFSET)
+#define C_ATU_ERR_FIRST_FLG_TS_SIZE	0x00000008
+#define C_ATU_ERR_CLR_OFFSET	0x00000120
+#define C_ATU_ERR_CLR	(C_ATU_BASE + C_ATU_ERR_CLR_OFFSET)
+#define C_ATU_ERR_CLR_SIZE	0x00000008
+#define C_ATU_ERR_IRQA_MSK_OFFSET	0x00000128
+#define C_ATU_ERR_IRQA_MSK	(C_ATU_BASE + C_ATU_ERR_IRQA_MSK_OFFSET)
+#define C_ATU_ERR_IRQA_MSK_SIZE	0x00000008
+#define C_ATU_ERR_IRQB_MSK_OFFSET	0x00000130
+#define C_ATU_ERR_IRQB_MSK	(C_ATU_BASE + C_ATU_ERR_IRQB_MSK_OFFSET)
+#define C_ATU_ERR_IRQB_MSK_SIZE	0x00000008
+#define C_ATU_ERR_INFO_MSK_OFFSET	0x00000140
+#define C_ATU_ERR_INFO_MSK	(C_ATU_BASE + C_ATU_ERR_INFO_MSK_OFFSET)
+#define C_ATU_ERR_INFO_MSK_SIZE	0x00000008
+#define C_ATU_EXT_ERR_FLG_OFFSET	0x00000148
+#define C_ATU_EXT_ERR_FLG	(C_ATU_BASE + C_ATU_EXT_ERR_FLG_OFFSET)
+#define C_ATU_EXT_ERR_FLG_SIZE	0x00000008
+
+union c_atu_ext_err_flg {
+	__u64 qw;
+	struct {
+		__u64 sw_diag              :  1;
+		__u64 ac_mem_cor           :  1;
+		__u64 otb_mem_cor          :  1;
+		__u64 tag_mem_cor          :  1;
+		__u64 ingress_bus_cor      :  1;
+		__u64 data_mem_cor         :  1;
+		__u64 chain_tail_mem_cor   :  1;
+		__u64 chain_next_mem_cor   :  1;
+		__u64 missq_mem_cor        :  1;
+		__u64 uniqq_mem_cor        :  1;
+		__u64 chain_mem_cor        :  1;
+		__u64 pointer_mem_cor      :  1;
+		__u64 replayq_mem_cor      :  1;
+		__u64 retryq_mem_cor       :  1;
+		__u64 prb_mem_cor          :  1;
+		__u64 invalq_mem_cor       :  1;
+		__u64 rspinfoq_mem_cor     :  1;
+		__u64 cmpldata_mem_cor     :  1;
+		__u64 atucq_mem_cor        :  1;
+		__u64 ats_prq_mem_cor      :  1;
+		__u64 rarb_hdr_bus_cor     :  1;
+		__u64 rarb_data_bus_cor    :  1;
+		__u64 odpq_mem_cor         :  1;
+		__u64: 9;
+		__u64: 1;
+		__u64 ac_mem_ucor          :  1;
+		__u64 otb_mem_ucor         :  1;
+		__u64 tag_mem_ucor         :  1;
+		__u64 ingress_bus_ucor     :  1;
+		__u64 data_mem_ucor        :  1;
+		__u64 chain_tail_mem_ucor  :  1;
+		__u64 chain_next_mem_ucor  :  1;
+		__u64 missq_mem_ucor       :  1;
+		__u64 uniqq_mem_ucor       :  1;
+		__u64 chain_mem_ucor       :  1;
+		__u64 pointer_mem_ucor     :  1;
+		__u64 replayq_mem_ucor     :  1;
+		__u64 retryq_mem_ucor      :  1;
+		__u64 prb_mem_ucor         :  1;
+		__u64 invalq_mem_ucor      :  1;
+		__u64 rspinfoq_mem_ucor    :  1;
+		__u64 cmpldata_mem_ucor    :  1;
+		__u64 atucq_mem_ucor       :  1;
+		__u64 ats_prq_mem_ucor     :  1;
+		__u64 rarb_hdr_bus_ucor    :  1;
+		__u64 rarb_data_bus_ucor   :  1;
+		__u64 odpq_mem_ucor        :  1;
+		__u64: 1;
+		__u64 anchor_vld_mem_ucor  :  1;
+		__u64 anchor_mem_ucor      :  1;
+		__u64: 2;
+		__u64: 4;
+	};
+};
+
+#define C_ATU_EXT_ERR_FIRST_FLG_OFFSET	0x00000150
+#define C_ATU_EXT_ERR_FIRST_FLG	(C_ATU_BASE + C_ATU_EXT_ERR_FIRST_FLG_OFFSET)
+#define C_ATU_EXT_ERR_FIRST_FLG_SIZE	0x00000008
+#define C_ATU_EXT_ERR_FIRST_FLG_TS_OFFSET	0x00000158
+#define C_ATU_EXT_ERR_FIRST_FLG_TS	(C_ATU_BASE + C_ATU_EXT_ERR_FIRST_FLG_TS_OFFSET)
+#define C_ATU_EXT_ERR_FIRST_FLG_TS_SIZE	0x00000008
+#define C_ATU_EXT_ERR_CLR_OFFSET	0x00000160
+#define C_ATU_EXT_ERR_CLR	(C_ATU_BASE + C_ATU_EXT_ERR_CLR_OFFSET)
+#define C_ATU_EXT_ERR_CLR_SIZE	0x00000008
+#define C_ATU_EXT_ERR_IRQA_MSK_OFFSET	0x00000168
+#define C_ATU_EXT_ERR_IRQA_MSK	(C_ATU_BASE + C_ATU_EXT_ERR_IRQA_MSK_OFFSET)
+#define C_ATU_EXT_ERR_IRQA_MSK_SIZE	0x00000008
+#define C_ATU_EXT_ERR_IRQB_MSK_OFFSET	0x00000170
+#define C_ATU_EXT_ERR_IRQB_MSK	(C_ATU_BASE + C_ATU_EXT_ERR_IRQB_MSK_OFFSET)
+#define C_ATU_EXT_ERR_IRQB_MSK_SIZE	0x00000008
+#define C_ATU_EXT_ERR_INFO_MSK_OFFSET	0x00000180
+#define C_ATU_EXT_ERR_INFO_MSK	(C_ATU_BASE + C_ATU_EXT_ERR_INFO_MSK_OFFSET)
+#define C_ATU_EXT_ERR_INFO_MSK_SIZE	0x00000008
+#define C_ATU_ERR_INFO_MEM_OFFSET	0x00000200
+#define C_ATU_ERR_INFO_MEM	(C_ATU_BASE + C_ATU_ERR_INFO_MEM_OFFSET)
+#define C_ATU_ERR_INFO_MEM_SIZE	0x00000008
+
+union c_atu_err_info_mem {
+	__u64 qw;
+	struct {
+		__u64 cor_syndrome       : 11;
+		__u64: 1;
+		__u64 cor_address        : 12;
+		__u64 cor_mem_id         :  6;
+		__u64: 1;
+		__u64 cor_csr_detected   :  1;
+		__u64 ucor_syndrome      : 11;
+		__u64: 1;
+		__u64 ucor_address       : 12;
+		__u64 ucor_mem_id        :  6;
+		__u64: 1;
+		__u64 ucor_csr_detected  :  1;
+	};
+};
+
+#define C_ATU_ERR_INFO_AC_OFFSET	0x00000208
+#define C_ATU_ERR_INFO_AC	(C_ATU_BASE + C_ATU_ERR_INFO_AC_OFFSET)
+#define C_ATU_ERR_INFO_AC_SIZE	0x00000008
+
+union c_atu_err_info_ac {
+	__u64 qw;
+	struct {
+		__u64 acid        : 10;
+		__u64: 2;
+		__u64 client      :  2;
+		__u64: 2;
+		__u64 error_type  :  3;
+		__u64: 45;
+	};
+};
+
+#define C_ATU_ERR_INFO_TRANSLATION_OFFSET	0x00000210
+#define C_ATU_ERR_INFO_TRANSLATION	(C_ATU_BASE + C_ATU_ERR_INFO_TRANSLATION_OFFSET)
+#define C_ATU_ERR_INFO_TRANSLATION_SIZE	0x00000008
+
+union c_atu_err_info_translation {
+	__u64 qw;
+	struct {
+		__u64 acid    : 10;
+		__u64 client  :  2;
+		__u64 addr    : 45;
+		__u64: 7;
+	};
+};
+
+#define C_ATU_ERR_INFO_ATS_PAGE_REQ_OFFSET	0x00000218
+#define C_ATU_ERR_INFO_ATS_PAGE_REQ	(C_ATU_BASE + C_ATU_ERR_INFO_ATS_PAGE_REQ_OFFSET)
+#define C_ATU_ERR_INFO_ATS_PAGE_REQ_SIZE	0x00000008
+
+union c_atu_err_info_ats_page_req {
+	__u64 qw;
+	struct {
+		__u64 acid          : 10;
+		__u64 client        :  2;
+		__u64 prg_rsp_code  :  4;
+		__u64 prb_ucor      :  1;
+		__u64: 47;
+	};
+};
+
+#define C_ATU_ERR_INFO_PCIE_EP_OFFSET	0x00000220
+#define C_ATU_ERR_INFO_PCIE_EP	(C_ATU_BASE + C_ATU_ERR_INFO_PCIE_EP_OFFSET)
+#define C_ATU_ERR_INFO_PCIE_EP_SIZE	0x00000008
+
+union c_atu_err_info_pcie_ep {
+	__u64 qw;
+	struct {
+		__u64 acid    : 10;
+		__u64: 2;
+		__u64 client  :  2;
+		__u64: 50;
+	};
+};
+
+#define C_ATU_ERR_INFO_PCIE_UC_OFFSET	0x00000228
+#define C_ATU_ERR_INFO_PCIE_UC	(C_ATU_BASE + C_ATU_ERR_INFO_PCIE_UC_OFFSET)
+#define C_ATU_ERR_INFO_PCIE_UC_SIZE	0x00000008
+
+union c_atu_err_info_pcie_uc {
+	__u64 qw;
+	struct {
+		__u64 acid         : 10;
+		__u64: 2;
+		__u64 client       :  2;
+		__u64: 2;
+		__u64 cmpl_status  :  3;
+		__u64: 45;
+	};
+};
+
+#define C_ATU_ERR_INFO_ATS_TRANS_OFFSET	0x00000230
+#define C_ATU_ERR_INFO_ATS_TRANS	(C_ATU_BASE + C_ATU_ERR_INFO_ATS_TRANS_OFFSET)
+#define C_ATU_ERR_INFO_ATS_TRANS_SIZE	0x00000008
+
+union c_atu_err_info_ats_trans {
+	__u64 qw;
+	struct {
+		__u64 acid         : 10;
+		__u64 client       :  2;
+		__u64 addr         : 45;
+		__u64 cmpl_status  :  3;
+		__u64: 4;
+	};
+};
+
+#define C_ATU_ERR_INFO_PAGE_PERM_OFFSET	0x00000238
+#define C_ATU_ERR_INFO_PAGE_PERM	(C_ATU_BASE + C_ATU_ERR_INFO_PAGE_PERM_OFFSET)
+#define C_ATU_ERR_INFO_PAGE_PERM_SIZE	0x00000008
+
+union c_atu_err_info_page_perm {
+	__u64 qw;
+	struct {
+		__u64 acid               : 10;
+		__u64: 2;
+		__u64 client             :  2;
+		__u64: 2;
+		__u64 perm_ats_priv      :  1;
+		__u64 perm_ats_exec      :  1;
+		__u64 perm_w             :  1;
+		__u64 perm_r             :  1;
+		__u64 perm_req_ats_priv  :  1;
+		__u64 perm_req_ats_exec  :  1;
+		__u64 perm_req_w         :  1;
+		__u64 perm_req_r         :  1;
+		__u64: 40;
+	};
+};
+
+#define C_ATU_ERR_INFO_NTA_PTE_ALIGN_OFFSET	0x00000240
+#define C_ATU_ERR_INFO_NTA_PTE_ALIGN	(C_ATU_BASE + C_ATU_ERR_INFO_NTA_PTE_ALIGN_OFFSET)
+#define C_ATU_ERR_INFO_NTA_PTE_ALIGN_SIZE	0x00000008
+
+union c_atu_err_info_nta_pte_align {
+	__u64 qw;
+	struct {
+		__u64 acid       : 10;
+		__u64 client     :  2;
+		__u64 addr       : 45;
+		__u64 page_size  :  5;
+		__u64: 2;
+	};
+};
+
+#define C_ATU_ERR_INFO_FIFO_OFFSET	0x00000248
+#define C_ATU_ERR_INFO_FIFO	(C_ATU_BASE + C_ATU_ERR_INFO_FIFO_OFFSET)
+#define C_ATU_ERR_INFO_FIFO_SIZE	0x00000008
+
+union c_atu_err_info_fifo {
+	__u64 qw;
+	struct {
+		__u64 overrun   :  1;
+		__u64 underrun  :  1;
+		__u64: 14;
+		__u64 fifo_id   :  4;
+		__u64: 44;
+	};
+};
+
+#define C_ATU_ERR_INFO_ADDR_OUT_OF_RANGE_OFFSET	0x00000250
+#define C_ATU_ERR_INFO_ADDR_OUT_OF_RANGE	(C_ATU_BASE + C_ATU_ERR_INFO_ADDR_OUT_OF_RANGE_OFFSET)
+#define C_ATU_ERR_INFO_ADDR_OUT_OF_RANGE_SIZE	0x00000008
+
+union c_atu_err_info_addr_out_of_range {
+	__u64 qw;
+	struct {
+		__u64 acid    : 10;
+		__u64 client  :  2;
+		__u64 addr    : 45;
+		__u64: 7;
+	};
+};
+
+#define C_ATU_ERR_INFO_ATS_PAGE_SIZE_CONFIG_OFFSET	0x00000258
+#define C_ATU_ERR_INFO_ATS_PAGE_SIZE_CONFIG	(C_ATU_BASE + C_ATU_ERR_INFO_ATS_PAGE_SIZE_CONFIG_OFFSET)
+#define C_ATU_ERR_INFO_ATS_PAGE_SIZE_CONFIG_SIZE	0x00000008
+
+union c_atu_err_info_ats_page_size_config {
+	__u64 qw;
+	struct {
+		__u64 acid     : 10;
+		__u64: 2;
+		__u64 client   :  2;
+		__u64: 2;
+		__u64 pg_size  :  5;
+		__u64: 43;
+	};
+};
+
+#define C_ATU_ERR_INFO_ATS_PAGE_SIZE_OFFSET	0x00000260
+#define C_ATU_ERR_INFO_ATS_PAGE_SIZE	(C_ATU_BASE + C_ATU_ERR_INFO_ATS_PAGE_SIZE_OFFSET)
+#define C_ATU_ERR_INFO_ATS_PAGE_SIZE_SIZE	0x00000008
+
+union c_atu_err_info_ats_page_size {
+	__u64 qw;
+	struct {
+		__u64 acid     : 10;
+		__u64: 2;
+		__u64 client   :  2;
+		__u64: 2;
+		__u64 pg_size  :  6;
+		__u64: 42;
+	};
+};
+
+#define C_ATU_ERR_INFO_EE_ODP_REQ_OFFSET	0x00000268
+#define C_ATU_ERR_INFO_EE_ODP_REQ	(C_ATU_BASE + C_ATU_ERR_INFO_EE_ODP_REQ_OFFSET)
+#define C_ATU_ERR_INFO_EE_ODP_REQ_SIZE	0x00000008
+
+union c_atu_err_info_ee_odp_req {
+	__u64 qw;
+	struct {
+		__u64 acid  : 10;
+		__u64: 2;
+		__u64 addr  : 45;
+		__u64: 7;
+	};
+};
+
+#define C_ATU_ERR_INFO_ATS_ODP_CONFIG_OFFSET	0x00000270
+#define C_ATU_ERR_INFO_ATS_ODP_CONFIG	(C_ATU_BASE + C_ATU_ERR_INFO_ATS_ODP_CONFIG_OFFSET)
+#define C_ATU_ERR_INFO_ATS_ODP_CONFIG_SIZE	0x00000008
+
+union c_atu_err_info_ats_odp_config {
+	__u64 qw;
+	struct {
+		__u64 acid    : 10;
+		__u64: 2;
+		__u64 client  :  2;
+		__u64: 50;
+	};
+};
+
+#define C_ATU_ERR_INFO_PRB_EXPIRED_OFFSET	0x00000278
+#define C_ATU_ERR_INFO_PRB_EXPIRED	(C_ATU_BASE + C_ATU_ERR_INFO_PRB_EXPIRED_OFFSET)
+#define C_ATU_ERR_INFO_PRB_EXPIRED_SIZE	0x00000008
+
+union c_atu_err_info_prb_expired {
+	__u64 qw;
+	struct {
+		__u64 index  :  9;
+		__u64: 55;
+	};
+};
+
+#define C_ATU_ERR_INFO_ATS_FN_DISABLED_OFFSET	0x00000280
+#define C_ATU_ERR_INFO_ATS_FN_DISABLED	(C_ATU_BASE + C_ATU_ERR_INFO_ATS_FN_DISABLED_OFFSET)
+#define C_ATU_ERR_INFO_ATS_FN_DISABLED_SIZE	0x00000008
+
+union c_atu_err_info_ats_fn_disabled {
+	__u64 qw;
+	struct {
+		__u64 acid    : 10;
+		__u64: 2;
+		__u64 client  :  2;
+		__u64: 50;
+	};
+};
+
+#define C_ATU_ERR_INFO_RARB_OFFSET	0x00000288
+#define C_ATU_ERR_INFO_RARB	(C_ATU_BASE + C_ATU_ERR_INFO_RARB_OFFSET)
+#define C_ATU_ERR_INFO_RARB_SIZE	0x00000008
+
+union c_atu_err_info_rarb {
+	__u64 qw;
+	struct {
+		__u64 hdr_ucor               :  1;
+		__u64 data_ucor              :  1;
+		__u64 bad_vld                :  1;
+		__u64 bad_eop                :  1;
+		__u64 bad_cmd                :  1;
+		__u64 unexpected_cmpl_ptid   :  1;
+		__u64 cmpl_tag_out_of_range  :  1;
+		__u64: 57;
+	};
+};
+
+#define C_ATU_ERR_INFO_EPOCH_CNT_OFFSET	0x00000290
+#define C_ATU_ERR_INFO_EPOCH_CNT	(C_ATU_BASE + C_ATU_ERR_INFO_EPOCH_CNT_OFFSET)
+#define C_ATU_ERR_INFO_EPOCH_CNT_SIZE	0x00000008
+
+union c_atu_err_info_epoch_cnt {
+	__u64 qw;
+	struct {
+		__u64 oxe_at_epoch0_cnt_underrun  :  1;
+		__u64 oxe_at_epoch0_cnt_overrun   :  1;
+		__u64 oxe_at_epoch1_cnt_underrun  :  1;
+		__u64 oxe_at_epoch1_cnt_overrun   :  1;
+		__u64 ixe_at_epoch0_cnt_underrun  :  1;
+		__u64 ixe_at_epoch0_cnt_overrun   :  1;
+		__u64 ixe_at_epoch1_cnt_underrun  :  1;
+		__u64 ixe_at_epoch1_cnt_overrun   :  1;
+		__u64 ee_at_epoch0_cnt_underrun   :  1;
+		__u64 ee_at_epoch0_cnt_overrun    :  1;
+		__u64 ee_at_epoch1_cnt_underrun   :  1;
+		__u64 ee_at_epoch1_cnt_overrun    :  1;
+		__u64 ib_epoch0_cnt_underrun      :  1;
+		__u64 ib_epoch0_cnt_overrun       :  1;
+		__u64 ib_epoch1_cnt_underrun      :  1;
+		__u64 ib_epoch1_cnt_overrun       :  1;
+		__u64: 48;
+	};
+};
+
+#define C_ATU_ERR_INFO_RSPQ_CMPL_OFFSET	0x00000298
+#define C_ATU_ERR_INFO_RSPQ_CMPL	(C_ATU_BASE + C_ATU_ERR_INFO_RSPQ_CMPL_OFFSET)
+#define C_ATU_ERR_INFO_RSPQ_CMPL_SIZE	0x00000008
+
+union c_atu_err_info_rspq_cmpl {
+	__u64 qw;
+	struct {
+		__u64 cmpl_last_surplus  :  1;
+		__u64 cmpl_last_deficit  :  1;
+		__u64 cmpl_missing       :  1;
+		__u64: 61;
+	};
+};
+
+#define C_ATU_ERR_INFO_ODP_UNEXP_IDX_OFFSET	0x000002a0
+#define C_ATU_ERR_INFO_ODP_UNEXP_IDX	(C_ATU_BASE + C_ATU_ERR_INFO_ODP_UNEXP_IDX_OFFSET)
+#define C_ATU_ERR_INFO_ODP_UNEXP_IDX_SIZE	0x00000008
+
+union c_atu_err_info_odp_unexp_idx {
+	__u64 qw;
+	struct {
+		__u64 prb_index   :  9;
+		__u64 ats_pg_rsp  :  1;
+		__u64: 54;
+	};
+};
+
+#define C_ATU_ERR_INFO_IN_PROGRESS_CNT_OFFSET	0x000002a8
+#define C_ATU_ERR_INFO_IN_PROGRESS_CNT	(C_ATU_BASE + C_ATU_ERR_INFO_IN_PROGRESS_CNT_OFFSET)
+#define C_ATU_ERR_INFO_IN_PROGRESS_CNT_SIZE	0x00000008
+
+union c_atu_err_info_in_progress_cnt {
+	__u64 qw;
+	struct {
+		__u64 oxe_epoch0_cnt_underrun  :  1;
+		__u64 oxe_epoch0_cnt_overrun   :  1;
+		__u64 oxe_epoch1_cnt_underrun  :  1;
+		__u64 oxe_epoch1_cnt_overrun   :  1;
+		__u64 ixe_epoch0_cnt_underrun  :  1;
+		__u64 ixe_epoch0_cnt_overrun   :  1;
+		__u64 ixe_epoch1_cnt_underrun  :  1;
+		__u64 ixe_epoch1_cnt_overrun   :  1;
+		__u64 ee_epoch0_cnt_underrun   :  1;
+		__u64 ee_epoch0_cnt_overrun    :  1;
+		__u64 ee_epoch1_cnt_underrun   :  1;
+		__u64 ee_epoch1_cnt_overrun    :  1;
+		__u64: 52;
+	};
+};
+
+#define C_ATU_CFG_NTA_OFFSET	0x00000400
+#define C_ATU_CFG_NTA	(C_ATU_BASE + C_ATU_CFG_NTA_OFFSET)
+#define C_ATU_CFG_NTA_SIZE	0x00000008
+
+union c_atu_cfg_nta {
+	__u64 qw;
+	struct {
+		__u64 acid  : 10;
+		__u64: 54;
+	};
+};
+
+#define C_ATU_CFG_ATS_OFFSET	0x00000408
+#define C_ATU_CFG_ATS	(C_ATU_BASE + C_ATU_CFG_ATS_OFFSET)
+#define C_ATU_CFG_ATS_SIZE	0x00000008
+
+union c_atu_cfg_ats {
+	__u64 qw;
+	struct {
+		__u64 inval_batch_mode        :  1;
+		__u64: 3;
+		__u64 num_xlations_req        :  2;
+		__u64: 2;
+		__u64 inval_process_interval  :  5;
+		__u64: 3;
+		__u64 truncate_gt_stu_rsp     :  1;
+		__u64: 47;
+	};
+};
+
+#define C_ATU_CFG_CMDPROC_OFFSET	0x00000410
+#define C_ATU_CFG_CMDPROC	(C_ATU_BASE + C_ATU_CFG_CMDPROC_OFFSET)
+#define C_ATU_CFG_CMDPROC_SIZE	0x00000008
+
+union c_atu_cfg_cmdproc {
+	__u64 qw;
+	struct {
+		__u64: 4;
+		__u64 rd_ptr  :  5;
+		__u64: 7;
+		__u64: 4;
+		__u64 wr_ptr  :  5;
+		__u64: 39;
+	};
+};
+
+#define C_ATU_CFG_WB_DATA_OFFSET	0x00000418
+#define C_ATU_CFG_WB_DATA	(C_ATU_BASE + C_ATU_CFG_WB_DATA_OFFSET)
+#define C_ATU_CFG_WB_DATA_SIZE	0x00000008
+
+union c_atu_cfg_wb_data {
+	__u64 qw;
+	struct {
+		__u64 data;
+	};
+};
+
+#define C_ATU_CFG_CMDS_OFFSET	0x00000430
+#define C_ATU_CFG_CMDS	(C_ATU_BASE + C_ATU_CFG_CMDS_OFFSET)
+#define C_ATU_CFG_CMDS_SIZE	0x00000008
+
+union c_atu_cfg_cmds {
+	__u64 qw;
+	struct {
+		__u64 writeback_acid        : 10;
+		__u64: 6;
+		__u64 ib_wait_int_idx       : 11;
+		__u64: 1;
+		__u64 ib_wait_int_enable    :  1;
+		__u64: 3;
+		__u64 cmpl_wait_int_idx     : 11;
+		__u64: 1;
+		__u64 cmpl_wait_int_enable  :  1;
+		__u64: 19;
+	};
+};
+
+#define C_ATU_CFG_ODPQ_OFFSET	0x00000438
+#define C_ATU_CFG_ODPQ	(C_ATU_BASE + C_ATU_CFG_ODPQ_OFFSET)
+#define C_ATU_CFG_ODPQ_SIZE	0x00000008
+
+union c_atu_cfg_odpq {
+	__u64 qw;
+	struct {
+		__u64 prb_index  :  9;
+		__u64: 7;
+		__u64 status     :  1;
+		__u64: 47;
+	};
+};
+
+#define C_ATU_CFG_ODP_OFFSET	0x00000440
+#define C_ATU_CFG_ODP	(C_ATU_BASE + C_ATU_CFG_ODP_OFFSET)
+#define C_ATU_CFG_ODP_SIZE	0x00000008
+
+union c_atu_cfg_odp {
+	__u64 qw;
+	struct {
+		__u64 acid        : 10;
+		__u64: 6;
+		__u64 int_idx     : 11;
+		__u64: 1;
+		__u64 int_enable  :  1;
+		__u64: 31;
+		__u64 odp_en      :  1;
+		__u64: 3;
+	};
+};
+
+#define C_ATU_CFG_PRI_OFFSET	0x00000448
+#define C_ATU_CFG_PRI	(C_ATU_BASE + C_ATU_CFG_PRI_OFFSET)
+#define C_ATU_CFG_PRI_SIZE	0x00000008
+
+union c_atu_cfg_pri {
+	__u64 qw;
+	struct {
+		__u64: 12;
+		__u64 base_addr            : 45;
+		__u64: 3;
+		__u64 relaxed_ordering_en  :  1;
+		__u64: 3;
+	};
+};
+
+#define C_ATU_CFG_PRB_OFFSET	0x00000450
+#define C_ATU_CFG_PRB	(C_ATU_BASE + C_ATU_CFG_PRB_OFFSET)
+#define C_ATU_CFG_PRB_SIZE	0x00000008
+
+union c_atu_cfg_prb {
+	__u64 qw;
+	struct {
+		__u64 timeout  :  4;
+		__u64: 60;
+	};
+};
+
+#define C1_ATU_CFG_ODP_DECOUPLE_OFFSET	0x00000478
+#define C1_ATU_CFG_ODP_DECOUPLE	(C_ATU_BASE + C1_ATU_CFG_ODP_DECOUPLE_OFFSET)
+#define C1_ATU_CFG_ODP_DECOUPLE_SIZE	0x00000008
+
+union c1_atu_cfg_odp_decouple {
+	__u64 qw;
+	struct {
+		__u64 flush_req_delay  : 10;
+		__u64: 2;
+		__u64 enable           :  1;
+		__u64: 51;
+	};
+};
+
+#define C2_ATU_CFG_ODP_DECOUPLE_OFFSET	0x00000478
+#define C2_ATU_CFG_ODP_DECOUPLE	(C_ATU_BASE + C2_ATU_CFG_ODP_DECOUPLE_OFFSET)
+#define C2_ATU_CFG_ODP_DECOUPLE_SIZE	0x00000008
+
+union c2_atu_cfg_odp_decouple {
+	__u64 qw;
+	struct {
+		__u64 flush_req_delay   : 32;
+		__u64 enable            :  1;
+		__u64 wait_no_trigger   :  1;
+		__u64 ip_all_client     :  1;
+		__u64 tcam_mask         :  2;
+		__u64 flush_to_trigger  :  1;
+		__u64 trigger_wo_odp    :  1;
+		__u64: 25;
+	};
+};
+
+#define C_ATU_CFG_INBOUND_WAIT_OFFSET	0x00000480
+#define C_ATU_CFG_INBOUND_WAIT	(C_ATU_BASE + C_ATU_CFG_INBOUND_WAIT_OFFSET)
+#define C_ATU_CFG_INBOUND_WAIT_SIZE	0x00000008
+
+union c_atu_cfg_inbound_wait {
+	__u64 qw;
+	struct {
+		__u64: 3;
+		__u64 rsp_addr  : 54;
+		__u64 rsp_en    :  1;
+		__u64: 6;
+	};
+};
+
+#define C_ATU_CFG_AC_TABLE_OFFSET(idx)	(0x00010000 + ((idx) * 32))
+#define C_ATU_CFG_AC_TABLE_ENTRIES	1024
+#define C_ATU_CFG_AC_TABLE(idx)	(C_ATU_BASE + C_ATU_CFG_AC_TABLE_OFFSET(idx))
+#define C_ATU_CFG_AC_TABLE_SIZE	0x00008000
+
+union c_atu_cfg_ac_table {
+	__u64 qw[4];
+	struct {
+		union {
+			struct {
+				__u64: 12;
+				__u64 nta_root_ptr     : 45;
+				__u64 nta_use_req_acid :  1;
+				__u64:  6;
+			};
+			struct {
+				__u64: 12;
+				__u64 ats_vf_num             : 6;
+				__u64 ats_vf_en              : 1;
+				__u64 ats_no_write           : 1;
+				__u64 ats_pasid              : 20;
+				__u64 ats_pasid_er           : 1;
+				__u64 ats_pasid_pmr          : 1;
+				__u64 ats_pasid_en           : 1;
+				__u64 ats_filter_optimistic  : 1;
+				__u64: 20;
+			};
+			struct {
+				__u64: 12;
+				__u64 ta_mode_opts : 46;
+				__u64: 6;
+			};
+		};
+		__u64: 12;
+		__u64 mem_size       : 45;
+		__u64:  7;
+		__u64: 15;
+		__u64 mem_base       : 42;
+		__u64:  7;
+		__u64: 32;
+		__u64 idx_salt	:  8;
+		__u64 ptn_salt	:  2;
+		__u64 cntr_pool_id	:  2;
+		__u64 odp_mode       :  1;
+		__u64 odp_en		:  1;
+		__u64 do_not_filter  :  1;
+		__u64:  1;
+		__u64 ptg_mode       :  3;
+		__u64:  1;
+		__u64 pg_table_size  :  4;
+		__u64 base_pg_size   :  4;
+		__u64 do_not_cache   :  1;
+		__u64 ta_mode	:  2;
+		__u64 context_en     :  1;
+	};
+};
+
+#define C_ATU_CFG_CQ_TABLE_OFFSET(idx)	(0x0001a000 + ((idx) * 8))
+#define C_ATU_CFG_CQ_TABLE_ENTRIES	32
+#define C_ATU_CFG_CQ_TABLE(idx)	(C_ATU_BASE + C_ATU_CFG_CQ_TABLE_OFFSET(idx))
+#define C_ATU_CFG_CQ_TABLE_SIZE	0x00000100
+
+union c_atu_cfg_cq_table {
+	__u64 qw;
+	union {
+		struct {
+			__u64 cmd_args  : 62;
+			__u64 cmd       :  2;
+		};
+		struct {
+			__u64:  3;
+			__u64 comp_wait_rsp_addr : 54;
+			__u64 comp_wait_rsp_en   :  1;
+			__u64:  4;
+			__u64 comp_wait_cmd	    :  2;
+		};
+		struct {
+			__u64 inval_acid     : 10;
+			__u64:  1;
+			__u64 inval_size     :  1;
+			__u64 inval_addr     : 45;
+			__u64:  5;
+			__u64 inval_addr_cmd :  2;
+		};
+	};
+};
+
+#define C_ATU_STS_INIT_DONE_OFFSET	0x00000800
+#define C_ATU_STS_INIT_DONE	(C_ATU_BASE + C_ATU_STS_INIT_DONE_OFFSET)
+#define C_ATU_STS_INIT_DONE_SIZE	0x00000008
+
+union c_atu_sts_init_done {
+	__u64 qw;
+	struct {
+		__u64 tag_init_done     :  1;
+		__u64 anchor_init_done  :  1;
+		__u64 prb_init_done     :  1;
+		__u64: 61;
+	};
+};
+
+#define C_ATU_STS_CMDPROC_OFFSET	0x00000808
+#define C_ATU_STS_CMDPROC	(C_ATU_BASE + C_ATU_STS_CMDPROC_OFFSET)
+#define C_ATU_STS_CMDPROC_SIZE	0x00000008
+
+union c_atu_sts_cmdproc {
+	__u64 qw;
+	struct {
+		__u64 atucq_cmd_count    : 16;
+		__u64: 8;
+		__u64 atucq_cmd          :  2;
+		__u64: 2;
+		__u64 atucq_running      :  1;
+		__u64 atucq_idle         :  1;
+		__u64 atucq_waiting_arb  :  1;
+		__u64 inbound_wait_idle  :  1;
+		__u64 unused             : 32;
+	};
+};
+
+#define C_ATU_STS_AT_EPOCH_OFFSET	0x00000810
+#define C_ATU_STS_AT_EPOCH	(C_ATU_BASE + C_ATU_STS_AT_EPOCH_OFFSET)
+#define C_ATU_STS_AT_EPOCH_SIZE	0x00000008
+
+union c_atu_sts_at_epoch {
+	__u64 qw;
+	struct {
+		__u64 current_epoch        :  1;
+		__u64: 7;
+		__u64 ee_epoch0_cntr_ne0   :  1;
+		__u64 ee_epoch1_cntr_ne0   :  1;
+		__u64: 2;
+		__u64 oxe_epoch0_cntr_ne0  :  1;
+		__u64 oxe_epoch1_cntr_ne0  :  1;
+		__u64: 2;
+		__u64 ixe_epoch0_cntr_ne0  :  1;
+		__u64 ixe_epoch1_cntr_ne0  :  1;
+		__u64: 46;
+	};
+};
+
+#define C_ATU_STS_IXE_AT_EPOCH_CNTR_OFFSET	0x00000818
+#define C_ATU_STS_IXE_AT_EPOCH_CNTR	(C_ATU_BASE + C_ATU_STS_IXE_AT_EPOCH_CNTR_OFFSET)
+#define C_ATU_STS_IXE_AT_EPOCH_CNTR_SIZE	0x00000008
+
+union c_atu_sts_ixe_at_epoch_cntr {
+	__u64 qw;
+	struct {
+		__u64 epoch0  : 16;
+		__u64 epoch1  : 16;
+		__u64 unused  : 32;
+	};
+};
+
+#define C_ATU_STS_OXE_AT_EPOCH_CNTR_OFFSET	0x00000820
+#define C_ATU_STS_OXE_AT_EPOCH_CNTR	(C_ATU_BASE + C_ATU_STS_OXE_AT_EPOCH_CNTR_OFFSET)
+#define C_ATU_STS_OXE_AT_EPOCH_CNTR_SIZE	0x00000008
+
+union c_atu_sts_oxe_at_epoch_cntr {
+	__u64 qw;
+	struct {
+		__u64 epoch0  : 16;
+		__u64 epoch1  : 16;
+		__u64 unused  : 32;
+	};
+};
+
+#define C_ATU_STS_EE_AT_EPOCH_CNTR_OFFSET	0x00000828
+#define C_ATU_STS_EE_AT_EPOCH_CNTR	(C_ATU_BASE + C_ATU_STS_EE_AT_EPOCH_CNTR_OFFSET)
+#define C_ATU_STS_EE_AT_EPOCH_CNTR_SIZE	0x00000008
+
+union c_atu_sts_ee_at_epoch_cntr {
+	__u64 qw;
+	struct {
+		__u64 epoch0  : 16;
+		__u64 epoch1  : 16;
+		__u64 unused  : 32;
+	};
+};
+
+#define C_ATU_STS_IB_EPOCH_OFFSET	0x00000830
+#define C_ATU_STS_IB_EPOCH	(C_ATU_BASE + C_ATU_STS_IB_EPOCH_OFFSET)
+#define C_ATU_STS_IB_EPOCH_SIZE	0x00000008
+
+union c_atu_sts_ib_epoch {
+	__u64 qw;
+	struct {
+		__u64 current_epoch    :  1;
+		__u64 mirrored_epoch   :  1;
+		__u64: 6;
+		__u64 epoch0_cntr_ne0  :  1;
+		__u64 epoch1_cntr_ne0  :  1;
+		__u64: 54;
+	};
+};
+
+#define C_ATU_STS_IB_EPOCH_CNTR_OFFSET	0x00000838
+#define C_ATU_STS_IB_EPOCH_CNTR	(C_ATU_BASE + C_ATU_STS_IB_EPOCH_CNTR_OFFSET)
+#define C_ATU_STS_IB_EPOCH_CNTR_SIZE	0x00000008
+
+union c_atu_sts_ib_epoch_cntr {
+	__u64 qw;
+	struct {
+		__u64 epoch0  : 16;
+		__u64 epoch1  : 16;
+		__u64 unused  : 32;
+	};
+};
+
+#define C_ATU_STS_ODPQ_OFFSET	0x00000848
+#define C_ATU_STS_ODPQ	(C_ATU_BASE + C_ATU_STS_ODPQ_OFFSET)
+#define C_ATU_STS_ODPQ_SIZE	0x00000008
+
+union c_atu_sts_odpq {
+	__u64 qw;
+	struct {
+		__u64 odpq_space  :  4;
+		__u64: 60;
+	};
+};
+
+#define C_ATU_STS_ATS_VF_DISABLED_OFFSET	0x00000858
+#define C_ATU_STS_ATS_VF_DISABLED	(C_ATU_BASE + C_ATU_STS_ATS_VF_DISABLED_OFFSET)
+#define C_ATU_STS_ATS_VF_DISABLED_SIZE	0x00000008
+
+union c_atu_sts_ats_vf_disabled {
+	__u64 qw;
+	struct {
+		__u64 vf_disabled;
+	};
+};
+
+#define C_ATU_STS_ATS_PF_DISABLED_OFFSET	0x00000860
+#define C_ATU_STS_ATS_PF_DISABLED	(C_ATU_BASE + C_ATU_STS_ATS_PF_DISABLED_OFFSET)
+#define C_ATU_STS_ATS_PF_DISABLED_SIZE	0x00000008
+
+union c_atu_sts_ats_pf_disabled {
+	__u64 qw;
+	struct {
+		__u64 pf_disabled  :  1;
+		__u64: 63;
+	};
+};
+
+#define C_ATU_STS_ATS_INVALQ_OFFSET	0x00000918
+#define C_ATU_STS_ATS_INVALQ	(C_ATU_BASE + C_ATU_STS_ATS_INVALQ_OFFSET)
+#define C_ATU_STS_ATS_INVALQ_SIZE	0x00000008
+
+union c_atu_sts_ats_invalq {
+	__u64 qw;
+	struct {
+		__u64 requester_id        : 16;
+		__u64 vf_num              :  6;
+		__u64: 2;
+		__u64 vf_en               :  1;
+		__u64: 3;
+		__u64 invals_to_process   :  6;
+		__u64: 2;
+		__u64 invalq_count        :  6;
+		__u64 invalq_full         :  1;
+		__u64 invalq_vld          :  1;
+		__u64 state_drive_rsp     :  1;
+		__u64 state_cmpl_wait     :  1;
+		__u64 state_invalidating  :  1;
+		__u64 state_wait_arb      :  1;
+		__u64 state_wait_trig     :  1;
+		__u64: 15;
+	};
+};
+
+#define C_ATU_STS_IXE_IN_PROGRESS_CNTR_OFFSET	0x00000920
+#define C_ATU_STS_IXE_IN_PROGRESS_CNTR	(C_ATU_BASE + C_ATU_STS_IXE_IN_PROGRESS_CNTR_OFFSET)
+#define C_ATU_STS_IXE_IN_PROGRESS_CNTR_SIZE	0x00000008
+
+union c_atu_sts_ixe_in_progress_cntr {
+	__u64 qw;
+	struct {
+		__u64 epoch0  :  9;
+		__u64: 7;
+		__u64 epoch1  :  9;
+		__u64: 39;
+	};
+};
+
+#define C_ATU_STS_OXE_IN_PROGRESS_CNTR_OFFSET	0x00000928
+#define C_ATU_STS_OXE_IN_PROGRESS_CNTR	(C_ATU_BASE + C_ATU_STS_OXE_IN_PROGRESS_CNTR_OFFSET)
+#define C_ATU_STS_OXE_IN_PROGRESS_CNTR_SIZE	0x00000008
+
+union c_atu_sts_oxe_in_progress_cntr {
+	__u64 qw;
+	struct {
+		__u64 epoch0  :  9;
+		__u64: 7;
+		__u64 epoch1  :  9;
+		__u64: 39;
+	};
+};
+
+#define C_ATU_STS_EE_IN_PROGRESS_CNTR_OFFSET	0x00000930
+#define C_ATU_STS_EE_IN_PROGRESS_CNTR	(C_ATU_BASE + C_ATU_STS_EE_IN_PROGRESS_CNTR_OFFSET)
+#define C_ATU_STS_EE_IN_PROGRESS_CNTR_SIZE	0x00000008
+
+union c_atu_sts_ee_in_progress_cntr {
+	__u64 qw;
+	struct {
+		__u64 epoch0  :  9;
+		__u64: 7;
+		__u64 epoch1  :  9;
+		__u64: 39;
+	};
+};
+
+#define C_ATU_STS_ODP_DECOUPLE_OFFSET	0x00000938
+#define C_ATU_STS_ODP_DECOUPLE	(C_ATU_BASE + C_ATU_STS_ODP_DECOUPLE_OFFSET)
+#define C_ATU_STS_ODP_DECOUPLE_SIZE	0x00000008
+
+union c_atu_sts_odp_decouple {
+	__u64 qw;
+	struct {
+		__u64 previous_epoch                :  1;
+		__u64 cmpl_wait_active              :  1;
+		__u64 ixe_at_prev_epoch_cnt_ne0     :  1;
+		__u64 ixe_at_prev_epoch_ip_cnt_eq0  :  1;
+		__u64 ixe_prb_vld                   :  1;
+		__u64 state                         :  2;
+		__u64: 57;
+	};
+};
+
+#define C_ATU_STS_PRB_TABLE_OFFSET(idx)	(0x00020000 + ((idx) * 8))
+#define C_ATU_STS_PRB_TABLE_ENTRIES	512
+#define C_ATU_STS_PRB_TABLE(idx)	(C_ATU_BASE + C_ATU_STS_PRB_TABLE_OFFSET(idx))
+#define C_ATU_STS_PRB_TABLE_SIZE	0x00001000
+
+union c_atu_sts_prb_table {
+	__u64 qw;
+	struct {
+		__u64 acid      : 10;
+		__u64 client    :  2;
+		__u64 addr      : 45;
+		__u64 w         :  1;
+		__u64 r         :  1;
+		__u64 ta_mode   :  2;
+		__u64 odp_mode  :  1;
+		__u64 expired   :  1;
+		__u64 valid     :  1;
+	};
+};
+
+#define C_CQ_CFG_CRNC_OFFSET	0x00000000
+#define C_CQ_CFG_CRNC	(C_CQ_BASE + C_CQ_CFG_CRNC_OFFSET)
+#define C_CQ_CFG_CRNC_SIZE	0x00000008
+
+union c_cq_cfg_crnc {
+	__u64 qw;
+	struct {
+		__u64 csr_timeout   :  8;
+		__u64 mcast_id      : 10;
+		__u64: 1;
+		__u64 mcast_enable  :  1;
+		__u64 mcast_mask    : 10;
+		__u64: 34;
+	};
+};
+
+#define C_CQ_MSC_SHADOW_ACTION_OFFSET	0x00000038
+#define C_CQ_MSC_SHADOW_ACTION	(C_CQ_BASE + C_CQ_MSC_SHADOW_ACTION_OFFSET)
+#define C_CQ_MSC_SHADOW_ACTION_SIZE	0x00000008
+#define C_CQ_MSC_SHADOW_OFFSET	0x00000040
+#define C_CQ_MSC_SHADOW	(C_CQ_BASE + C_CQ_MSC_SHADOW_OFFSET)
+#define C_CQ_MSC_SHADOW_SIZE	0x00000088
+
+union c_cq_msc_shadow {
+	__u64 qw[17];
+};
+
+#define C_CQ_ERR_ELAPSED_TIME_OFFSET	0x00000100
+#define C_CQ_ERR_ELAPSED_TIME	(C_CQ_BASE + C_CQ_ERR_ELAPSED_TIME_OFFSET)
+#define C_CQ_ERR_ELAPSED_TIME_SIZE	0x00000008
+
+union c_cq_err_elapsed_time {
+	__u64 qw;
+	struct {
+		__u64 nanoseconds  : 30;
+		__u64 seconds      : 34;
+	};
+};
+
+#define C_CQ_ERR_FLG_OFFSET	0x00000108
+#define C_CQ_ERR_FLG	(C_CQ_BASE + C_CQ_ERR_FLG_OFFSET)
+#define C_CQ_ERR_FLG_SIZE	0x00000008
+
+union c_cq_err_flg {
+	__u64 qw;
+	struct {
+		__u64 sw_diag                  :  1;
+		__u64 crnc_ring_sync_error     :  1;
+		__u64 crnc_ring_ecc_sbe        :  1;
+		__u64 crnc_ring_ecc_mbe        :  1;
+		__u64 crnc_ring_cmd_unknown    :  1;
+		__u64 crnc_csr_cmd_unknown     :  1;
+		__u64 crnc_csr_cmd_incomplete  :  1;
+		__u64 crnc_buf_ecc_sbe         :  1;
+		__u64 crnc_buf_ecc_mbe         :  1;
+		__u64: 7;
+		__u64 fifo_err                 :  1;
+		__u64 credit_uflw              :  1;
+		__u64 c_state_cor              :  1;
+		__u64 rarb_hdr_cor             :  1;
+		__u64 rarb_data_cor            :  1;
+		__u64 event_ram_cor            :  1;
+		__u64 ll_state_mem_cor         :  1;
+		__u64 ll_status_mem_cor        :  1;
+		__u64 c_state_ucor             :  1;
+		__u64 rarb_hdr_ucor            :  1;
+		__u64 rarb_data_ucor           :  1;
+		__u64 event_ram_ucor           :  1;
+		__u64 ll_state_mem_ucor        :  1;
+		__u64 ll_status_mem_ucor       :  1;
+		__u64 ll_nempty_vectr_ucor     :  1;
+		__u64 ll_full_vectr_ucor       :  1;
+		__u64 event_cnt_ovf            :  1;
+		__u64 tle_oversubscribed       :  1;
+		__u64 rarb_bad_xactn_err       :  1;
+		__u64 rarb_cmpltn_err          :  1;
+		__u64 rarb_tou_wr_hw_err       :  1;
+		__u64 rarb_ll_wr_hw_err        :  1;
+		__u64 rarb_invld_wr_sw_err     :  1;
+		__u64 rarb_tou_wr_sw_err       :  1;
+		__u64 rarb_ll_wr_sw_err        :  1;
+		__u64 msg_cnt_uflw             :  1;
+		__u64 fq_load_uflw             :  1;
+		__u64 wr_ptr_updt_err          :  1;
+		__u64 ard_ptr_update_ucor      :  1;
+		__u64 tx_fqu_free_list_ovf     :  1;
+		__u64 tou_fqu_free_list_ovf    :  1;
+		__u64: 17;
+	};
+};
+
+#define C_CQ_ERR_FIRST_FLG_OFFSET	0x00000110
+#define C_CQ_ERR_FIRST_FLG	(C_CQ_BASE + C_CQ_ERR_FIRST_FLG_OFFSET)
+#define C_CQ_ERR_FIRST_FLG_SIZE	0x00000008
+#define C_CQ_ERR_FIRST_FLG_TS_OFFSET	0x00000118
+#define C_CQ_ERR_FIRST_FLG_TS	(C_CQ_BASE + C_CQ_ERR_FIRST_FLG_TS_OFFSET)
+#define C_CQ_ERR_FIRST_FLG_TS_SIZE	0x00000008
+#define C_CQ_ERR_CLR_OFFSET	0x00000120
+#define C_CQ_ERR_CLR	(C_CQ_BASE + C_CQ_ERR_CLR_OFFSET)
+#define C_CQ_ERR_CLR_SIZE	0x00000008
+#define C_CQ_ERR_IRQA_MSK_OFFSET	0x00000128
+#define C_CQ_ERR_IRQA_MSK	(C_CQ_BASE + C_CQ_ERR_IRQA_MSK_OFFSET)
+#define C_CQ_ERR_IRQA_MSK_SIZE	0x00000008
+#define C_CQ_ERR_IRQB_MSK_OFFSET	0x00000130
+#define C_CQ_ERR_IRQB_MSK	(C_CQ_BASE + C_CQ_ERR_IRQB_MSK_OFFSET)
+#define C_CQ_ERR_IRQB_MSK_SIZE	0x00000008
+#define C_CQ_ERR_INFO_MSK_OFFSET	0x00000140
+#define C_CQ_ERR_INFO_MSK	(C_CQ_BASE + C_CQ_ERR_INFO_MSK_OFFSET)
+#define C_CQ_ERR_INFO_MSK_SIZE	0x00000008
+#define C_CQ_EXT_ERR_FLG_OFFSET	0x00000148
+#define C_CQ_EXT_ERR_FLG	(C_CQ_BASE + C_CQ_EXT_ERR_FLG_OFFSET)
+#define C_CQ_EXT_ERR_FLG_SIZE	0x00000008
+
+union c_cq_ext_err_flg {
+	__u64 qw;
+	struct {
+		__u64 sw_diag                 :  1;
+		__u64 remap_array_cor         :  1;
+		__u64 cprof_table_cor         :  1;
+		__u64 ac_remap_array_cor      :  1;
+		__u64 tou_fq_cmd_cor          :  1;
+		__u64 cq_fq_cmd_cor           :  1;
+		__u64 tou_fid_list_ptrs_cor   :  1;
+		__u64 cq_fid_list_ptrs_cor    :  1;
+		__u64 ll_buf_cor              :  1;
+		__u64 tx_ptr_cor              :  1;
+		__u64 tx_base_cor             :  1;
+		__u64 tx_ocuset_cor           :  1;
+		__u64 tg_ptr_cor              :  1;
+		__u64 tg_base_cor             :  1;
+		__u64 pfq_bufs_cor            :  1;
+		__u64 pfq_bufs_info_cor       :  1;
+		__u64 pfq_ptrs_cor            :  1;
+		__u64 target_pfq_cor          :  1;
+		__u64 tu_pfq_bufs_cor         :  1;
+		__u64 tu_pfq_info_cor         :  1;
+		__u64 tu_pfq_list_ptrs_cor    :  1;
+		__u64 ct_table_cor            :  1;
+		__u64 ee_table_cor            :  1;
+		__u64 ptlte_table_cor         :  1;
+		__u64 ct_events_cor           :  1;
+		__u64 thresh_table_cor        :  1;
+		__u64 trig_ct_field_cor       :  1;
+		__u64 trig_list_nodes_cor     :  1;
+		__u64 tou_ll_reorder_cor      :  1;
+		__u64 tou_cmd_ptrs_cor        :  1;
+		__u64 in_fifo_cor             :  1;
+		__u64 wb_addr_cor             :  1;
+		__u64: 1;
+		__u64 remap_array_ucor        :  1;
+		__u64 cprof_table_ucor        :  1;
+		__u64 ac_remap_array_ucor     :  1;
+		__u64 tou_fq_cmd_ucor         :  1;
+		__u64 cq_fq_cmd_ucor          :  1;
+		__u64 tou_fid_list_ptrs_ucor  :  1;
+		__u64 cq_fid_list_ptrs_ucor   :  1;
+		__u64 ll_buf_ucor             :  1;
+		__u64 tx_ptr_ucor             :  1;
+		__u64 tx_base_ucor            :  1;
+		__u64 tx_ocuset_ucor          :  1;
+		__u64 tg_ptr_ucor             :  1;
+		__u64 tg_base_ucor            :  1;
+		__u64 pfq_bufs_ucor           :  1;
+		__u64 pfq_bufs_info_ucor      :  1;
+		__u64 pfq_ptrs_ucor           :  1;
+		__u64 target_pfq_ucor         :  1;
+		__u64 tu_pfq_bufs_ucor        :  1;
+		__u64 tu_pfq_info_ucor        :  1;
+		__u64 tu_pfq_list_ptrs_ucor   :  1;
+		__u64 ct_table_ucor           :  1;
+		__u64 ee_table_ucor           :  1;
+		__u64 ptlte_table_ucor        :  1;
+		__u64 ct_events_ucor          :  1;
+		__u64 thresh_table_ucor       :  1;
+		__u64 trig_ct_field_ucor      :  1;
+		__u64 trig_list_nodes_ucor    :  1;
+		__u64 tou_ll_reorder_ucor     :  1;
+		__u64 tou_cmd_ptrs_ucor       :  1;
+		__u64 in_fifo_ucor            :  1;
+		__u64 wb_addr_ucor            :  1;
+	};
+};
+
+#define C_CQ_EXT_ERR_FIRST_FLG_OFFSET	0x00000150
+#define C_CQ_EXT_ERR_FIRST_FLG	(C_CQ_BASE + C_CQ_EXT_ERR_FIRST_FLG_OFFSET)
+#define C_CQ_EXT_ERR_FIRST_FLG_SIZE	0x00000008
+#define C_CQ_EXT_ERR_FIRST_FLG_TS_OFFSET	0x00000158
+#define C_CQ_EXT_ERR_FIRST_FLG_TS	(C_CQ_BASE + C_CQ_EXT_ERR_FIRST_FLG_TS_OFFSET)
+#define C_CQ_EXT_ERR_FIRST_FLG_TS_SIZE	0x00000008
+#define C_CQ_EXT_ERR_CLR_OFFSET	0x00000160
+#define C_CQ_EXT_ERR_CLR	(C_CQ_BASE + C_CQ_EXT_ERR_CLR_OFFSET)
+#define C_CQ_EXT_ERR_CLR_SIZE	0x00000008
+#define C_CQ_EXT_ERR_IRQA_MSK_OFFSET	0x00000168
+#define C_CQ_EXT_ERR_IRQA_MSK	(C_CQ_BASE + C_CQ_EXT_ERR_IRQA_MSK_OFFSET)
+#define C_CQ_EXT_ERR_IRQA_MSK_SIZE	0x00000008
+#define C_CQ_EXT_ERR_IRQB_MSK_OFFSET	0x00000170
+#define C_CQ_EXT_ERR_IRQB_MSK	(C_CQ_BASE + C_CQ_EXT_ERR_IRQB_MSK_OFFSET)
+#define C_CQ_EXT_ERR_IRQB_MSK_SIZE	0x00000008
+#define C_CQ_EXT_ERR_INFO_MSK_OFFSET	0x00000180
+#define C_CQ_EXT_ERR_INFO_MSK	(C_CQ_BASE + C_CQ_EXT_ERR_INFO_MSK_OFFSET)
+#define C_CQ_EXT_ERR_INFO_MSK_SIZE	0x00000008
+#define C_CQ_ERR_INFO_MEM_OFFSET	0x00000190
+#define C_CQ_ERR_INFO_MEM	(C_CQ_BASE + C_CQ_ERR_INFO_MEM_OFFSET)
+#define C_CQ_ERR_INFO_MEM_SIZE	0x00000008
+
+union c_cq_err_info_mem {
+	__u64 qw;
+	struct {
+		__u64 cor_syndrome       : 11;
+		__u64: 1;
+		__u64 cor_address        : 12;
+		__u64 cor_mem_id         :  7;
+		__u64 cor_csr_detected   :  1;
+		__u64 ucor_syndrome      : 11;
+		__u64: 1;
+		__u64 ucor_address       : 12;
+		__u64 ucor_mem_id        :  7;
+		__u64 ucor_csr_detected  :  1;
+	};
+};
+
+#define C_CQ_ERR_INFO_FIFO_ERR_OFFSET	0x00000198
+#define C_CQ_ERR_INFO_FIFO_ERR	(C_CQ_BASE + C_CQ_ERR_INFO_FIFO_ERR_OFFSET)
+#define C_CQ_ERR_INFO_FIFO_ERR_SIZE	0x00000008
+
+union c_cq_err_info_fifo_err {
+	__u64 qw;
+	struct {
+		__u64 overrun   :  1;
+		__u64 underrun  :  1;
+		__u64: 6;
+		__u64 fifo_id   :  6;
+		__u64: 50;
+	};
+};
+
+#define C_CQ_ERR_INFO_CC_OFFSET	0x000001a0
+#define C_CQ_ERR_INFO_CC	(C_CQ_BASE + C_CQ_ERR_INFO_CC_OFFSET)
+#define C_CQ_ERR_INFO_CC_SIZE	0x00000008
+
+union c_cq_err_info_cc {
+	__u64 qw;
+	struct {
+		__u64 cc_id   :  5;
+		__u64: 3;
+		__u64 sub_id  :  3;
+		__u64: 53;
+	};
+};
+
+#define C_CQ_ERR_INFO_RARB_OFFSET	0x000001b0
+#define C_CQ_ERR_INFO_RARB	(C_CQ_BASE + C_CQ_ERR_INFO_RARB_OFFSET)
+#define C_CQ_ERR_INFO_RARB_SIZE	0x00000010
+
+union c_cq_err_info_rarb {
+	__u64 qw[2];
+	struct {
+		__u64 bad_xactn_err        :  1;
+		__u64 cmpltn_sts_err       :  1;
+		__u64 cmpltn_ep_err        :  1;
+		__u64 cmpltn_len_err       :  1;
+		__u64 cmpltn_addr_err      :  1;
+		__u64 cmpltn_dv_err        :  1;
+		__u64 cmpltn_eop_err       :  1;
+		__u64 cmpltn_data_mbe_err  :  1;
+		__u64 tou_wr_hw_err        :  1;
+		__u64 invld_wr_sw_err      :  1;
+		__u64 tou_wr_sw_err        :  1;
+		__u64: 5;
+		__u64 msg_type             :  3;
+		__u64: 1;
+		__u64 cmpl_status          :  3;
+		__u64: 1;
+		__u64 ep                   :  1;
+		__u64 dv                   :  1;
+		__u64 eop                  :  1;
+		__u64 data_mbe             :  1;
+		__u64: 4;
+		__u64 tag                  :  9;
+		__u64: 7;
+		__u64 lower_address        :  7;
+		__u64: 9;
+		__u64 first_dw_be          :  4;
+		__u64 last_dw_be           :  4;
+		__u64: 8;
+		__u64 length               : 11;
+		__u64: 7;
+		__u64 addr_29_2            : 28;
+		__u64: 2;
+	};
+};
+
+#define C_CQ_ERR_INFO_RARB_LL_OFFSET	0x000001c0
+#define C_CQ_ERR_INFO_RARB_LL	(C_CQ_BASE + C_CQ_ERR_INFO_RARB_LL_OFFSET)
+#define C_CQ_ERR_INFO_RARB_LL_SIZE	0x00000010
+
+union c_cq_err_info_rarb_ll {
+	__u64 qw[2];
+	struct {
+		__u64 hw_data_uncorr_err  :  1;
+		__u64 hw_early_eop_err    :  1;
+		__u64 hw_missing_eop_err  :  1;
+		__u64 hw_data_valid_err   :  1;
+		__u64 sw_addr_err         :  1;
+		__u64 sw_align_err        :  1;
+		__u64 sw_op_chgd_err      :  1;
+		__u64 sw_offset_err       :  1;
+		__u64 sw_offset_chgd_err  :  1;
+		__u64 sw_overlap_err      :  1;
+		__u64: 6;
+		__u64 ll_op               :  3;
+		__u64: 13;
+		__u64 cq_id               : 10;
+		__u64: 6;
+		__u64 is_tgq              :  1;
+		__u64: 15;
+		__u64 first_dw_be         :  4;
+		__u64 last_dw_be          :  4;
+		__u64: 8;
+		__u64 length              : 11;
+		__u64: 7;
+		__u64 addr_in_pg_15_2     : 14;
+		__u64: 16;
+	};
+};
+
+#define C_CQ_ERR_INFO_OCU_MAP_OFFSET	0x000001d0
+#define C_CQ_ERR_INFO_OCU_MAP	(C_CQ_BASE + C_CQ_ERR_INFO_OCU_MAP_OFFSET)
+#define C_CQ_ERR_INFO_OCU_MAP_SIZE	0x00000008
+
+union c_cq_err_info_ocu_map {
+	__u64 qw;
+	struct {
+		__u64 ocu_id  :  8;
+		__u64 fq_id   :  6;
+		__u64: 50;
+	};
+};
+
+#define C_CQ_ERR_INFO_WR_PTR_UPDT_OFFSET	0x000001d8
+#define C_CQ_ERR_INFO_WR_PTR_UPDT	(C_CQ_BASE + C_CQ_ERR_INFO_WR_PTR_UPDT_OFFSET)
+#define C_CQ_ERR_INFO_WR_PTR_UPDT_SIZE	0x00000008
+
+union c_cq_err_info_wr_ptr_updt {
+	__u64 qw;
+	struct {
+		__u64 invalid_wr_ptr  : 16;
+		__u64 max_ptr         : 16;
+		__u64 cq_id           : 10;
+		__u64: 6;
+		__u64 is_tgq          :  1;
+		__u64: 15;
+	};
+};
+
+#define C_CQ_CFG_INIT_TXQ_HW_STATE_OFFSET	0x00000400
+#define C_CQ_CFG_INIT_TXQ_HW_STATE	(C_CQ_BASE + C_CQ_CFG_INIT_TXQ_HW_STATE_OFFSET)
+#define C_CQ_CFG_INIT_TXQ_HW_STATE_SIZE	0x00000008
+
+union c_cq_cfg_init_txq_hw_state {
+	__u64 qw;
+	struct {
+		__u64 cq_handle  : 10;
+		__u64: 6;
+		__u64 pending    :  1;
+		__u64: 47;
+	};
+};
+
+#define C_CQ_CFG_INIT_TGQ_HW_STATE_OFFSET	0x00000440
+#define C_CQ_CFG_INIT_TGQ_HW_STATE	(C_CQ_BASE + C_CQ_CFG_INIT_TGQ_HW_STATE_OFFSET)
+#define C_CQ_CFG_INIT_TGQ_HW_STATE_SIZE	0x00000008
+
+union c_cq_cfg_init_tgq_hw_state {
+	__u64 qw;
+	struct {
+		__u64 cq_handle  :  9;
+		__u64: 7;
+		__u64 pending    :  1;
+		__u64: 47;
+	};
+};
+
+#define C_CQ_CFG_INIT_CT_HW_STATE_OFFSET	0x00000480
+#define C_CQ_CFG_INIT_CT_HW_STATE	(C_CQ_BASE + C_CQ_CFG_INIT_CT_HW_STATE_OFFSET)
+#define C_CQ_CFG_INIT_CT_HW_STATE_SIZE	0x00000008
+
+union c_cq_cfg_init_ct_hw_state {
+	__u64 qw;
+	struct {
+		__u64 ct_handle  : 11;
+		__u64 init       :  1;
+		__u64 cancel     :  1;
+		__u64: 3;
+		__u64 pending    :  1;
+		__u64: 47;
+	};
+};
+
+#define C_CQ_CFG_TLE_POOL_OFFSET(idx)	(0x00000500 + ((idx) * 8))
+#define C_CQ_CFG_TLE_POOL_ENTRIES	4
+#define C_CQ_CFG_TLE_POOL(idx)	(C_CQ_BASE + C_CQ_CFG_TLE_POOL_OFFSET(idx))
+#define C_CQ_CFG_TLE_POOL_SIZE	0x00000020
+
+union c_cq_cfg_tle_pool {
+	__u64 qw;
+	struct {
+		__u64 num_reserved  : 12;
+		__u64: 4;
+		__u64 in_use        :  8;
+		__u64: 8;
+		__u64 max_alloc     : 12;
+		__u64: 20;
+	};
+};
+
+#define C_CQ_CFG_STS_TLE_SHARED_OFFSET	0x00000520
+#define C_CQ_CFG_STS_TLE_SHARED	(C_CQ_BASE + C_CQ_CFG_STS_TLE_SHARED_OFFSET)
+#define C_CQ_CFG_STS_TLE_SHARED_SIZE	0x00000008
+
+union c_cq_cfg_sts_tle_shared {
+	__u64 qw;
+	struct {
+		__u64 num_shared            : 12;
+		__u64: 20;
+		__u64 num_shared_allocated  : 12;
+		__u64: 4;
+		__u64 num_total_allocated   : 12;
+		__u64: 4;
+	};
+};
+
+#define C_CQ_CFG_CREDIT_LIMITS_OFFSET	0x00000530
+#define C_CQ_CFG_CREDIT_LIMITS	(C_CQ_BASE + C_CQ_CFG_CREDIT_LIMITS_OFFSET)
+#define C_CQ_CFG_CREDIT_LIMITS_SIZE	0x00000010
+
+union c_cq_cfg_credit_limits {
+	__u64 qw[2];
+	struct {
+		__u64 lpe_cmd_credits             : 10;
+		__u64: 6;
+		__u64 lpe_rcv_fifo_credits        :  4;
+		__u64: 4;
+		__u64 ee_event_credits            :  5;
+		__u64: 11;
+		__u64 tou_fq_credits              :  7;
+		__u64: 1;
+		__u64 tarb_p_credits              :  5;
+		__u64: 3;
+		__u64 tarb_np_credits             :  5;
+		__u64: 3;
+		__u64 prefetch_tou_credits        :  5;
+		__u64: 3;
+		__u64 tou_wb_credits              :  5;
+		__u64: 3;
+		__u64 tou_event_credits           :  3;
+		__u64: 5;
+		__u64 tgq_cmd_fail_event_credits  :  3;
+		__u64: 5;
+		__u64 txq_cmd_fail_event_credits  :  4;
+		__u64: 4;
+		__u64 tou_cmd_fail_event_credits  :  3;
+		__u64: 5;
+		__u64 fq_tot_credits              :  9;
+		__u64: 7;
+	};
+};
+
+#define C_CQ_CFG_EVENT_CNTS_OFFSET	0x00000540
+#define C_CQ_CFG_EVENT_CNTS	(C_CQ_BASE + C_CQ_CFG_EVENT_CNTS_OFFSET)
+#define C_CQ_CFG_EVENT_CNTS_SIZE	0x00000008
+
+union c_cq_cfg_event_cnts {
+	__u64 qw;
+	struct {
+		__u64 enable     :  1;
+		__u64 init       :  1;
+		__u64 init_done  :  1;
+		__u64: 1;
+		__u64 ovf_cnt    : 16;
+		__u64: 44;
+	};
+};
+
+#define C_CQ_TXQ_BASE_TABLE_OFFSET(idx)	(0x00010000 + ((idx) * 16))
+#define C_CQ_TXQ_BASE_TABLE_ENTRIES	1024
+#define C_CQ_TXQ_BASE_TABLE(idx)	(C_CQ_BASE + C_CQ_TXQ_BASE_TABLE_OFFSET(idx))
+#define C_CQ_TXQ_BASE_TABLE_SIZE	0x00004000
+
+union c_cq_txq_base_table {
+	__u64 qw[2];
+	struct {
+		__u64 mem_q_eq             : 11;
+		__u64: 1;
+		__u64 mem_q_base           : 45;
+		__u64: 7;
+		__u64 mem_q_max_ptr        : 16;
+		__u64 mem_q_rgid           :  8;
+		__u64: 1;
+		__u64: 1;
+		__u64 mem_q_stat_cnt_pool  :  2;
+		__u64: 8;
+		__u64 mem_q_pfq            :  6;
+		__u64: 2;
+		__u64 mem_q_lcid           :  4;
+		__u64 mem_q_acid           : 10;
+		__u64 mem_q_policy         :  2;
+		__u64: 4;
+	};
+};
+
+#define C_CQ_TXQ_ENABLE_OFFSET(idx)	(0x00002000 + ((idx) * 8))
+#define C_CQ_TXQ_ENABLE_ENTRIES	1024
+#define C_CQ_TXQ_ENABLE(idx)	(C_CQ_BASE + C_CQ_TXQ_ENABLE_OFFSET(idx))
+#define C_CQ_TXQ_ENABLE_SIZE	0x00002000
+
+union c_cq_txq_enable {
+	__u64 qw;
+	struct {
+		__u64 txq_enable  :  1;
+		__u64 drain       :  1;
+		__u64 fence       :  1;
+		__u64: 61;
+	};
+};
+
+#define C_CQ_TXQ_TC_TABLE_OFFSET(idx)	(0x00016000 + ((idx) * 8))
+#define C_CQ_TXQ_TC_TABLE_ENTRIES	1024
+#define C_CQ_TXQ_TC_TABLE(idx)	(C_CQ_BASE + C_CQ_TXQ_TC_TABLE_OFFSET(idx))
+#define C_CQ_TXQ_TC_TABLE_SIZE	0x00002000
+
+union c_cq_txq_tc_table {
+	__u64 qw;
+	struct {
+		__u64 mem_q_tc    :  3;
+		__u64 mem_q_trig  :  1;
+		__u64 mem_q_eth   :  1;
+		__u64: 59;
+	};
+};
+
+#define C_CQ_TXQ_WRPTR_TABLE_OFFSET(idx)	(0x00018000 + ((idx) * 8))
+#define C_CQ_TXQ_WRPTR_TABLE_ENTRIES	1024
+#define C_CQ_TXQ_WRPTR_TABLE(idx)	(C_CQ_BASE + C_CQ_TXQ_WRPTR_TABLE_OFFSET(idx))
+#define C_CQ_TXQ_WRPTR_TABLE_SIZE	0x00002000
+
+union c_cq_txq_wrptr_table {
+	__u64 qw;
+	struct {
+		__u64 mem_q_wr_ptr  : 16;
+		__u64: 48;
+	};
+};
+
+#define C_CQ_TXQ_RDPTR_TABLE_OFFSET(idx)	(0x00090000 + ((idx) * 8))
+#define C_CQ_TXQ_RDPTR_TABLE_ENTRIES	1024
+#define C_CQ_TXQ_RDPTR_TABLE(idx)	(C_CQ_BASE + C_CQ_TXQ_RDPTR_TABLE_OFFSET(idx))
+#define C_CQ_TXQ_RDPTR_TABLE_SIZE	0x00002000
+
+union c_cq_txq_rdptr_table {
+	__u64 qw;
+	struct {
+		__u64 mem_q_rd_ptr  : 16;
+		__u64: 48;
+	};
+};
+
+#define C_CQ_TXQ_PREPTR_TABLE_OFFSET(idx)	(0x00070000 + ((idx) * 8))
+#define C_CQ_TXQ_PREPTR_TABLE_ENTRIES	1024
+#define C_CQ_TXQ_PREPTR_TABLE(idx)	(C_CQ_BASE + C_CQ_TXQ_PREPTR_TABLE_OFFSET(idx))
+#define C_CQ_TXQ_PREPTR_TABLE_SIZE	0x00002000
+
+union c_cq_txq_preptr_table {
+	__u64 qw;
+	struct {
+		__u64 mem_q_pre_ptr      : 16;
+		__u64 mem_q_pre_ptr_par  :  1;
+		__u64: 47;
+	};
+};
+
+#define C_CQ_TXQ_ACK_CTR_OFFSET(idx)	(0x00094000 + ((idx) * 8))
+#define C_CQ_TXQ_ACK_CTR_ENTRIES	1024
+#define C_CQ_TXQ_ACK_CTR(idx)	(C_CQ_BASE + C_CQ_TXQ_ACK_CTR_OFFSET(idx))
+#define C_CQ_TXQ_ACK_CTR_SIZE	0x00002000
+
+union c_cq_txq_ack_ctr {
+	__u64 qw;
+	struct {
+		__u64 mem_q_ack_ctr  : 12;
+		__u64: 52;
+	};
+};
+
+#define C_CQ_TGQ_TABLE_OFFSET(idx)	(0x0001a000 + ((idx) * 16))
+#define C_CQ_TGQ_TABLE_ENTRIES	512
+#define C_CQ_TGQ_TABLE(idx)	(C_CQ_BASE + C_CQ_TGQ_TABLE_OFFSET(idx))
+#define C_CQ_TGQ_TABLE_SIZE	0x00002000
+
+union c_cq_tgq_table {
+	__u64 qw[2];
+	struct {
+		__u64 mem_q_eq             : 11;
+		__u64: 1;
+		__u64 mem_q_base           : 45;
+		__u64: 7;
+		__u64 mem_q_max_ptr        : 16;
+		__u64 mem_q_rgid           :  8;
+		__u64: 1;
+		__u64: 1;
+		__u64 mem_q_stat_cnt_pool  :  2;
+		__u64 mem_q_tc_reg         :  3;
+		__u64: 17;
+		__u64 mem_q_acid           : 10;
+		__u64 mem_q_policy         :  2;
+		__u64: 4;
+	};
+};
+
+#define C_CQ_TGQ_ENABLE_OFFSET(idx)	(0x00004000 + ((idx) * 8))
+#define C_CQ_TGQ_ENABLE_ENTRIES	512
+#define C_CQ_TGQ_ENABLE(idx)	(C_CQ_BASE + C_CQ_TGQ_ENABLE_OFFSET(idx))
+#define C_CQ_TGQ_ENABLE_SIZE	0x00001000
+
+union c_cq_tgq_enable {
+	__u64 qw;
+	struct {
+		__u64 tgq_enable  :  1;
+		__u64 drain       :  1;
+		__u64: 62;
+	};
+};
+
+#define C_CQ_TGQ_WRPTR_TABLE_OFFSET(idx)	(0x0001c000 + ((idx) * 8))
+#define C_CQ_TGQ_WRPTR_TABLE_ENTRIES	512
+#define C_CQ_TGQ_WRPTR_TABLE(idx)	(C_CQ_BASE + C_CQ_TGQ_WRPTR_TABLE_OFFSET(idx))
+#define C_CQ_TGQ_WRPTR_TABLE_SIZE	0x00001000
+
+union c_cq_tgq_wrptr_table {
+	__u64 qw;
+	struct {
+		__u64 mem_q_wr_ptr  : 16;
+		__u64: 48;
+	};
+};
+
+#define C_CQ_TGQ_RDPTR_TABLE_OFFSET(idx)	(0x00092000 + ((idx) * 8))
+#define C_CQ_TGQ_RDPTR_TABLE_ENTRIES	512
+#define C_CQ_TGQ_RDPTR_TABLE(idx)	(C_CQ_BASE + C_CQ_TGQ_RDPTR_TABLE_OFFSET(idx))
+#define C_CQ_TGQ_RDPTR_TABLE_SIZE	0x00001000
+
+union c_cq_tgq_rdptr_table {
+	__u64 qw;
+	struct {
+		__u64 mem_q_rd_ptr  : 16;
+		__u64: 48;
+	};
+};
+
+#define C_CQ_TGQ_PREPTR_TABLE_OFFSET(idx)	(0x00072000 + ((idx) * 8))
+#define C_CQ_TGQ_PREPTR_TABLE_ENTRIES	512
+#define C_CQ_TGQ_PREPTR_TABLE(idx)	(C_CQ_BASE + C_CQ_TGQ_PREPTR_TABLE_OFFSET(idx))
+#define C_CQ_TGQ_PREPTR_TABLE_SIZE	0x00001000
+
+union c_cq_tgq_preptr_table {
+	__u64 qw;
+	struct {
+		__u64 mem_q_pre_ptr      : 16;
+		__u64 mem_q_pre_ptr_par  :  1;
+		__u64: 47;
+	};
+};
+
+#define C_CQ_TGQ_ACK_CTR_OFFSET(idx)	(0x00096000 + ((idx) * 8))
+#define C_CQ_TGQ_ACK_CTR_ENTRIES	512
+#define C_CQ_TGQ_ACK_CTR(idx)	(C_CQ_BASE + C_CQ_TGQ_ACK_CTR_OFFSET(idx))
+#define C_CQ_TGQ_ACK_CTR_SIZE	0x00001000
+
+union c_cq_tgq_ack_ctr {
+	__u64 qw;
+	struct {
+		__u64 mem_q_ack_ctr  : 12;
+		__u64: 4;
+		__u64 append_ctr     : 14;
+		__u64: 34;
+	};
+};
+
+#define C_CQ_CFG_CQ_POLICY_OFFSET	0x00000640
+#define C_CQ_CFG_CQ_POLICY	(C_CQ_BASE + C_CQ_CFG_CQ_POLICY_OFFSET)
+#define C_CQ_CFG_CQ_POLICY_SIZE	0x00000008
+
+union c_cq_cfg_cq_policy {
+	__u64 qw;
+	struct {
+		struct {
+			__u8 shift  :  4;
+			__u8 empty  :  1;
+			__u8:  3;
+		} policy[4];
+		__u32 unused;
+	};
+};
+
+#define C_CQ_CFG_CP_TABLE_OFFSET(idx)	(0x0001d000 + ((idx) * 8))
+#define C_CQ_CFG_CP_TABLE_ENTRIES	256
+#define C_CQ_CFG_CP_TABLE(idx)	(C_CQ_BASE + C_CQ_CFG_CP_TABLE_OFFSET(idx))
+#define C_CQ_CFG_CP_TABLE_SIZE	0x00000800
+
+union c_cq_cfg_cp_table {
+	__u64 qw;
+	struct {
+		__u64 vni           : 16;
+		__u64 dscp_unrsto   :  6;
+		__u64: 2;
+		__u64 dscp_rstuno   :  6;
+		__u64: 2;
+		__u64 hrp_vld       :  1;
+		__u64 smt_disabled  :  1;
+		__u64 sct_disabled  :  1;
+		__u64 srb_disabled  :  1;
+		__u64 valid         :  1;
+		__u64: 27;
+	};
+};
+
+#define C_CQ_CFG_CP_FL_TABLE_OFFSET(idx)	(0x0001d800 + ((idx) * 8))
+#define C_CQ_CFG_CP_FL_TABLE_ENTRIES	256
+#define C_CQ_CFG_CP_FL_TABLE(idx)	(C_CQ_BASE + C_CQ_CFG_CP_FL_TABLE_OFFSET(idx))
+#define C_CQ_CFG_CP_FL_TABLE_SIZE	0x00000800
+
+union c_cq_cfg_cp_fl_table {
+	__u64 qw;
+	struct {
+		__u64 pfq   :  6;
+		__u64: 2;
+		__u64 tc    :  3;
+		__u64: 53;
+	};
+};
+
+#define C_CQ_CFG_CT_WB_MEM_ADDR_OFFSET(idx)	(0x00080000 + ((idx) * 8))
+#define C_CQ_CFG_CT_WB_MEM_ADDR_ENTRIES	2048
+#define C_CQ_CFG_CT_WB_MEM_ADDR(idx)	(C_CQ_BASE + C_CQ_CFG_CT_WB_MEM_ADDR_OFFSET(idx))
+#define C_CQ_CFG_CT_WB_MEM_ADDR_SIZE	0x00004000
+
+union c_cq_cfg_ct_wb_mem_addr {
+	__u64 qw;
+	struct {
+		__u64 wb_mem_context  : 10;
+		__u64 wb_mem_addr     : 54;
+	};
+};
+
+#define C_CQ_CFG_CT_ENABLE_OFFSET(idx)	(0x00088000 + ((idx) * 8))
+#define C_CQ_CFG_CT_ENABLE_ENTRIES	2048
+#define C_CQ_CFG_CT_ENABLE(idx)	(C_CQ_BASE + C_CQ_CFG_CT_ENABLE_OFFSET(idx))
+#define C_CQ_CFG_CT_ENABLE_SIZE	0x00004000
+
+union c_cq_cfg_ct_enable {
+	__u64 qw;
+	struct {
+		__u64 ct_enable  :  1;
+		__u64: 63;
+	};
+};
+
+#define C_CQ_CFG_CID_ARRAY_OFFSET(idx)	(0x00050000 + ((idx) * 8))
+#define C_CQ_CFG_CID_ARRAY_ENTRIES	4096
+#define C_CQ_CFG_CID_ARRAY(idx)	(C_CQ_BASE + C_CQ_CFG_CID_ARRAY_OFFSET(idx))
+#define C_CQ_CFG_CID_ARRAY_SIZE	0x00008000
+
+union c_cq_cfg_cid_array {
+	__u64 qw;
+	struct {
+		__u64 cid   :  8;
+		__u64: 56;
+	};
+};
+
+#define C_CQ_CFG_AC_ARRAY_OFFSET(idx)	(0x00060000 + ((idx) * 8))
+#define C_CQ_CFG_AC_ARRAY_ENTRIES	2048
+#define C_CQ_CFG_AC_ARRAY(idx)	(C_CQ_BASE + C_CQ_CFG_AC_ARRAY_OFFSET(idx))
+#define C_CQ_CFG_AC_ARRAY_SIZE	0x00004000
+
+union c_cq_cfg_ac_array {
+	__u64 qw;
+	struct {
+		__u64 ac    : 10;
+		__u64: 54;
+	};
+};
+
+#define C_CQ_CFG_PFQ_THRESH_TABLE_OFFSET(idx)	(0x0001e000 + ((idx) * 8))
+#define C_CQ_CFG_PFQ_THRESH_TABLE_ENTRIES	48
+#define C_CQ_CFG_PFQ_THRESH_TABLE(idx)	(C_CQ_BASE + C_CQ_CFG_PFQ_THRESH_TABLE_OFFSET(idx))
+#define C_CQ_CFG_PFQ_THRESH_TABLE_SIZE	0x00000180
+
+union c_cq_cfg_pfq_thresh_table {
+	__u64 qw;
+	struct {
+		__u64 high_thresh  :  9;
+		__u64: 7;
+		__u64 buf_cnt      : 10;
+		__u64: 38;
+	};
+};
+
+#define C_CQ_CFG_FQ_THRESH_TABLE_OFFSET(idx)	(0x0001e200 + ((idx) * 8))
+#define C_CQ_CFG_FQ_THRESH_TABLE_ENTRIES	48
+#define C_CQ_CFG_FQ_THRESH_TABLE(idx)	(C_CQ_BASE + C_CQ_CFG_FQ_THRESH_TABLE_OFFSET(idx))
+#define C_CQ_CFG_FQ_THRESH_TABLE_SIZE	0x00000180
+
+union c_cq_cfg_fq_thresh_table {
+	__u64 qw;
+	struct {
+		__u64 thresh  : 41;
+		__u64: 23;
+	};
+};
+
+#define C_CQ_CFG_PFQ_TC_MAP_OFFSET(idx)	(0x0001e400 + ((idx) * 8))
+#define C_CQ_CFG_PFQ_TC_MAP_ENTRIES	48
+#define C_CQ_CFG_PFQ_TC_MAP(idx)	(C_CQ_BASE + C_CQ_CFG_PFQ_TC_MAP_OFFSET(idx))
+#define C_CQ_CFG_PFQ_TC_MAP_SIZE	0x00000180
+
+union c_cq_cfg_pfq_tc_map {
+	__u64 qw;
+	struct {
+		__u64 pfq_tc  :  3;
+		__u64: 61;
+	};
+};
+
+#define C_CQ_CFG_OCUSET_OCU_TABLE_OFFSET(idx)	(0x0001e800 + ((idx) * 8))
+#define C_CQ_CFG_OCUSET_OCU_TABLE_ENTRIES	48
+#define C_CQ_CFG_OCUSET_OCU_TABLE(idx)	(C_CQ_BASE + C_CQ_CFG_OCUSET_OCU_TABLE_OFFSET(idx))
+#define C_CQ_CFG_OCUSET_OCU_TABLE_SIZE	0x00000180
+
+union c_cq_cfg_ocuset_ocu_table {
+	__u64 qw;
+	struct {
+		__u64 ocu_base    :  8;
+		__u64 ocu_count   :  4;
+		__u64 ocu_static  :  1;
+		__u64: 51;
+	};
+};
+
+#define C_CQ_CFG_OCU_HASH_MASK_OFFSET	0x00039050
+#define C_CQ_CFG_OCU_HASH_MASK	(C_CQ_BASE + C_CQ_CFG_OCU_HASH_MASK_OFFSET)
+#define C_CQ_CFG_OCU_HASH_MASK_SIZE	0x00000008
+
+union c_cq_cfg_ocu_hash_mask {
+	__u64 qw;
+	struct {
+		__u64 dfa   : 32;
+		__u64 vni   : 16;
+		__u64 dscp  :  6;
+		__u64: 10;
+	};
+};
+
+#define C_CQ_CFG_OCUSET_FQ_TABLE_OFFSET(idx)	(0x0001f000 + ((idx) * 8))
+#define C_CQ_CFG_OCUSET_FQ_TABLE_ENTRIES	48
+#define C_CQ_CFG_OCUSET_FQ_TABLE(idx)	(C_CQ_BASE + C_CQ_CFG_OCUSET_FQ_TABLE_OFFSET(idx))
+#define C_CQ_CFG_OCUSET_FQ_TABLE_SIZE	0x00000180
+
+union c_cq_cfg_ocuset_fq_table {
+	__u64 qw;
+	struct {
+		__u64 fq_count  :  4;
+		__u64: 60;
+	};
+};
+
+#define C_CQ_CFG_OCU_TABLE_OFFSET(idx)	(0x0001f800 + ((idx) * 8))
+#define C_CQ_CFG_OCU_TABLE_ENTRIES	256
+#define C_CQ_CFG_OCU_TABLE(idx)	(C_CQ_BASE + C_CQ_CFG_OCU_TABLE_OFFSET(idx))
+#define C_CQ_CFG_OCU_TABLE_SIZE	0x00000800
+
+union c_cq_cfg_ocu_table {
+	__u64 qw;
+	struct {
+		__u64 msg_count  : 11;
+		__u64: 1;
+		__u64 fq_saved   :  6;
+		__u64: 2;
+		__u64 fq         :  6;
+		__u64: 38;
+	};
+};
+
+#define C_CQ_CFG_CT_RGID_TABLE_OFFSET(idx)	(0x00020000 + ((idx) * 8))
+#define C_CQ_CFG_CT_RGID_TABLE_ENTRIES	2048
+#define C_CQ_CFG_CT_RGID_TABLE(idx)	(C_CQ_BASE + C_CQ_CFG_CT_RGID_TABLE_OFFSET(idx))
+#define C_CQ_CFG_CT_RGID_TABLE_SIZE	0x00004000
+
+union c_cq_cfg_ct_rgid_table {
+	__u64 qw;
+	struct {
+		__u64 rgid  :  8;
+		__u64: 56;
+	};
+};
+
+#define C_CQ_CFG_PTLTE_RGID_TABLE_OFFSET(idx)	(0x00028000 + ((idx) * 8))
+#define C_CQ_CFG_PTLTE_RGID_TABLE_ENTRIES	2048
+#define C_CQ_CFG_PTLTE_RGID_TABLE(idx)	(C_CQ_BASE + C_CQ_CFG_PTLTE_RGID_TABLE_OFFSET(idx))
+#define C_CQ_CFG_PTLTE_RGID_TABLE_SIZE	0x00004000
+
+union c_cq_cfg_ptlte_rgid_table {
+	__u64 qw;
+	struct {
+		__u64 rgid  :  8;
+		__u64: 56;
+	};
+};
+
+#define C_CQ_CFG_EQ_RGID_TABLE_OFFSET(idx)	(0x00030000 + ((idx) * 8))
+#define C_CQ_CFG_EQ_RGID_TABLE_ENTRIES	2048
+#define C_CQ_CFG_EQ_RGID_TABLE(idx)	(C_CQ_BASE + C_CQ_CFG_EQ_RGID_TABLE_OFFSET(idx))
+#define C_CQ_CFG_EQ_RGID_TABLE_SIZE	0x00004000
+
+union c_cq_cfg_eq_rgid_table {
+	__u64 qw;
+	struct {
+		__u64 rgid  :  8;
+		__u64: 56;
+	};
+};
+
+#define C_CQ_CFG_TG_THRESH_OFFSET	0x00038000
+#define C_CQ_CFG_TG_THRESH	(C_CQ_BASE + C_CQ_CFG_TG_THRESH_OFFSET)
+#define C_CQ_CFG_TG_THRESH_SIZE	0x00000008
+
+union c_cq_cfg_tg_thresh {
+	__u64 qw;
+	struct {
+		struct {
+			__u16 thresh : 14;
+			__u16:  2;
+		} tg[4];
+	};
+};
+
+#define C_CQ_CFG_FQ_RESRV_OFFSET(idx)	(0x00039000 + ((idx) * 8))
+#define C_CQ_CFG_FQ_RESRV_ENTRIES	8
+#define C_CQ_CFG_FQ_RESRV(idx)	(C_CQ_BASE + C_CQ_CFG_FQ_RESRV_OFFSET(idx))
+#define C_CQ_CFG_FQ_RESRV_SIZE	0x00000040
+
+union c_cq_cfg_fq_resrv {
+	__u64 qw;
+	struct {
+		__u64 num_reserved  :  8;
+		__u64 max_alloc     :  9;
+		__u64: 3;
+		__u64 num_alloc     :  9;
+		__u64: 35;
+	};
+};
+
+#define C_CQ_CFG_THRESH_MAP_OFFSET(idx)	(0x00040000 + ((idx) * 8))
+#define C_CQ_CFG_THRESH_MAP_ENTRIES	512
+#define C_CQ_CFG_THRESH_MAP(idx)	(C_CQ_BASE + C_CQ_CFG_THRESH_MAP_OFFSET(idx))
+#define C_CQ_CFG_THRESH_MAP_SIZE	0x00001000
+
+union c_cq_cfg_thresh_map {
+	__u64 qw;
+	struct {
+		__u64 thresh_id  :  2;
+		__u64: 62;
+	};
+};
+
+#define C_CQ_STS_INIT_DONE_OFFSET	0x00049ff8
+#define C_CQ_STS_INIT_DONE	(C_CQ_BASE + C_CQ_STS_INIT_DONE_OFFSET)
+#define C_CQ_STS_INIT_DONE_SIZE	0x00000008
+
+union c_cq_sts_init_done {
+	__u64 qw;
+	struct {
+		__u64 cq_init_done   :  1;
+		__u64 tou_init_done  :  1;
+		__u64: 62;
+	};
+};
+
+#define C_CQ_STS_TLE_IN_USE_OFFSET(idx)	(0x00000850 + ((idx) * 8))
+#define C_CQ_STS_TLE_IN_USE_ENTRIES	4
+#define C_CQ_STS_TLE_IN_USE(idx)	(C_CQ_BASE + C_CQ_STS_TLE_IN_USE_OFFSET(idx))
+#define C_CQ_STS_TLE_IN_USE_SIZE	0x00000020
+
+union c_cq_sts_tle_in_use {
+	__u64 qw;
+	struct {
+		__u64 count  : 12;
+		__u64: 52;
+	};
+};
+
+#define C_CQ_STS_MAX_TLE_IN_USE_OFFSET(idx)	(0x00000870 + ((idx) * 8))
+#define C_CQ_STS_MAX_TLE_IN_USE_ENTRIES	4
+#define C_CQ_STS_MAX_TLE_IN_USE(idx)	(C_CQ_BASE + C_CQ_STS_MAX_TLE_IN_USE_OFFSET(idx))
+#define C_CQ_STS_MAX_TLE_IN_USE_SIZE	0x00000020
+
+union c_cq_sts_max_tle_in_use {
+	__u64 qw;
+	struct {
+		__u64 max   : 12;
+		__u64: 52;
+	};
+};
+
+#define C_CQ_STS_CREDITS_IN_USE_OFFSET	0x000008b0
+#define C_CQ_STS_CREDITS_IN_USE	(C_CQ_BASE + C_CQ_STS_CREDITS_IN_USE_OFFSET)
+#define C_CQ_STS_CREDITS_IN_USE_SIZE	0x00000010
+
+union c_cq_sts_credits_in_use {
+	__u64 qw[2];
+	struct {
+		__u64 lpe_cmd_credits             : 10;
+		__u64: 6;
+		__u64 lpe_rcv_fifo_credits        :  4;
+		__u64: 4;
+		__u64 ee_event_credits            :  5;
+		__u64: 11;
+		__u64 tou_fq_credits              :  7;
+		__u64: 1;
+		__u64 tarb_p_credits              :  5;
+		__u64: 3;
+		__u64 tarb_np_credits             :  5;
+		__u64: 3;
+		__u64 prefetch_tou_credits        :  5;
+		__u64: 3;
+		__u64 tou_wb_credits              :  5;
+		__u64: 3;
+		__u64 tou_event_credits           :  3;
+		__u64: 5;
+		__u64 tgq_cmd_fail_event_credits  :  3;
+		__u64: 5;
+		__u64 txq_cmd_fail_event_credits  :  4;
+		__u64 tou_cmd_fail_event_credits  :  3;
+		__u64: 1;
+		__u64 fq_tot_credits              :  9;
+		__u64: 3;
+		__u64 fq_sh_credits               :  9;
+		__u64: 3;
+	};
+};
+
+#define C_CQ_STS_EVENT_CNTS_OFFSET(idx)	(0x00100000 + ((idx) * 8))
+#ifndef C_CQ_STS_EVENT_CNTS_ENTRIES
+#define C_CQ_STS_EVENT_CNTS_ENTRIES	512
+#endif
+#define C_CQ_STS_EVENT_CNTS(idx)	(C_CQ_BASE + C_CQ_STS_EVENT_CNTS_OFFSET(idx))
+#define C_CQ_STS_EVENT_CNTS_SIZE	0x00001000
+
+union c_cq_sts_event_cnts {
+	__u64 qw;
+	struct {
+		__u64 cnt  : 56;
+		__u64: 8;
+	};
+};
+
+#define C_EE_CFG_CRNC_OFFSET	0x00000000
+#define C_EE_CFG_CRNC	(C_EE_BASE + C_EE_CFG_CRNC_OFFSET)
+#define C_EE_CFG_CRNC_SIZE	0x00000008
+
+union c_ee_cfg_crnc {
+	__u64 qw;
+	struct {
+		__u64 csr_timeout   :  8;
+		__u64 mcast_id      : 10;
+		__u64: 1;
+		__u64 mcast_enable  :  1;
+		__u64 mcast_mask    : 10;
+		__u64: 34;
+	};
+};
+
+#define C_EE_CFG_RT_OFFSET_OFFSET	0x00000020
+#define C_EE_CFG_RT_OFFSET	(C_EE_BASE + C_EE_CFG_RT_OFFSET_OFFSET)
+#define C_EE_CFG_RT_OFFSET_SIZE	0x00000008
+
+union c_ee_cfg_rt_offset {
+	__u64 qw;
+	struct {
+		__u64 seconds  : 48;
+		__u64: 16;
+	};
+};
+
+#define C_EE_MSC_SHADOW_ACTION_OFFSET	0x00000038
+#define C_EE_MSC_SHADOW_ACTION	(C_EE_BASE + C_EE_MSC_SHADOW_ACTION_OFFSET)
+#define C_EE_MSC_SHADOW_ACTION_SIZE	0x00000008
+#define C_EE_MSC_SHADOW_OFFSET	0x00000040
+#define C_EE_MSC_SHADOW	(C_EE_BASE + C_EE_MSC_SHADOW_OFFSET)
+#define C_EE_MSC_SHADOW_SIZE	0x00000040
+
+union c_ee_msc_shadow {
+	__u64 qw[8];
+};
+
+#define C_EE_ERR_ELAPSED_TIME_OFFSET	0x00000100
+#define C_EE_ERR_ELAPSED_TIME	(C_EE_BASE + C_EE_ERR_ELAPSED_TIME_OFFSET)
+#define C_EE_ERR_ELAPSED_TIME_SIZE	0x00000008
+
+union c_ee_err_elapsed_time {
+	__u64 qw;
+	struct {
+		__u64 nanoseconds  : 30;
+		__u64 seconds      : 34;
+	};
+};
+
+#define C_EE_ERR_FLG_OFFSET	0x00000108
+#define C_EE_ERR_FLG	(C_EE_BASE + C_EE_ERR_FLG_OFFSET)
+#define C_EE_ERR_FLG_SIZE	0x00000008
+
+union c_ee_err_flg {
+	__u64 qw;
+	struct {
+		__u64 sw_diag                  :  1;
+		__u64 crnc_ring_sync_error     :  1;
+		__u64 crnc_ring_ecc_sbe        :  1;
+		__u64 crnc_ring_ecc_mbe        :  1;
+		__u64 crnc_ring_cmd_unknown    :  1;
+		__u64 crnc_csr_cmd_unknown     :  1;
+		__u64 crnc_csr_cmd_incomplete  :  1;
+		__u64 crnc_buf_ecc_sbe         :  1;
+		__u64 crnc_buf_ecc_mbe         :  1;
+		__u64: 23;
+		__u64 eq_ovflw_rsrvn           :  1;
+		__u64 eq_ovflw_fc_sc           :  1;
+		__u64 eq_ovflw_ordinary        :  1;
+		__u64 eq_dsabld_event          :  1;
+		__u64 eq_dsabld_sw_state_wr    :  1;
+		__u64 eq_dsabld_lpe_query      :  1;
+		__u64 eq_rsrvn_uflw            :  1;
+		__u64 unxpctd_trnsltn_rsp      :  1;
+		__u64 rarb_hw_err              :  1;
+		__u64 rarb_sw_err              :  1;
+		__u64 tarb_err                 :  1;
+		__u64 eq_state_ucor            :  1;
+		__u64: 4;
+		__u64 unxpctd_cq_cdt           :  1;
+		__u64 unxpctd_tarb_cdt         :  1;
+		__u64 eq_state_updt_urun       :  1;
+		__u64 eq_state_updt_orun       :  1;
+		__u64: 12;
+	};
+};
+
+#define C_EE_ERR_FIRST_FLG_OFFSET	0x00000110
+#define C_EE_ERR_FIRST_FLG	(C_EE_BASE + C_EE_ERR_FIRST_FLG_OFFSET)
+#define C_EE_ERR_FIRST_FLG_SIZE	0x00000008
+#define C_EE_ERR_FIRST_FLG_TS_OFFSET	0x00000118
+#define C_EE_ERR_FIRST_FLG_TS	(C_EE_BASE + C_EE_ERR_FIRST_FLG_TS_OFFSET)
+#define C_EE_ERR_FIRST_FLG_TS_SIZE	0x00000008
+#define C_EE_ERR_CLR_OFFSET	0x00000120
+#define C_EE_ERR_CLR	(C_EE_BASE + C_EE_ERR_CLR_OFFSET)
+#define C_EE_ERR_CLR_SIZE	0x00000008
+#define C_EE_ERR_IRQA_MSK_OFFSET	0x00000128
+#define C_EE_ERR_IRQA_MSK	(C_EE_BASE + C_EE_ERR_IRQA_MSK_OFFSET)
+#define C_EE_ERR_IRQA_MSK_SIZE	0x00000008
+#define C_EE_ERR_IRQB_MSK_OFFSET	0x00000130
+#define C_EE_ERR_IRQB_MSK	(C_EE_BASE + C_EE_ERR_IRQB_MSK_OFFSET)
+#define C_EE_ERR_IRQB_MSK_SIZE	0x00000008
+#define C_EE_ERR_INFO_MSK_OFFSET	0x00000140
+#define C_EE_ERR_INFO_MSK	(C_EE_BASE + C_EE_ERR_INFO_MSK_OFFSET)
+#define C_EE_ERR_INFO_MSK_SIZE	0x00000008
+#define C_EE_EXT_ERR_FLG_OFFSET	0x00000148
+#define C_EE_EXT_ERR_FLG	(C_EE_BASE + C_EE_EXT_ERR_FLG_OFFSET)
+#define C_EE_EXT_ERR_FLG_SIZE	0x00000008
+
+union c_ee_ext_err_flg {
+	__u64 qw;
+	struct {
+		__u64 sw_diag             :  1;
+		__u64 leo_mem_cor         :  1;
+		__u64 pts_mem_cor         :  1;
+		__u64 ixe_bus_cor         :  1;
+		__u64 lpe_bus_cor         :  1;
+		__u64 mst_bus_cor         :  1;
+		__u64 pct_bus_cor         :  1;
+		__u64 hni_bus_cor         :  1;
+		__u64 cq_bus_cor          :  1;
+		__u64 eqd_mem_cor         :  1;
+		__u64 eqsws_mem_cor       :  1;
+		__u64 eqhws_mem_cor       :  1;
+		__u64 ecbsb_mem_cor       :  1;
+		__u64 ecb_mem_cor         :  1;
+		__u64 rarb_hdr_bus_cor    :  1;
+		__u64 rarb_data_bus_cor   :  1;
+		__u64 acb_vect_cor        :  1;
+		__u64 eqswupd_vect_cor    :  1;
+		__u64 lm_cbeq_mem_cor     :  1;
+		__u64 lm_state_vect_cor   :  1;
+		__u64 trnrsp_mem_cor      :  1;
+		__u64 trnrsp_bus_cor      :  1;
+		__u64 rlscb_vect_cor      :  1;
+		__u64 trncb_vect_cor      :  1;
+		__u64: 2;
+		__u64 leo_mem_ucor        :  1;
+		__u64 pts_mem_ucor        :  1;
+		__u64 ixe_bus_ucor        :  1;
+		__u64 lpe_bus_ucor        :  1;
+		__u64 mst_bus_ucor        :  1;
+		__u64 pct_bus_ucor        :  1;
+		__u64 hni_bus_ucor        :  1;
+		__u64 cq_bus_ucor         :  1;
+		__u64 eqd_mem_ucor        :  1;
+		__u64 eqsws_mem_ucor      :  1;
+		__u64 eqhws_mem_ucor      :  1;
+		__u64 ecbsb_mem_ucor      :  1;
+		__u64 ecb_mem_ucor        :  1;
+		__u64 rarb_hdr_bus_ucor   :  1;
+		__u64 rarb_data_bus_ucor  :  1;
+		__u64 acb_vect_ucor       :  1;
+		__u64 lm_cbeq_mem_ucor    :  1;
+		__u64 trnrsp_mem_ucor     :  1;
+		__u64 trnrsp_bus_ucor     :  1;
+		__u64 rlscb_vect_ucor     :  1;
+		__u64 trncb_vect_ucor     :  1;
+		__u64: 2;
+		__u64 ixe_to_ee_urun      :  1;
+		__u64 ixe_to_ee_orun      :  1;
+		__u64 lpe_to_ee_urun      :  1;
+		__u64 lpe_to_ee_orun      :  1;
+		__u64 mst_to_ee_urun      :  1;
+		__u64 mst_to_ee_orun      :  1;
+		__u64 pct_to_ee_urun      :  1;
+		__u64 pct_to_ee_orun      :  1;
+		__u64 hni_to_ee_urun      :  1;
+		__u64 hni_to_ee_orun      :  1;
+		__u64 cq_to_ee_urun       :  1;
+		__u64 cq_to_ee_orun       :  1;
+		__u64: 3;
+	};
+};
+
+#define C_EE_EXT_ERR_FIRST_FLG_OFFSET	0x00000150
+#define C_EE_EXT_ERR_FIRST_FLG	(C_EE_BASE + C_EE_EXT_ERR_FIRST_FLG_OFFSET)
+#define C_EE_EXT_ERR_FIRST_FLG_SIZE	0x00000008
+#define C_EE_EXT_ERR_FIRST_FLG_TS_OFFSET	0x00000158
+#define C_EE_EXT_ERR_FIRST_FLG_TS	(C_EE_BASE + C_EE_EXT_ERR_FIRST_FLG_TS_OFFSET)
+#define C_EE_EXT_ERR_FIRST_FLG_TS_SIZE	0x00000008
+#define C_EE_EXT_ERR_CLR_OFFSET	0x00000160
+#define C_EE_EXT_ERR_CLR	(C_EE_BASE + C_EE_EXT_ERR_CLR_OFFSET)
+#define C_EE_EXT_ERR_CLR_SIZE	0x00000008
+#define C_EE_EXT_ERR_IRQA_MSK_OFFSET	0x00000168
+#define C_EE_EXT_ERR_IRQA_MSK	(C_EE_BASE + C_EE_EXT_ERR_IRQA_MSK_OFFSET)
+#define C_EE_EXT_ERR_IRQA_MSK_SIZE	0x00000008
+#define C_EE_EXT_ERR_IRQB_MSK_OFFSET	0x00000170
+#define C_EE_EXT_ERR_IRQB_MSK	(C_EE_BASE + C_EE_EXT_ERR_IRQB_MSK_OFFSET)
+#define C_EE_EXT_ERR_IRQB_MSK_SIZE	0x00000008
+#define C_EE_EXT_ERR_INFO_MSK_OFFSET	0x00000180
+#define C_EE_EXT_ERR_INFO_MSK	(C_EE_BASE + C_EE_EXT_ERR_INFO_MSK_OFFSET)
+#define C_EE_EXT_ERR_INFO_MSK_SIZE	0x00000008
+#define C_EE_ERR_INFO_MEM_OFFSET	0x00000190
+#define C_EE_ERR_INFO_MEM	(C_EE_BASE + C_EE_ERR_INFO_MEM_OFFSET)
+#define C_EE_ERR_INFO_MEM_SIZE	0x00000008
+
+union c_ee_err_info_mem {
+	__u64 qw;
+	struct {
+		__u64 cor_syndrome       : 12;
+		__u64 cor_address        : 11;
+		__u64: 1;
+		__u64 cor_mem_id         :  5;
+		__u64: 2;
+		__u64 cor_csr_detected   :  1;
+		__u64 ucor_syndrome      : 12;
+		__u64 ucor_address       : 11;
+		__u64: 1;
+		__u64 ucor_mem_id        :  5;
+		__u64: 2;
+		__u64 ucor_csr_detected  :  1;
+	};
+};
+
+#define C_EE_ERR_INFO_EQ_CFG_OFFSET	0x00000198
+#define C_EE_ERR_INFO_EQ_CFG	(C_EE_BASE + C_EE_ERR_INFO_EQ_CFG_OFFSET)
+#define C_EE_ERR_INFO_EQ_CFG_SIZE	0x00000008
+
+union c_ee_err_info_eq_cfg {
+	__u64 qw;
+	struct {
+		__u64 eq_ovflw_rsrvn         :  1;
+		__u64 eq_ovflw_fc_sc         :  1;
+		__u64 eq_ovflw_ordinary      :  1;
+		__u64 eq_dsabld_event        :  1;
+		__u64 eq_dsabld_sw_state_wr  :  1;
+		__u64 eq_dsabld_lpe_query    :  1;
+		__u64: 2;
+		__u64 event_type             :  5;
+		__u64: 3;
+		__u64 eq_handle              : 11;
+		__u64: 37;
+	};
+};
+
+#define C_EE_ERR_INFO_RSRVN_UFLW_OFFSET	0x000001a0
+#define C_EE_ERR_INFO_RSRVN_UFLW	(C_EE_BASE + C_EE_ERR_INFO_RSRVN_UFLW_OFFSET)
+#define C_EE_ERR_INFO_RSRVN_UFLW_SIZE	0x00000008
+
+union c_ee_err_info_rsrvn_uflw {
+	__u64 qw;
+	struct {
+		__u64: 8;
+		__u64 event_type           :  5;
+		__u64: 3;
+		__u64 eq_handle            : 11;
+		__u64: 5;
+		__u64 pending_events       : 26;
+		__u64: 2;
+		__u64 required_evnt_slots  :  3;
+		__u64: 1;
+	};
+};
+
+#define C_EE_ERR_INFO_TRNSLTN_OFFSET	0x000001a8
+#define C_EE_ERR_INFO_TRNSLTN	(C_EE_BASE + C_EE_ERR_INFO_TRNSLTN_OFFSET)
+#define C_EE_ERR_INFO_TRNSLTN_SIZE	0x00000008
+
+union c_ee_err_info_trnsltn {
+	__u64 qw;
+	struct {
+		__u64 cb_id            :  8;
+		__u64 free             :  1;
+		__u64 already_trnsltd  :  1;
+		__u64 eq_wr_pending    :  1;
+		__u64: 53;
+	};
+};
+
+#define C_EE_ERR_INFO_RARB_OFFSET	0x000001b0
+#define C_EE_ERR_INFO_RARB	(C_EE_BASE + C_EE_ERR_INFO_RARB_OFFSET)
+#define C_EE_ERR_INFO_RARB_SIZE	0x00000008
+
+union c_ee_err_info_rarb {
+	__u64 qw;
+	struct {
+		__u64 hdr_ucor        :  1;
+		__u64 data_ucor       :  1;
+		__u64 bad_vld         :  1;
+		__u64 bad_eop         :  1;
+		__u64 bad_cmd         :  1;
+		__u64 invalid_access  :  1;
+		__u64 eq_none         :  1;
+		__u64: 1;
+		__u64 first_dw_be     :  4;
+		__u64 last_dw_be      :  4;
+		__u64 length          : 11;
+		__u64: 5;
+		__u64: 2;
+		__u64 addr_29_2       : 28;
+		__u64: 2;
+	};
+};
+
+#define C_EE_ERR_INFO_TARB_OFFSET	0x000001b8
+#define C_EE_ERR_INFO_TARB	(C_EE_BASE + C_EE_ERR_INFO_TARB_OFFSET)
+#define C_EE_ERR_INFO_TARB_SIZE	0x00000008
+
+union c_ee_err_info_tarb {
+	__u64 qw;
+	struct {
+		__u64 ecb_mem_ucor       :  1;
+		__u64 ecbsb_mem_ucor     :  1;
+		__u64 trnrsp_mem_ucor    :  1;
+		__u64 trnsltn_err        :  1;
+		__u64 evnt_dropped       :  1;
+		__u64 irq_dropped        :  1;
+		__u64 trnsltn_performed  :  1;
+		__u64: 1;
+		__u64 trnsltn_rc         :  6;
+		__u64: 2;
+		__u64 acid               : 10;
+		__u64: 6;
+		__u64 eq_handle          : 11;
+		__u64: 21;
+	};
+};
+
+#define C_EE_ERR_INFO_EQ_UCOR_OFFSET	0x000001c0
+#define C_EE_ERR_INFO_EQ_UCOR	(C_EE_BASE + C_EE_ERR_INFO_EQ_UCOR_OFFSET)
+#define C_EE_ERR_INFO_EQ_UCOR_SIZE	0x00000008
+
+union c_ee_err_info_eq_ucor {
+	__u64 qw;
+	struct {
+		__u64 eqd_mem_ucor    :  1;
+		__u64 eqsws_mem_ucor  :  1;
+		__u64 eqhws_mem_ucor  :  1;
+		__u64: 5;
+		__u64 aes_rsn         :  4;
+		__u64: 20;
+		__u64 eq_handle       : 11;
+		__u64: 21;
+	};
+};
+
+#define C_EE_CFG_TIMESTAMP_FREQ_OFFSET	0x00000410
+#define C_EE_CFG_TIMESTAMP_FREQ	(C_EE_BASE + C_EE_CFG_TIMESTAMP_FREQ_OFFSET)
+#define C_EE_CFG_TIMESTAMP_FREQ_SIZE	0x00000008
+
+union c_ee_cfg_timestamp_freq {
+	__u64 qw;
+	struct {
+		__u64 clk_divider  : 32;
+		__u64: 32;
+	};
+};
+
+#define C_EE_CFG_INIT_EQ_HW_STATE_OFFSET	0x00000418
+#define C_EE_CFG_INIT_EQ_HW_STATE	(C_EE_BASE + C_EE_CFG_INIT_EQ_HW_STATE_OFFSET)
+#define C_EE_CFG_INIT_EQ_HW_STATE_SIZE	0x00000008
+
+union c_ee_cfg_init_eq_hw_state {
+	__u64 qw;
+	struct {
+		__u64 eq_handle  : 11;
+		__u64: 5;
+		__u64 pending    :  1;
+		__u64: 47;
+	};
+};
+
+#define C_EE_CFG_LATENCY_MONITOR_OFFSET	0x00000420
+#define C_EE_CFG_LATENCY_MONITOR	(C_EE_BASE + C_EE_CFG_LATENCY_MONITOR_OFFSET)
+#define C_EE_CFG_LATENCY_MONITOR_SIZE	0x00000020
+
+union c_ee_cfg_latency_monitor {
+	__u64 qw[4];
+	struct {
+		__u64 granularity     : 16;
+		__u64: 16;
+		__u64 lt_limit        :  9;
+		__u64: 23;
+		__u64 granularity_a   : 16;
+		__u64 lt_reduction_a  :  9;
+		__u64: 7;
+		__u64 lt_limit_a      :  9;
+		__u64: 23;
+		__u64 granularity_b   : 16;
+		__u64 lt_reduction_b  :  9;
+		__u64: 7;
+		__u64 lt_limit_b      :  9;
+		__u64: 23;
+		__u64 thresh_a        :  9;
+		__u64: 7;
+		__u64 hysteresis_a    :  9;
+		__u64: 7;
+		__u64 thresh_b        :  9;
+		__u64: 7;
+		__u64 hysteresis_b    :  9;
+		__u64: 7;
+	};
+};
+
+#define C_EE_CFG_EQ_DESCRIPTOR_OFFSET(idx)	(0x00020000 + ((idx) * 64))
+#define C_EE_CFG_EQ_DESCRIPTOR_ENTRIES	2048
+#define C_EE_CFG_EQ_DESCRIPTOR(idx)	(C_EE_BASE + C_EE_CFG_EQ_DESCRIPTOR_OFFSET(idx))
+#define C_EE_CFG_EQ_DESCRIPTOR_SIZE	0x00020000
+
+union c_ee_cfg_eq_descriptor {
+	__u64 qw[7];
+	struct {
+		__u64 eq_enable          :  1;
+		__u64: 7;
+		__u64 cntr_pool_id       :  2;
+		__u64: 6;
+		__u64 reserved_fc        : 14;
+		__u64: 2;
+		__u64 event_int_idx      : 11;
+		__u64: 4;
+		__u64 event_int_en       :  1;
+		__u64 latency_tolerance  :  9;
+		__u64: 7;
+		__u64 eq_sts_num_thld    :  2;
+		__u64: 6;
+		__u64 eq_sts_thld_base   :  6;
+		__u64: 2;
+		__u64 eq_sts_thld_offst  :  6;
+		__u64: 2;
+		__u64 eq_sts_thld_shift  :  5;
+		__u64: 1;
+		__u64 eq_sts_dropped_en  :  1;
+		__u64 use_buffer_b       :  1;
+		__u64 eq_sts_int_idx     : 11;
+		__u64: 4;
+		__u64 eq_sts_int_en      :  1;
+		__u64: 16;
+		__u64 buffer_a_size      : 20;
+		__u64: 11;
+		__u64 buffer_a_en        :  1;
+		__u64 buffer_b_size      : 20;
+		__u64: 11;
+		__u64 buffer_b_en        :  1;
+		__u64: 12;
+		__u64 buffer_a_addr      : 45;
+		__u64: 7;
+		__u64: 12;
+		__u64 buffer_b_addr      : 45;
+		__u64: 7;
+		__u64 acid               : 10;
+		__u64: 6;
+		__u64 pf_match           :  8;
+		__u64 pf_match_shift     :  6;
+		__u64: 2;
+		__u64 pf_mask_shift      :  6;
+		__u64: 26;
+		__u64: 3;
+		__u64: 61;
+	};
+};
+
+#define C_EE_CFG_EQ_SW_STATE_OFFSET(idx)	(0x00004000 + ((idx) * 8))
+#define C_EE_CFG_EQ_SW_STATE_ENTRIES	2048
+#define C_EE_CFG_EQ_SW_STATE(idx)	(C_EE_BASE + C_EE_CFG_EQ_SW_STATE_OFFSET(idx))
+#define C_EE_CFG_EQ_SW_STATE_SIZE	0x00004000
+
+union c_ee_cfg_eq_sw_state {
+	__u64 qw;
+	struct {
+		__u64 rd_ptr              : 26;
+		__u64: 5;
+		__u64 reading_buffer_b    :  1;
+		__u64 event_int_disable   :  1;
+		__u64 eq_sts_int_disable  :  1;
+		__u64: 6;
+		__u64 event_drop_seq_no   :  1;
+		__u64: 3;
+		__u64: 4;
+		__u64: 16;
+	};
+};
+
+#define C_EE_CFG_STS_EQ_HW_STATE_OFFSET(idx)	(0x00008000 + ((idx) * 16))
+#define C_EE_CFG_STS_EQ_HW_STATE_ENTRIES	2048
+#define C_EE_CFG_STS_EQ_HW_STATE(idx)	(C_EE_BASE + C_EE_CFG_STS_EQ_HW_STATE_OFFSET(idx))
+#define C_EE_CFG_STS_EQ_HW_STATE_SIZE	0x00008000
+
+union c_ee_cfg_sts_eq_hw_state {
+	__u64 qw[2];
+	struct {
+		__u64 wr_ptr             : 26;
+		__u64: 5;
+		__u64 writing_buffer_b   :  1;
+		__u64 pending_events     : 26;
+		__u64: 6;
+		__u64 ecb_idx            :  8;
+		__u64 ecb_state          :  3;
+		__u64: 5;
+		__u64 eq_switch_dfrd     :  1;
+		__u64 eq_switch_pending  :  1;
+		__u64 prefetch_pending   :  1;
+		__u64 event_int_blkd     :  1;
+		__u64 event_dropped      :  1;
+		__u64 event_drop_seq_no  :  1;
+		__u64: 10;
+		__u64: 2;
+		__u64: 30;
+	};
+};
+
+#define C_EE_CFG_LONG_EVNT_OVR_TABLE_OFFSET(idx)	(0x00001000 + ((idx) * 8))
+#define C_EE_CFG_LONG_EVNT_OVR_TABLE_ENTRIES	64
+#define C_EE_CFG_LONG_EVNT_OVR_TABLE(idx)	(C_EE_BASE + C_EE_CFG_LONG_EVNT_OVR_TABLE_OFFSET(idx))
+#define C_EE_CFG_LONG_EVNT_OVR_TABLE_SIZE	0x00000200
+
+union c_ee_cfg_long_evnt_ovr_table {
+	__u64 qw;
+};
+
+#define C_EE_CFG_PERIODIC_TSTAMP_TABLE_OFFSET(idx)	(0x00001200 + ((idx) * 8))
+#define C_EE_CFG_PERIODIC_TSTAMP_TABLE_ENTRIES	32
+#define C_EE_CFG_PERIODIC_TSTAMP_TABLE(idx)	(C_EE_BASE + C_EE_CFG_PERIODIC_TSTAMP_TABLE_OFFSET(idx))
+#define C_EE_CFG_PERIODIC_TSTAMP_TABLE_SIZE	0x00000100
+
+union c_ee_cfg_periodic_tstamp_table {
+	__u64 qw;
+	struct {
+		__u64 n63_n0_enable_periodic_tstamp;
+	};
+};
+
+#define C_EE_STS_INIT_DONE_OFFSET	0x00000828
+#define C_EE_STS_INIT_DONE	(C_EE_BASE + C_EE_STS_INIT_DONE_OFFSET)
+#define C_EE_STS_INIT_DONE_SIZE	0x00000008
+
+union c_ee_sts_init_done {
+	__u64 qw;
+	struct {
+		__u64 init_done   :  1;
+		__u64 warm_reset  :  1;
+		__u64: 62;
+	};
+};
+
+#define C_EE_DBG_ECB_SIDEBAND_OFFSET(idx)	(0x00001800 + ((idx) * 8))
+#define C_EE_DBG_ECB_SIDEBAND_ENTRIES	256
+#define C_EE_DBG_ECB_SIDEBAND(idx)	(C_EE_BASE + C_EE_DBG_ECB_SIDEBAND_OFFSET(idx))
+#define C_EE_DBG_ECB_SIDEBAND_SIZE	0x00000800
+
+union c_ee_dbg_ecb_sideband {
+	__u64 qw;
+	struct {
+		__u64: 6;
+		__u64 addr_11_6     :  6;
+		__u64: 4;
+		__u64 acid          : 10;
+		__u64: 4;
+		__u64 trnsltn       :  1;
+		__u64 data_present  :  1;
+		__u64 eq_handle     : 11;
+		__u64: 5;
+		__u64 int_idx       : 11;
+		__u64: 2;
+		__u64 int_present   :  1;
+		__u64 block_tarb    :  1;
+		__u64: 1;
+	};
+};
+
+#define C_EE_DBG_ECB_OFFSET(idx)	(0x00010000 + ((idx) * 64))
+#define C_EE_DBG_ECB_ENTRIES	256
+#define C_EE_DBG_ECB(idx)	(C_EE_BASE + C_EE_DBG_ECB_OFFSET(idx))
+#define C_EE_DBG_ECB_SIZE	0x00004000
+
+union c_ee_dbg_ecb {
+	__u64 qw[8];
+};
+
+#define C_EE_DBG_TRNSLTN_RSP_OFFSET(idx)	(0x00002000 + ((idx) * 8))
+#define C_EE_DBG_TRNSLTN_RSP_ENTRIES	256
+#define C_EE_DBG_TRNSLTN_RSP(idx)	(C_EE_BASE + C_EE_DBG_TRNSLTN_RSP_OFFSET(idx))
+#define C_EE_DBG_TRNSLTN_RSP_SIZE	0x00000800
+
+union c_ee_dbg_trnsltn_rsp {
+	__u64 qw;
+	struct {
+		__u64 return_code  :  6;
+		__u64: 2;
+		__u64 at_type      :  1;
+		__u64 nsa          :  1;
+		__u64 at_epoch     :  1;
+		__u64: 1;
+		__u64 addr_pg      : 45;
+		__u64: 4;
+		__u64: 3;
+	};
+};
+
+#define C_EE_DBG_LM_CB_TO_EQ_MAP_OFFSET(idx)	(0x00002800 + ((idx) * 8))
+#define C_EE_DBG_LM_CB_TO_EQ_MAP_ENTRIES	256
+#define C_EE_DBG_LM_CB_TO_EQ_MAP(idx)	(C_EE_BASE + C_EE_DBG_LM_CB_TO_EQ_MAP_OFFSET(idx))
+#define C_EE_DBG_LM_CB_TO_EQ_MAP_SIZE	0x00000800
+
+union c_ee_dbg_lm_cb_to_eq_map {
+	__u64 qw;
+	struct {
+		__u64 eq_handle  : 11;
+		__u64: 53;
+	};
+};
+
+#define C_HNI_CFG_CRNC_OFFSET	0x00000000
+#define C_HNI_CFG_CRNC	(C_HNI_BASE + C_HNI_CFG_CRNC_OFFSET)
+#define C_HNI_CFG_CRNC_SIZE	0x00000008
+
+union c_hni_cfg_crnc {
+	__u64 qw;
+	struct {
+		__u64 csr_timeout   :  8;
+		__u64 mcast_id      : 10;
+		__u64: 1;
+		__u64 mcast_enable  :  1;
+		__u64 mcast_mask    : 10;
+		__u64: 34;
+	};
+};
+
+#define C_HNI_CFG_RT_OFFSET_OFFSET	0x00000020
+#define C_HNI_CFG_RT_OFFSET	(C_HNI_BASE + C_HNI_CFG_RT_OFFSET_OFFSET)
+#define C_HNI_CFG_RT_OFFSET_SIZE	0x00000008
+
+union c_hni_cfg_rt_offset {
+	__u64 qw;
+	struct {
+		__u64 seconds  : 48;
+		__u64: 16;
+	};
+};
+
+#define C_HNI_MSC_SHADOW_ACTION_OFFSET	0x00000038
+#define C_HNI_MSC_SHADOW_ACTION	(C_HNI_BASE + C_HNI_MSC_SHADOW_ACTION_OFFSET)
+#define C_HNI_MSC_SHADOW_ACTION_SIZE	0x00000008
+#define C_HNI_MSC_SHADOW_OFFSET	0x00000040
+#define C_HNI_MSC_SHADOW	(C_HNI_BASE + C_HNI_MSC_SHADOW_OFFSET)
+#define C_HNI_MSC_SHADOW_SIZE	0x00000008
+
+union c_hni_msc_shadow {
+	__u64 qw[1];
+};
+
+#define C_HNI_ERR_ELAPSED_TIME_OFFSET	0x00000100
+#define C_HNI_ERR_ELAPSED_TIME	(C_HNI_BASE + C_HNI_ERR_ELAPSED_TIME_OFFSET)
+#define C_HNI_ERR_ELAPSED_TIME_SIZE	0x00000008
+
+union c_hni_err_elapsed_time {
+	__u64 qw;
+	struct {
+		__u64 nanoseconds  : 30;
+		__u64 seconds      : 34;
+	};
+};
+
+#define C1_HNI_ERR_FLG_OFFSET	0x00000108
+#define C1_HNI_ERR_FLG	(C_HNI_BASE + C1_HNI_ERR_FLG_OFFSET)
+#define C1_HNI_ERR_FLG_SIZE	0x00000008
+
+union c1_hni_err_flg {
+	__u64 qw;
+	struct {
+		__u64 sw_diag                  :  1;
+		__u64 crnc_ring_sync_error     :  1;
+		__u64 crnc_ring_ecc_sbe        :  1;
+		__u64 crnc_ring_ecc_mbe        :  1;
+		__u64 crnc_ring_cmd_unknown    :  1;
+		__u64 crnc_csr_cmd_unknown     :  1;
+		__u64 crnc_csr_cmd_incomplete  :  1;
+		__u64 crnc_buf_ecc_sbe         :  1;
+		__u64 crnc_buf_ecc_mbe         :  1;
+		__u64: 1;
+		__u64 event_cnt_ovf            :  1;
+		__u64 llr_flit_cor             :  1;
+		__u64 rx_stat_fifo_cor         :  1;
+		__u64 rx_pkt_fifo_cor          :  1;
+		__u64 timestamp_cor            :  1;
+		__u64 hrp_fifo_cor             :  1;
+		__u64 fgfc_fifo_cor            :  1;
+		__u64 tx_flit_cor              :  1;
+		__u64 event_ram_cor            :  1;
+		__u64 llr_flit_ucor            :  1;
+		__u64 rx_stat_fifo_ucor        :  1;
+		__u64 rx_pkt_fifo_ucor         :  1;
+		__u64 timestamp_ucor           :  1;
+		__u64 hrp_fifo_ucor            :  1;
+		__u64 fgfc_fifo_ucor           :  1;
+		__u64 tx_flit_ucor             :  1;
+		__u64 event_ram_ucor           :  1;
+		__u64 fifo_err                 :  1;
+		__u64 llr_chksum_bad           :  1;
+		__u64 llr_fcs_bad              :  1;
+		__u64 llr_ctrl_perr            :  1;
+		__u64 llr_exceed_mfs           :  1;
+		__u64 llr_eopb                 :  1;
+		__u64 rx_ctrl_perr             :  1;
+		__u64 pause_timeout            :  1;
+		__u64 fgfc_err                 :  1;
+		__u64 credit_uflw              :  1;
+		__u64 tx_ctrl_perr             :  1;
+		__u64 tx_size_err              :  1;
+		__u64 rx_pause_err             :  1;
+		__u64 pfc_fifo_oflw            :  8;
+		__u64 discard_err              :  8;
+		__u64 disable_err              :  8;
+	};
+};
+
+#define C2_HNI_ERR_FLG_OFFSET	0x00000108
+#define C2_HNI_ERR_FLG	(C_HNI_BASE + C2_HNI_ERR_FLG_OFFSET)
+#define C2_HNI_ERR_FLG_SIZE	0x00000008
+
+union c2_hni_err_flg {
+	__u64 qw;
+	struct {
+		__u64 sw_diag                  :  1;
+		__u64 crnc_ring_sync_error     :  1;
+		__u64 crnc_ring_ecc_sbe        :  1;
+		__u64 crnc_ring_ecc_mbe        :  1;
+		__u64 crnc_ring_cmd_unknown    :  1;
+		__u64 crnc_csr_cmd_unknown     :  1;
+		__u64 crnc_csr_cmd_incomplete  :  1;
+		__u64 crnc_buf_ecc_sbe         :  1;
+		__u64 crnc_buf_ecc_mbe         :  1;
+		__u64: 1;
+		__u64 event_cnt_ovf            :  1;
+		__u64 llr_flit_cor             :  1;
+		__u64 rx_stat_fifo_cor         :  1;
+		__u64 rx_pkt_fifo_cor          :  1;
+		__u64 timestamp_cor            :  1;
+		__u64 hrp_fifo_cor             :  1;
+		__u64 fgfc_fifo_cor            :  1;
+		__u64 tx_flit_cor              :  1;
+		__u64 event_ram_cor            :  1;
+		__u64 ixe_flit_cor             :  1;
+		__u64 llr_flit_ucor            :  1;
+		__u64 rx_stat_fifo_ucor        :  1;
+		__u64 rx_pkt_fifo_ucor         :  1;
+		__u64 timestamp_ucor           :  1;
+		__u64 hrp_fifo_ucor            :  1;
+		__u64 fgfc_fifo_ucor           :  1;
+		__u64 tx_flit_ucor             :  1;
+		__u64 event_ram_ucor           :  1;
+		__u64 ixe_flit_ucor            :  1;
+		__u64 fifo_err                 :  1;
+		__u64 llr_chksum_bad           :  1;
+		__u64 llr_fcs_bad              :  1;
+		__u64 llr_ctrl_perr            :  1;
+		__u64 llr_exceed_mfs           :  1;
+		__u64 llr_eopb                 :  1;
+		__u64 pause_timeout            :  1;
+		__u64 fgfc_err                 :  1;
+		__u64 credit_uflw              :  1;
+		__u64 tx_size_err              :  1;
+		__u64 rx_pause_err             :  1;
+		__u64 pfc_fifo_oflw            :  8;
+		__u64 discard_err              :  8;
+		__u64 disable_err              :  8;
+	};
+};
+
+#define C_HNI_ERR_FIRST_FLG_OFFSET	0x00000110
+#define C_HNI_ERR_FIRST_FLG	(C_HNI_BASE + C_HNI_ERR_FIRST_FLG_OFFSET)
+#define C_HNI_ERR_FIRST_FLG_SIZE	0x00000008
+#define C_HNI_ERR_FIRST_FLG_TS_OFFSET	0x00000118
+#define C_HNI_ERR_FIRST_FLG_TS	(C_HNI_BASE + C_HNI_ERR_FIRST_FLG_TS_OFFSET)
+#define C_HNI_ERR_FIRST_FLG_TS_SIZE	0x00000008
+#define C_HNI_ERR_CLR_OFFSET	0x00000120
+#define C_HNI_ERR_CLR	(C_HNI_BASE + C_HNI_ERR_CLR_OFFSET)
+#define C_HNI_ERR_CLR_SIZE	0x00000008
+#define C_HNI_ERR_IRQA_MSK_OFFSET	0x00000128
+#define C_HNI_ERR_IRQA_MSK	(C_HNI_BASE + C_HNI_ERR_IRQA_MSK_OFFSET)
+#define C_HNI_ERR_IRQA_MSK_SIZE	0x00000008
+#define C_HNI_ERR_IRQB_MSK_OFFSET	0x00000130
+#define C_HNI_ERR_IRQB_MSK	(C_HNI_BASE + C_HNI_ERR_IRQB_MSK_OFFSET)
+#define C_HNI_ERR_IRQB_MSK_SIZE	0x00000008
+#define C_HNI_ERR_INFO_MSK_OFFSET	0x00000140
+#define C_HNI_ERR_INFO_MSK	(C_HNI_BASE + C_HNI_ERR_INFO_MSK_OFFSET)
+#define C_HNI_ERR_INFO_MSK_SIZE	0x00000008
+#define C1_HNI_ERR_INFO_ECC_OFFSET	0x00000180
+#define C1_HNI_ERR_INFO_ECC	(C_HNI_BASE + C1_HNI_ERR_INFO_ECC_OFFSET)
+#define C1_HNI_ERR_INFO_ECC_SIZE	0x00000008
+
+union c1_hni_err_info_ecc {
+	__u64 qw;
+	struct {
+		__u64 cor_syndrome       : 11;
+		__u64: 1;
+		__u64 cor_address        :  9;
+		__u64: 3;
+		__u64 cor_id             :  3;
+		__u64: 4;
+		__u64 cor_csr_detected   :  1;
+		__u64 ucor_syndrome      : 11;
+		__u64: 1;
+		__u64 ucor_address       :  9;
+		__u64: 3;
+		__u64 ucor_id            :  3;
+		__u64: 4;
+		__u64 ucor_csr_detected  :  1;
+	};
+};
+
+#define C2_HNI_ERR_INFO_ECC_OFFSET	0x00000188
+#define C2_HNI_ERR_INFO_ECC	(C_HNI_BASE + C2_HNI_ERR_INFO_ECC_OFFSET)
+#define C2_HNI_ERR_INFO_ECC_SIZE	0x00000008
+
+union c2_hni_err_info_ecc {
+	__u64 qw;
+	struct {
+		__u64 cor_syndrome       : 11;
+		__u64: 1;
+		__u64 cor_address        :  9;
+		__u64: 3;
+		__u64 cor_id             :  4;
+		__u64: 3;
+		__u64 cor_csr_detected   :  1;
+		__u64 ucor_syndrome      : 11;
+		__u64: 1;
+		__u64 ucor_address       :  9;
+		__u64: 3;
+		__u64 ucor_id            :  4;
+		__u64: 3;
+		__u64 ucor_csr_detected  :  1;
+	};
+};
+
+#define C1_HNI_ERR_INFO_FIFO_OFFSET	0x00000188
+#define C1_HNI_ERR_INFO_FIFO	(C_HNI_BASE + C1_HNI_ERR_INFO_FIFO_OFFSET)
+#define C_HNI_ERR_INFO_FIFO_SIZE	0x00000008
+#define C1_HNI_ERR_INFO_FIFO_SIZE	C_HNI_ERR_INFO_FIFO_SIZE
+
+union c_hni_err_info_fifo {
+	__u64 qw;
+	struct {
+		__u64 overrun   :  1;
+		__u64 underrun  :  1;
+		__u64: 2;
+		__u64 fifo_id   :  3;
+		__u64: 57;
+	};
+};
+
+#define C2_HNI_ERR_INFO_FIFO_OFFSET	0x00000190
+#define C2_HNI_ERR_INFO_FIFO	(C_HNI_BASE + C2_HNI_ERR_INFO_FIFO_OFFSET)
+#define C2_HNI_ERR_INFO_FIFO_SIZE	C_HNI_ERR_INFO_FIFO_SIZE
+
+#define C1_HNI_ERR_INFO_CC_OFFSET	0x00000190
+#define C1_HNI_ERR_INFO_CC	(C_HNI_BASE + C1_HNI_ERR_INFO_CC_OFFSET)
+#define C_HNI_ERR_INFO_CC_SIZE	0x00000008
+#define C1_HNI_ERR_INFO_CC_SIZE	C_HNI_ERR_INFO_CC_SIZE
+
+union c_hni_err_info_cc {
+	__u64 qw;
+	struct {
+		__u64 cc_id  :  3;
+		__u64: 1;
+		__u64 cc_tc  :  3;
+		__u64: 57;
+	};
+};
+
+#define C2_HNI_ERR_INFO_CC_OFFSET	0x00000198
+#define C2_HNI_ERR_INFO_CC	(C_HNI_BASE + C2_HNI_ERR_INFO_CC_OFFSET)
+#define C2_HNI_ERR_INFO_CC_SIZE	C_HNI_ERR_INFO_CC_SIZE
+
+#define C1_HNI_ERR_INFO_FGFC_OFFSET	0x00000198
+#define C1_HNI_ERR_INFO_FGFC	(C_HNI_BASE + C1_HNI_ERR_INFO_FGFC_OFFSET)
+#define C_HNI_ERR_INFO_FGFC_SIZE	0x00000008
+#define C1_HNI_ERR_INFO_FGFC_SIZE	C_HNI_ERR_INFO_FGFC_SIZE
+
+union c_hni_err_info_fgfc {
+	__u64 qw;
+	struct {
+		__u64 invalid_type  :  1;
+		__u64 no_match      :  1;
+		__u64 cache_full    :  1;
+		__u64 fifo_full     :  1;
+		__u64: 60;
+	};
+};
+
+#define C2_HNI_ERR_INFO_FGFC_OFFSET	0x000001a0
+#define C2_HNI_ERR_INFO_FGFC	(C_HNI_BASE + C2_HNI_ERR_INFO_FGFC_OFFSET)
+#define C2_HNI_ERR_INFO_FGFC_SIZE	C_HNI_ERR_INFO_FGFC_SIZE
+
+#define C1_HNI_ERR_INFO_SIZE_ERR_OFFSET	0x000001a0
+#define C1_HNI_ERR_INFO_SIZE_ERR	(C_HNI_BASE + C1_HNI_ERR_INFO_SIZE_ERR_OFFSET)
+#define C_HNI_ERR_INFO_SIZE_ERR_SIZE	0x00000008
+#define C1_HNI_ERR_INFO_SIZE_ERR_SIZE	C_HNI_ERR_INFO_SIZE_ERR_SIZE
+
+union c_hni_err_info_size_err {
+	__u64 qw;
+	struct {
+		__u64 opt_too_small  :  1;
+		__u64 std_too_small  :  1;
+		__u64 opt_too_big    :  1;
+		__u64 std_too_big    :  1;
+		__u64: 60;
+	};
+};
+
+#define C2_HNI_ERR_INFO_SIZE_ERR_OFFSET	0x000001a8
+#define C2_HNI_ERR_INFO_SIZE_ERR	(C_HNI_BASE + C2_HNI_ERR_INFO_SIZE_ERR_OFFSET)
+#define C2_HNI_ERR_INFO_SIZE_ERR_SIZE	C_HNI_ERR_INFO_SIZE_ERR_SIZE
+
+#define C1_HNI_ERR_INFO_DISCARD_OFFSET	0x00000200
+#define C1_HNI_ERR_INFO_DISCARD	(C_HNI_BASE + C1_HNI_ERR_INFO_DISCARD_OFFSET)
+#define C_HNI_ERR_INFO_DISCARD_SIZE	0x00000018
+#define C1_HNI_ERR_INFO_DISCARD_SIZE	C_HNI_ERR_INFO_DISCARD_SIZE
+
+union c_hni_err_info_discard {
+	__u64 qw[3];
+	struct {
+		__u64 addr_low;
+		__u64 addr_high;
+		__u64 tc          :  3;
+		__u64: 1;
+		__u64 pkt_type    :  2;
+		__u64: 58;
+	};
+};
+
+#define C2_HNI_ERR_INFO_DISCARD_OFFSET	0x000001b0
+#define C2_HNI_ERR_INFO_DISCARD	(C_HNI_BASE + C2_HNI_ERR_INFO_DISCARD_OFFSET)
+#define C2_HNI_ERR_INFO_DISCARD_SIZE	C_HNI_ERR_INFO_DISCARD_SIZE
+
+#define C_HNI_CFG_GEN_OFFSET	0x00000400
+#define C_HNI_CFG_GEN	(C_HNI_BASE + C_HNI_CFG_GEN_OFFSET)
+#define C_HNI_CFG_GEN_SIZE	0x00000008
+
+union c_hni_cfg_gen {
+	__u64 qw;
+	struct {
+		__u64 tx_timestamp_en  :  1;
+		__u64 rx_timestamp_en  :  1;
+		__u64 timestamp_fmt    :  2;
+		__u64 default_pcp      :  3;
+		__u64 ip_enable_dscp   :  1;
+		__u64 default_dscp     :  6;
+		__u64: 50;
+	};
+};
+
+#define C_HNI_CFG_CDT_OFFSET	0x00000408
+#define C_HNI_CFG_CDT	(C_HNI_BASE + C_HNI_CFG_CDT_OFFSET)
+#define C_HNI_CFG_CDT_SIZE	0x00000008
+
+union c_hni_cfg_cdt {
+	__u64 qw;
+	struct {
+		__u64 ixe_cdts       :  6;
+		__u64: 2;
+		__u64 hrp_cdts       :  5;
+		__u64: 3;
+		__u64 llr_cdts       :  4;
+		__u64: 4;
+		__u64 ee_cdts        :  5;
+		__u64: 3;
+		__u64 ixe_pbuf_size  : 13;
+		__u64: 19;
+	};
+};
+
+#define C_HNI_CFG_TXTS_L2_MASK_OFFSET	0x00000430
+#define C_HNI_CFG_TXTS_L2_MASK	(C_HNI_BASE + C_HNI_CFG_TXTS_L2_MASK_OFFSET)
+#define C_HNI_CFG_TXTS_L2_MASK_SIZE	0x00000008
+
+union c_hni_cfg_txts_l2_mask {
+	__u64 qw;
+	struct {
+		__u64 dmac       : 48;
+		__u64 ethertype  : 16;
+	};
+};
+
+#define C_HNI_CFG_TXTS_L2_MATCH_OFFSET	0x00000438
+#define C_HNI_CFG_TXTS_L2_MATCH	(C_HNI_BASE + C_HNI_CFG_TXTS_L2_MATCH_OFFSET)
+#define C_HNI_CFG_TXTS_L2_MATCH_SIZE	0x00000008
+
+union c_hni_cfg_txts_l2_match {
+	__u64 qw;
+	struct {
+		__u64 dmac       : 48;
+		__u64 ethertype  : 16;
+	};
+};
+
+#define C_HNI_CFG_TXTS_L3_MASK_OFFSET	0x00000440
+#define C_HNI_CFG_TXTS_L3_MASK	(C_HNI_BASE + C_HNI_CFG_TXTS_L3_MASK_OFFSET)
+#define C_HNI_CFG_TXTS_L3_MASK_SIZE	0x00000008
+
+union c_hni_cfg_txts_l3_mask {
+	__u64 qw;
+	struct {
+		__u64 hdr;
+	};
+};
+
+#define C_HNI_CFG_TXTS_L3_MATCH_OFFSET	0x00000448
+#define C_HNI_CFG_TXTS_L3_MATCH	(C_HNI_BASE + C_HNI_CFG_TXTS_L3_MATCH_OFFSET)
+#define C_HNI_CFG_TXTS_L3_MATCH_SIZE	0x00000008
+
+union c_hni_cfg_txts_l3_match {
+	__u64 qw;
+	struct {
+		__u64 hdr;
+	};
+};
+
+#define C_HNI_CFG_RXTS_L2_MASK_OFFSET	0x00000450
+#define C_HNI_CFG_RXTS_L2_MASK	(C_HNI_BASE + C_HNI_CFG_RXTS_L2_MASK_OFFSET)
+#define C_HNI_CFG_RXTS_L2_MASK_SIZE	0x00000008
+
+union c_hni_cfg_rxts_l2_mask {
+	__u64 qw;
+	struct {
+		__u64 dmac       : 48;
+		__u64 ethertype  : 16;
+	};
+};
+
+#define C_HNI_CFG_RXTS_L2_MATCH_OFFSET	0x00000458
+#define C_HNI_CFG_RXTS_L2_MATCH	(C_HNI_BASE + C_HNI_CFG_RXTS_L2_MATCH_OFFSET)
+#define C_HNI_CFG_RXTS_L2_MATCH_SIZE	0x00000008
+
+union c_hni_cfg_rxts_l2_match {
+	__u64 qw;
+	struct {
+		__u64 dmac       : 48;
+		__u64 ethertype  : 16;
+	};
+};
+
+#define C_HNI_CFG_RXTS_L3_MASK_OFFSET	0x00000460
+#define C_HNI_CFG_RXTS_L3_MASK	(C_HNI_BASE + C_HNI_CFG_RXTS_L3_MASK_OFFSET)
+#define C_HNI_CFG_RXTS_L3_MASK_SIZE	0x00000008
+
+union c_hni_cfg_rxts_l3_mask {
+	__u64 qw;
+	struct {
+		__u64 hdr;
+	};
+};
+
+#define C_HNI_CFG_RXTS_L3_MATCH_OFFSET	0x00000468
+#define C_HNI_CFG_RXTS_L3_MATCH	(C_HNI_BASE + C_HNI_CFG_RXTS_L3_MATCH_OFFSET)
+#define C_HNI_CFG_RXTS_L3_MATCH_SIZE	0x00000008
+
+union c_hni_cfg_rxts_l3_match {
+	__u64 qw;
+	struct {
+		__u64 hdr;
+	};
+};
+
+#define C_HNI_CFG_PAUSE_QUANTA_OFFSET	0x00000470
+#define C_HNI_CFG_PAUSE_QUANTA	(C_HNI_BASE + C_HNI_CFG_PAUSE_QUANTA_OFFSET)
+#define C_HNI_CFG_PAUSE_QUANTA_SIZE	0x00000008
+
+union c_hni_cfg_pause_quanta {
+	__u64 qw;
+	struct {
+		__u64 sub_value   : 24;
+		__u64 sub_period  :  8;
+		__u64: 32;
+	};
+};
+
+#define C_HNI_CFG_PAUSE_TIMING_OFFSET	0x00000478
+#define C_HNI_CFG_PAUSE_TIMING	(C_HNI_BASE + C_HNI_CFG_PAUSE_TIMING_OFFSET)
+#define C_HNI_CFG_PAUSE_TIMING_SIZE	0x00000008
+
+union c_hni_cfg_pause_timing {
+	__u64 qw;
+	struct {
+		__u64 pause_period         : 16;
+		__u64 pause_repeat_period  : 16;
+		__u64: 32;
+	};
+};
+
+#define C_HNI_CFG_PAUSE_TX_CTRL_OFFSET	0x00000490
+#define C_HNI_CFG_PAUSE_TX_CTRL	(C_HNI_BASE + C_HNI_CFG_PAUSE_TX_CTRL_OFFSET)
+#define C_HNI_CFG_PAUSE_TX_CTRL_SIZE	0x00000008
+
+union c_hni_cfg_pause_tx_ctrl {
+	__u64 qw;
+	struct {
+		__u64 mac_cntl_opcode    : 16;
+		__u64 mac_cntl_type      : 16;
+		__u64 enable_send_pause  :  8;
+		__u64 pev                :  8;
+		__u64 enable_pause       :  1;
+		__u64 enable_pfc_pause   :  1;
+		__u64: 14;
+	};
+};
+
+#define C_HNI_CFG_PAUSE_RX_CTRL_OFFSET	0x00000498
+#define C_HNI_CFG_PAUSE_RX_CTRL	(C_HNI_BASE + C_HNI_CFG_PAUSE_RX_CTRL_OFFSET)
+#define C_HNI_CFG_PAUSE_RX_CTRL_SIZE	0x00000008
+
+union c_hni_cfg_pause_rx_ctrl {
+	__u64 qw;
+	struct {
+		__u64 enable_rec_pause  :  8;
+		__u64 pause_rec_enable  :  1;
+		__u64 pfc_rec_enable    :  1;
+		__u64: 2;
+		__u64 timer_bit         :  5;
+		__u64: 47;
+	};
+};
+
+#define C_HNI_CFG_MAX_SIZES_OFFSET	0x000004a8
+#define C_HNI_CFG_MAX_SIZES	(C_HNI_BASE + C_HNI_CFG_MAX_SIZES_OFFSET)
+#define C_HNI_CFG_MAX_SIZES_SIZE	0x00000008
+
+union c_hni_cfg_max_sizes {
+	__u64 qw;
+	struct {
+		__u64 max_std_size      : 14;
+		__u64: 2;
+		__u64 max_opt_size      : 14;
+		__u64: 2;
+		__u64 max_portals_size  : 14;
+		__u64: 18;
+	};
+};
+
+#define C_HNI_CFG_EVENT_CNTS_OFFSET	0x000004b8
+#define C_HNI_CFG_EVENT_CNTS	(C_HNI_BASE + C_HNI_CFG_EVENT_CNTS_OFFSET)
+#define C_HNI_CFG_EVENT_CNTS_SIZE	0x00000008
+
+union c_hni_cfg_event_cnts {
+	__u64 qw;
+	struct {
+		__u64 enable     :  1;
+		__u64 init       :  1;
+		__u64 init_done  :  1;
+		__u64: 1;
+		__u64 ovf_cnt    : 16;
+		__u64: 44;
+	};
+};
+
+#define C_HNI_CFG_PBUF_OFFSET(idx)	(0x00000500 + ((idx) * 8))
+#define C_HNI_CFG_PBUF_ENTRIES	8
+#define C_HNI_CFG_PBUF(idx)	(C_HNI_BASE + C_HNI_CFG_PBUF_OFFSET(idx))
+#define C_HNI_CFG_PBUF_SIZE	0x00000040
+
+union c_hni_cfg_pbuf {
+	__u64 qw;
+	struct {
+		__u64 static_rsvd  : 12;
+		__u64: 4;
+		__u64 mtu          :  7;
+		__u64: 41;
+	};
+};
+
+#define C1_HNI_CFG_PFC_BUF_OFFSET(idx)	(0x00000580 + ((idx) * 8))
+#define C1_HNI_CFG_PFC_BUF_ENTRIES	8
+#define C1_HNI_CFG_PFC_BUF(idx)	(C_HNI_BASE + C1_HNI_CFG_PFC_BUF_OFFSET(idx))
+#define C1_HNI_CFG_PFC_BUF_SIZE	0x00000040
+
+union c1_hni_cfg_pfc_buf {
+	__u64 qw;
+	struct {
+		__u64 low_water    : 11;
+		__u64: 1;
+		__u64 high_water   : 11;
+		__u64: 1;
+		__u64 timer_bit    :  5;
+		__u64: 3;
+		__u64 discard_max  :  3;
+		__u64: 1;
+		__u64 resume       :  1;
+		__u64: 27;
+	};
+};
+
+#define C2_HNI_CFG_PFC_BUF_OFFSET(idx)	(0x00000580 + ((idx) * 8))
+#define C2_HNI_CFG_PFC_BUF_ENTRIES	8
+#define C2_HNI_CFG_PFC_BUF(idx)	(C_HNI_BASE + C2_HNI_CFG_PFC_BUF_OFFSET(idx))
+#define C2_HNI_CFG_PFC_BUF_SIZE	0x00000040
+
+union c2_hni_cfg_pfc_buf {
+	__u64 qw;
+	struct {
+		__u64 low_water    : 12;
+		__u64 high_water   : 12;
+		__u64 timer_bit    :  5;
+		__u64: 3;
+		__u64 discard_max  :  3;
+		__u64: 1;
+		__u64 resume       :  1;
+		__u64: 27;
+	};
+};
+
+#define C_HNI_CFG_DSCP_PCP_OFFSET(idx)	(0x00000800 + ((idx) * 8))
+#define C_HNI_CFG_DSCP_PCP_ENTRIES	64
+#define C_HNI_CFG_DSCP_PCP(idx)	(C_HNI_BASE + C_HNI_CFG_DSCP_PCP_OFFSET(idx))
+#define C_HNI_CFG_DSCP_PCP_SIZE	0x00000200
+
+union c_hni_cfg_dscp_pcp {
+	__u64 qw;
+	struct {
+		__u64 pcp   :  3;
+		__u64: 61;
+	};
+};
+
+#define C_HNI_STS_CDT_OFFSET	0x00001000
+#define C_HNI_STS_CDT	(C_HNI_BASE + C_HNI_STS_CDT_OFFSET)
+#define C_HNI_STS_CDT_SIZE	0x00000008
+
+union c_hni_sts_cdt {
+	__u64 qw;
+	struct {
+		__u64 ixe_cdts  :  6;
+		__u64: 2;
+		__u64 hrp_cdts  :  5;
+		__u64: 3;
+		__u64 llr_cdts  :  4;
+		__u64: 4;
+		__u64 ee_cdts   :  5;
+		__u64: 3;
+		__u64 buf_cdts  : 13;
+		__u64: 19;
+	};
+};
+
+#define C_HNI_STS_PAUSE_TIMEOUT_OFFSET	0x00001008
+#define C_HNI_STS_PAUSE_TIMEOUT	(C_HNI_BASE + C_HNI_STS_PAUSE_TIMEOUT_OFFSET)
+#define C_HNI_STS_PAUSE_TIMEOUT_SIZE	0x00000008
+
+union c_hni_sts_pause_timeout {
+	__u64 qw;
+	struct {
+		__u64 pfc_0  :  4;
+		__u64 pfc_1  :  4;
+		__u64 pfc_2  :  4;
+		__u64 pfc_3  :  4;
+		__u64 pfc_4  :  4;
+		__u64 pfc_5  :  4;
+		__u64 pfc_6  :  4;
+		__u64 pfc_7  :  4;
+		__u64: 32;
+	};
+};
+
+#define C_HNI_STS_EVENT_CNTS_OFFSET(idx)	(0x00002000 + ((idx) * 8))
+#ifndef C_HNI_STS_EVENT_CNTS_ENTRIES
+#define C_HNI_STS_EVENT_CNTS_ENTRIES	512
+#endif
+#define C_HNI_STS_EVENT_CNTS(idx)	(C_HNI_BASE + C_HNI_STS_EVENT_CNTS_OFFSET(idx))
+#define C_HNI_STS_EVENT_CNTS_SIZE	0x00001000
+
+union c_hni_sts_event_cnts {
+	__u64 qw;
+	struct {
+		__u64 cnt  : 56;
+		__u64: 8;
+	};
+};
+
+#define C_HNI_UC_SBR_INTR_OFFSET	0x00004310
+#define C_HNI_UC_SBR_INTR	(C_HNI_BASE + C_HNI_UC_SBR_INTR_OFFSET)
+#define C_HNI_UC_SBR_INTR_SIZE	0x00000008
+
+union c_hni_uc_sbr_intr {
+	__u64 qw;
+	struct {
+		__u64 intr          :  8;
+		__u64 send_sbr      :  1;
+		__u64 send_sbr_dis  :  1;
+		__u64: 54;
+	};
+};
+
+#define C_HNI_PML_CFG_CRNC_OFFSET	0x00000000
+#define C_HNI_PML_CFG_CRNC	(C_HNI_PML_BASE + C_HNI_PML_CFG_CRNC_OFFSET)
+#define C_HNI_PML_CFG_CRNC_SIZE	0x00000008
+
+union c_hni_pml_cfg_crnc {
+	__u64 qw;
+	struct {
+		__u64 csr_timeout   :  8;
+		__u64 mcast_id      : 10;
+		__u64: 1;
+		__u64 mcast_enable  :  1;
+		__u64 mcast_mask    : 10;
+		__u64: 34;
+	};
+};
+
+#define C_HNI_PML_ERR_ELAPSED_TIME_OFFSET	0x00000100
+#define C_HNI_PML_ERR_ELAPSED_TIME	(C_HNI_PML_BASE + C_HNI_PML_ERR_ELAPSED_TIME_OFFSET)
+#define C_HNI_PML_ERR_ELAPSED_TIME_SIZE	0x00000008
+
+union c_hni_pml_err_elapsed_time {
+	__u64 qw;
+	struct {
+		__u64 nanoseconds  : 30;
+		__u64 seconds      : 34;
+	};
+};
+
+#define C1_HNI_PML_ERR_FLG_OFFSET	0x00000108
+#define C1_HNI_PML_ERR_FLG	(C_HNI_PML_BASE + C1_HNI_PML_ERR_FLG_OFFSET)
+#define C1_HNI_PML_ERR_FLG_SIZE	0x00000008
+
+union c1_hni_pml_err_flg {
+	__u64 qw;
+	struct {
+		__u64 sw_diag                  :  1;
+		__u64 crnc_ring_sync_error     :  1;
+		__u64 crnc_ring_ecc_sbe        :  1;
+		__u64 crnc_ring_ecc_mbe        :  1;
+		__u64 crnc_ring_cmd_unknown    :  1;
+		__u64 crnc_csr_cmd_unknown     :  1;
+		__u64 crnc_csr_cmd_incomplete  :  1;
+		__u64 crnc_buf_ecc_sbe         :  1;
+		__u64 crnc_buf_ecc_mbe         :  1;
+		__u64: 22;
+		__u64 mac_rx_frame_err         :  1;
+		__u64 autoneg_page_received    :  1;
+		__u64 autoneg_complete         :  1;
+		__u64 autoneg_failed           :  1;
+		__u64 pcs_tx_dp_err            :  1;
+		__u64 pcs_rx_dp_err            :  1;
+		__u64 pcs_rx_deskew_overflow   :  1;
+		__u64 pcs_rx_deskew_pe         :  1;
+		__u64 pcs_fec_mem0_sbe         :  1;
+		__u64 pcs_fec_mem0_mbe         :  1;
+		__u64 pcs_fec_mem1_sbe         :  1;
+		__u64 pcs_fec_mem1_mbe         :  1;
+		__u64 pcs_tx_degrade           :  1;
+		__u64 pcs_rx_degrade           :  1;
+		__u64 pcs_rx_degrade_failure   :  1;
+		__u64 pcs_tx_degrade_failure   :  1;
+		__u64 pcs_hi_ser               :  1;
+		__u64 pcs_link_down            :  1;
+		__u64 mac_tx_dp_err            :  1;
+		__u64 mac_rx_dp_err            :  1;
+		__u64 llr_tx_dp_sbe            :  1;
+		__u64 llr_tx_dp_mbe            :  1;
+		__u64 llr_tx_dp_err            :  1;
+		__u64 llr_seq_mem_sbe          :  1;
+		__u64 llr_seq_mem_mbe          :  1;
+		__u64 llr_replay_mem_sbe       :  1;
+		__u64 llr_replay_mem_mbe       :  1;
+		__u64 llr_ack_nack_error       :  1;
+		__u64 llr_ack_nack_seq_err     :  1;
+		__u64 llr_replay_at_max        :  1;
+		__u64 pcs_lanes_locked         :  1;
+		__u64 pcs_aligned              :  1;
+		__u64 pcs_ready                :  1;
+	};
+};
+
+#define SS2_PORT_PML_ERR_FLG_OFFSET	0x00000120
+#define SS2_PORT_PML_ERR_FLG	(C_HNI_PML_BASE + SS2_PORT_PML_ERR_FLG_OFFSET)
+#define SS2_PORT_PML_ERR_FLG_SIZE	0x00000020
+
+union ss2_port_pml_err_flg {
+	__u64 qw[4];
+	struct {
+		__u64 sw_diag                     :  1;
+		__u64 crnc_ring_sync_error        :  1;
+		__u64 crnc_ring_ecc_sbe           :  1;
+		__u64 crnc_ring_ecc_mbe           :  1;
+		__u64 crnc_ring_cmd_unknown       :  1;
+		__u64 crnc_csr_cmd_unknown        :  1;
+		__u64 crnc_csr_cmd_incomplete     :  1;
+		__u64 crnc_buf_ecc_sbe            :  1;
+		__u64 crnc_buf_ecc_mbe            :  1;
+		__u64 csrc_ring_sync_error        :  1;
+		__u64 csrc_ring_ecc_sbe           :  1;
+		__u64 csrc_ring_ecc_mbe           :  1;
+		__u64 csrc_ring_cmd_unknown       :  1;
+		__u64 csrc_sring_sync_error       :  1;
+		__u64 csrc_sring_ecc_sbe          :  1;
+		__u64 csrc_sring_ecc_mbe          :  1;
+		__u64 csrc_sring_cmd_unknown      :  1;
+		__u64 csrc_buf_ecc_sbe            :  1;
+		__u64 csrc_buf_ecc_mbe            :  1;
+		__u64: 13;
+		__u64 pcs_tx_dp_err               :  1;
+		__u64 pcs_rx_dp_err               :  1;
+		__u64 pcs_rx_deskew_overflow      :  1;
+		__u64 pcs_rx_deskew_pe            :  1;
+		__u64 pcs_fec0_mem_sbe            :  1;
+		__u64 pcs_fec0_mem_mbe            :  1;
+		__u64 pcs_fec1_mem_sbe            :  1;
+		__u64 pcs_fec1_mem_mbe            :  1;
+		__u64 mac_tx_dp_err               :  1;
+		__u64 mac_rx_dp_err               :  1;
+		__u64 llr_tx_dp_sbe               :  1;
+		__u64 llr_tx_dp_mbe               :  1;
+		__u64 llr_tx_dp_err               :  1;
+		__u64 llr_rx_dp_err               :  1;
+		__u64 llr_seq_mem_sbe             :  1;
+		__u64 llr_seq_mem_mbe             :  1;
+		__u64 llr_replay_mem_sbe          :  1;
+		__u64 llr_replay_mem_mbe          :  1;
+		__u64 event_mem_sbe               :  1;
+		__u64 event_mem_mbe               :  1;
+		__u64 mac_rx_fcs32_err_0          :  1;
+		__u64 mac_rx_fcs32_err_1          :  1;
+		__u64 mac_rx_fcs32_err_2          :  1;
+		__u64 mac_rx_fcs32_err_3          :  1;
+		__u64 mac_rx_framing_err_0        :  1;
+		__u64 mac_rx_framing_err_1        :  1;
+		__u64 mac_rx_framing_err_2        :  1;
+		__u64 mac_rx_framing_err_3        :  1;
+		__u64 mac_rx_preamble_err_0       :  1;
+		__u64 mac_rx_preamble_err_1       :  1;
+		__u64 mac_rx_preamble_err_2       :  1;
+		__u64 mac_rx_preamble_err_3       :  1;
+		__u64 pcs_link_down_0             :  1;
+		__u64 pcs_link_down_1             :  1;
+		__u64 pcs_link_down_2             :  1;
+		__u64 pcs_link_down_3             :  1;
+		__u64 pcs_link_down_lf_0          :  1;
+		__u64 pcs_link_down_lf_1          :  1;
+		__u64 pcs_link_down_lf_2          :  1;
+		__u64 pcs_link_down_lf_3          :  1;
+		__u64 pcs_link_down_rf_0          :  1;
+		__u64 pcs_link_down_rf_1          :  1;
+		__u64 pcs_link_down_rf_2          :  1;
+		__u64 pcs_link_down_rf_3          :  1;
+		__u64 pcs_hi_ser_0                :  1;
+		__u64 pcs_hi_ser_1                :  1;
+		__u64 pcs_hi_ser_2                :  1;
+		__u64 pcs_hi_ser_3                :  1;
+		__u64 pcs_tx_degrade              :  1;
+		__u64 pcs_rx_degrade              :  1;
+		__u64 pcs_rx_degrade_failure      :  1;
+		__u64 pcs_tx_degrade_failure      :  1;
+		__u64: 8;
+		__u64 autoneg_failed_0            :  1;
+		__u64 autoneg_failed_1            :  1;
+		__u64 autoneg_failed_2            :  1;
+		__u64 autoneg_failed_3            :  1;
+		__u64 llr_ack_nack_error_0        :  1;
+		__u64 llr_ack_nack_error_1        :  1;
+		__u64 llr_ack_nack_error_2        :  1;
+		__u64 llr_ack_nack_error_3        :  1;
+		__u64 llr_ack_nack_seq_err_0      :  1;
+		__u64 llr_ack_nack_seq_err_1      :  1;
+		__u64 llr_ack_nack_seq_err_2      :  1;
+		__u64 llr_ack_nack_seq_err_3      :  1;
+		__u64 llr_replay_at_max_0         :  1;
+		__u64 llr_replay_at_max_1         :  1;
+		__u64 llr_replay_at_max_2         :  1;
+		__u64 llr_replay_at_max_3         :  1;
+		__u64 llr_expected_frame_bad_0    :  1;
+		__u64 llr_expected_frame_bad_1    :  1;
+		__u64 llr_expected_frame_bad_2    :  1;
+		__u64 llr_expected_frame_bad_3    :  1;
+		__u64 llr_duplicate_frame_0       :  1;
+		__u64 llr_duplicate_frame_1       :  1;
+		__u64 llr_duplicate_frame_2       :  1;
+		__u64 llr_duplicate_frame_3       :  1;
+		__u64 llr_unexpected_frame_0      :  1;
+		__u64 llr_unexpected_frame_1      :  1;
+		__u64 llr_unexpected_frame_2      :  1;
+		__u64 llr_unexpected_frame_3      :  1;
+		__u64 llr_loop_time_fail_0        :  1;
+		__u64 llr_loop_time_fail_1        :  1;
+		__u64 llr_loop_time_fail_2        :  1;
+		__u64 llr_loop_time_fail_3        :  1;
+		__u64 llr_init_fail_0             :  1;
+		__u64 llr_init_fail_1             :  1;
+		__u64 llr_init_fail_2             :  1;
+		__u64 llr_init_fail_3             :  1;
+		__u64 llr_starved_0               :  1;
+		__u64 llr_starved_1               :  1;
+		__u64 llr_starved_2               :  1;
+		__u64 llr_starved_3               :  1;
+		__u64 llr_max_starvation_limit_0  :  1;
+		__u64 llr_max_starvation_limit_1  :  1;
+		__u64 llr_max_starvation_limit_2  :  1;
+		__u64 llr_max_starvation_limit_3  :  1;
+		__u64: 56;
+		__u64 pcs_lanes_locked_0          :  1;
+		__u64 pcs_lanes_locked_1          :  1;
+		__u64 pcs_lanes_locked_2          :  1;
+		__u64 pcs_lanes_locked_3          :  1;
+		__u64 pcs_aligned_0               :  1;
+		__u64 pcs_aligned_1               :  1;
+		__u64 pcs_aligned_2               :  1;
+		__u64 pcs_aligned_3               :  1;
+		__u64 pcs_link_up_0               :  1;
+		__u64 pcs_link_up_1               :  1;
+		__u64 pcs_link_up_2               :  1;
+		__u64 pcs_link_up_3               :  1;
+		__u64 pcs_rx_degrade_rdy          :  1;
+		__u64 pcs_lp_degrade_rdy          :  1;
+		__u64: 2;
+		__u64 autoneg_page_received_0     :  1;
+		__u64 autoneg_page_received_1     :  1;
+		__u64 autoneg_page_received_2     :  1;
+		__u64 autoneg_page_received_3     :  1;
+		__u64 autoneg_complete_0          :  1;
+		__u64 autoneg_complete_1          :  1;
+		__u64 autoneg_complete_2          :  1;
+		__u64 autoneg_complete_3          :  1;
+		__u64 llr_loop_time_0             :  1;
+		__u64 llr_loop_time_1             :  1;
+		__u64 llr_loop_time_2             :  1;
+		__u64 llr_loop_time_3             :  1;
+		__u64 time_stamp_valid_0          :  1;
+		__u64 time_stamp_valid_1          :  1;
+		__u64 time_stamp_valid_2          :  1;
+		__u64 time_stamp_valid_3          :  1;
+		__u64 fec_err_vector_valid        :  1;
+		__u64 llr_init_complete_0         :  1;
+		__u64 llr_init_complete_1         :  1;
+		__u64 llr_init_complete_2         :  1;
+		__u64 llr_init_complete_3         :  1;
+		__u64 event_cnt_ovf               :  1;
+		__u64 rx_signal_ok_0              :  1;
+		__u64 rx_signal_ok_1              :  1;
+		__u64 rx_signal_ok_2              :  1;
+		__u64 rx_signal_ok_3              :  1;
+		__u64: 22;
+	};
+};
+
+#define C1_HNI_PML_ERR_FIRST_FLG_OFFSET	0x00000110
+#define C1_HNI_PML_ERR_FIRST_FLG	(C_HNI_PML_BASE + C1_HNI_PML_ERR_FIRST_FLG_OFFSET)
+#define C1_HNI_PML_ERR_FIRST_FLG_SIZE	0x00000008
+#define SS2_PORT_PML_ERR_FIRST_FLG_OFFSET	0x00000140
+#define SS2_PORT_PML_ERR_FIRST_FLG	(C_HNI_PML_BASE + SS2_PORT_PML_ERR_FIRST_FLG_OFFSET)
+#define SS2_PORT_PML_ERR_FIRST_FLG_SIZE	0x00000020
+#define C1_HNI_PML_ERR_FIRST_FLG_TS_OFFSET	0x00000118
+#define C1_HNI_PML_ERR_FIRST_FLG_TS	(C_HNI_PML_BASE + C1_HNI_PML_ERR_FIRST_FLG_TS_OFFSET)
+#define C_HNI_PML_ERR_FIRST_FLG_TS_SIZE	0x00000008
+#define C1_HNI_PML_ERR_FIRST_FLG_TS_SIZE	C_HNI_PML_ERR_FIRST_FLG_TS_SIZE
+#define SS2_PORT_PML_ERR_FIRST_FLG_TS_OFFSET	0x00000160
+#define SS2_PORT_PML_ERR_FIRST_FLG_TS	(C_HNI_PML_BASE + SS2_PORT_PML_ERR_FIRST_FLG_TS_OFFSET)
+#define SS2_PORT_PML_ERR_FIRST_FLG_TS_SIZE	0x00000008
+#define C1_HNI_PML_ERR_CLR_OFFSET	0x00000120
+#define C1_HNI_PML_ERR_CLR	(C_HNI_PML_BASE + C1_HNI_PML_ERR_CLR_OFFSET)
+#define C1_HNI_PML_ERR_CLR_SIZE	0x00000008
+#define SS2_PORT_PML_ERR_CLR_OFFSET	0x00000180
+#define SS2_PORT_PML_ERR_CLR	(C_HNI_PML_BASE + SS2_PORT_PML_ERR_CLR_OFFSET)
+#define SS2_PORT_PML_ERR_CLR_SIZE	0x00000020
+#define C1_HNI_PML_ERR_IRQA_MSK_OFFSET	0x00000128
+#define C1_HNI_PML_ERR_IRQA_MSK	(C_HNI_PML_BASE + C1_HNI_PML_ERR_IRQA_MSK_OFFSET)
+#define C1_HNI_PML_ERR_IRQA_MSK_SIZE	0x00000008
+#define SS2_PORT_PML_ERR_IRQA_MSK_OFFSET	0x000001a0
+#define SS2_PORT_PML_ERR_IRQA_MSK	(C_HNI_PML_BASE + SS2_PORT_PML_ERR_IRQA_MSK_OFFSET)
+#define SS2_PORT_PML_ERR_IRQA_MSK_SIZE	0x00000020
+#define C1_HNI_PML_ERR_IRQB_MSK_OFFSET	0x00000130
+#define C1_HNI_PML_ERR_IRQB_MSK	(C_HNI_PML_BASE + C1_HNI_PML_ERR_IRQB_MSK_OFFSET)
+#define C1_HNI_PML_ERR_IRQB_MSK_SIZE	0x00000008
+#define SS2_PORT_PML_ERR_IRQB_MSK_OFFSET	0x000001c0
+#define SS2_PORT_PML_ERR_IRQB_MSK	(C_HNI_PML_BASE + SS2_PORT_PML_ERR_IRQB_MSK_OFFSET)
+#define SS2_PORT_PML_ERR_IRQB_MSK_SIZE	0x00000020
+#define C1_HNI_PML_ERR_INFO_MSK_OFFSET	0x00000140
+#define C1_HNI_PML_ERR_INFO_MSK	(C_HNI_PML_BASE + C1_HNI_PML_ERR_INFO_MSK_OFFSET)
+#define C1_HNI_PML_ERR_INFO_MSK_SIZE	0x00000008
+#define SS2_PORT_PML_ERR_INFO_MSK_OFFSET	0x00000200
+#define SS2_PORT_PML_ERR_INFO_MSK	(C_HNI_PML_BASE + SS2_PORT_PML_ERR_INFO_MSK_OFFSET)
+#define SS2_PORT_PML_ERR_INFO_MSK_SIZE	0x00000020
+#define C1_HNI_PML_ERR_INFO_MEM_OFFSET	0x00000180
+#define C1_HNI_PML_ERR_INFO_MEM	(C_HNI_PML_BASE + C1_HNI_PML_ERR_INFO_MEM_OFFSET)
+#define C1_HNI_PML_ERR_INFO_MEM_SIZE	0x00000008
+
+union c1_hni_pml_err_info_mem {
+	__u64 qw;
+	struct {
+		__u64 csr_detected_sbe  :  1;
+		__u64 csr_detected_mbe  :  1;
+		__u64: 2;
+		__u64 sbe_syndrome      : 10;
+		__u64: 2;
+		__u64 sbe_address       : 11;
+		__u64: 1;
+		__u64 sbe_mem_id        :  2;
+		__u64: 6;
+		__u64 mbe_syndrome      : 10;
+		__u64: 2;
+		__u64 mbe_address       : 11;
+		__u64: 1;
+		__u64 mbe_mem_id        :  2;
+		__u64: 2;
+	};
+};
+
+#define C1_HNI_PML_ERR_INFO_MBE_CNTS_OFFSET	0x00000188
+#define C1_HNI_PML_ERR_INFO_MBE_CNTS	(C_HNI_PML_BASE + C1_HNI_PML_ERR_INFO_MBE_CNTS_OFFSET)
+#define C1_HNI_PML_ERR_INFO_MBE_CNTS_SIZE	0x00000008
+
+union c1_hni_pml_err_info_mbe_cnts {
+	__u64 qw;
+	struct {
+		__u64 pcs_fec0_mbe_cnt    :  4;
+		__u64: 4;
+		__u64 pcs_fec1_mbe_cnt    :  4;
+		__u64: 4;
+		__u64 llr_seq_mbe_cnt     :  4;
+		__u64: 4;
+		__u64 llr_replay_mbe_cnt  :  4;
+		__u64: 36;
+	};
+};
+
+#define C1_HNI_PML_ERR_INFO_SBE_CNTS_OFFSET	0x00000190
+#define C1_HNI_PML_ERR_INFO_SBE_CNTS	(C_HNI_PML_BASE + C1_HNI_PML_ERR_INFO_SBE_CNTS_OFFSET)
+#define C1_HNI_PML_ERR_INFO_SBE_CNTS_SIZE	0x00000008
+
+union c1_hni_pml_err_info_sbe_cnts {
+	__u64 qw;
+	struct {
+		__u64 pcs_fec0_sbe_cnt    :  8;
+		__u64 pcs_fec1_sbe_cnt    :  8;
+		__u64 llr_seq_sbe_cnt     :  8;
+		__u64 llr_replay_sbe_cnt  :  8;
+		__u64: 32;
+	};
+};
+
+#define C1_HNI_PML_ERR_INFO_PCS_TX_DP_OFFSET	0x000001a0
+#define C1_HNI_PML_ERR_INFO_PCS_TX_DP	(C_HNI_PML_BASE + C1_HNI_PML_ERR_INFO_PCS_TX_DP_OFFSET)
+#define C1_HNI_PML_ERR_INFO_PCS_TX_DP_SIZE	0x00000008
+
+union c1_hni_pml_err_info_pcs_tx_dp {
+	__u64 qw;
+	struct {
+		__u64 tx_cdc_underrun             :  4;
+		__u64 tx_cdc_overflow             :  4;
+		__u64 tx_mac_if_fifo_overflow     :  1;
+		__u64 tx_mac_if_fifo_starved      :  1;
+		__u64 tx_serdes_if_fifo_overflow  :  1;
+		__u64: 53;
+	};
+};
+
+#define SS2_PORT_PML_ERR_INFO_PCS_TX_DP_OFFSET	0x00000320
+#define SS2_PORT_PML_ERR_INFO_PCS_TX_DP	(C_HNI_PML_BASE + SS2_PORT_PML_ERR_INFO_PCS_TX_DP_OFFSET)
+#define SS2_PORT_PML_ERR_INFO_PCS_TX_DP_SIZE	0x00000008
+
+union ss2_port_pml_err_info_pcs_tx_dp {
+	__u64 qw;
+	struct {
+		__u64 tx_cdc_underrun             :  4;
+		__u64 tx_cdc_overflow             :  4;
+		__u64 tx_mac_if_fifo_overflow     :  1;
+		__u64 tx_mac_if_fifo_starved      :  1;
+		__u64 tx_serdes_if_fifo_overflow  :  1;
+		__u64: 5;
+		__u64 subport                     :  2;
+		__u64: 46;
+	};
+};
+
+#define C1_HNI_PML_ERR_INFO_PCS_RX_DP_OFFSET	0x000001a8
+#define C1_HNI_PML_ERR_INFO_PCS_RX_DP	(C_HNI_PML_BASE + C1_HNI_PML_ERR_INFO_PCS_RX_DP_OFFSET)
+#define C1_HNI_PML_ERR_INFO_PCS_RX_DP_SIZE	0x00000008
+
+union c1_hni_pml_err_info_pcs_rx_dp {
+	__u64 qw;
+	struct {
+		__u64 rx_cdc_overflow        :  4;
+		__u64 rx_rs_buffer_overflow  :  1;
+		__u64: 59;
+	};
+};
+
+#define SS2_PORT_PML_ERR_INFO_PCS_RX_DP_OFFSET	0x00000328
+#define SS2_PORT_PML_ERR_INFO_PCS_RX_DP	(C_HNI_PML_BASE + SS2_PORT_PML_ERR_INFO_PCS_RX_DP_OFFSET)
+#define SS2_PORT_PML_ERR_INFO_PCS_RX_DP_SIZE	0x00000008
+
+union ss2_port_pml_err_info_pcs_rx_dp {
+	__u64 qw;
+	struct {
+		__u64 rx_cdc_overflow        :  4;
+		__u64 rx_rs_buffer_overflow  :  1;
+		__u64: 3;
+		__u64 subport                :  2;
+		__u64: 54;
+	};
+};
+
+#define C1_HNI_PML_ERR_INFO_PCS_RX_DESKEW_OFFSET	0x000001b0
+#define C1_HNI_PML_ERR_INFO_PCS_RX_DESKEW	(C_HNI_PML_BASE + C1_HNI_PML_ERR_INFO_PCS_RX_DESKEW_OFFSET)
+#define C1_HNI_PML_ERR_INFO_PCS_RX_DESKEW_SIZE	0x00000008
+
+union c1_hni_pml_err_info_pcs_rx_deskew {
+	__u64 qw;
+	struct {
+		__u64 rx_deskew_overflow  :  8;
+		__u64: 56;
+	};
+};
+
+#define SS2_PORT_PML_ERR_INFO_PCS_RX_DESKEW_OFFSET	0x00000330
+#define SS2_PORT_PML_ERR_INFO_PCS_RX_DESKEW	(C_HNI_PML_BASE + SS2_PORT_PML_ERR_INFO_PCS_RX_DESKEW_OFFSET)
+#define SS2_PORT_PML_ERR_INFO_PCS_RX_DESKEW_SIZE	0x00000008
+
+union ss2_port_pml_err_info_pcs_rx_deskew {
+	__u64 qw;
+	struct {
+		__u64 rx_deskew_overflow  : 16;
+		__u64: 48;
+	};
+};
+
+#define C1_HNI_PML_ERR_INFO_PCS_RX_DESKEW_PES_OFFSET	0x000001b8
+#define C1_HNI_PML_ERR_INFO_PCS_RX_DESKEW_PES	(C_HNI_PML_BASE + C1_HNI_PML_ERR_INFO_PCS_RX_DESKEW_PES_OFFSET)
+#define C1_HNI_PML_ERR_INFO_PCS_RX_DESKEW_PES_SIZE	0x00000008
+
+union c1_hni_pml_err_info_pcs_rx_deskew_pes {
+	__u64 qw;
+	struct {
+		__u64 deskew_0_pe_cnt  :  8;
+		__u64 deskew_1_pe_cnt  :  8;
+		__u64 deskew_2_pe_cnt  :  8;
+		__u64 deskew_3_pe_cnt  :  8;
+		__u64 deskew_4_pe_cnt  :  8;
+		__u64 deskew_5_pe_cnt  :  8;
+		__u64 deskew_6_pe_cnt  :  8;
+		__u64 deskew_7_pe_cnt  :  8;
+	};
+};
+
+#define SS2_PORT_PML_ERR_INFO_PCS_RX_DESKEW_PES_OFFSET	0x00000338
+#define SS2_PORT_PML_ERR_INFO_PCS_RX_DESKEW_PES	(C_HNI_PML_BASE + SS2_PORT_PML_ERR_INFO_PCS_RX_DESKEW_PES_OFFSET)
+#define SS2_PORT_PML_ERR_INFO_PCS_RX_DESKEW_PES_SIZE	0x00000008
+
+union ss2_port_pml_err_info_pcs_rx_deskew_pes {
+	__u64 qw;
+	struct {
+		__u64 rx_deskew_parity_err  : 16;
+		__u64: 48;
+	};
+};
+
+#define C1_HNI_PML_ERR_INFO_MAC_TX_DP_OFFSET	0x000001c0
+#define C1_HNI_PML_ERR_INFO_MAC_TX_DP	(C_HNI_PML_BASE + C1_HNI_PML_ERR_INFO_MAC_TX_DP_OFFSET)
+#define C1_HNI_PML_ERR_INFO_MAC_TX_DP_SIZE	0x00000008
+
+union c1_hni_pml_err_info_mac_tx_dp {
+	__u64 qw;
+	struct {
+		__u64 tx_llr_if_credit_error   :  1;
+		__u64 tx_llr_if_ctl_par_err    :  1;
+		__u64 tx_llr_if_llr_par_err    :  1;
+		__u64 tx_llr_if_bytes_vld_err  :  1;
+		__u64 tx_llr_if_framing_err    :  1;
+		__u64 tx_llr_if_fcs_16_err     :  1;
+		__u64 tx_mac_gb_underrun       :  1;
+		__u64: 57;
+	};
+};
+
+#define SS2_PORT_PML_ERR_INFO_MAC_TX_DP_OFFSET	0x00000348
+#define SS2_PORT_PML_ERR_INFO_MAC_TX_DP	(C_HNI_PML_BASE + SS2_PORT_PML_ERR_INFO_MAC_TX_DP_OFFSET)
+#define SS2_PORT_PML_ERR_INFO_MAC_TX_DP_SIZE	0x00000008
+
+union ss2_port_pml_err_info_mac_tx_dp {
+	__u64 qw;
+	struct {
+		__u64 tx_llr_if_credit_error     :  1;
+		__u64 tx_llr_if_ctl_par_err      :  1;
+		__u64 tx_llr_if_llr_par_err      :  1;
+		__u64 tx_llr_if_llr_seg_par_err  :  4;
+		__u64 tx_llr_if_bytes_vld_err    :  4;
+		__u64 tx_llr_if_framing_err      :  1;
+		__u64 tx_llr_if_fcs_16_err       :  1;
+		__u64 tx_mac_gb_underrun         :  1;
+		__u64 tx_mac_gb_overflow         :  1;
+		__u64 tx_mac_fifo_overflow       :  1;
+		__u64 subport                    :  2;
+		__u64: 46;
+	};
+};
+
+#define C1_HNI_PML_ERR_INFO_MAC_RX_DP_OFFSET	0x000001c8
+#define C1_HNI_PML_ERR_INFO_MAC_RX_DP	(C_HNI_PML_BASE + C1_HNI_PML_ERR_INFO_MAC_RX_DP_OFFSET)
+#define C1_HNI_PML_ERR_INFO_MAC_RX_DP_SIZE	0x00000008
+
+union c1_hni_pml_err_info_mac_rx_dp {
+	__u64 qw;
+	struct {
+		__u64 rx_mac_gb_err          :  1;
+		__u64 rx_mac_illegal_size    :  1;
+		__u64 rx_mac_fragment        :  1;
+		__u64 rx_mac_preamble_error  :  1;
+		__u64 rx_mac_framing_error   :  1;
+		__u64 rx_mac_fcs32_error     :  1;
+		__u64: 58;
+	};
+};
+
+#define SS2_PORT_PML_ERR_INFO_MAC_RX_DP_OFFSET	0x00000350
+#define SS2_PORT_PML_ERR_INFO_MAC_RX_DP	(C_HNI_PML_BASE + SS2_PORT_PML_ERR_INFO_MAC_RX_DP_OFFSET)
+#define SS2_PORT_PML_ERR_INFO_MAC_RX_DP_SIZE	0x00000008
+
+union ss2_port_pml_err_info_mac_rx_dp {
+	__u64 qw;
+	struct {
+		__u64 rx_mac_illegal_size        :  1;
+		__u64 rx_mac_fragment            :  1;
+		__u64 rx_mac_fifo_overflow       :  1;
+		__u64 rx_mac_short_pkt_buf_ovfw  :  1;
+		__u64: 4;
+		__u64 subport                    :  2;
+		__u64: 54;
+	};
+};
+
+#define C1_HNI_PML_ERR_INFO_LLR_TX_DP_OFFSET	0x000001d0
+#define C1_HNI_PML_ERR_INFO_LLR_TX_DP	(C_HNI_PML_BASE + C1_HNI_PML_ERR_INFO_LLR_TX_DP_OFFSET)
+#define C1_HNI_PML_ERR_INFO_LLR_TX_DP_SIZE	0x00000008
+
+union c1_hni_pml_err_info_llr_tx_dp {
+	__u64 qw;
+	struct {
+		__u64 tx_llr_sbe_syndrome            : 10;
+		__u64 tx_llr_bypass_sbe              :  1;
+		__u64 tx_llr_if_fifo_sbe             :  1;
+		__u64: 4;
+		__u64 tx_llr_mbe_syndrome            : 10;
+		__u64 tx_llr_bypass_mbe              :  1;
+		__u64 tx_llr_if_fifo_mbe             :  1;
+		__u64: 4;
+		__u64 tx_llr_bypass_par_err          :  1;
+		__u64 tx_llr_bypass_overflow_err     :  1;
+		__u64 tx_llr_bypass_illegal_len_err  :  1;
+		__u64 tx_llr_if_fifo_par_err         :  1;
+		__u64 tx_llr_if_fifo_overrun_err     :  1;
+		__u64 tx_llr_if_fifo_len_err         :  1;
+		__u64: 26;
+	};
+};
+
+#define SS2_PORT_PML_ERR_INFO_LLR_TX_DP_OFFSET	0x00000358
+#define SS2_PORT_PML_ERR_INFO_LLR_TX_DP	(C_HNI_PML_BASE + SS2_PORT_PML_ERR_INFO_LLR_TX_DP_OFFSET)
+#define SS2_PORT_PML_ERR_INFO_LLR_TX_DP_SIZE	0x00000008
+
+union ss2_port_pml_err_info_llr_tx_dp {
+	__u64 qw;
+	struct {
+		__u64 tx_llr_bypass_par_err             :  1;
+		__u64 tx_llr_bypass_overflow_err        :  1;
+		__u64 tx_llr_bypass_illegal_len_err     :  1;
+		__u64 tx_llr_if_fifo_seg0_par_err       :  1;
+		__u64 tx_llr_if_fifo_seg1_par_err       :  1;
+		__u64 tx_llr_if_fifo_seg2_par_err       :  1;
+		__u64 tx_llr_if_fifo_seg3_par_err       :  1;
+		__u64 tx_llr_if_fifo_par_err            :  1;
+		__u64 tx_llr_if_fifo_overrun_err        :  1;
+		__u64 tx_llr_if_fifo_len_err            :  1;
+		__u64 tx_llr_bypass_illegal_frame_type  :  1;
+		__u64 tx_llr_input_bus_err              :  1;
+		__u64: 12;
+		__u64 subport                           :  2;
+		__u64: 38;
+	};
+};
+
+#define C_HNI_PML_CFG_GENERAL_OFFSET	0x00000400
+#define C_HNI_PML_CFG_GENERAL	(C_HNI_PML_BASE + C_HNI_PML_CFG_GENERAL_OFFSET)
+#define C_HNI_PML_CFG_GENERAL_SIZE	0x00000008
+
+union c_hni_pml_cfg_general {
+	__u64 qw;
+	struct {
+		__u64 clock_period_ps  : 11;
+		__u64: 53;
+	};
+};
+
+#define C1_HNI_PML_CFG_SERDES_CORE_INTERRUPT_OFFSET	0x00000408
+#define C1_HNI_PML_CFG_SERDES_CORE_INTERRUPT	(C_HNI_PML_BASE + C1_HNI_PML_CFG_SERDES_CORE_INTERRUPT_OFFSET)
+#define C1_HNI_PML_CFG_SERDES_CORE_INTERRUPT_SIZE	0x00000008
+
+union c1_hni_pml_cfg_serdes_core_interrupt {
+	__u64 qw;
+	struct {
+		__u64 set_interrupt_delay           :  8;
+		__u64 clear_interrupt_delay         :  8;
+		__u64 capture_interrupt_data_delay  :  8;
+		__u64: 40;
+	};
+};
+
+#define C1_HNI_PML_SERDES_CORE_INTERRUPT_OFFSET	0x00000410
+#define C1_HNI_PML_SERDES_CORE_INTERRUPT	(C_HNI_PML_BASE + C1_HNI_PML_SERDES_CORE_INTERRUPT_OFFSET)
+#define C1_HNI_PML_SERDES_CORE_INTERRUPT_SIZE	0x00000008
+
+union c1_hni_pml_serdes_core_interrupt {
+	__u64 qw;
+	struct {
+		__u64 core_interrupt_data  : 16;
+		__u64 core_interrupt_code  : 16;
+		__u64 do_core_interrupt    :  1;
+		__u64 serdes_sel           :  2;
+		__u64: 29;
+	};
+};
+
+#define C1_HNI_PML_CFG_PCS_OFFSET	0x00000500
+#define C1_HNI_PML_CFG_PCS	(C_HNI_PML_BASE + C1_HNI_PML_CFG_PCS_OFFSET)
+#define C1_HNI_PML_CFG_PCS_SIZE	0x00000008
+
+union c1_hni_pml_cfg_pcs {
+	__u64 qw;
+	struct {
+		__u64 pcs_enable                :  1;
+		__u64 enable_auto_neg           :  1;
+		__u64: 6;
+		__u64 pcs_mode                  :  2;
+		__u64 enable_auto_lane_degrade  :  1;
+		__u64: 5;
+		__u64 ll_fec                    :  1;
+		__u64: 7;
+		__u64 timestamp_shift           :  2;
+		__u64: 38;
+	};
+};
+
+#define SS2_PORT_PML_CFG_PCS_OFFSET	0x00000500
+#define SS2_PORT_PML_CFG_PCS	(C_HNI_PML_BASE + SS2_PORT_PML_CFG_PCS_OFFSET)
+#define SS2_PORT_PML_CFG_PCS_SIZE	0x00000008
+
+union ss2_port_pml_cfg_pcs {
+	__u64 qw;
+	struct {
+		__u64 pcs_mode                  :  3;
+		__u64 enable_auto_lane_degrade  :  1;
+		__u64 by_25g_fec_mode           :  2;
+		__u64: 10;
+		__u64 timestamp_shift           :  2;
+		__u64: 46;
+	};
+};
+
+#define C1_HNI_PML_CFG_PCS_AUTONEG_OFFSET	0x00000508
+#define C1_HNI_PML_CFG_PCS_AUTONEG	(C_HNI_PML_BASE + C1_HNI_PML_CFG_PCS_AUTONEG_OFFSET)
+#define C1_HNI_PML_CFG_PCS_AUTONEG_SIZE	0x00000008
+
+union c_hni_pml_cfg_pcs_autoneg {
+	__u64 qw;
+	struct {
+		__u64 next_page_loaded  :  1;
+		__u64: 7;
+		__u64 restart           :  1;
+		__u64: 7;
+		__u64 reset             :  1;
+		__u64: 7;
+		__u64 tx_lane           :  2;
+		__u64 rx_lane           :  2;
+		__u64: 36;
+	};
+};
+
+#define SS2_PORT_PML_CFG_PCS_AUTONEG_OFFSET(idx)	(0x00000540 + ((idx) * 8))
+#define SS2_PORT_PML_CFG_PCS_AUTONEG_ENTRIES	4
+#define SS2_PORT_PML_CFG_PCS_AUTONEG(idx)	(C_HNI_PML_BASE + SS2_PORT_PML_CFG_PCS_AUTONEG_OFFSET(idx))
+#define SS2_PORT_PML_CFG_PCS_AUTONEG_SIZE	0x00000020
+
+union ss2_port_pml_cfg_pcs_autoneg {
+	__u64 qw;
+	struct {
+		__u64 next_page_loaded  :  1;
+		__u64: 7;
+		__u64 restart           :  1;
+		__u64: 7;
+		__u64 reset             :  1;
+		__u64: 7;
+		__u64 tx_lane           :  2;
+		__u64 rx_lane           :  2;
+		__u64: 36;
+	};
+};
+
+#define C1_HNI_PML_CFG_PCS_AUTONEG_TIMERS_OFFSET	0x00000510
+#define C1_HNI_PML_CFG_PCS_AUTONEG_TIMERS	(C_HNI_PML_BASE + C1_HNI_PML_CFG_PCS_AUTONEG_TIMERS_OFFSET)
+#define C1_HNI_PML_CFG_PCS_AUTONEG_TIMERS_SIZE	0x00000008
+
+union c1_hni_pml_cfg_pcs_autoneg_timers {
+	__u64 qw;
+	struct {
+		__u64 break_link_timer_max         : 32;
+		__u64 link_fail_inhibit_timer_max  : 32;
+	};
+};
+
+#define SS2_PORT_PML_CFG_PCS_AUTONEG_TIMERS_OFFSET	0x00000560
+#define SS2_PORT_PML_CFG_PCS_AUTONEG_TIMERS	(C_HNI_PML_BASE + SS2_PORT_PML_CFG_PCS_AUTONEG_TIMERS_OFFSET)
+#define SS2_PORT_PML_CFG_PCS_AUTONEG_TIMERS_SIZE	0x00000010
+
+union ss2_port_pml_cfg_pcs_autoneg_timers {
+	__u64 qw[2];
+	struct {
+		__u64 break_link_timer_max         : 32;
+		__u64: 32;
+		__u64 link_fail_inhibit_timer_max  : 34;
+		__u64: 30;
+	};
+};
+
+#define C1_HNI_PML_CFG_PCS_AUTONEG_BASE_PAGE_OFFSET	0x00000518
+#define C1_HNI_PML_CFG_PCS_AUTONEG_BASE_PAGE	(C_HNI_PML_BASE + C1_HNI_PML_CFG_PCS_AUTONEG_BASE_PAGE_OFFSET)
+#define C1_HNI_PML_CFG_PCS_AUTONEG_BASE_PAGE_SIZE	0x00000008
+
+union c_hni_pml_cfg_pcs_autoneg_base_page {
+	__u64 qw;
+	struct {
+		__u64 base_page  : 48;
+		__u64: 16;
+	};
+};
+
+#define SS2_PORT_PML_CFG_PCS_AUTONEG_BASE_PAGE_OFFSET(idx)	(0x00000580 + ((idx) * 8))
+#define SS2_PORT_PML_CFG_PCS_AUTONEG_BASE_PAGE_ENTRIES	4
+#define SS2_PORT_PML_CFG_PCS_AUTONEG_BASE_PAGE(idx)	(C_HNI_PML_BASE + SS2_PORT_PML_CFG_PCS_AUTONEG_BASE_PAGE_OFFSET(idx))
+#define SS2_PORT_PML_CFG_PCS_AUTONEG_BASE_PAGE_SIZE	0x00000020
+
+union ss2_port_pml_cfg_pcs_autoneg_base_page {
+	__u64 qw;
+	struct {
+		__u64 base_page  : 48;
+		__u64: 16;
+	};
+};
+
+#define C1_HNI_PML_CFG_PCS_AUTONEG_NEXT_PAGE_OFFSET	0x00000520
+#define C1_HNI_PML_CFG_PCS_AUTONEG_NEXT_PAGE	(C_HNI_PML_BASE + C1_HNI_PML_CFG_PCS_AUTONEG_NEXT_PAGE_OFFSET)
+#define C1_HNI_PML_CFG_PCS_AUTONEG_NEXT_PAGE_SIZE	0x00000008
+
+union c_hni_pml_cfg_pcs_autoneg_next_page {
+	__u64 qw;
+	struct {
+		__u64 next_page  : 48;
+		__u64: 16;
+	};
+};
+
+#define SS2_PORT_PML_CFG_PCS_AUTONEG_NEXT_PAGE_OFFSET(idx)	(0x000005a0 + ((idx) * 8))
+#define SS2_PORT_PML_CFG_PCS_AUTONEG_NEXT_PAGE_ENTRIES	4
+#define SS2_PORT_PML_CFG_PCS_AUTONEG_NEXT_PAGE(idx)	(C_HNI_PML_BASE + SS2_PORT_PML_CFG_PCS_AUTONEG_NEXT_PAGE_OFFSET(idx))
+#define SS2_PORT_PML_CFG_PCS_AUTONEG_NEXT_PAGE_SIZE	0x00000020
+
+union ss2_port_pml_cfg_pcs_autoneg_next_page {
+	__u64 qw;
+	struct {
+		__u64 next_page  : 48;
+		__u64: 16;
+	};
+};
+
+#define C1_HNI_PML_CFG_PCS_AMS_OFFSET	0x00000528
+#define C1_HNI_PML_CFG_PCS_AMS	(C_HNI_PML_BASE + C1_HNI_PML_CFG_PCS_AMS_OFFSET)
+#define C_HNI_PML_CFG_PCS_AMS_SIZE	0x00000008
+#define C1_HNI_PML_CFG_PCS_AMS_SIZE	C_HNI_PML_CFG_PCS_AMS_SIZE
+
+union c_hni_pml_cfg_pcs_ams {
+	__u64 qw;
+	struct {
+		__u64 am_spacing                   :  4;
+		__u64: 4;
+		__u64 ram_spacing                  :  4;
+		__u64: 12;
+		__u64 use_programmable_am_spacing  :  1;
+		__u64 use_programmable_ams         :  1;
+		__u64: 38;
+	};
+};
+
+#define SS2_PORT_PML_CFG_PCS_AMS_OFFSET	0x000005c0
+#define SS2_PORT_PML_CFG_PCS_AMS	(C_HNI_PML_BASE + SS2_PORT_PML_CFG_PCS_AMS_OFFSET)
+#define SS2_PORT_PML_CFG_PCS_AMS_SIZE	0x00000008
+
+union ss2_port_pml_cfg_pcs_ams {
+	__u64 qw;
+	struct {
+		__u64 am_spacing                   :  4;
+		__u64: 4;
+		__u64 ram_spacing                  :  4;
+		__u64: 12;
+		__u64 use_programmable_am_spacing  :  1;
+		__u64 use_programmable_ams         :  1;
+		__u64: 38;
+	};
+};
+
+#define C1_HNI_PML_CFG_PCS_UM_OFFSET(idx)	(0x00000530 + ((idx) * 8))
+#define C1_HNI_PML_CFG_PCS_UM_ENTRIES	8
+#define C1_HNI_PML_CFG_PCS_UM(idx)	(C_HNI_PML_BASE + C1_HNI_PML_CFG_PCS_UM_OFFSET(idx))
+#define C1_HNI_PML_CFG_PCS_UM_SIZE	0x00000040
+
+union c_hni_pml_cfg_pcs_um {
+	__u64 qw;
+	struct {
+		__u64 um   : 56;
+		__u64: 8;
+	};
+};
+
+#define SS2_PORT_PML_CFG_PCS_UM_OFFSET(idx)	(0x00000600 + ((idx) * 8))
+#define SS2_PORT_PML_CFG_PCS_UM_ENTRIES	16
+#define SS2_PORT_PML_CFG_PCS_UM(idx)	(C_HNI_PML_BASE + SS2_PORT_PML_CFG_PCS_UM_OFFSET(idx))
+#define SS2_PORT_PML_CFG_PCS_UM_SIZE	0x00000080
+
+union ss2_port_pml_cfg_pcs_um {
+	__u64 qw;
+	struct {
+		__u64 um   : 56;
+		__u64: 8;
+	};
+};
+
+#define C1_HNI_PML_CFG_PCS_CM_OFFSET	0x00000570
+#define C1_HNI_PML_CFG_PCS_CM	(C_HNI_PML_BASE + C1_HNI_PML_CFG_PCS_CM_OFFSET)
+#define C_HNI_PML_CFG_PCS_CM_SIZE	0x00000008
+#define C1_HNI_PML_CFG_PCS_CM_SIZE	C_HNI_PML_CFG_PCS_CM_SIZE
+
+union c_hni_pml_cfg_pcs_cm {
+	__u64 qw;
+	struct {
+		__u64 cm;
+	};
+};
+
+#define SS2_PORT_PML_CFG_PCS_CM_OFFSET	0x00000680
+#define SS2_PORT_PML_CFG_PCS_CM	(C_HNI_PML_BASE + SS2_PORT_PML_CFG_PCS_CM_OFFSET)
+#define SS2_PORT_PML_CFG_PCS_CM_SIZE	0x00000008
+
+union ss2_port_pml_cfg_pcs_cm {
+	__u64 qw;
+	struct {
+		__u64 cm;
+	};
+};
+
+#define C1_HNI_PML_CFG_TX_PCS_OFFSET	0x00000578
+#define C1_HNI_PML_CFG_TX_PCS	(C_HNI_PML_BASE + C1_HNI_PML_CFG_TX_PCS_OFFSET)
+#define C1_HNI_PML_CFG_TX_PCS_SIZE	0x00000008
+
+union c1_hni_pml_cfg_tx_pcs {
+	__u64 qw;
+	struct {
+		__u64 lane_0_source       :  2;
+		__u64: 6;
+		__u64 lane_1_source       :  2;
+		__u64: 6;
+		__u64 lane_2_source       :  2;
+		__u64: 6;
+		__u64 lane_3_source       :  2;
+		__u64: 6;
+		__u64 enable_ctl_os       :  1;
+		__u64 allow_auto_degrade  :  1;
+		__u64: 6;
+		__u64 gearbox_credits     :  4;
+		__u64: 4;
+		__u64 cdc_ready_level     :  4;
+		__u64: 12;
+	};
+};
+
+#define SS2_PORT_PML_CFG_TX_PCS_OFFSET	0x00000688
+#define SS2_PORT_PML_CFG_TX_PCS	(C_HNI_PML_BASE + SS2_PORT_PML_CFG_TX_PCS_OFFSET)
+#define SS2_PORT_PML_CFG_TX_PCS_SIZE	0x00000008
+
+union ss2_port_pml_cfg_tx_pcs {
+	__u64 qw;
+	struct {
+		__u64 lane_0_source       :  2;
+		__u64: 6;
+		__u64 lane_1_source       :  2;
+		__u64: 6;
+		__u64 lane_2_source       :  2;
+		__u64: 6;
+		__u64 lane_3_source       :  2;
+		__u64: 6;
+		__u64 allow_auto_degrade  :  1;
+		__u64: 7;
+		__u64 cdc_ready_level     :  4;
+		__u64 en_pk_bw_limiter    :  1;
+		__u64: 19;
+	};
+};
+
+#define C1_HNI_PML_CFG_RX_PCS_OFFSET	0x00000580
+#define C1_HNI_PML_CFG_RX_PCS	(C_HNI_PML_BASE + C1_HNI_PML_CFG_RX_PCS_OFFSET)
+#define C1_HNI_PML_CFG_RX_PCS_SIZE	0x00000008
+
+union c1_hni_pml_cfg_rx_pcs {
+	__u64 qw;
+	struct {
+		__u64 active_lanes               :  4;
+		__u64: 4;
+		__u64 rs_mode                    :  3;
+		__u64: 5;
+		__u64 enable_lock                :  1;
+		__u64 restart_lock_on_bad_ams    :  1;
+		__u64 restart_lock_on_bad_cws    :  1;
+		__u64: 5;
+		__u64 enable_ctl_os              :  1;
+		__u64: 7;
+		__u64 health_bad_sensitivity     :  4;
+		__u64 lp_health_bad_sensitivity  :  1;
+		__u64: 3;
+		__u64 allow_auto_degrade         :  1;
+		__u64: 7;
+		__u64 enable_rx_sm               :  1;
+		__u64: 15;
+	};
+};
+
+#define SS2_PORT_PML_CFG_RX_PCS_OFFSET	0x000006c0
+#define SS2_PORT_PML_CFG_RX_PCS	(C_HNI_PML_BASE + SS2_PORT_PML_CFG_RX_PCS_OFFSET)
+#define SS2_PORT_PML_CFG_RX_PCS_SIZE	0x00000008
+
+union ss2_port_pml_cfg_rx_pcs {
+	__u64 qw;
+	struct {
+		__u64 active_lanes               :  4;
+		__u64 cw_gap_544                 :  5;
+		__u64 cw_gap_ll                  :  5;
+		__u64 cw_gap_one_fec             :  5;
+		__u64 restart_lock_on_bad_ams    :  1;
+		__u64 restart_lock_on_bad_cws    :  1;
+		__u64 health_bad_sensitivity     :  4;
+		__u64 lp_health_bad_sensitivity  :  1;
+		__u64 allow_auto_degrade         :  1;
+		__u64 lane_0_source              :  2;
+		__u64 lane_1_source              :  2;
+		__u64 lane_2_source              :  2;
+		__u64 lane_3_source              :  2;
+		__u64 signal_detect_enn          :  4;
+		__u64 rx_lock_enn                :  4;
+		__u64 rx_clk_vld_enn             :  4;
+		__u64: 17;
+	};
+};
+
+#define C1_HNI_PML_CFG_RX_PCS_AMS_OFFSET	0x00000588
+#define C1_HNI_PML_CFG_RX_PCS_AMS	(C_HNI_PML_BASE + C1_HNI_PML_CFG_RX_PCS_AMS_OFFSET)
+#define C_HNI_PML_CFG_RX_PCS_AMS_SIZE	0x00000008
+#define C1_HNI_PML_CFG_RX_PCS_AMS_SIZE	C_HNI_PML_CFG_RX_PCS_AMS_SIZE
+
+union c_hni_pml_cfg_rx_pcs_ams {
+	__u64 qw;
+	struct {
+		__u64 cm_match_mask  : 16;
+		__u64 um_match_mask  : 14;
+		__u64: 34;
+	};
+};
+
+#define SS2_PORT_PML_CFG_RX_PCS_AMS_OFFSET	0x00000700
+#define SS2_PORT_PML_CFG_RX_PCS_AMS	(C_HNI_PML_BASE + SS2_PORT_PML_CFG_RX_PCS_AMS_OFFSET)
+#define SS2_PORT_PML_CFG_RX_PCS_AMS_SIZE	0x00000008
+
+union ss2_port_pml_cfg_rx_pcs_ams {
+	__u64 qw;
+	struct {
+		__u64 cm_match_mask  : 16;
+		__u64 um_match_mask  : 14;
+		__u64: 34;
+	};
+};
+
+#define C1_HNI_PML_CFG_TX_MAC_OFFSET	0x00000600
+#define C1_HNI_PML_CFG_TX_MAC	(C_HNI_PML_BASE + C1_HNI_PML_CFG_TX_MAC_OFFSET)
+#define C1_HNI_PML_CFG_TX_MAC_SIZE	0x00000008
+
+union c1_hni_pml_cfg_tx_mac {
+	__u64 qw;
+	struct {
+		__u64 mac_operational         :  1;
+		__u64 short_preamble          :  1;
+		__u64: 6;
+		__u64 pcs_credits             :  4;
+		__u64: 4;
+		__u64 ifg_mode                :  1;
+		__u64: 3;
+		__u64 vs_version              :  4;
+		__u64 ieee_ifg_adjustment     :  2;
+		__u64 non_portals_sof_window  :  5;
+		__u64 non_portals_max_sof     :  4;
+		__u64 any_frame_sof_window_0  :  5;
+		__u64 any_frame_max_sof_0     :  4;
+		__u64 any_frame_sof_window_1  :  5;
+		__u64 any_frame_max_sof_1     :  4;
+		__u64 portals_protocol        :  8;
+		__u64: 3;
+	};
+};
+
+#define SS2_PORT_PML_CFG_TX_MAC_OFFSET	0x00000800
+#define SS2_PORT_PML_CFG_TX_MAC	(C_HNI_PML_BASE + SS2_PORT_PML_CFG_TX_MAC_OFFSET)
+#define SS2_PORT_PML_CFG_TX_MAC_SIZE	0x00000008
+
+union ss2_port_pml_cfg_tx_mac {
+	__u64 qw;
+	struct {
+		__u64 ifg_mode                :  1;
+		__u64 min_ifg                 :  3;
+		__u64 mac_pad_idle_thresh     :  8;
+		__u64: 1;
+		__u64 ieee_ifg_adjustment     :  3;
+		__u64 vs_version              :  4;
+		__u64: 6;
+		__u64 non_st_sof_window       :  6;
+		__u64 non_st_max_sof          :  3;
+		__u64 any_frame_sof_window_0  :  6;
+		__u64 any_frame_max_sof_0     :  3;
+		__u64: 10;
+		__u64 st_protocol             :  8;
+		__u64: 2;
+	};
+};
+
+#define C1_HNI_PML_CFG_RX_MAC_OFFSET	0x00000608
+#define C1_HNI_PML_CFG_RX_MAC	(C_HNI_PML_BASE + C1_HNI_PML_CFG_RX_MAC_OFFSET)
+#define C1_HNI_PML_CFG_RX_MAC_SIZE	0x00000008
+
+union c1_hni_pml_cfg_rx_mac {
+	__u64 qw;
+	struct {
+		__u64 mac_operational      :  1;
+		__u64 short_preamble       :  1;
+		__u64: 6;
+		__u64 filter_illegal_size  :  1;
+		__u64: 55;
+	};
+};
+
+#define SS2_PORT_PML_CFG_RX_MAC_OFFSET	0x00000840
+#define SS2_PORT_PML_CFG_RX_MAC	(C_HNI_PML_BASE + SS2_PORT_PML_CFG_RX_MAC_OFFSET)
+#define SS2_PORT_PML_CFG_RX_MAC_SIZE	0x00000008
+
+union ss2_port_pml_cfg_rx_mac {
+	__u64 qw;
+	struct {
+		__u64 flit_packing_cnt  :  4;
+		__u64 stop_packing      :  1;
+		__u64: 59;
+	};
+};
+
+#define C1_HNI_PML_CFG_LLR_OFFSET	0x00000700
+#define C1_HNI_PML_CFG_LLR	(C_HNI_PML_BASE + C1_HNI_PML_CFG_LLR_OFFSET)
+#define C1_HNI_PML_CFG_LLR_SIZE	0x00000008
+
+union c1_hni_pml_cfg_llr {
+	__u64 qw;
+	struct {
+		__u64 llr_mode                  :  2;
+		__u64: 6;
+		__u64 mac_if_credits            :  4;
+		__u64: 4;
+		__u64 link_down_behavior        :  2;
+		__u64: 6;
+		__u64 enable_loop_timing        :  1;
+		__u64: 7;
+		__u64 size                      :  2;
+		__u64: 6;
+		__u64 filter_ctl_frames         :  1;
+		__u64 filter_lossless_when_off  :  1;
+		__u64 ack_nack_err_check        :  1;
+		__u64 preamble_seq_check        :  1;
+		__u64: 20;
+	};
+};
+
+#define SS2_PORT_PML_CFG_LLR_OFFSET	0x00000900
+#define SS2_PORT_PML_CFG_LLR	(C_HNI_PML_BASE + SS2_PORT_PML_CFG_LLR_OFFSET)
+#define SS2_PORT_PML_CFG_LLR_SIZE	0x00000008
+
+union ss2_port_pml_cfg_llr {
+	__u64 qw;
+	struct {
+		__u64 size                :  1;
+		__u64: 7;
+		__u64 ack_nack_err_check  :  1;
+		__u64 preamble_seq_check  :  1;
+		__u64: 6;
+		__u64 stop_packing        :  1;
+		__u64: 47;
+	};
+};
+
+#define C1_HNI_PML_CFG_LLR_CF_SMAC_OFFSET	0x00000710
+#define C1_HNI_PML_CFG_LLR_CF_SMAC	(C_HNI_PML_BASE + C1_HNI_PML_CFG_LLR_CF_SMAC_OFFSET)
+#define C_HNI_PML_CFG_LLR_CF_SMAC_SIZE	0x00000008
+#define C1_HNI_PML_CFG_LLR_CF_SMAC_SIZE	C_HNI_PML_CFG_LLR_CF_SMAC_SIZE
+
+union c_hni_pml_cfg_llr_cf_smac {
+	__u64 qw;
+	struct {
+		__u64 ctl_frame_smac  : 48;
+		__u64: 16;
+	};
+};
+
+#define SS2_PORT_PML_CFG_LLR_CF_SMAC_OFFSET	0x00000948
+#define SS2_PORT_PML_CFG_LLR_CF_SMAC	(C_HNI_PML_BASE + SS2_PORT_PML_CFG_LLR_CF_SMAC_OFFSET)
+#define SS2_PORT_PML_CFG_LLR_CF_SMAC_SIZE	0x00000008
+
+union ss2_port_pml_cfg_llr_cf_smac {
+	__u64 qw;
+	struct {
+		__u64 ctl_frame_smac  : 48;
+		__u64: 16;
+	};
+};
+
+#define C1_HNI_PML_CFG_LLR_CF_ETYPE_OFFSET	0x00000718
+#define C1_HNI_PML_CFG_LLR_CF_ETYPE	(C_HNI_PML_BASE + C1_HNI_PML_CFG_LLR_CF_ETYPE_OFFSET)
+#define C_HNI_PML_CFG_LLR_CF_ETYPE_SIZE	0x00000008
+#define C1_HNI_PML_CFG_LLR_CF_ETYPE_SIZE	C_HNI_PML_CFG_LLR_CF_ETYPE_SIZE
+
+union c_hni_pml_cfg_llr_cf_etype {
+	__u64 qw;
+	struct {
+		__u64 ctl_frame_ethertype  : 16;
+		__u64: 48;
+	};
+};
+
+#define SS2_PORT_PML_CFG_LLR_CF_ETYPE_OFFSET	0x00000950
+#define SS2_PORT_PML_CFG_LLR_CF_ETYPE	(C_HNI_PML_BASE + SS2_PORT_PML_CFG_LLR_CF_ETYPE_OFFSET)
+#define SS2_PORT_PML_CFG_LLR_CF_ETYPE_SIZE	0x00000008
+
+union ss2_port_pml_cfg_llr_cf_etype {
+	__u64 qw;
+	struct {
+		__u64 ctl_frame_ethertype  : 16;
+		__u64: 48;
+	};
+};
+
+#define C1_HNI_PML_CFG_LLR_CF_RATES_OFFSET	0x00000720
+#define C1_HNI_PML_CFG_LLR_CF_RATES	(C_HNI_PML_BASE + C1_HNI_PML_CFG_LLR_CF_RATES_OFFSET)
+#define C1_HNI_PML_CFG_LLR_CF_RATES_SIZE	0x00000008
+
+union c_hni_pml_cfg_llr_cf_rates {
+	__u64 qw;
+	struct {
+		__u64 loop_timing_period  : 16;
+		__u64 init_ctl_os_period  :  4;
+		__u64: 44;
+	};
+};
+
+#define SS2_PORT_PML_CFG_LLR_CF_RATES_OFFSET(idx)	(0x00000960 + ((idx) * 8))
+#define SS2_PORT_PML_CFG_LLR_CF_RATES_ENTRIES	4
+#define SS2_PORT_PML_CFG_LLR_CF_RATES(idx)	(C_HNI_PML_BASE + SS2_PORT_PML_CFG_LLR_CF_RATES_OFFSET(idx))
+#define SS2_PORT_PML_CFG_LLR_CF_RATES_SIZE	0x00000020
+
+union ss2_port_pml_cfg_llr_cf_rates {
+	__u64 qw;
+	struct {
+		__u64 loop_timing_period  : 16;
+		__u64 init_ctl_os_period  :  4;
+		__u64: 44;
+	};
+};
+
+#define C1_HNI_PML_CFG_LLR_SM_OFFSET	0x00000728
+#define C1_HNI_PML_CFG_LLR_SM	(C_HNI_PML_BASE + C1_HNI_PML_CFG_LLR_SM_OFFSET)
+#define C1_HNI_PML_CFG_LLR_SM_SIZE	0x00000008
+
+union c_hni_pml_cfg_llr_sm {
+	__u64 qw;
+	struct {
+		__u64 replay_timer_max  : 16;
+		__u64 replay_ct_max     :  8;
+		__u64 allow_re_init     :  1;
+		__u64: 7;
+		__u64 retry_threshold   :  8;
+		__u64: 24;
+	};
+};
+
+#define SS2_PORT_PML_CFG_LLR_SM_OFFSET(idx)	(0x00000980 + ((idx) * 8))
+#define SS2_PORT_PML_CFG_LLR_SM_ENTRIES	4
+#define SS2_PORT_PML_CFG_LLR_SM(idx)	(C_HNI_PML_BASE + SS2_PORT_PML_CFG_LLR_SM_OFFSET(idx))
+#define SS2_PORT_PML_CFG_LLR_SM_SIZE	0x00000020
+
+union ss2_port_pml_cfg_llr_sm {
+	__u64 qw;
+	struct {
+		__u64 replay_timer_max  : 16;
+		__u64 replay_ct_max     :  8;
+		__u64 allow_re_init     :  1;
+		__u64: 7;
+		__u64 retry_threshold   :  8;
+		__u64: 24;
+	};
+};
+
+#define C1_HNI_PML_CFG_LLR_CAPACITY_OFFSET	0x00000730
+#define C1_HNI_PML_CFG_LLR_CAPACITY	(C_HNI_PML_BASE + C1_HNI_PML_CFG_LLR_CAPACITY_OFFSET)
+#define C1_HNI_PML_CFG_LLR_CAPACITY_SIZE	0x00000008
+
+union c1_hni_pml_cfg_llr_capacity {
+	__u64 qw;
+	struct {
+		__u64 max_seq   : 12;
+		__u64: 4;
+		__u64 max_data  : 12;
+		__u64: 36;
+	};
+};
+
+#define SS2_PORT_PML_CFG_LLR_CAPACITY_OFFSET(idx)	(0x000009a0 + ((idx) * 8))
+#define SS2_PORT_PML_CFG_LLR_CAPACITY_ENTRIES	4
+#define SS2_PORT_PML_CFG_LLR_CAPACITY(idx)	(C_HNI_PML_BASE + SS2_PORT_PML_CFG_LLR_CAPACITY_OFFSET(idx))
+#define SS2_PORT_PML_CFG_LLR_CAPACITY_SIZE	0x00000020
+
+union ss2_port_pml_cfg_llr_capacity {
+	__u64 qw;
+	struct {
+		__u64 max_seq   : 12;
+		__u64: 4;
+		__u64 max_data  : 12;
+		__u64: 4;
+		__u64: 32;
+	};
+};
+
+#define C1_HNI_PML_CFG_LLR_TIMEOUTS_OFFSET	0x00000738
+#define C1_HNI_PML_CFG_LLR_TIMEOUTS	(C_HNI_PML_BASE + C1_HNI_PML_CFG_LLR_TIMEOUTS_OFFSET)
+#define C1_HNI_PML_CFG_LLR_TIMEOUTS_SIZE	0x00000008
+
+union c_hni_pml_cfg_llr_timeouts {
+	__u64 qw;
+	struct {
+		__u64 pcs_link_dn_timer_max  : 32;
+		__u64 data_age_timer_max     : 32;
+	};
+};
+
+#define SS2_PORT_PML_CFG_LLR_TIMEOUTS_OFFSET(idx)	(0x000009c0 + ((idx) * 8))
+#define SS2_PORT_PML_CFG_LLR_TIMEOUTS_ENTRIES	4
+#define SS2_PORT_PML_CFG_LLR_TIMEOUTS(idx)	(C_HNI_PML_BASE + SS2_PORT_PML_CFG_LLR_TIMEOUTS_OFFSET(idx))
+#define SS2_PORT_PML_CFG_LLR_TIMEOUTS_SIZE	0x00000020
+
+union ss2_port_pml_cfg_llr_timeouts {
+	__u64 qw;
+	struct {
+		__u64 pcs_link_dn_timer_max  : 32;
+		__u64 data_age_timer_max     : 32;
+	};
+};
+
+#define C1_HNI_PML_SERDES_CORE_STATUS_OFFSET(idx)	(0x00000800 + ((idx) * 8))
+#define C1_HNI_PML_SERDES_CORE_STATUS_ENTRIES	4
+#define C1_HNI_PML_SERDES_CORE_STATUS(idx)	(C_HNI_PML_BASE + C1_HNI_PML_SERDES_CORE_STATUS_OFFSET(idx))
+#define C1_HNI_PML_SERDES_CORE_STATUS_SIZE	0x00000020
+
+union c1_hni_pml_serdes_core_status {
+	__u64 qw;
+	struct {
+		__u64 core_status     : 32;
+		__u64 rx_idle_detect  :  1;
+		__u64 rx_rdy          :  1;
+		__u64 tx_rdy          :  1;
+		__u64: 29;
+	};
+};
+
+#define C1_HNI_PML_STS_PCS_AUTONEG_BASE_PAGE_OFFSET	0x00000820
+#define C1_HNI_PML_STS_PCS_AUTONEG_BASE_PAGE	(C_HNI_PML_BASE + C1_HNI_PML_STS_PCS_AUTONEG_BASE_PAGE_OFFSET)
+#define C1_HNI_PML_STS_PCS_AUTONEG_BASE_PAGE_SIZE	0x00000008
+
+union c_hni_pml_sts_pcs_autoneg_base_page {
+	__u64 qw;
+	struct {
+		__u64 lp_base_page      : 48;
+		__u64 lp_ability        :  1;
+		__u64 page_received     :  1;
+		__u64 base_page         :  1;
+		__u64 state             :  4;
+		__u64 complete          :  1;
+		__u64 remaining_ack_ct  :  3;
+		__u64 ack_match_ct      :  2;
+		__u64 ability_match_ct  :  2;
+		__u64: 1;
+	};
+};
+
+#define SS2_PORT_PML_STS_PCS_AUTONEG_BASE_PAGE_OFFSET(idx)	(0x00001300 + ((idx) * 8))
+#define SS2_PORT_PML_STS_PCS_AUTONEG_BASE_PAGE_ENTRIES	4
+#define SS2_PORT_PML_STS_PCS_AUTONEG_BASE_PAGE(idx)	(C_HNI_PML_BASE + SS2_PORT_PML_STS_PCS_AUTONEG_BASE_PAGE_OFFSET(idx))
+#define SS2_PORT_PML_STS_PCS_AUTONEG_BASE_PAGE_SIZE	0x00000020
+
+union ss2_port_pml_sts_pcs_autoneg_base_page {
+	__u64 qw;
+	struct {
+		__u64 lp_base_page      : 48;
+		__u64 lp_ability        :  1;
+		__u64 page_received     :  1;
+		__u64 base_page         :  1;
+		__u64 state             :  4;
+		__u64 complete          :  1;
+		__u64 remaining_ack_ct  :  3;
+		__u64 ack_match_ct      :  2;
+		__u64 ability_match_ct  :  2;
+		__u64: 1;
+	};
+};
+
+#define C1_HNI_PML_STS_PCS_AUTONEG_NEXT_PAGE_OFFSET	0x00000828
+#define C1_HNI_PML_STS_PCS_AUTONEG_NEXT_PAGE	(C_HNI_PML_BASE + C1_HNI_PML_STS_PCS_AUTONEG_NEXT_PAGE_OFFSET)
+#define C1_HNI_PML_STS_PCS_AUTONEG_NEXT_PAGE_SIZE	0x00000008
+
+union c_hni_pml_sts_pcs_autoneg_next_page {
+	__u64 qw;
+	struct {
+		__u64 lp_next_page      : 48;
+		__u64 lp_ability        :  1;
+		__u64 page_received     :  1;
+		__u64 base_page         :  1;
+		__u64 state             :  4;
+		__u64 complete          :  1;
+		__u64 remaining_ack_ct  :  3;
+		__u64 ack_match_ct      :  2;
+		__u64 ability_match_ct  :  2;
+		__u64: 1;
+	};
+};
+
+#define SS2_PORT_PML_STS_PCS_AUTONEG_NEXT_PAGE_OFFSET(idx)	(0x00001320 + ((idx) * 8))
+#define SS2_PORT_PML_STS_PCS_AUTONEG_NEXT_PAGE_ENTRIES	4
+#define SS2_PORT_PML_STS_PCS_AUTONEG_NEXT_PAGE(idx)	(C_HNI_PML_BASE + SS2_PORT_PML_STS_PCS_AUTONEG_NEXT_PAGE_OFFSET(idx))
+#define SS2_PORT_PML_STS_PCS_AUTONEG_NEXT_PAGE_SIZE	0x00000020
+
+union ss2_port_pml_sts_pcs_autoneg_next_page {
+	__u64 qw;
+	struct {
+		__u64 lp_next_page      : 48;
+		__u64 lp_ability        :  1;
+		__u64 page_received     :  1;
+		__u64 base_page         :  1;
+		__u64 state             :  4;
+		__u64 complete          :  1;
+		__u64 remaining_ack_ct  :  3;
+		__u64 ack_match_ct      :  2;
+		__u64 ability_match_ct  :  2;
+		__u64: 1;
+	};
+};
+
+#define C1_HNI_PML_STS_TX_PCS_OFFSET	0x00000830
+#define C1_HNI_PML_STS_TX_PCS	(C_HNI_PML_BASE + C1_HNI_PML_STS_TX_PCS_OFFSET)
+#define C1_HNI_PML_STS_TX_PCS_SIZE	0x00000008
+
+union c_hni_pml_sts_tx_pcs {
+	__u64 qw;
+	struct {
+		__u64 timestamp        : 32;
+		__u64 timestamp_valid  :  1;
+		__u64: 31;
+	};
+};
+
+#define SS2_PORT_PML_STS_TX_PCS_OFFSET(idx)	(0x00001340 + ((idx) * 8))
+#define SS2_PORT_PML_STS_TX_PCS_ENTRIES	4
+#define SS2_PORT_PML_STS_TX_PCS(idx)	(C_HNI_PML_BASE + SS2_PORT_PML_STS_TX_PCS_OFFSET(idx))
+#define SS2_PORT_PML_STS_TX_PCS_SIZE	0x00000020
+
+union ss2_port_pml_sts_tx_pcs {
+	__u64 qw;
+	struct {
+		__u64 timestamp        : 32;
+		__u64 timestamp_valid  :  1;
+		__u64: 31;
+	};
+};
+
+#define C1_HNI_PML_STS_RX_PCS_OFFSET	0x00000838
+#define C1_HNI_PML_STS_RX_PCS	(C_HNI_PML_BASE + C1_HNI_PML_STS_RX_PCS_OFFSET)
+#define C1_HNI_PML_STS_RX_PCS_SIZE	0x00000008
+
+union c1_hni_pml_sts_rx_pcs {
+	__u64 qw;
+	struct {
+		__u64 am_identity_0  :  3;
+		__u64: 1;
+		__u64 am_identity_1  :  3;
+		__u64: 1;
+		__u64 am_identity_2  :  3;
+		__u64: 1;
+		__u64 am_identity_3  :  3;
+		__u64: 1;
+		__u64 am_identity_4  :  3;
+		__u64: 1;
+		__u64 am_identity_5  :  3;
+		__u64: 1;
+		__u64 am_identity_6  :  3;
+		__u64: 1;
+		__u64 am_identity_7  :  3;
+		__u64: 1;
+		__u64 am_lock        :  8;
+		__u64 align_status   :  1;
+		__u64: 7;
+		__u64 fault          :  1;
+		__u64 local_fault    :  1;
+		__u64 hi_ser         :  1;
+		__u64: 13;
+	};
+};
+
+#define C1_HNI_PML_STS_RX_PCS_AM_MATCH_OFFSET	0x00000840
+#define C1_HNI_PML_STS_RX_PCS_AM_MATCH	(C_HNI_PML_BASE + C1_HNI_PML_STS_RX_PCS_AM_MATCH_OFFSET)
+#define C1_HNI_PML_STS_RX_PCS_AM_MATCH_SIZE	0x00000008
+
+union c1_hni_pml_sts_rx_pcs_am_match {
+	__u64 qw;
+	struct {
+		__u64 am_match_state_0  :  2;
+		__u64 am_match_pos_0    :  6;
+		__u64 am_match_state_1  :  2;
+		__u64 am_match_pos_1    :  6;
+		__u64 am_match_state_2  :  2;
+		__u64 am_match_pos_2    :  6;
+		__u64 am_match_state_3  :  2;
+		__u64 am_match_pos_3    :  6;
+		__u64 am_match_state_4  :  2;
+		__u64 am_match_pos_4    :  6;
+		__u64 am_match_state_5  :  2;
+		__u64 am_match_pos_5    :  6;
+		__u64 am_match_state_6  :  2;
+		__u64 am_match_pos_6    :  6;
+		__u64 am_match_state_7  :  2;
+		__u64 am_match_pos_7    :  6;
+	};
+};
+
+#define C1_HNI_PML_STS_RX_PCS_FECL_SOURCES_OFFSET	0x00000848
+#define C1_HNI_PML_STS_RX_PCS_FECL_SOURCES	(C_HNI_PML_BASE + C1_HNI_PML_STS_RX_PCS_FECL_SOURCES_OFFSET)
+#define C1_HNI_PML_STS_RX_PCS_FECL_SOURCES_SIZE	0x00000008
+
+union c1_hni_pml_sts_rx_pcs_fecl_sources {
+	__u64 qw;
+	struct {
+		__u64 fecl_source_0      :  3;
+		__u64 fecl_source_vld_0  :  1;
+		__u64: 4;
+		__u64 fecl_source_1      :  3;
+		__u64 fecl_source_vld_1  :  1;
+		__u64: 4;
+		__u64 fecl_source_2      :  3;
+		__u64 fecl_source_vld_2  :  1;
+		__u64: 4;
+		__u64 fecl_source_3      :  3;
+		__u64 fecl_source_vld_3  :  1;
+		__u64: 4;
+		__u64 fecl_source_4      :  3;
+		__u64 fecl_source_vld_4  :  1;
+		__u64: 4;
+		__u64 fecl_source_5      :  3;
+		__u64 fecl_source_vld_5  :  1;
+		__u64: 4;
+		__u64 fecl_source_6      :  3;
+		__u64 fecl_source_vld_6  :  1;
+		__u64: 4;
+		__u64 fecl_source_7      :  3;
+		__u64 fecl_source_vld_7  :  1;
+		__u64: 4;
+	};
+};
+
+#define C1_HNI_PML_STS_RX_PCS_DESKEW_DEPTHS_OFFSET	0x00000850
+#define C1_HNI_PML_STS_RX_PCS_DESKEW_DEPTHS	(C_HNI_PML_BASE + C1_HNI_PML_STS_RX_PCS_DESKEW_DEPTHS_OFFSET)
+#define C1_HNI_PML_STS_RX_PCS_DESKEW_DEPTHS_SIZE	0x00000008
+
+union c1_hni_pml_sts_rx_pcs_deskew_depths {
+	__u64 qw;
+	struct {
+		__u64 df_depth_0  :  8;
+		__u64 df_depth_1  :  8;
+		__u64 df_depth_2  :  8;
+		__u64 df_depth_3  :  8;
+		__u64 df_depth_4  :  8;
+		__u64 df_depth_5  :  8;
+		__u64 df_depth_6  :  8;
+		__u64 df_depth_7  :  8;
+	};
+};
+
+#define C1_HNI_PML_STS_PCS_LANE_DEGRADE_OFFSET	0x00000868
+#define C1_HNI_PML_STS_PCS_LANE_DEGRADE	(C_HNI_PML_BASE + C1_HNI_PML_STS_PCS_LANE_DEGRADE_OFFSET)
+#define C1_HNI_PML_STS_PCS_LANE_DEGRADE_SIZE	0x00000008
+
+union c1_hni_pml_sts_pcs_lane_degrade {
+	__u64 qw;
+	struct {
+		__u64 rx_fecl_health_good  :  8;
+		__u64 lp_pls_available     :  4;
+		__u64: 4;
+		__u64 rx_state             :  2;
+		__u64: 2;
+		__u64 rx_pls_available     :  4;
+		__u64 tx_state             :  2;
+		__u64: 2;
+		__u64 tx_lane              :  2;
+		__u64: 2;
+		__u64 lp_health_bad_0      :  4;
+		__u64 lp_health_bad_1      :  4;
+		__u64 lp_health_bad_2      :  4;
+		__u64 lp_health_bad_3      :  4;
+		__u64 lp_health_good_0     :  4;
+		__u64 lp_health_good_1     :  4;
+		__u64 lp_health_good_2     :  4;
+		__u64 lp_health_good_3     :  4;
+	};
+};
+
+#define SS2_PORT_PML_STS_PCS_LANE_DEGRADE_OFFSET	0x00001460
+#define SS2_PORT_PML_STS_PCS_LANE_DEGRADE	(C_HNI_PML_BASE + SS2_PORT_PML_STS_PCS_LANE_DEGRADE_OFFSET)
+#define SS2_PORT_PML_STS_PCS_LANE_DEGRADE_SIZE	0x00000010
+
+union ss2_port_pml_sts_pcs_lane_degrade {
+	__u64 qw[2];
+	struct {
+		__u64 rx_fecl_health_good  : 16;
+		__u64 lp_pls_available     :  4;
+		__u64 rx_state             :  3;
+		__u64: 1;
+		__u64 rx_pls_available     :  4;
+		__u64 tx_state             :  3;
+		__u64: 1;
+		__u64 tx_lane              :  2;
+		__u64: 2;
+		__u64 degrade_failure      :  1;
+		__u64 degrading            :  1;
+		__u64: 26;
+		__u64 lp_health_bad_0      :  5;
+		__u64: 3;
+		__u64 lp_health_bad_1      :  5;
+		__u64: 3;
+		__u64 lp_health_bad_2      :  5;
+		__u64: 3;
+		__u64 lp_health_bad_3      :  5;
+		__u64: 3;
+		__u64 lp_health_good_0     :  5;
+		__u64: 3;
+		__u64 lp_health_good_1     :  5;
+		__u64: 3;
+		__u64 lp_health_good_2     :  5;
+		__u64: 3;
+		__u64 lp_health_good_3     :  5;
+		__u64: 3;
+	};
+};
+
+#define C1_HNI_PML_STS_LLR_OFFSET	0x00000a00
+#define C1_HNI_PML_STS_LLR	(C_HNI_PML_BASE + C1_HNI_PML_STS_LLR_OFFSET)
+#define C1_HNI_PML_STS_LLR_SIZE	0x00000008
+
+union c_hni_pml_sts_llr {
+	__u64 qw;
+	struct {
+		__u64 llr_state                  :  3;
+		__u64: 1;
+		__u64 tx_seq                     : 20;
+		__u64 timestamp_frame_in_buffer  :  1;
+		__u64 timestamp_frame_ackd       :  1;
+		__u64: 6;
+		__u64 ack_state                  :  2;
+		__u64: 2;
+		__u64 ackd_seq                   : 20;
+		__u64: 8;
+	};
+};
+
+#define SS2_PORT_PML_STS_LLR_OFFSET(idx)	(0x00001500 + ((idx) * 8))
+#define SS2_PORT_PML_STS_LLR_ENTRIES	4
+#define SS2_PORT_PML_STS_LLR(idx)	(C_HNI_PML_BASE + SS2_PORT_PML_STS_LLR_OFFSET(idx))
+#define SS2_PORT_PML_STS_LLR_SIZE	0x00000020
+
+union ss2_port_pml_sts_llr {
+	__u64 qw;
+	struct {
+		__u64 llr_state                  :  3;
+		__u64: 1;
+		__u64 tx_seq                     : 20;
+		__u64 timestamp_frame_in_buffer  :  1;
+		__u64 timestamp_frame_ackd       :  1;
+		__u64: 6;
+		__u64 ack_state                  :  2;
+		__u64: 2;
+		__u64 ackd_seq                   : 20;
+		__u64: 8;
+	};
+};
+
+#define C1_HNI_PML_STS_LLR_LOOP_TIME_OFFSET	0x00000a08
+#define C1_HNI_PML_STS_LLR_LOOP_TIME	(C_HNI_PML_BASE + C1_HNI_PML_STS_LLR_LOOP_TIME_OFFSET)
+#define C1_HNI_PML_STS_LLR_LOOP_TIME_SIZE	0x00000008
+
+union c_hni_pml_sts_llr_loop_time {
+	__u64 qw;
+	struct {
+		__u64 loop_time  : 16;
+		__u64: 48;
+	};
+};
+
+#define SS2_PORT_PML_STS_LLR_LOOP_TIME_OFFSET(idx)	(0x00001520 + ((idx) * 8))
+#define SS2_PORT_PML_STS_LLR_LOOP_TIME_ENTRIES	4
+#define SS2_PORT_PML_STS_LLR_LOOP_TIME(idx)	(C_HNI_PML_BASE + SS2_PORT_PML_STS_LLR_LOOP_TIME_OFFSET(idx))
+#define SS2_PORT_PML_STS_LLR_LOOP_TIME_SIZE	0x00000020
+
+union ss2_port_pml_sts_llr_loop_time {
+	__u64 qw;
+	struct {
+		__u64 loop_time  : 16;
+		__u64: 48;
+	};
+};
+
+#define C1_HNI_PML_STS_LLR_USAGE_OFFSET	0x00000a18
+#define C1_HNI_PML_STS_LLR_USAGE	(C_HNI_PML_BASE + C1_HNI_PML_STS_LLR_USAGE_OFFSET)
+#define C1_HNI_PML_STS_LLR_USAGE_SIZE	0x00000008
+
+union c_hni_pml_sts_llr_usage {
+	__u64 qw;
+	struct {
+		__u64 buffer_space_used  : 12;
+		__u64: 4;
+		__u64 outstanding_seq    : 20;
+		__u64: 28;
+	};
+};
+
+#define SS2_PORT_PML_STS_LLR_USAGE_OFFSET(idx)	(0x00001560 + ((idx) * 8))
+#define SS2_PORT_PML_STS_LLR_USAGE_ENTRIES	4
+#define SS2_PORT_PML_STS_LLR_USAGE(idx)	(C_HNI_PML_BASE + SS2_PORT_PML_STS_LLR_USAGE_OFFSET(idx))
+#define SS2_PORT_PML_STS_LLR_USAGE_SIZE	0x00000020
+
+union ss2_port_pml_sts_llr_usage {
+	__u64 qw;
+	struct {
+		__u64 buffer_space_used  : 12;
+		__u64: 4;
+		__u64 outstanding_seq    : 20;
+		__u64: 28;
+	};
+};
+
+#define C1_HNI_PML_STS_LLR_MAX_USAGE_OFFSET	0x00000a20
+#define C1_HNI_PML_STS_LLR_MAX_USAGE	(C_HNI_PML_BASE + C1_HNI_PML_STS_LLR_MAX_USAGE_OFFSET)
+#define C1_HNI_PML_STS_LLR_MAX_USAGE_SIZE	0x00000008
+
+union c_hni_pml_sts_llr_max_usage {
+	__u64 qw;
+	struct {
+		__u64 max_buffer_space_used  : 12;
+		__u64 max_outstanding_seq    : 20;
+		__u64 max_starvation_time    : 16;
+		__u64 seq_starved            :  1;
+		__u64 buffer_space_starved   :  1;
+		__u64: 14;
+	};
+};
+
+#define SS2_PORT_PML_STS_LLR_MAX_USAGE_OFFSET(idx)	(0x00001580 + ((idx) * 8))
+#define SS2_PORT_PML_STS_LLR_MAX_USAGE_ENTRIES	4
+#define SS2_PORT_PML_STS_LLR_MAX_USAGE(idx)	(C_HNI_PML_BASE + SS2_PORT_PML_STS_LLR_MAX_USAGE_OFFSET(idx))
+#define SS2_PORT_PML_STS_LLR_MAX_USAGE_SIZE	0x00000020
+
+union ss2_port_pml_sts_llr_max_usage {
+	__u64 qw;
+	struct {
+		__u64 max_buffer_space_used  : 12;
+		__u64 max_outstanding_seq    : 20;
+		__u64 max_starvation_time    : 16;
+		__u64 seq_starved            :  1;
+		__u64 buffer_space_starved   :  1;
+		__u64: 14;
+	};
+};
+
+#define C1_HNI_PML_DBG_PCS_OFFSET	0x00000c10
+#define C1_HNI_PML_DBG_PCS	(C_HNI_PML_BASE + C1_HNI_PML_DBG_PCS_OFFSET)
+#define C1_HNI_PML_DBG_PCS_SIZE	0x00000008
+
+union c1_hni_pml_dbg_pcs {
+	__u64 qw;
+	struct {
+		__u64 tx_scrambler_en         :  1;
+		__u64 rx_descrambler_en       :  1;
+		__u64: 6;
+		__u64 enable_rapid_alignment  :  1;
+		__u64: 7;
+		__u64 force_bad_bip           :  5;
+		__u64: 3;
+		__u64 enable_idle_check       :  1;
+		__u64: 7;
+		__u64 force_tx_data           :  1;
+		__u64 force_tx_data_rf        :  1;
+		__u64: 6;
+		__u64 ppm_test_mode           :  1;
+		__u64: 23;
+	};
+};
+
+#define SS2_PORT_PML_DBG_PCS_OFFSET(idx)	(0x00001740 + ((idx) * 8))
+#define SS2_PORT_PML_DBG_PCS_ENTRIES	4
+#define SS2_PORT_PML_DBG_PCS(idx)	(C_HNI_PML_BASE + SS2_PORT_PML_DBG_PCS_OFFSET(idx))
+#define SS2_PORT_PML_DBG_PCS_SIZE	0x00000020
+
+union ss2_port_pml_dbg_pcs {
+	__u64 qw;
+	struct {
+		__u64 tx_scrambler_en         :  1;
+		__u64 rx_descrambler_en       :  1;
+		__u64: 6;
+		__u64 enable_rapid_alignment  :  1;
+		__u64: 7;
+		__u64 force_bad_bip           :  5;
+		__u64: 3;
+		__u64 enable_idle_check       :  1;
+		__u64: 7;
+		__u64 force_tx_data           :  1;
+		__u64 force_tx_data_rf        :  1;
+		__u64: 6;
+		__u64 ppm_test_mode           :  1;
+		__u64 tx_clk_select           :  2;
+		__u64: 21;
+	};
+};
+
+#define C_IXE_CFG_CRNC_OFFSET	0x00000000
+#define C_IXE_CFG_CRNC	(C_IXE_BASE + C_IXE_CFG_CRNC_OFFSET)
+#define C_IXE_CFG_CRNC_SIZE	0x00000008
+
+union c_ixe_cfg_crnc {
+	__u64 qw;
+	struct {
+		__u64 csr_timeout   :  8;
+		__u64 mcast_id      : 10;
+		__u64: 1;
+		__u64 mcast_enable  :  1;
+		__u64 mcast_mask    : 10;
+		__u64: 34;
+	};
+};
+
+#define C_IXE_MSC_SHADOW_ACTION_OFFSET	0x00000038
+#define C_IXE_MSC_SHADOW_ACTION	(C_IXE_BASE + C_IXE_MSC_SHADOW_ACTION_OFFSET)
+#define C_IXE_MSC_SHADOW_ACTION_SIZE	0x00000008
+#define C_IXE_MSC_SHADOW_OFFSET	0x00000080
+#define C_IXE_MSC_SHADOW	(C_IXE_BASE + C_IXE_MSC_SHADOW_OFFSET)
+#define C_IXE_MSC_SHADOW_SIZE	0x00000048
+
+union c_ixe_msc_shadow {
+	__u64 qw[9];
+};
+
+#define C_IXE_ERR_ELAPSED_TIME_OFFSET	0x00000100
+#define C_IXE_ERR_ELAPSED_TIME	(C_IXE_BASE + C_IXE_ERR_ELAPSED_TIME_OFFSET)
+#define C_IXE_ERR_ELAPSED_TIME_SIZE	0x00000008
+
+union c_ixe_err_elapsed_time {
+	__u64 qw;
+	struct {
+		__u64 nanoseconds  : 30;
+		__u64 seconds      : 34;
+	};
+};
+
+#define C_IXE_ERR_FLG_OFFSET	0x00000108
+#define C_IXE_ERR_FLG	(C_IXE_BASE + C_IXE_ERR_FLG_OFFSET)
+#define C_IXE_ERR_FLG_SIZE	0x00000008
+
+union c_ixe_err_flg {
+	__u64 qw;
+	struct {
+		__u64 sw_diag                  :  1;
+		__u64 crnc_ring_sync_error     :  1;
+		__u64 crnc_ring_ecc_sbe        :  1;
+		__u64 crnc_ring_ecc_mbe        :  1;
+		__u64 crnc_ring_cmd_unknown    :  1;
+		__u64 crnc_csr_cmd_unknown     :  1;
+		__u64 crnc_csr_cmd_incomplete  :  1;
+		__u64 crnc_buf_ecc_sbe         :  1;
+		__u64 crnc_buf_ecc_mbe         :  1;
+		__u64: 23;
+		__u64 pafa_perr                :  1;
+		__u64 fifo_err                 :  1;
+		__u64 credit_uflw              :  1;
+		__u64 pcie_unsuccess_cmpl      :  1;
+		__u64 pcie_error_poisoned      :  1;
+		__u64 port_dfa_mismatch        :  1;
+		__u64 port_discard_trig        :  1;
+		__u64 hdr_checksum_err         :  1;
+		__u64 hdr_ecc_err              :  1;
+		__u64 get_len_err              :  1;
+		__u64 ipv4_checksum_err        :  1;
+		__u64 ipv4_options_err         :  1;
+		__u64 ipv6_options_err         :  1;
+		__u64 hrp_req_err              :  1;
+		__u64 parser_disable           :  1;
+		__u64 pbuf_pkt_perr            :  1;
+		__u64 pbuf_rd_err              :  1;
+		__u64 pkt_flit_fifo_perr       :  1;
+		__u64 amo_align_err            :  1;
+		__u64 amo_op_err               :  1;
+		__u64 amo_fp_inexact           :  1;
+		__u64 amo_fp_overflow          :  1;
+		__u64 amo_fp_underflow         :  1;
+		__u64 amo_fp_invalid           :  1;
+		__u64 rarb_hw_err              :  1;
+		__u64 amo_length_err           :  1;
+		__u64 pbuf_overflow            :  1;
+		__u64: 5;
+	};
+};
+
+#define C_IXE_ERR_FIRST_FLG_OFFSET	0x00000110
+#define C_IXE_ERR_FIRST_FLG	(C_IXE_BASE + C_IXE_ERR_FIRST_FLG_OFFSET)
+#define C_IXE_ERR_FIRST_FLG_SIZE	0x00000008
+#define C_IXE_ERR_FIRST_FLG_TS_OFFSET	0x00000118
+#define C_IXE_ERR_FIRST_FLG_TS	(C_IXE_BASE + C_IXE_ERR_FIRST_FLG_TS_OFFSET)
+#define C_IXE_ERR_FIRST_FLG_TS_SIZE	0x00000008
+#define C_IXE_ERR_CLR_OFFSET	0x00000120
+#define C_IXE_ERR_CLR	(C_IXE_BASE + C_IXE_ERR_CLR_OFFSET)
+#define C_IXE_ERR_CLR_SIZE	0x00000008
+#define C_IXE_ERR_IRQA_MSK_OFFSET	0x00000128
+#define C_IXE_ERR_IRQA_MSK	(C_IXE_BASE + C_IXE_ERR_IRQA_MSK_OFFSET)
+#define C_IXE_ERR_IRQA_MSK_SIZE	0x00000008
+#define C_IXE_ERR_IRQB_MSK_OFFSET	0x00000130
+#define C_IXE_ERR_IRQB_MSK	(C_IXE_BASE + C_IXE_ERR_IRQB_MSK_OFFSET)
+#define C_IXE_ERR_IRQB_MSK_SIZE	0x00000008
+#define C_IXE_ERR_INFO_MSK_OFFSET	0x00000140
+#define C_IXE_ERR_INFO_MSK	(C_IXE_BASE + C_IXE_ERR_INFO_MSK_OFFSET)
+#define C_IXE_ERR_INFO_MSK_SIZE	0x00000008
+#define C_IXE_EXT_ERR_FLG_OFFSET	0x00000148
+#define C_IXE_EXT_ERR_FLG	(C_IXE_BASE + C_IXE_EXT_ERR_FLG_OFFSET)
+#define C_IXE_EXT_ERR_FLG_SIZE	0x00000008
+
+union c_ixe_ext_err_flg {
+	__u64 qw;
+	struct {
+		__u64 sw_diag             :  1;
+		__u64 flop_fifo_cor       :  1;
+		__u64 put_resp_mem_cor    :  1;
+		__u64 get_req_mem_cor     :  1;
+		__u64 rdfq_list_mem_cor   :  1;
+		__u64 wr_md_mem_cor       :  1;
+		__u64 event_fifo_cor      :  1;
+		__u64 wr_ev_mem_cor       :  1;
+		__u64 pkt_flit_fifo_cor   :  1;
+		__u64 pbuf_list_mem_cor   :  1;
+		__u64 pbuf_sb_mem_cor     :  1;
+		__u64 atu_resp_cor        :  1;
+		__u64 rdoq_cor            :  1;
+		__u64 ingressq_cor        :  1;
+		__u64 info_cor            :  1;
+		__u64 cmd_info_cor        :  1;
+		__u64 sideband_cor        :  1;
+		__u64 p_cmd_cor           :  1;
+		__u64 np_cmd_cor          :  1;
+		__u64 amo_info_cor        :  1;
+		__u64 addr_cor            :  1;
+		__u64 rd_buf_cor          :  1;
+		__u64 ack_rd_buf_cor      :  1;
+		__u64 hni_flit_cor        :  1;
+		__u64 rpu_list_mem_cor    :  1;
+		__u64 rpu_st_mem_cor      :  1;
+		__u64 rarb_hdr_bus_cor    :  1;
+		__u64 rarb_data_bus_cor   :  1;
+		__u64 pbuf_flit_mem_cor   :  1;
+		__u64: 3;
+		__u64: 1;
+		__u64 flop_fifo_ucor      :  1;
+		__u64 put_resp_mem_ucor   :  1;
+		__u64 get_req_mem_ucor    :  1;
+		__u64 rdfq_list_mem_ucor  :  1;
+		__u64 wr_md_mem_ucor      :  1;
+		__u64 event_fifo_ucor     :  1;
+		__u64 wr_ev_mem_ucor      :  1;
+		__u64 pkt_flit_fifo_ucor  :  1;
+		__u64 pbuf_list_mem_ucor  :  1;
+		__u64 pbuf_sb_mem_ucor    :  1;
+		__u64 atu_resp_ucor       :  1;
+		__u64 rdoq_ucor           :  1;
+		__u64 ingressq_ucor       :  1;
+		__u64 info_ucor           :  1;
+		__u64 cmd_info_ucor       :  1;
+		__u64 sideband_ucor       :  1;
+		__u64 p_cmd_ucor          :  1;
+		__u64 np_cmd_ucor         :  1;
+		__u64 amo_info_ucor       :  1;
+		__u64 addr_ucor           :  1;
+		__u64 rd_buf_ucor         :  1;
+		__u64 ack_rd_buf_ucor     :  1;
+		__u64 hni_flit_ucor       :  1;
+		__u64 rpu_list_mem_ucor   :  1;
+		__u64 rpu_st_mem_ucor     :  1;
+		__u64 rarb_hdr_bus_ucor   :  1;
+		__u64 rarb_data_bus_ucor  :  1;
+		__u64 pbuf_flit_mem_ucor  :  1;
+		__u64: 3;
+	};
+};
+
+#define C_IXE_EXT_ERR_FIRST_FLG_OFFSET	0x00000150
+#define C_IXE_EXT_ERR_FIRST_FLG	(C_IXE_BASE + C_IXE_EXT_ERR_FIRST_FLG_OFFSET)
+#define C_IXE_EXT_ERR_FIRST_FLG_SIZE	0x00000008
+#define C_IXE_EXT_ERR_FIRST_FLG_TS_OFFSET	0x00000158
+#define C_IXE_EXT_ERR_FIRST_FLG_TS	(C_IXE_BASE + C_IXE_EXT_ERR_FIRST_FLG_TS_OFFSET)
+#define C_IXE_EXT_ERR_FIRST_FLG_TS_SIZE	0x00000008
+#define C_IXE_EXT_ERR_CLR_OFFSET	0x00000160
+#define C_IXE_EXT_ERR_CLR	(C_IXE_BASE + C_IXE_EXT_ERR_CLR_OFFSET)
+#define C_IXE_EXT_ERR_CLR_SIZE	0x00000008
+#define C_IXE_EXT_ERR_IRQA_MSK_OFFSET	0x00000168
+#define C_IXE_EXT_ERR_IRQA_MSK	(C_IXE_BASE + C_IXE_EXT_ERR_IRQA_MSK_OFFSET)
+#define C_IXE_EXT_ERR_IRQA_MSK_SIZE	0x00000008
+#define C_IXE_EXT_ERR_IRQB_MSK_OFFSET	0x00000170
+#define C_IXE_EXT_ERR_IRQB_MSK	(C_IXE_BASE + C_IXE_EXT_ERR_IRQB_MSK_OFFSET)
+#define C_IXE_EXT_ERR_IRQB_MSK_SIZE	0x00000008
+#define C_IXE_EXT_ERR_INFO_MSK_OFFSET	0x00000180
+#define C_IXE_EXT_ERR_INFO_MSK	(C_IXE_BASE + C_IXE_EXT_ERR_INFO_MSK_OFFSET)
+#define C_IXE_EXT_ERR_INFO_MSK_SIZE	0x00000008
+#define C_IXE_ERR_INFO_MEM_OFFSET	0x00000190
+#define C_IXE_ERR_INFO_MEM	(C_IXE_BASE + C_IXE_ERR_INFO_MEM_OFFSET)
+#define C_IXE_ERR_INFO_MEM_SIZE	0x00000008
+
+union c_ixe_err_info_mem {
+	__u64 qw;
+	struct {
+		__u64 cor_syndrome       : 11;
+		__u64: 1;
+		__u64 cor_address        : 11;
+		__u64: 1;
+		__u64 cor_mem_id         :  6;
+		__u64: 1;
+		__u64 cor_csr_detected   :  1;
+		__u64 ucor_syndrome      : 11;
+		__u64: 1;
+		__u64 ucor_address       : 11;
+		__u64: 1;
+		__u64 ucor_mem_id        :  6;
+		__u64: 1;
+		__u64 ucor_csr_detected  :  1;
+	};
+};
+
+#define C_IXE_ERR_INFO_FIFO_ERR_OFFSET	0x00000198
+#define C_IXE_ERR_INFO_FIFO_ERR	(C_IXE_BASE + C_IXE_ERR_INFO_FIFO_ERR_OFFSET)
+#define C_IXE_ERR_INFO_FIFO_ERR_SIZE	0x00000008
+
+union c_ixe_err_info_fifo_err {
+	__u64 qw;
+	struct {
+		__u64 overrun   :  1;
+		__u64 underrun  :  1;
+		__u64: 6;
+		__u64 fifo_id   :  5;
+		__u64: 51;
+	};
+};
+
+#define C_IXE_ERR_INFO_CC_OFFSET	0x000001a0
+#define C_IXE_ERR_INFO_CC	(C_IXE_BASE + C_IXE_ERR_INFO_CC_OFFSET)
+#define C_IXE_ERR_INFO_CC_SIZE	0x00000008
+
+union c_ixe_err_info_cc {
+	__u64 qw;
+	struct {
+		__u64 cc_id   :  4;
+		__u64: 4;
+		__u64 sub_id  :  5;
+		__u64: 51;
+	};
+};
+
+#define C_IXE_ERR_INFO_PCIE_EP_OFFSET	0x00000200
+#define C_IXE_ERR_INFO_PCIE_EP	(C_IXE_BASE + C_IXE_ERR_INFO_PCIE_EP_OFFSET)
+#define C_IXE_ERR_INFO_PCIE_EP_SIZE	0x00000008
+
+union c_ixe_err_info_pcie_ep {
+	__u64 qw;
+	struct {
+		__u64 pcie_tag  :  9;
+		__u64: 55;
+	};
+};
+
+#define C_IXE_ERR_INFO_PCIE_UC_OFFSET	0x00000208
+#define C_IXE_ERR_INFO_PCIE_UC	(C_IXE_BASE + C_IXE_ERR_INFO_PCIE_UC_OFFSET)
+#define C_IXE_ERR_INFO_PCIE_UC_SIZE	0x00000008
+
+union c_ixe_err_info_pcie_uc {
+	__u64 qw;
+	struct {
+		__u64 pcie_tag     :  9;
+		__u64: 3;
+		__u64 cmpl_status  :  3;
+		__u64: 49;
+	};
+};
+
+#define C_IXE_ERR_INFO_ETH_PARSE_OFFSET	0x00000210
+#define C_IXE_ERR_INFO_ETH_PARSE	(C_IXE_BASE + C_IXE_ERR_INFO_ETH_PARSE_OFFSET)
+#define C_IXE_ERR_INFO_ETH_PARSE_SIZE	0x00000008
+
+union c_ixe_err_info_eth_parse {
+	__u64 qw;
+	struct {
+		__u64 ptlte_index        : 11;
+		__u64: 1;
+		__u64 ipv4_checksum_err  :  1;
+		__u64 ipv4_options_err   :  1;
+		__u64 ipv6_options_err   :  1;
+		__u64: 49;
+	};
+};
+
+#define C_IXE_ERR_INFO_RARB_OFFSET	0x00000218
+#define C_IXE_ERR_INFO_RARB	(C_IXE_BASE + C_IXE_ERR_INFO_RARB_OFFSET)
+#define C_IXE_ERR_INFO_RARB_SIZE	0x00000008
+
+union c_ixe_err_info_rarb {
+	__u64 qw;
+	struct {
+		__u64 hdr_ucor               :  1;
+		__u64 data_ucor              :  1;
+		__u64 bad_cmpl_last          :  1;
+		__u64 bad_vld                :  1;
+		__u64 bad_eop                :  1;
+		__u64 bad_cmd                :  1;
+		__u64 unexpected_cmpl_tag    :  1;
+		__u64 cmpl_tag_out_of_range  :  1;
+		__u64: 56;
+	};
+};
+
+#define C_IXE_ERR_INFO_FP_INVALID_OFFSET	0x00000220
+#define C_IXE_ERR_INFO_FP_INVALID	(C_IXE_BASE + C_IXE_ERR_INFO_FP_INVALID_OFFSET)
+#define C_IXE_ERR_INFO_FP_INVALID_SIZE	0x00000010
+
+union c_ixe_err_info_fp_invalid {
+	__u64 qw[2];
+	struct {
+		__u64: 2;
+		__u64 addr_56_2    : 55;
+		__u64: 7;
+		__u64 acid         : 10;
+		__u64: 2;
+		__u64 atomic_type  :  4;
+		__u64: 48;
+	};
+};
+
+#define C_IXE_ERR_INFO_FP_UNDERFLOW_OFFSET	0x00000230
+#define C_IXE_ERR_INFO_FP_UNDERFLOW	(C_IXE_BASE + C_IXE_ERR_INFO_FP_UNDERFLOW_OFFSET)
+#define C_IXE_ERR_INFO_FP_UNDERFLOW_SIZE	0x00000010
+
+union c_ixe_err_info_fp_underflow {
+	__u64 qw[2];
+	struct {
+		__u64: 2;
+		__u64 addr_56_2    : 55;
+		__u64: 7;
+		__u64 acid         : 10;
+		__u64: 2;
+		__u64 atomic_type  :  4;
+		__u64: 48;
+	};
+};
+
+#define C_IXE_ERR_INFO_FP_OVERFLOW_OFFSET	0x00000240
+#define C_IXE_ERR_INFO_FP_OVERFLOW	(C_IXE_BASE + C_IXE_ERR_INFO_FP_OVERFLOW_OFFSET)
+#define C_IXE_ERR_INFO_FP_OVERFLOW_SIZE	0x00000010
+
+union c_ixe_err_info_fp_overflow {
+	__u64 qw[2];
+	struct {
+		__u64: 2;
+		__u64 addr_56_2    : 55;
+		__u64: 7;
+		__u64 acid         : 10;
+		__u64: 2;
+		__u64 atomic_type  :  4;
+		__u64: 48;
+	};
+};
+
+#define C_IXE_ERR_INFO_FP_INEXACT_OFFSET	0x00000250
+#define C_IXE_ERR_INFO_FP_INEXACT	(C_IXE_BASE + C_IXE_ERR_INFO_FP_INEXACT_OFFSET)
+#define C_IXE_ERR_INFO_FP_INEXACT_SIZE	0x00000010
+
+union c_ixe_err_info_fp_inexact {
+	__u64 qw[2];
+	struct {
+		__u64: 2;
+		__u64 addr_56_2    : 55;
+		__u64: 7;
+		__u64 acid         : 10;
+		__u64: 2;
+		__u64 atomic_type  :  4;
+		__u64: 48;
+	};
+};
+
+#define C_IXE_ERR_INFO_AMO_ALIGN_OFFSET	0x00000260
+#define C_IXE_ERR_INFO_AMO_ALIGN	(C_IXE_BASE + C_IXE_ERR_INFO_AMO_ALIGN_OFFSET)
+#define C_IXE_ERR_INFO_AMO_ALIGN_SIZE	0x00000010
+
+union c_ixe_err_info_amo_align {
+	__u64 qw[2];
+	struct {
+		__u64 addr_56_0    : 57;
+		__u64: 7;
+		__u64 acid         : 10;
+		__u64: 2;
+		__u64 atomic_type  :  4;
+		__u64: 48;
+	};
+};
+
+#define C_IXE_ERR_INFO_AMO_OP_OFFSET	0x00000270
+#define C_IXE_ERR_INFO_AMO_OP	(C_IXE_BASE + C_IXE_ERR_INFO_AMO_OP_OFFSET)
+#define C_IXE_ERR_INFO_AMO_OP_SIZE	0x00000010
+
+union c_ixe_err_info_amo_op {
+	__u64 qw[2];
+	struct {
+		__u64 addr_56_0    : 57;
+		__u64: 7;
+		__u64 acid         : 10;
+		__u64: 2;
+		__u64 atomic_type  :  4;
+		__u64 cswap_op     :  3;
+		__u64: 1;
+		__u64 atomic_op    :  4;
+		__u64: 40;
+	};
+};
+
+#define C_IXE_ERR_INFO_AMO_LENGTH_OFFSET	0x00000280
+#define C_IXE_ERR_INFO_AMO_LENGTH	(C_IXE_BASE + C_IXE_ERR_INFO_AMO_LENGTH_OFFSET)
+#define C_IXE_ERR_INFO_AMO_LENGTH_SIZE	0x00000010
+
+union c_ixe_err_info_amo_length {
+	__u64 qw[2];
+	struct {
+		__u64 addr_56_0    : 57;
+		__u64: 7;
+		__u64 acid         : 10;
+		__u64: 2;
+		__u64 atomic_type  :  4;
+		__u64 cmd_length   : 13;
+		__u64: 35;
+	};
+};
+
+#define C_IXE_CFG_DSCP_WRQ_MAP_OFFSET(idx)	(0x00000400 + ((idx) * 8))
+#define C_IXE_CFG_DSCP_WRQ_MAP_ENTRIES	64
+#define C_IXE_CFG_DSCP_WRQ_MAP(idx)	(C_IXE_BASE + C_IXE_CFG_DSCP_WRQ_MAP_OFFSET(idx))
+#define C_IXE_CFG_DSCP_WRQ_MAP_SIZE	0x00000200
+
+union c_ixe_cfg_dscp_wrq_map {
+	__u64 qw;
+	struct {
+		__u64 mask0      : 22;
+		__u64: 2;
+		__u64 mask1      : 22;
+		__u64: 2;
+		__u64 hash_mask  :  2;
+		__u64: 6;
+		__u64 base       :  5;
+		__u64: 3;
+	};
+};
+
+#define C_IXE_CFG_DSCP_DSCP_TC_MAP_OFFSET(idx)	(0x00000600 + ((idx) * 8))
+#define C_IXE_CFG_DSCP_DSCP_TC_MAP_ENTRIES	16
+#define C_IXE_CFG_DSCP_DSCP_TC_MAP(idx)	(C_IXE_BASE + C_IXE_CFG_DSCP_DSCP_TC_MAP_OFFSET(idx))
+#define C_IXE_CFG_DSCP_DSCP_TC_MAP_SIZE	0x00000080
+
+struct c_dscp_map {
+	__u8 dscp    : 6;
+	__u8: 2;
+	__u8 tc      : 3;
+	__u8: 5;
+};
+#define C_IXE_CFG_DSCP_DSCP_TC_MAP_ARRAY_SIZE 4
+union c_ixe_cfg_dscp_dscp_tc_map {
+	__u64 qw;
+	struct c_dscp_map map[C_IXE_CFG_DSCP_DSCP_TC_MAP_ARRAY_SIZE];
+};
+
+#define C_IXE_CFG_TC_FQ_MAP_OFFSET(idx)	(0x00000700 + ((idx) * 8))
+#define C_IXE_CFG_TC_FQ_MAP_ENTRIES	8
+#define C_IXE_CFG_TC_FQ_MAP(idx)	(C_IXE_BASE + C_IXE_CFG_TC_FQ_MAP_OFFSET(idx))
+#define C_IXE_CFG_TC_FQ_MAP_SIZE	0x00000040
+
+union c_ixe_cfg_tc_fq_map {
+	__u64 qw;
+	struct {
+		__u64 put_resp_mask  : 24;
+		__u64: 8;
+		__u64 get_req_mask   : 24;
+		__u64: 8;
+	};
+};
+
+#define C_IXE_CFG_MP_TC_FQ_MAP_OFFSET(idx)	(0x00000740 + ((idx) * 8))
+#define C_IXE_CFG_MP_TC_FQ_MAP_ENTRIES	8
+#define C_IXE_CFG_MP_TC_FQ_MAP(idx)	(C_IXE_BASE + C_IXE_CFG_MP_TC_FQ_MAP_OFFSET(idx))
+#define C_IXE_CFG_MP_TC_FQ_MAP_SIZE	0x00000040
+
+union c_ixe_cfg_mp_tc_fq_map {
+	__u64 qw;
+	struct {
+		__u64 num_fqs_mask  :  2;
+		__u64: 14;
+		__u64 base          :  5;
+		__u64: 43;
+	};
+};
+
+#define C_IXE_CFG_DISP_CDT_LIM_OFFSET	0x00000788
+#define C_IXE_CFG_DISP_CDT_LIM	(C_IXE_BASE + C_IXE_CFG_DISP_CDT_LIM_OFFSET)
+#define C_IXE_CFG_DISP_CDT_LIM_SIZE	0x00000008
+
+union c_ixe_cfg_disp_cdt_lim {
+	__u64 qw;
+	struct {
+		__u64 mst_match_cdts  :  6;
+		__u64: 2;
+		__u64 wrq_ff_cdts     :  2;
+		__u64: 2;
+		__u64 atu_req_cdts    :  3;
+		__u64: 1;
+		__u64 rpu_err_cdts    :  3;
+		__u64: 1;
+		__u64 rpu_resp_cdts   :  3;
+		__u64: 1;
+		__u64 pct_gcomp_cdts  :  6;
+		__u64: 2;
+		__u64 put_resp_cdts   : 10;
+		__u64: 6;
+		__u64 put_atu_cdts    :  9;
+		__u64 ee_cdts         :  5;
+		__u64: 2;
+	};
+};
+
+#define C_IXE_CFG_AMO_OFFLOAD_EN_OFFSET	0x00000800
+#define C_IXE_CFG_AMO_OFFLOAD_EN	(C_IXE_BASE + C_IXE_CFG_AMO_OFFLOAD_EN_OFFSET)
+#define C_IXE_CFG_AMO_OFFLOAD_EN_SIZE	0x00000008
+
+union c_ixe_cfg_amo_offload_en {
+	__u64 qw;
+	struct {
+		__u64 op_min       :  4;
+		__u64 op_max       :  4;
+		__u64 op_sum       :  4;
+		__u64 op_lor       :  4;
+		__u64 op_land      :  4;
+		__u64 op_bor       :  4;
+		__u64 op_band      :  4;
+		__u64 op_lxor      :  4;
+		__u64 op_bxor      :  4;
+		__u64 op_swap      :  4;
+		__u64 op_cswap_eq  :  3;
+		__u64: 1;
+		__u64 op_cswap_ne  :  2;
+		__u64 op_cswap_le  :  2;
+		__u64 op_cswap_lt  :  2;
+		__u64 op_cswap_ge  :  2;
+		__u64 op_cswap_gt  :  2;
+		__u64 op_axor      :  2;
+		__u64: 8;
+	};
+};
+
+#define C_IXE_CFG_AMO_OFFLOAD_CODE_1OP_OFFSET	0x00000808
+#define C_IXE_CFG_AMO_OFFLOAD_CODE_1OP	(C_IXE_BASE + C_IXE_CFG_AMO_OFFLOAD_CODE_1OP_OFFSET)
+#define C_IXE_CFG_AMO_OFFLOAD_CODE_1OP_SIZE	0x00000008
+
+union c_ixe_cfg_amo_offload_code_1op {
+	__u64 qw;
+	struct {
+		__u64 op_min_code   :  4;
+		__u64 op_max_code   :  4;
+		__u64 op_sum_code   :  4;
+		__u64 op_lor_code   :  4;
+		__u64 op_land_code  :  4;
+		__u64 op_bor_code   :  4;
+		__u64 op_band_code  :  4;
+		__u64 op_lxor_code  :  4;
+		__u64 op_bxor_code  :  4;
+		__u64 op_swap_code  :  4;
+		__u64: 24;
+	};
+};
+
+#define C_IXE_CFG_AMO_OFFLOAD_OFFSET	0x00000818
+#define C_IXE_CFG_AMO_OFFLOAD	(C_IXE_BASE + C_IXE_CFG_AMO_OFFLOAD_OFFSET)
+#define C_IXE_CFG_AMO_OFFLOAD_SIZE	0x00000008
+
+union c_ixe_cfg_amo_offload {
+	__u64 qw;
+	struct {
+		__u64 base_amo_req           :  1;
+		__u64 force_native_swap      :  1;
+		__u64 force_native_fetchadd  :  1;
+		__u64: 13;
+		__u64 first_dw_be_32bit      :  4;
+		__u64 last_dw_be_32bit       :  4;
+		__u64 first_dw_be_64bit      :  4;
+		__u64 last_dw_be_64bit       :  4;
+		__u64: 32;
+	};
+};
+
+#define C_IXE_CFG_PARSER_OFFSET	0x00000908
+#define C_IXE_CFG_PARSER	(C_IXE_BASE + C_IXE_CFG_PARSER_OFFSET)
+#define C_IXE_CFG_PARSER_SIZE	0x00000008
+
+union c_ixe_cfg_parser {
+	__u64 qw;
+	struct {
+		__u64 ipv4_flowlab_type  :  8;
+		__u64 ipv6_frag_type     :  8;
+		__u64 udp_type           :  8;
+		__u64 tcp_type           :  8;
+		__u64 eth_segment        :  5;
+		__u64: 3;
+		__u64 rpu_wrdisp_cdt     :  4;
+		__u64: 20;
+	};
+};
+
+#define C_IXE_CFG_ROCE_OFFSET	0x00000910
+#define C_IXE_CFG_ROCE	(C_IXE_BASE + C_IXE_CFG_ROCE_OFFSET)
+#define C_IXE_CFG_ROCE_SIZE	0x00000008
+
+union c_ixe_cfg_roce {
+	__u64 qw;
+	struct {
+		__u64 udp_dstport_bth  : 16;
+		__u64 enable_1k        :  1;
+		__u64 enable_2k        :  1;
+		__u64 enable_4k        :  1;
+		__u64: 45;
+	};
+};
+
+#define C_IXE_CFG_HRP_OFFSET	0x00000918
+#define C_IXE_CFG_HRP	(C_IXE_BASE + C_IXE_CFG_HRP_OFFSET)
+#define C_IXE_CFG_HRP_SIZE	0x00000008
+
+union c_ixe_cfg_hrp {
+	__u64 qw;
+	struct {
+		__u64 hrp_enable;
+	};
+};
+
+#define C_IXE_CFG_DFA_OFFSET	0x00000920
+#define C_IXE_CFG_DFA	(C_IXE_BASE + C_IXE_CFG_DFA_OFFSET)
+#define C_IXE_CFG_DFA_SIZE	0x00000008
+
+union c_ixe_cfg_dfa {
+	__u64 qw;
+	struct {
+		__u64: 12;
+		__u64 dfa_nid     : 20;
+		__u64 dfa_chk_en  :  8;
+		__u64: 24;
+	};
+};
+
+#define C_IXE_CFG_DISCARD_OFFSET	0x00000928
+#define C_IXE_CFG_DISCARD	(C_IXE_BASE + C_IXE_CFG_DISCARD_OFFSET)
+#define C_IXE_CFG_DISCARD_SIZE	0x00000008
+
+union c_ixe_cfg_discard {
+	__u64 qw;
+	struct {
+		__u64 v4_pkt_type_mask   :  8;
+		__u64 v4_pkt_type_match  :  8;
+		__u64 vs_pkt_type_mask   :  8;
+		__u64 vs_pkt_type_match  :  8;
+		__u64 armed              :  8;
+		__u64: 24;
+	};
+};
+
+#define C_IXE_CFG_IPV6_OPT_ABORT_OFFSET(idx)	(0x00000960 + ((idx) * 8))
+#define C_IXE_CFG_IPV6_OPT_ABORT_ENTRIES	4
+#define C_IXE_CFG_IPV6_OPT_ABORT(idx)	(C_IXE_BASE + C_IXE_CFG_IPV6_OPT_ABORT_OFFSET(idx))
+#define C_IXE_CFG_IPV6_OPT_ABORT_SIZE	0x00000020
+
+union c_ixe_cfg_ipv6_opt_abort {
+	__u64 qw;
+	struct {
+		__u64 abort;
+	};
+};
+
+#define C_IXE_CFG_BTH_OPCODE_OFFSET(idx)	(0x00000980 + ((idx) * 8))
+#define C_IXE_CFG_BTH_OPCODE_ENTRIES	16
+#define C_IXE_CFG_BTH_OPCODE(idx)	(C_IXE_BASE + C_IXE_CFG_BTH_OPCODE_OFFSET(idx))
+#define C_IXE_CFG_BTH_OPCODE_SIZE	0x00000080
+
+union c_ixe_cfg_bth_opcode {
+	__u64 qw;
+	struct {
+		__u64 len_0   :  4;
+		__u64 len_1   :  4;
+		__u64 len_2   :  4;
+		__u64 len_3   :  4;
+		__u64 len_4   :  4;
+		__u64 len_5   :  4;
+		__u64 len_6   :  4;
+		__u64 len_7   :  4;
+		__u64 len_8   :  4;
+		__u64 len_9   :  4;
+		__u64 len_10  :  4;
+		__u64 len_11  :  4;
+		__u64 len_12  :  4;
+		__u64 len_13  :  4;
+		__u64 len_14  :  4;
+		__u64 len_15  :  4;
+	};
+};
+
+#define C_IXE_STS_PARSER_DECODE_OFFSET	0x00000c40
+#define C_IXE_STS_PARSER_DECODE	(C_IXE_BASE + C_IXE_STS_PARSER_DECODE_OFFSET)
+#define C_IXE_STS_PARSER_DECODE_SIZE	0x00000008
+
+union c_ixe_sts_parser_decode {
+	__u64 qw;
+	struct {
+		__u64 flit_fifo_depth     :  6;
+		__u64: 2;
+		__u64 pkt_fifo_depth      :  6;
+		__u64: 2;
+		__u64 pct_req_fifo_depth  :  6;
+		__u64: 2;
+		__u64 pct_rsp_fifo_depth  :  6;
+		__u64: 2;
+		__u64 rmu_fifo_depth      :  6;
+		__u64: 26;
+	};
+};
+
+#define C_LPE_CFG_CRNC_OFFSET	0x00000000
+#define C_LPE_CFG_CRNC	(C_LPE_BASE + C_LPE_CFG_CRNC_OFFSET)
+#define C_LPE_CFG_CRNC_SIZE	0x00000008
+
+union c_lpe_cfg_crnc {
+	__u64 qw;
+	struct {
+		__u64 csr_timeout   :  8;
+		__u64 mcast_id      : 10;
+		__u64: 1;
+		__u64 mcast_enable  :  1;
+		__u64 mcast_mask    : 10;
+		__u64: 34;
+	};
+};
+
+#define C_LPE_MSC_SHADOW_ACTION_OFFSET	0x00000038
+#define C_LPE_MSC_SHADOW_ACTION	(C_LPE_BASE + C_LPE_MSC_SHADOW_ACTION_OFFSET)
+#define C_LPE_MSC_SHADOW_ACTION_SIZE	0x00000008
+#define C_LPE_MSC_SHADOW_OFFSET	0x00000040
+#define C_LPE_MSC_SHADOW	(C_LPE_BASE + C_LPE_MSC_SHADOW_OFFSET)
+#define C_LPE_MSC_SHADOW_SIZE	0x00000040
+
+union c_lpe_msc_shadow {
+	__u64 qw[8];
+};
+
+#define C_LPE_ERR_ELAPSED_TIME_OFFSET	0x00000100
+#define C_LPE_ERR_ELAPSED_TIME	(C_LPE_BASE + C_LPE_ERR_ELAPSED_TIME_OFFSET)
+#define C_LPE_ERR_ELAPSED_TIME_SIZE	0x00000008
+
+union c_lpe_err_elapsed_time {
+	__u64 qw;
+	struct {
+		__u64 nanoseconds  : 30;
+		__u64 seconds      : 34;
+	};
+};
+
+#define C_LPE_ERR_FLG_OFFSET	0x00000108
+#define C_LPE_ERR_FLG	(C_LPE_BASE + C_LPE_ERR_FLG_OFFSET)
+#define C_LPE_ERR_FLG_SIZE	0x00000008
+
+union c_lpe_err_flg {
+	__u64 qw;
+	struct {
+		__u64 sw_diag                  :  1;
+		__u64 crnc_ring_sync_error     :  1;
+		__u64 crnc_ring_ecc_sbe        :  1;
+		__u64 crnc_ring_ecc_mbe        :  1;
+		__u64 crnc_ring_cmd_unknown    :  1;
+		__u64 crnc_csr_cmd_unknown     :  1;
+		__u64 crnc_csr_cmd_incomplete  :  1;
+		__u64 crnc_buf_ecc_sbe         :  1;
+		__u64 crnc_buf_ecc_mbe         :  1;
+		__u64 event_cnt_ovf            :  1;
+		__u64 le_oversubscribed        :  1;
+		__u64: 1;
+		__u64 illegal_op               :  1;
+		__u64 src_error                :  1;
+		__u64 delayed                  :  1;
+		__u64 restricted_unicast       :  1;
+		__u64 no_space                 :  1;
+		__u64 invalid_endpoint         :  1;
+		__u64 entry_not_found          :  1;
+		__u64 op_violation             :  1;
+		__u64 eq_disabled              :  1;
+		__u64 pt_disabled_fc           :  1;
+		__u64 pt_disabled_dis          :  1;
+		__u64 pt_disabled_rst          :  1;
+		__u64 illegal_cq_op            :  1;
+		__u64 fifo_err                 :  1;
+		__u64 cq_fifo_overrun          :  1;
+		__u64 cdt_cnt_uflow            :  1;
+		__u64 mrr_mem_cor              :  1;
+		__u64 free_list_mem_cor        :  1;
+		__u64 event_ram_cor            :  1;
+		__u64 plec_mem_cor             :  1;
+		__u64 ptlte_mem_cor            :  1;
+		__u64 ixemrq_front_mem_cor     :  1;
+		__u64 ixemrq_back_mem_cor      :  1;
+		__u64 ixemrq_list_mem_cor      :  1;
+		__u64 petcq_list_mem_cor       :  1;
+		__u64 list_entry_mem_cor       :  1;
+		__u64 cqmrq_front_mem_cor      :  1;
+		__u64 cqmrq_back_mem_cor       :  1;
+		__u64 cqmrq_list_mem_cor       :  1;
+		__u64 rget_ram_mem_cor         :  1;
+		__u64 rrq_fifo_cor             :  1;
+		__u64 cq_fifo_cor              :  1;
+		__u64: 1;
+		__u64 rdy_pleq_cor             :  1;
+		__u64 mrr_mem_ucor             :  1;
+		__u64 free_list_mem_ucor       :  1;
+		__u64 event_ram_ucor           :  1;
+		__u64 plec_mem_ucor            :  1;
+		__u64 ptlte_mem_ucor           :  1;
+		__u64 ixemrq_front_mem_ucor    :  1;
+		__u64 ixemrq_back_mem_ucor     :  1;
+		__u64 ixemrq_list_mem_ucor     :  1;
+		__u64 petcq_list_mem_ucor      :  1;
+		__u64 list_entry_mem_ucor      :  1;
+		__u64 cqmrq_front_mem_ucor     :  1;
+		__u64 cqmrq_back_mem_ucor      :  1;
+		__u64 cqmrq_list_mem_ucor      :  1;
+		__u64 rget_ram_mem_ucor        :  1;
+		__u64 rrq_fifo_ucor            :  1;
+		__u64 cq_fifo_ucor             :  1;
+		__u64: 1;
+		__u64 rdy_pleq_ucor            :  1;
+	};
+};
+
+#define C_LPE_ERR_FIRST_FLG_OFFSET	0x00000110
+#define C_LPE_ERR_FIRST_FLG	(C_LPE_BASE + C_LPE_ERR_FIRST_FLG_OFFSET)
+#define C_LPE_ERR_FIRST_FLG_SIZE	0x00000008
+#define C_LPE_ERR_FIRST_FLG_TS_OFFSET	0x00000118
+#define C_LPE_ERR_FIRST_FLG_TS	(C_LPE_BASE + C_LPE_ERR_FIRST_FLG_TS_OFFSET)
+#define C_LPE_ERR_FIRST_FLG_TS_SIZE	0x00000008
+#define C_LPE_ERR_CLR_OFFSET	0x00000120
+#define C_LPE_ERR_CLR	(C_LPE_BASE + C_LPE_ERR_CLR_OFFSET)
+#define C_LPE_ERR_CLR_SIZE	0x00000008
+#define C_LPE_ERR_IRQA_MSK_OFFSET	0x00000128
+#define C_LPE_ERR_IRQA_MSK	(C_LPE_BASE + C_LPE_ERR_IRQA_MSK_OFFSET)
+#define C_LPE_ERR_IRQA_MSK_SIZE	0x00000008
+#define C_LPE_ERR_IRQB_MSK_OFFSET	0x00000130
+#define C_LPE_ERR_IRQB_MSK	(C_LPE_BASE + C_LPE_ERR_IRQB_MSK_OFFSET)
+#define C_LPE_ERR_IRQB_MSK_SIZE	0x00000008
+#define C_LPE_ERR_INFO_MSK_OFFSET	0x00000140
+#define C_LPE_ERR_INFO_MSK	(C_LPE_BASE + C_LPE_ERR_INFO_MSK_OFFSET)
+#define C_LPE_ERR_INFO_MSK_SIZE	0x00000008
+#define C_LPE_ERR_INFO_MEM_OFFSET	0x00000180
+#define C_LPE_ERR_INFO_MEM	(C_LPE_BASE + C_LPE_ERR_INFO_MEM_OFFSET)
+#define C_LPE_ERR_INFO_MEM_SIZE	0x00000008
+
+union c_lpe_err_info_mem {
+	__u64 qw;
+	struct {
+		__u64 cor_syndrome       : 11;
+		__u64 cor_address        : 14;
+		__u64 cor_mem_id         :  5;
+		__u64: 1;
+		__u64 cor_csr_detected   :  1;
+		__u64 ucor_syndrome      : 11;
+		__u64 ucor_address       : 14;
+		__u64 ucor_mem_id        :  5;
+		__u64: 1;
+		__u64 ucor_csr_detected  :  1;
+	};
+};
+
+#define C_LPE_ERR_INFO_CDT_CNT_UFLOW_OFFSET	0x00000188
+#define C_LPE_ERR_INFO_CDT_CNT_UFLOW	(C_LPE_BASE + C_LPE_ERR_INFO_CDT_CNT_UFLOW_OFFSET)
+#define C_LPE_ERR_INFO_CDT_CNT_UFLOW_SIZE	0x00000008
+
+union c_lpe_err_info_cdt_cnt_uflow {
+	__u64 qw;
+	struct {
+		__u64 cdt_cnt_id  :  4;
+		__u64: 60;
+	};
+};
+
+#define C_LPE_ERR_INFO_NET_HDR_OFFSET	0x00000190
+#define C_LPE_ERR_INFO_NET_HDR	(C_LPE_BASE + C_LPE_ERR_INFO_NET_HDR_OFFSET)
+#define C_LPE_ERR_INFO_NET_HDR_SIZE	0x00000008
+
+union c_lpe_err_info_net_hdr {
+	__u64 qw;
+	struct {
+		__u64 initiator       : 32;
+		__u64 ptlte_index     : 11;
+		__u64 src_error       :  1;
+		__u64 tc              :  3;
+		__u64: 1;
+		__u64 opcode          :  4;
+		__u64 net_hdr_err_id  :  4;
+		__u64: 8;
+	};
+};
+
+#define C_LPE_CFG_FQ_TC_MAP_OFFSET	0x00000410
+#define C_LPE_CFG_FQ_TC_MAP	(C_LPE_BASE + C_LPE_CFG_FQ_TC_MAP_OFFSET)
+#define C_LPE_CFG_FQ_TC_MAP_SIZE	0x00000008
+
+struct c_lpe_cfg_tc_fqs {
+	__u8 fq_base	: 4;
+	__u8 fq_mask	: 3;
+	__u8: 1;
+};
+union c_lpe_cfg_fq_tc_map {
+	__u64 qw;
+	struct c_lpe_cfg_tc_fqs tc[8];
+};
+
+#define C_LPE_CFG_CDT_LIMITS_OFFSET	0x00000418
+#define C_LPE_CFG_CDT_LIMITS	(C_LPE_BASE + C_LPE_CFG_CDT_LIMITS_OFFSET)
+#define C_LPE_CFG_CDT_LIMITS_SIZE	0x00000008
+
+union c_lpe_cfg_cdt_limits {
+	__u64 qw;
+	struct {
+		__u64 ixemrq_wc_cdts  :  4;
+		__u64 cqmrq_wc_cdts   :  4;
+		__u64 rdy_ple_cdts    :  4;
+		__u64 event_cdts      :  5;
+		__u64: 3;
+		__u64 ixe_put_cdts    :  4;
+		__u64 ixe_get_cdts    :  4;
+		__u64 ixe_mst_cdts    :  4;
+		__u64 rrq_cdts        :  3;
+		__u64: 29;
+	};
+};
+
+#define C_LPE_CFG_GET_CTRL_OFFSET	0x00000428
+#define C_LPE_CFG_GET_CTRL	(C_LPE_BASE + C_LPE_CFG_GET_CTRL_OFFSET)
+#define C_LPE_CFG_GET_CTRL_SIZE	0x00000008
+
+union c_lpe_cfg_get_ctrl {
+	__u64 qw;
+	struct {
+		__u64 get_index         : 12;
+		__u64: 4;
+		__u64 get_index_ext     :  5;
+		__u64 get_pid_shift     :  3;
+		__u64 transaction_type  :  4;
+		__u64: 3;
+		__u64 get_en            :  1;
+		__u64 dfa_nid           : 20;
+		__u64: 12;
+	};
+};
+
+#define C_LPE_CFG_INITIATOR_CTRL_OFFSET	0x00000430
+#define C_LPE_CFG_INITIATOR_CTRL	(C_LPE_BASE + C_LPE_CFG_INITIATOR_CTRL_OFFSET)
+#define C_LPE_CFG_INITIATOR_CTRL_SIZE	0x00000008
+
+union c_lpe_cfg_initiator_ctrl {
+	__u64 qw;
+	struct {
+		__u64 pid_bits  :  4;
+		__u64: 60;
+	};
+};
+
+#define C_LPE_CFG_ETHERNET_THRESHOLD_OFFSET	0x00000438
+#define C_LPE_CFG_ETHERNET_THRESHOLD	(C_LPE_BASE + C_LPE_CFG_ETHERNET_THRESHOLD_OFFSET)
+#define C_LPE_CFG_ETHERNET_THRESHOLD_SIZE	0x00000008
+
+union c_lpe_cfg_ethernet_threshold {
+	__u64 qw;
+	struct {
+		__u64 threshold  : 14;
+		__u64: 50;
+	};
+};
+
+#define C_LPE_CFG_MIN_FREE_SHFT_OFFSET	0x00000440
+#define C_LPE_CFG_MIN_FREE_SHFT	(C_LPE_BASE + C_LPE_CFG_MIN_FREE_SHFT_OFFSET)
+#define C_LPE_CFG_MIN_FREE_SHFT_SIZE	0x00000008
+
+union c_lpe_cfg_min_free_shft {
+	__u64 qw;
+	struct {
+		__u64 min_free_shft  :  4;
+		__u64: 60;
+	};
+};
+
+#define C_LPE_CFG_EVENT_CNTS_OFFSET	0x00000448
+#define C_LPE_CFG_EVENT_CNTS	(C_LPE_BASE + C_LPE_CFG_EVENT_CNTS_OFFSET)
+#define C_LPE_CFG_EVENT_CNTS_SIZE	0x00000008
+
+union c_lpe_cfg_event_cnts {
+	__u64 qw;
+	struct {
+		__u64 enable     :  1;
+		__u64 init       :  1;
+		__u64 init_done  :  1;
+		__u64: 1;
+		__u64 ovf_cnt    : 16;
+		__u64: 44;
+	};
+};
+
+#define C_LPE_CFG_PE_LE_POOLS_OFFSET(idx)	(0x00000480 + ((idx) * 8))
+#define C_LPE_CFG_PE_LE_POOLS_ENTRIES	64
+#define C_LPE_CFG_PE_LE_POOLS(idx)	(C_LPE_BASE + C_LPE_CFG_PE_LE_POOLS_OFFSET(idx))
+#define C_LPE_CFG_PE_LE_POOLS_SIZE	0x00000200
+
+union c_lpe_cfg_pe_le_pools {
+	__u64 qw;
+	struct {
+		__u64 num_reserved  : 15;
+		__u64: 17;
+		__u64 max_alloc     : 15;
+		__u64: 17;
+	};
+};
+
+#define C_LPE_STS_PE_LE_ALLOC_OFFSET(idx)	(0x00000800 + ((idx) * 8))
+#define C_LPE_STS_PE_LE_ALLOC_ENTRIES	64
+#define C_LPE_STS_PE_LE_ALLOC(idx)	(C_LPE_BASE + C_LPE_STS_PE_LE_ALLOC_OFFSET(idx))
+#define C_LPE_STS_PE_LE_ALLOC_SIZE	0x00000200
+
+union c_lpe_sts_pe_le_alloc {
+	__u64 qw;
+	struct {
+		__u64 num_allocated  : 15;
+		__u64: 49;
+	};
+};
+
+#define C_LPE_CFG_PE_LE_SHARED_OFFSET(idx)	(0x00000a00 + ((idx) * 8))
+#define C_LPE_CFG_PE_LE_SHARED_ENTRIES	4
+#define C_LPE_CFG_PE_LE_SHARED(idx)	(C_LPE_BASE + C_LPE_CFG_PE_LE_SHARED_OFFSET(idx))
+#define C_LPE_CFG_PE_LE_SHARED_SIZE	0x00000020
+
+union c_lpe_cfg_pe_le_shared {
+	__u64 qw;
+	struct {
+		__u64 num_shared_allocated  : 15;
+		__u64: 1;
+		__u64 num_total_allocated   : 15;
+		__u64: 1;
+		__u64 num_shared            : 15;
+		__u64: 1;
+		__u64 num_total             : 15;
+		__u64: 1;
+	};
+};
+
+#define C_LPE_STS_INIT_DONE_OFFSET	0x00000a28
+#define C_LPE_STS_INIT_DONE	(C_LPE_BASE + C_LPE_STS_INIT_DONE_OFFSET)
+#define C_LPE_STS_INIT_DONE_SIZE	0x00000008
+
+union c_lpe_sts_init_done {
+	__u64 qw;
+	struct {
+		__u64 ptlte_init_done      :  1;
+		__u64 free_mask_init_done  :  4;
+		__u64: 59;
+	};
+};
+
+#define C_LPE_STS_CDTS_IN_USE_OFFSET	0x00000a30
+#define C_LPE_STS_CDTS_IN_USE	(C_LPE_BASE + C_LPE_STS_CDTS_IN_USE_OFFSET)
+#define C_LPE_STS_CDTS_IN_USE_SIZE	0x00000008
+
+union c_lpe_sts_cdts_in_use {
+	__u64 qw;
+	struct {
+		__u64 ixemrq_wc_cdts_in_use  :  4;
+		__u64 cqmrq_wc_cdts_in_use   :  4;
+		__u64 rdy_ple_cdts_in_use    :  4;
+		__u64 event_cdts_in_use      :  5;
+		__u64: 3;
+		__u64 ixe_put_cdts_in_use    :  4;
+		__u64 ixe_get_cdts_in_use    :  4;
+		__u64 ixe_mst_cdts_in_use    :  4;
+		__u64 pe0_rrq_cdts_in_use    :  3;
+		__u64: 1;
+		__u64 pe1_rrq_cdts_in_use    :  3;
+		__u64: 1;
+		__u64 pe2_rrq_cdts_in_use    :  3;
+		__u64: 1;
+		__u64 pe3_rrq_cdts_in_use    :  3;
+		__u64: 17;
+	};
+};
+
+#define C_LPE_MSC_LE_POOL_FREE_OFFSET(idx)	(0x00000a40 + ((idx) * 8))
+#define C_LPE_MSC_LE_POOL_FREE_ENTRIES	4
+#define C_LPE_MSC_LE_POOL_FREE(idx)	(C_LPE_BASE + C_LPE_MSC_LE_POOL_FREE_OFFSET(idx))
+#define C_LPE_MSC_LE_POOL_FREE_SIZE	0x00000020
+
+union c_lpe_msc_le_pool_free {
+	__u64 qw;
+	struct {
+		__u64 le_pool  :  4;
+		__u64 free_en  :  1;
+		__u64: 59;
+	};
+};
+
+#define C_LPE_MSC_LOAD_STATS_DOORBELL_OFFSET	0x00000a60
+#define C_LPE_MSC_LOAD_STATS_DOORBELL	(C_LPE_BASE + C_LPE_MSC_LOAD_STATS_DOORBELL_OFFSET)
+#define C_LPE_MSC_LOAD_STATS_DOORBELL_SIZE	0x00000008
+
+union c_lpe_msc_load_stats_doorbell {
+	__u64 qw;
+	struct {
+		__u64 doorbell  :  1;
+		__u64: 63;
+	};
+};
+
+#define C_LPE_STS_PE_FREE_MASK_OFFSET(idx)	(0x00001000 + ((idx) * 8))
+#define C_LPE_STS_PE_FREE_MASK_ENTRIES	1024
+#define C_LPE_STS_PE_FREE_MASK(idx)	(C_LPE_BASE + C_LPE_STS_PE_FREE_MASK_OFFSET(idx))
+#define C_LPE_STS_PE_FREE_MASK_SIZE	0x00002000
+
+union c_lpe_sts_pe_free_mask {
+	__u64 qw;
+	struct {
+		__u64 free_mask;
+	};
+};
+
+#define C_LPE_STS_LOAD_STATS_OFFSET(idx)	(0x00003000 + ((idx) * 8))
+#define C_LPE_STS_LOAD_STATS_ENTRIES	4
+#define C_LPE_STS_LOAD_STATS(idx)	(C_LPE_BASE + C_LPE_STS_LOAD_STATS_OFFSET(idx))
+#define C_LPE_STS_LOAD_STATS_SIZE	0x00000020
+
+union c_lpe_sts_load_stats {
+	__u64 qw;
+	struct {
+		__u64 load  : 48;
+		__u64: 12;
+		__u64 max   :  4;
+	};
+};
+
+#define C_LPE_CFG_PTL_TABLE_OFFSET(idx)	(0x00010000 + ((idx) * 32))
+#define C_LPE_CFG_PTL_TABLE_ENTRIES	2048
+#define C_LPE_CFG_PTL_TABLE(idx)	(C_LPE_BASE + C_LPE_CFG_PTL_TABLE_OFFSET(idx))
+#define C_LPE_CFG_PTL_TABLE_SIZE	0x00010000
+
+struct c_lpe_cfg_ptl_table_ptrs {
+	__u32 tail		  : 14;
+	__u32:  2;
+	__u32 head             : 14;
+	__u32 append_disabled  :  1; /* not for unexpected */
+	__u32 list_vld         :  1;
+};
+union c_lpe_cfg_ptl_table {
+	__u64 qw[4];
+	struct {
+		__u64 clr_remote_offset      :  1;
+		__u64 en_flowctrl            :  1;
+		__u64 use_long_event         :  1;
+		__u64 lossless               :  1;
+		__u64 en_event_match         :  1;
+		__u64: 11;
+		__u64 eq_handle              : 11;
+		__u64:  5;
+		__u64 eq_handle_no_rget      : 11;
+		__u64:  5;
+		__u64 le_pool                :  4;
+		__u64 en_restricted_unicast_lm :  1;
+		__u64 use_logical            :  1;
+		__u64 is_matching            :  1;
+		__u64 do_space_check         :  1;
+		__u64 cntr_pool              :  2;
+		__u64 pe_num                 :  2;
+		__u64 en_align_lm            :  1;
+		__u64 en_match_on_vni        :  1; /* Cassini 2 only */
+		__u64:  1;
+		__u64 en_sw_hw_st_chng       :  1;
+		struct c_lpe_cfg_ptl_table_ptrs l[4];
+		__u64 ptl_state              :  3;
+		__u64: 29;
+		__u64 drop_count             : 24;
+		__u64 signal_invalid         :  1;
+		__u64 signal_underflow       :  1;
+		__u64 signal_overflow        :  1;
+		__u64 signal_inexact         :  1;
+		__u64:  4;
+	};
+};
+
+#define C_LPE_DBG_MRR_OFFSET(idx)	(0x00040000 + ((idx) * 64))
+#define C_LPE_DBG_MRR_ENTRIES	2560
+#define C_LPE_DBG_MRR(idx)	(C_LPE_BASE + C_LPE_DBG_MRR_OFFSET(idx))
+#define C_LPE_DBG_MRR_SIZE	0x00028000
+
+union c_lpe_dbg_mrr {
+	__u64 qw[7];
+};
+
+#define C_LPE_DBG_RGET_RAM_OFFSET(idx)	(0x00068000 + ((idx) * 64))
+#define C_LPE_DBG_RGET_RAM_ENTRIES	256
+#define C_LPE_DBG_RGET_RAM(idx)	(C_LPE_BASE + C_LPE_DBG_RGET_RAM_OFFSET(idx))
+#define C_LPE_DBG_RGET_RAM_SIZE	0x00004000
+
+union c_lpe_dbg_rget_ram {
+	__u64 qw[7];
+	struct {
+		__u64 vni             : 16;
+		__u64 buffer_id       : 16;
+		__u64 eq              : 11;
+		__u64 ct              : 11;
+		__u64 ac              : 10;
+		__u64 ptlte_index     : 11;
+		__u64: 1;
+		__u64 sfa_nid         : 20;
+		__u64 eager_len       : 20;
+		__u64: 4;
+		__u64 rendezvous_id   :  8;
+		__u64 hdr_data;
+		__u64 addr            : 57;
+		__u64: 7;
+		__u64 remote_offset   : 56;
+		__u64 event_ct_reply  :  1;
+		__u64 event_ct_bytes  :  1;
+		__u64 dscp            :  6;
+		__u64 request_len     : 32;
+		__u64: 23;
+		__u64 initiator_pid   :  9;
+		__u64 cmdq_id         :  9;
+		__u64: 39;
+		__u64 match_bits_up   : 16;
+	};
+};
+
+#define C_LPE_STS_EVENT_CNTS_OFFSET(idx)	(0x00070000 + ((idx) * 8))
+#ifndef C_LPE_STS_EVENT_CNTS_ENTRIES
+#define C_LPE_STS_EVENT_CNTS_ENTRIES	512
+#endif
+#define C_LPE_STS_EVENT_CNTS(idx)	(C_LPE_BASE + C_LPE_STS_EVENT_CNTS_OFFSET(idx))
+#define C_LPE_STS_EVENT_CNTS_SIZE	0x00001000
+
+union c_lpe_sts_event_cnts {
+	__u64 qw;
+	struct {
+		__u64 cnt  : 56;
+		__u64: 8;
+	};
+};
+
+#define C_LPE_STS_LIST_ENTRIES_OFFSET(idx)	(0x00400000 + ((idx) * 64))
+#define C_LPE_STS_LIST_ENTRIES_ENTRIES	65536
+#define C_LPE_STS_LIST_ENTRIES(idx)	(C_LPE_BASE + C_LPE_STS_LIST_ENTRIES_OFFSET(idx))
+#define C_LPE_STS_LIST_ENTRIES_SIZE	0x00400000
+
+union c_lpe_sts_list_entries {
+	__u64 qw[6];
+};
+
+#define C_MB_CFG_CRNC_OFFSET	0x00000000
+#define C_MB_CFG_CRNC	(C_MB_BASE + C_MB_CFG_CRNC_OFFSET)
+#define C_MB_CFG_CRNC_SIZE	0x00000008
+
+union c_mb_cfg_crnc {
+	__u64 qw;
+	struct {
+		__u64 csr_timeout   :  8;
+		__u64 mcast_id      : 10;
+		__u64: 1;
+		__u64 mcast_enable  :  1;
+		__u64 mcast_mask    : 10;
+		__u64: 34;
+	};
+};
+
+#define C_MB_CFG_RT_OFFSET_OFFSET	0x00000020
+#define C_MB_CFG_RT_OFFSET	(C_MB_BASE + C_MB_CFG_RT_OFFSET_OFFSET)
+#define C_MB_CFG_RT_OFFSET_SIZE	0x00000008
+
+union c_mb_cfg_rt_offset {
+	__u64 qw;
+	struct {
+		__u64 seconds  : 48;
+		__u64: 16;
+	};
+};
+
+#define C_MB_MSC_SHADOW_ACTION_OFFSET	0x00000038
+#define C_MB_MSC_SHADOW_ACTION	(C_MB_BASE + C_MB_MSC_SHADOW_ACTION_OFFSET)
+#define C_MB_MSC_SHADOW_ACTION_SIZE	0x00000008
+
+union c_any_msc_shadow_action {
+	__u64 qw;
+	struct {
+		__u64 addr_offset  : 23;
+		__u64: 8;
+		__u64 write        :  1;
+		__u64: 32;
+	};
+};
+
+#define C_MB_MSC_SHADOW_OFFSET	0x00000040
+#define C_MB_MSC_SHADOW	(C_MB_BASE + C_MB_MSC_SHADOW_OFFSET)
+#define C_MB_MSC_SHADOW_SIZE	0x00000028
+
+union c_mb_msc_shadow {
+	__u64 qw[5];
+};
+
+#define C_MB_ERR_ELAPSED_TIME_OFFSET	0x00000100
+#define C_MB_ERR_ELAPSED_TIME	(C_MB_BASE + C_MB_ERR_ELAPSED_TIME_OFFSET)
+#define C_MB_ERR_ELAPSED_TIME_SIZE	0x00000008
+
+union c_mb_err_elapsed_time {
+	__u64 qw;
+	struct {
+		__u64 nanoseconds  : 30;
+		__u64 seconds      : 34;
+	};
+};
+
+#define C_MB_ERR_FLG_OFFSET	0x00000108
+#define C_MB_ERR_FLG	(C_MB_BASE + C_MB_ERR_FLG_OFFSET)
+#define C_MB_ERR_FLG_SIZE	0x00000008
+
+union c_mb_err_flg {
+	__u64 qw;
+	struct {
+		__u64 sw_diag                   :  1;
+		__u64 crnc_ring_sync_error      :  1;
+		__u64 crnc_ring_ecc_sbe         :  1;
+		__u64 crnc_ring_ecc_mbe         :  1;
+		__u64 crnc_ring_cmd_unknown     :  1;
+		__u64 crnc_csr_cmd_unknown      :  1;
+		__u64 crnc_csr_cmd_incomplete   :  1;
+		__u64 crnc_buf_ecc_sbe          :  1;
+		__u64 crnc_buf_ecc_mbe          :  1;
+		__u64: 7;
+		__u64 crmc_ring_sync_error      :  1;
+		__u64 crmc_ring_ecc_sbe         :  1;
+		__u64 crmc_ring_ecc_mbe         :  1;
+		__u64 crmc_ring_cmd_unknown     :  1;
+		__u64 crmc_wr_error             :  1;
+		__u64 crmc_wr_addr_invalid      :  1;
+		__u64 crmc_wr_cmd_invalid       :  1;
+		__u64 crmc_wr_be_invalid        :  1;
+		__u64 crmc_wr_cor_error         :  1;
+		__u64 crmc_wr_uncor_error       :  1;
+		__u64 crmc_wr_burst_error       :  1;
+		__u64 crmc_wr_mcast_nack        :  1;
+		__u64 crmc_wr_rsvd_error        :  1;
+		__u64 crmc_wr_wrapped           :  1;
+		__u64 crmc_wr_timeout           :  1;
+		__u64 crmc_wr_axi_req_error     :  1;
+		__u64 crmc_wr_axi_ring_error    :  1;
+		__u64 crmc_wr_axi_wstrb_error   :  1;
+		__u64 crmc_wr_axi_parity_error  :  1;
+		__u64 crmc_rd_error             :  1;
+		__u64 crmc_rd_addr_invalid      :  1;
+		__u64 crmc_rd_cmd_invalid       :  1;
+		__u64 crmc_rd_be_invalid        :  1;
+		__u64 crmc_rd_cor_error         :  1;
+		__u64 crmc_rd_uncor_error       :  1;
+		__u64 crmc_rd_burst_error       :  1;
+		__u64 crmc_rd_mcast_nack        :  1;
+		__u64 crmc_rd_rsvd_error        :  1;
+		__u64 crmc_rd_wrapped           :  1;
+		__u64 crmc_rd_timeout           :  1;
+		__u64 crmc_rd_axi_req_error     :  1;
+		__u64 crmc_rd_axi_ring_error    :  1;
+		__u64 cmc_wr_error              :  4;
+		__u64 cmc_rd_error              :  4;
+		__u64 event_cnt_ovf             :  1;
+		__u64 event_ram_cor             :  1;
+		__u64 event_ram_ucor            :  1;
+		__u64 flash_cache0_cor          :  1;
+		__u64 flash_cache0_ucor         :  1;
+		__u64 flash_cache1_cor          :  1;
+		__u64 flash_cache1_ucor         :  1;
+		__u64 spi_ecc_error             :  1;
+	};
+};
+
+#define C_MB_ERR_FIRST_FLG_OFFSET	0x00000110
+#define C_MB_ERR_FIRST_FLG	(C_MB_BASE + C_MB_ERR_FIRST_FLG_OFFSET)
+#define C_MB_ERR_FIRST_FLG_SIZE	0x00000008
+
+union c_any_err_first_flg {
+	__u64 qw;
+	struct {
+		__u64 err_first_flg;
+	};
+};
+
+#define C_MB_ERR_FIRST_FLG_TS_OFFSET	0x00000118
+#define C_MB_ERR_FIRST_FLG_TS	(C_MB_BASE + C_MB_ERR_FIRST_FLG_TS_OFFSET)
+#define C_MB_ERR_FIRST_FLG_TS_SIZE	0x00000008
+
+union c_any_err_first_flg_ts {
+	__u64 qw;
+	struct {
+		__u64 nanoseconds  : 30;
+		__u64 seconds      : 34;
+	};
+};
+
+#define C_MB_ERR_CLR_OFFSET	0x00000120
+#define C_MB_ERR_CLR	(C_MB_BASE + C_MB_ERR_CLR_OFFSET)
+#define C_MB_ERR_CLR_SIZE	0x00000008
+
+union c_any_err_clr {
+	__u64 qw;
+	struct {
+		__u64 err_clr;
+	};
+};
+
+#define C_MB_ERR_IRQA_MSK_OFFSET	0x00000128
+#define C_MB_ERR_IRQA_MSK	(C_MB_BASE + C_MB_ERR_IRQA_MSK_OFFSET)
+#define C_MB_ERR_IRQA_MSK_SIZE	0x00000008
+
+union c_any_err_irqa_msk {
+	__u64 qw;
+	struct {
+		__u64 err_irq_msk;
+	};
+};
+
+#define C_MB_ERR_IRQB_MSK_OFFSET	0x00000130
+#define C_MB_ERR_IRQB_MSK	(C_MB_BASE + C_MB_ERR_IRQB_MSK_OFFSET)
+#define C_MB_ERR_IRQB_MSK_SIZE	0x00000008
+
+union c_any_err_irqb_msk {
+	__u64 qw;
+	struct {
+		__u64 err_irq_msk;
+	};
+};
+
+#define C_MB_ERR_INFO_MSK_OFFSET	0x00000140
+#define C_MB_ERR_INFO_MSK	(C_MB_BASE + C_MB_ERR_INFO_MSK_OFFSET)
+#define C_MB_ERR_INFO_MSK_SIZE	0x00000008
+
+union c_any_err_info_msk {
+	__u64 qw;
+	struct {
+		__u64 err_info_msk;
+	};
+};
+
+#define C_MB_ERR_INFO_MEM_OFFSET	0x00000150
+#define C_MB_ERR_INFO_MEM	(C_MB_BASE + C_MB_ERR_INFO_MEM_OFFSET)
+#define C_MB_ERR_INFO_MEM_SIZE	0x00000008
+
+union c_mb_err_info_mem {
+	__u64 qw;
+	struct {
+		__u64 cor_syndrome       :  9;
+		__u64: 3;
+		__u64 cor_address        : 13;
+		__u64: 3;
+		__u64 cor_mem_id         :  2;
+		__u64: 1;
+		__u64 cor_csr_detected   :  1;
+		__u64 ucor_syndrome      :  9;
+		__u64: 3;
+		__u64 ucor_address       : 13;
+		__u64: 3;
+		__u64 ucor_mem_id        :  2;
+		__u64: 1;
+		__u64 ucor_csr_detected  :  1;
+	};
+};
+
+#define C_MB_ERR_INFO_CRMC_OFFSET	0x00000158
+#define C_MB_ERR_INFO_CRMC	(C_MB_BASE + C_MB_ERR_INFO_CRMC_OFFSET)
+#define C_MB_ERR_INFO_CRMC_SIZE	0x00000008
+
+union c_mb_err_info_crmc {
+	__u64 qw;
+	struct {
+		__u64 ring_id        : 10;
+		__u64: 2;
+		__u64 ring           :  3;
+		__u64: 1;
+		__u64 crnc_ring_sts  :  4;
+		__u64 crmc_ring_sts  :  1;
+		__u64: 43;
+	};
+};
+
+#define C_MB_ERR_INFO_CMC_WR_OFFSET	0x00000160
+#define C_MB_ERR_INFO_CMC_WR	(C_MB_BASE + C_MB_ERR_INFO_CMC_WR_OFFSET)
+#define C_MB_ERR_INFO_CMC_WR_SIZE	0x00000018
+
+union c_mb_err_info_cmc_wr {
+	__u64 qw[3];
+	struct {
+		__u64 mst_awaddr    : 32;
+		__u64 mst_awuser    : 32;
+		__u64 mst_wdata;
+		__u64 mst_wderr     :  8;
+		__u64 mst_wstrb     :  8;
+		__u64 mst_awid      :  4;
+		__u64 mst_awregion  :  4;
+		__u64 mst_awlen     :  8;
+		__u64 mst_awsize    :  3;
+		__u64 mst_awburst   :  2;
+		__u64 mst_awmid     :  4;
+		__u64 mst_awlock    :  1;
+		__u64 mst_awqos     :  4;
+		__u64 mst_awprot    :  3;
+		__u64 mst_awcache   :  4;
+		__u64 slv_bresp     :  2;
+		__u64 slv_bid       :  4;
+		__u64 cmc_port      :  2;
+		__u64 ring          :  3;
+	};
+};
+
+#define C_MB_ERR_INFO_CMC_RD_OFFSET	0x00000180
+#define C_MB_ERR_INFO_CMC_RD	(C_MB_BASE + C_MB_ERR_INFO_CMC_RD_OFFSET)
+#define C_MB_ERR_INFO_CMC_RD_SIZE	0x00000018
+
+union c_mb_err_info_cmc_rd {
+	__u64 qw[3];
+	struct {
+		__u64 mst_araddr    : 32;
+		__u64 mst_aruser    : 32;
+		__u64 slv_rdata;
+		__u64 slv_rderr     :  8;
+		__u64 slv_ruser     :  8;
+		__u64 mst_arid      :  4;
+		__u64 mst_arregion  :  4;
+		__u64 mst_arlen     :  8;
+		__u64 mst_arsize    :  3;
+		__u64 mst_arburst   :  2;
+		__u64 mst_armid     :  4;
+		__u64 mst_arlock    :  1;
+		__u64 mst_arqos     :  4;
+		__u64 mst_arprot    :  3;
+		__u64 mst_arcache   :  4;
+		__u64 slv_rresp     :  2;
+		__u64 slv_rid       :  4;
+		__u64 cmc_port      :  2;
+		__u64 ring          :  3;
+	};
+};
+
+#define C_MB_ERR_INFO_SPI_OFFSET	0x000001a0
+#define C_MB_ERR_INFO_SPI	(C_MB_BASE + C_MB_ERR_INFO_SPI_OFFSET)
+#define C_MB_ERR_INFO_SPI_SIZE	0x00000008
+
+union c_mb_err_info_spi {
+	__u64 qw;
+	struct {
+		__u64: 3;
+		__u64 address  : 29;
+		__u64 status   :  8;
+		__u64: 24;
+	};
+};
+
+#define C_MB_EXT_ERR_FLG_OFFSET	0x00000208
+#define C_MB_EXT_ERR_FLG	(C_MB_BASE + C_MB_EXT_ERR_FLG_OFFSET)
+#define C_MB_EXT_ERR_FLG_SIZE	0x00000008
+
+union c_mb_ext_err_flg {
+	__u64 qw;
+	struct {
+		__u64 sw_diag                      :  1;
+		__u64 jai_axi_cadr_unexpected_cmd  :  1;
+		__u64 jai_axi_cadr_unknown_cmd     :  1;
+		__u64 jai_axi_wr_decerr            :  1;
+		__u64 jai_axi_wr_slverr            :  1;
+		__u64 jai_axi_rd_decerr            :  1;
+		__u64 jai_axi_rd_slverr            :  1;
+		__u64 jai_axi_rd_parity_error      :  1;
+		__u64 flm_csr_init_p1_spi_err      :  1;
+		__u64 flm_csr_init_p2_spi_err      :  1;
+		__u64 flm_csr_init_p1_fail         :  1;
+		__u64 flm_csr_init_p2_fail         :  1;
+		__u64 flm_csr_init_p1_abort        :  1;
+		__u64 flm_csr_init_p2_abort        :  1;
+		__u64 flm_csr_init_p1_len_err      :  1;
+		__u64 flm_csr_init_p2_len_err      :  1;
+		__u64 flm_csr_init_p1_cont_err     :  1;
+		__u64 flm_csr_init_p2_cont_err     :  1;
+		__u64 flm_csr_init_p1_axi_decerr   :  1;
+		__u64 flm_csr_init_p2_axi_decerr   :  1;
+		__u64 flm_csr_init_p1_axi_slverr   :  1;
+		__u64 flm_csr_init_p2_axi_slverr   :  1;
+		__u64 flm_serdes_rom_load_spi_err  :  1;
+		__u64 flm_serdes_rom_load_error    :  1;
+		__u64 flm_serdes_rom_load_abort    :  1;
+		__u64 flm_serdes_rom_load_fail     :  1;
+		__u64 flm_hg_spi_error             :  1;
+		__u64 flm_hg_addr_error            :  1;
+		__u64 flm_sbus_wr_error            :  1;
+		__u64 flm_sbus_rd_error            :  1;
+		__u64: 34;
+	};
+};
+
+#define C_MB_EXT_ERR_FIRST_FLG_OFFSET	0x00000210
+#define C_MB_EXT_ERR_FIRST_FLG	(C_MB_BASE + C_MB_EXT_ERR_FIRST_FLG_OFFSET)
+#define C_MB_EXT_ERR_FIRST_FLG_SIZE	0x00000008
+#define C_MB_EXT_ERR_FIRST_FLG_TS_OFFSET	0x00000218
+#define C_MB_EXT_ERR_FIRST_FLG_TS	(C_MB_BASE + C_MB_EXT_ERR_FIRST_FLG_TS_OFFSET)
+#define C_MB_EXT_ERR_FIRST_FLG_TS_SIZE	0x00000008
+#define C_MB_EXT_ERR_CLR_OFFSET	0x00000220
+#define C_MB_EXT_ERR_CLR	(C_MB_BASE + C_MB_EXT_ERR_CLR_OFFSET)
+#define C_MB_EXT_ERR_CLR_SIZE	0x00000008
+#define C_MB_EXT_ERR_IRQA_MSK_OFFSET	0x00000228
+#define C_MB_EXT_ERR_IRQA_MSK	(C_MB_BASE + C_MB_EXT_ERR_IRQA_MSK_OFFSET)
+#define C_MB_EXT_ERR_IRQA_MSK_SIZE	0x00000008
+#define C_MB_EXT_ERR_IRQB_MSK_OFFSET	0x00000230
+#define C_MB_EXT_ERR_IRQB_MSK	(C_MB_BASE + C_MB_EXT_ERR_IRQB_MSK_OFFSET)
+#define C_MB_EXT_ERR_IRQB_MSK_SIZE	0x00000008
+#define C_MB_EXT_ERR_INFO_MSK_OFFSET	0x00000240
+#define C_MB_EXT_ERR_INFO_MSK	(C_MB_BASE + C_MB_EXT_ERR_INFO_MSK_OFFSET)
+#define C_MB_EXT_ERR_INFO_MSK_SIZE	0x00000008
+#define C_MB_CFG_MISC_OFFSET	0x00004000
+#define C_MB_CFG_MISC	(C_MB_BASE + C_MB_CFG_MISC_OFFSET)
+#define C_MB_CFG_MISC_SIZE	0x00000008
+
+union c_mb_cfg_misc {
+	__u64 qw;
+	struct {
+		__u64 nic_warm_rst0                     :  1;
+		__u64 nic_warm_rst1                     :  1;
+		__u64 nic_warm_rst2                     :  1;
+		__u64 nic_warm_rst3                     :  1;
+		__u64 nic_warm_rst4                     :  1;
+		__u64 nic_warm_rst5                     :  1;
+		__u64 nic_warm_rst6                     :  1;
+		__u64 nic_warm_rst7                     :  1;
+		__u64 nic_warm_rst8                     :  1;
+		__u64 nic_warm_rst9                     :  1;
+		__u64: 6;
+		__u64 nic_warm_rst_mask                 : 10;
+		__u64 mb_warm_rst_mask                  :  1;
+		__u64 pi_warm_rst_mask                  :  1;
+		__u64: 3;
+		__u64 halt_clock_en                     :  1;
+		__u64 cold_rst_enable                   : 16;
+		__u64 cold_rst                          :  1;
+		__u64 mb_cold_rst_enable                :  1;
+		__u64 cold_rst_on_perst                 :  1;
+		__u64 cold_rst_on_hot_rst               :  1;
+		__u64 skip_rom_load_on_forced_cold_rst  :  1;
+		__u64 ignore_link_req_rst               :  1;
+		__u64 ignore_gpout_all_done             :  1;
+		__u64 ignore_gpout_efuse_done           :  1;
+		__u64 ignore_gpout_temp_pushed          :  1;
+		__u64 ignore_ancil_osc_clk_rdy          :  1;
+		__u64: 6;
+	};
+};
+
+#define C_MB_STS_REV_OFFSET	0x00004008
+#define C_MB_STS_REV	(C_MB_BASE + C_MB_STS_REV_OFFSET)
+#define C_MB_STS_REV_SIZE	0x00000008
+
+union c_mb_sts_rev {
+	__u64 qw;
+	struct {
+		__u64 rev        : 16;
+		__u64 device_id  : 16;
+		__u64 vendor_id  : 16;
+		__u64 proto      : 12;
+		__u64 platform   :  4;
+	};
+};
+
+#define C_MB_CFG_EVENT_CNTS_OFFSET	0x00004010
+#define C_MB_CFG_EVENT_CNTS	(C_MB_BASE + C_MB_CFG_EVENT_CNTS_OFFSET)
+#define C_MB_CFG_EVENT_CNTS_SIZE	0x00000008
+
+union c_mb_cfg_event_cnts {
+	__u64 qw;
+	struct {
+		__u64 enable            :  1;
+		__u64 init              :  1;
+		__u64 init_done         :  1;
+		__u64 warm_rst_disable  :  1;
+		__u64 ovf_cnt           : 16;
+		__u64: 44;
+	};
+};
+
+#define C_MB_DBG_SCRATCH_OFFSET(idx)	(0x00004020 + ((idx) * 8))
+#define C_MB_DBG_SCRATCH_ENTRIES	8
+#define C_MB_DBG_SCRATCH(idx)	(C_MB_BASE + C_MB_DBG_SCRATCH_OFFSET(idx))
+#define C_MB_DBG_SCRATCH_SIZE	0x00000040
+
+union c_mb_dbg_scratch {
+	__u64 qw;
+	struct {
+		__u64 scratch;
+	};
+};
+
+#define C_MB_CFG_CRMC_OFFSET(idx)	(0x0000d000 + ((idx) * 8))
+#define C_MB_CFG_CRMC_ENTRIES	3
+#define C_MB_CFG_CRMC(idx)	(C_MB_BASE + C_MB_CFG_CRMC_OFFSET(idx))
+#define C_MB_CFG_CRMC_SIZE	0x00000018
+
+union c_mb_cfg_crmc {
+	__u64 qw;
+	struct {
+		__u64 ring_timeout                    :  8;
+		__u64 rready_timeout_disable          :  1;
+		__u64 bready_timeout_disable          :  1;
+		__u64 rd_addr_invalid_decerr_disable  :  1;
+		__u64: 53;
+	};
+};
+
+#define C_MB_DBG_CFG_SBUS_MASTER_OFFSET	0x0000e000
+#define C_MB_DBG_CFG_SBUS_MASTER	(C_MB_BASE + C_MB_DBG_CFG_SBUS_MASTER_OFFSET)
+#define C_MB_DBG_CFG_SBUS_MASTER_SIZE	0x00000008
+
+union c_mb_dbg_cfg_sbus_master {
+	__u64 qw;
+	struct {
+		__u64 execute              :  1;
+		__u64 rcv_data_valid_sel   :  1;
+		__u64 mode                 :  1;
+		__u64 stop_on_overrun      :  1;
+		__u64 stop_on_write_error  :  1;
+		__u64: 3;
+		__u64 command              :  8;
+		__u64 receiver_address     :  8;
+		__u64 data_address         :  8;
+		__u64 data                 : 32;
+	};
+};
+
+#define C_MB_DBG_STS_SBUS_MASTER_OFFSET	0x0000e010
+#define C_MB_DBG_STS_SBUS_MASTER	(C_MB_BASE + C_MB_DBG_STS_SBUS_MASTER_OFFSET)
+#define C_MB_DBG_STS_SBUS_MASTER_SIZE	0x00000008
+
+union c_mb_dbg_sts_sbus_master {
+	__u64 qw;
+	struct {
+		__u64 done              :  1;
+		__u64 rcv_data_valid    :  1;
+		__u64 overrun           :  1;
+		__u64 write_error       :  1;
+		__u64 result_code       :  3;
+		__u64: 1;
+		__u64 command           :  8;
+		__u64 receiver_address  :  8;
+		__u64 data_address      :  8;
+		__u64 data              : 32;
+	};
+};
+
+#define C_MB_CFG_RTC_OFFSET	0x0000f000
+#define C_MB_CFG_RTC	(C_MB_BASE + C_MB_CFG_RTC_OFFSET)
+#define C_MB_CFG_RTC_SIZE	0x00000008
+
+union c_mb_cfg_rtc {
+	__u64 qw;
+	struct {
+		__u64 rtc_enable               :  1;
+		__u64 rtc_load                 :  1;
+		__u64 rtc_update               :  1;
+		__u64: 1;
+		__u64 rtc_etc_sec_change_mask  :  3;
+		__u64: 9;
+		__u64 etc_enable               :  1;
+		__u64 etc_load                 :  1;
+		__u64: 2;
+		__u64 etc_ns_lock_resolution   :  3;
+		__u64: 41;
+	};
+};
+
+#define C_MB_STS_RTC_OFFSET	0x0000f008
+#define C_MB_STS_RTC	(C_MB_BASE + C_MB_STS_RTC_OFFSET)
+#define C_MB_STS_RTC_SIZE	0x00000008
+
+union c_mb_sts_rtc {
+	__u64 qw;
+	struct {
+		__u64 rtc_minus_etc_sec         : 48;
+		__u64 rtc_lt_etc_sec            :  1;
+		__u64 rtc_minus_etc_sec_change  :  1;
+		__u64 etc_ns_locked             :  1;
+		__u64 etc_ns_lost_lock          :  1;
+		__u64: 12;
+	};
+};
+
+#define C_MB_CFG_RTC_TIME_OFFSET	0x0000f010
+#define C_MB_CFG_RTC_TIME	(C_MB_BASE + C_MB_CFG_RTC_TIME_OFFSET)
+#define C_MB_CFG_RTC_TIME_SIZE	0x00000010
+
+union c_mb_cfg_rtc_time {
+	__u64 qw[2];
+	struct {
+		__u64 nanoseconds    : 30;
+		__u64 seconds_33_0   : 34;
+		__u64 seconds_47_34  : 14;
+		__u64: 50;
+	};
+};
+
+#define C_MB_CFG_RTC_INC_OFFSET	0x0000f020
+#define C_MB_CFG_RTC_INC	(C_MB_BASE + C_MB_CFG_RTC_INC_OFFSET)
+#define C_MB_CFG_RTC_INC_SIZE	0x00000008
+
+union c_mb_cfg_rtc_inc {
+	__u64 qw;
+	struct {
+		__u64 fractional_ns  : 32;
+		__u64 nanoseconds    : 10;
+		__u64: 22;
+	};
+};
+
+#define C_MB_STS_RTC_CURRENT_TIME_OFFSET	0x0000f030
+#define C_MB_STS_RTC_CURRENT_TIME	(C_MB_BASE + C_MB_STS_RTC_CURRENT_TIME_OFFSET)
+#define C_MB_STS_RTC_CURRENT_TIME_SIZE	0x00000010
+
+union c_mb_sts_rtc_current_time {
+	__u64 qw[2];
+	struct {
+		__u64 nanoseconds    : 30;
+		__u64 seconds_33_0   : 34;
+		__u64 seconds_47_34  : 14;
+		__u64: 50;
+	};
+};
+
+#define C_MB_STS_RTC_LAST_TIME_OFFSET	0x0000f040
+#define C_MB_STS_RTC_LAST_TIME	(C_MB_BASE + C_MB_STS_RTC_LAST_TIME_OFFSET)
+#define C_MB_STS_RTC_LAST_TIME_SIZE	0x00000010
+
+union c_mb_sts_rtc_last_time {
+	__u64 qw[2];
+	struct {
+		__u64 nanoseconds    : 30;
+		__u64 seconds_33_0   : 34;
+		__u64 seconds_47_34  : 14;
+		__u64: 50;
+	};
+};
+
+#define C_MB_STS_RTC_ETC_CUR_TIME_OFFSET	0x0000f050
+#define C_MB_STS_RTC_ETC_CUR_TIME	(C_MB_BASE + C_MB_STS_RTC_ETC_CUR_TIME_OFFSET)
+#define C_MB_STS_RTC_ETC_CUR_TIME_SIZE	0x00000008
+
+union c_mb_sts_rtc_etc_cur_time {
+	__u64 qw;
+	struct {
+		__u64 nanoseconds  : 30;
+		__u64 seconds      : 34;
+	};
+};
+
+#define C_MB_STS_RTC_ETC_LAST_TIME_OFFSET	0x0000f058
+#define C_MB_STS_RTC_ETC_LAST_TIME	(C_MB_BASE + C_MB_STS_RTC_ETC_LAST_TIME_OFFSET)
+#define C_MB_STS_RTC_ETC_LAST_TIME_SIZE	0x00000008
+
+union c_mb_sts_rtc_etc_last_time {
+	__u64 qw;
+	struct {
+		__u64 nanoseconds  : 30;
+		__u64 seconds      : 34;
+	};
+};
+
+#define C_MB_STS_EVENT_CNTS_OFFSET(idx)	(0x00020000 + ((idx) * 8))
+#ifndef C_MB_STS_EVENT_CNTS_ENTRIES
+#define C_MB_STS_EVENT_CNTS_ENTRIES	256
+#endif
+#define C_MB_STS_EVENT_CNTS(idx)	(C_MB_BASE + C_MB_STS_EVENT_CNTS_OFFSET(idx))
+#define C_MB_STS_EVENT_CNTS_SIZE	0x00000800
+
+union c_mb_sts_event_cnts {
+	__u64 qw;
+	struct {
+		__u64 cnt  : 56;
+		__u64: 8;
+	};
+};
+
+#define C_MST_CFG_CRNC_OFFSET	0x00000000
+#define C_MST_CFG_CRNC	(C_MST_BASE + C_MST_CFG_CRNC_OFFSET)
+#define C_MST_CFG_CRNC_SIZE	0x00000008
+
+union c_mst_cfg_crnc {
+	__u64 qw;
+	struct {
+		__u64 csr_timeout   :  8;
+		__u64 mcast_id      : 10;
+		__u64: 1;
+		__u64 mcast_enable  :  1;
+		__u64 mcast_mask    : 10;
+		__u64: 34;
+	};
+};
+
+#define C_MST_CFG_RT_OFFSET_OFFSET	0x00000020
+#define C_MST_CFG_RT_OFFSET	(C_MST_BASE + C_MST_CFG_RT_OFFSET_OFFSET)
+#define C_MST_CFG_RT_OFFSET_SIZE	0x00000008
+
+union c_mst_cfg_rt_offset {
+	__u64 qw;
+	struct {
+		__u64 seconds  : 48;
+		__u64: 16;
+	};
+};
+
+#define C_MST_MSC_SHADOW_ACTION_OFFSET	0x00000038
+#define C_MST_MSC_SHADOW_ACTION	(C_MST_BASE + C_MST_MSC_SHADOW_ACTION_OFFSET)
+#define C_MST_MSC_SHADOW_ACTION_SIZE	0x00000008
+#define C_MST_MSC_SHADOW_OFFSET	0x00000040
+#define C_MST_MSC_SHADOW	(C_MST_BASE + C_MST_MSC_SHADOW_OFFSET)
+#define C_MST_MSC_SHADOW_SIZE	0x00000040
+
+union c_mst_msc_shadow {
+	__u64 qw[8];
+};
+
+#define C_MST_ERR_ELAPSED_TIME_OFFSET	0x00000100
+#define C_MST_ERR_ELAPSED_TIME	(C_MST_BASE + C_MST_ERR_ELAPSED_TIME_OFFSET)
+#define C_MST_ERR_ELAPSED_TIME_SIZE	0x00000008
+
+union c_mst_err_elapsed_time {
+	__u64 qw;
+	struct {
+		__u64 nanoseconds  : 30;
+		__u64 seconds      : 34;
+	};
+};
+
+#define C_MST_ERR_FLG_OFFSET	0x00000108
+#define C_MST_ERR_FLG	(C_MST_BASE + C_MST_ERR_FLG_OFFSET)
+#define C_MST_ERR_FLG_SIZE	0x00000008
+
+union c_mst_err_flg {
+	__u64 qw;
+	struct {
+		__u64 sw_diag                  :  1;
+		__u64 crnc_ring_sync_error     :  1;
+		__u64 crnc_ring_ecc_sbe        :  1;
+		__u64 crnc_ring_ecc_mbe        :  1;
+		__u64 crnc_ring_cmd_unknown    :  1;
+		__u64 crnc_csr_cmd_unknown     :  1;
+		__u64 crnc_csr_cmd_incomplete  :  1;
+		__u64 crnc_buf_ecc_sbe         :  1;
+		__u64 crnc_buf_ecc_mbe         :  1;
+		__u64: 23;
+		__u64 lnk_list_ptrs_cor        :  1;
+		__u64 lnk_list_ptrs_ucor       :  1;
+		__u64: 2;
+		__u64 req_fifo_unrun           :  1;
+		__u64 req_fifo_ovrun           :  1;
+		__u64 req_fifo_crdt_unflw      :  1;
+		__u64: 5;
+		__u64 match_crdt_unflw_get     :  1;
+		__u64 match_crdt_unflw_put     :  1;
+		__u64 evnt_fifo_cor            :  1;
+		__u64 evnt_fifo_ucor           :  1;
+		__u64 evnt_fifo_unrun          :  1;
+		__u64 evnt_fifo_ovrun          :  1;
+		__u64 ee_crdt_unflw            :  1;
+		__u64 req_fifo_cor             :  1;
+		__u64 req_fifo_ucor            :  1;
+		__u64 mst_table_cor            :  1;
+		__u64 mst_table_ucor           :  1;
+		__u64 ll_data_ram_cor          :  1;
+		__u64 ll_data_ram_ucor         :  1;
+		__u64: 7;
+	};
+};
+
+#define C_MST_ERR_FIRST_FLG_OFFSET	0x00000110
+#define C_MST_ERR_FIRST_FLG	(C_MST_BASE + C_MST_ERR_FIRST_FLG_OFFSET)
+#define C_MST_ERR_FIRST_FLG_SIZE	0x00000008
+#define C_MST_ERR_FIRST_FLG_TS_OFFSET	0x00000118
+#define C_MST_ERR_FIRST_FLG_TS	(C_MST_BASE + C_MST_ERR_FIRST_FLG_TS_OFFSET)
+#define C_MST_ERR_FIRST_FLG_TS_SIZE	0x00000008
+#define C_MST_ERR_CLR_OFFSET	0x00000120
+#define C_MST_ERR_CLR	(C_MST_BASE + C_MST_ERR_CLR_OFFSET)
+#define C_MST_ERR_CLR_SIZE	0x00000008
+#define C_MST_ERR_IRQA_MSK_OFFSET	0x00000128
+#define C_MST_ERR_IRQA_MSK	(C_MST_BASE + C_MST_ERR_IRQA_MSK_OFFSET)
+#define C_MST_ERR_IRQA_MSK_SIZE	0x00000008
+#define C_MST_ERR_IRQB_MSK_OFFSET	0x00000130
+#define C_MST_ERR_IRQB_MSK	(C_MST_BASE + C_MST_ERR_IRQB_MSK_OFFSET)
+#define C_MST_ERR_IRQB_MSK_SIZE	0x00000008
+#define C_MST_ERR_INFO_MSK_OFFSET	0x00000140
+#define C_MST_ERR_INFO_MSK	(C_MST_BASE + C_MST_ERR_INFO_MSK_OFFSET)
+#define C_MST_ERR_INFO_MSK_SIZE	0x00000008
+#define C_MST_ERR_INFO_MEM_OFFSET	0x00000180
+#define C_MST_ERR_INFO_MEM	(C_MST_BASE + C_MST_ERR_INFO_MEM_OFFSET)
+#define C_MST_ERR_INFO_MEM_SIZE	0x00000008
+
+union c_mst_err_info_mem {
+	__u64 qw;
+	struct {
+		__u64 cor_syndrome       : 11;
+		__u64: 1;
+		__u64 cor_address        : 12;
+		__u64 cor_mem_id         :  6;
+		__u64: 1;
+		__u64 cor_csr_detected   :  1;
+		__u64 ucor_syndrome      : 11;
+		__u64: 1;
+		__u64 ucor_address       : 12;
+		__u64 ucor_mem_id        :  6;
+		__u64: 1;
+		__u64 ucor_csr_detected  :  1;
+	};
+};
+
+#define C_MST_CFG_RC_UPDATE_OFFSET	0x00000400
+#define C_MST_CFG_RC_UPDATE	(C_MST_BASE + C_MST_CFG_RC_UPDATE_OFFSET)
+#define C_MST_CFG_RC_UPDATE_SIZE	0x00000008
+
+union c_mst_cfg_rc_update {
+	__u64 qw;
+	struct {
+		__u64 return_code  :  6;
+		__u64: 2;
+		__u64 mst_idx      : 11;
+		__u64: 5;
+		__u64 buffer_idx   : 16;
+		__u64 portal_idx   : 11;
+		__u64: 1;
+		__u64 ptl_list     :  2;
+		__u64: 2;
+		__u64 ptl_vld      :  1;
+		__u64 portal_vld   :  1;
+		__u64 buffer_vld   :  1;
+		__u64: 5;
+	};
+};
+
+#define C_MST_STS_RC_STS_OFFSET	0x00010000
+#define C_MST_STS_RC_STS	(C_MST_BASE + C_MST_STS_RC_STS_OFFSET)
+#define C_MST_STS_RC_STS_SIZE	0x00000008
+
+union c_mst_sts_rc_sts {
+	__u64 qw;
+	struct {
+		__u64 done   :  1;
+		__u64 match  :  1;
+		__u64: 62;
+	};
+};
+
+#define C_MST_STS_NUM_REQ_OFFSET	0x00010018
+#define C_MST_STS_NUM_REQ	(C_MST_BASE + C_MST_STS_NUM_REQ_OFFSET)
+#define C_MST_STS_NUM_REQ_SIZE	0x00000008
+
+union c_mst_sts_num_req {
+	__u64 qw;
+	struct {
+		__u64 cnt   : 12;
+		__u64: 52;
+	};
+};
+
+#define C_MST_DBG_MST_TABLE_OFFSET(idx)	(0x00020000 + ((idx) * 64))
+#define C_MST_DBG_MST_TABLE_ENTRIES	2048
+#define C_MST_DBG_MST_TABLE(idx)	(C_MST_BASE + C_MST_DBG_MST_TABLE_OFFSET(idx))
+#define C_MST_DBG_MST_TABLE_SIZE	0x00020000
+
+union c_mst_dbg_mst_table {
+	__u64 qw[8];
+	struct {
+		__u64 cntr_pool_id           :  2;
+		__u64: 2;
+		__u64 rendezvous             :  1;
+		__u64: 3;
+		__u64 rendezvous_id          :  8;
+		__u64 vni                    : 16;
+		__u64 lpe_stat_1             : 16;
+		__u64 lpe_stat_2             : 16;
+		__u64 auto_unlinked          :  1;
+		__u64: 7;
+		__u64 dma_hdr_len            :  6;
+		__u64: 2;
+		__u64 event_ct_bytes         :  1;
+		__u64 event_ct_comm          :  1;
+		__u64 event_success_disable  :  1;
+		__u64 event_comm_disable     :  1;
+		__u64 use_once               :  1;
+		__u64 event_use_long_fmt     :  1;
+		__u64 event_start_at_base    :  1;
+		__u64 unrestricted_end_ro    :  1;
+		__u64 unrestricted_body_ro   :  1;
+		__u64 acid                   : 10;
+		__u64: 5;
+		__u64 ct_handle              : 11;
+		__u64: 1;
+		__u64 eq_handle              : 11;
+		__u64: 1;
+		__u64 portal_index           : 11;
+		__u64: 1;
+		__u64 ptl_list               :  2;
+		__u64: 2;
+		__u64 buffer_id              : 16;
+		__u64 initiator              : 32;
+		__u64 hdr_data;
+		__u64 match_bits;
+		__u64 mlength                : 32;
+		__u64 rlength                : 32;
+		__u64 remote_offset          : 56;
+		__u64 return_code            :  6;
+		__u64: 2;
+		__u64 start_addr             : 57;
+		__u64: 7;
+	};
+};
+
+#define C_MST_DBG_MATCH_DONE_OFFSET	0x00064100
+#define C_MST_DBG_MATCH_DONE	(C_MST_BASE + C_MST_DBG_MATCH_DONE_OFFSET)
+#define C_MST_DBG_MATCH_DONE_SIZE	0x00000008
+
+union c_mst_dbg_match_done {
+	__u64 qw;
+	struct {
+		__u64 mst_idx     : 11;
+		__u64: 5;
+		__u64 wr_en       :  1;
+		__u64: 3;
+		__u64 mst_idx_st  :  1;
+		__u64: 43;
+	};
+};
+
+#define C_OXE_CFG_CRNC_OFFSET	0x00000000
+#define C_OXE_CFG_CRNC	(C_OXE_BASE + C_OXE_CFG_CRNC_OFFSET)
+#define C_OXE_CFG_CRNC_SIZE	0x00000008
+
+union c_oxe_cfg_crnc {
+	__u64 qw;
+	struct {
+		__u64 csr_timeout   :  8;
+		__u64 mcast_id      : 10;
+		__u64: 1;
+		__u64 mcast_enable  :  1;
+		__u64 mcast_mask    : 10;
+		__u64: 34;
+	};
+};
+
+#define C_OXE_CFG_RT_OFFSET_OFFSET	0x00000020
+#define C_OXE_CFG_RT_OFFSET	(C_OXE_BASE + C_OXE_CFG_RT_OFFSET_OFFSET)
+#define C_OXE_CFG_RT_OFFSET_SIZE	0x00000008
+
+union c_oxe_cfg_rt_offset {
+	__u64 qw;
+	struct {
+		__u64 seconds  : 48;
+		__u64: 16;
+	};
+};
+
+#define C_OXE_MSC_SHADOW_ACTION_OFFSET	0x00000038
+#define C_OXE_MSC_SHADOW_ACTION	(C_OXE_BASE + C_OXE_MSC_SHADOW_ACTION_OFFSET)
+#define C_OXE_MSC_SHADOW_ACTION_SIZE	0x00000008
+#define C_OXE_MSC_SHADOW_OFFSET	0x00000040
+#define C_OXE_MSC_SHADOW	(C_OXE_BASE + C_OXE_MSC_SHADOW_OFFSET)
+#define C_OXE_MSC_SHADOW_SIZE	0x00000040
+
+union c_oxe_msc_shadow {
+	__u64 qw[8];
+};
+
+#define C_OXE_ERR_ELAPSED_TIME_OFFSET	0x00000100
+#define C_OXE_ERR_ELAPSED_TIME	(C_OXE_BASE + C_OXE_ERR_ELAPSED_TIME_OFFSET)
+#define C_OXE_ERR_ELAPSED_TIME_SIZE	0x00000008
+
+union c_oxe_err_elapsed_time {
+	__u64 qw;
+	struct {
+		__u64 nanoseconds  : 30;
+		__u64 seconds      : 34;
+	};
+};
+
+#define C_OXE_ERR_FLG_OFFSET	0x00000108
+#define C_OXE_ERR_FLG	(C_OXE_BASE + C_OXE_ERR_FLG_OFFSET)
+#define C_OXE_ERR_FLG_SIZE	0x00000008
+
+union c_oxe_err_flg {
+	__u64 qw;
+	struct {
+		__u64 sw_diag                  :  1;
+		__u64 crnc_ring_sync_error     :  1;
+		__u64 crnc_ring_ecc_sbe        :  1;
+		__u64 crnc_ring_ecc_mbe        :  1;
+		__u64 crnc_ring_cmd_unknown    :  1;
+		__u64 crnc_csr_cmd_unknown     :  1;
+		__u64 crnc_csr_cmd_incomplete  :  1;
+		__u64 crnc_buf_ecc_sbe         :  1;
+		__u64 crnc_buf_ecc_mbe         :  1;
+		__u64: 5;
+		__u64 spt_cdt_err              :  1;
+		__u64 smt_cdt_err              :  1;
+		__u64 cells_mem_cor            :  1;
+		__u64 pkl_mem_cor              :  1;
+		__u64 pct_sb_mcu_mem_cor       :  1;
+		__u64 pct_sb_sct_mem_cor       :  1;
+		__u64 dmu_mem_cor              :  1;
+		__u64 rec_mem_cor              :  1;
+		__u64 atreq_mem_cor            :  1;
+		__u64 atrsp_mem_cor            :  1;
+		__u64 tso_flit_cor             :  1;
+		__u64 sb_fifo_cor              :  1;
+		__u64 rarb_hdr_cor             :  1;
+		__u64 rarb_data_cor            :  1;
+		__u64 at_resp_bus_cor          :  1;
+		__u64 ixe_cmd_cor              :  1;
+		__u64 lpe_cmd_cor              :  1;
+		__u64 tou_cmd_cor              :  1;
+		__u64 cq_cmd_cor               :  1;
+		__u64 cells_mem_ucor           :  1;
+		__u64 pkl_mem_ucor             :  1;
+		__u64 pct_sb_mcu_mem_ucor      :  1;
+		__u64 pct_sb_sct_mem_ucor      :  1;
+		__u64 dmu_mem_ucor             :  1;
+		__u64 rec_mem_ucor             :  1;
+		__u64 atreq_mem_ucor           :  1;
+		__u64 atrsp_mem_ucor           :  1;
+		__u64 tso_flit_ucor            :  1;
+		__u64 sb_fifo_ucor             :  1;
+		__u64 rarb_hdr_ucor            :  1;
+		__u64 rarb_data_ucor           :  1;
+		__u64 at_resp_bus_ucor         :  1;
+		__u64 ixe_cmd_ucor             :  1;
+		__u64 lpe_cmd_ucor             :  1;
+		__u64 tou_cmd_ucor             :  1;
+		__u64 cq_cmd_ucor              :  1;
+		__u64 fifo_err                 :  1;
+		__u64 credit_uflw              :  1;
+		__u64 spt_ignore_err           :  1;
+		__u64 smt_ignore_err           :  1;
+		__u64 sct_ignore_err           :  1;
+		__u64 srb_ignore_err           :  1;
+		__u64 cmd_unexpected           :  1;
+		__u64 rarb_hw_err              :  1;
+		__u64 pcie_unsuccess_cmpl      :  1;
+		__u64 pcie_error_poisoned      :  1;
+		__u64 at_overrun_err           :  1;
+		__u64 mdr_pipe_ucor            :  1;
+		__u64 cell_xlate_parity_err    :  1;
+		__u64: 1;
+	};
+};
+
+#define C_OXE_ERR_FIRST_FLG_OFFSET	0x00000110
+#define C_OXE_ERR_FIRST_FLG	(C_OXE_BASE + C_OXE_ERR_FIRST_FLG_OFFSET)
+#define C_OXE_ERR_FIRST_FLG_SIZE	0x00000008
+#define C_OXE_ERR_FIRST_FLG_TS_OFFSET	0x00000118
+#define C_OXE_ERR_FIRST_FLG_TS	(C_OXE_BASE + C_OXE_ERR_FIRST_FLG_TS_OFFSET)
+#define C_OXE_ERR_FIRST_FLG_TS_SIZE	0x00000008
+#define C_OXE_ERR_CLR_OFFSET	0x00000120
+#define C_OXE_ERR_CLR	(C_OXE_BASE + C_OXE_ERR_CLR_OFFSET)
+#define C_OXE_ERR_CLR_SIZE	0x00000008
+#define C_OXE_ERR_IRQA_MSK_OFFSET	0x00000128
+#define C_OXE_ERR_IRQA_MSK	(C_OXE_BASE + C_OXE_ERR_IRQA_MSK_OFFSET)
+#define C_OXE_ERR_IRQA_MSK_SIZE	0x00000008
+#define C_OXE_ERR_IRQB_MSK_OFFSET	0x00000130
+#define C_OXE_ERR_IRQB_MSK	(C_OXE_BASE + C_OXE_ERR_IRQB_MSK_OFFSET)
+#define C_OXE_ERR_IRQB_MSK_SIZE	0x00000008
+#define C_OXE_ERR_INFO_MSK_OFFSET	0x00000140
+#define C_OXE_ERR_INFO_MSK	(C_OXE_BASE + C_OXE_ERR_INFO_MSK_OFFSET)
+#define C_OXE_ERR_INFO_MSK_SIZE	0x00000008
+#define C_OXE_ERR_INFO_MEM_OFFSET	0x00000180
+#define C_OXE_ERR_INFO_MEM	(C_OXE_BASE + C_OXE_ERR_INFO_MEM_OFFSET)
+#define C_OXE_ERR_INFO_MEM_SIZE	0x00000008
+
+union c_oxe_err_info_mem {
+	__u64 qw;
+	struct {
+		__u64 cor_syndrome       : 11;
+		__u64: 1;
+		__u64 cor_address        : 12;
+		__u64 cor_mem_id         :  5;
+		__u64: 2;
+		__u64 cor_csr_detected   :  1;
+		__u64 ucor_syndrome      : 11;
+		__u64: 1;
+		__u64 ucor_address       : 12;
+		__u64 ucor_mem_id        :  5;
+		__u64: 2;
+		__u64 ucor_csr_detected  :  1;
+	};
+};
+
+#define C_OXE_ERR_INFO_FIFO_ERR_OFFSET	0x00000188
+#define C_OXE_ERR_INFO_FIFO_ERR	(C_OXE_BASE + C_OXE_ERR_INFO_FIFO_ERR_OFFSET)
+#define C_OXE_ERR_INFO_FIFO_ERR_SIZE	0x00000008
+
+union c_oxe_err_info_fifo_err {
+	__u64 qw;
+	struct {
+		__u64 overrun   :  1;
+		__u64 underrun  :  1;
+		__u64: 6;
+		__u64 fifo_id   :  4;
+		__u64: 52;
+	};
+};
+
+#define C_OXE_ERR_INFO_CC_OFFSET	0x00000190
+#define C_OXE_ERR_INFO_CC	(C_OXE_BASE + C_OXE_ERR_INFO_CC_OFFSET)
+#define C_OXE_ERR_INFO_CC_SIZE	0x00000008
+
+union c_oxe_err_info_cc {
+	__u64 qw;
+	struct {
+		__u64 cc_id   :  5;
+		__u64: 3;
+		__u64 sub_id  :  4;
+		__u64: 52;
+	};
+};
+
+#define C_OXE_ERR_INFO_PCIE_UC_OFFSET	0x00000198
+#define C_OXE_ERR_INFO_PCIE_UC	(C_OXE_BASE + C_OXE_ERR_INFO_PCIE_UC_OFFSET)
+#define C_OXE_ERR_INFO_PCIE_UC_SIZE	0x00000008
+
+union c_oxe_err_info_pcie_uc {
+	__u64 qw;
+	struct {
+		__u64 pcie_tag     :  9;
+		__u64: 3;
+		__u64 cmpl_status  :  3;
+		__u64: 49;
+	};
+};
+
+#define C_OXE_ERR_INFO_PCIE_EP_OFFSET	0x000001a0
+#define C_OXE_ERR_INFO_PCIE_EP	(C_OXE_BASE + C_OXE_ERR_INFO_PCIE_EP_OFFSET)
+#define C_OXE_ERR_INFO_PCIE_EP_SIZE	0x00000008
+
+union c_oxe_err_info_pcie_ep {
+	__u64 qw;
+	struct {
+		__u64 pcie_tag  :  9;
+		__u64: 55;
+	};
+};
+
+#define C_OXE_ERR_INFO_RARB_OFFSET	0x000001a8
+#define C_OXE_ERR_INFO_RARB	(C_OXE_BASE + C_OXE_ERR_INFO_RARB_OFFSET)
+#define C_OXE_ERR_INFO_RARB_SIZE	0x00000008
+
+union c_oxe_err_info_rarb {
+	__u64 qw;
+	struct {
+		__u64 hdr_ucor               :  1;
+		__u64 data_ucor              :  1;
+		__u64 bad_vld                :  1;
+		__u64 bad_size               :  1;
+		__u64 bad_cmd                :  1;
+		__u64 unexpected_cmpl_tag    :  1;
+		__u64 cmpl_tag_out_of_range  :  1;
+		__u64 pcie_tag               :  9;
+		__u64: 48;
+	};
+};
+
+#define C_OXE_ERR_INFO_UNEXPCTD_OFFSET	0x000001b0
+#define C_OXE_ERR_INFO_UNEXPCTD	(C_OXE_BASE + C_OXE_ERR_INFO_UNEXPCTD_OFFSET)
+#define C_OXE_ERR_INFO_UNEXPCTD_SIZE	0x00000008
+
+union c_oxe_err_info_unexpctd {
+	__u64 qw;
+	struct {
+		__u64 mcu_unexpc_cmd  :  7;
+		__u64: 1;
+		__u64 ixe_unexp_cmd   :  1;
+		__u64 lpe_unexp_cmd   :  1;
+		__u64 tou_unexp_cmd   :  1;
+		__u64 cq_unexp_cmd    :  1;
+		__u64: 52;
+	};
+};
+
+#define C_OXE_ERR_INFO_CELL_XLATE_OFFSET	0x000001b8
+#define C_OXE_ERR_INFO_CELL_XLATE	(C_OXE_BASE + C_OXE_ERR_INFO_CELL_XLATE_OFFSET)
+#define C_OXE_ERR_INFO_CELL_XLATE_SIZE	0x00000008
+
+union c_oxe_err_info_cell_xlate {
+	__u64 qw;
+	struct {
+		__u64 free_list_perr   :  1;
+		__u64 vptr_table_perr  :  1;
+		__u64 tt1_perr         :  1;
+		__u64 tt2_perr         :  1;
+		__u64 tt3_perr         :  1;
+		__u64: 59;
+	};
+};
+
+#define C_OXE_ERR_INFO_IGNORE_ERR_OFFSET	0x000001e0
+#define C_OXE_ERR_INFO_IGNORE_ERR	(C_OXE_BASE + C_OXE_ERR_INFO_IGNORE_ERR_OFFSET)
+#define C_OXE_ERR_INFO_IGNORE_ERR_SIZE	0x00000008
+
+union c_oxe_err_info_ignore_err {
+	__u64 qw;
+	struct {
+		__u64 spt_err  :  1;
+		__u64 smt_err  :  1;
+		__u64 sct_err  :  1;
+		__u64 srb_err  :  1;
+		__u64 bc       :  4;
+		__u64 mcu_num  :  7;
+		__u64: 49;
+	};
+};
+
+#define C_OXE_CFG_COMMON_OFFSET	0x00000400
+#define C_OXE_CFG_COMMON	(C_OXE_BASE + C_OXE_CFG_COMMON_OFFSET)
+#define C_OXE_CFG_COMMON_SIZE	0x00000008
+
+union c_oxe_cfg_common {
+	__u64 qw;
+	struct {
+		__u64 occ_bin0_sz    : 10;
+		__u64 occ_bin1_sz    : 10;
+		__u64 occ_bin2_sz    : 10;
+		__u64 occ_bin3_sz    : 10;
+		__u64 ioi_enable     :  1;
+		__u64 mcu_meas_unit  :  2;
+		__u64: 21;
+	};
+};
+
+#define C_OXE_CFG_FAB_PARAM_OFFSET	0x00000410
+#define C_OXE_CFG_FAB_PARAM	(C_OXE_BASE + C_OXE_CFG_FAB_PARAM_OFFSET)
+#define C_OXE_CFG_FAB_PARAM_SIZE	0x00000008
+
+union c_oxe_cfg_fab_param {
+	__u64 qw;
+	struct {
+		__u64 ver              :  4;
+		__u64 req_32b_enabled  :  1;
+		__u64 rsp_32b_enabled  :  1;
+		__u64 req_40b_enabled  :  1;
+		__u64 rsp_40b_enabled  :  1;
+		__u64 ttl              :  8;
+		__u64 protocol         :  8;
+		__u64 ecn_enable       :  8;
+		__u64 min_req_size     :  6;
+		__u64: 2;
+		__u64 min_rsp_size     :  6;
+		__u64: 18;
+	};
+};
+
+#define C_OXE_CFG_FAB_SFA_OFFSET	0x00000418
+#define C_OXE_CFG_FAB_SFA	(C_OXE_BASE + C_OXE_CFG_FAB_SFA_OFFSET)
+#define C_OXE_CFG_FAB_SFA_SIZE	0x00000008
+
+union c_oxe_cfg_fab_sfa {
+	__u64 qw;
+	struct {
+		__u64 nid   : 20;
+		__u64: 44;
+	};
+};
+
+#define C_OXE_CFG_DUMMY_ADDR_OFFSET	0x00000420
+#define C_OXE_CFG_DUMMY_ADDR	(C_OXE_BASE + C_OXE_CFG_DUMMY_ADDR_OFFSET)
+#define C_OXE_CFG_DUMMY_ADDR_SIZE	0x00000008
+
+union c_oxe_cfg_dummy_addr {
+	__u64 qw;
+	struct {
+		__u64 ac       : 10;
+		__u64: 2;
+		__u64 subaddr  : 45;
+		__u64: 7;
+	};
+};
+
+#define C_OXE_CFG_PAUSE_QUANTA_OFFSET	0x00000438
+#define C_OXE_CFG_PAUSE_QUANTA	(C_OXE_BASE + C_OXE_CFG_PAUSE_QUANTA_OFFSET)
+#define C_OXE_CFG_PAUSE_QUANTA_SIZE	0x00000008
+
+union c_oxe_cfg_pause_quanta {
+	__u64 qw;
+	struct {
+		__u64 sub_value   : 24;
+		__u64 sub_period  :  8;
+		__u64: 32;
+	};
+};
+
+#define C_OXE_CFG_FGFC_OFFSET	0x00000440
+#define C_OXE_CFG_FGFC	(C_OXE_BASE + C_OXE_CFG_FGFC_OFFSET)
+#define C_OXE_CFG_FGFC_SIZE	0x00000008
+
+union c_oxe_cfg_fgfc {
+	__u64 qw;
+	struct {
+		__u64 extra_bytes  :  4;
+		__u64 round_pos    :  4;
+		__u64 enable       :  1;
+		__u64: 7;
+		__u64 cdt_adj      : 14;
+		__u64: 2;
+		__u64 cdt_limit    : 24;
+		__u64: 8;
+	};
+};
+
+#define C_OXE_CFG_PCT_CDT_OFFSET	0x00000448
+#define C_OXE_CFG_PCT_CDT	(C_OXE_BASE + C_OXE_CFG_PCT_CDT_OFFSET)
+#define C_OXE_CFG_PCT_CDT_SIZE	0x00000008
+
+union c_oxe_cfg_pct_cdt {
+	__u64 qw;
+	struct {
+		__u64 spt_cdt_limit  : 11;
+		__u64: 5;
+		__u64 smt_cdt_limit  :  9;
+		__u64: 7;
+		__u64 sct_cdt_limit  : 13;
+		__u64: 3;
+		__u64 srb_cdt_limit  : 12;
+		__u64: 4;
+	};
+};
+
+#define C_OXE_CFG_BUF_BC_PARAM_OFFSET(idx)	(0x00000500 + ((idx) * 8))
+#define C_OXE_CFG_BUF_BC_PARAM_ENTRIES	10
+#define C_OXE_CFG_BUF_BC_PARAM(idx)	(C_OXE_BASE + C_OXE_CFG_BUF_BC_PARAM_OFFSET(idx))
+#define C_OXE_CFG_BUF_BC_PARAM_SIZE	0x00000050
+
+union c_oxe_cfg_buf_bc_param {
+	__u64 qw;
+	struct {
+		__u64 bc_reserv_buf_cdt  : 11;
+		__u64: 5;
+		__u64 bc_max_mtu         :  8;
+		__u64: 40;
+	};
+};
+
+#define C_OXE_CFG_PCT_BC_CDT_OFFSET(idx)	(0x00000600 + ((idx) * 8))
+#define C_OXE_CFG_PCT_BC_CDT_ENTRIES	10
+#define C_OXE_CFG_PCT_BC_CDT(idx)	(C_OXE_BASE + C_OXE_CFG_PCT_BC_CDT_OFFSET(idx))
+#define C_OXE_CFG_PCT_BC_CDT_SIZE	0x00000050
+
+union c_oxe_cfg_pct_bc_cdt {
+	__u64 qw;
+	struct {
+		__u64 spt_cdt_rsvd  : 11;
+		__u64: 5;
+		__u64 smt_cdt_rsvd  :  9;
+		__u64: 7;
+		__u64 sct_cdt_rsvd  : 13;
+		__u64: 3;
+		__u64 srb_cdt_rsvd  : 12;
+		__u64 ignore_spt    :  1;
+		__u64 ignore_smt    :  1;
+		__u64 ignore_sct    :  1;
+		__u64 ignore_srb    :  1;
+	};
+};
+
+#define C_OXE_CFG_BUF_SH_CDT_OFFSET(idx)	(0x00000700 + ((idx) * 8))
+#define C_OXE_CFG_BUF_SH_CDT_ENTRIES	10
+#define C_OXE_CFG_BUF_SH_CDT(idx)	(C_OXE_BASE + C_OXE_CFG_BUF_SH_CDT_OFFSET(idx))
+#define C_OXE_CFG_BUF_SH_CDT_SIZE	0x00000050
+
+union c_oxe_cfg_buf_sh_cdt {
+	__u64 qw;
+	struct {
+		__u64 buf_sh_cdt         : 11;
+		__u64: 5;
+		__u64 buf_sh_bc_cdt      : 11;
+		__u64: 5;
+		__u64 buf_sh_bc_idc_cdt  : 11;
+		__u64: 21;
+	};
+};
+
+#define C_OXE_CFG_MCU_PARAM_OFFSET(idx)	(0x00001000 + ((idx) * 8))
+#define C_OXE_CFG_MCU_PARAM_ENTRIES	96
+#define C_OXE_CFG_MCU_PARAM(idx)	(C_OXE_BASE + C_OXE_CFG_MCU_PARAM_OFFSET(idx))
+#define C_OXE_CFG_MCU_PARAM_SIZE	0x00000300
+
+union c_oxe_cfg_mcu_param {
+	__u64 qw;
+	struct {
+		__u64 bc_map         :  4;
+		__u64 tsc_map        :  4;
+		__u64 wdrr_out_sel   :  2;
+		__u64 wdrr_in_sel    :  2;
+		__u64 stall_cnt_en0  :  1;
+		__u64 stall_cnt_en1  :  1;
+		__u64 pcp_map        :  3;
+		__u64 limit_sel      :  2;
+		__u64: 45;
+	};
+};
+
+#define C_OXE_CFG_MCU_PRIORITY_LIMIT_OFFSET(idx)	(0x00001400 + ((idx) * 8))
+#define C_OXE_CFG_MCU_PRIORITY_LIMIT_ENTRIES	96
+#define C_OXE_CFG_MCU_PRIORITY_LIMIT(idx)	(C_OXE_BASE + C_OXE_CFG_MCU_PRIORITY_LIMIT_OFFSET(idx))
+#define C_OXE_CFG_MCU_PRIORITY_LIMIT_SIZE	0x00000300
+
+union c_oxe_cfg_mcu_priority_limit {
+	__u64 qw;
+	struct {
+		__u64 occ_blimit  : 11;
+		__u64: 5;
+		__u64 occ_climit  : 11;
+		__u64: 37;
+	};
+};
+
+#define C_OXE_CFG_ARB_CONFIG_OFFSET	0x00001808
+#define C_OXE_CFG_ARB_CONFIG	(C_OXE_BASE + C_OXE_CFG_ARB_CONFIG_OFFSET)
+#define C_OXE_CFG_ARB_CONFIG_SIZE	0x00000008
+
+union c_oxe_cfg_arb_config {
+	__u64 qw;
+	struct {
+		__u64 fill_rate    : 10;
+		__u64: 2;
+		__u64 mfs_out_sel  :  2;
+		__u64 mfs_in_sel   :  2;
+		__u64: 48;
+	};
+};
+
+#define C_OXE_CFG_ARB_MFS_OUT_OFFSET	0x00001810
+#define C_OXE_CFG_ARB_MFS_OUT	(C_OXE_BASE + C_OXE_CFG_ARB_MFS_OUT_OFFSET)
+#define C_OXE_CFG_ARB_MFS_OUT_SIZE	0x00000008
+
+union c_oxe_cfg_arb_mfs_out {
+	__u64 qw;
+	struct {
+		__u64 mfs0  :  9;
+		__u64: 3;
+		__u64 mfs1  :  9;
+		__u64: 3;
+		__u64 mfs2  :  9;
+		__u64: 3;
+		__u64 mfs3  :  9;
+		__u64: 19;
+	};
+};
+
+#define C_OXE_CFG_ARB_MFS_IN_OFFSET	0x00001818
+#define C_OXE_CFG_ARB_MFS_IN	(C_OXE_BASE + C_OXE_CFG_ARB_MFS_IN_OFFSET)
+#define C_OXE_CFG_ARB_MFS_IN_SIZE	0x00000008
+
+union c_oxe_cfg_arb_mfs_in {
+	__u64 qw;
+	struct {
+		__u64 mfs0  :  9;
+		__u64: 3;
+		__u64 mfs1  :  9;
+		__u64: 3;
+		__u64 mfs2  :  9;
+		__u64: 3;
+		__u64 mfs3  :  9;
+		__u64: 19;
+	};
+};
+
+#define C_OXE_CFG_ARB_DRR_OUT_OFFSET	0x00001820
+#define C_OXE_CFG_ARB_DRR_OUT	(C_OXE_BASE + C_OXE_CFG_ARB_DRR_OUT_OFFSET)
+#define C_OXE_CFG_ARB_DRR_OUT_SIZE	0x00000008
+
+union c_oxe_cfg_arb_drr_out {
+	__u64 qw;
+	struct {
+		__u64 quanta_val0  : 12;
+		__u64 quanta_val1  : 12;
+		__u64 quanta_val2  : 12;
+		__u64 quanta_val3  : 12;
+		__u64: 16;
+	};
+};
+
+#define C_OXE_CFG_ARB_DRR_IN_OFFSET	0x00001828
+#define C_OXE_CFG_ARB_DRR_IN	(C_OXE_BASE + C_OXE_CFG_ARB_DRR_IN_OFFSET)
+#define C_OXE_CFG_ARB_DRR_IN_SIZE	0x00000008
+
+union c_oxe_cfg_arb_drr_in {
+	__u64 qw;
+	struct {
+		__u64 quanta_val0  : 12;
+		__u64 quanta_val1  : 12;
+		__u64 quanta_val2  : 12;
+		__u64 quanta_val3  : 12;
+		__u64: 16;
+	};
+};
+
+#define C_OXE_CFG_ARB_HEAD_OUT_C_OFFSET	0x00001830
+#define C_OXE_CFG_ARB_HEAD_OUT_C	(C_OXE_BASE + C_OXE_CFG_ARB_HEAD_OUT_C_OFFSET)
+#define C_OXE_CFG_ARB_HEAD_OUT_C_SIZE	0x00000008
+
+union c_oxe_cfg_arb_head_out_c {
+	__u64 qw;
+	struct {
+		__u64 fill_qty  : 11;
+		__u64: 1;
+		__u64 limit     : 18;
+		__u64 enable    :  1;
+		__u64: 33;
+	};
+};
+
+#define C_OXE_CFG_ARB_HEAD_IN_C_OFFSET	0x00001838
+#define C_OXE_CFG_ARB_HEAD_IN_C	(C_OXE_BASE + C_OXE_CFG_ARB_HEAD_IN_C_OFFSET)
+#define C_OXE_CFG_ARB_HEAD_IN_C_SIZE	0x00000008
+
+union c_oxe_cfg_arb_head_in_c {
+	__u64 qw;
+	struct {
+		__u64 fill_qty  : 11;
+		__u64: 1;
+		__u64 limit     : 18;
+		__u64 enable    :  1;
+		__u64: 33;
+	};
+};
+
+#define C_OXE_CFG_ARB_PCP_MASK_OFFSET(idx)	(0x00001840 + ((idx) * 8))
+#define C_OXE_CFG_ARB_PCP_MASK_ENTRIES	8
+#define C_OXE_CFG_ARB_PCP_MASK(idx)	(C_OXE_BASE + C_OXE_CFG_ARB_PCP_MASK_OFFSET(idx))
+#define C_OXE_CFG_ARB_PCP_MASK_SIZE	0x00000040
+
+union c_oxe_cfg_arb_pcp_mask {
+	__u64 qw;
+	struct {
+		__u64 tsc_mask  : 10;
+		__u64: 54;
+	};
+};
+
+#define C_OXE_CFG_OUTSTANDING_LIMIT_OFFSET(idx)	(0x00001880 + ((idx) * 8))
+#define C_OXE_CFG_OUTSTANDING_LIMIT_ENTRIES	4
+#define C_OXE_CFG_OUTSTANDING_LIMIT(idx)	(C_OXE_BASE + C_OXE_CFG_OUTSTANDING_LIMIT_OFFSET(idx))
+#define C_OXE_CFG_OUTSTANDING_LIMIT_SIZE	0x00000020
+
+union c_oxe_cfg_outstanding_limit {
+	__u64 qw;
+	struct {
+		__u64 put_limit        : 11;
+		__u64 get_limit        : 11;
+		__u64 ioi_ord_limit    : 11;
+		__u64 ioi_unord_limit  : 13;
+		__u64: 18;
+	};
+};
+
+#define C_OXE_CFG_ARB_LEAF_OFFSET(idx)	(0x000018a0 + ((idx) * 8))
+#define C_OXE_CFG_ARB_LEAF_ENTRIES	10
+#define C_OXE_CFG_ARB_LEAF(idx)	(C_OXE_BASE + C_OXE_CFG_ARB_LEAF_OFFSET(idx))
+#define C_OXE_CFG_ARB_LEAF_SIZE	0x00000050
+
+union c_oxe_cfg_arb_leaf {
+	__u64 qw;
+	struct {
+		__u64 pri          :  3;
+		__u64: 1;
+		__u64 parent       :  3;
+		__u64: 1;
+		__u64 mfs_out_sel  :  2;
+		__u64 mfs_in_sel   :  2;
+		__u64 enable_in    :  1;
+		__u64: 51;
+	};
+};
+
+#define C_OXE_CFG_ARB_LEAF_OUT_A_OFFSET(idx)	(0x00001900 + ((idx) * 8))
+#define C_OXE_CFG_ARB_LEAF_OUT_A_ENTRIES	10
+#define C_OXE_CFG_ARB_LEAF_OUT_A(idx)	(C_OXE_BASE + C_OXE_CFG_ARB_LEAF_OUT_A_OFFSET(idx))
+#define C_OXE_CFG_ARB_LEAF_OUT_A_SIZE	0x00000050
+
+union c_oxe_cfg_arb_leaf_out_a {
+	__u64 qw;
+	struct {
+		__u64 fill_qty  : 11;
+		__u64: 1;
+		__u64 limit     : 18;
+		__u64: 34;
+	};
+};
+
+#define C_OXE_CFG_ARB_LEAF_OUT_C_OFFSET(idx)	(0x00001980 + ((idx) * 8))
+#define C_OXE_CFG_ARB_LEAF_OUT_C_ENTRIES	10
+#define C_OXE_CFG_ARB_LEAF_OUT_C(idx)	(C_OXE_BASE + C_OXE_CFG_ARB_LEAF_OUT_C_OFFSET(idx))
+#define C_OXE_CFG_ARB_LEAF_OUT_C_SIZE	0x00000050
+
+union c_oxe_cfg_arb_leaf_out_c {
+	__u64 qw;
+	struct {
+		__u64 fill_qty  : 11;
+		__u64: 1;
+		__u64 limit     : 18;
+		__u64 enable    :  1;
+		__u64: 33;
+	};
+};
+
+#define C_OXE_CFG_ARB_LEAF_IN_A_OFFSET(idx)	(0x00001a00 + ((idx) * 8))
+#define C_OXE_CFG_ARB_LEAF_IN_A_ENTRIES	10
+#define C_OXE_CFG_ARB_LEAF_IN_A(idx)	(C_OXE_BASE + C_OXE_CFG_ARB_LEAF_IN_A_OFFSET(idx))
+#define C_OXE_CFG_ARB_LEAF_IN_A_SIZE	0x00000050
+
+union c_oxe_cfg_arb_leaf_in_a {
+	__u64 qw;
+	struct {
+		__u64 fill_qty  : 11;
+		__u64: 1;
+		__u64 limit     : 18;
+		__u64: 34;
+	};
+};
+
+#define C_OXE_CFG_ARB_LEAF_IN_C_OFFSET(idx)	(0x00001a80 + ((idx) * 8))
+#define C_OXE_CFG_ARB_LEAF_IN_C_ENTRIES	10
+#define C_OXE_CFG_ARB_LEAF_IN_C(idx)	(C_OXE_BASE + C_OXE_CFG_ARB_LEAF_IN_C_OFFSET(idx))
+#define C_OXE_CFG_ARB_LEAF_IN_C_SIZE	0x00000050
+
+union c_oxe_cfg_arb_leaf_in_c {
+	__u64 qw;
+	struct {
+		__u64 fill_qty  : 11;
+		__u64: 1;
+		__u64 limit     : 18;
+		__u64 enable    :  1;
+		__u64: 33;
+	};
+};
+
+#define C_OXE_CFG_ARB_BRANCH_OFFSET(idx)	(0x00001b00 + ((idx) * 8))
+#define C_OXE_CFG_ARB_BRANCH_ENTRIES	5
+#define C_OXE_CFG_ARB_BRANCH(idx)	(C_OXE_BASE + C_OXE_CFG_ARB_BRANCH_OFFSET(idx))
+#define C_OXE_CFG_ARB_BRANCH_SIZE	0x00000028
+
+union c_oxe_cfg_arb_branch {
+	__u64 qw;
+	struct {
+		__u64 pri          :  3;
+		__u64: 1;
+		__u64 mfs_out_sel  :  2;
+		__u64 mfs_in_sel   :  2;
+		__u64: 56;
+	};
+};
+
+#define C_OXE_CFG_ARB_BRANCH_OUT_A_OFFSET(idx)	(0x00001b40 + ((idx) * 8))
+#define C_OXE_CFG_ARB_BRANCH_OUT_A_ENTRIES	5
+#define C_OXE_CFG_ARB_BRANCH_OUT_A(idx)	(C_OXE_BASE + C_OXE_CFG_ARB_BRANCH_OUT_A_OFFSET(idx))
+#define C_OXE_CFG_ARB_BRANCH_OUT_A_SIZE	0x00000028
+
+union c_oxe_cfg_arb_branch_out_a {
+	__u64 qw;
+	struct {
+		__u64 fill_qty  : 11;
+		__u64: 1;
+		__u64 limit     : 18;
+		__u64: 34;
+	};
+};
+
+#define C_OXE_CFG_ARB_BRANCH_OUT_C_OFFSET(idx)	(0x00001b80 + ((idx) * 8))
+#define C_OXE_CFG_ARB_BRANCH_OUT_C_ENTRIES	5
+#define C_OXE_CFG_ARB_BRANCH_OUT_C(idx)	(C_OXE_BASE + C_OXE_CFG_ARB_BRANCH_OUT_C_OFFSET(idx))
+#define C_OXE_CFG_ARB_BRANCH_OUT_C_SIZE	0x00000028
+
+union c_oxe_cfg_arb_branch_out_c {
+	__u64 qw;
+	struct {
+		__u64 fill_qty  : 11;
+		__u64: 1;
+		__u64 limit     : 18;
+		__u64 enable    :  1;
+		__u64: 33;
+	};
+};
+
+#define C_OXE_CFG_ARB_BRANCH_IN_A_OFFSET(idx)	(0x00001bc0 + ((idx) * 8))
+#define C_OXE_CFG_ARB_BRANCH_IN_A_ENTRIES	5
+#define C_OXE_CFG_ARB_BRANCH_IN_A(idx)	(C_OXE_BASE + C_OXE_CFG_ARB_BRANCH_IN_A_OFFSET(idx))
+#define C_OXE_CFG_ARB_BRANCH_IN_A_SIZE	0x00000028
+
+union c_oxe_cfg_arb_branch_in_a {
+	__u64 qw;
+	struct {
+		__u64 fill_qty  : 11;
+		__u64: 1;
+		__u64 limit     : 18;
+		__u64: 34;
+	};
+};
+
+#define C_OXE_CFG_ARB_BRANCH_IN_C_OFFSET(idx)	(0x00001c00 + ((idx) * 8))
+#define C_OXE_CFG_ARB_BRANCH_IN_C_ENTRIES	5
+#define C_OXE_CFG_ARB_BRANCH_IN_C(idx)	(C_OXE_BASE + C_OXE_CFG_ARB_BRANCH_IN_C_OFFSET(idx))
+#define C_OXE_CFG_ARB_BRANCH_IN_C_SIZE	0x00000028
+
+union c_oxe_cfg_arb_branch_in_c {
+	__u64 qw;
+	struct {
+		__u64 fill_qty  : 11;
+		__u64: 1;
+		__u64 limit     : 18;
+		__u64 enable    :  1;
+		__u64: 33;
+	};
+};
+
+#define C_OXE_CFG_FGFC_CNT_OFFSET(idx)	(0x00001c40 + ((idx) * 8))
+#define C_OXE_CFG_FGFC_CNT_ENTRIES	4
+#define C_OXE_CFG_FGFC_CNT(idx)	(C_OXE_BASE + C_OXE_CFG_FGFC_CNT_OFFSET(idx))
+#define C_OXE_CFG_FGFC_CNT_SIZE	0x00000020
+
+union c_oxe_cfg_fgfc_cnt {
+	__u64 qw;
+	struct {
+		__u64 vni_match  : 16;
+		__u64 vni_mask   : 16;
+		__u64: 32;
+	};
+};
+
+#define C_OXE_STS_COMMON_OFFSET	0x00002000
+#define C_OXE_STS_COMMON	(C_OXE_BASE + C_OXE_STS_COMMON_OFFSET)
+#define C_OXE_STS_COMMON_SIZE	0x00000008
+
+union c_oxe_sts_common {
+	__u64 qw;
+	struct {
+		__u64 init_done  :  1;
+		__u64: 63;
+	};
+};
+
+#define C_PARBS_CFG_CRNC_OFFSET	0x00000000
+#define C_PARBS_CFG_CRNC	(C_PARBS_BASE + C_PARBS_CFG_CRNC_OFFSET)
+#define C_PARBS_CFG_CRNC_SIZE	0x00000008
+
+union c_parbs_cfg_crnc {
+	__u64 qw;
+	struct {
+		__u64 csr_timeout   :  8;
+		__u64 mcast_id      : 10;
+		__u64: 1;
+		__u64 mcast_enable  :  1;
+		__u64 mcast_mask    : 10;
+		__u64: 34;
+	};
+};
+
+#define C_PARBS_CFG_RT_OFFSET_OFFSET	0x00000020
+#define C_PARBS_CFG_RT_OFFSET	(C_PARBS_BASE + C_PARBS_CFG_RT_OFFSET_OFFSET)
+#define C_PARBS_CFG_RT_OFFSET_SIZE	0x00000008
+
+union c_parbs_cfg_rt_offset {
+	__u64 qw;
+	struct {
+		__u64 seconds  : 48;
+		__u64: 16;
+	};
+};
+
+#define C_PARBS_ERR_ELAPSED_TIME_OFFSET	0x00000100
+#define C_PARBS_ERR_ELAPSED_TIME	(C_PARBS_BASE + C_PARBS_ERR_ELAPSED_TIME_OFFSET)
+#define C_PARBS_ERR_ELAPSED_TIME_SIZE	0x00000008
+
+union c_parbs_err_elapsed_time {
+	__u64 qw;
+	struct {
+		__u64 nanoseconds  : 30;
+		__u64 seconds      : 34;
+	};
+};
+
+#define C_PARBS_ERR_FLG_OFFSET	0x00000108
+#define C_PARBS_ERR_FLG	(C_PARBS_BASE + C_PARBS_ERR_FLG_OFFSET)
+#define C_PARBS_ERR_FLG_SIZE	0x00000008
+
+union c_parbs_err_flg {
+	__u64 qw;
+	struct {
+		__u64 sw_diag                   :  1;
+		__u64 crnc_ring_sync_error      :  1;
+		__u64 crnc_ring_ecc_sbe         :  1;
+		__u64 crnc_ring_ecc_mbe         :  1;
+		__u64 crnc_ring_cmd_unknown     :  1;
+		__u64 crnc_csr_cmd_unknown      :  1;
+		__u64 crnc_csr_cmd_incomplete   :  1;
+		__u64 crnc_buf_ecc_sbe          :  1;
+		__u64 crnc_buf_ecc_mbe          :  1;
+		__u64: 7;
+		__u64 cq_tarb_hdr_cor           :  1;
+		__u64 cq_tarb_hdr_ucor          :  1;
+		__u64 cq_tarb_data_cor          :  1;
+		__u64 cq_tarb_data_ucor         :  1;
+		__u64 ee_tarb_hdr_cor           :  1;
+		__u64 ee_tarb_hdr_ucor          :  1;
+		__u64 ee_tarb_data_cor          :  1;
+		__u64 ee_tarb_data_ucor         :  1;
+		__u64 ixe_tarb_hdr_cor          :  1;
+		__u64 ixe_tarb_hdr_ucor         :  1;
+		__u64 ixe_tarb_data_cor         :  1;
+		__u64 ixe_tarb_data_ucor        :  1;
+		__u64 oxe_tarb_hdr_cor          :  1;
+		__u64 oxe_tarb_hdr_ucor         :  1;
+		__u64 atu_tarb_hdr_cor          :  1;
+		__u64 atu_tarb_hdr_ucor         :  1;
+		__u64 atu_tarb_data_cor         :  1;
+		__u64 atu_tarb_data_ucor        :  1;
+		__u64 tarb_pi_hdr_cor           :  1;
+		__u64 tarb_pi_hdr_ucor          :  1;
+		__u64 tarb_pi_data_cor          :  1;
+		__u64 tarb_pi_data_ucor         :  1;
+		__u64 cq_p_fifo_overrun         :  1;
+		__u64 cq_p_fifo_underrun        :  1;
+		__u64 cq_np_fifo_overrun        :  1;
+		__u64 cq_np_fifo_underrun       :  1;
+		__u64 ee_p_fifo_overrun         :  1;
+		__u64 ee_p_fifo_underrun        :  1;
+		__u64 ixe_p_fifo_overrun        :  1;
+		__u64 ixe_p_fifo_underrun       :  1;
+		__u64 ixe_np_fifo_overrun       :  1;
+		__u64 ixe_np_fifo_underrun      :  1;
+		__u64 oxe_np_fifo_overrun       :  1;
+		__u64 oxe_np_fifo_underrun      :  1;
+		__u64 atu_p_fifo_overrun        :  1;
+		__u64 atu_p_fifo_underrun       :  1;
+		__u64 atu_np_fifo_overrun       :  1;
+		__u64 atu_np_fifo_underrun      :  1;
+		__u64 ord_p_fifo_overrun        :  1;
+		__u64 ord_p_fifo_underrun       :  1;
+		__u64 ord_np_fifo_overrun       :  1;
+		__u64 ord_np_fifo_underrun      :  1;
+		__u64 ord_np_cnt_overrun        :  1;
+		__u64 ord_np_cnt_underrun       :  1;
+		__u64 tarb_pi_p_cdt_underflow   :  1;
+		__u64 tarb_pi_np_cdt_underflow  :  1;
+		__u64: 2;
+	};
+};
+
+#define C_PARBS_ERR_FIRST_FLG_OFFSET	0x00000110
+#define C_PARBS_ERR_FIRST_FLG	(C_PARBS_BASE + C_PARBS_ERR_FIRST_FLG_OFFSET)
+#define C_PARBS_ERR_FIRST_FLG_SIZE	0x00000008
+#define C_PARBS_ERR_FIRST_FLG_TS_OFFSET	0x00000118
+#define C_PARBS_ERR_FIRST_FLG_TS	(C_PARBS_BASE + C_PARBS_ERR_FIRST_FLG_TS_OFFSET)
+#define C_PARBS_ERR_FIRST_FLG_TS_SIZE	0x00000008
+#define C_PARBS_ERR_CLR_OFFSET	0x00000120
+#define C_PARBS_ERR_CLR	(C_PARBS_BASE + C_PARBS_ERR_CLR_OFFSET)
+#define C_PARBS_ERR_CLR_SIZE	0x00000008
+#define C_PARBS_ERR_IRQA_MSK_OFFSET	0x00000128
+#define C_PARBS_ERR_IRQA_MSK	(C_PARBS_BASE + C_PARBS_ERR_IRQA_MSK_OFFSET)
+#define C_PARBS_ERR_IRQA_MSK_SIZE	0x00000008
+#define C_PARBS_ERR_IRQB_MSK_OFFSET	0x00000130
+#define C_PARBS_ERR_IRQB_MSK	(C_PARBS_BASE + C_PARBS_ERR_IRQB_MSK_OFFSET)
+#define C_PARBS_ERR_IRQB_MSK_SIZE	0x00000008
+#define C_PARBS_ERR_INFO_MSK_OFFSET	0x00000140
+#define C_PARBS_ERR_INFO_MSK	(C_PARBS_BASE + C_PARBS_ERR_INFO_MSK_OFFSET)
+#define C_PARBS_ERR_INFO_MSK_SIZE	0x00000008
+#define C_PARBS_ERR_INFO_MEM_OFFSET	0x00000180
+#define C_PARBS_ERR_INFO_MEM	(C_PARBS_BASE + C_PARBS_ERR_INFO_MEM_OFFSET)
+#define C_PARBS_ERR_INFO_MEM_SIZE	0x00000008
+
+union c_parbs_err_info_mem {
+	__u64 qw;
+	struct {
+		__u64 cor_syndrome       : 11;
+		__u64: 1;
+		__u64 cor_address        : 11;
+		__u64: 1;
+		__u64 cor_mem_id         :  4;
+		__u64: 3;
+		__u64 cor_csr_detected   :  1;
+		__u64 ucor_syndrome      : 11;
+		__u64: 1;
+		__u64 ucor_address       : 11;
+		__u64: 1;
+		__u64 ucor_mem_id        :  4;
+		__u64: 3;
+		__u64 ucor_csr_detected  :  1;
+	};
+};
+
+#define C_PARBS_EXT_ERR_FLG_OFFSET	0x00000208
+#define C_PARBS_EXT_ERR_FLG	(C_PARBS_BASE + C_PARBS_EXT_ERR_FLG_OFFSET)
+#define C_PARBS_EXT_ERR_FLG_SIZE	0x00000008
+
+union c_parbs_ext_err_flg {
+	__u64 qw;
+	struct {
+		__u64 sw_diag            :  1;
+		__u64 pi_rarb_hdr_cor    :  1;
+		__u64 pi_rarb_hdr_ucor   :  1;
+		__u64 pi_rarb_data_cor   :  1;
+		__u64 pi_rarb_data_ucor  :  1;
+		__u64: 59;
+	};
+};
+
+#define C_PARBS_EXT_ERR_FIRST_FLG_OFFSET	0x00000210
+#define C_PARBS_EXT_ERR_FIRST_FLG	(C_PARBS_BASE + C_PARBS_EXT_ERR_FIRST_FLG_OFFSET)
+#define C_PARBS_EXT_ERR_FIRST_FLG_SIZE	0x00000008
+#define C_PARBS_EXT_ERR_FIRST_FLG_TS_OFFSET	0x00000218
+#define C_PARBS_EXT_ERR_FIRST_FLG_TS	(C_PARBS_BASE + C_PARBS_EXT_ERR_FIRST_FLG_TS_OFFSET)
+#define C_PARBS_EXT_ERR_FIRST_FLG_TS_SIZE	0x00000008
+#define C_PARBS_EXT_ERR_CLR_OFFSET	0x00000220
+#define C_PARBS_EXT_ERR_CLR	(C_PARBS_BASE + C_PARBS_EXT_ERR_CLR_OFFSET)
+#define C_PARBS_EXT_ERR_CLR_SIZE	0x00000008
+#define C_PARBS_EXT_ERR_IRQA_MSK_OFFSET	0x00000228
+#define C_PARBS_EXT_ERR_IRQA_MSK	(C_PARBS_BASE + C_PARBS_EXT_ERR_IRQA_MSK_OFFSET)
+#define C_PARBS_EXT_ERR_IRQA_MSK_SIZE	0x00000008
+#define C_PARBS_EXT_ERR_IRQB_MSK_OFFSET	0x00000230
+#define C_PARBS_EXT_ERR_IRQB_MSK	(C_PARBS_BASE + C_PARBS_EXT_ERR_IRQB_MSK_OFFSET)
+#define C_PARBS_EXT_ERR_IRQB_MSK_SIZE	0x00000008
+#define C_PARBS_EXT_ERR_INFO_MSK_OFFSET	0x00000240
+#define C_PARBS_EXT_ERR_INFO_MSK	(C_PARBS_BASE + C_PARBS_EXT_ERR_INFO_MSK_OFFSET)
+#define C_PARBS_EXT_ERR_INFO_MSK_SIZE	0x00000008
+#define C_PCT_CFG_CRNC_OFFSET	0x00000000
+#define C_PCT_CFG_CRNC	(C_PCT_BASE + C_PCT_CFG_CRNC_OFFSET)
+#define C_PCT_CFG_CRNC_SIZE	0x00000008
+
+union c_pct_cfg_crnc {
+	__u64 qw;
+	struct {
+		__u64 csr_timeout   :  8;
+		__u64 mcast_id      : 10;
+		__u64: 1;
+		__u64 mcast_enable  :  1;
+		__u64 mcast_mask    : 10;
+		__u64: 34;
+	};
+};
+
+#define C_PCT_MSC_SHADOW_ACTION_OFFSET	0x00000038
+#define C_PCT_MSC_SHADOW_ACTION	(C_PCT_BASE + C_PCT_MSC_SHADOW_ACTION_OFFSET)
+#define C_PCT_MSC_SHADOW_ACTION_SIZE	0x00000008
+#define C_PCT_MSC_SHADOW_OFFSET	0x00000040
+#define C_PCT_MSC_SHADOW	(C_PCT_BASE + C_PCT_MSC_SHADOW_OFFSET)
+#define C_PCT_MSC_SHADOW_SIZE	0x00000080
+
+union c_pct_msc_shadow {
+	__u64 qw[16];
+};
+
+#define C_PCT_ERR_ELAPSED_TIME_OFFSET	0x00000100
+#define C_PCT_ERR_ELAPSED_TIME	(C_PCT_BASE + C_PCT_ERR_ELAPSED_TIME_OFFSET)
+#define C_PCT_ERR_ELAPSED_TIME_SIZE	0x00000008
+
+union c_pct_err_elapsed_time {
+	__u64 qw;
+	struct {
+		__u64 nanoseconds  : 30;
+		__u64 seconds      : 34;
+	};
+};
+
+#define C1_PCT_ERR_FLG_OFFSET	0x00000108
+#define C1_PCT_ERR_FLG	(C_PCT_BASE + C1_PCT_ERR_FLG_OFFSET)
+#define C1_PCT_ERR_FLG_SIZE	0x00000008
+
+union c1_pct_err_flg {
+	__u64 qw;
+	struct {
+		__u64 sw_diag                  :  1;
+		__u64 crnc_ring_sync_error     :  1;
+		__u64 crnc_ring_ecc_sbe        :  1;
+		__u64 crnc_ring_ecc_mbe        :  1;
+		__u64 crnc_ring_cmd_unknown    :  1;
+		__u64 crnc_csr_cmd_unknown     :  1;
+		__u64 crnc_csr_cmd_incomplete  :  1;
+		__u64 crnc_buf_ecc_sbe         :  1;
+		__u64 crnc_buf_ecc_mbe         :  1;
+		__u64 srb_alloc_dup            :  1;
+		__u64 srb_dealloc_dup          :  1;
+		__u64: 1;
+		__u64 flop_fifo_cor            :  1;
+		__u64 mst_cam_free_cor         :  1;
+		__u64 sct_cam_free_cor         :  1;
+		__u64 tct_cam_free_cor         :  1;
+		__u64 trs_cam_free_cor         :  1;
+		__u64 sct_tbl_cor              :  1;
+		__u64 smt_tbl_cor              :  1;
+		__u64 spt_tbl_cor              :  1;
+		__u64 tct_tbl_cor              :  1;
+		__u64 trs_tbl_cor              :  1;
+		__u64 req_redo_cor             :  1;
+		__u64 cls_clr_req_gen_cor      :  1;
+		__u64 srb_nlist_ram_cor        :  1;
+		__u64 srb_data_ram_cor         :  1;
+		__u64 flop_fifo_ucor           :  1;
+		__u64 mst_cam_free_ucor        :  1;
+		__u64 sct_cam_free_ucor        :  1;
+		__u64 tct_cam_free_ucor        :  1;
+		__u64 trs_cam_free_ucor        :  1;
+		__u64 sct_tbl_ucor             :  1;
+		__u64 smt_tbl_ucor             :  1;
+		__u64 spt_tbl_ucor             :  1;
+		__u64 tct_tbl_ucor             :  1;
+		__u64 trs_tbl_ucor             :  1;
+		__u64 req_redo_ucor            :  1;
+		__u64 cls_clr_req_gen_ucor     :  1;
+		__u64 srb_nlist_ram_ucor       :  1;
+		__u64 srb_data_ram_ucor        :  1;
+		__u64 mst_cam_ucor             :  1;
+		__u64 sct_cam_ucor             :  1;
+		__u64 tct_cam_ucor             :  1;
+		__u64 trs_cam_ucor             :  1;
+		__u64 fifo_err                 :  1;
+		__u64 credit_uflw              :  1;
+		__u64: 18;
+	};
+};
+
+#define C2_PCT_ERR_FLG_OFFSET	0x00000108
+#define C2_PCT_ERR_FLG	(C_PCT_BASE + C2_PCT_ERR_FLG_OFFSET)
+#define C2_PCT_ERR_FLG_SIZE	0x00000008
+
+union c2_pct_err_flg {
+	__u64 qw;
+	struct {
+		__u64 sw_diag                  :  1;
+		__u64 crnc_ring_sync_error     :  1;
+		__u64 crnc_ring_ecc_sbe        :  1;
+		__u64 crnc_ring_ecc_mbe        :  1;
+		__u64 crnc_ring_cmd_unknown    :  1;
+		__u64 crnc_csr_cmd_unknown     :  1;
+		__u64 crnc_csr_cmd_incomplete  :  1;
+		__u64 crnc_buf_ecc_sbe         :  1;
+		__u64 crnc_buf_ecc_mbe         :  1;
+		__u64 srb_alloc_dup            :  1;
+		__u64 srb_dealloc_dup          :  1;
+		__u64: 1;
+		__u64 flop_fifo_cor            :  1;
+		__u64 mst_cam_free_cor         :  1;
+		__u64 sct_cam_free_cor         :  1;
+		__u64 tct_cam_free_cor         :  1;
+		__u64 trs_cam_free_cor         :  1;
+		__u64 sct_tbl_cor              :  1;
+		__u64 smt_tbl_cor              :  1;
+		__u64 spt_tbl_cor              :  1;
+		__u64 tct_tbl_cor              :  1;
+		__u64 trs_tbl_cor              :  1;
+		__u64 req_redo_cor             :  1;
+		__u64 cls_clr_req_gen_cor      :  1;
+		__u64 srb_nlist_ram_cor        :  1;
+		__u64 srb_data_ram_cor         :  1;
+		__u64 cls_rsp_gen_cor          :  1;
+		__u64 nack_trs_rsp_gen_cor     :  1;
+		__u64 flop_fifo_ucor           :  1;
+		__u64 mst_cam_free_ucor        :  1;
+		__u64 sct_cam_free_ucor        :  1;
+		__u64 tct_cam_free_ucor        :  1;
+		__u64 trs_cam_free_ucor        :  1;
+		__u64 sct_tbl_ucor             :  1;
+		__u64 smt_tbl_ucor             :  1;
+		__u64 spt_tbl_ucor             :  1;
+		__u64 tct_tbl_ucor             :  1;
+		__u64 trs_tbl_ucor             :  1;
+		__u64 req_redo_ucor            :  1;
+		__u64 cls_clr_req_gen_ucor     :  1;
+		__u64 srb_nlist_ram_ucor       :  1;
+		__u64 srb_data_ram_ucor        :  1;
+		__u64 mst_cam_ucor             :  1;
+		__u64 sct_cam_ucor             :  1;
+		__u64 tct_cam_ucor             :  1;
+		__u64 trs_cam_ucor             :  1;
+		__u64 nack_trs_rsp_gen_ucor    :  1;
+		__u64 cls_rsp_gen_ucor         :  1;
+		__u64 fifo_err                 :  1;
+		__u64 credit_uflw              :  1;
+		__u64: 14;
+	};
+};
+
+#define C_PCT_ERR_FIRST_FLG_OFFSET	0x00000110
+#define C_PCT_ERR_FIRST_FLG	(C_PCT_BASE + C_PCT_ERR_FIRST_FLG_OFFSET)
+#define C_PCT_ERR_FIRST_FLG_SIZE	0x00000008
+#define C_PCT_ERR_FIRST_FLG_TS_OFFSET	0x00000118
+#define C_PCT_ERR_FIRST_FLG_TS	(C_PCT_BASE + C_PCT_ERR_FIRST_FLG_TS_OFFSET)
+#define C_PCT_ERR_FIRST_FLG_TS_SIZE	0x00000008
+#define C_PCT_ERR_CLR_OFFSET	0x00000120
+#define C_PCT_ERR_CLR	(C_PCT_BASE + C_PCT_ERR_CLR_OFFSET)
+#define C_PCT_ERR_CLR_SIZE	0x00000008
+#define C_PCT_ERR_IRQA_MSK_OFFSET	0x00000128
+#define C_PCT_ERR_IRQA_MSK	(C_PCT_BASE + C_PCT_ERR_IRQA_MSK_OFFSET)
+#define C_PCT_ERR_IRQA_MSK_SIZE	0x00000008
+#define C_PCT_ERR_IRQB_MSK_OFFSET	0x00000130
+#define C_PCT_ERR_IRQB_MSK	(C_PCT_BASE + C_PCT_ERR_IRQB_MSK_OFFSET)
+#define C_PCT_ERR_IRQB_MSK_SIZE	0x00000008
+#define C_PCT_ERR_INFO_MSK_OFFSET	0x00000140
+#define C_PCT_ERR_INFO_MSK	(C_PCT_BASE + C_PCT_ERR_INFO_MSK_OFFSET)
+#define C_PCT_ERR_INFO_MSK_SIZE	0x00000008
+#define C_PCT_EXT_ERR_FLG_OFFSET	0x00000148
+#define C_PCT_EXT_ERR_FLG	(C_PCT_BASE + C_PCT_EXT_ERR_FLG_OFFSET)
+#define C_PCT_EXT_ERR_FLG_SIZE	0x00000008
+
+union c_pct_ext_err_flg {
+	__u64 qw;
+	struct {
+		__u64 sw_diag                         :  1;
+		__u64 sct_tbl_dealloc                 :  1;
+		__u64 sct_tbl_alloc                   :  1;
+		__u64 sct_tbl_rd_misc_unused          :  1;
+		__u64 sct_tbl_wr_misc_unused          :  1;
+		__u64 sct_tbl_rd_ram_unused           :  1;
+		__u64 sct_tbl_wr_ram_unused           :  1;
+		__u64 smt_tbl_dealloc                 :  1;
+		__u64 smt_tbl_alloc                   :  1;
+		__u64 smt_tbl_rd_ram_unused           :  1;
+		__u64 smt_tbl_wr_ram_unused           :  1;
+		__u64 spt_tbl_dealloc                 :  1;
+		__u64 spt_tbl_alloc                   :  1;
+		__u64 spt_tbl_rd_misc_unused          :  1;
+		__u64 spt_tbl_wr_misc_unused          :  1;
+		__u64 spt_tbl_rd_ram_unused           :  1;
+		__u64 spt_tbl_wr_ram_unused           :  1;
+		__u64 spt_tbl_set_wrong_status        :  1;
+		__u64 tct_tbl_dealloc                 :  1;
+		__u64 tct_tbl_alloc                   :  1;
+		__u64 tct_tbl_rd_misc_unused          :  1;
+		__u64 tct_tbl_rd_ram_unused           :  1;
+		__u64 tct_tbl_wr_ram_unused           :  1;
+		__u64 trs_tbl_dealloc                 :  1;
+		__u64 trs_tbl_alloc                   :  1;
+		__u64 trs_tbl_rd_ram_unused           :  1;
+		__u64 trs_tbl_wr_ram_unused           :  1;
+		__u64 oxe_sct_miss_on_mid             :  1;
+		__u64 oxe_failed_sct_alloc            :  1;
+		__u64 oxe_illegal_req                 :  1;
+		__u64 oxe_new_conn_not_som            :  1;
+		__u64 oxe_invalid_smt_not_som         :  1;
+		__u64 oxe_illegal_access2_fsm         :  1;
+		__u64 oxe_smt_req_cnt_exceed          :  1;
+		__u64 oxe_sct_req_cnt_exceed          :  1;
+		__u64 ixe_req_tct_not_in_use          :  1;
+		__u64 ixe_req_tct_miss_unordered_mid  :  1;
+		__u64 ixe_req_mst_missing             :  1;
+		__u64 ixe_req_clr_out_of_range        :  1;
+		__u64 ixe_rsp_spt_not_in_use          :  1;
+		__u64 ixe_rsp_spt_status_not_pend     :  1;
+		__u64 ixe_rsp_smt_pend_cnt_exceed     :  1;
+		__u64 ixe_rsp_sct_pend_cnt_exceed     :  1;
+		__u64 ixe_rsp_smt_invalid             :  1;
+		__u64 ixe_rsp_spt_not_get_vld         :  1;
+		__u64 ixe_rsp_cls_not_pend            :  1;
+		__u64 ixe_gcomp_spt_not_in_use        :  1;
+		__u64 ixe_gcomp_not_get_ack_rcvd      :  1;
+		__u64 ixe_gcomp_smt_pend_cnt_exceed   :  1;
+		__u64 ixe_gcomp_sct_pend_cnt_exceed   :  1;
+		__u64 ixe_gcomp_smt_invalid           :  1;
+		__u64 ixe_gcomp_spt_not_get_vld       :  1;
+		__u64 src_cls_spt_wrong_sct           :  1;
+		__u64 src_cls_spt_not_used            :  1;
+		__u64 src_cls_spt_not_opcomp          :  1;
+		__u64 src_cls_bad_close               :  1;
+		__u64 pkto_illegal_req                :  1;
+		__u64 pkto_illegal_pkttype            :  1;
+		__u64 pkto_head_fsm                   :  1;
+		__u64 srb_wr_rd_same_cycle            :  1;
+		__u64 sct_miss_unrestricted_mid       :  1;
+		__u64 mbe_in_ctrls                    :  1;
+		__u64 sct_cam_err                     :  1;
+		__u64 mst_cam_err                     :  1;
+	};
+};
+
+#define C_PCT_EXT_ERR_FIRST_FLG_OFFSET	0x00000150
+#define C_PCT_EXT_ERR_FIRST_FLG	(C_PCT_BASE + C_PCT_EXT_ERR_FIRST_FLG_OFFSET)
+#define C_PCT_EXT_ERR_FIRST_FLG_SIZE	0x00000008
+#define C_PCT_EXT_ERR_FIRST_FLG_TS_OFFSET	0x00000158
+#define C_PCT_EXT_ERR_FIRST_FLG_TS	(C_PCT_BASE + C_PCT_EXT_ERR_FIRST_FLG_TS_OFFSET)
+#define C_PCT_EXT_ERR_FIRST_FLG_TS_SIZE	0x00000008
+#define C_PCT_EXT_ERR_CLR_OFFSET	0x00000160
+#define C_PCT_EXT_ERR_CLR	(C_PCT_BASE + C_PCT_EXT_ERR_CLR_OFFSET)
+#define C_PCT_EXT_ERR_CLR_SIZE	0x00000008
+#define C_PCT_EXT_ERR_IRQA_MSK_OFFSET	0x00000168
+#define C_PCT_EXT_ERR_IRQA_MSK	(C_PCT_BASE + C_PCT_EXT_ERR_IRQA_MSK_OFFSET)
+#define C_PCT_EXT_ERR_IRQA_MSK_SIZE	0x00000008
+#define C_PCT_EXT_ERR_IRQB_MSK_OFFSET	0x00000170
+#define C_PCT_EXT_ERR_IRQB_MSK	(C_PCT_BASE + C_PCT_EXT_ERR_IRQB_MSK_OFFSET)
+#define C_PCT_EXT_ERR_IRQB_MSK_SIZE	0x00000008
+#define C_PCT_EXT_ERR_INFO_MSK_OFFSET	0x00000180
+#define C_PCT_EXT_ERR_INFO_MSK	(C_PCT_BASE + C_PCT_EXT_ERR_INFO_MSK_OFFSET)
+#define C_PCT_EXT_ERR_INFO_MSK_SIZE	0x00000008
+#define C_PCT_ERR_INFO_MEM_OFFSET	0x00000188
+#define C_PCT_ERR_INFO_MEM	(C_PCT_BASE + C_PCT_ERR_INFO_MEM_OFFSET)
+#define C_PCT_ERR_INFO_MEM_SIZE	0x00000008
+
+union c_pct_err_info_mem {
+	__u64 qw;
+	struct {
+		__u64 cor_syndrome       : 11;
+		__u64 cor_address        : 13;
+		__u64 cor_mem_id         :  7;
+		__u64 cor_csr_detected   :  1;
+		__u64 ucor_syndrome      : 11;
+		__u64 ucor_address       : 13;
+		__u64 ucor_mem_id        :  7;
+		__u64 ucor_csr_detected  :  1;
+	};
+};
+
+#define C_PCT_ERR_INFO_FIFO_OFFSET	0x00000190
+#define C_PCT_ERR_INFO_FIFO	(C_PCT_BASE + C_PCT_ERR_INFO_FIFO_OFFSET)
+#define C_PCT_ERR_INFO_FIFO_SIZE	0x00000008
+
+union c_pct_err_info_fifo {
+	__u64 qw;
+	struct {
+		__u64 overrun   :  1;
+		__u64 underrun  :  1;
+		__u64: 6;
+		__u64 fifo_id   :  6;
+		__u64: 50;
+	};
+};
+
+#define C_PCT_ERR_INFO_CC_OFFSET	0x00000198
+#define C_PCT_ERR_INFO_CC	(C_PCT_BASE + C_PCT_ERR_INFO_CC_OFFSET)
+#define C_PCT_ERR_INFO_CC_SIZE	0x00000008
+
+union c_pct_err_info_cc {
+	__u64 qw;
+	struct {
+		__u64 cc_id   :  6;
+		__u64: 2;
+		__u64 sub_id  :  3;
+		__u64: 53;
+	};
+};
+
+#define C_PCT_ERR_INFO_EXT_OFFSET	0x000001a0
+#define C_PCT_ERR_INFO_EXT	(C_PCT_BASE + C_PCT_ERR_INFO_EXT_OFFSET)
+#define C_PCT_ERR_INFO_EXT_SIZE	0x00000008
+
+union c_pct_err_info_ext {
+	__u64 qw;
+	struct {
+		__u64 sct_wr_err_id  :  5;
+		__u64 sct_rd_err_id  :  5;
+		__u64: 2;
+		__u64 smt_wr_err_id  :  4;
+		__u64 smt_rd_err_id  :  4;
+		__u64 spt_wr_err_id  :  5;
+		__u64 spt_rd_err_id  :  5;
+		__u64: 2;
+		__u64 tct_wr_err_id  :  3;
+		__u64 tct_rd_err_id  :  3;
+		__u64: 2;
+		__u64 trs_wr_err_id  :  3;
+		__u64 trs_rd_err_id  :  3;
+		__u64: 2;
+		__u64 mbe_err_id     :  5;
+		__u64: 11;
+	};
+};
+
+#define C_PCT_CFG_EQ_RETRY_Q_HANDLE_OFFSET	0x00000300
+#define C_PCT_CFG_EQ_RETRY_Q_HANDLE	(C_PCT_BASE + C_PCT_CFG_EQ_RETRY_Q_HANDLE_OFFSET)
+#define C_PCT_CFG_EQ_RETRY_Q_HANDLE_SIZE	0x00000008
+
+union c_pct_cfg_eq_retry_q_handle {
+	__u64 qw;
+	struct {
+		__u64 eq_handle  : 11;
+		__u64: 53;
+	};
+};
+
+#define C_PCT_CFG_EQ_TGT_Q_HANDLE_OFFSET	0x00000308
+#define C_PCT_CFG_EQ_TGT_Q_HANDLE	(C_PCT_BASE + C_PCT_CFG_EQ_TGT_Q_HANDLE_OFFSET)
+#define C_PCT_CFG_EQ_TGT_Q_HANDLE_SIZE	0x00000008
+
+union c_pct_cfg_eq_tgt_q_handle {
+	__u64 qw;
+	struct {
+		__u64 eq_handle  : 11;
+		__u64: 53;
+	};
+};
+
+#define C_PCT_CFG_EQ_CONN_LD_Q_HANDLE_OFFSET	0x00000310
+#define C_PCT_CFG_EQ_CONN_LD_Q_HANDLE	(C_PCT_BASE + C_PCT_CFG_EQ_CONN_LD_Q_HANDLE_OFFSET)
+#define C_PCT_CFG_EQ_CONN_LD_Q_HANDLE_SIZE	0x00000008
+
+union c_pct_cfg_eq_conn_ld_q_handle {
+	__u64 qw;
+	struct {
+		__u64 eq_handle  : 11;
+		__u64: 53;
+	};
+};
+
+#define C_PCT_CFG_SRB_RETRY_PTRS_OFFSET(idx)	(0x000003e0 + ((idx) * 8))
+#define C_PCT_CFG_SRB_RETRY_PTRS_ENTRIES	4
+#define C_PCT_CFG_SRB_RETRY_PTRS(idx)	(C_PCT_BASE + C_PCT_CFG_SRB_RETRY_PTRS_OFFSET(idx))
+#define C_PCT_CFG_SRB_RETRY_PTRS_SIZE	0x00000020
+
+struct c_pct_cfg_srb_retry_ptrs_entry {
+	__u32 ptr     : 11;
+	__u32:  1;
+	__u32 vld     :  1;
+	__u32:  3;
+	__u32 spt_idx : 11;
+	__u32:  1;
+	__u32 try_num :  3;
+	__u32:  1;
+};
+
+union c_pct_cfg_srb_retry_ptrs {
+	__u64 qw;
+	struct c_pct_cfg_srb_retry_ptrs_entry e[2];
+};
+
+#define C_PCT_CFG_SRB_RETRY_CTRL_OFFSET	0x00000400
+#define C_PCT_CFG_SRB_RETRY_CTRL	(C_PCT_BASE + C_PCT_CFG_SRB_RETRY_CTRL_OFFSET)
+#define C_PCT_CFG_SRB_RETRY_CTRL_SIZE	0x00000008
+
+union c_pct_cfg_srb_retry_ctrl {
+	__u64 qw;
+	struct {
+		__u64 pcp_pause_st  :  8;
+		__u64 current_ptr   :  3;
+		__u64: 5;
+		__u64 grp_nxt       :  1;
+		__u64: 7;
+		__u64 error         :  1;
+		__u64: 3;
+		__u64 sw_abort      :  1;
+		__u64: 3;
+		__u64 hw_sw_sync    :  1;
+		__u64: 3;
+		__u64 pause_mode    :  1;
+		__u64: 27;
+	};
+};
+
+#define C1_PCT_CFG_SRB_RETRY_GRP_CTRL_OFFSET(idx)	(0x00000408 + ((idx) * 8))
+#define C1_PCT_CFG_SRB_RETRY_GRP_CTRL_ENTRIES	2
+#define C1_PCT_CFG_SRB_RETRY_GRP_CTRL(idx)	(C_PCT_BASE + C1_PCT_CFG_SRB_RETRY_GRP_CTRL_OFFSET(idx))
+#define C1_PCT_CFG_SRB_RETRY_GRP_CTRL_SIZE	0x00000010
+
+union c1_pct_cfg_srb_retry_grp_ctrl {
+	__u64 qw;
+	struct {
+		__u64 grp_loaded            :  1;
+		__u64 grp_active            :  1;
+		__u64 grp_paused            :  1;
+		__u64 grp_sct_idx_vld       :  1;
+		__u64 grp_sct_idx           : 12;
+		__u64 grp_pcp               :  3;
+		__u64: 5;
+		__u64 grp_unset_clr_seqnum  :  1;
+		__u64: 39;
+	};
+};
+
+#define C2_PCT_CFG_SRB_RETRY_GRP_CTRL_OFFSET(idx)	(0x00000408 + ((idx) * 8))
+#define C2_PCT_CFG_SRB_RETRY_GRP_CTRL_ENTRIES	2
+#define C2_PCT_CFG_SRB_RETRY_GRP_CTRL(idx)	(C_PCT_BASE + C2_PCT_CFG_SRB_RETRY_GRP_CTRL_OFFSET(idx))
+#define C2_PCT_CFG_SRB_RETRY_GRP_CTRL_SIZE	0x00000010
+
+union c2_pct_cfg_srb_retry_grp_ctrl {
+	__u64 qw;
+	struct {
+		__u64 grp_loaded                :  1;
+		__u64 grp_active                :  1;
+		__u64 grp_paused                :  1;
+		__u64 grp_sct_idx_vld           :  1;
+		__u64 grp_sct_idx               : 12;
+		__u64 grp_pcp                   :  3;
+		__u64: 5;
+		__u64 grp_update_clr_seqnum_en  :  1;
+		__u64 grp_update_clr_seqnum     : 12;
+		__u64: 27;
+	};
+};
+
+#define C_PCT_CFG_PKT_MISC_OFFSET	0x00000430
+#define C_PCT_CFG_PKT_MISC	(C_PCT_BASE + C_PCT_CFG_PKT_MISC_OFFSET)
+#define C_PCT_CFG_PKT_MISC_SIZE	0x00000008
+
+union c_pct_cfg_pkt_misc {
+	__u64 qw;
+	struct {
+		__u64 sm_fab_hdr                 :  4;
+		__u64: 4;
+		__u64 ptl_proto                  :  8;
+		__u64 pktid_4000                 :  1;
+		__u64: 7;
+		__u64 simple_mode                :  1;
+		__u64: 3;
+		__u64 trs_pend_rsp_nack_disable  :  1;
+		__u64: 15;
+		__u64 sfa_nid                    : 20;
+	};
+};
+
+#define C_PCT_CFG_TIMING_OFFSET	0x00000440
+#define C_PCT_CFG_TIMING	(C_PCT_BASE + C_PCT_CFG_TIMING_OFFSET)
+#define C_PCT_CFG_TIMING_SIZE	0x00000008
+
+union c_pct_cfg_timing {
+	__u64 qw;
+	struct {
+		__u64 stall_ctr              :  5;
+		__u64: 3;
+		__u64 spt_timeout_epoch_sel  :  6;
+		__u64: 2;
+		__u64 sct_idle_epoch_sel     :  6;
+		__u64: 2;
+		__u64 sct_close_epoch_sel    :  6;
+		__u64: 2;
+		__u64 tct_timeout_epoch_sel  :  6;
+		__u64: 2;
+		__u64 put_get_same_sct_en    :  1;
+		__u64: 7;
+		__u64 accept_late_spt_rsp    :  1;
+		__u64: 15;
+	};
+};
+
+#define C1_PCT_CFG_IXE_REQ_FIFO_LIMITS_OFFSET	0x00000508
+#define C1_PCT_CFG_IXE_REQ_FIFO_LIMITS	(C_PCT_BASE + C1_PCT_CFG_IXE_REQ_FIFO_LIMITS_OFFSET)
+#define C1_PCT_CFG_IXE_REQ_FIFO_LIMITS_SIZE	0x00000008
+
+union c1_pct_cfg_ixe_req_fifo_limits {
+	__u64 qw;
+	struct {
+		__u64 ixe_req_clr_limit   :  6;
+		__u64: 2;
+		__u64 ixe_req_clr1_limit  :  3;
+		__u64: 5;
+		__u64 ixe_req_clr2_limit  :  3;
+		__u64: 5;
+		__u64 ixe_req_rsp_limit   :  5;
+		__u64: 35;
+	};
+};
+
+#define C2_PCT_CFG_IXE_REQ_FIFO_LIMITS_OFFSET	0x00000508
+#define C2_PCT_CFG_IXE_REQ_FIFO_LIMITS	(C_PCT_BASE + C2_PCT_CFG_IXE_REQ_FIFO_LIMITS_OFFSET)
+#define C2_PCT_CFG_IXE_REQ_FIFO_LIMITS_SIZE	0x00000008
+
+union c2_pct_cfg_ixe_req_fifo_limits {
+	__u64 qw;
+	struct {
+		__u64 ixe_req_clr_limit   :  6;
+		__u64: 2;
+		__u64 ixe_req_clr1_limit  :  3;
+		__u64: 5;
+		__u64 ixe_req_clr2_limit  :  3;
+		__u64: 5;
+		__u64 nack_trs_rsp_limit  :  4;
+		__u64: 36;
+	};
+};
+
+#define C_PCT_CFG_IXE_RSP_FIFO_LIMITS_OFFSET	0x00000528
+#define C_PCT_CFG_IXE_RSP_FIFO_LIMITS	(C_PCT_BASE + C_PCT_CFG_IXE_RSP_FIFO_LIMITS_OFFSET)
+#define C_PCT_CFG_IXE_RSP_FIFO_LIMITS_SIZE	0x00000008
+
+union c_pct_cfg_ixe_rsp_fifo_limits {
+	__u64 qw;
+	struct {
+		__u64 clr_limit          :  4;
+		__u64 ee_limit           :  5;
+		__u64: 3;
+		__u64 cq_limit           :  5;
+		__u64: 3;
+		__u64 srb_dealloc_limit  :  5;
+		__u64: 3;
+		__u64 smt_cdt_ack_limit  :  4;
+		__u64 spt_cdt_ack_limit  :  4;
+		__u64 sct_cdt_ack_limit  :  4;
+		__u64: 24;
+	};
+};
+
+#define C_PCT_CFG_TGT_CLR_REQ_FIFO_LIMIT_OFFSET	0x00000538
+#define C_PCT_CFG_TGT_CLR_REQ_FIFO_LIMIT	(C_PCT_BASE + C_PCT_CFG_TGT_CLR_REQ_FIFO_LIMIT_OFFSET)
+#define C_PCT_CFG_TGT_CLR_REQ_FIFO_LIMIT_SIZE	0x00000008
+
+union c_pct_cfg_tgt_clr_req_fifo_limit {
+	__u64 qw;
+	struct {
+		__u64 tgt_clr_req_limit       :  6;
+		__u64: 2;
+		__u64 mst_dealloc_fifo_limit  :  4;
+		__u64: 52;
+	};
+};
+
+#define C1_PCT_CFG_TRS_TC_DED_LIMIT_OFFSET(idx)	(0x00000600 + ((idx) * 8))
+#define C1_PCT_CFG_TRS_TC_DED_LIMIT_ENTRIES	8
+#define C1_PCT_CFG_TRS_TC_DED_LIMIT(idx)	(C_PCT_BASE + C1_PCT_CFG_TRS_TC_DED_LIMIT_OFFSET(idx))
+#define C1_PCT_CFG_TRS_TC_DED_LIMIT_SIZE	0x00000040
+
+union c1_pct_cfg_trs_tc_ded_limit {
+	__u64 qw;
+	struct {
+		__u64 ded_limit  : 12;
+		__u64: 52;
+	};
+};
+
+#define C2_PCT_CFG_TRS_TC_DED_LIMIT_OFFSET(idx)	(0x00000600 + ((idx) * 8))
+#define C2_PCT_CFG_TRS_TC_DED_LIMIT_ENTRIES	8
+#define C2_PCT_CFG_TRS_TC_DED_LIMIT(idx)	(C_PCT_BASE + C2_PCT_CFG_TRS_TC_DED_LIMIT_OFFSET(idx))
+#define C2_PCT_CFG_TRS_TC_DED_LIMIT_SIZE	0x00000040
+
+union c2_pct_cfg_trs_tc_ded_limit {
+	__u64 qw;
+	struct {
+		__u64 ded_limit  : 14;
+		__u64: 50;
+	};
+};
+
+#define C1_PCT_CFG_TRS_TC_MAX_LIMIT_OFFSET(idx)	(0x00000640 + ((idx) * 8))
+#define C1_PCT_CFG_TRS_TC_MAX_LIMIT_ENTRIES	8
+#define C1_PCT_CFG_TRS_TC_MAX_LIMIT(idx)	(C_PCT_BASE + C1_PCT_CFG_TRS_TC_MAX_LIMIT_OFFSET(idx))
+#define C1_PCT_CFG_TRS_TC_MAX_LIMIT_SIZE	0x00000040
+
+union c1_pct_cfg_trs_tc_max_limit {
+	__u64 qw;
+	struct {
+		__u64 max_limit  : 12;
+		__u64: 52;
+	};
+};
+
+#define C2_PCT_CFG_TRS_TC_MAX_LIMIT_OFFSET(idx)	(0x00000640 + ((idx) * 8))
+#define C2_PCT_CFG_TRS_TC_MAX_LIMIT_ENTRIES	8
+#define C2_PCT_CFG_TRS_TC_MAX_LIMIT(idx)	(C_PCT_BASE + C2_PCT_CFG_TRS_TC_MAX_LIMIT_OFFSET(idx))
+#define C2_PCT_CFG_TRS_TC_MAX_LIMIT_SIZE	0x00000040
+
+union c2_pct_cfg_trs_tc_max_limit {
+	__u64 qw;
+	struct {
+		__u64 max_limit  : 14;
+		__u64: 50;
+	};
+};
+
+#define C1_PCT_CFG_TRS_CRDT_LIMITS_OFFSET	0x00000680
+#define C1_PCT_CFG_TRS_CRDT_LIMITS	(C_PCT_BASE + C1_PCT_CFG_TRS_CRDT_LIMITS_OFFSET)
+#define C1_PCT_CFG_TRS_CRDT_LIMITS_SIZE	0x00000008
+
+union c1_pct_cfg_trs_crdt_limits {
+	__u64 qw;
+	struct {
+		__u64 total_limit   : 12;
+		__u64: 4;
+		__u64 shared_limit  : 12;
+		__u64: 36;
+	};
+};
+
+#define C2_PCT_CFG_TRS_CRDT_LIMITS_OFFSET	0x00000680
+#define C2_PCT_CFG_TRS_CRDT_LIMITS	(C_PCT_BASE + C2_PCT_CFG_TRS_CRDT_LIMITS_OFFSET)
+#define C2_PCT_CFG_TRS_CRDT_LIMITS_SIZE	0x00000008
+
+union c2_pct_cfg_trs_crdt_limits {
+	__u64 qw;
+	struct {
+		__u64 total_limit   : 14;
+		__u64: 2;
+		__u64 shared_limit  : 14;
+		__u64: 34;
+	};
+};
+
+#define C_PCT_CFG_MST_TC_DED_LIMIT_OFFSET(idx)	(0x00000690 + ((idx) * 8))
+#define C_PCT_CFG_MST_TC_DED_LIMIT_ENTRIES	8
+#define C_PCT_CFG_MST_TC_DED_LIMIT(idx)	(C_PCT_BASE + C_PCT_CFG_MST_TC_DED_LIMIT_OFFSET(idx))
+#define C_PCT_CFG_MST_TC_DED_LIMIT_SIZE	0x00000040
+
+union c_pct_cfg_mst_tc_ded_limit {
+	__u64 qw;
+	struct {
+		__u64 ded_limit  : 12;
+		__u64: 52;
+	};
+};
+
+#define C_PCT_CFG_MST_TC_MAX_LIMIT_OFFSET(idx)	(0x000006d0 + ((idx) * 8))
+#define C_PCT_CFG_MST_TC_MAX_LIMIT_ENTRIES	8
+#define C_PCT_CFG_MST_TC_MAX_LIMIT(idx)	(C_PCT_BASE + C_PCT_CFG_MST_TC_MAX_LIMIT_OFFSET(idx))
+#define C_PCT_CFG_MST_TC_MAX_LIMIT_SIZE	0x00000040
+
+union c_pct_cfg_mst_tc_max_limit {
+	__u64 qw;
+	struct {
+		__u64 max_limit  : 12;
+		__u64: 52;
+	};
+};
+
+#define C_PCT_CFG_MST_CRDT_LIMITS_OFFSET	0x00000710
+#define C_PCT_CFG_MST_CRDT_LIMITS	(C_PCT_BASE + C_PCT_CFG_MST_CRDT_LIMITS_OFFSET)
+#define C_PCT_CFG_MST_CRDT_LIMITS_SIZE	0x00000008
+
+union c_pct_cfg_mst_crdt_limits {
+	__u64 qw;
+	struct {
+		__u64 total_limit   : 12;
+		__u64: 4;
+		__u64 shared_limit  : 12;
+		__u64: 36;
+	};
+};
+
+#define C_PCT_CFG_TCT_TC_DED_LIMIT_OFFSET(idx)	(0x00000720 + ((idx) * 8))
+#define C_PCT_CFG_TCT_TC_DED_LIMIT_ENTRIES	8
+#define C_PCT_CFG_TCT_TC_DED_LIMIT(idx)	(C_PCT_BASE + C_PCT_CFG_TCT_TC_DED_LIMIT_OFFSET(idx))
+#define C_PCT_CFG_TCT_TC_DED_LIMIT_SIZE	0x00000040
+
+union c_pct_cfg_tct_tc_ded_limit {
+	__u64 qw;
+	struct {
+		__u64 ded_limit  : 14;
+		__u64: 50;
+	};
+};
+
+#define C_PCT_CFG_TCT_TC_MAX_LIMIT_OFFSET(idx)	(0x00000760 + ((idx) * 8))
+#define C_PCT_CFG_TCT_TC_MAX_LIMIT_ENTRIES	8
+#define C_PCT_CFG_TCT_TC_MAX_LIMIT(idx)	(C_PCT_BASE + C_PCT_CFG_TCT_TC_MAX_LIMIT_OFFSET(idx))
+#define C_PCT_CFG_TCT_TC_MAX_LIMIT_SIZE	0x00000040
+
+union c_pct_cfg_tct_tc_max_limit {
+	__u64 qw;
+	struct {
+		__u64 max_limit  : 14;
+		__u64: 50;
+	};
+};
+
+#define C_PCT_CFG_TCT_CRDT_LIMITS_OFFSET	0x000007a0
+#define C_PCT_CFG_TCT_CRDT_LIMITS	(C_PCT_BASE + C_PCT_CFG_TCT_CRDT_LIMITS_OFFSET)
+#define C_PCT_CFG_TCT_CRDT_LIMITS_SIZE	0x00000008
+
+union c_pct_cfg_tct_crdt_limits {
+	__u64 qw;
+	struct {
+		__u64 total_limit   : 14;
+		__u64: 2;
+		__u64 shared_limit  : 14;
+		__u64: 34;
+	};
+};
+
+#define C_PCT_CFG_RSP_DSCP_REQ_TC_MAP_OFFSET(idx)	(0x00000800 + ((idx) * 8))
+#define C_PCT_CFG_RSP_DSCP_REQ_TC_MAP_ENTRIES	4
+#define C_PCT_CFG_RSP_DSCP_REQ_TC_MAP(idx)	(C_PCT_BASE + C_PCT_CFG_RSP_DSCP_REQ_TC_MAP_OFFSET(idx))
+#define C_PCT_CFG_RSP_DSCP_REQ_TC_MAP_SIZE	0x00000020
+
+union c_pct_cfg_rsp_dscp_req_tc_map {
+	__u64 qw;
+	struct {
+		__u64 dscp0_tc   :  3;
+		__u64: 1;
+		__u64 dscp1_tc   :  3;
+		__u64: 1;
+		__u64 dscp2_tc   :  3;
+		__u64: 1;
+		__u64 dscp3_tc   :  3;
+		__u64: 1;
+		__u64 dscp4_tc   :  3;
+		__u64: 1;
+		__u64 dscp5_tc   :  3;
+		__u64: 1;
+		__u64 dscp6_tc   :  3;
+		__u64: 1;
+		__u64 dscp7_tc   :  3;
+		__u64: 1;
+		__u64 dscp8_tc   :  3;
+		__u64: 1;
+		__u64 dscp9_tc   :  3;
+		__u64: 1;
+		__u64 dscp10_tc  :  3;
+		__u64: 1;
+		__u64 dscp11_tc  :  3;
+		__u64: 1;
+		__u64 dscp12_tc  :  3;
+		__u64: 1;
+		__u64 dscp13_tc  :  3;
+		__u64: 1;
+		__u64 dscp14_tc  :  3;
+		__u64: 1;
+		__u64 dscp15_tc  :  3;
+		__u64: 1;
+	};
+};
+
+#define C_PCT_CFG_REQ_DSCP_RSP_DSCP_MAP_OFFSET(idx)	(0x00000820 + ((idx) * 8))
+#define C_PCT_CFG_REQ_DSCP_RSP_DSCP_MAP_ENTRIES	8
+#define C_PCT_CFG_REQ_DSCP_RSP_DSCP_MAP(idx)	(C_PCT_BASE + C_PCT_CFG_REQ_DSCP_RSP_DSCP_MAP_OFFSET(idx))
+#define C_PCT_CFG_REQ_DSCP_RSP_DSCP_MAP_SIZE	0x00000040
+
+struct c_rsp_dscp {
+	__u8 rsp_dscp    : 6;
+	__u8: 2;
+};
+#define C_PCT_CFG_REQ_DSCP_RSP_DSCP_MAP_ARRAY_SIZE 8
+union c_pct_cfg_req_dscp_rsp_dscp_map {
+	__u64 qw;
+	struct c_rsp_dscp map[C_PCT_CFG_REQ_DSCP_RSP_DSCP_MAP_ARRAY_SIZE];
+};
+
+#define C_PCT_CFG_REQ_TC_RSP_TC_MAP_OFFSET	0x00000860
+#define C_PCT_CFG_REQ_TC_RSP_TC_MAP	(C_PCT_BASE + C_PCT_CFG_REQ_TC_RSP_TC_MAP_OFFSET)
+#define C_PCT_CFG_REQ_TC_RSP_TC_MAP_SIZE	0x00000008
+
+union c_pct_cfg_req_tc_rsp_tc_map {
+	__u64 qw;
+	struct {
+		__u64 req_tc0  :  3;
+		__u64: 1;
+		__u64 req_tc1  :  3;
+		__u64: 1;
+		__u64 req_tc2  :  3;
+		__u64: 1;
+		__u64 req_tc3  :  3;
+		__u64: 1;
+		__u64 req_tc4  :  3;
+		__u64: 1;
+		__u64 req_tc5  :  3;
+		__u64: 1;
+		__u64 req_tc6  :  3;
+		__u64: 1;
+		__u64 req_tc7  :  3;
+		__u64: 33;
+	};
+};
+
+#define C_PCT_CFG_SCT_TAG_DFA_MASK_OFFSET(idx)	(0x00000878 + ((idx) * 8))
+#define C_PCT_CFG_SCT_TAG_DFA_MASK_ENTRIES	16
+#define C_PCT_CFG_SCT_TAG_DFA_MASK(idx)	(C_PCT_BASE + C_PCT_CFG_SCT_TAG_DFA_MASK_OFFSET(idx))
+#define C_PCT_CFG_SCT_TAG_DFA_MASK_SIZE	0x00000080
+
+union c_pct_cfg_sct_tag_dfa_mask {
+	__u64 qw;
+	struct {
+		__u16 dfa_mask : 12;
+		__u16: 4;
+	} dscp[4];
+};
+
+#define C_PCT_CFG_SW_RECYCLE_SPT_OFFSET	0x00000908
+#define C_PCT_CFG_SW_RECYCLE_SPT	(C_PCT_BASE + C_PCT_CFG_SW_RECYCLE_SPT_OFFSET)
+#define C_PCT_CFG_SW_RECYCLE_SPT_SIZE	0x00000008
+
+union c_pct_cfg_sw_recycle_spt {
+	__u64 qw;
+	struct {
+		__u64 spt_idx  : 11;
+		__u64: 5;
+		__u64 bc       :  4;
+		__u64: 44;
+	};
+};
+
+#define C_PCT_CFG_SW_RECYCLE_SCT_OFFSET	0x00000910
+#define C_PCT_CFG_SW_RECYCLE_SCT	(C_PCT_BASE + C_PCT_CFG_SW_RECYCLE_SCT_OFFSET)
+#define C_PCT_CFG_SW_RECYCLE_SCT_SIZE	0x00000008
+
+union c_pct_cfg_sw_recycle_sct {
+	__u64 qw;
+	struct {
+		__u64 sct_idx  : 12;
+		__u64: 4;
+		__u64 bc       :  4;
+		__u64: 44;
+	};
+};
+
+#define C_PCT_CFG_SW_SIM_SRC_RSP_OFFSET	0x00000918
+#define C_PCT_CFG_SW_SIM_SRC_RSP	(C_PCT_BASE + C_PCT_CFG_SW_SIM_SRC_RSP_OFFSET)
+#define C_PCT_CFG_SW_SIM_SRC_RSP_SIZE	0x00000008
+
+union c_pct_cfg_sw_sim_src_rsp {
+	__u64 qw;
+	struct {
+		__u64 spt_sct_idx    : 12;
+		__u64: 12;
+		__u64 return_code    :  6;
+		__u64: 2;
+		__u64 opcode         :  4;
+		__u64: 4;
+		__u64 rsp_not_gcomp  :  1;
+		__u64: 7;
+		__u64 loaded         :  1;
+		__u64: 15;
+	};
+};
+
+#define C_PCT_CFG_SW_RETRY_SRC_CLS_REQ_OFFSET	0x00000920
+#define C_PCT_CFG_SW_RETRY_SRC_CLS_REQ	(C_PCT_BASE + C_PCT_CFG_SW_RETRY_SRC_CLS_REQ_OFFSET)
+#define C_PCT_CFG_SW_RETRY_SRC_CLS_REQ_SIZE	0x00000008
+
+union c_pct_cfg_sw_retry_src_cls_req {
+	__u64 qw;
+	struct {
+		__u64 sct_idx          : 12;
+		__u64: 3;
+		__u64 close_not_clear  :  1;
+		__u64 loaded           :  1;
+		__u64: 47;
+	};
+};
+
+#define C_PCT_CFG_SW_SIM_TGT_CLS_REQ_OFFSET	0x00000928
+#define C_PCT_CFG_SW_SIM_TGT_CLS_REQ	(C_PCT_BASE + C_PCT_CFG_SW_SIM_TGT_CLS_REQ_OFFSET)
+#define C_PCT_CFG_SW_SIM_TGT_CLS_REQ_SIZE	0x00000008
+
+union c_pct_cfg_sw_sim_tgt_cls_req {
+	__u64 qw;
+	struct {
+		__u64 tct_idx  : 13;
+		__u64: 3;
+		__u64 loaded   :  1;
+		__u64: 47;
+	};
+};
+
+#define C_PCT_CFG_SCT_RAM0_OFFSET(idx)	(0x00028000 + ((idx) * 8))
+#define C_PCT_CFG_SCT_RAM0_ENTRIES	4096
+#define C_PCT_CFG_SCT_RAM0(idx)	(C_PCT_BASE + C_PCT_CFG_SCT_RAM0_OFFSET(idx))
+#define C_PCT_CFG_SCT_RAM0_SIZE	0x00008000
+
+union c_pct_cfg_sct_ram0 {
+	__u64 qw;
+	struct {
+		__u64 clr_tail      : 11;
+		__u64: 5;
+		__u64 req_pend_cnt  : 11;
+		__u64: 37;
+	};
+};
+
+#define C_PCT_CFG_SCT_RAM1_OFFSET(idx)	(0x00030000 + ((idx) * 8))
+#define C_PCT_CFG_SCT_RAM1_ENTRIES	4096
+#define C_PCT_CFG_SCT_RAM1(idx)	(C_PCT_BASE + C_PCT_CFG_SCT_RAM1_OFFSET(idx))
+#define C_PCT_CFG_SCT_RAM1_SIZE	0x00008000
+
+union c_pct_cfg_sct_ram1 {
+	__u64 qw;
+	struct {
+		__u64 put_comp_cnt  : 11;
+		__u64: 5;
+		__u64 mcu           :  7;
+		__u64: 1;
+		__u64 pcp           :  3;
+		__u64: 1;
+		__u64 bc            :  4;
+		__u64: 8;
+		__u64 sw_recycle    :  1;
+		__u64: 23;
+	};
+};
+
+#define C_PCT_CFG_SCT_RAM2_OFFSET(idx)	(0x00040000 + ((idx) * 8))
+#define C_PCT_CFG_SCT_RAM2_ENTRIES	4096
+#define C_PCT_CFG_SCT_RAM2(idx)	(C_PCT_BASE + C_PCT_CFG_SCT_RAM2_OFFSET(idx))
+#define C_PCT_CFG_SCT_RAM2_SIZE	0x00008000
+
+union c_pct_cfg_sct_ram2 {
+	__u64 qw;
+	struct {
+		__u64: 16;
+		__u64 clr_head   : 11;
+		__u64: 5;
+		__u64 req_seqno  : 12;
+		__u64: 20;
+	};
+};
+
+#define C_PCT_CFG_SCT_RAM3_OFFSET(idx)	(0x00050000 + ((idx) * 8))
+#define C_PCT_CFG_SCT_RAM3_ENTRIES	4096
+#define C_PCT_CFG_SCT_RAM3(idx)	(C_PCT_BASE + C_PCT_CFG_SCT_RAM3_OFFSET(idx))
+#define C_PCT_CFG_SCT_RAM3_SIZE	0x00008000
+
+union c_pct_cfg_sct_ram3 {
+	__u64 qw;
+	struct {
+		__u64 close_try       :  3;
+		__u64 hw_clr_cls_dis  :  1;
+		__u64: 60;
+	};
+};
+
+#define C_PCT_CFG_SCT_RAM4_OFFSET(idx)	(0x00060000 + ((idx) * 8))
+#define C_PCT_CFG_SCT_RAM4_ENTRIES	4096
+#define C_PCT_CFG_SCT_RAM4(idx)	(C_PCT_BASE + C_PCT_CFG_SCT_RAM4_OFFSET(idx))
+#define C_PCT_CFG_SCT_RAM4_SIZE	0x00008000
+
+union c_pct_cfg_sct_ram4 {
+	__u64 qw;
+	struct {
+		__u64 get_comp_cnt  : 11;
+		__u64: 53;
+	};
+};
+
+#define C_PCT_CFG_SCT_CAM_OFFSET(idx)	(0x00070000 + ((idx) * 8))
+#define C_PCT_CFG_SCT_CAM_ENTRIES	4096
+#define C_PCT_CFG_SCT_CAM(idx)	(C_PCT_BASE + C_PCT_CFG_SCT_CAM_OFFSET(idx))
+#define C_PCT_CFG_SCT_CAM_SIZE	0x00008000
+
+union c_pct_cfg_sct_cam {
+	__u64 qw;
+	struct {
+		__u64 dfa        : 32;
+		__u64 vni        : 16;
+		__u64 mcu_group  :  2;
+		__u64: 2;
+		__u64 dscp       :  6;
+		__u64: 2;
+		__u64 vld        :  1;
+		__u64: 3;
+	};
+};
+
+#define C_PCT_CFG_SMT_RAM0_OFFSET(idx)	(0x00080000 + ((idx) * 8))
+#define C_PCT_CFG_SMT_RAM0_ENTRIES	256
+#define C_PCT_CFG_SMT_RAM0(idx)	(C_PCT_BASE + C_PCT_CFG_SMT_RAM0_OFFSET(idx))
+#define C_PCT_CFG_SMT_RAM0_SIZE	0x00000800
+
+union c_pct_cfg_smt_ram0 {
+	__u64 qw;
+	struct {
+		__u64 sw_retry      :  1;
+		__u64 return_code   :  6;
+		__u64 tgt_error     :  1;
+		__u64 req_comp_cnt  : 11;
+		__u64: 5;
+		__u64 mcu           :  7;
+		__u64: 1;
+		__u64 bc            :  4;
+		__u64: 4;
+		__u64 unrestricted  :  1;
+		__u64: 23;
+	};
+};
+
+#define C_PCT_CFG_SMT_RAM1_OFFSET(idx)	(0x00088000 + ((idx) * 8))
+#define C_PCT_CFG_SMT_RAM1_ENTRIES	256
+#define C_PCT_CFG_SMT_RAM1(idx)	(C_PCT_BASE + C_PCT_CFG_SMT_RAM1_OFFSET(idx))
+#define C_PCT_CFG_SMT_RAM1_SIZE	0x00000800
+
+union c_pct_cfg_smt_ram1 {
+	__u64 qw;
+	struct {
+		__u64 last_req      :  1;
+		__u64 req_pend_cnt  : 11;
+		__u64: 52;
+	};
+};
+
+#define C_PCT_CFG_SPT_RAM0_OFFSET(idx)	(0x000a0000 + ((idx) * 64))
+#define C_PCT_CFG_SPT_RAM0_ENTRIES	2048
+#define C_PCT_CFG_SPT_RAM0(idx)	(C_PCT_BASE + C_PCT_CFG_SPT_RAM0_OFFSET(idx))
+#define C_PCT_CFG_SPT_RAM0_SIZE	0x00020000
+
+union c_pct_cfg_spt_ram0 {
+	__u64 qw[6];
+	struct {
+		__u64 sw_recycle             :  1;
+		__u64 hrp                    :  1;
+		__u64 req_mp                 :  1;
+		__u64 req_order              :  1;
+		__u64 eom                    :  1;
+		__u64: 3;
+		__u64 event_send_disable     :  1;
+		__u64 event_success_disable  :  1;
+		__u64 event_ct_send          :  1;
+		__u64 event_ct_reply         :  1;
+		__u64 event_ct_ack           :  1;
+		__u64 event_ct_bytes         :  1;
+		__u64 lpe_gen_rndzvs_get     :  1;
+		__u64: 1;
+		__u64 mlength                : 32;
+		__u64 ptl_list               :  2;
+		__u64: 14;
+		__u64 comp_data;
+		__u64 comp_cq                : 11;
+		__u64: 5;
+		__u64 comp_ct                : 11;
+		__u64: 5;
+		__u64 comp_eq                : 11;
+		__u64: 21;
+		__u64 smt_idx                :  8;
+		__u64: 56;
+		__u64 get_addr               : 57;
+		__u64: 6;
+		__u64 get_with_local_flag    :  1;
+		__u64 get_atc                : 10;
+		__u64: 2;
+		__u64 get_vld                :  1;
+		__u64: 3;
+		__u64 pcp                    :  3;
+		__u64: 1;
+		__u64 bc                     :  4;
+		__u64 mcu                    :  7;
+		__u64: 1;
+		__u64 timestamp              : 20;
+		__u64: 12;
+	};
+};
+
+#define C_PCT_CFG_SPT_RAM1_OFFSET(idx)	(0x000c0000 + ((idx) * 8))
+#define C_PCT_CFG_SPT_RAM1_ENTRIES	2048
+#define C_PCT_CFG_SPT_RAM1(idx)	(C_PCT_BASE + C_PCT_CFG_SPT_RAM1_OFFSET(idx))
+#define C_PCT_CFG_SPT_RAM1_SIZE	0x00004000
+
+union c_pct_cfg_spt_ram1 {
+	__u64 qw;
+	struct {
+		__u64 clr_nxt  : 11;
+		__u64: 5;
+		__u64 sct_idx  : 12;
+		__u64: 36;
+	};
+};
+
+#define C_PCT_CFG_SPT_RAM2_OFFSET(idx)	(0x000c8000 + ((idx) * 8))
+#define C_PCT_CFG_SPT_RAM2_ENTRIES	2048
+#define C_PCT_CFG_SPT_RAM2(idx)	(C_PCT_BASE + C_PCT_CFG_SPT_RAM2_OFFSET(idx))
+#define C_PCT_CFG_SPT_RAM2_SIZE	0x00004000
+
+union c_pct_cfg_spt_ram2 {
+	__u64 qw;
+	struct {
+		__u64 srb_ptr      : 11;
+		__u64: 5;
+		__u64 sct_seqno    : 12;
+		__u64: 4;
+		__u64 return_code  :  6;
+		__u64: 26;
+	};
+};
+
+#define C_PCT_CFG_TCT_RAM_OFFSET(idx)	(0x000d0000 + ((idx) * 8))
+#define C_PCT_CFG_TCT_RAM_ENTRIES	8192
+#define C_PCT_CFG_TCT_RAM(idx)	(C_PCT_BASE + C_PCT_CFG_TCT_RAM_OFFSET(idx))
+#define C_PCT_CFG_TCT_RAM_SIZE	0x00010000
+
+union c_pct_cfg_tct_ram {
+	__u64 qw;
+	struct {
+		__u64 last_active_mst         : 11;
+		__u64: 3;
+		__u64 last_active_mst_is_put  :  1;
+		__u64 last_active_mst_vld     :  1;
+		__u64 clr_seqno               : 12;
+		__u64: 4;
+		__u64 exp_seqno               : 12;
+		__u64: 4;
+		__u64 tc                      :  3;
+		__u64: 13;
+	};
+};
+
+#define C_PCT_CFG_TCT_CAM_OFFSET(idx)	(0x000e0000 + ((idx) * 8))
+#define C_PCT_CFG_TCT_CAM_ENTRIES	8192
+#define C_PCT_CFG_TCT_CAM(idx)	(C_PCT_BASE + C_PCT_CFG_TCT_CAM_OFFSET(idx))
+#define C_PCT_CFG_TCT_CAM_SIZE	0x00010000
+
+union c_pct_cfg_tct_cam {
+	__u64 qw;
+	struct {
+		__u64 sfa_nid  : 20;
+		__u64: 4;
+		__u64 sct_idx  : 12;
+		__u64: 24;
+		__u64 vld      :  1;
+		__u64: 3;
+	};
+};
+
+#define C1_PCT_CFG_TRS_RAM0_OFFSET(idx)	(0x000f0000 + ((idx) * 8))
+#define C1_PCT_CFG_TRS_RAM0_ENTRIES	2048
+#define C1_PCT_CFG_TRS_RAM0(idx)	(C_PCT_BASE + C1_PCT_CFG_TRS_RAM0_OFFSET(idx))
+#define C1_PCT_CFG_TRS_RAM0_SIZE	0x00004000
+
+union c_pct_cfg_trs_ram0 {
+	__u64 qw;
+	struct {
+		__u64 mst_idx              : 11;
+		__u64: 5;
+		__u64 put_not_get          :  1;
+		__u64: 7;
+		__u64 mst_idx_dealloc_vld  :  1;
+		__u64: 39;
+	};
+};
+
+#define C2_PCT_CFG_TRS_RAM0_OFFSET(idx)	(0x000f0000 + ((idx) * 8))
+#define C2_PCT_CFG_TRS_RAM0_ENTRIES	8192
+#define C2_PCT_CFG_TRS_RAM0(idx)	(C_PCT_BASE + C2_PCT_CFG_TRS_RAM0_OFFSET(idx))
+#define C2_PCT_CFG_TRS_RAM0_SIZE	0x00010000
+
+#define C1_PCT_CFG_TRS_RAM1_OFFSET(idx)	(0x00100000 + ((idx) * 32))
+#define C1_PCT_CFG_TRS_RAM1_ENTRIES	2048
+#define C1_PCT_CFG_TRS_RAM1(idx)	(C_PCT_BASE + C1_PCT_CFG_TRS_RAM1_OFFSET(idx))
+#define C1_PCT_CFG_TRS_RAM1_SIZE	0x00010000
+
+union c_pct_cfg_trs_ram1 {
+	__u64 qw[3];
+	struct {
+		__u64 data_lower;
+		__u64 data_upper;
+		__u64 famo_data_vld  :  1;
+		__u64: 7;
+		__u64 return_code    :  6;
+		__u64: 2;
+		__u64 ptl_list       :  2;
+		__u64: 6;
+		__u64 rsp_len        :  5;
+		__u64: 3;
+		__u64 pend_rsp       :  1;
+		__u64: 31;
+	};
+};
+
+#define C2_PCT_CFG_TRS_RAM1_OFFSET(idx)	(0x00100000 + ((idx) * 32))
+#define C2_PCT_CFG_TRS_RAM1_ENTRIES	8192
+#define C2_PCT_CFG_TRS_RAM1(idx)	(C_PCT_BASE + C2_PCT_CFG_TRS_RAM1_OFFSET(idx))
+#define C2_PCT_CFG_TRS_RAM1_SIZE	0x00040000
+
+#define C1_PCT_CFG_TRS_CAM_OFFSET(idx)	(0x00110000 + ((idx) * 8))
+#define C1_PCT_CFG_TRS_CAM_ENTRIES	2048
+#define C1_PCT_CFG_TRS_CAM(idx)	(C_PCT_BASE + C1_PCT_CFG_TRS_CAM_OFFSET(idx))
+#define C1_PCT_CFG_TRS_CAM_SIZE	0x00004000
+
+union c_pct_cfg_trs_cam {
+	__u64 qw;
+	struct {
+		__u64 req_seqno  : 12;
+		__u64: 4;
+		__u64 tct_idx    : 13;
+		__u64: 3;
+		__u64 vld        :  1;
+		__u64: 31;
+	};
+};
+
+#define C2_PCT_CFG_TRS_CAM_OFFSET(idx)	(0x00180000 + ((idx) * 8))
+#define C2_PCT_CFG_TRS_CAM_ENTRIES	8192
+#define C2_PCT_CFG_TRS_CAM(idx)	(C_PCT_BASE + C2_PCT_CFG_TRS_CAM_OFFSET(idx))
+#define C2_PCT_CFG_TRS_CAM_SIZE	0x00010000
+
+#define C1_PCT_CFG_MST_CAM_OFFSET(idx)	(0x00114000 + ((idx) * 8))
+#define C_PCT_CFG_MST_CAM_ENTRIES	2048
+#define C1_PCT_CFG_MST_CAM_ENTRIES	C_PCT_CFG_MST_CAM_ENTRIES
+#define C1_PCT_CFG_MST_CAM(idx)	(C_PCT_BASE + C1_PCT_CFG_MST_CAM_OFFSET(idx))
+#define C_PCT_CFG_MST_CAM_SIZE	0x00004000
+#define C1_PCT_CFG_MST_CAM_SIZE	C_PCT_CFG_MST_CAM_SIZE
+
+union c_pct_cfg_mst_cam {
+	__u64 qw;
+	struct {
+		__u64 msg_id     : 11;
+		__u64: 5;
+		__u64 multi_pkt  :  1;
+		__u64: 7;
+		__u64 sfa_nid    : 20;
+		__u64 vld        :  1;
+		__u64: 19;
+	};
+};
+
+#define C2_PCT_CFG_MST_CAM_OFFSET(idx)	(0x00190000 + ((idx) * 8))
+#define C2_PCT_CFG_MST_CAM_ENTRIES	C_PCT_CFG_MST_CAM_ENTRIES
+#define C2_PCT_CFG_MST_CAM(idx)	(C_PCT_BASE + C2_PCT_CFG_MST_CAM_OFFSET(idx))
+#define C2_PCT_CFG_MST_CAM_SIZE	C_PCT_CFG_MST_CAM_SIZE
+
+#define C1_PCT_CFG_SPT_MISC_INFO_OFFSET(idx)	(0x00118000 + ((idx) * 8))
+#define C_PCT_CFG_SPT_MISC_INFO_ENTRIES	2048
+#define C1_PCT_CFG_SPT_MISC_INFO_ENTRIES	C_PCT_CFG_SPT_MISC_INFO_ENTRIES
+#define C1_PCT_CFG_SPT_MISC_INFO(idx)	(C_PCT_BASE + C1_PCT_CFG_SPT_MISC_INFO_OFFSET(idx))
+#define C_PCT_CFG_SPT_MISC_INFO_SIZE	0x00004000
+#define C1_PCT_CFG_SPT_MISC_INFO_SIZE	C_PCT_CFG_SPT_MISC_INFO_SIZE
+
+union c_pct_cfg_spt_misc_info {
+	__u64 qw;
+	struct {
+		__u64 start_epoch  :  2;
+		__u64: 6;
+		__u64 to_flag      :  1;
+		__u64: 7;
+		__u64 req_try      :  3;
+		__u64: 5;
+		__u64 rsp_status   :  2;
+		__u64: 6;
+		__u64 sw_retry     :  1;
+		__u64: 7;
+		__u64 pkt_sent     :  1;
+		__u64: 7;
+		__u64 vld          :  1;
+		__u64: 15;
+	};
+};
+
+#define C2_PCT_CFG_SPT_MISC_INFO_OFFSET(idx)	(0x00194000 + ((idx) * 8))
+#define C2_PCT_CFG_SPT_MISC_INFO_ENTRIES	C_PCT_CFG_SPT_MISC_INFO_ENTRIES
+#define C2_PCT_CFG_SPT_MISC_INFO(idx)	(C_PCT_BASE + C2_PCT_CFG_SPT_MISC_INFO_OFFSET(idx))
+#define C2_PCT_CFG_SPT_MISC_INFO_SIZE	C_PCT_CFG_SPT_MISC_INFO_SIZE
+
+#define C1_PCT_CFG_SCT_MISC_INFO_OFFSET(idx)	(0x00120000 + ((idx) * 8))
+#define C_PCT_CFG_SCT_MISC_INFO_ENTRIES	4096
+#define C1_PCT_CFG_SCT_MISC_INFO_ENTRIES	C_PCT_CFG_SCT_MISC_INFO_ENTRIES
+#define C1_PCT_CFG_SCT_MISC_INFO(idx)	(C_PCT_BASE + C1_PCT_CFG_SCT_MISC_INFO_OFFSET(idx))
+#define C_PCT_CFG_SCT_MISC_INFO_SIZE	0x00008000
+#define C1_PCT_CFG_SCT_MISC_INFO_SIZE	C_PCT_CFG_SCT_MISC_INFO_SIZE
+
+union c_pct_cfg_sct_misc_info {
+	__u64 qw;
+	struct {
+		__u64 req_redo_vld       :  1;
+		__u64: 7;
+		__u64 deny_new_msg       :  1;
+		__u64: 7;
+		__u64 at_msg_boundary    :  1;
+		__u64: 7;
+		__u64 clr_empty          :  1;
+		__u64: 7;
+		__u64 last_active_epoch  :  2;
+		__u64: 6;
+		__u64 sct_status         :  3;
+		__u64: 21;
+	};
+};
+
+#define C2_PCT_CFG_SCT_MISC_INFO_OFFSET(idx)	(0x00198000 + ((idx) * 8))
+#define C2_PCT_CFG_SCT_MISC_INFO_ENTRIES	C_PCT_CFG_SCT_MISC_INFO_ENTRIES
+#define C2_PCT_CFG_SCT_MISC_INFO(idx)	(C_PCT_BASE + C2_PCT_CFG_SCT_MISC_INFO_OFFSET(idx))
+#define C2_PCT_CFG_SCT_MISC_INFO_SIZE	C_PCT_CFG_SCT_MISC_INFO_SIZE
+
+#define C1_PCT_CFG_TCT_MISC_INFO_OFFSET(idx)	(0x00130000 + ((idx) * 8))
+#define C1_PCT_CFG_TCT_MISC_INFO_ENTRIES	8192
+#define C1_PCT_CFG_TCT_MISC_INFO(idx)	(C_PCT_BASE + C1_PCT_CFG_TCT_MISC_INFO_OFFSET(idx))
+#define C1_PCT_CFG_TCT_MISC_INFO_SIZE	0x00010000
+
+union c1_pct_cfg_tct_misc_info {
+	__u64 qw;
+	struct {
+		__u64 last_active_epoch  :  2;
+		__u64: 6;
+		__u64 to_flag            :  1;
+		__u64: 7;
+		__u64 vld                :  1;
+		__u64: 47;
+	};
+};
+
+#define C2_PCT_CFG_TCT_MISC_INFO_OFFSET(idx)	(0x001a0000 + ((idx) * 8))
+#define C2_PCT_CFG_TCT_MISC_INFO_ENTRIES	8192
+#define C2_PCT_CFG_TCT_MISC_INFO(idx)	(C_PCT_BASE + C2_PCT_CFG_TCT_MISC_INFO_OFFSET(idx))
+#define C2_PCT_CFG_TCT_MISC_INFO_SIZE	0x00010000
+
+union c2_pct_cfg_tct_misc_info {
+	__u64 qw;
+	struct {
+		__u64 last_active_epoch  :  2;
+		__u64: 6;
+		__u64 to_flag            :  1;
+		__u64: 3;
+		__u64 closing            :  1;
+		__u64: 3;
+		__u64 vld                :  1;
+		__u64: 47;
+	};
+};
+
+#define C1_PCT_CFG_SCT_INVALIDATE_OFFSET(idx)	(0x00140000 + ((idx) * 8))
+#define C_PCT_CFG_SCT_INVALIDATE_ENTRIES	4096
+#define C1_PCT_CFG_SCT_INVALIDATE_ENTRIES	C_PCT_CFG_SCT_INVALIDATE_ENTRIES
+#define C1_PCT_CFG_SCT_INVALIDATE(idx)	(C_PCT_BASE + C1_PCT_CFG_SCT_INVALIDATE_OFFSET(idx))
+#define C_PCT_CFG_SCT_INVALIDATE_SIZE	0x00008000
+#define C1_PCT_CFG_SCT_INVALIDATE_SIZE	C_PCT_CFG_SCT_INVALIDATE_SIZE
+
+union c_pct_cfg_sct_invalidate {
+	__u64 qw;
+	struct {
+		__u64 invalidate  :  1;
+		__u64: 63;
+	};
+};
+
+#define C2_PCT_CFG_SCT_INVALIDATE_OFFSET(idx)	(0x001d0000 + ((idx) * 8))
+#define C2_PCT_CFG_SCT_INVALIDATE_ENTRIES	C_PCT_CFG_SCT_INVALIDATE_ENTRIES
+#define C2_PCT_CFG_SCT_INVALIDATE(idx)	(C_PCT_BASE + C2_PCT_CFG_SCT_INVALIDATE_OFFSET(idx))
+#define C2_PCT_CFG_SCT_INVALIDATE_SIZE	C_PCT_CFG_SCT_INVALIDATE_SIZE
+
+#define C1_PCT_CFG_TCT_INVALIDATE_OFFSET(idx)	(0x00150000 + ((idx) * 8))
+#define C_PCT_CFG_TCT_INVALIDATE_ENTRIES	8192
+#define C1_PCT_CFG_TCT_INVALIDATE_ENTRIES	C_PCT_CFG_TCT_INVALIDATE_ENTRIES
+#define C1_PCT_CFG_TCT_INVALIDATE(idx)	(C_PCT_BASE + C1_PCT_CFG_TCT_INVALIDATE_OFFSET(idx))
+#define C_PCT_CFG_TCT_INVALIDATE_SIZE	0x00010000
+#define C1_PCT_CFG_TCT_INVALIDATE_SIZE	C_PCT_CFG_TCT_INVALIDATE_SIZE
+
+union c_pct_cfg_tct_invalidate {
+	__u64 qw;
+	struct {
+		__u64 invalidate  :  1;
+		__u64: 63;
+	};
+};
+
+#define C2_PCT_CFG_TCT_INVALIDATE_OFFSET(idx)	(0x001b0000 + ((idx) * 8))
+#define C2_PCT_CFG_TCT_INVALIDATE_ENTRIES	C_PCT_CFG_TCT_INVALIDATE_ENTRIES
+#define C2_PCT_CFG_TCT_INVALIDATE(idx)	(C_PCT_BASE + C2_PCT_CFG_TCT_INVALIDATE_OFFSET(idx))
+#define C2_PCT_CFG_TCT_INVALIDATE_SIZE	C_PCT_CFG_TCT_INVALIDATE_SIZE
+
+#define C1_PCT_CFG_TRS_INVALIDATE_OFFSET(idx)	(0x00168000 + ((idx) * 8))
+#define C1_PCT_CFG_TRS_INVALIDATE_ENTRIES	2048
+#define C1_PCT_CFG_TRS_INVALIDATE(idx)	(C_PCT_BASE + C1_PCT_CFG_TRS_INVALIDATE_OFFSET(idx))
+#define C1_PCT_CFG_TRS_INVALIDATE_SIZE	0x00004000
+
+union c_pct_cfg_trs_invalidate {
+	__u64 qw;
+	struct {
+		__u64 invalidate  :  1;
+		__u64: 63;
+	};
+};
+
+#define C2_PCT_CFG_TRS_INVALIDATE_OFFSET(idx)	(0x001c0000 + ((idx) * 8))
+#define C2_PCT_CFG_TRS_INVALIDATE_ENTRIES	8192
+#define C2_PCT_CFG_TRS_INVALIDATE(idx)	(C_PCT_BASE + C2_PCT_CFG_TRS_INVALIDATE_OFFSET(idx))
+#define C2_PCT_CFG_TRS_INVALIDATE_SIZE	0x00010000
+
+#define C1_PCT_CFG_MST_INVALIDATE_OFFSET(idx)	(0x00170000 + ((idx) * 8))
+#define C_PCT_CFG_MST_INVALIDATE_ENTRIES	2048
+#define C1_PCT_CFG_MST_INVALIDATE_ENTRIES	C_PCT_CFG_MST_INVALIDATE_ENTRIES
+#define C1_PCT_CFG_MST_INVALIDATE(idx)	(C_PCT_BASE + C1_PCT_CFG_MST_INVALIDATE_OFFSET(idx))
+#define C_PCT_CFG_MST_INVALIDATE_SIZE	0x00004000
+#define C1_PCT_CFG_MST_INVALIDATE_SIZE	C_PCT_CFG_MST_INVALIDATE_SIZE
+
+union c_pct_cfg_mst_invalidate {
+	__u64 qw;
+	struct {
+		__u64 invalidate  :  1;
+		__u64: 63;
+	};
+};
+
+#define C2_PCT_CFG_MST_INVALIDATE_OFFSET(idx)	(0x001d8000 + ((idx) * 8))
+#define C2_PCT_CFG_MST_INVALIDATE_ENTRIES	C_PCT_CFG_MST_INVALIDATE_ENTRIES
+#define C2_PCT_CFG_MST_INVALIDATE(idx)	(C_PCT_BASE + C2_PCT_CFG_MST_INVALIDATE_OFFSET(idx))
+#define C2_PCT_CFG_MST_INVALIDATE_SIZE	C_PCT_CFG_MST_INVALIDATE_SIZE
+
+#define C1_PCT_CFG_SRB_LINK_LIST_OFFSET(idx)	(0x00178000 + ((idx) * 8))
+#define C_PCT_CFG_SRB_LINK_LIST_ENTRIES	2048
+#define C1_PCT_CFG_SRB_LINK_LIST_ENTRIES	C_PCT_CFG_SRB_LINK_LIST_ENTRIES
+#define C1_PCT_CFG_SRB_LINK_LIST(idx)	(C_PCT_BASE + C1_PCT_CFG_SRB_LINK_LIST_OFFSET(idx))
+#define C_PCT_CFG_SRB_LINK_LIST_SIZE	0x00004000
+#define C1_PCT_CFG_SRB_LINK_LIST_SIZE	C_PCT_CFG_SRB_LINK_LIST_SIZE
+
+union c_pct_cfg_srb_link_list {
+	__u64 qw;
+	struct {
+		__u64 tail      :  1;
+		__u64: 7;
+		__u64 next_ptr  : 11;
+		__u64: 45;
+	};
+};
+
+#define C2_PCT_CFG_SRB_LINK_LIST_OFFSET(idx)	(0x001e0000 + ((idx) * 8))
+#define C2_PCT_CFG_SRB_LINK_LIST_ENTRIES	C_PCT_CFG_SRB_LINK_LIST_ENTRIES
+#define C2_PCT_CFG_SRB_LINK_LIST(idx)	(C_PCT_BASE + C2_PCT_CFG_SRB_LINK_LIST_OFFSET(idx))
+#define C2_PCT_CFG_SRB_LINK_LIST_SIZE	C_PCT_CFG_SRB_LINK_LIST_SIZE
+
+#define C_PCT_CFG_SRB_CELL_DATA_OFFSET(idx)	(0x00200000 + ((idx) * 128))
+#define C_PCT_CFG_SRB_CELL_DATA_ENTRIES	8192
+#define C_PCT_CFG_SRB_CELL_DATA(idx)	(C_PCT_BASE + C_PCT_CFG_SRB_CELL_DATA_OFFSET(idx))
+#define C_PCT_CFG_SRB_CELL_DATA_SIZE	0x00100000
+
+union c_pct_cfg_srb_cell_data {
+	__u64 qw[9];
+	struct {
+		__u64 byte_len  : 14;
+		__u64: 2;
+		__u64 fmt       :  1;
+		__u64 eopb      :  1;
+		__u64 eop       :  1;
+		__u64 sop       :  1;
+		__u64: 44;
+		__u64 word0;
+		__u64 word1;
+		__u64 word2;
+		__u64 word3;
+		__u64 word4;
+		__u64 word5;
+		__u64 word6;
+		__u64 word7;
+	};
+};
+
+#define C_PCT_PRF_SCT_STATUS_OFFSET	0x00300100
+#define C_PCT_PRF_SCT_STATUS	(C_PCT_BASE + C_PCT_PRF_SCT_STATUS_OFFSET)
+#define C_PCT_PRF_SCT_STATUS_SIZE	0x00000008
+
+union c_pct_prf_sct_status {
+	__u64 qw;
+	struct {
+		__u64 sct_in_use      : 13;
+		__u64: 19;
+		__u64 max_sct_in_use  : 13;
+		__u64: 19;
+	};
+};
+
+#define C_PCT_PRF_TCT_STATUS_OFFSET	0x00300108
+#define C_PCT_PRF_TCT_STATUS	(C_PCT_BASE + C_PCT_PRF_TCT_STATUS_OFFSET)
+#define C_PCT_PRF_TCT_STATUS_SIZE	0x00000008
+
+union c_pct_prf_tct_status {
+	__u64 qw;
+	struct {
+		__u64 tct_in_use      : 14;
+		__u64: 18;
+		__u64 max_tct_in_use  : 14;
+		__u64: 18;
+	};
+};
+
+#define C_PCT_PRF_SPT_STATUS_OFFSET	0x00300110
+#define C_PCT_PRF_SPT_STATUS	(C_PCT_BASE + C_PCT_PRF_SPT_STATUS_OFFSET)
+#define C_PCT_PRF_SPT_STATUS_SIZE	0x00000008
+
+union c_pct_prf_spt_status {
+	__u64 qw;
+	struct {
+		__u64 spt_in_use      : 12;
+		__u64: 20;
+		__u64 max_spt_in_use  : 12;
+		__u64: 20;
+	};
+};
+
+#define C_PCT_PRF_SMT_STATUS_OFFSET	0x00300118
+#define C_PCT_PRF_SMT_STATUS	(C_PCT_BASE + C_PCT_PRF_SMT_STATUS_OFFSET)
+#define C_PCT_PRF_SMT_STATUS_SIZE	0x00000008
+
+union c_pct_prf_smt_status {
+	__u64 qw;
+	struct {
+		__u64 smt_in_use      :  9;
+		__u64: 23;
+		__u64 max_smt_in_use  :  9;
+		__u64: 23;
+	};
+};
+
+#define C1_PCT_PRF_TRS_STATUS_OFFSET	0x00300120
+#define C1_PCT_PRF_TRS_STATUS	(C_PCT_BASE + C1_PCT_PRF_TRS_STATUS_OFFSET)
+#define C1_PCT_PRF_TRS_STATUS_SIZE	0x00000008
+
+union c1_pct_prf_trs_status {
+	__u64 qw;
+	struct {
+		__u64 trs_in_use      : 12;
+		__u64: 20;
+		__u64 max_trs_in_use  : 12;
+		__u64: 20;
+	};
+};
+
+#define C2_PCT_PRF_TRS_STATUS_OFFSET	0x00300120
+#define C2_PCT_PRF_TRS_STATUS	(C_PCT_BASE + C2_PCT_PRF_TRS_STATUS_OFFSET)
+#define C2_PCT_PRF_TRS_STATUS_SIZE	0x00000008
+
+union c2_pct_prf_trs_status {
+	__u64 qw;
+	struct {
+		__u64 trs_in_use      : 14;
+		__u64: 18;
+		__u64 max_trs_in_use  : 14;
+		__u64: 18;
+	};
+};
+
+#define C_PCT_PRF_SRB_STATUS_OFFSET	0x00300128
+#define C_PCT_PRF_SRB_STATUS	(C_PCT_BASE + C_PCT_PRF_SRB_STATUS_OFFSET)
+#define C_PCT_PRF_SRB_STATUS_SIZE	0x00000008
+
+union c_pct_prf_srb_status {
+	__u64 qw;
+	struct {
+		__u64 srb_in_use      : 12;
+		__u64: 20;
+		__u64 max_srb_in_use  : 12;
+		__u64: 20;
+	};
+};
+
+#define C_PCT_PRF_MST_STATUS_OFFSET	0x00300130
+#define C_PCT_PRF_MST_STATUS	(C_PCT_BASE + C_PCT_PRF_MST_STATUS_OFFSET)
+#define C_PCT_PRF_MST_STATUS_SIZE	0x00000008
+
+union c_pct_prf_mst_status {
+	__u64 qw;
+	struct {
+		__u64 mst_in_use      : 12;
+		__u64: 20;
+		__u64 max_mst_in_use  : 12;
+		__u64: 20;
+	};
+};
+
+#define C_PI_CFG_CRNC_OFFSET	0x00000000
+#define C_PI_CFG_CRNC	(C_PI_BASE + C_PI_CFG_CRNC_OFFSET)
+#define C_PI_CFG_CRNC_SIZE	0x00000008
+
+union c_pi_cfg_crnc {
+	__u64 qw;
+	struct {
+		__u64 csr_timeout   :  8;
+		__u64 mcast_id      : 10;
+		__u64: 1;
+		__u64 mcast_enable  :  1;
+		__u64 mcast_mask    : 10;
+		__u64: 34;
+	};
+};
+
+#define C_PI_CFG_RT_OFFSET_OFFSET	0x00000020
+#define C_PI_CFG_RT_OFFSET	(C_PI_BASE + C_PI_CFG_RT_OFFSET_OFFSET)
+#define C_PI_CFG_RT_OFFSET_SIZE	0x00000008
+
+union c_pi_cfg_rt_offset {
+	__u64 qw;
+	struct {
+		__u64 seconds  : 48;
+		__u64: 16;
+	};
+};
+
+#define C_PI_MSC_SHADOW_ACTION_OFFSET	0x00000038
+#define C_PI_MSC_SHADOW_ACTION	(C_PI_BASE + C_PI_MSC_SHADOW_ACTION_OFFSET)
+#define C_PI_MSC_SHADOW_ACTION_SIZE	0x00000008
+#define C_PI_MSC_SHADOW_OFFSET	0x00000040
+#define C_PI_MSC_SHADOW	(C_PI_BASE + C_PI_MSC_SHADOW_OFFSET)
+#define C_PI_MSC_SHADOW_SIZE	0x00000010
+
+union c_pi_msc_shadow {
+	__u64 qw[2];
+};
+
+#define C_PI_ERR_ELAPSED_TIME_OFFSET	0x00000100
+#define C_PI_ERR_ELAPSED_TIME	(C_PI_BASE + C_PI_ERR_ELAPSED_TIME_OFFSET)
+#define C_PI_ERR_ELAPSED_TIME_SIZE	0x00000008
+
+union c_pi_err_elapsed_time {
+	__u64 qw;
+	struct {
+		__u64 nanoseconds  : 30;
+		__u64 seconds      : 34;
+	};
+};
+
+#define C_PI_ERR_FLG_OFFSET	0x00000108
+#define C_PI_ERR_FLG	(C_PI_BASE + C_PI_ERR_FLG_OFFSET)
+#define C_PI_ERR_FLG_SIZE	0x00000008
+
+union c_pi_err_flg {
+	__u64 qw;
+	struct {
+		__u64 sw_diag                         :  1;
+		__u64 crnc_ring_sync_error            :  1;
+		__u64 crnc_ring_ecc_sbe               :  1;
+		__u64 crnc_ring_ecc_mbe               :  1;
+		__u64 crnc_ring_cmd_unknown           :  1;
+		__u64 crnc_csr_cmd_unknown            :  1;
+		__u64 crnc_csr_cmd_incomplete         :  1;
+		__u64 crnc_buf_ecc_sbe                :  1;
+		__u64 crnc_buf_ecc_mbe                :  1;
+		__u64: 7;
+		__u64 acxt_cor                        :  1;
+		__u64 acxt_ucor                       :  1;
+		__u64 sriovt_cor                      :  1;
+		__u64 sriovt_ucor                     :  1;
+		__u64 dmac_desc_cor                   :  1;
+		__u64 dmac_desc_ucor                  :  1;
+		__u64 pri_mb_xlat_rtrgt_fifo_cor      :  4;
+		__u64 pri_mb_xlat_rtrgt_fifo_ucor     :  4;
+		__u64 pri_rarb_xlat_rtrgt_fifo_cor    :  4;
+		__u64 pri_rarb_xlat_rtrgt_fifo_ucor   :  4;
+		__u64 pri_rarb_xlat_rbyp_fifo_cor     :  4;
+		__u64 pri_rarb_xlat_rbyp_fifo_ucor    :  4;
+		__u64 pti_tarb_xlat_pipe0_hdr_cor     :  1;
+		__u64 pti_tarb_xlat_pipe0_hdr_ucor    :  1;
+		__u64 pti_tarb_xlat_pipe3_hdr_cor     :  1;
+		__u64 pti_tarb_xlat_pipe3_hdr_ucor    :  1;
+		__u64 pti_tarb_xlat_pipe3_data_cor    :  1;
+		__u64 pti_tarb_xlat_pipe3_data_ucor   :  1;
+		__u64 pti_tarb_xlat_unexpected_dv     :  1;
+		__u64 pti_tarb_xlat_ac_en_error       :  1;
+		__u64 pti_tarb_xlat_cfg_vf_en_error   :  1;
+		__u64 pti_tarb_xlat_cfg_vf_num_error  :  1;
+		__u64 pti_tarb_xlat_cfg_vf_bme_error  :  1;
+		__u64 pti_tarb_xlat_cfg_bme_error     :  1;
+		__u64 pti_tarb_xlat_cfg_amo_error     :  1;
+		__u64: 3;
+		__u64 uc_attention                    :  2;
+	};
+};
+
+#define C_PI_ERR_FIRST_FLG_OFFSET	0x00000110
+#define C_PI_ERR_FIRST_FLG	(C_PI_BASE + C_PI_ERR_FIRST_FLG_OFFSET)
+#define C_PI_ERR_FIRST_FLG_SIZE	0x00000008
+#define C_PI_ERR_FIRST_FLG_TS_OFFSET	0x00000118
+#define C_PI_ERR_FIRST_FLG_TS	(C_PI_BASE + C_PI_ERR_FIRST_FLG_TS_OFFSET)
+#define C_PI_ERR_FIRST_FLG_TS_SIZE	0x00000008
+#define C_PI_ERR_CLR_OFFSET	0x00000120
+#define C_PI_ERR_CLR	(C_PI_BASE + C_PI_ERR_CLR_OFFSET)
+#define C_PI_ERR_CLR_SIZE	0x00000008
+#define C_PI_ERR_IRQA_MSK_OFFSET	0x00000128
+#define C_PI_ERR_IRQA_MSK	(C_PI_BASE + C_PI_ERR_IRQA_MSK_OFFSET)
+#define C_PI_ERR_IRQA_MSK_SIZE	0x00000008
+#define C_PI_ERR_IRQB_MSK_OFFSET	0x00000130
+#define C_PI_ERR_IRQB_MSK	(C_PI_BASE + C_PI_ERR_IRQB_MSK_OFFSET)
+#define C_PI_ERR_IRQB_MSK_SIZE	0x00000008
+#define C_PI_ERR_INFO_MSK_OFFSET	0x00000140
+#define C_PI_ERR_INFO_MSK	(C_PI_BASE + C_PI_ERR_INFO_MSK_OFFSET)
+#define C_PI_ERR_INFO_MSK_SIZE	0x00000008
+#define C_PI_ERR_INFO_MEM_OFFSET	0x00000180
+#define C_PI_ERR_INFO_MEM	(C_PI_BASE + C_PI_ERR_INFO_MEM_OFFSET)
+#define C_PI_ERR_INFO_MEM_SIZE	0x00000008
+
+union c_pi_err_info_mem {
+	__u64 qw;
+	struct {
+		__u64 cor_syndrome       : 11;
+		__u64: 1;
+		__u64 cor_address        : 13;
+		__u64: 1;
+		__u64 cor_mem_id         :  5;
+		__u64 cor_csr_detected   :  1;
+		__u64 ucor_syndrome      : 11;
+		__u64: 1;
+		__u64 ucor_address       : 13;
+		__u64: 1;
+		__u64 ucor_mem_id        :  5;
+		__u64 ucor_csr_detected  :  1;
+	};
+};
+
+#define C_PI_ERR_INFO_TARB_OFFSET	0x00000190
+#define C_PI_ERR_INFO_TARB	(C_PI_BASE + C_PI_ERR_INFO_TARB_OFFSET)
+#define C_PI_ERR_INFO_TARB_SIZE	0x00000010
+
+union c_pi_err_info_tarb {
+	__u64 qw[2];
+	struct {
+		__u64 msg_type   :  4;
+		__u64 acid       : 10;
+		__u64 msg_49_0   : 50;
+		__u64 msg_84_50  : 35;
+		__u64 source     :  3;
+		__u64: 26;
+	};
+};
+
+#define C_PI_EXT_ERR_FLG_OFFSET	0x00000208
+#define C_PI_EXT_ERR_FLG	(C_PI_BASE + C_PI_EXT_ERR_FLG_OFFSET)
+#define C_PI_EXT_ERR_FLG_SIZE	0x00000008
+
+union c_pi_ext_err_flg {
+	__u64 qw;
+	struct {
+		__u64 sw_diag                                     :  1;
+		__u64 pri_mb_xlat_rtrgt_abort_error               :  1;
+		__u64 pri_mb_xlat_rtrgt_hdr_parity_error          :  1;
+		__u64 pri_mb_xlat_rtrgt_data_parity_error         :  1;
+		__u64 pri_mb_xlat_axi_wr_decerr                   :  1;
+		__u64 pri_mb_xlat_axi_wr_slverr                   :  1;
+		__u64 pri_mb_xlat_axi_rd_decerr                   :  1;
+		__u64 pri_mb_xlat_axi_rd_slverr                   :  1;
+		__u64 pri_mb_xlat_axi_rd_parity_error             :  1;
+		__u64 pri_mb_xlat_msg_tlp_discard                 :  1;
+		__u64 pri_mb_xlat_unexpected_np_tlp               :  1;
+		__u64 pri_mb_xlat_unexpected_tlp                  :  1;
+		__u64 pri_mb_xlat_pf_addr_error                   :  1;
+		__u64 pri_mb_xlat_vf_addr_error                   :  1;
+		__u64 pri_mb_xlat_rom_wr_error                    :  1;
+		__u64 pri_mb_xlat_partial_discard                 :  1;
+		__u64 pri_mb_xlat_rtrgt_fifo_underrun             :  1;
+		__u64 pri_mb_xlat_rtrgt_rdy_fifo_underrun         :  1;
+		__u64 pri_mb_xlat_comp_fifo_overrun               :  1;
+		__u64 pri_mb_xlat_comp_ca                         :  1;
+		__u64 pri_mb_xlat_comp_ur                         :  1;
+		__u64 pri_rarb_xlat_rtrgt_abort_error             :  1;
+		__u64 pri_rarb_xlat_rtrgt_hdr_parity_error        :  1;
+		__u64 pri_rarb_xlat_rtrgt_data_parity_error       :  1;
+		__u64 pri_rarb_xlat_rtrgt_unexpected_tlp          :  1;
+		__u64 pri_rarb_xlat_rtrgt_unexpected_msg          :  1;
+		__u64 pri_rarb_xlat_rtrgt_vf_addr_error           :  1;
+		__u64 pri_rarb_xlat_rtrgt_vf_en_num_error         :  1;
+		__u64 pri_rarb_xlat_rtrgt_vf_en_error             :  1;
+		__u64 pri_rarb_xlat_rtrgt_inv_req_vf_error        :  1;
+		__u64 pri_rarb_xlat_rtrgt_inv_req_dev_id_error    :  1;
+		__u64 pri_rarb_xlat_rtrgt_prgr_vf_error           :  1;
+		__u64 pri_rarb_xlat_rtrgt_prgr_dev_id_error       :  1;
+		__u64 pri_rarb_xlat_rtrgt_fifo_underrun           :  1;
+		__u64 pri_rarb_xlat_rtrgt_rdy_fifo_underrun       :  1;
+		__u64 pri_rarb_xlat_rbyp_abort_error              :  1;
+		__u64 pri_rarb_xlat_rbyp_hdr_parity_error         :  1;
+		__u64 pri_rarb_xlat_rbyp_data_parity_error        :  1;
+		__u64 pri_rarb_xlat_rbyp_tag_error                :  1;
+		__u64 pri_rarb_xlat_rbyp_unexpected_tlp_error     :  1;
+		__u64 pri_rarb_xlat_rbyp_fifo_underrun            :  1;
+		__u64 pri_rarb_xlat_rbyp_rdy_fifo_underrun        :  1;
+		__u64 pti_tarb_xlat_p_fifo_overrun                :  1;
+		__u64 pti_tarb_xlat_np_fifo_overrun               :  1;
+		__u64 pti_tarb_xlat_ord_fifo_overrun              :  1;
+		__u64 pti_tarb_xlat_np_err_fifo_overrun           :  1;
+		__u64 pti_tarb_xlat_np_err_fifo_underrun          :  1;
+		__u64 pti_tarb_xlat_pti_pri_cpl_to_fifo_underrun  :  1;
+		__u64 dmac_axi_rd_decerr                          :  1;
+		__u64 dmac_axi_rd_slverr                          :  1;
+		__u64 dmac_axi_rd_parity_error                    :  1;
+		__u64 ahb_overwrite                               :  1;
+		__u64 ahb_resp_err                                :  1;
+		__u64: 11;
+	};
+};
+
+#define C_PI_EXT_ERR_FIRST_FLG_OFFSET	0x00000210
+#define C_PI_EXT_ERR_FIRST_FLG	(C_PI_BASE + C_PI_EXT_ERR_FIRST_FLG_OFFSET)
+#define C_PI_EXT_ERR_FIRST_FLG_SIZE	0x00000008
+#define C_PI_EXT_ERR_FIRST_FLG_TS_OFFSET	0x00000218
+#define C_PI_EXT_ERR_FIRST_FLG_TS	(C_PI_BASE + C_PI_EXT_ERR_FIRST_FLG_TS_OFFSET)
+#define C_PI_EXT_ERR_FIRST_FLG_TS_SIZE	0x00000008
+#define C_PI_EXT_ERR_CLR_OFFSET	0x00000220
+#define C_PI_EXT_ERR_CLR	(C_PI_BASE + C_PI_EXT_ERR_CLR_OFFSET)
+#define C_PI_EXT_ERR_CLR_SIZE	0x00000008
+#define C_PI_EXT_ERR_IRQA_MSK_OFFSET	0x00000228
+#define C_PI_EXT_ERR_IRQA_MSK	(C_PI_BASE + C_PI_EXT_ERR_IRQA_MSK_OFFSET)
+#define C_PI_EXT_ERR_IRQA_MSK_SIZE	0x00000008
+#define C_PI_EXT_ERR_IRQB_MSK_OFFSET	0x00000230
+#define C_PI_EXT_ERR_IRQB_MSK	(C_PI_BASE + C_PI_EXT_ERR_IRQB_MSK_OFFSET)
+#define C_PI_EXT_ERR_IRQB_MSK_SIZE	0x00000008
+#define C_PI_EXT_ERR_INFO_MSK_OFFSET	0x00000240
+#define C_PI_EXT_ERR_INFO_MSK	(C_PI_BASE + C_PI_EXT_ERR_INFO_MSK_OFFSET)
+#define C_PI_EXT_ERR_INFO_MSK_SIZE	0x00000008
+#define C_PI_ERR_INFO_RTRGT_OFFSET	0x00000250
+#define C_PI_ERR_INFO_RTRGT	(C_PI_BASE + C_PI_ERR_INFO_RTRGT_OFFSET)
+#define C_PI_ERR_INFO_RTRGT_SIZE	0x00000018
+
+union c_pi_err_info_rtrgt {
+	__u64 qw[3];
+	struct {
+		__u64 addr;
+		__u64 tlp_type      :  5;
+		__u64 fmt           :  2;
+		__u64 tc            :  3;
+		__u64 attr          :  3;
+		__u64 td            :  1;
+		__u64 th            :  1;
+		__u64 poisoned      :  1;
+		__u64 reqid         : 16;
+		__u64 tag           : 10;
+		__u64 dw_len        : 10;
+		__u64 first_be      :  4;
+		__u64 last_be       :  4;
+		__u64 ats           :  2;
+		__u64 ph            :  2;
+		__u64 st            :  8;
+		__u64 vfunc_num     :  6;
+		__u64 vfunc_active  :  1;
+		__u64 nw            :  1;
+		__u64 ecrc_err      :  1;
+		__u64 dllp_abort    :  1;
+		__u64 tlp_abort     :  1;
+		__u64: 13;
+		__u64 tlp_prfx      : 32;
+	};
+};
+
+#define C_PI_ERR_INFO_RBYP_OFFSET	0x00000280
+#define C_PI_ERR_INFO_RBYP	(C_PI_BASE + C_PI_ERR_INFO_RBYP_OFFSET)
+#define C_PI_ERR_INFO_RBYP_SIZE	0x00000018
+
+union c_pi_err_info_rbyp {
+	__u64 qw[3];
+	struct {
+		__u64 addr          :  7;
+		__u64: 9;
+		__u64 ats           :  2;
+		__u64 ph            :  2;
+		__u64: 12;
+		__u64 byte_cnt      : 12;
+		__u64: 4;
+		__u64 completer_id  : 16;
+		__u64 tlp_type      :  5;
+		__u64 fmt           :  2;
+		__u64 tc            :  3;
+		__u64 attr          :  3;
+		__u64 td            :  1;
+		__u64 th            :  1;
+		__u64 poisoned      :  1;
+		__u64 reqid         : 16;
+		__u64 tag           : 10;
+		__u64 dw_len        : 10;
+		__u64 cpl_status    :  3;
+		__u64 cpl_last      :  1;
+		__u64 bcm           :  1;
+		__u64 ecrc_err      :  1;
+		__u64 dllp_abort    :  1;
+		__u64 tlp_abort     :  1;
+		__u64: 4;
+		__u64 tlp_prfx      : 32;
+		__u64: 32;
+	};
+};
+
+#define C_PI_ERR_INFO_DMAC_OFFSET	0x000002a0
+#define C_PI_ERR_INFO_DMAC	(C_PI_BASE + C_PI_ERR_INFO_DMAC_OFFSET)
+#define C_PI_ERR_INFO_DMAC_SIZE	0x00000008
+
+union c_pi_err_info_dmac {
+	__u64 qw;
+	struct {
+		__u64 desc_addr  : 10;
+		__u64: 54;
+	};
+};
+
+#define C_PI_CFG_PRI_SRIOV_OFFSET	0x00001100
+#define C_PI_CFG_PRI_SRIOV	(C_PI_BASE + C_PI_CFG_PRI_SRIOV_OFFSET)
+#define C_PI_CFG_PRI_SRIOV_SIZE	0x00000008
+
+union c_pi_cfg_pri_sriov {
+	__u64 qw;
+	struct {
+		__u64 vf_offset  : 16;
+		__u64 vf_stride  : 16;
+		__u64: 32;
+	};
+};
+
+#define C_PI_CFG_DMAC_CPL_ADDR_OFFSET	0x00002000
+#define C_PI_CFG_DMAC_CPL_ADDR	(C_PI_BASE + C_PI_CFG_DMAC_CPL_ADDR_OFFSET)
+#define C_PI_CFG_DMAC_CPL_ADDR_SIZE	0x00000008
+
+union c_pi_cfg_dmac_cpl_addr {
+	__u64 qw;
+	struct {
+		__u64: 3;
+		__u64 address  : 61;
+	};
+};
+
+#define C_PI_CFG_DMAC_OFFSET	0x00002008
+#define C_PI_CFG_DMAC	(C_PI_BASE + C_PI_CFG_DMAC_OFFSET)
+#define C_PI_CFG_DMAC_SIZE	0x00000008
+
+union c_pi_cfg_dmac {
+	__u64 qw;
+	struct {
+		__u64 desc_index        : 10;
+		__u64: 2;
+		__u64 enable            :  1;
+		__u64 start             :  1;
+		__u64 done              :  1;
+		__u64 cpl_event_enable  :  1;
+		__u64 status            :  2;
+		__u64 irq_on_done       :  1;
+		__u64 irq_on_error      :  1;
+		__u64: 44;
+	};
+};
+
+#define C_PI_CFG_SRIOVT_OFFSET(idx)	(0x00010000 + ((idx) * 8))
+#define C_PI_CFG_SRIOVT_ENTRIES	6144
+#define C_PI_CFG_SRIOVT(idx)	(C_PI_BASE + C_PI_CFG_SRIOVT_OFFSET(idx))
+#define C_PI_CFG_SRIOVT_SIZE	0x0000c000
+
+union c_pi_cfg_sriovt {
+	__u64 qw;
+	struct {
+		__u64 vf_num  :  6;
+		__u64 vf_en   :  1;
+		__u64: 57;
+	};
+};
+
+#define C_PI_CFG_ACXT_OFFSET(idx)	(0x00020000 + ((idx) * 8))
+#define C_PI_CFG_ACXT_ENTRIES	1024
+#define C_PI_CFG_ACXT(idx)	(C_PI_BASE + C_PI_CFG_ACXT_OFFSET(idx))
+#define C_PI_CFG_ACXT_SIZE	0x00002000
+
+union c_pi_cfg_acxt {
+	__u64 qw;
+	struct {
+		__u64 ac_en               :  1;
+		__u64 vf_en               :  1;
+		__u64 vf_num              :  6;
+		__u64 steering_tag        :  8;
+		__u64 ph_en               :  1;
+		__u64 phints              :  2;
+		__u64 no_snoop            :  1;
+		__u64 mem_rd_ro           :  1;
+		__u64 flush_req_ro        :  1;
+		__u64 translation_req_ro  :  1;
+		__u64 fetching_amo_ro     :  1;
+		__u64 ido                 :  1;
+		__u64 at1                 :  1;
+		__u64 pasid_en            :  1;
+		__u64 pasid               : 20;
+		__u64 pasid_rsvd          :  2;
+		__u64 pasid_er            :  1;
+		__u64 pasid_pmr           :  1;
+		__u64 reserved            : 13;
+	};
+};
+
+#define C_PI_CFG_DMAC_DESC_OFFSET(idx)	(0x00030000 + ((idx) * 16))
+#define C_PI_CFG_DMAC_DESC_ENTRIES	1024
+/*
+ * Since there are an 'abundance' of DMAC descriptors, some of them have
+ * been repurposed & reserved as 'scratch registers' for other purposes.
+ *
+ * Such as for communication between UC & HOST (see cass_uc.c).
+ *
+ * The rule is a contiguous block of descriptors from
+ *
+ *	I ... (C_PI_CFG_DMAC_DESC_ENTRIES - 1)
+ *
+ * will be the reserved pool not to be used by the DMAC for DMAing.
+ */
+#define C_PI_CFG_DMAC_DESC_NUM_RSVD_ENTRIES	32
+#define C_PI_CFG_DMAC_DESC_NUM_AVAILABLE_ENTRIES \
+	(C_PI_CFG_DMAC_DESC_ENTRIES - C_PI_CFG_DMAC_DESC_NUM_RSVD_ENTRIES)
+
+#define C_PI_CFG_DMAC_DESC(idx)	(C_PI_BASE + C_PI_CFG_DMAC_DESC_OFFSET(idx))
+#define C_PI_CFG_DMAC_DESC_SIZE	0x00004000
+
+union c_pi_cfg_dmac_desc {
+	__u64 qw[2];
+	struct {
+		__u64 reserved0  :  3;
+		__u64 dst_addr   : 61;
+		__u64 reserved1  :  3;
+		__u64 src_addr   : 27;
+		__u64 reserved2  :  2;
+		__u64 length     : 20;
+		__u64 cont       :  1;
+		__u64 reserved3  : 11;
+	};
+};
+
+#define C_PI_IPD_CFG_CRNC_OFFSET	0x00000000
+#define C_PI_IPD_CFG_CRNC	(C_PI_IPD_BASE + C_PI_IPD_CFG_CRNC_OFFSET)
+#define C_PI_IPD_CFG_CRNC_SIZE	0x00000008
+
+union c_pi_ipd_cfg_crnc {
+	__u64 qw;
+	struct {
+		__u64 csr_timeout   :  8;
+		__u64 mcast_id      : 10;
+		__u64: 1;
+		__u64 mcast_enable  :  1;
+		__u64 mcast_mask    : 10;
+		__u64: 34;
+	};
+};
+
+#define C_PI_IPD_CFG_RT_OFFSET_OFFSET	0x00000020
+#define C_PI_IPD_CFG_RT_OFFSET	(C_PI_IPD_BASE + C_PI_IPD_CFG_RT_OFFSET_OFFSET)
+#define C_PI_IPD_CFG_RT_OFFSET_SIZE	0x00000008
+
+union c_pi_ipd_cfg_rt_offset {
+	__u64 qw;
+	struct {
+		__u64 seconds  : 48;
+		__u64: 16;
+	};
+};
+
+#define C_PI_IPD_MSC_SHADOW_ACTION_OFFSET	0x00000038
+#define C_PI_IPD_MSC_SHADOW_ACTION	(C_PI_IPD_BASE + C_PI_IPD_MSC_SHADOW_ACTION_OFFSET)
+#define C_PI_IPD_MSC_SHADOW_ACTION_SIZE	0x00000008
+#define C_PI_IPD_MSC_SHADOW_OFFSET	0x00000040
+#define C_PI_IPD_MSC_SHADOW	(C_PI_IPD_BASE + C_PI_IPD_MSC_SHADOW_OFFSET)
+#define C_PI_IPD_MSC_SHADOW_SIZE	0x00000028
+
+union c_pi_ipd_msc_shadow {
+	__u64 qw[5];
+};
+
+#define C_PI_IPD_ERR_ELAPSED_TIME_OFFSET	0x00000100
+#define C_PI_IPD_ERR_ELAPSED_TIME	(C_PI_IPD_BASE + C_PI_IPD_ERR_ELAPSED_TIME_OFFSET)
+#define C_PI_IPD_ERR_ELAPSED_TIME_SIZE	0x00000008
+
+union c_pi_ipd_err_elapsed_time {
+	__u64 qw;
+	struct {
+		__u64 nanoseconds  : 30;
+		__u64 seconds      : 34;
+	};
+};
+
+#define C_PI_IPD_ERR_FLG_OFFSET	0x00000108
+#define C_PI_IPD_ERR_FLG	(C_PI_IPD_BASE + C_PI_IPD_ERR_FLG_OFFSET)
+#define C_PI_IPD_ERR_FLG_SIZE	0x00000008
+
+union c_pi_ipd_err_flg {
+	__u64 qw;
+	struct {
+		__u64 sw_diag                         :  1;
+		__u64 crnc_ring_sync_error            :  1;
+		__u64 crnc_ring_ecc_sbe               :  1;
+		__u64 crnc_ring_ecc_mbe               :  1;
+		__u64 crnc_ring_cmd_unknown           :  1;
+		__u64 crnc_csr_cmd_unknown            :  1;
+		__u64 crnc_csr_cmd_incomplete         :  1;
+		__u64 crnc_buf_ecc_sbe                :  1;
+		__u64 crnc_buf_ecc_mbe                :  1;
+		__u64: 7;
+		__u64 event_cnt_ovf                   :  1;
+		__u64 event_ram_cor                   :  1;
+		__u64 event_ram_ucor                  :  1;
+		__u64 msix_table_cor                  :  1;
+		__u64 msix_table_ucor                 :  1;
+		__u64 msix_pba_cor                    :  1;
+		__u64 msix_pba_ucor                   :  1;
+		__u64 pti_tarb_xlat_p_fifo_cor        :  4;
+		__u64 pti_tarb_xlat_p_fifo_ucor       :  4;
+		__u64 pti_tarb_xlat_np_fifo_cor       :  3;
+		__u64 pti_tarb_xlat_np_fifo_ucor      :  3;
+		__u64 pti_tarb_xlat_tbuf_cor          :  1;
+		__u64 pti_tarb_xlat_tbuf_ucor         :  1;
+		__u64 pti_tarb_xlat_cpl_to_fifo_cor   :  1;
+		__u64 pti_tarb_xlat_cpl_to_fifo_ucor  :  1;
+		__u64 pri_mb_xlat_comp_fifo_cor       :  4;
+		__u64 pri_mb_xlat_comp_fifo_ucor      :  4;
+		__u64 pti_msixc_fifo_cor              :  1;
+		__u64 pti_msixc_fifo_ucor             :  1;
+		__u64 msixc_pti_fifo_cor              :  1;
+		__u64 msixc_pti_fifo_ucor             :  1;
+		__u64 dmac_p_fifo_cor                 :  4;
+		__u64 dmac_p_fifo_ucor                :  4;
+		__u64: 3;
+	};
+};
+
+#define C_PI_IPD_ERR_FIRST_FLG_OFFSET	0x00000110
+#define C_PI_IPD_ERR_FIRST_FLG	(C_PI_IPD_BASE + C_PI_IPD_ERR_FIRST_FLG_OFFSET)
+#define C_PI_IPD_ERR_FIRST_FLG_SIZE	0x00000008
+#define C_PI_IPD_ERR_FIRST_FLG_TS_OFFSET	0x00000118
+#define C_PI_IPD_ERR_FIRST_FLG_TS	(C_PI_IPD_BASE + C_PI_IPD_ERR_FIRST_FLG_TS_OFFSET)
+#define C_PI_IPD_ERR_FIRST_FLG_TS_SIZE	0x00000008
+#define C_PI_IPD_ERR_CLR_OFFSET	0x00000120
+#define C_PI_IPD_ERR_CLR	(C_PI_IPD_BASE + C_PI_IPD_ERR_CLR_OFFSET)
+#define C_PI_IPD_ERR_CLR_SIZE	0x00000008
+#define C_PI_IPD_ERR_IRQA_MSK_OFFSET	0x00000128
+#define C_PI_IPD_ERR_IRQA_MSK	(C_PI_IPD_BASE + C_PI_IPD_ERR_IRQA_MSK_OFFSET)
+#define C_PI_IPD_ERR_IRQA_MSK_SIZE	0x00000008
+#define C_PI_IPD_ERR_IRQB_MSK_OFFSET	0x00000130
+#define C_PI_IPD_ERR_IRQB_MSK	(C_PI_IPD_BASE + C_PI_IPD_ERR_IRQB_MSK_OFFSET)
+#define C_PI_IPD_ERR_IRQB_MSK_SIZE	0x00000008
+#define C_PI_IPD_ERR_INFO_MSK_OFFSET	0x00000140
+#define C_PI_IPD_ERR_INFO_MSK	(C_PI_IPD_BASE + C_PI_IPD_ERR_INFO_MSK_OFFSET)
+#define C_PI_IPD_ERR_INFO_MSK_SIZE	0x00000008
+#define C_PI_IPD_ERR_INFO_MEM_OFFSET	0x00000180
+#define C_PI_IPD_ERR_INFO_MEM	(C_PI_IPD_BASE + C_PI_IPD_ERR_INFO_MEM_OFFSET)
+#define C_PI_IPD_ERR_INFO_MEM_SIZE	0x00000008
+
+union c_pi_ipd_err_info_mem {
+	__u64 qw;
+	struct {
+		__u64 cor_syndrome       : 10;
+		__u64: 2;
+		__u64 cor_address        : 12;
+		__u64: 2;
+		__u64 cor_mem_id         :  5;
+		__u64 cor_csr_detected   :  1;
+		__u64 ucor_syndrome      : 10;
+		__u64: 2;
+		__u64 ucor_address       : 12;
+		__u64: 2;
+		__u64 ucor_mem_id        :  5;
+		__u64 ucor_csr_detected  :  1;
+	};
+};
+
+#define C_PI_IPD_EXT_ERR_FLG_OFFSET	0x00000208
+#define C_PI_IPD_EXT_ERR_FLG	(C_PI_IPD_BASE + C_PI_IPD_EXT_ERR_FLG_OFFSET)
+#define C_PI_IPD_EXT_ERR_FLG_SIZE	0x00000008
+
+union c_pi_ipd_ext_err_flg {
+	__u64 qw;
+	struct {
+		__u64 sw_diag                                    :  1;
+		__u64 ip_app_parity_errs                         :  3;
+		__u64 ip_radm_qoverflow                          :  1;
+		__u64 ip_radm_msg_unlock                         :  1;
+		__u64 ip_radm_pm_turnoff                         :  1;
+		__u64 ip_wake                                    :  1;
+		__u64 ip_cfg_uncor_internal_err_sts              :  1;
+		__u64 ip_cfg_corrected_internal_err_sts          :  1;
+		__u64 ip_cfg_rcvr_overflow_err_sts               :  1;
+		__u64 ip_cfg_fc_protocol_err_sts                 :  1;
+		__u64 ip_cfg_mlf_tlp_err_sts                     :  1;
+		__u64 ip_cfg_surprise_down_er_sts                :  1;
+		__u64 ip_cfg_dl_protocol_err_sts                 :  1;
+		__u64 ip_cfg_ecrc_err_sts                        :  1;
+		__u64 ip_cfg_replay_number_rollover_err_sts      :  1;
+		__u64 ip_cfg_replay_timer_timeout_err_sts        :  1;
+		__u64 ip_cfg_bad_dllp_err_sts                    :  1;
+		__u64 ip_cfg_bad_tlp_err_sts                     :  1;
+		__u64 ip_cfg_rcvr_err_sts                        :  1;
+		__u64: 5;
+		__u64 pti_tarb_xlat_xali_ph_crd_warn             :  1;
+		__u64 pti_tarb_xlat_xali_pd_crd_warn             :  1;
+		__u64 pti_tarb_xlat_xali_nph_crd_warn            :  1;
+		__u64 pti_tarb_xlat_xali_npd_crd_warn            :  1;
+		__u64 pti_tarb_xlat_ten_bit_tag_msb_error        :  1;
+		__u64 pti_tarb_xlat_p_fifo_underrun              :  1;
+		__u64 pti_tarb_xlat_np_fifo_underrun             :  1;
+		__u64 pti_tarb_xlat_ord_fifo_underrun            :  1;
+		__u64 pti_tarb_xlat_cpl_to_fifo_overrun          :  1;
+		__u64 pti_tarb_xlat_cpl_to_fifo_underrun         :  1;
+		__u64 pti_tarb_xlat_pti_pri_cpl_to_fifo_overrun  :  1;
+		__u64 pti_tarb_xlat_ord_np_cnt_overrun           :  1;
+		__u64 pti_tarb_xlat_ord_np_cnt_underrun          :  1;
+		__u64 pri_rtrgt_hdr_parity_error                 :  1;
+		__u64 pri_rtrgt_data_parity_error                :  1;
+		__u64 pri_rtrgt_abort                            :  1;
+		__u64 pri_rbyp_hdr_parity_error                  :  1;
+		__u64 pri_rbyp_data_parity_error                 :  1;
+		__u64 pri_rbyp_abort                             :  1;
+		__u64 pri_rarb_xlat_rtrgt_fifo_overrun           :  1;
+		__u64 pri_rarb_xlat_rtrgt_rdy_fifo_overrun       :  1;
+		__u64 pri_rarb_xlat_rbyp_fifo_overrun            :  1;
+		__u64 pri_rarb_xlat_rbyp_rdy_fifo_overrun        :  1;
+		__u64 pri_mb_xlat_rtrgt_fifo_overrun             :  1;
+		__u64 pri_mb_xlat_rtrgt_rdy_fifo_overrun         :  1;
+		__u64 pri_mb_xlat_comp_fifo_underrun             :  1;
+		__u64 msixc_pti_fifo_overrun                     :  1;
+		__u64 msixc_pti_fifo_underrun                    :  1;
+		__u64 pti_msixc_fifo_overrun                     :  1;
+		__u64 pti_msixc_fifo_underrun                    :  1;
+		__u64 msix_disabled_error                        :  1;
+		__u64 msix_hg_vf_size_error                      :  1;
+		__u64 msix_pti_idx_error                         :  1;
+		__u64 dmac_bme_error                             :  1;
+		__u64: 4;
+	};
+};
+
+#define C_PI_IPD_EXT_ERR_FIRST_FLG_OFFSET	0x00000210
+#define C_PI_IPD_EXT_ERR_FIRST_FLG	(C_PI_IPD_BASE + C_PI_IPD_EXT_ERR_FIRST_FLG_OFFSET)
+#define C_PI_IPD_EXT_ERR_FIRST_FLG_SIZE	0x00000008
+#define C_PI_IPD_EXT_ERR_FIRST_FLG_TS_OFFSET	0x00000218
+#define C_PI_IPD_EXT_ERR_FIRST_FLG_TS	(C_PI_IPD_BASE + C_PI_IPD_EXT_ERR_FIRST_FLG_TS_OFFSET)
+#define C_PI_IPD_EXT_ERR_FIRST_FLG_TS_SIZE	0x00000008
+#define C_PI_IPD_EXT_ERR_CLR_OFFSET	0x00000220
+#define C_PI_IPD_EXT_ERR_CLR	(C_PI_IPD_BASE + C_PI_IPD_EXT_ERR_CLR_OFFSET)
+#define C_PI_IPD_EXT_ERR_CLR_SIZE	0x00000008
+#define C_PI_IPD_EXT_ERR_IRQA_MSK_OFFSET	0x00000228
+#define C_PI_IPD_EXT_ERR_IRQA_MSK	(C_PI_IPD_BASE + C_PI_IPD_EXT_ERR_IRQA_MSK_OFFSET)
+#define C_PI_IPD_EXT_ERR_IRQA_MSK_SIZE	0x00000008
+#define C_PI_IPD_EXT_ERR_IRQB_MSK_OFFSET	0x00000230
+#define C_PI_IPD_EXT_ERR_IRQB_MSK	(C_PI_IPD_BASE + C_PI_IPD_EXT_ERR_IRQB_MSK_OFFSET)
+#define C_PI_IPD_EXT_ERR_IRQB_MSK_SIZE	0x00000008
+#define C_PI_IPD_EXT_ERR_INFO_MSK_OFFSET	0x00000240
+#define C_PI_IPD_EXT_ERR_INFO_MSK	(C_PI_IPD_BASE + C_PI_IPD_EXT_ERR_INFO_MSK_OFFSET)
+#define C_PI_IPD_EXT_ERR_INFO_MSK_SIZE	0x00000008
+#define C_PI_IPD_CFG_MSIXC_OFFSET	0x00004000
+#define C_PI_IPD_CFG_MSIXC	(C_PI_IPD_BASE + C_PI_IPD_CFG_MSIXC_OFFSET)
+#define C_PI_IPD_CFG_MSIXC_SIZE	0x00000008
+
+union c_pi_ipd_cfg_msixc {
+	__u64 qw;
+	struct {
+		__u64 legacy_irq_enable    :  1;
+		__u64 legacy_irq_mask      :  1;
+		__u64 legacy_irq_asserted  :  1;
+		__u64: 5;
+		__u64 vf_pf_irq_enable     :  1;
+		__u64: 55;
+	};
+};
+
+#define C_PI_IPD_CFG_VF_PF_IRQ_MASK_OFFSET	0x00004010
+#define C_PI_IPD_CFG_VF_PF_IRQ_MASK	(C_PI_IPD_BASE + C_PI_IPD_CFG_VF_PF_IRQ_MASK_OFFSET)
+#define C_PI_IPD_CFG_VF_PF_IRQ_MASK_SIZE	0x00000008
+
+union c_pi_ipd_cfg_vf_pf_irq_mask {
+	__u64 qw;
+	struct {
+		__u64 mask;
+	};
+};
+
+#define C_PI_IPD_STS_VF_PF_IRQ_OFFSET	0x00004018
+#define C_PI_IPD_STS_VF_PF_IRQ	(C_PI_IPD_BASE + C_PI_IPD_STS_VF_PF_IRQ_OFFSET)
+#define C_PI_IPD_STS_VF_PF_IRQ_SIZE	0x00000008
+
+union c_pi_ipd_sts_vf_pf_irq {
+	__u64 qw;
+	struct {
+		__u64 irq;
+	};
+};
+
+#define C_PI_IPD_CFG_VF_PF_IRQ_CLR_OFFSET	0x00004020
+#define C_PI_IPD_CFG_VF_PF_IRQ_CLR	(C_PI_IPD_BASE + C_PI_IPD_CFG_VF_PF_IRQ_CLR_OFFSET)
+#define C_PI_IPD_CFG_VF_PF_IRQ_CLR_SIZE	0x00000008
+
+union c_pi_ipd_cfg_vf_pf_irq_clr {
+	__u64 qw;
+	struct {
+		__u64 clr;
+	};
+};
+
+#define C_PI_IPD_CFG_PF_VF_IRQ_OFFSET	0x00004028
+#define C_PI_IPD_CFG_PF_VF_IRQ	(C_PI_IPD_BASE + C_PI_IPD_CFG_PF_VF_IRQ_OFFSET)
+#define C_PI_IPD_CFG_PF_VF_IRQ_SIZE	0x00000008
+
+union c_pi_ipd_cfg_pf_vf_irq {
+	__u64 qw;
+	struct {
+		__u64 irq;
+	};
+};
+
+#define C_PI_IPD_CFG_EVENT_CNTS_OFFSET	0x00005000
+#define C_PI_IPD_CFG_EVENT_CNTS	(C_PI_IPD_BASE + C_PI_IPD_CFG_EVENT_CNTS_OFFSET)
+#define C_PI_IPD_CFG_EVENT_CNTS_SIZE	0x00000008
+
+union c_pi_ipd_cfg_event_cnts {
+	__u64 qw;
+	struct {
+		__u64 enable            :  1;
+		__u64 init              :  1;
+		__u64 init_done         :  1;
+		__u64 warm_rst_disable  :  1;
+		__u64 ovf_cnt           : 16;
+		__u64: 44;
+	};
+};
+
+#define C_PI_IPD_STS_EVENT_CNTS_OFFSET(idx)	(0x00006000 + ((idx) * 8))
+#ifndef C_PI_IPD_STS_EVENT_CNTS_ENTRIES
+#define C_PI_IPD_STS_EVENT_CNTS_ENTRIES	128
+#endif
+#define C_PI_IPD_STS_EVENT_CNTS(idx)	(C_PI_IPD_BASE + C_PI_IPD_STS_EVENT_CNTS_OFFSET(idx))
+#define C_PI_IPD_STS_EVENT_CNTS_SIZE	0x00000400
+
+union c_pi_ipd_sts_event_cnts {
+	__u64 qw;
+	struct {
+		__u64 cnt  : 56;
+		__u64: 8;
+	};
+};
+
+#define C_PI_IPD_CFG_MSIX_TABLE_OFFSET(idx)	(0x00010000 + ((idx) * 16))
+#define C_PI_IPD_CFG_MSIX_TABLE_ENTRIES	4096
+#define C_PI_IPD_CFG_MSIX_TABLE(idx)	(C_PI_IPD_BASE + C_PI_IPD_CFG_MSIX_TABLE_OFFSET(idx))
+#define C_PI_IPD_CFG_MSIX_TABLE_SIZE	0x00010000
+
+union c_pi_ipd_cfg_msix_table {
+	__u64 qw[2];
+	struct {
+		__u64 msg_addr;
+		__u64 msg_data         : 32;
+		__u64 vector_ctl_mask  :  1;
+		__u64 vector_ctl_rsvd  : 31;
+	};
+};
+
+#define C_PI_IPD_CFG_VF_MSIX_TABLE_OFFSET(idx)	(0x00400000 + ((idx) * 16))
+#define C_PI_IPD_CFG_VF_MSIX_TABLE_ENTRIES	131072
+#define C_PI_IPD_CFG_VF_MSIX_TABLE(idx)	(C_PI_IPD_BASE + C_PI_IPD_CFG_VF_MSIX_TABLE_OFFSET(idx))
+#define C_PI_IPD_CFG_VF_MSIX_TABLE_SIZE	0x00200000
+
+union c_pi_ipd_cfg_vf_msix_table {
+	__u64 qw[2];
+	struct {
+		__u64 msg_addr;
+		__u64 msg_data         : 32;
+		__u64 vector_ctl_mask  :  1;
+		__u64 vector_ctl_rsvd  : 31;
+	};
+};
+
+#define C_RMU_CFG_CRNC_OFFSET	0x00000000
+#define C_RMU_CFG_CRNC	(C_RMU_BASE + C_RMU_CFG_CRNC_OFFSET)
+#define C_RMU_CFG_CRNC_SIZE	0x00000008
+
+union c_rmu_cfg_crnc {
+	__u64 qw;
+	struct {
+		__u64 csr_timeout   :  8;
+		__u64 mcast_id      : 10;
+		__u64: 1;
+		__u64 mcast_enable  :  1;
+		__u64 mcast_mask    : 10;
+		__u64: 34;
+	};
+};
+
+#define C_RMU_MSC_SHADOW_ACTION_OFFSET	0x00000038
+#define C_RMU_MSC_SHADOW_ACTION	(C_RMU_BASE + C_RMU_MSC_SHADOW_ACTION_OFFSET)
+#define C_RMU_MSC_SHADOW_ACTION_SIZE	0x00000008
+#define C_RMU_MSC_SHADOW_OFFSET	0x00000040
+#define C_RMU_MSC_SHADOW	(C_RMU_BASE + C_RMU_MSC_SHADOW_OFFSET)
+#define C_RMU_MSC_SHADOW_SIZE	0x00000020
+
+union c_rmu_msc_shadow {
+	__u64 qw[4];
+};
+
+#define C_RMU_ERR_ELAPSED_TIME_OFFSET	0x00000100
+#define C_RMU_ERR_ELAPSED_TIME	(C_RMU_BASE + C_RMU_ERR_ELAPSED_TIME_OFFSET)
+#define C_RMU_ERR_ELAPSED_TIME_SIZE	0x00000008
+
+union c_rmu_err_elapsed_time {
+	__u64 qw;
+	struct {
+		__u64 nanoseconds  : 30;
+		__u64 seconds      : 34;
+	};
+};
+
+#define C_RMU_ERR_FLG_OFFSET	0x00000108
+#define C_RMU_ERR_FLG	(C_RMU_BASE + C_RMU_ERR_FLG_OFFSET)
+#define C_RMU_ERR_FLG_SIZE	0x00000008
+
+union c_rmu_err_flg {
+	__u64 qw;
+	struct {
+		__u64 sw_diag                      :  1;
+		__u64 crnc_ring_sync_error         :  1;
+		__u64 crnc_ring_ecc_sbe            :  1;
+		__u64 crnc_ring_ecc_mbe            :  1;
+		__u64 crnc_ring_cmd_unknown        :  1;
+		__u64 crnc_csr_cmd_unknown         :  1;
+		__u64 crnc_csr_cmd_incomplete      :  1;
+		__u64 crnc_buf_ecc_sbe             :  1;
+		__u64 crnc_buf_ecc_mbe             :  1;
+		__u64: 23;
+		__u64 ptl_idx_mem_cor              :  1;
+		__u64 ptlte_set_ctrl_mem_cor       :  1;
+		__u64 ptl_idx_indir_mem_cor        :  1;
+		__u64: 1;
+		__u64 vni_list_mem_ucor            :  1;
+		__u64 vni_list_vld_mem_ucor        :  1;
+		__u64 ptl_list_mem_ucor            :  1;
+		__u64 ptl_list_vld_mem_ucor        :  1;
+		__u64 ptl_idx_mem_ucor             :  1;
+		__u64 ptlte_set_list_mem_ucor      :  1;
+		__u64 ptlte_set_list_vld_mem_ucor  :  1;
+		__u64 ptlte_set_ctrl_mem_ucor      :  1;
+		__u64 ptl_idx_indir_mem_ucor       :  1;
+		__u64: 3;
+		__u64 ptl_invld_dfa                :  1;
+		__u64 ptl_invld_vni                :  1;
+		__u64 ptl_no_ptlte                 :  1;
+		__u64 enet_frame_rejected          :  1;
+		__u64 enet_ptlte_set_ctrl_err      :  1;
+		__u64: 11;
+	};
+};
+
+#define C_RMU_ERR_FIRST_FLG_OFFSET	0x00000110
+#define C_RMU_ERR_FIRST_FLG	(C_RMU_BASE + C_RMU_ERR_FIRST_FLG_OFFSET)
+#define C_RMU_ERR_FIRST_FLG_SIZE	0x00000008
+#define C_RMU_ERR_FIRST_FLG_TS_OFFSET	0x00000118
+#define C_RMU_ERR_FIRST_FLG_TS	(C_RMU_BASE + C_RMU_ERR_FIRST_FLG_TS_OFFSET)
+#define C_RMU_ERR_FIRST_FLG_TS_SIZE	0x00000008
+#define C_RMU_ERR_CLR_OFFSET	0x00000120
+#define C_RMU_ERR_CLR	(C_RMU_BASE + C_RMU_ERR_CLR_OFFSET)
+#define C_RMU_ERR_CLR_SIZE	0x00000008
+#define C_RMU_ERR_IRQA_MSK_OFFSET	0x00000128
+#define C_RMU_ERR_IRQA_MSK	(C_RMU_BASE + C_RMU_ERR_IRQA_MSK_OFFSET)
+#define C_RMU_ERR_IRQA_MSK_SIZE	0x00000008
+#define C_RMU_ERR_IRQB_MSK_OFFSET	0x00000130
+#define C_RMU_ERR_IRQB_MSK	(C_RMU_BASE + C_RMU_ERR_IRQB_MSK_OFFSET)
+#define C_RMU_ERR_IRQB_MSK_SIZE	0x00000008
+#define C_RMU_ERR_INFO_MSK_OFFSET	0x00000140
+#define C_RMU_ERR_INFO_MSK	(C_RMU_BASE + C_RMU_ERR_INFO_MSK_OFFSET)
+#define C_RMU_ERR_INFO_MSK_SIZE	0x00000008
+#define C_RMU_ERR_INFO_MEM_OFFSET	0x00000180
+#define C_RMU_ERR_INFO_MEM	(C_RMU_BASE + C_RMU_ERR_INFO_MEM_OFFSET)
+#define C_RMU_ERR_INFO_MEM_SIZE	0x00000008
+
+union c_rmu_err_info_mem {
+	__u64 qw;
+	struct {
+		__u64 cor_syndrome       : 12;
+		__u64 cor_address        : 13;
+		__u64: 1;
+		__u64 cor_mem_id         :  4;
+		__u64: 1;
+		__u64 cor_csr_detected   :  1;
+		__u64 ucor_syndrome      : 12;
+		__u64 ucor_address       : 13;
+		__u64: 1;
+		__u64 ucor_mem_id        :  4;
+		__u64: 1;
+		__u64 ucor_csr_detected  :  1;
+	};
+};
+
+#define C_RMU_ERR_INFO_PTL_INVLD_DFA_OFFSET	0x00000188
+#define C_RMU_ERR_INFO_PTL_INVLD_DFA	(C_RMU_BASE + C_RMU_ERR_INFO_PTL_INVLD_DFA_OFFSET)
+#define C_RMU_ERR_INFO_PTL_INVLD_DFA_SIZE	0x00000008
+
+union c_rmu_err_info_ptl_invld_dfa {
+	__u64 qw;
+	struct {
+		__u64 dfa  : 32;
+		__u64 sfa  : 32;
+	};
+};
+
+#define C_RMU_ERR_INFO_PTL_INVLD_VNI_OFFSET	0x00000190
+#define C_RMU_ERR_INFO_PTL_INVLD_VNI	(C_RMU_BASE + C_RMU_ERR_INFO_PTL_INVLD_VNI_OFFSET)
+#define C_RMU_ERR_INFO_PTL_INVLD_VNI_SIZE	0x00000008
+
+union c_rmu_err_info_ptl_invld_vni {
+	__u64 qw;
+	struct {
+		__u64 vni   : 16;
+		__u64: 16;
+		__u64 sfa   : 32;
+	};
+};
+
+#define C_RMU_ERR_INFO_PTL_NO_PTLTE_OFFSET	0x00000198
+#define C_RMU_ERR_INFO_PTL_NO_PTLTE	(C_RMU_BASE + C_RMU_ERR_INFO_PTL_NO_PTLTE_OFFSET)
+#define C_RMU_ERR_INFO_PTL_NO_PTLTE_SIZE	0x00000008
+
+union c_rmu_err_info_ptl_no_ptlte {
+	__u64 qw;
+	struct {
+		__u64 index_ext     :  5;
+		__u64 multicast_id  : 13;
+		__u64: 2;
+		__u64 is_multicast  :  1;
+		__u64: 3;
+		__u64 vni_list_idx  :  8;
+		__u64 sfa           : 32;
+	};
+};
+
+#define C_RMU_ERR_INFO_ENET_NO_PTLTE_SET_OFFSET	0x000001c0
+#define C_RMU_ERR_INFO_ENET_NO_PTLTE_SET	(C_RMU_BASE + C_RMU_ERR_INFO_ENET_NO_PTLTE_SET_OFFSET)
+#define C_RMU_ERR_INFO_ENET_NO_PTLTE_SET_SIZE	0x00000028
+
+union c_rmu_err_info_enet_no_ptlte_set {
+	__u64 qw[5];
+	struct {
+		union {
+			struct {
+				__u64 dipv6_lower;
+				__u64 dipv6_upper;
+				__u64 sipv6_lower;
+				__u64 sipv6_upper;
+			};
+			struct {
+				__u32 dipv4;
+				__u32 unused_opt_ipv4_0;
+				__u64 unused_opt_ipv4_1;
+				__u32 sipv4;
+				__u32 unused_opt_ipv4_2;
+				__u64 unused_opt_ipv4_3;
+			};
+			struct {
+				__u64 dmac : 48;
+				__u64 vid  : 12;
+				__u64 dei  :  1;
+				__u64 pcp  :  3;
+				__u64 vlan_present        :  1;
+				__u64 unused_ieee_802_3_0 : 63;
+			};
+		};
+		__u64 smac          : 48;
+		__u64 tc            :  3;
+		__u64:  1;
+		__u64 lossless      :  1;
+		__u64:  3;
+		__u64 frame_type    :  2;
+		__u64 ip_v4_present :  1;
+		__u64 ip_v6_present :  1;
+		__u64:  4;
+	};
+};
+
+#define C_RMU_ERR_INFO_ENET_BAD_PTLTE_SET_CTRL_OFFSET	0x000001e8
+#define C_RMU_ERR_INFO_ENET_BAD_PTLTE_SET_CTRL	(C_RMU_BASE + C_RMU_ERR_INFO_ENET_BAD_PTLTE_SET_CTRL_OFFSET)
+#define C_RMU_ERR_INFO_ENET_BAD_PTLTE_SET_CTRL_SIZE	0x00000008
+
+union c_rmu_err_info_enet_bad_ptlte_set_ctrl {
+	__u64 qw;
+	struct {
+		__u64 ptlte_set_ctrl_entry     :  7;
+		__u64: 1;
+		__u64 hash_type                :  5;
+		__u64: 3;
+		__u64 portal_index_indir_base  : 11;
+		__u64: 1;
+		__u64 hash_bits                :  4;
+		__u64 hash_value               : 32;
+	};
+};
+
+#define C_RMU_CFG_VNI_LIST_X_OFFSET(idx)	(0x00001000 + ((idx) * 8))
+#define C_RMU_CFG_VNI_LIST_X(idx)	(C_RMU_BASE + C_RMU_CFG_VNI_LIST_X_OFFSET(idx))
+#define C_RMU_CFG_VNI_LIST_X_SIZE	0x00000800
+#define C_RMU_CFG_VNI_LIST_Y_OFFSET(idx)	(0x00001800 + ((idx) * 8))
+#define C_RMU_CFG_VNI_LIST_ENTRIES	256
+#define C_RMU_CFG_VNI_LIST_Y(idx)	(C_RMU_BASE + C_RMU_CFG_VNI_LIST_Y_OFFSET(idx))
+#define C_RMU_CFG_VNI_LIST_Y_SIZE	0x00000800
+
+union c_rmu_cfg_vni_list {
+	__u64 qw;
+	struct {
+		__u64 vni    : 16;
+		__u64 valid  :  1;
+		__u64: 47;
+	};
+};
+
+#define C_RMU_CFG_VNI_LIST_INVALIDATE_OFFSET(idx)	(0x00002000 + ((idx) * 8))
+#define C_RMU_CFG_VNI_LIST_INVALIDATE(idx)	(C_RMU_BASE + C_RMU_CFG_VNI_LIST_INVALIDATE_OFFSET(idx))
+#define C_RMU_CFG_VNI_LIST_INVALIDATE_SIZE	0x00000800
+
+union c_rmu_cfg_vni_list_invalidate {
+	__u64 qw;
+	struct {
+		__u64 invalidate  :  1;
+		__u64: 63;
+	};
+};
+
+#define C_RMU_CFG_VNI_LIST_CHK_OFFSET	0x00000400
+#define C_RMU_CFG_VNI_LIST_CHK	(C_RMU_BASE + C_RMU_CFG_VNI_LIST_CHK_OFFSET)
+#define C_RMU_CFG_VNI_LIST_CHK_SIZE	0x00000008
+
+union c_rmu_cfg_vni_list_chk {
+	__u64 qw;
+	struct {
+		__u64 intrvl  : 32;
+		__u64: 32;
+	};
+};
+
+#define C_RMU_CFG_PORTAL_LIST_X_OFFSET(idx)	(0x00010000 + ((idx) * 8))
+#define C_RMU_CFG_PORTAL_LIST_X(idx)	(C_RMU_BASE + C_RMU_CFG_PORTAL_LIST_X_OFFSET(idx))
+#define C_RMU_CFG_PORTAL_LIST_X_SIZE	0x00005000
+#define C_RMU_CFG_PORTAL_LIST_Y_OFFSET(idx)	(0x00018000 + ((idx) * 8))
+#define C_RMU_CFG_PORTAL_LIST_ENTRIES	2560
+#define C_RMU_CFG_PORTAL_LIST_Y(idx)	(C_RMU_BASE + C_RMU_CFG_PORTAL_LIST_Y_OFFSET(idx))
+#define C_RMU_CFG_PORTAL_LIST_Y_SIZE	0x00005000
+
+union c_rmu_cfg_portal_list {
+	__u64 qw;
+	struct {
+		union {
+			struct {
+				__u64 index_ext     :  5;
+				__u64 multicast_id  : 13;
+				__u64:  2;
+				__u64 is_multicast  :  1;
+				__u64:  3;
+				__u64 vni_list_idx  :  8;
+				__u64 valid	       :  1;
+				__u64: 31;
+			};
+			struct {
+				__u64: 5;
+				__u64 endpoint_defined : 12;
+				__u64: 7;
+			};
+		};
+	};
+};
+
+#define C_RMU_CFG_PORTAL_LIST_INVALIDATE_OFFSET(idx)	(0x00020000 + ((idx) * 8))
+#define C_RMU_CFG_PORTAL_LIST_INVALIDATE(idx)	(C_RMU_BASE + C_RMU_CFG_PORTAL_LIST_INVALIDATE_OFFSET(idx))
+#define C_RMU_CFG_PORTAL_LIST_INVALIDATE_SIZE	0x00005000
+
+union c_rmu_cfg_portal_list_invalidate {
+	__u64 qw;
+	struct {
+		__u64 invalidate  :  1;
+		__u64: 63;
+	};
+};
+
+#define C_RMU_CFG_PORTAL_LIST_CHK_OFFSET	0x00000408
+#define C_RMU_CFG_PORTAL_LIST_CHK	(C_RMU_BASE + C_RMU_CFG_PORTAL_LIST_CHK_OFFSET)
+#define C_RMU_CFG_PORTAL_LIST_CHK_SIZE	0x00000008
+
+union c_rmu_cfg_portal_list_chk {
+	__u64 qw;
+	struct {
+		__u64 intrvl  : 32;
+		__u64: 32;
+	};
+};
+
+#define C_RMU_CFG_PORTAL_INDEX_TABLE_OFFSET(idx)	(0x00004000 + ((idx) * 8))
+#define C_RMU_CFG_PORTAL_INDEX_TABLE_ENTRIES	640
+#define C_RMU_CFG_PORTAL_INDEX_TABLE(idx)	(C_RMU_BASE + C_RMU_CFG_PORTAL_INDEX_TABLE_OFFSET(idx))
+#define C_RMU_CFG_PORTAL_INDEX_TABLE_SIZE	0x00001400
+
+#define C_RMU_CFG_PORTAL_INDEX_TABLE_ARRAY_SIZE 4
+union c_rmu_cfg_portal_index_table {
+	__u64 qw;
+	struct {
+		__u16 phys_portal_table_idx : 11;
+		__u16:  5;
+	} e[C_RMU_CFG_PORTAL_INDEX_TABLE_ARRAY_SIZE];
+};
+
+#define C_RMU_CFG_PTLTE_SET_LIST_X_OFFSET(idx)	(0x00006000 + ((idx) * 32))
+#define C_RMU_CFG_PTLTE_SET_LIST_X(idx)	(C_RMU_BASE + C_RMU_CFG_PTLTE_SET_LIST_X_OFFSET(idx))
+#define C_RMU_CFG_PTLTE_SET_LIST_X_SIZE	0x00001000
+#define C_RMU_CFG_PTLTE_SET_LIST_Y_OFFSET(idx)	(0x00007000 + ((idx) * 32))
+#define C_RMU_CFG_PTLTE_SET_LIST_ENTRIES	128
+#define C_RMU_CFG_PTLTE_SET_LIST_Y(idx)	(C_RMU_BASE + C_RMU_CFG_PTLTE_SET_LIST_Y_OFFSET(idx))
+#define C_RMU_CFG_PTLTE_SET_LIST_Y_SIZE	0x00001000
+
+union c_rmu_cfg_ptlte_set_list {
+	__u64 qw[4];
+	struct {
+		union {
+			struct {
+				__u64	dmac		: 48;
+				__u64	vid		: 12;
+				__u64	dei		:  1;
+				__u64	pcp		:  3;
+			};
+			__u64	dipv6[2];
+			struct {
+				__u32	dipv4;
+				__u32	opt_ipv4_unused_0;
+				union {
+					struct {
+						__u64	vlan_present	  :  1;
+						__u64	ieee_802_3_unused : 63;
+					};
+					__u64 opt_ipv4_unused_1;
+				};
+			};
+		};
+		__u64	lossless	:  1;
+		__u64:  7;
+		__u64	frame_type	:  2;
+		__u64: 54;
+		__u64	valid		:  1;
+		__u64: 63;
+	};
+};
+
+#define C_RMU_CFG_PTLTE_SET_LIST_INVALIDATE_OFFSET(idx)	(0x00008000 + ((idx) * 32))
+#define C_RMU_CFG_PTLTE_SET_LIST_INVALIDATE(idx)	(C_RMU_BASE + C_RMU_CFG_PTLTE_SET_LIST_INVALIDATE_OFFSET(idx))
+#define C_RMU_CFG_PTLTE_SET_LIST_INVALIDATE_SIZE	0x00001000
+
+union c_rmu_cfg_ptlte_set_list_invalidate {
+	__u64 qw;
+	struct {
+		__u64 invalidate  :  1;
+		__u64: 63;
+	};
+};
+
+#define C_RMU_CFG_PTLTE_SET_LIST_CHK_OFFSET	0x00000418
+#define C_RMU_CFG_PTLTE_SET_LIST_CHK	(C_RMU_BASE + C_RMU_CFG_PTLTE_SET_LIST_CHK_OFFSET)
+#define C_RMU_CFG_PTLTE_SET_LIST_CHK_SIZE	0x00000008
+
+union c_rmu_cfg_ptlte_set_list_chk {
+	__u64 qw;
+	struct {
+		__u64 intrvl  : 32;
+		__u64: 32;
+	};
+};
+
+#define C_RMU_CFG_PTLTE_SET_CTRL_TABLE_OFFSET(idx)	(0x00009000 + ((idx) * 8))
+#define C_RMU_CFG_PTLTE_SET_CTRL_TABLE_ENTRIES	64
+#define C_RMU_CFG_PTLTE_SET_CTRL_TABLE(idx)	(C_RMU_BASE + C_RMU_CFG_PTLTE_SET_CTRL_TABLE_OFFSET(idx))
+#define C_RMU_CFG_PTLTE_SET_CTRL_TABLE_SIZE	0x00000200
+
+struct c_rmu_cfg_ptlte_set_ctrl_table_entry {
+	__u32 portal_index_indir_base  : 11;
+	__u32:  1;
+	__u32 hash_bits                :  4;
+	__u32 hash_types_enabled       : 16;
+};
+
+#define C_RMU_CFG_PTLTE_SET_CTRL_TABLE_ARRAY_SIZE 2
+union c_rmu_cfg_ptlte_set_ctrl_table {
+	__u64 qw;
+	struct c_rmu_cfg_ptlte_set_ctrl_table_entry e[C_RMU_CFG_PTLTE_SET_CTRL_TABLE_ARRAY_SIZE];
+};
+
+#define C_RMU_CFG_PORTAL_INDEX_INDIR_TABLE_OFFSET(idx)	(0x0000a000 + ((idx) * 8))
+#define C_RMU_CFG_PORTAL_INDEX_INDIR_TABLE_ENTRIES	544
+#define C_RMU_CFG_PORTAL_INDEX_INDIR_TABLE(idx)	(C_RMU_BASE + C_RMU_CFG_PORTAL_INDEX_INDIR_TABLE_OFFSET(idx))
+#define C_RMU_CFG_PORTAL_INDEX_INDIR_TABLE_SIZE	0x00001100
+
+#define C_RMU_CFG_PORTAL_INDEX_INDIR_TABLE_ARRAY_SIZE 4
+union c_rmu_cfg_portal_index_indir_table {
+	__u64 qw;
+	struct {
+		__u16 phys_portal_table_idx : 11;
+		__u16:  5;
+	} e[C_RMU_CFG_PORTAL_INDEX_INDIR_TABLE_ARRAY_SIZE];
+};
+
+#define C_RMU_CFG_HASH_KEY_OFFSET	0x00000440
+#define C_RMU_CFG_HASH_KEY	(C_RMU_BASE + C_RMU_CFG_HASH_KEY_OFFSET)
+#define C_RMU_CFG_HASH_KEY_SIZE	0x00000030
+
+union c_rmu_cfg_hash_key {
+	__u64 qw[6];
+	struct {
+		__u64 key_wd_0;
+		__u64 key_wd_1;
+		__u64 key_wd_2;
+		__u64 key_wd_3;
+		__u64 key_wd_4;
+		__u64 key_wd_5   : 31;
+		__u64: 33;
+	};
+};
+
+#define C_RMU_STS_INIT_DONE_OFFSET	0x00000818
+#define C_RMU_STS_INIT_DONE	(C_RMU_BASE + C_RMU_STS_INIT_DONE_OFFSET)
+#define C_RMU_STS_INIT_DONE_SIZE	0x00000008
+
+union c_rmu_sts_init_done {
+	__u64 qw;
+	struct {
+		__u64 init_done   :  1;
+		__u64 warm_reset  :  1;
+		__u64: 62;
+	};
+};
+
+#define C2_HNI_EXT_ERR_FLG_OFFSET	0x00000148
+#define C2_HNI_EXT_ERR_FLG	(C_HNI_BASE + C2_HNI_EXT_ERR_FLG_OFFSET)
+#define C2_HNI_EXT_ERR_FLG_SIZE	0x00000008
+
+union c2_hni_ext_err_flg {
+	__u64 qw;
+	struct {
+		__u64 sw_diag       :  1;
+		__u64 pmi_err       :  1;
+		__u64 fsm_err       :  1;
+		__u64 pmi_ack       :  1;
+		__u64 rx_ctrl_perr  :  1;
+		__u64 tx_ctrl_perr  :  1;
+		__u64: 58;
+	};
+};
+
+#define C2_HNI_EXT_ERR_FIRST_FLG_OFFSET	0x00000150
+#define C2_HNI_EXT_ERR_FIRST_FLG	(C_HNI_BASE + C2_HNI_EXT_ERR_FIRST_FLG_OFFSET)
+#define C2_HNI_EXT_ERR_FIRST_FLG_SIZE	0x00000008
+#define C2_HNI_EXT_ERR_FIRST_FLG_TS_OFFSET	0x00000158
+#define C2_HNI_EXT_ERR_FIRST_FLG_TS	(C_HNI_BASE + C2_HNI_EXT_ERR_FIRST_FLG_TS_OFFSET)
+#define C2_HNI_EXT_ERR_FIRST_FLG_TS_SIZE	0x00000008
+#define C2_HNI_EXT_ERR_CLR_OFFSET	0x00000160
+#define C2_HNI_EXT_ERR_CLR	(C_HNI_BASE + C2_HNI_EXT_ERR_CLR_OFFSET)
+#define C2_HNI_EXT_ERR_CLR_SIZE	0x00000008
+#define C2_HNI_EXT_ERR_IRQA_MSK_OFFSET	0x00000168
+#define C2_HNI_EXT_ERR_IRQA_MSK	(C_HNI_BASE + C2_HNI_EXT_ERR_IRQA_MSK_OFFSET)
+#define C2_HNI_EXT_ERR_IRQA_MSK_SIZE	0x00000008
+#define C2_HNI_EXT_ERR_IRQB_MSK_OFFSET	0x00000170
+#define C2_HNI_EXT_ERR_IRQB_MSK	(C_HNI_BASE + C2_HNI_EXT_ERR_IRQB_MSK_OFFSET)
+#define C2_HNI_EXT_ERR_IRQB_MSK_SIZE	0x00000008
+#define C2_HNI_EXT_ERR_INFO_MSK_OFFSET	0x00000180
+#define C2_HNI_EXT_ERR_INFO_MSK	(C_HNI_BASE + C2_HNI_EXT_ERR_INFO_MSK_OFFSET)
+#define C2_HNI_EXT_ERR_INFO_MSK_SIZE	0x00000008
+#define C2_HNI_EXT_ERR_INFO_PMI_OFFSET	0x000001c8
+#define C2_HNI_EXT_ERR_INFO_PMI	(C_HNI_BASE + C2_HNI_EXT_ERR_INFO_PMI_OFFSET)
+#define C2_HNI_EXT_ERR_INFO_PMI_SIZE	0x00000008
+
+union c2_hni_ext_err_info_pmi {
+	__u64 qw;
+	struct {
+		__u64 pmi_lp_error  :  1;
+		__u64: 63;
+	};
+};
+
+#define C2_HNI_EXT_ERR_INFO_FSM_OFFSET	0x000001d0
+#define C2_HNI_EXT_ERR_INFO_FSM	(C_HNI_BASE + C2_HNI_EXT_ERR_INFO_FSM_OFFSET)
+#define C2_HNI_EXT_ERR_INFO_FSM_SIZE	0x00000008
+
+union c2_hni_ext_err_info_fsm {
+	__u64 qw;
+	struct {
+		__u64 fsm_timeout         :  1;
+		__u64 fsm_illegal_access  :  1;
+		__u64: 62;
+	};
+};
+
+#define C2_HNI_SERDES_PMI_DATA_OFFSET	0x00000a08
+#define C2_HNI_SERDES_PMI_DATA	(C_HNI_BASE + C2_HNI_SERDES_PMI_DATA_OFFSET)
+#define C2_HNI_SERDES_PMI_DATA_SIZE	0x00000008
+
+union c2_hni_serdes_pmi_data {
+	__u64 qw;
+	struct {
+		__u64 pmi_lp_rddata    : 16;
+		__u64 pmi_lp_wrdata    : 16;
+		__u64 pmi_lp_maskdata  : 16;
+		__u64: 16;
+	};
+};
+
+#define C2_HNI_SERDES_PMI_CTL_OFFSET	0x00000a10
+#define C2_HNI_SERDES_PMI_CTL	(C_HNI_BASE + C2_HNI_SERDES_PMI_CTL_OFFSET)
+#define C2_HNI_SERDES_PMI_CTL_SIZE	0x00000008
+
+union c2_hni_serdes_pmi_ctl {
+	__u64 qw;
+	struct {
+		__u64 pmi_lp_addr      : 32;
+		__u64 pmi_lp_write     :  1;
+		__u64 pmi_lp_read_vld  :  1;
+		__u64 pmi_lp_ack       :  1;
+		__u64 pmi_lp_error     :  1;
+		__u64 pmi_lp_en        :  1;
+		__u64: 27;
+	};
+};
+
+#define SS2_PORT_PML_CFG_CRNC_OFFSET	0x00000000
+#define SS2_PORT_PML_CFG_CRNC	(C_HNI_PML_BASE + SS2_PORT_PML_CFG_CRNC_OFFSET)
+#define SS2_PORT_PML_CFG_CRNC_SIZE	0x00000008
+
+union ss2_port_pml_cfg_crnc {
+	__u64 qw;
+	struct {
+		__u64 csr_timeout   :  8;
+		__u64 mcast_id      : 10;
+		__u64: 1;
+		__u64 mcast_enable  :  1;
+		__u64 mcast_mask    : 10;
+		__u64: 34;
+	};
+};
+
+#define SS2_PORT_PML_MSC_SHADOW_ACTION_OFFSET	0x00000028
+#define SS2_PORT_PML_MSC_SHADOW_ACTION	(C_HNI_PML_BASE + SS2_PORT_PML_MSC_SHADOW_ACTION_OFFSET)
+#define SS2_PORT_PML_MSC_SHADOW_ACTION_SIZE	0x00000008
+#define SS2_PORT_PML_MSC_SHADOW_OFFSET	0x00000030
+#define SS2_PORT_PML_MSC_SHADOW	(C_HNI_PML_BASE + SS2_PORT_PML_MSC_SHADOW_OFFSET)
+#define SS2_PORT_PML_MSC_SHADOW_SIZE	0x00000040
+
+union ss2_port_pml_msc_shadow {
+	__u64 qw[5];
+};
+
+#define SS2_PORT_PML_ERR_ELAPSED_TIME_OFFSET	0x00000100
+#define SS2_PORT_PML_ERR_ELAPSED_TIME	(C_HNI_PML_BASE + SS2_PORT_PML_ERR_ELAPSED_TIME_OFFSET)
+#define SS2_PORT_PML_ERR_ELAPSED_TIME_SIZE	0x00000008
+
+union ss2_port_pml_err_elapsed_time {
+	__u64 qw;
+	struct {
+		__u64 nanoseconds  : 30;
+		__u64 seconds      : 34;
+	};
+};
+
+#define SS2_PORT_PML_ERR_INFO_EDC_COR_OFFSET	0x00000300
+#define SS2_PORT_PML_ERR_INFO_EDC_COR	(C_HNI_PML_BASE + SS2_PORT_PML_ERR_INFO_EDC_COR_OFFSET)
+#define SS2_PORT_PML_ERR_INFO_EDC_COR_SIZE	0x00000008
+
+union ss2_port_pml_err_info_edc_cor {
+	__u64 qw;
+	struct {
+		__u64 syndrome      : 12;
+		__u64 address       : 14;
+		__u64: 1;
+		__u64 csr_detected  :  1;
+		__u64 mem_id        :  5;
+		__u64: 31;
+	};
+};
+
+#define SS2_PORT_PML_ERR_INFO_EDC_UCOR_OFFSET	0x00000308
+#define SS2_PORT_PML_ERR_INFO_EDC_UCOR	(C_HNI_PML_BASE + SS2_PORT_PML_ERR_INFO_EDC_UCOR_OFFSET)
+#define SS2_PORT_PML_ERR_INFO_EDC_UCOR_SIZE	0x00000008
+
+union ss2_port_pml_err_info_edc_ucor {
+	__u64 qw;
+	struct {
+		__u64 syndrome      : 12;
+		__u64 address       : 14;
+		__u64: 1;
+		__u64 csr_detected  :  1;
+		__u64 mem_id        :  5;
+		__u64: 31;
+	};
+};
+
+#define SS2_PORT_PML_ERR_INFO_LLR_TX_DP_SBE_OFFSET	0x00000360
+#define SS2_PORT_PML_ERR_INFO_LLR_TX_DP_SBE	(C_HNI_PML_BASE + SS2_PORT_PML_ERR_INFO_LLR_TX_DP_SBE_OFFSET)
+#define SS2_PORT_PML_ERR_INFO_LLR_TX_DP_SBE_SIZE	0x00000008
+
+union ss2_port_pml_err_info_llr_tx_dp_sbe {
+	__u64 qw;
+	struct {
+		__u64 syndrome  : 11;
+		__u64: 5;
+		__u64 subport   :  2;
+		__u64: 6;
+		__u64 dp_id     :  3;
+		__u64: 37;
+	};
+};
+
+#define SS2_PORT_PML_ERR_INFO_LLR_TX_DP_MBE_OFFSET	0x00000368
+#define SS2_PORT_PML_ERR_INFO_LLR_TX_DP_MBE	(C_HNI_PML_BASE + SS2_PORT_PML_ERR_INFO_LLR_TX_DP_MBE_OFFSET)
+#define SS2_PORT_PML_ERR_INFO_LLR_TX_DP_MBE_SIZE	0x00000008
+
+union ss2_port_pml_err_info_llr_tx_dp_mbe {
+	__u64 qw;
+	struct {
+		__u64 syndrome  : 11;
+		__u64: 5;
+		__u64 subport   :  2;
+		__u64: 6;
+		__u64 dp_id     :  3;
+		__u64: 37;
+	};
+};
+
+#define SS2_PORT_PML_CFG_GENERAL_OFFSET	0x00000400
+#define SS2_PORT_PML_CFG_GENERAL	(C_HNI_PML_BASE + SS2_PORT_PML_CFG_GENERAL_OFFSET)
+#define SS2_PORT_PML_CFG_GENERAL_SIZE	0x00000008
+
+union ss2_port_pml_cfg_general {
+	__u64 qw;
+	struct {
+		__u64 clock_period_ps  : 11;
+		__u64: 53;
+	};
+};
+
+#define SS2_PORT_PML_CFG_PORT_GROUP_OFFSET	0x00000408
+#define SS2_PORT_PML_CFG_PORT_GROUP	(C_HNI_PML_BASE + SS2_PORT_PML_CFG_PORT_GROUP_OFFSET)
+#define SS2_PORT_PML_CFG_PORT_GROUP_SIZE	0x00000008
+
+union ss2_port_pml_cfg_port_group {
+	__u64 qw;
+	struct {
+		__u64 pg_cfg         :  2;
+		__u64: 6;
+		__u64 link_function  :  4;
+		__u64: 52;
+	};
+};
+
+#define SS2_PORT_PML_CFG_SUBPORT_RESET_OFFSET(idx)	(0x00000420 + ((idx) * 8))
+#define SS2_PORT_PML_CFG_SUBPORT_RESET_ENTRIES	4
+#define SS2_PORT_PML_CFG_SUBPORT_RESET(idx)	(C_HNI_PML_BASE + SS2_PORT_PML_CFG_SUBPORT_RESET_OFFSET(idx))
+#define SS2_PORT_PML_CFG_SUBPORT_RESET_SIZE	0x00000020
+
+union ss2_port_pml_cfg_subport_reset {
+	__u64 qw;
+	struct {
+		__u64 warm_rst_from_csr  :  1;
+		__u64: 63;
+	};
+};
+
+#define SS2_PORT_PML_CFG_PCS_SUBPORT_OFFSET(idx)	(0x00000520 + ((idx) * 8))
+#define SS2_PORT_PML_CFG_PCS_SUBPORT_ENTRIES	4
+#define SS2_PORT_PML_CFG_PCS_SUBPORT(idx)	(C_HNI_PML_BASE + SS2_PORT_PML_CFG_PCS_SUBPORT_OFFSET(idx))
+#define SS2_PORT_PML_CFG_PCS_SUBPORT_SIZE	0x00000020
+
+union ss2_port_pml_cfg_pcs_subport {
+	__u64 qw;
+	struct {
+		__u64 pcs_enable       :  1;
+		__u64 enable_auto_neg  :  1;
+		__u64: 14;
+		__u64 ll_fec           :  1;
+		__u64: 47;
+	};
+};
+
+#define SS2_PORT_PML_CFG_TX_PCS_SUBPORT_OFFSET(idx)	(0x000006a0 + ((idx) * 8))
+#define SS2_PORT_PML_CFG_TX_PCS_SUBPORT_ENTRIES	4
+#define SS2_PORT_PML_CFG_TX_PCS_SUBPORT(idx)	(C_HNI_PML_BASE + SS2_PORT_PML_CFG_TX_PCS_SUBPORT_OFFSET(idx))
+#define SS2_PORT_PML_CFG_TX_PCS_SUBPORT_SIZE	0x00000020
+
+union ss2_port_pml_cfg_tx_pcs_subport {
+	__u64 qw;
+	struct {
+		__u64 enable_ctl_os    :  1;
+		__u64 ctl_os_rate      :  1;
+		__u64: 2;
+		__u64 gearbox_credits  :  5;
+		__u64: 55;
+	};
+};
+
+#define SS2_PORT_PML_CFG_RX_PCS_SUBPORT_OFFSET(idx)	(0x000006e0 + ((idx) * 8))
+#define SS2_PORT_PML_CFG_RX_PCS_SUBPORT_ENTRIES	4
+#define SS2_PORT_PML_CFG_RX_PCS_SUBPORT(idx)	(C_HNI_PML_BASE + SS2_PORT_PML_CFG_RX_PCS_SUBPORT_OFFSET(idx))
+#define SS2_PORT_PML_CFG_RX_PCS_SUBPORT_SIZE	0x00000020
+
+union ss2_port_pml_cfg_rx_pcs_subport {
+	__u64 qw;
+	struct {
+		__u64 enable_rx_sm   :  1;
+		__u64 enable_ctl_os  :  1;
+		__u64 enable_lock    :  1;
+		__u64: 5;
+		__u64 rs_mode        :  3;
+		__u64: 53;
+	};
+};
+
+#define SS2_PORT_PML_CFG_TX_MAC_SUBPORT_OFFSET(idx)	(0x00000820 + ((idx) * 8))
+#define SS2_PORT_PML_CFG_TX_MAC_SUBPORT_ENTRIES	4
+#define SS2_PORT_PML_CFG_TX_MAC_SUBPORT(idx)	(C_HNI_PML_BASE + SS2_PORT_PML_CFG_TX_MAC_SUBPORT_OFFSET(idx))
+#define SS2_PORT_PML_CFG_TX_MAC_SUBPORT_SIZE	0x00000020
+
+union ss2_port_pml_cfg_tx_mac_subport {
+	__u64 qw;
+	struct {
+		__u64 mac_operational   :  1;
+		__u64 short_preamble    :  1;
+		__u64: 6;
+		__u64 pcs_credits       :  4;
+		__u64: 4;
+		__u64 mac_cdt_init_val  :  8;
+		__u64 mac_cdt_thresh    :  8;
+		__u64: 32;
+	};
+};
+
+#define SS2_PORT_PML_CFG_RX_MAC_SUBPORT_OFFSET(idx)	(0x00000860 + ((idx) * 8))
+#define SS2_PORT_PML_CFG_RX_MAC_SUBPORT_ENTRIES	4
+#define SS2_PORT_PML_CFG_RX_MAC_SUBPORT(idx)	(C_HNI_PML_BASE + SS2_PORT_PML_CFG_RX_MAC_SUBPORT_OFFSET(idx))
+#define SS2_PORT_PML_CFG_RX_MAC_SUBPORT_SIZE	0x00000020
+
+union ss2_port_pml_cfg_rx_mac_subport {
+	__u64 qw;
+	struct {
+		__u64 mac_operational  :  1;
+		__u64 short_preamble   :  1;
+		__u64: 62;
+	};
+};
+
+#define SS2_PORT_PML_CFG_LLR_SUBPORT_OFFSET(idx)	(0x00000920 + ((idx) * 8))
+#define SS2_PORT_PML_CFG_LLR_SUBPORT_ENTRIES	4
+#define SS2_PORT_PML_CFG_LLR_SUBPORT(idx)	(C_HNI_PML_BASE + SS2_PORT_PML_CFG_LLR_SUBPORT_OFFSET(idx))
+#define SS2_PORT_PML_CFG_LLR_SUBPORT_SIZE	0x00000020
+
+union ss2_port_pml_cfg_llr_subport {
+	__u64 qw;
+	struct {
+		__u64 llr_mode                  :  2;
+		__u64: 6;
+		__u64 enable_loop_timing        :  1;
+		__u64: 7;
+		__u64 filter_ctl_frames         :  1;
+		__u64: 3;
+		__u64 filter_lossless_when_off  :  1;
+		__u64: 3;
+		__u64 mac_if_credits            :  4;
+		__u64: 4;
+		__u64 link_down_behavior        :  2;
+		__u64: 6;
+		__u64 max_starvation_limit      : 16;
+		__u64: 8;
+	};
+};
+
+#define SS2_PORT_PML_CFG_SERDES_RX_OFFSET(idx)	(0x00001000 + ((idx) * 8))
+#define SS2_PORT_PML_CFG_SERDES_RX_ENTRIES	4
+#define SS2_PORT_PML_CFG_SERDES_RX(idx)	(C_HNI_PML_BASE + SS2_PORT_PML_CFG_SERDES_RX_OFFSET(idx))
+#define SS2_PORT_PML_CFG_SERDES_RX_SIZE	0x00000020
+
+union ss2_port_pml_cfg_serdes_rx {
+	__u64 qw;
+	struct {
+		__u64 pmd_rx_lane_mode     : 16;
+		__u64 pmd_rx_osr_mode      :  9;
+		__u64: 3;
+		__u64 pmd_ext_los          :  1;
+		__u64: 3;
+		__u64 pmd_ln_rx_h_pwrdn    :  1;
+		__u64: 3;
+		__u64 pmd_ln_rx_dp_h_rstb  :  1;
+		__u64: 3;
+		__u64 pmd_ln_rx_h_rstb     :  1;
+		__u64: 23;
+	};
+};
+
+#define SS2_PORT_PML_CFG_SERDES_TX_OFFSET(idx)	(0x00001020 + ((idx) * 8))
+#define SS2_PORT_PML_CFG_SERDES_TX_ENTRIES	4
+#define SS2_PORT_PML_CFG_SERDES_TX(idx)	(C_HNI_PML_BASE + SS2_PORT_PML_CFG_SERDES_TX_OFFSET(idx))
+#define SS2_PORT_PML_CFG_SERDES_TX_SIZE	0x00000020
+
+union ss2_port_pml_cfg_serdes_tx {
+	__u64 qw;
+	struct {
+		__u64 pmd_tx_lane_mode     : 16;
+		__u64 pmd_tx_osr_mode      :  9;
+		__u64: 3;
+		__u64 pmd_tx_disable       :  1;
+		__u64: 3;
+		__u64 pmd_ln_tx_h_pwrdn    :  1;
+		__u64: 3;
+		__u64 pmd_ln_tx_dp_h_rstb  :  1;
+		__u64: 3;
+		__u64 pmd_ln_tx_h_rstb     :  1;
+		__u64: 23;
+	};
+};
+
+#define SS2_PORT_PML_STS_SERDES_OFFSET(idx)	(0x00001200 + ((idx) * 8))
+#define SS2_PORT_PML_STS_SERDES_ENTRIES	4
+#define SS2_PORT_PML_STS_SERDES(idx)	(C_HNI_PML_BASE + SS2_PORT_PML_STS_SERDES_OFFSET(idx))
+#define SS2_PORT_PML_STS_SERDES_SIZE	0x00000020
+
+union ss2_port_pml_sts_serdes {
+	__u64 qw;
+	struct {
+		__u64 pmd_signal_detect  :  1;
+		__u64: 3;
+		__u64 pmd_rx_lock        :  1;
+		__u64: 3;
+		__u64 pmd_rx_clk_vld     :  1;
+		__u64: 3;
+		__u64 pmd_rx_data_vld    :  1;
+		__u64: 3;
+		__u64 pmd_tx_clk_vld     :  1;
+		__u64: 3;
+		__u64 pmd_tx_data_vld    :  1;
+		__u64: 3;
+		__u64 rx_signal_ok       :  1;
+		__u64: 39;
+	};
+};
+
+#define SS2_PORT_PML_STS_RX_PCS_AM_LOCK_OFFSET	0x00001380
+#define SS2_PORT_PML_STS_RX_PCS_AM_LOCK	(C_HNI_PML_BASE + SS2_PORT_PML_STS_RX_PCS_AM_LOCK_OFFSET)
+#define SS2_PORT_PML_STS_RX_PCS_AM_LOCK_SIZE	0x00000008
+
+union ss2_port_pml_sts_rx_pcs_am_lock {
+	__u64 qw;
+	struct {
+		__u64 am_lock  : 16;
+		__u64: 48;
+	};
+};
+
+#define SS2_PORT_PML_STS_RX_PCS_SUBPORT_OFFSET(idx)	(0x000013a0 + ((idx) * 8))
+#define SS2_PORT_PML_STS_RX_PCS_SUBPORT_ENTRIES	4
+#define SS2_PORT_PML_STS_RX_PCS_SUBPORT(idx)	(C_HNI_PML_BASE + SS2_PORT_PML_STS_RX_PCS_SUBPORT_OFFSET(idx))
+#define SS2_PORT_PML_STS_RX_PCS_SUBPORT_SIZE	0x00000020
+
+union ss2_port_pml_sts_rx_pcs_subport {
+	__u64 qw;
+	struct {
+		__u64: 4;
+		__u64 align_status  :  1;
+		__u64: 3;
+		__u64 fault         :  1;
+		__u64: 3;
+		__u64 local_fault   :  1;
+		__u64: 3;
+		__u64 hi_ser        :  1;
+		__u64: 47;
+	};
+};
+
+#define C2_IXE_CFG_DISP_ORD_OFFSET	0x000007a8
+#define C2_IXE_CFG_DISP_ORD	(C_IXE_BASE + C2_IXE_CFG_DISP_ORD_OFFSET)
+#define C2_IXE_CFG_DISP_ORD_SIZE	0x00000008
+
+union c2_ixe_cfg_disp_ord {
+	__u64 qw;
+	struct {
+		__u64 wr_atomic_op  :  1;
+		__u64 get_ro_last   :  1;
+		__u64 get_ro_body   :  1;
+		__u64: 61;
+	};
+};
+
+#define C2_LPE_CFG_MATCH_SEL_OFFSET	0x00000a20
+#define C2_LPE_CFG_MATCH_SEL	(C_LPE_BASE + C2_LPE_CFG_MATCH_SEL_OFFSET)
+#define C2_LPE_CFG_MATCH_SEL_SIZE	0x00000008
+
+union c2_lpe_cfg_match_sel {
+	__u64 qw;
+	struct {
+		__u64 vni_cfg  :  2;
+		__u64: 62;
+	};
+};
+
+#define C2_LPE_CFG_GET_FQ_DFA_MASK_OFFSET(idx)	(0x00000b00 + ((idx) * 8))
+#define C2_LPE_CFG_GET_FQ_DFA_MASK_ENTRIES	16
+#define C2_LPE_CFG_GET_FQ_DFA_MASK(idx)	(C_LPE_BASE + C2_LPE_CFG_GET_FQ_DFA_MASK_OFFSET(idx))
+#define C2_LPE_CFG_GET_FQ_DFA_MASK_SIZE	0x00000080
+
+union c2_lpe_cfg_get_fq_dfa_mask {
+	__u64 qw;
+	struct {
+		__u64 dscp0_dfa_mask  : 12;
+		__u64: 4;
+		__u64 dscp1_dfa_mask  : 12;
+		__u64: 4;
+		__u64 dscp2_dfa_mask  : 12;
+		__u64: 4;
+		__u64 dscp3_dfa_mask  : 12;
+		__u64: 4;
+	};
+};
+
+#define C2_OXE_ERR_INFO_SPT_CDT_ERR_OFFSET	0x000001e8
+#define C2_OXE_ERR_INFO_SPT_CDT_ERR	(C_OXE_BASE + C2_OXE_ERR_INFO_SPT_CDT_ERR_OFFSET)
+#define C2_OXE_ERR_INFO_SPT_CDT_ERR_SIZE	0x00000008
+
+union c2_oxe_err_info_spt_cdt_err {
+	__u64 qw;
+	struct {
+		__u64 index  : 11;
+		__u64: 5;
+		__u64 bc     :  4;
+		__u64: 44;
+	};
+};
+
+#define C2_OXE_ERR_INFO_SMT_CDT_ERR_OFFSET	0x000001f0
+#define C2_OXE_ERR_INFO_SMT_CDT_ERR	(C_OXE_BASE + C2_OXE_ERR_INFO_SMT_CDT_ERR_OFFSET)
+#define C2_OXE_ERR_INFO_SMT_CDT_ERR_SIZE	0x00000008
+
+union c2_oxe_err_info_smt_cdt_err {
+	__u64 qw;
+	struct {
+		__u64 index  :  8;
+		__u64: 8;
+		__u64 bc     :  4;
+		__u64: 44;
+	};
+};
+
+#define C2_OXE_CFG_SPT_BC_LIMIT_OFFSET(idx)	(0x00000680 + ((idx) * 8))
+#define C2_OXE_CFG_SPT_BC_LIMIT_ENTRIES	10
+#define C2_OXE_CFG_SPT_BC_LIMIT(idx)	(C_OXE_BASE + C2_OXE_CFG_SPT_BC_LIMIT_OFFSET(idx))
+#define C2_OXE_CFG_SPT_BC_LIMIT_SIZE	0x00000050
+
+union c2_oxe_cfg_spt_bc_limit {
+	__u64 qw;
+	struct {
+		__u64 limit  : 11;
+		__u64: 53;
+	};
+};
+
+#define C2_PI_ERR_INFO_AHB_OFFSET	0x00000300
+#define C2_PI_ERR_INFO_AHB	(C_PI_BASE + C2_PI_ERR_INFO_AHB_OFFSET)
+#define C2_PI_ERR_INFO_AHB_SIZE	0x00000018
+
+union c2_pi_err_info_ahb {
+	__u64 qw[3];
+	struct {
+		__u64 hwrite      :  1;
+		__u64 htrans      :  2;
+		__u64 hsize       :  3;
+		__u64 hrdata_sel  :  4;
+		__u64: 5;
+		__u64 ahb_err_id  :  1;
+		__u64 haddr       : 14;
+		__u64: 2;
+		__u64 hsel        : 16;
+		__u64: 16;
+		__u64 req         :  1;
+		__u64: 31;
+		__u64 hwdata      : 32;
+		__u64 done        : 16;
+		__u64 hresp       : 16;
+		__u64 hrdata      : 32;
+	};
+};
+
+
+
+struct c_cq_cntrs_group {
+	struct c_cq_cntrs cq;
+	struct c_tou_cntrs tou;
+	struct c_pct_cntrs pct;
+	struct c_ee_cntrs ee;
+};
+
+struct c_lpe_cntrs_group {
+	struct c_lpe_cntrs lpe;
+	struct c_ixe_cntrs ixe;
+	struct c_rmu_cntrs rmu;
+	struct c_parbs_cntrs parbs;
+	struct c_mst_cntrs mst;
+};
+
+struct c_hni_cntrs_group {
+	struct c_hni_cntrs hni;
+	struct c1_hni_pcs_cntrs pcs;
+	struct c1_hni_mac_cntrs mac;
+	struct c1_hni_llr_cntrs llr;
+	struct c1_oxe_cntrs oxe;
+};
+
+struct c_mb_cntrs_group {
+	struct c_mb_cntrs mb;
+	struct c_pi_cntrs pi;
+	struct c_atu_cntrs atu;
+};
+
+struct c_pi_ipd_cntrs_group {
+	struct c_pi_ipd_cntrs pi_ipd;
+};
+
+
+
+#define  C_PI_CFG_DMAC_STATUS_AXI_RESP_OKAY             (0)
+#define  C_PI_CFG_DMAC_STATUS_AXI_RESP_EXOKAY           (1)
+#define  C_PI_CFG_DMAC_STATUS_AXI_RESP_SLVERR           (2)
+#define  C_PI_CFG_DMAC_STATUS_AXI_RESP_DECERR           (3)
+
+#define  C_PI_DMAC_CDESC_STATUS_AXI_RESP_OKAY           \
+	C_PI_CFG_DMAC_STATUS_AXI_RESP_OKAY
+#define  C_PI_DMAC_CDESC_STATUS_AXI_RESP_EXOKAY         \
+	C_PI_CFG_DMAC_STATUS_AXI_RESP_EXOKAY
+#define  C_PI_DMAC_CDESC_STATUS_AXI_RESP_SLVERR         \
+	C_PI_CFG_DMAC_STATUS_AXI_RESP_SLVERR
+#define  C_PI_DMAC_CDESC_STATUS_AXI_RESP_DECERR         \
+	C_PI_CFG_DMAC_STATUS_AXI_RESP_DECERR
+
+
+#endif
diff --git a/usr/include/Makefile b/usr/include/Makefile
index ee69dd9d970e..43c4609db1d4 100644
--- a/usr/include/Makefile
+++ b/usr/include/Makefile
@@ -62,6 +62,11 @@ endif
 # asm-generic/*.h is used by asm/*.h, and should not be included directly
 no-header-test += asm-generic/%
 
+# Shared with the out-of-tree CXI userspace library. It provides inline
+# accessors and so pulls in errno.h, string.h and size_t, none of which a
+# standalone UAPI header can rely on.
+no-header-test += ethernet/cassini_user_defs.h
+
 # The following are not compatible with C++.
 #
 # Do not add a new header to the list without legitimate reason.

-- 
2.56.0


^ permalink raw reply	[flat|nested] 25+ messages in thread
* [PATCH 02/23] net: hpe: sbl: add the Slingshot Base Link headers
  2026-10-30 20:58 [PATCH 00/23] Subject: [PATCH net-next 00/23] net/hpe: add HPE Slingshot NIC drivers Doug Ledford
  2026-10-30 20:58 ` [PATCH 01/23] net: hpe: ss1: add the Cassini headers Doug Ledford
@ 2026-10-30 20:58 ` Doug Ledford
  2026-10-30 20:58 ` [PATCH 03/23] net: hpe: sbl: add the core instance and configuration layer Doug Ledford
                   ` (21 subsequent siblings)
  23 siblings, 0 replies; 25+ messages in thread
From: Doug Ledford @ 2026-10-30 20:58 UTC (permalink / raw)
  To: Slingshot Open Source Team, Nathan Chancellor, Nicolas Schier,
	Richard Cochran, Andrew Lunn, David S. Miller, Eric Dumazet,
	Jakub Kicinski, Paolo Abeni, Sumit Semwal, Christian König,
	Guenter Roeck
  Cc: linux-kernel, netdev, linux-kbuild, Doug Ledford, Sandeep Bhoot,
	Iraimani P

Add the headers for the Slingshot Base Link (SBL) driver, the 200 Gb/s
link layer used by the first generation Cassini NIC.  SBL owns link
bring-up for the PML (MAC/PCS/LLR), SerDes and auto-negotiation blocks
and exposes its interface to the NIC driver through sbl.h.

sbl-abi.h and sbl_serdes.h live in include/uapi/ethernet because the
same files are shared with user space tools that query the link; the
SerDes helpers that are not part of that ABI sit in the kernel-only
include/linux/hpe/sbl/sbl.h.

Every header of the driver, including those private to one layer, is
added here so that each later patch, which adds the sources of one
layer, compiles on its own.

The Kconfig and Makefile hookup for this driver is deliberately the
last patch of the driver group, so that every earlier patch adds
sources without changing what the tree builds.

checkpatch --strict (100 columns) still reports the following in this
patch. They need coordination with the internal repositories this code
is maintained in and will be fixed in V2:
- ERROR: COMPLEX_MACRO (1)
- WARNING: LONG_LINE_COMMENT (60), MACRO_ARG_UNUSED (18), LONG_LINE
  (16), BLOCK_COMMENT_STYLE (4)
- CHECK: SPACING (119), LINE_SPACING (47), BIT_MACRO (31),
  PARENTHESIS_ALIGNMENT (23), MACRO_ARG_PRECEDENCE (22), MACRO_ARG_REUSE
  (5), PREFER_KERNEL_TYPES (2), BRACES (1)

Co-developed-by: Sandeep Bhoot <sandeep.bhoot@hpe.com>
Signed-off-by: Sandeep Bhoot <sandeep.bhoot@hpe.com>
Co-developed-by: Iraimani P <iraimani.pavadai@hpe.com>
Signed-off-by: Iraimani P <iraimani.pavadai@hpe.com>
Signed-off-by: Doug Ledford <doug.ledford@hpe.com>
---
 drivers/net/ethernet/hpe/sbl/sbl_config_list.h |   61 ++
 drivers/net/ethernet/hpe/sbl/sbl_constants.h   |  352 ++++++++
 drivers/net/ethernet/hpe/sbl/sbl_internal.h    |  279 ++++++
 drivers/net/ethernet/hpe/sbl/sbl_link.h        |   44 +
 drivers/net/ethernet/hpe/sbl/sbl_platform.h    |   35 +
 drivers/net/ethernet/hpe/sbl/sbl_pml_fn.h      |  132 +++
 drivers/net/ethernet/hpe/sbl/sbl_sbm.h         |   73 ++
 drivers/net/ethernet/hpe/sbl/sbl_sbm_serdes.h  |  152 ++++
 drivers/net/ethernet/hpe/sbl/sbl_serdes.h      |   94 +++
 drivers/net/ethernet/hpe/sbl/sbl_serdes_fn.h   |  151 ++++
 drivers/net/ethernet/hpe/sbl/sbl_serdes_map.h  |   10 +
 include/linux/hpe/sbl/sbl.h                    |  436 ++++++++++
 include/linux/hpe/sbl/sbl_an.h                 |  174 ++++
 include/linux/hpe/sbl/sbl_csr_common.h         |   63 ++
 include/linux/hpe/sbl/sbl_fec.h                |   88 ++
 include/linux/hpe/sbl/sbl_kconfig.h            |   33 +
 include/linux/hpe/sbl/sbl_mb.h                 |   77 ++
 include/linux/hpe/sbl/sbl_platform.h           |   35 +
 include/linux/hpe/sbl/sbl_pml.h                | 1081 ++++++++++++++++++++++++
 include/linux/hpe/sbl/sbl_test.h               |   20 +
 include/uapi/ethernet/sbl-abi.h                |  648 ++++++++++++++
 include/uapi/ethernet/sbl_cassini.h            |   21 +
 include/uapi/ethernet/sbl_counters.h           |  152 ++++
 include/uapi/ethernet/sbl_platform_config.h    |   13 +
 include/uapi/ethernet/sbl_sbm_constants.h      |  330 ++++++++
 include/uapi/ethernet/sbl_serdes.h             |  390 +++++++++
 include/uapi/ethernet/sbl_serdes_defaults.h    |   66 ++
 include/uapi/ethernet/sbl_serdes_map.h         |   41 +
 include/uapi/ethernet/sbl_serdes_map_init.h    |   65 ++
 29 files changed, 5116 insertions(+)

diff --git a/drivers/net/ethernet/hpe/sbl/sbl_config_list.h b/drivers/net/ethernet/hpe/sbl/sbl_config_list.h
new file mode 100644
index 000000000000..568e5fdeccd0
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sbl/sbl_config_list.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2019-2026 Hewlett Packard Enterprise Development LP. All rights reserved. */
+
+#ifndef SBL_CONFIG_LIST_H
+#define SBL_CONFIG_LIST_H
+
+#include <uapi/ethernet/sbl_serdes.h>
+#include <uapi/ethernet/sbl_serdes_defaults.h>
+
+/* A SerDes configuration list entry specifies a set of config values which
+ * are selected to get the SerDes to tune reliably for a given setup. Some default
+ * entries are statically defined - additional entries can be added and removed from the
+ * list dynamically
+ *
+ * To add a static serdes configuration
+ * 1. create an initializer as below
+ * 2. create an static structure in sbl_init.c
+ * 3. Add the structure into sbl_setup_serdes_configs()
+ *
+ */
+struct sbl_serdes_config {
+	u64 tp_state_mask0;         /* State lookup mask */
+	u64 tp_state_mask1;         /* State lookup mask */
+	u64 tp_state_match0;        /* match values after masking */
+	u64 tp_state_match1;        /* match values after masking */
+	u64 port_mask;              /* applicable ports */
+	u8  serdes_mask;            /* applicable serdes */
+	struct sbl_sc_values vals;  /* Configuration values */
+
+	struct list_head list;
+	bool is_default;            /* Default configuration */
+	u32 tag;                    /* tag for debugging */
+};
+
+/* Default serdes config initializer */
+#define SBL_SERDES_CONFIG_INITIALIZER					\
+{									\
+	/*                   --mlmlmtlmtplblp           */              \
+	.tp_state_mask0	 = 0x0000000000000000,				\
+	/*                   mvmvmvmvmvmvmvmv           */              \
+	.tp_state_mask1	 = 0x0000000000000000,				\
+	.tp_state_match0 = 0x0000000000000000,				\
+	.tp_state_match1 = 0x0000000000000000,				\
+	.port_mask	 = 0xffffffffffffffff,				\
+	.serdes_mask	 = 0xf,						\
+	.vals = {							\
+		.magic		= SBL_SERDES_CONFIG_MAGIC,		\
+		.atten		= SBL_DFLT_PORT_CONFIG_ATTEN,		\
+		.pre		= SBL_DFLT_PORT_CONFIG_PRE,		\
+		.post		= SBL_DFLT_PORT_CONFIG_POST,		\
+		.pre2		= SBL_DFLT_PORT_CONFIG_PRE2,		\
+		.pre3		= SBL_DFLT_PORT_CONFIG_PRE3,		\
+		.gs1		= SBL_DFLT_PORT_CONFIG_GS1_OPTICAL,	\
+		.gs2		= SBL_DFLT_PORT_CONFIG_GS2_OPTICAL,	\
+		.num_intr	= SBL_DFLT_PORT_CONFIG_NUM_INTR,	\
+		.intr_val	= SBL_DFLT_PORT_CONFIG_INTR_VAL,	\
+		.data_val	= SBL_DFLT_PORT_CONFIG_DATA_VAL,	\
+	},								\
+}
+
+#endif /* SBL_CONFIG_LIST_H */
diff --git a/drivers/net/ethernet/hpe/sbl/sbl_constants.h b/drivers/net/ethernet/hpe/sbl/sbl_constants.h
new file mode 100644
index 000000000000..a21a43f84a04
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sbl/sbl_constants.h
@@ -0,0 +1,352 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/* Copyright 2020-2026 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SBL_CONSTANTS_H_
+#define _SBL_CONSTANTS_H_
+
+#ifdef TRACE2
+#define dev_trace2 dev_dbg
+#endif /* TRACE2 */
+
+#ifdef TRACE3
+#define dev_trace3 dev_dbg
+#endif /* TRACE3 */
+
+#define SBL_MODEL_ROS_COLORADO "sc-ros"
+#define SBL_MODEL_ROS_COLUMBIA "sc-ros-tor"
+#define SBL_MODEL_ROS_TEXAS "sc-ros-tex"
+
+#define SBUS_ADDR(ring, rx_addr)        ((ring << 8) | rx_addr)
+#define SBUS_RING(sbus_addr)            ((sbus_addr & 0x300) >> 8)
+#define SBUS_RX_ADDR(sbus_addr)         (sbus_addr & 0xff)
+
+#define SBL_FW_REV_LEN		4
+#define SBL_FW_BUILD_LEN	4
+
+#define LEVEL_ERR                            4
+#define LEVEL_WARN                           3
+#define LEVEL_INFO                           2
+#define LEVEL_DBG                            1
+
+#define SERDES_OP_TIMEOUT_MS          1000
+#define SBUS_OP_TIMEOUT_MS            1000
+#define SERDES_OP_FLAGS               (SBL_FLAG_INTERVAL_1MS | SBL_FLAG_DELAY_5US)
+
+#define SBL_ALL_PORTS                 -1
+
+#define SBL_CONFIG_RX_PHASE_SLIP_CNT_DFLT    0xc
+#define SBL_CONFIG_DFE_PRE_DELAY_DFLT        0x0
+#define SBL_CONFIG_DFE_TIMEOUT_MS_DFLT       5000
+#define SBL_CONFIG_DFE_RETRY_CNT_DFLT        2
+#define SBL_CONFIG_NRZ_MIN_EYE_HEIGHT_DFLT   0xc0
+#define SBL_CONFIG_PAM4_MIN_EYE_HEIGHT_DFLT  0x10
+
+#define SBL_PORT_CONFIG_LINK_PARTNER_DFLT         0
+#define SBL_PORT_CONFIG_TUNING_PATTERN_DFLT       0
+#define SBL_PORT_CONFIG_LOOPBACK_MODE_DFLT        0
+#define SBL_PORT_CONFIG_LINK_MODE_DFLT            0
+
+/* Provided by SI */
+#define SBL_ENC_NRZ                 SPICO_INT_DATA_ENC_NRZ
+#define SBL_DIV_25G                 165
+#define SBL_WID_25G                 SPICO_INT_DATA_WIDTH_25G
+#define SBL_ENC_PAM4                SPICO_INT_DATA_ENC_PAM4
+#define SBL_DIV_50G                 170
+#define SBL_WID_50G                 SPICO_INT_DATA_WIDTH_50G
+#define SBL_DIV_AN                  8
+#define SBL_WID_AN                  SPICO_INT_DATA_WIDTH_2_5G
+
+#define SBL_RX_TERM_AGND            0
+#define SBL_RX_TERM_AVDD            1
+#define SBL_RX_TERM_FLOAT           2
+
+#define SBL_DS_CORE                 0
+#define SBL_DS_PRBS                 1
+
+#define SBL_SERDES_REFCLK           126250000
+
+#define SBL_SBUS_DIVIDER_DFLT       3 /* clock divider of 8 */
+#define SBL_SBUS_DIVIDER_SPEEDUP    1 /* clock divider of 2 */
+
+#define SPICO_SBR_DATA_NONE                0x00000000
+#define SPICO_SBR_DATA_SET_BURST_WR        0x80000000
+#define SPICO_SBR_DATA_RESET_HIGH          0x000000c0
+#define SPICO_SBR_DATA_RESET_LOW           0x00000040
+#define SPICO_SBR_DATA_IMEM_CNTL_EN        0x00000240
+#define SPICO_SBR_DATA_IMEM_CNTL_EN_RD     0x00000340
+#define SPICO_SBR_DATA_IMEM_CNTL_DIS       0x00000040
+#define SPICO_SBR_DATA_ECC_EN              0x000c0000
+#define SPICO_SBR_DATA_SPICO_EN            0x00000140
+#define SPICO_SBR_DATA_BE_012              0xc0000000
+#define SPICO_SBR_DATA_BE_01               0x80000000
+#define SPICO_SBR_DATA_BE_0                0x40000000
+
+#define SPICO_SBR_DATA_W0_OFFSET           0
+#define SPICO_SBR_DATA_W1_OFFSET           10
+#define SPICO_SBR_DATA_W2_OFFSET           20
+
+#define SPICO_SERDES_DATA_SET_GLOBAL_RESET  0x00000011
+#define SPICO_SERDES_DATA_CLR_GLOBAL_RESET  0x00000010
+#define SPICO_SERDES_DATA_SET_INTR_DIS      0x00000030
+#define SPICO_SERDES_DATA_SET_IMEM_CNTL_EN  0xc0000000
+#define SPICO_SERDES_DATA_CLR_IMEM_CNTL_EN  0x00000000
+#define SPICO_SERDES_DATA_SET_ECC_EN        0x000c0000
+#define SPICO_SERDES_DATA_CLR_ECC_ERR       0xc0000000
+#define SPICO_SERDES_DATA_SET_SPICO_EN      0x00000002
+#define SPICO_SERDES_DATA_SET_INTR_EN       0x00000000
+#define SPICO_SERDES_DATA_RESET             0x00000000
+
+#define SPICO_STATE_RESET                   0x00000000
+#define SPICO_STATE_PAUSE                   0x00000012
+#define SPICO_STATE_ERROR                   0x0000001f
+#define SPICO_STATE_MASK                    0x0000001f
+
+#define SPICO_INT_DATA_NONE             0x0000
+#define SPICO_INT_DATA_SERDES_EN_OFF    0x0000
+#define SPICO_INT_DATA_BR_1_25          0x9008
+#define SPICO_INT_DATA_ELB              0x0100
+#define SPICO_INT_DATA_ILB              0x0101
+#define SPICO_INT_DATA_WM_20NRZ         0x0011
+#define SPICO_INT_DATA_TPCE             0x0001 /* TX Phase Cal Enable */
+#define SPICO_INT_DATA_STRUCT_OFFSET    0x8
+#define SPICO_INT_DATA_MEMBER_OFFSET    0x0
+#define SPICO_INT_DATA_STRUCT_CLTE      0x09
+#define SPICO_INT_DATA_HF_MIN           0x07
+#define SPICO_INT_DATA_HF_MAX           0x08
+#define SPICO_INT_DATA_SET_TX_EN        0x0001
+#define SPICO_INT_DATA_SET_RX_EN        0x0002
+#define SPICO_INT_DATA_SET_TXO_EN       0x0004
+#define SPICO_INT_DATA_ENC_NRZ          0x0000
+#define SPICO_INT_DATA_ENC_PAM4         0x0088
+#define SPICO_INT_DATA_WIDTH_2_5G       0x0022
+#define SPICO_INT_DATA_WIDTH_25G        0x0033 /* width-mode: 40 */
+#define SPICO_INT_DATA_WIDTH_50G        0x0077 /* width-mode: 80 */
+#define SPICO_INT_DATA_TX_OVERRIDE      0x0020
+#define SPICO_INT_DATA_RX_EID_EN        0x0040
+#define SPICO_INT_DATA_SET_TXINV        0x0101
+#define SPICO_INT_DATA_CLR_TXINV        0x0100
+#define SPICO_INT_DATA_SET_RXINV        0x0210
+#define SPICO_INT_DATA_CLR_RXINV        0x0200
+#define SPICO_INT_DATA_SET_PRECODE      0x0344
+#define SPICO_INT_DATA_CLR_PRECODE      0x0300
+#define SPICO_INT_DATA_SET_GRAY_SWZ     0x0caa
+#define SPICO_INT_DATA_CLR_GRAY_SWZ     0x0c00
+#define SPICO_INT_DATA_RXT_AGND         0x0000
+#define SPICO_INT_DATA_RXT_AVDD         0x0001
+#define SPICO_INT_DATA_RXT_FLOAT        0x0002
+#define SPICO_INT_DATA_SET_LOOPBACK     0x0101
+#define SPICO_INT_DATA_CLR_LOOPBACK     0x0100
+#define SPICO_INT_DATA_PRBS31_AS_TXGEN  0x0125
+#define SPICO_INT_DATA_PRBS31_AS_RXGEN  0x0235
+#define SPICO_INT_DATA_DISABLE_TXRXGEN  0x03ff
+#define SPICO_INT_DATA_TXTX_RC_NOT_SS   0x9000
+#define SPICO_INT_DATA_TXRX_FC_IGNORE   0x8800
+#define SPICO_INT_DATA_DFE_ICAL         0x0001
+#define SPICO_INT_DATA_DFE_CONT_PCAL    0x0006
+#define SPICO_INT_DATA_DFE_PAUSE_PCAL   0x0002
+#define SPICO_INT_DATA_DFE_READ_PARAMS  0x5b00
+#define SPICO_INT_DATA_SET_TXEQ_PRE1    0x0000
+#define SPICO_INT_DATA_SET_TXEQ_PRE2    0xc000
+#define SPICO_INT_DATA_SET_TXEQ_PRE3    0x3000
+#define SPICO_INT_DATA_SET_TXEQ_POST    0x8000
+#define SPICO_INT_DATA_SET_TXEQ_ATTEN   0x4000
+#define SPICO_INT_DATA_GET_TXEQ_PRE1    0x0100
+#define SPICO_INT_DATA_GET_TXEQ_PRE2    0xc100
+#define SPICO_INT_DATA_GET_TXEQ_PRE3    0x3100
+#define SPICO_INT_DATA_GET_TXEQ_POST    0x8100
+#define SPICO_INT_DATA_GET_TXEQ_ATTEN   0x4100
+#define SPICO_INT_DATA_TXEQ_DATA_MASK   0x00ff
+#define SPICO_INT_DATA_RXEQ_VAL_MASK    0x00ff
+#define SPICO_INT_DATA_PRBS_SUCCESS     0x0002
+#define SPICO_INT_DATA_PRBS_RETRY       0x0000
+#define SPICO_INT_DATA_PROC_RESET       0x0001
+
+#define SPICO_INT_DATA_RXEQ_STS_DFE_ST  0x0a00
+#define SPICO_INT_DATA_RXEQ_STS_DFE_STS 0x0b00
+#define SPICO_INT_DATA_RXEQ_FFE_PRE2    0x1000
+#define SPICO_INT_DATA_RXEQ_FFE_PRE1    0x1100
+#define SPICO_INT_DATA_RXEQ_FFE_POST1   0x1200
+#define SPICO_INT_DATA_RXEQ_FFE_BFLF    0x1300
+#define SPICO_INT_DATA_RXEQ_FFE_BFHF    0x1400
+#define SPICO_INT_DATA_RXEQ_FFE_DRATE   0x1500
+#define SPICO_INT_DATA_RXEQ_CTLE_HF     0x2000
+#define SPICO_INT_DATA_RXEQ_CTLE_LF     0x2100
+#define SPICO_INT_DATA_RXEQ_CTLE_BW     0x2200
+#define SPICO_INT_DATA_RXEQ_CTLE_GS1    0x2400
+#define SPICO_INT_DATA_RXEQ_CTLE_GS2    0x2500
+#define SPICO_INT_DATA_RXEQ_DFE_GAIN    0x3000
+#define SPICO_INT_DATA_RXEQ_DFE_GAIN2   0x3100
+#define SPICO_INT_DATA_RXEQ_DFE_2       0x3200
+#define SPICO_INT_DATA_RXEQ_DFE_3       0x3300
+#define SPICO_INT_DATA_RXEQ_DFE_4       0x3400
+#define SPICO_INT_DATA_RXEQ_DFE_5       0x3500
+#define SPICO_INT_DATA_RXEQ_DFE_6       0x3600
+#define SPICO_INT_DATA_RXEQ_DFE_7       0x3700
+#define SPICO_INT_DATA_RXEQ_DFE_8       0x3800
+#define SPICO_INT_DATA_RXEQ_DFE_9       0x3900
+#define SPICO_INT_DATA_RXEQ_DFE_A       0x3a00
+#define SPICO_INT_DATA_RXEQ_DFE_B       0x3b00
+#define SPICO_INT_DATA_RXEQ_DFE_C       0x3c00
+#define SPICO_INT_DATA_RXEQ_EH_THLE     0x4000
+#define SPICO_INT_DATA_RXEQ_EH_THME     0x4100
+#define SPICO_INT_DATA_RXEQ_EH_THUE     0x4200
+#define SPICO_INT_DATA_RXEQ_EH_THLO     0x4300
+#define SPICO_INT_DATA_RXEQ_EH_THMO     0x4400
+#define SPICO_INT_DATA_RXEQ_EH_THUO     0x4500
+
+#define SPICO_INT_DATA_RXEQ_SIGN_MASK   0x8000
+#define SPICO_INT_DATA_RXEQ_VAL_MASK    0x00ff
+
+#define SPICO_INT_DATA_HAL_DFE_APPLY    0x0018
+#define SPICO_INT_DATA_HAL_CTLE_APPLY   0x0015
+#define SPICO_INT_DATA_HAL_FFE_APPLY    0x0012
+#define SPICO_INT_DATA_HAL_RXV_APPLY    0x0003
+#define SPICO_INT_DATA_HAL_DC_APPLY     0x000a
+#define SPICO_INT_DATA_HAL_TC_APPLY     0x000d
+#define SPICO_INT_DATA_HAL_PCAL_SETUP   0x003f
+#define SPICO_INT_DATA_HAL_CTLE_HF      0x0900
+#define SPICO_INT_DATA_HAL_CTLE_LF      0x0901
+#define SPICO_INT_DATA_HAL_CTLE_DC      0x0902
+#define SPICO_INT_DATA_HAL_CTLE_BW      0x0903
+#define SPICO_INT_DATA_HAL_CTLE_GS1     0x0904
+#define SPICO_INT_DATA_HAL_CTLE_GS2     0x0905
+#define SPICO_INT_DATA_HAL_CTLE_SCE     0x0906
+#define SPICO_INT_DATA_HAL_FFE_PRE2     0x0d00
+#define SPICO_INT_DATA_HAL_FFE_PRE1     0x0d01
+#define SPICO_INT_DATA_HAL_FFE_POST1    0x0d02
+#define SPICO_INT_DATA_HAL_FFE_4        0x0d03
+#define SPICO_INT_DATA_HAL_FFE_5        0x0d04
+#define SPICO_INT_DATA_HAL_FFE_6        0x0d05
+#define SPICO_INT_DATA_HAL_FFE_7        0x0d06
+#define SPICO_INT_DATA_HAL_DFE_GT1      0x0b00
+#define SPICO_INT_DATA_HAL_DFE_GT2      0x0b01
+#define SPICO_INT_DATA_HAL_DFE_G2       0x0b02
+#define SPICO_INT_DATA_HAL_DFE_G3       0x0b03
+#define SPICO_INT_DATA_HAL_DFE_G4       0x0b04
+#define SPICO_INT_DATA_HAL_DFE_G5       0x0b05
+#define SPICO_INT_DATA_HAL_DFE_G6       0x0b06
+#define SPICO_INT_DATA_HAL_DFE_G7       0x0b07
+#define SPICO_INT_DATA_HAL_DFE_G8       0x0b08
+#define SPICO_INT_DATA_HAL_DFE_G9       0x0b09
+#define SPICO_INT_DATA_HAL_DFE_G10      0x0b0a
+#define SPICO_INT_DATA_HAL_DFE_G11      0x0b0b
+#define SPICO_INT_DATA_HAL_DFE_G12      0x0b0c
+#define SPICO_INT_DATA_HAL_DFE_G13      0x0b0d
+#define SPICO_INT_DATA_HAL_GTP_CTLE_FX  0x0108
+#define SPICO_INT_DATA_HAL_GTP_FFE_FX   0x0109
+#define SPICO_INT_DATA_HAL_GTP_DFE_FX   0x010a
+#define SPICO_INT_DATA_HAL_GTP_VER_FX   0x0115
+#define SPICO_INT_DATA_HAL_CTLE_BASE    0x0900
+#define SPICO_INT_DATA_HAL_FFE_BASE     0x0d00
+#define SPICO_INT_DATA_HAL_DFE_BASE     0x0b00
+#define SPICO_INT_DATA_HAL_RXVS_BASE    0x0300 /* Rx clock vernier settings */
+#define SPICO_INT_DATA_HAL_RXVS_OFFSET  0x0005 /* Rx clock vernier settings */
+#define SPICO_INT_DATA_HAL_RXVC_BASE    0x2f00 /* Rx clock vernier cals */
+#define SPICO_INT_DATA_HAL_RSDO_BASE    0x0f00
+#define SPICO_INT_DATA_HAL_RSDC_BASE    0x1100
+#define SPICO_INT_DATA_HAL_RSTO_BASE    0x1200
+#define SPICO_INT_DATA_HAL_RSTC_BASE    0x1400
+#define SPICO_INT_DATA_HAL_EH_BASE      0x1700
+#define SPICO_INT_DATA_HAL_GTP_BASE     0x0100
+#define SPICO_INT_DATA_HAL_DCCD_BASE    0x2c00
+#define SPICO_INT_DATA_HAL_P4LV_BASE    0x1f00
+
+#define SPICO_INT_DATA_ICAL_EFFORT_SEL  0x0118
+#define SPICO_INT_DATA_ICAL_EFFORT_0    0x0000 /* Min effort */
+#define SPICO_INT_DATA_ICAL_EFFORT_1    0x0001 /* Max effort */
+#define SPICO_INT_DATA_ICAL_EFFORT_2    0x0002 /* Min effort w/o vernier rst */
+#define SPICO_INT_DATA_ICAL_EFFORT_10   0x0010 /* Med effort */
+
+#define SPICO_INT_DATA_ICAL_MAX_EFFORT  SPICO_INT_DATA_ICAL_EFFORT_1
+#define SPICO_INT_DATA_ICAL_MED_EFFORT  SPICO_INT_DATA_ICAL_EFFORT_10
+#define SPICO_INT_DATA_ICAL_MIN_EFFORT  SPICO_INT_DATA_ICAL_EFFORT_0
+
+#define SPICO_INT_DATA_EID_FILTER_SEL   0x011c
+#define SPICO_INT_DATA_EID_FILTER_DFE   0x0155
+#define SPICO_INT_DATA_EID_FILTER_OFF   0x0000
+
+#define SBUS_AFE_CTRL_KNOWN_FW0_BASE     0x039e /* Different for each FW build */
+
+#define TXEQ_PRE1_MIN                   -31
+#define TXEQ_PRE1_MAX                   31
+#define TXEQ_PRE2_MIN                   -31
+#define TXEQ_PRE2_MAX                   31
+#define TXEQ_PRE3_MIN                   -1
+#define TXEQ_PRE3_MAX                   1
+#define TXEQ_POST_MIN                   -31
+#define TXEQ_POST_MAX                   31
+#define TXEQ_ATTEN_MIN                  0
+#define TXEQ_ATTEN_MAX                  31
+#define RXEQ_DFE_GS1_MIN                0
+#define RXEQ_DFE_GS1_MAX                3
+#define RXEQ_DFE_GS2_MIN                0
+#define RXEQ_DFE_GS2_MAX                3
+
+#define DFE_LOS_MASK                    0x0200
+#define DFE_CAL_RUN_IN_PRGRS_MASK       0x0037
+#define DFE_CAL_DONE                    0x0080
+
+#define SERDES_MEM_ADDR_O_CORE_STATUS   0x26
+
+#define SPICO_INT_DATA_CTLE_MIN \
+	((SPICO_INT_DATA_STRUCT_CLTE << SPICO_INT_DATA_STRUCT_OFFSET) | \
+	 (SPICO_INT_DATA_HF_MIN << SPICO_INT_DATA_MEMBER_OFFSET))
+#define SPICO_INT_DATA_CTLE_HF_MIN_VAL  0x3
+#define SPICO_INT_DATA_CTLE_MAX \
+	((SPICO_INT_DATA_STRUCT_CLTE << SPICO_INT_DATA_STRUCT_OFFSET) | \
+	 (SPICO_INT_DATA_HF_MAX << SPICO_INT_DATA_MEMBER_OFFSET))
+#define SPICO_INT_DATA_CTLE_HF_MAX_VAL  0x7
+
+#define SPICO_INT_DATA_RXP_APPLY_OFFSET 15
+#define SPICO_INT_DATA_RX_PHASE_OFFSET  8
+#define SPICO_INT_DATA_RX_PHASE_MAX     0x3f
+
+#define SPICO_RESULT_SERDES_CRC_PASS    0
+#define SPICO_RESULT_SERDES_CRC_FAIL    0xff
+
+#define SPICO_RESULT_SBR_CRC_PASS       1
+#define SPICO_RESULT_SBR_CRC_FAIL       0xffff
+
+#define SBUS_INT_LOOP_LIMIT             2000
+#define SERDES_EN_LOOP_LIMIT            20
+#define SERDES_EN_LOOP_DELAY            1
+
+#define SERDES_CORE_STATUS_TX_RDY_MASK		0x400000000
+#define SERDES_CORE_STATUS_RX_RDY_MASK		0x200000000
+#define SERDES_CORE_STATUS_RX_IDLE_DETECT_MASK  0x100000000
+#define SERDES_CORE_STATUS_CORE_STS_MASK	0x0ffffffff
+#define SERDES_CORE_STATUS_RX_SIG_OK_MASK       0x000000010
+#define SERDES_CORE_STATUS_SPICO_READY_MASK     0x000000020
+
+#define TUNE_DATA_PRBS                  0
+#define TUNE_DATA_CORE                  1
+#define TUNE_DATA                       TUNE_DATA_CORE
+
+#define BDC_SERDES_RATE_UNINITIALIZED   0
+#define BDC_SERDES_RATE_DOWN_MIN        (BDC_SERDES_RATE_UNINITIALIZED + 1)
+#define BDC_SERDES_RATE_DOWN_MAX        1000
+#define BDC_SERDES_RATE_25G_NRZ_MIN     (BDC_SERDES_RATE_DOWN_MAX + 1)
+#define BDC_SERDES_RATE_25G_NRZ_MAX     30000
+#define BDC_SERDES_RATE_50G_PAM4_MIN    (BDC_SERDES_RATE_25G_NRZ_MAX + 1)
+#define BDC_SERDES_RATE_50G_PAM4_MAX    60000
+
+#define ROS_ETH_SERDES_SBUS_BCAST       0xee
+
+#define ROSHMS_PORT_UNAVAILABLE         0
+#define ROSHMS_PORT_AVAILABLE           1
+
+#define NUM_PAM4_EYES                   6
+#define NUM_NRZ_EYES                    1
+
+#define SBL_BER_DWELL               2
+#define SBL_CORE_STATUS_RD_RETRY_DELAY  1
+
+#define SPICO_INT_DATA_PRBS_RETRY_LIMIT 8
+#define SPICO_INT_DATA_PRBS_RETRY_DELAY 1
+
+#define SPICO_PROC_RESET_RETRY_TIMEOUT_MS 2000
+
+#define SERDES_POST_FLASH_READY_CNT     50
+
+#endif /* _SBL_CONSTANTS_H_ */
diff --git a/drivers/net/ethernet/hpe/sbl/sbl_internal.h b/drivers/net/ethernet/hpe/sbl/sbl_internal.h
new file mode 100644
index 000000000000..690c327e2961
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sbl/sbl_internal.h
@@ -0,0 +1,279 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/* Copyright 2019-2023,2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SBL_INTERNAL_H_
+#define _SBL_INTERNAL_H_
+
+#include <linux/version.h>
+#include <linux/completion.h>
+
+#include <uapi/ethernet/sbl_serdes.h>
+
+#ifdef TRACE2
+#define DEV_TRACE2(dev, format, args...) dev_dbg(dev, format, ## args)
+#else
+#define DEV_TRACE2(dev, format, args...) dev_ignore(dev, format, ## args)
+#endif /* TRACE2 */
+
+#ifdef TRACE3
+#define DEV_TRACE3(dev, format, args...) dev_dbg(dev, format, ## args)
+#else
+#define DEV_TRACE3(dev, format, args...) dev_ignore(dev, format, ## args)
+#endif /* TRACE3 */
+
+#ifndef fallthrough
+#define fallthrough __attribute__((__fallthrough__))
+#endif
+
+#define SBL_AN_MAX_TX_PAGES             3
+
+/* Max number of times we can tune using saved params and find params out-of-bounds
+ * before we give up and do a full tune without saved params
+ */
+#define SBL_MAX_TUNE_PARAM_OOB_FAILS   4
+
+/* The amount of time SBL waits before reloading firmware
+ * when firmware corruption is detected.
+ */
+#define SBL_SERDES_STATE_DUMP_DELAY 200 /* ms */
+
+/* approximate time for signal to travel 1m (for copper cables) */
+#define SBL_MEDIA_NS_PER_M                              4
+/* approximate time for signal to travel 1m (for optical cables) */
+#define SBL_MEDIA_OPTICAL_NS_PER_M                      5
+/* approximate time for signal to pass through an optical transceiver */
+#define SBL_MEDIA_OPTICAL_TRANCEIVER_DELAY             35  /* ns */
+/* approximate time for packet to pass from PCS to Serdes */
+#define SBL_ASIC_TX_DELAY                              25  /* ns */
+#define SBL_ASIC_RX_DELAY                              91  /* ns */
+
+#define SBL_PML_REC_POLL_INTERVAL                       4  /* ms */
+#define SBL_PML_REC_LLR_TIMEOUT_OFFSET                  8  /* ms */
+
+#ifndef timer_container_of
+#define timer_container_of from_timer
+#endif
+
+struct sbl_pml_recovery {
+	struct sbl_inst *sbl;
+	struct timer_list timer;
+	spinlock_t lock;      /* protects enabled, started and timer arming */
+	bool  enabled;        /* new recovery may start or rearm */
+	bool  started;
+	u32 port_num;
+	u32 timeout;
+	enum sbl_link_down_origin down_origin;
+	u64 init_jiffies;
+	u64 last_poll_jiffies;
+	u64 rl_window_start;
+	int rl_time_remaining;
+};
+
+void sbl_pml_recovery_init(struct sbl_pml_recovery *recovery);
+void sbl_pml_recovery_enable(struct sbl_inst *sbl, int port_num);
+
+/* link database record */
+struct sbl_link {
+	int num;                                  /* link/port number */
+	spinlock_t lock;                          /* Data lock */
+
+	struct sbl_media_attr     mattr;          /* physical media properties */
+	bool mconfigured;                         /* is the media attr configured */
+	struct sbl_base_link_attr blattr;         /* link related configuration */
+	bool blconfigured;                        /* is the base-link attr configured */
+
+	u32 sstate;                               /* serdes state */
+	u32 serr;                                 /* serdes error number */
+	u32 blstate;                              /* base link state */
+	u32 blerr;                                /* base link error number */
+	u32 link_info;                            /* misc informative bits describing links internal state */
+
+	struct mutex busy_mtx;                    /* held when starting/stopping */
+
+	spinlock_t timeout_lock;                  /* protect timing values */
+	unsigned long last_start_jiffy;           /* last jiffy before link start time out */
+
+	u32 start_timeout;                        /* active start timeout */
+	ktime_t start_time_begin;                 /* start timestamp (for sysfs) */
+	struct timespec64 start_time;             /* time for start to complete (link up time) (for sysfs) */
+	ktime_t up_time_begin;                    /* timestamp when an/lpd completed (for sysfs) */
+	struct timespec64 up_time;                /* time for link to come up after an/lpd (for sysfs) */
+	ktime_t tune_time_begin;                  /* timestamp when serdes started tuning (for sysfs) */
+	struct timespec64 tune_time;              /* time for serdes tuning attempt to complete (for sysfs) */
+	struct timespec64 total_tune_time;        /* total time for serdes tuning to complete (for sysfs) */
+
+	u32 active_rx_lanes;                      /* pcs rx lanes in use for the current mode */
+	u32 active_fec_lanes;                     /* fec lanes in use for the current mode */
+	bool pcs_config;                          /* is the pcs hw configured */
+
+	u64 an_tx_page[SBL_AN_MAX_TX_PAGES];      /* pages to send during autoneg */
+	int an_tx_count;                          /* count of autoneg pages to send */
+	u64 an_rx_page[SBL_AN_MAX_RX_PAGES];      /* pages received during autoneg */
+	int an_rx_count;                          /* count of autoneg pages received */
+	u32 an_try_count;                         /* number of autoneg attempts */
+	u32 an_nonce;                             /* The nonce used for autoneg */
+	struct completion an_hw_change;           /* signal an hw err flag has been set */
+	bool an_timeout_active;                   /* are we using the autoneg timeout */
+	bool an_100cr4_fixup_applied;             /* have applied this fixup */
+	u32 an_options;                           /* actual an options received */
+	int lp_subtype;                           /* link partner subtype */
+
+	bool reload_serdes_fw;                    /* do we need to reload the serdes fw */
+	bool lp_detected;                         /* has link partner been detected */
+	int lpd_try_count;                        /* count of lp detect attempts */
+
+	int dfe_tune_count;                       /* track the number of dfe tuning attempts */
+	bool optical_delay_active;                /* waiting in dfe-pre-delay before serdes tuning */
+	bool dfe_predelay_active;                 /* waiting in dfe-pre-delay before serdes tuning */
+	bool pcal_running;                        /* periodic calibration running */
+	u32 tune_param_oob_count;                 /* number of consecutive tunes with bad tuning params */
+	unsigned long pcal_start_jiffies;         /* time pcal started */
+	u32 ical_effort;                          /* serdes tuning effort level */
+	struct sbl_tuning_params tuning_params;   /* saved serdes tuning parameters */
+	struct mutex tuning_params_mtx;           /* lock tuning params */
+	bool start_cancelled;                     /* starting procedure was cancelled */
+
+	u32 link_mode;                            /* actual link mode to use after AN */
+	u32 ifg_config;                           /* actual ifg config */
+	u32 loopback_mode;                        /* actual loopback mode to use */
+	bool precoding_enabled;                   /* Is precoding on */
+	u32 llr_mode;                             /* actual llr mode used */
+	u32 llr_options;                          /* actual llr options used */
+	u64 llr_loop_time;                        /* the measured llr round trip time (ns) */
+
+	u64 intr_err_flgs;                        /* error flags registered with handler */
+	struct mutex serdes_mtx;                  /* lock for serdes operations */
+	atomic_t debug_config;                    /* debug flags */
+
+	bool       pcs_recovery_flag;             /* PCS recovery flag */
+	spinlock_t pcs_recovery_lock;             /* PCS recovery lock */
+
+	struct sbl_pml_recovery pml_recovery;     /* PML recovery fields */
+
+	bool is_degraded;                         /* link is degraded flag */
+	spinlock_t is_degraded_lock;              /* link is degraded lock */
+
+	atomic_t *counters;                       /* SBL link counters */
+
+	struct fec_data *fec_data;
+	bool fec_monitor_enabled;                 /* protected by lock */
+	unsigned long fec_discard_time;               /* fec mon discard trigger time */
+	enum sbl_fec_discard_type fec_discard_type;   /* fec mon discard trigger type */
+	spinlock_t fec_discard_lock;                  /* fec mon discard trigger lock */
+};
+
+/* debug support */
+bool sbl_debug_option(struct sbl_inst *sbl, int port_num, u32 flags);
+void dev_ignore(struct device *dev, const char *format, ...) __printf(2, 3);
+
+void sbl_fec_monitor_start(struct sbl_inst *sbl, int port_num);
+void sbl_fec_monitor_stop(struct sbl_inst *sbl, int port_num);
+
+/* access the single char dev */
+struct device *sbl_get_device(void);
+
+/* serdes */
+u32 sbl_serdes_get_config_tag(void);
+
+/* timing and timeouts */
+void sbl_link_init_start_timeout(struct sbl_inst *sbl, int port_num);
+void sbl_link_update_start_timeout(struct sbl_inst *sbl, int port_num,
+				   unsigned int timeout_ms);
+bool sbl_start_timeout(struct sbl_inst *sbl, int port_num);
+void sbl_start_timeout_ensure_remaining(struct sbl_inst *sbl, int port_num,
+					unsigned int remaining_s);
+u32  sbl_get_start_timeout(struct sbl_inst *sbl, int port_num);
+int  sbl_link_start_elapsed(struct sbl_inst *sbl, int port_num);
+void sbl_link_start_record_timespec(struct sbl_inst *sbl, int port_num);
+void sbl_link_up_begin(struct sbl_inst *sbl, int port_num);
+void sbl_link_up_record_timespec(struct sbl_inst *sbl, int port_num);
+void sbl_link_tune_begin(struct sbl_inst *sbl, int port_num);
+int  sbl_link_tune_elapsed(struct sbl_inst *sbl, int port_num);
+void sbl_link_tune_zero_total_timespec(struct sbl_inst *sbl, int port_num);
+void sbl_link_tune_update_total_timespec(struct sbl_inst *sbl, int port_num);
+int sbl_switch_info_get(struct sbl_inst *sbl, struct sbl_init_attr *init_attr);
+
+/* misc */
+int sbl_validate_port_num(struct sbl_inst *sbl, int port_num);
+const char *sbl_an_state_str(int state);
+const char *sbl_an_get_sm_state(struct sbl_inst *sbl, int port_num);
+
+/* These functions are provides by the calling framework
+ *
+ * register access
+ */
+static inline u32  sbl_read32(struct sbl_inst *sbl, long offset)
+{
+	return (*sbl->ops.sbl_read32)(sbl->pci_accessor, offset);
+}
+
+static inline u64  sbl_read64(struct sbl_inst *sbl, long offset)
+{
+	return (*sbl->ops.sbl_read64)(sbl->pci_accessor, offset);
+}
+
+static inline void sbl_write32(struct sbl_inst *sbl, long offset, u32 val)
+{
+	(*sbl->ops.sbl_write32)(sbl->pci_accessor, offset, val);
+}
+
+static inline void sbl_write64(struct sbl_inst *sbl, long offset, u64 val)
+{
+	(*sbl->ops.sbl_write64)(sbl->pci_accessor, offset, val);
+}
+
+/* sbus access */
+static inline int sbl_sbus_op(struct sbl_inst *sbl, int ring, u32 req_data,
+			      u8 data_addr, u8 rx_addr, u8 command,
+		u32 *rsp_data, u8 *result_code, u8 *overrun,
+		int timeout, unsigned int flags)
+{
+	return (*sbl->ops.sbl_sbus_op)(sbl->accessor, ring, req_data,
+				       data_addr, rx_addr, command,
+			rsp_data, result_code, overrun,
+			timeout, flags);
+}
+
+static inline int sbl_sbus_op_reset(struct sbl_inst *sbl, int ring)
+{
+	return (*sbl->ops.sbl_sbus_op_reset)(sbl->accessor, ring);
+}
+
+/* misc other functions */
+static inline bool sbl_is_fabric_link(struct sbl_inst *sbl, int port_num)
+{
+	return (*sbl->ops.sbl_is_fabric_link)(sbl->accessor, port_num);
+}
+
+static inline int sbl_get_max_frame_size(struct sbl_inst *sbl, int port_num)
+{
+	return (*sbl->ops.sbl_get_max_frame_size)(sbl->accessor, port_num);
+}
+
+static inline void sbl_async_alert(struct sbl_inst *sbl, int port_num, int alert_type,
+				   void *alert_data, int size)
+{
+	(*sbl->ops.sbl_async_alert)(sbl->accessor, port_num, alert_type, alert_data, size);
+}
+
+void sbl_llr_max_data_get(struct sbl_inst *sbl, int port_num,
+			  u64 *cap_data_max, u64 *cap_seq_max);
+int sbl_frame_size(struct sbl_inst *sbl, int port_num);
+u64 sbl_llr_edge_cap_data_max_get(void);
+u64 sbl_llr_edge_cap_seq_max_get(void);
+void sbl_an_send_next_page(struct sbl_inst *sbl, int port_num) __maybe_unused;
+void sbl_an_setup_next_page(struct sbl_inst *sbl, int port_num, int page_idx) __maybe_unused;
+void sbl_an_setup_null_page(struct sbl_inst *sbl, int port_num)  __maybe_unused;
+int sbl_an_page_exchange(struct sbl_inst *sbl, int port_num, unsigned long remaining_jiffies);
+bool sbl_an_is_next_page(struct sbl_inst *sbl, int port_num) __maybe_unused;
+void sbl_an_dump_state(struct sbl_inst *sbl, int port_num) __maybe_unused;
+void sbl_an_version_read(struct sbl_inst *sbl, int port_num);
+int  sbl_an_hw_wait_prepare(struct sbl_inst *sbl, int port_num)  __maybe_unused;
+bool sbl_an_next_is_complete(struct sbl_inst *sbl, int port_num) __maybe_unused;
+/* SBL counter functions */
+int sbl_link_counters_init(struct sbl_link *link);
+void sbl_link_counters_term(struct sbl_link *link);
+int sbl_link_counters_incr(struct sbl_inst *sbl, int port_num, u16 counter);
+
+#endif /* _SBL_INTERNAL_H_ */
diff --git a/drivers/net/ethernet/hpe/sbl/sbl_link.h b/drivers/net/ethernet/hpe/sbl/sbl_link.h
new file mode 100644
index 000000000000..f8d51b1215f5
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sbl/sbl_link.h
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/* Copyright 2019-2022,2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SBL_LINK_H_
+#define _SBL_LINK_H_
+
+/* link mode auto negotiation */
+int sbl_link_autoneg(struct sbl_inst *sbl, int port_num);
+
+/* state info flags for trace/debug */
+enum sbl_link_info_flags {
+	SBL_LINK_INFO_LP_DET       = (1 << 0),  /* trying to detect lp */
+	SBL_LINK_INFO_PCS_ANEG     = (1 << 1),  /* pcs configured for autoneg */
+	SBL_LINK_INFO_PCS_TX_AM    = (1 << 2),  /* pcs is sending AM */
+	SBL_LINK_INFO_PCS_ALIGN_EN = (1 << 3),  /* pcs alignment enabled */
+	SBL_LINK_INFO_PCS_A_WAIT   = (1 << 4),  /* pcs waiting for alignment */
+	SBL_LINK_INFO_PCS_TX_RF    = (1 << 5),  /* pcs is sending remote fault */
+	SBL_LINK_INFO_PCS_F_WAIT   = (1 << 6),  /* pcs waiting for faults to clear */
+	SBL_LINK_INFO_PCS_UP       = (1 << 7),  /* pcs is up and aligned */
+	SBL_LINK_INFO_MAC_OP       = (1 << 8),  /* MAC is operational */
+	SBL_LINK_INFO_OS           = (1 << 9),  /* sending ordered sets */
+	SBL_LINK_INFO_LLR_LOOP     = (1 << 10), /* llr can measure loop time */
+	SBL_LINK_INFO_LLR_DETECT   = (1 << 11), /* llr detect */
+	SBL_LINK_INFO_LLR_MEASURE  = (1 << 12), /* llr measuring loop time */
+	SBL_LINK_INFO_LLR_WAIT     = (1 << 13), /* waiting for llr to be ready */
+	SBL_LINK_INFO_LLR_RUN      = (1 << 14), /* llr is operational */
+	SBL_LINK_INFO_LLR_DISABLED = (1 << 15), /* llr is setup but disabled */
+	SBL_LINK_INFO_FAULT_MON    = (1 << 16), /* link fault detection is operational */
+};
+
+void sbl_link_info_set(struct sbl_inst *sbl, int port_num, u32 flag);
+void sbl_link_info_clear(struct sbl_inst *sbl, int port_num, u32 flag);
+
+/* sysfs */
+#ifdef CONFIG_SYSFS
+int sbl_pml_pcs_sysfs_sprint(struct sbl_inst *sbl, int port_num, char *buf, size_t size);
+int sbl_pml_pcs_lane_degrade_sysfs_sprint(struct sbl_inst *sbl, int port_num, char *buf, size_t size);
+#endif
+
+/* debug */
+void sbl_link_lock_dbg(struct sbl_inst *sbl, int port_num, char *text);
+
+#endif /* _SBL_LINK_H_ */
diff --git a/drivers/net/ethernet/hpe/sbl/sbl_platform.h b/drivers/net/ethernet/hpe/sbl/sbl_platform.h
new file mode 100644
index 000000000000..d47630f9e84a
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sbl/sbl_platform.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SBL_PLATFORM_H_
+#define _SBL_PLATFORM_H_
+
+#define SBUS_RING_MTX(sbl, ring) ((sbl)->sbus_ring_mtx)
+#define SBM_FW_MTX(sbl, ring) ((sbl)->sbm_fw_mtx)
+
+#define sbl_dev_log(_logfn, _dev, _fmt, ...)						\
+	do {									\
+		char __sbl_inst[sizeof(sbl->iattr.inst_name)];			\
+		char __sbl_eth[sizeof(sbl->iattr.eth_if_name)];		\
+		sbl_inst_names_get(sbl, __sbl_inst, __sbl_eth);			\
+		_logfn((_dev), "%s[%s]: " _fmt, __sbl_inst, __sbl_eth, ##__VA_ARGS__);	\
+	} while (0)
+
+#define sbl_dev_err(_dev, _fmt, ...) sbl_dev_log(dev_err, _dev, _fmt, ##__VA_ARGS__)
+#define sbl_dev_dbg(_dev, _fmt, ...) sbl_dev_log(dev_dbg, _dev, _fmt, ##__VA_ARGS__)
+#define sbl_dev_warn(_dev, _fmt, ...) sbl_dev_log(dev_warn, _dev, _fmt, ##__VA_ARGS__)
+#define sbl_dev_info(_dev, _fmt, ...) sbl_dev_log(dev_info, _dev, _fmt, ##__VA_ARGS__)
+#define sbl_dev_err_ratelimited(_dev, _fmt, ...) \
+	sbl_dev_log(dev_err_ratelimited, _dev, _fmt, ##__VA_ARGS__)
+#define sbl_dev_dbg_ratelimited(_dev, _fmt, ...) \
+	sbl_dev_log(dev_dbg_ratelimited, _dev, _fmt, ##__VA_ARGS__)
+/* Configuration passing into SBL init */
+struct sbl_init_attr {
+	u32 magic;
+	u32 uc_nic;
+	u32 uc_platform;
+	bool is_hw;
+};
+
+#endif /* _SBL_PLATFORM_H_ */
diff --git a/drivers/net/ethernet/hpe/sbl/sbl_pml_fn.h b/drivers/net/ethernet/hpe/sbl/sbl_pml_fn.h
new file mode 100644
index 000000000000..cfe12f0da980
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sbl/sbl_pml_fn.h
@@ -0,0 +1,132 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/* Copyright 2019-2023 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SBL_PML_FN_H_
+#define _SBL_PML_FN_H_
+
+/* min time to bring up pml block */
+#define SBL_PML_MIN_START_TIME                2 /* s */
+
+/* pcs alignment */
+#define SBL_PML_PCS_ALIGN_TIMEOUT          1000 /* ms */
+#define SBL_PML_PCS_ALIGN_SLOW_POLL_DELAY  1000 /* ms */
+
+/* number of times we see no fault to decide pcs is up */
+#define SBL_PML_REQUIRED_NO_FAULT_COUNT       2
+
+/* number of llr timing measurements required */
+#define SBL_PML_LLR_TIMING_LOOPS              10
+
+/* delay for llr measurement to complete (us) */
+#define SBL_PML_LLR_TIMING_MEASURE_DELAY      50
+
+/* llr capacity calc nums */
+#define SBL_PML_LLR_MIN_LOOP_TIME       60ULL /* ns per spec                 */
+#define SBL_PML_LLR_MAX_LOOP_TIME     3000ULL /* ns max 100m cable           */
+#define SBL_PML_LLR_NUM_FRAMES           2ULL /* frame multiplier            */
+
+/* delay after unsuccessful measurement attempt (ms) */
+#define SBL_PML_LLR_TIMING_PERIOD        2000ULL /* ns for 200m */
+#define SBL_PML_LLR_TIMING_RETRY_DELAY       200
+
+/* LLR detect timing */
+#define SBL_PML_LLR_DETECT_DELAY    100 /* ms */
+#define SBL_PML_LLR_DETECT_TIMEOUT 1000 /* ms */
+
+/* LLR options */
+#define SBL_PML_LLR_OPTION_HPC_WIH_LLR (1 << 0)
+
+/* Max number of Physical Lanes available on Tx/Rx */
+#define MAX_PLS_AVAILABLE 0xF
+
+/* Timeout for Health Markers. We'll surely receive health markers in 100 us, if any */
+#define HM_TIMEOUT 100
+
+/* the PML error flags that can be generated by the various blocks */
+#define SBL_PML_ALL_PCS_ERR_FLGS              0x0001fff800000000ULL
+#define SBL_PML_ALL_MAC_ERR_FLGS              0x0006000000000000ULL
+#define SBL_PML_ALL_LLR_ERR_FLGS              0x1ff8000000000000ULL
+
+/* PML error flags monitored during autoneg */
+#define SBL_AUTONEG_ERR_FLGS	 (SBL_PML_ERR_FLG_AUTONEG_COMPLETE_SET(1ULL) | \
+				  SBL_PML_ERR_FLG_AUTONEG_PAGE_RECEIVED_SET(1ULL))
+
+/* PML error flags monitored for link faults */
+#define SBL_PML_FAULT_ERR_FLAGS		(SBL_PML_ERR_FLG_PCS_LINK_DOWN_SET(1ULL) | \
+					 SBL_PML_ERR_FLG_PCS_HI_SER_SET(1ULL) | \
+					 SBL_PML_ERR_FLG_LLR_REPLAY_AT_MAX_SET(1ULL) | \
+					 SBL_PML_ERR_FLG_PCS_TX_DEGRADE_SET(1ULL) | \
+					 SBL_PML_ERR_FLG_PCS_RX_DEGRADE_SET(1ULL) | \
+					 SBL_PML_ERR_FLG_PCS_TX_DEGRADE_FAILURE_SET(1ULL) | \
+					 SBL_PML_ERR_FLG_PCS_RX_DEGRADE_FAILURE_SET(1ULL))
+
+#define SBL_PML_REC_FAULT_ERR_FLAGS	(SBL_PML_ERR_FLG_PCS_LINK_DOWN_SET(1ULL) | \
+					 SBL_PML_ERR_FLG_PCS_HI_SER_SET(1ULL) | \
+					 SBL_PML_ERR_FLG_PCS_TX_DEGRADE_SET(1ULL) | \
+					 SBL_PML_ERR_FLG_PCS_RX_DEGRADE_SET(1ULL) | \
+					 SBL_PML_ERR_FLG_PCS_TX_DEGRADE_FAILURE_SET(1ULL) | \
+					 SBL_PML_ERR_FLG_PCS_RX_DEGRADE_FAILURE_SET(1ULL))
+
+/* general PML */
+int  sbl_pml_start(struct sbl_inst *sbl, int port_num);
+int  sbl_pml_link_down(struct sbl_inst *sbl, int port_num);
+void sbl_pml_set_defaults(struct sbl_inst *sbl, int port_num);
+bool sbl_pml_err_flgs_test(struct sbl_inst *sbl, int port_num, u64 err_flgs);
+void sbl_pml_err_flgs_clear(struct sbl_inst *sbl, int port_num, u64 err_flgs);
+void sbl_pml_err_flgs_clear_all(struct sbl_inst *sbl, int port_num);
+void sbl_pml_link_down_async_alert(struct sbl_inst *sbl, int port_num,
+				   enum sbl_link_down_origin down_origin);
+
+/* interrupts */
+int sbl_pml_install_intr_handler(struct sbl_inst *sbl, int port_num, u64 err_flags);
+int sbl_pml_enable_intr_handler(struct sbl_inst *sbl, int port_num, u64 err_flags);
+int sbl_pml_disable_intr_handler(struct sbl_inst *sbl, int port_num, u64 err_flags);
+int sbl_pml_remove_intr_handler(struct sbl_inst *sbl, int port_num);
+
+/* PCS */
+int   sbl_pml_pcs_am_start(struct sbl_inst *sbl, int port_num);
+bool  sbl_pml_pcs_high_serdes_error(struct sbl_inst *sbl, int port_num);
+bool  sbl_pml_pcs_up(struct sbl_inst *sbl, int port_num);
+void  sbl_pml_pcs_enable_alignment(struct sbl_inst *sbl, int port_num);
+void  sbl_pml_pcs_disable_alignment(struct sbl_inst *sbl, int port_num);
+int   sbl_pml_pcs_wait(struct sbl_inst *sbl, int port_num);
+void  sbl_pml_pcs_start(struct sbl_inst *sbl, int port_num);
+void  sbl_pml_pcs_stop(struct sbl_inst *sbl, int port_num);
+void  sbl_pml_pcs_ordered_sets(struct sbl_inst *sbl, int port_num, int enable);
+void  sbl_pml_pcs_set_tx_rf(struct sbl_inst *sbl, int port_num);
+void  sbl_pml_pcs_clear_tx_rf(struct sbl_inst *sbl, int port_num);
+char *sbl_pml_pcs_state_str(struct sbl_inst *sbl, int port_num, char *buf, int len);
+void  sbl_pml_pcs_enable_auto_lane_degrade(struct sbl_inst *sbl, int port_num);
+bool  sbl_pml_rx_pls_available(struct sbl_inst *sbl, int port_num);
+bool  sbl_pml_lp_pls_available(struct sbl_inst *sbl, int port_num);
+bool  sbl_pml_recovery_no_faults(struct sbl_inst *sbl, int port_num);
+void  sbl_pml_recovery_log_pcs_status(struct sbl_inst *sbl, int port_num);
+
+/* MAC */
+int  sbl_pml_mac_config(struct sbl_inst *sbl, int port_num);
+void sbl_pml_mac_hw_status(struct sbl_inst *sbl, int port_num, bool *tx_op,
+			   bool *rx_op, u32 *ifg_mode, u32 *ifg_adjustment);
+void sbl_pml_mac_hpc_set(struct sbl_inst *sbl, int port_num);
+
+/* LLR */
+void sbl_pml_llr_config(struct sbl_inst *sbl, int port_num);
+int  sbl_pml_llr_start(struct sbl_inst *sbl, int port_num);
+u64  sbl_pml_llr_link_down_behaviour(struct sbl_inst *sbl, int port_num);
+
+/* TODO: update the values below to reflect changes in the draft
+ * standard
+ */
+#define SBL_PCS_200_CM                        0xD6D9B56505264A9A
+#define SBL_PCS_200_UM0                         0x733F4C298CC0B3
+#define SBL_PCS_200_UM1                         0x8121A5987EDE5A
+#define SBL_PCS_200_UM2                         0xA90CC10156F33E
+#define SBL_PCS_200_UM3                         0x2F7F797BD08086
+#define SBL_PCS_200_UM4                         0x0DAED5E6F2512A
+#define SBL_PCS_200_UM5                         0x2EB0EDB1D14F12
+#define SBL_PCS_200_UM6                         0x5E63BD11A19C42
+#define SBL_PCS_200_UM7                         0xA48929CD5B76D6
+#define SBL_PCS_200_CM_MATCH_MSK                          0x3F3F
+#define SBL_PCS_200_UM_MATCH_MSK                          0x3F3F
+
+#endif  /* _SBL_PML_FN_H_ */
diff --git a/drivers/net/ethernet/hpe/sbl/sbl_sbm.h b/drivers/net/ethernet/hpe/sbl/sbl_sbm.h
new file mode 100644
index 000000000000..73b97081a5d7
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sbl/sbl_sbm.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2019-2026 Hewlett Packard Enterprise Development LP. All rights reserved. */
+
+#ifndef SBL_SBM_H
+#define SBL_SBM_H
+
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+
+#include <linux/hpe/sbl/sbl.h>
+
+#include "sbl_internal.h"
+
+#define SBL_ERR(dev, format, args...)    sbl_dev_err(dev, format, ## args)
+#define SBL_WARN(dev, format, args...)   sbl_dev_warn(dev, format, ## args)
+#define SBL_INFO(dev, format, args...)   sbl_dev_info(dev, format, ## args)
+#define SBL_TRACE1(dev, format, args...) dev_dbg(dev, format, ## args)
+#define SBL_TRACE2(dev, format, args...) DEV_TRACE2(dev, format, ## args)
+#define SBL_TRACE3(dev, format, args...) DEV_TRACE3(dev, format, ## args)
+
+inline int sbl_sbm_sbus_op(struct sbl_inst *sbl, int ring, u32 req_data,
+			     u8 data_addr, u8 rx_addr, u8 command,
+			     u32 *rsp_data, u8 *result_code, u8 *overrun,
+			     int timeout, u32 flags)
+{
+	return sbl_sbus_op(sbl, ring, req_data, data_addr, rx_addr, command,
+			   rsp_data, result_code, overrun, timeout, flags);
+}
+
+inline int sbl_sbm_sbus_op_reset(struct sbl_inst *sbl, int ring)
+{
+	return sbl_sbus_op_reset(sbl, ring);
+}
+
+inline int sbl_sbm_pml_serdes_op(struct sbl_inst *sbl, int port_num,
+				   u64 serdes_sel, u64 op, u64 data,
+				   u16 *result, int timeout, u32 flags)
+{
+	return sbl_pml_serdes_op(sbl, port_num, serdes_sel, op, data, result,
+				 timeout, flags);
+}
+
+inline int sbl_sbm_get_sbus_op_timeout_ms(struct sbl_inst *sbl)
+{
+	return sbl->iattr.sbus_op_timeout_ms;
+}
+
+inline int sbl_sbm_get_sbus_int_timeout(struct sbl_inst *sbl)
+{
+	return sbl->iattr.sbus_int_timeout;
+}
+
+inline int sbl_sbm_get_sbus_int_poll_interval(struct sbl_inst *sbl)
+{
+	return sbl->iattr.sbus_int_poll_interval;
+}
+
+inline int sbl_sbm_get_serdes_op_timeout_ms(struct sbl_inst *sbl)
+{
+	return sbl->iattr.serdes_op_timeout_ms;
+}
+
+inline int sbl_sbm_get_sbus_op_flags(struct sbl_inst *sbl)
+{
+	return sbl->sbus_op_flags;
+}
+
+inline int sbl_sbm_get_serdes_op_flags(struct sbl_inst *sbl)
+{
+	return sbl->iattr.serdes_op_flags;
+}
+#endif /* SBL_SBM_H */
diff --git a/drivers/net/ethernet/hpe/sbl/sbl_sbm_serdes.h b/drivers/net/ethernet/hpe/sbl/sbl_sbm_serdes.h
new file mode 100644
index 000000000000..dc52632b77a7
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sbl/sbl_sbm_serdes.h
@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2025-2026 Hewlett Packard Enterprise Development LP. All rights reserved. */
+
+#ifndef SBL_SBM_SERDES_H
+#define SBL_SBM_SERDES_H
+
+/**
+ * @brief Returns true if the sbus_addr is a CM4 SerDes
+ *
+ * @param sbus_addr address describing a serdes ring and rxaddr
+ *
+ * @return true if match, else false
+ */
+bool is_cm4_serdes_addr(u32 sbus_addr);
+
+/**
+ * @brief Returns true if the sbus_addr is a PCIe SerDes
+ *
+ * @param sbus_addr address describing a serdes ring and rxaddr
+ *
+ * @return true if match, else false
+ */
+bool is_pcie_serdes_addr(u32 sbus_addr);
+
+/**
+ * @brief Returns true if the sbus_addr is a Sbus Master Controller Receiver
+ *         Memory
+ *
+ * @param sbus_addr address describing a serdes ring and rxaddr
+ *
+ * @return true if match, else false
+ */
+bool is_sbm_crm_addr(u32 sbus_addr);
+
+/**
+ * @brief Returns true if the sbus_addr is a Spico processor
+ *
+ * @param sbus_addr address describing a serdes ring and rxaddr
+ *
+ * @return true if match, else false
+ */
+bool is_sbm_spico_addr(u32 sbus_addr);
+
+/**
+ * @brief Issue an interrupt to read SerDes memory
+ *
+ * @param port target port number
+ * @param serdes target serdes lane
+ * @param addr memory address to read
+ * @param data location to store read result
+ *
+ * @return 0 on success, -1 on failure
+ */
+int sbl_serdes_mem_rd(void *sbl, u32 port, u32 serdes, u32 addr,
+		      u16 *data);
+
+/**
+ * @brief Issue an interrupt to write SerDes memory
+ *
+ * @param port target port number
+ * @param serdes target serdes lane
+ * @param addr memory address to write
+ * @param data write data
+ *
+ * @return 0 on success, -1 on failure
+ */
+int sbl_serdes_mem_wr(void *sbl, u32 port, u32 serdes, u32 addr,
+		      u16 data);
+
+/**
+ * @brief Issue an interrupt to read-modify-write SerDes memory
+ *
+ * @param port target port number
+ * @param serdes target serdes lane
+ * @param addr memory address to write
+ * @param data write data
+ * @param mask write mask
+ *
+ * @return 0 on success, -1 on failure
+ */
+int sbl_serdes_mem_rmw(void *sbl, u32 port, u32 serdes, u32 addr,
+		       u16 data, u16 mask);
+
+/**
+ * @brief Convenience function to issue an SBus op and check the result_code
+ *	 and overrun against the original command
+ *
+ * @param sbus_ring target sbus ring
+ * @param reg_addr target sbus register address
+ * @param command 8-bit sbus command field
+ * @param sbus_data target sbus data
+ * @param result location to store result of command (for reads)
+ *
+ * @return 0 on success, -1 on failure
+ */
+int sbl_sbus_wr(void *sbl, u32 sbus_addr, u8 reg_addr,
+		u32 sbus_data);
+int sbl_sbus_rd(void *sbl, u32 sbus_addr, u8 reg_addr,
+		u32 *result);
+int sbl_sbus_op_aux(void *sbl, u32 sbus_addr, u8 reg_addr,
+		    u8 command, u32 sbus_data, u32 *result);
+
+/**
+ * @brief upload rom to target sbus address
+ *
+ * @param sbus_ring target sbus ring
+ * @param reg_addr target sbus register address
+ * @param fw_size byte size of firmware image
+ * @param fw_data byte array of size fw_size
+ *
+ * @return 0 on success, -1 on failure
+ */
+int sbl_spico_burst_upload(void *sbl, u32 sbus, u32 reg,
+			   size_t fw_size, const u8 *fw_data);
+
+/**
+ * @brief Write an interrupt request to a target SBM Spico
+ *
+ * @param sbus_addr address describing a serdes ring and rxaddr
+ * @param code interrupt command
+ * @param data interrupt data
+ * @param result location to store result of interrupt
+ *
+ * @return 0 on success, -1 on failure
+ */
+int sbl_sbm_spico_int(void *sbl, u32 sbus_addr, int code,
+		      int data, u32 *result);
+
+/**
+ * @brief Write an interrupt request to a set of SerDes Spicos
+ *
+ * @param config_entry address list describing SerDes lanes
+ * @param interrupt command
+ * @param data interrupt data
+ * @param result pointer to store result in.
+ * @param result_action ignore the interrupt result, store it to the result
+ *		      pointer, or validate it matches code
+ *
+ * @return 0 if all results are the same, else -1
+ */
+int sbl_serdes_spico_int(void *sbl, u32 port, u32 serdes,
+			 int code, int data, u16 *result, u8 result_action);
+/**
+ * @param sbus_addr address describing a serdes ring and rxaddr
+ */
+int sbl_serdes_spico_int2(void *sbl, u32 sbus_addr, int code,
+			  int data, u16 *result, u8 result_action);
+void sbl_sbus_addr_get(u32 *sbus_addr);
+bool is_pcie_serdes_pcs_addr(u32 sbus_addr);
+void sbus_addr_to_string(u32 sbus_addr, char *data_str);
+
+#endif /* SBL_SBM_SERDES_H */
diff --git a/drivers/net/ethernet/hpe/sbl/sbl_serdes.h b/drivers/net/ethernet/hpe/sbl/sbl_serdes.h
new file mode 100644
index 000000000000..77db5e042e8c
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sbl/sbl_serdes.h
@@ -0,0 +1,94 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2019-2020,2022-2023 Hewlett Packard Enterprise Development LP. All rights reserved. */
+
+#ifndef _SBL_SERDES_H_
+#define _SBL_SERDES_H_
+
+/**
+ * @brief SerDes test function
+ *
+ * @param sbl sbl_inst pointer containing target config and state
+ *
+ * @return 0 on success or negative errno on failure
+ */
+int sbl_serdes_test(struct sbl_inst *sbl);
+
+/**
+ * @brief SerDes initial load function
+ *
+ *  To be called after the Rosetta power cycle or the controller boots
+ *  Applyies the SBus speedup and flashes all SBM/SerDes firmware images
+ *
+ * @param sbl sbl_inst pointer containing target config and state
+ * @param port_num target port number
+ * @param force reset and flash even if current fw is at the correct
+ *        rev and build number
+ *
+ * @return 0 on success or negative errno on failure
+ */
+int sbl_serdes_load(struct sbl_inst *sbl, int port_num, bool force);
+
+/**
+ * @brief SerDes link partner detection
+ *
+ * This blocking function will use the Serdes to determine if the
+ * link partner is present ant trying to come up.
+ *
+ * @param sbl sbl_inst pointer containing target config and state
+ * @param port_num target port number
+ *
+ * @return 0 on success or negative errno on failure
+ */
+int sbl_serdes_lp_detect(struct sbl_inst *sbl, int port_num);
+
+/**
+ * @brief Start the SerDes lanes for a given port
+ *
+ * @param sbl sbl_inst pointer containing target config and state
+ * @param port_num target port number
+ *
+ * @return 0 on success or negative errno on failure
+ */
+int sbl_serdes_start(struct sbl_inst *sbl, int port_num);
+
+/**
+ * @brief Stops the SerDes lanes for a given port
+ *
+ * @param sbl sbl_inst pointer containing target config and state
+ * @param port_num target port number
+ *
+ * @return 0 on success or negative errno on failure
+ */
+int sbl_serdes_stop(struct sbl_inst *sbl, int port_num);
+
+/**
+ * @brief Resets all SerDes lanes for a given port
+ *
+ * @param sbl sbl_inst pointer containing target config and state
+ * @param port_num target port number
+ *
+ * @return 0 on success or negative errno on failure
+ */
+int sbl_serdes_reset(struct sbl_inst *sbl, int port_num);
+
+/**
+ * @brief Sets up the serdes at the correct speed to perform autonegotiation
+ *
+ * @param sbl sbl_inst pointer containing target config and state
+ * @param port_num target port number
+ *
+ * @return 0 on success or negative errno on failure
+ */
+int sbl_an_serdes_start(struct sbl_inst *sbl, int port_num);
+
+/**
+ * @brief Stops the SerDes lanes for a given port
+ *
+ * @param sbl sbl_inst pointer containing target config and state
+ * @param port_num target port number
+ *
+ * @return 0 on success or negative errno on failure
+ */
+int sbl_an_serdes_stop(struct sbl_inst *sbl, int port_num);
+
+#endif /* _SBL_SERDES_H_ */
diff --git a/drivers/net/ethernet/hpe/sbl/sbl_serdes_fn.h b/drivers/net/ethernet/hpe/sbl/sbl_serdes_fn.h
new file mode 100644
index 000000000000..b72a6acb8c93
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sbl/sbl_serdes_fn.h
@@ -0,0 +1,151 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/* Copyright 2019-2026 Hewlett Packard Enterprise Development LP */
+#ifndef SBL_SERDES_FN_H
+#define SBL_SERDES_FN_H
+
+#include <linux/hpe/sbl/sbl.h>
+
+/* Get SBM firmware version from the given SBUS ring. */
+void sbl_sbm_get_fw_vers(struct sbl_inst *sbl, int sbus_ring, uint *fw_rev,
+			 uint *fw_build);
+
+/* Get serdes firmware version for the specified port and serdes lane. */
+void sbl_serdes_get_fw_vers(struct sbl_inst *sbl, int port_num, int serdes,
+			    uint *fw_rev, uint *fw_build);
+
+/* Sbus Master firmware flash - all rings */
+int sbl_sbm_firmware_flash(struct sbl_inst *sbl);
+
+/* Sbus Master firmware flash */
+int sbl_sbm_firmware_flash_ring(struct sbl_inst *sbl, int first_ring,
+				int last_ring, bool force);
+
+/* SerDes firmware flash */
+int sbl_serdes_firmware_flash(struct sbl_inst *sbl, int port_num, bool force);
+
+/* SerDes firmware flash with auto-recovery attempt */
+int sbl_serdes_firmware_flash_safe(struct sbl_inst *sbl, int port_num,
+				   bool force);
+
+/* Check if CRC for target serdes lane is valid */
+int sbl_validate_serdes_fw_crc(struct sbl_inst *sbl, int port_num, int serdes);
+
+/* Check if SerDes desired_rev matches flashed version */
+int sbl_validate_serdes_fw_vers(struct sbl_inst *sbl, int port_num, int serdes,
+				int fw_rev, int fw_build);
+
+/* Check if SerDes desired_rev matches flashed version */
+int sbl_validate_sbm_fw_vers(struct sbl_inst *sbl, u32 sbus_ring,
+			     int fw_rev, int fw_build);
+
+/* Upload target firmware image to single location */
+int sbl_serdes_firm_upload(struct sbl_inst *sbl, int port_num, size_t fw_size,
+			   const u8 *fw_data);
+
+/* Upload target firmware image to multiple locations */
+int sbl_sbm_firm_upload(struct sbl_inst *sbl, int sbus_ring,
+			size_t fw_size, const u8 *fw_data);
+
+/* Ensures most tuning parameters for a given port are within range. */
+int sbl_check_serdes_tuning_params(struct sbl_inst *sbl, int port_num);
+
+/* Gets a given SerDes' tuning params */
+int sbl_save_serdes_tuning_params(struct sbl_inst *sbl, int port_num);
+
+/* Set a given SerDes tuning params */
+int sbl_apply_serdes_tuning_params(struct sbl_inst *sbl, int port, int serdes);
+
+/* Perfrom dfe tune on a particular serdes */
+int sbl_serdes_dfe_tune_start(struct sbl_inst *sbl, int port_num, int serdes,
+			      bool is_retune);
+
+/* Wait for a particular serdes to complete its DFE tune */
+int sbl_serdes_dfe_tune_wait(struct sbl_inst *sbl, int port_num);
+
+/* Perfrom dfe tune on a port */
+int sbl_port_dfe_tune_start(struct sbl_inst *sbl, int port_num, bool is_retune);
+
+/* Wait for a port to complete its DFE tune */
+int sbl_port_dfe_tune_wait(struct sbl_inst *sbl, int port_num);
+
+/* Read and validate eye heights for a port */
+int sbl_port_check_eyes(struct sbl_inst *sbl, int port_num);
+
+/* Return maps of serdes status for a port */
+int sbl_port_get_serdes_state_maps(struct sbl_inst *sbl, int port_num,
+				   u8 *active_map, u8 *not_idle_map, u8 *ok_eye_map);
+
+/* Updates the state in the sbl struct from the tgt values */
+void sbl_update_internal_state(struct sbl_inst *sbl, int port_num);
+
+/* DFE tune a port */
+int sbl_port_dfe_tune(struct sbl_inst *sbl, int port_num, bool is_retune);
+
+/* Get the 6 eye heights */
+int sbl_get_eye_heights(struct sbl_inst *sbl, int port_num, int serdes,
+			int *eye_heights);
+
+/* Issues a soft SBus reset */
+int sbl_serdes_soft_reset(struct sbl_inst *sbl, int port_num, int serdes);
+
+/* Runs SerDes initization */
+int sbl_serdes_init(struct sbl_inst *sbl, int port_num, int serdes,
+		    int encoding, int divisor, int width);
+
+/* Applies tx/rx polarity inversion and other config */
+int sbl_serdes_polarity_ctrl(struct sbl_inst *sbl, int port_num, int serdes,
+			     int encoding, bool an);
+
+/* Enables/Disabled SerDes Tx/Rx */
+int sbl_set_tx_rx_enable(struct sbl_inst *sbl, int port_num, int serdes,
+			 bool tx_en, bool rx_en, bool txo_en);
+
+/* Sets the CTLE parameters */
+int sbl_set_gs(struct sbl_inst *sbl, int port_num, int serdes, int gs1,
+	       int gs2);
+
+/* Sets the TX data select */
+int sbl_set_tx_data_sel(struct sbl_inst *sbl, int port_num, int serdes,
+			int data_sel);
+
+/* Sets the TX data select */
+int sbl_set_tx_eq(struct sbl_inst *sbl, int port_num, int serdes,
+		  int atten, int pre, int post, int pre2, int pre3);
+
+/* Sets the Rx compare mode and data, qualification, and performs an
+ *	error reset
+ */
+int sbl_set_prbs_rx_mode(struct sbl_inst *sbl, int port_num, int serdes);
+
+/* Set SBM clock divider */
+int sbl_apply_sbus_divider(struct sbl_inst *sbl, int value);
+
+/* Begin continuous adaptive tuning on all enabled lanes for this port */
+int sbl_port_start_pcal(struct sbl_inst *sbl, int port_num);
+
+/* Stop continuous adaptive tuning on all enabled lanes for this port */
+int sbl_port_stop_pcal(struct sbl_inst *sbl, int port_num);
+
+/* Setup to perform a SerDes mini-tune */
+int sbl_serdes_minitune_setup(struct sbl_inst *sbl, int port_num);
+
+/* Block until a SerDes mini-tune completes, fails or times out */
+int sbl_serdes_minitune_block(struct sbl_inst *sbl, int port_num);
+
+/* Configure the SerDes lanes for a given port */
+int sbl_serdes_config(struct sbl_inst *sbl, int port_num, bool allow_an);
+
+/* Tune the SerDes lanes for a given port */
+int sbl_serdes_tuning(struct sbl_inst *sbl, int port_num);
+
+/* Reset SPICO micro */
+int sbl_spico_reset(struct sbl_inst *sbl, int port_num);
+
+/* Reset the PLLs on a serdes */
+int sbl_reset_serdes_plls(struct sbl_inst *sbl, int port_num);
+
+/* Log port eye heights */
+void sbl_log_port_eye_heights(struct sbl_inst *sbl, int port_num);
+
+#endif /* SBL_SERDES_FN_H */
diff --git a/drivers/net/ethernet/hpe/sbl/sbl_serdes_map.h b/drivers/net/ethernet/hpe/sbl/sbl_serdes_map.h
new file mode 100644
index 000000000000..f2ea2129a4cb
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sbl/sbl_serdes_map.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2019-2026 Hewlett Packard Enterprise Development LP. All rights reserved. */
+#ifndef SBL_SERDES_MAP_H
+#define SBL_SERDES_MAP_H
+
+#include <linux/hpe/sbl/sbl_kconfig.h>
+#include <uapi/ethernet/sbl_serdes_map.h>
+#include <uapi/ethernet/sbl_serdes_map_init.h>
+
+#endif /* SBL_SERDES_MAP_H */
diff --git a/include/linux/hpe/sbl/sbl.h b/include/linux/hpe/sbl/sbl.h
new file mode 100644
index 000000000000..e4f1063ba88f
--- /dev/null
+++ b/include/linux/hpe/sbl/sbl.h
@@ -0,0 +1,436 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/* Copyright 2019-2026 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SBL_H_
+#define _SBL_H_
+
+#include <linux/types.h>
+#include <linux/mutex.h>
+#include <linux/spinlock.h>
+#include <linux/string.h>
+#include <linux/firmware.h>
+
+#include <uapi/ethernet/sbl-abi.h>
+#include <uapi/ethernet/sbl_serdes.h>
+#include <uapi/ethernet/sbl_counters.h>
+
+#include "sbl_platform.h"
+
+#define SBL_VERSION_MAJOR		      3
+#define SBL_VERSION_MINOR		     22
+#define SBL_VERSION_INC			     24
+
+#define SBL_MAGIC		     0x6273696c  /* sbli */
+#define SBL_INIT_ATTR_MAGIC	     0x62736965  /* sbla */
+
+#define SBL_AN_MAX_RX_PAGES		     20
+#define SBL_DFE_USED_SAVED_PARAMS	     -2
+
+/* min size of buffer for pcs state string */
+#define SBL_PCS_STATE_STR_LEN		     64
+
+/* min size of buffer for base link state string */
+#define SBL_BASE_LINK_STATE_STR_LEN	     (SBL_PCS_STATE_STR_LEN + 16)
+
+struct sbl_tuning_params;
+struct sbl_sc_values;
+struct sbl_serdes_config;
+
+
+/* Reasons for taking the link down asynchronously */
+enum sbl_link_down_origin {
+	SBL_LINK_DOWN_ORIGIN_UNKNOWN = 0,
+	SBL_LINK_DOWN_ORIGIN_LINK_DOWN,
+	SBL_LINK_DOWN_ORIGIN_LOCAL_FAULT,
+	SBL_LINK_DOWN_ORIGIN_REMOTE_FAULT,
+	SBL_LINK_DOWN_ORIGIN_ALIGN,
+	SBL_LINK_DOWN_ORIGIN_HISER,
+	SBL_LINK_DOWN_ORIGIN_LLR_MAX,
+	SBL_LINK_DOWN_ORIGIN_DEGRADE_FAILURE,
+	SBL_LINK_DOWN_ORIGIN_UCW,		/* FEC - high uncorrected fec error rate */
+	SBL_LINK_DOWN_ORIGIN_CCW,		/* FEC - high corrected fec error rate */
+	SBL_LINK_DOWN_ORIGIN_LLR_TX_REPLAY,	/* FEC - high llr_tx_replay fec error rate */
+};
+
+
+/* Internal llr state machine states
+ * (missing from pml header)
+ */
+enum sbl_pml_llr_state_e {
+	SBL_PML_LLR_STATE_UNKNOWN = 0,
+	SBL_PML_LLR_STATE_OFF,
+	SBL_PML_LLR_STATE_INIT,
+	SBL_PML_LLR_STATE_ADVANCE,
+	SBL_PML_LLR_STATE_HALT,
+	SBL_PML_LLR_STATE_REPLAY,
+	SBL_PML_LLR_STATE_DISCARD,
+	SBL_PML_LLR_STATE_MONITOR,
+};
+
+
+/**
+ * @brief Inter-frame gap config
+ */
+enum sbl_ifg_mode {
+	SBL_IFG_MODE_INVALID = 0,
+	SBL_IFG_MODE_UNKNOWN,
+	SBL_IFG_MODE_HPC,	  /**< Fabric link  */
+	SBL_IFG_MODE_IEEE,	  /**< Use IEEE standard */
+};
+
+
+/**
+ * @brief IEEE inter-frame gap adjustment
+ */
+enum sbl_ifg_ieee_adjustment {
+	SBL_IFG_IEEE_ADJUSTMENT_INVALID = 0,
+	SBL_IFG_IEEE_ADJUSTMENT_UNKNOWN,
+	SBL_IFG_IEEE_ADJUSTMENT_200G,	      /**< IEEE 200G adjustment */
+	SBL_IFG_IEEE_ADJUSTMENT_100G,	      /**< IEEE 100G adjustment */
+	SBL_IFG_IEEE_ADJUSTMENT_50G,	      /**< IEEE 50G adjustment */
+	SBL_IFG_IEEE_ADJUSTMENT_NONE,	      /**< No adjustment */
+};
+
+
+/**
+ * @brief Async alert types
+ */
+enum sbl_async_alert_type {
+	SBL_ASYNC_ALERT_INVALID		     = 0, /**< Invalid alert */
+	SBL_ASYNC_ALERT_LINK_DOWN	     = 1, /**< Link down alert */
+	SBL_ASYNC_ALERT_SERDES_FW_CORRUPTION = 2, /**< SerDes firmware corruption alert */
+	SBL_ASYNC_ALERT_TX_DEGRADE	     = 3, /**< TX lane degrade alert */
+	SBL_ASYNC_ALERT_RX_DEGRADE	     = 4, /**< RX lane degrade alert */
+	SBL_ASYNC_ALERT_TX_DEGRADE_FAILURE   = 5, /**< TX lane degrade failure alert */
+	SBL_ASYNC_ALERT_RX_DEGRADE_FAILURE   = 6, /**< RX lane degrade failure alert */
+	SBL_ASYNC_ALERT_SBM_FW_LOAD_FAILURE  = 7, /**< SBus master fw load failure alert */
+};
+
+
+/**
+ * @brief event triggers to discard fec window
+ */
+enum sbl_fec_discard_type {
+	SBL_FEC_DISCARD_TYPE_INVALID = 0,	/**< Invalid discard reason */
+	SBL_FEC_DISCARD_TYPE_RX_DEGRADE,	/**< RX lane degraded */
+	SBL_FEC_DISCARD_TYPE_PML_REC_START,	/**< PML recovery started */
+	SBL_FEC_DISCARD_TYPE_PML_REC_END,	/**< PML recovery ended */
+};
+
+
+/**
+ * @brief Link Partner Type
+ */
+enum sbl_lp_subtype {
+	SBL_LP_SUBTYPE_INVALID	  = -1,    /**< Invalid - uninitialized		*/
+	SBL_LP_SUBTYPE_UNKNOWN	  = 0,	   /**< Link is up, but type is Unknown */
+	SBL_LP_SUBTYPE_CASSINI_V1 = 1,	   /**< Type is Cassini V1		*/
+	SBL_LP_SUBTYPE_CASSINI_V2 = 2	   /**< Type is Cassini V2		*/
+};
+
+
+/* Operations provided by the calling framework */
+struct sbl_ops {
+	/* register access */
+	u32  (*sbl_read32)(void *pci_accessor, long offset);
+	u64  (*sbl_read64)(void *pci_accessor, long offset);
+	void (*sbl_write32)(void *pci_accessor, long offset, u32 val);
+	void (*sbl_write64)(void *pci_accessor, long offset, u64 val);
+
+	/* sbus access */
+	int (*sbl_sbus_op)(void *accessor, int ring, u32 req_data,
+			u8 data_addr, u8 rx_addr, u8 command,
+			u32 *rsp_data, u8 *result_code, u8 *overrun,
+			int timeout, unsigned int flags);
+	int (*sbl_sbus_op_reset)(void *accessor, int ring);
+
+	/* external state */
+	bool (*sbl_is_fabric_link)(void *accessor, int port_num);
+	int  (*sbl_get_max_frame_size)(void *accessor, int port_num);
+
+	/* pml block intr support */
+	int  (*sbl_pml_install_intr_handler)(void *accessor, int port_num, u64 err_flags);
+	int  (*sbl_pml_enable_intr_handler)(void *accessor, int port_num, u64 err_flags);
+	int  (*sbl_pml_disable_intr_handler)(void *accessor, int port_num, u64 err_flags);
+	int  (*sbl_pml_remove_intr_handler)(void *accessor, int port_num, u64 err_flags);
+
+	/* async alert */
+	void (*sbl_async_alert)(void *accessor, int port_num, int alert_type, void *alert_data, int size);
+};
+
+struct lane_degrade {
+	u64 tx;
+	u64 rx;
+};
+
+struct fec_data {
+	struct sbl_fec *fec_prmts;	/* fec parameters */
+	struct timer_list fec_timer;	/* Fec timer */
+	struct sbl_inst *sbl;
+	int port_num;
+	struct work_struct fec_timer_work;
+};
+
+/* A slingshot base link device instance */
+struct sbl_inst {
+	int magic;
+	int id;
+	struct device *dev;			 /* shared linux device */
+
+	void *accessor;				 /* accessor for calling framework */
+	void *pci_accessor;			 /* accessor for pci io */
+	struct sbl_ops ops;			 /* table of external operations provided by caller */
+	struct sbl_instance_attr iattr;		 /* instance attributes */
+	spinlock_t name_lock;			 /* iattr name writers vs log snapshots */
+	struct sbl_switch_info *switch_info;
+
+	u32 sbus_op_flags;			 /* active sbus op flags */
+
+	struct list_head serdes_config_list;	 /* list of serdes configurations */
+	spinlock_t serdes_config_lock;		 /* lock serdes configurations list */
+
+	struct sbl_link *link;			 /* link database */
+
+	struct mutex *sbus_ring_mtx;		 /* locks for sbus critical section management */
+
+	struct mutex *sbm_fw_mtx;		 /* locks for sbus master firmware load */
+
+	bool *reload_sbm_fw;			 /* do we need to reload the sbm fw for each ring */
+
+	atomic_t *sbm_fw_reload_count;		 /* counter to track sbus master fw reload */
+
+	struct workqueue_struct *workq;
+
+	bool is_hw;
+};
+
+static inline void sbl_inst_names_get(struct sbl_inst *sbl, char *inst_name,
+				      char *eth_if_name)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&sbl->name_lock, flags);
+	memcpy(inst_name, sbl->iattr.inst_name, sizeof(sbl->iattr.inst_name));
+	memcpy(eth_if_name, sbl->iattr.eth_if_name, sizeof(sbl->iattr.eth_if_name));
+	spin_unlock_irqrestore(&sbl->name_lock, flags);
+
+	inst_name[sizeof(sbl->iattr.inst_name) - 1] = '\0';
+	eth_if_name[sizeof(sbl->iattr.eth_if_name) - 1] = '\0';
+}
+
+static inline int sbl_validate_instance(struct sbl_inst *sbl)
+{
+	if (!sbl)
+		return -EINVAL;
+	else if (sbl->magic != SBL_MAGIC)
+		return -EINVAL;
+	else
+		return 0;
+}
+
+void sbl_get_version(int *major, int *minor, int *inc);
+
+int sbl_get_num_sbus_rings(struct sbl_inst *sbl);
+
+/* Instance management */
+struct sbl_inst *sbl_new_instance(void *accessor, void *pci_accessor,
+				  const struct sbl_ops *ops,
+				  struct sbl_init_attr *init_attr);
+void   sbl_set_eth_name(struct sbl_inst *sbl, const char *name);
+int    sbl_delete_instance(struct sbl_inst *sbl);
+int    sbl_initialise_instance(struct sbl_inst *sbl, struct sbl_instance_attr *attr);
+int    sbl_restore_instance(struct sbl_inst *sbl);
+
+/* media management */
+int  sbl_media_config(struct sbl_inst *sbl, int port_num,
+		struct sbl_media_attr *attr);
+int  sbl_media_unconfig(struct sbl_inst *sbl, int port_num);
+bool sbl_media_check_mode_supported(struct sbl_inst *sbl, int port_num,
+		u32 mode);
+bool sbl_media_check_headshell_reset_supported(struct sbl_inst *sbl, int port_num);
+int  sbl_media_validate_config(struct sbl_inst *sbl, int port_num);
+int  sbl_media_calc_loop_time(struct sbl_inst *sbl, int port_num, u64 *min_loop_time);
+u64  sbl_media_get_loop_time_ns(struct sbl_inst *sbl, int port_num,
+		bool require_measurement);
+u32 sbl_media_get_len_cm(struct sbl_inst *sbl, int port_num, u64 len);
+
+/* Base link control */
+int  sbl_get_lp_subtype(struct sbl_inst *sbl, int port_num, enum sbl_lp_subtype *lp_subtype);
+int  sbl_base_link_config(struct sbl_inst *sbl, int port_num,
+		struct sbl_base_link_attr *blattr);
+int  sbl_base_link_start(struct sbl_inst *sbl, int port_num);
+int  sbl_base_link_enable_start(struct sbl_inst *sbl, int port_num);
+int  sbl_base_link_cancel_start(struct sbl_inst *sbl, int port_num);
+bool sbl_base_link_start_cancelled(struct sbl_inst *sbl, int port_num);
+int  sbl_base_link_stop(struct sbl_inst *sbl, int port_num);
+int  sbl_base_link_reset(struct sbl_inst *sbl, int port_num);
+int  sbl_base_link_get_status(struct sbl_inst *sbl, int port_num,
+		int *blstate, int *blerr, int *sstate, int *serr,
+		int *media_type, int *link_mode);
+void sbl_base_link_try_start_fail_cleanup(struct sbl_inst *sbl,
+		int port_num);
+char *sbl_base_link_state_str(struct sbl_inst *sbl, int port_num, char *buf, int len);
+int  sbl_base_link_dump_attr(struct sbl_inst *sbl, int port_num,
+		char *buf, size_t size);
+
+/* fec thresholds */
+int  sbl_link_get_fec_thresholds(struct sbl_inst *sbl, int port_num,
+		int *ucw_bad, int *ccw_bad, int *fecl_warn);
+u64  sbl_link_get_ucw_thresh_ieee(struct sbl_inst *sbl, int port_num);
+u64  sbl_link_get_ucw_thresh_hpe(struct sbl_inst *sbl, int port_num);
+u64  sbl_link_get_ccw_thresh_ieee(struct sbl_inst *sbl, int port_num);
+u64  sbl_link_get_ccw_thresh_hpe(struct sbl_inst *sbl, int port_num);
+u64  sbl_link_get_stp_ccw_thresh_ieee(struct sbl_inst *sbl, int port_num);
+u64  sbl_link_get_stp_ccw_thresh_hpe(struct sbl_inst *sbl, int port_num);
+
+/* serdes tuning params */
+int sbl_serdes_get_tuning_params(struct sbl_inst *sbl, int port_num,
+		struct sbl_tuning_params *tuning_params);
+int sbl_serdes_set_tuning_params(struct sbl_inst *sbl, int port_num,
+		struct sbl_tuning_params *tuning_params);
+int sbl_serdes_invalidate_tuning_params(struct sbl_inst *sbl, int port_num);
+int sbl_serdes_invalidate_all_tuning_params(struct sbl_inst *sbl);
+
+/* Timing flags */
+int sbl_flags_get_poll_interval_from_flags(unsigned int flags);
+int sbl_flags_get_delay_from_flags(unsigned int flags);
+
+/* serdes configurations */
+int  sbl_serdes_add_config(struct sbl_inst *sbl, u64 tp_state_mask0,
+		u64 tp_state_mask1, u64 tp_state_match0,
+		u64 tp_state_match1, u64 port_mask, u8 serdes_mask,
+		struct sbl_sc_values *vals, bool is_default);
+int  sbl_serdes_del_config(struct sbl_inst *sbl, u64 tp_state_mask0,
+		u64 tp_state_mask1, u64 tp_state_match0, u64 tp_state_match1,
+		u64 port_mask, u8  serdes_mask);
+int sbl_serdes_clear_all_configs(struct sbl_inst *sbl, bool clr_default);
+void sbl_serdes_dump_configs(struct sbl_inst *sbl);
+struct sbl_switch_info *sbl_get_switch_info(int *size);
+
+/* pml block intr handler */
+int sbl_pml_hdlr(struct sbl_inst *sbl, int port_num, void *data);
+void sbl_pml_recovery_cancel(struct sbl_inst *sbl, int port_num);
+
+/* serdes operations (using core interrupt mechanism) */
+int sbl_pml_serdes_op_timing(struct sbl_inst *sbl, int port_num, u64 capture,
+		u64 clear, u64 set);
+int sbl_pml_serdes_op(struct sbl_inst *sbl, int port_num, u64 serdes_sel,
+		u64 op, u64 data, u16 *result, int timeout, unsigned int flags);
+
+/* MAC */
+void sbl_pml_mac_start(struct sbl_inst *sbl, int port_num);
+void sbl_pml_mac_stop(struct sbl_inst *sbl, int port_num);
+
+/* misc */
+void sbl_pml_llr_stop(struct sbl_inst *sbl, int port_num);
+void sbl_pml_llr_disable(struct sbl_inst *sbl, int port_num);
+void sbl_pml_llr_enable(struct sbl_inst *sbl, int port_num);
+bool sbl_pml_llr_check_is_ready(struct sbl_inst *sbl, int port_num, unsigned int timeout_ms);
+u32  sbl_pml_llr_get_state(struct sbl_inst *sbl, int port_num);
+int  sbl_get_an_pages(struct sbl_inst *sbl, int port_num, int *count, u64 *pages);
+bool sbl_pml_pcs_aligned(struct sbl_inst *sbl, int port_num);
+void sbl_pml_pcs_recovery_enable(struct sbl_inst *sbl, int port_num);
+void sbl_pml_pcs_recovery_disable(struct sbl_inst *sbl, int port_num);
+void sbl_ignore_save_tuning_param(struct sbl_inst *sbl, int port_num, bool ignore);
+void sbl_enable_opt_lane_degrade(struct sbl_inst *sbl, int port_num, bool enable);
+void sbl_disable_pml_recovery(struct sbl_inst *sbl, int port_num, bool disable);
+void sbl_pml_recovery_log_link_down(struct sbl_inst *sbl, int port_num);
+void sbl_set_degraded_flag(struct sbl_inst *sbl, int port_num);
+void sbl_clear_degraded_flag(struct sbl_inst *sbl, int port_num);
+bool sbl_get_degraded_flag(struct sbl_inst *sbl, int port_num);
+
+/* sysfs support */
+#ifdef CONFIG_SYSFS
+int sbl_media_sysfs_sprint(struct sbl_inst *sbl, int port_num, char *buf, size_t size);
+int sbl_media_type_sysfs_sprint(struct sbl_inst *sbl, int port_num, char *buf, size_t size);
+int sbl_serdes_sysfs_sprint(struct sbl_inst *sbl, int port_num, char *buf, size_t size);
+int sbl_serdes_fw_sysfs_sprint(struct sbl_inst *sbl, int port_num, char *buf, size_t size);
+int sbl_pml_pcs_sysfs_sprint(struct sbl_inst *sbl, int port_num, char *buf, size_t size);
+int sbl_pml_pcs_lane_degrade_sysfs_sprint(struct sbl_inst *sbl, int port_num, char *buf, size_t size);
+int sbl_pml_pcs_speed_sysfs_sprint(struct sbl_inst *sbl, int port_num, char *buf, size_t size);
+int sbl_base_link_sysfs_sprint(struct sbl_inst *sbl, int port_num, char *buf, size_t size);
+int sbl_base_link_llr_sysfs_sprint(struct sbl_inst *sbl, int port_num, char *buf, size_t size);
+int sbl_base_link_loopback_sysfs_sprint(struct sbl_inst *sbl, int port_num, char *buf, size_t size);
+int sbl_debug_sysfs_sprint(struct sbl_inst *sbl, int port_num, char *buf, size_t size);
+int sbl_sbm_fw_sysfs_sprint(struct sbl_inst *sbl, int ring, char *buf, size_t size);
+int sbl_fec_sysfs_sprint(struct sbl_inst *sbl, int port_num, char *buf, size_t size);
+#endif
+
+/* debug support */
+void sbl_debug_clear_config(struct sbl_inst *sbl, int port_num);
+void sbl_debug_update_config(struct sbl_inst *sbl, int port_num,
+		u32 clear_flags, u32 set_flags);
+int sbl_debug_get_config(struct sbl_inst *sbl, int port_num, u32 *options);
+
+/* pretty printing */
+const char *sbl_link_state_str(enum sbl_base_link_status state);
+const char *sbl_link_len_str(enum sbl_link_len len);
+const char *sbl_link_vendor_str(enum sbl_link_vendor vendor);
+const char *sbl_link_media_str(enum sbl_link_media media);
+const char *sbl_an_mode_str(enum sbl_an_mode mode);
+const char *sbl_link_mode_str(enum sbl_link_mode mode);
+const char *sbl_rs_mode_str(enum sbl_rs_mode mode);
+const char *sbl_ifg_mode_str(enum sbl_ifg_mode mode);
+const char *sbl_ifg_config_str(enum sbl_ifg_config config);
+const char *sbl_llr_mode_str(enum sbl_llr_mode mode);
+const char *sbl_llr_down_behaviour_str(enum sbl_llr_down_behaviour behaviour);
+const char *sbl_loopback_mode_str(enum sbl_loopback_mode state);
+const char *sbl_serdes_effort_str(u32 effort);
+const char *sbl_serdes_state_str(enum sbl_serdes_status state);
+const char *sbl_async_alert_str(enum sbl_async_alert_type alert_type);
+const char *sbl_fec_discard_str(enum sbl_fec_discard_type discard_type);
+const char *sbl_down_origin_str(enum sbl_link_down_origin down_origin);
+
+/* SBL counter get functions */
+int sbl_link_counters_get(struct sbl_inst *sbl, int port_num,
+						int *counters, u16 first, u16 count);
+int sbl_link_counters_read(struct sbl_inst *sbl, int port_num, u16 counter);
+
+/*
+ * Function to generate a hash of the given state configuration.
+ * The function can be used to create either match values or match masks
+ *     hash0:
+ *     link_partner:	0x00000000000000ff
+ *     loopback_mode:	0x000000000000ff00
+ *     tuning_pattern:	0x0000000000ff0000
+ *     link_mode:	0x00000000ff000000
+ *     media_type:	0x000000ff00000000
+ *     media_vendor:	0x00ffff0000000000
+ *     hash1:
+ *     media_len:	0xffffffffffffffff
+ *     e.g. If the configuration applies for all LPs and TPs, and for LB off,
+ *          LM of BJ_100, 1m copper cables for all vendors, then set the
+ *          following:
+ *     hash0 = 0x00ff010201ff04ff
+ *     hash1 = 0x0000000000000020
+ *
+ */
+static inline u64 sbl_create_tp_hash0(u8 link_partner_mask,
+					u8 loopback_mode_mask,
+					u8 tuning_pattern_mask,
+					u8 link_mode_mask,
+					u8 media_type_mask,
+					u16 media_vendor_mask)
+{
+	u64 hash = 0;
+
+	SBL_TPH_LP_SET(hash, link_partner_mask);
+	SBL_TPH_LB_SET(hash, loopback_mode_mask);
+	SBL_TPH_TP_SET(hash, tuning_pattern_mask);
+	SBL_TPH_LM_SET(hash, link_mode_mask);
+	SBL_TPH_MT_SET(hash, media_type_mask);
+	SBL_TPH_MV_SET(hash, media_vendor_mask);
+
+	return hash;
+}
+static inline u64 sbl_create_tp_hash1(u64 media_len_mask)
+{
+	u64 hash = 0;
+
+	SBL_TPH_ML_SET(hash, media_len_mask);
+
+	return hash;
+}
+
+#endif /* _SBL_H_ */
diff --git a/include/linux/hpe/sbl/sbl_an.h b/include/linux/hpe/sbl/sbl_an.h
new file mode 100644
index 000000000000..09b30743636f
--- /dev/null
+++ b/include/linux/hpe/sbl/sbl_an.h
@@ -0,0 +1,174 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/* Copyright 2019-2026 Hewlett Packard Enterprise Development LP */
+
+/* This header file includes definitions relating to the autonegotiation
+   feature. This information comes largely from Clause 73 of 802.3-2015 */
+
+
+#ifndef SBL_AN_H
+#define SBL_AN_H
+
+/* See section 73.6 of the IEEE 802.3-2015 standard for an explanation of the link
+   codeword encoding */
+
+/* Control word (base page) structure */
+
+/* Selector Field */
+/* Bits D0:D4/S0:S4 */
+#define AN_CW_S_BASE_BIT            0
+#define AN_CW_S_MASK                0x1F
+#define AN_CW_S_802_3               1
+
+/* Echoed Nonce */
+/* Bits D5:D9/E0:E4 */
+#define AN_CW_E_BASE_BIT            5
+#define AN_CW_E_MASK                (0x1FL << AN_CW_E_BASE_BIT)
+
+/* Pause Ability */
+/* Bits D10:D12/C0:C2 */
+#define AN_CW_C_BASE_BIT            10
+#define AN_CW_C_MASK                (0x7L << AN_CW_C_BASE_BIT)
+#define AN_CW_C_SYMMETRIC_BIT       0
+#define AN_CW_C_SYMMETRIC           (1L << AN_CW_C_SYMMETRIC_BIT)
+#define AN_CW_C_ASYMMETRIC_BIT      1
+#define AN_CW_C_ASYMMETRIC          (1L << AN_CW_C_ASYMMETRIC_BIT)
+/* C2 is reserved */
+
+/* Remote Fault */
+/* Bit D13 */
+#define AN_CW_RF_BIT                13
+#define AN_CW_RF_MASK               (1L << AN_CW_RF_BIT)
+
+/* Ack */
+/* Bit D14 */
+#define AN_CW_ACK_BIT               14
+#define AN_CW_ACK_MASK              (1L << AN_CW_ACK_BIT)
+
+/* Next Page */
+/* Bit D15 */
+#define AN_CW_NP_BIT                15
+#define AN_CW_NP_MASK               (1L << AN_CW_NP_BIT)
+
+/* Transmitted Nonce */
+/* Bits D16:D20/T0:T4 */
+#define AN_CW_T_BASE_BIT            16
+#define AN_CW_T_MASK                (0x1FL << AN_CW_T_BASE_BIT)
+
+/* Technology Ability */
+/* Bits D21:D43/A0:A22 */
+/* NB top 2 bits moved into Fec ability field in updated spec ???? */
+#define AN_CW_A_BASE_BIT            21
+#define AN_CW_A_MASK                (0x1FFFFFL << AN_CW_A_BASE_BIT)
+#define AN_CW_A_1000BASE_KX_BIT     0
+#define AN_CW_A_1000BASE_KX         (1L << AN_CW_A_1000BASE_KX_BIT)
+#define AN_CW_A_10GBASE_KX4_BIT     1
+#define AN_CW_A_10GBASE_KX4         (1L << AN_CW_A_10GBASE_KX4_BIT)
+#define AN_CW_A_10GBASE_KR_BIT      2
+#define AN_CW_A_10GBASE_KR          (1L << AN_CW_A_10GBASE_KR_BIT)
+#define AN_CW_A_40GBASE_KR4_BIT     3
+#define AN_CW_A_40GBASE_KR4         (1L << AN_CW_A_40GBASE_KR4_BIT)
+#define AN_CW_A_40GBASE_CR4_BIT     4
+#define AN_CW_A_40GBASE_CR4         (1L << AN_CW_A_40GBASE_CR4_BIT)
+#define AN_CW_A_100GBASE_CR10_BIT   5
+#define AN_CW_A_100GBASE_CR10       (1L << AN_CW_A_100GBASE_CR10_BIT)
+#define AN_CW_A_100GBASE_KP4_BIT    6
+#define AN_CW_A_100GBASE_KP4        (1L << AN_CW_A_100GBASE_KP4_BIT)
+#define AN_CW_A_100GBASE_KR4_BIT    7
+#define AN_CW_A_100GBASE_KR4        (1L << AN_CW_A_100GBASE_KR4_BIT)
+#define AN_CW_A_100GBASE_CR4_BIT    8
+#define AN_CW_A_100GBASE_CR4        (1L << AN_CW_A_100GBASE_CR4_BIT)
+#define AN_CW_A_25GBASE_KR_S_BIT    9
+#define AN_CW_A_25GBASE_KR_S        (1L << AN_CW_A_25GBASE_KR_S_BIT)
+#define AN_CW_A_25GBASE_KR_BIT      10
+#define AN_CW_A_25GBASE_KR          (1L << AN_CW_A_25GBASE_KR_BIT)
+#define AN_CW_A_2P5GBASE_KX_BIT     11
+#define AN_CW_A_2P5GBASE_KX         (1L << AN_CW_A_2P5GBASE_KX_BIT)
+#define AN_CW_A_5GBASE_KR_BIT       12
+#define AN_CW_A_5GBASE_KR           (1L << AN_CW_A_5GBASE_KR_BIT)
+#define AN_CW_A_50GBASE_KR_BIT      13
+#define AN_CW_A_50GBASE_KR          (1L << AN_CW_A_50GBASE_KR_BIT)
+#define AN_CW_A_50GBASE_CR_BIT      AN_CW_A_50GBASE_KR_BIT
+#define AN_CW_A_50GBASE_CR          AN_CW_A_50GBASE_KR
+#define AN_CW_A_100GBASE_KR2_BIT    14
+#define AN_CW_A_100GBASE_KR2        (1L << AN_CW_A_100GBASE_KR2_BIT)
+#define AN_CW_A_100GBASE_CR2_BIT    AN_CW_A_100GBASE_KR2_BIT
+#define AN_CW_A_100GBASE_CR2        AN_CW_A_100GBASE_KR2
+#define AN_CW_A_200GBASE_KR4_BIT    15
+#define AN_CW_A_200GBASE_KR4        (1ULL << AN_CW_A_200GBASE_KR4_BIT)
+#define AN_CW_A_200GBASE_CR4_BIT    AN_CW_A_200GBASE_KR4_BIT
+#define AN_CW_A_200GBASE_CR4        AN_CW_A_200GBASE_KR4
+/* Bits 16-22 are reserved for future use */
+
+/* FEC Capability */
+/* Bits D46:D47/F0:F1, D44:D45/F2:F3 */
+#define AN_CW_F_BASE_BIT            44
+#define AN_CW_F_MASK                (0xFL << AN_CW_F_BASE_BIT)
+#define AN_CW_F_10G_ABILITY_BIT     2
+#define AN_CW_F_10G_ABILITY         (1L << AN_CW_F_10G_ABILITY_BIT)
+#define AN_CW_F_10G_REQUESTED_BIT   3
+#define AN_CW_F_10G_REQUESTED       (1L << AN_CW_F_10G_REQUESTED_BIT)
+#define AN_CW_F_25G_RS_REQ_BIT      0
+#define AN_CW_F_25G_RS_REQ          (1L << AN_CW_F_25G_RS_REQ_BIT)
+#define AN_CW_F_25G_BASER_REQ_BIT   1
+#define AN_CW_F_25G_BASER_REQ       (1L << AN_CW_F_25G_BASER_REQ_BIT)
+
+/* Next page structure */
+
+/* Next page (same as CW) */
+/* Bit D15 */
+#define AN_NP_NP_MASK               AN_CW_NP_MASK
+
+/* Toggle */
+/* Bit D11 */
+#define AN_NP_T_BIT                 11
+#define AN_NP_T_MASK                (1L << AN_NP_T_BIT)
+
+/* Message page */
+/* Bit D13 */
+#define AN_NP_MP_BIT                13
+#define AN_NP_MP_MASK               (1 << AN_NP_MP_BIT)
+
+/* Message code */
+/* Bits D0:D10,M0:M10 */
+#define AN_NP_MSG_BASE_BIT          0x0L
+#define AN_NP_MSG_MASK              (0x7ffULL << AN_NP_MSG_BASE_BIT)
+
+/* Unformatted code field */
+/* Bits D16:D47,U0:U31 */
+#define AN_NP_UCF_BASE_BIT          16
+#define AN_NP_UCF_MASK              (0xffffffffULL << AN_NP_UCF_BASE_BIT)
+
+/* OUI field */
+/* Bits D16:D39,U0:U23 */
+#define AN_NP_OUI_BASE_BIT          16
+#define AN_NP_OUI_MASK              (0xffffffULL << AN_NP_OUI_BASE_BIT)
+
+/* user defined data field */
+/* Bits D40:D47,U24:U31 */
+#define AN_NP_USR_BASE_BIT          40
+#define AN_NP_USR_MASK              (0xffULL << AN_NP_USR_BASE_BIT)
+
+/* Message codes */
+#define AN_NP_CODE_NULL_MSG         0x1ULL
+#define AN_NP_CODE_OUI_MSG          0x5ULL   /* Organizationally Unique Identifier Tagged Message            */
+#define AN_NP_CODE_OUI_EXTENDED_MSG 0xBULL   /* Organizationally Unique Identifier Tagged Message (Extended) */
+
+/* HPE OUI */
+#define AN_NP_OUI_HPE               (0xEC9B8BULL << AN_NP_OUI_BASE_BIT)
+#define AN_NP_OUI_VER_0_1           (0x01ULL << AN_NP_UCF_BASE_BIT)
+#define AN_NP_OUI_VER_MASK          (0xFFULL << AN_NP_UCF_BASE_BIT)
+
+/* AN options */
+#define AN_OPT_LLR                  (1ULL << 0)
+#define AN_OPT_ETHER_LLR            (1ULL << 1)
+#define AN_OPT_HPC_WITH_LLR         (1ULL << 2)
+/* TODO: add IPV4 option */
+#define AN_OPT_BASE_BIT             (AN_NP_UCF_BASE_BIT + 8)
+#define AN_OPT_MASK                 (AN_OPT_ETHER_LLR | AN_OPT_HPC_WITH_LLR | AN_OPT_LLR)
+
+/* Cassini */
+#define AN_LP_SUBTYPE_BASE_BIT      (AN_OPT_BASE_BIT + 8)
+#define AN_LP_SUBTYPE_MASK          (0x7ULL)
+
+#endif /* SBL_AN_H */
diff --git a/include/linux/hpe/sbl/sbl_csr_common.h b/include/linux/hpe/sbl/sbl_csr_common.h
new file mode 100644
index 000000000000..f8229b992436
--- /dev/null
+++ b/include/linux/hpe/sbl/sbl_csr_common.h
@@ -0,0 +1,63 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Common utility defines.
+ * Copyright 2020 Cray Inc. All rights reserved
+ */
+#ifndef _SBL_CSR_COMMON_H_
+#define _SBL_CSR_COMMON_H_
+
+/* Extra massaging of Cassini definitions */
+#define C_CSR_MASK(type, member)      \
+	({                            \
+		uint64_t mask = 0;    \
+		union type t = { 0 }; \
+		t.member = -1;        \
+		mask = t.qw;          \
+		mask;                 \
+	})
+#define C_CSR_WORD_MASK(type, member, word) \
+	({                                  \
+		uint64_t mask = 0;          \
+		union type t = { 0 };       \
+		t.member = -1;              \
+		mask = t.qw[word];          \
+		mask;                       \
+	})
+#define C_CSR_OFFSET(type, member)                    \
+	({                                            \
+		int offset = 0;                       \
+		union type t = { 0 };                 \
+		t.member = 1;                         \
+		while (((t.qw >> offset) & 1) == 0) { \
+			offset++;                     \
+		}                                     \
+		offset;                               \
+	})
+#define C_CSR_WORD_OFFSET(type, member, word)               \
+	({                                                  \
+		int offset = 0;                             \
+		union type t = { 0 };                       \
+		t.member = 1;                               \
+		while (((t.qw[word] >> offset) & 1) == 0) { \
+			offset++;                           \
+		}                                           \
+		offset;                                     \
+	})
+
+/* UPDATE defines */
+#define C_UPDATE(val, value, type, member) \
+	(((val) & (~C_CSR_MASK(type, member))) | C_SET(value, type, member))
+
+/* SET defines */
+#define C_SET(value, type, member)                                       \
+	((((unsigned long long)(value)) << C_CSR_OFFSET(type, member)) & \
+	 C_CSR_MASK(type, member))
+
+/* GET defines */
+#define C_GET(value, type, member) \
+	(((value) & C_CSR_MASK(type, member)) >> C_CSR_OFFSET(type, member))
+#define C_WORD_GET(value, type, member, word)               \
+	(((value) & C_CSR_WORD_MASK(type, member, word)) >> \
+	 C_CSR_WORD_OFFSET(type, member, word))
+
+#endif /* _SBL_CSR_COMMON_H_ */
diff --git a/include/linux/hpe/sbl/sbl_fec.h b/include/linux/hpe/sbl/sbl_fec.h
new file mode 100644
index 000000000000..23594d79a91a
--- /dev/null
+++ b/include/linux/hpe/sbl/sbl_fec.h
@@ -0,0 +1,88 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/* Copyright 2024 Hewlett Packard Enterprise Development LP */
+
+/* FEC up check */
+#define SBL_FEC_UP_SETTLE_PERIOD	 250	   /* ms */
+#define SBL_FEC_UP_WINDOW		 250	   /* ms */
+#define SBL_FEC_UP_COUNT_FABRIC		 4
+#define SBL_FEC_UP_COUNT_EDGE		 1
+#define SBL_FEC_MON_PERIOD		 1000	   /* 1sec*/
+#define SBL_FEC_LLR_TX_REPLAY_THRESH	 100000	   /* llr_tx_replays/s */
+#define SBL_PCS_NUM_FECL_CNTRS		 8
+#define SBL_MAX_FEC_WARNINGS		 3	   /* number of warnings issued */
+
+struct sbl_pcs_fec_cntrs {
+	u64 ccw;				  /* corrected code words */
+	u64 ucw;				  /* uncorrected code words */
+	u64 llr_tx_replay;			  /* llr_tx_replay_event count */
+	u64 fecl[SBL_PCS_NUM_FECL_CNTRS];	  /* lane errors */
+	unsigned long time;			  /* either abs or interval */
+};
+
+
+
+struct sbl_inst;
+
+struct sbl_fec {
+	struct sbl_pcs_fec_cntrs *fec_curr_cnts;   /* current fec counters */
+	struct sbl_pcs_fec_cntrs *fec_prev_cnts;   /* previous fec counts */
+	struct sbl_pcs_fec_cntrs *fec_rates;	   /* current fec rates */
+	struct sbl_pcs_fec_cntrs fec_cntrs[2];
+	spinlock_t fec_cnt_lock;		   /* locks above pointers */
+
+	u64 fec_ucw_thresh;			   /* uncorrected codewords link up threshold */
+	u32 fec_ucw_up_thresh_adj;		   /* debug: percentage adjustment for link up threshold */
+	u32 fec_ucw_down_thresh_adj;		   /* percentage adjustment for link down threshold */
+	u32 fec_ucw_hwm;			   /* highest value measured */
+
+	u64 fec_ccw_thresh;			   /* corrected codewords link up threshold */
+	u32 fec_ccw_up_thresh_adj;		   /* debug: percentage adjustment for link up threshold */
+	u64 fec_stp_ccw_thresh;			   /* corrected codewords link up threshold when STP is used */
+	u32 fec_stp_ccw_up_thresh_adj;		   /* percentage adjustment for link up threshold when STP is used */
+	u32 fec_ccw_down_thresh_adj;		   /* percentage adjustment for link down threshold */
+	u32 fec_ccw_hwm;			   /* highest value measured */
+
+	u64 fec_llr_tx_replay_thresh;		   /* LLR TX Replay threshold */
+	u32 fec_llr_tx_replay_hwm;		   /* highest value measured */
+	u32 fecl_warn;				   /* corrected codewords per fec lane warning threshold */
+	spinlock_t fec_cw_lock;			   /* lock above thresholds */
+};
+
+
+/**
+ * @brief link monitor flags for setting fec thresholds
+ *
+ *	  Can be used in place of explicit threshold values
+ *
+ */
+
+enum sbl_link_fec_flags {
+	SBL_LINK_FEC_INVALID	=  0,	/**< invalid */
+	SBL_LINK_FEC_OFF	= -1,	/**< disable monitoring */
+	SBL_LINK_FEC_IEEE	= -2,	/**< Use IEEE value for link mode and media */
+	SBL_LINK_FEC_HPE	= -3,	/**< Use HPE value for link mode and media */
+	SBL_LINK_FEC_DEFAULT	= SBL_LINK_FEC_HPE,
+};
+
+void sbl_fec_thresholds_clear(struct sbl_inst *sbl, int port_num);
+int sbl_fec_adjustments_set(struct sbl_inst *sbl, int port_num,
+		u32 ucw_adj, u32 ccw_adj);
+
+int sbl_fec_thresholds_set(struct sbl_inst *sbl, int port_num,
+		s32 ucw_in, s32 ccw_in);
+
+void sbl_fec_counts_get(struct sbl_inst *sbl, int port_num, struct sbl_pcs_fec_cntrs *cntrs);
+int sbl_fec_up_check(struct sbl_inst *sbl, int port_num);
+void sbl_zero_all_fec_counts(struct sbl_inst *sbl, int port_num);
+void sbl_fec_timer(struct timer_list *timer);
+void sbl_fec_hwms_clear(struct sbl_inst *sbl, int port_num);
+void sbl_fec_dump(struct sbl_inst *sbl, int port_num);
+void sbl_fec_modify_adjustments(struct sbl_inst *sbl, int port_num,
+		u32 *ucw_up_adj, u32 *ccw_up_adj, u32 *ucw_down_adj, u32 *ccw_down_adj, u32 *stp_ccw_up_adj);
+int sbl_fec_txr_rate_set(struct sbl_inst *sbl, int port_num,
+		u32 txr_rate);
+void sbl_fec_timer_work(struct work_struct *work);
+void sbl_fec_ccw_bad_get(struct sbl_fec *fec_prmts, bool use_stp_thresh,
+			u64 *ccw_bad, u64 *ccw_hwm);
+void sbl_fec_ucw_bad_get(struct sbl_fec *fec_prmts, u64 *ucw_bad, u64 *ucw_hwm);
diff --git a/include/linux/hpe/sbl/sbl_kconfig.h b/include/linux/hpe/sbl/sbl_kconfig.h
new file mode 100644
index 000000000000..87a312716906
--- /dev/null
+++ b/include/linux/hpe/sbl/sbl_kconfig.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2019-2026 Hewlett Packard Enterprise Development LP. All rights reserved. */
+/*   Kconfig fixup for external modules
+ *
+ *   It is not possible to use the normal Kconfig infrastructure for
+ *   externally built modules
+ *
+ *   When building out-of-tree we define an SBL_EXTERNAL_BUILD=1 environment
+ *   variable and we use this to setup the configuration
+ *
+ *   We must also define one of the following target platforms:
+ *    PLATFORM_ROSETTA_HW=1
+ *    PLATFORM_CASSINI_HW=1
+ *
+ *   If we ever need to build in-tree then constructing a Kconfig
+ *   file should be simple
+ *
+ */
+
+#ifndef _SBL_KCONFIG_H_
+#define _SBL_KCONFIG_H_
+
+/* currently unused config options we don't want to forget about */
+#undef  SBL_FAST_AUTONEG
+#undef  SBL_MAC_PCS_EMU
+
+/* Share platform-specific build constants with exported UAPI users. */
+#include <uapi/ethernet/sbl_platform_config.h>
+
+#undef SBL_PLATFORM_ROS_HW
+#undef SBL_PLATFORM_CAS_HW
+
+#endif /* _SBL_KCONFIG_H_ */
diff --git a/include/linux/hpe/sbl/sbl_mb.h b/include/linux/hpe/sbl/sbl_mb.h
new file mode 100644
index 000000000000..0805e4e389cc
--- /dev/null
+++ b/include/linux/hpe/sbl/sbl_mb.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Platform-specific definitions of SBL_* macros.
+ * Copyright 2020 Cray Inc. All rights reserved
+ */
+#ifndef _SBL_MB_H_
+#define _SBL_MB_H_
+
+#include <uapi/ethernet/cassini_user_defs.h>
+#include "sbl_csr_common.h"
+
+/* BASE defines */
+#define SBL_MB_MB_BASE C_MB_BASE
+
+/* OFFSET defines */
+#define SBL_MB_DBG_CFG_SBUS_MASTER_OFFSET(a) C_MB_DBG_CFG_SBUS_MASTER_OFFSET
+#define SBL_MB_DBG_STS_SBUS_MASTER_OFFSET(a) C_MB_DBG_STS_SBUS_MASTER_OFFSET
+
+/* UPDATE defines */
+
+/* DFLT defines */
+
+/* SET defines */
+#define SBL_MB_DBG_STS_SBUS_MASTER_OVERRUN_SET(a) \
+	C_SET(a, c_mb_dbg_sts_sbus_master, overrun)
+#define SBL_MB_DBG_STS_SBUS_MASTER_WRITE_ERROR_SET(a) \
+	C_SET(a, c_mb_dbg_sts_sbus_master, write_error)
+#define SBL_MB_DBG_CFG_SBUS_MASTER_DATA_SET(a) \
+	C_SET(a, c_mb_dbg_cfg_sbus_master, data)
+#define SBL_MB_DBG_CFG_SBUS_MASTER_DATA_ADDRESS_SET(a) \
+	C_SET(a, c_mb_dbg_cfg_sbus_master, data_address)
+#define SBL_MB_DBG_CFG_SBUS_MASTER_RECEIVER_ADDRESS_SET(a) \
+	C_SET(a, c_mb_dbg_cfg_sbus_master, receiver_address)
+#define SBL_MB_DBG_CFG_SBUS_MASTER_COMMAND_SET(a) \
+	C_SET(a, c_mb_dbg_cfg_sbus_master, command)
+#define SBL_MB_DBG_CFG_SBUS_MASTER_STOP_ON_WRITE_ERROR_SET(a) \
+	C_SET(a, c_mb_dbg_cfg_sbus_master, stop_on_write_error)
+#define SBL_MB_DBG_CFG_SBUS_MASTER_STOP_ON_OVERRUN_SET(a) \
+	C_SET(a, c_mb_dbg_cfg_sbus_master, stop_on_overrun)
+#define SBL_MB_DBG_CFG_SBUS_MASTER_MODE_SET(a) \
+	C_SET(a, c_mb_dbg_cfg_sbus_master, mode)
+#define SBL_MB_DBG_CFG_SBUS_MASTER_RCV_DATA_VALID_SEL_SET(a) \
+	C_SET(a, c_mb_dbg_cfg_sbus_master, rcv_data_valid_sel)
+#define SBL_MB_DBG_CFG_SBUS_MASTER_EXECUTE_SET(a) \
+	C_SET(a, c_mb_dbg_cfg_sbus_master, execute)
+#define SBL_MB_DBG_CFG_SBUS_MASTER_SET(DATA, DATA_ADDRESS, RECEIVER_ADDRESS, \
+				       COMMAND, STOP_ON_WRITE_ERROR,         \
+				       STOP_ON_OVERRUN, MODE,                \
+				       RCV_DATA_VALID_SEL, EXECUTE)          \
+	(SBL_MB_DBG_CFG_SBUS_MASTER_DATA_SET(DATA) |                         \
+	 SBL_MB_DBG_CFG_SBUS_MASTER_DATA_ADDRESS_SET(DATA_ADDRESS) |         \
+	 SBL_MB_DBG_CFG_SBUS_MASTER_RECEIVER_ADDRESS_SET(RECEIVER_ADDRESS) | \
+	 SBL_MB_DBG_CFG_SBUS_MASTER_COMMAND_SET(COMMAND) |                   \
+	 SBL_MB_DBG_CFG_SBUS_MASTER_STOP_ON_WRITE_ERROR_SET(                 \
+		 STOP_ON_WRITE_ERROR) |                                      \
+	 SBL_MB_DBG_CFG_SBUS_MASTER_STOP_ON_OVERRUN_SET(STOP_ON_OVERRUN) |   \
+	 SBL_MB_DBG_CFG_SBUS_MASTER_MODE_SET(MODE) |                         \
+	 SBL_MB_DBG_CFG_SBUS_MASTER_RCV_DATA_VALID_SEL_SET(                  \
+		 RCV_DATA_VALID_SEL) |                                       \
+	 SBL_MB_DBG_CFG_SBUS_MASTER_EXECUTE_SET(EXECUTE))
+
+/* GET defines */
+#define SBL_MB_DBG_STS_SBUS_MASTER_DATA_GET(a) \
+	C_GET(a, c_mb_dbg_sts_sbus_master, data)
+#define SBL_MB_DBG_STS_SBUS_MASTER_RESULT_CODE_GET(a) \
+	C_GET(a, c_mb_dbg_sts_sbus_master, result_code)
+#define SBL_MB_DBG_STS_SBUS_MASTER_OVERRUN_GET(a) \
+	C_GET(a, c_mb_dbg_sts_sbus_master, overrun)
+#define SBL_MB_DBG_STS_SBUS_MASTER_RCV_DATA_VALID_GET(a) \
+	C_GET(a, c_mb_dbg_sts_sbus_master, rcv_data_valid)
+#define SBL_MB_DBG_STS_SBUS_MASTER_WRITE_ERROR_GET(a) \
+	C_GET(a, c_mb_dbg_sts_sbus_master, write_error)
+
+/* Other defines */
+#define SBL_MB_DBG_CFG_SBUS_MASTER_ENTRIES 1
+
+#endif /* _SBL_MB_H_ */
diff --git a/include/linux/hpe/sbl/sbl_platform.h b/include/linux/hpe/sbl/sbl_platform.h
new file mode 100644
index 000000000000..d47630f9e84a
--- /dev/null
+++ b/include/linux/hpe/sbl/sbl_platform.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SBL_PLATFORM_H_
+#define _SBL_PLATFORM_H_
+
+#define SBUS_RING_MTX(sbl, ring) ((sbl)->sbus_ring_mtx)
+#define SBM_FW_MTX(sbl, ring) ((sbl)->sbm_fw_mtx)
+
+#define sbl_dev_log(_logfn, _dev, _fmt, ...)						\
+	do {									\
+		char __sbl_inst[sizeof(sbl->iattr.inst_name)];			\
+		char __sbl_eth[sizeof(sbl->iattr.eth_if_name)];		\
+		sbl_inst_names_get(sbl, __sbl_inst, __sbl_eth);			\
+		_logfn((_dev), "%s[%s]: " _fmt, __sbl_inst, __sbl_eth, ##__VA_ARGS__);	\
+	} while (0)
+
+#define sbl_dev_err(_dev, _fmt, ...) sbl_dev_log(dev_err, _dev, _fmt, ##__VA_ARGS__)
+#define sbl_dev_dbg(_dev, _fmt, ...) sbl_dev_log(dev_dbg, _dev, _fmt, ##__VA_ARGS__)
+#define sbl_dev_warn(_dev, _fmt, ...) sbl_dev_log(dev_warn, _dev, _fmt, ##__VA_ARGS__)
+#define sbl_dev_info(_dev, _fmt, ...) sbl_dev_log(dev_info, _dev, _fmt, ##__VA_ARGS__)
+#define sbl_dev_err_ratelimited(_dev, _fmt, ...) \
+	sbl_dev_log(dev_err_ratelimited, _dev, _fmt, ##__VA_ARGS__)
+#define sbl_dev_dbg_ratelimited(_dev, _fmt, ...) \
+	sbl_dev_log(dev_dbg_ratelimited, _dev, _fmt, ##__VA_ARGS__)
+/* Configuration passing into SBL init */
+struct sbl_init_attr {
+	u32 magic;
+	u32 uc_nic;
+	u32 uc_platform;
+	bool is_hw;
+};
+
+#endif /* _SBL_PLATFORM_H_ */
diff --git a/include/linux/hpe/sbl/sbl_pml.h b/include/linux/hpe/sbl/sbl_pml.h
new file mode 100644
index 000000000000..92b32f1dcf22
--- /dev/null
+++ b/include/linux/hpe/sbl/sbl_pml.h
@@ -0,0 +1,1081 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Platform-specific definitions of SBL_* macros.
+ * Copyright 2020-2023 Cray Inc. All rights reserved
+ */
+#ifndef _SBL_PML_H_
+#define _SBL_PML_H_
+
+#include <uapi/ethernet/cassini_user_defs.h>
+#include <linux/hpe/cxi/cassini_csr_defaults.h>
+#include "sbl_csr_common.h"
+#include <linux/hpe/cxi/cassini_cntr_defs.h>
+
+/* BASE defines */
+#define SBL_PML_BASE(a) C_HNI_PML_BASE
+
+#define SBL_PCS_FECL_ERRORS_00_ADDR(a)                       \
+	C_HNI_STS_EVENT_CNTS(C1_CNTR_HNI_PCS_FECL_ERRORS_0 - \
+			     C_CNTR_HNI_COR_ECC_ERR_CNTR)
+#define SBL_PCS_FECL_ERRORS_01_ADDR(a)                       \
+	C_HNI_STS_EVENT_CNTS(C1_CNTR_HNI_PCS_FECL_ERRORS_1 - \
+			     C_CNTR_HNI_COR_ECC_ERR_CNTR)
+#define SBL_PCS_FECL_ERRORS_02_ADDR(a)                       \
+	C_HNI_STS_EVENT_CNTS(C1_CNTR_HNI_PCS_FECL_ERRORS_2 - \
+			     C_CNTR_HNI_COR_ECC_ERR_CNTR)
+#define SBL_PCS_FECL_ERRORS_03_ADDR(a)                       \
+	C_HNI_STS_EVENT_CNTS(C1_CNTR_HNI_PCS_FECL_ERRORS_3 - \
+			     C_CNTR_HNI_COR_ECC_ERR_CNTR)
+#define SBL_PCS_FECL_ERRORS_04_ADDR(a)                       \
+	C_HNI_STS_EVENT_CNTS(C1_CNTR_HNI_PCS_FECL_ERRORS_4 - \
+			     C_CNTR_HNI_COR_ECC_ERR_CNTR)
+#define SBL_PCS_FECL_ERRORS_05_ADDR(a)                       \
+	C_HNI_STS_EVENT_CNTS(C1_CNTR_HNI_PCS_FECL_ERRORS_5 - \
+			     C_CNTR_HNI_COR_ECC_ERR_CNTR)
+#define SBL_PCS_FECL_ERRORS_06_ADDR(a)                       \
+	C_HNI_STS_EVENT_CNTS(C1_CNTR_HNI_PCS_FECL_ERRORS_6 - \
+			     C_CNTR_HNI_COR_ECC_ERR_CNTR)
+#define SBL_PCS_FECL_ERRORS_07_ADDR(a)                       \
+	C_HNI_STS_EVENT_CNTS(C1_CNTR_HNI_PCS_FECL_ERRORS_7 - \
+			     C_CNTR_HNI_COR_ECC_ERR_CNTR)
+#define SBL_PCS_CORRECTED_CW_ADDR(a)                        \
+	C_HNI_STS_EVENT_CNTS(C1_CNTR_HNI_PCS_CORRECTED_CW - \
+			     C_CNTR_HNI_COR_ECC_ERR_CNTR)
+#define SBL_PCS_UNCORRECTED_CW_ADDR(a)                        \
+	C_HNI_STS_EVENT_CNTS(C1_CNTR_HNI_PCS_UNCORRECTED_CW - \
+			     C_CNTR_HNI_COR_ECC_ERR_CNTR)
+#define SBL_LLR_TX_REPLAY_EVENT_ADDR(a)                        \
+	C_HNI_STS_EVENT_CNTS(C1_CNTR_HNI_LLR_TX_REPLAY_EVENT - \
+			     C_CNTR_HNI_COR_ECC_ERR_CNTR)
+
+/* OFFSET defines */
+#define SBL_PML_CFG_LLR_CAPACITY_OFFSET C1_HNI_PML_CFG_LLR_CAPACITY_OFFSET
+#define SBL_PML_CFG_LLR_CF_ETYPE_OFFSET C1_HNI_PML_CFG_LLR_CF_ETYPE_OFFSET
+#define SBL_PML_CFG_LLR_CF_SMAC_OFFSET C1_HNI_PML_CFG_LLR_CF_SMAC_OFFSET
+#define SBL_PML_CFG_LLR_CF_RATES_OFFSET C1_HNI_PML_CFG_LLR_CF_RATES_OFFSET
+#define SBL_PML_CFG_LLR_OFFSET C1_HNI_PML_CFG_LLR_OFFSET
+#define SBL_PML_CFG_LLR_SM_OFFSET C1_HNI_PML_CFG_LLR_SM_OFFSET
+#define SBL_PML_CFG_LLR_TIMEOUTS_OFFSET C1_HNI_PML_CFG_LLR_TIMEOUTS_OFFSET
+#define SBL_PML_CFG_PCS_AMS_OFFSET C1_HNI_PML_CFG_PCS_AMS_OFFSET
+#define SBL_PML_CFG_PCS_AUTONEG_BASE_PAGE_OFFSET \
+	C1_HNI_PML_CFG_PCS_AUTONEG_BASE_PAGE_OFFSET
+#define SBL_PML_CFG_PCS_AUTONEG_NEXT_PAGE_OFFSET \
+	C1_HNI_PML_CFG_PCS_AUTONEG_NEXT_PAGE_OFFSET
+#define SBL_PML_CFG_PCS_AUTONEG_OFFSET C1_HNI_PML_CFG_PCS_AUTONEG_OFFSET
+#define SBL_PML_CFG_PCS_AUTONEG_TIMERS_OFFSET \
+	C1_HNI_PML_CFG_PCS_AUTONEG_TIMERS_OFFSET
+#define SBL_PML_CFG_PCS_CM_OFFSET C1_HNI_PML_CFG_PCS_CM_OFFSET
+#define SBL_PML_CFG_PCS_OFFSET C1_HNI_PML_CFG_PCS_OFFSET
+#define SBL_PML_CFG_PCS_UM_OFFSET C1_HNI_PML_CFG_PCS_UM_OFFSET
+#define SBL_PML_CFG_RX_MAC_OFFSET C1_HNI_PML_CFG_RX_MAC_OFFSET
+#define SBL_PML_CFG_RX_PCS_AMS_OFFSET C1_HNI_PML_CFG_RX_PCS_AMS_OFFSET
+#define SBL_PML_CFG_RX_PCS_OFFSET C1_HNI_PML_CFG_RX_PCS_OFFSET
+#define SBL_PML_CFG_SERDES_CORE_INTERRUPT_OFFSET \
+	C1_HNI_PML_CFG_SERDES_CORE_INTERRUPT_OFFSET
+#define SBL_PML_CFG_TX_MAC_OFFSET C1_HNI_PML_CFG_TX_MAC_OFFSET
+#define SBL_PML_CFG_TX_PCS_OFFSET C1_HNI_PML_CFG_TX_PCS_OFFSET
+#define SBL_PML_DBG_PCS_OFFSET C1_HNI_PML_DBG_PCS_OFFSET
+#define SBL_PML_ERR_CLR_OFFSET C1_HNI_PML_ERR_CLR_OFFSET
+#define SBL_PML_ERR_FLG_OFFSET C1_HNI_PML_ERR_FLG_OFFSET
+#define SBL_PML_SERDES_CORE_INTERRUPT_OFFSET \
+	C1_HNI_PML_SERDES_CORE_INTERRUPT_OFFSET
+#define SBL_PML_SERDES_CORE_STATUS_OFFSET C1_HNI_PML_SERDES_CORE_STATUS_OFFSET
+#define SBL_PML_STS_LLR_LOOP_TIME_OFFSET C1_HNI_PML_STS_LLR_LOOP_TIME_OFFSET
+#define SBL_PML_STS_LLR_OFFSET C1_HNI_PML_STS_LLR_OFFSET
+#define SBL_PML_STS_LLR_USAGE_OFFSET C1_HNI_PML_STS_LLR_USAGE_OFFSET
+#define SBL_PML_STS_LLR_MAX_USAGE_OFFSET C1_HNI_PML_STS_LLR_MAX_USAGE_OFFSET
+#define SBL_PML_STS_PCS_AUTONEG_BASE_PAGE_OFFSET \
+	C1_HNI_PML_STS_PCS_AUTONEG_BASE_PAGE_OFFSET
+#define SBL_PML_STS_PCS_AUTONEG_NEXT_PAGE_OFFSET \
+	C1_HNI_PML_STS_PCS_AUTONEG_NEXT_PAGE_OFFSET
+#define SBL_PML_STS_RX_PCS_OFFSET C1_HNI_PML_STS_RX_PCS_OFFSET
+#define SBL_PML_STS_PCS_LANE_DEGRADE_OFFSET \
+	C1_HNI_PML_STS_PCS_LANE_DEGRADE_OFFSET
+#define SBL_PML_STS_RX_PCS_DESKEW_DEPTHS_OFFSET \
+	C1_HNI_PML_STS_RX_PCS_DESKEW_DEPTHS_OFFSET
+#define SBL_PML_STS_RX_PCS_AM_MATCH_OFFSET C1_HNI_PML_STS_RX_PCS_AM_MATCH_OFFSET
+#define SBL_PML_STS_RX_PCS_FECL_SOURCES_OFFSET \
+	C1_HNI_PML_STS_RX_PCS_FECL_SOURCES_OFFSET
+
+/* UPDATE defines */
+#define SBL_PML_CFG_LLR_ACK_NACK_ERR_CHECK_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_llr, ack_nack_err_check)
+#define SBL_PML_CFG_LLR_ENABLE_LOOP_TIMING_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_llr, enable_loop_timing)
+#define SBL_PML_CFG_LLR_FILTER_CTL_FRAMES_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_llr, filter_ctl_frames)
+#define SBL_PML_CFG_LLR_FILTER_LOSSLESS_WHEN_OFF_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_llr, filter_lossless_when_off)
+#define SBL_PML_CFG_LLR_LINK_DOWN_BEHAVIOR_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_llr, link_down_behavior)
+#define SBL_PML_CFG_LLR_MAC_IF_CREDITS_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_llr, mac_if_credits)
+#define SBL_PML_CFG_LLR_LLR_MODE_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_llr, llr_mode)
+#define SBL_PML_CFG_LLR_CF_RATES_LOOP_TIMING_PERIOD_UPDATE(a, b) \
+	C_UPDATE(a, b, c_hni_pml_cfg_llr_cf_rates, loop_timing_period)
+#define SBL_PML_CFG_LLR_PREAMBLE_SEQ_CHECK_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_llr, preamble_seq_check)
+#define SBL_PML_CFG_LLR_SIZE_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_llr, size)
+#define SBL_PML_CFG_LLR_SM_REPLAY_CT_MAX_UPDATE(a, b) \
+	C_UPDATE(a, b, c_hni_pml_cfg_llr_sm, replay_ct_max)
+#define SBL_PML_CFG_LLR_SM_REPLAY_TIMER_MAX_UPDATE(a, b) \
+	C_UPDATE(a, b, c_hni_pml_cfg_llr_sm, replay_timer_max)
+#define SBL_PML_CFG_LLR_TIMEOUTS_DATA_AGE_TIMER_MAX_UPDATE(a, b) \
+	C_UPDATE(a, b, c_hni_pml_cfg_llr_timeouts, data_age_timer_max)
+#define SBL_PML_CFG_LLR_TIMEOUTS_PCS_LINK_DN_TIMER_MAX_UPDATE(a, b) \
+	C_UPDATE(a, b, c_hni_pml_cfg_llr_timeouts, pcs_link_dn_timer_max)
+#define SBL_PML_CFG_PCS_AMS_USE_PROGRAMMABLE_AMS_UPDATE(a, b) \
+	C_UPDATE(a, b, c_hni_pml_cfg_pcs_ams, use_programmable_ams)
+#define SBL_PML_CFG_PCS_AUTONEG_NEXT_PAGE_LOADED_UPDATE(a, b) \
+	C_UPDATE(a, b, c_hni_pml_cfg_pcs_autoneg, next_page_loaded)
+#define SBL_PML_CFG_RX_PCS_ALLOW_AUTO_DEGRADE_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_rx_pcs, allow_auto_degrade)
+#define SBL_PML_CFG_PCS_AUTONEG_RESET_UPDATE(a, b) \
+	C_UPDATE(a, b, c_hni_pml_cfg_pcs_autoneg, reset)
+#define SBL_PML_CFG_PCS_AUTONEG_TIMERS_BREAK_LINK_TIMER_MAX_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_pcs_autoneg_timers, break_link_timer_max)
+#define SBL_PML_CFG_PCS_AUTONEG_TIMERS_LINK_FAIL_INHIBIT_TIMER_MAX_UPDATE(a, \
+									  b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_pcs_autoneg_timers,                    \
+		 link_fail_inhibit_timer_max)
+#define SBL_PML_CFG_PCS_ENABLE_AUTO_LANE_DEGRADE_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_pcs, enable_auto_lane_degrade)
+#define SBL_PML_CFG_PCS_ENABLE_AUTO_NEG_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_pcs, enable_auto_neg)
+#define SBL_PML_CFG_PCS_PCS_ENABLE_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_pcs, pcs_enable)
+#define SBL_PML_CFG_PCS_PCS_MODE_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_pcs, pcs_mode)
+#define SBL_PML_CFG_PCS_BY_25G_FEC_MODE_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_pcs, by_25g_fec_mode)
+#define SBL_PML_CFG_PCS_TIMESTAMP_SHIFT_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_pcs, timestamp_shift)
+#define SBL_PML_CFG_RX_MAC_FILTER_ILLEGAL_SIZE_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_rx_mac, filter_illegal_size)
+#define SBL_PML_CFG_RX_MAC_MAC_OPERATIONAL_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_rx_mac, mac_operational)
+#define SBL_PML_CFG_RX_MAC_SHORT_PREAMBLE_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_rx_mac, short_preamble)
+#define SBL_PML_CFG_RX_PCS_ACTIVE_LANES_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_rx_pcs, active_lanes)
+#define SBL_PML_CFG_RX_PCS_ENABLE_CTL_OS_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_rx_pcs, enable_ctl_os)
+#define SBL_PML_CFG_RX_PCS_ENABLE_LOCK_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_rx_pcs, enable_lock)
+#define SBL_PML_CFG_RX_PCS_ENABLE_RX_SM_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_rx_pcs, enable_rx_sm)
+#define SBL_PML_CFG_RX_PCS_HEALTH_BAD_SENSITIVITY_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_rx_pcs, health_bad_sensitivity)
+#define SBL_PML_CFG_RX_PCS_RESTART_LOCK_ON_BAD_AMS_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_rx_pcs, restart_lock_on_bad_ams)
+#define SBL_PML_CFG_RX_PCS_RESTART_LOCK_ON_BAD_CWS_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_rx_pcs, restart_lock_on_bad_cws)
+#define SBL_PML_CFG_RX_PCS_RS_MODE_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_rx_pcs, rs_mode)
+#define SBL_PML_CFG_TX_MAC_IEEE_IFG_ADJUSTMENT_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_tx_mac, ieee_ifg_adjustment)
+#define SBL_PML_CFG_TX_MAC_IFG_MODE_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_tx_mac, ifg_mode)
+#define SBL_PML_CFG_TX_MAC_MAC_OPERATIONAL_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_tx_mac, mac_operational)
+#define SBL_PML_CFG_TX_MAC_PCS_CREDITS_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_tx_mac, pcs_credits)
+#define SBL_PML_CFG_TX_MAC_SHORT_PREAMBLE_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_tx_mac, short_preamble)
+#define SBL_PML_CFG_TX_PCS_CDC_READY_LEVEL_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_tx_pcs, cdc_ready_level)
+#define SBL_PML_CFG_TX_PCS_ENABLE_CTL_OS_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_tx_pcs, enable_ctl_os)
+#define SBL_PML_CFG_TX_PCS_GEARBOX_CREDITS_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_tx_pcs, gearbox_credits)
+#define SBL_PML_CFG_TX_PCS_LANE_0_SOURCE_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_tx_pcs, lane_0_source)
+#define SBL_PML_CFG_TX_PCS_LANE_1_SOURCE_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_tx_pcs, lane_1_source)
+#define SBL_PML_CFG_TX_PCS_LANE_2_SOURCE_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_tx_pcs, lane_2_source)
+#define SBL_PML_CFG_TX_PCS_LANE_3_SOURCE_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_tx_pcs, lane_3_source)
+#define SBL_PML_CFG_TX_PCS_ALLOW_AUTO_DEGRADE_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_cfg_tx_pcs, allow_auto_degrade)
+#define SBL_PML_DBG_PCS_ENABLE_RAPID_ALIGNMENT_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_dbg_pcs, enable_rapid_alignment)
+#define SBL_PML_DBG_PCS_FORCE_TX_DATA_RF_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_dbg_pcs, force_tx_data_rf)
+#define SBL_PML_DBG_PCS_FORCE_TX_DATA_UPDATE(a, b) \
+	C_UPDATE(a, b, c1_hni_pml_dbg_pcs, force_tx_data)
+
+/* DFLT defines */
+#define SBL_PML_CFG_LLR_MAC_IF_CREDITS C1_HNI_CFG_LLR_MAC__IF_CREDITS
+#define SBL_PML_CFG_TX_MAC_PCS_CREDITS C1_HNI_CFG_TX_MAC__PCS_CREDITS
+#define SBL_PML_CFG_TX_PCS_CDC_READY_LEVEL C1_HNI_CFG_TX_PCS__CDC_READY_LEVEL
+#define SBL_PML_CFG_TX_PCS_GEARBOX_CREDITS C1_HNI_CFG_TX_PCS__GEARBOX_CREDITS
+#define SBL_PML_CFG_TX_PCS_CDC_READY_LEVEL_DFLT \
+	C1_HNI_PML_CFG_TX_PCS__CDC_READY_LEVEL
+#define SBL_PML_CFG_TX_PCS_GEARBOX_CREDITS_DFLT \
+	C1_HNI_PML_CFG_TX_PCS__GEARBOX_CREDITS
+#define SBL_PML_CFG_TX_MAC_PCS_CREDITS_DFLT C1_HNI_PML_CFG_TX_MAC__PCS_CREDITS
+#define SBL_PML_CFG_LLR_MAC_IF_CREDITS_DFLT C1_HNI_PML_CFG_LLR__MAC_IF_CREDITS
+#define SBL_PML_CFG_LLR_CAPACITY_MAX_SEQ_DFLT \
+	C1_HNI_PML_CFG_LLR_CAPACITY__MAX_SEQ
+
+/* TODO - cassini_csr_defaults.h skips defaults when they are 0? */
+#define C1_HNI_PML_CFG_LLR__PREAMBLE_SEQ_CHECK 0x0
+#define C1_HNI_PML_CFG_LLR__ACK_NACK_ERR_CHECK 0x0
+#define C1_HNI_PML_CFG_LLR__LLR_MODE 0x0
+#define C1_HNI_PML_CFG_LLR__ENABLE_LOOP_TIMING 0x0
+#define C1_HNI_PML_CFG_LLR_SM__ALLOW_RE_INIT 0x0
+#define C_HNI_PML_CFG_LLR_CF_SMAC__CTL_FRAME_SMAC 0x0
+#define C1_HNI_PML_CFG_TX_MAC__IEEE_IFG_ADJUSTMENT 0ull
+#define C1_HNI_PML_CFG_TX_MAC__SHORT_PREAMBLE 0ull
+#define C1_HNI_PML_CFG_TX_MAC__MAC_OPERATIONAL 0ull
+#define C1_HNI_PML_CFG_RX_MAC__SHORT_PREAMBLE 0x0
+#define C1_HNI_PML_CFG_RX_MAC__MAC_OPERATIONAL 0x0
+#define C1_HNI_PML_CFG_RX_MAC__FILTER_ILLEGAL_SIZE 0x0
+#define C1_HNI_PML_DBG_PCS__ENABLE_RAPID_ALIGNMENT 0x0
+#define C1_HNI_PML_DBG_PCS__ENABLE_IDLE_CHECK 0x0
+#define C1_HNI_PML_DBG_PCS__FORCE_TX_DATA 0x0
+#define C1_HNI_PML_DBG_PCS__FORCE_TX_DATA_RF 0x0
+#define C1_HNI_PML_DBG_PCS__PPM_TEST_MODE 0x0
+#define C1_HNI_PML_CFG_RX_PCS__ACTIVE_LANES 0x0
+#define C1_HNI_PML_CFG_RX_PCS__ENABLE_LOCK 0x0
+#define C1_HNI_PML_CFG_RX_PCS__RESTART_LOCK_ON_BAD_AMS 0x0
+#define C1_HNI_PML_CFG_RX_PCS__RESTART_LOCK_ON_BAD_CWS 0x0
+#define C1_HNI_PML_CFG_RX_PCS__ENABLE_CTL_OS 0x0
+#define C1_HNI_PML_CFG_RX_PCS__LP_HEALTH_BAD_SENSITIVITY 0x0
+#define C1_HNI_PML_CFG_RX_PCS__ALLOW_AUTO_DEGRADE 0x0
+#define C1_HNI_PML_CFG_RX_PCS__ENABLE_RX_SM 0x0
+#define C1_HNI_PML_CFG_TX_PCS__LANE_0_SOURCE 0x0
+#define C1_HNI_PML_CFG_TX_PCS__ENABLE_CTL_OS 0x0
+#define C1_HNI_PML_CFG_TX_PCS__ALLOW_AUTO_DEGRADE 0x0
+#define C1_HNI_PML_CFG_PCS_AMS__USE_PROGRAMMABLE_AM_SPACING 0x0
+#define C1_HNI_PML_CFG_PCS_AMS__USE_PROGRAMMABLE_AMS 0x0
+#define C1_HNI_PML_CFG_PCS_AUTONEG_NEXT_PAGE__NEXT_PAGE 0x0
+#define C1_HNI_PML_CFG_PCS_AUTONEG_BASE_PAGE__BASE_PAGE 0x0
+#define C1_HNI_PML_CFG_PCS_AUTONEG__NEXT_PAGE_LOADED 0x0
+#define C1_HNI_PML_CFG_PCS_AUTONEG__RESTART 0x0
+#define C1_HNI_PML_CFG_PCS_AUTONEG__TX_LANE 0x0
+#define C1_HNI_PML_CFG_PCS_AUTONEG__RX_LANE 0x0
+#define C1_HNI_PML_CFG_PCS__PCS_ENABLE 0x0
+#define C1_HNI_PML_CFG_PCS__ENABLE_AUTO_NEG 0x0
+#define C1_HNI_PML_CFG_PCS__PCS_MODE 0x0
+#define C1_HNI_PML_CFG_PCS__ENABLE_AUTO_LANE_DEGRADE 0x0
+#define C1_HNI_PML_CFG_PCS__LL_FEC 0x0
+#define C1_HNI_PML_CFG_PCS__TIMESTAMP_SHIFT 0x0
+#define SBL_PML_CFG_LLR_CAPACITY_DFLT                     \
+	(SBL_PML_CFG_LLR_CAPACITY_MAX_DATA_SET(           \
+		 C1_HNI_PML_CFG_LLR_CAPACITY__MAX_DATA) | \
+	 SBL_PML_CFG_LLR_CAPACITY_MAX_SEQ_SET(            \
+		 C1_HNI_PML_CFG_LLR_CAPACITY__MAX_SEQ))
+#define SBL_PML_CFG_LLR_CF_ETYPE_DFLT                      \
+	(SBL_PML_CFG_LLR_CF_ETYPE_CTL_FRAME_ETHERTYPE_SET( \
+		C1_HNI_PML_CFG_LLR_CF_ETYPE__CTL_FRAME_ETHERTYPE))
+#define SBL_PML_CFG_LLR_CF_SMAC_DFLT                 \
+	(SBL_PML_CFG_LLR_CF_SMAC_CTL_FRAME_SMAC_SET( \
+		C_HNI_PML_CFG_LLR_CF_SMAC__CTL_FRAME_SMAC))
+#define SBL_PML_CFG_LLR_DFLT                                     \
+	(SBL_PML_CFG_LLR_PREAMBLE_SEQ_CHECK_SET(                 \
+		 C1_HNI_PML_CFG_LLR__PREAMBLE_SEQ_CHECK) |       \
+	 SBL_PML_CFG_LLR_ACK_NACK_ERR_CHECK_SET(                 \
+		 C1_HNI_PML_CFG_LLR__ACK_NACK_ERR_CHECK) |       \
+	 SBL_PML_CFG_LLR_FILTER_LOSSLESS_WHEN_OFF_SET(           \
+		 C1_HNI_PML_CFG_LLR__FILTER_LOSSLESS_WHEN_OFF) | \
+	 SBL_PML_CFG_LLR_FILTER_CTL_FRAMES_SET(                  \
+		 C1_HNI_PML_CFG_LLR__FILTER_CTL_FRAMES) |        \
+	 SBL_PML_CFG_LLR_SIZE_SET(C1_HNI_PML_CFG_LLR__SIZE) |    \
+	 SBL_PML_CFG_LLR_ENABLE_LOOP_TIMING_SET(                 \
+		 C1_HNI_PML_CFG_LLR__ENABLE_LOOP_TIMING) |       \
+	 SBL_PML_CFG_LLR_LINK_DOWN_BEHAVIOR_SET(                 \
+		 C1_HNI_PML_CFG_LLR__LINK_DOWN_BEHAVIOR) |       \
+	 SBL_PML_CFG_LLR_MAC_IF_CREDITS_SET(                     \
+		 C1_HNI_PML_CFG_LLR__MAC_IF_CREDITS) |           \
+	 SBL_PML_CFG_LLR_LLR_MODE_SET(C1_HNI_PML_CFG_LLR__LLR_MODE))
+#define SBL_PML_CFG_LLR_SM_DFLT                            \
+	(SBL_PML_CFG_LLR_SM_RETRY_THRESHOLD_SET(           \
+		 C1_HNI_PML_CFG_LLR_SM__RETRY_THRESHOLD) | \
+	 SBL_PML_CFG_LLR_SM_ALLOW_RE_INIT_SET(             \
+		 C1_HNI_PML_CFG_LLR_SM__ALLOW_RE_INIT) |   \
+	 SBL_PML_CFG_LLR_SM_REPLAY_CT_MAX_SET(             \
+		 C1_HNI_PML_CFG_LLR_SM__REPLAY_CT_MAX) |   \
+	 SBL_PML_CFG_LLR_SM_REPLAY_TIMER_MAX_SET(          \
+		 C1_HNI_PML_CFG_LLR_SM__REPLAY_TIMER_MAX))
+#define SBL_PML_CFG_LLR_TIMEOUTS_DFLT                               \
+	(SBL_PML_CFG_LLR_TIMEOUTS_DATA_AGE_TIMER_MAX_SET(           \
+		 C1_HNI_PML_CFG_LLR_TIMEOUTS__DATA_AGE_TIMER_MAX) | \
+	 SBL_PML_CFG_LLR_TIMEOUTS_PCS_LINK_DN_TIMER_MAX_SET(        \
+		 C1_HNI_PML_CFG_LLR_TIMEOUTS__PCS_LINK_DN_TIMER_MAX))
+#define SBL_PML_CFG_PCS_AMS_DFLT                                        \
+	(SBL_PML_CFG_PCS_AMS_USE_PROGRAMMABLE_AMS_SET(                  \
+		 C1_HNI_PML_CFG_PCS_AMS__USE_PROGRAMMABLE_AMS) |        \
+	 SBL_PML_CFG_PCS_AMS_USE_PROGRAMMABLE_AM_SPACING_SET(           \
+		 C1_HNI_PML_CFG_PCS_AMS__USE_PROGRAMMABLE_AM_SPACING) | \
+	 SBL_PML_CFG_PCS_AMS_RAM_SPACING_SET(                           \
+		 C1_HNI_PML_CFG_PCS_AMS__RAM_SPACING) |                 \
+	 SBL_PML_CFG_PCS_AMS_AM_SPACING_SET(                            \
+		 C1_HNI_PML_CFG_PCS_AMS__AM_SPACING))
+#define SBL_PML_CFG_PCS_AUTONEG_BASE_PAGE_DFLT            \
+	(SBL_PML_CFG_PCS_AUTONEG_BASE_PAGE_BASE_PAGE_SET( \
+		C1_HNI_PML_CFG_PCS_AUTONEG_BASE_PAGE__BASE_PAGE))
+#define SBL_PML_CFG_PCS_AUTONEG_DFLT                    \
+	(SBL_PML_CFG_PCS_AUTONEG_RX_LANE_SET(           \
+		 C1_HNI_PML_CFG_PCS_AUTONEG__RX_LANE) | \
+	 SBL_PML_CFG_PCS_AUTONEG_TX_LANE_SET(           \
+		 C1_HNI_PML_CFG_PCS_AUTONEG__TX_LANE) | \
+	 SBL_PML_CFG_PCS_AUTONEG_RESET_SET(             \
+		 C1_HNI_PML_CFG_PCS_AUTONEG__RESET) |   \
+	 SBL_PML_CFG_PCS_AUTONEG_RESTART_SET(           \
+		 C1_HNI_PML_CFG_PCS_AUTONEG__RESTART) | \
+	 SBL_PML_CFG_PCS_AUTONEG_NEXT_PAGE_LOADED_SET(  \
+		 C1_HNI_PML_CFG_PCS_AUTONEG__NEXT_PAGE_LOADED))
+#define SBL_PML_CFG_PCS_AUTONEG_NEXT_PAGE_DFLT            \
+	(SBL_PML_CFG_PCS_AUTONEG_NEXT_PAGE_NEXT_PAGE_SET( \
+		C1_HNI_PML_CFG_PCS_AUTONEG_NEXT_PAGE__NEXT_PAGE))
+#define SBL_PML_CFG_PCS_AUTONEG_TIMERS_DFLT                                        \
+	(SBL_PML_CFG_PCS_AUTONEG_TIMERS_LINK_FAIL_INHIBIT_TIMER_MAX_SET(           \
+		 C1_HNI_PML_CFG_PCS_AUTONEG_TIMERS__LINK_FAIL_INHIBIT_TIMER_MAX) | \
+	 SBL_PML_CFG_PCS_AUTONEG_TIMERS_BREAK_LINK_TIMER_MAX_SET(                  \
+		 C1_HNI_PML_CFG_PCS_AUTONEG_TIMERS__BREAK_LINK_TIMER_MAX))
+#define SBL_PML_CFG_PCS_DFLT                                          \
+	(SBL_PML_CFG_PCS_TIMESTAMP_SHIFT_SET(                         \
+		 C1_HNI_PML_CFG_PCS__TIMESTAMP_SHIFT) |               \
+	 SBL_PML_CFG_PCS_LL_FEC_SET(C1_HNI_PML_CFG_PCS__LL_FEC) |     \
+	 SBL_PML_CFG_PCS_ENABLE_AUTO_LANE_DEGRADE_SET(                \
+		 C1_HNI_PML_CFG_PCS__ENABLE_AUTO_LANE_DEGRADE) |      \
+	 SBL_PML_CFG_PCS_PCS_MODE_SET(C1_HNI_PML_CFG_PCS__PCS_MODE) | \
+	 SBL_PML_CFG_PCS_ENABLE_AUTO_NEG_SET(                         \
+		 C1_HNI_PML_CFG_PCS__ENABLE_AUTO_NEG) |               \
+	 SBL_PML_CFG_PCS_PCS_ENABLE_SET(C1_HNI_PML_CFG_PCS__PCS_ENABLE))
+#define SBL_PML_CFG_RX_MAC_DFLT                                \
+	(SBL_PML_CFG_RX_MAC_FILTER_ILLEGAL_SIZE_SET(           \
+		 C1_HNI_PML_CFG_RX_MAC__FILTER_ILLEGAL_SIZE) | \
+	 SBL_PML_CFG_RX_MAC_SHORT_PREAMBLE_SET(                \
+		 C1_HNI_PML_CFG_RX_MAC__SHORT_PREAMBLE) |      \
+	 SBL_PML_CFG_RX_MAC_MAC_OPERATIONAL_SET(               \
+		 C1_HNI_PML_CFG_RX_MAC__MAC_OPERATIONAL))
+#define SBL_PML_CFG_RX_PCS_DFLT                                           \
+	(SBL_PML_CFG_RX_PCS_ENABLE_RX_SM_SET(                             \
+		 C1_HNI_PML_CFG_RX_PCS__ENABLE_RX_SM) |                   \
+	 SBL_PML_CFG_RX_PCS_ALLOW_AUTO_DEGRADE_SET(                       \
+		 C1_HNI_PML_CFG_RX_PCS__ALLOW_AUTO_DEGRADE) |             \
+	 SBL_PML_CFG_RX_PCS_LP_HEALTH_BAD_SENSITIVITY_SET(                \
+		 C1_HNI_PML_CFG_RX_PCS__LP_HEALTH_BAD_SENSITIVITY) |      \
+	 SBL_PML_CFG_RX_PCS_HEALTH_BAD_SENSITIVITY_SET(                   \
+		 C1_HNI_PML_CFG_RX_PCS__HEALTH_BAD_SENSITIVITY) |         \
+	 SBL_PML_CFG_RX_PCS_ENABLE_CTL_OS_SET(                            \
+		 C1_HNI_PML_CFG_RX_PCS__ENABLE_CTL_OS) |                  \
+	 SBL_PML_CFG_RX_PCS_RESTART_LOCK_ON_BAD_CWS_SET(                  \
+		 C1_HNI_PML_CFG_RX_PCS__RESTART_LOCK_ON_BAD_CWS) |        \
+	 SBL_PML_CFG_RX_PCS_RESTART_LOCK_ON_BAD_AMS_SET(                  \
+		 C1_HNI_PML_CFG_RX_PCS__RESTART_LOCK_ON_BAD_AMS) |        \
+	 SBL_PML_CFG_RX_PCS_ENABLE_LOCK_SET(                              \
+		 C1_HNI_PML_CFG_RX_PCS__ENABLE_LOCK) |                    \
+	 SBL_PML_CFG_RX_PCS_RS_MODE_SET(C1_HNI_PML_CFG_RX_PCS__RS_MODE) | \
+	 SBL_PML_CFG_RX_PCS_ACTIVE_LANES_SET(                             \
+		 C1_HNI_PML_CFG_RX_PCS__ACTIVE_LANES))
+#define SBL_PML_CFG_SERDES_CORE_INTERRUPT_DFLT                                         \
+	(SBL_PML_CFG_SERDES_CORE_INTERRUPT_CAPTURE_INTERRUPT_DATA_DELAY_SET(           \
+		 C1_HNI_PML_CFG_SERDES_CORE_INTERRUPT__CAPTURE_INTERRUPT_DATA_DELAY) | \
+	 SBL_PML_CFG_SERDES_CORE_INTERRUPT_CLEAR_INTERRUPT_DELAY_SET(                  \
+		 C1_HNI_PML_CFG_SERDES_CORE_INTERRUPT__CLEAR_INTERRUPT_DELAY) |        \
+	 SBL_PML_CFG_SERDES_CORE_INTERRUPT_SET_INTERRUPT_DELAY_SET(                    \
+		 C1_HNI_PML_CFG_SERDES_CORE_INTERRUPT__SET_INTERRUPT_DELAY))
+#define SBL_PML_CFG_TX_MAC_DFLT                                             \
+	(SBL_PML_CFG_TX_MAC_PORTALS_PROTOCOL_SET(                           \
+		 C1_HNI_PML_CFG_TX_MAC__PORTALS_PROTOCOL) |                 \
+	 SBL_PML_CFG_TX_MAC_ANY_FRAME_MAX_SOF_1_SET(                        \
+		 C1_HNI_PML_CFG_TX_MAC__ANY_FRAME_MAX_SOF_1) |              \
+	 SBL_PML_CFG_TX_MAC_ANY_FRAME_SOF_WINDOW_1_SET(                     \
+		 C1_HNI_PML_CFG_TX_MAC__ANY_FRAME_SOF_WINDOW_1) |           \
+	 SBL_PML_CFG_TX_MAC_ANY_FRAME_MAX_SOF_0_SET(                        \
+		 C1_HNI_PML_CFG_TX_MAC__ANY_FRAME_MAX_SOF_0) |              \
+	 SBL_PML_CFG_TX_MAC_ANY_FRAME_SOF_WINDOW_0_SET(                     \
+		 C1_HNI_PML_CFG_TX_MAC__ANY_FRAME_SOF_WINDOW_0) |           \
+	 SBL_PML_CFG_TX_MAC_NON_PORTALS_MAX_SOF_SET(                        \
+		 C1_HNI_PML_CFG_TX_MAC__NON_PORTALS_MAX_SOF) |              \
+	 SBL_PML_CFG_TX_MAC_NON_PORTALS_SOF_WINDOW_SET(                     \
+		 C1_HNI_PML_CFG_TX_MAC__NON_PORTALS_SOF_WINDOW) |           \
+	 SBL_PML_CFG_TX_MAC_IEEE_IFG_ADJUSTMENT_SET(                        \
+		 C1_HNI_PML_CFG_TX_MAC__IEEE_IFG_ADJUSTMENT) |              \
+	 SBL_PML_CFG_TX_MAC_VS_VERSION_SET(                                 \
+		 C1_HNI_PML_CFG_TX_MAC__VS_VERSION) |                       \
+	 SBL_PML_CFG_TX_MAC_IFG_MODE_SET(C1_HNI_PML_CFG_TX_MAC__IFG_MODE) | \
+	 SBL_PML_CFG_TX_MAC_PCS_CREDITS_SET(                                \
+		 C1_HNI_PML_CFG_TX_MAC__PCS_CREDITS) |                      \
+	 SBL_PML_CFG_TX_MAC_SHORT_PREAMBLE_SET(                             \
+		 C1_HNI_PML_CFG_TX_MAC__SHORT_PREAMBLE) |                   \
+	 SBL_PML_CFG_TX_MAC_MAC_OPERATIONAL_SET(                            \
+		 C1_HNI_PML_CFG_TX_MAC__MAC_OPERATIONAL))
+#define SBL_PML_CFG_TX_PCS_DFLT                               \
+	(SBL_PML_CFG_TX_PCS_CDC_READY_LEVEL_SET(              \
+		 C1_HNI_PML_CFG_TX_PCS__CDC_READY_LEVEL) |    \
+	 SBL_PML_CFG_TX_PCS_GEARBOX_CREDITS_SET(              \
+		 C1_HNI_PML_CFG_TX_PCS__GEARBOX_CREDITS) |    \
+	 SBL_PML_CFG_TX_PCS_ALLOW_AUTO_DEGRADE_SET(           \
+		 C1_HNI_PML_CFG_TX_PCS__ALLOW_AUTO_DEGRADE) | \
+	 SBL_PML_CFG_TX_PCS_ENABLE_CTL_OS_SET(                \
+		 C1_HNI_PML_CFG_TX_PCS__ENABLE_CTL_OS) |      \
+	 SBL_PML_CFG_TX_PCS_LANE_3_SOURCE_SET(                \
+		 C1_HNI_PML_CFG_TX_PCS__LANE_3_SOURCE) |      \
+	 SBL_PML_CFG_TX_PCS_LANE_2_SOURCE_SET(                \
+		 C1_HNI_PML_CFG_TX_PCS__LANE_2_SOURCE) |      \
+	 SBL_PML_CFG_TX_PCS_LANE_1_SOURCE_SET(                \
+		 C1_HNI_PML_CFG_TX_PCS__LANE_1_SOURCE) |      \
+	 SBL_PML_CFG_TX_PCS_LANE_0_SOURCE_SET(                \
+		 C1_HNI_PML_CFG_TX_PCS__LANE_0_SOURCE))
+#define SBL_PML_DBG_PCS_DFLT                                   \
+	(SBL_PML_DBG_PCS_PPM_TEST_MODE_SET(                    \
+		 C1_HNI_PML_DBG_PCS__PPM_TEST_MODE) |          \
+	 SBL_PML_DBG_PCS_FORCE_TX_DATA_RF_SET(                 \
+		 C1_HNI_PML_DBG_PCS__FORCE_TX_DATA_RF) |       \
+	 SBL_PML_DBG_PCS_FORCE_TX_DATA_SET(                    \
+		 C1_HNI_PML_DBG_PCS__FORCE_TX_DATA) |          \
+	 SBL_PML_DBG_PCS_ENABLE_IDLE_CHECK_SET(                \
+		 C1_HNI_PML_DBG_PCS__ENABLE_IDLE_CHECK) |      \
+	 SBL_PML_DBG_PCS_FORCE_BAD_BIP_SET(                    \
+		 C1_HNI_PML_DBG_PCS__FORCE_BAD_BIP) |          \
+	 SBL_PML_DBG_PCS_ENABLE_RAPID_ALIGNMENT_SET(           \
+		 C1_HNI_PML_DBG_PCS__ENABLE_RAPID_ALIGNMENT) | \
+	 SBL_PML_DBG_PCS_RX_DESCRAMBLER_EN_SET(                \
+		 C1_HNI_PML_DBG_PCS__RX_DESCRAMBLER_EN) |      \
+	 SBL_PML_DBG_PCS_TX_SCRAMBLER_EN_SET(                  \
+		 C1_HNI_PML_DBG_PCS__TX_SCRAMBLER_EN))
+
+/* SET defines */
+#define SBL_PML_CFG_LLR_CAPACITY_MAX_DATA_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_llr_capacity, max_data)
+#define SBL_PML_CFG_LLR_CAPACITY_MAX_SEQ_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_llr_capacity, max_seq)
+#define SBL_PML_CFG_PCS_AUTONEG_NEXT_PAGE_LOADED_SET(a) \
+	C_SET(a, c_hni_pml_cfg_pcs_autoneg, next_page_loaded)
+#define SBL_PML_CFG_PCS_AUTONEG_RESET_SET(a) \
+	C_SET(a, c_hni_pml_cfg_pcs_autoneg, reset)
+#define SBL_PML_CFG_PCS_AUTONEG_RESTART_SET(a) \
+	C_SET(a, c_hni_pml_cfg_pcs_autoneg, restart)
+#define SBL_PML_CFG_PCS_AUTONEG_RX_LANE_SET(a) \
+	C_SET(a, c_hni_pml_cfg_pcs_autoneg, rx_lane)
+#define SBL_PML_CFG_PCS_AUTONEG_TX_LANE_SET(a) \
+	C_SET(a, c_hni_pml_cfg_pcs_autoneg, tx_lane)
+#define SBL_PML_CFG_RX_PCS_AMS_UM_MATCH_MASK_SET(a) \
+	C_SET(a, c_hni_pml_cfg_rx_pcs_ams, um_match_mask)
+#define SBL_PML_CFG_RX_PCS_AMS_CM_MATCH_MASK_SET(a) \
+	C_SET(a, c_hni_pml_cfg_rx_pcs_ams, cm_match_mask)
+#define SBL_PML_CFG_SERDES_CORE_INTERRUPT_CAPTURE_INTERRUPT_DATA_DELAY_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_serdes_core_interrupt,                        \
+	      capture_interrupt_data_delay)
+#define SBL_PML_CFG_SERDES_CORE_INTERRUPT_CLEAR_INTERRUPT_DELAY_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_serdes_core_interrupt, clear_interrupt_delay)
+#define SBL_PML_CFG_SERDES_CORE_INTERRUPT_SET_INTERRUPT_DELAY_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_serdes_core_interrupt, set_interrupt_delay)
+#define SBL_PML_ERR_FLG_AUTONEG_COMPLETE_SET(a) \
+	C_SET(a, c1_hni_pml_err_flg, autoneg_complete)
+#define SBL_PML_ERR_FLG_AUTONEG_PAGE_RECEIVED_SET(a) \
+	C_SET(a, c1_hni_pml_err_flg, autoneg_page_received)
+#define SBL_PML_ERR_FLG_LLR_REPLAY_AT_MAX_SET(a) \
+	C_SET(a, c1_hni_pml_err_flg, llr_replay_at_max)
+#define SBL_PML_ERR_FLG_MAC_RX_DP_ERR_SET(a) \
+	C_SET(a, c1_hni_pml_err_flg, mac_rx_dp_err)
+#define SBL_PML_ERR_FLG_MAC_TX_DP_ERR_SET(a) \
+	C_SET(a, c1_hni_pml_err_flg, mac_tx_dp_err)
+#define SBL_PML_ERR_FLG_PCS_HI_SER_SET(a) \
+	C_SET(a, c1_hni_pml_err_flg, pcs_hi_ser)
+#define SBL_PML_ERR_FLG_PCS_LINK_DOWN_SET(a) \
+	C_SET(a, c1_hni_pml_err_flg, pcs_link_down)
+#define SBL_PML_ERR_FLG_PCS_TX_DEGRADE_SET(a) \
+	C_SET(a, c1_hni_pml_err_flg, pcs_tx_degrade)
+#define SBL_PML_ERR_FLG_PCS_RX_DEGRADE_SET(a) \
+	C_SET(a, c1_hni_pml_err_flg, pcs_rx_degrade)
+#define SBL_PML_ERR_FLG_PCS_TX_DEGRADE_FAILURE_SET(a) \
+	C_SET(a, c1_hni_pml_err_flg, pcs_tx_degrade_failure)
+#define SBL_PML_ERR_FLG_PCS_RX_DEGRADE_FAILURE_SET(a) \
+	C_SET(a, c1_hni_pml_err_flg, pcs_rx_degrade_failure)
+#define SBL_PML_SERDES_CORE_INTERRUPT_SERDES_SEL_SET(a) \
+	C_SET(a, c1_hni_pml_serdes_core_interrupt, serdes_sel)
+#define SBL_PML_SERDES_CORE_INTERRUPT_DO_CORE_INTERRUPT_SET(a) \
+	C_SET(a, c1_hni_pml_serdes_core_interrupt, do_core_interrupt)
+#define SBL_PML_SERDES_CORE_INTERRUPT_CORE_INTERRUPT_CODE_SET(a) \
+	C_SET(a, c1_hni_pml_serdes_core_interrupt, core_interrupt_code)
+#define SBL_PML_SERDES_CORE_INTERRUPT_CORE_INTERRUPT_DATA_SET(a) \
+	C_SET(a, c1_hni_pml_serdes_core_interrupt, core_interrupt_data)
+
+#define SBL_PML_CFG_LLR_CAPACITY_SET(MAX_DATA, MAX_SEQ)    \
+	(SBL_PML_CFG_LLR_CAPACITY_MAX_DATA_SET(MAX_DATA) | \
+	 SBL_PML_CFG_LLR_CAPACITY_MAX_SEQ_SET(MAX_SEQ))
+#define SBL_PML_CFG_RX_PCS_AMS_SET(UM_MATCH_MASK, CM_MATCH_MASK)   \
+	(SBL_PML_CFG_RX_PCS_AMS_UM_MATCH_MASK_SET(UM_MATCH_MASK) | \
+	 SBL_PML_CFG_RX_PCS_AMS_CM_MATCH_MASK_SET(CM_MATCH_MASK))
+#define SBL_PML_SERDES_CORE_INTERRUPT_SET(SERDES_SEL, DO_CORE_INTERRUPT, \
+					  CORE_INTERRUPT_CODE,           \
+					  CORE_INTERRUPT_DATA)           \
+	(SBL_PML_SERDES_CORE_INTERRUPT_SERDES_SEL_SET(SERDES_SEL) |      \
+	 SBL_PML_SERDES_CORE_INTERRUPT_DO_CORE_INTERRUPT_SET(            \
+		 DO_CORE_INTERRUPT) |                                    \
+	 SBL_PML_SERDES_CORE_INTERRUPT_CORE_INTERRUPT_CODE_SET(          \
+		 CORE_INTERRUPT_CODE) |                                  \
+	 SBL_PML_SERDES_CORE_INTERRUPT_CORE_INTERRUPT_DATA_SET(          \
+		 CORE_INTERRUPT_DATA))
+
+#define SBL_PML_CFG_LLR_CF_ETYPE_CTL_FRAME_ETHERTYPE_SET(a) \
+	C_SET(a, c_hni_pml_cfg_llr_cf_etype, ctl_frame_ethertype)
+#define SBL_PML_CFG_LLR_CF_SMAC_CTL_FRAME_SMAC_SET(a) \
+	C_SET(a, c_hni_pml_cfg_llr_cf_smac, ctl_frame_smac)
+#define SBL_PML_CFG_LLR_PREAMBLE_SEQ_CHECK_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_llr, preamble_seq_check)
+#define SBL_PML_CFG_LLR_ACK_NACK_ERR_CHECK_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_llr, ack_nack_err_check)
+#define SBL_PML_CFG_LLR_FILTER_LOSSLESS_WHEN_OFF_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_llr, filter_lossless_when_off)
+#define SBL_PML_CFG_LLR_FILTER_CTL_FRAMES_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_llr, filter_ctl_frames)
+#define SBL_PML_CFG_LLR_SIZE_SET(a) C_SET(a, c1_hni_pml_cfg_llr, size)
+#define SBL_PML_CFG_LLR_ENABLE_LOOP_TIMING_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_llr, enable_loop_timing)
+#define SBL_PML_CFG_LLR_LINK_DOWN_BEHAVIOR_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_llr, link_down_behavior)
+#define SBL_PML_CFG_LLR_MAC_IF_CREDITS_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_llr, mac_if_credits)
+#define SBL_PML_CFG_LLR_LLR_MODE_SET(a) C_SET(a, c1_hni_pml_cfg_llr, llr_mode)
+#define SBL_PML_CFG_LLR_SM_RETRY_THRESHOLD_SET(a) \
+	C_SET(a, c_hni_pml_cfg_llr_sm, retry_threshold)
+#define SBL_PML_CFG_LLR_SM_ALLOW_RE_INIT_SET(a) \
+	C_SET(a, c_hni_pml_cfg_llr_sm, allow_re_init)
+#define SBL_PML_CFG_LLR_SM_REPLAY_CT_MAX_SET(a) \
+	C_SET(a, c_hni_pml_cfg_llr_sm, replay_ct_max)
+#define SBL_PML_CFG_LLR_SM_REPLAY_TIMER_MAX_SET(a) \
+	C_SET(a, c_hni_pml_cfg_llr_sm, replay_timer_max)
+#define SBL_PML_CFG_LLR_TIMEOUTS_DATA_AGE_TIMER_MAX_SET(a) \
+	C_SET(a, c_hni_pml_cfg_llr_timeouts, data_age_timer_max)
+#define SBL_PML_CFG_LLR_TIMEOUTS_PCS_LINK_DN_TIMER_MAX_SET(a) \
+	C_SET(a, c_hni_pml_cfg_llr_timeouts, pcs_link_dn_timer_max)
+#define SBL_PML_CFG_PCS_AMS_USE_PROGRAMMABLE_AMS_SET(a) \
+	C_SET(a, c_hni_pml_cfg_pcs_ams, use_programmable_ams)
+#define SBL_PML_CFG_PCS_AMS_USE_PROGRAMMABLE_AM_SPACING_SET(a) \
+	C_SET(a, c_hni_pml_cfg_pcs_ams, use_programmable_am_spacing)
+#define SBL_PML_CFG_PCS_AMS_RAM_SPACING_SET(a) \
+	C_SET(a, c_hni_pml_cfg_pcs_ams, ram_spacing)
+#define SBL_PML_CFG_PCS_AMS_AM_SPACING_SET(a) \
+	C_SET(a, c_hni_pml_cfg_pcs_ams, am_spacing)
+#define SBL_PML_CFG_PCS_AUTONEG_BASE_PAGE_BASE_PAGE_SET(a) \
+	C_SET(a, c_hni_pml_cfg_pcs_autoneg_base_page, base_page)
+#define SBL_PML_CFG_PCS_AUTONEG_NEXT_PAGE_NEXT_PAGE_SET(a) \
+	C_SET(a, c_hni_pml_cfg_pcs_autoneg_next_page, next_page)
+#define SBL_PML_CFG_PCS_AUTONEG_TIMERS_LINK_FAIL_INHIBIT_TIMER_MAX_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_pcs_autoneg_timers, link_fail_inhibit_timer_max)
+#define SBL_PML_CFG_PCS_AUTONEG_TIMERS_BREAK_LINK_TIMER_MAX_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_pcs_autoneg_timers, break_link_timer_max)
+#define SBL_PML_CFG_PCS_TIMESTAMP_SHIFT_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_pcs, timestamp_shift)
+#define SBL_PML_CFG_PCS_LL_FEC_SET(a) C_SET(a, c1_hni_pml_cfg_pcs, ll_fec)
+#define SBL_PML_CFG_PCS_ENABLE_AUTO_LANE_DEGRADE_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_pcs, enable_auto_lane_degrade)
+#define SBL_PML_CFG_PCS_PCS_MODE_SET(a) C_SET(a, c1_hni_pml_cfg_pcs, pcs_mode)
+#define SBL_PML_CFG_PCS_ENABLE_AUTO_NEG_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_pcs, enable_auto_neg)
+#define SBL_PML_CFG_PCS_PCS_ENABLE_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_pcs, pcs_enable)
+#define SBL_PML_CFG_RX_MAC_FILTER_ILLEGAL_SIZE_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_rx_mac, filter_illegal_size)
+#define SBL_PML_CFG_RX_MAC_SHORT_PREAMBLE_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_rx_mac, short_preamble)
+#define SBL_PML_CFG_RX_MAC_MAC_OPERATIONAL_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_rx_mac, mac_operational)
+#define SBL_PML_CFG_RX_PCS_ENABLE_RX_SM_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_rx_pcs, enable_rx_sm)
+#define SBL_PML_CFG_RX_PCS_ALLOW_AUTO_DEGRADE_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_rx_pcs, allow_auto_degrade)
+#define SBL_PML_CFG_RX_PCS_LP_HEALTH_BAD_SENSITIVITY_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_rx_pcs, lp_health_bad_sensitivity)
+#define SBL_PML_CFG_RX_PCS_HEALTH_BAD_SENSITIVITY_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_rx_pcs, health_bad_sensitivity)
+#define SBL_PML_CFG_RX_PCS_ENABLE_CTL_OS_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_rx_pcs, enable_ctl_os)
+#define SBL_PML_CFG_RX_PCS_RESTART_LOCK_ON_BAD_CWS_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_rx_pcs, restart_lock_on_bad_cws)
+#define SBL_PML_CFG_RX_PCS_RESTART_LOCK_ON_BAD_AMS_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_rx_pcs, restart_lock_on_bad_ams)
+#define SBL_PML_CFG_RX_PCS_ENABLE_LOCK_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_rx_pcs, enable_lock)
+#define SBL_PML_CFG_RX_PCS_RS_MODE_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_rx_pcs, rs_mode)
+#define SBL_PML_CFG_RX_PCS_ACTIVE_LANES_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_rx_pcs, active_lanes)
+#define SBL_PML_CFG_SERDES_CORE_INTERRUPT_CAPTURE_INTERRUPT_DATA_DELAY_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_serdes_core_interrupt,                        \
+	      capture_interrupt_data_delay)
+#define SBL_PML_CFG_SERDES_CORE_INTERRUPT_CLEAR_INTERRUPT_DELAY_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_serdes_core_interrupt, clear_interrupt_delay)
+#define SBL_PML_CFG_SERDES_CORE_INTERRUPT_SET_INTERRUPT_DELAY_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_serdes_core_interrupt, set_interrupt_delay)
+#define SBL_PML_CFG_TX_MAC_PORTALS_PROTOCOL_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_tx_mac, portals_protocol)
+#define SBL_PML_CFG_TX_MAC_ANY_FRAME_MAX_SOF_1_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_tx_mac, any_frame_max_sof_1)
+#define SBL_PML_CFG_TX_MAC_ANY_FRAME_SOF_WINDOW_1_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_tx_mac, any_frame_sof_window_1)
+#define SBL_PML_CFG_TX_MAC_ANY_FRAME_MAX_SOF_0_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_tx_mac, any_frame_max_sof_0)
+#define SBL_PML_CFG_TX_MAC_ANY_FRAME_SOF_WINDOW_0_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_tx_mac, any_frame_sof_window_0)
+#define SBL_PML_CFG_TX_MAC_NON_PORTALS_MAX_SOF_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_tx_mac, non_portals_max_sof)
+#define SBL_PML_CFG_TX_MAC_NON_PORTALS_SOF_WINDOW_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_tx_mac, non_portals_sof_window)
+#define SBL_PML_CFG_TX_MAC_VS_VERSION_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_tx_mac, vs_version)
+#define SBL_PML_CFG_TX_MAC_IEEE_IFG_ADJUSTMENT_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_tx_mac, ieee_ifg_adjustment)
+#define SBL_PML_CFG_TX_MAC_IFG_MODE_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_tx_mac, ifg_mode)
+#define SBL_PML_CFG_TX_MAC_PCS_CREDITS_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_tx_mac, pcs_credits)
+#define SBL_PML_CFG_TX_MAC_SHORT_PREAMBLE_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_tx_mac, short_preamble)
+#define SBL_PML_CFG_TX_MAC_MAC_OPERATIONAL_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_tx_mac, mac_operational)
+#define SBL_PML_CFG_TX_PCS_CDC_READY_LEVEL_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_tx_pcs, cdc_ready_level)
+#define SBL_PML_CFG_TX_PCS_GEARBOX_CREDITS_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_tx_pcs, gearbox_credits)
+#define SBL_PML_CFG_TX_PCS_ALLOW_AUTO_DEGRADE_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_tx_pcs, allow_auto_degrade)
+#define SBL_PML_CFG_TX_PCS_ENABLE_CTL_OS_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_tx_pcs, enable_ctl_os)
+#define SBL_PML_CFG_TX_PCS_LANE_3_SOURCE_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_tx_pcs, lane_3_source)
+#define SBL_PML_CFG_TX_PCS_LANE_2_SOURCE_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_tx_pcs, lane_2_source)
+#define SBL_PML_CFG_TX_PCS_LANE_1_SOURCE_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_tx_pcs, lane_1_source)
+#define SBL_PML_CFG_TX_PCS_LANE_0_SOURCE_SET(a) \
+	C_SET(a, c1_hni_pml_cfg_tx_pcs, lane_0_source)
+#define SBL_PML_DBG_PCS_PPM_TEST_MODE_SET(a) \
+	C_SET(a, c1_hni_pml_dbg_pcs, ppm_test_mode)
+#define SBL_PML_DBG_PCS_FORCE_TX_DATA_RF_SET(a) \
+	C_SET(a, c1_hni_pml_dbg_pcs, force_tx_data_rf)
+#define SBL_PML_DBG_PCS_FORCE_TX_DATA_SET(a) \
+	C_SET(a, c1_hni_pml_dbg_pcs, force_tx_data)
+#define SBL_PML_DBG_PCS_ENABLE_IDLE_CHECK_SET(a) \
+	C_SET(a, c1_hni_pml_dbg_pcs, enable_idle_check)
+#define SBL_PML_DBG_PCS_FORCE_BAD_BIP_SET(a) \
+	C_SET(a, c1_hni_pml_dbg_pcs, force_bad_bip)
+#define SBL_PML_DBG_PCS_ENABLE_RAPID_ALIGNMENT_SET(a) \
+	C_SET(a, c1_hni_pml_dbg_pcs, enable_rapid_alignment)
+#define SBL_PML_DBG_PCS_RX_DESCRAMBLER_EN_SET(a) \
+	C_SET(a, c1_hni_pml_dbg_pcs, rx_descrambler_en)
+#define SBL_PML_DBG_PCS_TX_SCRAMBLER_EN_SET(a) \
+	C_SET(a, c1_hni_pml_dbg_pcs, tx_scrambler_en)
+
+/* GET defines */
+#define SBL_PML_CFG_LLR_LINK_DOWN_BEHAVIOR_GET(a) \
+	C_GET(a, c1_hni_pml_cfg_llr, link_down_behavior)
+#define SBL_PML_CFG_LLR_LLR_MODE_GET(a) C_GET(a, c1_hni_pml_cfg_llr, llr_mode)
+#define SBL_PML_CFG_LLR_SM_REPLAY_CT_MAX_GET(a) \
+	C_GET(a, c_hni_pml_cfg_llr_sm, replay_ct_max)
+#define SBL_PML_CFG_PCS_AUTONEG_NEXT_PAGE_LOADED_GET(a) \
+	C_GET(a, c1_hni_pml_cfg_pcs_autoneg, next_page_loaded)
+#define SBL_PML_CFG_PCS_ENABLE_AUTO_NEG_GET(a) \
+	C_GET(a, c1_hni_pml_cfg_pcs, enable_auto_neg)
+#define SBL_PML_CFG_PCS_PCS_ENABLE_GET(a) \
+	C_GET(a, c1_hni_pml_cfg_pcs, pcs_enable)
+#define SBL_PML_CFG_RX_PCS_ENABLE_LOCK_GET(a) \
+	C_GET(a, c1_hni_pml_cfg_rx_pcs, enable_lock)
+#define SBL_PML_ERR_FLG_AUTONEG_COMPLETE_GET(a) \
+	C_GET(a, c1_hni_pml_err_flg, autoneg_complete)
+#define SBL_PML_ERR_FLG_AUTONEG_PAGE_RECEIVED_GET(a) \
+	C_GET(a, c1_hni_pml_err_flg, autoneg_page_received)
+#define SBL_PML_ERR_FLG_LLR_REPLAY_AT_MAX_GET(a) \
+	C_GET(a, c1_hni_pml_err_flg, llr_replay_at_max)
+#define SBL_PML_ERR_FLG_PCS_HI_SER_GET(a) \
+	C_GET(a, c1_hni_pml_err_flg, pcs_hi_ser)
+#define SBL_PML_ERR_FLG_PCS_LINK_DOWN_GET(a) \
+	C_GET(a, c1_hni_pml_err_flg, pcs_link_down)
+#define SBL_PML_ERR_FLG_PCS_TX_DEGRADE_GET(a) \
+	C_GET(a, c1_hni_pml_err_flg, pcs_tx_degrade)
+#define SBL_PML_ERR_FLG_PCS_RX_DEGRADE_GET(a) \
+	C_GET(a, c1_hni_pml_err_flg, pcs_rx_degrade)
+#define SBL_PML_ERR_FLG_PCS_TX_DEGRADE_FAILURE_GET(a) \
+	C_GET(a, c1_hni_pml_err_flg, pcs_tx_degrade_failure)
+#define SBL_PML_ERR_FLG_PCS_RX_DEGRADE_FAILURE_GET(a) \
+	C_GET(a, c1_hni_pml_err_flg, pcs_rx_degrade_failure)
+#define SBL_PML_CFG_PCS_ENABLE_AUTO_LANE_DEGRADE_GET(a) \
+	C_GET(a, c1_hni_pml_cfg_pcs, enable_auto_lane_degrade)
+#define SBL_PML_SERDES_CORE_INTERRUPT_CORE_INTERRUPT_DATA_GET(a) \
+	C_GET(a, c1_hni_pml_serdes_core_interrupt, core_interrupt_data)
+#define SBL_PML_SERDES_CORE_INTERRUPT_DO_CORE_INTERRUPT_GET(a) \
+	C_GET(a, c1_hni_pml_serdes_core_interrupt, do_core_interrupt)
+#define SBL_PML_STS_LLR_LLR_STATE_GET(a) C_GET(a, c_hni_pml_sts_llr, llr_state)
+#define SBL_PML_STS_LLR_LOOP_TIME_LOOP_TIME_GET(a) \
+	C_GET(a, c_hni_pml_sts_llr_loop_time, loop_time)
+#define SBL_PML_STS_LLR_MAX_USAGE_BUFF_SPC_STARVED_GET(a) \
+	C_GET(a, c_hni_pml_sts_llr_max_usage, buffer_space_starved)
+#define SBL_PML_STS_LLR_MAX_USAGE_SEQ_STARVED_GET(a) \
+	C_GET(a, c_hni_pml_sts_llr_max_usage, seq_starved)
+#define SBL_PML_CFG_RX_MAC_MAC_OPERATIONAL_GET(a) \
+	C_GET(a, c1_hni_pml_cfg_rx_mac, mac_operational)
+#define SBL_PML_CFG_TX_MAC_IEEE_IFG_ADJUSTMENT_GET(a) \
+	C_GET(a, c1_hni_pml_cfg_tx_mac, ieee_ifg_adjustment)
+#define SBL_PML_CFG_TX_MAC_IFG_MODE_GET(a) \
+	C_GET(a, c1_hni_pml_cfg_tx_mac, ifg_mode)
+#define SBL_PML_CFG_TX_MAC_MAC_OPERATIONAL_GET(a) \
+	C_GET(a, c1_hni_pml_cfg_tx_mac, mac_operational)
+#define SBL_PML_STS_PCS_AUTONEG_BASE_PAGE_BASE_PAGE_GET(a) \
+	C_GET(a, c_hni_pml_sts_pcs_autoneg_base_page, base_page)
+#define SBL_PML_STS_PCS_AUTONEG_BASE_PAGE_LP_BASE_PAGE_GET(a) \
+	C_GET(a, c_hni_pml_sts_pcs_autoneg_base_page, lp_base_page)
+#define SBL_PML_STS_PCS_AUTONEG_BASE_PAGE_LP_ABILITY_GET(a) \
+	C_GET(a, c_hni_pml_sts_pcs_autoneg_base_page, lp_ability)
+#define SBL_PML_STS_PCS_AUTONEG_BASE_PAGE_STATE_GET(a) \
+	C_GET(a, c_hni_pml_sts_pcs_autoneg_base_page, state)
+#define SBL_PML_STS_PCS_AUTONEG_BASE_PAGE_COMPLETE_GET(a) \
+	C_GET(a, c_hni_pml_sts_pcs_autoneg_base_page, complete)
+#define SBL_PML_STS_PCS_AUTONEG_BASE_PAGE_PAGE_RECEIVED_GET(a) \
+	C_GET(a, c_hni_pml_sts_pcs_autoneg_base_page, page_received)
+#define SBL_PML_STS_PCS_AUTONEG_NEXT_PAGE_BASE_PAGE_GET(a) \
+	C_GET(a, c_hni_pml_sts_pcs_autoneg_next_page, base_page)
+#define SBL_PML_STS_PCS_AUTONEG_NEXT_PAGE_LP_NEXT_PAGE_GET(a) \
+	C_GET(a, c_hni_pml_sts_pcs_autoneg_next_page, lp_next_page)
+#define SBL_PML_STS_PCS_AUTONEG_NEXT_PAGE_LP_ABILITY_GET(a) \
+	C_GET(a, c_hni_pml_sts_pcs_autoneg_next_page, lp_ability)
+#define SBL_PML_STS_PCS_AUTONEG_NEXT_PAGE_STATE_GET(a) \
+	C_GET(a, c_hni_pml_sts_pcs_autoneg_next_page, state)
+#define SBL_PML_STS_PCS_AUTONEG_NEXT_PAGE_COMPLETE_GET(a) \
+	C_GET(a, c_hni_pml_sts_pcs_autoneg_next_page, complete)
+#define SBL_PML_STS_PCS_AUTONEG_NEXT_PAGE_PAGE_RECEIVED_GET(a) \
+	C_GET(a, c_hni_pml_sts_pcs_autoneg_next_page, page_received)
+#define SBL_PML_STS_RX_PCS_ALIGN_STATUS_GET(a) \
+	C_GET(a, c1_hni_pml_sts_rx_pcs, align_status)
+#define SBL_PML_STS_RX_PCS_AM_LOCK_GET(a) \
+	C_GET(a, c1_hni_pml_sts_rx_pcs, am_lock)
+#define SBL_PML_STS_RX_PCS_FAULT_GET(a) C_GET(a, c1_hni_pml_sts_rx_pcs, fault)
+#define SBL_PML_STS_RX_PCS_HI_SER_GET(a) C_GET(a, c1_hni_pml_sts_rx_pcs, hi_ser)
+#define SBL_PML_STS_RX_PCS_LOCAL_FAULT_GET(a) \
+	C_GET(a, c1_hni_pml_sts_rx_pcs, local_fault)
+#define SBL_PML_STS_PCS_LANE_DEGRADE_RX_PLS_AVAILABLE_GET(a) \
+	C_GET(a, c1_hni_pml_sts_pcs_lane_degrade, rx_pls_available)
+#define SBL_PML_STS_PCS_LANE_DEGRADE_LP_PLS_AVAILABLE_GET(a) \
+	C_GET(a, c1_hni_pml_sts_pcs_lane_degrade, lp_pls_available)
+
+/* Other defines */
+#define SBL_PML_AUTONEG_STATE_AUTONEG_OFF 0x0
+#define SBL_PML_AUTONEG_STATE_AUTONEG_ENABLE 0x1
+#define SBL_PML_AUTONEG_STATE_TX_DISABLE 0x2
+#define SBL_PML_AUTONEG_STATE_ABILITY_DETECT 0x3
+#define SBL_PML_AUTONEG_STATE_ACK_DETECT 0x4
+#define SBL_PML_AUTONEG_STATE_COMPLETE_ACK 0x5
+#define SBL_PML_AUTONEG_STATE_NEXT_PAGE_WAIT 0x6
+#define SBL_PML_AUTONEG_STATE_AN_GOOD_CHECK 0x9
+#define SBL_PML_AUTONEG_STATE_AN_GOOD 0xa
+
+/* Cassini 2 macros */
+
+#define SS2_PORT_PML_CFG_SUBPORT_RESET_WARM_RST_FROM_CSR_SET(a) \
+	C_SET(a, ss2_port_pml_cfg_subport_reset, warm_rst_from_csr)
+
+#define SS2_PORT_PML_CFG_GENERAL_CLOCK_PERIOD_PS_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_general, clock_period_ps)
+
+#define SS2_PORT_PML_CFG_LLR_CAPACITY_MAX_DATA_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_llr_capacity, max_data)
+#define SS2_PORT_PML_CFG_LLR_CAPACITY_MAX_SEQ_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_llr_capacity, max_seq)
+#define SS2_PORT_PML_CFG_LLR_SIZE_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_llr, size)
+#define SS2_PORT_PML_CFG_LLR_ACK_NACK_ERR_CHECK_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_llr, ack_nack_err_check)
+#define SS2_PORT_PML_CFG_LLR_PREAMBLE_SEQ_CHECK_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_llr, preamble_seq_check)
+#define SS2_PORT_PML_CFG_LLR_CF_RATES_LOOP_TIMING_PERIOD_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_llr_cf_rates, loop_timing_period)
+#define SS2_PORT_PML_CFG_LLR_CF_SMAC_CTL_FRAME_SMAC_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_llr_cf_smac, ctl_frame_smac)
+#define SS2_PORT_PML_CFG_LLR_CF_ETYPE_CTL_FRAME_ETHERTYPE_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_llr_cf_etype, ctl_frame_ethertype)
+#define SS2_PORT_PML_CFG_LLR_SM_REPLAY_CT_MAX_GET(a) \
+	C_GET(a, ss2_port_pml_cfg_llr_sm, replay_ct_max)
+#define SS2_PORT_PML_CFG_LLR_SM_REPLAY_CT_MAX_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_llr_sm, replay_ct_max)
+#define SS2_PORT_PML_CFG_LLR_SM_REPLAY_TIMER_MAX_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_llr_sm, replay_timer_max)
+#define SS2_PORT_PML_CFG_LLR_SM_RETRY_THRESHOLD_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_llr_sm, retry_threshold)
+#define SS2_PORT_PML_CFG_LLR_SM_ALLOW_RE_INIT_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_llr_sm, allow_re_init)
+#define SS2_PORT_PML_CFG_LLR_SUBPORT_FILTER_LOSSLESS_WHEN_OFF_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_llr_subport, filter_lossless_when_off)
+#define SS2_PORT_PML_CFG_LLR_SUBPORT_MAX_STARVATION_LIMIT_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_llr_subport, max_starvation_limit)
+#define SS2_PORT_PML_CFG_LLR_SUBPORT_LINK_DOWN_BEHAVIOR_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_llr_subport, link_down_behavior)
+#define SS2_PORT_PML_CFG_LLR_SUBPORT_MAC_IF_CREDITS_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_llr_subport, mac_if_credits)
+#define SS2_PORT_PML_CFG_LLR_SUBPORT_FILTER_CTL_FRAMES_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_llr_subport, filter_ctl_frames)
+#define SS2_PORT_PML_CFG_LLR_SUBPORT_ENABLE_LOOP_TIMING_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_llr_subport, enable_loop_timing)
+#define SS2_PORT_PML_CFG_LLR_SUBPORT_LLR_MODE_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_llr_subport, llr_mode)
+#define SS2_PORT_PML_CFG_LLR_TIMEOUTS_DATA_AGE_TIMER_MAX_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_llr_timeouts, data_age_timer_max)
+#define SS2_PORT_PML_CFG_LLR_TIMEOUTS_PCS_LINK_DN_TIMER_MAX_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_llr_timeouts, pcs_link_dn_timer_max)
+
+#define SS2_PORT_PML_CFG_PCS_AUTONEG_RESET_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_pcs_autoneg, reset)
+#define SS2_PORT_PML_CFG_PCS_AUTONEG_RESTART_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_pcs_autoneg, restart)
+#define SS2_PORT_PML_CFG_PCS_AUTONEG_NEXT_PAGE_LOADED_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_pcs_autoneg, next_page_loaded)
+
+#define SS2_PORT_PML_CFG_PCS_ENABLE_AUTO_LANE_DEGRADE_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_pcs, enable_auto_lane_degrade)
+#define SS2_PORT_PML_CFG_PCS_ENABLE_AUTO_LANE_DEGRADE_GET(a) \
+	C_GET(a, ss2_port_pml_cfg_pcs, enable_auto_lane_degrade)
+#define SS2_PORT_PML_CFG_PCS_PCS_MODE_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_pcs, pcs_mode)
+#define SS2_PORT_PML_CFG_PCS_TIMESTAMP_SHIFT_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_pcs, timestamp_shift)
+#define SS2_PORT_PML_CFG_PCS_SUBPORT_PCS_ENABLE_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_pcs_subport, pcs_enable)
+#define SS2_PORT_PML_CFG_PCS_SUBPORT_ENABLE_AUTO_NEG_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_pcs_subport, enable_auto_neg)
+
+#define SS2_PORT_PML_CFG_RX_MAC_FLIT_PACKING_CNT_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_rx_mac, flit_packing_cnt)
+#define SS2_PORT_PML_CFG_RX_MAC_SUBPORT_MAC_OPERATIONAL_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_rx_mac_subport, mac_operational)
+#define SS2_PORT_PML_CFG_RX_MAC_SUBPORT_MAC_OPERATIONAL_GET(a) \
+	C_GET(a, ss2_port_pml_cfg_rx_mac_subport, mac_operational)
+#define SS2_PORT_PML_CFG_RX_MAC_SUBPORT_SHORT_PREAMBLE_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_rx_mac_subport, short_preamble)
+
+#define SS2_PORT_PML_CFG_RX_PCS_SUBPORT_ENABLE_CTL_OS_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_rx_pcs_subport, enable_ctl_os)
+#define SS2_PORT_PML_CFG_RX_PCS_SUBPORT_ENABLE_LOCK_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_rx_pcs_subport, enable_lock)
+#define SS2_PORT_PML_CFG_RX_PCS_SUBPORT_ENABLE_RX_SM_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_rx_pcs_subport, enable_rx_sm)
+#define SS2_PORT_PML_CFG_RX_PCS_SUBPORT_RS_MODE_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_rx_pcs_subport, rs_mode)
+#define SS2_PORT_PML_CFG_RX_PCS_ACTIVE_LANES_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_rx_pcs, active_lanes)
+#define SS2_PORT_PML_CFG_RX_PCS_CW_GAP_544_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_rx_pcs, cw_gap_544)
+#define SS2_PORT_PML_CFG_RX_PCS_RESTART_LOCK_ON_BAD_AMS_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_rx_pcs, restart_lock_on_bad_ams)
+#define SS2_PORT_PML_CFG_RX_PCS_RESTART_LOCK_ON_BAD_CWS_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_rx_pcs, restart_lock_on_bad_cws)
+#define SS2_PORT_PML_CFG_RX_PCS_ALLOW_AUTO_DEGRADE_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_rx_pcs, allow_auto_degrade)
+#define SS2_PORT_PML_CFG_RX_PCS_LANE_0_SOURCE_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_rx_pcs, lane_0_source)
+#define SS2_PORT_PML_CFG_RX_PCS_LANE_1_SOURCE_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_rx_pcs, lane_1_source)
+#define SS2_PORT_PML_CFG_RX_PCS_LANE_2_SOURCE_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_rx_pcs, lane_2_source)
+#define SS2_PORT_PML_CFG_RX_PCS_LANE_3_SOURCE_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_rx_pcs, lane_3_source)
+
+#define SS2_PORT_PML_CFG_TX_MAC_IEEE_IFG_ADJUSTMENT_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_tx_mac, ieee_ifg_adjustment)
+#define SS2_PORT_PML_CFG_TX_MAC_MAC_PAD_IDLE_THRESH_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_tx_mac, mac_pad_idle_thresh)
+#define SS2_PORT_PML_CFG_TX_MAC_IFG_MODE_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_tx_mac, ifg_mode)
+#define SS2_PORT_PML_CFG_TX_MAC_SUBPORT_MAC_OPERATIONAL_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_tx_mac_subport, mac_operational)
+#define SS2_PORT_PML_CFG_TX_MAC_SUBPORT_MAC_OPERATIONAL_GET(a) \
+	C_GET(a, ss2_port_pml_cfg_tx_mac_subport, mac_operational)
+#define SS2_PORT_PML_CFG_TX_MAC_SUBPORT_MAC_CDT_THRESH_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_tx_mac_subport, mac_cdt_thresh)
+#define SS2_PORT_PML_CFG_TX_MAC_SUBPORT_MAC_CDT_INIT_VAL_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_tx_mac_subport, mac_cdt_init_val)
+#define SS2_PORT_PML_CFG_TX_MAC_SUBPORT_PCS_CREDITS_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_tx_mac_subport, pcs_credits)
+#define SS2_PORT_PML_CFG_TX_MAC_SUBPORT_SHORT_PREAMBLE_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_tx_mac_subport, short_preamble)
+
+#define SS2_PORT_PML_CFG_TX_PCS_SUBPORT_ENABLE_CTL_OS_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_tx_pcs_subport, enable_ctl_os)
+#define SS2_PORT_PML_CFG_TX_PCS_CDC_READY_LEVEL_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_tx_pcs, cdc_ready_level)
+#define SS2_PORT_PML_CFG_TX_PCS_EN_PK_BW_LIMITER_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_tx_pcs, en_pk_bw_limiter)
+#define SS2_PORT_PML_CFG_TX_PCS_LANE_0_SOURCE_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_tx_pcs, lane_0_source)
+#define SS2_PORT_PML_CFG_TX_PCS_LANE_1_SOURCE_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_tx_pcs, lane_1_source)
+#define SS2_PORT_PML_CFG_TX_PCS_LANE_2_SOURCE_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_tx_pcs, lane_2_source)
+#define SS2_PORT_PML_CFG_TX_PCS_LANE_3_SOURCE_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_tx_pcs, lane_3_source)
+#define SS2_PORT_PML_CFG_TX_PCS_ALLOW_AUTO_DEGRADE_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_tx_pcs, allow_auto_degrade)
+#define SS2_PORT_PML_CFG_TX_PCS_SUBPORT_GEARBOX_CREDITS_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_tx_pcs_subport, gearbox_credits)
+#define SS2_PORT_PML_CFG_TX_PCS_KEEP_ALL_LANES_ACTIVE_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_tx_pcs, keep_all_lanes_active)
+
+#define SS2_PORT_PML_ERR_INFO_PCS_TX_DP_TX_CDC_UNDERRUN_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_err_info_pcs_tx_dp, tx_cdc_underrun)
+
+#define SS2_PORT_PML_STS_LLR_LOOP_TIME_LOOP_TIME_GET(a) \
+	C_GET(a, ss2_port_pml_sts_llr_loop_time, loop_time)
+#define SS2_PORT_PML_STS_LLR_LLR_STATE_GET(a) \
+	C_GET(a, ss2_port_pml_sts_llr, llr_state)
+
+#define SS2_PORT_PML_STS_RX_PCS_SUBPORT_ALIGN_STATUS_GET(a) \
+	C_GET(a, ss2_port_pml_sts_rx_pcs_subport, align_status)
+#define SS2_PORT_PML_STS_RX_PCS_SUBPORT_FAULT_GET(a) \
+	C_GET(a, ss2_port_pml_sts_rx_pcs_subport, fault)
+#define SS2_PORT_PML_STS_RX_PCS_SUBPORT_LOCAL_FAULT_GET(a) \
+	C_GET(a, ss2_port_pml_sts_rx_pcs_subport, local_fault)
+#define SS2_PORT_PML_STS_RX_PCS_SUBPORT_HI_SER_GET(a) \
+	C_GET(a, ss2_port_pml_sts_rx_pcs_subport, hi_ser)
+
+#define SS2_PORT_PML_STS_PCS_AUTONEG_BASE_PAGE_LP_BASE_PAGE_GET(a) \
+	C_GET(a, ss2_port_pml_sts_pcs_autoneg_base_page, lp_base_page)
+#define SS2_PORT_PML_STS_PCS_AUTONEG_BASE_PAGE_LP_ABILITY_GET(a) \
+	C_GET(a, ss2_port_pml_sts_pcs_autoneg_base_page, lp_ability)
+#define SS2_PORT_PML_STS_PCS_AUTONEG_BASE_PAGE_BASE_PAGE_GET(a) \
+	C_GET(a, ss2_port_pml_sts_pcs_autoneg_base_page, base_page)
+#define SS2_PORT_PML_STS_PCS_AUTONEG_BASE_PAGE_COMPLETE_GET(a) \
+	C_GET(a, ss2_port_pml_sts_pcs_autoneg_base_page, complete)
+#define SS2_PORT_PML_STS_PCS_AUTONEG_BASE_PAGE_STATE_GET(a) \
+	C_GET(a, ss2_port_pml_sts_pcs_autoneg_base_page, state)
+#define SS2_PORT_PML_STS_PCS_AUTONEG_NEXT_PAGE_LP_NEXT_PAGE_GET(a) \
+	C_GET(a, ss2_port_pml_sts_pcs_autoneg_next_page, lp_next_page)
+#define SS2_PORT_PML_STS_PCS_AUTONEG_NEXT_PAGE_LP_ABILITY_GET(a) \
+	C_GET(a, ss2_port_pml_sts_pcs_autoneg_next_page, lp_ability)
+#define SS2_PORT_PML_STS_PCS_AUTONEG_NEXT_PAGE_BASE_PAGE_GET(a) \
+	C_GET(a, ss2_port_pml_sts_pcs_autoneg_next_page, base_page)
+#define SS2_PORT_PML_STS_PCS_AUTONEG_NEXT_PAGE_COMPLETE_GET(a) \
+	C_GET(a, ss2_port_pml_sts_pcs_autoneg_next_page, complete)
+#define SS2_PORT_PML_STS_PCS_AUTONEG_NEXT_PAGE_STATE_GET(a) \
+	C_GET(a, ss2_port_pml_sts_pcs_autoneg_next_page, state)
+
+#define SS2_PORT_PML_CFG_RX_PCS_ACTIVE_LANES_GET(a) \
+	C_GET(a, ss2_port_pml_cfg_rx_pcs, active_lanes)
+
+#define SS2_PORT_PML_LINK_DN_BEHAVIOR_T_LD_DISCARD C2_HNI_PML_LD_DISCARD
+#define SS2_PORT_PML_LINK_DN_BEHAVIOR_T_LD_BLOCK C2_HNI_PML_LD_BLOCK
+#define SS2_PORT_PML_LINK_DN_BEHAVIOR_T_LD_BEST_EFFORT C2_HNI_PML_LD_BEST_EFFORT
+
+#define SS2_PORT_SERDES_PMI_CTL C2_HNI_SERDES_PMI_CTL
+#define SS2_PORT_SERDES_PMI_CTL_LP_ADDR_SET(a) \
+	C_SET(a, c2_hni_serdes_pmi_ctl, pmi_lp_addr)
+#define SS2_PORT_SERDES_PMI_CTL_LP_WRITE_SET(a) \
+	C_SET(a, c2_hni_serdes_pmi_ctl, pmi_lp_write)
+#define SS2_PORT_SERDES_PMI_CTL_LP_READ_VLD_GET(a) \
+	C_GET(a, c2_hni_serdes_pmi_ctl, pmi_lp_read_vld)
+#define SS2_PORT_SERDES_PMI_CTL_LP_ACK_GET(a) \
+	C_GET(a, c2_hni_serdes_pmi_ctl, pmi_lp_ack)
+#define SS2_PORT_SERDES_PMI_CTL_LP_ERROR_GET(a) \
+	C_GET(a, c2_hni_serdes_pmi_ctl, pmi_lp_error)
+#define SS2_PORT_SERDES_PMI_CTL_LP_EN_SET(a) \
+	C_SET(a, c2_hni_serdes_pmi_ctl, pmi_lp_en)
+#define SS2_PORT_SERDES_PMI_DATA C2_HNI_SERDES_PMI_DATA
+#define SS2_PORT_SERDES_PMI_DATA_LP_RDDATA_GET(a) \
+	C_GET(a, c2_hni_serdes_pmi_data, pmi_lp_rddata)
+#define SS2_PORT_SERDES_PMI_DATA_LP_WRDATA_SET(a) \
+	C_SET(a, c2_hni_serdes_pmi_data, pmi_lp_wrdata)
+#define SS2_PORT_SERDES_PMI_DATA_LP_MASKDATA_SET(a) \
+	C_SET(a, c2_hni_serdes_pmi_data, pmi_lp_maskdata)
+
+#define SS2_PORT_PML_CFG_SERDES_RX_PMD_RX_LANE_MODE_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_serdes_rx, pmd_rx_lane_mode)
+#define SS2_PORT_PML_CFG_SERDES_RX_PMD_RX_OSR_MODE_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_serdes_rx, pmd_rx_osr_mode)
+#define SS2_PORT_PML_CFG_SERDES_RX_PMD_EXT_LOS_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_serdes_rx, pmd_ext_los)
+#define SS2_PORT_PML_CFG_SERDES_RX_PMD_LN_RX_H_PWRDN_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_serdes_rx, pmd_ln_rx_h_pwrdn)
+#define SS2_PORT_PML_CFG_SERDES_RX_PMD_LN_RX_DP_H_RSTB_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_serdes_rx, pmd_ln_rx_dp_h_rstb)
+#define SS2_PORT_PML_CFG_SERDES_RX_PMD_LN_RX_H_RSTB_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_serdes_rx, pmd_ln_rx_h_rstb)
+
+#define SS2_PORT_PML_CFG_SERDES_RX_PMD_RX_OSR_MODE_GET(a) \
+	C_GET(a, ss2_port_pml_cfg_serdes_rx, pmd_rx_osr_mode)
+
+#define SS2_PORT_PML_CFG_SERDES_TX_PMD_TX_LANE_MODE_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_serdes_tx, pmd_tx_lane_mode)
+#define SS2_PORT_PML_CFG_SERDES_TX_PMD_TX_OSR_MODE_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_serdes_tx, pmd_tx_osr_mode)
+#define SS2_PORT_PML_CFG_SERDES_TX_PMD_TX_DISABLE_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_serdes_tx, pmd_tx_disable)
+#define SS2_PORT_PML_CFG_SERDES_TX_PMD_LN_TX_H_PWRDN_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_serdes_tx, pmd_ln_tx_h_pwrdn)
+#define SS2_PORT_PML_CFG_SERDES_TX_PMD_LN_TX_DP_H_RSTB_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_serdes_tx, pmd_ln_tx_dp_h_rstb)
+#define SS2_PORT_PML_CFG_SERDES_TX_PMD_LN_TX_H_RSTB_UPDATE(a, b) \
+	C_UPDATE(a, b, ss2_port_pml_cfg_serdes_tx, pmd_ln_tx_h_rstb)
+
+#define SS2_PORT_PML_CFG_SERDES_TX_PMD_TX_OSR_MODE_GET(a) \
+	C_GET(a, ss2_port_pml_cfg_serdes_tx, pmd_tx_osr_mode)
+
+#define SS2_PORT_PML_STS_SERDES_PMD_TX_DATA_VLD_GET(a) \
+	C_GET(a, ss2_port_pml_sts_serdes, pmd_tx_data_vld)
+#define SS2_PORT_PML_STS_SERDES_PMD_TX_CLK_VLD_GET(a) \
+	C_GET(a, ss2_port_pml_sts_serdes, pmd_tx_clk_vld)
+#define SS2_PORT_PML_STS_SERDES_PMD_RX_DATA_VLD_GET(a) \
+	C_GET(a, ss2_port_pml_sts_serdes, pmd_rx_data_vld)
+#define SS2_PORT_PML_STS_SERDES_PMD_RX_CLK_VLD_GET(a) \
+	C_GET(a, ss2_port_pml_sts_serdes, pmd_rx_clk_vld)
+#define SS2_PORT_PML_STS_SERDES_PMD_RX_LOCK_GET(a) \
+	C_GET(a, ss2_port_pml_sts_serdes, pmd_rx_lock)
+#define SS2_PORT_PML_STS_SERDES_PMD_SIGNAL_DETECTGET(a) \
+	C_GET(a, ss2_port_pml_sts_serdes, pmd_signal_detect)
+
+#define SS2_PORT_PML_ERR_FLG_WORD1_LLR_REPLAY_AT_MAX_0_GET(a) \
+	C_WORD_GET(a, ss2_port_pml_err_flg, llr_replay_at_max_0, 1)
+#define SS2_PORT_PML_ERR_FLG_WORD1_LLR_REPLAY_AT_MAX_1_GET(a) \
+	C_WORD_GET(a, ss2_port_pml_err_flg, llr_replay_at_max_1, 1)
+#define SS2_PORT_PML_ERR_FLG_WORD1_LLR_REPLAY_AT_MAX_2_GET(a) \
+	C_WORD_GET(a, ss2_port_pml_err_flg, llr_replay_at_max_2, 1)
+#define SS2_PORT_PML_ERR_FLG_WORD1_LLR_REPLAY_AT_MAX_3_GET(a) \
+	C_WORD_GET(a, ss2_port_pml_err_flg, llr_replay_at_max_3, 1)
+
+#define SS2_PORT_PML_ERR_FLG_WORD1_PCS_LINK_DOWN_0_GET(a) \
+	C_WORD_GET(a, ss2_port_pml_err_flg, pcs_link_down_0, 1)
+#define SS2_PORT_PML_ERR_FLG_WORD1_PCS_LINK_DOWN_1_GET(a) \
+	C_WORD_GET(a, ss2_port_pml_err_flg, pcs_link_down_1, 1)
+#define SS2_PORT_PML_ERR_FLG_WORD1_PCS_LINK_DOWN_2_GET(a) \
+	C_WORD_GET(a, ss2_port_pml_err_flg, pcs_link_down_2, 1)
+#define SS2_PORT_PML_ERR_FLG_WORD1_PCS_LINK_DOWN_3_GET(a) \
+	C_WORD_GET(a, ss2_port_pml_err_flg, pcs_link_down_3, 1)
+
+#define SS2_PORT_PML_ERR_FLG_WORD1_PCS_LINK_DOWN_LF_0_GET(a) \
+	C_WORD_GET(a, ss2_port_pml_err_flg, pcs_link_down_lf_0, 1)
+#define SS2_PORT_PML_ERR_FLG_WORD1_PCS_LINK_DOWN_LF_1_GET(a) \
+	C_WORD_GET(a, ss2_port_pml_err_flg, pcs_link_down_lf_1, 1)
+#define SS2_PORT_PML_ERR_FLG_WORD1_PCS_LINK_DOWN_LF_2_GET(a) \
+	C_WORD_GET(a, ss2_port_pml_err_flg, pcs_link_down_lf_2, 1)
+#define SS2_PORT_PML_ERR_FLG_WORD1_PCS_LINK_DOWN_LF_3_GET(a) \
+	C_WORD_GET(a, ss2_port_pml_err_flg, pcs_link_down_lf_3, 1)
+
+#define SS2_PORT_PML_ERR_FLG_WORD1_PCS_LINK_DOWN_RF_0_GET(a) \
+	C_WORD_GET(a, ss2_port_pml_err_flg, pcs_link_down_rf_0, 1)
+#define SS2_PORT_PML_ERR_FLG_WORD1_PCS_LINK_DOWN_RF_1_GET(a) \
+	C_WORD_GET(a, ss2_port_pml_err_flg, pcs_link_down_rf_1, 1)
+#define SS2_PORT_PML_ERR_FLG_WORD1_PCS_LINK_DOWN_RF_2_GET(a) \
+	C_WORD_GET(a, ss2_port_pml_err_flg, pcs_link_down_rf_2, 1)
+#define SS2_PORT_PML_ERR_FLG_WORD1_PCS_LINK_DOWN_RF_3_GET(a) \
+	C_WORD_GET(a, ss2_port_pml_err_flg, pcs_link_down_rf_3, 1)
+
+#define SS2_PORT_PML_STS_PCS_LANE_DEGRADE_WORD0_LP_PLS_AVAILABLE_GET(a) \
+	C_WORD_GET(a, ss2_port_pml_sts_pcs_lane_degrade, lp_pls_available, 0)
+#define SS2_PORT_PML_STS_PCS_LANE_DEGRADE_WORD0_RX_PLS_AVAILABLE_GET(a) \
+	C_WORD_GET(a, ss2_port_pml_sts_pcs_lane_degrade, rx_pls_available, 0)
+
+#define SS2_PORT_PML_LLR_STATE_T_OFF_LLR C2_HNI_PML_OFF_LLR
+#define SS2_PORT_PML_LLR_STATE_T_INIT C2_HNI_PML_INIT
+#define SS2_PORT_PML_LLR_STATE_T_ADVANCE C2_HNI_PML_ADVANCE
+#define SS2_PORT_PML_LLR_STATE_T_HALT C2_HNI_PML_HALT
+#define SS2_PORT_PML_LLR_STATE_T_REPLAY C2_HNI_PML_REPLAY
+#define SS2_PORT_PML_LLR_STATE_T_DISCARD C2_HNI_PML_DISCARD
+#define SS2_PORT_PML_LLR_STATE_T_MONITOR C2_HNI_PML_MONITOR
+
+#define SS2_MB_STS_REV_PLATFORM_GET(a) C_GET(a, c_mb_sts_rev, platform)
+
+#endif /* _SBL_PML_H_ */
diff --git a/include/linux/hpe/sbl/sbl_test.h b/include/linux/hpe/sbl/sbl_test.h
new file mode 100644
index 000000000000..0f94bb16e1ef
--- /dev/null
+++ b/include/linux/hpe/sbl/sbl_test.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/* Copyright 2019-2021 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SBL_TEST_H_
+#define _SBL_TEST_H_
+
+int sbl_test_core_intr(struct sbl_inst *sbl, int port_num);
+
+int sbl_test_link_up(struct sbl_inst *sbl, int port_num, int loopback_mode);
+int sbl_test_link_reup(struct sbl_inst *sbl, int port_num, int loopback_mode);
+int sbl_test_link_down(struct sbl_inst *sbl, int port_num);
+int sbl_test_link_reset(struct sbl_inst *sbl, int port_num);
+int sbl_test_scratch(struct sbl_inst *sbl, int port_num);
+int sbl_test_serdes_stop(struct sbl_inst *sbl, int port_num);
+int sbl_test_pcs_tx_rf(struct sbl_inst *sbl, int port_num);
+void sbl_test_manipulate_serdes_fw_crc_result(u16 *crc_result);
+void sbl_test_inject_serdes_fw_crc_failure(bool set);
+
+#endif /* _SBL_SERDES_H_ */
diff --git a/include/uapi/ethernet/sbl-abi.h b/include/uapi/ethernet/sbl-abi.h
new file mode 100644
index 000000000000..d5426c4bf973
--- /dev/null
+++ b/include/uapi/ethernet/sbl-abi.h
@@ -0,0 +1,648 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+
+/* Copyright 2019-2024 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SBL_UAPI_BASE_LINK_H_
+#define _SBL_UAPI_BASE_LINK_H_
+
+#include <linux/types.h>
+
+
+#define SBL_INSTANCE_ATTR_MAGIC           0x69736d61  /* siam */
+#define SBL_MEDIA_ATTR_MAGIC              0x6d736d61  /* smam */
+#define SBL_LINK_ATTR_MAGIC               0x6c736d61  /* slam */
+
+
+#define SBL_KNOWN_FW0_REV                           0x109E
+#define SBL_KNOWN_FW0_BUILD                         0x208D
+#define SBL_FW_DEFAULT_SBM_FNAME                    "sbus_master.0x1021_2001.rom.bin"
+#define SBL_FW_DEFAULT_SERDES_FNAME                 "serdes.0x109E_208D.rom.bin"
+#define SBL_FW_NAME_LEN                           64
+
+
+/**
+ * @brief Various defaults for link startup
+ *
+ */
+#define SBL_LINK_START_TIMEOUT_PEC                48
+	/* Time out for Electrical links using AN = (1.2 * SBL_DFLT_DFE_TIMEOUT_PEC) as they are synchronized by AN */
+#define SBL_LINK_START_TIMEOUT_AOC                88
+	/* Time out for Electrical without AN/optical links = (2.2 * SBL_DFLT_DFE_TIMEOUT_AOC) to ensure a full overlap */
+#define SBL_LINK_DFLT_AN_RETRY_TIMEOUT             5
+#define SBL_LINK_DFLT_AN_MAX_RETRY                 5
+#define SBL_LINK_ALL_LANES                       0xf
+
+
+/**
+ * @brief Autoneg timeouts in ms
+ *
+ *   The link options SBL_OPT_AN_TIMEOUT_SSHOT
+ *   and  SBL_OPT_AN_TIMEOUT_IEEE are used to
+ *   select which set are used
+ *
+ *   TODO Check IEEE values
+ */
+#define SBL_LINK_AUTONEG_TIMEOUT_SSHOT_200         22000
+#define SBL_LINK_AUTONEG_TIMEOUT_SSHOT_100         10000
+#define SBL_LINK_AUTONEG_TIMEOUT_SSHOT_50           8000
+
+#define SBL_LINK_AUTONEG_TIMEOUT_IEEE_200           4000
+#define SBL_LINK_AUTONEG_TIMEOUT_IEEE_100           2250
+#define SBL_LINK_AUTONEG_TIMEOUT_IEEE_50            1125
+
+#define SBL_DFLT_PML_REC_TIMEOUT                       60  /* 60ms */
+#define SBL_DFLT_PML_REC_RL_MAX_DURATION               60  /* 60ms */
+#define SBL_DFLT_PML_REC_RL_WINDOW_SIZE              1000  /* 1000ms */
+
+/**
+ * @brief timing flags for s-bus operations
+ *
+ *   Delays are the time to pause before issuing first operation
+ *   and intervals are the time to wait between operations
+ *
+ *   Values less than 1ms will use a busy wait, values 1ms and greater
+ *   will sleep
+ */
+enum sbl_serdes_sbus_op_flag {
+	SBL_FLAG_DELAY_3US       =  1<<0,  /**< 3us delay */
+	SBL_FLAG_DELAY_4US       =  1<<1,  /**< 4us delay */
+	SBL_FLAG_DELAY_5US       =  1<<2,  /**< 5us delay */
+	SBL_FLAG_DELAY_10US      =  1<<3,  /**< 10U delay */
+	SBL_FLAG_DELAY_20US      =  1<<4,  /**< 20us delay */
+	SBL_FLAG_DELAY_50US      =  1<<5,  /**< 50 us delay */
+	SBL_FLAG_DELAY_100US     =  1<<6,  /**< 100us delay */
+	SBL_FLAG_INTERVAL_1MS    =  1<<7,  /**< 1ms interval */
+	SBL_FLAG_INTERVAL_10MS   =  1<<8,  /**< 10ms interval */
+	SBL_FLAG_INTERVAL_100MS  =  1<<9,  /**< 100ms interval */
+	SBL_FLAG_INTERVAL_1S     =  1<<10, /**< 1s interval */
+};
+
+#include "sbl_serdes_defaults.h"
+
+
+/**
+ * @brief instance attributes
+ */
+struct sbl_instance_attr {
+	__u32 magic;                           /**< = SBL_INSTANCE_ATTR_MAGIC */
+
+	char  inst_name[10];                   /**< instance name  */
+	char  eth_if_name[10];                 /**< interface name */
+
+	const char *sbm_fw_fname;              /**< sbus master fw file name */
+	const char *serdes_fw_fname;           /**< serdes fw file name */
+
+	__u32 rx_phase_slip_cnt;               /**< phase slip */
+
+	__u32 sbus_op_flags_slow;              /**< flags for sbus operations */
+	__u32 sbus_op_flags_fast;              /**< flags for sbus operations after sbus speed-up*/
+	__u32 sbus_op_timeout_ms;
+	__u32 sbus_int_timeout;                /**< Sbus interrupt timeout (s) */
+	__u32 sbus_int_poll_interval;          /**< Sbus interrupt polling interval (ms) */
+	__u32 serdes_op_flags;                 /**< flags for serdes operations */
+	__u32 serdes_op_timeout_ms;
+	__u32 serdes_en_timeout;               /* SerDes enable timeout (s) */
+	__u32 serdes_en_poll_interval;         /* SerDes enable done polling interval (ms) */
+	__u32 core_status_rd_timeout;          /* o_core_status read timeout (s) */
+	__u32 core_status_rd_poll_interval;    /* o_core_status read polling interval (ms) */
+};
+
+
+/**
+ * @brief Default static instance attributes initialiser
+ */
+#define SBL_INSTANCE_ATTR_INITIALIZER \
+	{ \
+		.magic = SBL_INSTANCE_ATTR_MAGIC, \
+		.sbm_fw_fname = SBL_FW_DEFAULT_SBM_FNAME, \
+		.serdes_fw_fname = SBL_FW_DEFAULT_SERDES_FNAME, \
+		.inst_name = {0}, \
+		.eth_if_name = {0}, \
+		.rx_phase_slip_cnt = SBL_DFLT_RX_PHASE_SLIP_CNT, \
+		.sbus_op_flags_slow = SBL_DFLT_SBUS_OP_FLAGS_SLOW, \
+		.sbus_op_flags_fast = SBL_DFLT_SBUS_OP_FLAGS_FAST, \
+		.sbus_op_timeout_ms = SBL_DFLT_SBUS_OP_TIMEOUT_MS, \
+		.sbus_int_timeout = SBL_DFLT_SBUS_INT_TIMEOUT, \
+		.sbus_int_poll_interval = SBL_DFLT_SBUS_INT_POLL_INTERVAL, \
+		.serdes_op_flags = SBL_DFLT_SERDES_OP_FLAGS, \
+		.serdes_op_timeout_ms = SBL_DFLT_SERDES_OP_TIMEOUT_MS, \
+		.serdes_en_timeout = SBL_DFLT_SERDES_EN_TIMEOUT, \
+		.serdes_en_poll_interval = SBL_DFLT_SERDES_EN_POLL_INTERVAL, \
+		.core_status_rd_timeout = SBL_DFLT_CORE_STATUS_RD_TIMEOUT, \
+		.core_status_rd_poll_interval = SBL_DFLT_CORE_STATUS_RD_POLL_INTERVAL, \
+	}
+
+/**
+ * @brief Default static instance attributes initialiser
+ */
+static inline void sbl_instance_attr_initializer(struct sbl_instance_attr *attr)
+{
+	attr->magic = SBL_INSTANCE_ATTR_MAGIC;
+	attr->sbm_fw_fname = SBL_FW_DEFAULT_SBM_FNAME;
+	attr->serdes_fw_fname = SBL_FW_DEFAULT_SERDES_FNAME;
+	attr->rx_phase_slip_cnt = SBL_DFLT_RX_PHASE_SLIP_CNT;
+	attr->sbus_op_flags_slow = SBL_DFLT_SBUS_OP_FLAGS_SLOW;
+	attr->sbus_op_flags_fast = SBL_DFLT_SBUS_OP_FLAGS_FAST;
+	attr->sbus_op_timeout_ms = SBL_DFLT_SBUS_OP_TIMEOUT_MS;
+	attr->sbus_int_timeout = SBL_DFLT_SBUS_INT_TIMEOUT;
+	attr->sbus_int_poll_interval = SBL_DFLT_SBUS_INT_POLL_INTERVAL;
+	attr->serdes_op_flags = SBL_DFLT_SERDES_OP_FLAGS;
+	attr->serdes_op_timeout_ms = SBL_DFLT_SERDES_OP_TIMEOUT_MS;
+	attr->serdes_en_timeout = SBL_DFLT_SERDES_EN_TIMEOUT;
+	attr->serdes_en_poll_interval = SBL_DFLT_SERDES_EN_POLL_INTERVAL;
+	attr->core_status_rd_timeout = SBL_DFLT_CORE_STATUS_RD_TIMEOUT;
+	attr->core_status_rd_poll_interval = SBL_DFLT_CORE_STATUS_RD_POLL_INTERVAL;
+}
+
+
+/**
+ * @brief The physical type of the link media
+ */
+enum sbl_link_media {
+	SBL_LINK_MEDIA_INVALID = 0,
+	SBL_LINK_MEDIA_UNKNOWN,
+	SBL_LINK_MEDIA_ELECTRICAL,  /**< physical wires */
+	SBL_LINK_MEDIA_OPTICAL,     /**< optical fiber  */
+};
+
+
+/**
+ * @brief The physical type of the link media with digital/analog
+ */
+enum sbl_link_media_extended {
+	SBL_EXT_LINK_MEDIA_ELECTRICAL      = 1<<0, /**< physical wires        */
+	SBL_EXT_LINK_MEDIA_OPTICAL_ANALOG  = 1<<1, /**< analog optical fiber  */
+	SBL_EXT_LINK_MEDIA_OPTICAL_DIGITAL = 1<<2, /**< digital optical fiber */
+	SBL_EXT_LINK_MEDIA_ELECTRICAL_ACT  = 1<<3, /**< active electrical     */
+};
+
+
+/**
+ * @brief The cable vendor
+ */
+enum sbl_link_vendor {
+	SBL_LINK_VENDOR_INVALID        = 0,
+	SBL_LINK_VENDOR_TE             = 1<<0,
+	SBL_LINK_VENDOR_LEONI          = 1<<1,
+	SBL_LINK_VENDOR_MOLEX          = 1<<2,
+	SBL_LINK_VENDOR_HISENSE        = 1<<3,
+	SBL_LINK_VENDOR_DUST_PHOTONICS = 1<<4,
+	SBL_LINK_VENDOR_FINISAR        = 1<<5,
+	SBL_LINK_VENDOR_LUXSHARE       = 1<<6,
+	SBL_LINK_VENDOR_FIT            = 1<<7,
+	SBL_LINK_VENDOR_FT             = 1<<8,
+	SBL_LINK_VENDOR_MELLANOX       = 1<<9,
+	SBL_LINK_VENDOR_HITACHI        = 1<<10,
+	SBL_LINK_VENDOR_HPE            = 1<<11,
+	SBL_LINK_VENDOR_CLOUD_LIGHT    = 1<<12,
+	SBL_LINK_VENDOR_AMPHENOL       = 1<<13,
+};
+
+
+/**
+ * @brief Cable length indicator
+ */
+/* Remember to update validation function */
+enum sbl_link_len {
+	SBL_LINK_LEN_INVALID   = 0,
+	SBL_LINK_LEN_BACKPLANE = 1ULL << 0,
+	SBL_LINK_LEN_000_300   = 1ULL << 1,
+	SBL_LINK_LEN_000_400   = 1ULL << 2,
+	SBL_LINK_LEN_000_750   = 1ULL << 3,
+	SBL_LINK_LEN_000_800   = 1ULL << 4,
+	SBL_LINK_LEN_001_000   = 1ULL << 5,
+	SBL_LINK_LEN_001_100   = 1ULL << 6,
+	SBL_LINK_LEN_001_150   = 1ULL << 7,
+	SBL_LINK_LEN_001_200   = 1ULL << 8,
+	SBL_LINK_LEN_001_400   = 1ULL << 9,
+	SBL_LINK_LEN_001_420   = 1ULL << 10,
+	SBL_LINK_LEN_001_500   = 1ULL << 11,
+	SBL_LINK_LEN_001_600   = 1ULL << 12,
+	SBL_LINK_LEN_001_640   = 1ULL << 13,
+	SBL_LINK_LEN_001_700   = 1ULL << 14,
+	SBL_LINK_LEN_001_800   = 1ULL << 15,
+	SBL_LINK_LEN_001_900   = 1ULL << 16,
+	SBL_LINK_LEN_001_910   = 1ULL << 17,
+	SBL_LINK_LEN_002_000   = 1ULL << 18,
+	SBL_LINK_LEN_002_100   = 1ULL << 19,
+	SBL_LINK_LEN_002_130   = 1ULL << 20,
+	SBL_LINK_LEN_002_200   = 1ULL << 21,
+	SBL_LINK_LEN_002_300   = 1ULL << 22,
+	SBL_LINK_LEN_002_390   = 1ULL << 23,
+	SBL_LINK_LEN_002_400   = 1ULL << 24,
+	SBL_LINK_LEN_002_500   = 1ULL << 25,
+	SBL_LINK_LEN_002_600   = 1ULL << 26,
+	SBL_LINK_LEN_002_620   = 1ULL << 27,
+	SBL_LINK_LEN_002_700   = 1ULL << 28,
+	SBL_LINK_LEN_002_800   = 1ULL << 29,
+	SBL_LINK_LEN_002_900   = 1ULL << 30,
+	SBL_LINK_LEN_002_990   = 1ULL << 31,
+	SBL_LINK_LEN_003_000   = 1ULL << 32,
+	SBL_LINK_LEN_004_000   = 1ULL << 33,
+	SBL_LINK_LEN_005_000   = 1ULL << 34,
+	SBL_LINK_LEN_006_000   = 1ULL << 35,
+	SBL_LINK_LEN_007_000   = 1ULL << 36,
+	SBL_LINK_LEN_008_000   = 1ULL << 37,
+	SBL_LINK_LEN_010_000   = 1ULL << 38,
+	SBL_LINK_LEN_014_000   = 1ULL << 39,
+	SBL_LINK_LEN_015_000   = 1ULL << 40,
+	SBL_LINK_LEN_019_000   = 1ULL << 41,
+	SBL_LINK_LEN_025_000   = 1ULL << 42,
+	SBL_LINK_LEN_030_000   = 1ULL << 43,
+	SBL_LINK_LEN_035_000   = 1ULL << 44,
+	SBL_LINK_LEN_050_000   = 1ULL << 45,
+	SBL_LINK_LEN_075_000   = 1ULL << 46,
+	SBL_LINK_LEN_100_000   = 1ULL << 47,
+};
+
+
+/**
+ * @brief Attributes describing the media configuration
+ *
+ */
+struct sbl_media_attr {
+	__u32 magic;
+	__u32 media;   /**< The link media type */
+	__u64 len;     /**< Cable length */
+	__u32 info;    /**< Additional information flags */
+	__u32 vendor;  /**< Cable vendor info */
+};
+
+
+/**
+ * @brief static media attributes initialiser
+ *
+ */
+#define SBL_MEDIA_ATTR_INITIALIZER   \
+	{ \
+		.magic  = SBL_MEDIA_ATTR_MAGIC, \
+		.media  = SBL_LINK_MEDIA_INVALID, \
+		.len    = SBL_LINK_LEN_INVALID, \
+		.info   = 0, \
+		.vendor = SBL_LINK_VENDOR_INVALID, \
+	}
+
+
+/**
+ * @brief dynamic media attributes initialiser
+ *
+ */
+static inline void sbl_media_attr_initializer(struct sbl_media_attr *attr)
+{
+	attr->magic  = SBL_MEDIA_ATTR_MAGIC;
+	attr->media  = SBL_LINK_MEDIA_INVALID;
+	attr->len    = SBL_LINK_LEN_INVALID;
+	attr->info   = 0;
+	attr->vendor = SBL_LINK_VENDOR_INVALID;
+}
+
+
+/**
+ * @brief media attributes flags
+ *
+ */
+enum sbl_media_attr_info_flags {
+	SBL_MEDIA_INFO_SUPPORTS_BS_200G         = 1<<0,  /**< Media supports SBL_LINK_MODE_BS_200G */
+	SBL_MEDIA_INFO_SUPPORTS_BJ_100G         = 1<<1,  /**< Media supports SBL_LINK_MODE_BJ_100G */
+	SBL_MEDIA_INFO_SUPPORTS_CD_100G         = 1<<2,  /**< Media supports SBL_LINK_MODE_CD_100G */
+	SBL_MEDIA_INFO_SUPPORTS_CD_50G          = 1<<3,  /**< Media supports SBL_LINK_MODE_CD_50G  */
+	SBL_MEDIA_INFO_ANALOG                   = 1<<4,  /**< Media is analog                      */
+	SBL_MEDIA_INFO_DIGITAL                  = 1<<5,  /**< Media is digital                     */
+	SBL_MEDIA_INFO_SUPPORTS_HEADSHELL_RESET = 1<<6,  /**< Media supports headshell reset       */
+	SBL_MEDIA_INFO_SUPPORTS_BS_400G         = 1<<7,  /**< Media supports SBL_LINK_MODE_BS_400G */
+};
+
+
+/**
+ * @brief IEEE modes for a link
+ */
+enum sbl_link_mode {
+	SBL_LINK_MODE_INVALID = 0,
+	SBL_LINK_MODE_BS_200G = 1<<0, /**< 4 lanes of 50Gbps PAM-4 */
+	SBL_LINK_MODE_BJ_100G = 1<<1, /**< 4 lanes of 25Gbps NRZ   */
+	SBL_LINK_MODE_CD_100G = 1<<2, /**< 2 lanes of 50Gbps PAM-4 */
+	SBL_LINK_MODE_CD_50G  = 1<<3, /**< 1 lane of 50Gbps PAM-4  */
+};
+
+
+/**
+ * @brief AN modes for a link
+ */
+enum sbl_an_mode {
+	SBL_AN_MODE_INVALID = 0,
+	SBL_AN_MODE_UNKNOWN,
+	SBL_AN_MODE_OFF,         /**< AN off, use link_mode */
+	SBL_AN_MODE_ON,          /**< AN to highest common speed */
+	SBL_AN_MODE_FIXED,       /**< AN to fixed speed set in link_mode */
+};
+
+
+/**
+ * @brief option flags
+ */
+enum sbl_options_flags {
+	SBL_OPT_FABRIC_LINK                = 1<<1,  /**< assert link is a fabric link */
+	SBL_OPT_SERDES_LPD                 = 1<<2,  /**< use the serdes to detect the link partner */
+	SBL_OPT_DFE_SAVE_PARAMS            = 1<<3,  /**< Save current tuning params after tuning */
+	SBL_OPT_USE_SAVED_PARAMS           = 1<<4,  /**< Load saved tuning params before tuning */
+	SBL_OPT_RESET_CLEAR_PARAMS         = 1<<5,  /**< Clear any saved tuning params during reset */
+	SBL_OPT_ENABLE_PCAL                = 1<<6,  /**< Enable periodic retuning */
+	SBL_OPT_DFE_ALWAYS_MAX_EFFORT      = 1<<7,  /**< Always tune with full effort */
+	SBL_OPT_DFE_ALWAYS_MED_EFFORT      = 1<<8,  /**< Always tune with medium effort */
+	SBL_OPT_DFE_ALWAYS_MIN_EFFORT      = 1<<9,  /**< Always tune with low effort */
+	SBL_OPT_AUTONEG_TIMEOUT_IEEE       = 1<<10, /**< Use IEEE timeout for autoneg link up */
+	SBL_OPT_AUTONEG_TIMEOUT_SSHOT      = 1<<11, /**< Use Slingshot timeout for autoneg link up */
+	SBL_OPT_AUTONEG_100CR4_FIXUP       = 1<<12, /**< Add cr4 capability to lp's an tec abilities */
+	SBL_OPT_RELOAD_FW_ON_TIMEOUT       = 1<<13, /**< Reload serdes fw on tune/minitune timeouts */
+	SBL_OPT_ALLOW_MEDIA_BAD_MODE       = 1<<14, /**< Mode not supported by media is non-fatal */
+	SBL_OPT_ALLOW_MEDIA_BAD_LEN        = 1<<15, /**< Unrecognised media len is non-fatal */
+	SBL_OPT_ENABLE_ETHER_LLR           = 1<<16, /**< enable LLR if detected */
+	SBL_OPT_ENABLE_IFG_HPC_WITH_LLR    = 1<<17, /**< enable HPC with LLR when detected*/
+	SBL_OPT_ENABLE_IFG_CONFIG          = 1<<18, /**< enable use of ifg config */
+	SBL_OPT_DISABLE_AN_LLR             = 1<<19, /**< disable AN LLR detect */
+	SBL_OPT_LANE_DEGRADE               = 1<<20, /**< enable auto lane degrade */
+	SBL_DISABLE_PML_RECOVERY           = 1<<21, /**< disable pml recovery */
+};
+
+
+/**
+ * @brief The loopback mode
+ *
+ */
+enum sbl_loopback_mode {
+	SBL_LOOPBACK_MODE_INVALID = 0,
+	SBL_LOOPBACK_MODE_LOCAL   = 1<<0, /**< Loopback in local serdes                           */
+	SBL_LOOPBACK_MODE_REMOTE  = 1<<1, /**< Loopback in remote serdes (not currently possible) */
+	SBL_LOOPBACK_MODE_OFF     = 1<<2, /**< No loopback                                        */
+};
+
+
+/**
+ * @brief Link partner
+ */
+enum sbl_link_partner {
+	SBL_LINK_PARTNER_INVALID = 0,
+	SBL_LINK_PARTNER_SWITCH  = 1<<0, /**< Switch port */
+	SBL_LINK_PARTNER_NIC     = 1<<1, /**< Edge port   */
+	SBL_LINK_PARTNER_NIC_C2  = 1<<2, /**< Cassini2 Edge port   */
+};
+
+
+/**
+ * @brief Tuning pattern
+ */
+enum sbl_tuning_pattern {
+	SBL_TUNING_PATTERN_INVALID = 0,
+	SBL_TUNING_PATTERN_CORE    = 1<<0, /**< Tune off core data        */
+	SBL_TUNING_PATTERN_PRBS    = 1<<1, /**< Tune off a PRBS13 pattern */
+};
+
+
+/**
+ * @brief Precoding config
+ */
+enum sbl_precoding_config {
+	SBL_PRECODING_INVALID = 0,
+	SBL_PRECODING_UNKNOWN,
+	SBL_PRECODING_DEFAULT,    /**< On for fabric links, Off for Ethernet links */
+	SBL_PRECODING_ON,         /**< Always on */
+	SBL_PRECODING_OFF,        /**< Always off */
+};
+
+
+/**
+ * @brief The status of a link SerDes
+ *
+ */
+enum sbl_serdes_status {
+	SBL_SERDES_STATUS_UNKNOWN    = 0,
+	SBL_SERDES_STATUS_AUTONEG    = 1<<0,  /**< SerDes in autoneg mode */
+	SBL_SERDES_STATUS_LPD_MT     = 1<<1,  /**< SerDes detecting the link partner by minitune */
+	SBL_SERDES_STATUS_DOWN       = 1<<2,  /**< SerDes down  */
+	SBL_SERDES_STATUS_TUNING     = 1<<3,  /**< SerDes is tuning  */
+	SBL_SERDES_STATUS_RUNNING    = 1<<4,  /**< SerDes running */
+	SBL_SERDES_STATUS_ERROR      = 1<<5,  /**< SerDes has an error */
+	SBL_SERDES_STATUS_RESETTING  = 1<<6,  /**< SerDes is resetting */
+};
+
+
+/**
+ * @brief The status of a link SerDes
+ *
+ */
+enum sbl_fw_status {
+	SBL_FW_STATUS_UNKNOWN            = 0,
+	SBL_FW_STATUS_NOT_FLASHED        = 1<<0,  /**< Not flashed  */
+	SBL_FW_STATUS_FLASHED            = 1<<1,  /**< SBM and SerDes flashed */
+	SBL_FW_STATUS_ERROR              = 1<<2,  /**< Flash error */
+};
+
+
+/**
+ * @brief FEC (Reed-Solomon) mode
+ */
+enum sbl_rs_mode {
+	SBL_RS_MODE_INVALID = 0,
+	SBL_RS_MODE_UNKNOWN,
+	SBL_RS_MODE_OFF,            /**< error correction OFF error checking OFF syndrome checking OFF marking OFF */
+	SBL_RS_MODE_OFF_SYN,        /**< error correction OFF error checking OFF syndrome checking  ON marking OFF */
+	SBL_RS_MODE_OFF_CHK,        /**< error correction OFF error checking  ON syndrome checking OFF marking OFF */
+	SBL_RS_MODE_ON,             /**< error correction  ON error checking  ON syndrome checking OFF marking OFF */
+	SBL_RS_MODE_ON_SYN_MRK,     /**< error correction  ON error checking OFF syndrome checking  ON marking  ON */
+	SBL_RS_MODE_ON_CHK_SYN_MRK, /**< error correction  ON error checking  ON syndrome checking  ON marking  ON */
+};
+
+
+/**
+ * @brief IFG config
+ */
+enum sbl_ifg_config {
+	SBL_IFG_CONFIG_INVALID = 0,
+	SBL_IFG_CONFIG_UNKNOWN,
+	SBL_IFG_CONFIG_HPC,          /**< mode hpc,  adj ignored */
+	SBL_IFG_CONFIG_IEEE_200G,    /**< mode ieee, adj 200     */
+	SBL_IFG_CONFIG_IEEE_100G,    /**< mode ieee, adj 100     */
+	SBL_IFG_CONFIG_IEEE_50G,     /**< mode ieee, adj 50      */
+};
+
+
+/**
+ * @brief link-level retry (LLR) mode
+ */
+enum sbl_llr_mode {
+	SBL_LLR_MODE_INVALID = 0,
+	SBL_LLR_MODE_UNKNOWN,
+	SBL_LLR_MODE_OFF,          /**< No Retry */
+	SBL_LLR_MODE_MONITOR,      /**< Monitor but don't retry */
+	SBL_LLR_MODE_ON,           /**< Retry  */
+	SBL_LLR_MODE_AUTO,         /**< try LLR */
+};
+
+
+/**
+ * @brief LLR link down behaviour
+ *
+ *  @note Fabric link must be set to SBL_LLR_LINK_DOWN_BLOCK
+ *
+ */
+enum sbl_llr_down_behaviour {
+	SBL_LLR_LINK_DOWN_INVALID = 0,
+	SBL_LLR_LINK_DOWN_UNKNOWN,
+	SBL_LLR_LINK_DOWN_DISCARD,      /**< Discard frame */
+	SBL_LLR_LINK_DOWN_BLOCK,        /**< Block waiting for link up */
+	SBL_LLR_LINK_DOWN_BEST_EFFORT,  /**< <b>Do not use</b> For Debug  */
+};
+
+
+/**
+ * @brief Other LLR settings
+ */
+#define SBL_LLR_REPLAY_CT_MAX_UNLIMITED                                0xFFULL
+#define SBL_DFLT_REPLAY_CT_MAX                                         0xFEULL  /* max - 1 */
+
+/**
+ * @brief Attributes for link configuration
+ *
+ *   These attributes must be configured for a link.
+ *   Different setting will be required for fabric or Ethernet links
+ *
+ */
+struct sbl_base_link_attr {
+	__u32 magic;
+
+	/* option flags */
+	__u32 options;                   /**< misc config options */
+
+	/* bringup */
+	__u32 start_timeout;             /**< timeout for base_link_start (s) */
+
+	/* electrical or optical exclusive configuration */
+	__u32 config_target;             /**< PEC or AOC valid */
+	union {
+		struct {
+			/* auto negotiation */
+			__u32 an_mode;                 /**< Requested autonegotiate mode */
+			__u32 an_retry_timeout;        /**< Timeout for an AN attempt to complete before retrying (s) */
+			__u32 an_max_retry;            /**< Max number of retries before failing */
+		} pec;
+		struct {
+			/* optical transceiver locking delay */
+			__u32 optical_lock_delay;      /**< time to wait for lock (ms) */
+			__u32 optical_lock_interval;   /**< wakeup interval (ms) */
+			__u32 reserved;                /**< unused */
+		} aoc;
+	};
+
+	/* link partner detection */
+	__u32 lpd_timeout;               /**< timeout for a lp detection attempt to complete before retrying (s) */
+	__u32 lpd_poll_interval;         /**< lp detection polling interval (ms) */
+
+	/* requested config */
+	__u32 link_mode;                 /**< Requested link speed mode */
+	__u32 loopback_mode;             /**< Requested Loopback mode */
+	__u32 link_partner;              /**< NIC or SWITCH link partner */
+	__u32 tuning_pattern;            /**< PRBS or CORE tuning pattern */
+	__u32 precoding;                 /**< Precoding configuration */
+
+	/* serdes attributes */
+	__u32 dfe_pre_delay;             /**< Delay before starting DFE tune (s) */
+	__u32 dfe_timeout;               /**< DFE tune wait time (ms) */
+	__u32 dfe_poll_interval;         /**< DFE tune done polling interval (ms) */
+	__u32 pcal_eyecheck_holdoff;     /**< period to ignore eye heights after pcal starts (ms) */
+	__u32 nrz_min_eye_height;        /**< Min eye height criteria for electrical cables with nrz */
+	__u32 nrz_max_eye_height;        /**< Max eye height criteria for electrical cables with nrz */
+	__u32 pam4_min_eye_height;       /**< Min eye height criteria for optical cables with pam4  */
+	__u32 pam4_max_eye_height;       /**< Max eye height criteria for optical cables with pam4 */
+
+	/* pml block attributes */
+	__u32 fec_mode;                  /**< FEC (RS) mode */
+	__u32 enable_autodegrade;        /**< Enable automatic link degrade handling */
+	__u32 llr_mode;                  /**< Link-level retry (LLR) mode */
+	__u32 ifg_config;                /**< Inter-frame gap (IFG) config */
+
+	struct {
+		__u32 timeout;           /**< PML recovery timeout */
+		__u32 rl_max_duration;   /**< Rate limiter recovery time per window */
+		__u32 rl_window_size;    /**< Rate limiter window size */
+	} pml_recovery;
+};
+
+
+/**
+ * @brief PEC or AOC configured
+ */
+enum sbl_base_link_config_target {
+	SBL_BASE_LINK_CONFIG_INVALID   = 0,
+	SBL_BASE_LINK_CONFIG_UNKNOWN,
+	SBL_BASE_LINK_CONFIG_PEC,
+	SBL_BASE_LINK_CONFIG_AOC,
+	SBL_BASE_LINK_CONFIG_AEC,
+};
+
+
+/**
+ * @brief The status of a base link
+ *
+ */
+enum sbl_base_link_status {
+	SBL_BASE_LINK_STATUS_UNKNOWN          = 0,
+	SBL_BASE_LINK_STATUS_UNCONFIGURED     = 1<<0,  /**< Base link is not configured */
+	SBL_BASE_LINK_STATUS_STARTING         = 1<<1,  /**< Base link bring-up in progress */
+	SBL_BASE_LINK_STATUS_UP               = 1<<2,  /**< Base link Up */
+	SBL_BASE_LINK_STATUS_STOPPING         = 1<<3,  /**< Base link bring-down in progress */
+	SBL_BASE_LINK_STATUS_DOWN             = 1<<4,  /**< Base link Down */
+	SBL_BASE_LINK_STATUS_RESETTING        = 1<<5,  /**< Base link reset in progress */
+	SBL_BASE_LINK_STATUS_ERROR            = 1<<6,  /**< Base link has an error */
+};
+
+
+/**
+ * @brief Debug options
+ *
+ */
+enum sbl_debug_options {
+	SBL_DEBUG_ALL_OPTS                = 0xffffffff,  /**< all flags  */
+
+	SBL_DEBUG_TRACE_LINK_DOWN         = (1<<0),      /**< report link down - generally too verbose*/
+	SBL_DEBUG_IGNORE_HISER            = (1<<1),      /**< make hiser errors a warning */
+	SBL_DEBUG_INHIBIT_CLEANUP         = (1<<2),      /**< do not cleanup after start fail */
+	SBL_DEBUG_INHIBIT_SPLL_RESET      = (1<<3),      /**< do not reset serdes PLLs after tuning failure */
+
+	SBL_DEBUG_BAD_PARAM_1             = (1<<4),      /**< allow one bad tuning param */
+	SBL_DEBUG_BAD_PARAM_2             = (1<<5),      /**< allow two bad tuning params */
+	SBL_DEBUG_INHIBIT_RELOAD_FW       = (1<<6),      /**< stop serdes fw reload on startup failure */
+	SBL_DEBUG_FORCE_RELOAD_FW         = (1<<7),      /**< force serdes fw to reload on startup failure */
+
+	SBL_DEBUG_FORCE_MAX_EFFORT        = (1<<8),      /**< force maximum effort tuning */
+	SBL_DEBUG_FORCE_MED_EFFORT        = (1<<9),      /**< force_medium effort tuning */
+	SBL_DEBUG_FORCE_MIN_EFFORT        = (1<<10),     /**< force_minium effort tuning */
+	SBL_DEBUG_INHIBIT_USE_SAVED_TP    = (1<<11),     /**< do not use saved tuning params */
+
+	SBL_DEBUG_FORCE_PRECODING_ON      = (1<<12),     /**< Force serdes precoding on */
+	SBL_DEBUG_FORCE_PRECODING_OFF     = (1<<13),     /**< Force serdes precoding off */
+	SBL_DEBUG_ALLOW_MEDIA_BAD_MODE    = (1<<14),     /**< Mode not supported by media not error */
+	SBL_DEBUG_ALLOW_MEDIA_BAD_LEN     = (1<<15),     /**< Unrecognised media length not error */
+
+	SBL_DEBUG_INHIBIT_PCAL            = (1<<16),     /**< do not start PCAL */
+	SBL_DEBUG_INHIBIT_RELOAD_SBM_FW   = (1<<17),     /**< stop sbus master fw reload on serdes fw reload failure */
+	SBL_DEBUG_FORCE_RELOAD_SBM_FW     = (1<<18),     /**< force sbus master fw reload on serdes fw reload failure */
+	SBL_DEBUG_DISABLE_AN_NEXT_PAGES   = (1<<19),     /**< disable next pages during auto negotiation */
+
+	SBL_DEBUG_KEEP_SERDES_UP          = (1<<20),     /**< keep serdes up when link is going down */
+	SBL_DEBUG_SERDES_MAP_DELAY        = (1<<21),     /**< add delay before checking serdes eye heights */
+	SBL_DEBUG_FORCE_RELOAD_SERDES_FW  = (1<<22),     /**< force serdes fw reload during link reset */
+	SBL_DEBUG_ALLOW_LOOP_TIME_FAIL    = (1<<23),     /**< fail loop time measurement */
+
+	SBL_DEBUG_IGNORE_ALIGN            = (1<<24),     /**< ignore alignment interrupt */
+	SBL_DEBUG_TRACE_PML_INT           = (1<<25),     /**< enable pml interrupt output */
+	SBL_DEBUG_REMOTE_FAULT_RECOVERY   = (1<<26),     /**< enable pml recovery for remote faults */
+	SBL_DEBUG_IGNORE_HIGH_FEC_UCW     = (1<<27),     /**< enable FEC UCW debug */
+
+	SBL_DEBUG_DEV0                    = (1<<28),     /**< for development - no fixed use */
+	SBL_DEBUG_IGNORE_HIGH_FEC_TXR     = (1<<29),     /**< enable FEC TXR debug */
+	SBL_DEBUG_IGNORE_HIGH_FEC_CCW     = (1<<30),     /**< enable FEC CCW debug */
+	SBL_DEBUG_TEST                    = (1<<31),     /**< for testing the debug system  */
+};
+
+
+#endif  /* _SBL_UAPI_BASE_LINK_H_ */
diff --git a/include/uapi/ethernet/sbl_cassini.h b/include/uapi/ethernet/sbl_cassini.h
new file mode 100644
index 000000000000..e8b0bf6811dc
--- /dev/null
+++ b/include/uapi/ethernet/sbl_cassini.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+
+/* Copyright 2020 Hewlett Packard Enterprise Development LP */
+#ifndef _CASSINI_SBL_UAPI_H_
+#define _CASSINI_SBL_UAPI_H_
+
+/**
+ * @brief Cassini platform options provided by the microcontroller
+ *
+ */
+enum cass_uc_platform {
+	SBL_UC_PLATFORM_UNDEFINED = 0,
+	SBL_UC_PLATFORM_UNKNOWN,
+	SBL_UC_PLATFORM_SAWTOOTH,
+	SBL_UC_PLATFORM_BRAZOS,
+	SBL_UC_PLATFORM_WASHINGTON,
+	SBL_UC_PLATFORM_KENNEBEC,
+	SBL_UC_PLATFORM_PANGANI,
+};
+
+#endif  /* _CASSINI_SBL_UAPI_H_ */
diff --git a/include/uapi/ethernet/sbl_counters.h b/include/uapi/ethernet/sbl_counters.h
new file mode 100644
index 000000000000..4a8d9d178ffc
--- /dev/null
+++ b/include/uapi/ethernet/sbl_counters.h
@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+
+/* Copyright 2019, 2022 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SBL_UAPI_COUNTERS_H_
+#define _SBL_UAPI_COUNTERS_H_
+
+#define SBL_NUM_COUNTERS SBL_LINK_NUM_COUNTERS
+#define SBL_COUNTERS SBL_LINK_COUNTERS
+#define SBL_COUNTERS_NAME SBL_LINK_COUNTERS_NAME
+#define SBL_COUNTERS_FIRST sbl_serdes0_fw_reload
+#define SBL_PML_REC_HISTOGRAM_MAX 120
+
+/* Used in enum as well*/
+#define SBL_LINK_COUNTERS sbl_serdes0_fw_reload,   \
+	sbl_serdes1_fw_reload,   \
+	sbl_serdes2_fw_reload,   \
+	sbl_serdes3_fw_reload,   \
+	sbl_serdes0_spico_reset, \
+	sbl_serdes1_spico_reset, \
+	sbl_serdes2_spico_reset, \
+	sbl_serdes3_spico_reset, \
+	sbl_serdes0_pll_reset,   \
+	sbl_serdes1_pll_reset,   \
+	sbl_serdes2_pll_reset,   \
+	sbl_serdes3_pll_reset,   \
+	sbl_serdes_fw_reload_skip,  \
+	sbl_pml_recovery_attempts,  \
+	sbl_pml_recovery_successes, \
+	sbl_pml_recovery_origin_bl_ldown,  \
+	sbl_pml_recovery_origin_bl_lfault, \
+	sbl_pml_recovery_origin_bl_rfault, \
+	sbl_pml_recovery_origin_bl_align,  \
+	sbl_pml_recovery_origin_bl_hiser,  \
+	sbl_pml_recovery_origin_bl_llr,    \
+	sbl_pml_recovery_histogram_0_9ms,   \
+	sbl_pml_recovery_histogram_10_19ms, \
+	sbl_pml_recovery_histogram_20_29ms, \
+	sbl_pml_recovery_histogram_30_39ms, \
+	sbl_pml_recovery_histogram_40_49ms, \
+	sbl_pml_recovery_histogram_50_59ms, \
+	sbl_pml_recovery_histogram_60_69ms, \
+	sbl_pml_recovery_histogram_70_79ms, \
+	sbl_pml_recovery_histogram_80_89ms, \
+	sbl_pml_recovery_histogram_90_99ms, \
+	sbl_pml_recovery_histogram_100_109ms, \
+	sbl_pml_recovery_histogram_110_119ms, \
+	sbl_pml_recovery_histogram_high,	\
+	sbl_pml_recovery_rate_exceeded,	\
+	sbl_fec_ucw_err,	\
+	sbl_fec_ccw_err,	\
+	sbl_fec_txr_err,	\
+	sbl_fec_warn,		\
+	sbl_fec_up_fail
+
+#define SBL_LINK_COUNTERS_NAME "sbl_serdes0_fw_reload",   \
+	"sbl_serdes1_fw_reload",   \
+	"sbl_serdes2_fw_reload",   \
+	"sbl_serdes3_fw_reload",   \
+	"sbl_serdes0_spico_reset", \
+	"sbl_serdes1_spico_reset", \
+	"sbl_serdes2_spico_reset", \
+	"sbl_serdes3_spico_reset", \
+	"sbl_serdes0_pll_reset",   \
+	"sbl_serdes1_pll_reset",   \
+	"sbl_serdes2_pll_reset",   \
+	"sbl_serdes3_pll_reset",   \
+	"sbl_serdes_fw_reload_skip",  \
+	"sbl_pml_recovery_attempts",  \
+	"sbl_pml_recovery_successes", \
+	"sbl_pml_recovery_origin_bl_ldown",  \
+	"sbl_pml_recovery_origin_bl_lfault", \
+	"sbl_pml_recovery_origin_bl_rfault", \
+	"sbl_pml_recovery_origin_bl_align",  \
+	"sbl_pml_recovery_origin_bl_hiser",  \
+	"sbl_pml_recovery_origin_bl_llr",	 \
+	"sbl_pml_recovery_histogram_0_9ms",	 \
+	"sbl_pml_recovery_histogram_10_19ms", \
+	"sbl_pml_recovery_histogram_20_29ms", \
+	"sbl_pml_recovery_histogram_30_39ms", \
+	"sbl_pml_recovery_histogram_40_49ms", \
+	"sbl_pml_recovery_histogram_50_59ms", \
+	"sbl_pml_recovery_histogram_60_69ms", \
+	"sbl_pml_recovery_histogram_70_79ms", \
+	"sbl_pml_recovery_histogram_80_89ms", \
+	"sbl_pml_recovery_histogram_90_99ms", \
+	"sbl_pml_recovery_histogram_100_109ms", \
+	"sbl_pml_recovery_histogram_110_119ms", \
+	"sbl_pml_recovery_histogram_high",	   \
+	"sbl_pml_recovery_rate_exceeded",	   \
+	"sbl_fec_ucw_err",		\
+	"sbl_fec_ccw_err",		\
+	"sbl_fec_txr_err",		\
+	"sbl_fec_warn",			\
+	"sbl_fec_up_fail"
+
+/**
+ * @brief SBL link level counter indexes
+ *
+ */
+
+enum sbl_link_counters_idx {
+
+	serdes0_fw_reload = 0,		/**< serdes 0 firmware reload count */
+	serdes1_fw_reload,		/**< serdes 1 firmware reload count */
+	serdes2_fw_reload,		/**< serdes 2 firmware reload count */
+	serdes3_fw_reload,		/**< serdes 3 firmware reload count */
+
+	serdes0_spico_reset,		/**< serdes 0 spico reset count */
+	serdes1_spico_reset,		/**< serdes 1 spico reset count */
+	serdes2_spico_reset,		/**< serdes 2 spico reset count */
+	serdes3_spico_reset,		/**< serdes 3 spico reset count */
+
+	serdes0_pll_reset,		/**< serdes 0 pll reset count */
+	serdes1_pll_reset,		/**< serdes 1 pll reset count */
+	serdes2_pll_reset,		/**< serdes 2 pll reset count */
+	serdes3_pll_reset,		/**< serdes 3 pll reset count */
+
+	serdes_fw_reload_skip,		/**< serdes fw reloads skipped count */
+
+	pml_recovery_attempts,			/**< pml recovery attempts */
+	pml_recovery_successes,			/**< pml recovery successes */
+	pml_recovery_origin_bl_ldown,		/**< pml recovery count for link down */
+	pml_recovery_origin_bl_lfault,		/**< pml recovery count for local fault */
+	pml_recovery_origin_bl_rfault,		/**< pml recovery count for remote fault */
+	pml_recovery_origin_bl_align,		/**< pml recovery count for align fault */
+	pml_recovery_origin_bl_hiser,		/**< pml recovery count for hiser */
+	pml_recovery_origin_bl_llr,		/**< pml recovery count for max llr replay */
+	pml_recovery_histogram_0_9ms,		/**< pml recovery time 0-9 ms */
+	pml_recovery_histogram_10_19ms,		/**< pml recovery time 10-19 ms */
+	pml_recovery_histogram_20_29ms,		/**< pml recovery time 20-29 ms */
+	pml_recovery_histogram_30_39ms,		/**< pml recovery time 30-39 ms */
+	pml_recovery_histogram_40_49ms,		/**< pml recovery time 40-49 ms */
+	pml_recovery_histogram_50_59ms,		/**< pml recovery time 50-59 ms */
+	pml_recovery_histogram_60_69ms,		/**< pml recovery time 60-69 ms */
+	pml_recovery_histogram_70_79ms,		/**< pml recovery time 70-79 ms */
+	pml_recovery_histogram_80_89ms,		/**< pml recovery time 80-89 ms */
+	pml_recovery_histogram_90_99ms,		/**< pml recovery time 90-99 ms */
+	pml_recovery_histogram_100_109ms,	/**< pml recovery time 100-109 ms */
+	pml_recovery_histogram_110_119ms,	/**< pml recovery time 110-119 ms */
+	pml_recovery_histogram_high,		/**< pml recovery time 120+ ms (SBL_PML_REC_HISTOGRAM_MAX) */
+	pml_recovery_rate_exceeded,		/**< pml recovery rate limit exceeded */
+	fec_ucw_err,		/** fec ucw bad */
+	fec_ccw_err,		/** fec ccw bad */
+	fec_txr_err,		/** fec txr bad */
+	fec_warn,		/** fec ccw warning */
+	fec_up_fail,		/** fec start check fail */
+
+	SBL_LINK_NUM_COUNTERS,		/* the number of SBL counters */
+};
+
+#endif /* _SBL_UAPI_COUNTERS_H_ */
diff --git a/include/uapi/ethernet/sbl_platform_config.h b/include/uapi/ethernet/sbl_platform_config.h
new file mode 100644
index 000000000000..09ea57072a55
--- /dev/null
+++ b/include/uapi/ethernet/sbl_platform_config.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/* Copyright 2026 Hewlett Packard Enterprise Development LP. All rights reserved. */
+
+#ifndef _UAPI_ETHERNET_SBL_PLATFORM_CONFIG_H_
+#define _UAPI_ETHERNET_SBL_PLATFORM_CONFIG_H_
+
+#define SBL_PLATFORM_CAS_HW		1
+#define SBL_PLATFORM_CAS		1
+#define SBL_BUILD_NAME			"cassini"
+#define SBL_NUM_PORTS			1
+#define SBL_NUM_SBUS_RINGS		1  /* 2 rings, but only one per NIC */
+
+#endif /* _UAPI_ETHERNET_SBL_PLATFORM_CONFIG_H_ */
diff --git a/include/uapi/ethernet/sbl_sbm_constants.h b/include/uapi/ethernet/sbl_sbm_constants.h
new file mode 100644
index 000000000000..7aaad92ed939
--- /dev/null
+++ b/include/uapi/ethernet/sbl_sbm_constants.h
@@ -0,0 +1,330 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/* Copyright 2019-2026 Hewlett Packard Enterprise Development LP. All rights reserved. */
+
+#ifndef _SBL_SBM_CONSTANTS_H_
+#define _SBL_SBM_CONSTANTS_H_
+
+/* Port Macro constants */
+#define SBL_SERDES_LANES_PER_PORT            4
+
+/* General constants */
+#define SBL_MAX_STR_LEN                      256
+#define SBL_HALF_MAX_STR_LEN                 128
+#define LEVEL_ERR                            4
+#define LEVEL_WARN                           3
+#define LEVEL_INFO                           2
+#define LEVEL_DBG                            1
+
+/* SBus address conversion macros */
+#define SBUS_ADDR(ring, rx_addr)        ((ring << 8) | rx_addr)
+#define SBUS_RING(sbus_addr)            ((sbus_addr & 0x300) >> 8)
+#define SBUS_RX_ADDR(sbus_addr)         (sbus_addr & 0xff)
+
+/* SBus operation defines */
+#define SBUS_CMD_MODE_OFFSET             7
+#define SBUS_CMD_MODE_MASK               (0x1 << SBUS_CMD_MODE_OFFSET)
+#define SBUS_IFACE_DST_OFFSET            5
+#define SBUS_IFACE_DST_MASK              (0x3 << SBUS_IFACE_DST_OFFSET)
+#define SBUS_CMD_OFFSET                  0
+#define SBUS_CMD_MASK                    (0xf << SBUS_CMD_OFFSET)
+
+#define SBUS_CMD_MODE_CTLR               (1 << SBUS_CMD_MODE_OFFSET)
+#define SBUS_CMD_MODE_RCVR               (0 << SBUS_CMD_MODE_OFFSET)
+#define SBUS_IFACE_DST_TAP               (0 << SBUS_IFACE_DST_OFFSET)
+#define SBUS_IFACE_DST_CORE              (1 << SBUS_IFACE_DST_OFFSET)
+#define SBUS_IFACE_DST_SPICO             (2 << SBUS_IFACE_DST_OFFSET)
+#define SBUS_IFACE_DST_SPARE             (3 << SBUS_IFACE_DST_OFFSET)
+#define SBUS_CMD_RESET                   (0 << SBUS_CMD_OFFSET)
+#define SBUS_CMD_WRITE                   (1 << SBUS_CMD_OFFSET)
+#define SBUS_CMD_READ                    (2 << SBUS_CMD_OFFSET)
+#define SBUS_CMD_READ_RESULT             (3 << SBUS_CMD_OFFSET)
+
+#define SBUS_RC_RESET                    0
+#define SBUS_RC_WRITE_COMPLETE           1
+#define SBUS_RC_WRITE_FAILED             2
+#define SBUS_RC_READ_ALL_COMPLETE        3
+#define SBUS_RC_READ_COMPLETE            4
+#define SBUS_RC_READ_FAILED              5
+#define SBUS_RC_CMD_ISSUE_DONE           6
+#define SBUS_RC_MODE_CHANGE_COMPLETE     7
+
+/* Rosetta */
+#define SBUS_RING0_CORE_PLL              0x1
+#define SBUS_RING0_PCIE_PLL              0x2
+#define SBUS_RING0_PCIE_SERDES_SPICO     0x3
+#define SBUS_RING0_PCIE_PCS              0x4
+#define SBUS_RING0_CM4_SERDES_FIRST      0x5
+#define SBUS_RING0_PMRO0                 0x15
+#define SBUS_RING0_THERMVOLT             0x16
+#define SBUS_RING0_PMRO1                 0x57
+#define SBUS_RING0_CM4_SERDES_LAST       0x87
+#define SBUS_RING0_SBM0                  0x88
+#define SBUS_RING0_SBM0_SPICO            0x89
+
+#define SBUS_RING1_CM4_SERDES_FIRST      0x1
+#define SBUS_RING1_PMRO2                 0x11
+#define SBUS_RING1_PMRO3                 0x52
+#define SBUS_RING1_CM4_SERDES_LAST       0x82
+#define SBUS_RING1_SBM1                  0x83
+#define SBUS_RING1_SBM1_SPICO            0x84
+
+/* Cassini */
+#define SBUS_RINGX_PCIE_PLL0                0x1
+#define SBUS_RINGX_PCIE_PLL1                0x2
+#define SBUS_RINGX_PCIE_PLL2                0x3
+#define SBUS_RINGX_CORE_PLL                 0x4
+#define SBUS_RINGX_THERMVOLT                0x5
+#define SBUS_RINGX_PMRO0                    0x6
+#define SBUS_RINGX_PMRO1                    0x7
+#define SBUS_RINGX_PCIE_SERDES_SPICO_FIRST  0x8
+#define SBUS_RINGX_PCIE_SERDES_SPICO_LAST   0x26
+#define SBUS_RINGX_PCIE_SERDES_PCS_FIRST    0x9
+#define SBUS_RINGX_PCIE_SERDES_PCS_LAST     0x27
+#define SBUS_RINGX_CM4_SERDES_FIRST         0x28
+#define SBUS_RINGX_CM4_SERDES_LAST          0x2B
+#define SBUS_RINGX_SBM                      0x2C
+#define SBUS_RINGX_SBM_SPICO                0x2D
+#define SBUS_RINGX_PCIE_SERDES_SPICO_LSB    0x0
+#define SBUS_RINGX_PCIE_SERDES_PCS_LSB      0x1
+
+/* Broadcast */
+#define SBUS_BCAST_PCIE_SERDES_SPICO     0xff
+#define SBUS_BCAST_PCIE_SERDES_PCS       0xf7
+#define SBUS_BCAST_CM4_SERDES_SPICO      0xee
+#define SBUS_BCAST_SBM_SPICO             0xfd
+#define SBUS_BCAST_SBM                   0xfe
+#define SBUS_BCAST_PLL                   0xf6
+#define SBUS_BCAST_PMRO                  0xf5
+#define SBUS_BCAST_THERMVOLT             0xef
+
+/* SBus receiver interface */
+#define SPICO_SBR_ADDR_SRAM_BIST           0x0
+#define SPICO_SBR_ADDR_CTL                 0x1
+#define SPICO_SBR_ADDR_DMEM_IN             0x2
+#define SPICO_SBR_ADDR_IMEM                0x3
+#define SPICO_SBR_ADDR_DMEM                0x4
+#define SPICO_SBR_ADDR_STEP_BP             0x5
+#define SPICO_SBR_ADDR_BP_ADDR             0x6
+#define SPICO_SBR_ADDR_INTR                0x7
+#define SPICO_SBR_ADDR_DMEM_OUT            0x8
+#define SPICO_SBR_ADDR_RDATA               0x9
+#define SPICO_SBR_ADDR_PC                  0xa
+#define SPICO_SBR_ADDR_PC_OVERRIDE         0xb
+#define SPICO_SBR_ADDR_FLAG                0xc
+#define SPICO_SBR_ADDR_OP                  0xd
+#define SPICO_SBR_ADDR_SP_EC               0xe
+#define SPICO_SBR_ADDR_STATE               0xf
+#define SPICO_SBR_ADDR_RESULT              0x10
+#define SPICO_SBR_ADDR_A_B_REG             0x11
+#define SPICO_SBR_ADDR_IMEM_BURST_DATA     0x14
+#define SPICO_SBR_ADDR_IMEM_BURST_ADDR     0x15
+#define SPICO_SBR_ADDR_ECC                 0x16
+#define SPICO_SBR_ADDR_UNNAMED_0           0x17
+#define SPICO_SBR_ADDR_UNNAMED_1           0x18
+#define SPICO_SBR_ADDR_UNNAMED_2           0x19
+#define SPICO_SBR_ADDR_UNNAMED_3           0x1a
+#define SPICO_SBR_ADDR_UNNAMED_4           0x1b
+#define SPICO_SBR_ADDR_IP_IDCODE           0xff
+
+/* SBus Controller receiver memory */
+#define SBM_CRM_ADDR_CISM0             0x0
+#define SBM_CRM_ADDR_CISM1             0x1
+#define SBM_CRM_ADDR_LAST_ADDR         0x2
+#define SBM_CRM_ADDR_CLK_DIV           0xa
+#define SBM_CRM_ADDR_CLK_DIV_RST       0xb
+#define SBM_CRM_ADDR_CLK_DIV_RST_P0    0xc
+#define SBM_CRM_ADDR_CLK_DIV_RST_P1    0xd
+#define SBM_CRM_ADDR_CISM_RX_ADDR      0x10
+#define SBM_CRM_ADDR_CISM_CMD1         0x11
+#define SBM_CRM_ADDR_CISM_DATA_ADDR1   0x12
+#define SBM_CRM_ADDR_CISM_DATA_WORD1   0x13
+#define SBM_CRM_ADDR_CISM_CMD2         0x14
+#define SBM_CRM_ADDR_CISM_DATA_ADDR2   0x15
+#define SBM_CRM_ADDR_CISM_DATA_WORD2   0x16
+#define SBM_CRM_ADDR_DATA_OUT_SEL      0x20
+#define SBM_CRM_ADDR_BIST              0x21
+#define SBM_CRM_ADDR_PROC_STS          0x2a
+#define SBM_CRM_ADDR_ROM_EN            0x30
+#define SBM_CRM_ADDR_ROM_FAILED_ADDR   0x31
+#define SBM_CRM_ADDR_ROM_DATA_VAL_CNT  0x32
+#define SBM_CRM_ADDR_ROM_ACK           0x33
+#define SBM_CRM_ADDR_ROM_STOP_ADDR     0x34
+#define SBM_CRM_ADDR_ROM_OUTPUT        0x35
+#define SBM_CRM_ADDR_ROM_DATA0         0x36
+#define SBM_CRM_ADDR_ROM_DATA1         0x37
+#define SBM_CRM_ADDR_CLK_HALT          0x40
+#define SBM_CRM_ADDR_GEN_WRITE         0x80
+#define SBM_CRM_ADDR_GEN_READ          0x81
+#define SBM_CRM_ADDR_GEN_WRITE_P0      0x82
+#define SBM_CRM_ADDR_GEN_WRITE_P1      0x83
+#define SBM_CRM_ADDR_GEN_WRITE_P2      0x84
+#define SBM_CRM_ADDR_GEN_WRITE_P3      0x85
+#define SBM_CRM_ADDR_GEN_READ_P0       0x86
+#define SBM_CRM_ADDR_GEN_READ_P1       0x87
+#define SBM_CRM_ADDR_GEN_READ_P2       0x88
+#define SBM_CRM_ADDR_GEN_READ_P3       0x89
+#define SBM_CRM_ADDR_SBUS_ID           0xfe
+#define SBM_CRM_ADDR_IP_IDCODE         0xff
+
+#define SPICO_SBR_DATA_W0_OFFSET           0
+#define SPICO_SBR_DATA_W1_OFFSET           10
+#define SPICO_SBR_DATA_W2_OFFSET           20
+
+#define SPICO_SERDES_ADDR_IMEM               0x0
+#define SPICO_SERDES_ADDR_INTR0              0x3
+#define SPICO_SERDES_ADDR_INTR1              0x4
+#define SPICO_SERDES_ADDR_RESET_EN           0x7
+#define SPICO_SERDES_ADDR_INTR_DIS           0x8
+#define SPICO_SERDES_ADDR_BIST               0x9
+#define SPICO_SERDES_ADDR_IMEM_BURST         0xa
+#define SPICO_SERDES_ADDR_ECC                0xb
+#define SPICO_SERDES_ADDR_ECCLOG             0xc
+#define SPICO_SERDES_ADDR_BCAST              0xfd
+#define SPICO_SERDES_ADDR_IP_IDCODE          0xff
+
+/* See Spico_Firmware_2002.pdf */
+/* #define SPICO_INT_SBMC_REV_ID            0x00 */
+/* #define SPICO_INT_SBMC_BUILD_ID          0x01 */
+/* #define SPICO_INT_SBMC_GET_PMRO_DATA     0x02 */
+/* #define SPICO_INT_SBMC_GET_TEMP_DATA     0x03 */
+/* #define SPICO_INT_SBMC_GET_VOLT_DATA     0x04 */
+
+#define SPICO_INT_SBMS_REV_ID            0x00
+#define SPICO_INT_SBMS_BUILD_ID          0x01
+#define SPICO_INT_SBMS_DO_CRC            0x02
+#define SPICO_INT_SBMS_READ_DMEM_VAL     0x03
+#define SPICO_INT_SBMS_DO_XDMEM_CRC      0x04
+#define SPICO_INT_SBMS_GET_PMRO_DATA     0x16
+#define SPICO_INT_SBMS_GET_TEMP_DATA     0x17
+#define SPICO_INT_SBMS_GET_VOLT_DATA     0x18
+#define SPICO_INT_SBMS_IMEM_CRC_CHECK    0x1a
+#define SPICO_INT_SBMS_IMEM_SWP_SA       0x1c
+#define SPICO_INT_SBMS_FW_STS            0x20
+#define SPICO_INT_SBMS_PCIE3_SWP         0x28
+#define SPICO_INT_SBMS_DRMON_SETUP       0x29
+#define SPICO_INT_SBMS_TEMP_SETUP        0x2a
+#define SPICO_INT_SBMS_RR_PCAL           0x2b
+#define SPICO_INT_SBMS_DDR_HMB_FIRST     0x30
+#define SPICO_INT_SBMS_DDR_HMB_LAST      0x3f
+
+#define SBMS_INTERRUPT_DATA_OUT_MASK     0xffff0000
+#define SBMS_INTERRUPT_IN_PROGRESSS_MASK 0x00008000
+#define SBMS_INTERRUPT_STATUS_MASK       0x00007fff
+#define SBMS_INTERRUPT_DATA_MASK         0xffff0000
+#define SBMS_INTERRUPT_DATA_OFFSET       16
+#define SBMS_INTERRUPT_CODE_MASK         0x0000ffff
+#define SBMS_INTERRUPT_CODE_OFFSET       0
+
+#define SBMS_INTERRUPT_STATUS_OK         0x1
+
+#define SPICO_INT_CM4_REV_ID             0x00
+#define SPICO_INT_CM4_SERDES_EN          0x01
+#define SPICO_INT_CM4_PRBS_CTRL          0x02
+#define SPICO_INT_CM4_COMPARE_CTRL       0x03
+#define SPICO_INT_CM4_PMD_CTRL           0x04
+#define SPICO_INT_CM4_TX_BAUD            0x05
+#define SPICO_INT_CM4_RX_BAUD            0x06
+#define SPICO_INT_CM4_AN_CONFIG          0x07
+#define SPICO_INT_CM4_LOOPBACK           0x08
+#define SPICO_INT_CM4_DFE_CTRL           0x0a
+#define SPICO_INT_CM4_TX_PHASE_CAL       0x0b
+#define SPICO_INT_CM4_BIT_SLIP           0x0c
+#define SPICO_INT_CM4_TX_PHASE_SLIP      0x0d
+#define SPICO_INT_CM4_RX_PHASE_SLIP      0x0e
+#define SPICO_INT_CM4_PCIE_PD            0x10
+#define SPICO_INT_CM4_PLL_RECAL          0x11
+#define SPICO_INT_CM4_SAS_APTA_CTRL      0x12
+#define SPICO_INT_CM4_POLARITY_CTRL      0x13
+#define SPICO_INT_CM4_WIDTH_MODE         0x14
+#define SPICO_INT_CM4_TXEQ_LOAD          0x15
+#define SPICO_INT_CM4_ERROR_RST          0x16
+#define SPICO_INT_CM4_BIG_REG_SEL        0x18
+#define SPICO_INT_CM4_BIG_REG_WR         0x19
+#define SPICO_INT_CM4_BIG_REG_RD         0x1a
+#define SPICO_INT_CM4_ERR_INJECT         0x1b
+#define SPICO_INT_CM4_DO_DATA_CAP        0x1c
+#define SPICO_INT_CM4_WAIT_TTD           0x1d
+#define SPICO_INT_CM4_ERR_STS            0x1e
+#define SPICO_INT_CM4_ERR_TIMER_STS      0x1f
+#define SPICO_INT_CM4_PCIE_SLICES        0x20
+#define SPICO_INT_CM4_PCIE3_RX_EQ        0x24
+#define SPICO_INT_CM4_SET_RX_EQ          0x26
+#define SPICO_INT_CM4_GET_RX_EQ          0x126
+#define SPICO_INT_CM4_CORE_TO_CNTL_EN    0x27
+#define SPICO_INT_CM4_AN_DME_PAGE        0x29
+#define SPICO_INT_CM4_INT_RX_TERM        0x2b
+#define SPICO_INT_CM4_HAL_READ           0x2c
+#define SPICO_INT_CM4_HAL_WRITE          0x6c
+#define SPICO_INT_CM4_HAL_CALL           0xec
+#define SPICO_INT_CM4_SPICO_CLK_SWP      0x30
+#define SPICO_INT_CM4_PCIE3_TX_MRG1      0x31
+#define SPICO_INT_CM4_PCIE3_TX_MRG2      0x32
+#define SPICO_INT_CM4_PCIE3_TX_MRG3      0x33
+#define SPICO_INT_CM4_PCIE3_TX_MRG4      0x34
+#define SPICO_INT_CM4_PCIE3_TX_MRG5      0x35
+#define SPICO_INT_CM4_PROC_RESET         0x39
+#define SPICO_INT_CM4_PCIE_SWP_SETUP     0x3a
+#define SPICO_INT_CM4_IP_STAT_INFO       0x3b
+#define SPICO_INT_CM4_CRC                0x3c
+#define SPICO_INT_CM4_PMD_CONFIG         0x3d
+#define SPICO_INT_CM4_BUILD_ID           0x3f
+#define SPICO_INT_CM4_O_CORE_STS_15_0    0x4027
+#define SPICO_INT_CM4_O_CORE_STS_31_16   0x4069
+#define SPICO_INT_CM4_MEM_READ           0x4000
+#define SPICO_INT_CM4_MEM_WRITE          0x8000
+
+#define SPICO_INT_RESULT_CODE_MASK      0xff
+#define SPICO_INT_RETURN_RESULT         2
+#define SPICO_INT_VALIDATE_RESULT       1
+#define SPICO_INT_IGNORE_RESULT         0
+#define SPICO_INT_DIVIDER_MASK          0xff
+#define SPICO_INT_MEM_READ_ADDR_MASK    0xfff
+
+#define SPICO_INT_DATA_NONE             0x0000
+
+#define SPICO_SBR_DATA_BE_012              0xc0000000
+#define SPICO_SBR_DATA_BE_01               0x80000000
+#define SPICO_SBR_DATA_BE_0                0x40000000
+
+/* From apd16_IO_databook.pdf */
+#define SBUS_SENSOR_ADDR_RESET_START                     0
+#define SBUS_SENSOR_ADDR_SENSOR_CLK_DIVIDE               1
+#define SBUS_SENSOR_ADDR_REMOTE_SENSOR_MODE              3
+#define SBUS_SENSOR_ADDR_SPARE_REG                       4
+#define SBUS_SENSOR_ADDR_THERM_STATE                     5
+#define SBUS_SENSOR_ADDR_TEMP_GAIN_OVRD_VAL              6
+#define SBUS_SENSOR_ADDR_TEMP_OFFSET_OVRD_VAL            7
+#define SBUS_SENSOR_ADDR_TEMP_C_RES_OVRD_VAL             8
+#define SBUS_SENSOR_ADDR_TEMP_GAIN_TRIM_OVRD_VAL         9
+#define SBUS_SENSOR_ADDR_TEMP_OFFSET_TRIM_OVRD_VAL       10
+#define SBUS_SENSOR_ADDR_TEMP_OVRD_SEL                   11
+#define SBUS_SENSOR_ADDR_VOLTAGE_GAIN_OVRD_VAL           12
+#define SBUS_SENSOR_ADDR_VOLTAGE_OFFSET_OVRD_VAL         13
+#define SBUS_SENSOR_ADDR_VOLTAGE_C_RES_OVRD_VAL          14
+#define SBUS_SENSOR_ADDR_VOLTAGE_GAIN_TRIM_OVRD_VAL      15
+#define SBUS_SENSOR_ADDR_VOLTAGE_OVRD_SEL                16
+#define SBUS_SENSOR_ADDR_REMOTE_GAIN_OVRD_VAL            17
+#define SBUS_SENSOR_ADDR_REMOTE_OFFSET_OVRD_VAL          18
+#define SBUS_SENSOR_ADDR_REMOTE_C_RES_OVRD_VAL           19
+#define SBUS_SENSOR_ADDR_REMOTE_OVRD_SEL                 20
+#define SBUS_SENSOR_ADDR_ACCUMULATOR                     64
+#define SBUS_SENSOR_ADDR_TEMPERATURE_SENSOR              65
+#define SBUS_SENSOR_ADDR_REMOTE_TEMPERATURE_SENSOR_0     66
+#define SBUS_SENSOR_ADDR_REMOTE_TEMPERATURE_SENSOR_1     67
+#define SBUS_SENSOR_ADDR_REMOTE_TEMPERATURE_SENSOR_2     68
+#define SBUS_SENSOR_ADDR_REMOTE_TEMPERATURE_SENSOR_3     69
+#define SBUS_SENSOR_ADDR_REMOTE_TEMPERATURE_SENSOR_4     70
+#define SBUS_SENSOR_ADDR_REMOTE_TEMPERATURE_SENSOR_5     71
+#define SBUS_SENSOR_ADDR_REMOTE_TEMPERATURE_SENSOR_6     72
+#define SBUS_SENSOR_ADDR_REMOTE_TEMPERATURE_SENSOR_7     73
+#define SBUS_SENSOR_ADDR_VDD_VOLTAGE_SENSOR              74
+#define SBUS_SENSOR_ADDR_CORE_VDD_VIN_VOLTAGE_SENSOR     75
+#define SBUS_SENSOR_ADDR_SENSOR_A2D_VIN_0_VOLTAGE_SENSOR 76
+#define SBUS_SENSOR_ADDR_SENSOR_A2D_VIN_1_VOLTAGE_SENSOR 77
+#define SBUS_SENSOR_ADDR_SENSOR_A2D_VIN_2_VOLTAGE_SENSOR 78
+#define SBUS_SENSOR_ADDR_SENSOR_A2D_VIN_3_VOLTAGE_SENSOR 79
+#define SBUS_SENSOR_ADDR_SENSOR_A2D_VIN_4_VOLTAGE_SENSOR 80
+#define SBUS_SENSOR_ADDR_SENSOR_A2D_VIN_5_VOLTAGE_SENSOR 81
+#define SBUS_SENSOR_ADDR_IP_IDENTIFICATION_REGISTER      255
+
+#endif /* _SBL_SBM_CONSTANTS_H_ */
diff --git a/include/uapi/ethernet/sbl_serdes.h b/include/uapi/ethernet/sbl_serdes.h
new file mode 100644
index 000000000000..853b88b9df60
--- /dev/null
+++ b/include/uapi/ethernet/sbl_serdes.h
@@ -0,0 +1,390 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+
+/* Copyright 2019-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+
+#ifndef _SBL_UAPI_BASE_LINK_SERDES_H_
+#define _SBL_UAPI_BASE_LINK_SERDES_H_
+
+
+#define SBL_TUNING_PARAM_MAGIC           0x74736d70  /* stpm */
+#define SBL_TUNING_PARAM_VERSION                  2
+
+#define SBL_SERDES_CONFIG_MAGIC          0x63736d76  /* scvm */
+#define SBL_MAX_OOB_SERDES_PARAMS        0 /* Allow no more than this number of params to be out of bounds */
+#define SBL_CTLE_HF_MIN          0
+#define SBL_CTLE_HF_MAX          15
+#define SBL_CTLE_LF_MIN          0
+#define SBL_CTLE_LF_MAX          15
+#define SBL_CTLE_DC_MIN          0
+#define SBL_CTLE_DC_MAX          0
+#define SBL_CTLE_BW_MIN          0
+#define SBL_CTLE_BW_MAX          15
+#define SBL_CTLE_GS1_MIN         0
+#define SBL_CTLE_GS1_MAX         3
+#define SBL_CTLE_GS2_MIN         0
+#define SBL_CTLE_GS2_MAX         3
+#define SBL_CTLE_SCE_MIN         0
+#define SBL_CTLE_SCE_MAX         0
+#define SBL_CTLE_HF_MIN_MIN      0
+#define SBL_CTLE_HF_MIN_MAX      0
+#define SBL_CTLE_HF_MAX_MIN      15
+#define SBL_CTLE_HF_MAX_MAX      15
+#define SBL_CTLE_LF_MIN_MIN      0
+#define SBL_CTLE_LF_MIN_MAX      3  /* relaxed */
+#define SBL_CTLE_LF_MAX_MIN      10 /* relaxed */
+#define SBL_CTLE_LF_MAX_MAX      15
+
+#define SBL_FFE_PRE2_MIN	 -10 /* relaxed */
+#define SBL_FFE_PRE2_MAX	 3  /* relaxed to 3 for BJ_100G */
+#define SBL_FFE_PRE1_MIN	 0
+#define SBL_FFE_PRE1_MAX	 11  /* relaxed */
+#define SBL_FFE_POST1_MIN	 -3
+#define SBL_FFE_POST1_MAX	 8
+#define SBL_FFE_BFLF_MIN	 0
+#define SBL_FFE_BFLF_MAX	 0
+#define SBL_FFE_BFHF_MIN	 0
+#define SBL_FFE_BFHF_MAX	 0
+#define SBL_FFE_DATARATE_MIN	 0
+#define SBL_FFE_DATARATE_MAX	 0
+#define SBL_FFE_SCE_MIN		 0
+#define SBL_FFE_SCE_MAX		 0
+#define SBL_FFE_PRE1_MIN_MIN	 0
+#define SBL_FFE_PRE1_MIN_MAX	 0
+#define SBL_FFE_PRE1_MAX_MIN	 15
+#define SBL_FFE_PRE1_MAX_MAX	 15
+#define SBL_FFE_PRE2_MIN_MIN	 -10
+#define SBL_FFE_PRE2_MIN_MAX	 -10
+#define SBL_FFE_PRE2_MAX_MIN	 10
+#define SBL_FFE_PRE2_MAX_MAX	 10
+#define SBL_FFE_BFLF_ICAL_MIN	 0
+#define SBL_FFE_BFLF_ICAL_MAX	 0
+#define SBL_FFE_POST1_MIN_MIN	 -3
+#define SBL_FFE_POST1_MIN_MAX	 -3
+#define SBL_FFE_POST1_MAX_MIN	 8
+#define SBL_FFE_POST1_MAX_MAX	 8
+
+#define SBL_DFE_GT1_MIN		 255
+#define SBL_DFE_GT1_MAX		 255
+#define SBL_DFE_GT2_MIN		 255
+#define SBL_DFE_GT2_MAX		 255
+#define SBL_DFE_G2_MIN		 -31 /* relaxed */
+#define SBL_DFE_G2_MAX		 15  /* relaxed */
+#define SBL_DFE_G3_MIN		 -9  /* relaxed */
+#define SBL_DFE_G3_MAX		 14
+#define SBL_DFE_G4_MIN		 -6  /* relaxed */
+#define SBL_DFE_G4_MAX		 8   /* relaxed */
+#define SBL_DFE_G5_MIN		 -4  /* relaxed */
+#define SBL_DFE_G5_MAX		 12  /* relaxed */
+#define SBL_DFE_G6_MIN		 -4  /* relaxed */
+#define SBL_DFE_G6_MAX		 6   /* relaxed */
+#define SBL_DFE_G7_MIN		 -4  /* relaxed */
+#define SBL_DFE_G7_MAX		 6   /* relaxed */
+#define SBL_DFE_G8_MIN		 -5
+#define SBL_DFE_G8_MAX		 7   /* relaxed */
+#define SBL_DFE_G9_MIN		 -4  /* constrained */
+#define SBL_DFE_G9_MAX		 6
+#define SBL_DFE_G10_MIN		 -7
+#define SBL_DFE_G10_MAX		 5
+#define SBL_DFE_G11_MIN		 -4  /* relaxed */
+#define SBL_DFE_G11_MAX		 4   /* relaxed */
+#define SBL_DFE_G12_MIN		 -3  /* relaxed */
+#define SBL_DFE_G12_MAX		 4   /* relaxed */
+#define SBL_DFE_G13_MIN		 0
+#define SBL_DFE_G13_MAX		 0
+
+/*
+ * @brief SerDes tuning parameters
+ *
+ */
+enum sbl_ctle_params {
+	CTLE_HF_OFFSET = 0,
+	CTLE_LF_OFFSET,
+	CTLE_DC_OFFSET,
+	CTLE_BW_OFFSET,
+	CTLE_GS1_OFFSET,
+	CTLE_GS2_OFFSET,
+	CTLE_SCE_OFFSET,
+	CTLE_HF_MIN_OFFSET,
+	CTLE_HF_MAX_OFFSET,
+	CTLE_LF_MIN_OFFSET,
+	CTLE_LF_MAX_OFFSET,
+	NUM_CTLE_PARAMS
+};
+
+enum sbl_ffe_params {
+	FFE_PRE2_OFFSET = 0,
+	FFE_PRE1_OFFSET,
+	FFE_POST1_OFFSET,
+	FFE_BFLF_OFFSET,
+	FFE_BFHF_OFFSET,
+	FFE_DATARATE_OFFSET,
+	FFE_SCE_OFFSET,
+	FFE_PRE1_MIN_OFFSET,
+	FFE_PRE1_MAX_OFFSET,
+	FFE_PRE2_MIN_OFFSET,
+	FFE_PRE2_MAX_OFFSET,
+	FFE_BFLF_ICAL_OFFSET,
+	FFE_POST1_MIN_OFFSET,
+	FFE_POST1_MAX_OFFSET,
+	NUM_FFE_PARAMS
+};
+
+enum sbl_dfe_params {
+	DFE_GT1_OFFSET = 0,
+	DFE_GT2_OFFSET,
+	DFE_G2_OFFSET,
+	DFE_G3_OFFSET,
+	DFE_G4_OFFSET,
+	DFE_G5_OFFSET,
+	DFE_G6_OFFSET,
+	DFE_G7_OFFSET,
+	DFE_G8_OFFSET,
+	DFE_G9_OFFSET,
+	DFE_G10_OFFSET,
+	DFE_G11_OFFSET,
+	DFE_G12_OFFSET,
+	DFE_G13_OFFSET,
+	NUM_DFE_PARAMS
+};
+
+enum sbl_rxvc_params {
+	RXVC_UOC_OFFSET = 0,
+	RXVC_UEC_OFFSET,
+	RXVC_MOC_OFFSET,
+	RXVC_MEC_OFFSET,
+	RXVC_LOC_OFFSET,
+	RXVC_LEC_OFFSET,
+	NUM_RXVC_PARAMS
+};
+
+enum sbl_rxvs_params {
+	RXVS_UOD_OFFSET = 0,
+	RXVS_UED_OFFSET,
+	RXVS_MOD_OFFSET,
+	RXVS_MED_OFFSET,
+	RXVS_LOD_OFFSET,
+	RXVS_LED_OFFSET,
+	RXVS_TOD_OFFSET,
+	RXVS_TED_OFFSET,
+	RXVS_EOD_OFFSET,
+	RXVS_EED_OFFSET,
+	RXVS_TD_OFFSET,
+	NUM_RXVS_PARAMS
+};
+
+enum sbl_rsdo_params {
+	RSDO_LE_OFFSET = 0,
+	RSDO_LO_OFFSET,
+	RSDO_ME_OFFSET,
+	RSDO_MO_OFFSET,
+	RSDO_UE_OFFSET,
+	RSDO_UO_OFFSET,
+	NUM_RSDO_PARAMS
+};
+
+enum sbl_rsdc_params {
+	RSDC_LE_OFFSET = 0,
+	RSDC_LO_OFFSET,
+	RSDC_ME_OFFSET,
+	RSDC_MO_OFFSET,
+	RSDC_UE_OFFSET,
+	RSDC_UO_OFFSET,
+	NUM_RSDC_PARAMS
+};
+
+enum sbl_rsto_params {
+	RSTO_TE_OFFSET = 0,
+	RSTO_TO_OFFSET,
+	RSTO_CE_OFFSET,
+	RSTO_CO_OFFSET,
+	NUM_RSTO_PARAMS
+};
+
+enum sbl_rstc_params {
+	RSTC_TE_OFFSET = 0,
+	RSTC_TO_OFFSET,
+	RSTC_CE_OFFSET,
+	RSTC_CO_OFFSET,
+	NUM_RSTC_PARAMS
+};
+
+enum sbl_eh_params {
+	EH_HLE_OFFSET = 0,
+	EH_HME_OFFSET,
+	EH_HUE_OFFSET,
+	EH_HLO_OFFSET,
+	EH_HMO_OFFSET,
+	EH_HUO_OFFSET,
+	EH_SEL_OFFSET,
+	EH_SEM_OFFSET,
+	EH_SEU_OFFSET,
+	EH_SOL_OFFSET,
+	EH_SOM_OFFSET,
+	EH_SOU_OFFSET,
+	NUM_EH_PARAMS
+};
+
+enum sbl_gtp_params {
+	GTP_ERTH_OFFSET = 0,
+	GTP_NCDW_OFFSET,
+	GTP_NCLD_OFFSET,
+	GTP_EOVS_OFFSET,
+	GTP_PCDW_OFFSET,
+	GTP_PDDW_OFFSET,
+	GTP_PDPD_OFFSET,
+	GTP_LMDW_OFFSET,
+	GTP_CTLF_OFFSET,
+	GTP_RXFF_OFFSET,
+	GTP_DFEF_OFFSET,
+	GTP_GTMM_OFFSET,
+	GTP_G2MM_OFFSET,
+	GTP_PCLL_OFFSET,
+	GTP_DOSP_OFFSET,
+	GTP_LPDW_OFFSET,
+	GTP_DPDW_OFFSET,
+	GTP_PCLD_OFFSET,
+	GTP_ICID_OFFSET,
+	GTP_CLMM_OFFSET,
+	GTP_CDMM_OFFSET,
+	GTP_VRFX_OFFSET,
+	GTP_PRTM_OFFSET,
+	GTP_GROP_OFFSET,
+	GTP_ICLE_OFFSET,
+	GTP_URCC_OFFSET,
+	GTP_LTFL_OFFSET,
+	GTP_DTCF_OFFSET,
+	NUM_GTP_PARAMS
+};
+
+enum sbl_dccd_params {
+	DCCD_UE_OFFSET = 0,
+	DCCD_UO_OFFSET,
+	DCCD_ME_OFFSET,
+	DCCD_MO_OFFSET,
+	DCCD_LE_OFFSET,
+	DCCD_LO_OFFSET,
+	NUM_DCCD_PARAMS
+};
+
+enum sbl_p4lv_params {
+	P4LV_X3XE_OFFSET = 0,
+	P4LV_X3XO_OFFSET,
+	P4LV_X2XE_OFFSET,
+	P4LV_X2XO_OFFSET,
+	P4LV_X1XE_OFFSET,
+	P4LV_X1XO_OFFSET,
+	P4LV_X0XE_OFFSET,
+	P4LV_X0XO_OFFSET,
+	NUM_P4LV_PARAMS
+};
+
+enum sbl_afec_params {
+	AFEC_HFPM_OFFSET = 0,
+	AFEC_HFMN_OFFSET,
+	AFEC_HFMX_OFFSET,
+	AFEC_TEMP_OFFSET,
+	AFEC_NWHF_OFFSET,
+	AFEC_NWP1_OFFSET,
+	NUM_AFEC_PARAMS
+};
+
+/*
+ * @brief Arrays of SerDes tuning parameters.
+ */
+struct sbl_serdes_params {
+	__s16 ctle[NUM_CTLE_PARAMS];  /**< CTLE tuning params */
+	__s16 ffe[NUM_FFE_PARAMS];    /**< FFE tuning params */
+	__s16 dfe[NUM_DFE_PARAMS];    /**< DFE tuning params */
+	__s16 rxvs[NUM_RXVS_PARAMS];  /**< Rx CLK Vernier Settings */
+	__s16 rxvc[NUM_RXVC_PARAMS];  /**< Rx CLK Vernier Cals */
+	__s16 rsdo[NUM_RSDO_PARAMS];  /**< Rx Sampler Data Offset */
+	__s16 rsdc[NUM_RSDC_PARAMS];  /**< Rx Sampler Data Cal */
+	__s16 rsto[NUM_RSTO_PARAMS];  /**< Rx Sampler Test/CDR Offset */
+	__s16 rstc[NUM_RSTC_PARAMS];  /**< Rx Sampler Test/CDR Cal */
+	__s16 eh[NUM_EH_PARAMS];      /**< Eye Heights */
+	__s16 gtp[NUM_GTP_PARAMS];    /**< Global Tuning Params */
+	__s16 dccd[NUM_DCCD_PARAMS];  /**< Data Channel Cal Deltas */
+	__s16 p4lv[NUM_P4LV_PARAMS];  /**< PAM4 Levels */
+	__s16 afec[NUM_AFEC_PARAMS];  /**< AFE Control */
+};
+
+/**
+ * @brief Set of tuning parameters used to configure a link, allowing the SerDes
+ *         to come up without needing to DFE tune.
+ *
+ *        tp_state_hash maps the params with the SerDes state for which they
+ *         were derived. This allows us to prevent applying saved parameters
+ *         to configurations different from which they were intended for.
+ */
+struct sbl_tuning_params {
+	__u32 magic;          /**< = SBL_TUNING_PARAM_MAGIC */
+	__u32 version;        /**< version number */
+	__u64 tp_state_hash0;  /**< Info for lp, lb, tp, lb, mt, mv */
+	__u64 tp_state_hash1;  /**< Info for ml */
+	struct sbl_serdes_params params[4];
+};
+
+
+/**
+ * @brief SerDes configuration values
+ *
+ */
+#define SBL_SC_MAX_INTR          16
+
+struct sbl_sc_values {
+	__u32 magic;                        /**< = SBL_SERDES_CONFIG_MAGIC */
+	__u32 atten;                        /**< attenuation */
+	__u32 pre;                          /**<  */
+	__u32 post;                         /**<  */
+	__u32 pre2;                         /**<  */
+	__u32 pre3;                         /**<  */
+	__u32 gs1;                          /**< gainshape 1 */
+	__u32 gs2;                          /**< gainshape 2 */
+	__u32 num_intr;                     /**< number of serdes core interrupts (serdes ops)*/
+	__u16 intr_val[SBL_SC_MAX_INTR];    /**< interrupts to perform */
+	__u16 data_val[SBL_SC_MAX_INTR];    /**< data for interrupts */
+};
+
+
+/*
+ * serdes configuration hash.
+ *
+ *   used for serdes configurations and saving tuning parameters.
+ */
+#define SBL_TPH_LP_OFFSET	0x0
+#define SBL_TPH_LB_OFFSET	0x8
+#define SBL_TPH_TP_OFFSET	0x10
+#define SBL_TPH_LM_OFFSET	0x18
+#define SBL_TPH_MT_OFFSET	0x20
+#define SBL_TPH_MV_OFFSET	0x28
+
+#define SBL_TPH_ML_OFFSET	0x0
+
+#define SBL_TPH_LP_MASK		0xffULL
+#define SBL_TPH_LB_MASK		0xffULL
+#define SBL_TPH_TP_MASK		0xffULL
+#define SBL_TPH_LM_MASK		0xffULL
+#define SBL_TPH_MT_MASK		0xffULL
+#define SBL_TPH_MV_MASK		0xffffULL
+
+#define SBL_TPH_ML_MASK		0xffffffffffffffffULL
+
+#define SBL_TPH_LP_SET(hash, val) (hash |= (((__u64)val & SBL_TPH_LP_MASK) << \
+					    SBL_TPH_LP_OFFSET))
+#define SBL_TPH_LB_SET(hash, val) (hash |= (((__u64)val & SBL_TPH_LB_MASK) << \
+					    SBL_TPH_LB_OFFSET))
+#define SBL_TPH_TP_SET(hash, val) (hash |= (((__u64)val & SBL_TPH_TP_MASK) << \
+					    SBL_TPH_TP_OFFSET))
+#define SBL_TPH_LM_SET(hash, val) (hash |= (((__u64)val & SBL_TPH_LM_MASK) << \
+					    SBL_TPH_LM_OFFSET))
+#define SBL_TPH_MT_SET(hash, val) (hash |= (((__u64)val & SBL_TPH_MT_MASK) << \
+					    SBL_TPH_MT_OFFSET))
+#define SBL_TPH_MV_SET(hash, val) (hash |= (((__u64)val & SBL_TPH_MV_MASK) << \
+					    SBL_TPH_MV_OFFSET))
+
+#define SBL_TPH_ML_SET(hash, val) (hash |= (((__u64)val & SBL_TPH_ML_MASK) << \
+					    SBL_TPH_ML_OFFSET))
+
+#endif  /* _SBL_UAPI_BASE_LINK_SERDES_H_ */
diff --git a/include/uapi/ethernet/sbl_serdes_defaults.h b/include/uapi/ethernet/sbl_serdes_defaults.h
new file mode 100644
index 000000000000..440ee8631ce7
--- /dev/null
+++ b/include/uapi/ethernet/sbl_serdes_defaults.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/* Copyright 2019-2020,2022-2024 Hewlett Packard Enterprise Development LP. All rights reserved. */
+
+#ifndef _SBL_UAPI_SBL_SERDES_DEFAULTS_H_
+#define _SBL_UAPI_SBL_SERDES_DEFAULTS_H_
+
+/**
+ * @brief Defaults for per-port SerDes attributes
+ *
+ */
+#define SBL_DFLT_OPTICAL_LOCK_DELAY                      2000
+#define SBL_DFLT_OPTICAL_LOCK_INTERVAL                    500
+#define SBL_DFLT_DFE_PRE_DELAY_PEC                          0
+#define SBL_DFLT_DFE_PRE_DELAY_AOC                          0
+#define SBL_DFLT_DFE_TIMEOUT_PEC                           40
+#define SBL_DFLT_DFE_TIMEOUT_AOC                           40
+#define SBL_DFLT_DFE_POLL_INTERVAL                        250
+#define SBL_DFLT_NRZ_PEC_MIN_EYE_HEIGHT                  0xc0
+#define SBL_DFLT_NRZ_PEC_MAX_EYE_HEIGHT                 0x200
+#define SBL_DFLT_NRZ_AOC_MIN_EYE_HEIGHT                  0xc0
+#define SBL_DFLT_NRZ_AOC_MAX_EYE_HEIGHT                 0x200
+#define SBL_DFLT_PAM4_PEC_MIN_EYE_HEIGHT                 0x10
+#define SBL_DFLT_PAM4_PEC_MAX_EYE_HEIGHT                 0x50
+#define SBL_DFLT_PAM4_AOC_MIN_EYE_HEIGHT                 0x25
+#define SBL_DFLT_PAM4_AOC_MAX_EYE_HEIGHT                 0x70
+#define SBL_DFLT_LPD_TIMEOUT                               12
+#define SBL_DFLT_LPD_POLL_INTERVAL                        333
+#define SBL_DFLT_PCAL_EYECHECK_HOLDOFF_PEC                  0
+#define SBL_DFLT_PCAL_EYECHECK_HOLDOFF_AOC                  0
+
+/**
+ * @brief Defaults SerDes attributes common for the instance
+ *
+ */
+#define SBL_DFLT_SBUS_OP_FLAGS_SLOW        (SBL_FLAG_INTERVAL_10MS | SBL_FLAG_DELAY_50US)
+#define SBL_DFLT_SBUS_OP_FLAGS_FAST        (SBL_FLAG_INTERVAL_1MS  | SBL_FLAG_DELAY_5US)
+#define SBL_DFLT_SERDES_OP_FLAGS           (SBL_FLAG_INTERVAL_1MS  | SBL_FLAG_DELAY_5US)
+#define SBL_DFLT_RX_PHASE_SLIP_CNT                        0xc
+#define SBL_DFLT_SBUS_INT_TIMEOUT                           2
+#define SBL_DFLT_SBUS_INT_POLL_INTERVAL                     1
+#define SBL_DFLT_SBUS_OP_TIMEOUT_MS                      1000
+#define SBL_DFLT_SERDES_EN_TIMEOUT                         20
+#define SBL_DFLT_SERDES_EN_POLL_INTERVAL                    1
+#define SBL_DFLT_SERDES_OP_TIMEOUT_MS                    1000
+#define SBL_DFLT_CORE_STATUS_RD_TIMEOUT                     1
+#define SBL_DFLT_CORE_STATUS_RD_POLL_INTERVAL              50
+#define SBL_DFLT_PLATFORM                   SBL_PLAT_HARDWARE
+/**
+ * @brief SerDes config table field defaults
+ *
+ */
+#define SBL_DFLT_PORT_CONFIG_ATTEN                           2
+#define SBL_DFLT_PORT_CONFIG_PRE                             0
+#define SBL_DFLT_PORT_CONFIG_POST                            0
+#define SBL_DFLT_PORT_CONFIG_PRE2                            0
+#define SBL_DFLT_PORT_CONFIG_PRE3                            0
+#define SBL_DFLT_PORT_CONFIG_GS1                             0
+#define SBL_DFLT_PORT_CONFIG_GS2                             0
+#define SBL_DFLT_PORT_CONFIG_NUM_INTR                        0
+#define SBL_DFLT_PORT_CONFIG_INTR_VAL                     { 0 }
+#define SBL_DFLT_PORT_CONFIG_DATA_VAL                     { 0 }
+
+#define SBL_DFLT_PORT_CONFIG_GS1_OPTICAL                     2
+#define SBL_DFLT_PORT_CONFIG_GS2_OPTICAL                     0
+
+#endif  /* _SBL_UAPI_SBL_SERDES_DEFAULTS_H_ */
diff --git a/include/uapi/ethernet/sbl_serdes_map.h b/include/uapi/ethernet/sbl_serdes_map.h
new file mode 100644
index 000000000000..3028d1bafa0f
--- /dev/null
+++ b/include/uapi/ethernet/sbl_serdes_map.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/* Copyright 2019-2026 Hewlett Packard Enterprise Development LP. All rights reserved. */
+
+#ifndef UAPI_SBL_SERDES_MAP_H
+#define UAPI_SBL_SERDES_MAP_H
+
+#include <linux/types.h>
+
+#include <ethernet/sbl_platform_config.h>
+#include <ethernet/sbl_sbm_constants.h>
+
+#define SBL_SERDES_MAP_NUM_PORTS SBL_NUM_PORTS
+#define SBL_SERDES_MAP_PORTS SBL_SERDES_MAP_NUM_PORTS
+#define SBL_SERDES_MAP_NUM_SBUS_RINGS SBL_NUM_SBUS_RINGS
+
+struct serdes_info {
+	/* Autogenerated values */
+	__s32 device;
+	__s32 sbus_ring;
+	__s32 rx_addr;
+	__s32 tx_lane_source;
+	__s32 rx_lane_source;
+	__u8 txinv;
+	__u8 rxinv;
+};
+
+struct port_info {
+	/* Autogenerated values */
+	__s32 rx_an_swizzle;
+	__s32 tx_an_swizzle;
+	struct serdes_info serdes[SBL_SERDES_LANES_PER_PORT];
+};
+
+struct sbl_switch_info {
+	__s32 num_ports;
+	__s32 num_serdes; /* per port */
+	__s32 num_sbus_rings;
+	struct port_info ports[SBL_SERDES_MAP_NUM_PORTS];
+};
+
+#endif /* UAPI_SBL_SERDES_MAP_H */
diff --git a/include/uapi/ethernet/sbl_serdes_map_init.h b/include/uapi/ethernet/sbl_serdes_map_init.h
new file mode 100644
index 000000000000..b108a6547c42
--- /dev/null
+++ b/include/uapi/ethernet/sbl_serdes_map_init.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+/* Copyright 2019-2026 Hewlett Packard Enterprise Development LP */
+
+#ifndef SBL_SERDES_MAP_INIT_H
+#define SBL_SERDES_MAP_INIT_H
+
+#include <ethernet/sbl_serdes_map.h>
+
+#define SBL_CASSINI_BRAZOS_SW_INFO_INITIALIZER \
+{ \
+	.num_ports = SBL_SERDES_MAP_PORTS, \
+	.num_serdes = SBL_SERDES_LANES_PER_PORT, \
+	.num_sbus_rings = SBL_SERDES_MAP_NUM_SBUS_RINGS, \
+	.ports = { \
+	{ /* 0x00 */ \
+		.rx_an_swizzle = 3, \
+		.tx_an_swizzle = 1, \
+		.serdes = { \
+			{ .device = 0, .sbus_ring = 0, .rx_addr = 0x28, .tx_lane_source = 1, .txinv = 1, .rx_lane_source = 2, .rxinv = 0 }, \
+			{ .device = 0, .sbus_ring = 0, .rx_addr = 0x29, .tx_lane_source = 0, .txinv = 1, .rx_lane_source = 3, .rxinv = 0 }, \
+			{ .device = 0, .sbus_ring = 0, .rx_addr = 0x2A, .tx_lane_source = 2, .txinv = 1, .rx_lane_source = 1, .rxinv = 0 }, \
+			{ .device = 0, .sbus_ring = 0, .rx_addr = 0x2B, .tx_lane_source = 3, .txinv = 1, .rx_lane_source = 0, .rxinv = 0 }, \
+			} \
+		} \
+	} \
+}
+
+#define SBL_CASSINI_NIC0_SW_INFO_INITIALIZER \
+{ \
+	.num_ports = SBL_SERDES_MAP_PORTS, \
+	.num_serdes = SBL_SERDES_LANES_PER_PORT, \
+	.num_sbus_rings = SBL_SERDES_MAP_NUM_SBUS_RINGS, \
+	.ports = { \
+	{ /* 0x00 */ \
+		.rx_an_swizzle = 3, \
+		.tx_an_swizzle = 3, \
+		.serdes = { \
+			{ .device = 0, .sbus_ring = 0, .rx_addr = 0x28, .tx_lane_source = 3, .txinv = 1, .rx_lane_source = 3, .rxinv = 1 }, \
+			{ .device = 0, .sbus_ring = 0, .rx_addr = 0x29, .tx_lane_source = 2, .txinv = 1, .rx_lane_source = 2, .rxinv = 1 }, \
+			{ .device = 0, .sbus_ring = 0, .rx_addr = 0x2A, .tx_lane_source = 1, .txinv = 1, .rx_lane_source = 1, .rxinv = 1 }, \
+			{ .device = 0, .sbus_ring = 0, .rx_addr = 0x2B, .tx_lane_source = 0, .txinv = 1, .rx_lane_source = 0, .rxinv = 1 }, \
+			} \
+		} \
+	} \
+}
+
+#define SBL_CASSINI_NIC1_SW_INFO_INITIALIZER \
+{ \
+	.num_ports = SBL_SERDES_MAP_PORTS, \
+	.num_serdes = SBL_SERDES_LANES_PER_PORT, \
+	.num_sbus_rings = SBL_SERDES_MAP_NUM_SBUS_RINGS, \
+	.ports = { \
+	{ /* 0x00 */ \
+		.rx_an_swizzle = 0, \
+		.tx_an_swizzle = 0, \
+		.serdes = { \
+			{ .device = 0, .sbus_ring = 1, .rx_addr = 0x28, .tx_lane_source = 0, .txinv = 1, .rx_lane_source = 0, .rxinv = 1 }, \
+			{ .device = 0, .sbus_ring = 1, .rx_addr = 0x29, .tx_lane_source = 1, .txinv = 1, .rx_lane_source = 1, .rxinv = 1 }, \
+			{ .device = 0, .sbus_ring = 1, .rx_addr = 0x2A, .tx_lane_source = 2, .txinv = 1, .rx_lane_source = 2, .rxinv = 1 }, \
+			{ .device = 0, .sbus_ring = 1, .rx_addr = 0x2B, .tx_lane_source = 3, .txinv = 1, .rx_lane_source = 3, .rxinv = 1 }, \
+			} \
+		} \
+	} \
+}
+#endif /* SBL_SERDES_MAP_INIT_H */

-- 
2.56.0


^ permalink raw reply	[flat|nested] 25+ messages in thread
* [PATCH 03/23] net: hpe: sbl: add the core instance and configuration layer
  2026-10-30 20:58 [PATCH 00/23] Subject: [PATCH net-next 00/23] net/hpe: add HPE Slingshot NIC drivers Doug Ledford
  2026-10-30 20:58 ` [PATCH 01/23] net: hpe: ss1: add the Cassini headers Doug Ledford
  2026-10-30 20:58 ` [PATCH 02/23] net: hpe: sbl: add the Slingshot Base Link headers Doug Ledford
@ 2026-10-30 20:58 ` Doug Ledford
  2026-10-30 20:59 ` [PATCH 04/23] net: hpe: sbl: add the SerDes layer Doug Ledford
                   ` (20 subsequent siblings)
  23 siblings, 0 replies; 25+ messages in thread
From: Doug Ledford @ 2026-10-30 20:58 UTC (permalink / raw)
  To: Slingshot Open Source Team, Nathan Chancellor, Nicolas Schier,
	Richard Cochran, Andrew Lunn, David S. Miller, Eric Dumazet,
	Jakub Kicinski, Paolo Abeni, Sumit Semwal, Christian König,
	Guenter Roeck
  Cc: linux-kernel, netdev, linux-kbuild, Doug Ledford, Iraimani P,
	Mamila Santosh

Add the SBL instance management: allocation and teardown of an SBL
instance for a NIC, the configuration list, timers, debug helpers,
and the NIC specific module glue.  Everything else in SBL hangs off
the instance created here.

checkpatch --strict (100 columns) still reports the following in this
patch. They need coordination with the internal repositories this code
is maintained in and will be fixed in V2:
- WARNING: LONG_LINE (8), ALLOC_WITH_SIZEOF (3), TYPO_SPELLING (1)
- CHECK: ALLOC_SIZEOF_STRUCT (4), BRACES (2), PARENTHESIS_ALIGNMENT (2),
  MACRO_ARG_PRECEDENCE (1), MACRO_ARG_REUSE (1), OPEN_ENDED_LINE (1)

Co-developed-by: Iraimani P <iraimani.pavadai@hpe.com>
Signed-off-by: Iraimani P <iraimani.pavadai@hpe.com>
Co-developed-by: Mamila Santosh <santosh-kumar.mamila@hpe.com>
Signed-off-by: Mamila Santosh <santosh-kumar.mamila@hpe.com>
Signed-off-by: Doug Ledford <doug.ledford@hpe.com>
---
 drivers/net/ethernet/hpe/sbl/sbl_debug.c      | 167 ++++++++
 drivers/net/ethernet/hpe/sbl/sbl_inst.c       | 529 ++++++++++++++++++++++++++
 drivers/net/ethernet/hpe/sbl/sbl_inst_nic.c   |  70 ++++
 drivers/net/ethernet/hpe/sbl/sbl_internal.c   |  23 ++
 drivers/net/ethernet/hpe/sbl/sbl_misc.c       | 505 ++++++++++++++++++++++++
 drivers/net/ethernet/hpe/sbl/sbl_module_nic.c | 132 +++++++
 drivers/net/ethernet/hpe/sbl/sbl_test.c       | 406 ++++++++++++++++++++
 drivers/net/ethernet/hpe/sbl/sbl_timers.c     | 228 +++++++++++
 8 files changed, 2060 insertions(+)

diff --git a/drivers/net/ethernet/hpe/sbl/sbl_debug.c b/drivers/net/ethernet/hpe/sbl/sbl_debug.c
new file mode 100644
index 000000000000..2ddc07e6ab03
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sbl/sbl_debug.c
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* Copyright 2019-2022 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+
+#include <linux/hpe/sbl/sbl.h>
+#include <linux/hpe/sbl/sbl_kconfig.h>
+
+#include "sbl_internal.h"
+
+/**
+ * sbl_debug_clear_config() - Clear debug config
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ *
+ * Set debug_config to 0
+ */
+void sbl_debug_clear_config(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+
+	atomic_set(&link->debug_config, 0);
+}
+EXPORT_SYMBOL(sbl_debug_clear_config);
+
+/**
+ * sbl_debug_update_config() - Update debug config
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ * @clear_flags: Flag which is used to clear a config
+ * @set_flags: Flag which is used to set a config
+ *
+ * A 'new' value is picked based on flags provided.
+ * debug_config will have 'new' value if debug_old
+ * and 'old' are the same.
+ */
+void sbl_debug_update_config(struct sbl_inst *sbl, int port_num, u32 clear_flags, u32 set_flags)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	u32 old;
+	u32 new;
+
+	do {
+		old = atomic_read(&link->debug_config);
+		new = (old & ~clear_flags) | set_flags;
+	} while (atomic_cmpxchg(&link->debug_config, old, new) != old);
+}
+EXPORT_SYMBOL(sbl_debug_update_config);
+
+/**
+ * sbl_debug_get_config() - Get value of debug config
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ * @config: param used to get the value of the config
+ *
+ * 'config' will have debug_config value
+ *
+ * Return: 0 on success, negative error code on failure
+ */
+int sbl_debug_get_config(struct sbl_inst *sbl, int port_num, u32 *config)
+{
+	struct sbl_link *link = sbl->link + port_num;
+
+	if (!config)
+		return -EINVAL;
+
+	*config = atomic_read(&link->debug_config);
+
+	return 0;
+}
+EXPORT_SYMBOL(sbl_debug_get_config);
+
+bool sbl_debug_option(struct sbl_inst *sbl, int port_num, u32 flags)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	bool flag_set;
+
+	flag_set = atomic_read(&link->debug_config) & flags;
+
+	return flag_set;
+}
+
+#ifdef CONFIG_SYSFS
+int sbl_debug_sysfs_sprint(struct sbl_inst *sbl, int port_num, char *buf, size_t size)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	u32 debug_config = atomic_read(&link->debug_config);
+	int s = 0;
+
+	if (!debug_config)
+		return 0;
+
+	s += scnprintf(buf + s, size - s, "base link debug: ");
+	if (debug_config & SBL_DEBUG_TRACE_LINK_DOWN)
+		s += scnprintf(buf + s, size - s, "async-down ");
+	if (debug_config & SBL_DEBUG_IGNORE_HISER)
+		s += scnprintf(buf + s, size - s, "ignore-hiser ");
+	if (debug_config & SBL_DEBUG_INHIBIT_CLEANUP)
+		s += scnprintf(buf + s, size - s, "inhibit-cleanup ");
+	if (debug_config & SBL_DEBUG_INHIBIT_SPLL_RESET)
+		s += scnprintf(buf + s, size - s, "inhibit-spll-reset ");
+
+	if (debug_config & SBL_DEBUG_BAD_PARAM_1)
+		s += scnprintf(buf + s, size - s, "bad-param-1 ");
+	if (debug_config & SBL_DEBUG_BAD_PARAM_2)
+		s += scnprintf(buf + s, size - s, "bad-param-2 ");
+	if (debug_config & SBL_DEBUG_INHIBIT_RELOAD_FW)
+		s += scnprintf(buf + s, size - s, "inhibit-reload-fw ");
+	if (debug_config & SBL_DEBUG_FORCE_RELOAD_FW)
+		s += scnprintf(buf + s, size - s, "force-reload-fw ");
+
+	if (debug_config & SBL_DEBUG_FORCE_MAX_EFFORT)
+		s += scnprintf(buf + s, size - s, "max-effort ");
+	if (debug_config & SBL_DEBUG_FORCE_MED_EFFORT)
+		s += scnprintf(buf + s, size - s, "med-effort ");
+	if (debug_config & SBL_DEBUG_FORCE_MIN_EFFORT)
+		s += scnprintf(buf + s, size - s, "min-effort ");
+	if (debug_config & SBL_DEBUG_INHIBIT_USE_SAVED_TP)
+		s += scnprintf(buf + s, size - s, "inhibit-use-saved-tp ");
+
+	if (debug_config & SBL_DEBUG_FORCE_PRECODING_ON)
+		s += scnprintf(buf + s, size - s, "precoding-on ");
+	if (debug_config & SBL_DEBUG_FORCE_PRECODING_OFF)
+		s += scnprintf(buf + s, size - s, "precoding-off ");
+	if (debug_config & SBL_DEBUG_ALLOW_MEDIA_BAD_MODE)
+		s += scnprintf(buf + s, size - s, "allow-media-bad-mode ");
+	if (debug_config & SBL_DEBUG_ALLOW_MEDIA_BAD_LEN)
+		s += scnprintf(buf + s, size - s, "allow-media-bad-len ");
+
+	if (debug_config & SBL_DEBUG_INHIBIT_PCAL)
+		s += scnprintf(buf + s, size - s, "inhibit-pcal ");
+	if (debug_config & SBL_DEBUG_INHIBIT_RELOAD_SBM_FW)
+		s += scnprintf(buf + s, size - s, "inhibit-reload-sbm-fw ");
+	if (debug_config & SBL_DEBUG_FORCE_RELOAD_SBM_FW)
+		s += scnprintf(buf + s, size - s, "force-reload-sbm-fw ");
+	if (debug_config & SBL_DEBUG_DISABLE_AN_NEXT_PAGES)
+		s += scnprintf(buf + s, size - s, "disable-an-next-pages ");
+
+	if (debug_config & SBL_DEBUG_KEEP_SERDES_UP)
+		s += scnprintf(buf + s, size - s, "keep-serdes-up ");
+	if (debug_config & SBL_DEBUG_SERDES_MAP_DELAY)
+		s += scnprintf(buf + s, size - s, "serdes-map-delay ");
+	if (debug_config & SBL_DEBUG_FORCE_RELOAD_SERDES_FW)
+		s += scnprintf(buf + s, size - s, "force-reload-serdes-fw ");
+	if (debug_config & SBL_DEBUG_ALLOW_LOOP_TIME_FAIL)
+		s += scnprintf(buf + s, size - s, "allow-loop-time-fail ");
+	if (debug_config & SBL_DEBUG_IGNORE_ALIGN)
+		s += scnprintf(buf + s, size - s, "ignore-align ");
+	if (debug_config & SBL_DEBUG_TRACE_PML_INT)
+		s += scnprintf(buf + s, size - s, "pml-interrupt ");
+	if (debug_config & SBL_DEBUG_REMOTE_FAULT_RECOVERY)
+		s += scnprintf(buf + s, size - s, "remote-fault-recovery ");
+
+	if (debug_config & SBL_DEBUG_DEV0)
+		s += scnprintf(buf + s, size - s, "dev0 ");
+	if (debug_config & SBL_DEBUG_TEST)
+		s += scnprintf(buf + s, size - s, "test ");
+
+	s += scnprintf(buf + s, size - s, "\n");
+
+	return s;
+}
+#endif
diff --git a/drivers/net/ethernet/hpe/sbl/sbl_inst.c b/drivers/net/ethernet/hpe/sbl/sbl_inst.c
new file mode 100644
index 000000000000..af55ac619031
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sbl/sbl_inst.c
@@ -0,0 +1,529 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* Copyright 2019-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+
+#include <linux/hpe/sbl/sbl.h>
+#include <linux/hpe/sbl/sbl_fec.h>
+#include <linux/hpe/sbl/sbl_kconfig.h>
+
+#include <uapi/ethernet/sbl_sbm_constants.h>
+
+#include "sbl_constants.h"
+#include "sbl_serdes.h"
+#include "sbl_config_list.h"
+#include "sbl_serdes_map.h"
+#include "sbl_pml_fn.h"
+#include "sbl_internal.h"
+
+static atomic_t sbl_inst_id = ATOMIC_INIT(-1);
+
+static struct sbl_link *sbl_create_link_db(struct sbl_switch_info *switch_info)
+{
+	int i;
+	int j;
+	int err;
+	struct sbl_link *link;
+
+	link = kcalloc(switch_info->num_ports, sizeof(struct sbl_link), GFP_KERNEL);
+	if (!link)
+		return ERR_PTR(-ENOMEM);
+
+	for (i = 0; i < switch_info->num_ports; ++i) {
+		err = sbl_link_counters_init(link + i);
+		if (err)
+			goto out_free_sbl_link_counters;
+
+		link[i].num = i;
+		link[i].mconfigured = false;
+		link[i].blconfigured = false;
+		atomic_set(&link[i].debug_config, 0);
+		/* Initialize blattr with default values; these are applied on first config */
+		link[i].blattr.pec.an_mode   = SBL_AN_MODE_OFF;
+		link[i].blattr.link_mode     = SBL_LINK_MODE_BS_200G;
+		link[i].blattr.loopback_mode = SBL_LOOPBACK_MODE_OFF;
+		link[i].blattr.llr_mode      = SBL_LLR_MODE_OFF;
+		link[i].blattr.ifg_config    = SBL_IFG_CONFIG_HPC;
+		link[i].sstate = SBL_SERDES_STATUS_DOWN;
+		link[i].serr = 0;
+		link[i].blstate = SBL_BASE_LINK_STATUS_UNCONFIGURED;
+		link[i].blerr = 0;
+		link[i].link_info = 0;
+		link[i].link_mode     = SBL_LINK_MODE_INVALID;
+		link[i].ifg_config    = SBL_IFG_CONFIG_INVALID;
+		link[i].loopback_mode = SBL_LOOPBACK_MODE_INVALID;
+		link[i].llr_mode      = SBL_LLR_MODE_INVALID;
+		link[i].llr_loop_time = 0;
+		link[i].pcs_config = false;
+		link[i].intr_err_flgs = 0ULL;
+		link[i].an_rx_count = 0;
+		link[i].an_tx_count = 0;
+		link[i].an_timeout_active = false;
+		init_completion(&link[i].an_hw_change);
+		link[i].lp_subtype = SBL_LP_SUBTYPE_INVALID;
+		link[i].tuning_params.tp_state_hash0 = 0;
+		link[i].tuning_params.tp_state_hash1 = 0;
+		link[i].last_start_jiffy = jiffies;
+		link[i].start_cancelled = false;
+		link[i].dfe_tune_count = 0;
+		link[i].optical_delay_active = false;
+		link[i].dfe_predelay_active = false;
+		link[i].pcal_running = false;
+		link[i].tune_param_oob_count = 0;
+		link[i].reload_serdes_fw = false;
+		link[i].pcs_recovery_flag = false;
+		link[i].pml_recovery.started = false;
+		link[i].pml_recovery.rl_window_start = 0;
+		sbl_pml_recovery_init(&link[i].pml_recovery);
+		link[i].fec_discard_time = 0;
+		link[i].fec_discard_type = SBL_FEC_DISCARD_TYPE_INVALID;
+
+		spin_lock_init(&link[i].lock);
+		spin_lock_init(&link[i].timeout_lock);
+		spin_lock_init(&link[i].pcs_recovery_lock);
+		spin_lock_init(&link[i].is_degraded_lock);
+		spin_lock_init(&link[i].fec_discard_lock);
+		mutex_init(&link[i].busy_mtx);
+		mutex_init(&link[i].serdes_mtx);
+		mutex_init(&link[i].tuning_params_mtx);
+	}
+
+	return link;
+
+out_free_sbl_link_counters:
+	for (j = 0; j < i; ++j)
+		sbl_link_counters_term(link + j);
+	kfree(link);
+	return ERR_PTR(-ENOMEM);
+}
+
+/* All operations must be supplied or SBL cannot function */
+#define SBL_SETUP_OP_TBL_ENTRY(e)  \
+	if (ops->e) \
+		sbl->ops.e = ops->e; \
+	else { \
+		sbl_dev_err(sbl->dev, "missing ops tbl entry " #e); \
+		error = true; \
+	}
+
+static int sbl_setup_ops(struct sbl_inst *sbl, const struct sbl_ops *ops)
+{
+	bool error = false;
+
+	if (!ops) {
+		sbl_dev_err(sbl->dev, "missing ops table\n");
+		return -EINVAL;
+	}
+
+	SBL_SETUP_OP_TBL_ENTRY(sbl_read32);
+	SBL_SETUP_OP_TBL_ENTRY(sbl_read64);
+	SBL_SETUP_OP_TBL_ENTRY(sbl_write32);
+	SBL_SETUP_OP_TBL_ENTRY(sbl_write64);
+	SBL_SETUP_OP_TBL_ENTRY(sbl_sbus_op);
+	SBL_SETUP_OP_TBL_ENTRY(sbl_sbus_op_reset);
+	SBL_SETUP_OP_TBL_ENTRY(sbl_is_fabric_link);
+	SBL_SETUP_OP_TBL_ENTRY(sbl_get_max_frame_size);
+	SBL_SETUP_OP_TBL_ENTRY(sbl_pml_install_intr_handler);
+	SBL_SETUP_OP_TBL_ENTRY(sbl_pml_enable_intr_handler);
+	SBL_SETUP_OP_TBL_ENTRY(sbl_pml_disable_intr_handler);
+	SBL_SETUP_OP_TBL_ENTRY(sbl_pml_remove_intr_handler);
+	SBL_SETUP_OP_TBL_ENTRY(sbl_async_alert);
+
+	if (error)
+		return -ENOENT;
+	else
+		return 0;
+}
+
+static int sbl_setup_serdes_configs(struct sbl_inst *sbl)
+{
+	struct sbl_serdes_config default_config;
+
+	spin_lock_init(&sbl->serdes_config_lock);
+	INIT_LIST_HEAD(&sbl->serdes_config_list);
+
+	default_config = (struct sbl_serdes_config)SBL_SERDES_CONFIG_INITIALIZER;
+
+	return sbl_serdes_add_config(sbl, default_config.tp_state_mask0,
+					default_config.tp_state_mask1,
+					default_config.tp_state_match0,
+					default_config.tp_state_match1,
+					default_config.port_mask,
+					default_config.serdes_mask,
+					&default_config.vals, true);
+}
+
+static int sbl_fec_init(struct sbl_inst *sbl)
+{
+	int i, j;
+	struct sbl_link *link;
+
+	for (i = 0; i < SBL_NUM_PORTS; ++i) {
+		link = sbl->link + i;
+
+		link->fec_data = kzalloc(sizeof(struct fec_data), GFP_KERNEL);
+
+		if (!link->fec_data)
+			goto out_free_fec_data;
+
+		link->fec_data->fec_prmts = kzalloc(sizeof(struct sbl_fec), GFP_KERNEL);
+
+		if (!link->fec_data->fec_prmts)
+			goto out_free_fec_data;
+
+		link->fec_data->fec_prmts->fec_curr_cnts = &link->fec_data->fec_prmts->fec_cntrs[0];
+		link->fec_data->fec_prmts->fec_prev_cnts = &link->fec_data->fec_prmts->fec_cntrs[1];
+		link->fec_data->fec_prmts->fec_rates = kzalloc(sizeof(struct sbl_pcs_fec_cntrs), GFP_KERNEL);
+		if (!link->fec_data->fec_prmts->fec_rates)
+			goto out_free_fec_data;
+
+		spin_lock_init(&link->fec_data->fec_prmts->fec_cnt_lock);
+
+		link->fec_data->fec_prmts->fec_ucw_thresh = 0;
+		link->fec_data->fec_prmts->fec_ucw_up_thresh_adj = 100;
+		link->fec_data->fec_prmts->fec_ucw_down_thresh_adj = 100;
+		link->fec_data->fec_prmts->fec_ucw_hwm = 0;
+		link->fec_data->fec_prmts->fec_ccw_thresh = 0;
+		link->fec_data->fec_prmts->fec_ccw_up_thresh_adj = 100;
+		link->fec_data->fec_prmts->fec_ccw_down_thresh_adj = 100;
+		link->fec_data->fec_prmts->fec_stp_ccw_thresh = 0;
+		link->fec_data->fec_prmts->fec_stp_ccw_up_thresh_adj = 100;
+		link->fec_data->fec_prmts->fec_ccw_hwm = 0;
+		link->fec_data->fec_prmts->fecl_warn = 0;
+
+		spin_lock_init(&link->fec_data->fec_prmts->fec_cw_lock);
+		timer_setup(&link->fec_data->fec_timer, sbl_fec_timer, 0);
+		link->fec_data->sbl		= sbl;
+		link->fec_data->port_num = i;
+
+		INIT_WORK(&link->fec_data->fec_timer_work, sbl_fec_timer_work);
+	}
+
+	return 0;
+
+out_free_fec_data:
+	for (j = 0; j <= i; ++j) {
+		link = sbl->link + j;
+		if (link->fec_data) {
+			if (link->fec_data->fec_prmts) {
+				kfree(link->fec_data->fec_prmts->fec_rates);
+				kfree(link->fec_data->fec_prmts);
+			}
+			kfree(link->fec_data);
+			link->fec_data = NULL;
+		}
+	}
+	return -ENOMEM;
+}
+
+/**
+ * sbl_get_version() - Get SBL Version
+ * @major: Major version number
+ * @minor: Minor version number
+ * @inc: Incremented version
+ */
+void sbl_get_version(int *major, int *minor, int *inc)
+{
+	if (major)
+		*major = SBL_VERSION_MAJOR;
+	if (minor)
+		*minor = SBL_VERSION_MINOR;
+	if (inc)
+		*inc = SBL_VERSION_INC;
+}
+EXPORT_SYMBOL(sbl_get_version);
+
+/**
+ * sbl_get_num_sbus_rings() - Get the number of sbus rings
+ * @sbl: A slingshot base link device instance
+ *
+ * Return: number of sbus rings
+ */
+int sbl_get_num_sbus_rings(struct sbl_inst *sbl)
+{
+	int err;
+
+	err = sbl_validate_instance(sbl);
+	if (err)
+		return err;
+
+	return sbl->switch_info->num_sbus_rings;
+}
+EXPORT_SYMBOL(sbl_get_num_sbus_rings);
+
+/**
+ * sbl_new_instance() - Create new sbl instance
+ * @accessor: Determined by the client driver, Which acts
+ *            as abstraction to perform low-level operation
+ * @pci_accessor: Points to bus/vendor specific PCI access
+ * @ops: callback function operations
+ * @init_attr: Pointer to struct sbl_init_attr
+ *
+ * This function initializes multiple members which
+ * helps to create new sbl instance
+ *
+ * Return: sbl instance on success, negative error code on failure
+ */
+struct sbl_inst *sbl_new_instance(void *accessor, void *pci_accessor,
+				  const struct sbl_ops *ops,
+				  struct sbl_init_attr *init_attr)
+{
+	struct sbl_inst *sbl;
+	struct device *dev = sbl_get_device();
+	int err;
+	int i;
+
+	if (!accessor || !pci_accessor || !ops || !init_attr) {
+		err = -EINVAL;
+		goto out;
+	}
+	if (init_attr->magic != SBL_INIT_ATTR_MAGIC) {
+		err = -EINVAL;
+		goto out;
+	}
+
+	sbl = kzalloc(sizeof(struct sbl_inst), GFP_KERNEL);
+	if (!sbl) {
+		err = -ENOMEM;
+		goto out;
+	}
+
+	sbl->magic = SBL_MAGIC;
+	spin_lock_init(&sbl->name_lock);
+	sbl->id = atomic_inc_return(&sbl_inst_id);
+	sbl->dev = dev;
+	sbl->accessor = accessor;
+	sbl->pci_accessor = pci_accessor;
+	sbl->sbus_op_flags = SBL_DFLT_SBUS_OP_FLAGS_SLOW;
+
+	sbl->workq = alloc_workqueue("%s", WQ_MEM_RECLAIM | WQ_UNBOUND, 0, "sbl-fec");
+	if (!sbl->workq) {
+		err = -ENOMEM;
+		goto out_free_sbl;
+	}
+
+	/* Initialize the hardware-specific map */
+	err = sbl_switch_info_get(sbl, init_attr);
+
+	if (err)
+		goto out_free;
+
+	sbl_dev_info(dev, "new instance (%d): %d ports x %d serdes\n", sbl->id,
+		     sbl->switch_info->num_ports, sbl->switch_info->num_serdes);
+
+	sbl->sbus_ring_mtx =
+		kcalloc(sbl->switch_info->num_sbus_rings, sizeof(struct mutex), GFP_KERNEL);
+	if (!sbl->sbus_ring_mtx) {
+		err = -ENOMEM;
+		goto out_free;
+	}
+
+	sbl->sbm_fw_mtx =
+		kzalloc(sbl->switch_info->num_sbus_rings * sizeof(struct mutex), GFP_KERNEL);
+	if (!sbl->sbm_fw_mtx) {
+		err = -ENOMEM;
+		goto out_free_sbus_mtx;
+	}
+
+	sbl->reload_sbm_fw =
+		kzalloc(sbl->switch_info->num_sbus_rings * sizeof(bool), GFP_KERNEL);
+	if (!sbl->reload_sbm_fw) {
+		err = -ENOMEM;
+		goto out_free_sbm_fw_mtx;
+	}
+
+	sbl->sbm_fw_reload_count =
+		kzalloc(sbl->switch_info->num_sbus_rings * sizeof(atomic_t), GFP_KERNEL);
+	if (!sbl->sbm_fw_reload_count) {
+		err = -ENOMEM;
+		goto out_free_reload_sbm;
+	}
+
+	for (i = 0; i < sbl->switch_info->num_sbus_rings; ++i) {
+		mutex_init(&sbl->sbus_ring_mtx[i]);
+		mutex_init(&sbl->sbm_fw_mtx[i]);
+		sbl->reload_sbm_fw[i] = false;
+		atomic_set(&sbl->sbm_fw_reload_count[i], 0);
+	}
+
+	/* setup the op table */
+	err = sbl_setup_ops(sbl, ops);
+	if (err) {
+		sbl_dev_err(sbl->dev, "op table setup failed [%d]\n", err);
+		goto out_free_sbm_fw_reload_count;
+	}
+
+	/* setup serdes lock, configuration list and add default */
+	err = sbl_setup_serdes_configs(sbl);
+	if (err) {
+		sbl_dev_err(sbl->dev, "serdes setup failed [%d]\n", err);
+		goto out_free_sbm_fw_reload_count;
+	}
+
+	/* create link database */
+	sbl->link = sbl_create_link_db(sbl->switch_info);
+	if (IS_ERR(sbl->link)) {
+		err = PTR_ERR(sbl->link);
+		sbl_dev_err(sbl->dev, "link db creation failed [%d]\n", err);
+		goto out_free_configs;
+	}
+
+	err = sbl_fec_init(sbl);
+	if (err) {
+		sbl_dev_err(sbl->dev, "fec init failed [%d]\n", err);
+		goto out_free_link;
+	}
+
+	for (i = 0; i < sbl->switch_info->num_ports; ++i) {
+		/* ensure no valid saved tuning params */
+		sbl_serdes_invalidate_tuning_params(sbl, i);
+
+		/* set default values for PML */
+		sbl_pml_set_defaults(sbl, i);
+	}
+
+	return sbl;
+
+out_free_link:
+	for (i = 0; i < sbl->switch_info->num_ports; ++i)
+		sbl_link_counters_term(sbl->link + i);
+	kfree(sbl->link);
+out_free_configs:
+	sbl_serdes_clear_all_configs(sbl, true /* clear default */);
+out_free_sbm_fw_reload_count:
+	kfree(sbl->sbm_fw_reload_count);
+out_free_reload_sbm:
+	kfree(sbl->reload_sbm_fw);
+out_free_sbm_fw_mtx:
+	kfree(sbl->sbm_fw_mtx);
+out_free_sbus_mtx:
+	kfree(sbl->sbus_ring_mtx);
+out_free:
+	destroy_workqueue(sbl->workq);
+out_free_sbl:
+	kfree(sbl);
+out:
+	return ERR_PTR(err);
+}
+EXPORT_SYMBOL(sbl_new_instance);
+
+/**
+ * sbl_delete_instance() - Delete sbl instance
+ * @sbl: A slingshot base link device instance
+ *
+ * This function clears the config and frees all
+ * memory associated with an SBL.
+ *
+ * Return: 0 on success, negative error code on failure
+ */
+int sbl_delete_instance(struct sbl_inst *sbl)
+{
+	struct sbl_link *link;
+	int err;
+	int i;
+
+	err = sbl_validate_instance(sbl);
+	if (err)
+		return err;
+
+	for (i = 0; i < sbl->switch_info->num_ports; ++i) {
+		link = sbl->link + i;
+		if (!link->intr_err_flgs)
+			continue;
+		err = sbl_pml_disable_intr_handler(sbl, i, link->intr_err_flgs);
+		if (err)
+			return err;
+		err = sbl_pml_remove_intr_handler(sbl, i);
+		if (err)
+			return err;
+	}
+
+	for (i = 0; i < sbl->switch_info->num_ports; ++i)
+		sbl_pml_recovery_cancel(sbl, i);
+	for (i = 0; i < SBL_NUM_PORTS; ++i) {
+		link = sbl->link + i;
+
+		timer_shutdown_sync(&link->fec_data->fec_timer);
+		cancel_work_sync(&link->fec_data->fec_timer_work);
+		kfree(link->fec_data->fec_prmts->fec_rates);
+		link->fec_data->fec_prmts->fec_rates = NULL;
+		kfree(link->fec_data->fec_prmts);
+		link->fec_data->fec_prmts = NULL;
+		kfree(link->fec_data);
+		link->fec_data = NULL;
+	}
+
+	for (i = 0; i < sbl->switch_info->num_ports; ++i)
+		sbl_link_counters_term(sbl->link + i);
+
+	kfree(sbl->link);
+	sbl_serdes_clear_all_configs(sbl, true /* clear default */);
+	kfree(sbl->sbm_fw_reload_count);
+	kfree(sbl->reload_sbm_fw);
+	kfree(sbl->sbm_fw_mtx);
+	kfree(sbl->sbus_ring_mtx);
+	flush_workqueue(sbl->workq);
+	destroy_workqueue(sbl->workq);
+	sbl->magic = 0;   /* paranoia */
+	kfree(sbl);
+
+	return 0;
+}
+EXPORT_SYMBOL(sbl_delete_instance);
+
+/**
+ * sbl_initialise_instance() - Initialize the instance
+ * @sbl: A slingshot base link device instance
+ * @attr: Pointer to struct sbl_instance_attr
+ *
+ * This function loads required firmware to SBM/Serdes as part of
+ * Initialising the base link instance
+ *
+ * Return: 0 on success, negative error code on failure
+ */
+int sbl_initialise_instance(struct sbl_inst *sbl, struct sbl_instance_attr *attr)
+{
+	unsigned long flags;
+	int err;
+
+	if (!attr)
+		return -EINVAL;
+
+	if (attr->magic != SBL_INSTANCE_ATTR_MAGIC)
+		return -EINVAL;
+
+	spin_lock_irqsave(&sbl->name_lock, flags);
+	memcpy(&sbl->iattr, attr, sizeof(struct sbl_instance_attr));
+	spin_unlock_irqrestore(&sbl->name_lock, flags);
+
+	/* load the required firmware
+	 * force load all ports if serdes firmware validation fails
+	 */
+	err = sbl_serdes_load(sbl, SBL_ALL_PORTS, false);
+	if (err) {
+		sbl_dev_err(sbl->dev, "initial serdes fw load failed [%d]", err);
+		return err;
+	}
+	sbl_dev_err(sbl->dev, "serdes fw loaded");
+
+	return 0;
+
+}
+EXPORT_SYMBOL(sbl_initialise_instance);
+
+/**
+ * sbl_restore_instance() - Restoring instance
+ * @sbl: A slingshot base link device instance
+ *
+ * Return: negative error code on failure
+ */
+int sbl_restore_instance(struct sbl_inst *sbl)
+{
+	sbl_dev_err(sbl->dev, "Restoring an instance not supported (yet)\n");
+	return -EOPNOTSUPP;
+}
+EXPORT_SYMBOL(sbl_restore_instance);
diff --git a/drivers/net/ethernet/hpe/sbl/sbl_inst_nic.c b/drivers/net/ethernet/hpe/sbl/sbl_inst_nic.c
new file mode 100644
index 000000000000..cc3d3b570fc9
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sbl/sbl_inst_nic.c
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+
+#include <linux/hpe/sbl/sbl.h>
+#include <linux/hpe/sbl/sbl_fec.h>
+#include <linux/hpe/sbl/sbl_kconfig.h>
+
+#include <uapi/ethernet/sbl_cassini.h>
+
+#include "sbl_serdes_map.h"
+#include "sbl_internal.h"
+
+static struct sbl_switch_info cas_brazos_switch_info = SBL_CASSINI_BRAZOS_SW_INFO_INITIALIZER;
+static struct sbl_switch_info cas_nic0_switch_info = SBL_CASSINI_NIC0_SW_INFO_INITIALIZER;
+static struct sbl_switch_info cas_nic1_switch_info = SBL_CASSINI_NIC1_SW_INFO_INITIALIZER;
+
+/**
+ * sbl_set_eth_name() - Set ethernet interface name
+ * @sbl: A slingshot base link device instance
+ * @name: String used to set as interface name
+ */
+void sbl_set_eth_name(struct sbl_inst *sbl, const char *name)
+{
+	unsigned long flags;
+
+	if (!sbl || !name)
+		return;
+
+	spin_lock_irqsave(&sbl->name_lock, flags);
+	strscpy(sbl->iattr.eth_if_name, name, sizeof(sbl->iattr.eth_if_name));
+	spin_unlock_irqrestore(&sbl->name_lock, flags);
+
+	sbl_dev_info(sbl->dev, "eth if name changed to %s", name);
+}
+EXPORT_SYMBOL(sbl_set_eth_name);
+
+int sbl_switch_info_get(struct sbl_inst *sbl, struct sbl_init_attr *init_attr)
+{
+	sbl->is_hw = init_attr->is_hw;
+	switch (init_attr->uc_platform) {
+	case SBL_UC_PLATFORM_SAWTOOTH:
+		if (init_attr->uc_nic == 0) {
+			sbl->switch_info = &cas_nic0_switch_info;
+		} else if (init_attr->uc_nic == 1) {
+			sbl->switch_info = &cas_nic1_switch_info;
+		} else {
+			sbl_dev_err(sbl->dev, "Bad NIC index (%d)!\n",
+				    init_attr->uc_nic);
+			return -EINVAL;
+		}
+		break;
+	case SBL_UC_PLATFORM_BRAZOS:
+		sbl->switch_info = &cas_brazos_switch_info;
+		break;
+	case SBL_UC_PLATFORM_UNDEFINED:
+		sbl_dev_err(sbl->dev, "Undefined uC platform!\n");
+		return -EINVAL;
+	default:
+		sbl_dev_err(sbl->dev, "Unknown uC platform (%d)!\n", init_attr->uc_platform);
+		return -EINVAL;
+	}
+
+	return 0;
+}
diff --git a/drivers/net/ethernet/hpe/sbl/sbl_internal.c b/drivers/net/ethernet/hpe/sbl/sbl_internal.c
new file mode 100644
index 000000000000..aeac466f3c47
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sbl/sbl_internal.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2019-2020,2022-2024 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kernel.h>
+#include <linux/device.h>
+
+#include <linux/hpe/sbl/sbl.h>
+#include <linux/hpe/sbl/sbl_kconfig.h>
+
+#include <uapi/ethernet/sbl-abi.h>
+
+#include "sbl_constants.h"
+#include "sbl_internal.h"
+#include "sbl_serdes_map.h"
+
+/* validate a port (link) number */
+int sbl_validate_port_num(struct sbl_inst *sbl, int port_num)
+{
+	if (port_num < 0 || port_num >= sbl->switch_info->num_ports)
+		return -EINVAL;
+	return 0;
+}
+
diff --git a/drivers/net/ethernet/hpe/sbl/sbl_misc.c b/drivers/net/ethernet/hpe/sbl/sbl_misc.c
new file mode 100644
index 000000000000..2ed99dea9511
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sbl/sbl_misc.c
@@ -0,0 +1,505 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* Copyright 2019-2024 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kernel.h>
+
+#include <linux/hpe/sbl/sbl.h>
+#include <linux/hpe/sbl/sbl_kconfig.h>
+
+#include <linux/hpe/sbl/sbl_pml.h>
+
+#include <uapi/ethernet/sbl-abi.h>
+
+#include "sbl_constants.h"
+#include "sbl_internal.h"
+
+/**
+ * sbl_link_state_str() - Get link status as string
+ * @state: This Value used to find status
+ *
+ * Get link status as string based on value 'state'
+ * provided from caller.
+ *
+ * Return: link status as string
+ */
+const char *sbl_link_state_str(enum sbl_base_link_status state)
+{
+	switch (state) {
+	case SBL_BASE_LINK_STATUS_UNKNOWN:      return "unknown";
+	case SBL_BASE_LINK_STATUS_RESETTING:    return "resetting";
+	case SBL_BASE_LINK_STATUS_UNCONFIGURED: return "unconfigured";
+	case SBL_BASE_LINK_STATUS_STARTING:     return "starting";
+	case SBL_BASE_LINK_STATUS_UP:           return "up";
+	case SBL_BASE_LINK_STATUS_STOPPING:     return "stopping";
+	case SBL_BASE_LINK_STATUS_DOWN:         return "down";
+	case SBL_BASE_LINK_STATUS_ERROR:        return "error";
+	default:                                return "unrecognized";
+	}
+}
+EXPORT_SYMBOL(sbl_link_state_str);
+
+/**
+ * sbl_link_len_str() - Get cable length as string
+ * @len: Value used to find link length
+ *
+ * Get Cable length as string based on the 'len' provided
+ * from the caller.
+ *
+ * Return: Link length as string
+ */
+const char *sbl_link_len_str(enum sbl_link_len len)
+{
+	switch (len) {
+	case SBL_LINK_LEN_INVALID:   return "invalid";
+	case SBL_LINK_LEN_BACKPLANE: return "backplane";
+	case SBL_LINK_LEN_000_300:   return "0.30m";
+	case SBL_LINK_LEN_000_400:   return "0.40m";
+	case SBL_LINK_LEN_000_750:   return "0.75m";
+	case SBL_LINK_LEN_000_800:   return "0.80m";
+	case SBL_LINK_LEN_001_000:   return "1.00m";
+	case SBL_LINK_LEN_001_100:   return "1.10m";
+	case SBL_LINK_LEN_001_150:   return "1.15m";
+	case SBL_LINK_LEN_001_200:   return "1.20m";
+	case SBL_LINK_LEN_001_400:   return "1.40m";
+	case SBL_LINK_LEN_001_420:   return "1.42m";
+	case SBL_LINK_LEN_001_500:   return "1.50m";
+	case SBL_LINK_LEN_001_600:   return "1.60m";
+	case SBL_LINK_LEN_001_640:   return "1.64m";
+	case SBL_LINK_LEN_001_700:   return "1.70m";
+	case SBL_LINK_LEN_001_800:   return "1.80m";
+	case SBL_LINK_LEN_001_900:   return "1.90m";
+	case SBL_LINK_LEN_001_910:   return "1.91m";
+	case SBL_LINK_LEN_002_000:   return "2.00m";
+	case SBL_LINK_LEN_002_100:   return "2.10m";
+	case SBL_LINK_LEN_002_130:   return "2.13m";
+	case SBL_LINK_LEN_002_200:   return "2.20m";
+	case SBL_LINK_LEN_002_300:   return "2.30m";
+	case SBL_LINK_LEN_002_390:   return "2.39m";
+	case SBL_LINK_LEN_002_400:   return "2.40m";
+	case SBL_LINK_LEN_002_500:   return "2.50m";
+	case SBL_LINK_LEN_002_600:   return "2.60m";
+	case SBL_LINK_LEN_002_620:   return "2.62m";
+	case SBL_LINK_LEN_002_700:   return "2.70m";
+	case SBL_LINK_LEN_002_800:   return "2.80m";
+	case SBL_LINK_LEN_002_900:   return "2.90m";
+	case SBL_LINK_LEN_002_990:   return "2.99m";
+	case SBL_LINK_LEN_003_000:   return "3.00m";
+	case SBL_LINK_LEN_004_000:   return "4.00m";
+	case SBL_LINK_LEN_005_000:   return "5.00m";
+	case SBL_LINK_LEN_006_000:   return "6.00m";
+	case SBL_LINK_LEN_007_000:   return "7.00m";
+	case SBL_LINK_LEN_008_000:   return "8.00m";
+	case SBL_LINK_LEN_010_000:   return "10.00m";
+	case SBL_LINK_LEN_014_000:   return "14.00m";
+	case SBL_LINK_LEN_015_000:   return "15.00m";
+	case SBL_LINK_LEN_019_000:   return "19.00m";
+	case SBL_LINK_LEN_025_000:   return "25.00m";
+	case SBL_LINK_LEN_030_000:   return "30.00m";
+	case SBL_LINK_LEN_035_000:   return "35.00m";
+	case SBL_LINK_LEN_050_000:   return "50.00m";
+	case SBL_LINK_LEN_075_000:   return "75.00m";
+	case SBL_LINK_LEN_100_000:   return "100.00m";
+	default:                     return "unrecognized";
+	}
+}
+EXPORT_SYMBOL(sbl_link_len_str);
+
+/**
+ * sbl_link_vendor_str() - Get cable vendor as string
+ * @vendor: Value to find vendor
+ *
+ * Get cable vendor information as string
+ * based on 'vendor' value
+ *
+ * Return: Vendor name as string
+ */
+const char *sbl_link_vendor_str(enum sbl_link_vendor vendor)
+{
+	switch (vendor) {
+	case SBL_LINK_VENDOR_INVALID:        return "invalid";
+	case SBL_LINK_VENDOR_TE:             return "TE Connectivity";
+	case SBL_LINK_VENDOR_LEONI:          return "Leoni";
+	case SBL_LINK_VENDOR_MOLEX:          return "Molex";
+	case SBL_LINK_VENDOR_HISENSE:        return "Hisense";
+	case SBL_LINK_VENDOR_DUST_PHOTONICS: return "Dust Photonics";
+	case SBL_LINK_VENDOR_FINISAR:        return "Finisar";
+	case SBL_LINK_VENDOR_LUXSHARE:       return "Luxshare";
+	case SBL_LINK_VENDOR_FIT:            return "FIT";
+	case SBL_LINK_VENDOR_FT:             return "FT";
+	case SBL_LINK_VENDOR_MELLANOX:       return "Mellanox";
+	case SBL_LINK_VENDOR_HITACHI:        return "Hitachi";
+	case SBL_LINK_VENDOR_HPE:            return "HPE";
+	case SBL_LINK_VENDOR_CLOUD_LIGHT:    return "Cloud Light";
+	case SBL_LINK_VENDOR_AMPHENOL:       return "Amphenol";
+	default:                             return "unrecognized";
+	}
+}
+EXPORT_SYMBOL(sbl_link_vendor_str);
+
+/**
+ * sbl_link_media_str() - Get type of the link media as string
+ * @media: Value used to find media used
+ *
+ * Get physical type of the link media as string
+ *  based on 'media' value provided from caller.
+ *
+ * Return: Media used as string
+ */
+const char *sbl_link_media_str(enum sbl_link_media media)
+{
+	switch (media) {
+	case SBL_LINK_MEDIA_INVALID:         return "invalid";
+	case SBL_LINK_MEDIA_UNKNOWN:         return "unknown";
+	case SBL_LINK_MEDIA_ELECTRICAL:      return "electrical";
+	case SBL_LINK_MEDIA_OPTICAL:         return "optical";
+	default:                             return "unrecognized";
+	}
+}
+EXPORT_SYMBOL(sbl_link_media_str);
+
+/**
+ * sbl_an_mode_str() - Get AN modes for a link as a string
+ * @mode: Value used to find the auto negotiation mode
+ *
+ * Get auto negotiation mode as string based on value 'mode'
+ *
+ * Return: Auto negotiation status as string
+ */
+const char *sbl_an_mode_str(enum sbl_an_mode mode)
+{
+	switch (mode) {
+	case SBL_AN_MODE_INVALID: return "invalid";
+	case SBL_AN_MODE_UNKNOWN: return "unknown";
+	case SBL_AN_MODE_OFF:     return "off";
+	case SBL_AN_MODE_ON:      return "on";
+	case SBL_AN_MODE_FIXED:   return "fixed";
+	default:                  return "unrecognized";
+	}
+}
+EXPORT_SYMBOL(sbl_an_mode_str);
+
+/**
+ * sbl_link_mode_str() - Get IEEE mode for a link as string
+ * @mode: Value used to find the link mode
+ *
+ * Get Link mode as string based on value 'mode'
+ *
+ * Return: Link mode as string
+ */
+const char *sbl_link_mode_str(enum sbl_link_mode mode)
+{
+	switch (mode) {
+	case SBL_LINK_MODE_INVALID: return "invalid";
+	case SBL_LINK_MODE_BS_200G: return "BS_200G";
+	case SBL_LINK_MODE_BJ_100G: return "BJ_100G";
+	case SBL_LINK_MODE_CD_100G: return "CD_100G";
+	case SBL_LINK_MODE_CD_50G:  return "CD_50G";
+	default:                    return "unrecognized";
+	}
+}
+EXPORT_SYMBOL(sbl_link_mode_str);
+
+/**
+ * sbl_rs_mode_str() - Get FEC (Reed-Solomon) mode
+ * @mode: Contains RS MODE selection value
+ *
+ * Return: RS MODE as string
+ */
+const char *sbl_rs_mode_str(enum sbl_rs_mode mode)
+{
+	switch (mode) {
+	case SBL_RS_MODE_INVALID:        return "invalid";
+	case SBL_RS_MODE_UNKNOWN:        return "unknown";
+	case SBL_RS_MODE_OFF:            return "error correction OFF error checking OFF syndrome checking OFF marking OFF";
+	case SBL_RS_MODE_OFF_SYN:        return "error correction OFF error checking OFF syndrome checking  ON marking OFF";
+	case SBL_RS_MODE_OFF_CHK:        return "error correction OFF error checking  ON syndrome checking OFF marking OFF";
+	case SBL_RS_MODE_ON:             return "error correction  ON error checking  ON syndrome checking OFF marking OFF";
+	case SBL_RS_MODE_ON_SYN_MRK:     return "error correction  ON error checking OFF syndrome checking  ON marking  ON";
+	case SBL_RS_MODE_ON_CHK_SYN_MRK: return "error correction  ON error checking  ON syndrome checking  ON marking  ON";
+	default:                         return "unrecognized";
+	}
+}
+EXPORT_SYMBOL(sbl_rs_mode_str);
+
+/**
+ * sbl_ifg_mode_str() - Get Inter-frame gap mode as string
+ * @mode: Value
+ *
+ * Return: IFG mode as string
+ */
+const char *sbl_ifg_mode_str(enum sbl_ifg_mode mode)
+{
+	switch (mode) {
+	case SBL_IFG_MODE_INVALID:  return "invalid";
+	case SBL_IFG_MODE_UNKNOWN:  return "unknown";
+	case SBL_IFG_MODE_HPC:      return "hpc";
+	case SBL_IFG_MODE_IEEE:     return "ieee";
+	default:                    return "unrecognized";
+	}
+}
+EXPORT_SYMBOL(sbl_ifg_mode_str);
+
+/**
+ * sbl_ifg_config_str() - Get IFG config as string
+ * @config: Value
+ *
+ * Get IFG config as string based on 'config' value.
+ *
+ * Return: IFG Config as string
+ */
+const char *sbl_ifg_config_str(enum sbl_ifg_config config)
+{
+	switch (config) {
+	case SBL_IFG_CONFIG_INVALID:   return "invalid";
+	case SBL_IFG_CONFIG_UNKNOWN:   return "unknown";
+	case SBL_IFG_CONFIG_HPC:       return "hpc";
+	case SBL_IFG_CONFIG_IEEE_200G: return "ieee 200G";
+	case SBL_IFG_CONFIG_IEEE_100G: return "ieee 100G";
+	case SBL_IFG_CONFIG_IEEE_50G:  return "ieee 50G";
+	default:                       return "unrecognized";
+}
+
+}
+EXPORT_SYMBOL(sbl_ifg_config_str);
+
+/**
+ * sbl_llr_mode_str() - Get link-level retry (LLR) mode as string
+ * @mode: Value
+ *
+ * Get llr mode as string based on value 'mode'
+ *
+ * Return: LLR mode as string
+ */
+const char *sbl_llr_mode_str(enum sbl_llr_mode mode)
+{
+	switch (mode) {
+	case SBL_LLR_MODE_INVALID:  return "invalid";
+	case SBL_LLR_MODE_UNKNOWN:  return "unknown";
+	case SBL_LLR_MODE_OFF:      return "off";
+	case SBL_LLR_MODE_MONITOR:  return "monitor";
+	case SBL_LLR_MODE_ON:       return "on";
+	case SBL_LLR_MODE_AUTO:     return "auto";
+	default:                    return "unrecognized";
+	}
+}
+EXPORT_SYMBOL(sbl_llr_mode_str);
+
+/**
+ * sbl_llr_down_behaviour_str() - Get LLR link down behaviour
+ * @behaviour: Value used to find the link down behaviour
+ *
+ * Get LLR link down behaviour as string based on 'behaviour'
+ * value provided.
+ *
+ * Return: LLR Link down behaviour as string
+ */
+const char *sbl_llr_down_behaviour_str(
+		enum sbl_llr_down_behaviour behaviour)
+{
+	switch (behaviour) {
+	case SBL_LLR_LINK_DOWN_INVALID:      return "invalid";
+	case SBL_LLR_LINK_DOWN_UNKNOWN:      return "unknown";
+	case SBL_LLR_LINK_DOWN_DISCARD:      return "discard";
+	case SBL_LLR_LINK_DOWN_BLOCK:        return "block";
+	case SBL_LLR_LINK_DOWN_BEST_EFFORT:  return "best-effort";
+	default:                             return "unrecognized";
+	}
+}
+EXPORT_SYMBOL(sbl_llr_down_behaviour_str);
+
+/**
+ * sbl_loopback_mode_str() - Get loopback mode status
+ * @state: Value used to find loopback mode
+ *
+ * Get loopback mode as string based on 'state' provided.
+ *
+ * Return: Loopback mode as string
+ */
+const char *sbl_loopback_mode_str(enum sbl_loopback_mode state)
+{
+	switch (state) {
+	case SBL_LOOPBACK_MODE_INVALID:  return "invalid";
+	case SBL_LOOPBACK_MODE_LOCAL:    return "local";
+	case SBL_LOOPBACK_MODE_REMOTE:   return "remote";
+	case SBL_LOOPBACK_MODE_OFF:      return "off";
+	default:                         return "unrecognized";
+	}
+}
+EXPORT_SYMBOL(sbl_loopback_mode_str);
+
+const char *sbl_serdes_effort_str(u32 effort)
+{
+	switch (effort) {
+	case SPICO_INT_DATA_ICAL_EFFORT_1:   return "max";
+	case SPICO_INT_DATA_ICAL_EFFORT_10:  return "med";
+	case SPICO_INT_DATA_ICAL_EFFORT_0:   return "min";
+	default:                             return "unrecognized";
+	}
+}
+
+/**
+ * sbl_serdes_state_str() - Get serdes state as string
+ * @state: Value used to find status
+ *
+ * Get serdes state as string based on 'state' value.
+ *
+ * Return: Serdes state as string
+ */
+const char *sbl_serdes_state_str(enum sbl_serdes_status state)
+{
+	switch (state) {
+	case SBL_SERDES_STATUS_UNKNOWN:             return "unknown";
+	case SBL_SERDES_STATUS_AUTONEG:             return "autoneg-mode";
+	case SBL_SERDES_STATUS_LPD_MT:              return "lpd-mt";
+	case SBL_SERDES_STATUS_DOWN:                return "down";
+	case SBL_SERDES_STATUS_TUNING:              return "tuning";
+	case SBL_SERDES_STATUS_RUNNING:             return "running";
+	case SBL_SERDES_STATUS_ERROR:               return "error";
+	case SBL_SERDES_STATUS_RESETTING:           return "resetting";
+	default:                                    return "unrecognized";
+	}
+}
+EXPORT_SYMBOL(sbl_serdes_state_str);
+
+const char *sbl_an_state_str(int state)
+{
+	switch (state) {
+	case SBL_PML_AUTONEG_STATE_AUTONEG_OFF:    return "off";
+	case SBL_PML_AUTONEG_STATE_AUTONEG_ENABLE: return "enable";
+	case SBL_PML_AUTONEG_STATE_TX_DISABLE:     return "tx_disable";
+	case SBL_PML_AUTONEG_STATE_ABILITY_DETECT: return "ability_detect";
+	case SBL_PML_AUTONEG_STATE_ACK_DETECT:     return "ack_detect";
+	case SBL_PML_AUTONEG_STATE_COMPLETE_ACK:   return "complete_ack";
+	case SBL_PML_AUTONEG_STATE_NEXT_PAGE_WAIT: return "next_page_wait";
+	case SBL_PML_AUTONEG_STATE_AN_GOOD_CHECK:  return "good_check";
+	case SBL_PML_AUTONEG_STATE_AN_GOOD:        return "good";
+	default:                                   return "unrecognized";
+	}
+}
+
+/**
+ * sbl_async_alert_str() - Get Async alert type as string
+ * @alert_type: Value
+ *
+ * Get Async alert type as string based on 'alert_type' provided.
+ *
+ * Return: ASYNC ALERT as string
+ */
+const char *sbl_async_alert_str(enum sbl_async_alert_type alert_type)
+{
+	switch (alert_type) {
+	case SBL_ASYNC_ALERT_INVALID:              return "invalid";
+	case SBL_ASYNC_ALERT_LINK_DOWN:            return "link down";
+	case SBL_ASYNC_ALERT_SERDES_FW_CORRUPTION: return "serdes fw corruption";
+	case SBL_ASYNC_ALERT_TX_DEGRADE:           return "tx degrade";
+	case SBL_ASYNC_ALERT_RX_DEGRADE:           return "rx degrade";
+	case SBL_ASYNC_ALERT_TX_DEGRADE_FAILURE:   return "tx degrade failure";
+	case SBL_ASYNC_ALERT_RX_DEGRADE_FAILURE:   return "rx degrade failure";
+	case SBL_ASYNC_ALERT_SBM_FW_LOAD_FAILURE:  return "sbus master fw load failure";
+	default:                                   return "unrecognized";
+	}
+}
+EXPORT_SYMBOL(sbl_async_alert_str);
+
+/**
+ * sbl_fec_discard_str() - Get discard fec type as string
+ * @discard_type: Value used to find discard type
+ *
+ * Get discard fec type as string based on 'discard_type' provided.
+ *
+ * Return: Discard type as string
+ */
+const char *sbl_fec_discard_str(enum sbl_fec_discard_type discard_type)
+{
+	switch (discard_type) {
+	case SBL_FEC_DISCARD_TYPE_INVALID:         return "invalid";
+	case SBL_FEC_DISCARD_TYPE_RX_DEGRADE:      return "rx lane degraded";
+	case SBL_FEC_DISCARD_TYPE_PML_REC_START:   return "pml recovery started";
+	case SBL_FEC_DISCARD_TYPE_PML_REC_END:     return "pml recovery ended";
+	default:                                   return "unrecognized";
+	}
+}
+EXPORT_SYMBOL(sbl_fec_discard_str);
+
+/**
+ * sbl_down_origin_str() - Get link down reason as string
+ * @down_origin: Value used to find link down origin
+ *
+ * Get the reason for taking link down asynchronously as string
+ * based on 'down_origin' provided.
+ *
+ * Return: Link down origin as string
+ */
+const char *sbl_down_origin_str(enum sbl_link_down_origin down_origin)
+{
+	switch (down_origin) {
+	case SBL_LINK_DOWN_ORIGIN_UNKNOWN:         return "unknown";
+	case SBL_LINK_DOWN_ORIGIN_LINK_DOWN:       return "link down";
+	case SBL_LINK_DOWN_ORIGIN_LOCAL_FAULT:     return "local fault";
+	case SBL_LINK_DOWN_ORIGIN_REMOTE_FAULT:    return "remote fault";
+	case SBL_LINK_DOWN_ORIGIN_ALIGN:           return "align";
+	case SBL_LINK_DOWN_ORIGIN_HISER:           return "hiser";
+	case SBL_LINK_DOWN_ORIGIN_LLR_MAX:         return "max llr replay";
+	case SBL_LINK_DOWN_ORIGIN_DEGRADE_FAILURE: return "degrade failure";
+	case SBL_LINK_DOWN_ORIGIN_UCW:             return "uncorrected fec";
+	case SBL_LINK_DOWN_ORIGIN_CCW:             return "corrected fec";
+	case SBL_LINK_DOWN_ORIGIN_LLR_TX_REPLAY:   return "llr tx replay";
+	default:                                   return "unrecognized";
+	}
+}
+EXPORT_SYMBOL(sbl_down_origin_str);
+
+/**
+ * sbl_flags_get_poll_interval_from_flags() - Get interval for sbus operations
+ * @flags: Value
+ *
+ * This function get Interval value which is needed time to wait
+ * between sbus operations
+ *
+ * Return: Interval value on success, 0 if no flag is found
+ */
+int sbl_flags_get_poll_interval_from_flags(unsigned int flags)
+{
+	if (flags & SBL_FLAG_INTERVAL_1MS)
+		return 1;
+	else if (flags & SBL_FLAG_INTERVAL_10MS)
+		return 10;
+	else if (flags & SBL_FLAG_INTERVAL_100MS)
+		return 100;
+	else if (flags & SBL_FLAG_INTERVAL_1S)
+		return 1000;
+	else
+		return 0;
+}
+EXPORT_SYMBOL(sbl_flags_get_poll_interval_from_flags);
+
+/**
+ * sbl_flags_get_delay_from_flags() - Get delay for sbus operations
+ * @flags: Value
+ *
+ * This function get sbus delay. Delays are the time to pause
+ * before issuing first operation of sbus
+ *
+ * Return: Delay value on success, 0 if no flag is found
+ */
+int sbl_flags_get_delay_from_flags(unsigned int flags)
+{
+	if (flags & SBL_FLAG_DELAY_3US)
+		return 3;
+	else if (flags & SBL_FLAG_DELAY_4US)
+		return 4;
+	else if (flags & SBL_FLAG_DELAY_5US)
+		return 5;
+	else if (flags & SBL_FLAG_DELAY_10US)
+		return 10;
+	else if (flags & SBL_FLAG_DELAY_20US)
+		return 20;
+	else if (flags & SBL_FLAG_DELAY_50US)
+		return 50;
+	else if (flags & SBL_FLAG_DELAY_100US)
+		return 100;
+	else
+		return 0;
+}
+EXPORT_SYMBOL(sbl_flags_get_delay_from_flags);
diff --git a/drivers/net/ethernet/hpe/sbl/sbl_module_nic.c b/drivers/net/ethernet/hpe/sbl/sbl_module_nic.c
new file mode 100644
index 000000000000..a26eb357adb6
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sbl/sbl_module_nic.c
@@ -0,0 +1,132 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* Copyright 2025-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/cdev.h>
+#include <linux/fs.h>
+#include <linux/slab.h>
+#include <linux/version.h>
+#include <linux/of.h>
+
+#include <linux/hpe/sbl/sbl.h>
+#include <linux/hpe/sbl/sbl_kconfig.h>
+
+#include "sbl_internal.h"
+#include "sbl_serdes_map.h"
+
+#define DEVICE_NAME         "sbl"
+
+static struct class  *sbl_cls;
+static struct device *sbl_dev;
+static dev_t          sbl_devt;
+
+#define tostr(x) #x
+#define version_str(a, b, c) tostr(a.b.c)
+#define SBL_VERSION_STR version_str(SBL_VERSION_MAJOR,	\
+				    SBL_VERSION_MINOR,	\
+				    SBL_VERSION_INC)
+
+/*   module init function
+ *
+ *   The char device is only used for fw loading and printing to the console
+ *   For now multiple instances all share the same device
+ */
+static int __init sbl_init(void)
+{
+	int err;
+
+	pr_info("%s : v%s loading (%s build)\n", module_name(THIS_MODULE),
+		SBL_VERSION_STR, SBL_BUILD_NAME);
+
+	/* create a device */
+	err = alloc_chrdev_region(&sbl_devt, 0, 1, DEVICE_NAME);
+	if (err) {
+		pr_err("%s : failed to get dev region [%d]\n",
+		       module_name(THIS_MODULE), err);
+		goto out;
+	}
+
+		sbl_cls = class_create(DEVICE_NAME);
+	if (IS_ERR(sbl_cls)) {
+		pr_err("%s : class create failed [%ld]\n",
+		       module_name(THIS_MODULE), PTR_ERR(sbl_cls));
+		err = PTR_ERR(sbl_cls);
+		goto out_region;
+	}
+
+	sbl_dev = device_create(sbl_cls, NULL, sbl_devt, NULL,
+				module_name(THIS_MODULE));
+	if (IS_ERR(sbl_dev)) {
+		err = PTR_ERR(sbl_dev);
+		pr_err("%s : failed to add dev [%d]\n",
+		       module_name(THIS_MODULE), err);
+		goto out_class;
+	}
+
+	return 0;
+
+out_class:
+	class_destroy(sbl_cls);
+out_region:
+	unregister_chrdev_region(sbl_devt, 1);
+out:
+	return err;
+}
+module_init(sbl_init);
+
+struct device *sbl_get_device(void)
+{
+	return sbl_dev;
+}
+
+/* module exit function */
+static void __exit sbl_exit(void)
+{
+	pr_info("%s : module unloading\n", module_name(THIS_MODULE));
+
+	device_destroy(sbl_cls, sbl_devt);
+	class_destroy(sbl_cls);
+	unregister_chrdev_region(sbl_devt, 1);
+}
+module_exit(sbl_exit);
+
+static int llr_cap_set(const char *val, const struct kernel_param *kp)
+{
+	int           err;
+	unsigned long data;
+
+	err = kstrtoul(val, 0, &data);
+	if (err || data > 0x800)
+		return -EINVAL;
+
+	return param_set_ulong(val, kp);
+}
+
+static const struct kernel_param_ops llr_cap_ops = {
+	.set = llr_cap_set,
+	.get = param_get_ulong,
+};
+
+static unsigned long llr_edge_cap_data_max = 0x320;
+module_param_cb(llr_edge_cap_data_max, &llr_cap_ops, &llr_edge_cap_data_max, 0664);
+MODULE_PARM_DESC(llr_edge_cap_data_max, "LLR data capacity max for edge link");
+u64 sbl_llr_edge_cap_data_max_get(void)
+{
+	return llr_edge_cap_data_max;
+}
+
+static unsigned long llr_edge_cap_seq_max = 0x160;
+module_param_cb(llr_edge_cap_seq_max, &llr_cap_ops, &llr_edge_cap_seq_max, 0664);
+MODULE_PARM_DESC(llr_edge_cap_seq_max, "LLR sequence num capacity max for edge link");
+u64 sbl_llr_edge_cap_seq_max_get(void)
+{
+	return llr_edge_cap_seq_max;
+}
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("HPE Slingshot <support@hpe.com>");
+MODULE_DESCRIPTION("Slingshot Base Link module");
+MODULE_VERSION(SBL_VERSION_STR);
diff --git a/drivers/net/ethernet/hpe/sbl/sbl_test.c b/drivers/net/ethernet/hpe/sbl/sbl_test.c
new file mode 100644
index 000000000000..56f9f19ae5c4
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sbl/sbl_test.c
@@ -0,0 +1,406 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* Copyright 2019-2021 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kernel.h>
+#include <linux/device.h>
+
+#include <linux/hpe/sbl/sbl.h>
+#include <linux/hpe/sbl/sbl_kconfig.h>
+#include <linux/hpe/sbl/sbl_test.h>
+
+#include <uapi/ethernet/sbl_serdes_defaults.h>
+
+#include "sbl_serdes.h"
+#include "sbl_serdes_fn.h"
+#include "sbl_pml_fn.h"
+#include "sbl_internal.h"
+#include "sbl_constants.h"
+
+static bool sbl_test_crc_failure;
+
+/**
+ * sbl_test_core_intr() - test core interrupt access to the serdes
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ *
+ * This function is used to test the serdes operations
+ * and check its results
+ *
+ * Return: 0 on success, error on failure
+ */
+int sbl_test_core_intr(struct sbl_inst *sbl, int port_num)
+{
+	int err;
+	u16 result = 0;
+	unsigned int flags = SBL_FLAG_DELAY_5US | SBL_FLAG_INTERVAL_1MS;
+
+	err = sbl_validate_instance(sbl);
+	if (err)
+		return err;
+
+	err = sbl_validate_port_num(sbl, port_num);
+	if (err)
+		return err;
+
+	dev_dbg(sbl->dev, "%s starting\n", __func__);
+
+	err = sbl_pml_serdes_op(sbl,
+				port_num, /* port num */
+				0,        /* serdes_sel */
+				0,        /* op */
+				0,        /* data */
+				&result,
+				100,      /* timeout ms */
+				flags);   /* flags */
+	if (err)
+		dev_info(sbl->dev, "op 0, err %d\n", err);
+	else
+		dev_info(sbl->dev, "op 0, result 0x%x\n", result);
+
+	return err;
+}
+EXPORT_SYMBOL(sbl_test_core_intr);
+
+static void sbl_blattr_init(struct sbl_base_link_attr *blattr,
+			    int loopback_mode)
+{
+	/* simple PEC, fabric link config */
+	memset(blattr, 0, sizeof(struct sbl_base_link_attr));
+
+	blattr->magic                = SBL_LINK_ATTR_MAGIC;
+
+	blattr->options              = SBL_OPT_FABRIC_LINK |
+				       SBL_OPT_DFE_SAVE_PARAMS |
+				       SBL_OPT_USE_SAVED_PARAMS |
+				       SBL_OPT_ENABLE_PCAL;
+
+	blattr->start_timeout        = SBL_LINK_START_TIMEOUT_PEC;
+
+	blattr->config_target        = SBL_BASE_LINK_CONFIG_PEC;
+	blattr->pec.an_mode          = SBL_AN_MODE_OFF;
+	blattr->pec.an_retry_timeout = SBL_LINK_DFLT_AN_RETRY_TIMEOUT;
+	blattr->pec.an_max_retry     = SBL_LINK_DFLT_AN_MAX_RETRY;
+
+	blattr->lpd_timeout          = SBL_DFLT_LPD_TIMEOUT;        /* not enabled in options */
+	blattr->lpd_poll_interval    = SBL_DFLT_LPD_POLL_INTERVAL;  /* not enabled in options */
+
+	blattr->link_mode            = SBL_LINK_MODE_BS_200G;
+	blattr->loopback_mode        = loopback_mode;
+	blattr->link_partner         = SBL_LINK_PARTNER_SWITCH;
+	blattr->tuning_pattern       = SBL_TUNING_PATTERN_CORE;
+
+	blattr->dfe_pre_delay        = SBL_DFLT_DFE_PRE_DELAY_PEC;
+	blattr->dfe_timeout          = SBL_DFLT_DFE_TIMEOUT_PEC;
+	blattr->dfe_poll_interval    = SBL_DFLT_DFE_POLL_INTERVAL;
+
+	blattr->nrz_min_eye_height   = SBL_DFLT_NRZ_PEC_MIN_EYE_HEIGHT;
+	blattr->nrz_max_eye_height   = SBL_DFLT_NRZ_PEC_MAX_EYE_HEIGHT;
+	blattr->pam4_min_eye_height  = SBL_DFLT_PAM4_PEC_MIN_EYE_HEIGHT;
+	blattr->pam4_max_eye_height  = SBL_DFLT_PAM4_PEC_MAX_EYE_HEIGHT;
+
+	blattr->fec_mode             = SBL_RS_MODE_ON;
+	blattr->enable_autodegrade   = 0;
+	blattr->llr_mode             = SBL_LLR_MODE_ON;
+	blattr->ifg_config           = SBL_IFG_CONFIG_HPC;
+}
+
+/**
+ * sbl_test_link_up() - test link up
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ * @loopback_mode: selected enum value of loopback mode
+ *
+ * Return: 0 on success, error on failure
+ */
+int sbl_test_link_up(struct sbl_inst *sbl, int port_num, int loopback_mode)
+{
+	struct sbl_media_attr mattr;
+	struct sbl_base_link_attr blattr;
+	int blstate;
+	int blerr;
+	int sstate;
+	int serr;
+	int err;
+
+	err = sbl_validate_instance(sbl);
+	if (err)
+		return err;
+
+	dev_dbg(sbl->dev, "%s starting\n", __func__);
+
+	err = sbl_validate_port_num(sbl, port_num);
+	if (err)
+		return err;
+
+	/* configure media */
+	mattr.magic = SBL_MEDIA_ATTR_MAGIC;
+	mattr.media = SBL_LINK_MEDIA_ELECTRICAL;
+	mattr.len   = 2;
+
+	err = sbl_media_config(sbl, port_num, &mattr);
+	if (err) {
+		dev_err(sbl->dev, "%d: media config failed [%d]\n", port_num, err);
+		goto out;
+	}
+
+	/* configure base-link */
+	sbl_blattr_init(&blattr, loopback_mode);
+
+	err = sbl_base_link_config(sbl, port_num, &blattr);
+	if (err) {
+		dev_err(sbl->dev, "%d: base link config failed [%d]\n", port_num, err);
+		goto out;
+	}
+
+	/* start the base link */
+	err = sbl_base_link_start(sbl, port_num);
+	if (err)
+		dev_err(sbl->dev, "%d: base link start failed [%d]\n", port_num, err);
+
+out:
+	sbl_base_link_get_status(sbl, port_num, &blstate, &blerr, &sstate, &serr, NULL, NULL);
+	dev_info(sbl->dev, "%d: base link %s (%d), serdes %s (%d)\n", port_num,
+		 sbl_link_state_str(blstate), blerr,
+		 sbl_serdes_state_str(sstate), serr);
+
+	return err;
+}
+EXPORT_SYMBOL(sbl_test_link_up);
+
+/**
+ * sbl_test_link_reup() - Test to link reup
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ * @loopback_mode: selected enum value of loopback mode
+ *
+ * This function is used to test base link
+ * operation of start/stop.
+ *
+ * Return: 0 on success, error on failure
+ */
+int sbl_test_link_reup(struct sbl_inst *sbl, int port_num, int loopback_mode)
+{
+	struct sbl_base_link_attr blattr;
+	int err;
+
+	err = sbl_validate_instance(sbl);
+	if (err)
+		return err;
+
+	dev_dbg(sbl->dev, "%s starting\n", __func__);
+
+	err = sbl_validate_port_num(sbl, port_num);
+	if (err)
+		return err;
+
+	sbl_blattr_init(&blattr, loopback_mode);
+
+	err = sbl_base_link_config(sbl, port_num, &blattr);
+	if (err)
+		dev_err(sbl->dev, "%d: base link config failed [%d]\n", port_num, err);
+
+	err = sbl_base_link_start(sbl, port_num);
+	if (err)
+		dev_err(sbl->dev, "%d: base link start failed [%d]\n", port_num, err);
+
+	err = sbl_base_link_stop(sbl, port_num);
+	if (err)
+		dev_err(sbl->dev, "%d: base link stop failed [%d]\n", port_num, err);
+
+	err = sbl_base_link_start(sbl, port_num);
+	if (err)
+		dev_err(sbl->dev, "%d: base link start failed [%d]\n", port_num, err);
+
+	return err;
+}
+EXPORT_SYMBOL(sbl_test_link_reup);
+
+/**
+ * sbl_test_link_down() - Test to link down
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ *
+ * Return: 0 on success, error on failure
+ */
+int sbl_test_link_down(struct sbl_inst *sbl, int port_num)
+{
+	int blstate;
+	int blerr;
+	int sstate;
+	int serr;
+	int err;
+
+	err = sbl_validate_instance(sbl);
+	if (err)
+		return err;
+
+	dev_dbg(sbl->dev, "%s starting\n", __func__);
+
+	err = sbl_validate_port_num(sbl, port_num);
+	if (err)
+		return err;
+
+	err = sbl_base_link_stop(sbl, port_num);
+	if (err)
+		dev_err(sbl->dev, "%d: base link stop failed [%d]\n", port_num, err);
+
+	sbl_base_link_get_status(sbl, port_num, &blstate, &blerr, &sstate, &serr, NULL, NULL);
+	dev_info(sbl->dev, "%d: base link %s (%d), serdes %s (%d)\n", port_num,
+		 sbl_link_state_str(blstate), blerr,
+		 sbl_serdes_state_str(sstate), serr);
+
+	return err;
+}
+EXPORT_SYMBOL(sbl_test_link_down);
+
+/**
+ * sbl_test_link_reset() - Test to reset link
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ *
+ * Return: 0 on success, error on failure
+ */
+int sbl_test_link_reset(struct sbl_inst *sbl, int port_num)
+{
+	int err;
+
+	err = sbl_validate_instance(sbl);
+	if (err)
+		return err;
+
+	dev_dbg(sbl->dev, "%s starting\n", __func__);
+
+	err = sbl_validate_port_num(sbl, port_num);
+	if (err)
+		return err;
+
+	err = sbl_base_link_reset(sbl, port_num);
+	if (err)
+		dev_err(sbl->dev, "%d: base link reset failed [%d]\n", port_num, err);
+
+	return err;
+}
+EXPORT_SYMBOL(sbl_test_link_reset);
+
+/**
+ * sbl_test_serdes_stop() - Test to stop serdes
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ *
+ * Stopping the serdes provides a way to test link error pathways
+ * can be used to simulate link failure
+ *
+ * Context: Process context. May sleep. The caller must keep @sbl alive and
+ * must not hold this port's busy_mtx.
+ *
+ * Return: 0 on success, error on failure
+ */
+int sbl_test_serdes_stop(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link;
+	int err;
+
+	err = sbl_validate_instance(sbl);
+	if (err)
+		return err;
+
+	dev_dbg(sbl->dev, "%s starting\n", __func__);
+
+	err = sbl_validate_port_num(sbl, port_num);
+	if (err)
+		return err;
+
+	link = sbl->link + port_num;
+	err = mutex_lock_interruptible(&link->busy_mtx);
+	if (err)
+		return -ERESTARTSYS;
+
+	err = sbl_spico_reset(sbl, port_num);
+	mutex_unlock(&link->busy_mtx);
+	if (err)
+		dev_err(sbl->dev, "%d: sbl serdes stop failed [%d]\n", port_num, err);
+
+	return err;
+}
+EXPORT_SYMBOL(sbl_test_serdes_stop);
+
+/**
+ * sbl_test_pcs_tx_rf() - set pcs to transmit remote fault
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ *
+ * Return: 0 on success, error on failure
+ */
+int sbl_test_pcs_tx_rf(struct sbl_inst *sbl, int port_num)
+{
+	int err;
+
+	err = sbl_validate_instance(sbl);
+	if (err)
+		return err;
+
+	dev_dbg(sbl->dev, "%s starting\n", __func__);
+
+	err = sbl_validate_port_num(sbl, port_num);
+	if (err)
+		return err;
+
+	sbl_pml_pcs_set_tx_rf(sbl, port_num);
+
+	return 0;
+}
+EXPORT_SYMBOL(sbl_test_pcs_tx_rf);
+
+/**
+ * sbl_test_scratch() - Test to reload serdes firmware
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ *
+ * Return: 0 on success,  error on failure
+ */
+int sbl_test_scratch(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link;
+	int err = 0;
+
+	err = sbl_validate_instance(sbl);
+	if (err)
+		return err;
+
+	dev_dbg(sbl->dev, "%s toggling reload serdes fw option\n", __func__);
+
+	err = sbl_validate_port_num(sbl, port_num);
+	if (err)
+		return err;
+
+	link = sbl->link + port_num;
+
+	if (link->blattr.options & SBL_OPT_RELOAD_FW_ON_TIMEOUT)
+		link->blattr.options &= ~SBL_OPT_RELOAD_FW_ON_TIMEOUT;
+	else
+		link->blattr.options |= SBL_OPT_RELOAD_FW_ON_TIMEOUT;
+
+	return err;
+}
+EXPORT_SYMBOL(sbl_test_scratch);
+
+/* Updates return value of SerDes FW CRC check.
+ * If sbl_test_crc_failure set by sbl_test_inject_serdes_fw_crc_failure is 1,
+ * CRC returns failure.
+ */
+void sbl_test_manipulate_serdes_fw_crc_result(u16 *crc_result)
+{
+	if (sbl_test_crc_failure)
+		*crc_result = SPICO_RESULT_SERDES_CRC_FAIL;
+}
+
+/**
+ * sbl_test_inject_serdes_fw_crc_failure() - Test to inject crc failure for serdes fw
+ * @set: if set then inject crc
+ */
+void sbl_test_inject_serdes_fw_crc_failure(bool set)
+{
+	sbl_test_crc_failure = set;
+}
+EXPORT_SYMBOL(sbl_test_inject_serdes_fw_crc_failure);
diff --git a/drivers/net/ethernet/hpe/sbl/sbl_timers.c b/drivers/net/ethernet/hpe/sbl/sbl_timers.c
new file mode 100644
index 000000000000..9af676193667
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sbl/sbl_timers.c
@@ -0,0 +1,228 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2019-2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/ktime.h>
+
+#include <linux/hpe/sbl/sbl.h>
+#include <linux/hpe/sbl/sbl_kconfig.h>
+
+#include <linux/hpe/sbl/sbl_pml.h>
+
+#include "sbl_pml_fn.h"
+#include "sbl_link.h"
+#include "sbl_internal.h"
+
+/* start timeout is the limit for sbl_base_link_start() to bring the link up
+ * this includes all stages of link bringup
+ */
+void sbl_link_init_start_timeout(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+
+	sbl_dev_dbg(sbl->dev, "%d: %s\n", port_num, __func__);
+
+	spin_lock(&link->timeout_lock);
+	link->start_timeout = link->blattr.start_timeout;
+	link->an_timeout_active = false;
+	link->last_start_jiffy = jiffies +
+		min_t(u64, (u64)link->start_timeout * HZ, MAX_JIFFY_OFFSET);
+	link->start_time_begin = ktime_get();
+	link->total_tune_time.tv_sec = 0;
+	link->total_tune_time.tv_nsec = 0;
+	spin_unlock(&link->timeout_lock);
+}
+
+/* change the start timeout */
+void sbl_link_update_start_timeout(struct sbl_inst *sbl, int port_num, unsigned int timeout_ms)
+{
+	struct sbl_link *link = sbl->link + port_num;
+
+	sbl_dev_dbg(sbl->dev, "%d: %s\n", port_num, __func__);
+
+	spin_lock(&link->timeout_lock);
+	link->start_timeout = DIV_ROUND_UP(timeout_ms, 1000);
+	link->last_start_jiffy = jiffies + msecs_to_jiffies(timeout_ms);
+	spin_unlock(&link->timeout_lock);
+
+	sbl_dev_dbg(sbl->dev, "%d: update start timeout to %d s, %d ms\n",
+		    port_num, link->start_timeout, timeout_ms);
+}
+
+/* test if we have timed out - returns true if we have */
+bool sbl_start_timeout(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	unsigned long last_start_jiffy;
+	bool timed_out;
+
+	spin_lock(&link->timeout_lock);
+	last_start_jiffy = link->last_start_jiffy;
+	timed_out = time_is_before_jiffies(last_start_jiffy);
+	spin_unlock(&link->timeout_lock);
+
+	if (timed_out)
+		sbl_dev_dbg(sbl->dev, "%d: %s timed out\n", port_num, __func__);
+
+	return timed_out;
+}
+
+u32 sbl_get_start_timeout(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	u32 start_timeout;
+
+	spin_lock(&link->timeout_lock);
+	start_timeout = link->start_timeout;
+	spin_unlock(&link->timeout_lock);
+
+	return start_timeout;
+}
+
+/* update start timeout to ensure there is a minimum  amout of time remaining */
+void sbl_start_timeout_ensure_remaining(struct sbl_inst *sbl, int port_num, unsigned int remaining_s)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	unsigned long now;
+	unsigned long left;
+	unsigned long required = min_t(u64, (u64)remaining_s * HZ,
+				       MAX_JIFFY_OFFSET);
+
+	sbl_dev_dbg(sbl->dev, "%d: %s\n", port_num, __func__);
+
+	spin_lock(&link->timeout_lock);
+
+	/* Don't mess with timeouts setup by autoneg */
+	if (link->an_timeout_active) {
+		spin_unlock(&link->timeout_lock);
+		return;
+	}
+
+	now = jiffies;
+	if (time_before(now, link->last_start_jiffy)) {
+		left = link->last_start_jiffy - now;
+		if (left < required) {
+			sbl_dev_info(sbl->dev, "%d: extending timeout by %ld\n", port_num,
+					(required - left) / HZ);
+			link->start_timeout += DIV_ROUND_UP(required - left, HZ);
+			link->last_start_jiffy = now + required;
+		} else {
+			sbl_dev_dbg(sbl->dev, "%d: timeout OK - now %ld, last %ld, left %ld, req %ld\n",
+				    port_num, now, link->last_start_jiffy, left, required);
+		}
+	} else {
+		/* we should timeout but extend instead */
+		sbl_dev_info(sbl->dev, "%d: extending timeout by %ld\n", port_num,
+				required / HZ);
+		link->start_timeout += DIV_ROUND_UP(now - link->last_start_jiffy +
+						 required, HZ);
+		link->last_start_jiffy = now + required;
+	}
+
+	spin_unlock(&link->timeout_lock);
+}
+
+int sbl_link_start_elapsed(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	struct timespec64 elapsed;
+
+	spin_lock(&link->timeout_lock);
+	elapsed = ktime_to_timespec64(ktime_sub(ktime_get(), link->start_time_begin));
+	spin_unlock(&link->timeout_lock);
+
+	return elapsed.tv_sec;
+}
+
+void sbl_link_start_record_timespec(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+
+	sbl_dev_dbg(sbl->dev, "%d: %s\n", port_num, __func__);
+
+	spin_lock(&link->timeout_lock);
+	link->start_time = ktime_to_timespec64(ktime_sub(ktime_get(), link->start_time_begin));
+	spin_unlock(&link->timeout_lock);
+}
+
+/* up time is the time to tune serdes and bring-up pml */
+void sbl_link_up_begin(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+
+	sbl_dev_dbg(sbl->dev, "%d: %s\n", port_num, __func__);
+
+	spin_lock(&link->timeout_lock);
+	link->up_time_begin = ktime_get();
+	spin_unlock(&link->timeout_lock);
+}
+
+void sbl_link_up_record_timespec(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+
+	sbl_dev_dbg(sbl->dev, "%d: %s\n", port_num, __func__);
+
+	spin_lock(&link->timeout_lock);
+	link->up_time = ktime_to_timespec64(ktime_sub(ktime_get(), link->up_time_begin));
+	spin_unlock(&link->timeout_lock);
+}
+
+/* tune time is the time serdes spent actually tuning */
+void sbl_link_tune_begin(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+
+	sbl_dev_dbg(sbl->dev, "%d: %s\n", port_num, __func__);
+
+	spin_lock(&link->timeout_lock);
+	link->tune_time_begin = ktime_get();
+	spin_unlock(&link->timeout_lock);
+}
+
+int sbl_link_tune_elapsed(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	struct timespec64 elapsed;
+
+	spin_lock(&link->timeout_lock);
+	elapsed = ktime_to_timespec64(ktime_sub(ktime_get(), link->tune_time_begin));
+	spin_unlock(&link->timeout_lock);
+
+	return elapsed.tv_sec;
+}
+
+void sbl_link_tune_zero_total_timespec(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+
+	sbl_dev_dbg(sbl->dev, "%d: %s\n", port_num, __func__);
+
+	spin_lock(&link->timeout_lock);
+	link->total_tune_time.tv_sec = 0;
+	link->total_tune_time.tv_nsec = 0;
+	spin_unlock(&link->timeout_lock);
+}
+
+void sbl_link_tune_update_total_timespec(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	u64 ns;
+
+	sbl_dev_dbg(sbl->dev, "%d: %s\n", port_num, __func__);
+
+	spin_lock(&link->timeout_lock);
+	link->tune_time = ktime_to_timespec64(ktime_sub(ktime_get(), link->tune_time_begin));
+
+	link->total_tune_time.tv_sec += link->tune_time.tv_sec;
+	ns = link->total_tune_time.tv_nsec + link->tune_time.tv_nsec;
+	if (ns >= NSEC_PER_SEC) {
+		link->total_tune_time.tv_sec += 1;
+		ns -= NSEC_PER_SEC;
+	}
+	link->total_tune_time.tv_nsec = ns;
+	spin_unlock(&link->timeout_lock);
+}

-- 
2.56.0


^ permalink raw reply	[flat|nested] 25+ messages in thread
* [PATCH 04/23] net: hpe: sbl: add the SerDes layer
  2026-10-30 20:58 [PATCH 00/23] Subject: [PATCH net-next 00/23] net/hpe: add HPE Slingshot NIC drivers Doug Ledford
                   ` (2 preceding siblings ...)
  2026-10-30 20:58 ` [PATCH 03/23] net: hpe: sbl: add the core instance and configuration layer Doug Ledford
@ 2026-10-30 20:59 ` Doug Ledford
  2026-10-30 20:59 ` [PATCH 05/23] net: hpe: sbl: add the PML link layer Doug Ledford
                   ` (19 subsequent siblings)
  23 siblings, 0 replies; 25+ messages in thread
From: Doug Ledford @ 2026-10-30 20:59 UTC (permalink / raw)
  To: Slingshot Open Source Team, Nathan Chancellor, Nicolas Schier,
	Richard Cochran, Andrew Lunn, David S. Miller, Eric Dumazet,
	Jakub Kicinski, Paolo Abeni, Sumit Semwal, Christian König,
	Guenter Roeck
  Cc: linux-kernel, netdev, linux-kbuild, Doug Ledford, Mamila Santosh

Add the SerDes layer: per-lane configuration, the autogenerated lane
map, and the function-pointer table that lets the PML layer drive the
SerDes without knowing which SerDes core is present.

sbl_serdes_map_autogen.h is generated from the hardware lane
description and is kept in generated form, so style checkers will flag
it for line length and macro layout.

checkpatch --strict (100 columns) still reports the following in this
patch. They need coordination with the internal repositories this code
is maintained in and will be fixed in V2:
- WARNING: LONG_LINE (45), BLOCK_COMMENT_STYLE (36), ALLOC_WITH_SIZEOF
  (2), ENOTSUPP (1), LONG_LINE_COMMENT (1), LONG_LINE_STRING (1),
  TYPO_SPELLING (1)
- CHECK: UNNECESSARY_PARENTHESES (37), BRACES (13), ALLOC_SIZEOF_STRUCT
  (2), PARENTHESIS_ALIGNMENT (2), COMPARISON_TO_NULL (1), LINE_SPACING
  (1)

Co-developed-by: Mamila Santosh <santosh-kumar.mamila@hpe.com>
Signed-off-by: Mamila Santosh <santosh-kumar.mamila@hpe.com>
Signed-off-by: Doug Ledford <doug.ledford@hpe.com>
---
 drivers/net/ethernet/hpe/sbl/sbl_serdes.c    | 1117 +++++++
 drivers/net/ethernet/hpe/sbl/sbl_serdes_fn.c | 4310 ++++++++++++++++++++++++++
 2 files changed, 5427 insertions(+)

diff --git a/drivers/net/ethernet/hpe/sbl/sbl_serdes.c b/drivers/net/ethernet/hpe/sbl/sbl_serdes.c
new file mode 100644
index 000000000000..4db5bb1a0bb9
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sbl/sbl_serdes.c
@@ -0,0 +1,1117 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* Copyright 2019-2022, 2024-2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+
+#include <linux/hpe/sbl/sbl.h>
+#include <linux/hpe/sbl/sbl_kconfig.h>
+
+#include "sbl_constants.h"
+#include "sbl_serdes.h"
+#include "sbl_config_list.h"
+#include "sbl_serdes_map.h"
+#include "sbl_serdes_fn.h"
+#include "sbl_internal.h"
+
+static atomic_t sbl_next_serdes_config_tag = ATOMIC_INIT(-1);
+
+static int sbl_serdes_stop_internal(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	int err = 0;
+	int serdes;
+
+	sbl_dev_dbg(sbl->dev, "p%d: SerDes stop", port_num);
+
+	err = sbl_port_stop_pcal(sbl, port_num);
+	if (err) {
+		sbl_dev_err(sbl->dev, "p%d: SerDes stop: port_pcal_stop failed [%d]",
+			    port_num, err);
+		goto out;
+	}
+
+	for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+		err = sbl_set_tx_rx_enable(sbl, port_num, serdes,
+					   false, false, false);
+		if (err) {
+			sbl_dev_err(sbl->dev,
+				    "p%d: SerDes stop: disable failed [%d]",
+				port_num, err);
+			goto out;
+		}
+	}
+
+	err = sbl_spico_reset(sbl, port_num);
+	if (err) {
+		sbl_dev_err(sbl->dev, "p%d: SerDes stop: spico_reset failed [%d]",
+			    port_num, err);
+		goto out;
+	}
+
+out:
+	if (err) {
+		link->sstate = SBL_SERDES_STATUS_ERROR;
+		/* Try and recover from errors with FW reload */
+		link->reload_serdes_fw = true;
+	} else {
+		sbl_dev_dbg(sbl->dev, "p%d: SerDes stop: done", port_num);
+		link->sstate = SBL_SERDES_STATUS_DOWN;
+	}
+	link->serr = err;
+
+	return err;
+}
+
+/* This delay is to give time for the optical transceivers to lock */
+static int sbl_serdes_optical_lock_delay(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	unsigned long last_jiffy;
+	int err = 0;
+
+	sbl_dev_dbg(sbl->dev, "p%d: optical lock delay", port_num);
+
+	if (link->blattr.config_target != SBL_BASE_LINK_CONFIG_AOC) {
+		sbl_dev_err(sbl->dev, "p%d: optical lock delay - config not optical", port_num);
+		return -EINVAL;
+	}
+
+	link->optical_delay_active = true;
+	last_jiffy = jiffies + msecs_to_jiffies(link->blattr.aoc.optical_lock_delay);
+	while (time_is_after_jiffies(last_jiffy)) {
+		if (sbl_base_link_start_cancelled(sbl, port_num)) {
+			err = -ECANCELED;
+			goto out;
+		}
+		if (sbl_start_timeout(sbl, port_num)) {
+			err = -ETIMEDOUT;
+			goto out;
+		}
+		msleep(link->blattr.aoc.optical_lock_interval);
+	}
+out:
+	link->optical_delay_active = false;
+	return err;
+}
+
+/**
+ * sbl_serdes_load() - SerDes initial load function
+ * @sbl: pointer containing target config and state
+ * @port_num: target port number
+ * @force: reset and flash even if current fw is at the correct
+ *        rev and build number
+ *
+ *  When power cycle or controller boots, This function
+ *  Applies the SBus speedup and flashes all SBM/SerDes firmware images
+ *
+ * Return: 0 on success or negative errno on failure
+ */
+int sbl_serdes_load(struct sbl_inst *sbl, int port_num, bool force)
+{
+	int err;
+
+	if (!sbl->is_hw)
+		return 0;
+
+	if (port_num == SBL_ALL_PORTS) {
+		err = sbl_apply_sbus_divider(sbl, SBL_SBUS_DIVIDER_DFLT);
+		if (err) {
+			sbl_dev_err(sbl->dev, "p%d: SBus speedup failed [%d]", port_num, err);
+			return err;
+		}
+	}
+
+	/* retrieve, flash and release SBM firmware */
+	if (port_num == SBL_ALL_PORTS) {
+		err = sbl_sbm_firmware_flash(sbl);
+		if (err) {
+			sbl_dev_err(sbl->dev, "p%d: failed to flash SBM fw [%d]", port_num, err);
+			return err;
+		}
+	}
+
+	/* retrieve and flash SerDes firmware */
+	err = sbl_serdes_firmware_flash(sbl, port_num, force);
+	if (err) {
+		sbl_dev_err(sbl->dev, "p%d: failed to flash SerDes fw [%d]",
+			    port_num, err);
+		return err;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(sbl_serdes_load);
+
+/* link partner detection
+ *
+ * This function will attempt a serdes minitune. This fast tune will only
+ * succeed if the lp is sending AM using the same mode as we are using.
+ *
+ */
+int sbl_serdes_lp_detect(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link;
+	int err;
+	int tmp_err;
+
+	err = sbl_validate_instance(sbl);
+	if (err)
+		return err;
+
+	err = sbl_validate_port_num(sbl, port_num);
+	if (err)
+		return err;
+
+	link = sbl->link + port_num;
+
+	/* in loopback mode the link partner (ourself) is always present! */
+	if (link->loopback_mode == SBL_LOOPBACK_MODE_LOCAL)
+		return 0;
+
+	if (link->sstate != SBL_SERDES_STATUS_DOWN) {
+		sbl_dev_err(sbl->dev, "p%d: serdes_lpd wrong state to start (%s)",
+			    port_num, sbl_serdes_state_str(link->sstate));
+		/* leave state unchanged */
+		return -EUCLEAN;
+	}
+
+	link->sstate = SBL_SERDES_STATUS_LPD_MT;
+	link->serr = 0;
+
+	for (link->lpd_try_count = 0; true; ++link->lpd_try_count) {
+		err = sbl_serdes_minitune_setup(sbl, port_num);
+		if (err) {
+			sbl_dev_err(sbl->dev, "p%d: serdes_lpd setup failed [%d]",
+				    port_num, err);
+			goto out_err;
+		}
+
+		/* If the other end is there then we should block for no more
+		 * than 5s
+		 */
+		err = sbl_serdes_minitune_block(sbl, port_num);
+		switch (err) {
+		case 0:
+			sbl_dev_dbg(sbl->dev, "p%d: serdes_lpd done", port_num);
+			link->lp_detected = true;
+			goto out_done;
+
+		case -ETIMEDOUT:
+			sbl_dev_warn(sbl->dev, "p%d: serdes_lpd timed out", port_num);
+			/* Occasionally serdes minitune will fail even though the link
+			 * partner is actually there!
+			 * Sometimes we can recover by resetting the serdes PLLs and/or
+			 * reloading the serdes firmware
+			 */
+			if (!sbl_debug_option(sbl, port_num, SBL_DEBUG_INHIBIT_SPLL_RESET)) {
+				tmp_err = sbl_reset_serdes_plls(sbl, port_num);
+				if (tmp_err) {
+					/* if this fails nothing we can do */
+					sbl_dev_err(sbl->dev, "p%d: serdes_lpd pll reset failed [%d]",
+						    port_num, tmp_err);
+					/* TODO maybe force fw reload here? */
+				}
+			}
+
+			if (link->blattr.options & SBL_OPT_RELOAD_FW_ON_TIMEOUT)
+				link->reload_serdes_fw = true;
+
+			goto out_done;
+
+		case -ECANCELED:
+			sbl_dev_dbg(sbl->dev, "p%d: serdes_lpd cancelled", port_num);
+			goto out_done;
+
+		case -ETIME:
+			sbl_dev_dbg(sbl->dev, "p%d: serdes_lpd nothing detected", port_num);
+			/* just try again */
+			break;
+
+		default:
+			sbl_dev_err(sbl->dev, "p%d: serdes_lpd block failed [%d]", port_num, err);
+			goto out_err;
+		}
+	};
+
+out_done:
+	link->sstate = SBL_SERDES_STATUS_DOWN;
+	link->serr = 0;
+	return err;
+
+out_err:
+	/* serdes is broken and requires reset */
+	link->sstate = SBL_SERDES_STATUS_ERROR;
+	link->serr = err;
+	return err;
+}
+
+int sbl_serdes_start(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link;
+	int err;
+	int tmp_err;
+
+	err = sbl_validate_instance(sbl);
+	if (err)
+		return err;
+
+	err = sbl_validate_port_num(sbl, port_num);
+	if (err)
+		return err;
+
+	sbl_dev_dbg(sbl->dev, "p%d: SerDes start", port_num);
+
+	link = sbl->link + port_num;
+
+	if (link->sstate != SBL_SERDES_STATUS_DOWN) {
+		sbl_dev_err(sbl->dev, "p%d: SerDes start: wrong state (%s)",
+			    port_num, sbl_serdes_state_str(link->sstate));
+		/* leave state unchanged */
+		return -EUCLEAN;
+	}
+
+	/* configure serdes */
+	err = sbl_serdes_config(sbl, port_num, false);
+	if (err) {
+		sbl_dev_err(sbl->dev,
+			    "p%d: SerDes start: serdes_config failed [%d]",
+			    port_num, err);
+		if (err == -EBADE)
+			link->reload_serdes_fw = true;
+		goto out;
+	}
+
+	/* wait a while before starting to tune to let the optics lock if present
+	 * (in local loopback mode however there are never any optics to wait for)
+	 */
+	if (link->blattr.loopback_mode != SBL_LOOPBACK_MODE_LOCAL) {
+		if (link->mattr.media == SBL_LINK_MEDIA_OPTICAL) {
+			err = sbl_serdes_optical_lock_delay(sbl, port_num);
+			if (err)
+				goto out;
+		}
+	}
+
+	/* make sure we have time left for at lease 2 tuning cycles */
+	sbl_start_timeout_ensure_remaining(sbl, port_num,
+					   2 * (link->blattr.dfe_timeout +
+						 link->blattr.dfe_pre_delay));
+
+	/* tune serdes */
+	link->sstate = SBL_SERDES_STATUS_TUNING;
+
+	err = sbl_serdes_tuning(sbl, port_num);
+	if (err) {
+		switch (err) {
+		case -ECANCELED:
+			sbl_dev_dbg(sbl->dev, "p%d: SerDes start: tuning cancelled", port_num);
+			break;
+		case -ETIMEDOUT:
+			sbl_dev_dbg(sbl->dev, "p%d: SerDes start: tuning timed out", port_num);
+			/* occasionally tuning can fail even thought the lp is good
+			 * resetting the serdes rx plls or reloading the serdes fw can
+			 * sometimes fix this
+			 */
+			if (!sbl_debug_option(sbl, port_num, SBL_DEBUG_INHIBIT_SPLL_RESET)) {
+				tmp_err = sbl_reset_serdes_plls(sbl, port_num);
+				if (tmp_err) {
+					/* if this fails nothing we can do */
+					sbl_dev_err(sbl->dev, "p%d: SerDes start: reset_serdes_plls failed [%d]",
+						    port_num, tmp_err);
+					/* TODO maybe force fw reload here? */
+				}
+			}
+
+			if (link->blattr.options & SBL_OPT_RELOAD_FW_ON_TIMEOUT)
+				link->reload_serdes_fw = true;
+			break;
+		default:
+			sbl_dev_err(sbl->dev,
+				    "p%d: SerDes start: serdes_tuning failed [%d]",
+				    port_num, err);
+			break;
+		}
+	}
+
+out:
+	/* update status */
+	if (err) {
+		link->sstate = SBL_SERDES_STATUS_ERROR;
+		link->serr = err;
+	} else {
+		sbl_dev_dbg(sbl->dev, "p%d: SerDes start: done", port_num);
+		link->sstate = SBL_SERDES_STATUS_RUNNING;
+		link->serr = 0;
+	}
+
+	return err;
+}
+
+int sbl_serdes_stop(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link;
+	int err;
+
+	err = sbl_validate_instance(sbl);
+	if (err)
+		return err;
+
+	err = sbl_validate_port_num(sbl, port_num);
+	if (err)
+		return err;
+
+	link = sbl->link + port_num;
+
+	if (!(link->sstate & (SBL_SERDES_STATUS_RUNNING | SBL_SERDES_STATUS_AUTONEG))) {
+		sbl_dev_err(sbl->dev, "p%d: SerDes stop: wrong state (%s)",
+			    port_num, sbl_serdes_state_str(link->sstate));
+		/* leave state unchanged */
+		return -EUCLEAN;
+	}
+
+	if (sbl_debug_option(sbl, port_num, SBL_DEBUG_KEEP_SERDES_UP)) {
+		sbl_dev_err(sbl->dev, "p%d: KEEP SERDES UP", port_num);
+		return 0;
+	}
+
+	return sbl_serdes_stop_internal(sbl, port_num);
+}
+
+int sbl_serdes_reset(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link;
+	int fail_reset_serdes = 0;
+	int serdes;
+	int err;
+
+	err = sbl_validate_instance(sbl);
+	if (err)
+		return err;
+
+	err = sbl_validate_port_num(sbl, port_num);
+	if (err)
+		return err;
+
+	sbl_dev_dbg(sbl->dev, "p%d: SerDes reset", port_num);
+
+	link = sbl->link + port_num;
+	link->sstate = SBL_SERDES_STATUS_RESETTING;
+
+	/* optionally clear any saved tuning params */
+	if (link->blattr.options & SBL_OPT_RESET_CLEAR_PARAMS) {
+		link->tuning_params.tp_state_hash0 = 0;
+		link->tuning_params.tp_state_hash1 = 0;
+		for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+			memset(link->tuning_params.params[serdes].ctle, 0,
+			       sizeof(u16) * NUM_CTLE_PARAMS);
+			memset(link->tuning_params.params[serdes].ffe, 0,
+			       sizeof(u16) * NUM_FFE_PARAMS);
+			memset(link->tuning_params.params[serdes].dfe, 0,
+			       sizeof(u16) * NUM_DFE_PARAMS);
+			memset(link->tuning_params.params[serdes].rxvs, 0,
+			       sizeof(u16) * NUM_RXVS_PARAMS);
+			memset(link->tuning_params.params[serdes].rxvc, 0,
+			       sizeof(u16) * NUM_RXVC_PARAMS);
+			memset(link->tuning_params.params[serdes].rsdo, 0,
+			       sizeof(u16) * NUM_RSDO_PARAMS);
+			memset(link->tuning_params.params[serdes].rsdc, 0,
+			       sizeof(u16) * NUM_RSDC_PARAMS);
+			memset(link->tuning_params.params[serdes].rsto, 0,
+			       sizeof(u16) * NUM_RSTO_PARAMS);
+			memset(link->tuning_params.params[serdes].rstc, 0,
+			       sizeof(u16) * NUM_RSTC_PARAMS);
+			memset(link->tuning_params.params[serdes].eh, 0,
+			       sizeof(u16) * NUM_EH_PARAMS);
+			memset(link->tuning_params.params[serdes].gtp, 0,
+			       sizeof(u16) * NUM_GTP_PARAMS);
+			memset(link->tuning_params.params[serdes].dccd, 0,
+			       sizeof(u16) * NUM_DCCD_PARAMS);
+			memset(link->tuning_params.params[serdes].p4lv, 0,
+			       sizeof(u16) * NUM_P4LV_PARAMS);
+			memset(link->tuning_params.params[serdes].afec, 0,
+			       sizeof(u16) * NUM_AFEC_PARAMS);
+		}
+	}
+
+	/* Stop continuous tune */
+	err = sbl_port_stop_pcal(sbl, port_num);
+	if (err)
+		sbl_dev_warn(sbl->dev, "p%d: SerDes reset: port_stop_pcal failed [%d]",
+			     port_num, err);
+
+	/* Previously sbl_spico_reset() is now changed to
+	 * sbl_serdes_soft_reset() to avoid SBUS lockups - SSHOTPLAT-2222.
+	 * Upon error, spico reset will reload serdes firmware.
+	 * Note, reloading the firmware can be forced with a
+	 * debug option.
+	 */
+	for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+		err = sbl_serdes_soft_reset(sbl, port_num, serdes);
+		if (err) {
+			fail_reset_serdes = serdes;
+			break;
+		}
+	}
+	if (err)
+		sbl_dev_err(sbl->dev, "p%ds%d: SerDes reset: serdes_soft_reset failed [%d]",
+			    port_num, fail_reset_serdes, err);
+	else if (sbl_debug_option(sbl, port_num, SBL_DEBUG_FORCE_RELOAD_SERDES_FW))
+		/* Skip out_success and continue to SPICO reload */
+		sbl_dev_info(sbl->dev, "p%d: SPICO force serdes_firmware_flash_safe", port_num);
+	else
+		goto out_success;
+
+	/* reload fw */
+	err = sbl_serdes_firmware_flash_safe(sbl, port_num, true);
+	if (err)
+		sbl_dev_err(sbl->dev, "p%d: SerDes reset: serdes_firmware_flash_safe failed [%d]",
+			    port_num, err);
+	else
+		goto out_success;
+
+	/* This is really bad!
+	 * There is nothing we can do but say we are in error and
+	 * be reset again
+	 */
+	sbl_dev_err(sbl->dev, "p%d: SerDes reset: failed [%d]", port_num, err);
+	link->sstate = SBL_SERDES_STATUS_ERROR;
+	link->serr = err;
+
+	return err;
+
+out_success:
+	/* serdes should be fine */
+	sbl_dev_dbg(sbl->dev, "p%d: SerDes reset: done", port_num);
+	link->sstate = SBL_SERDES_STATUS_DOWN;
+	link->serr = 0;
+
+	return 0;
+}
+
+int sbl_an_serdes_start(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link;
+	int err;
+
+	err = sbl_validate_instance(sbl);
+	if (err)
+		return err;
+
+	err = sbl_validate_port_num(sbl, port_num);
+	if (err)
+		return err;
+
+	link = sbl->link + port_num;
+
+	if (link->mattr.media != SBL_LINK_MEDIA_ELECTRICAL) {
+		sbl_dev_err(sbl->dev, "p%d: SerDes AN start - media not electrical",
+			    port_num);
+		return -EINVAL;
+	}
+
+	if (link->blattr.pec.an_mode != SBL_AN_MODE_ON &&
+	    link->blattr.pec.an_mode != SBL_AN_MODE_FIXED) {
+		sbl_dev_err(sbl->dev, "p%d: SerDes AN start - bad mode specified (%s)",
+			    port_num, sbl_an_mode_str(link->blattr.pec.an_mode));
+		return -EINVAL;
+	}
+
+	if (link->sstate != SBL_SERDES_STATUS_DOWN) {
+		sbl_dev_err(sbl->dev, "p%d: SerDes AN start - wrong state (%s)",
+			    port_num, sbl_serdes_state_str(link->sstate));
+		/* leave state unchanged */
+		return -EUCLEAN;
+	}
+
+	err = sbl_serdes_stop_internal(sbl, port_num);
+	if (err) {
+		sbl_dev_err(sbl->dev, "p%d: SerDes AN start - stop internal failed [%d]",
+			    port_num, err);
+		goto out_err;
+	}
+
+	err = sbl_serdes_config(sbl, port_num, true);
+	if (err) {
+		sbl_dev_err(sbl->dev, "p%d: SerDes AN start - config failed [%d]",
+			    port_num, err);
+		goto out_err;
+	}
+
+	sbl_dev_dbg(sbl->dev, "p%d: SerDes AN started", port_num);
+	link->sstate = SBL_SERDES_STATUS_AUTONEG;
+	link->serr = 0;
+	return 0;
+
+out_err:
+	link->sstate = SBL_SERDES_STATUS_ERROR;
+	link->serr = err;
+	return err;
+}
+
+int sbl_an_serdes_stop(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link;
+	int err;
+
+	err = sbl_validate_instance(sbl);
+	if (err)
+		return err;
+
+	err = sbl_validate_port_num(sbl, port_num);
+	if (err)
+		return err;
+
+	link = sbl->link + port_num;
+
+	if (link->sstate != SBL_SERDES_STATUS_AUTONEG) {
+		sbl_dev_err(sbl->dev, "p%d: SerDes in wrong state (%s) for AN stop\n",
+			    port_num, sbl_serdes_state_str(link->sstate));
+		/* leave state unchanged */
+		return -EUCLEAN;
+	}
+
+	err = sbl_serdes_stop_internal(sbl, port_num);
+	if (err) {
+		sbl_dev_err(sbl->dev, "p%d: SerDes AN stop failed [%d]\n",
+			    port_num, err);
+		link->sstate = SBL_SERDES_STATUS_ERROR;
+	} else {
+		sbl_dev_dbg(sbl->dev, "p%d: SerDes AN stopped", port_num);
+		link->sstate = SBL_SERDES_STATUS_DOWN;
+	}
+	link->serr = err;
+	return err;
+}
+
+/**
+ * sbl_serdes_get_tuning_params() - Save tuning params
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ * @tuning_params: tuning parameters used to configure a link,
+ *                allowing the SerDes to come up without needing to DFE tune.
+ *
+ * Get tuning parameters which was used to configure a link
+ *
+ * Context: Process, May sleep. Uses mutex_lock
+ *
+ * Return: 0 on success, negative error code on failure
+ */
+int sbl_serdes_get_tuning_params(struct sbl_inst *sbl, int port_num,
+				 struct sbl_tuning_params *tuning_params)
+{
+	struct sbl_link *link;
+	int err;
+
+	err = sbl_validate_instance(sbl);
+	if (err)
+		return err;
+
+	err = sbl_validate_port_num(sbl, port_num);
+	if (err)
+		return err;
+
+	link = sbl->link + port_num;
+
+	/* don't return invalid parameters */
+	mutex_lock(&link->tuning_params_mtx);
+	if (link->tuning_params.magic != SBL_TUNING_PARAM_MAGIC) {
+		mutex_unlock(&link->tuning_params_mtx);
+		return -ENODATA;
+	}
+
+	sbl_dev_dbg(sbl->dev, "p%d: tp get - returning hash0 0x%llx hash1 0x%llx\n",
+		    port_num, link->tuning_params.tp_state_hash0,
+		link->tuning_params.tp_state_hash1);
+
+	memcpy(tuning_params, &link->tuning_params, sizeof(struct sbl_tuning_params));
+	mutex_unlock(&link->tuning_params_mtx);
+
+	return 0;
+}
+EXPORT_SYMBOL(sbl_serdes_get_tuning_params);
+
+/**
+ * sbl_serdes_set_tuning_params() - set tuning params for serdes
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ * @tuning_params: Pointer to struct sbl_tuning_params
+ *
+ *  Set tuning parameters used to configure a link, allowing the SerDes
+ *  to come up.
+ *
+ * Context: Process, May sleep. Uses mutex_lock
+ *
+ * Return: 0 on success, negative error code on failure
+ */
+int sbl_serdes_set_tuning_params(struct sbl_inst *sbl, int port_num,
+				 struct sbl_tuning_params *tuning_params)
+{
+	struct sbl_link *link;
+	int err;
+
+	err = sbl_validate_instance(sbl);
+	if (err)
+		return err;
+
+	err = sbl_validate_port_num(sbl, port_num);
+	if (err)
+		return err;
+
+	link = sbl->link + port_num;
+
+	if (tuning_params->magic != SBL_TUNING_PARAM_MAGIC)
+		return -EINVAL;
+
+	/* only support one verion for now */
+	if (tuning_params->version != SBL_TUNING_PARAM_VERSION)
+		return -EINVAL;
+
+	mutex_lock(&link->tuning_params_mtx);
+	memcpy(&link->tuning_params, tuning_params, sizeof(struct sbl_tuning_params));
+	mutex_unlock(&link->tuning_params_mtx);
+
+	sbl_dev_dbg(sbl->dev, "p%d: tp set - received hash0 0x%llx hash1 0x%llx\n",
+		    port_num, link->tuning_params.tp_state_hash0,
+		link->tuning_params.tp_state_hash1);
+
+	return 0;
+}
+EXPORT_SYMBOL(sbl_serdes_set_tuning_params);
+
+/**
+ * sbl_serdes_invalidate_tuning_params() - Invalidate tuning params
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ *
+ * Clearing per port tuning parameters
+ *
+ * Context: Process, May sleep. Uses mutex_lock
+ *
+ * Return: 0 on success, negative error code on failure.
+ */
+int sbl_serdes_invalidate_tuning_params(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link;
+	int err;
+
+	err = sbl_validate_instance(sbl);
+	if (err)
+		return err;
+
+	err = sbl_validate_port_num(sbl, port_num);
+	if (err)
+		return err;
+
+	link = sbl->link + port_num;
+
+	mutex_lock(&link->tuning_params_mtx);
+	link->tuning_params.magic = 0;               /* prevent transfer to usr-space */
+	link->tuning_params.tp_state_hash0 = 0;      /* prevent use */
+	link->tuning_params.tp_state_hash1 = 0;      /* prevent use */
+	mutex_unlock(&link->tuning_params_mtx);
+
+	return 0;
+}
+EXPORT_SYMBOL(sbl_serdes_invalidate_tuning_params);
+
+/**
+ * sbl_serdes_invalidate_all_tuning_params() - Invalidate all tuning params
+ * @sbl: A slingshot base link device instance
+ *
+ * Clearing all ports tuning parameters
+ *
+ * Return: 0 on success
+ */
+int sbl_serdes_invalidate_all_tuning_params(struct sbl_inst *sbl)
+{
+	int i;
+
+	for (i = 0; i < sbl->switch_info->num_ports; ++i)
+		sbl_serdes_invalidate_tuning_params(sbl, i);
+
+	return 0;
+}
+EXPORT_SYMBOL(sbl_serdes_invalidate_all_tuning_params);
+
+/**
+ * sbl_serdes_add_config() - Serdes configuration addition
+ * @sbl: A slingshot base link device instance
+ * @tp_state_mask0: State lookup mask
+ * @tp_state_mask1: State lookup mask
+ * @tp_state_match0: match values after masking
+ * @tp_state_match1: match values after masking
+ * @port_mask: applicable ports
+ * @serdes_mask: applicable serdes
+ * @vals: Configuration values
+ * @is_default: Default configuration
+ *
+ * A SerDes configuration entry specifies a set of config values which
+ * are selected to get the SerDes to tune reliably for a given setup.
+ *
+ * Context: Process context, Acquires lock and release serdes_config_lock <spin_lock>
+ *
+ * Return: 0 on success, negative error code on failure
+ */
+int sbl_serdes_add_config(struct sbl_inst *sbl,
+			  u64 tp_state_mask0, u64 tp_state_mask1,
+		u64 tp_state_match0, u64 tp_state_match1,
+		u64 port_mask, u8 serdes_mask, struct sbl_sc_values *vals,
+		bool is_default)
+{
+	struct sbl_serdes_config *new_sc;
+	struct sbl_serdes_config *sc;
+	int err;
+
+	err = sbl_validate_instance(sbl);
+	if (err)
+		return err;
+
+	if (vals->magic != SBL_SERDES_CONFIG_MAGIC)
+		return -EINVAL;
+
+	sbl_dev_dbg(sbl->dev, "serdes add config");
+
+	new_sc = kmalloc(sizeof(struct sbl_serdes_config), GFP_KERNEL);
+	if (!new_sc)
+		return -ENOMEM;
+
+	new_sc->tp_state_mask0  = tp_state_mask0;
+	new_sc->tp_state_mask1  = tp_state_mask1;
+	new_sc->tp_state_match0 = tp_state_match0;
+	new_sc->tp_state_match1 = tp_state_match1;
+	new_sc->port_mask       = port_mask;
+	new_sc->serdes_mask     = serdes_mask;
+	new_sc->is_default      = is_default;
+	new_sc->tag             = sbl_serdes_get_config_tag();
+	memcpy(&new_sc->vals, vals, sizeof(struct sbl_sc_values));
+	INIT_LIST_HEAD(&new_sc->list);
+
+	spin_lock(&sbl->serdes_config_lock);
+
+	/* check new entry is unique */
+	list_for_each_entry(sc, &sbl->serdes_config_list, list) {
+		if (sc->port_mask == port_mask &&
+		    sc->serdes_mask == serdes_mask &&
+		    sc->tp_state_mask0 == tp_state_mask0 &&
+		    sc->tp_state_mask1 == tp_state_mask1 &&
+		    sc->tp_state_match0 == tp_state_match0 &&
+		    sc->tp_state_match1 == tp_state_match1) {
+			spin_unlock(&sbl->serdes_config_lock);
+			kfree(new_sc);
+			return -EEXIST;
+		}
+	}
+
+	/* add the new entry */
+	list_add(&new_sc->list, &sbl->serdes_config_list);
+	sbl_dev_dbg(sbl->dev, "added serdes config, tag %d\n", new_sc->tag);
+	spin_unlock(&sbl->serdes_config_lock);
+	return 0;
+}
+EXPORT_SYMBOL(sbl_serdes_add_config);
+
+/**
+ * sbl_serdes_del_config() - Delete serdes configuration
+ * @sbl: A slingshot base link device instance
+ * @tp_state_mask0: State lookup mask
+ * @tp_state_mask1: State lookup mask
+ * @tp_state_match0: match values after masking
+ * @tp_state_match1: match values after masking
+ * @port_mask: applicable ports
+ * @serdes_mask: applicable serdes
+ *
+ * Delete SerDes config values which are selected to get the
+ * SerDes to tune
+ *
+ * Context: Process context, Acquires lock and release serdes_config_lock <spin_lock>
+ *
+ * Return: 0 on success, negative error code on failure
+ */
+int sbl_serdes_del_config(struct sbl_inst *sbl,
+			  u64 tp_state_mask0, u64 tp_state_mask1,
+		u64 tp_state_match0, u64 tp_state_match1,
+		u64 port_mask, u8  serdes_mask)
+{
+	struct sbl_serdes_config *sc;
+	int err;
+
+	err = sbl_validate_instance(sbl);
+	if (err)
+		return err;
+
+	sbl_dev_dbg(sbl->dev, "serdes del config");
+
+	spin_lock(&sbl->serdes_config_lock);
+
+	/* find the entry and remove it */
+	list_for_each_entry(sc, &sbl->serdes_config_list, list) {
+		if (sc->port_mask == port_mask &&
+		    sc->serdes_mask == serdes_mask &&
+		    sc->tp_state_mask0 == tp_state_mask0 &&
+		    sc->tp_state_mask1 == tp_state_mask1 &&
+		    sc->tp_state_match0 == tp_state_match0 &&
+		    sc->tp_state_match1 == tp_state_match1) {
+			list_del(&sc->list);
+			spin_unlock(&sbl->serdes_config_lock);
+			sbl_dev_dbg(sbl->dev, "deleted serdes config, tag %d\n", sc->tag);
+			kfree(sc);
+			return 0;
+		}
+	}
+
+	/* not found */
+	spin_unlock(&sbl->serdes_config_lock);
+	return -ENOENT;
+}
+EXPORT_SYMBOL(sbl_serdes_del_config);
+
+/**
+ * sbl_serdes_clear_all_configs() - serdes clear all configurations
+ * @sbl: A slingshot base link device instance
+ * @clr_default: Clear default value
+ *
+ * Context: Process context, Acquires lock and release serdes_config_lock <spin_lock>
+ *
+ * Return: 0 on success, negative error on failure
+ */
+int sbl_serdes_clear_all_configs(struct sbl_inst *sbl, bool clr_default)
+{
+	struct sbl_serdes_config *sc;
+	struct sbl_serdes_config *tmp_sc;
+	int err;
+
+	err = sbl_validate_instance(sbl);
+	if (err)
+		return err;
+
+	sbl_dev_dbg(sbl->dev, "serdes clear all configs");
+
+	/* find the entries and remove them */
+	spin_lock(&sbl->serdes_config_lock);
+	list_for_each_entry_safe(sc, tmp_sc, &sbl->serdes_config_list, list) {
+		/* clear if not default or we want to clear the default */
+		if (!sc->is_default || clr_default) {
+			list_del(&sc->list);
+			kfree(sc);
+		}
+	}
+	spin_unlock(&sbl->serdes_config_lock);
+
+	return 0;
+}
+EXPORT_SYMBOL(sbl_serdes_clear_all_configs);
+
+/**
+ * sbl_serdes_dump_configs() - Print all serdes configs
+ * @sbl: A slingshot base link device instance
+ *
+ * Context: Process context, Acquires lock and release serdes_config_lock <spin_lock>
+ * Return: on error
+ */
+void sbl_serdes_dump_configs(struct sbl_inst *sbl)
+{
+	struct sbl_serdes_config *sc;
+	int count = 0;
+	int err;
+
+	err = sbl_validate_instance(sbl);
+	if (err)
+		return;
+
+	spin_lock(&sbl->serdes_config_lock);
+	list_for_each_entry_reverse(sc, &sbl->serdes_config_list, list) {
+		sbl_dev_info(sbl->dev,
+			     "serdes config %d: dflt: %d, tag %d, mask0 0x%llx, match0 0x%llx, mask1 0x%llx, match1 0x%llx, ports 0x%llx, serdes 0x%x\n",
+			count++, sc->is_default, sc->tag, sc->tp_state_mask0, sc->tp_state_match0, sc->tp_state_mask1, sc->tp_state_match1, sc->port_mask, sc->serdes_mask);
+	}
+	spin_unlock(&sbl->serdes_config_lock);
+}
+EXPORT_SYMBOL(sbl_serdes_dump_configs);
+
+u32 sbl_serdes_get_config_tag(void)
+{
+	return atomic_inc_return(&sbl_next_serdes_config_tag);
+}
+
+#ifdef CONFIG_SYSFS
+/**
+ * sbl_serdes_sysfs_sprint() - Format all seredes status into buffer
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ * @buf: Destination buffer to write the data
+ * @size: Size of @buf in bytes, the output is truncated to fit
+ *
+ * Inspects the current SERDES state and based on the value, formats
+ * relevant status or counter information into a readable string. The
+ * formatted output is written to the provided buffer. The output includes
+ * flags such as ":on", ":off", or serdes-reload-counters[fw,spico,pll] values
+ *
+ * Context: Process context, Acquires lock and release link->lock <spin_lock>
+ *
+ * Return: Number of characters written, at most @size - 1
+ */
+int sbl_serdes_sysfs_sprint(struct sbl_inst *sbl, int port_num, char *buf, size_t size)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	int s = 0;
+	int i;
+	int s_fw_reload_count[4] = {0};
+	int s_spico_reset_count[4] = {0};
+	int s_pll_reset_count[4] = {0};
+
+	spin_lock(&link->lock);
+	s += scnprintf(buf + s, size - s, "serdes: %s",
+			sbl_serdes_state_str(link->sstate));
+	switch (link->sstate) {
+	case SBL_SERDES_STATUS_ERROR:
+		s += scnprintf(buf + s, size - s, " [%d]", link->serr);
+		break;
+	case SBL_SERDES_STATUS_LPD_MT:
+		s += scnprintf(buf + s, size - s, " cnt %d", link->lpd_try_count);
+		break;
+	case SBL_SERDES_STATUS_RUNNING:
+		if (link->loopback_mode != SBL_LOOPBACK_MODE_OFF) {
+			s += scnprintf(buf + s, size - s, ", loopback: %s",
+					sbl_loopback_mode_str(link->loopback_mode));
+		}
+		s += scnprintf(buf + s, size - s, ", precoding: %s",
+				(link->precoding_enabled) ? "on" : "off");
+		if (link->dfe_tune_count == SBL_DFE_USED_SAVED_PARAMS) {
+			s += scnprintf(buf + s, size - s, ", tune: used-saved-params");
+		} else {
+			s += scnprintf(buf + s, size - s,
+				       ", tune: cnt %d, eff %s (%lld.%.3ld/%lld.%.3ld)",
+					link->dfe_tune_count,
+					sbl_serdes_effort_str(link->ical_effort),
+					(long long)link->tune_time.tv_sec,
+					link->tune_time.tv_nsec / 1000000,
+					(long long)link->total_tune_time.tv_sec,
+					link->total_tune_time.tv_nsec / 1000000);
+		}
+		break;
+	case SBL_SERDES_STATUS_TUNING:
+		if (link->dfe_tune_count == SBL_DFE_USED_SAVED_PARAMS) {
+			s += scnprintf(buf + s, size - s, ", loading-saved-params");
+		} else {
+			s += scnprintf(buf + s, size - s, ", cnt %d, eff %s (%d/%d)",
+					link->dfe_tune_count,
+					sbl_serdes_effort_str(link->ical_effort),
+					sbl_link_tune_elapsed(sbl, port_num),
+					link->blattr.dfe_timeout);
+		}
+		break;
+	default:
+		break;
+	}
+
+	s += scnprintf(buf + s, size - s, ", pcal: %s",
+			(link->pcal_running) ? "on" : "off");
+	if (link->dfe_predelay_active)
+		s += scnprintf(buf + s, size - s, ", pre-delay");
+	if (link->optical_delay_active)
+		s += scnprintf(buf + s, size - s, ", optical-delay");
+	s += scnprintf(buf + s, size - s, ", fw_reload_skip_cnt: %d",
+			sbl_link_counters_read(sbl, port_num, serdes_fw_reload_skip));
+	s += scnprintf(buf + s, size - s, "\n");
+
+	s += scnprintf(buf + s, size - s, "serdes-reload-counters[fw,spico,pll]:");
+	sbl_link_counters_get(sbl, port_num, s_fw_reload_count,
+			      serdes0_fw_reload, 4);
+	sbl_link_counters_get(sbl, port_num, s_spico_reset_count,
+			      serdes0_spico_reset, 4);
+	sbl_link_counters_get(sbl, port_num, s_pll_reset_count,
+			      serdes0_pll_reset, 4);
+	for (i = 0; i < sbl->switch_info->num_serdes; ++i) {
+		s += scnprintf(buf + s, size - s, " s%d:[%d,%d,%d]", i, s_fw_reload_count[i],
+					s_spico_reset_count[i], s_pll_reset_count[i]);
+	}
+	s += scnprintf(buf + s, size - s, "\n");
+	spin_unlock(&link->lock);
+
+	return s;
+}
+EXPORT_SYMBOL(sbl_serdes_sysfs_sprint);
+
+/**
+ * sbl_serdes_fw_sysfs_sprint() - Format SERDES firmware rev and build into buffer
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ * @buf: Destination buffer to write the data
+ * @size: Size of @buf in bytes, the output is truncated to fit
+ *
+ * Get the serdes firmware version and build information for the port as a string.
+ * Multiple serdes firmware versions and build exist per port. Format those information
+ * into provided buffer
+ *
+ * Return: Number of characters written (at most @size - 1), negative error on failure
+ */
+int sbl_serdes_fw_sysfs_sprint(struct sbl_inst *sbl, int port_num, char *buf, size_t size)
+{
+	int serdes = 0;
+	struct fw {
+		uint rev;
+		uint build;
+	} fw[SBL_SERDES_LANES_PER_PORT];
+	ssize_t s = 0;
+
+	int err = sbl_validate_instance(sbl);
+
+	if (err)
+		return err;
+
+	err = sbl_validate_port_num(sbl, port_num);
+	if (err)
+		return err;
+
+	if (!buf || size == 0U)
+		return -ENOMEM;
+
+	memset(fw, 0, sizeof(fw));
+	for (serdes = 0; serdes < SBL_SERDES_LANES_PER_PORT; ++serdes) {
+		struct fw *pfw = fw + serdes;
+
+		sbl_serdes_get_fw_vers(sbl, port_num, serdes,
+				       &pfw->rev, &pfw->build);
+
+		s += scnprintf(buf + s, size - s,
+			"0x%4.4x_%4.4x\n", pfw->rev, pfw->build);
+	}
+
+	return s;
+}
+EXPORT_SYMBOL(sbl_serdes_fw_sysfs_sprint);
+
+/**
+ * sbl_sbm_fw_sysfs_sprint() - Get sbus master firmware version
+ * @sbl: A slingshot base link device instance
+ * @ring: Value
+ * @buf: Destination buffer to write the data
+ * @size: Size of @buf in bytes, the output is truncated to fit
+ *
+ * Return: Number of characters written (at most @size - 1), negative error on failure
+ */
+int sbl_sbm_fw_sysfs_sprint(struct sbl_inst *sbl, int ring, char *buf, size_t size)
+{
+	uint fw_rev, fw_build = 0;
+
+	int err = sbl_validate_instance(sbl);
+
+	if (err)
+		return err;
+
+	if (ring < 0 || ring >= sbl_get_num_sbus_rings(sbl))
+		return -EINVAL;
+
+	if (!buf || size == 0U)
+		return -ENOMEM;
+
+	sbl_sbm_get_fw_vers(sbl, ring, &fw_rev, &fw_build);
+	return scnprintf(buf, size, "0x%4.4x_%4.4x\n", fw_rev, fw_build);
+}
+EXPORT_SYMBOL(sbl_sbm_fw_sysfs_sprint);
+
+#endif
diff --git a/drivers/net/ethernet/hpe/sbl/sbl_serdes_fn.c b/drivers/net/ethernet/hpe/sbl/sbl_serdes_fn.c
new file mode 100644
index 000000000000..f085d5c41da1
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sbl/sbl_serdes_fn.c
@@ -0,0 +1,4310 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* Copyright 2019-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+
+#include <linux/hpe/sbl/sbl.h>
+#include <linux/hpe/sbl/sbl_kconfig.h>
+#include <linux/hpe/sbl/sbl_test.h>
+
+#include <linux/hpe/sbl/sbl_pml.h>
+
+#include <uapi/ethernet/sbl_sbm_constants.h>
+#include <uapi/ethernet/sbl_serdes_defaults.h>
+
+#include "sbl_constants.h"
+#include "sbl_serdes_map.h"
+#include "sbl_serdes.h"
+#include "sbl_sbm_serdes.h"
+#include "sbl_serdes_fn.h"
+#include "sbl_internal.h"
+#include "sbl_config_list.h"
+#include "sbl_pml_fn.h"
+
+static void sbl_send_serdes_fw_corruption_alert(struct sbl_inst *sbl, int port, int serdes)
+{
+	u32 alert_data;
+	struct serdes_info *serdes_info;
+
+	serdes_info = &sbl->switch_info->ports[port].serdes[serdes];
+	alert_data = ((serdes_info->sbus_ring & 0xffff) << 16) |
+		(serdes_info->rx_addr & 0xffff);
+
+	sbl_async_alert(sbl, port,
+			SBL_ASYNC_ALERT_SERDES_FW_CORRUPTION,
+			(void *)(uintptr_t)alert_data, 0);
+
+	/* Delay to allow userspace to get a serdes state dump */
+	msleep(SBL_SERDES_STATE_DUMP_DELAY);
+}
+
+static bool get_serdes_precoding(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+
+	if (sbl_debug_option(sbl, port_num, SBL_DEBUG_FORCE_PRECODING_ON))
+		return true;
+
+	if (sbl_debug_option(sbl, port_num, SBL_DEBUG_FORCE_PRECODING_OFF))
+		return false;
+
+	switch (link->blattr.precoding) {
+	case SBL_PRECODING_ON:
+		return true;
+	case SBL_PRECODING_OFF:
+		return false;
+	case SBL_PRECODING_DEFAULT:
+		return (link->blattr.options & SBL_OPT_FABRIC_LINK) ? true : false;
+	default:
+		sbl_dev_err(sbl->dev, "%d: invalid precoding (%d) - switching off",
+			    port_num, link->blattr.precoding);
+		/* switch off anyway */
+		return false;
+	}
+}
+
+/* Dummy function used when DEV_TRACE2 or DEV_TRACE3 are not defined */
+void dev_ignore(struct device *dev, const char *format, ...)
+{
+
+}
+
+/* Creates a u64 hash key based on the currently requested serdes state */
+/* NOTE: enums need to be bitwise values to use this hashing */
+static u64 sbl_get_tp_hash0(struct sbl_inst *sbl, int port_num)
+{
+	int media;
+
+	switch (sbl->link[port_num].mattr.media) {
+	case SBL_LINK_MEDIA_ELECTRICAL:
+		if (sbl->link[port_num].mattr.info & SBL_MEDIA_INFO_DIGITAL)
+			media = SBL_EXT_LINK_MEDIA_ELECTRICAL_ACT;
+		else
+			media = SBL_EXT_LINK_MEDIA_ELECTRICAL;
+
+		break;
+
+	case SBL_LINK_MEDIA_OPTICAL:
+		if (sbl->link[port_num].mattr.info & SBL_MEDIA_INFO_DIGITAL)
+			media = SBL_EXT_LINK_MEDIA_OPTICAL_DIGITAL;
+		else
+			media = SBL_EXT_LINK_MEDIA_OPTICAL_ANALOG;
+
+		break;
+
+	default:
+		media = SBL_EXT_LINK_MEDIA_ELECTRICAL;
+		break;
+	}
+
+	return sbl_create_tp_hash0(sbl->link[port_num].blattr.link_partner,
+			sbl->link[port_num].loopback_mode,
+			sbl->link[port_num].blattr.tuning_pattern,
+			sbl->link[port_num].link_mode,
+			media,
+			sbl->link[port_num].mattr.vendor);
+}
+
+static u64 sbl_get_tp_hash1(struct sbl_inst *sbl, int port_num)
+{
+	return sbl_create_tp_hash1(sbl->link[port_num].mattr.len);
+}
+
+void sbl_serdes_get_fw_vers(struct sbl_inst *sbl, int port_num, int serdes,
+			    uint *fw_rev, uint *fw_build)
+{
+	if (sbl_serdes_spico_int(sbl, port_num, serdes, SPICO_INT_CM4_REV_ID,
+				 SPICO_INT_DATA_NONE, (uint16_t *)fw_rev,
+				SPICO_INT_RETURN_RESULT)) {
+		/* Failure expected when Spico is in reset */
+		dev_dbg(sbl->dev, "p%ds%d: Failed to read firmware rev!", port_num, serdes);
+		*fw_rev = 0x0;
+	}
+	if (sbl_serdes_spico_int(sbl, port_num, serdes, SPICO_INT_CM4_BUILD_ID,
+				 SPICO_INT_DATA_NONE, (uint16_t *)fw_build,
+				SPICO_INT_RETURN_RESULT)) {
+		/* Failure expected when Spico is in reset */
+		dev_dbg(sbl->dev, "p%ds%d: Failed to read firmware build!", port_num, serdes);
+		*fw_build = 0x0;
+	}
+}
+
+/* Get mask of serdes used for target link mode */
+static u8 get_serdes_tx_mask(struct sbl_inst *sbl, int port_num)
+{
+	int serdes;
+	u8 serdes_mask = 0;
+
+	switch (sbl->link[port_num].link_mode) {
+	case SBL_LINK_MODE_CD_50G:
+		for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+			if (sbl->switch_info->ports[port_num].serdes[serdes].tx_lane_source == 0) {
+				serdes_mask |= 1 << serdes;
+				break;
+			}
+		}
+		break;
+	case SBL_LINK_MODE_CD_100G:
+		for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+			if ((sbl->switch_info->ports[port_num].serdes[serdes].tx_lane_source == 0) ||
+			    (sbl->switch_info->ports[port_num].serdes[serdes].tx_lane_source == 1)) {
+				serdes_mask |= 1 << serdes;
+			}
+		}
+		break;
+	case SBL_LINK_MODE_BS_200G:
+	case SBL_LINK_MODE_BJ_100G:
+		serdes_mask = 0xf;
+		break;
+	default:
+		sbl_dev_warn(sbl->dev, "%d: Unsupported link mode (%d)",
+			     port_num, sbl->link[port_num].link_mode);
+		serdes_mask = 0x0;
+		break;
+	}
+
+	return serdes_mask;
+}
+
+/* Get mask of serdes used for target link mode */
+static u8 get_serdes_rx_mask(struct sbl_inst *sbl, int port_num)
+{
+	int serdes;
+	u8 serdes_mask = 0;
+
+	/* if we are looped back then rx serdes are the same as the tx ones */
+	if (sbl->link[port_num].loopback_mode == SBL_LOOPBACK_MODE_LOCAL)
+		return get_serdes_tx_mask(sbl, port_num);
+
+	/* otherwise look them up */
+	switch (sbl->link[port_num].link_mode) {
+	case SBL_LINK_MODE_CD_50G:
+		for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+			if (sbl->switch_info->ports[port_num].serdes[serdes].rx_lane_source == 0) {
+				serdes_mask |= 1 << serdes;
+				break;
+			}
+		}
+		break;
+	case SBL_LINK_MODE_CD_100G:
+		for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+			if ((sbl->switch_info->ports[port_num].serdes[serdes].rx_lane_source == 0) ||
+			    (sbl->switch_info->ports[port_num].serdes[serdes].rx_lane_source == 1)) {
+				serdes_mask |= 1 << serdes;
+			}
+		}
+		break;
+	case SBL_LINK_MODE_BS_200G:
+	case SBL_LINK_MODE_BJ_100G:
+		serdes_mask = 0xf;
+		break;
+	default:
+		sbl_dev_warn(sbl->dev, "%d: Unsupported link mode (%d)",
+			     port_num, sbl->link[port_num].link_mode);
+		serdes_mask = 0x0;
+		break;
+	}
+
+	return serdes_mask;
+}
+
+/* Utility function to skip over irrelevant serdes lanes */
+static bool tx_serdes_required_for_link_mode(struct sbl_inst *sbl, int port_num,
+					     int serdes)
+{
+	u8 serdes_mask = get_serdes_tx_mask(sbl, port_num);
+
+	/* Enable physical lane 0 - this has the clock for all serdes and is
+	   always required. */
+	if ((serdes == 0) || (serdes_mask & (1 << serdes)))
+		return true;
+	else
+		return false;
+}
+
+/* Utility function to skip over irrelevant serdes lanes */
+static bool rx_serdes_required_for_link_mode(struct sbl_inst *sbl, int port_num,
+					     int serdes)
+{
+	u8 serdes_mask = get_serdes_rx_mask(sbl, port_num);
+
+	if (serdes_mask & (1 << serdes))
+		return true;
+	else
+		return false;
+}
+
+/* Returns a count of the number of bits set in input val */
+static int sbl_num_bits_set(u64 val)
+{
+	int bits_set = 0;
+	int i;
+
+	for (i = 0; i < 64; ++i) {
+		if (val & (1ULL << i))
+			bits_set++;
+	}
+	return bits_set;
+}
+
+/* Looks up sbl_sc_val struct for the given port, serdes, and hash */
+static int sbl_get_serdes_config_values(struct sbl_inst *sbl, int port_num,
+					int serdes, struct sbl_sc_values *vals)
+{
+	u64 hash0 = sbl_get_tp_hash0(sbl, port_num);
+	u64 hash1 = sbl_get_tp_hash1(sbl, port_num);
+	struct sbl_serdes_config *sc;
+	int num_ports_bits, num_serdes_bits, num_mask_bits;
+	int least_port_bits = 64;
+	int least_serdes_bits = 64;
+	int most_mask_bits = 0;
+	bool curr_best;
+	int rc = -1;
+
+	spin_lock(&sbl->serdes_config_lock);
+
+	list_for_each_entry(sc, &sbl->serdes_config_list, list) {
+
+		if ((sc->port_mask & (1ULL << port_num)) &&
+		    (sc->serdes_mask & (1ULL << serdes)) &&
+		    /* Ensure no bits are set in hash that are not set
+		       in tp_state_match for all bits included in the mask */
+		    (((sc->tp_state_mask0 & hash0) &
+		      ~(sc->tp_state_mask0 & sc->tp_state_match0)) == 0) &&
+		    (((sc->tp_state_mask1 & hash1) &
+		      ~(sc->tp_state_mask1 & sc->tp_state_match1)) == 0)) {
+			/* This is A match, but there may be >1. We want to
+			   choose the match that's most specific to this
+			   config. To determine this, we choose a match which:
+			   * [1] Has the least number of bits set in its
+			   port_mask
+			   * [2] If tie, has the least number of bits set in
+			    its serdes_mask
+			   * [3] If tie, has the most number bits set it its
+			    tp_state_mask0 and tp_state_mask1.
+			   * [4] If tie, pick the one with the lowest index */
+			sbl_dev_dbg(sbl->dev,
+				    "p%d: get values: hash0 0x%llx hash1 0x%llx matched 0x%llx 0x%llx, tag %d\n",
+				port_num, hash0, hash1, sc->tp_state_match0, sc->tp_state_match1, sc->tag);
+			curr_best = false;
+			num_ports_bits	= sbl_num_bits_set(sc->port_mask);
+			num_serdes_bits = sbl_num_bits_set(sc->serdes_mask);
+			num_mask_bits	= sbl_num_bits_set(sc->tp_state_mask0);
+			num_mask_bits  += sbl_num_bits_set(sc->tp_state_mask1);
+			if (num_ports_bits < least_port_bits) {
+				/* [1] */
+				curr_best = true;
+			} else if (num_ports_bits == least_port_bits) {
+				if (num_serdes_bits < least_serdes_bits) {
+					/* [2] */
+					curr_best = true;
+				} else if (num_serdes_bits == least_serdes_bits) {
+					if (num_mask_bits > most_mask_bits) {
+						/* [3] */
+						curr_best = true;
+					}
+				}
+			}
+
+			if (curr_best) {
+				sbl_dev_dbg(sbl->dev, "p%d: tag %d is current best match\n", port_num, sc->tag);
+				*vals = sc->vals;
+				least_port_bits = num_ports_bits;
+				least_serdes_bits = num_serdes_bits;
+				most_mask_bits = num_mask_bits;
+				rc = 0;
+			}
+		}
+	}
+	spin_unlock(&sbl->serdes_config_lock);
+
+	if (rc == 0)
+		return 0;
+
+	sbl_dev_err(sbl->dev, "%d: get values: no match for hash0 0x%llx hash1 0x%llx\n",
+		    port_num, hash0, hash1);
+	return -ENOENT;
+}
+
+/* Checks if there are valid tuning params in the sbl struct which can
+ * be used for this serdes tune
+ */
+static bool sbl_is_retune(struct sbl_inst *sbl, int port_num)
+{
+	int serdes, i;
+	u64 tp_state_hash0, tp_state_hash1;
+	struct sbl_link *link = sbl->link + port_num;
+
+	DEV_TRACE2(sbl->dev, "p%d", port_num);
+
+	/* Reuse of cached tuning params are disabled until AOC sync is implemented */
+	if (link->mattr.media == SBL_LINK_MEDIA_OPTICAL)
+		return false;
+
+	/* Check tuning params are for this target configuration */
+	tp_state_hash0 = sbl_get_tp_hash0(sbl, port_num);
+	tp_state_hash1 = sbl_get_tp_hash1(sbl, port_num);
+	if ((sbl->link[port_num].tuning_params.tp_state_hash0 != tp_state_hash0) ||
+	    (sbl->link[port_num].tuning_params.tp_state_hash1 != tp_state_hash1)) {
+		sbl_dev_dbg(sbl->dev,
+			    "p%d: tuning param mismatch (saved: 0x%llx 0x%llx curr:0x%llx 0x%llx) - not retune\n",
+			port_num, sbl->link[port_num].tuning_params.tp_state_hash0,
+			sbl->link[port_num].tuning_params.tp_state_hash1, tp_state_hash0, tp_state_hash1);
+		return false;
+	}
+
+	/* Check that we actually have tuning params to apply */
+	for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+		if (!(rx_serdes_required_for_link_mode(sbl, port_num, serdes) ||
+		      tx_serdes_required_for_link_mode(sbl, port_num, serdes)))
+			continue;
+		for (i = 0; i < NUM_CTLE_PARAMS; ++i) {
+			if (sbl->link[port_num].tuning_params.params[serdes].ctle[i]) {
+				sbl_dev_dbg(sbl->dev, "p%d: tuning params OK - retune\n", port_num);
+				return true;
+			}
+		}
+		for (i = 0; i < NUM_FFE_PARAMS; ++i) {
+			if (sbl->link[port_num].tuning_params.params[serdes].ffe[i]) {
+				sbl_dev_dbg(sbl->dev, "p%d: tuning params OK - retune\n", port_num);
+				return true;
+			}
+		}
+		for (i = 0; i < NUM_DFE_PARAMS; ++i) {
+			if (sbl->link[port_num].tuning_params.params[serdes].dfe[i]) {
+				sbl_dev_dbg(sbl->dev, "p%d: tuning params OK - retune\n", port_num);
+				return true;
+			}
+		}
+		/* Could continue on to check vernier, etc., but if all the above are 0,
+		    we've got other problems. */
+	}
+
+	sbl_dev_warn(sbl->dev, "p%d: Saved tuning parameters but all 0-forcing retune", port_num);
+
+	return false;
+}
+
+/* Parse the vers string into rev and build */
+static int sbl_parse_version_string(struct sbl_inst *sbl, const char *fw_fname,
+				    int *fw_rev, int *fw_build)
+{
+	char  rev_str[SBL_MAX_STR_LEN];
+	char  build_str[SBL_MAX_STR_LEN];
+	char  *p;
+	int err;
+
+	p = strstr(fw_fname, ".");
+	if (p == NULL) {
+		sbl_dev_err(sbl->dev, "Bad firmware file name: %s", fw_fname);
+		return -EINVAL;
+	}
+
+	if (strlen(p) < strlen(".0x0000_0000")) {
+		sbl_dev_err(sbl->dev, "Bad firmware file name: %s", fw_fname);
+		return -EINVAL;
+	}
+
+	memcpy(rev_str, &(p[3]), SBL_FW_REV_LEN);
+	rev_str[SBL_FW_REV_LEN] = '\n';
+	rev_str[SBL_FW_REV_LEN + 1] = '\0';
+	memcpy(build_str, &(p[8]), SBL_FW_BUILD_LEN);
+	build_str[SBL_FW_BUILD_LEN] = '\n';
+	build_str[SBL_FW_BUILD_LEN + 1] = '\0';
+
+	err = kstrtou32(rev_str, 16, fw_rev);
+	if (err) {
+		sbl_dev_err(sbl->dev, "Failed to convert %s to an integer [%d]", rev_str, err);
+		return err;
+	}
+
+	err = kstrtou32(build_str, 16, fw_build);
+	if (err) {
+		sbl_dev_err(sbl->dev, "Failed to convert %s to an integer [%d]", build_str, err);
+		return err;
+	}
+	return 0;
+}
+
+void sbl_sbm_get_fw_vers(struct sbl_inst *sbl, int sbus_ring, uint *fw_rev, uint *fw_build)
+{
+	uint sbus_addr = SBUS_ADDR(sbus_ring, SBUS_BCAST_SBM_SPICO);
+
+	/* SBUS Critical Section */
+	mutex_lock(&sbl->sbus_ring_mtx[sbus_ring]);
+
+	if (sbl_sbm_spico_int(sbl, sbus_addr, SPICO_INT_SBMS_REV_ID,
+			      SPICO_INT_DATA_NONE, fw_rev)) {
+		/* Failure expected when Spico is in reset */
+		dev_dbg(sbl->dev, "sbm%d: Failed to read firmware rev from 0x%x", sbus_ring, sbus_addr);
+		*fw_rev = 0x0;
+	}
+	if (sbl_sbm_spico_int(sbl, sbus_addr, SPICO_INT_SBMS_BUILD_ID,
+			      SPICO_INT_DATA_NONE, fw_build)) {
+		/* Failure expected when Spico is in reset */
+		dev_dbg(sbl->dev, "sbm%d: Failed to read firmware build from 0x%x", sbus_ring, sbus_addr);
+		*fw_build = 0x0;
+	}
+	mutex_unlock(&sbl->sbus_ring_mtx[sbus_ring]);
+}
+
+int sbl_sbm_firmware_flash(struct sbl_inst *sbl)
+{
+	int err;
+
+	err = sbl_sbm_firmware_flash_ring(sbl, 0,
+					  sbl->switch_info->num_sbus_rings - 1, false);
+	if (err)
+		/* sending port 0 in event as this event doesn't apply to any specific port */
+		sbl_async_alert(sbl, 0, SBL_ASYNC_ALERT_SBM_FW_LOAD_FAILURE, NULL, 0);
+
+	return err;
+}
+
+int sbl_sbm_firmware_flash_ring(struct sbl_inst *sbl, int first_ring,
+				int last_ring, bool force)
+{
+	bool flash_needed, fw_requested = false;
+	int sbus_ring;
+	int err;
+	int fw_rev, fw_build;
+	const struct firmware *fw = NULL;
+
+	if ((last_ring < first_ring) || (first_ring < 0) ||
+	    (last_ring > sbl->switch_info->num_sbus_rings - 1)) {
+		sbl_dev_err(sbl->dev, "Invalid rings specified first:%d last:%d",
+			    first_ring, last_ring);
+		return -EINVAL;
+	}
+
+	err = sbl_parse_version_string(sbl, sbl->iattr.sbm_fw_fname,
+				       &fw_rev, &fw_build);
+	if (err) {
+		sbl_dev_err(sbl->dev, "Failed to parse version string %s [%d]",
+			    sbl->iattr.sbm_fw_fname, err);
+		return err;
+	}
+
+	/* Check SBus Master firmware versions */
+	for (sbus_ring = first_ring; sbus_ring <= last_ring; ++sbus_ring) {
+		flash_needed = false;
+		if (sbl_validate_sbm_fw_vers(sbl, sbus_ring, fw_rev,
+					     fw_build)) {
+			flash_needed = true;
+		}
+
+		if (flash_needed || force) {
+			if (!fw_requested) {
+				err = request_firmware(&fw, sbl->iattr.sbm_fw_fname,
+						       sbl->dev);
+				if (err) {
+					sbl_dev_err(sbl->dev, "firmware request failed [%d]", err);
+					return err;
+				}
+				sbl_dev_dbg(sbl->dev, "loaded fw (size %zd)", fw->size);
+				fw_requested = true;
+			}
+			sbl_dev_dbg(sbl->dev, "ring %d sbus_master firmware out of date! Flashing...", sbus_ring);
+
+			err = sbl_sbm_firm_upload(sbl, sbus_ring, fw->size, fw->data);
+			if (err) {
+				sbl_dev_err(sbl->dev, "Failed to upload ring %d firmware!", sbus_ring);
+				goto out_release;
+			} else {
+				sbl_dev_info(sbl->dev, "Ring %d Sbus Master firmware flashed successfully.", sbus_ring);
+			}
+		}
+	}
+
+ out_release:
+	release_firmware(fw);
+
+	return err;
+}
+
+static void sbl_serdes_firmware_validation(struct sbl_inst *sbl, const struct firmware *fw,
+					   u32 sbus_addr, u32 result, u32 sbus_ring)
+{
+	int rc, i;
+	u8 data;
+	bool corruption_found = false;
+
+	for (i = 0; i < fw->size; ++i) {
+		if (i % 2 == 0) {
+			rc = sbl_sbus_wr(sbl, sbus_addr,
+					SPICO_SBR_ADDR_IMEM, i / 2);
+			if (rc)
+				break;
+			rc = sbl_sbus_rd(sbl, sbus_addr,
+					 SPICO_SBR_ADDR_RDATA,
+					&result);
+			if (rc)
+				break;
+			data = (result & 0xff00) >> 8;
+		} else {
+			data = result & 0xff;
+		}
+		if (data != fw->data[i]) {
+			corruption_found = true;
+			sbl_dev_warn(sbl->dev, "0x%x: Act 0x%4.4x Exp 0x%4.4x", i, data, fw->data[i]);
+		}
+	}
+	rc = sbl_sbus_wr(sbl, sbus_addr, SPICO_SBR_ADDR_CTL,
+			 SPICO_SBR_DATA_IMEM_CNTL_DIS);
+	if (rc)
+		sbl_dev_err(sbl->dev, "SBM Imem rd disable failed [%d]", rc);
+	if (corruption_found)
+		sbl_dev_err(sbl->dev, "r%d: SBM FW corruption found", sbus_ring);
+	else
+		sbl_dev_info(sbl->dev, "r%d: No SBM FW corruption found", sbus_ring);
+}
+
+int sbl_serdes_firmware_flash_safe(struct sbl_inst *sbl, int port_num,
+				   bool force)
+{
+	int rc;
+	u32 sbus_addr, crc_result, sbus_ring;
+	u32 curr_fw_rev = 0, curr_fw_build = 0;
+	u32 result;
+	const struct firmware *fw = NULL;
+	int fw_rev, fw_build;
+	int serdes = 0;
+
+	if (!sbl->is_hw)
+		return 0;
+
+	if (port_num == SBL_ALL_PORTS)
+		return -ENOTSUPP;
+
+	sbus_ring = sbl->switch_info->ports[port_num].serdes[serdes].sbus_ring;
+
+	/* First, try the FW flash */
+	rc = sbl_serdes_firmware_flash(sbl, port_num, force);
+	if (rc)
+		goto sbm_fw_reload;
+
+	/* Now, validate the SerDes FW - this also validates
+	 * SPICO interrupts are working correctly.
+	 */
+	rc = sbl_parse_version_string(sbl, sbl->iattr.serdes_fw_fname,
+				      &fw_rev, &fw_build);
+	if (rc) {
+		sbl_dev_err(sbl->dev,
+			    "Failed to parse version string %s [%d]",
+			sbl->iattr.sbm_fw_fname, rc);
+		return rc;
+	}
+	rc = sbl_validate_serdes_fw_vers(sbl, port_num, serdes, fw_rev, fw_build);
+	if (rc)
+		goto sbm_fw_reload;
+
+	/* Finally, validate the SBM FW - this also validates
+	 * Sbus reads/writes are working correctly.
+	 */
+	rc = sbl_parse_version_string(sbl, sbl->iattr.sbm_fw_fname,
+				      &fw_rev, &fw_build);
+	if (rc) {
+		sbl_dev_err(sbl->dev,
+			    "Failed to parse version string %s [%d]",
+			sbl->iattr.sbm_fw_fname, rc);
+		return rc;
+	}
+	rc = sbl_validate_sbm_fw_vers(sbl, sbus_ring, fw_rev, fw_build);
+	if (rc)
+		goto sbm_fw_reload;
+
+	/* If all the above succeed, we're done unless we force SBM FW reload */
+	if (sbl_debug_option(sbl, port_num,
+			     SBL_DEBUG_FORCE_RELOAD_SBM_FW)) {
+		sbl_dev_info(sbl->dev, "p%d: SBus Master FW reload forced", port_num);
+		goto sbm_fw_reload;
+	}
+	return 0;
+
+ sbm_fw_reload:
+	if (sbl_debug_option(sbl, port_num, SBL_DEBUG_INHIBIT_RELOAD_SBM_FW)) {
+		sbl_dev_warn(sbl->dev, "p%d: SBus Master FW reload inhibited", port_num);
+		return rc;
+	}
+
+	/* We may trigger a sbus master FW reload from multiple ports at the
+	 * same time. Ensure we only actually reload the firmware once per
+	 * sbus ring
+	 */
+	sbl->reload_sbm_fw[sbus_ring] = true;
+	mutex_lock(SBM_FW_MTX(sbl, sbus_ring));
+	if (!sbl->reload_sbm_fw[sbus_ring]) {
+		sbl_dev_info(sbl->dev, "r%d: Sbus master FW reload no longer needed", sbus_ring);
+	} else {
+
+		if (mutex_is_locked(SBUS_RING_MTX(sbl, sbus_ring)))
+			sbl_dev_dbg(sbl->dev,
+				    "%s: Sbus contention detected, sbus_ring_mtx[%d] locked",
+				    __func__, sbus_ring);
+
+		/* SBUS Critical Section */
+		mutex_lock(SBUS_RING_MTX(sbl, sbus_ring));
+
+		/* First, dump the SBM FW info for debug */
+		sbus_addr = SBUS_ADDR(sbus_ring, SBUS_BCAST_SBM_SPICO);
+		/* Version info: Rev.Build */
+		if (sbl_sbm_spico_int(sbl, sbus_addr, SPICO_INT_SBMS_REV_ID,
+				      SPICO_INT_DATA_NONE, &curr_fw_rev)) {
+			sbl_dev_warn(sbl->dev,
+				     "r%d: Failed to read firmware rev from 0x%x",
+				 sbus_ring, sbus_addr);
+		} else {
+			sbl_dev_info(sbl->dev, "r%d: firmware rev 0x%x", sbus_ring, curr_fw_rev);
+		}
+		if (sbl_sbm_spico_int(sbl, sbus_addr, SPICO_INT_SBMS_BUILD_ID,
+				      SPICO_INT_DATA_NONE, &curr_fw_build)) {
+			sbl_dev_warn(sbl->dev,
+				     "r%d: Failed to read firmware build from 0x%x",
+				 sbus_ring, sbus_addr);
+		} else {
+			sbl_dev_info(sbl->dev, "r%d: firmware build 0x%x",
+				     sbus_ring, curr_fw_build);
+		}
+		/* CRC */
+		rc = sbl_sbm_spico_int(sbl, sbus_addr, SPICO_INT_SBMS_DO_CRC,
+				       SPICO_INT_DATA_NONE, &crc_result);
+		if (rc) {
+			sbl_dev_err(sbl->dev,
+				    "p%d(0x%x): CRC check interrupt failed (%d)!",
+				port_num, sbus_addr, rc);
+		} else {
+			if (crc_result != SPICO_RESULT_SBR_CRC_PASS) {
+				sbl_dev_err(sbl->dev,
+					    "p%d(0x%x): CRC check fail (result: 0x%x exp: 0x%x)!",
+					port_num, sbus_addr, crc_result, SPICO_RESULT_SBR_CRC_PASS);
+			} else {
+				sbl_dev_info(sbl->dev,
+					     "p%d(0x%x): CRC check passed",
+					 port_num, sbus_addr);
+			}
+		}
+		/* FW Status */
+		rc = sbl_sbus_rd(sbl, sbus_addr, SPICO_INT_SBMS_FW_STS,
+				 &result);
+		if (rc) {
+			sbl_dev_err(sbl->dev,
+				    "p%d(0x%x): FW status read failed (%d)!",
+				port_num, sbus_addr, rc);
+		} else {
+			sbl_dev_info(sbl->dev, "p%d(0x%x): FW status: 0x%x",
+				     port_num, sbus_addr, result);
+		}
+
+		rc = request_firmware(&fw, sbl->iattr.sbm_fw_fname, sbl->dev);
+		if (rc != 0) {
+			sbl_dev_err(sbl->dev, "firmware request failed [%d]", rc);
+		} else {
+			sbl_dev_info(sbl->dev,
+				     "p%d(0x%x): Checking SBM FW for corruption...",
+				 port_num, sbus_addr);
+			rc = sbl_sbus_wr(sbl, sbus_addr, SPICO_SBR_ADDR_CTL,
+					 SPICO_SBR_DATA_IMEM_CNTL_EN_RD);
+			if (rc)
+				sbl_dev_err(sbl->dev, "SBM Imem rd enable failed [%d]", rc);
+			else
+				sbl_serdes_firmware_validation(sbl, fw, sbus_addr, result, sbus_ring);
+
+			release_firmware(fw);
+		}
+
+		mutex_unlock(SBUS_RING_MTX(sbl, sbus_ring));
+
+		/* Now, try reloading the sbus master FW */
+		rc = sbl_sbm_firmware_flash_ring(sbl, sbus_ring, sbus_ring, true);
+		if (rc)
+			sbl_dev_err(sbl->dev, "r%d: SBM FW flash failed (%d)!", sbus_ring, rc);
+		else
+			sbl_dev_info(sbl->dev, "r%d: SBM FW flash succeeded", sbus_ring);
+
+		sbl->reload_sbm_fw[sbus_ring] = false;
+	}
+	mutex_unlock(SBM_FW_MTX(sbl, sbus_ring));
+
+	/* Finally, retry the SerDes FW reload */
+	rc = sbl_serdes_firmware_flash(sbl, port_num, true);
+	if (rc != 0)
+		sbl_dev_err(sbl->dev,
+			    "p%d: SerDes FW flash failed (%d) despite SBM reload!",
+			port_num, rc);
+	else
+		sbl_dev_info(sbl->dev, "p%d: SerDes FW flash succeeded", port_num);
+
+	/* Regardless of the success/failure of the initial flash and recovery
+	 * attempt, we return the status of the final serdes firmware flash,
+	 * which is the true metric of if this function was successful.
+	 */
+	return rc;
+}
+
+int sbl_serdes_firmware_flash(struct sbl_inst *sbl, int port_num, bool force)
+{
+	bool flash_needed;
+	int serdes = 0;
+	int sr, err = 0;
+	int fw_rev, fw_build;
+	int port = port_num;
+	int first_port, last_port;
+	const struct firmware *fw = NULL;
+
+	/* Lock sbm_fw_mtx to ensure we don't reload the sbus master FW
+	 * while reloading the SerDes FW
+	 */
+	if (port_num == SBL_ALL_PORTS) {
+		for (sr = 0; sr < sbl->switch_info->num_sbus_rings; ++sr)
+			mutex_lock(SBM_FW_MTX(sbl, sr));
+	} else {
+		sr = sbl->switch_info->ports[port_num].serdes[0].sbus_ring;
+		mutex_lock(SBM_FW_MTX(sbl, sr));
+	}
+
+	if (!force) {
+		err = sbl_parse_version_string(sbl, sbl->iattr.serdes_fw_fname,
+					       &fw_rev, &fw_build);
+		if (err) {
+			sbl_dev_err(sbl->dev,
+				    "Failed to parse version string %s [%d]",
+				sbl->iattr.serdes_fw_fname, err);
+			goto out;
+		}
+
+		/* Check SerDes firmware versions */
+		flash_needed = false;
+		if (port_num == SBL_ALL_PORTS) {
+			first_port = 0;
+			last_port = sbl->switch_info->num_ports - 1;
+		} else {
+			first_port = port_num;
+			last_port = port_num;
+		}
+		for (port = first_port; port <= last_port; ++port) {
+			for (serdes = 0; serdes < sbl->switch_info->num_serdes;
+			     ++serdes) {
+				if (sbl_validate_serdes_fw_vers(sbl, port,
+								serdes, fw_rev,
+								fw_build)) {
+					sbl_dev_info(sbl->dev, "port %d serdes: %d firmware out of date! Flash required",
+						     port, serdes);
+					flash_needed = true;
+					break;
+				}
+			}
+			if (flash_needed)
+				break;
+		}
+	} else {
+		flash_needed = true;
+	}
+
+	if (flash_needed) {
+		err = request_firmware(&fw, sbl->iattr.serdes_fw_fname, sbl->dev);
+		if (err) {
+			sbl_dev_err(sbl->dev, "firmware request failed [%d]",
+				    err);
+			goto out;
+		}
+
+		err = sbl_serdes_firm_upload(sbl, port_num, fw->size, fw->data);
+		if (err) {
+			sbl_dev_err(sbl->dev, "%d: serdes firmware upload failed [%d]", port_num, err);
+			if (port_num == SBL_ALL_PORTS)
+				sbl_send_serdes_fw_corruption_alert(sbl, 0, 0);
+			else
+				sbl_send_serdes_fw_corruption_alert(sbl, port, serdes);
+			goto out;
+		} else {
+			if (port_num == SBL_ALL_PORTS)
+				sbl_dev_dbg(sbl->dev, "All SerDes firmware flashed successfully.");
+			else
+				sbl_dev_dbg(sbl->dev, "p%d SerDes firmware flashed successfully.", port_num);
+		}
+	} else {
+		/* Serdes firmware reload skipped as the firmware validation succeeded */
+		for (port = first_port; port <= last_port; ++port)
+			sbl_link_counters_incr(sbl, port, serdes_fw_reload_skip);
+	}
+
+ out:
+	release_firmware(fw);
+
+	if (port_num == SBL_ALL_PORTS) {
+		for (sr = 0; sr < sbl->switch_info->num_sbus_rings; ++sr)
+			mutex_unlock(SBM_FW_MTX(sbl, sr));
+	} else {
+		mutex_unlock(SBM_FW_MTX(sbl, sr));
+	}
+	return err;
+}
+
+int sbl_validate_sbm_fw_vers(struct sbl_inst *sbl, u32 sbus_ring,
+			     int fw_rev, int fw_build)
+{
+	u32 curr_fw_rev = 0, curr_fw_build = 0;
+	u32 sbus_addr = SBUS_ADDR(sbus_ring, SBUS_BCAST_SBM_SPICO);
+
+	DEV_TRACE2(sbl->dev,
+		   "sbus_addr: 0x%x, desired rev: 0x%x, desired build: 0x%x",
+		   sbus_ring, fw_rev, fw_build);
+
+	/* SBUS Critical Section */
+	mutex_lock(SBUS_RING_MTX(sbl, sbus_ring));
+
+	if (sbl_sbm_spico_int(sbl, sbus_addr, SPICO_INT_SBMS_REV_ID,
+			      SPICO_INT_DATA_NONE, &curr_fw_rev)) {
+		/* Failure expected when Spico is in reset */
+		sbl_dev_warn(sbl->dev, "r%d: Failed to read SBM firmware rev from 0x%x",
+			     sbus_ring, sbus_addr);
+	}
+	if (sbl_sbm_spico_int(sbl, sbus_addr, SPICO_INT_SBMS_BUILD_ID,
+			      SPICO_INT_DATA_NONE, &curr_fw_build)) {
+		/* Failure expected when Spico is in reset */
+		sbl_dev_warn(sbl->dev, "r%d: Failed to read SBM firmware build from 0x%x",
+			     sbus_ring, sbus_addr);
+	}
+
+	mutex_unlock(SBUS_RING_MTX(sbl, sbus_ring));
+
+	if (((int)curr_fw_rev == fw_rev) && ((int)curr_fw_build == fw_build)) {
+		sbl_dev_dbg(sbl->dev, "r%d: Found expected SBM rev: 0x%x_%x",
+			    sbus_ring, curr_fw_rev, curr_fw_build);
+		return 0;
+	}
+	sbl_dev_warn(sbl->dev,
+		     "r%d: Expected rev: 0x%x_%x Current SBM rev: 0x%x_%x",
+			sbus_ring, fw_rev, fw_build, curr_fw_rev, curr_fw_build);
+	return -1;
+}
+
+int sbl_validate_serdes_fw_crc(struct sbl_inst *sbl, int port, int serdes)
+{
+	u16 crc_result;
+	int err;
+
+	err = sbl_serdes_spico_int(sbl, port, serdes, SPICO_INT_CM4_CRC,
+				   SPICO_INT_DATA_NONE, &crc_result,
+					SPICO_INT_RETURN_RESULT);
+	if (err)
+		return err;
+
+	/* CRC failure can be injected for test purposes */
+	sbl_test_manipulate_serdes_fw_crc_result(&crc_result);
+
+	if (crc_result != SPICO_RESULT_SERDES_CRC_PASS) {
+		sbl_dev_dbg(sbl->dev,
+			    "p%ds%d: CRC check fail (result 0x%x, expected 0x%x)!",
+			port, serdes, crc_result, SPICO_RESULT_SERDES_CRC_PASS);
+		return -EBADE;
+	}
+
+	return 0;
+}
+
+int sbl_validate_serdes_fw_vers(struct sbl_inst *sbl, int port_num, int serdes,
+				int fw_rev, int fw_build)
+{
+	u16 curr_fw_rev = 0, curr_fw_build = 0;
+	int err;
+
+	DEV_TRACE2(sbl->dev, "p%ds%d: desired rev: 0x%x, desired build: 0x%x",
+		   port_num, serdes, fw_rev, fw_build);
+
+	if (!sbl->is_hw)
+		return 0;
+
+	if (sbl_serdes_spico_int(sbl, port_num, serdes, SPICO_INT_CM4_REV_ID,
+				 SPICO_INT_DATA_NONE, &curr_fw_rev,
+				 SPICO_INT_RETURN_RESULT)) {
+		/* Failure expected when Spico is in reset */
+		sbl_dev_dbg(sbl->dev, "p%ds%d: Failed to read firmware rev!",
+			    port_num, serdes);
+	}
+	if (sbl_serdes_spico_int(sbl, port_num, serdes, SPICO_INT_CM4_BUILD_ID,
+				 SPICO_INT_DATA_NONE, &curr_fw_build,
+				 SPICO_INT_RETURN_RESULT)) {
+		/* Failure expected when Spico is in reset */
+		sbl_dev_dbg(sbl->dev, "p%ds%d: Failed to read firmware build!",
+			    port_num, serdes);
+	}
+
+	err = sbl_validate_serdes_fw_crc(sbl, port_num, serdes);
+	if (err) {
+		sbl_dev_warn(sbl->dev, "p%ds%d: Failed CRC check",
+			     port_num, serdes);
+		return -1;
+	}
+
+	if (((int)curr_fw_rev == fw_rev) && ((int)curr_fw_build == fw_build)) {
+		sbl_dev_dbg(sbl->dev, "p%ds%d: Found expected rev: 0x%x_%x",
+			    port_num, serdes, curr_fw_rev, curr_fw_build);
+		return 0;
+	}
+	sbl_dev_warn(sbl->dev, "p%ds%d: Expected rev: 0x%x_%x Current rev: 0x%x_%x",
+		     port_num, serdes, fw_rev, fw_build,
+			curr_fw_rev, curr_fw_build);
+	return -1;
+}
+
+/* does the CRC check */
+int sbl_sbm_firm_upload(struct sbl_inst *sbl, int sbus_ring,
+			size_t fw_size, const u8 *fw_data)
+{
+	u32 sbus_addr, unused, crc_result;
+	int err;
+
+	if (!sbl->is_hw)
+		return 0;
+
+	/* SBUS Critical Section */
+	mutex_lock(SBUS_RING_MTX(sbl, sbus_ring));
+
+	sbus_addr = SBUS_ADDR(sbus_ring, SBUS_BCAST_SBM_SPICO);
+
+	err = sbl_sbus_op_aux(sbl, sbus_addr, SPICO_SBR_ADDR_IP_IDCODE,
+			      SBUS_IFACE_DST_CORE | SBUS_CMD_RESET,
+				   SPICO_SBR_DATA_NONE, &unused);
+	if (err)
+		goto err_out;
+
+	err = sbl_sbus_wr(sbl, sbus_addr, SPICO_SBR_ADDR_CTL,
+			  SPICO_SBR_DATA_RESET_HIGH);
+	if (err)
+		goto err_out;
+
+	err = sbl_sbus_wr(sbl, sbus_addr, SPICO_SBR_ADDR_CTL,
+			  SPICO_SBR_DATA_RESET_LOW);
+	if (err)
+		goto err_out;
+
+	err = sbl_sbus_wr(sbl, sbus_addr, SPICO_SBR_ADDR_CTL,
+			  SPICO_SBR_DATA_IMEM_CNTL_EN);
+	if (err)
+		goto err_out;
+
+	err = sbl_sbus_wr(sbl, sbus_addr, SPICO_SBR_ADDR_IMEM,
+			  SPICO_SBR_DATA_NONE);
+	if (err)
+		goto err_out;
+
+	err = sbl_sbus_wr(sbl, sbus_addr, SPICO_SBR_ADDR_IMEM,
+			  SPICO_SBR_DATA_SET_BURST_WR);
+	if (err)
+		goto err_out;
+
+	err = sbl_spico_burst_upload(sbl, sbus_addr,
+				     SPICO_SBR_ADDR_IMEM_BURST_DATA,
+					  fw_size, fw_data);
+	if (err) {
+		sbl_dev_err(sbl->dev, "Upload failed!");
+		goto err_out;
+	}
+
+	err = sbl_sbus_wr(sbl, sbus_addr, SPICO_SBR_ADDR_IMEM,
+			  SPICO_SBR_DATA_SET_BURST_WR | fw_size);
+	if (err)
+		goto err_out;
+
+	err = sbl_sbus_wr(sbl, sbus_addr, SPICO_SBR_ADDR_IMEM,
+			  SPICO_SBR_DATA_SET_BURST_WR |
+			       (fw_size + 1));
+	if (err)
+		goto err_out;
+
+	err = sbl_sbus_wr(sbl, sbus_addr, SPICO_SBR_ADDR_IMEM,
+			  SPICO_SBR_DATA_SET_BURST_WR |
+			       (fw_size + 2));
+	if (err)
+		goto err_out;
+
+	err = sbl_sbus_wr(sbl, sbus_addr, SPICO_SBR_ADDR_IMEM,
+			  SPICO_SBR_DATA_SET_BURST_WR |
+			       (fw_size + 3));
+	if (err)
+		goto err_out;
+
+	err = sbl_sbus_wr(sbl, sbus_addr, SPICO_SBR_ADDR_CTL,
+			  SPICO_SBR_DATA_IMEM_CNTL_DIS);
+	if (err)
+		goto err_out;
+
+	err = sbl_sbus_wr(sbl, sbus_addr, SPICO_SBR_ADDR_ECC,
+			  SPICO_SBR_DATA_ECC_EN);
+	if (err)
+		goto err_out;
+
+	err = sbl_sbus_wr(sbl, sbus_addr, SPICO_SBR_ADDR_CTL,
+			  SPICO_SBR_DATA_SPICO_EN);
+	if (err)
+		goto err_out;
+
+	err = sbl_sbm_spico_int(sbl, sbus_addr, SPICO_INT_SBMS_DO_CRC,
+				SPICO_INT_DATA_NONE, &crc_result);
+	if (err)
+		goto err_out;
+
+	if (crc_result != SPICO_RESULT_SBR_CRC_PASS) {
+		sbl_dev_err(sbl->dev, "0x%x: CRC check fail (result 0x%x, expected 0x%x)!",
+			    sbus_addr, crc_result, SPICO_RESULT_SBR_CRC_PASS);
+		err = -EBADE;
+	}
+
+	/* Increment sbus master fw reload counter */
+	atomic_inc(&sbl->sbm_fw_reload_count[sbus_ring]);
+
+err_out:
+	mutex_unlock(SBUS_RING_MTX(sbl, sbus_ring));
+	return err;
+}
+
+int sbl_serdes_firm_upload(struct sbl_inst *sbl, int port_num, size_t fw_size,
+			   const u8 *fw_data)
+{
+	int serdes;
+	u32 sbus_addr;
+	u64 core_status_value;
+	int sbus_ring;
+	int err = -1;
+	int port, first_port, last_port, first_ring, last_ring;
+	int first_serdes, last_serdes;
+	unsigned long last_jiffy;
+
+	if (port_num == SBL_ALL_PORTS) {
+		sbl_dev_dbg(sbl->dev, "Loading SerDes firmware for all ports...");
+		first_port = 0;
+		last_port = sbl->switch_info->num_ports - 1;
+		first_serdes = 0; /* force to a single iteration */
+		last_serdes = 0;
+		first_ring = 0;
+		last_ring = sbl->switch_info->num_sbus_rings - 1;
+	} else {
+		sbl_dev_dbg(sbl->dev, "p%d: Loading SerDes firmware...", port_num);
+		first_port = port_num;
+		last_port = port_num;
+		first_serdes = 0;
+		last_serdes = sbl->switch_info->num_serdes - 1;
+		/* All serdes for a given port are always on the same ring, so
+		   just use serdes 0 to determine the ring. */
+		first_ring = sbl->switch_info->ports[port_num].serdes[0].sbus_ring;
+		last_ring = sbl->switch_info->ports[port_num].serdes[0].sbus_ring;
+	}
+	for (port = first_port; port <= last_port; ++port) {
+		for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+			err = sbl_serdes_soft_reset(sbl, port, serdes);
+			if (err)
+				return err;
+		}
+	}
+
+	/* Don't allow SPICO interrupts while we are reloading firmware */
+	for (port = first_port; port <= last_port; ++port)
+		mutex_lock(&sbl->link[port].serdes_mtx);
+
+	sbl_dev_dbg(sbl->dev, "p%d: Flashing SerDes firmware...", port_num);
+	for (sbus_ring = first_ring; sbus_ring <= last_ring; ++sbus_ring) {
+
+		/* SBUS Critical Section */
+		mutex_lock(SBUS_RING_MTX(sbl, sbus_ring));
+
+		for (serdes = first_serdes; serdes <= last_serdes; ++serdes) {
+			if (port_num == SBL_ALL_PORTS)
+				sbus_addr = SBUS_ADDR(sbus_ring, SBUS_BCAST_CM4_SERDES_SPICO);
+			else
+				sbus_addr = SBUS_ADDR(sbl->switch_info->ports[port_num].serdes[serdes].sbus_ring,
+						      sbl->switch_info->ports[port_num].serdes[serdes].rx_addr);
+
+			err = sbl_sbus_wr(sbl, sbus_addr,
+					  SPICO_SERDES_ADDR_RESET_EN,
+				       SPICO_SERDES_DATA_SET_GLOBAL_RESET);
+			if (err)
+				break;
+
+			err = sbl_sbus_wr(sbl, sbus_addr,
+					  SPICO_SERDES_ADDR_RESET_EN,
+				       SPICO_SERDES_DATA_CLR_GLOBAL_RESET);
+			if (err)
+				break;
+
+			err = sbl_sbus_wr(sbl, sbus_addr,
+					  SPICO_SERDES_ADDR_INTR_DIS,
+				       SPICO_SERDES_DATA_SET_INTR_DIS);
+			if (err)
+				break;
+
+			err = sbl_sbus_wr(sbl, sbus_addr,
+					  SPICO_SERDES_ADDR_IMEM,
+				       SPICO_SERDES_DATA_SET_IMEM_CNTL_EN);
+			if (err)
+				break;
+
+			err = sbl_spico_burst_upload(sbl, sbus_addr,
+						     SPICO_SERDES_ADDR_IMEM_BURST,
+						  fw_size, fw_data);
+			if (err) {
+				sbl_dev_err(sbl->dev, "Upload failed!");
+				break;
+			}
+
+			err = sbl_sbus_wr(sbl, sbus_addr,
+					  SPICO_SERDES_ADDR_IMEM,
+				       SPICO_SERDES_DATA_CLR_IMEM_CNTL_EN);
+			if (err)
+				break;
+
+			err = sbl_sbus_wr(sbl, sbus_addr,
+					  SPICO_SERDES_ADDR_ECC,
+				       SPICO_SERDES_DATA_SET_ECC_EN);
+			if (err)
+				break;
+
+			err = sbl_sbus_wr(sbl, sbus_addr,
+					  SPICO_SERDES_ADDR_ECCLOG,
+				       SPICO_SERDES_DATA_CLR_ECC_ERR);
+			if (err)
+				break;
+
+			err = sbl_sbus_wr(sbl, sbus_addr,
+					  SPICO_SERDES_ADDR_RESET_EN,
+				       SPICO_SERDES_DATA_SET_SPICO_EN);
+			if (err)
+				break;
+
+			err = sbl_sbus_wr(sbl, sbus_addr,
+					  SPICO_SERDES_ADDR_INTR_DIS,
+				       SPICO_SERDES_DATA_SET_INTR_EN);
+			if (err)
+				break;
+		}
+
+		mutex_unlock(SBUS_RING_MTX(sbl, sbus_ring));
+
+		if (err)
+			break;
+	}
+
+	for (port = first_port; port <= last_port; ++port)
+		mutex_unlock(&sbl->link[port].serdes_mtx);
+
+	/* If any errors occurred above, return now we've unlocked all mutexes. */
+	if (err)
+		return err;
+
+	/* Increment SerDes firmware reload counters */
+	if (port_num != SBL_ALL_PORTS)
+		for (serdes = first_serdes; serdes <= last_serdes; ++serdes)
+			sbl_link_counters_incr(sbl, port_num, serdes0_fw_reload + serdes);
+
+	if (!sbl->is_hw)
+		return 0;
+
+	sbl_dev_dbg(sbl->dev, "p%d: Validating flash..", port_num);
+	for (port = first_port; port <= last_port; ++port) {
+		for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+			sbus_addr =
+				SBUS_ADDR(sbl->switch_info->ports[port].serdes[serdes].sbus_ring,
+					  sbl->switch_info->ports[port].serdes[serdes].rx_addr);
+			last_jiffy = jiffies + msecs_to_jiffies(1000 *
+								 sbl->iattr.core_status_rd_timeout);
+			do {
+				core_status_value = sbl_read64(sbl, SBL_PML_BASE(port) |
+							       SBL_PML_SERDES_CORE_STATUS_OFFSET(serdes));
+				if (core_status_value &
+				    SERDES_CORE_STATUS_SPICO_READY_MASK) {
+					break;
+				}
+				msleep(sbl->iattr.core_status_rd_poll_interval);
+			} while (time_is_after_jiffies(last_jiffy));
+
+			if (!(core_status_value & (1 << 5))) {
+				sbl_dev_err(sbl->dev, "p%ds%d Timeout reading o_core_status (timeout:%ds)",
+					    port_num, serdes, sbl->iattr.core_status_rd_timeout);
+				return -ETIME;
+			}
+
+			err = sbl_validate_serdes_fw_crc(sbl, port, serdes);
+			if (err)
+				return err;
+
+		}
+	}
+	sbl_dev_dbg(sbl->dev, "p%d: FW upload complete!", port_num);
+
+	return 0;
+}
+
+static int sbl_get_serdes_tuning_params(struct sbl_inst *sbl, int port_num,
+					struct sbl_tuning_params *tps)
+{
+	int i, serdes, err;
+
+	if (!tps)
+		return -EINVAL;
+
+	tps->magic = SBL_TUNING_PARAM_MAGIC;
+	tps->version = SBL_TUNING_PARAM_VERSION;
+
+	for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+		if (!rx_serdes_required_for_link_mode(sbl, port_num, serdes))
+			continue;
+
+		for (i = 0; i < NUM_CTLE_PARAMS; ++i) {
+			err = sbl_serdes_spico_int(sbl, port_num, serdes,
+						   SPICO_INT_CM4_HAL_READ,
+					SPICO_INT_DATA_HAL_CTLE_BASE | i,
+					&tps->params[serdes].ctle[i],
+					SPICO_INT_RETURN_RESULT);
+			if (err)
+				return err;
+
+			sbl_dev_dbg(sbl->dev, "p%ds%d: CTLE[%d]: %d",
+				    port_num, serdes, i,
+					tps->params[serdes].ctle[i]);
+		}
+		for (i = 0; i < NUM_FFE_PARAMS; ++i) {
+			err = sbl_serdes_spico_int(sbl, port_num, serdes,
+						   SPICO_INT_CM4_HAL_READ,
+					SPICO_INT_DATA_HAL_FFE_BASE | i,
+					&tps->params[serdes].ffe[i],
+					SPICO_INT_RETURN_RESULT);
+			if (err)
+				return err;
+
+			sbl_dev_dbg(sbl->dev, "p%ds%d: FFE[%d]: %d",
+				    port_num, serdes, i,
+					tps->params[serdes].ffe[i]);
+		}
+		for (i = 0; i < NUM_DFE_PARAMS; ++i) {
+			err = sbl_serdes_spico_int(sbl, port_num, serdes,
+						   SPICO_INT_CM4_HAL_READ,
+					SPICO_INT_DATA_HAL_DFE_BASE | i,
+					&tps->params[serdes].dfe[i],
+					SPICO_INT_RETURN_RESULT);
+			if (err)
+				return err;
+
+			sbl_dev_dbg(sbl->dev, "p%ds%d: DFE[%d]: %d",
+				    port_num, serdes, i,
+					tps->params[serdes].dfe[i]);
+		}
+		for (i = 0; i < NUM_RXVS_PARAMS; ++i) {
+			err = sbl_serdes_spico_int(sbl, port_num, serdes,
+						   SPICO_INT_CM4_HAL_READ,
+					SPICO_INT_DATA_HAL_RXVS_BASE |
+						(i + SPICO_INT_DATA_HAL_RXVS_OFFSET),
+					&tps->params[serdes].rxvs[i],
+					SPICO_INT_RETURN_RESULT);
+			if (err)
+				return err;
+
+			sbl_dev_dbg(sbl->dev, "p%ds%d: RXVS[%d]: %d",
+				    port_num, serdes, i,
+					tps->params[serdes].rxvs[i]);
+		}
+		for (i = 0; i < NUM_RXVC_PARAMS; ++i) {
+			err = sbl_serdes_spico_int(sbl, port_num, serdes,
+						   SPICO_INT_CM4_HAL_READ,
+					SPICO_INT_DATA_HAL_RXVC_BASE | i,
+					&tps->params[serdes].rxvc[i],
+					SPICO_INT_RETURN_RESULT);
+			if (err)
+				return err;
+
+			sbl_dev_dbg(sbl->dev, "p%ds%d: RXVC[%d]: %d",
+				    port_num, serdes, i,
+					tps->params[serdes].rxvc[i]);
+		}
+		for (i = 0; i < NUM_RSDO_PARAMS; ++i) {
+			err = sbl_serdes_spico_int(sbl, port_num, serdes,
+						   SPICO_INT_CM4_HAL_READ,
+					SPICO_INT_DATA_HAL_RSDO_BASE | i,
+					&tps->params[serdes].rsdo[i],
+					SPICO_INT_RETURN_RESULT);
+			if (err)
+				return err;
+
+			sbl_dev_dbg(sbl->dev, "p%ds%d: RSDO[%d]: %d",
+				    port_num, serdes, i,
+					tps->params[serdes].rsdo[i]);
+		}
+		for (i = 0; i < NUM_RSDC_PARAMS; ++i) {
+			err = sbl_serdes_spico_int(sbl, port_num, serdes,
+						   SPICO_INT_CM4_HAL_READ,
+					SPICO_INT_DATA_HAL_RSDC_BASE | i,
+					&tps->params[serdes].rsdc[i],
+					SPICO_INT_RETURN_RESULT);
+			if (err)
+				return err;
+
+			sbl_dev_dbg(sbl->dev, "p%ds%d: RSDC[%d]: %d",
+				    port_num, serdes, i,
+					tps->params[serdes].rsdc[i]);
+		}
+		for (i = 0; i < NUM_RSTO_PARAMS; ++i) {
+			err = sbl_serdes_spico_int(sbl, port_num, serdes,
+						   SPICO_INT_CM4_HAL_READ,
+					SPICO_INT_DATA_HAL_RSTO_BASE | i,
+					&tps->params[serdes].rsto[i],
+					SPICO_INT_RETURN_RESULT);
+			if (err)
+				return err;
+
+			sbl_dev_dbg(sbl->dev, "p%ds%d: RSTO[%d]: %d",
+				    port_num, serdes, i,
+					tps->params[serdes].rsto[i]);
+		}
+		for (i = 0; i < NUM_RSTC_PARAMS; ++i) {
+			err = sbl_serdes_spico_int(sbl, port_num, serdes,
+						   SPICO_INT_CM4_HAL_READ,
+					SPICO_INT_DATA_HAL_RSTC_BASE | i,
+					&tps->params[serdes].rstc[i],
+					SPICO_INT_RETURN_RESULT);
+			if (err)
+				return err;
+
+			sbl_dev_dbg(sbl->dev, "p%ds%d: RSTC[%d]: %d",
+				    port_num, serdes, i,
+					tps->params[serdes].rstc[i]);
+		}
+		for (i = 0; i < NUM_EH_PARAMS; ++i) {
+			err = sbl_serdes_spico_int(sbl, port_num, serdes,
+						   SPICO_INT_CM4_HAL_READ,
+					SPICO_INT_DATA_HAL_EH_BASE | i,
+					&tps->params[serdes].eh[i],
+					SPICO_INT_RETURN_RESULT);
+			if (err)
+				return err;
+
+			sbl_dev_dbg(sbl->dev, "p%ds%d: EH[%d]: %d",
+				    port_num, serdes, i,
+					tps->params[serdes].eh[i]);
+		}
+		for (i = 0; i < NUM_GTP_PARAMS; ++i) {
+			err = sbl_serdes_spico_int(sbl, port_num, serdes,
+						   SPICO_INT_CM4_HAL_READ,
+					SPICO_INT_DATA_HAL_GTP_BASE | i,
+					&tps->params[serdes].gtp[i],
+					SPICO_INT_RETURN_RESULT);
+			if (err)
+				return err;
+
+			sbl_dev_dbg(sbl->dev, "p%ds%d: GTP[%d]: %d",
+				    port_num, serdes, i,
+					tps->params[serdes].gtp[i]);
+		}
+		for (i = 0; i < NUM_DCCD_PARAMS; ++i) {
+			err = sbl_serdes_spico_int(sbl, port_num, serdes,
+						   SPICO_INT_CM4_HAL_READ,
+					SPICO_INT_DATA_HAL_DCCD_BASE | i,
+					&tps->params[serdes].dccd[i],
+					SPICO_INT_RETURN_RESULT);
+			if (err)
+				return err;
+
+			sbl_dev_dbg(sbl->dev, "p%ds%d: DCCD[%d]: %d",
+				    port_num, serdes, i,
+					tps->params[serdes].dccd[i]);
+		}
+		for (i = 0; i < NUM_P4LV_PARAMS; ++i) {
+			err = sbl_serdes_spico_int(sbl, port_num, serdes,
+						   SPICO_INT_CM4_HAL_READ,
+					SPICO_INT_DATA_HAL_P4LV_BASE | i,
+					&tps->params[serdes].p4lv[i],
+					SPICO_INT_RETURN_RESULT);
+			if (err)
+				return err;
+
+			sbl_dev_dbg(sbl->dev, "p%ds%d: P4LV[%d]: %d",
+				    port_num, serdes, i,
+					tps->params[serdes].p4lv[i]);
+		}
+
+		if (sbl_validate_serdes_fw_vers(sbl, port_num, serdes,
+						SBL_KNOWN_FW0_REV,
+					SBL_KNOWN_FW0_BUILD)) {
+			return -EADDRNOTAVAIL;
+		}
+
+		for (i = 0; i < NUM_AFEC_PARAMS; ++i) {
+			err = sbl_serdes_spico_int(sbl, port_num, serdes,
+						   SPICO_INT_CM4_MEM_READ |
+						(SBUS_AFE_CTRL_KNOWN_FW0_BASE + i), 0x0,
+					&tps->params[serdes].afec[i],
+					SPICO_INT_RETURN_RESULT);
+			if (err)
+				return err;
+
+			sbl_dev_dbg(sbl->dev, "p%ds%d: AFEC[%d]: %d",
+				    port_num, serdes, i,
+					tps->params[serdes].afec[i]);
+		}
+	}
+
+	return 0;
+}
+
+int sbl_check_serdes_tuning_params(struct sbl_inst *sbl, int port_num)
+{
+	int i, serdes, err;
+	struct sbl_tuning_params *tps;
+	int min, max;
+	int num_oob_params;
+	int max_oob_params = SBL_MAX_OOB_SERDES_PARAMS;
+
+	tps = kzalloc(sizeof(struct sbl_tuning_params), GFP_KERNEL);
+	if (!tps)
+		return -ENOMEM;
+
+	/* debug adjustment to number of oob tuning params allowed */
+	if (sbl_debug_option(sbl, port_num, SBL_DEBUG_BAD_PARAM_1))
+		max_oob_params += 1;
+	if (sbl_debug_option(sbl, port_num, SBL_DEBUG_BAD_PARAM_2))
+		max_oob_params += 2;
+
+	err = sbl_get_serdes_tuning_params(sbl, port_num, tps);
+	if (err) {
+		kfree(tps);
+		return err;
+	}
+
+	if (!sbl->is_hw) {
+		kfree(tps);
+		return 0;
+	}
+
+	for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+		if (!rx_serdes_required_for_link_mode(sbl, port_num, serdes))
+			continue;
+
+		num_oob_params = 0;
+		for (i = 0; i < NUM_CTLE_PARAMS; ++i) {
+			switch (i) {
+			case CTLE_HF_OFFSET:
+				min = SBL_CTLE_HF_MIN;
+				max = SBL_CTLE_HF_MAX;
+				break;
+			case CTLE_LF_OFFSET:
+				min = SBL_CTLE_LF_MIN;
+				max = SBL_CTLE_LF_MAX;
+				break;
+			case CTLE_DC_OFFSET:
+				min = SBL_CTLE_DC_MIN;
+				max = SBL_CTLE_DC_MAX;
+				break;
+			case CTLE_BW_OFFSET:
+				min = SBL_CTLE_BW_MIN;
+				max = SBL_CTLE_BW_MAX;
+				break;
+			case CTLE_GS1_OFFSET:
+				min = SBL_CTLE_GS1_MIN;
+				max = SBL_CTLE_GS1_MAX;
+				break;
+			case CTLE_GS2_OFFSET:
+				min = SBL_CTLE_GS2_MIN;
+				max = SBL_CTLE_GS2_MAX;
+				break;
+			case CTLE_SCE_OFFSET:
+				min = SBL_CTLE_SCE_MIN;
+				max = SBL_CTLE_SCE_MAX;
+				break;
+			case CTLE_HF_MIN_OFFSET:
+				min = SBL_CTLE_HF_MIN_MIN;
+				max = SBL_CTLE_HF_MIN_MAX;
+				break;
+			case CTLE_HF_MAX_OFFSET:
+				min = SBL_CTLE_HF_MAX_MIN;
+				max = SBL_CTLE_HF_MAX_MAX;
+				break;
+			case CTLE_LF_MIN_OFFSET:
+				min = SBL_CTLE_LF_MIN_MIN;
+				max = SBL_CTLE_LF_MIN_MAX;
+				break;
+			case CTLE_LF_MAX_OFFSET:
+				min = SBL_CTLE_LF_MAX_MIN;
+				max = SBL_CTLE_LF_MAX_MAX;
+				break;
+			default:
+				continue;
+			}
+			if ((tps->params[serdes].ctle[i] < min) ||
+			    (tps->params[serdes].ctle[i] > max)) {
+				sbl_dev_warn(sbl->dev, "p%ds%d: CTLE[%d] value(%d) out of bounds(%d:%d)!",
+					     port_num, serdes, i,
+					 tps->params[serdes].ctle[i], min, max);
+				num_oob_params++;
+			} else {
+				sbl_dev_dbg(sbl->dev, "p%ds%d: CTLE[%d] value(%d) within bounds(%d:%d)",
+					    port_num, serdes, i,
+					 tps->params[serdes].ctle[i], min, max);
+			}
+		}
+
+		for (i = 0; i < NUM_FFE_PARAMS; ++i) {
+			switch (i) {
+			case FFE_PRE2_OFFSET:
+				min = SBL_FFE_PRE2_MIN;
+				max = SBL_FFE_PRE2_MAX;
+				break;
+			case FFE_PRE1_OFFSET:
+				min = SBL_FFE_PRE1_MIN;
+				max = SBL_FFE_PRE1_MAX;
+				break;
+			case FFE_POST1_OFFSET:
+				min = SBL_FFE_POST1_MIN;
+				max = SBL_FFE_POST1_MAX;
+				break;
+			case FFE_BFLF_OFFSET:
+				min = SBL_FFE_BFLF_MIN;
+				max = SBL_FFE_BFLF_MAX;
+				break;
+			case FFE_BFHF_OFFSET:
+				min = SBL_FFE_BFHF_MIN;
+				max = SBL_FFE_BFHF_MAX;
+				break;
+			case FFE_DATARATE_OFFSET:
+				min = SBL_FFE_DATARATE_MIN;
+				max = SBL_FFE_DATARATE_MAX;
+				break;
+			case FFE_SCE_OFFSET:
+				min = SBL_FFE_SCE_MIN;
+				max = SBL_FFE_SCE_MAX;
+				break;
+			case FFE_PRE1_MIN_OFFSET:
+				min = SBL_FFE_PRE1_MIN_MIN;
+				max = SBL_FFE_PRE1_MIN_MAX;
+				break;
+			case FFE_PRE1_MAX_OFFSET:
+				min = SBL_FFE_PRE1_MAX_MIN;
+				max = SBL_FFE_PRE1_MAX_MAX;
+				break;
+			case FFE_PRE2_MIN_OFFSET:
+				min = SBL_FFE_PRE2_MIN_MIN;
+				max = SBL_FFE_PRE2_MIN_MAX;
+				break;
+			case FFE_PRE2_MAX_OFFSET:
+				min = SBL_FFE_PRE2_MAX_MIN;
+				max = SBL_FFE_PRE2_MAX_MAX;
+				break;
+			case FFE_BFLF_ICAL_OFFSET:
+				min = SBL_FFE_BFLF_ICAL_MIN;
+				max = SBL_FFE_BFLF_ICAL_MAX;
+				break;
+			case FFE_POST1_MIN_OFFSET:
+				min = SBL_FFE_POST1_MIN_MIN;
+				max = SBL_FFE_POST1_MIN_MAX;
+				break;
+			case FFE_POST1_MAX_OFFSET:
+				min = SBL_FFE_POST1_MAX_MIN;
+				max = SBL_FFE_POST1_MAX_MAX;
+				break;
+			default:
+				continue;
+			}
+			if ((tps->params[serdes].ffe[i] < min) ||
+			    (tps->params[serdes].ffe[i] > max)) {
+				sbl_dev_warn(sbl->dev, "p%ds%d: FFE[%d] value(%d) out of bounds(%d:%d)!",
+					     port_num, serdes, i,
+					 tps->params[serdes].ffe[i], min, max);
+				num_oob_params++;
+			} else {
+				sbl_dev_dbg(sbl->dev, "p%ds%d: FFE[%d] value(%d) within bounds(%d:%d)",
+					    port_num, serdes, i,
+					 tps->params[serdes].ffe[i], min, max);
+			}
+		}
+		for (i = 0; i < NUM_DFE_PARAMS; ++i) {
+			switch (i) {
+			case DFE_GT1_OFFSET:
+				min = SBL_DFE_GT1_MIN;
+				max = SBL_DFE_GT1_MAX;
+				break;
+			case DFE_GT2_OFFSET:
+				min = SBL_DFE_GT2_MIN;
+				max = SBL_DFE_GT2_MAX;
+				break;
+			case DFE_G2_OFFSET:
+				min = SBL_DFE_G2_MIN;
+				max = SBL_DFE_G2_MAX;
+				break;
+			case DFE_G3_OFFSET:
+				min = SBL_DFE_G3_MIN;
+				max = SBL_DFE_G3_MAX;
+				break;
+			case DFE_G4_OFFSET:
+				min = SBL_DFE_G4_MIN;
+				max = SBL_DFE_G4_MAX;
+				break;
+			case DFE_G5_OFFSET:
+				min = SBL_DFE_G5_MIN;
+				max = SBL_DFE_G5_MAX;
+				break;
+			case DFE_G6_OFFSET:
+				min = SBL_DFE_G6_MIN;
+				max = SBL_DFE_G6_MAX;
+				break;
+			case DFE_G7_OFFSET:
+				min = SBL_DFE_G7_MIN;
+				max = SBL_DFE_G7_MAX;
+				break;
+			case DFE_G8_OFFSET:
+				min = SBL_DFE_G8_MIN;
+				max = SBL_DFE_G8_MAX;
+				break;
+			case DFE_G9_OFFSET:
+				min = SBL_DFE_G9_MIN;
+				max = SBL_DFE_G9_MAX;
+				break;
+			case DFE_G10_OFFSET:
+				min = SBL_DFE_G10_MIN;
+				max = SBL_DFE_G10_MAX;
+				break;
+			case DFE_G11_OFFSET:
+				min = SBL_DFE_G11_MIN;
+				max = SBL_DFE_G11_MAX;
+				break;
+			case DFE_G12_OFFSET:
+				min = SBL_DFE_G12_MIN;
+				max = SBL_DFE_G12_MAX;
+				break;
+			case DFE_G13_OFFSET:
+				min = SBL_DFE_G13_MIN;
+				max = SBL_DFE_G13_MAX;
+				break;
+			default:
+				continue;
+			}
+			if ((tps->params[serdes].dfe[i] < min) ||
+			    (tps->params[serdes].dfe[i] > max)) {
+				sbl_dev_warn(sbl->dev, "p%ds%d: DFE[%d] value(%d) out of bounds(%d:%d)!",
+					     port_num, serdes, i,
+					 tps->params[serdes].dfe[i], min, max);
+				num_oob_params++;
+			} else {
+				sbl_dev_dbg(sbl->dev, "p%ds%d: DFE[%d] value(%d) within bounds(%d:%d)",
+					    port_num, serdes, i,
+					 tps->params[serdes].dfe[i], min, max);
+			}
+		}
+
+		if (num_oob_params > max_oob_params) {
+			sbl_dev_err(sbl->dev, "p%ds%d: Too many tuning params out of bounds(%d, max %d)!",
+				    port_num, serdes, num_oob_params, max_oob_params);
+			return -EDQUOT;
+		} else if (num_oob_params > 0) {
+			sbl_dev_info(sbl->dev, "p%ds%d: Some tuning params out of bounds(%d, max %d)",
+				     port_num, serdes, num_oob_params, max_oob_params);
+		}
+	}
+
+	kfree(tps);
+	return 0;
+}
+
+int sbl_save_serdes_tuning_params(struct sbl_inst *sbl, int port_num)
+{
+	int err;
+
+	sbl->link[port_num].tuning_params.tp_state_hash0 =
+		sbl_get_tp_hash0(sbl, port_num);
+	sbl->link[port_num].tuning_params.tp_state_hash1 =
+		sbl_get_tp_hash1(sbl, port_num);
+	sbl_dev_dbg(sbl->dev, "Updated hash0 to 0x%llx, hash1 to 0x%llx",
+		    sbl->link[port_num].tuning_params.tp_state_hash0,
+		sbl->link[port_num].tuning_params.tp_state_hash1);
+
+	err = sbl_get_serdes_tuning_params(sbl, port_num,
+					   &sbl->link[port_num].tuning_params);
+
+	return err;
+}
+
+int sbl_apply_serdes_tuning_params(struct sbl_inst *sbl, int port_num,
+				   int serdes)
+{
+	int i, err;
+	u16 result;
+
+	sbl_dev_dbg(sbl->dev, "p%ds%d: applying saved tuning params", port_num, serdes);
+
+	DEV_TRACE2(sbl->dev, "CTLE params");
+	for (i = 0; i < NUM_CTLE_PARAMS; ++i) {
+		DEV_TRACE2(sbl->dev, "%d ",
+			   sbl->link[port_num].tuning_params.params[serdes].ctle[i]);
+	}
+	DEV_TRACE2(sbl->dev, "RXFFE params");
+	for (i = 0; i < NUM_FFE_PARAMS; ++i) {
+		DEV_TRACE2(sbl->dev, "%d ",
+			   sbl->link[port_num].tuning_params.params[serdes].ffe[i]);
+	}
+	DEV_TRACE2(sbl->dev, "DFE params");
+	for (i = 0; i < NUM_DFE_PARAMS; ++i) {
+		DEV_TRACE2(sbl->dev, "%d ",
+			   sbl->link[port_num].tuning_params.params[serdes].dfe[i]);
+	}
+	DEV_TRACE2(sbl->dev, "RXVS params");
+	for (i = 0; i < NUM_RXVS_PARAMS; ++i) {
+		DEV_TRACE2(sbl->dev, "%d ",
+			   sbl->link[port_num].tuning_params.params[serdes].rxvs[i]);
+	}
+	DEV_TRACE2(sbl->dev, "RXVC params");
+	for (i = 0; i < NUM_RXVC_PARAMS; ++i) {
+		DEV_TRACE2(sbl->dev, "%d ",
+			   sbl->link[port_num].tuning_params.params[serdes].rxvc[i]);
+	}
+	DEV_TRACE2(sbl->dev, "RSDO params");
+	for (i = 0; i < NUM_RSDO_PARAMS; ++i) {
+		DEV_TRACE2(sbl->dev, "%d ",
+			   sbl->link[port_num].tuning_params.params[serdes].rsdo[i]);
+	}
+	DEV_TRACE2(sbl->dev, "RSDC params");
+	for (i = 0; i < NUM_RSDC_PARAMS; ++i) {
+		DEV_TRACE2(sbl->dev, "%d ",
+			   sbl->link[port_num].tuning_params.params[serdes].rsdc[i]);
+	}
+	DEV_TRACE2(sbl->dev, "RSTO params");
+	for (i = 0; i < NUM_RSTO_PARAMS; ++i) {
+		DEV_TRACE2(sbl->dev, "%d ",
+			   sbl->link[port_num].tuning_params.params[serdes].rsto[i]);
+	}
+	DEV_TRACE2(sbl->dev, "RSTC params");
+	for (i = 0; i < NUM_RSTC_PARAMS; ++i) {
+		DEV_TRACE2(sbl->dev, "%d ",
+			   sbl->link[port_num].tuning_params.params[serdes].rstc[i]);
+	}
+	DEV_TRACE2(sbl->dev, "EH params");
+	for (i = 0; i < NUM_EH_PARAMS; ++i) {
+		DEV_TRACE2(sbl->dev, "%d ",
+			   sbl->link[port_num].tuning_params.params[serdes].eh[i]);
+	}
+	DEV_TRACE2(sbl->dev, "GTP params");
+	for (i = 0; i < NUM_GTP_PARAMS; ++i) {
+		DEV_TRACE2(sbl->dev, "%d ",
+			   sbl->link[port_num].tuning_params.params[serdes].gtp[i]);
+	}
+	DEV_TRACE2(sbl->dev, "DCCD params");
+	for (i = 0; i < NUM_DCCD_PARAMS; ++i) {
+		DEV_TRACE2(sbl->dev, "%d ",
+			   sbl->link[port_num].tuning_params.params[serdes].dccd[i]);
+	}
+	DEV_TRACE2(sbl->dev, "P4LV params");
+	for (i = 0; i < NUM_P4LV_PARAMS; ++i) {
+		DEV_TRACE2(sbl->dev, "%d ",
+			   sbl->link[port_num].tuning_params.params[serdes].p4lv[i]);
+	}
+	DEV_TRACE2(sbl->dev, "AFEC params");
+	for (i = 0; i < NUM_AFEC_PARAMS; ++i) {
+		DEV_TRACE2(sbl->dev, "%d ",
+			   sbl->link[port_num].tuning_params.params[serdes].afec[i]);
+	}
+
+	for (i = 0; i < NUM_CTLE_PARAMS; ++i) {
+		/* GS1/GS2 are "config values" - don't apply them from saved
+		   "turning params", as this will override the desired config */
+		if (((SPICO_INT_DATA_HAL_CTLE_BASE | i) ==
+		     SPICO_INT_DATA_HAL_CTLE_GS1) ||
+		    ((SPICO_INT_DATA_HAL_CTLE_BASE | i) ==
+		     SPICO_INT_DATA_HAL_CTLE_GS2)) {
+			continue;
+		}
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_HAL_READ,
+						SPICO_INT_DATA_HAL_CTLE_BASE | i,
+						&result, SPICO_INT_RETURN_RESULT);
+		if (err)
+			return err;
+
+		DEV_TRACE2(sbl->dev, "Updating CLTE param %d from 0x%x to 0x%x",
+			   i, result, sbl->link[port_num].tuning_params.params[serdes].ctle[i]);
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_HAL_WRITE,
+						sbl->link[port_num].tuning_params.params[serdes].ctle[i],
+						&result, SPICO_INT_RETURN_RESULT);
+		if (err)
+			return err;
+
+		if (result != SPICO_INT_CM4_HAL_READ) {
+			sbl_dev_err(sbl->dev, "p%ds%d: Failed updating CTLE[%d] tuning param!",
+				    port_num, serdes, i);
+			return -EBADE;
+		}
+	}
+	for (i = 0; i < NUM_FFE_PARAMS; ++i) {
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_HAL_READ,
+						SPICO_INT_DATA_HAL_FFE_BASE | i,
+						&result, SPICO_INT_RETURN_RESULT);
+		if (err)
+			return err;
+
+		DEV_TRACE2(sbl->dev, "Updating FFE param %d from 0x%x to 0x%x",
+			   i, result, sbl->link[port_num].tuning_params.params[serdes].ffe[i]);
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_HAL_WRITE,
+						sbl->link[port_num].tuning_params.params[serdes].ffe[i],
+						&result, SPICO_INT_RETURN_RESULT);
+		if (err)
+			return err;
+
+		if (result != SPICO_INT_CM4_HAL_READ) {
+			sbl_dev_err(sbl->dev, "p%ds%d: Failed updating FFE[%d] tuning param!",
+				    port_num, serdes, i);
+			return -EBADE;
+		}
+	}
+	for (i = 0; i < NUM_DFE_PARAMS; ++i) {
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_HAL_READ,
+						SPICO_INT_DATA_HAL_DFE_BASE | i,
+						&result, SPICO_INT_RETURN_RESULT);
+		if (err)
+			return err;
+
+		DEV_TRACE2(sbl->dev, "Updating DFE param %d from 0x%x to 0x%x",
+			   i, result, sbl->link[port_num].tuning_params.params[serdes].dfe[i]);
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_HAL_WRITE,
+						sbl->link[port_num].tuning_params.params[serdes].dfe[i],
+						&result, SPICO_INT_RETURN_RESULT);
+		if (err)
+			return err;
+
+		if (result != SPICO_INT_CM4_HAL_READ) {
+			sbl_dev_err(sbl->dev, "p%ds%d: Failed updating DFE[%d] tuning param!",
+				    port_num, serdes, i);
+			return -EBADE;
+		}
+	}
+
+	for (i = 0; i < NUM_RXVS_PARAMS; ++i) {
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_HAL_READ,
+						SPICO_INT_DATA_HAL_RXVS_BASE |
+							(i + SPICO_INT_DATA_HAL_RXVS_OFFSET),
+						&result, SPICO_INT_RETURN_RESULT);
+		if (err)
+			return err;
+
+		DEV_TRACE2(sbl->dev, "Updating RXVS param %d from 0x%x to 0x%x",
+			   i, result, sbl->link[port_num].tuning_params.params[serdes].rxvs[i]);
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_HAL_WRITE,
+						sbl->link[port_num].tuning_params.params[serdes].rxvs[i],
+						&result, SPICO_INT_RETURN_RESULT);
+		if (err)
+			return err;
+
+		if (result != SPICO_INT_CM4_HAL_READ) {
+			sbl_dev_err(sbl->dev, "p%ds%d: Failed updating RXVS[%d] tuning param!",
+				    port_num, serdes, i);
+			return -EBADE;
+		}
+	}
+
+	for (i = 0; i < NUM_RXVC_PARAMS; ++i) {
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_HAL_READ,
+						SPICO_INT_DATA_HAL_RXVC_BASE | i,
+						&result, SPICO_INT_RETURN_RESULT);
+		if (err)
+			return err;
+
+		DEV_TRACE2(sbl->dev, "Updating RXVC param %d from 0x%x to 0x%x",
+			   i, result, sbl->link[port_num].tuning_params.params[serdes].rxvc[i]);
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_HAL_WRITE,
+						sbl->link[port_num].tuning_params.params[serdes].rxvc[i],
+						&result, SPICO_INT_RETURN_RESULT);
+		if (err)
+			return err;
+
+		if (result != SPICO_INT_CM4_HAL_READ) {
+			sbl_dev_err(sbl->dev, "p%ds%d: Failed updating RXVC[%d] tuning param!",
+				    port_num, serdes, i);
+			return -EBADE;
+		}
+	}
+
+	for (i = 0; i < NUM_RSDO_PARAMS; ++i) {
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_HAL_READ,
+						SPICO_INT_DATA_HAL_RSDO_BASE | i,
+						&result, SPICO_INT_RETURN_RESULT);
+		if (err)
+			return err;
+
+		DEV_TRACE2(sbl->dev, "Updating RSDO param %d from 0x%x to 0x%x",
+			   i, result, sbl->link[port_num].tuning_params.params[serdes].rsdo[i]);
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_HAL_WRITE,
+						sbl->link[port_num].tuning_params.params[serdes].rsdo[i],
+						&result, SPICO_INT_RETURN_RESULT);
+		if (err)
+			return err;
+
+		if (result != SPICO_INT_CM4_HAL_READ) {
+			sbl_dev_err(sbl->dev, "p%ds%d: Failed updating RSDO[%d] tuning param!",
+				    port_num, serdes, i);
+			return -EBADE;
+		}
+	}
+
+	for (i = 0; i < NUM_RSDC_PARAMS; ++i) {
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_HAL_READ,
+						SPICO_INT_DATA_HAL_RSDC_BASE | i,
+						&result, SPICO_INT_RETURN_RESULT);
+		if (err)
+			return err;
+
+		DEV_TRACE2(sbl->dev, "Updating RSDC param %d from 0x%x to 0x%x",
+			   i, result, sbl->link[port_num].tuning_params.params[serdes].rsdc[i]);
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_HAL_WRITE,
+						sbl->link[port_num].tuning_params.params[serdes].rsdc[i],
+						&result, SPICO_INT_RETURN_RESULT);
+		if (err)
+			return err;
+
+		if (result != SPICO_INT_CM4_HAL_READ) {
+			sbl_dev_err(sbl->dev, "p%ds%d: Failed updating RSDC[%d] tuning param!",
+				    port_num, serdes, i);
+			return -EBADE;
+		}
+	}
+
+	for (i = 0; i < NUM_RSTO_PARAMS; ++i) {
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_HAL_READ,
+						SPICO_INT_DATA_HAL_RSTO_BASE | i,
+						&result, SPICO_INT_RETURN_RESULT);
+		if (err)
+			return err;
+
+		DEV_TRACE2(sbl->dev, "Updating RSTO param %d from 0x%x to 0x%x",
+			   i, result, sbl->link[port_num].tuning_params.params[serdes].rsto[i]);
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_HAL_WRITE,
+						sbl->link[port_num].tuning_params.params[serdes].rsto[i],
+						&result, SPICO_INT_RETURN_RESULT);
+		if (err)
+			return err;
+
+		if (result != SPICO_INT_CM4_HAL_READ) {
+			sbl_dev_err(sbl->dev, "p%ds%d: Failed updating RSTO[%d] tuning param!",
+				    port_num, serdes, i);
+			return -EBADE;
+		}
+	}
+
+	for (i = 0; i < NUM_RSTC_PARAMS; ++i) {
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_HAL_READ,
+						SPICO_INT_DATA_HAL_RSTC_BASE | i,
+						&result, SPICO_INT_RETURN_RESULT);
+		if (err)
+			return err;
+
+		DEV_TRACE2(sbl->dev, "Updating RSTC param %d from 0x%x to 0x%x",
+			   i, result, sbl->link[port_num].tuning_params.params[serdes].rstc[i]);
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_HAL_WRITE,
+						sbl->link[port_num].tuning_params.params[serdes].rstc[i],
+						&result, SPICO_INT_RETURN_RESULT);
+		if (err)
+			return err;
+
+		if (result != SPICO_INT_CM4_HAL_READ) {
+			sbl_dev_err(sbl->dev, "p%ds%d: Failed updating RSTC[%d] tuning param!",
+				    port_num, serdes, i);
+			return -EBADE;
+		}
+	}
+
+	for (i = 0; i < NUM_EH_PARAMS; ++i) {
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_HAL_READ,
+						SPICO_INT_DATA_HAL_EH_BASE | i,
+						&result, SPICO_INT_RETURN_RESULT);
+		if (err)
+			return err;
+
+		DEV_TRACE2(sbl->dev, "Updating EH param %d from 0x%x to 0x%x",
+			   i, result, sbl->link[port_num].tuning_params.params[serdes].eh[i]);
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_HAL_WRITE,
+						sbl->link[port_num].tuning_params.params[serdes].eh[i],
+						&result, SPICO_INT_RETURN_RESULT);
+		if (err)
+			return err;
+
+		if (result != SPICO_INT_CM4_HAL_READ) {
+			sbl_dev_err(sbl->dev, "p%ds%d: Failed updating EH[%d] tuning param!",
+				    port_num, serdes, i);
+			return -EBADE;
+		}
+	}
+
+	for (i = 0; i < NUM_GTP_PARAMS; ++i) {
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_HAL_READ,
+						SPICO_INT_DATA_HAL_GTP_BASE | i,
+						&result, SPICO_INT_RETURN_RESULT);
+		if (err)
+			return err;
+
+		DEV_TRACE2(sbl->dev, "Updating GTP param %d from 0x%x to 0x%x",
+			   i, result, sbl->link[port_num].tuning_params.params[serdes].gtp[i]);
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_HAL_WRITE,
+						sbl->link[port_num].tuning_params.params[serdes].gtp[i],
+						&result, SPICO_INT_RETURN_RESULT);
+		if (err)
+			return err;
+
+		if (result != SPICO_INT_CM4_HAL_READ) {
+			sbl_dev_err(sbl->dev, "p%ds%d: Failed updating GTP[%d] tuning param!",
+				    port_num, serdes, i);
+			return -EBADE;
+		}
+	}
+
+	for (i = 0; i < NUM_DCCD_PARAMS; ++i) {
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_HAL_READ,
+						SPICO_INT_DATA_HAL_DCCD_BASE | i,
+						&result, SPICO_INT_RETURN_RESULT);
+		if (err)
+			return err;
+
+		DEV_TRACE2(sbl->dev, "Updating DCCD param %d from 0x%x to 0x%x",
+			   i, result, sbl->link[port_num].tuning_params.params[serdes].dccd[i]);
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_HAL_WRITE,
+						sbl->link[port_num].tuning_params.params[serdes].dccd[i],
+						&result, SPICO_INT_RETURN_RESULT);
+		if (err)
+			return err;
+
+		if (result != SPICO_INT_CM4_HAL_READ) {
+			sbl_dev_err(sbl->dev, "p%ds%d: Failed updating DCCD[%d] tuning param!",
+				    port_num, serdes, i);
+			return -EBADE;
+		}
+	}
+
+	for (i = 0; i < NUM_P4LV_PARAMS; ++i) {
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_HAL_READ,
+						SPICO_INT_DATA_HAL_P4LV_BASE | i,
+						&result, SPICO_INT_RETURN_RESULT);
+		if (err)
+			return err;
+
+		DEV_TRACE2(sbl->dev, "Updating P4LV param %d from 0x%x to 0x%x",
+			   i, result, sbl->link[port_num].tuning_params.params[serdes].p4lv[i]);
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_HAL_WRITE,
+						sbl->link[port_num].tuning_params.params[serdes].p4lv[i],
+						&result, SPICO_INT_RETURN_RESULT);
+		if (err)
+			return err;
+
+		if (result != SPICO_INT_CM4_HAL_READ) {
+			sbl_dev_err(sbl->dev, "p%ds%d: Failed updating P4LV[%d] tuning param!",
+				    port_num, serdes, i);
+			return -EBADE;
+		}
+	}
+
+	if (sbl_validate_serdes_fw_vers(sbl, port_num, serdes,
+					SBL_KNOWN_FW0_REV,
+									SBL_KNOWN_FW0_BUILD)) {
+		return -EADDRNOTAVAIL;
+	}
+	for (i = 0; i < NUM_AFEC_PARAMS; ++i) {
+		DEV_TRACE2(sbl->dev, "Updating AFEC param %d to 0x%x",
+			   i, sbl->link[port_num].tuning_params.params[serdes].afec[i]);
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_MEM_WRITE |
+							(SBUS_AFE_CTRL_KNOWN_FW0_BASE + i),
+						sbl->link[port_num].tuning_params.params[serdes].afec[i],
+						&result, SPICO_INT_IGNORE_RESULT);
+		if (err)
+			return err;
+	}
+
+	/* Apply values */
+	err = sbl_serdes_spico_int(sbl, port_num, serdes,
+				   SPICO_INT_CM4_HAL_CALL,
+					SPICO_INT_DATA_HAL_CTLE_APPLY, NULL,
+					SPICO_INT_IGNORE_RESULT);
+	if (err)
+		return err;
+
+	err = sbl_serdes_spico_int(sbl, port_num, serdes,
+				   SPICO_INT_CM4_HAL_CALL,
+					SPICO_INT_DATA_HAL_FFE_APPLY, NULL,
+					SPICO_INT_IGNORE_RESULT);
+	if (err)
+		return err;
+
+	err = sbl_serdes_spico_int(sbl, port_num, serdes,
+				   SPICO_INT_CM4_HAL_CALL,
+					SPICO_INT_DATA_HAL_DFE_APPLY, NULL,
+					SPICO_INT_IGNORE_RESULT);
+	if (err)
+		return err;
+
+	err = sbl_serdes_spico_int(sbl, port_num, serdes,
+				   SPICO_INT_CM4_HAL_CALL,
+					SPICO_INT_DATA_HAL_RXV_APPLY, NULL,
+					SPICO_INT_IGNORE_RESULT);
+	if (err)
+		return err;
+
+	err = sbl_serdes_spico_int(sbl, port_num, serdes,
+				   SPICO_INT_CM4_HAL_CALL,
+					SPICO_INT_DATA_HAL_DC_APPLY, NULL,
+					SPICO_INT_IGNORE_RESULT);
+	if (err)
+		return err;
+
+	err = sbl_serdes_spico_int(sbl, port_num, serdes,
+				   SPICO_INT_CM4_HAL_CALL,
+					SPICO_INT_DATA_HAL_TC_APPLY, NULL,
+					SPICO_INT_IGNORE_RESULT);
+	if (err)
+		return err;
+
+	err = sbl_serdes_spico_int(sbl, port_num, serdes,
+				   SPICO_INT_CM4_HAL_CALL,
+					SPICO_INT_DATA_HAL_PCAL_SETUP, NULL,
+					SPICO_INT_IGNORE_RESULT);
+	if (err)
+		return err;
+
+	DEV_TRACE2(sbl->dev, "rc: 0");
+
+	return 0;
+}
+
+int sbl_get_eye_heights(struct sbl_inst *sbl, int port_num, int serdes,
+			int *eye_heights)
+{
+	u16 result;
+	int err;
+
+	if (!eye_heights) {
+		sbl_dev_err(sbl->dev, "Bad args");
+		return -EINVAL;
+	}
+
+	DEV_TRACE2(sbl->dev, "p%ds%d", port_num, serdes);
+	err = sbl_serdes_spico_int(sbl, port_num, serdes,
+				   SPICO_INT_CM4_GET_RX_EQ,
+					SPICO_INT_DATA_RXEQ_EH_THLE, &result,
+					SPICO_INT_RETURN_RESULT);
+	if (err) {
+		sbl_dev_err(sbl->dev, "p%ds%d: Failed to read setting!", port_num, serdes);
+		return err;
+	}
+	eye_heights[0] = result;
+	err = sbl_serdes_spico_int(sbl, port_num, serdes,
+				   SPICO_INT_CM4_GET_RX_EQ,
+					SPICO_INT_DATA_RXEQ_EH_THME, &result,
+					SPICO_INT_RETURN_RESULT);
+	if (err) {
+		sbl_dev_err(sbl->dev, "p%ds%d: Failed to read setting!", port_num, serdes);
+		return err;
+	}
+	eye_heights[1] = result;
+	err = sbl_serdes_spico_int(sbl, port_num, serdes,
+				   SPICO_INT_CM4_GET_RX_EQ,
+					SPICO_INT_DATA_RXEQ_EH_THUE, &result,
+					SPICO_INT_RETURN_RESULT);
+	if (err) {
+		sbl_dev_err(sbl->dev, "p%ds%d: Failed to read setting!", port_num, serdes);
+		return err;
+	}
+	eye_heights[2] = result;
+	err = sbl_serdes_spico_int(sbl, port_num, serdes,
+				   SPICO_INT_CM4_GET_RX_EQ,
+					SPICO_INT_DATA_RXEQ_EH_THLO, &result,
+					SPICO_INT_RETURN_RESULT);
+	if (err) {
+		sbl_dev_err(sbl->dev, "p%ds%d: Failed to read setting!", port_num, serdes);
+		return err;
+	}
+	eye_heights[3] = result;
+	err = sbl_serdes_spico_int(sbl, port_num, serdes,
+				   SPICO_INT_CM4_GET_RX_EQ,
+					SPICO_INT_DATA_RXEQ_EH_THMO, &result,
+					SPICO_INT_RETURN_RESULT);
+	if (err) {
+		sbl_dev_err(sbl->dev, "p%ds%d: Failed to read setting!", port_num, serdes);
+		return err;
+	}
+	eye_heights[4] = result;
+	err = sbl_serdes_spico_int(sbl, port_num, serdes,
+				   SPICO_INT_CM4_GET_RX_EQ,
+					SPICO_INT_DATA_RXEQ_EH_THUO, &result,
+					SPICO_INT_RETURN_RESULT);
+	if (err) {
+		sbl_dev_err(sbl->dev, "p%ds%d: Failed to read setting!", port_num, serdes);
+		return err;
+	}
+	eye_heights[5] = result;
+
+	DEV_TRACE2(sbl->dev, "rc: 0");
+
+	return 0;
+}
+
+int sbl_serdes_soft_reset(struct sbl_inst *sbl, int port_num, int serdes)
+{
+	u32 unused;
+	int err;
+	u32 sbus_ring = sbl->switch_info->ports[port_num].serdes[serdes].sbus_ring;
+	u32 sbus_addr =
+		SBUS_ADDR(sbus_ring,
+			  sbl->switch_info->ports[port_num].serdes[serdes].rx_addr);
+
+	DEV_TRACE2(sbl->dev, "p%ds%d", port_num, serdes);
+
+	/* Don't allow SPICO interrupts while we are resetting the SerDes */
+	mutex_lock(&sbl->link[port_num].serdes_mtx);
+	/* SBUS Critical Section */
+	mutex_lock(SBUS_RING_MTX(sbl, sbus_ring));
+
+	/* Reset high */
+	err = sbl_sbus_op_aux(sbl, sbus_addr, SPICO_SERDES_ADDR_IMEM,
+			      SBUS_IFACE_DST_CORE | SBUS_CMD_RESET,
+				   SPICO_SERDES_DATA_RESET, &unused);
+	if (err) {
+		mutex_unlock(SBUS_RING_MTX(sbl, sbus_ring));
+		mutex_unlock(&sbl->link[port_num].serdes_mtx);
+		return err;
+	}
+
+	/* Reset low */
+	err = sbl_sbus_wr(sbl, sbus_addr, SPICO_SERDES_ADDR_RESET_EN,
+			  SPICO_SERDES_DATA_CLR_GLOBAL_RESET);
+	if (err) {
+		mutex_unlock(SBUS_RING_MTX(sbl, sbus_ring));
+		mutex_unlock(&sbl->link[port_num].serdes_mtx);
+		return err;
+	}
+
+	/* Enable ECC */
+	err = sbl_sbus_wr(sbl, sbus_addr, SPICO_SERDES_ADDR_ECC,
+			  SPICO_SERDES_DATA_SET_ECC_EN);
+	if (err) {
+		mutex_unlock(SBUS_RING_MTX(sbl, sbus_ring));
+		mutex_unlock(&sbl->link[port_num].serdes_mtx);
+		return err;
+	}
+
+	/* Clear any ECC errors that occurred previously */
+	err = sbl_sbus_wr(sbl, sbus_addr, SPICO_SERDES_ADDR_ECCLOG,
+			  SPICO_SERDES_DATA_CLR_ECC_ERR);
+	if (err) {
+		mutex_unlock(SBUS_RING_MTX(sbl, sbus_ring));
+		mutex_unlock(&sbl->link[port_num].serdes_mtx);
+		return err;
+	}
+
+	/* Enable SPICO */
+	err = sbl_sbus_wr(sbl, sbus_addr, SPICO_SERDES_ADDR_RESET_EN,
+			  SPICO_SERDES_DATA_SET_SPICO_EN);
+	if (err) {
+		mutex_unlock(SBUS_RING_MTX(sbl, sbus_ring));
+		mutex_unlock(&sbl->link[port_num].serdes_mtx);
+		return err;
+	}
+
+	/* Enable interrupts */
+	err = sbl_sbus_wr(sbl, sbus_addr, SPICO_SERDES_ADDR_INTR_DIS,
+			  SPICO_SERDES_DATA_SET_INTR_EN);
+	if (err) {
+		mutex_unlock(SBUS_RING_MTX(sbl, sbus_ring));
+		mutex_unlock(&sbl->link[port_num].serdes_mtx);
+		return err;
+	}
+
+	mutex_unlock(SBUS_RING_MTX(sbl, sbus_ring));
+	mutex_unlock(&sbl->link[port_num].serdes_mtx);
+
+	DEV_TRACE2(sbl->dev, "rc: 0");
+
+	sbl->link[port_num].pcal_running = false;
+	return 0;
+}
+
+int sbl_serdes_init(struct sbl_inst *sbl, int port_num, int serdes,
+		    int encoding, int divisor, int width)
+{
+	int err;
+	bool tx_en, rx_en;
+
+	DEV_TRACE2(sbl->dev, "p%ds%d: encoding: %d divisor: %d width: %d",
+		   port_num, serdes, encoding, divisor, width);
+
+	err = sbl_set_tx_rx_enable(sbl, port_num, serdes, false, false,
+				   false);
+	if (err)
+		return err;
+
+	err = sbl_serdes_spico_int(sbl, port_num, serdes,
+				   SPICO_INT_CM4_PLL_RECAL,
+					SPICO_INT_DATA_NONE, NULL,
+					SPICO_INT_VALIDATE_RESULT);
+	if (err)
+		return err;
+
+	err = sbl_serdes_spico_int(sbl, port_num, serdes,
+				   SPICO_INT_CM4_TX_PHASE_CAL,
+					SPICO_INT_DATA_NONE, NULL,
+					SPICO_INT_VALIDATE_RESULT);
+	if (err)
+		return err;
+
+	err = sbl_serdes_spico_int(sbl, port_num, serdes,
+				   SPICO_INT_CM4_TX_BAUD,
+					(divisor & SPICO_INT_DIVIDER_MASK) |
+					SPICO_INT_DATA_TXTX_RC_NOT_SS,
+					NULL, SPICO_INT_VALIDATE_RESULT);
+	if (err)
+		return err;
+
+	err = sbl_serdes_spico_int(sbl, port_num, serdes,
+				   SPICO_INT_CM4_WIDTH_MODE,
+					encoding | width |
+					SPICO_INT_DATA_TXRX_FC_IGNORE, NULL,
+					SPICO_INT_VALIDATE_RESULT);
+	if (err)
+		return err;
+
+	/* tx/rx based on link mode, and always configuing physical lane 0 */
+	if (tx_serdes_required_for_link_mode(sbl, port_num, serdes))
+		tx_en = true;
+	else
+		tx_en = false;
+
+	if (rx_serdes_required_for_link_mode(sbl, port_num, serdes))
+		rx_en = true;
+	else
+		rx_en = false;
+
+	err = sbl_set_tx_rx_enable(sbl, port_num, serdes, tx_en, rx_en,
+				   false);
+	if (err)
+		return err;
+
+	err = sbl_serdes_spico_int(sbl, port_num, serdes,
+				   SPICO_INT_CM4_PCIE_SLICES,
+					SPICO_INT_DATA_TX_OVERRIDE, NULL,
+					SPICO_INT_VALIDATE_RESULT);
+	if (err)
+		return err;
+
+	err = sbl_serdes_spico_int(sbl, port_num, serdes,
+				   SPICO_INT_CM4_PCIE_SLICES,
+					SPICO_INT_DATA_RX_EID_EN, NULL,
+					SPICO_INT_VALIDATE_RESULT);
+	if (err)
+		return err;
+
+	/* Reset signal_ok */
+	sbl_serdes_mem_rmw(sbl, port_num, serdes, SERDES_MEM_ADDR_O_CORE_STATUS,
+			   0, SERDES_CORE_STATUS_RX_SIG_OK_MASK);
+
+	/* Set PRBS for loopback mode - will be changed later */
+	if (sbl->link[port_num].loopback_mode == SBL_LOOPBACK_MODE_LOCAL) {
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_PRBS_CTRL,
+						SPICO_INT_DATA_PRBS31_AS_TXGEN, NULL,
+						SPICO_INT_VALIDATE_RESULT);
+		if (err)
+			return err;
+
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_PRBS_CTRL,
+						SPICO_INT_DATA_PRBS31_AS_RXGEN, NULL,
+						SPICO_INT_VALIDATE_RESULT);
+		if (err)
+			return err;
+	}
+	DEV_TRACE2(sbl->dev, "rc: 0");
+
+	return 0;
+}
+
+int sbl_serdes_polarity_ctrl(struct sbl_inst *sbl, int port_num, int serdes,
+			     int encoding, bool an)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	u32 datapath = 0;
+	int err;
+
+	DEV_TRACE2(sbl->dev, "p%ds%d: encoding:0x%x", port_num, serdes, encoding);
+
+	/* Set Polarity Inversions */
+	switch (sbl->link[port_num].loopback_mode) {
+	case SBL_LOOPBACK_MODE_REMOTE:
+	case SBL_LOOPBACK_MODE_OFF:
+		if (sbl->switch_info->ports[port_num].serdes[serdes].txinv)
+			datapath |= SPICO_INT_DATA_SET_TXINV;
+		else
+			datapath |= SPICO_INT_DATA_CLR_TXINV;
+
+		if (sbl->switch_info->ports[port_num].serdes[serdes].rxinv)
+			datapath |= SPICO_INT_DATA_SET_RXINV;
+		else
+			datapath |= SPICO_INT_DATA_CLR_RXINV;
+
+		break;
+	case SBL_LOOPBACK_MODE_LOCAL:
+		datapath |= SPICO_INT_DATA_CLR_TXINV;
+		datapath |= SPICO_INT_DATA_CLR_RXINV;
+		break;
+	default:
+		sbl_dev_warn(sbl->dev, "%d: Unsupported loopback mode (%d)",
+			     port_num, sbl->link[port_num].loopback_mode);
+		return -EINVAL;
+	}
+
+	/* Set Precode */
+	if (encoding == SBL_ENC_PAM4) {
+		link->precoding_enabled = get_serdes_precoding(sbl, port_num);
+		if (link->precoding_enabled)
+			datapath |= SPICO_INT_DATA_SET_PRECODE;
+		else
+			datapath |= SPICO_INT_DATA_CLR_PRECODE;
+	} else {
+		datapath |= SPICO_INT_DATA_CLR_PRECODE;
+	}
+
+	/* Set Graycode & Swizzle */
+	if (an || (encoding == SBL_ENC_NRZ))
+		datapath |= SPICO_INT_DATA_CLR_GRAY_SWZ;
+	else
+		datapath |= SPICO_INT_DATA_SET_GRAY_SWZ;
+
+	err = sbl_serdes_spico_int(sbl, port_num, serdes,
+				   SPICO_INT_CM4_POLARITY_CTRL,
+					datapath, NULL,
+					SPICO_INT_VALIDATE_RESULT);
+	if (err)
+		return err;
+
+	return 0;
+}
+
+int sbl_set_tx_rx_enable(struct sbl_inst *sbl, int port_num, int serdes,
+			 bool tx_en, bool rx_en, bool txo_en)
+{
+	u32 int_data = 0;
+	u64 core_status_value;
+	int tx_rdy, rx_rdy;
+	unsigned long last_jiffy;
+	int err;
+
+	DEV_TRACE2(sbl->dev, "p%ds%d: tx_en: %d rx_en: %d txo_en: %d",
+		   port_num, serdes, tx_en, rx_en, txo_en);
+
+	if (!sbl->is_hw)
+		return 0;
+
+	if (tx_en)
+		int_data |= SPICO_INT_DATA_SET_TX_EN;
+
+	if (rx_en)
+		int_data |= SPICO_INT_DATA_SET_RX_EN;
+
+	if (txo_en)
+		int_data |= SPICO_INT_DATA_SET_TXO_EN;
+
+	err = sbl_serdes_spico_int(sbl, port_num, serdes,
+				   SPICO_INT_CM4_SERDES_EN,
+					int_data, NULL,
+					SPICO_INT_VALIDATE_RESULT);
+	if (err)
+		return err;
+
+	/* Wait for tx_rdy and rx_rdy to be set. */
+	last_jiffy = jiffies + msecs_to_jiffies(1000 * sbl->iattr.serdes_en_timeout);
+	do {
+		core_status_value = sbl_read64(sbl, SBL_PML_BASE(port_num) |
+					       SBL_PML_SERDES_CORE_STATUS_OFFSET(serdes));
+		tx_rdy = (core_status_value & SERDES_CORE_STATUS_TX_RDY_MASK) ? 1 : 0;
+		rx_rdy = (core_status_value & SERDES_CORE_STATUS_RX_RDY_MASK) ? 1 : 0;
+		if ((tx_rdy == tx_en) && (rx_rdy == rx_en))
+			break;
+		msleep(sbl->iattr.serdes_en_poll_interval);
+	} while (time_is_after_jiffies(last_jiffy));
+
+	if ((tx_rdy != tx_en) || (rx_rdy != rx_en)) {
+		sbl_dev_err(sbl->dev,
+			    "p%ds%d: Timeout setting tx/rx/txo enable! tx_en:%d rx_en:%d txo_en:%d tx_rdy:%d rx_rdy:%d (timeout:%ds)",
+			    port_num, serdes, tx_en, rx_en, txo_en, tx_rdy, rx_rdy,
+			    sbl->iattr.serdes_en_timeout);
+		return -ETIME;
+	}
+	DEV_TRACE2(sbl->dev, "rc 0");
+
+	return 0;
+}
+
+int sbl_set_tx_eq(struct sbl_inst *sbl, int port_num, int serdes,
+		  int atten, int pre, int post, int pre2, int pre3)
+{
+	int err, rc = 0;
+
+	DEV_TRACE2(sbl->dev,
+		   "p%ds%d: atten: %d pre: %d post: %d pre2: %d pre3: %d",
+		   port_num, serdes, atten, pre, post, pre2, pre3);
+
+	if ((atten < TXEQ_ATTEN_MIN) || (atten > TXEQ_ATTEN_MAX)) {
+		sbl_dev_err(sbl->dev,
+			    "Invalid value for atten(%d) Expected in the range of %d to %d",
+			atten, TXEQ_ATTEN_MIN, TXEQ_ATTEN_MAX);
+		return -EINVAL;
+	}
+	if ((pre < TXEQ_PRE1_MIN) || (pre > TXEQ_PRE1_MAX)) {
+		sbl_dev_err(sbl->dev,
+			    "Invalid value for pre(%d) Expected in the range of %d to %d",
+			pre, TXEQ_PRE1_MIN, TXEQ_PRE1_MAX);
+		return -EINVAL;
+	}
+	if ((post < TXEQ_POST_MIN) || (post > TXEQ_POST_MAX)) {
+		sbl_dev_err(sbl->dev,
+			    "Invalid value for post(%d) Expected in the range of %d to %d",
+			post, TXEQ_POST_MIN, TXEQ_POST_MAX);
+		return -EINVAL;
+	}
+	if ((pre2 < TXEQ_PRE2_MIN) || (pre2 > TXEQ_PRE2_MAX)) {
+		sbl_dev_err(sbl->dev,
+			    "Invalid value for pre2(%d) Expected in the range of %d to %d",
+			pre2, TXEQ_PRE2_MIN, TXEQ_PRE2_MAX);
+		return -EINVAL;
+	}
+	if ((pre3 < TXEQ_PRE3_MIN) || (pre3 > TXEQ_PRE3_MAX)) {
+		sbl_dev_err(sbl->dev,
+			    "Invalid value for pre3(%d) Expected in the range of %d to %d",
+			pre3, TXEQ_PRE3_MIN, TXEQ_PRE3_MAX);
+		return -EINVAL;
+	}
+
+	err = sbl_serdes_spico_int(sbl, port_num, serdes,
+				   SPICO_INT_CM4_TXEQ_LOAD,
+					SPICO_INT_DATA_SET_TXEQ_ATTEN |
+						(atten & SPICO_INT_DATA_TXEQ_DATA_MASK), NULL,
+					SPICO_INT_VALIDATE_RESULT);
+	if (err)
+		return err;
+
+	err = sbl_serdes_spico_int(sbl, port_num, serdes,
+				   SPICO_INT_CM4_TXEQ_LOAD,
+					SPICO_INT_DATA_SET_TXEQ_PRE1 |
+						(pre & SPICO_INT_DATA_TXEQ_DATA_MASK), NULL,
+					SPICO_INT_VALIDATE_RESULT);
+	if (err)
+		return err;
+
+	err = sbl_serdes_spico_int(sbl, port_num, serdes,
+				   SPICO_INT_CM4_TXEQ_LOAD,
+					SPICO_INT_DATA_SET_TXEQ_POST |
+						(post & SPICO_INT_DATA_TXEQ_DATA_MASK), NULL,
+					SPICO_INT_VALIDATE_RESULT);
+	if (err)
+		return err;
+
+	err = sbl_serdes_spico_int(sbl, port_num, serdes,
+				   SPICO_INT_CM4_TXEQ_LOAD,
+					SPICO_INT_DATA_SET_TXEQ_PRE2 |
+						(pre2 & SPICO_INT_DATA_TXEQ_DATA_MASK), NULL,
+					SPICO_INT_VALIDATE_RESULT);
+	if (err)
+		return err;
+
+	err = sbl_serdes_spico_int(sbl, port_num, serdes,
+				   SPICO_INT_CM4_TXEQ_LOAD,
+					SPICO_INT_DATA_SET_TXEQ_PRE3 |
+						(pre3 & SPICO_INT_DATA_TXEQ_DATA_MASK), NULL,
+					SPICO_INT_VALIDATE_RESULT);
+	if (err)
+		return err;
+
+	DEV_TRACE2(sbl->dev, "rc: %d", rc);
+
+	return rc;
+}
+
+int sbl_set_gs(struct sbl_inst *sbl, int port_num, int serdes, int gs1, int gs2)
+{
+	int err;
+	u16 result;
+
+	DEV_TRACE2(sbl->dev, "port: %d gs1: %d gs2: %d", port_num, gs1, gs2);
+
+	if ((gs1 < RXEQ_DFE_GS1_MIN) || (gs1 > RXEQ_DFE_GS1_MAX)) {
+		sbl_dev_err(sbl->dev,
+			    "Invalid value for gs1(%d) Expected in the range of %d to %d",
+			gs1, RXEQ_DFE_GS1_MIN, RXEQ_DFE_GS1_MAX);
+		return -EINVAL;
+	}
+	if ((gs2 < RXEQ_DFE_GS2_MIN) || (gs2 > RXEQ_DFE_GS2_MAX)) {
+		sbl_dev_err(sbl->dev,
+			    "Invalid value for gs2(%d) Expected in the range of %d to %d",
+			gs2, RXEQ_DFE_GS2_MIN, RXEQ_DFE_GS2_MAX);
+		return -EINVAL;
+	}
+
+	if (!sbl->is_hw)
+		return 0;
+
+	/* Write GS1 */
+	err = sbl_serdes_spico_int(sbl, port_num, serdes,
+				   SPICO_INT_CM4_HAL_READ,
+					SPICO_INT_DATA_HAL_CTLE_GS1,
+					&result,
+					SPICO_INT_RETURN_RESULT);
+	if (err)
+		return err;
+
+	DEV_TRACE2(sbl->dev,
+		   "p%ds%d: Updating GS1 from 0x%x to 0x%x",
+		   port_num, serdes, result, gs1);
+	err = sbl_serdes_spico_int(sbl, port_num, serdes,
+				   SPICO_INT_CM4_HAL_WRITE,
+					gs1, &result,
+					SPICO_INT_RETURN_RESULT);
+	if (err)
+		return err;
+
+	if (result != SPICO_INT_CM4_HAL_READ) {
+		sbl_dev_err(sbl->dev,
+			    "p%ds%d: Failed updating gs1 (0x%x)!",
+			port_num, serdes, gs1);
+		return -EBADE;
+	}
+
+	/* Write GS2 */
+	err = sbl_serdes_spico_int(sbl, port_num, serdes,
+				   SPICO_INT_CM4_HAL_READ,
+					SPICO_INT_DATA_HAL_CTLE_GS2,
+					&result,
+					SPICO_INT_RETURN_RESULT);
+	if (err)
+		return err;
+
+	DEV_TRACE2(sbl->dev,
+		   "p%ds%d: Updating GS2 from 0x%x to 0x%x",
+		   port_num, serdes, result, gs2);
+	err = sbl_serdes_spico_int(sbl, port_num, serdes,
+				   SPICO_INT_CM4_HAL_WRITE,
+					gs2, &result,
+					SPICO_INT_RETURN_RESULT);
+	if (err)
+		return err;
+
+	if (result != SPICO_INT_CM4_HAL_READ) {
+		sbl_dev_err(sbl->dev,
+			    "p%ds%d: Failed updating gs2 (0x%x)!",
+			port_num, serdes, gs2);
+		return -EBADE;
+	}
+
+	DEV_TRACE2(sbl->dev, "rc: 0");
+
+	return 0;
+}
+
+int sbl_set_tx_data_sel(struct sbl_inst *sbl, int port_num, int serdes,
+			int data_sel)
+{
+	int err;
+	u16 result;
+	int retry_cnt = 0;
+
+	DEV_TRACE2(sbl->dev, "p%ds%d data_sel: %d", port_num, serdes, data_sel);
+
+	if (!sbl->is_hw)
+		return 0;
+
+	if (data_sel == SBL_DS_CORE) {
+		do {
+			err = sbl_serdes_spico_int(sbl, port_num, serdes,
+						   SPICO_INT_CM4_PRBS_CTRL,
+						SPICO_INT_DATA_DISABLE_TXRXGEN,
+						&result,
+						SPICO_INT_RETURN_RESULT);
+			if (err)
+				return err;
+
+			if (result == SPICO_INT_DATA_PRBS_SUCCESS)
+				return 0;
+
+			sbl_dev_dbg(sbl->dev, "p%ds%d: attempt %d tx data sel returned %d",
+				    port_num, serdes, retry_cnt, result);
+			usleep_range(1000, 2000);
+		} while (retry_cnt++ < SPICO_INT_DATA_PRBS_RETRY_LIMIT);
+	} else { /* SBL_DS_PRBS */
+		do {
+			err = sbl_serdes_spico_int(sbl, port_num, serdes,
+						   SPICO_INT_CM4_PRBS_CTRL,
+						SPICO_INT_DATA_PRBS31_AS_TXGEN,
+						&result,
+						SPICO_INT_RETURN_RESULT);
+			if (err)
+				return err;
+
+			if (result == SPICO_INT_DATA_PRBS_SUCCESS)
+				return 0;
+
+			sbl_dev_dbg(sbl->dev, "p%ds%d: attempt %d tx data sel returned %d",
+				    port_num, serdes, retry_cnt, result);
+			usleep_range(1000, 2000);
+		} while (retry_cnt++ < SPICO_INT_DATA_PRBS_RETRY_LIMIT);
+	}
+
+	sbl_dev_err(sbl->dev, "p%ds%d: Failed to set TX data select (%d)!",
+		    port_num, serdes, data_sel);
+	return -EBADE;
+}
+
+int sbl_set_prbs_rx_mode(struct sbl_inst *sbl, int port_num, int serdes)
+{
+	int err;
+	/* Avago_serdes_data_qual_t qual; */
+
+	DEV_TRACE2(sbl->dev, "p%ds%d", port_num, serdes);
+	err = sbl_serdes_spico_int(sbl, port_num, serdes,
+				   SPICO_INT_CM4_DFE_CTRL,
+					SPICO_INT_DATA_NONE, NULL,
+					SPICO_INT_VALIDATE_RESULT);
+	if (err)
+		return err;
+
+	err = sbl_serdes_dfe_tune_wait(sbl, port_num);
+	if (err)
+		return err;
+
+	DEV_TRACE2(sbl->dev, "rc: 0");
+
+	return 0;
+}
+
+int sbl_apply_sbus_divider(struct sbl_inst *sbl, int divider)
+{
+	int sbus_ring, err;
+	u32 sbus_addr;
+
+	/* Force divider to either SPEEDUP or DFLT */
+	if (divider == SBL_SBUS_DIVIDER_SPEEDUP) {
+		sbl_dev_dbg(sbl->dev, "Applying SBUS speedup.");
+	} else {
+		sbl_dev_dbg(sbl->dev, "Disabling SBUS speedup.");
+		divider = SBL_SBUS_DIVIDER_DFLT;
+	}
+
+	/* increase SBUS ring clock frequency */
+	for (sbus_ring = 0; sbus_ring < sbl->switch_info->num_sbus_rings; ++sbus_ring) {
+		sbus_addr = SBUS_ADDR(sbus_ring, SBUS_BCAST_SBM);
+		DEV_TRACE2(sbl->dev, "ring: %d divider_exp: %d", sbus_ring,
+			   divider);
+		/* SBUS Critical Section */
+		mutex_lock(SBUS_RING_MTX(sbl, sbus_ring));
+		err = sbl_sbus_wr(sbl, sbus_addr, SBM_CRM_ADDR_CLK_DIV, divider);
+		mutex_unlock(SBUS_RING_MTX(sbl, sbus_ring));
+		if (err)
+			return err;
+	}
+
+	/* adjust op flags */
+	if (divider == SBL_SBUS_DIVIDER_SPEEDUP)
+		sbl->sbus_op_flags = sbl->iattr.sbus_op_flags_fast;
+	else /* SBL_SBUS_DIVIDER_DFLT */
+		sbl->sbus_op_flags = sbl->iattr.sbus_op_flags_slow;
+
+	sbl_dev_dbg(sbl->dev, "SBus divider update complete");
+	return 0;
+}
+
+/* Note - cannot do broadcast here! */
+int sbl_serdes_dfe_tune_start(struct sbl_inst *sbl, int port_num, int serdes,
+			      bool is_retune)
+{
+	int err;
+	u16 result;
+	struct sbl_link *link = sbl->link + port_num;
+
+	err = sbl_serdes_spico_int(sbl, port_num, serdes,
+				   SPICO_INT_CM4_GET_RX_EQ,
+					SPICO_INT_DATA_RXEQ_STS_DFE_STS,
+					&result, SPICO_INT_RETURN_RESULT);
+	if (err) {
+		sbl_dev_err(sbl->dev, "p%ds%d: Failed checking status of DFE tune!",
+			    port_num, serdes);
+		return -EIO;
+	}
+	if (result == DFE_CAL_DONE) {
+		sbl_dev_dbg(sbl->dev, "p%ds%d: DFE done before we started",
+			    port_num, serdes);
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_SET_RX_EQ,
+					SPICO_INT_DATA_RXEQ_STS_DFE_STS | 0x0,
+					NULL, SPICO_INT_IGNORE_RESULT);
+		if (err) {
+			sbl_dev_err(sbl->dev, "p%ds%d: Failed to clear DFE sts!",
+				    port_num, serdes);
+			return err;
+		}
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_GET_RX_EQ,
+					SPICO_INT_DATA_RXEQ_STS_DFE_STS,
+					&result, SPICO_INT_RETURN_RESULT);
+		if (err) {
+			sbl_dev_err(sbl->dev,
+				    "p%ds%d: Failed checking status of DFE tune!",
+				port_num, serdes);
+			return -EIO;
+		}
+		if (result == DFE_CAL_DONE) {
+			sbl_dev_err(sbl->dev, "p%ds%d: DFE done before we started!",
+				    port_num, serdes);
+			return -ENOMSG;
+		}
+	}
+
+	DEV_TRACE2(sbl->dev, "p%ds%d is_retune:%d", port_num, serdes,
+		   is_retune);
+
+	/* Set effort level */
+	err = sbl_serdes_spico_int(sbl, port_num, serdes,
+				   SPICO_INT_CM4_HAL_READ,
+					SPICO_INT_DATA_ICAL_EFFORT_SEL, &result,
+					SPICO_INT_RETURN_RESULT);
+	if (err)
+		return err;
+
+	if (sbl_debug_option(sbl, port_num, SBL_DEBUG_FORCE_MAX_EFFORT)) {
+		link->ical_effort = SPICO_INT_DATA_ICAL_MAX_EFFORT;
+	} else if (sbl_debug_option(sbl, port_num, SBL_DEBUG_FORCE_MED_EFFORT)) {
+		link->ical_effort = SPICO_INT_DATA_ICAL_MED_EFFORT;
+	} else if (sbl_debug_option(sbl, port_num, SBL_DEBUG_FORCE_MIN_EFFORT)) {
+		link->ical_effort = SPICO_INT_DATA_ICAL_MIN_EFFORT;
+	} else if (link->blattr.options & SBL_OPT_DFE_ALWAYS_MAX_EFFORT) {
+		link->ical_effort = SPICO_INT_DATA_ICAL_MAX_EFFORT;
+	} else if (link->blattr.options & SBL_OPT_DFE_ALWAYS_MED_EFFORT) {
+		link->ical_effort = SPICO_INT_DATA_ICAL_MED_EFFORT;
+	} else if (link->blattr.options & SBL_OPT_DFE_ALWAYS_MIN_EFFORT) {
+		link->ical_effort = SPICO_INT_DATA_ICAL_MIN_EFFORT;
+	} else if (link->dfe_tune_count < 3) {
+		/* medium effort for first few attempts */
+		link->ical_effort = SPICO_INT_DATA_ICAL_MED_EFFORT;
+	} else {
+		/* rest full effort */
+		link->ical_effort = SPICO_INT_DATA_ICAL_MAX_EFFORT;
+	}
+	/* sync with sysfs */
+	mb();
+
+	if (!sbl->is_hw)
+		return 0;
+
+	DEV_TRACE2(sbl->dev, "p%ds%d: Updating ICAL effort from 0x%x to 0x%x",
+		   port_num, serdes, result, link->ical_effort);
+	err = sbl_serdes_spico_int(sbl, port_num, serdes,
+				   SPICO_INT_CM4_HAL_WRITE,
+					link->ical_effort, &result,
+					SPICO_INT_RETURN_RESULT);
+	if (err)
+		return err;
+
+	if (result != SPICO_INT_CM4_HAL_READ) {
+		sbl_dev_err(sbl->dev, "p%ds%d: Failed updating ICAL effort (0x%x)!",
+			    port_num, serdes, link->ical_effort);
+		return -EBADE;
+	}
+	sbl_dev_dbg(sbl->dev, "p%ds%d: Setup ICAL effort 0x%x",
+		    port_num, serdes, link->ical_effort);
+
+	/* Initiate DFE tune */
+	err = sbl_serdes_spico_int(sbl, port_num, serdes,
+				   SPICO_INT_CM4_DFE_CTRL,
+					SPICO_INT_DATA_DFE_ICAL, NULL,
+					SPICO_INT_VALIDATE_RESULT);
+	if (err)
+		return err;
+
+	DEV_TRACE2(sbl->dev, "rc: 0");
+	return 0;
+}
+
+int sbl_serdes_dfe_tune_wait(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	u16 result;
+	int err, serdes;
+	u8 in_progress_mask, serdes_mask, tuned_mask = 0;
+	unsigned long last_jiffy;
+
+	serdes_mask = get_serdes_rx_mask(sbl, port_num);
+	in_progress_mask = serdes_mask;
+
+	DEV_TRACE2(sbl->dev, "p%d serdes_mask:0x%x", port_num, serdes_mask);
+
+	last_jiffy = jiffies + msecs_to_jiffies(1000 * link->blattr.dfe_timeout);
+	do {
+		for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+			if (!rx_serdes_required_for_link_mode(sbl, port_num, serdes))
+				continue;
+
+			if (!((1 << serdes) & in_progress_mask))
+				continue;
+
+			err = sbl_serdes_spico_int(sbl, port_num, serdes,
+						   SPICO_INT_CM4_GET_RX_EQ,
+							SPICO_INT_DATA_RXEQ_STS_DFE_STS,
+							&result, SPICO_INT_RETURN_RESULT);
+			if (err) {
+				sbl_dev_err(sbl->dev, "p%ds%d: Failed checking status of DFE tune!",
+					    port_num, serdes);
+				return -EIO;
+			}
+			if (!sbl->is_hw)
+				result = DFE_CAL_DONE;
+
+			if (result & DFE_LOS_MASK) {
+				sbl_dev_warn(sbl->dev, "p%ds%d: Loss of signal when in DFE tune!",
+					     port_num, serdes);
+				return -ENOMSG;
+			} else if (result & DFE_CAL_RUN_IN_PRGRS_MASK) {
+				sbl_dev_dbg(sbl->dev, "p%ds%d: DFE still in progress", port_num,
+					    serdes);
+			} else if (result & DFE_CAL_DONE) {
+				sbl_dev_dbg(sbl->dev, "p%ds%d: DFE done", port_num,
+					    serdes);
+				tuned_mask      |= (1 << serdes);
+				in_progress_mask &= ~(1 << serdes);
+			} else {
+				sbl_dev_dbg(sbl->dev, "p%ds%d: DFE complete", port_num, serdes);
+				tuned_mask      |= (1 << serdes);
+				in_progress_mask &= ~(1 << serdes);
+			}
+		}
+		if (!in_progress_mask)
+			break;
+
+		msleep(link->blattr.dfe_poll_interval);
+	} while (time_is_after_jiffies(last_jiffy) &&
+		 !sbl_start_timeout(sbl, port_num) &&
+		 !sbl_base_link_start_cancelled(sbl, port_num));
+
+	if (serdes_mask == tuned_mask)
+		return 0;
+
+	if (sbl_base_link_start_cancelled(sbl, port_num))
+		return -ECANCELED;
+
+	if (sbl_start_timeout(sbl, port_num)) {
+		sbl_dev_dbg(sbl->dev, "p%d: start timeout waiting for DFE to tune to complete\n",
+			    port_num);
+		return -ETIMEDOUT;
+	}
+
+	/* just didnt finish */
+	sbl_dev_dbg(sbl->dev, "p%d serdes_mask:0x%x: Timeout waiting for DFE to complete (timeout:%ds)",
+		    port_num, serdes_mask, link->blattr.dfe_timeout);
+	return -ETIME;
+}
+
+int sbl_port_dfe_tune_start(struct sbl_inst *sbl, int port_num, bool is_retune)
+{
+	int err, serdes;
+
+	sbl_dev_dbg(sbl->dev, "p%d: DFE tune retune:%d", port_num, is_retune);
+
+	/* DFE Tune */
+	for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+		if (!(rx_serdes_required_for_link_mode(sbl, port_num, serdes) ||
+		      tx_serdes_required_for_link_mode(sbl, port_num, serdes)))
+			continue;
+		err = sbl_serdes_dfe_tune_start(sbl, port_num, serdes,
+						is_retune);
+		if (err) {
+			sbl_dev_err(sbl->dev, "p%d: Failed to start DFE tune!",
+				    port_num);
+			return err;
+		}
+	}
+
+	return 0;
+}
+
+int sbl_port_dfe_tune_wait(struct sbl_inst *sbl, int port_num)
+{
+	int err;
+
+	/* DFE Tune */
+	err = sbl_serdes_dfe_tune_wait(sbl, port_num);
+	if (err) {
+		switch (err) {
+		case -ECANCELED:
+			sbl_dev_dbg(sbl->dev, "p%d: DFE wait cancelled", port_num);
+			break;
+		case -ETIMEDOUT:
+			sbl_dev_dbg(sbl->dev, "p%d: DFE wait start timeout", port_num);
+			break;
+		case -ETIME:
+			sbl_dev_dbg(sbl->dev, "p%d: DFE wait timed out", port_num);
+			break;
+		default:
+			sbl_dev_err(sbl->dev, "p%d: DFE wait failed [%d]", port_num, err);
+		}
+		return err;
+	}
+
+	/* extra checks */
+	if (sbl->link[port_num].loopback_mode != SBL_LOOPBACK_MODE_LOCAL) {
+
+		/* Eye height check (without pcal active) */
+		err = sbl_port_check_eyes(sbl, port_num);
+		if (err) {
+			sbl_dev_dbg(sbl->dev, "p%d: some eyes bad", port_num);
+			return err;
+		}
+		sbl_dev_dbg(sbl->dev, "p%d: all eyes good", port_num);
+
+		/* Validate tuning params */
+		err = sbl_check_serdes_tuning_params(sbl, port_num);
+		if (err) {
+			sbl_dev_err(sbl->dev, "p%d: some tuning params bad", port_num);
+			sbl->link[port_num].tune_param_oob_count++;
+			return -ELNRNG;
+		}
+		sbl_dev_dbg(sbl->dev, "p%d: all tuning params good", port_num);
+		sbl->link[port_num].tune_param_oob_count = 0;
+
+		/* Set up PCAL */
+		/*   (This can reduce the eye heights but increase the eye widths).
+		     Future eye height checks will be held off for a period while
+		     the pcal process settles */
+		if (sbl->link[port_num].blattr.options & SBL_OPT_ENABLE_PCAL) {
+			if (sbl_debug_option(sbl, port_num, SBL_DEBUG_INHIBIT_PCAL)) {
+				sbl_dev_warn(sbl->dev, "p%d: pcal inhibited\n", port_num);
+			} else {
+				err = sbl_port_start_pcal(sbl, port_num);
+				if (err)
+					return err;
+			}
+		} else {
+			sbl_dev_dbg(sbl->dev, "p%d: PCAL is disabled!", port_num);
+		}
+	}
+
+	return 0;
+}
+
+void sbl_log_port_eye_heights(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	int eye, num_eyes = 0;
+	int eye_heights[NUM_PAM4_EYES];
+	int serdes;
+
+	switch (link->link_mode) {
+	default:
+	case SBL_LINK_MODE_BJ_100G: /* NRZ */
+		num_eyes = NUM_NRZ_EYES;
+		break;
+	case SBL_LINK_MODE_CD_50G:
+	case SBL_LINK_MODE_CD_100G:
+	case SBL_LINK_MODE_BS_200G: /* PAM4 */
+		num_eyes = NUM_PAM4_EYES;
+		break;
+	}
+
+	for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+		if (!rx_serdes_required_for_link_mode(sbl, port_num, serdes))
+			continue;
+		if (sbl_get_eye_heights(sbl, port_num, serdes, eye_heights)) {
+			sbl_dev_err(sbl->dev, "p%ds%d: Failed to read eye heights",
+				    port_num, serdes);
+			return;
+		}
+		for (eye = 0; eye < num_eyes; ++eye) {
+			sbl_dev_info(sbl->dev, "p%ds%d eye[%d] height: 0x%x",
+				     port_num, serdes, eye, eye_heights[eye]);
+		}
+	}
+}
+
+int sbl_port_check_eyes(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	int min_eye_height, max_eye_height;
+	int eye, num_eyes = 0;
+	int eye_heights[NUM_PAM4_EYES];
+	unsigned long holdoff_end_jiffies;
+	int serdes;
+
+	/* pcal can generate bad eyes temporarily when its starting up so
+	   if its not settled yet ignore this test */
+	if (link->pcal_running && link->blattr.pcal_eyecheck_holdoff) {
+		holdoff_end_jiffies = link->pcal_start_jiffies +
+				msecs_to_jiffies(link->blattr.pcal_eyecheck_holdoff);
+		if (time_is_after_jiffies(holdoff_end_jiffies)) {
+			sbl_dev_info(sbl->dev, "p%d: holding off eye checks",
+				     port_num);
+			return 0;
+		}
+	}
+
+	if (!sbl->is_hw)
+		return 0;
+
+	/* setup test criteria */
+	switch (link->link_mode) {
+	default:
+	case SBL_LINK_MODE_BJ_100G: /* NRZ */
+		num_eyes = NUM_NRZ_EYES;
+		min_eye_height =
+			link->blattr.nrz_min_eye_height;
+		max_eye_height =
+			link->blattr.nrz_max_eye_height;
+		break;
+	case SBL_LINK_MODE_CD_50G:
+	case SBL_LINK_MODE_CD_100G:
+	case SBL_LINK_MODE_BS_200G: /* PAM4 */
+		num_eyes = NUM_PAM4_EYES;
+		min_eye_height =
+			link->blattr.pam4_min_eye_height;
+		max_eye_height =
+			link->blattr.pam4_max_eye_height;
+		break;
+	}
+
+	/* check eye height */
+	for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+		if (!rx_serdes_required_for_link_mode(sbl, port_num, serdes))
+			continue;
+
+		sbl_dev_dbg(sbl->dev, "p%ds%d: checking eye height(s)", port_num, serdes);
+		if (sbl_get_eye_heights(sbl, port_num, serdes, eye_heights)) {
+			sbl_dev_err(sbl->dev, "p%ds%d: Failed to read eye heights",
+				    port_num, serdes);
+			return -EIO;
+		}
+
+		for (eye = 0; eye < num_eyes; ++eye) {
+			sbl_dev_dbg(sbl->dev, "p%ds%d eye[%d] height: 0x%x",
+				    port_num, serdes, eye, eye_heights[eye]);
+			if (eye_heights[eye] < min_eye_height) {
+				sbl_dev_dbg(sbl->dev,
+					    "p%ds%d eye[%d] height (0x%x) less than requirement (0x%x)!",
+					    port_num, serdes, eye, eye_heights[eye],
+					    min_eye_height);
+				return -ECHRNG;
+			} else if ((sbl->link[port_num].loopback_mode !=
+				    SBL_LOOPBACK_MODE_LOCAL) &&
+				   (eye_heights[eye] > max_eye_height)) {
+				sbl_dev_dbg(sbl->dev,
+					    "p%ds%d eye[%d] height (0x%x) greater than max (0x%x)!",
+					    port_num, serdes, eye, eye_heights[eye],
+					    max_eye_height);
+				return -ECHRNG;
+			}
+		}
+	}
+
+	return 0;
+}
+
+/* Constructs maps of */
+/* - active serdes (ones in use for this mode)
+   - serdes not reporting electrical idle (i.e. seeing a signal)
+   - serdes with all good eyes (i.e. data can be extracted from the signal) */
+
+/* Only called on Rosetta */
+/* active map is always valid and returned
+   other maps only valid if function succeeds otherwise zero */
+
+/* Electrical idle detect seems fast to respond but sometimes shows unexpected
+   and probably wrong, electrical idle. */
+
+/* TODO investigate EID filtering - if its fast enough? */
+
+/* Eye height measurements seem to be very slow at being updated after a change to the
+   serdes. BRCM say this is because the PLL takes a long time to unlock
+   There is an optional delay that can be added to give the eye heights time
+   to be updated. */
+
+int sbl_port_get_serdes_state_maps(struct sbl_inst *sbl, int port_num, u8 *active_map,
+				   u8 *not_idle_map, u8 *ok_eye_map)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	int min_eye_height, max_eye_height;
+	int eye, num_eyes = 0;
+	u64 core_status;
+	int eye_heights[NUM_PAM4_EYES];
+	int err;
+	int serdes;
+
+	if (!active_map || !not_idle_map || !ok_eye_map)
+		return -EINVAL;
+
+	*active_map = *not_idle_map = *ok_eye_map = 0;
+
+	/* always build active serdes map */
+	for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes)
+		if (rx_serdes_required_for_link_mode(sbl, port_num, serdes))
+			*active_map  |= (1 << serdes);
+
+	/* must be configured to get criteria from attributes */
+	if (!link->blconfigured)
+		return -EUCLEAN;
+
+	/* get eye test criteria */
+	switch (link->link_mode) {
+	case SBL_LINK_MODE_BJ_100G: /* NRZ */
+		num_eyes = NUM_NRZ_EYES;
+		min_eye_height = link->blattr.nrz_min_eye_height;
+		max_eye_height = link->blattr.nrz_max_eye_height;
+		break;
+	case SBL_LINK_MODE_CD_50G:
+	case SBL_LINK_MODE_CD_100G:
+	case SBL_LINK_MODE_BS_200G: /* PAM4 */
+		num_eyes = NUM_PAM4_EYES;
+		min_eye_height = link->blattr.pam4_min_eye_height;
+		max_eye_height = link->blattr.pam4_max_eye_height;
+		break;
+	default:
+		sbl_dev_dbg(sbl->dev, "%d: get_serdes_state_maps, unrecognised link mode (%d)",
+			    port_num, link->link_mode);
+		return -ENODATA;
+	}
+
+	/* check electrical idle not asserted */
+	for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+
+		if (!rx_serdes_required_for_link_mode(sbl, port_num, serdes))
+			continue;
+
+		core_status = sbl_read64(sbl, SBL_PML_BASE(port_num) |
+		       SBL_PML_SERDES_CORE_STATUS_OFFSET(serdes));
+
+		/* TODO fix to use normal address map macro */
+		if (!(core_status & SERDES_CORE_STATUS_RX_IDLE_DETECT_MASK))
+			*not_idle_map |= 1 << serdes;
+	}
+
+	/* optionally wait a little to allow current eye heights to be available */
+	if (sbl_debug_option(sbl, port_num, SBL_DEBUG_SERDES_MAP_DELAY))
+		msleep(150);
+
+	/* check eyes */
+	for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+
+		/* assume good if serdes is used */
+		if (rx_serdes_required_for_link_mode(sbl, port_num, serdes))
+			*ok_eye_map |= (1 << serdes);
+		else
+			continue;
+
+		/* get eyes */
+		err = sbl_get_eye_heights(sbl, port_num, serdes, eye_heights);
+		if (err) {
+			sbl_dev_dbg(sbl->dev, "%d: get_serdes_state_maps, get_eye_heights failed [%d]",
+				    port_num, err);
+			*not_idle_map = *ok_eye_map = 0;
+			return err;
+		}
+
+		/* All eyes must be good
+		   drop from map if any bad eyes found */
+		for (eye = 0; eye < num_eyes; ++eye) {
+
+			if (eye_heights[eye] < min_eye_height) {
+				*ok_eye_map &= ~(1 << serdes);
+				break;
+			} else if ((link->loopback_mode != SBL_LOOPBACK_MODE_LOCAL) &&
+				   (eye_heights[eye] > max_eye_height)) {
+				*ok_eye_map &= ~(1 << serdes);
+				break;
+			}
+		}
+	}
+
+	return 0;
+}
+
+int sbl_port_start_pcal(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	int serdes, err;
+
+	if (link->pcal_running)
+		return 0;
+
+	sbl_dev_dbg(sbl->dev, "p%d: starting PCAL", port_num);
+	for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+		if (!rx_serdes_required_for_link_mode(sbl, port_num, serdes))
+			continue;
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_DFE_CTRL,
+						SPICO_INT_DATA_DFE_CONT_PCAL,
+						NULL,
+						SPICO_INT_VALIDATE_RESULT);
+		if (err)
+			return err;
+	}
+	link->pcal_running = true;
+	link->pcal_start_jiffies = jiffies;
+
+	return 0;
+}
+
+int sbl_port_stop_pcal(struct sbl_inst *sbl, int port_num)
+{
+	int serdes, err;
+
+	if (!sbl->link[port_num].pcal_running)
+		return 0;
+
+	sbl_dev_dbg(sbl->dev, "p%d: stopping PCAL", port_num);
+	for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+		if (!rx_serdes_required_for_link_mode(sbl, port_num, serdes))
+			continue;
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_DFE_CTRL,
+						SPICO_INT_DATA_DFE_PAUSE_PCAL,
+						NULL,
+						SPICO_INT_VALIDATE_RESULT);
+		if (err)
+			return err;
+	}
+
+	sbl->link[port_num].pcal_running = false;
+	return 0;
+}
+
+int sbl_port_dfe_tune(struct sbl_inst *sbl, int port_num, bool is_retune)
+{
+	int err;
+
+	sbl_dev_dbg(sbl->dev, "p%d: Starting DFE %stune...", port_num,
+		    is_retune ? "re" : "");
+
+	sbl_link_tune_begin(sbl, port_num);
+
+	err = sbl_port_dfe_tune_start(sbl, port_num, is_retune);
+	if (err) {
+		sbl_dev_dbg(sbl->dev, "p%d: Failed to start DFE tune!", port_num);
+		goto out;
+	}
+
+	sbl_dev_dbg(sbl->dev, "p%d: Waiting for DFE tuning to complete...", port_num);
+	err = sbl_port_dfe_tune_wait(sbl, port_num);
+	if (err) {
+		sbl_dev_dbg(sbl->dev, "p%d: DFE tune failed!", port_num);
+		goto out;
+	}
+
+out:
+	sbl_link_tune_update_total_timespec(sbl, port_num);
+	return err;
+}
+
+int sbl_serdes_minitune_setup(struct sbl_inst *sbl, int port_num)
+{
+	int err;
+	u16 result;
+	int serdes;
+
+	err = sbl_serdes_config(sbl, port_num, false);
+	if (err) {
+		sbl_dev_err(sbl->dev,
+			    "mt: SerDes config failed for port %d with err %d",
+			port_num, err);
+		return err;
+	}
+
+	for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+		if (!rx_serdes_required_for_link_mode(sbl, port_num, serdes))
+			continue;
+		/* Set effort level */
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_HAL_READ,
+						SPICO_INT_DATA_ICAL_EFFORT_SEL,
+						&result,
+						SPICO_INT_RETURN_RESULT);
+		if (err)
+			return err;
+
+		DEV_TRACE2(sbl->dev,
+			   "p%ds%d: mt: Updating ICAL effort from 0x%x to 0x%x",
+			   port_num, serdes, result,
+			   SPICO_INT_DATA_ICAL_EFFORT_0);
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_HAL_WRITE,
+						SPICO_INT_DATA_ICAL_EFFORT_0,
+						&result,
+						SPICO_INT_RETURN_RESULT);
+		if (err)
+			return err;
+
+		if (result != SPICO_INT_CM4_HAL_READ) {
+			sbl_dev_err(sbl->dev,
+				    "p%ds%d: mt: Failed updating ICAL effort (0x%x)!",
+				port_num, serdes, SPICO_INT_DATA_ICAL_EFFORT_0);
+			return -EBADE;
+		}
+		/* Enable EID based on DFE tuning */
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_HAL_READ,
+						SPICO_INT_DATA_EID_FILTER_SEL,
+						&result,
+						SPICO_INT_RETURN_RESULT);
+		if (err)
+			return err;
+
+		DEV_TRACE2(sbl->dev,
+			   "p%ds%d: mt: Updating EID Filter from 0x%x to 0x%x",
+			   port_num, serdes, result,
+			   SPICO_INT_DATA_EID_FILTER_DFE);
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_HAL_WRITE,
+						SPICO_INT_DATA_EID_FILTER_DFE,
+						&result,
+						SPICO_INT_RETURN_RESULT);
+		if (err)
+			return err;
+
+		if (result != SPICO_INT_CM4_HAL_READ) {
+			sbl_dev_err(sbl->dev,
+				    "p%ds%d: mt: Failed updating EID Filter (0x%x)!",
+				port_num, serdes,
+				SPICO_INT_DATA_EID_FILTER_DFE);
+			return -EBADE;
+		}
+	}
+
+	return 0;
+}
+
+int sbl_serdes_minitune_block(struct sbl_inst *sbl, int port_num)
+{
+	u64 core_status_value;
+	u8 sig_ok_mask = 0;
+	u8 tgt_serdes = 0;
+	u16 result;
+	int serdes;
+	int err;
+	u8 serdes_mask;
+	unsigned long last_jiffy;
+
+	serdes_mask = get_serdes_rx_mask(sbl, port_num);
+
+	/* Wait for signal OK */
+	last_jiffy = jiffies + msecs_to_jiffies(1000 * sbl->link[port_num].blattr.lpd_timeout);
+	do {
+		for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+			if (!rx_serdes_required_for_link_mode(sbl, port_num, serdes))
+				continue;
+			tgt_serdes = 1 << serdes;
+
+			if (tgt_serdes & sig_ok_mask)
+				continue;
+
+			core_status_value = sbl_read64(sbl,
+						       SBL_PML_BASE(port_num) |
+			       SBL_PML_SERDES_CORE_STATUS_OFFSET(serdes));
+			if (((core_status_value &
+			      SERDES_CORE_STATUS_RX_IDLE_DETECT_MASK) == 0) &&
+			    ((core_status_value &
+			      SERDES_CORE_STATUS_RX_SIG_OK_MASK) == 0)) {
+				sbl_dev_dbg(sbl->dev, "p%ds%d: mt: Found EID 0 or SIG OK 0", port_num, serdes);
+				sig_ok_mask |= 1 << serdes;
+				continue;
+			} else {
+				DEV_TRACE2(sbl->dev, "p%ds%d: mt: Waiting for EID==0(%d) or SIG OK==0(%d)",
+					   port_num, serdes,
+						(core_status_value & SERDES_CORE_STATUS_RX_IDLE_DETECT_MASK) ? 1 : 0,
+						(core_status_value & SERDES_CORE_STATUS_RX_SIG_OK_MASK) ? 1 : 0);
+			}
+		}
+
+		if (sig_ok_mask == serdes_mask)
+			break;
+		if (sbl_base_link_start_cancelled(sbl, port_num))
+			break;
+		if (sbl_start_timeout(sbl, port_num))
+			break;
+
+		msleep(sbl->link[port_num].blattr.lpd_poll_interval);
+	} while (time_is_after_jiffies(last_jiffy));
+
+	/* Disable EID filter */
+	for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+		if (!rx_serdes_required_for_link_mode(sbl, port_num, serdes))
+			continue;
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_HAL_READ,
+						SPICO_INT_DATA_EID_FILTER_SEL,
+						&result,
+						SPICO_INT_RETURN_RESULT);
+		if (err) {
+			sbl_dev_err(sbl->dev,
+				    "p%ds%d: mt block exit@1: sbl_serdes_spico_int failed [%d]",
+				port_num, serdes, err);
+			return err;
+		}
+		DEV_TRACE2(sbl->dev,
+			   "p%ds%d: Updating EID Filter from 0x%x to 0x%x",
+			   port_num, serdes, result,
+			   SPICO_INT_DATA_EID_FILTER_OFF);
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_HAL_WRITE,
+						SPICO_INT_DATA_EID_FILTER_OFF,
+						&result,
+						SPICO_INT_RETURN_RESULT);
+		if (err) {
+			sbl_dev_err(sbl->dev,
+				    "p%ds%d: mt block exit@2: sbl_serdes_spico_int failed [%d]",
+				port_num, serdes, err);
+			return err;
+		}
+		if (result != SPICO_INT_CM4_HAL_READ) {
+			sbl_dev_err(sbl->dev,
+				    "p%ds%d: mt: Failed updating EID Filter (0x%x)!",
+				port_num, serdes,
+				SPICO_INT_DATA_EID_FILTER_OFF);
+			return -EBADE;
+		}
+	}
+	/* Make sure all tunes are complete */
+	err = sbl_serdes_dfe_tune_wait(sbl, port_num);
+	if (err) {
+		sbl_dev_dbg(sbl->dev, "%d: mt: Failed to detect with link partner!",
+			    port_num);
+	}
+
+	if (sbl_base_link_start_cancelled(sbl, port_num))
+		return -ECANCELED;
+	if (sbl_start_timeout(sbl, port_num))
+		return -ETIMEDOUT;
+
+	if (sig_ok_mask != serdes_mask) {
+		sbl_dev_dbg(sbl->dev,
+			    "p%ds<mask>0x%x: mt: SerDes signal ok not detected (timeout:%ds)",
+			    port_num, (serdes_mask & ~sig_ok_mask),
+			    sbl->link[port_num].blattr.lpd_timeout);
+		return -ETIME;
+	}
+
+	return err;
+}
+
+int sbl_serdes_config(struct sbl_inst *sbl, int port_num, bool allow_an)
+{
+	int err, encoding, divisor, width, serdes, j;
+	struct sbl_sc_values values = {0};
+	u16 result;
+	u32 rx_phase_slip_cnt;
+	u32 rx_phase_slip_reapply;
+	bool use_default_tx_eq, use_default_gs;
+	bool tx_en, rx_en, txo_en;
+
+	if (allow_an && (sbl->link[port_num].blattr.config_target != SBL_BASE_LINK_CONFIG_PEC)) {
+		sbl_dev_err(sbl->dev, "%d: AN allowed but has no config", port_num);
+		return -ENAVAIL;
+	}
+
+	/* Stop continuous tune */
+	err = sbl_port_stop_pcal(sbl, port_num);
+	if (err) {
+		sbl_dev_warn(sbl->dev, "%d: serdes config: stop pcal failed [%d]",
+			     port_num, err);
+		return err;
+	}
+
+	/* Handle requested speed */
+	if (allow_an) {
+		switch (sbl->link[port_num].blattr.pec.an_mode) {
+		case SBL_AN_MODE_FIXED:
+		case SBL_AN_MODE_ON:
+			encoding = SBL_ENC_NRZ;
+			divisor  = SBL_DIV_AN;
+			width    = SBL_WID_AN;
+			break;
+		case SBL_AN_MODE_OFF:
+		default:
+			sbl_dev_warn(sbl->dev, "%d: Unsupported an mode (%d)",
+				     port_num, sbl->link[port_num].blattr.pec.an_mode);
+			return -EINVAL;
+
+		}
+	} else {
+		switch (sbl->link[port_num].link_mode) {
+		case SBL_LINK_MODE_BJ_100G:
+			encoding = SBL_ENC_NRZ;
+			divisor  = SBL_DIV_25G;
+			width    = SBL_WID_25G;
+			break;
+		case SBL_LINK_MODE_CD_50G:
+		case SBL_LINK_MODE_CD_100G:
+		case SBL_LINK_MODE_BS_200G:
+			encoding = SBL_ENC_PAM4;
+			divisor  = SBL_DIV_50G;
+			width    = SBL_WID_50G;
+			break;
+		default:
+			sbl_dev_warn(sbl->dev, "%d: Unsupported link mode (%d)",
+				     port_num, sbl->link[port_num].link_mode);
+			return -EINVAL;
+		}
+	}
+
+	for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+		if (!(rx_serdes_required_for_link_mode(sbl, port_num, serdes) ||
+		      tx_serdes_required_for_link_mode(sbl, port_num, serdes)))
+			continue;
+		err = sbl_serdes_init(sbl, port_num, serdes, encoding,
+				      divisor, width);
+		if (err)
+			return err;
+	}
+
+	for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+		if (!(rx_serdes_required_for_link_mode(sbl, port_num, serdes) ||
+		      tx_serdes_required_for_link_mode(sbl, port_num, serdes)))
+			continue;
+		err = sbl_serdes_polarity_ctrl(sbl, port_num, serdes,
+					       encoding, allow_an);
+		if (err)
+			return err;
+	}
+
+	/* Set Rx Termination */
+	switch (sbl->link[port_num].blattr.link_partner) {
+	case SBL_LINK_PARTNER_SWITCH:
+		for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+			if (!(rx_serdes_required_for_link_mode(sbl, port_num, serdes) ||
+			      tx_serdes_required_for_link_mode(sbl, port_num, serdes)))
+				continue;
+			err = sbl_serdes_spico_int(sbl, port_num, serdes,
+						   SPICO_INT_CM4_INT_RX_TERM,
+						SPICO_INT_DATA_RXT_FLOAT, NULL,
+						SPICO_INT_VALIDATE_RESULT);
+			if (err)
+				return err;
+		}
+		break;
+	case SBL_LINK_PARTNER_NIC:
+	case SBL_LINK_PARTNER_NIC_C2:
+		for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+			if (!(rx_serdes_required_for_link_mode(sbl, port_num, serdes) ||
+			      tx_serdes_required_for_link_mode(sbl, port_num, serdes)))
+				continue;
+			err = sbl_serdes_spico_int(sbl, port_num, serdes,
+						   SPICO_INT_CM4_INT_RX_TERM,
+						SPICO_INT_DATA_RXT_AVDD, NULL,
+						SPICO_INT_VALIDATE_RESULT);
+			if (err)
+				return err;
+		}
+		break;
+	default:
+		sbl_dev_warn(sbl->dev, "p%d: Unsupported link partner mode (enum %d)!",
+			     port_num, sbl->link[port_num].blattr.link_partner);
+		return -EINVAL;
+	}
+
+	/* Handle requested loopback mode */
+	switch (sbl->link[port_num].loopback_mode) {
+	case SBL_LOOPBACK_MODE_LOCAL:
+		for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+			if (!(rx_serdes_required_for_link_mode(sbl, port_num, serdes) ||
+			      tx_serdes_required_for_link_mode(sbl, port_num, serdes)))
+				continue;
+			err = sbl_serdes_spico_int(sbl, port_num, serdes,
+						   SPICO_INT_CM4_LOOPBACK,
+						SPICO_INT_DATA_ILB, NULL,
+						SPICO_INT_VALIDATE_RESULT);
+			if (err)
+				return err;
+		}
+		break;
+	case SBL_LOOPBACK_MODE_REMOTE:
+	case SBL_LOOPBACK_MODE_OFF:
+		for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+			if (!(rx_serdes_required_for_link_mode(sbl, port_num, serdes) ||
+			      tx_serdes_required_for_link_mode(sbl, port_num, serdes)))
+				continue;
+			err = sbl_serdes_spico_int(sbl, port_num, serdes,
+						   SPICO_INT_CM4_LOOPBACK,
+						SPICO_INT_DATA_ELB, NULL,
+						SPICO_INT_VALIDATE_RESULT);
+			if (err)
+				return err;
+		}
+		break;
+	default:
+		sbl_dev_warn(sbl->dev, "Unsupported loopback mode (enum %d)!",
+			     sbl->link[port_num].loopback_mode);
+		return -EINVAL;
+	}
+
+	/* Set port config values */
+	if (!allow_an) {
+		for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+			if (!(rx_serdes_required_for_link_mode(sbl, port_num, serdes) ||
+			      tx_serdes_required_for_link_mode(sbl, port_num, serdes)))
+				continue;
+			use_default_tx_eq = false;
+			use_default_gs    = false;
+			err = sbl_get_serdes_config_values(sbl, port_num,
+							   serdes,
+								&values);
+			if (err) {
+				sbl_dev_warn(sbl->dev,
+						     "p%ds%d: Unable to read config list!",
+						     port_num, serdes);
+				use_default_tx_eq = true;
+				use_default_gs    = true;
+			}
+			/* Apply tx eq values */
+			if (!use_default_tx_eq) {
+				err = sbl_set_tx_eq(sbl, port_num, serdes,
+						    values.atten,
+							 values.pre,
+							 values.post,
+							 values.pre2,
+							 values.pre3);
+				if (err) {
+					sbl_dev_warn(sbl->dev,
+						     "Bad settings for port %d! Applying defaults.",
+						     port_num);
+					use_default_tx_eq = true;
+				}
+			}
+			if (use_default_tx_eq) {
+				err = sbl_set_tx_eq(sbl, port_num, serdes,
+						    SBL_DFLT_PORT_CONFIG_ATTEN,
+						 SBL_DFLT_PORT_CONFIG_PRE,
+						 SBL_DFLT_PORT_CONFIG_POST,
+						 SBL_DFLT_PORT_CONFIG_PRE2,
+						 SBL_DFLT_PORT_CONFIG_PRE3);
+				if (err) {
+					sbl_dev_err(sbl->dev, "Default serdes atten/pre/post settings failed!");
+					return err;
+				}
+			}
+			/* Apply gainshape values */
+			if (!use_default_gs) {
+				err = sbl_set_gs(sbl, port_num, serdes,
+						 values.gs1,
+						      values.gs2);
+				if (err) {
+					sbl_dev_warn(sbl->dev,
+						     "Bad gs1/gs2 settings for port %d! Applying defaults.",
+						     port_num);
+					use_default_gs = true;
+				}
+			}
+			if (use_default_gs) {
+				err = sbl_set_gs(sbl, port_num, serdes,
+						 SBL_DFLT_PORT_CONFIG_GS1,
+					      SBL_DFLT_PORT_CONFIG_GS2);
+				if (err) {
+					sbl_dev_err(sbl->dev,
+						    "Default serdes gainshape settings failed!");
+					return err;
+				}
+			}
+
+			if (values.num_intr) {
+				sbl_dev_dbg(sbl->dev,
+					    "p%ds%d: Applying %d interrupts",
+					port_num, serdes, values.num_intr);
+			}
+			for (j = 0; j < values.num_intr; ++j) {
+				sbl_dev_dbg(sbl->dev,
+					    "p%d: Applying interrupt 0x%x with data 0x%x",
+				port_num, values.intr_val[j],
+				values.data_val[j]);
+				err = sbl_serdes_spico_int(sbl, port_num,
+							   serdes, values.intr_val[j],
+						values.data_val[j], &result,
+						SPICO_INT_RETURN_RESULT);
+				if (err) {
+					sbl_dev_warn(sbl->dev,
+						     "p%ds%d: interrupt 0x%x data 0x%x failed!",
+						     port_num, serdes, values.intr_val[j],
+						     values.data_val[j]);
+				}
+				if (result != values.intr_val[j]) {
+					sbl_dev_dbg(sbl->dev,
+						    "p%ds%d: interrupt:0x%x data:0x%x result:0x%x != code:0x%x. This is okay in some cases.",
+						 port_num, serdes, values.intr_val[j], values.data_val[j], result, values.intr_val[j]);
+				}
+			}
+		}
+	}
+	/* TODO - Set PRBS here */
+
+	/* Set Tx Phase Cal */
+	for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+		if (!(rx_serdes_required_for_link_mode(sbl, port_num, serdes) ||
+		      tx_serdes_required_for_link_mode(sbl, port_num, serdes)))
+			continue;
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_TX_PHASE_CAL,
+						SPICO_INT_DATA_TPCE, NULL,
+						SPICO_INT_VALIDATE_RESULT);
+		if (err)
+			return err;
+	}
+
+	/* Set Rx Phase Slip */
+	if (sbl->link[port_num].loopback_mode == SBL_LOOPBACK_MODE_LOCAL)
+		rx_phase_slip_reapply = 1;
+	else
+		rx_phase_slip_reapply = 0;
+
+	rx_phase_slip_cnt = sbl->iattr.rx_phase_slip_cnt;
+	if (rx_phase_slip_cnt > SPICO_INT_DATA_RX_PHASE_MAX) {
+		sbl_dev_warn(sbl->dev,
+			     "Invalid value for rx_phase_slip_cnt (0x%x). Setting to 0x%x",
+			 rx_phase_slip_cnt, SPICO_INT_DATA_RX_PHASE_MAX);
+		rx_phase_slip_cnt = SPICO_INT_DATA_RX_PHASE_MAX;
+	}
+	sbl_dev_dbg(sbl->dev, "p%d: rx_phase_slip_cnt: 0x%x", port_num,
+		    rx_phase_slip_cnt);
+	sbl_dev_dbg(sbl->dev, "p%d: rx_phase_slip_reapply: 0x%x", port_num,
+		    rx_phase_slip_reapply);
+
+	for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+		if (!(rx_serdes_required_for_link_mode(sbl, port_num, serdes) ||
+		      tx_serdes_required_for_link_mode(sbl, port_num, serdes)))
+			continue;
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_RX_PHASE_SLIP,
+						(rx_phase_slip_reapply << SPICO_INT_DATA_RXP_APPLY_OFFSET) |
+						(rx_phase_slip_cnt << SPICO_INT_DATA_RX_PHASE_OFFSET), NULL,
+						SPICO_INT_VALIDATE_RESULT);
+		if (err)
+			return err;
+	}
+
+	switch (sbl->link[port_num].loopback_mode) {
+	case SBL_LOOPBACK_MODE_LOCAL:
+		/* Disable TX and RX */
+		for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+			err = sbl_set_tx_rx_enable(sbl, port_num, serdes,
+						   false, false, false);
+			if (err)
+				return err;
+		}
+		break;
+	case SBL_LOOPBACK_MODE_REMOTE:
+	case SBL_LOOPBACK_MODE_OFF:
+		/* Disable TX */
+		for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+			if (rx_serdes_required_for_link_mode(sbl, port_num, serdes))
+				rx_en = true;
+			else
+				rx_en = false;
+			err = sbl_set_tx_rx_enable(sbl, port_num, serdes,
+						   false, rx_en, false);
+			if (err)
+				return err;
+		}
+		break;
+	default:
+		sbl_dev_warn(sbl->dev, "Unsupported loopback mode (enum %d)!",
+			     sbl->link[port_num].loopback_mode);
+		return -EINVAL;
+	}
+
+	msleep(20);
+
+	/* Enable tx on physical lane 0 - this has the clock for all serdes and
+	   is always required. */
+	/* rx based on link mode */
+	if (rx_serdes_required_for_link_mode(sbl, port_num, 0))
+		rx_en = true;
+	else
+		rx_en = false;
+	/* txo based on link mode */
+	if (get_serdes_tx_mask(sbl, port_num) & (1 << 0))
+		txo_en = true;
+	else
+		txo_en = false;
+	err = sbl_set_tx_rx_enable(sbl, port_num, 0,
+				   true, rx_en, txo_en);
+	if (err)
+		return err;
+
+	usleep_range(1000, 2000);
+
+	/* Enable lane 1 2 3 as needed */
+	for (serdes = 1; serdes < sbl->switch_info->num_serdes; ++serdes) {
+		if (rx_serdes_required_for_link_mode(sbl, port_num, serdes))
+			rx_en = true;
+		else
+			rx_en = false;
+		if (tx_serdes_required_for_link_mode(sbl, port_num, serdes)) {
+			tx_en = true;
+			txo_en = true;
+		} else {
+			tx_en = false;
+			txo_en = false;
+		}
+		err = sbl_set_tx_rx_enable(sbl, port_num, serdes,
+					   tx_en, rx_en, txo_en);
+		if (err)
+			return err;
+	}
+
+	for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+		if (!(rx_serdes_required_for_link_mode(sbl, port_num, serdes) ||
+		      tx_serdes_required_for_link_mode(sbl, port_num, serdes)))
+			continue;
+		if (sbl->link[port_num].blattr.tuning_pattern ==
+		    SBL_TUNING_PATTERN_CORE) {
+			err = sbl_set_tx_data_sel(sbl, port_num, serdes,
+						  SBL_DS_CORE);
+			if (err)
+				return err;
+		} else {
+			err = sbl_set_tx_data_sel(sbl, port_num, serdes,
+						  SBL_DS_PRBS);
+			if (err)
+				return err;
+		}
+	}
+
+	return 0;
+}
+
+int sbl_serdes_tuning(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	int err = 0;
+	int serdes;
+	bool is_retune;
+	int j;
+
+	sbl_dev_dbg(sbl->dev, "SerDes tuning for port %d", port_num);
+
+	mutex_lock(&link->tuning_params_mtx);
+	if (!(link->blattr.options & SBL_OPT_FABRIC_LINK)) {
+		sbl_dev_dbg(sbl->dev,
+			    "p%d: Saved tuning params disabled for edge links",
+				port_num);
+		is_retune = false;
+	} else if (link->tune_param_oob_count >= SBL_MAX_TUNE_PARAM_OOB_FAILS) {
+		sbl_dev_dbg(sbl->dev,
+			    "p%d: Ignoring saved param load - too many params oob!",
+				port_num);
+		link->tune_param_oob_count = 0;
+		is_retune = false;
+	} else if ((link->blattr.options & SBL_OPT_USE_SAVED_PARAMS) &&
+			(link->loopback_mode != SBL_LOOPBACK_MODE_LOCAL) &&
+			!sbl_debug_option(sbl, port_num, SBL_DEBUG_INHIBIT_USE_SAVED_TP)) {
+		is_retune = sbl_is_retune(sbl, port_num);
+	} else {
+		sbl_dev_dbg(sbl->dev,
+			    "p%d: Usage of saved tuning params is disabled!",
+				port_num);
+		is_retune = false;
+	}
+
+	if (is_retune) {
+		sbl_dev_dbg(sbl->dev, "p%d: Applying saved tuning params",
+			    port_num);
+		for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+			if (!rx_serdes_required_for_link_mode(sbl, port_num, serdes))
+				continue;
+			err = sbl_apply_serdes_tuning_params(sbl, port_num, serdes);
+			if (err) {
+				sbl_dev_err(sbl->dev, "p%ds%d: Failed to apply saved tuning params!",
+					    port_num, serdes);
+				mutex_unlock(&link->tuning_params_mtx);
+				return err;
+			}
+			sbl_dev_dbg(sbl->dev, "p%ds%d: saved tuning params applied", port_num, serdes);
+		}
+	} else {
+		sbl_dev_dbg(sbl->dev, "p%d: No saved tuning params found", port_num);
+	}
+	mutex_unlock(&link->tuning_params_mtx);
+
+	/* If we have applied saved params then the serdes should work straight away,
+	   we do not need to tune again. However we will start PCAL as normal.
+	   We mark the tune count to indicate we have done this */
+	if (is_retune) {
+		sbl_link_tune_zero_total_timespec(sbl, port_num);
+		link->dfe_tune_count = SBL_DFE_USED_SAVED_PARAMS;
+		link->serr = 0;
+
+		if (link->blattr.options & SBL_OPT_ENABLE_PCAL) {
+			if (sbl_debug_option(sbl, port_num, SBL_DEBUG_INHIBIT_PCAL)) {
+				sbl_dev_warn(sbl->dev, "%d: pcal inhibited\n", port_num);
+			} else {
+				err = sbl_port_start_pcal(sbl, port_num);
+				if (err)
+					return err;
+			}
+		} else {
+			sbl_dev_warn(sbl->dev, "p%d PCAL is disabled with SerDes saved params enabled!", port_num);
+		}
+
+		return link->serr;
+	}
+
+	/* There is already a delay after starting (configuring) the serdes to allow the
+	   optics to lock..
+	   This extra delay is about waiting for the link partner to start as we currently
+	   have no way of knowing this */
+	if (link->blattr.dfe_pre_delay) {
+		sbl_dev_dbg(sbl->dev, "p%d: pre delay of %d seconds...", port_num,
+			    link->blattr.dfe_pre_delay);
+		link->dfe_predelay_active = true;
+		for (j = 0; j < link->blattr.dfe_pre_delay; ++j) {
+			if (sbl_base_link_start_cancelled(sbl, port_num)) {
+				link->dfe_predelay_active = false;
+				return -ECANCELED;
+			}
+			if (sbl_start_timeout(sbl, port_num)) {
+				link->dfe_predelay_active = false;
+				return -ETIMEDOUT;
+			}
+			msleep(1000);
+		}
+		link->dfe_predelay_active = false;
+	}
+
+	/* Try to tune, keep going unless error, cancelled, timeout
+	   or too many failed param checks.
+	   In the latter case this is possibly because the saved tuning
+	   params are not good and we keep tuning to a bad place. We therefore
+	   need to fail here and reset the serdes on the next cycle to clear out
+	   the current tuning params */
+	sbl_dev_dbg(sbl->dev, "p%d: DFE %stune starting", port_num,
+		    is_retune ? "re" : "");
+
+	sbl_link_tune_zero_total_timespec(sbl, port_num);
+	link->dfe_tune_count = -1;
+	while (true) {
+		link->dfe_tune_count++;
+		link->serr = sbl_port_dfe_tune(sbl, port_num, is_retune);
+
+		switch (link->serr) {
+		case 0:
+			sbl_dev_dbg(sbl->dev, "p%d: dfe %stune good\n", port_num,
+				    is_retune ? "re" : "");
+
+			/* Setup the current tuning params for next time */
+			if (link->blattr.options & SBL_OPT_DFE_SAVE_PARAMS) {
+				sbl_dev_dbg(sbl->dev, "p%d: Saving tuning params...", port_num);
+				mutex_lock(&link->tuning_params_mtx);
+				err = sbl_save_serdes_tuning_params(sbl, port_num);
+				if (err) {
+					sbl_dev_warn(sbl->dev, "p%d: Failed to save tuning params [%d]",
+						     port_num, err);
+					/* not a fatal error */
+				}
+				mutex_unlock(&link->tuning_params_mtx);
+				sbl_dev_dbg(sbl->dev, "p%d: Saved tuning params", port_num);
+			}
+
+			if (sbl->link[port_num].blattr.tuning_pattern ==
+			    SBL_TUNING_PATTERN_PRBS) {
+				for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+					if (!rx_serdes_required_for_link_mode(sbl, port_num, serdes))
+						continue;
+					err = sbl_set_prbs_rx_mode(sbl, port_num, serdes);
+					if (err)
+						return err;
+
+				}
+			}
+			goto out;
+
+		case -ELNRNG:   /* tuning params out of range */
+			if (link->tune_param_oob_count >= SBL_MAX_TUNE_PARAM_OOB_FAILS) {
+				sbl_dev_info(sbl->dev, "%d: too many params oob fails\n", port_num);
+				/* give up and return error
+				   The calling framework should reset the spico to delete any
+				   applied tuning params so we can do a full tune */
+				goto out;
+			}
+			fallthrough;
+
+		case -ETIME:    /* tuning did not complete */
+		case -ECHRNG:   /* eye heights bad */
+
+			/*  try to tune again */
+
+			break;
+
+		case -ECANCELED:
+			sbl_dev_dbg(sbl->dev, "p%d: %stune cancelled\n", port_num,
+				    is_retune ? "re" : "");
+			goto out;
+
+		case -ETIMEDOUT:
+			sbl_dev_dbg(sbl->dev, "p%d: %stune timed out\n", port_num,
+				    is_retune ? "re" : "");
+			goto out;
+
+		default:
+			sbl_dev_dbg(sbl->dev, "p%d: %stune failed [%d]\n", port_num,
+				    is_retune ? "re" : "", link->serr);
+			goto out;
+		}
+	}
+
+out:
+	sbl_dev_dbg(sbl->dev, "p%d: SerDes tuning complete", port_num);
+	return link->serr;
+}
+
+int sbl_spico_reset(struct sbl_inst *sbl, int port_num)
+{
+	int serdes;
+	int err = 0;
+	int pass;
+	u32 sbus_addr;
+	u32 sbus_ring;
+	u32 result[SBL_SERDES_LANES_PER_PORT];
+	unsigned long last_jiffy;
+
+	sbl_dev_dbg(sbl->dev, "p%d: spico reset start", port_num);
+
+	sbus_ring = sbl->switch_info->ports[port_num].serdes[0].sbus_ring;
+	if (mutex_is_locked(SBUS_RING_MTX(sbl, sbus_ring)))
+		sbl_dev_dbg(sbl->dev, "spico_reset: Sbus contention detected, sbus_ring_mtx[%d] locked", sbus_ring);
+
+	/* SBUS Critical Section */
+	mutex_lock(SBUS_RING_MTX(sbl, sbus_ring));
+
+	/* Issue the reset */
+	for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+		if (!(rx_serdes_required_for_link_mode(sbl, port_num, serdes) ||
+		      tx_serdes_required_for_link_mode(sbl, port_num, serdes)))
+			continue;
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_PROC_RESET,
+				SPICO_INT_DATA_PROC_RESET, NULL,
+				SPICO_INT_IGNORE_RESULT);
+		if (err) {
+			mutex_unlock(SBUS_RING_MTX(sbl, sbus_ring));
+			sbl_dev_err(sbl->dev, "s%d: sbl_serdes_spico_int failed %d", sbus_ring, err);
+			return err;
+		}
+
+		/* Increment SPICO reset counter */
+		sbl_link_counters_incr(sbl, port_num, serdes0_spico_reset + serdes);
+	}
+
+	/* Check that each lane has been reset */
+	last_jiffy = jiffies + msecs_to_jiffies(SPICO_PROC_RESET_RETRY_TIMEOUT_MS);
+	pass = 0;
+	for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+		if (!(rx_serdes_required_for_link_mode(sbl, port_num, serdes) ||
+		      tx_serdes_required_for_link_mode(sbl, port_num, serdes)))
+			continue;
+		sbus_addr = SBUS_ADDR(sbl->switch_info->ports[port_num].serdes[serdes].sbus_ring,
+				      sbl->switch_info->ports[port_num].serdes[serdes].rx_addr);
+		do {
+			err = sbl_sbus_rd(sbl, sbus_addr,
+					  SBM_CRM_ADDR_PROC_STS,
+					       &result[serdes]);
+			if (err) {
+				mutex_unlock(SBUS_RING_MTX(sbl, sbus_ring));
+				return err;
+			}
+
+			if (!sbl->is_hw)
+				result[serdes] = SPICO_STATE_PAUSE;
+
+			if ((result[serdes] & SPICO_STATE_MASK) == SPICO_STATE_PAUSE) {
+				sbl_dev_dbg(sbl->dev, "p%ds%d: SPICO reset PAUSE: pass %d",
+					    port_num, serdes, pass);
+				break;
+			} else if ((result[serdes] & SPICO_STATE_MASK) == SPICO_STATE_ERROR) {
+				sbl_dev_dbg(sbl->dev, "p%ds%d: SPICO reset ERROR: pass %d",
+					    port_num, serdes, pass);
+				/* NOTE: I've seen the transition form ERROR -> PAUSE successfully */
+			} else {
+				sbl_dev_dbg(sbl->dev, "p%ds%d: SPICO reset OTHER 0x%x: pass %d",
+					    port_num, serdes, result[serdes], pass);
+			}
+			pass++;
+			/* No delay here, as we could miss the PAUSE state */
+		} while (time_is_after_jiffies(last_jiffy));
+
+	}
+	for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+		if (!(rx_serdes_required_for_link_mode(sbl, port_num, serdes) ||
+		      tx_serdes_required_for_link_mode(sbl, port_num, serdes)))
+			continue;
+		if ((result[serdes] & SPICO_STATE_MASK) != SPICO_STATE_PAUSE) {
+			sbl_dev_err(sbl->dev, "p%ds%d: SPICO reset failed! result: 0x%x after passes: %d",
+				    port_num, serdes, result[serdes], pass);
+			err = -ETIME;
+		}
+	}
+	if (err) {
+		mutex_unlock(SBUS_RING_MTX(sbl, sbus_ring));
+		return -ETIME;
+	}
+
+	sbl->link[port_num].pcal_running = false;
+
+	mutex_unlock(SBUS_RING_MTX(sbl, sbus_ring));
+
+	sbl_dev_dbg(sbl->dev, "p%d: spico reset done", port_num);
+	return 0;
+}
+
+
+#define SPICO_INT_DATA_PLL_RESET     0xffff
+
+int sbl_reset_serdes_plls(struct sbl_inst *sbl, int port_num)
+{
+	int serdes;
+	int err;
+
+	sbl_dev_info(sbl->dev, "p%d: resetting serdes PLLs", port_num);
+
+	for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+		if (!rx_serdes_required_for_link_mode(sbl, port_num, serdes))
+			continue;
+
+		err = sbl_serdes_spico_int(sbl, port_num, serdes,
+					   SPICO_INT_CM4_DFE_CTRL,
+				SPICO_INT_DATA_PLL_RESET, NULL,
+				SPICO_INT_VALIDATE_RESULT);
+		if (err) {
+			sbl_dev_err(sbl->dev, "p%ds%d: serdes PLL reset failed!", port_num, serdes);
+			return err;
+		}
+
+		/* Increment PLL reset counter */
+		sbl_link_counters_incr(sbl, port_num, serdes0_pll_reset + serdes);
+	}
+
+	return 0;
+}
+

-- 
2.56.0


^ permalink raw reply	[flat|nested] 25+ messages in thread
* [PATCH 05/23] net: hpe: sbl: add the PML link layer
  2026-10-30 20:58 [PATCH 00/23] Subject: [PATCH net-next 00/23] net/hpe: add HPE Slingshot NIC drivers Doug Ledford
                   ` (3 preceding siblings ...)
  2026-10-30 20:59 ` [PATCH 04/23] net: hpe: sbl: add the SerDes layer Doug Ledford
@ 2026-10-30 20:59 ` Doug Ledford
  2026-10-30 20:59 ` [PATCH 06/23] net: hpe: sbl: add link state management Doug Ledford
                   ` (18 subsequent siblings)
  23 siblings, 0 replies; 25+ messages in thread
From: Doug Ledford @ 2026-10-30 20:59 UTC (permalink / raw)
  To: Slingshot Open Source Team, Nathan Chancellor, Nicolas Schier,
	Richard Cochran, Andrew Lunn, David S. Miller, Eric Dumazet,
	Jakub Kicinski, Paolo Abeni, Sumit Semwal, Christian König,
	Guenter Roeck
  Cc: linux-kernel, netdev, linux-kbuild, Doug Ledford, Sandeep Bhoot,
	Mamila Santosh

Add the PML (physical media layer) code: MAC, PCS and LLR (link level
retry) configuration and the SerDes operation hooks.  The *_nic files
hold the parts that only apply to the NIC; the base files are shared
with the switch variant of this block.

checkpatch --strict (100 columns) still reports the following in this
patch. They need coordination with the internal repositories this code
is maintained in and will be fixed in V2:
- WARNING: LONG_LINE (33), LONG_LINE_COMMENT (7), TYPO_SPELLING (2)
- CHECK: BRACES (20), PARENTHESIS_ALIGNMENT (8), UNNECESSARY_PARENTHESES
  (7), OPEN_ENDED_LINE (2)

Co-developed-by: Sandeep Bhoot <sandeep.bhoot@hpe.com>
Signed-off-by: Sandeep Bhoot <sandeep.bhoot@hpe.com>
Co-developed-by: Mamila Santosh <santosh-kumar.mamila@hpe.com>
Signed-off-by: Mamila Santosh <santosh-kumar.mamila@hpe.com>
Signed-off-by: Doug Ledford <doug.ledford@hpe.com>
---
 drivers/net/ethernet/hpe/sbl/sbl_pml.c           |  787 ++++++++++++++++
 drivers/net/ethernet/hpe/sbl/sbl_pml_llr.c       |  736 +++++++++++++++
 drivers/net/ethernet/hpe/sbl/sbl_pml_llr_nic.c   |   34 +
 drivers/net/ethernet/hpe/sbl/sbl_pml_mac.c       |  220 +++++
 drivers/net/ethernet/hpe/sbl/sbl_pml_pcs.c       | 1085 ++++++++++++++++++++++
 drivers/net/ethernet/hpe/sbl/sbl_pml_pcs_nic.c   |   53 ++
 drivers/net/ethernet/hpe/sbl/sbl_pml_serdes_op.c |  145 +++
 7 files changed, 3060 insertions(+)

diff --git a/drivers/net/ethernet/hpe/sbl/sbl_pml.c b/drivers/net/ethernet/hpe/sbl/sbl_pml.c
new file mode 100644
index 000000000000..367c3184fb79
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sbl/sbl_pml.c
@@ -0,0 +1,787 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* Copyright 2019-2023 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/sched.h>
+#include <linux/jiffies.h>
+#include <linux/init.h>
+#include <linux/timer.h>
+
+#include <linux/hpe/sbl/sbl_kconfig.h>
+#include <linux/hpe/sbl/sbl.h>
+
+#include <linux/hpe/sbl/sbl_pml.h>
+
+#include "sbl_pml_fn.h"
+#include "sbl_link.h"
+#include "sbl_internal.h"
+#include "sbl_serdes_fn.h"
+
+/* Bring-up PML block of a link */
+int sbl_pml_start(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	int err;
+
+	sbl_dev_dbg(sbl->dev, "%d: pml bring-up starting", port_num);
+
+	/* serdes must be up */
+	if (link->sstate != SBL_SERDES_STATUS_RUNNING) {
+		sbl_dev_err(sbl->dev, "%d: pml serdes not running", port_num);
+		err = -ENOLINK;
+		goto out_err;
+	}
+
+	/* pcs must be sending am so link partner can tune */
+	if (!(READ_ONCE(link->link_info) & SBL_LINK_INFO_PCS_TX_AM)) {
+		sbl_dev_err(sbl->dev, "%d: pml pcs not tx am", port_num);
+		err = -ENODATA;
+		goto out_err;
+	}
+
+	/* make sure we have time left */
+	 sbl_start_timeout_ensure_remaining(sbl, port_num,
+					    SBL_PML_MIN_START_TIME);
+
+	/* make sure am locking is enabled */
+	if (!(READ_ONCE(link->link_info) & SBL_LINK_INFO_PCS_ALIGN_EN))
+		sbl_pml_pcs_enable_alignment(sbl, port_num);
+
+	err = sbl_pml_mac_config(sbl, port_num);
+	if (err) {
+		sbl_dev_err(sbl->dev, "%d: pml mac config failed [%d]", port_num, err);
+		goto out_err;
+	}
+
+	sbl_pml_llr_config(sbl, port_num);
+
+	/* keep trying to get the PML block up until
+	 * we succeed, timeout or have a fatal error
+	 */
+	while (true) {
+
+		/* wait for the pcs to come up  */
+		err = sbl_pml_pcs_wait(sbl, port_num);
+		switch (err) {
+		case 0:
+			/* good - carry on with mac */
+			break;
+		case -ECANCELED:
+			sbl_dev_dbg(sbl->dev, "%d: pml pcs wait cancelled", port_num);
+			goto out_err;
+		case -ETIMEDOUT:
+			sbl_dev_dbg(sbl->dev, "%d: pml pcs wait timeout", port_num);
+			goto out_err_invalidate;
+		default:
+			sbl_dev_dbg(sbl->dev, "%d: pml pcs wait failed [%d]", port_num, err);
+			goto out_err_invalidate;
+		}
+
+		sbl_pml_pcs_enable_auto_lane_degrade(sbl, port_num);
+
+		/* start mac */
+		sbl_pml_mac_start(sbl, port_num);
+
+		/* start llr */
+		err = sbl_pml_llr_start(sbl, port_num);
+		switch (err) {
+		case 0:
+			/* all good */
+			goto out_done;
+		case -ECANCELED:
+			sbl_dev_dbg(sbl->dev, "%d: pml llr start cancelled", port_num);
+			goto out_err;
+		case -ETIMEDOUT:
+			sbl_dev_dbg(sbl->dev, "%d: pml llr start timeout", port_num);
+			goto out_err;
+		default:
+			sbl_dev_dbg(sbl->dev, "%d: pml llr start failed [%d]", port_num, err);
+			goto out_err;
+		}
+	};
+
+out_done:
+	/* clear any PML errors which might have been set during startup */
+	sbl_pml_err_flgs_clear_all(sbl, port_num);
+
+	/* pml block is up */
+	sbl_dev_dbg(sbl->dev, "%d: pml bring-up done (up)", port_num);
+	return 0;
+
+out_err_invalidate:
+	if (link->dfe_tune_count == SBL_DFE_USED_SAVED_PARAMS) {
+		/* either the link partner is not starting or the saved params could be bad -
+		 * we cannot (currently) determine which so destroy the saved params
+		 * just in case
+		 */
+		sbl_dev_dbg(sbl->dev, "%d: pml bring-up - invalidating tuning params", port_num);
+		sbl_serdes_invalidate_tuning_params(sbl, port_num);
+	}
+out_err:
+	sbl_pml_mac_stop(sbl, port_num);
+	if (!sbl_debug_option(sbl, port_num, SBL_DEBUG_INHIBIT_CLEANUP))
+		sbl_pml_pcs_disable_alignment(sbl, port_num);
+	sbl_dev_dbg(sbl->dev, "%d: pml bring-up failed [%d]", port_num, err);
+	return err;
+}
+
+/* Take down the PML block of a link */
+int sbl_pml_link_down(struct sbl_inst *sbl, int port_num)
+{
+	sbl_dev_dbg(sbl->dev, "%d: pml bring-down starting\n", port_num);
+
+	sbl_pml_recovery_cancel(sbl, port_num);
+
+	/* stop everything in order */
+	sbl_pml_llr_stop(sbl, port_num);
+	sbl_pml_mac_stop(sbl, port_num);
+	sbl_pml_pcs_stop(sbl, port_num);
+
+	/* clear pml errors */
+	sbl_pml_err_flgs_clear_all(sbl, port_num);
+
+	sbl_dev_dbg(sbl->dev, "%d: pml bring-down done (down)\n", port_num);
+	return 0;
+}
+
+/* function to reset the major PML cfg regs to their default values
+ *
+ * It would seem that the default for the llr down behaviour is
+ * SBL_LLR_LINK_DOWN_BLOCK this should be SBL_LLR_LINK_DOWN_DISCARD;
+ */
+void sbl_pml_set_defaults(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	u32 base = SBL_PML_BASE(port_num);
+	u64 val64;
+	u64 llr_link_down_behavior;
+
+	/* pcs */
+	if (link->sstate != SBL_SERDES_STATUS_DOWN) {
+		/* default is to not tx am.
+		 * we should not do this because it can break optical headshells
+		 */
+		sbl_dev_warn(sbl->dev, "%d: pcs reset while serdes is running\n", port_num);
+	}
+
+	sbl_write64(sbl, base | SBL_PML_CFG_PCS_OFFSET,
+		    SBL_PML_CFG_PCS_DFLT);
+	sbl_write64(sbl, base | SBL_PML_CFG_PCS_AUTONEG_OFFSET,
+		    SBL_PML_CFG_PCS_AUTONEG_DFLT);
+	sbl_write64(sbl, base | SBL_PML_CFG_PCS_AUTONEG_TIMERS_OFFSET,
+		    SBL_PML_CFG_PCS_AUTONEG_TIMERS_DFLT);
+	sbl_write64(sbl, base | SBL_PML_CFG_PCS_AUTONEG_BASE_PAGE_OFFSET,
+		    SBL_PML_CFG_PCS_AUTONEG_BASE_PAGE_DFLT);
+	sbl_write64(sbl, base | SBL_PML_CFG_PCS_AUTONEG_NEXT_PAGE_OFFSET,
+		    SBL_PML_CFG_PCS_AUTONEG_NEXT_PAGE_DFLT);
+	sbl_write64(sbl, base | SBL_PML_CFG_PCS_AMS_OFFSET,
+		    SBL_PML_CFG_PCS_AMS_DFLT);
+	sbl_write64(sbl, base | SBL_PML_CFG_TX_PCS_OFFSET,
+		    SBL_PML_CFG_TX_PCS_DFLT);
+	sbl_write64(sbl, base | SBL_PML_CFG_RX_PCS_OFFSET,
+		    SBL_PML_CFG_RX_PCS_DFLT);
+
+	sbl_write64(sbl, base | SBL_PML_DBG_PCS_OFFSET, SBL_PML_DBG_PCS_DFLT);
+
+	/* pcs: we need special AMs for 200GHz mode */
+	sbl_write64(sbl, base | SBL_PML_CFG_RX_PCS_AMS_OFFSET,
+		    SBL_PML_CFG_RX_PCS_AMS_SET(SBL_PCS_200_UM_MATCH_MSK,
+					       SBL_PCS_200_CM_MATCH_MSK));
+	sbl_write64(sbl, base | SBL_PML_CFG_PCS_CM_OFFSET,
+		    SBL_PCS_200_CM);
+	sbl_write64(sbl, base | SBL_PML_CFG_PCS_UM_OFFSET(0), SBL_PCS_200_UM0);
+	sbl_write64(sbl, base | SBL_PML_CFG_PCS_UM_OFFSET(1), SBL_PCS_200_UM1);
+	sbl_write64(sbl, base | SBL_PML_CFG_PCS_UM_OFFSET(2), SBL_PCS_200_UM2);
+	sbl_write64(sbl, base | SBL_PML_CFG_PCS_UM_OFFSET(3), SBL_PCS_200_UM3);
+	sbl_write64(sbl, base | SBL_PML_CFG_PCS_UM_OFFSET(4), SBL_PCS_200_UM4);
+	sbl_write64(sbl, base | SBL_PML_CFG_PCS_UM_OFFSET(5), SBL_PCS_200_UM5);
+	sbl_write64(sbl, base | SBL_PML_CFG_PCS_UM_OFFSET(6), SBL_PCS_200_UM6);
+	sbl_write64(sbl, base | SBL_PML_CFG_PCS_UM_OFFSET(7), SBL_PCS_200_UM7);
+
+	/* assert we have destroyed any previous pcs config */
+	link->pcs_config = false;
+
+	/* mac */
+	sbl_write64(sbl, base | SBL_PML_CFG_TX_MAC_OFFSET,
+		    SBL_PML_CFG_TX_MAC_DFLT);
+	sbl_write64(sbl, base | SBL_PML_CFG_RX_MAC_OFFSET,
+		    SBL_PML_CFG_RX_MAC_DFLT);
+
+	/* llr */
+	val64 = SBL_PML_CFG_LLR_DFLT;
+	llr_link_down_behavior = sbl_pml_llr_link_down_behaviour(sbl, port_num);
+	val64 = SBL_PML_CFG_LLR_LINK_DOWN_BEHAVIOR_UPDATE(val64,
+							  llr_link_down_behavior);
+	sbl_write64(sbl, base | SBL_PML_CFG_LLR_OFFSET, val64);
+	sbl_write64(sbl, base | SBL_PML_CFG_LLR_SM_OFFSET,
+		    SBL_PML_CFG_LLR_SM_DFLT);
+
+	/* read to flush everything */
+	sbl_read64(sbl, base | SBL_PML_CFG_LLR_OFFSET);
+}
+
+/* interrupt support
+ *
+ * we only have one handler
+ */
+int sbl_pml_install_intr_handler(struct sbl_inst *sbl, int port_num, u64 err_flags)
+{
+	struct sbl_link *link = sbl->link + port_num;
+
+	if (link->intr_err_flgs) {
+		sbl_dev_err(sbl->dev, "intr %d: handler already registered\n", port_num);
+		return -EALREADY;
+	}
+	link->intr_err_flgs = err_flags;
+
+	return (*sbl->ops.sbl_pml_install_intr_handler)(sbl->accessor, port_num, err_flags);
+}
+
+int sbl_pml_enable_intr_handler(struct sbl_inst *sbl, int port_num, u64 err_flags)
+{
+	struct sbl_link *link = sbl->link + port_num;
+
+	if (!link->intr_err_flgs) {
+		sbl_dev_warn(sbl->dev, "intr %d: no handler registered for enable\n", port_num);
+		return 0;
+	}
+
+	if ((err_flags & ~link->intr_err_flgs) || !(err_flags & link->intr_err_flgs)) {
+		sbl_dev_err(sbl->dev, "intr %d: cannot enable flags 0x%llx, 0x%llx\n", port_num,
+			    err_flags, link->intr_err_flgs);
+		return -EINVAL;
+	}
+
+	return (*sbl->ops.sbl_pml_enable_intr_handler)(sbl->accessor, port_num, err_flags);
+}
+
+int sbl_pml_disable_intr_handler(struct sbl_inst *sbl, int port_num, u64 err_flags)
+{
+	struct sbl_link *link = sbl->link + port_num;
+
+	if (!link->intr_err_flgs) {
+		sbl_dev_warn(sbl->dev, "intr %d: no handler registered for disable\n", port_num);
+		return 0;
+	}
+
+	if ((err_flags & ~link->intr_err_flgs) || !(err_flags & link->intr_err_flgs)) {
+		sbl_dev_err(sbl->dev, "intr %d: cannot disable flags 0x%llx, 0x%llx\n", port_num,
+			    err_flags, link->intr_err_flgs);
+		return -EINVAL;
+	}
+
+	return (*sbl->ops.sbl_pml_disable_intr_handler)(sbl->accessor, port_num, err_flags);
+}
+
+int sbl_pml_remove_intr_handler(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	int err;
+
+	if (!link->intr_err_flgs) {
+		sbl_dev_warn(sbl->dev, "intr %d: no handler registered to remove\n", port_num);
+		return 0;
+	}
+
+	err =  (*sbl->ops.sbl_pml_remove_intr_handler)(sbl->accessor, port_num,
+			link->intr_err_flgs);
+	if (!err)
+		link->intr_err_flgs = 0;
+
+	return err;
+}
+
+/* Error flags
+ *
+ * TODO: inline?
+ */
+bool sbl_pml_err_flgs_test(struct sbl_inst *sbl, int port_num, u64 err_flgs)
+{
+	u32 base = SBL_PML_BASE(port_num);
+	u64 val64;
+
+	val64 = sbl_read64(sbl, base | SBL_PML_ERR_FLG_OFFSET);
+
+	return val64 & err_flgs;
+}
+
+void sbl_pml_err_flgs_clear(struct sbl_inst *sbl, int port_num, u64 err_flgs)
+{
+	u32 base = SBL_PML_BASE(port_num);
+
+	sbl_write64(sbl, base | SBL_PML_ERR_CLR_OFFSET, err_flgs);
+}
+
+void sbl_pml_err_flgs_clear_all(struct sbl_inst *sbl, int port_num)
+{
+	u32 base = SBL_PML_BASE(port_num);
+	u64 err_flgs;
+
+	err_flgs = sbl_read64(sbl, base | SBL_PML_ERR_FLG_OFFSET);
+	sbl_write64(sbl, base | SBL_PML_ERR_CLR_OFFSET, err_flgs);
+}
+
+static bool sbl_pml_recovery_ignore_down_origin_fault(enum sbl_link_down_origin down_origin)
+{
+	switch (down_origin) {
+	case SBL_LINK_DOWN_ORIGIN_LINK_DOWN:
+	case SBL_LINK_DOWN_ORIGIN_LOCAL_FAULT:
+	case SBL_LINK_DOWN_ORIGIN_REMOTE_FAULT:
+	case SBL_LINK_DOWN_ORIGIN_ALIGN:
+	case SBL_LINK_DOWN_ORIGIN_HISER:
+	case SBL_LINK_DOWN_ORIGIN_LLR_MAX:
+		return true;
+	default:
+		return false;
+	}
+}
+
+void sbl_pml_link_down_async_alert(struct sbl_inst *sbl, int port_num,
+				   enum sbl_link_down_origin down_origin)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	u32 base = SBL_PML_BASE(port_num);
+	u64 val64;
+	u64 err_flags;
+
+	val64 = sbl_read64(sbl, base | SBL_PML_CFG_LLR_SM_OFFSET);
+	if (SBL_PML_CFG_LLR_SM_REPLAY_CT_MAX_GET(val64) < SBL_LLR_REPLAY_CT_MAX_UNLIMITED)
+		err_flags = SBL_PML_FAULT_ERR_FLAGS;
+	else
+		err_flags = SBL_PML_REC_FAULT_ERR_FLAGS;
+
+	/* going down or in recovery state, so don't need more intrs */
+	sbl_pml_disable_intr_handler(sbl, port_num, err_flags);
+
+	if (sbl_debug_option(sbl, port_num, SBL_DEBUG_INHIBIT_CLEANUP)) {
+		/* set state to error and signal no cleanup with the error number */
+		link->blstate = SBL_BASE_LINK_STATUS_ERROR;
+		link->blerr = -ECONNABORTED;
+	}
+
+	sbl_async_alert(sbl, port_num, SBL_ASYNC_ALERT_LINK_DOWN,
+			(void *)(uintptr_t)down_origin, 0);
+}
+
+static void sbl_pml_recovery_origin_counter_update(struct sbl_inst *sbl, int port_num,
+						   enum sbl_link_down_origin origin)
+{
+	switch (origin) {
+	case SBL_LINK_DOWN_ORIGIN_LINK_DOWN:
+		sbl_link_counters_incr(sbl, port_num, pml_recovery_origin_bl_ldown);
+		break;
+	case SBL_LINK_DOWN_ORIGIN_LOCAL_FAULT:
+		sbl_link_counters_incr(sbl, port_num, pml_recovery_origin_bl_lfault);
+		break;
+	case SBL_LINK_DOWN_ORIGIN_REMOTE_FAULT:
+		sbl_link_counters_incr(sbl, port_num, pml_recovery_origin_bl_rfault);
+		break;
+	case SBL_LINK_DOWN_ORIGIN_ALIGN:
+		sbl_link_counters_incr(sbl, port_num, pml_recovery_origin_bl_align);
+		break;
+	case SBL_LINK_DOWN_ORIGIN_HISER:
+		sbl_link_counters_incr(sbl, port_num, pml_recovery_origin_bl_hiser);
+		break;
+	case SBL_LINK_DOWN_ORIGIN_LLR_MAX:
+		sbl_link_counters_incr(sbl, port_num, pml_recovery_origin_bl_llr);
+		break;
+	default:
+		sbl_dev_warn(sbl->dev, "%d: pml recovery origin (%d) with no counter",
+			     port_num, origin);
+		break;
+	}
+}
+
+/* PML recovery is limited by the combined amount of time spent in one or more
+ * recovery attempts over a window, rather than by a count. This approximates
+ * bandwidth loss. For example, 60 ms per second in PML recovery corresponds
+ * to a roughly %6 loss of bandwidth.
+ *
+ * After each successful recovery, the duration is subtracted from the
+ * remaining time budgeted for the window. The rate test fails if the remaining
+ * time is insufficient for another attempt.
+ */
+static bool sbl_pml_recovery_rate_test(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	u64 window_end = link->pml_recovery.rl_window_start + msecs_to_jiffies(link->blattr.pml_recovery.rl_window_size);
+
+	/* reset if not started or window has elapsed */
+	if (!link->pml_recovery.rl_window_start ||
+	    link->pml_recovery.init_jiffies > window_end) {
+		link->pml_recovery.rl_window_start = link->pml_recovery.init_jiffies;
+		link->pml_recovery.rl_time_remaining = link->blattr.pml_recovery.rl_max_duration;
+		return true;
+	}
+
+	if (link->pml_recovery.rl_time_remaining < SBL_PML_REC_POLL_INTERVAL)
+		return false;
+
+	return true;
+}
+
+static void sbl_pml_recovery_monitor_fallback_timer(struct timer_list *t)
+{
+	struct sbl_pml_recovery *pml_recovery = container_of(t, struct sbl_pml_recovery, timer);
+	struct sbl_inst *sbl;
+	struct sbl_link *link;
+	int port_num;
+	enum sbl_link_down_origin down_origin;
+	u32 elapsed;
+	u32 rl_total_time;
+	unsigned long timeout;
+	unsigned long irq_flags;
+
+	if (!pml_recovery || !pml_recovery->sbl)
+		return;
+
+	spin_lock_irqsave(&pml_recovery->lock, irq_flags);
+	if (!pml_recovery->enabled || !pml_recovery->started) {
+		spin_unlock_irqrestore(&pml_recovery->lock, irq_flags);
+		return;
+	}
+	spin_unlock_irqrestore(&pml_recovery->lock, irq_flags);
+
+	sbl = pml_recovery->sbl;
+	port_num = pml_recovery->port_num;
+	down_origin = pml_recovery->down_origin;
+	link = sbl->link + port_num;
+	timeout = pml_recovery->init_jiffies + msecs_to_jiffies(pml_recovery->timeout);
+	elapsed = jiffies_to_msecs(jiffies - link->pml_recovery.init_jiffies);
+	link->pml_recovery.rl_time_remaining -=
+		jiffies_to_msecs(jiffies -
+				 link->pml_recovery.last_poll_jiffies);
+	link->pml_recovery.last_poll_jiffies  = jiffies;
+
+	if (sbl_pml_recovery_no_faults(sbl, port_num)) {
+		sbl_dev_info(sbl->dev, "%d: PML recovered successfully in %ums", port_num, elapsed);
+		sbl_link_counters_incr(sbl, port_num, pml_recovery_successes);
+		sbl_pml_recovery_origin_counter_update(sbl, port_num, down_origin);
+		sbl_link_counters_incr(sbl, port_num, (elapsed < SBL_PML_REC_HISTOGRAM_MAX) ?
+				      (pml_recovery_histogram_0_9ms + elapsed / 10) :
+				       pml_recovery_histogram_high);
+		goto out;
+	} else if (time_is_before_eq_jiffies(timeout)) {
+		sbl_dev_info(sbl->dev, "%d: PML recovery monitor timed out (%ums)", port_num, elapsed);
+		goto out_fail;
+	} else if (!sbl_pml_recovery_rate_test(sbl, port_num)) {
+		rl_total_time = link->blattr.pml_recovery.rl_max_duration - link->pml_recovery.rl_time_remaining;
+		sbl_dev_err(sbl->dev, "%d: PML recovery rate exceeded (%ums/%ums) after %ums", port_num, rl_total_time,
+			    link->blattr.pml_recovery.rl_window_size, elapsed);
+		sbl_link_counters_incr(sbl, port_num, pml_recovery_rate_exceeded);
+		goto out_fail;
+	}
+
+	/* start timer for next poll */
+	spin_lock_irqsave(&pml_recovery->lock, irq_flags);
+	if (pml_recovery->enabled)
+		mod_timer(&pml_recovery->timer,
+			  jiffies + msecs_to_jiffies(SBL_PML_REC_POLL_INTERVAL));
+	spin_unlock_irqrestore(&pml_recovery->lock, irq_flags);
+	return;
+
+out_fail:
+	sbl_pml_link_down_async_alert(sbl, port_num, down_origin);
+
+out:
+	spin_lock_irqsave(&link->fec_discard_lock, irq_flags);
+	link->fec_discard_time = jiffies;
+	link->fec_discard_type = SBL_FEC_DISCARD_TYPE_PML_REC_END;
+	spin_unlock_irqrestore(&link->fec_discard_lock, irq_flags);
+	spin_lock_irqsave(&pml_recovery->lock, irq_flags);
+	pml_recovery->started = false;
+	spin_unlock_irqrestore(&pml_recovery->lock, irq_flags);
+}
+
+void sbl_pml_recovery_init(struct sbl_pml_recovery *recovery)
+{
+	spin_lock_init(&recovery->lock);
+	recovery->enabled = false;
+	timer_setup(&recovery->timer, sbl_pml_recovery_monitor_fallback_timer,
+		    TIMER_IRQSAFE);
+}
+
+/* Allow recovery once the fault monitor is about to deliver PML faults */
+void sbl_pml_recovery_enable(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_pml_recovery *recovery = &sbl->link[port_num].pml_recovery;
+	unsigned long irq_flags;
+
+	spin_lock_irqsave(&recovery->lock, irq_flags);
+	recovery->enabled = true;
+	spin_unlock_irqrestore(&recovery->lock, irq_flags);
+}
+
+static void sbl_pml_recovery_monitor(struct sbl_inst *sbl, int port_num,
+				     enum sbl_link_down_origin down_origin)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	struct sbl_pml_recovery *recovery = &link->pml_recovery;
+	u32 rl_total_time;
+	unsigned long irq_flags;
+
+	spin_lock_irqsave(&recovery->lock, irq_flags);
+	if (!recovery->enabled || recovery->started) {
+		spin_unlock_irqrestore(&recovery->lock, irq_flags);
+		return;
+	}
+
+	recovery->started = true;
+	recovery->init_jiffies = jiffies;
+	recovery->last_poll_jiffies = recovery->init_jiffies;
+	recovery->sbl = sbl;
+	recovery->port_num = port_num;
+	recovery->down_origin = down_origin;
+	recovery->timeout = link->blattr.pml_recovery.timeout;
+
+	if (!sbl_pml_recovery_rate_test(sbl, port_num)) {
+		rl_total_time = link->blattr.pml_recovery.rl_max_duration -
+				recovery->rl_time_remaining;
+		recovery->started = false;
+		spin_unlock_irqrestore(&recovery->lock, irq_flags);
+		sbl_dev_err(sbl->dev, "%d: PML recovery rate exceeded (%ums/%ums)", port_num,
+			    rl_total_time, link->blattr.pml_recovery.rl_window_size);
+		sbl_pml_link_down_async_alert(sbl, port_num, down_origin);
+		sbl_link_counters_incr(sbl, port_num, pml_recovery_rate_exceeded);
+		return;
+	}
+	sbl_link_counters_incr(sbl, port_num, pml_recovery_attempts);
+
+	spin_lock(&link->fec_discard_lock);
+	link->fec_discard_time = recovery->init_jiffies;
+	link->fec_discard_type = SBL_FEC_DISCARD_TYPE_PML_REC_START;
+	spin_unlock(&link->fec_discard_lock);
+
+	/* cancel cannot slip between restarting alignment and arming the poll */
+	sbl_pml_pcs_disable_alignment(sbl, port_num);
+	sbl_pml_pcs_enable_alignment(sbl, port_num);
+	mod_timer(&recovery->timer,
+		  jiffies + msecs_to_jiffies(SBL_PML_REC_POLL_INTERVAL));
+	spin_unlock_irqrestore(&recovery->lock, irq_flags);
+
+	sbl_dev_info(sbl->dev, "%d: PML recovery started - %s", port_num,
+		     sbl_down_origin_str(down_origin));
+}
+
+void sbl_pml_recovery_cancel(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	struct sbl_pml_recovery *recovery = &link->pml_recovery;
+	unsigned long irq_flags;
+	bool was_started;
+	u32 elapsed;
+
+	spin_lock_irqsave(&recovery->lock, irq_flags);
+	recovery->enabled = false;
+	spin_unlock_irqrestore(&recovery->lock, irq_flags);
+
+	/* with the gate closed neither the handler nor the timer can rearm */
+	timer_delete_sync(&recovery->timer);
+
+	spin_lock_irqsave(&recovery->lock, irq_flags);
+	was_started = recovery->started;
+	recovery->started = false;
+	spin_unlock_irqrestore(&recovery->lock, irq_flags);
+
+	if (!was_started)
+		return;
+
+	elapsed = jiffies_to_msecs(jiffies - recovery->init_jiffies);
+	spin_lock_irqsave(&link->fec_discard_lock, irq_flags);
+	link->fec_discard_time = jiffies;
+	link->fec_discard_type = SBL_FEC_DISCARD_TYPE_PML_REC_END;
+	spin_unlock_irqrestore(&link->fec_discard_lock, irq_flags);
+
+	sbl_dev_info(sbl->dev, "%d: PML recovery canceled (%ums)", port_num, elapsed);
+}
+
+/**
+ * sbl_pml_hdlr() - local interrupt handler called by surrounding framework
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ * @data: Value is NULL in all cases
+ *
+ * This function does the following operations: Reads PML error-flag
+ * registers, extracts PCS-lane degradation information for both TX
+ * and RX paths and issues warning alerts when failure conditions are
+ * met. If auto negotiation error flags are raised, the function disables
+ * further PML interrupts. It also logs critical error when all lanes
+ * are reported down, link faults. It also checks possible case of
+ * down origin and alert the clients.
+ *
+ * Context: Interrupt
+ *
+ * Return: 0 on success
+ */
+int sbl_pml_hdlr(struct sbl_inst *sbl, int port_num, void *data)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	u32 base = SBL_PML_BASE(port_num);
+	u64 raised_flgs;
+	u64 sts_pcs_lane_degrade_reg;
+	enum sbl_link_down_origin down_origin = SBL_LINK_DOWN_ORIGIN_UNKNOWN;
+	char pcs_state_str[SBL_PCS_STATE_STR_LEN];
+	u64 val64;
+	struct lane_degrade degrade_data;
+	enum sbl_async_alert_type alert = SBL_ASYNC_ALERT_INVALID;
+	int result;
+	unsigned long irq_flags;
+
+	raised_flgs = sbl_read64(sbl, base | SBL_PML_ERR_FLG_OFFSET) & link->intr_err_flgs;
+
+	if (!raised_flgs)
+		return 0;
+
+	if (sbl_debug_option(sbl, port_num, SBL_DEBUG_TRACE_PML_INT)) {
+		sbl_dev_info(sbl->dev,
+			     "%d: pml hdlr (%lld %lld hs%lld mr%lld ld%lld) in 0x%llx",
+			port_num,
+			SBL_PML_ERR_FLG_AUTONEG_PAGE_RECEIVED_GET(raised_flgs),
+			SBL_PML_ERR_FLG_AUTONEG_COMPLETE_GET(raised_flgs),
+			SBL_PML_ERR_FLG_PCS_HI_SER_GET(raised_flgs),
+			SBL_PML_ERR_FLG_LLR_REPLAY_AT_MAX_GET(raised_flgs),
+			SBL_PML_ERR_FLG_PCS_LINK_DOWN_GET(raised_flgs),
+			link->intr_err_flgs);
+	}
+
+	sts_pcs_lane_degrade_reg = sbl_read64(sbl, base | SBL_PML_STS_PCS_LANE_DEGRADE_OFFSET);
+	degrade_data.tx = SBL_PML_STS_PCS_LANE_DEGRADE_LP_PLS_AVAILABLE_GET(sts_pcs_lane_degrade_reg);
+	degrade_data.rx = SBL_PML_STS_PCS_LANE_DEGRADE_RX_PLS_AVAILABLE_GET(sts_pcs_lane_degrade_reg);
+	if (SBL_PML_ERR_FLG_PCS_RX_DEGRADE_GET(raised_flgs) && degrade_data.tx && degrade_data.rx) {
+		spin_lock_irqsave(&link->fec_discard_lock, irq_flags);
+		link->fec_discard_time = jiffies;
+		link->fec_discard_type = SBL_FEC_DISCARD_TYPE_RX_DEGRADE;
+		spin_unlock_irqrestore(&link->fec_discard_lock, irq_flags);
+		sbl_dev_warn(sbl->dev, "%d: RX side Degraded -> TX Lanes Available: 0x%llx - RX Lanes Available: 0x%llx",
+			     port_num, degrade_data.tx, degrade_data.rx);
+		sbl_async_alert(sbl, port_num, SBL_ASYNC_ALERT_RX_DEGRADE,
+				&degrade_data, sizeof(degrade_data));
+	}
+
+	if (SBL_PML_ERR_FLG_PCS_TX_DEGRADE_GET(raised_flgs) && degrade_data.tx && degrade_data.rx) {
+		sbl_dev_warn(sbl->dev, "%d: TX side Degraded -> TX Lanes Available: 0x%llx - RX Lanes Available: 0x%llx",
+			     port_num, degrade_data.tx, degrade_data.rx);
+		sbl_async_alert(sbl, port_num, SBL_ASYNC_ALERT_TX_DEGRADE,
+				&degrade_data, sizeof(degrade_data));
+	}
+
+	result = SBL_PML_ERR_FLG_PCS_TX_DEGRADE_FAILURE_GET(raised_flgs);
+
+	if (result) {
+		alert = SBL_ASYNC_ALERT_TX_DEGRADE_FAILURE;
+		sbl_async_alert(sbl, port_num, alert, NULL, 0);
+	}
+
+	result = SBL_PML_ERR_FLG_PCS_RX_DEGRADE_FAILURE_GET(raised_flgs);
+
+	if (result) {
+		alert = SBL_ASYNC_ALERT_RX_DEGRADE_FAILURE;
+		sbl_async_alert(sbl, port_num, alert, NULL, 0);
+	}
+
+	if (alert != SBL_ASYNC_ALERT_INVALID) {
+		/* if Auto Lane Degrade is enabled, we will print this message regardless of whether
+		 * the link went down because of lane degrade failure or not
+		 */
+		sbl_dev_err(sbl->dev, "%d: pml hdlr - link going down - all lanes down [%d]", port_num, alert);
+		down_origin = SBL_LINK_DOWN_ORIGIN_DEGRADE_FAILURE;
+	}
+
+	/* autoneg err flags */
+	if (raised_flgs & SBL_AUTONEG_ERR_FLGS) {
+		sbl_pml_disable_intr_handler(sbl, port_num, SBL_AUTONEG_ERR_FLGS);
+		complete(&link->an_hw_change);
+	}
+
+	/* link faults */
+	if (SBL_PML_ERR_FLG_PCS_HI_SER_GET(raised_flgs)) {
+		if (sbl_debug_option(sbl, port_num, SBL_DEBUG_IGNORE_HISER)) {
+			sbl_dev_warn(sbl->dev, "%d: pml hdlr - hiser - ignored", port_num);
+		} else {
+			sbl_dev_dbg(sbl->dev, "%d: pml hdlr - hiser", port_num);
+			down_origin = SBL_LINK_DOWN_ORIGIN_HISER;
+		}
+	}
+
+	val64 = sbl_read64(sbl, base | SBL_PML_CFG_LLR_SM_OFFSET);
+	if (SBL_PML_ERR_FLG_LLR_REPLAY_AT_MAX_GET(raised_flgs) &&
+	    SBL_PML_CFG_LLR_SM_REPLAY_CT_MAX_GET(val64) < SBL_LLR_REPLAY_CT_MAX_UNLIMITED) {
+		sbl_dev_dbg(sbl->dev, "%d: pml hdlr - max llr replay", port_num);
+		down_origin = SBL_LINK_DOWN_ORIGIN_LLR_MAX;
+	}
+
+	if (SBL_PML_ERR_FLG_PCS_LINK_DOWN_GET(raised_flgs)) {
+		val64 = sbl_read64(sbl, base | SBL_PML_STS_RX_PCS_OFFSET);
+
+		if (sbl_debug_option(sbl, port_num, SBL_DEBUG_TRACE_PML_INT)) {
+			sbl_dev_info(sbl->dev, "%d: pml hdlr - link down (%s)", port_num,
+				     sbl_pml_pcs_state_str(sbl, port_num, pcs_state_str,
+							   SBL_PCS_STATE_STR_LEN));
+		}
+
+		if (!SBL_PML_STS_RX_PCS_ALIGN_STATUS_GET(val64)) {
+			if (sbl_debug_option(sbl, port_num, SBL_DEBUG_IGNORE_ALIGN)) {
+				sbl_dev_warn(sbl->dev, "%d: pml hdlr - align - ignored", port_num);
+			} else {
+				sbl_dev_dbg(sbl->dev, "%d: pml hdlr - align", port_num);
+				down_origin = SBL_LINK_DOWN_ORIGIN_ALIGN;
+			}
+		} else if (SBL_PML_STS_RX_PCS_LOCAL_FAULT_GET(val64)) {
+			sbl_dev_dbg(sbl->dev, "%d: pml hdlr - local fault", port_num);
+			down_origin = SBL_LINK_DOWN_ORIGIN_LOCAL_FAULT;
+		} else if (SBL_PML_STS_RX_PCS_FAULT_GET(val64)) {
+			if (link->blattr.options & SBL_DISABLE_PML_RECOVERY ||
+			    sbl_debug_option(sbl, port_num, SBL_DEBUG_REMOTE_FAULT_RECOVERY)) {
+				sbl_dev_dbg(sbl->dev, "%d: pml hdlr - remote fault", port_num);
+				down_origin = SBL_LINK_DOWN_ORIGIN_REMOTE_FAULT;
+			} else {
+				sbl_dev_dbg(sbl->dev, "%d: pml hdlr - remote fault - ignored", port_num);
+			}
+		} else {
+			sbl_dev_dbg(sbl->dev, "%d: pml hdlr - link down", port_num);
+			down_origin = SBL_LINK_DOWN_ORIGIN_LINK_DOWN;
+		}
+	}
+
+	if (down_origin != SBL_LINK_DOWN_ORIGIN_UNKNOWN) {
+		if (!(link->blattr.options & SBL_DISABLE_PML_RECOVERY) && !link->is_degraded) {
+			if (sbl_pml_recovery_ignore_down_origin_fault(down_origin)) {
+				sbl_dev_dbg(sbl->dev, "%d: PML recovery, pml hdlr fault(%d) is ignored", port_num, down_origin);
+				sbl_pml_recovery_monitor(sbl, port_num, down_origin);
+
+			} else
+				sbl_pml_link_down_async_alert(sbl, port_num, down_origin);
+		} else {
+			sbl_dev_info(sbl->dev, "%d: PML recovery is disabled", port_num);
+			sbl_pml_link_down_async_alert(sbl, port_num, down_origin);
+		}
+	}
+
+	sbl_write64(sbl, base | SBL_PML_ERR_CLR_OFFSET, raised_flgs);
+	sbl_read64(sbl, base | SBL_PML_ERR_CLR_OFFSET);  /* flush */
+
+	return 0;
+}
+EXPORT_SYMBOL(sbl_pml_hdlr);
+
+/**
+ * sbl_pml_recovery_log_link_down() - Print pcs status when link down
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ *
+ * Print PCS receive path status and eye heights signal when
+ * reporting link down reason
+ */
+void sbl_pml_recovery_log_link_down(struct sbl_inst *sbl, int port_num)
+{
+	if (!sbl_pml_recovery_no_faults(sbl, port_num)) {
+		sbl_pml_recovery_log_pcs_status(sbl, port_num);
+		sbl_log_port_eye_heights(sbl, port_num);
+	}
+}
+EXPORT_SYMBOL(sbl_pml_recovery_log_link_down);
diff --git a/drivers/net/ethernet/hpe/sbl/sbl_pml_llr.c b/drivers/net/ethernet/hpe/sbl/sbl_pml_llr.c
new file mode 100644
index 000000000000..a190f6890b4e
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sbl/sbl_pml_llr.c
@@ -0,0 +1,736 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* Copyright 2019-2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/sched.h>
+
+#include <linux/hpe/sbl/sbl.h>
+#include <linux/hpe/sbl/sbl_an.h>
+#include <linux/hpe/sbl/sbl_kconfig.h>
+
+#include <linux/hpe/sbl/sbl_pml.h>
+
+#include "sbl_pml_fn.h"
+#include "sbl_link.h"
+#include "sbl_internal.h"
+
+static int sbl_pml_llr_ready_wait(struct sbl_inst *sbl, int port_num)
+{
+	int err = -1;
+
+	sbl_dev_dbg(sbl->dev, "%d: LLR ready wait", port_num);
+
+	sbl_link_info_set(sbl, port_num, SBL_LINK_INFO_LLR_WAIT);
+
+	while (sbl_pml_llr_get_state(sbl, port_num) != SBL_PML_LLR_STATE_ADVANCE) {
+
+		if (sbl_start_timeout(sbl, port_num)) {
+			sbl_dev_err(sbl->dev, "%d: LLR ready wait timeout", port_num);
+			err = -ETIMEDOUT;
+			goto out;
+		}
+
+		if (sbl_base_link_start_cancelled(sbl, port_num)) {
+			sbl_dev_err(sbl->dev, "%d: LLR ready wait cancelled", port_num);
+			err = -ECANCELED;
+			goto out;
+		}
+
+		/* should be relatively well synchronised by this point */
+		usleep_range(5000, 6000);
+	}
+
+	err = 0;
+
+out:
+	sbl_link_info_clear(sbl, port_num, SBL_LINK_INFO_LLR_WAIT);
+	return err;
+}
+
+/* calculate the loop time
+ *
+ * try to make a number of measurements or timeout/cancelled
+ */
+static int sbl_pml_llr_measure_loop_time_ns(struct sbl_inst *sbl, int port_num,
+					    u64 *llr_loop_time)
+{
+	struct sbl_link *link;
+	u32              base;
+	u64              min_loop_time;
+	u64              max_loop_time;
+	int              x;
+	u64              val64;
+	u64              time64;
+	int              err;
+
+	sbl_link_info_set(sbl, port_num, SBL_LINK_INFO_LLR_MEASURE);
+
+	link = sbl->link + port_num;
+	base = SBL_PML_BASE(port_num);
+
+	min_loop_time  = SBL_PML_LLR_MIN_LOOP_TIME;
+	max_loop_time  = SBL_PML_LLR_MAX_LOOP_TIME;
+	*llr_loop_time = SBL_PML_LLR_MAX_LOOP_TIME;
+	time64         = 0ULL;
+
+	sbl_dev_dbg(sbl->dev, "%d: LLR measure loop time (len = %s)(media = %s)",
+		    port_num, sbl_link_len_str(link->mattr.len),
+		    sbl_link_media_str(link->mattr.media));
+
+	/* calc loop time bounds */
+	if (link->mattr.len != SBL_LINK_LEN_INVALID) {
+		err = sbl_media_calc_loop_time(sbl, port_num, &min_loop_time);
+		if (err) {
+			sbl_dev_err(sbl->dev, "%d: LLR measure calc loop time failed [%d]", port_num, err);
+			goto out;
+		}
+		/* arbitrary range for max */
+		max_loop_time = min_loop_time + 100 /* ns */;
+	}
+	sbl_dev_dbg(sbl->dev, "%d: LLR measure loop time bounds: min = %lldns, max = %lldns",
+		    port_num, min_loop_time, max_loop_time);
+
+	/* measure loop time */
+	for (x = 0; x < SBL_PML_LLR_TIMING_LOOPS; ++x) {
+
+		if (sbl_start_timeout(sbl, port_num)) {
+			sbl_dev_err(sbl->dev, "%d: LLR measure loop time timeout", port_num);
+			err = -ETIMEDOUT;
+			goto out;
+		}
+
+		if (sbl_base_link_start_cancelled(sbl, port_num)) {
+			sbl_dev_err(sbl->dev, "%d: LLR measure loop time cancelled", port_num);
+			err = -ECANCELED;
+			goto out;
+		}
+
+		/* start a measurement */
+		sbl_write64(sbl, base | SBL_PML_STS_LLR_LOOP_TIME_OFFSET, 0ULL);
+		sbl_read64(sbl, base | SBL_PML_STS_LLR_LOOP_TIME_OFFSET);  /* flush */
+		/* give the measurement time to complete */
+		udelay(SBL_PML_LLR_TIMING_MEASURE_DELAY);
+		/* read the measurement */
+		val64 = sbl_read64(sbl, base | SBL_PML_STS_LLR_LOOP_TIME_OFFSET);
+
+		time64 = SBL_PML_STS_LLR_LOOP_TIME_LOOP_TIME_GET(val64); /* ns */
+		sbl_dev_dbg(sbl->dev, "%d: LLR measure time = %lldns (%d)", port_num, time64, x);
+
+		/* if we didn't get a valid time, then wait to retry */
+		if (!time64)
+			msleep(SBL_PML_LLR_TIMING_RETRY_DELAY);
+
+		/* if we did get a valid time, then check it here */
+		else if ((time64 >= min_loop_time) && (time64 <= max_loop_time)) {
+			/* save the fastest time here */
+			if (time64 < *llr_loop_time)
+				*llr_loop_time = time64;
+		}
+	}
+
+	/* check result here */
+	if (*llr_loop_time == SBL_PML_LLR_MAX_LOOP_TIME) {
+		if (sbl_debug_option(sbl, port_num, SBL_DEBUG_ALLOW_LOOP_TIME_FAIL)) {
+			sbl_dev_err(sbl->dev, "%d: LLR measure loop time failed (min = %lld, max = %lld, last = %lld)",
+				    port_num, min_loop_time, max_loop_time, time64);
+			err = -ENODATA;
+			goto out;
+		}
+		/* set to max calculated loop time */
+		*llr_loop_time = max_loop_time;
+	}
+
+	sbl_dev_dbg(sbl->dev, "%d: LLR measure loop time = %lldns", port_num, *llr_loop_time);
+	err = 0;
+
+out:
+	sbl_link_info_clear(sbl, port_num, SBL_LINK_INFO_LLR_MEASURE);
+	return err;
+}
+
+/*   calculate the required size of the llr buffer
+ *
+ *   we will use the measured loop time not cable length as we dont
+ *   always have that.
+ *
+ *   TODO: link degrade & mfs
+ */
+static void sbl_pml_llr_calculate_capacity(struct sbl_inst *sbl, int port_num,
+					   u64 *max_data, u64 *max_seq)
+{
+	struct sbl_link *link = sbl->link + port_num;
+
+	u64 bytes_per_ns = 25;
+	u64 bytes_per_frame = sbl_frame_size(sbl, port_num);
+	u64 cap_data_max;
+	u64 cap_seq_max;
+	u64 calc;
+
+	switch (link->link_mode) {
+	case SBL_LINK_MODE_BS_200G:
+		bytes_per_ns = 25;  /* 25000us */
+		break;
+	case SBL_LINK_MODE_BJ_100G:
+	case SBL_LINK_MODE_CD_100G:
+		bytes_per_ns = 13;  /* 12500us */
+		break;
+	case SBL_LINK_MODE_CD_50G:
+		bytes_per_ns =  7;  /*  6250us */
+		break;
+	}
+
+	sbl_llr_max_data_get(sbl, port_num, &cap_data_max, &cap_seq_max);
+
+	calc = (link->llr_loop_time * bytes_per_ns) + (bytes_per_frame * SBL_PML_LLR_NUM_FRAMES);
+
+	/* units 48 byte quanta */
+	*max_data = DIV_ROUND_UP(calc, 48);
+	if (*max_data > cap_data_max) {
+		sbl_dev_dbg(sbl->dev,
+			    "%d: LLR max data cap 0x%llx out of bounds, setting to 0x%llx",
+			port_num, *max_data, cap_data_max);
+		*max_data = cap_data_max;
+	}
+
+	/* units 32 byte frame size */
+	*max_seq  = DIV_ROUND_UP(calc, 32);
+	if (*max_seq > cap_seq_max) {
+		sbl_dev_dbg(sbl->dev,
+			    "%d: LLR max seq cap 0x%llx out of bounds, setting to 0x%llx",
+			port_num, *max_seq, cap_seq_max);
+		*max_seq = cap_seq_max;
+	}
+
+	sbl_dev_dbg(sbl->dev,
+		    "%d: LLR cap: data = 0x%llx, seq = 0x%llx",
+		port_num, *max_data, *max_seq);
+}
+
+/* enable llr timing measurements */
+static void sbl_pml_llr_enable_loop_timing(struct sbl_inst *sbl, int port_num)
+{
+	u32 base = SBL_PML_BASE(port_num);
+	u64 val64;
+
+	sbl_dev_dbg(sbl->dev, "%d: LLR enable loop timing", port_num);
+
+	val64 = sbl_read64(sbl, base | SBL_PML_CFG_LLR_OFFSET);
+	val64 = SBL_PML_CFG_LLR_ENABLE_LOOP_TIMING_UPDATE(val64, 1ULL);
+	sbl_write64(sbl, base | SBL_PML_CFG_LLR_OFFSET, val64);
+	sbl_read64(sbl, base | SBL_PML_CFG_LLR_OFFSET);  /* flush */
+
+	sbl_link_info_set(sbl, port_num, SBL_LINK_INFO_LLR_LOOP);
+}
+
+/* disable llr timing measurements */
+static void sbl_pml_llr_disable_loop_timing(struct sbl_inst *sbl, int port_num)
+{
+	u32 base = SBL_PML_BASE(port_num);
+	u64 val64;
+
+	sbl_dev_dbg(sbl->dev, "%d: LLR disable loop timing", port_num);
+
+	val64 = sbl_read64(sbl, base | SBL_PML_CFG_LLR_OFFSET);
+	val64 = SBL_PML_CFG_LLR_ENABLE_LOOP_TIMING_UPDATE(val64, 0ULL);
+	sbl_write64(sbl, base | SBL_PML_CFG_LLR_OFFSET, val64);
+	sbl_read64(sbl, base | SBL_PML_CFG_LLR_OFFSET);  /* flush */
+
+	sbl_link_info_clear(sbl, port_num, SBL_LINK_INFO_LLR_LOOP);
+}
+
+/* set LLR mode */
+static void sbl_pml_llr_mode_set(struct sbl_inst *sbl, int port_num, u32 llr_mode)
+{
+	u32 base = SBL_PML_BASE(port_num);
+	u64 val64;
+
+	sbl_dev_dbg(sbl->dev, "%d: LLR mode set (%d)", port_num, llr_mode);
+
+	val64 = sbl_read64(sbl, base | SBL_PML_CFG_LLR_OFFSET);
+	switch (llr_mode) {
+	case SBL_LLR_MODE_OFF:
+		val64 = SBL_PML_CFG_LLR_LLR_MODE_UPDATE(val64, 0ULL);
+		break;
+	case SBL_LLR_MODE_MONITOR:
+		val64 = SBL_PML_CFG_LLR_LLR_MODE_UPDATE(val64, 1ULL);
+		break;
+	case SBL_LLR_MODE_ON:
+		val64 = SBL_PML_CFG_LLR_LLR_MODE_UPDATE(val64, 2ULL);
+		break;
+	default:
+		sbl_dev_dbg(sbl->dev, "%d: LLR mode invalid (%d)", port_num, llr_mode);
+		return;
+	}
+	sbl_write64(sbl, base | SBL_PML_CFG_LLR_OFFSET, val64);
+	sbl_read64(sbl, base | SBL_PML_CFG_LLR_OFFSET);  /* flush */
+}
+
+/* LLR detect */
+static int sbl_pml_llr_detect(struct sbl_inst *sbl, int port_num, u32 *llr_mode)
+{
+	u32           base       = SBL_PML_BASE(port_num);
+	u64           val64      = 0;
+	u64           time64     = 0;
+	unsigned long last_jiffy = jiffies + msecs_to_jiffies(SBL_PML_LLR_DETECT_TIMEOUT);
+	int           err        = -1;
+
+	sbl_dev_dbg(sbl->dev, "%d: LLR detect", port_num);
+
+	sbl_link_info_set(sbl, port_num, SBL_LINK_INFO_LLR_DETECT);
+
+	/* OFF unless we detect a loop */
+	*llr_mode = SBL_LLR_MODE_OFF;
+
+	sbl_write64(sbl, (base | SBL_PML_STS_LLR_LOOP_TIME_OFFSET), 0ULL);
+	sbl_read64(sbl, (base | SBL_PML_STS_LLR_LOOP_TIME_OFFSET));  /* flush */
+	do {
+
+		if (sbl_start_timeout(sbl, port_num)) {
+			err = -ETIMEDOUT;
+			goto out;
+		}
+
+		if (sbl_base_link_start_cancelled(sbl, port_num)) {
+			err = -ECANCELED;
+			goto out;
+		}
+
+		msleep(SBL_PML_LLR_DETECT_DELAY);
+
+		val64 = sbl_read64(sbl, (base | SBL_PML_STS_LLR_LOOP_TIME_OFFSET));
+		time64 = SBL_PML_STS_LLR_LOOP_TIME_LOOP_TIME_GET(val64);                 /* ns */
+		sbl_dev_dbg(sbl->dev, "%d: LLR time = %lldns", port_num, time64);
+
+		if (time64) {
+			/* loop detected */
+			if ((time64 < SBL_PML_LLR_MIN_LOOP_TIME) || (time64 > SBL_PML_LLR_MAX_LOOP_TIME)) {
+				sbl_dev_warn(sbl->dev, "%d: LLR time out of bounds (%lldns)", port_num, time64);
+				continue;
+			}
+			*llr_mode = SBL_LLR_MODE_ON;
+			err = 0;
+			goto out;
+		}
+
+	} while (time_before(jiffies, last_jiffy));
+
+out:
+	sbl_link_info_clear(sbl, port_num, SBL_LINK_INFO_LLR_DETECT);
+	return err;
+}
+
+/* get LLR mode */
+static int sbl_pml_llr_mode_get(struct sbl_inst *sbl, int port_num, u32 *llr_mode)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	int               err = -1;
+
+	sbl_dev_dbg(sbl->dev, "%d: LLR mode get (%d)", port_num, link->blattr.llr_mode);
+
+	switch (link->blattr.llr_mode) {
+
+	case SBL_LLR_MODE_MONITOR:
+		sbl_dev_dbg(sbl->dev, "%d: LLR mode monitor", port_num);
+		*llr_mode = SBL_LLR_MODE_MONITOR;
+		return 0;
+
+	case SBL_LLR_MODE_ON:
+		sbl_dev_dbg(sbl->dev, "%d: LLR mode on", port_num);
+		goto out_on;
+
+	case SBL_LLR_MODE_AUTO:
+		/* check fabric link here */
+		if (link->blattr.options & SBL_OPT_FABRIC_LINK) {
+			sbl_dev_dbg(sbl->dev, "%d: LLR mode on fabric", port_num);
+			goto out_on;
+		}
+		/* check ether link here */
+		if (!(link->blattr.options & SBL_OPT_ENABLE_ETHER_LLR))
+			goto out_off;
+		/* check AN options here */
+		if (link->an_options & AN_OPT_LLR) {
+			if (link->an_options & AN_OPT_ETHER_LLR) {
+				if (link->an_options & AN_OPT_HPC_WITH_LLR) {
+					link->llr_options |= SBL_PML_LLR_OPTION_HPC_WIH_LLR;
+					link->ifg_config = SBL_IFG_CONFIG_HPC;
+					sbl_dev_dbg(sbl->dev, "%d: LLR mode on with HPC from AN", port_num);
+					goto out_on;
+				}
+				sbl_dev_dbg(sbl->dev, "%d: LLR mode on without HPC from AN", port_num);
+				goto out_on;
+			}
+			goto out_off;
+		}
+		/* do loop detect here */
+		err = sbl_pml_llr_detect(sbl, port_num, &(link->llr_mode));
+		switch (err) {
+		case 0:
+			if (link->llr_mode == SBL_LLR_MODE_OFF)
+				goto out_off;
+			if (link->blattr.options & SBL_OPT_ENABLE_IFG_HPC_WITH_LLR) {
+				link->llr_options |= SBL_PML_LLR_OPTION_HPC_WIH_LLR;
+				link->ifg_config = SBL_IFG_CONFIG_HPC;
+				sbl_dev_dbg(sbl->dev, "%d: LLR mode on with HPC from LOOP", port_num);
+				goto out_on;
+			}
+			sbl_dev_dbg(sbl->dev, "%d: LLR mode on without HPC from LOOP", port_num);
+			goto out_on;
+		case -ECANCELED:
+			sbl_dev_dbg(sbl->dev, "%d: LLR detect cancelled", port_num);
+			goto out_err;
+		case -ETIMEDOUT:
+			sbl_dev_dbg(sbl->dev, "%d: LLR detect timed out", port_num);
+			goto out_err;
+		default:
+			goto out_off;
+		}
+		goto out_off;
+
+	case SBL_LLR_MODE_OFF:
+		goto out_off;
+
+	default:
+		sbl_dev_err(sbl->dev, "%d: LLR invalid mode [%d]", port_num, link->blattr.llr_mode);
+		err = -EBADRQC;
+		goto out_err;
+	}
+
+out_off:
+	sbl_dev_dbg(sbl->dev, "%d: LLR mode off", port_num);
+	*llr_mode = SBL_LLR_MODE_OFF;
+	return 0;
+
+out_on:
+	*llr_mode = SBL_LLR_MODE_ON;
+	return 0;
+
+out_err:
+	*llr_mode = SBL_LLR_MODE_OFF;
+	return err;
+}
+
+/* configure */
+void sbl_pml_llr_config(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	u32 base = SBL_PML_BASE(port_num);
+	u64 val64;
+
+	sbl_dev_dbg(sbl->dev, "%d: LLR config", port_num);
+
+	/* init to original requested */
+	link->llr_mode = link->blattr.llr_mode;
+
+	/* config */
+	sbl_write64(sbl, base | SBL_PML_STS_LLR_MAX_USAGE_OFFSET, 0ULL);
+	val64 = sbl_read64(sbl, base | SBL_PML_CFG_LLR_OFFSET);
+	val64 = SBL_PML_CFG_LLR_LLR_MODE_UPDATE(val64, 0ULL);  /* LLR OFF */
+	val64 = SBL_PML_CFG_LLR_PREAMBLE_SEQ_CHECK_UPDATE(val64, 1ULL);
+	val64 = SBL_PML_CFG_LLR_ACK_NACK_ERR_CHECK_UPDATE(val64, 1ULL);
+	val64 = SBL_PML_CFG_LLR_FILTER_LOSSLESS_WHEN_OFF_UPDATE(val64, 1ULL);
+	val64 = SBL_PML_CFG_LLR_FILTER_CTL_FRAMES_UPDATE(val64, 1ULL);
+	val64 = SBL_PML_CFG_LLR_SIZE_UPDATE(val64, 3ULL);
+	val64 = SBL_PML_CFG_LLR_ENABLE_LOOP_TIMING_UPDATE(val64, 0ULL);  /* loop timing off */
+	val64 = SBL_PML_CFG_LLR_LINK_DOWN_BEHAVIOR_UPDATE(val64,
+				 sbl_pml_llr_link_down_behaviour(sbl,
+								 port_num));
+	val64 = SBL_PML_CFG_LLR_MAC_IF_CREDITS_UPDATE(val64,
+						      SBL_PML_CFG_LLR_MAC_IF_CREDITS_DFLT);
+	sbl_write64(sbl, base | SBL_PML_CFG_LLR_OFFSET, val64);
+
+	sbl_write64(sbl, base | SBL_PML_CFG_LLR_CF_SMAC_OFFSET,
+		    SBL_PML_CFG_LLR_CF_SMAC_DFLT);
+
+	sbl_write64(sbl, base | SBL_PML_CFG_LLR_CF_ETYPE_OFFSET,
+		    SBL_PML_CFG_LLR_CF_ETYPE_DFLT);
+
+	sbl_write64(sbl, base | SBL_PML_CFG_LLR_SM_OFFSET,
+		    SBL_PML_CFG_LLR_SM_DFLT);
+
+	val64 = sbl_read64(sbl, base | SBL_PML_CFG_LLR_CF_RATES_OFFSET);
+	val64 = SBL_PML_CFG_LLR_CF_RATES_LOOP_TIMING_PERIOD_UPDATE(val64, SBL_PML_LLR_TIMING_PERIOD);
+	sbl_write64(sbl, base | SBL_PML_CFG_LLR_CF_RATES_OFFSET, val64);
+
+	sbl_read64(sbl, base | SBL_PML_CFG_LLR_OFFSET);  /* flush */
+}
+
+/* start */
+int sbl_pml_llr_start(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	u32 base = SBL_PML_BASE(port_num);
+	u64 llr_max_data;
+	u64 llr_max_seq;
+	u64 val64;
+	u64 recovery_timeout_ns;
+	int err = -1;
+
+	sbl_dev_dbg(sbl->dev, "%d: LLR start", port_num);
+
+	sbl_link_info_clear(sbl, port_num, SBL_LINK_INFO_LLR_DISABLED);
+
+	sbl_pml_llr_enable_loop_timing(sbl, port_num);
+
+	/* get mode here */
+	err = sbl_pml_llr_mode_get(sbl, port_num, &(link->llr_mode));
+	if (err) {
+		sbl_dev_err(sbl->dev, "%d: LLR get mode failed [%d]", port_num, err);
+		goto out_err;
+	}
+
+	/* if LLR is OFF then nothing to do here */
+	if (link->llr_mode == SBL_LLR_MODE_OFF)
+		goto out;
+
+	/* set HPC if needed */
+	if (link->llr_options & SBL_PML_LLR_OPTION_HPC_WIH_LLR)
+		sbl_pml_mac_hpc_set(sbl, port_num);
+
+	/* start ordered sets */
+	sbl_pml_pcs_ordered_sets(sbl, port_num, true);
+
+	/* measure llr loop time if we don't have it already */
+	if (!link->llr_loop_time) {
+		err = sbl_pml_llr_measure_loop_time_ns(sbl, port_num, &link->llr_loop_time);
+		if (err) {
+			sbl_dev_err(sbl->dev, "%d: LLR loop measurement failed [%d]", port_num, err);
+			goto out_err;
+		}
+	}
+
+	/* set max replay time from loop-back time */
+	val64 = sbl_read64(sbl, base | SBL_PML_CFG_LLR_SM_OFFSET);
+	if (link->blattr.options & SBL_DISABLE_PML_RECOVERY)
+		val64 = SBL_PML_CFG_LLR_SM_REPLAY_CT_MAX_UPDATE(val64, SBL_DFLT_REPLAY_CT_MAX);
+	else
+		val64 = SBL_PML_CFG_LLR_SM_REPLAY_CT_MAX_UPDATE(val64, SBL_LLR_REPLAY_CT_MAX_UNLIMITED);
+	val64 = SBL_PML_CFG_LLR_SM_REPLAY_TIMER_MAX_UPDATE(val64,
+							   3 * link->llr_loop_time + 500);
+	sbl_write64(sbl, base | SBL_PML_CFG_LLR_SM_OFFSET, val64);
+	sbl_read64(sbl, base | SBL_PML_CFG_LLR_SM_OFFSET);  /* flush */
+
+	/* capacity configuration */
+	if (link->blattr.options & SBL_OPT_FABRIC_LINK) {
+		/* these can be set to their defaults for fabric links */
+		sbl_write64(sbl, base | SBL_PML_CFG_LLR_CAPACITY_OFFSET,
+			    SBL_PML_CFG_LLR_CAPACITY_DFLT);
+		sbl_read64(sbl, base | SBL_PML_CFG_LLR_CAPACITY_OFFSET);  /* flush */
+	} else {
+		sbl_pml_llr_calculate_capacity(sbl, port_num, &llr_max_data, &llr_max_seq);
+		val64 = SBL_PML_CFG_LLR_CAPACITY_MAX_DATA_SET(llr_max_data) |
+			SBL_PML_CFG_LLR_CAPACITY_MAX_SEQ_SET(llr_max_seq);
+		sbl_write64(sbl, base | SBL_PML_CFG_LLR_CAPACITY_OFFSET, val64);
+		sbl_read64(sbl, base | SBL_PML_CFG_LLR_CAPACITY_OFFSET);  /* flush */
+	}
+
+	/* set max data age timer & link down timer */
+	if (link->blattr.options & SBL_DISABLE_PML_RECOVERY)
+		sbl_write64(sbl, base | SBL_PML_CFG_LLR_TIMEOUTS_OFFSET,
+			    SBL_PML_CFG_LLR_TIMEOUTS_DFLT);
+	else {
+		recovery_timeout_ns = ((u64)link->blattr.pml_recovery.timeout +
+			SBL_PML_REC_LLR_TIMEOUT_OFFSET) * NSEC_PER_MSEC;
+		if (recovery_timeout_ns > U32_MAX) {
+			err = -ERANGE;
+			goto out_err;
+		}
+		val64 = sbl_read64(sbl, base | SBL_PML_CFG_LLR_TIMEOUTS_OFFSET);
+		val64 = SBL_PML_CFG_LLR_TIMEOUTS_DATA_AGE_TIMER_MAX_UPDATE(val64,
+			recovery_timeout_ns);
+		val64 = SBL_PML_CFG_LLR_TIMEOUTS_PCS_LINK_DN_TIMER_MAX_UPDATE(val64,
+			recovery_timeout_ns);
+		sbl_write64(sbl, base | SBL_PML_CFG_LLR_TIMEOUTS_OFFSET, val64);
+	}
+	sbl_read64(sbl, base | SBL_PML_CFG_LLR_TIMEOUTS_OFFSET);  /* flush */
+
+	/* clear all the llr related error flags */
+	sbl_pml_err_flgs_clear(sbl, port_num, SBL_PML_ALL_LLR_ERR_FLGS);
+
+	/* set required mode */
+	sbl_pml_llr_mode_set(sbl, port_num, link->llr_mode);
+
+	/* wait for llr to start */
+	err = sbl_pml_llr_ready_wait(sbl, port_num);
+	if (err) {
+		sbl_dev_err(sbl->dev, "%d: LLR ready wait failed [%d]", port_num, err);
+		goto out_err;
+	}
+
+	/* success */
+	sbl_dev_dbg(sbl->dev, "%d: LLR running", port_num);
+	sbl_link_info_set(sbl, port_num, SBL_LINK_INFO_LLR_RUN);
+
+out:
+	sbl_pml_llr_disable_loop_timing(sbl, port_num);
+	return 0;
+
+out_err:
+	sbl_pml_llr_disable_loop_timing(sbl, port_num);
+	sbl_pml_llr_stop(sbl, port_num);
+	return err;
+}
+
+/**
+ * sbl_pml_llr_get_state() - Get pml llr state
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ *
+ * Return: state value
+ */
+u32 sbl_pml_llr_get_state(struct sbl_inst *sbl, int port_num)
+{
+	u32 base  = SBL_PML_BASE(port_num);
+	u64 val64 = sbl_read64(sbl, base | SBL_PML_STS_LLR_OFFSET);
+
+	switch (SBL_PML_STS_LLR_LLR_STATE_GET(val64)) {
+	case 0: /* OFF */
+		return SBL_PML_LLR_STATE_OFF;
+	case 1: /* INIT */
+		return SBL_PML_LLR_STATE_INIT;
+	case 2: /* ADVANCE */
+		return SBL_PML_LLR_STATE_ADVANCE;
+	case 3: /* HALT */
+		return SBL_PML_LLR_STATE_HALT;
+	case 4: /* REPLAY */
+		return SBL_PML_LLR_STATE_REPLAY;
+	case 5: /* DISCARD */
+		return SBL_PML_LLR_STATE_DISCARD;
+	case 6: /* MONITOR */
+		return SBL_PML_LLR_STATE_MONITOR;
+	default:
+		return SBL_PML_LLR_STATE_UNKNOWN;
+	}
+}
+EXPORT_SYMBOL(sbl_pml_llr_get_state);
+
+/**
+ * sbl_pml_llr_stop() - Stop pml llr functionality
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ *
+ * Configure various pml llr registers to stop functionality
+ */
+void sbl_pml_llr_stop(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	u32 base = SBL_PML_BASE(port_num);
+	u64 val64;
+
+	sbl_dev_dbg(sbl->dev, "%d: LLR stop", port_num);
+
+	link->llr_mode = SBL_LLR_MODE_OFF;
+
+	val64 = sbl_read64(sbl, base | SBL_PML_CFG_LLR_OFFSET);
+	val64 = SBL_PML_CFG_LLR_LLR_MODE_UPDATE(val64, 0LL);  /* LLR OFF */
+	val64 = SBL_PML_CFG_LLR_FILTER_LOSSLESS_WHEN_OFF_UPDATE(val64, 1ULL);
+	val64 = SBL_PML_CFG_LLR_FILTER_CTL_FRAMES_UPDATE(val64, 0ULL);
+	val64 = SBL_PML_CFG_LLR_ENABLE_LOOP_TIMING_UPDATE(val64, 0ULL);
+	val64 = SBL_PML_CFG_LLR_LINK_DOWN_BEHAVIOR_UPDATE(val64,
+				 sbl_pml_llr_link_down_behaviour(sbl,
+								 port_num));
+	val64 = SBL_PML_CFG_LLR_MAC_IF_CREDITS_UPDATE(val64,
+						      SBL_PML_CFG_LLR_MAC_IF_CREDITS_DFLT);
+	sbl_write64(sbl, base | SBL_PML_CFG_LLR_OFFSET, val64);
+	sbl_read64(sbl, base | SBL_PML_CFG_LLR_OFFSET);  /* flush */
+
+	sbl_pml_pcs_ordered_sets(sbl, port_num, false);
+
+	sbl_link_info_clear(sbl, port_num, SBL_LINK_INFO_LLR_RUN);
+	sbl_link_info_clear(sbl, port_num, SBL_LINK_INFO_LLR_DISABLED);
+}
+EXPORT_SYMBOL(sbl_pml_llr_stop);
+
+/**
+ * sbl_pml_llr_disable() - Disable pml llr
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ *
+ * This function disables the LLR feature by updating the LLR
+ * mode configuration register. Also updates the link info to reflect
+ * disabled state and clear active status.
+ */
+void sbl_pml_llr_disable(struct sbl_inst *sbl, int port_num)
+{
+	u32 base = SBL_PML_BASE(port_num);
+	u64 val64;
+
+	sbl_dev_dbg(sbl->dev, "%d: LLR disable", port_num);
+
+	val64 = sbl_read64(sbl, base | SBL_PML_CFG_LLR_OFFSET);
+	val64 = SBL_PML_CFG_LLR_LLR_MODE_UPDATE(val64, 0ULL); /* LLR OFF */
+	sbl_write64(sbl, base | SBL_PML_CFG_LLR_OFFSET, val64);
+	sbl_read64(sbl, base | SBL_PML_CFG_LLR_OFFSET);  /* flush */
+
+	sbl_link_info_set(sbl, port_num, SBL_LINK_INFO_LLR_DISABLED);
+	sbl_link_info_clear(sbl, port_num, SBL_LINK_INFO_LLR_RUN);
+}
+EXPORT_SYMBOL(sbl_pml_llr_disable);
+
+/**
+ * sbl_pml_llr_enable() - Enable pml llr
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ *
+ * Sets the LLR mode based on the link configuration to
+ * enable the LLR feature.
+ */
+void sbl_pml_llr_enable(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+
+	sbl_dev_dbg(sbl->dev, "%d: LLR enable", port_num);
+
+	sbl_pml_llr_mode_set(sbl, port_num, link->llr_mode);
+}
+EXPORT_SYMBOL(sbl_pml_llr_enable);
+
+/**
+ * sbl_pml_llr_check_is_ready() - check llr state
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ * @timeout_ms: Value
+ *
+ * Check matching LLR state in invervals, if state
+ * matches then return else sleep in intervals untill timeout.
+ *
+ * Context: Sleep in intervals based on condition
+ *
+ * Return: true on success
+ */
+bool sbl_pml_llr_check_is_ready(struct sbl_inst *sbl, int port_num, unsigned int timeout_ms)
+{
+	unsigned long to_jiffy = jiffies + msecs_to_jiffies(timeout_ms);
+
+	sbl_dev_dbg(sbl->dev, "%d: LLR check is ready", port_num);
+
+	do {
+		if (sbl_pml_llr_get_state(sbl, port_num) == SBL_PML_LLR_STATE_ADVANCE)
+			return true;
+		usleep_range(5000, 6000);
+	} while (time_before(jiffies, to_jiffy));
+
+	return false;
+}
+EXPORT_SYMBOL(sbl_pml_llr_check_is_ready);
+
+/* behaviour when the link is down
+ * TODO - revisit with cassini and/or faster restart
+ */
+u64 sbl_pml_llr_link_down_behaviour(struct sbl_inst *sbl,
+				    int port_num)
+{
+	if (sbl_is_fabric_link(sbl, port_num)) {
+		/*   fabric link should really be BLOCK, but only if the pcs
+		 *   can recover quickly. Currently it can't - pcs failure means
+		 *   going right back to tuning the serdes.
+		 */
+		return 0ULL;
+	}
+
+	return 0ULL;
+}
diff --git a/drivers/net/ethernet/hpe/sbl/sbl_pml_llr_nic.c b/drivers/net/ethernet/hpe/sbl/sbl_pml_llr_nic.c
new file mode 100644
index 000000000000..d154a2f25c6e
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sbl/sbl_pml_llr_nic.c
@@ -0,0 +1,34 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/sched.h>
+
+#include <linux/hpe/sbl/sbl.h>
+#include <linux/hpe/sbl/sbl_an.h>
+#include <linux/hpe/sbl/sbl_kconfig.h>
+
+#include <linux/hpe/sbl/sbl_pml.h>
+
+#include "sbl_pml_fn.h"
+#include "sbl_link.h"
+#include "sbl_internal.h"
+
+int sbl_frame_size(struct sbl_inst *sbl, int port_num)
+{
+	u64 bytes_per_frame = 9216;
+
+	return bytes_per_frame;
+}
+
+void sbl_llr_max_data_get(struct sbl_inst *sbl, int port_num,
+			  u64 *cap_data_max, u64 *cap_seq_max)
+{
+	*cap_data_max = sbl_llr_edge_cap_data_max_get();
+	*cap_seq_max  = sbl_llr_edge_cap_seq_max_get();
+}
diff --git a/drivers/net/ethernet/hpe/sbl/sbl_pml_mac.c b/drivers/net/ethernet/hpe/sbl/sbl_pml_mac.c
new file mode 100644
index 000000000000..782bfc26451e
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sbl/sbl_pml_mac.c
@@ -0,0 +1,220 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* Copyright 2019-2021 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/sched.h>
+
+#include <linux/hpe/sbl/sbl.h>
+#include <linux/hpe/sbl/sbl_kconfig.h>
+
+#include <linux/hpe/sbl/sbl_pml.h>
+
+#include "sbl_pml_fn.h"
+#include "sbl_link.h"
+#include "sbl_internal.h"
+
+/* get mode */
+static void sbl_pml_mac_get_mode(struct sbl_inst *sbl, int port_num, u64 *ifg_mode, u64 *ifg_adjustment)
+{
+	struct sbl_link *link = sbl->link + port_num;
+
+	sbl_dev_dbg(sbl->dev, "%d: MAC get mode", port_num);
+
+	/* start with what was requested */
+	link->ifg_config = link->blattr.ifg_config;
+
+	/* check BL options */
+	if (link->blattr.options & SBL_OPT_ENABLE_IFG_CONFIG) {
+		/* set using IFG config */
+		switch (link->ifg_config) {
+		case SBL_IFG_CONFIG_HPC:
+			*ifg_mode       = 0;
+			*ifg_adjustment = 3;
+			break;
+		case SBL_IFG_CONFIG_IEEE_200G:
+			*ifg_mode       = 1;
+			*ifg_adjustment = 0;
+			break;
+		case SBL_IFG_CONFIG_IEEE_100G:
+			*ifg_mode       = 1;
+			*ifg_adjustment = 1;
+			break;
+		case SBL_IFG_CONFIG_IEEE_50G:
+		default:
+			*ifg_mode       = 1;
+			*ifg_adjustment = 2;
+			break;
+		}
+	} else if (link->blattr.options & SBL_OPT_FABRIC_LINK) {
+		/* set fabric link */
+		*ifg_mode       = 0;
+		*ifg_adjustment = 3;
+	} else {
+		/* set ether link */
+		switch (link->link_mode) {
+		case SBL_LINK_MODE_BS_200G:
+			*ifg_mode       = 1;
+			*ifg_adjustment = 0;
+			break;
+		case SBL_LINK_MODE_BJ_100G:
+			*ifg_mode       = 1;
+			*ifg_adjustment = 1;
+			break;
+		case SBL_LINK_MODE_CD_100G:
+			*ifg_mode       = 1;
+			*ifg_adjustment = 1;
+			break;
+		case SBL_LINK_MODE_CD_50G:
+		default:
+			*ifg_mode       = 1;
+			*ifg_adjustment = 2;
+			break;
+		}
+	}
+}
+
+/* configure */
+int sbl_pml_mac_config(struct sbl_inst *sbl, int port_num)
+{
+	u32 base = SBL_PML_BASE(port_num);
+	u64 ifg_mode       = 0;
+	u64 ifg_adjustment = 0;
+	u64 val64;
+
+	sbl_dev_dbg(sbl->dev, "%d: MAC config", port_num);
+
+	sbl_pml_mac_get_mode(sbl, port_num, &ifg_mode, &ifg_adjustment);
+
+	/* tx mac config */
+	val64 = sbl_read64(sbl, base | SBL_PML_CFG_TX_MAC_OFFSET);
+	val64 = SBL_PML_CFG_TX_MAC_PCS_CREDITS_UPDATE(val64,
+						      SBL_PML_CFG_TX_MAC_PCS_CREDITS_DFLT);
+	val64 = SBL_PML_CFG_TX_MAC_IFG_MODE_UPDATE(val64, ifg_mode);
+	val64 = SBL_PML_CFG_TX_MAC_IEEE_IFG_ADJUSTMENT_UPDATE(val64, ifg_adjustment);
+	/* Short preamble is always 0 for now. See Rosetta ERRATA-2594 */
+	val64 = SBL_PML_CFG_TX_MAC_SHORT_PREAMBLE_UPDATE(val64, 0ULL);
+	val64 = SBL_PML_CFG_TX_MAC_MAC_OPERATIONAL_UPDATE(val64, 0ULL);
+	sbl_write64(sbl, base | SBL_PML_CFG_TX_MAC_OFFSET, val64);
+	sbl_read64(sbl, base | SBL_PML_CFG_TX_MAC_OFFSET);  /* flush */
+
+	/* rx mac config */
+	val64 = sbl_read64(sbl, base | SBL_PML_CFG_RX_MAC_OFFSET);
+	val64 = SBL_PML_CFG_RX_MAC_SHORT_PREAMBLE_UPDATE(val64, 0ULL);
+	val64 = SBL_PML_CFG_RX_MAC_FILTER_ILLEGAL_SIZE_UPDATE(val64, 1ULL);
+	val64 = SBL_PML_CFG_RX_MAC_MAC_OPERATIONAL_UPDATE(val64, 0ULL);
+	sbl_write64(sbl, base | SBL_PML_CFG_RX_MAC_OFFSET, val64);
+	sbl_read64(sbl, base | SBL_PML_CFG_RX_MAC_OFFSET);  /* flush */
+
+	return 0;
+}
+
+/**
+ * sbl_pml_mac_start() - Start mac
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ *
+ * Configure various MAC registers to start tx/rx mac
+ * and clear if any errors
+ */
+void sbl_pml_mac_start(struct sbl_inst *sbl, int port_num)
+{
+	u32 base = SBL_PML_BASE(port_num);
+	u64 val64;
+
+	sbl_dev_dbg(sbl->dev, "%d: MAC start", port_num);
+
+	/* tx mac start */
+	val64 = sbl_read64(sbl, base | SBL_PML_CFG_TX_MAC_OFFSET);
+	val64 = SBL_PML_CFG_TX_MAC_MAC_OPERATIONAL_UPDATE(val64, 1ULL);
+	sbl_write64(sbl, base | SBL_PML_CFG_TX_MAC_OFFSET, val64);
+	sbl_read64(sbl, base | SBL_PML_CFG_TX_MAC_OFFSET);  /* flush */
+
+	/* rx mac start */
+	val64 = sbl_read64(sbl, base | SBL_PML_CFG_RX_MAC_OFFSET);
+	val64 = SBL_PML_CFG_RX_MAC_MAC_OPERATIONAL_UPDATE(val64, 1ULL);
+	sbl_write64(sbl, base | SBL_PML_CFG_RX_MAC_OFFSET, val64);
+	sbl_read64(sbl, base | SBL_PML_CFG_RX_MAC_OFFSET);  /* flush */
+
+	/* clear any errors */
+	val64 = SBL_PML_ERR_FLG_MAC_TX_DP_ERR_SET(1ULL) |
+		SBL_PML_ERR_FLG_MAC_RX_DP_ERR_SET(1ULL);
+	sbl_write64(sbl, base | SBL_PML_ERR_CLR_OFFSET, val64);
+	sbl_read64(sbl, base | SBL_PML_ERR_CLR_OFFSET);  /* flush */
+
+	sbl_link_info_set(sbl, port_num, SBL_LINK_INFO_MAC_OP);
+
+}
+EXPORT_SYMBOL(sbl_pml_mac_start);
+
+/**
+ * sbl_pml_mac_stop() - Stop mac
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ *
+ * Configure various MAC registers to off tx/rx mac
+ */
+void sbl_pml_mac_stop(struct sbl_inst *sbl, int port_num)
+{
+	u32 base = SBL_PML_BASE(port_num);
+	u64 val64;
+
+	sbl_dev_dbg(sbl->dev, "%d: MAC stop", port_num);
+
+	/* rx mac off */
+	val64 = sbl_read64(sbl, base | SBL_PML_CFG_RX_MAC_OFFSET);
+	val64 = SBL_PML_CFG_RX_MAC_MAC_OPERATIONAL_UPDATE(val64, 0ULL);
+	sbl_write64(sbl, base | SBL_PML_CFG_RX_MAC_OFFSET, val64);
+	sbl_read64(sbl, base | SBL_PML_CFG_RX_MAC_OFFSET);  /* flush */
+
+	/* tx mac off */
+	val64 = sbl_read64(sbl, base | SBL_PML_CFG_TX_MAC_OFFSET);
+	val64 = SBL_PML_CFG_TX_MAC_MAC_OPERATIONAL_UPDATE(val64, 0ULL);
+	sbl_write64(sbl, base | SBL_PML_CFG_TX_MAC_OFFSET, val64);
+	sbl_read64(sbl, base | SBL_PML_CFG_TX_MAC_OFFSET);  /* flush */
+
+	sbl_link_info_clear(sbl, port_num, SBL_LINK_INFO_MAC_OP);
+}
+EXPORT_SYMBOL(sbl_pml_mac_stop);
+
+/* get the current hw status */
+void sbl_pml_mac_hw_status(struct sbl_inst *sbl, int port_num, bool *tx_op, bool *rx_op,
+			   u32 *ifg_mode, u32 *ifg_adjustment)
+{
+	u32 base = SBL_PML_BASE(port_num);
+	u64 val64;
+
+	sbl_dev_dbg(sbl->dev, "%d: MAC status", port_num);
+
+	val64 = sbl_read64(sbl, base | SBL_PML_CFG_TX_MAC_OFFSET);
+	if (tx_op)
+		*tx_op = SBL_PML_CFG_TX_MAC_MAC_OPERATIONAL_GET(val64);
+	if (ifg_mode)
+		*ifg_mode = SBL_PML_CFG_TX_MAC_IFG_MODE_GET(val64);
+	if (ifg_adjustment)
+		*ifg_adjustment = SBL_PML_CFG_TX_MAC_IEEE_IFG_ADJUSTMENT_GET(val64);
+	if (rx_op) {
+		val64 = sbl_read64(sbl, base | SBL_PML_CFG_RX_MAC_OFFSET);
+		*rx_op = SBL_PML_CFG_RX_MAC_MAC_OPERATIONAL_GET(val64);
+	}
+}
+
+/* HPC IFG set */
+void sbl_pml_mac_hpc_set(struct sbl_inst *sbl, int port_num)
+{
+	u32 base  = SBL_PML_BASE(port_num);
+	u64 val64 = 0;
+
+	sbl_dev_dbg(sbl->dev, "%d: MAC HPC set", port_num);
+
+	val64 = sbl_read64(sbl, (base | SBL_PML_CFG_TX_MAC_OFFSET));
+	val64 = SBL_PML_CFG_TX_MAC_IFG_MODE_UPDATE(val64, 0ULL); /* HPC */
+	val64 = SBL_PML_CFG_TX_MAC_IEEE_IFG_ADJUSTMENT_UPDATE(val64, 3ULL); /* no adjustment */
+	sbl_write64(sbl, (base | SBL_PML_CFG_TX_MAC_OFFSET), val64);
+	sbl_read64(sbl, (base | SBL_PML_CFG_TX_MAC_OFFSET));  /* flush */
+}
+
diff --git a/drivers/net/ethernet/hpe/sbl/sbl_pml_pcs.c b/drivers/net/ethernet/hpe/sbl/sbl_pml_pcs.c
new file mode 100644
index 000000000000..81484e177394
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sbl/sbl_pml_pcs.c
@@ -0,0 +1,1085 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* Copyright 2019,2022-2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/sched.h>
+
+#include <linux/hpe/sbl/sbl.h>
+#include <linux/hpe/sbl/sbl_kconfig.h>
+#include <linux/hpe/sbl/sbl_pml.h>
+
+#include "sbl_pml_fn.h"
+#include "sbl_link.h"
+#include "sbl_serdes_map.h"
+#include "sbl_internal.h"
+#include "sbl_serdes_fn.h"
+
+/* Function to find the lanes that data will be arriving on and
+ * setup the correct active lanes to align and active fec lanes.
+ */
+static int sbl_pml_pcs_determine_active_lanes(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	struct serdes_info *serdes =  sbl->switch_info->ports[port_num].serdes;
+	int i;
+
+	sbl_dev_dbg(sbl->dev, "%d: pcs config lanes", port_num);
+
+	switch (link->link_mode) {
+	case SBL_LINK_MODE_BS_200G:
+		/* 4 lanes of 50Gbps - 8 internal 25Gbps fec lanes
+		 * setup directly
+		 */
+		link->active_rx_lanes  = 0xf;    /* all */
+		link->active_fec_lanes = 0xff;   /* all */
+		break;
+	case SBL_LINK_MODE_BJ_100G:
+		/* 4 lanes of 25Gbps - 4 internal 25Gbps lanes
+		 * setup directly
+		 */
+		link->active_rx_lanes  = 0xf;    /* all */
+		link->active_fec_lanes = 0xf;    /* special case */
+		break;
+	case SBL_LINK_MODE_CD_100G:
+		/* 2 lanes of 50Gbps - 4 internal 25Gbps lanes
+		 * locate incoming lanes 0 and 1
+		 */
+		link->active_rx_lanes  = 0;
+		link->active_fec_lanes = 0;
+		if (link->loopback_mode == SBL_LOOPBACK_MODE_LOCAL) {
+			/* we will receive on the tx lanes we went out on */
+			for (i = 0; i < SBL_SERDES_LANES_PER_PORT; ++i) {
+				if (serdes[i].tx_lane_source < 2) {
+					link->active_rx_lanes  |= 0x1 << i;
+					link->active_fec_lanes |= 0x3 << 2 * i;
+				}
+			}
+		} else {
+			/* we will receive on the rx lanes */
+			for (i = 0; i < SBL_SERDES_LANES_PER_PORT; ++i) {
+				if (serdes[i].rx_lane_source < 2) {
+					link->active_rx_lanes  |= 0x1 << i;
+					link->active_fec_lanes |= 0x3 << 2 * i;
+				}
+			}
+		}
+		break;
+	case SBL_LINK_MODE_CD_50G:
+		/* 1 lanes of 50Gbps - 2 internal 25Gbps lanes
+		 * locate incoming lane 0
+		 */
+		if (link->loopback_mode == SBL_LOOPBACK_MODE_LOCAL) {
+			/* we will receive on the lane 0 we went out on */
+			for (i = 0; i < SBL_SERDES_LANES_PER_PORT; ++i) {
+				if (serdes[i].tx_lane_source == 0) {
+					link->active_rx_lanes  = 0x1 << i;
+					link->active_fec_lanes = 0x3 << 2 * i;
+					break;
+				}
+			}
+		} else {
+			/* we will receive on the rx lane */
+			for (i = 0; i < SBL_SERDES_LANES_PER_PORT; ++i) {
+				if (serdes[i].rx_lane_source == 0) {
+					link->active_rx_lanes  = 0x1 << i;
+					link->active_fec_lanes = 0x3 << 2 * i;
+				}
+			}
+		}
+		break;
+	default:
+		sbl_dev_err(sbl->dev, "%d: pcs bad link_mode (%d)", port_num, link->link_mode);
+		return -EBADRQC;
+	}
+
+	return 0;
+}
+
+/* helper state functions */
+static bool sbl_pml_pcs_locked(struct sbl_inst *sbl, int port_num)
+{
+	u32 base = SBL_PML_BASE(port_num);
+	struct sbl_link *link = sbl->link + port_num;
+	u64 locked_lanes;
+	u64 val64;
+
+	val64 = sbl_read64(sbl, base | SBL_PML_STS_RX_PCS_OFFSET);
+	locked_lanes = SBL_PML_STS_RX_PCS_AM_LOCK_GET(val64);
+
+	return (locked_lanes == link->active_fec_lanes);
+}
+
+static void sbl_pml_pcs_start_lock(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	u32 base = SBL_PML_BASE(port_num);
+	u64 val64;
+
+	sbl_dev_dbg(sbl->dev, "%d: pml bring-up start am lock\n", port_num);
+
+	val64 = sbl_read64(sbl, base | SBL_PML_CFG_RX_PCS_OFFSET);
+	val64 = SBL_PML_CFG_RX_PCS_ENABLE_LOCK_UPDATE(val64, 1ULL);
+	val64 = SBL_PML_CFG_RX_PCS_ACTIVE_LANES_UPDATE(val64, link->active_rx_lanes);
+	sbl_write64(sbl, base | SBL_PML_CFG_RX_PCS_OFFSET, val64);
+	sbl_read64(sbl, base | SBL_PML_CFG_RX_PCS_OFFSET);
+}
+
+static void sbl_pml_pcs_stop_lock(struct sbl_inst *sbl, int port_num)
+{
+	u32 base = SBL_PML_BASE(port_num);
+	u64 val64;
+
+	sbl_dev_dbg(sbl->dev, "%d: pml bring-up stop am lock\n", port_num);
+
+	val64 = sbl_read64(sbl, base | SBL_PML_CFG_RX_PCS_OFFSET);
+	val64 = SBL_PML_CFG_RX_PCS_ENABLE_LOCK_UPDATE(val64, 0ULL);
+	val64 = SBL_PML_CFG_RX_PCS_ACTIVE_LANES_UPDATE(val64, 0ULL);
+	sbl_write64(sbl, base | SBL_PML_CFG_RX_PCS_OFFSET, val64);
+	sbl_read64(sbl, base | SBL_PML_CFG_RX_PCS_OFFSET);
+}
+
+/* wait for the pcs to become aligned */
+static int sbl_pml_pcs_alignment_wait(struct sbl_inst *sbl, int port_num)
+{
+	unsigned long start_jiffy;
+	int elapsed;
+	int err = 0;
+
+	sbl_dev_dbg(sbl->dev, "%d: pml pcs alignment wait\n", port_num);
+
+	sbl_link_info_set(sbl, port_num, SBL_LINK_INFO_PCS_A_WAIT);
+
+	 /*   poll for all lanes to get bitlock
+	  *
+	  *   This might be a very long time as the other end obviously needs to
+	  *   be coming up at the same time. So start eagerly checking and then back off.
+	  *
+	  *   If we are getting a high serdes error rate or bad eyes then we can never
+	  *   meaningfully lock so bail with an error and the serdes will be retuned.
+	  *
+	  *   Occasionally the pcs seems to get stuck and some lanes never come up.
+	  *   Restarting locking seems to clear this.
+	  */
+restart:
+	start_jiffy = jiffies;
+	while (!sbl_pml_pcs_locked(sbl, port_num)) {
+
+		if (sbl_start_timeout(sbl, port_num)) {
+			sbl_dev_dbg(sbl->dev, "%d: pcs lock wait timeout\n",
+				    port_num);
+			err = -ETIMEDOUT;
+			goto out;
+		}
+
+		if (sbl_base_link_start_cancelled(sbl, port_num)) {
+			sbl_dev_dbg(sbl->dev, "%d: pcs lock wait cancelled\n",
+				    port_num);
+			err = -ECANCELED;
+			goto out;
+		}
+
+		elapsed = jiffies_to_msecs(jiffies - start_jiffy);
+		if (elapsed > 1000) {
+
+			/* if we have a high serdes error, we will never align  */
+			if (sbl_pml_pcs_high_serdes_error(sbl, port_num)) {
+				sbl_dev_warn(sbl->dev, "%d: pcs lock high serdes error detected\n", port_num);
+				err = -EADV;
+				goto out;
+			}
+
+			/* Ensure the serdes is still good (eyes stay open)  */
+			err = sbl_port_check_eyes(sbl, port_num);
+			if (err) {
+				sbl_dev_warn(sbl->dev, "%d: pcs lock some eyes have gone bad", port_num);
+				goto out;
+			}
+
+			/* restart locking in case it's locked up */
+			sbl_pml_pcs_stop_lock(sbl, port_num);
+			sbl_pml_pcs_start_lock(sbl, port_num);
+
+			msleep(SBL_PML_PCS_ALIGN_SLOW_POLL_DELAY);
+		} else if (elapsed > 50)
+			msleep(100);
+		else
+			usleep_range(10000, 11000);
+	}
+
+	/* poll for lane alignment */
+	start_jiffy = jiffies;
+
+	while (!sbl_pml_pcs_aligned(sbl, port_num)) {
+
+		if (sbl_start_timeout(sbl, port_num)) {
+			sbl_dev_dbg(sbl->dev, "%d: pcs align wait timeout\n",
+				    port_num);
+			err = -ETIMEDOUT;
+			goto out;
+		}
+
+		if (sbl_base_link_start_cancelled(sbl, port_num)) {
+			sbl_dev_dbg(sbl->dev, "%d: pcs align wait cancelled\n",
+				    port_num);
+			err = -ECANCELED;
+			goto out;
+		}
+
+		/* if we lose lock restart trying to lock again  */
+		if (!sbl_pml_pcs_locked(sbl, port_num)) {
+			sbl_dev_warn(sbl->dev, "%d: pcs align - lost lock\n", port_num);
+			goto restart;
+		}
+
+		elapsed = jiffies_to_msecs(jiffies - start_jiffy);
+		if (elapsed > SBL_PML_PCS_ALIGN_TIMEOUT) {
+
+			/* we should have got alignment by now
+			 * give up, restart locking and try again
+			 */
+			sbl_pml_pcs_stop_lock(sbl, port_num);
+			sbl_pml_pcs_start_lock(sbl, port_num);
+			goto restart;
+		} else if (elapsed > 50)
+			msleep(100);
+		else
+			usleep_range(10000, 11000);
+	}
+
+out:
+	sbl_link_info_clear(sbl, port_num, SBL_LINK_INFO_PCS_A_WAIT);
+
+	return err;
+}
+
+static bool sbl_pml_pcs_no_faults(struct sbl_inst *sbl, int port_num)
+{
+	u32 base = SBL_PML_BASE(port_num);
+	u64 faults;
+	u64 val64;
+
+	val64 = sbl_read64(sbl, base | SBL_PML_STS_RX_PCS_OFFSET);
+	faults = SBL_PML_STS_RX_PCS_FAULT_GET(val64) | SBL_PML_STS_RX_PCS_LOCAL_FAULT_GET(val64);
+
+	return (faults == 0ULL);
+}
+
+/* wait for pcs faults to clear
+ *
+ * we wait for fault to stay clear as it is momentarily set sometimes
+ */
+static int sbl_pml_pcs_fault_clear_wait(struct sbl_inst *sbl, int port_num)
+{
+	unsigned long start_jiffy = jiffies;
+	int no_fault_count = 0;
+	int elapsed;
+	int err;
+
+	sbl_dev_dbg(sbl->dev, "%d: pml pcs fault clear wait\n", port_num);
+
+	sbl_link_info_set(sbl, port_num, SBL_LINK_INFO_PCS_F_WAIT);
+
+	while (true) {
+
+		/* check for timeout */
+		if (sbl_start_timeout(sbl, port_num)) {
+			sbl_dev_dbg(sbl->dev, "%d: pml fault clear wait timeout\n",
+				    port_num);
+			err = -ETIMEDOUT;
+			goto out;
+		}
+
+		if (sbl_base_link_start_cancelled(sbl, port_num)) {
+			sbl_dev_dbg(sbl->dev, "%d: pml fault clear wait cancelled\n",
+				    port_num);
+			err = -ECANCELED;
+			goto out;
+		}
+
+		/* check we are still aligned */
+		if (!sbl_pml_pcs_aligned(sbl, port_num)) {
+			sbl_dev_dbg(sbl->dev, "%d: pml fault clear wait lost alignment\n",
+				    port_num);
+			err = -ENOLCK;
+			goto out;
+		}
+
+		/* check for no fault
+		 * we need multiple good tests to be sure it is up
+		 */
+		if (sbl_pml_pcs_no_faults(sbl, port_num)) {
+			++no_fault_count;
+			if (no_fault_count == SBL_PML_REQUIRED_NO_FAULT_COUNT) {
+				/* done */
+				err = 0;
+				goto out;
+			} else {
+				/* poll fast and check again */
+				start_jiffy = jiffies;
+			}
+		} else
+			no_fault_count = 0;
+
+		/* wait with backoff */
+		elapsed = jiffies_to_msecs(jiffies - start_jiffy);
+		if (elapsed > 5000)
+			msleep(1000);
+		else if (elapsed > 100)
+			msleep(100);
+		else
+			usleep_range(10000, 11000);
+	}
+
+out:
+	sbl_link_info_clear(sbl, port_num, SBL_LINK_INFO_PCS_F_WAIT);
+
+	return err;
+}
+
+/* PCS configuration */
+static int sbl_pml_pcs_config(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	u32 base = SBL_PML_BASE(port_num);
+	u64 val64;
+	int err;
+	u64 en_lane_degrade_reg;
+
+	sbl_dev_dbg(sbl->dev, "%d: pcs config", port_num);
+
+	/* work out all the lane config and store in link db */
+	err = sbl_pml_pcs_determine_active_lanes(sbl, port_num);
+	if (err) {
+		sbl_dev_dbg(sbl->dev, "%d: pcs config lanes failed [%d]", port_num, err);
+		return err;
+	}
+
+	/* pcs must be off for setting  */
+	sbl_pml_pcs_stop(sbl, port_num);
+
+	/* clear out the previous active lanes and disable lock */
+	val64 = sbl_read64(sbl, base | SBL_PML_CFG_RX_PCS_OFFSET);
+	val64 = SBL_PML_CFG_RX_PCS_ACTIVE_LANES_UPDATE(val64, 0ULL);
+	val64 = SBL_PML_CFG_RX_PCS_ENABLE_LOCK_UPDATE(val64, 0ULL);
+	sbl_write64(sbl, base | SBL_PML_CFG_RX_PCS_OFFSET, val64);
+	sbl_read64(sbl, base | SBL_PML_CFG_RX_PCS_OFFSET);
+
+	/* rapid alignment is broken so disable */
+	val64 = sbl_read64(sbl, base | SBL_PML_DBG_PCS_OFFSET);
+	val64 = SBL_PML_DBG_PCS_ENABLE_RAPID_ALIGNMENT_UPDATE(val64, 0ULL);
+	sbl_write64(sbl, base | SBL_PML_DBG_PCS_OFFSET, val64);
+
+	/* pcs config */
+	val64 = sbl_read64(sbl, base | SBL_PML_CFG_PCS_OFFSET);
+	switch (link->link_mode) {
+	case SBL_LINK_MODE_BS_200G:
+		val64 = SBL_PML_CFG_PCS_PCS_MODE_UPDATE(val64, 0ULL);
+		break;
+	case SBL_LINK_MODE_BJ_100G:
+		val64 = SBL_PML_CFG_PCS_PCS_MODE_UPDATE(val64, 1ULL);
+		break;
+	case SBL_LINK_MODE_CD_100G:
+		val64 = SBL_PML_CFG_PCS_PCS_MODE_UPDATE(val64, 2ULL);
+		break;
+	case SBL_LINK_MODE_CD_50G:
+		val64 = SBL_PML_CFG_PCS_PCS_MODE_UPDATE(val64, 3ULL);
+		break;
+	default:
+		sbl_dev_dbg(sbl->dev, "%d: pcs link mode invalid (%d)", port_num, link->link_mode);
+		return -EBADRQC;
+	}
+	val64 = SBL_PML_CFG_PCS_ENABLE_AUTO_NEG_UPDATE(val64, 0ULL);
+	if ((link->blattr.options & SBL_OPT_LANE_DEGRADE) &&
+	    (link->link_mode == SBL_LINK_MODE_BS_200G))
+		val64 = SBL_PML_CFG_PCS_ENABLE_AUTO_LANE_DEGRADE_UPDATE(val64, 1ULL);
+	else
+		val64 = SBL_PML_CFG_PCS_ENABLE_AUTO_LANE_DEGRADE_UPDATE(val64, 0ULL);
+
+	sbl_write64(sbl, base | SBL_PML_CFG_PCS_OFFSET, val64);
+
+	/* pcs tx  */
+	val64 = sbl_read64(sbl, base | SBL_PML_CFG_TX_PCS_OFFSET);
+	val64 = SBL_PML_CFG_TX_PCS_ENABLE_CTL_OS_UPDATE(val64, 0ULL);
+	val64 = SBL_PML_CFG_TX_PCS_CDC_READY_LEVEL_UPDATE(val64,
+							  SBL_PML_CFG_TX_PCS_CDC_READY_LEVEL_DFLT);
+	val64 = SBL_PML_CFG_TX_PCS_GEARBOX_CREDITS_UPDATE(val64,
+							  SBL_PML_CFG_TX_PCS_GEARBOX_CREDITS_DFLT);
+	val64 = SBL_PML_CFG_TX_PCS_LANE_0_SOURCE_UPDATE(val64,
+		 sbl->switch_info->ports[port_num].serdes[0].tx_lane_source);
+	val64 = SBL_PML_CFG_TX_PCS_LANE_1_SOURCE_UPDATE(val64,
+		 sbl->switch_info->ports[port_num].serdes[1].tx_lane_source);
+	val64 = SBL_PML_CFG_TX_PCS_LANE_2_SOURCE_UPDATE(val64,
+		 sbl->switch_info->ports[port_num].serdes[2].tx_lane_source);
+	val64 = SBL_PML_CFG_TX_PCS_LANE_3_SOURCE_UPDATE(val64,
+		 sbl->switch_info->ports[port_num].serdes[3].tx_lane_source);
+	sbl_write64(sbl, base | SBL_PML_CFG_TX_PCS_OFFSET, val64);
+
+	/* pcs rx */
+	val64 = sbl_read64(sbl, base | SBL_PML_CFG_RX_PCS_OFFSET);
+	switch (link->blattr.fec_mode) {
+	case SBL_RS_MODE_OFF:
+		val64 = SBL_PML_CFG_RX_PCS_RS_MODE_UPDATE(val64, 0ULL);
+		break;
+	case SBL_RS_MODE_OFF_SYN:
+		val64 = SBL_PML_CFG_RX_PCS_RS_MODE_UPDATE(val64, 1ULL);
+		break;
+	case SBL_RS_MODE_OFF_CHK:
+		val64 = SBL_PML_CFG_RX_PCS_RS_MODE_UPDATE(val64, 2ULL);
+		break;
+	case SBL_RS_MODE_ON_SYN_MRK:
+		val64 = SBL_PML_CFG_RX_PCS_RS_MODE_UPDATE(val64, 3ULL);
+		break;
+	case SBL_RS_MODE_ON_CHK_SYN_MRK:
+		val64 = SBL_PML_CFG_RX_PCS_RS_MODE_UPDATE(val64, 4ULL);
+		break;
+	case SBL_RS_MODE_ON:
+		val64 = SBL_PML_CFG_RX_PCS_RS_MODE_UPDATE(val64, 5ULL);
+		break;
+	default:
+		sbl_dev_dbg(sbl->dev, "%d: pcs fec mode invalid (%d)", port_num, link->blattr.fec_mode);
+		return -EBADRQC;
+	}
+	val64 = SBL_PML_CFG_RX_PCS_ENABLE_CTL_OS_UPDATE(val64, 0ULL);                   /* ordered sets off */
+	val64 = SBL_PML_CFG_RX_PCS_HEALTH_BAD_SENSITIVITY_UPDATE(val64, 4ULL);          /* less sensitive */
+	val64 = SBL_PML_CFG_RX_PCS_ENABLE_RX_SM_UPDATE(val64,                           /* state machine */
+			(link->blattr.options & SBL_OPT_FABRIC_LINK) ? 0ULL : 1ULL);
+	en_lane_degrade_reg = sbl_read64(sbl, base | SBL_PML_CFG_PCS_OFFSET);
+	/* If we disable the following CSR, Auto Lane Degrade is enabled and
+	 * there is a concern regarding handling of short burst errors
+	 */
+	if (SBL_PML_CFG_PCS_ENABLE_AUTO_LANE_DEGRADE_GET(en_lane_degrade_reg))
+		val64 = SBL_PML_CFG_RX_PCS_RESTART_LOCK_ON_BAD_CWS_UPDATE(val64, 0ULL);     /* restart on 3 bad RS codewords - 0 with autodegrade enabled */
+	else
+		val64 = SBL_PML_CFG_RX_PCS_RESTART_LOCK_ON_BAD_CWS_UPDATE(val64, 1ULL);     /* restart on 3 bad RS codewords - 1 with autodegrade disabled */
+	val64 = SBL_PML_CFG_RX_PCS_RESTART_LOCK_ON_BAD_AMS_UPDATE(val64,                /* restart on 5 bad AMs */
+			(link->link_mode == SBL_LINK_MODE_BS_200G) ? 1ULL : 0ULL);
+	val64 = SBL_PML_CFG_RX_PCS_ACTIVE_LANES_UPDATE(val64, link->active_rx_lanes);
+	val64 = SBL_PML_CFG_RX_PCS_ENABLE_LOCK_UPDATE(val64, 0ULL);                     /* pcs disable lock  (really enable alignment process) */
+	sbl_write64(sbl, base | SBL_PML_CFG_RX_PCS_OFFSET, val64);
+
+	link->pcs_config = true;
+
+	return 0;
+}
+
+/* Enables auto lane degrading in the hardware.
+ *
+ * This function can also be called if the AM_LOCK is observed on some lanes
+ * but not all and the timeout has expired. This will allow auto lane degrade
+ * feature to be used when not all lanes are available at the initial link
+ * bringup.
+ */
+void sbl_pml_pcs_enable_auto_lane_degrade(struct sbl_inst *sbl, int port_num)
+{
+	u32 base = SBL_PML_BASE(port_num);
+	u64 val64, en_lane_degrade_reg;
+	unsigned long timeout;
+	int err = 0;
+
+	en_lane_degrade_reg = sbl_read64(sbl, base | SBL_PML_CFG_PCS_OFFSET);
+	if (SBL_PML_CFG_PCS_ENABLE_AUTO_LANE_DEGRADE_GET(en_lane_degrade_reg)) {
+		timeout = jiffies + usecs_to_jiffies(HM_TIMEOUT);
+		while (!sbl_pml_rx_pls_available(sbl, port_num)) {
+			if (time_after(jiffies, timeout)) {
+				sbl_dev_dbg(sbl->dev, "%d: timeout for rx pls available\n", port_num);
+				err = -ETIMEDOUT;
+				goto out;
+			}
+		}
+		timeout = jiffies + usecs_to_jiffies(HM_TIMEOUT);
+		while (!sbl_pml_lp_pls_available(sbl, port_num)) {
+			if (time_after(jiffies, timeout)) {
+				sbl_dev_dbg(sbl->dev, "%d: timeout for lp pls available\n", port_num);
+				err = -ETIMEDOUT;
+				goto out;
+			}
+		}
+
+		val64 = sbl_read64(sbl, base | SBL_PML_CFG_RX_PCS_OFFSET);
+		val64 = SBL_PML_CFG_RX_PCS_ALLOW_AUTO_DEGRADE_UPDATE(val64, 1ULL);
+		sbl_write64(sbl, base | SBL_PML_CFG_RX_PCS_OFFSET, val64);
+
+		val64 = sbl_read64(sbl, base | SBL_PML_CFG_TX_PCS_OFFSET);
+		val64 = SBL_PML_CFG_TX_PCS_ALLOW_AUTO_DEGRADE_UPDATE(val64, 1ULL);
+		sbl_write64(sbl, base | SBL_PML_CFG_TX_PCS_OFFSET, val64);
+		sbl_read64(sbl, base | SBL_PML_CFG_PCS_OFFSET); /* flush */
+		sbl_dev_dbg(sbl->dev, "auto lane degrade is enabled");
+	}
+out:
+	if (err) {
+		sbl_dev_err(sbl->dev, "%d: auto lane degrade is not enabled", port_num);
+		en_lane_degrade_reg = sbl_read64(sbl, base | SBL_PML_CFG_PCS_OFFSET);
+		en_lane_degrade_reg = SBL_PML_CFG_PCS_ENABLE_AUTO_LANE_DEGRADE_UPDATE(en_lane_degrade_reg, 0ULL);
+		sbl_write64(sbl, base | SBL_PML_CFG_PCS_OFFSET, en_lane_degrade_reg);
+
+		val64 = sbl_read64(sbl, base | SBL_PML_CFG_RX_PCS_OFFSET);
+		val64 = SBL_PML_CFG_RX_PCS_RESTART_LOCK_ON_BAD_CWS_UPDATE(val64, 1ULL);
+		sbl_write64(sbl, base | SBL_PML_CFG_RX_PCS_OFFSET, val64);
+		sbl_read64(sbl, base | SBL_PML_CFG_PCS_OFFSET); /* flush */
+		sbl_dev_dbg(sbl->dev, "Restart lock on bad CWS set back to 1 since couldn't enable ALD\n");
+	}
+}
+
+bool sbl_pml_rx_pls_available(struct sbl_inst *sbl, int port_num)
+{
+	u32 base = SBL_PML_BASE(port_num);
+	u64 val64;
+	u64 sts_pcs_lane_degrade_reg;
+
+	sts_pcs_lane_degrade_reg = sbl_read64(sbl, base | SBL_PML_STS_PCS_LANE_DEGRADE_OFFSET);
+	val64 = SBL_PML_STS_PCS_LANE_DEGRADE_RX_PLS_AVAILABLE_GET(sts_pcs_lane_degrade_reg);
+
+	return (val64 == MAX_PLS_AVAILABLE);
+}
+
+bool sbl_pml_lp_pls_available(struct sbl_inst *sbl, int port_num)
+{
+	u32 base = SBL_PML_BASE(port_num);
+	u64 val64;
+	u64 sts_pcs_lane_degrade_reg;
+
+	sts_pcs_lane_degrade_reg = sbl_read64(sbl, base | SBL_PML_STS_PCS_LANE_DEGRADE_OFFSET);
+	val64 = SBL_PML_STS_PCS_LANE_DEGRADE_LP_PLS_AVAILABLE_GET(sts_pcs_lane_degrade_reg);
+
+	return (val64 == MAX_PLS_AVAILABLE);
+}
+
+/* PCS start-up */
+void sbl_pml_pcs_start(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	u32 base = SBL_PML_BASE(port_num);
+	u64 val64;
+	u32 val32;
+
+	sbl_dev_dbg(sbl->dev, "%d: pcs start", port_num);
+
+	/* we need updated AMs for 200GHz mode */
+	val32 = SBL_PML_CFG_PCS_AMS_DFLT;
+	if (link->link_mode == SBL_LINK_MODE_BS_200G)
+		val32 = SBL_PML_CFG_PCS_AMS_USE_PROGRAMMABLE_AMS_UPDATE(
+				val32, 1ULL);
+	else
+		val32 = SBL_PML_CFG_PCS_AMS_USE_PROGRAMMABLE_AMS_UPDATE(
+				val32, 0ULL);
+	sbl_write32(sbl, base | SBL_PML_CFG_PCS_AMS_OFFSET, val32);
+
+	/* start pcs */
+	val64 = sbl_read64(sbl, base | SBL_PML_CFG_PCS_OFFSET);
+	val64 = SBL_PML_CFG_PCS_PCS_ENABLE_UPDATE(val64, 1ULL);
+	sbl_write64(sbl, base | SBL_PML_CFG_PCS_OFFSET, val64);
+	sbl_read64(sbl, base | SBL_PML_CFG_PCS_OFFSET); /* flush */
+
+	/* record if we are trying to align */
+	val64 = sbl_read64(sbl, base | SBL_PML_CFG_RX_PCS_OFFSET);
+	if (SBL_PML_CFG_RX_PCS_ENABLE_LOCK_GET(val64))
+		sbl_link_info_set(sbl, port_num, SBL_LINK_INFO_PCS_ALIGN_EN);
+	else
+		sbl_link_info_clear(sbl, port_num, SBL_LINK_INFO_PCS_ALIGN_EN);
+}
+
+void sbl_pml_pcs_enable_alignment(struct sbl_inst *sbl, int port_num)
+{
+	u32 base = SBL_PML_BASE(port_num);
+	u64 val64;
+
+	sbl_dev_dbg(sbl->dev, "%d: pcs enable alignment", port_num);
+
+	val64 = sbl_read64(sbl, base | SBL_PML_CFG_RX_PCS_OFFSET);
+	val64 = SBL_PML_CFG_RX_PCS_ENABLE_LOCK_UPDATE(val64, 1ULL);
+	sbl_write64(sbl, base | SBL_PML_CFG_RX_PCS_OFFSET, val64);
+
+	/* alignment process is underway */
+	sbl_link_info_set(sbl, port_num, SBL_LINK_INFO_PCS_ALIGN_EN);
+}
+
+void sbl_pml_pcs_disable_alignment(struct sbl_inst *sbl, int port_num)
+{
+	u32 base = SBL_PML_BASE(port_num);
+	u64 val64;
+
+	sbl_dev_dbg(sbl->dev, "%d: pcs disable alignment", port_num);
+
+	val64 = sbl_read64(sbl, base | SBL_PML_CFG_RX_PCS_OFFSET);
+	val64 = SBL_PML_CFG_RX_PCS_ENABLE_LOCK_UPDATE(val64, 0ULL);
+	sbl_write64(sbl, base | SBL_PML_CFG_RX_PCS_OFFSET, val64);
+
+	/* alignment process is stopped */
+	sbl_link_info_clear(sbl, port_num, SBL_LINK_INFO_PCS_ALIGN_EN);
+}
+
+/* remote fault.
+ *
+ * there is a debug reg we can use to send remote fault to our link partner
+ */
+void sbl_pml_pcs_set_tx_rf(struct sbl_inst *sbl, int port_num)
+{
+	u32 base = SBL_PML_BASE(port_num);
+	u64 val64;
+
+	sbl_dev_dbg(sbl->dev, "%d: pcs set tx rf", port_num);
+
+	val64 = sbl_read64(sbl, base | SBL_PML_DBG_PCS_OFFSET);
+	val64 = SBL_PML_DBG_PCS_FORCE_TX_DATA_UPDATE(val64, 1ULL);
+	val64 = SBL_PML_DBG_PCS_FORCE_TX_DATA_RF_UPDATE(val64, 1ULL);
+	sbl_write64(sbl, base | SBL_PML_DBG_PCS_OFFSET, val64);
+	sbl_read64(sbl, base | SBL_PML_DBG_PCS_OFFSET);
+
+	sbl_link_info_set(sbl, port_num, SBL_LINK_INFO_PCS_TX_RF);
+}
+
+void sbl_pml_pcs_clear_tx_rf(struct sbl_inst *sbl, int port_num)
+{
+	u32 base = SBL_PML_BASE(port_num);
+	u64 val64;
+
+	sbl_dev_dbg(sbl->dev, "%d: pcs clear tx rf", port_num);
+
+	val64 = sbl_read64(sbl, base | SBL_PML_DBG_PCS_OFFSET);
+	val64 = SBL_PML_DBG_PCS_FORCE_TX_DATA_UPDATE(val64, 0ULL);
+	val64 = SBL_PML_DBG_PCS_FORCE_TX_DATA_RF_UPDATE(val64, 0ULL);
+	sbl_write64(sbl, base | SBL_PML_DBG_PCS_OFFSET, val64);
+	sbl_read64(sbl, base | SBL_PML_DBG_PCS_OFFSET);
+
+	sbl_link_info_clear(sbl, port_num, SBL_LINK_INFO_PCS_TX_RF);
+}
+
+/*   wait for the pcs to come up
+ *
+ *   i.e for it to be locked and aligned and faults to have cleared
+ *
+ *
+ */
+int sbl_pml_pcs_wait(struct sbl_inst *sbl, int port_num)
+{
+	char pcs_state_str[SBL_PCS_STATE_STR_LEN];
+	int err;
+
+	sbl_dev_dbg(sbl->dev, "%d: pcs wait", port_num);
+
+	/* start locking */
+	sbl_pml_pcs_start_lock(sbl, port_num);
+
+	/* clear forcing remote fault.
+	 * (it will continue to be set until PCS is actually ready)
+	 */
+	sbl_pml_pcs_clear_tx_rf(sbl, port_num);
+
+	/* keep trying to bring the pcs up until we timeout */
+	while (true) {
+
+		/* wait for alignment */
+		err = sbl_pml_pcs_alignment_wait(sbl, port_num);
+		switch (err) {
+		case 0:
+			break;
+
+		case -ETIMEDOUT:
+			/* out of time, dump state and give up  */
+			sbl_dev_err(sbl->dev, "%d: pcs_wait alignment timeout (%s)\n", port_num,
+				    sbl_pml_pcs_state_str(sbl, port_num, pcs_state_str,
+							  SBL_PCS_STATE_STR_LEN));
+			goto out;
+
+		case -ECANCELED:
+			sbl_dev_dbg(sbl->dev, "%d: pcs_wait alignment failed [%d]\n", port_num, err);
+			goto out;
+
+		default:
+			/* something unexpected */
+			sbl_dev_err(sbl->dev, "%d: pcs_wait alignment failed [%d]\n", port_num, err);
+			goto out;
+		}
+
+		/* wait for faults to clear */
+		err = sbl_pml_pcs_fault_clear_wait(sbl, port_num);
+		switch (err) {
+
+		case 0:
+			goto out;
+
+		case -ENOLCK:
+			/* alignment lost - try to align again  */
+			sbl_dev_warn(sbl->dev, "%d: pcs_wait alignment lost - restart (%s)\n", port_num,
+				     sbl_pml_pcs_state_str(sbl, port_num, pcs_state_str,
+							   SBL_PCS_STATE_STR_LEN));
+			continue;
+
+		case -ETIMEDOUT:
+			sbl_dev_err(sbl->dev, "%d: pcs_wait fault clear timeout (%s)\n", port_num,
+				    sbl_pml_pcs_state_str(sbl, port_num, pcs_state_str,
+							  SBL_PCS_STATE_STR_LEN));
+			goto out;
+
+		case -ECANCELED:
+			sbl_dev_dbg(sbl->dev, "%d: pcs_wait fault clear cancelled\n", port_num);
+			goto out;
+
+		default:
+			/* something unexpected */
+			sbl_dev_err(sbl->dev, "%d: pcs_wait fault clear failed [%d]\n", port_num, err);
+			goto out;
+		}
+	}
+
+out:
+	/* drop all stage info */
+	sbl_link_info_clear(sbl, port_num, SBL_LINK_INFO_PCS_ALIGN_EN);
+	sbl_link_info_clear(sbl, port_num, SBL_LINK_INFO_PCS_A_WAIT);
+	sbl_link_info_clear(sbl, port_num, SBL_LINK_INFO_PCS_F_WAIT);
+
+	if (err)
+		return err;
+
+	/* clear all the PCS related error flags */
+	sbl_pml_err_flgs_clear(sbl, port_num, SBL_PML_ALL_PCS_ERR_FLGS);
+
+	/* note pcs is up */
+	sbl_link_info_clear(sbl, port_num, SBL_LINK_INFO_PCS_TX_AM);
+	sbl_link_info_set(sbl, port_num, SBL_LINK_INFO_PCS_UP);
+
+	return 0;
+}
+
+char *sbl_pml_pcs_state_str(struct sbl_inst *sbl, int port_num, char *buf, int len)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	u32 base = SBL_PML_BASE(port_num);
+	u64 val64;
+
+	if (!buf || !len)
+		return "";
+
+	val64 = sbl_read64(sbl, base | SBL_PML_STS_RX_PCS_OFFSET);
+	snprintf(buf, len, "lk %llx/%.2x, a%lld f%lld lf%lld hs%lld",
+		 SBL_PML_STS_RX_PCS_AM_LOCK_GET(val64),
+			link->active_fec_lanes,
+			SBL_PML_STS_RX_PCS_ALIGN_STATUS_GET(val64),
+			SBL_PML_STS_RX_PCS_FAULT_GET(val64),
+			SBL_PML_STS_RX_PCS_LOCAL_FAULT_GET(val64),
+			SBL_PML_STS_RX_PCS_HI_SER_GET(val64));
+	return buf;
+}
+
+/**
+ * sbl_pml_pcs_recovery_enable() - Enable PCS recovery
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ *
+ * Context: Process context, Acquires lock and release
+ * pcs_recovery_lock <spin_lock>
+ */
+void sbl_pml_pcs_recovery_enable(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link;
+
+	link = sbl->link + port_num;
+
+	sbl_dev_dbg(sbl->dev, "%d: PCS recovery enable", port_num);
+
+	spin_lock(&link->pcs_recovery_lock);
+	link->pcs_recovery_flag = true;
+	spin_unlock(&link->pcs_recovery_lock);
+}
+EXPORT_SYMBOL(sbl_pml_pcs_recovery_enable);
+
+/**
+ * sbl_pml_pcs_recovery_disable() - Disable PCS recovery
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ *
+ * Context: Process context, Acquires lock and release
+ * pcs_recovery_lock <spin_lock>
+ */
+void sbl_pml_pcs_recovery_disable(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link;
+
+	link = sbl->link + port_num;
+
+	sbl_dev_dbg(sbl->dev, "%d: PCS recovery disable", port_num);
+
+	spin_lock(&link->pcs_recovery_lock);
+	link->pcs_recovery_flag = false;
+	spin_unlock(&link->pcs_recovery_lock);
+}
+EXPORT_SYMBOL(sbl_pml_pcs_recovery_disable);
+
+/**
+ * sbl_pml_pcs_aligned() - Check pcs align status
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ *
+ * Return: status of pcs align
+ */
+bool sbl_pml_pcs_aligned(struct sbl_inst *sbl, int port_num)
+{
+	u32 base = SBL_PML_BASE(port_num);
+	u64 val64;
+
+	val64 = sbl_read64(sbl, base | SBL_PML_STS_RX_PCS_OFFSET);
+
+	return (SBL_PML_STS_RX_PCS_ALIGN_STATUS_GET(val64) == 1);
+}
+EXPORT_SYMBOL(sbl_pml_pcs_aligned);
+
+bool sbl_pml_pcs_high_serdes_error(struct sbl_inst *sbl, int port_num)
+{
+	u32 base = SBL_PML_BASE(port_num);
+	u64 val64;
+
+	val64 = sbl_read64(sbl, base | SBL_PML_STS_RX_PCS_OFFSET);
+	return SBL_PML_STS_RX_PCS_HI_SER_GET(val64);
+}
+
+bool sbl_pml_pcs_up(struct sbl_inst *sbl, int port_num)
+{
+	u32 base = SBL_PML_BASE(port_num);
+	u64 val64;
+
+	if (!sbl->is_hw)
+		return true;
+
+	val64 = sbl_read64(sbl, base | SBL_PML_STS_RX_PCS_OFFSET);
+
+	return SBL_PML_STS_RX_PCS_ALIGN_STATUS_GET(val64) &&
+			!SBL_PML_STS_RX_PCS_FAULT_GET(val64) &&
+			!SBL_PML_STS_RX_PCS_LOCAL_FAULT_GET(val64) &&
+			!SBL_PML_STS_RX_PCS_HI_SER_GET(val64);
+}
+
+bool sbl_pml_recovery_no_faults(struct sbl_inst *sbl, int port_num)
+{
+	u32 base = SBL_PML_BASE(port_num);
+	struct sbl_link *link = sbl->link + port_num;
+	u64 val64;
+
+	val64 = sbl_read64(sbl, base | SBL_PML_STS_RX_PCS_OFFSET);
+
+	sbl_dev_dbg(sbl->dev, "%d:sbl_pml_recovery fault info val=0x%llx aml=0x%llx fecl:0x%x",
+		    port_num, val64, SBL_PML_STS_RX_PCS_AM_LOCK_GET(val64), link->active_fec_lanes);
+
+	return SBL_PML_STS_RX_PCS_ALIGN_STATUS_GET(val64) &&
+			!SBL_PML_STS_RX_PCS_FAULT_GET(val64) &&
+			!SBL_PML_STS_RX_PCS_LOCAL_FAULT_GET(val64) &&
+			!SBL_PML_STS_RX_PCS_HI_SER_GET(val64) &&
+			(SBL_PML_STS_RX_PCS_AM_LOCK_GET(val64) == link->active_fec_lanes);
+}
+
+void sbl_pml_recovery_log_pcs_status(struct sbl_inst *sbl, int port_num)
+{
+	u32 base = SBL_PML_BASE(port_num);
+	u64 val64;
+
+	val64 = sbl_read64(sbl, base | SBL_PML_STS_RX_PCS_DESKEW_DEPTHS_OFFSET);
+	sbl_dev_info(sbl->dev, "%d: SBL_PML_STS_RX_PCS_DESKEW_DEPTHS_OFFSET = 0x%llx",
+		     port_num, val64);
+
+	val64 = sbl_read64(sbl, base | SBL_PML_STS_RX_PCS_AM_MATCH_OFFSET);
+	sbl_dev_info(sbl->dev, "%d: SBL_PML_STS_RX_PCS_AM_MATCH_OFFSET = 0x%llx",
+		     port_num, val64);
+
+	val64 = sbl_read64(sbl, base | SBL_PML_STS_RX_PCS_FECL_SOURCES_OFFSET);
+	sbl_dev_info(sbl->dev, "%d: SBL_PML_STS_RX_PCS_FECL_SOURCES_OFFSET = 0x%llx",
+		     port_num, val64);
+}
+
+/* stop the pcs */
+void sbl_pml_pcs_stop(struct sbl_inst *sbl, int port_num)
+{
+	u32 base = SBL_PML_BASE(port_num);
+	struct sbl_link *link = sbl->link + port_num;
+	u64 val64;
+
+	if (sbl_debug_option(sbl, port_num, SBL_DEBUG_KEEP_SERDES_UP)) {
+		sbl_dev_err(sbl->dev, "%d: KEEP SERDES UP", port_num);
+		return;
+	}
+
+	sbl_dev_dbg(sbl->dev, "%d: pml pcs stop\n", port_num);
+
+	if ((link->sstate != SBL_SERDES_STATUS_DOWN) &&
+	    (link->mattr.media == SBL_LINK_MEDIA_OPTICAL)) {
+		sbl_dev_err(sbl->dev, "%d: not stopping pcs because serdes is running",
+			    port_num);
+		return;
+	}
+
+	val64 = sbl_read64(sbl, base | SBL_PML_CFG_PCS_OFFSET);
+	val64 = SBL_PML_CFG_PCS_PCS_ENABLE_UPDATE(val64, 0ULL);
+	sbl_write64(sbl, base | SBL_PML_CFG_PCS_OFFSET, val64);
+	sbl_read64(sbl, base | SBL_PML_CFG_PCS_OFFSET); /* flush */
+
+	sbl_link_info_clear(sbl, port_num, SBL_LINK_INFO_PCS_TX_AM);
+	sbl_link_info_clear(sbl, port_num, SBL_LINK_INFO_PCS_ALIGN_EN);
+	sbl_link_info_clear(sbl, port_num, SBL_LINK_INFO_PCS_A_WAIT);
+	sbl_link_info_clear(sbl, port_num, SBL_LINK_INFO_PCS_F_WAIT);
+	sbl_link_info_clear(sbl, port_num, SBL_LINK_INFO_PCS_UP);
+}
+
+/* enable/disable pcs sending ordered sets */
+void sbl_pml_pcs_ordered_sets(struct sbl_inst *sbl,
+			      int port_num, int enable)
+{
+	u32 base = SBL_PML_BASE(port_num);
+	u64 val64;
+	u64 state = (enable) ? 1ULL : 0ULL;
+
+	sbl_dev_dbg(sbl->dev, "%d: pml pcs ordered sets - %s\n", port_num,
+		    (enable) ? "start" : "stop");
+
+	val64 = sbl_read64(sbl, base | SBL_PML_CFG_RX_PCS_OFFSET);
+	val64 = SBL_PML_CFG_RX_PCS_ENABLE_CTL_OS_UPDATE(val64, state);
+	sbl_write64(sbl, base | SBL_PML_CFG_RX_PCS_OFFSET, val64);
+
+	val64 = sbl_read64(sbl, base | SBL_PML_CFG_TX_PCS_OFFSET);
+	val64 = SBL_PML_CFG_TX_PCS_ENABLE_CTL_OS_UPDATE(val64, state);
+	sbl_write64(sbl, base | SBL_PML_CFG_TX_PCS_OFFSET, val64);
+
+	/* pci flush */
+	sbl_read64(sbl, base | SBL_PML_CFG_PCS_OFFSET);
+
+	if (enable)
+		sbl_link_info_set(sbl, port_num, SBL_LINK_INFO_OS);
+	else
+		sbl_link_info_clear(sbl, port_num, SBL_LINK_INFO_OS);
+}
+
+/*   Start/Stop sending am.
+ *
+ *   Start: configures and starts the PCS and then immediately disables the alignment
+ *   locking process
+ *
+ *   Stop: just switched off the PCS
+ */
+int  sbl_pml_pcs_am_start(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link;
+	int err;
+
+	err = sbl_validate_instance(sbl);
+	if (err)
+		return err;
+
+	err = sbl_validate_port_num(sbl, port_num);
+	if (err)
+		return err;
+
+	link = sbl->link + port_num;
+
+	if (!(link->blstate & (SBL_BASE_LINK_STATUS_STARTING | SBL_BASE_LINK_STATUS_STARTING))) {
+		sbl_dev_err(sbl->dev, "pcs_am_start %d: wrong state (%s)\n", port_num,
+			    sbl_link_state_str(link->blstate));
+		return -ENAVAIL;
+	}
+
+	/* configuring will stop the pcs
+	 * this might perturb link partner when tuning so report we do this
+	 */
+	if (READ_ONCE(link->link_info) & SBL_LINK_INFO_PCS_TX_AM)
+		sbl_dev_dbg(sbl->dev, "%d pcs_am_start: tx am restart\n", port_num);
+
+	err = sbl_pml_pcs_config(sbl, port_num);
+	if (err) {
+		sbl_dev_err(sbl->dev, "pcs_config %d: failed [%d]\n", port_num, err);
+		return err;
+	}
+
+	/* send remote fault to the link partner */
+	sbl_pml_pcs_set_tx_rf(sbl, port_num);
+
+	/* start the pcs - which will start it sending AM */
+	sbl_pml_pcs_start(sbl, port_num);
+
+	/* if pcs is running it will be sending AMs */
+	sbl_link_info_set(sbl, port_num, SBL_LINK_INFO_PCS_TX_AM);
+
+	/* but definitely not doing any of this yet */
+	sbl_link_info_clear(sbl, port_num, SBL_LINK_INFO_PCS_ANEG);
+	sbl_link_info_clear(sbl, port_num, SBL_LINK_INFO_PCS_A_WAIT);
+	sbl_link_info_clear(sbl, port_num, SBL_LINK_INFO_PCS_F_WAIT);
+	sbl_link_info_clear(sbl, port_num, SBL_LINK_INFO_PCS_UP);
+
+	return 0;
+}
+
+#ifdef CONFIG_SYSFS
+/**
+ * sbl_pml_pcs_sysfs_sprint() - Format serdes info into buffer
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ * @buf: Destination buffer to write the data
+ * @size: Size of @buf in bytes, the output is truncated to fit
+ *
+ * This function checks the pcs_config flag and based on that
+ * it will format serdes info string into buffer.
+ *
+ * Context: Process context, Acquires lock and release
+ * link->lock <spin_lock>
+ *
+ * Return: Number of characters written, at most @size - 1
+ */
+int sbl_pml_pcs_sysfs_sprint(struct sbl_inst *sbl, int port_num, char *buf, size_t size)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	char state_str[SBL_PCS_STATE_STR_LEN];
+	int s = 0;
+
+	spin_lock(&link->lock);
+	if (link->pcs_config) {
+		s += scnprintf(buf + s, size - s, "pcs:  %s (%d %d %d %d) rx %x %s\n",
+				sbl_link_mode_str(link->link_mode),
+				sbl->switch_info->ports[port_num].serdes[0].tx_lane_source,
+				sbl->switch_info->ports[port_num].serdes[1].tx_lane_source,
+				sbl->switch_info->ports[port_num].serdes[2].tx_lane_source,
+				sbl->switch_info->ports[port_num].serdes[3].tx_lane_source,
+				link->active_rx_lanes,
+				sbl_pml_pcs_state_str(sbl, port_num, state_str, SBL_PCS_STATE_STR_LEN));
+	}
+	spin_unlock(&link->lock);
+
+	return s;
+}
+EXPORT_SYMBOL(sbl_pml_pcs_sysfs_sprint);
+
+/**
+ * sbl_pml_pcs_lane_degrade_sysfs_sprint() - Formats PCS ALD,TX/RX lane degrade into buffer
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ * @buf: Destination buffer to write the data
+ * @size: Size of @buf in bytes, the output is truncated to fit
+ *
+ * This function formats PCS ALD/(TX/RX) lane degrade string into buffer
+ * based on the flag 'pcs_config'.
+ *
+ * Context: Process context, Acquires lock and release
+ * link->lock <spin_lock>
+ *
+ * Return: Number of characters written, at most @size - 1
+ */
+int sbl_pml_pcs_lane_degrade_sysfs_sprint(struct sbl_inst *sbl, int port_num, char *buf, size_t size)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	int s = 0;
+	u32 base = SBL_PML_BASE(port_num);
+	u64 sts_pcs_lane_degrade_reg = sbl_read64(sbl, base | SBL_PML_STS_PCS_LANE_DEGRADE_OFFSET);
+	u64 cfg_pcs_reg = sbl_read64(sbl, base | SBL_PML_CFG_PCS_OFFSET);
+
+	spin_lock(&link->lock);
+	if (link->pcs_config) {
+		s += scnprintf(buf + s, size - s, "ALD: %lld - TX: 0x%llx - RX: 0x%llx\n",
+				SBL_PML_CFG_PCS_ENABLE_AUTO_LANE_DEGRADE_GET(cfg_pcs_reg),
+				SBL_PML_STS_PCS_LANE_DEGRADE_LP_PLS_AVAILABLE_GET(sts_pcs_lane_degrade_reg),
+				SBL_PML_STS_PCS_LANE_DEGRADE_RX_PLS_AVAILABLE_GET(sts_pcs_lane_degrade_reg));
+	}
+	spin_unlock(&link->lock);
+
+	return s;
+}
+EXPORT_SYMBOL(sbl_pml_pcs_lane_degrade_sysfs_sprint);
+#endif
diff --git a/drivers/net/ethernet/hpe/sbl/sbl_pml_pcs_nic.c b/drivers/net/ethernet/hpe/sbl/sbl_pml_pcs_nic.c
new file mode 100644
index 000000000000..220039733053
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sbl/sbl_pml_pcs_nic.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/sched.h>
+
+#include <linux/hpe/sbl/sbl.h>
+#include <linux/hpe/sbl/sbl_kconfig.h>
+
+#include <linux/hpe/sbl/sbl_pml.h>
+
+#include "sbl_pml_fn.h"
+#include "sbl_link.h"
+#include "sbl_serdes_map.h"
+#include "sbl_internal.h"
+#include "sbl_serdes_fn.h"
+
+#ifdef CONFIG_SYSFS
+/**
+ * sbl_pml_pcs_speed_sysfs_sprint() - Report PCS mode into buffer
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ * @buf: Destination buffer to write the data
+ * @size: Size of @buf in bytes, the output is truncated to fit
+ *
+ * Based on PCS config, this function writes the link mode into
+ * the provided buffer
+ *
+ * Context: Process context, Acquires lock and release link->lock <spin_lock>
+ *
+ * Return: Number of characters written, at most @size - 1
+ */
+int sbl_pml_pcs_speed_sysfs_sprint(struct sbl_inst *sbl, int port_num, char *buf, size_t size)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	int s = 0;
+
+	spin_lock(&link->lock);
+	if (link->pcs_config)
+		s += scnprintf(buf + s, size - s, "%s", sbl_link_mode_str(link->link_mode));
+	else
+		s += scnprintf(buf + s, size - s, "NA");
+	spin_unlock(&link->lock);
+
+	return s;
+}
+EXPORT_SYMBOL(sbl_pml_pcs_speed_sysfs_sprint);
+#endif
diff --git a/drivers/net/ethernet/hpe/sbl/sbl_pml_serdes_op.c b/drivers/net/ethernet/hpe/sbl/sbl_pml_serdes_op.c
new file mode 100644
index 000000000000..4ade8b13b398
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sbl/sbl_pml_serdes_op.c
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2019-2023,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+
+#include <linux/hpe/sbl/sbl.h>
+#include <linux/hpe/sbl/sbl_kconfig.h>
+
+#include <linux/hpe/sbl/sbl_pml.h>
+
+#include "sbl_serdes.h"
+#include "sbl_internal.h"
+
+static inline bool sbl_pml_serdes_op_busy(struct sbl_inst *sbl, int port_num)
+{
+	u64 val64;
+
+	val64 = sbl_read64(sbl, SBL_PML_BASE(port_num) |
+			SBL_PML_SERDES_CORE_INTERRUPT_OFFSET);
+	return SBL_PML_SERDES_CORE_INTERRUPT_DO_CORE_INTERRUPT_GET(val64);
+}
+
+/**
+ * sbl_pml_serdes_op() - Perform a serdes interrupt configuration
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ * @serdes_sel: Value
+ * @op: Read serdes version
+ * @data: Set to zero
+ * @result: Pass this value to caller
+ * @timeout: Time set used for polling
+ * @flags: Used to set US/MSec delay
+ *
+ * This function validates the instance and port number, picks
+ * polling interval from the provided flags and executes SERDES
+ * core interrupt configuration. It polls the completion or timeout
+ * for this operation and returns success or negative on failure
+ *
+ * Context: May sleep based on access to serdes
+ *
+ * Return: 0 on success, negative error code on failure
+ */
+int sbl_pml_serdes_op(struct sbl_inst *sbl, int port_num, u64 serdes_sel,
+		      u64 op, u64 data, u16 *result, int timeout,
+		      unsigned int flags)
+{
+	struct sbl_link *link;
+	u32 base = SBL_PML_BASE(port_num);
+	u64 val64;
+	int delay;
+	int poll_interval;
+	unsigned long last_jiffy;
+	int err;
+
+	err = sbl_validate_instance(sbl);
+	if (err)
+		return err;
+
+	err = sbl_validate_port_num(sbl, port_num);
+	if (err)
+		return err;
+
+	sbl_dev_dbg(sbl->dev, "serdes op, p%ds%lld, %lld, %lld, %d 0x%x\n",
+		    port_num, serdes_sel, op, data, timeout, flags);
+
+	if (!result)
+		return -EINVAL;
+
+	/* cannot wait infinitely */
+	if (timeout <= 0)
+		return -EINVAL;
+
+	/* a polling interval is mandatory */
+	poll_interval = sbl_flags_get_poll_interval_from_flags(flags);
+	if (!poll_interval)
+		return -EINVAL;
+
+	delay = sbl_flags_get_delay_from_flags(flags);
+
+	link = sbl->link + port_num;
+	err = mutex_lock_interruptible(&link->serdes_mtx);
+	if (err)
+		return -ERESTARTSYS;
+
+	if (sbl_pml_serdes_op_busy(sbl, port_num)) {
+		mutex_unlock(&link->serdes_mtx);
+		return -EBUSY;
+	}
+
+	/* start the operation  */
+	val64 = SBL_PML_SERDES_CORE_INTERRUPT_SET(serdes_sel, 1ULL, op, data);
+	sbl_write64(sbl, base | SBL_PML_SERDES_CORE_INTERRUPT_OFFSET, val64);
+	sbl_read64(sbl, base | SBL_PML_SERDES_CORE_INTERRUPT_OFFSET); /* flush */
+
+	if (delay)
+		udelay(delay);
+
+	/* poll for completion or timeout */
+	last_jiffy = jiffies + msecs_to_jiffies(timeout) + 1;
+	while (sbl_pml_serdes_op_busy(sbl, port_num)) {
+		if (time_is_before_jiffies(last_jiffy)) {
+			mutex_unlock(&link->serdes_mtx);
+			return -ETIMEDOUT;
+		}
+		msleep(poll_interval);
+	}
+
+	/* get the result */
+	val64 = sbl_read64(sbl, base | SBL_PML_SERDES_CORE_INTERRUPT_OFFSET);
+	*result = SBL_PML_SERDES_CORE_INTERRUPT_CORE_INTERRUPT_DATA_GET(val64);
+
+	mutex_unlock(&link->serdes_mtx);
+	return 0;
+}
+EXPORT_SYMBOL(sbl_pml_serdes_op);
+
+/**
+ * sbl_pml_serdes_op_timing() - serdes core interrupt access timings
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ * @capture: Value to capture the interrupt delay
+ * @clear: Value to clear interrupt delay
+ * @set: Value to set interrupt delay
+ *
+ * Return: 0 on success
+ */
+int sbl_pml_serdes_op_timing(struct sbl_inst *sbl, int port_num, u64 capture,
+			     u64 clear, u64 set)
+{
+	u32 base = SBL_PML_BASE(port_num);
+	u64 val64;
+
+	val64 = SBL_PML_CFG_SERDES_CORE_INTERRUPT_CAPTURE_INTERRUPT_DATA_DELAY_SET(capture) |
+		SBL_PML_CFG_SERDES_CORE_INTERRUPT_CLEAR_INTERRUPT_DELAY_SET(clear) |
+		SBL_PML_CFG_SERDES_CORE_INTERRUPT_SET_INTERRUPT_DELAY_SET(set);
+
+	sbl_write64(sbl, base | SBL_PML_CFG_SERDES_CORE_INTERRUPT_OFFSET,
+		    val64);
+	return 0;
+}
+EXPORT_SYMBOL(sbl_pml_serdes_op_timing);

-- 
2.56.0


^ permalink raw reply	[flat|nested] 25+ messages in thread
* [PATCH 06/23] net: hpe: sbl: add link state management
  2026-10-30 20:58 [PATCH 00/23] Subject: [PATCH net-next 00/23] net/hpe: add HPE Slingshot NIC drivers Doug Ledford
                   ` (4 preceding siblings ...)
  2026-10-30 20:59 ` [PATCH 05/23] net: hpe: sbl: add the PML link layer Doug Ledford
@ 2026-10-30 20:59 ` Doug Ledford
  2026-10-30 20:59 ` [PATCH 07/23] net: hpe: sbl: add the SBM serial bus layer Doug Ledford
                   ` (17 subsequent siblings)
  23 siblings, 0 replies; 25+ messages in thread
From: Doug Ledford @ 2026-10-30 20:59 UTC (permalink / raw)
  To: Slingshot Open Source Team, Nathan Chancellor, Nicolas Schier,
	Richard Cochran, Andrew Lunn, David S. Miller, Eric Dumazet,
	Jakub Kicinski, Paolo Abeni, Sumit Semwal, Christian König,
	Guenter Roeck
  Cc: linux-kernel, netdev, linux-kbuild, Doug Ledford, Mamila Santosh

Add the link state machine: bring-up, auto-negotiation and the NIC
specific link ops.  This ties the PML and SerDes layers together and
is what the NIC driver calls to take a link up or down.

checkpatch --strict (100 columns) still reports the following in this
patch. They need coordination with the internal repositories this code
is maintained in and will be fixed in V2:
- WARNING: LONG_LINE (22), LONG_LINE_COMMENT (2)
- CHECK: BRACES (22), UNNECESSARY_PARENTHESES (8), COMPARISON_TO_NULL
  (1)

Co-developed-by: Mamila Santosh <santosh-kumar.mamila@hpe.com>
Signed-off-by: Mamila Santosh <santosh-kumar.mamila@hpe.com>
Signed-off-by: Doug Ledford <doug.ledford@hpe.com>
---
 drivers/net/ethernet/hpe/sbl/sbl_link.c        | 1739 ++++++++++++++++++++++++
 drivers/net/ethernet/hpe/sbl/sbl_link_an.c     | 1010 ++++++++++++++
 drivers/net/ethernet/hpe/sbl/sbl_link_an_nic.c |  111 ++
 drivers/net/ethernet/hpe/sbl/sbl_link_nic.c    |  196 +++
 4 files changed, 3056 insertions(+)

diff --git a/drivers/net/ethernet/hpe/sbl/sbl_link.c b/drivers/net/ethernet/hpe/sbl/sbl_link.c
new file mode 100644
index 000000000000..706fa9ba9676
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sbl/sbl_link.c
@@ -0,0 +1,1739 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* Copyright 2019-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/bitops.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+
+#include <linux/hpe/sbl/sbl.h>
+#include <linux/hpe/sbl/sbl_an.h>
+#include <linux/hpe/sbl/sbl_fec.h>
+#include <linux/hpe/sbl/sbl_kconfig.h>
+
+#include <linux/hpe/sbl/sbl_pml.h>
+
+#include "sbl_serdes_map.h"
+#include "sbl_pml_fn.h"
+#include "sbl_link.h"
+#include "sbl_serdes.h"
+#include "sbl_serdes_fn.h"
+#include "sbl_internal.h"
+
+/* detect the presence of our link partner */
+static int sbl_base_link_lp_detect(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	int err = 0;
+
+	/* already detected - probably from autoneg */
+	if (link->lp_detected)
+		return 0;
+
+	sbl_link_info_set(sbl, port_num, SBL_LINK_INFO_LP_DET);
+
+	/* currently we have only one way to do this */
+	if (link->blattr.options & SBL_OPT_SERDES_LPD) {
+		err =  sbl_serdes_lp_detect(sbl, port_num);
+		if (!err)
+			link->lp_detected = true;
+	}
+
+	sbl_link_info_clear(sbl, port_num, SBL_LINK_INFO_LP_DET);
+
+	return err;
+}
+
+/* Check/recover SBL FW */
+static int sbl_base_link_check_fix_fw(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	int serdes;
+	int err;
+
+	for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+		err = sbl_validate_serdes_fw_crc(sbl, port_num, serdes);
+		if (err) {
+			/* Any lane with corrputed FW will cause all lanes for
+			 * the port to be reloaded.
+			 */
+			goto reload_fw;
+		}
+	}
+	return 0;
+
+ reload_fw:
+	err = sbl_serdes_firmware_flash_safe(sbl, port_num, false);
+	if (err) {
+		/* All we can do is report failure here */
+		sbl_dev_err(sbl->dev, "%d: check/fix: fw flash failed [%d]\n",
+			    port_num, err);
+		link->sstate = SBL_SERDES_STATUS_ERROR;
+	}
+	return err;
+}
+
+static int sbl_link_get_mode_electrical(struct sbl_inst *sbl, int port_num)
+{
+	sbl_dev_dbg(sbl->dev, "bl %d: elec get mode", port_num);
+
+	return sbl_link_autoneg(sbl, port_num);
+}
+
+/* For now we will just use the configured speed */
+static int sbl_link_get_mode_optical(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+
+	sbl_dev_dbg(sbl->dev, "bl %d: optical link - fixing speed to config value (%s)\n",
+		    port_num, sbl_link_mode_str(link->blattr.link_mode));
+	link->link_mode = link->blattr.link_mode;
+
+	return 0;
+}
+
+/* determine the link mode (speed) */
+static int sbl_base_link_get_mode(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	int err = 0;
+
+	/* determine required mode */
+	if (link->loopback_mode == SBL_LOOPBACK_MODE_LOCAL) {
+		/* directly use the mode specified - no media check */
+		link->link_mode = link->blattr.link_mode;
+		return 0;
+	}
+
+	switch (link->mattr.media) {
+
+	case SBL_LINK_MEDIA_ELECTRICAL:
+		err = sbl_link_get_mode_electrical(sbl, port_num);
+		break;
+
+	case SBL_LINK_MEDIA_OPTICAL:
+		err = sbl_link_get_mode_optical(sbl, port_num);
+		break;
+
+	default:
+		sbl_dev_err(sbl->dev, "bl %d: bad media to determine mode", port_num);
+		err = -ENOMEDIUM;
+		break;
+	}
+	if (err)
+		return err;
+
+	/* ensure the media supports the required mode */
+	if (!sbl_media_check_mode_supported(sbl, port_num, link->link_mode)) {
+		sbl_dev_err(sbl->dev, "bl %d: config mode (%s) not supported by media",
+			    port_num, sbl_link_mode_str(link->blattr.link_mode));
+		return -EMEDIUMTYPE;
+	} else
+		return 0;
+}
+
+/* return true if get_mode failed because autoneg timed out */
+static bool sbl_base_link_an_timed_out(struct sbl_inst *sbl, int port_num, int err)
+{
+	struct sbl_link *link = sbl->link + port_num;
+
+	if (err != -ETIME)
+		return false;
+
+	if (link->mattr.media != SBL_LINK_MEDIA_ELECTRICAL)
+		return false;
+
+	if (link->blattr.pec.an_mode == SBL_AN_MODE_OFF)
+		return false;
+
+	return true;
+}
+
+static int sbl_link_fault_monitor_start(struct sbl_inst *sbl, int port_num)
+{
+	int err;
+	u32 base = SBL_PML_BASE(port_num);
+	u64 val64;
+	u64 err_flags;
+
+	val64 = sbl_read64(sbl, base | SBL_PML_CFG_LLR_SM_OFFSET);
+	if (SBL_PML_CFG_LLR_SM_REPLAY_CT_MAX_GET(val64) < SBL_LLR_REPLAY_CT_MAX_UNLIMITED)
+		err_flags = SBL_PML_FAULT_ERR_FLAGS;
+	else
+		err_flags = SBL_PML_REC_FAULT_ERR_FLAGS;
+
+	/* make sure we have not already had an error */
+	if (sbl_pml_err_flgs_test(sbl, port_num, err_flags)) {
+		sbl_dev_err(sbl->dev, "fm %d: start - errors already present\n",
+			    port_num);
+		err = -ENETDOWN;
+		goto out;
+	}
+
+	sbl_pml_recovery_enable(sbl, port_num);
+
+	err = sbl_pml_install_intr_handler(sbl, port_num, err_flags);
+	if (err) {
+		sbl_dev_err(sbl->dev, "fm %d: intr install failed [%d]\n", port_num, err);
+		goto out;
+	}
+
+	err = sbl_pml_enable_intr_handler(sbl, port_num, err_flags);
+	if (err) {
+		sbl_dev_err(sbl->dev, "fm %d: intr enable failed [%d]\n", port_num, err);
+		goto out_uninstall;
+		return err;
+	}
+
+	if (sbl_pml_err_flgs_test(sbl, port_num, err_flags)) {
+		sbl_dev_err(sbl->dev, "fm %d: link down during start\n", port_num);
+		err = -ENETDOWN;
+		goto out_disable;
+	} else {
+		/* all up and running */
+		sbl_link_info_set(sbl, port_num, SBL_LINK_INFO_FAULT_MON);
+	}
+	return 0;
+
+out_disable:
+	sbl_pml_disable_intr_handler(sbl, port_num, err_flags);
+out_uninstall:
+	sbl_pml_remove_intr_handler(sbl, port_num);
+out:
+	sbl_link_info_clear(sbl, port_num, SBL_LINK_INFO_FAULT_MON);
+
+	return err;
+}
+
+static int sbl_link_fault_monitor_stop(struct sbl_inst *sbl, int port_num)
+{
+	int err;
+	u32 base = SBL_PML_BASE(port_num);
+	u64 val64;
+	u64 err_flags;
+
+	val64 = sbl_read64(sbl, base | SBL_PML_CFG_LLR_SM_OFFSET);
+	if (SBL_PML_CFG_LLR_SM_REPLAY_CT_MAX_GET(val64) < SBL_LLR_REPLAY_CT_MAX_UNLIMITED)
+		err_flags = SBL_PML_FAULT_ERR_FLAGS;
+	else
+		err_flags = SBL_PML_REC_FAULT_ERR_FLAGS;
+
+	err = sbl_pml_disable_intr_handler(sbl, port_num, err_flags);
+	if (err) {
+		sbl_dev_err(sbl->dev, "fm %d: intr disable failed [%d]\n", port_num, err);
+		return err;
+	}
+
+	err = sbl_pml_remove_intr_handler(sbl, port_num);
+	if (err) {
+		sbl_dev_err(sbl->dev, "fm %d: intr remove failed [%d]\n", port_num, err);
+		return err;
+	}
+
+	sbl_link_info_clear(sbl, port_num, SBL_LINK_INFO_FAULT_MON);
+	return 0;
+}
+
+static void sbl_base_link_report_err(struct sbl_inst *sbl, char *txt, int port_num, int err)
+{
+	switch (err) {
+	case -ECANCELED:
+		sbl_dev_dbg(sbl->dev, "bl %d: %s cancelled\n", port_num, txt);
+		break;
+	case -ETIMEDOUT:
+		sbl_dev_dbg(sbl->dev, "bl %d: %s timed out\n", port_num, txt);
+		break;
+	default:
+		sbl_dev_err(sbl->dev, "bl %d: %s failed [%d]\n", port_num, txt, err);
+	}
+}
+
+/**
+ * sbl_get_lp_subtype() - Get link partner sub type
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ * @lp_subtype: Value to get Link partner subtype
+ *
+ * This function reads the versions used (cas(v1/v2))
+ * which refers to link partner sub type. Client driver
+ * uses this information for later process
+ *
+ * Return: 0 on success, negative error code on failure
+ */
+int sbl_get_lp_subtype(struct sbl_inst *sbl, int port_num, enum sbl_lp_subtype *lp_subtype)
+{
+	int              err;
+	struct sbl_link *link;
+
+	err = sbl_validate_instance(sbl);
+	if (err)
+		return err;
+
+	err = sbl_validate_port_num(sbl, port_num);
+	if (err)
+		return err;
+
+	if (lp_subtype == NULL)
+		return -EINVAL;
+
+	sbl_dev_dbg(sbl->dev, "%d: get lp subtype", port_num);
+
+	link = sbl->link + port_num;
+
+	*lp_subtype = link->lp_subtype;
+
+	return 0;
+}
+EXPORT_SYMBOL(sbl_get_lp_subtype);
+
+/**
+ * sbl_base_link_config() - config base link
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ * @blattr: Pointer to struct sbl_base_link_attr
+ *
+ * Set base link config based on attributes provided
+ *
+ * Context: Process context, Acquires lock and release link->lock <spin_lock>
+ *
+ * Return: 0 on success, negative error code on failure
+ */
+int sbl_base_link_config(struct sbl_inst *sbl, int port_num, struct sbl_base_link_attr *blattr)
+{
+	struct sbl_link *link;
+	int err;
+
+	err = sbl_validate_instance(sbl);
+	if (err)
+		return err;
+
+	err = sbl_validate_port_num(sbl, port_num);
+	if (err)
+		return err;
+
+	sbl_dev_dbg(sbl->dev, "bl %d: config\n", port_num);
+
+	if (!blattr)
+		return -EINVAL;
+
+	if (blattr->magic != SBL_LINK_ATTR_MAGIC)
+		return -EINVAL;
+
+	link = sbl->link + port_num;
+
+	spin_lock(&link->lock);
+
+	if (!(link->blstate & (SBL_BASE_LINK_STATUS_DOWN | SBL_BASE_LINK_STATUS_UNCONFIGURED))) {
+
+		sbl_dev_err(sbl->dev, "bl %d: wrong state (%s) for config", port_num,
+			    sbl_link_state_str(link->blstate));
+		spin_unlock(&link->lock);
+		return -EUCLEAN;
+	}
+
+	memcpy(&link->blattr, blattr, sizeof(struct sbl_base_link_attr));
+
+	link->blconfigured = true;
+
+	if (link->blattr.loopback_mode == SBL_LOOPBACK_MODE_LOCAL) {
+		/* we dont need media to go to down */
+		link->blstate = SBL_BASE_LINK_STATUS_DOWN;
+	} else if (link->mconfigured) {
+		/* we need media as well if not loopback */
+		link->blstate = SBL_BASE_LINK_STATUS_DOWN;
+	}
+
+	spin_unlock(&link->lock);
+
+	return 0;
+}
+EXPORT_SYMBOL(sbl_base_link_config);
+
+/**
+ * sbl_base_link_start() - Initialize and bring up links
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ *
+ * This function performs full sequence to bring up serdes link.
+ * It handles firmware validation, link mode detection, alignment,
+ * SerDes startup and link integrity checks. This process ensures
+ * link partner is detected and all lanes are properly initialized
+ * and active before reporting the link is up
+ *
+ * Context: Process, May sleep. Uses mutex_lock_interruptible
+ *
+ * Return: 0 on success, negative error code on failure
+ */
+int sbl_base_link_start(struct sbl_inst *sbl, int port_num)
+{
+	int err;
+	int tmp_err;
+	u32 base = SBL_PML_BASE(port_num);
+	u64 cfg_pcs_reg;
+	u64 sts_pcs_lane_degrade_reg;
+	struct lane_degrade lanes;
+	u32 ucw_adj = 100;
+	u32 ccw_adj = 0;
+	s32 ucw_in = SBL_LINK_FEC_HPE;
+	s32 ccw_in = SBL_LINK_FEC_HPE;
+	struct sbl_link *link;
+
+	err = sbl_validate_instance(sbl);
+	if (err)
+		return err;
+
+	err = sbl_validate_port_num(sbl, port_num);
+	if (err)
+		return err;
+
+	sbl_dev_dbg(sbl->dev, "bl %d: start\n", port_num);
+
+	link = sbl->link + port_num;
+
+	err = mutex_lock_interruptible(&link->busy_mtx);
+	if (err)
+		return -ERESTARTSYS;
+
+	if (link->blstate == SBL_BASE_LINK_STATUS_UP) {
+		/* link came up while waiting for the mutex */
+		mutex_unlock(&link->busy_mtx);
+		return 0;
+	}
+
+	if (link->blstate != SBL_BASE_LINK_STATUS_DOWN) {
+
+		sbl_dev_err(sbl->dev, "bl %d: wrong state (%s) for start", port_num,
+			    sbl_link_state_str(link->blstate));
+		mutex_unlock(&link->busy_mtx);
+		return -EUCLEAN;
+	}
+
+	/* only local loopback is possible without media */
+	if (link->blattr.loopback_mode != SBL_LOOPBACK_MODE_LOCAL) {
+		err = sbl_media_validate_config(sbl, port_num);
+		if (err) {
+			sbl_dev_err(sbl->dev, "bl %d: config unsuitable for media type", port_num);
+			mutex_unlock(&link->busy_mtx);
+			return err;
+		}
+	}
+
+	link->blstate = SBL_BASE_LINK_STATUS_STARTING;
+
+	/* check for loopback mode change */
+	if (link->blattr.loopback_mode != link->loopback_mode)
+		link->llr_loop_time = 0;
+	link->loopback_mode = link->blattr.loopback_mode;
+
+	/* setup the timeout for start to complete
+	 * (autoneg might modify this later)
+	 */
+	sbl_link_init_start_timeout(sbl, port_num);
+
+	/* clear out any residual pcs state */
+	sbl_pml_set_defaults(sbl, port_num);
+
+	/* reset state */
+	link->lp_detected = false;
+
+	/* validate serdes firmwares are (still) uncorrupted, recover them if
+	 * needed
+	 */
+	err = sbl_base_link_check_fix_fw(sbl, port_num);
+	if (err) {
+		sbl_base_link_report_err(sbl, "ensure_healthly", port_num, err);
+		goto out;
+	}
+
+	/* determine the link mode
+	 * this may do autoneg for electrical links
+	 */
+	err = sbl_base_link_get_mode(sbl, port_num);
+	if (err) {
+		if (sbl_base_link_an_timed_out(sbl, port_num, err))
+			sbl_dev_dbg(sbl->dev, "bl %d: autoneg timeout", port_num);
+		else
+			sbl_base_link_report_err(sbl, "get_mode", port_num, err);
+		goto out;
+	}
+
+	/* start sending alignment markers for lp to tune against */
+	err = sbl_pml_pcs_am_start(sbl, port_num);
+	if (err) {
+		sbl_dev_err(sbl->dev, "bl %d: am_start failed [%d]\n", port_num, err);
+		goto out;
+	}
+
+	/* wait until we detect the link partner */
+	err = sbl_base_link_lp_detect(sbl, port_num);
+	if (err) {
+		sbl_base_link_report_err(sbl, "lpd", port_num, err);
+		goto out;
+	}
+
+	/* record when we really start to bring up the link */
+	sbl_link_up_begin(sbl, port_num);
+
+	/* start the serdes */
+	err = sbl_serdes_start(sbl, port_num);
+	if (err) {
+		sbl_base_link_report_err(sbl, "serdes_start", port_num, err);
+		goto out;
+	}
+
+	/* start the pml block (pcs,mac,llr) */
+	err = sbl_pml_start(sbl, port_num);
+	if (err) {
+		sbl_base_link_report_err(sbl, "pml_start", port_num, err);
+		goto out_serdes;
+	}
+
+	/* clearing fec values before start */
+	sbl_zero_all_fec_counts(sbl, port_num);
+
+	/* setup thresholds and adjustments for fec monitoring */
+	err = sbl_fec_thresholds_set(sbl, port_num, ucw_in, ccw_in);
+	if (err) {
+		sbl_dev_err(sbl->dev, "%d: setting fec thresholds failed [%d]",
+			    port_num, err);
+		goto out_pcs;
+	}
+
+	err = sbl_fec_adjustments_set(sbl, port_num, ucw_adj, ccw_adj);
+	if (err) {
+		sbl_dev_err(sbl->dev, "%d: setting fec adjustments failed [%d]",
+			    port_num, err);
+		goto out_pcs;
+	}
+
+	/* start fec checking */
+	err = sbl_fec_up_check(sbl, port_num);
+	if (err) {
+		unsigned long flags;
+
+		sbl_serdes_invalidate_tuning_params(sbl, port_num);
+		sbl_dev_info(sbl->dev, "%d: failed start fec check", port_num);
+
+		/* SSHOTPLAT-5697 forces a maximum effort tune
+		 * straight away after FEC up check fails.
+		 */
+		sbl_dev_dbg(sbl->dev, "bl %d: forcing a maximum effort tune for next retry", port_num);
+		spin_lock_irqsave(&link->lock, flags);
+		link->blattr.options |= SBL_OPT_DFE_ALWAYS_MAX_EFFORT;
+		spin_unlock_irqrestore(&link->lock, flags);
+
+		goto out_pcs;
+	}
+
+	/* start monitoring for link faults */
+	err = sbl_link_fault_monitor_start(sbl, port_num);
+	if (err) {
+		sbl_dev_err(sbl->dev, "bl %d: link fault detect start failed [%d]\n", port_num, err);
+		goto out_pcs;
+	}
+
+	/* final check the link is still up and all lanes remain active */
+	if (!sbl_pml_pcs_up(sbl, port_num)) {
+		sbl_dev_err(sbl->dev, "bl %d: link failed during startup\n", port_num);
+		err = -ENETDOWN;
+		goto out_fm;
+	}
+
+	cfg_pcs_reg = sbl_read64(sbl, base | SBL_PML_CFG_PCS_OFFSET);
+	if (SBL_PML_CFG_PCS_ENABLE_AUTO_LANE_DEGRADE_GET(cfg_pcs_reg)) {
+
+		sts_pcs_lane_degrade_reg = sbl_read64(sbl, base | SBL_PML_STS_PCS_LANE_DEGRADE_OFFSET);
+		lanes.tx = SBL_PML_STS_PCS_LANE_DEGRADE_LP_PLS_AVAILABLE_GET(sts_pcs_lane_degrade_reg);
+		lanes.rx = SBL_PML_STS_PCS_LANE_DEGRADE_RX_PLS_AVAILABLE_GET(sts_pcs_lane_degrade_reg);
+
+		if (lanes.tx != SBL_LINK_ALL_LANES || lanes.rx != SBL_LINK_ALL_LANES) {
+			sbl_dev_err(sbl->dev, "bl %d: lane failed during startup - TX: 0x%llx - RX: 0x%llx",
+				    port_num, lanes.tx, lanes.rx);
+			err = -ENETDOWN;
+			goto out_fm;
+		}
+	}
+
+	/* success ! */
+	sbl_link_up_record_timespec(sbl, port_num);
+	sbl_link_start_record_timespec(sbl, port_num);
+
+	link->blstate = SBL_BASE_LINK_STATUS_UP;
+	link->blerr = 0;
+
+	sbl_dev_dbg(sbl->dev, "starting timer port_num:%d ", port_num);
+	sbl_fec_monitor_start(sbl, port_num);
+	mutex_unlock(&link->busy_mtx);
+
+	return 0;
+
+	/* failed */
+out_fm:
+	sbl_link_fault_monitor_stop(sbl, port_num);
+out_pcs:
+	if (!sbl_debug_option(sbl, port_num, SBL_DEBUG_INHIBIT_CLEANUP))
+		sbl_pml_link_down(sbl, port_num);
+out_serdes:
+	if (!sbl_debug_option(sbl, port_num, SBL_DEBUG_INHIBIT_CLEANUP))
+		sbl_serdes_stop(sbl, port_num);
+out:
+	if (sbl_debug_option(sbl, port_num, SBL_DEBUG_INHIBIT_CLEANUP) ||
+	    sbl_debug_option(sbl, port_num, SBL_DEBUG_INHIBIT_RELOAD_FW))
+		link->reload_serdes_fw = false;
+	else if (sbl_debug_option(sbl, port_num, SBL_DEBUG_FORCE_RELOAD_FW))
+		link->reload_serdes_fw = true;
+
+	if (link->reload_serdes_fw) {
+		sbl_dev_info(sbl->dev, "bl %d: reloading serdes fw\n", port_num);
+		tmp_err = sbl_serdes_firmware_flash_safe(sbl, port_num, true);
+		if (tmp_err) {
+			/* All we can do is report failure here */
+			sbl_dev_err(sbl->dev, "bl %d: fw flash failed [%d]\n",
+				    port_num, tmp_err);
+			link->sstate = SBL_SERDES_STATUS_ERROR;
+		} else
+			link->sstate = SBL_SERDES_STATUS_DOWN;
+		link->serr = tmp_err;
+		link->reload_serdes_fw = false;
+	}
+	link->blstate = SBL_BASE_LINK_STATUS_ERROR;
+	link->blerr = err;
+	mutex_unlock(&link->busy_mtx);
+
+	return err;
+}
+EXPORT_SYMBOL(sbl_base_link_start);
+
+/**
+ * sbl_ignore_save_tuning_param() - Config ignore save tuning parameters
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ * @ignore: If set then ignore save tuning
+ *
+ * This function performs the Load saved tuning params before tuning
+ * when 'ignore' is set false from caller.
+ */
+void sbl_ignore_save_tuning_param(struct sbl_inst *sbl, int port_num, bool ignore)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	unsigned long flags;
+
+	spin_lock_irqsave(&link->lock, flags);
+	if (ignore)
+		link->blattr.options &= ~SBL_OPT_USE_SAVED_PARAMS;
+	else
+		link->blattr.options |= SBL_OPT_USE_SAVED_PARAMS;
+	spin_unlock_irqrestore(&link->lock, flags);
+}
+EXPORT_SYMBOL(sbl_ignore_save_tuning_param);
+
+/**
+ * sbl_enable_opt_lane_degrade() - Enable opt lane degrade
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ * @enable: if set then enable OPT LANE DEGRADE
+ *
+ * This function performs enable auto lane degrade when
+ * 'enable' is set from the caller
+ */
+void sbl_enable_opt_lane_degrade(struct sbl_inst *sbl, int port_num, bool enable)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	unsigned long flags;
+
+	spin_lock_irqsave(&link->lock, flags);
+	if (enable)
+		link->blattr.options |= SBL_OPT_LANE_DEGRADE;
+	else
+		link->blattr.options &= ~SBL_OPT_LANE_DEGRADE;
+	spin_unlock_irqrestore(&link->lock, flags);
+}
+EXPORT_SYMBOL(sbl_enable_opt_lane_degrade);
+
+/**
+ * sbl_disable_pml_recovery() - Disable PML recovery
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ * @disable: if set, then disable PML recovery
+ *
+ * This function performs disable PML recovery
+ * when 'disable' is set from the caller
+ */
+void sbl_disable_pml_recovery(struct sbl_inst *sbl, int port_num, bool disable)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	unsigned long flags;
+
+	spin_lock_irqsave(&link->lock, flags);
+	if (disable)
+		link->blattr.options |= SBL_DISABLE_PML_RECOVERY;
+	else
+		link->blattr.options &= ~SBL_DISABLE_PML_RECOVERY;
+	spin_unlock_irqrestore(&link->lock, flags);
+}
+EXPORT_SYMBOL(sbl_disable_pml_recovery);
+
+/**
+ * sbl_set_degraded_flag() - Set degraded flag
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ *
+ * Context: Process context, Acquires lock and releases is_degraded_lock <spin_lock>
+ */
+void sbl_set_degraded_flag(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+
+	spin_lock(&link->is_degraded_lock);
+	link->is_degraded = true;
+	spin_unlock(&link->is_degraded_lock);
+}
+EXPORT_SYMBOL(sbl_set_degraded_flag);
+
+/**
+ * sbl_clear_degraded_flag() - Clear degraded flag
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ *
+ * Context: Process context, Acquires lock and releases is_degraded_lock <spin_lock>
+ */
+void sbl_clear_degraded_flag(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+
+	spin_lock(&link->is_degraded_lock);
+	link->is_degraded = false;
+	spin_unlock(&link->is_degraded_lock);
+}
+EXPORT_SYMBOL(sbl_clear_degraded_flag);
+
+/**
+ * sbl_get_degraded_flag() - Get degraded flag
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ *
+ * Context: Process context, Acquires lock and releases is_degraded_lock <spin_lock>
+ *
+ * Return: status of degraded flag
+ */
+bool sbl_get_degraded_flag(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	bool degraded_flag;
+
+	spin_lock(&link->is_degraded_lock);
+	degraded_flag = link->is_degraded;
+	spin_unlock(&link->is_degraded_lock);
+
+	return degraded_flag;
+}
+EXPORT_SYMBOL(sbl_get_degraded_flag);
+
+/**
+ * sbl_base_link_enable_start() - Enable base link start
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ *
+ * Context: Process context, Acquires lock and releases link->lock <spin_lock>
+ *
+ * Return: 0
+ */
+int sbl_base_link_enable_start(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+
+	sbl_dev_dbg(sbl->dev, "bl %d: enable start\n", port_num);
+
+	spin_lock(&link->lock);
+	link->start_cancelled = false;
+	spin_unlock(&link->lock);
+
+	return 0;
+}
+EXPORT_SYMBOL(sbl_base_link_enable_start);
+
+/**
+ * sbl_base_link_cancel_start() - Cancel base link start
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ *
+ * Context: Process context, Acquires lock and releases link->lock <spin_lock>
+ *
+ * Return: 0
+ */
+int sbl_base_link_cancel_start(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+
+	sbl_dev_dbg(sbl->dev, "bl %d: cancelling start\n", port_num);
+
+	spin_lock(&link->lock);
+	link->start_cancelled = true;
+	complete_all(&link->an_hw_change);
+	spin_unlock(&link->lock);
+	sbl_fec_monitor_stop(sbl, port_num);
+
+	return 0;
+}
+EXPORT_SYMBOL(sbl_base_link_cancel_start);
+
+bool sbl_base_link_start_cancelled(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	bool cancelled;
+
+	spin_lock(&link->lock);
+	cancelled = link->start_cancelled;
+	spin_unlock(&link->lock);
+
+	return cancelled;
+}
+
+/**
+ * sbl_base_link_stop() - Stop base link
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ *
+ * This function cleanly shuts down previously initialized
+ * SerDes link, link monitoring and stops the PML block.
+ *
+ * Context: Process, May sleep. Uses mutex_lock_interruptible
+ *
+ * Return: 0 on success, negative error code on failure
+ */
+int sbl_base_link_stop(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link;
+	int err;
+
+	err = sbl_validate_instance(sbl);
+	if (err)
+		return err;
+
+	err = sbl_validate_port_num(sbl, port_num);
+	if (err)
+		return err;
+
+	sbl_dev_dbg(sbl->dev, "bl %d: stop", port_num);
+
+	link = sbl->link + port_num;
+
+	err = mutex_lock_interruptible(&link->busy_mtx);
+	if (err)
+		return -ERESTARTSYS;
+
+	sbl_fec_monitor_stop(sbl, port_num);
+
+	if (link->blstate == SBL_BASE_LINK_STATUS_DOWN) {
+		/* link went down while waiting for the mutex */
+		mutex_unlock(&link->busy_mtx);
+		return 0;
+	}
+
+	if (link->blstate != SBL_BASE_LINK_STATUS_UP) {
+		sbl_dev_err(sbl->dev, "bl %d: not up (%s) for stop - ignored", port_num,
+			    sbl_link_state_str(link->blstate));
+		mutex_unlock(&link->busy_mtx);
+		return -EBUSY;
+	}
+
+	/* if keeping serdes up, don't change state to stopping */
+	if (!sbl_debug_option(sbl, port_num, SBL_DEBUG_KEEP_SERDES_UP))
+		link->blstate = SBL_BASE_LINK_STATUS_STOPPING;
+
+	/* We stop the serdes before stopping the pml to avoid breaking AOC firmware,
+	 * really we should stop the pml first. This should be harmless provided
+	 * down detection is off.
+	 */
+	err = sbl_link_fault_monitor_stop(sbl, port_num);
+	if (err) {
+		sbl_dev_err(sbl->dev, "bl %d: link_fault_monitor_stop failed [%d]", port_num, err);
+		goto out;
+	}
+
+	sbl_pml_recovery_cancel(sbl, port_num);
+
+	err = sbl_serdes_stop(sbl, port_num);
+	if (err) {
+		sbl_dev_err(sbl->dev, "bl %d: serdes_stop failed [%d]", port_num, err);
+		goto out;
+	}
+
+	err = sbl_pml_link_down(sbl, port_num);
+	if (err) {
+		sbl_dev_err(sbl->dev, "bl %d: pml_link_down failed [%d]", port_num, err);
+		goto out;
+	}
+
+out:
+	spin_lock(&link->lock);
+	if (err)
+		link->blstate = SBL_BASE_LINK_STATUS_ERROR;
+	/* if keep serdes up, don't change state to down */
+	else if (!sbl_debug_option(sbl, port_num, SBL_DEBUG_KEEP_SERDES_UP))
+		link->blstate = SBL_BASE_LINK_STATUS_DOWN;
+	link->blerr = err;
+	spin_unlock(&link->lock);
+
+	mutex_unlock(&link->busy_mtx);
+
+	sbl_dev_dbg(sbl->dev, "bl %d: stop done", port_num);
+
+	return link->blerr;
+}
+EXPORT_SYMBOL(sbl_base_link_stop);
+
+/**
+ * sbl_base_link_reset() - Reset base link
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ *
+ * This function resets the base link by disabling
+ * pml interrupt handlers, resets serdes and PML block.
+ *
+ * Context: Process, May sleep. Uses mutex_lock_interruptible
+ *
+ * Return: 0 on success, negative error code on failure
+ */
+int sbl_base_link_reset(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link;
+	int err;
+
+	err = sbl_validate_instance(sbl);
+	if (err)
+		return err;
+
+	err = sbl_validate_port_num(sbl, port_num);
+	if (err)
+		return err;
+
+	sbl_dev_dbg(sbl->dev, "bl %d: reset\n", port_num);
+
+	link = sbl->link + port_num;
+
+	err = mutex_lock_interruptible(&link->busy_mtx);
+	if (err)
+		return -ERESTARTSYS;
+
+	sbl_fec_monitor_stop(sbl, port_num);
+
+	link->blstate = SBL_BASE_LINK_STATUS_RESETTING;
+
+	/* disable and remove any pml intr handlers */
+	if (link->intr_err_flgs) {
+		sbl_pml_disable_intr_handler(sbl, port_num, link->intr_err_flgs);
+		sbl_pml_remove_intr_handler(sbl, port_num);
+		link->intr_err_flgs = 0;
+	}
+
+	sbl_pml_recovery_cancel(sbl, port_num);
+
+	err = sbl_serdes_reset(sbl, port_num);
+	if (err)
+		sbl_dev_err(sbl->dev, "bl %d: reset: serdes_reset failed [%d]", port_num, err);
+
+	err = sbl_pml_link_down(sbl, port_num);
+	if (err)
+		sbl_dev_warn(sbl->dev, "bl %d: reset: pcs_link_down failed [%d]", port_num, err);
+
+	link->blstate = SBL_BASE_LINK_STATUS_UNCONFIGURED;
+	link->blerr = 0;
+	link->blconfigured = false;
+	link->pcs_config = false;
+	link->llr_loop_time = 0;
+	link->start_cancelled = false;
+	WRITE_ONCE(link->link_info, 0);
+	link->lp_subtype = SBL_LP_SUBTYPE_INVALID;
+	/* dont reset media attribute */
+
+	/* reset hw */
+	sbl_pml_set_defaults(sbl, port_num);
+
+	sbl_pml_err_flgs_clear_all(sbl, port_num);
+
+	mutex_unlock(&link->busy_mtx);
+
+	return 0;
+}
+EXPORT_SYMBOL(sbl_base_link_reset);
+
+/**
+ * sbl_base_link_try_start_fail_cleanup() - Clean up resources
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ *
+ * Try to clear any error states that are non-fatal so we can directly
+ * attempt another start up.
+ *
+ * Context: Process, May sleep. Uses mutex_lock_interruptible
+ */
+void sbl_base_link_try_start_fail_cleanup(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link;
+	int err;
+
+	err = sbl_validate_instance(sbl);
+	if (err)
+		return;
+
+	err = sbl_validate_port_num(sbl, port_num);
+	if (err)
+		return;
+
+	sbl_dev_dbg(sbl->dev, "bl %d: try start fail cleanup\n", port_num);
+
+	link = sbl->link + port_num;
+
+	err = mutex_lock_interruptible(&link->busy_mtx);
+	if (err)
+		return;
+
+	/* disable and remove any pml intr handlers */
+	if (link->intr_err_flgs) {
+		sbl_pml_disable_intr_handler(sbl, port_num, link->intr_err_flgs);
+		sbl_pml_remove_intr_handler(sbl, port_num);
+		link->intr_err_flgs = 0;
+	}
+
+	/* when debugging we can leave the hw in its current state */
+	if (sbl_debug_option(sbl, port_num, SBL_DEBUG_INHIBIT_CLEANUP)) {
+		sbl_dev_warn(sbl->dev, "%d: hw cleanup inhibited\n", port_num);
+		mutex_unlock(&link->busy_mtx);
+		return;
+	}
+
+	/* clean up the serdes state
+	 * We have to do this before resetting the PML or the optical transceivers can
+	 * fail.
+	 */
+	switch (link->sstate) {
+	case SBL_SERDES_STATUS_RUNNING:
+		sbl_serdes_stop(sbl, port_num);
+		break;
+	case SBL_SERDES_STATUS_AUTONEG:
+		sbl_an_serdes_stop(sbl, port_num);
+		break;
+	default:
+		break;
+	}
+
+	/* still not down! */
+	if (link->sstate != SBL_SERDES_STATUS_DOWN)
+		sbl_serdes_reset(sbl, port_num);
+
+	/* some errors we can clean up and move to down so
+	 * we can try to come up again directly
+	 */
+	if (link->blstate == SBL_BASE_LINK_STATUS_ERROR) {
+		switch (link->blerr) {
+
+		case -EADV:          /* pcs startup saw high serdes error rate */
+		case -EBADE:         /* bad page exchange during auto neg */
+		case -ENETDOWN:      /* pcs dropped out after starting */
+		case -ECHRNG:        /* serdes eye heights went bad during pcs startup */
+		case -ELNRNG:        /* unable to tune properly */
+			sbl_serdes_invalidate_all_tuning_params(sbl);
+			fallthrough;
+		case -ETIME:
+		case -ETIMEDOUT:
+		case -EOVERFLOW:
+		case -ECANCELED:
+		case -ENOSR:         /* llr failed to start */
+
+			link->blstate = SBL_BASE_LINK_STATUS_DOWN;
+			link->blerr = 0;
+			link->pcs_config = false;
+			link->llr_loop_time = 0;
+			link->start_cancelled = false;
+
+			sbl_pml_link_down(sbl, port_num);
+			sbl_pml_set_defaults(sbl, port_num);
+			break;
+
+		default:
+			sbl_dev_err(sbl->dev, "%d: start fail cleanup not clearing err %d\n",
+				    port_num, link->blerr);
+			break;
+		}
+	}
+
+	mutex_unlock(&link->busy_mtx);
+}
+EXPORT_SYMBOL(sbl_base_link_try_start_fail_cleanup);
+
+/**
+ * sbl_base_link_get_status() - Get link status
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ * @blstate: link state
+ * @blerr: link err
+ * @sstate: state
+ * @serr: err
+ * @media_type: media type
+ * @link_mode: link mode
+ *
+ * This function gets base link status from params
+ * used
+ *
+ * Return: 0 on success, negative error code on failure
+ */
+int sbl_base_link_get_status(struct sbl_inst *sbl, int port_num,
+			     int *blstate, int *blerr, int *sstate, int *serr,
+		int *media_type, int *link_mode)
+{
+	struct sbl_link *link;
+	int err;
+
+	err = sbl_validate_instance(sbl);
+	if (err)
+		return err;
+
+	err = sbl_validate_port_num(sbl, port_num);
+	if (err)
+		return err;
+
+	link = sbl->link + port_num;
+
+	if (blstate)
+		*blstate = link->blstate;
+	if (blerr)
+		*blerr = link->blerr;
+	if (sstate)
+		*sstate = link->sstate;
+	if (serr)
+		*serr = link->serr;
+	if (media_type)
+		*media_type = link->mattr.media;
+
+	if (link_mode) {
+		if (link->sstate == SBL_SERDES_STATUS_RUNNING)
+			*link_mode = link->link_mode;            /* actual mode */
+		else
+			*link_mode = link->blattr.link_mode;     /* target mode */
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(sbl_base_link_get_status);
+
+/**
+ * sbl_base_link_state_str() - Read the state of the pcs and serdes
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ * @buf: Destination buffer to write the data
+ * @len: Length of data to write
+ *
+ * This function reads the state of pcs and serdes
+ * and return in the string format
+ *
+ * Return: Number of characters written on success
+ */
+char *sbl_base_link_state_str(struct sbl_inst *sbl, int port_num, char *buf, int len)
+{
+	char pcs_buf[SBL_PCS_STATE_STR_LEN];
+	u8 not_idle_map;  /* not signalling electrical idle */
+	u8 good_eyes_map;
+	u8 active_map;
+
+	if (!buf || !len)
+		return "";
+
+	sbl_pml_pcs_state_str(sbl, port_num, pcs_buf, SBL_PCS_STATE_STR_LEN);
+
+	if (sbl_port_get_serdes_state_maps(sbl, port_num, &active_map,
+					   &not_idle_map, &good_eyes_map)) {
+		/* only active map unavailable */
+		snprintf(buf, len, "pcs %s, serdes -,-/%x", pcs_buf, active_map);
+	} else
+		snprintf(buf, len, "pcs %s, serdes %x,%x/%x", pcs_buf,
+			 not_idle_map, good_eyes_map, active_map);
+
+	return buf;
+}
+EXPORT_SYMBOL(sbl_base_link_state_str);
+
+/**
+ * sbl_link_get_ucw_thresh_hpe() - uncorrected codeword thresholds(hpe)
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ *
+ * This function reads ucw(hpe) based on link mode
+ *
+ * Return: Threshold value on success, 0 on failure.
+ */
+u64  sbl_link_get_ucw_thresh_hpe(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+
+	/* return a little under 1e-10 for all modes and cable types */
+	switch (link->link_mode) {
+	case SBL_LINK_MODE_BS_200G:
+		return 21;
+	case SBL_LINK_MODE_BJ_100G:
+	case SBL_LINK_MODE_CD_100G:
+		return 11;
+	case SBL_LINK_MODE_CD_50G:
+		return 5;
+	default:
+		sbl_dev_err(sbl->dev, "%d: cannot determine ucw rate", port_num);
+		return 0;
+	}
+}
+EXPORT_SYMBOL(sbl_link_get_ucw_thresh_hpe);
+
+/**
+ * sbl_link_get_ucw_thresh_ieee() - uncorrected codeword thresholds(ieee)
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ *
+ * This function reads ucw(ieee).
+ *
+ * Return: Threshold value on success, 0 on failure.
+ */
+u64  sbl_link_get_ucw_thresh_ieee(struct sbl_inst *sbl, int port_num)
+{
+	/* currently these are the same as the hpe values */
+	return sbl_link_get_ucw_thresh_hpe(sbl, port_num);
+}
+EXPORT_SYMBOL(sbl_link_get_ucw_thresh_ieee);
+
+/**
+ * sbl_link_get_ccw_thresh_hpe() - corrected codeword thresholds
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ *
+ * This function reads ccw(hpe) based on link mode
+ *
+ * Return: Threshold value on success, 0 on failure.
+ */
+u64  sbl_link_get_ccw_thresh_hpe(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+
+	/* for electrical links use a threshold of 1.e-5
+	 * (we consider loopback links to be electrical)
+	 */
+	if ((link->mattr.media == SBL_LINK_MEDIA_ELECTRICAL) ||
+	    (link->loopback_mode == SBL_LOOPBACK_MODE_LOCAL)) {
+		switch (link->link_mode) {
+		case SBL_LINK_MODE_BS_200G:
+			return 21250000;
+		case SBL_LINK_MODE_BJ_100G:
+			return 10312500;
+		case SBL_LINK_MODE_CD_100G:
+			return 10625000;
+		case SBL_LINK_MODE_CD_50G:
+			return 5312500;
+		default:
+			sbl_dev_err(sbl->dev, "%d: cannot determine PEC ccw rate", port_num);
+			return 0;
+		}
+
+	}
+
+	/* optical links seem to require a threshold of about 4e-5
+	 * (otherwise pcal can sometimes take us over the threshold)
+	 */
+	if (link->mattr.media == SBL_LINK_MEDIA_OPTICAL) {
+		switch (link->link_mode) {
+		case SBL_LINK_MODE_BS_200G:
+			return 85000000;
+		case SBL_LINK_MODE_BJ_100G:
+			return 41250000;
+		case SBL_LINK_MODE_CD_100G:
+			return 42500000;
+		case SBL_LINK_MODE_CD_50G:
+			return 21250000;
+		default:
+			sbl_dev_err(sbl->dev, "%d: cannot determine AOC ccw rate", port_num);
+			return 0;
+		}
+	}
+
+	/* dont recognise media */
+	sbl_dev_err(sbl->dev, "%d: cannot determine ccw rate - unrecognised media", port_num);
+	return 0;
+}
+EXPORT_SYMBOL(sbl_link_get_ccw_thresh_hpe);
+
+/**
+ * sbl_link_get_ccw_thresh_ieee() - Get correcred code words threshold
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ *
+ * This function reads ccw(ieee) based on link mode
+ *
+ * Return: Threshold value on success, 0 on failure.
+ */
+u64  sbl_link_get_ccw_thresh_ieee(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+
+	/* ieee thresholds are about 2e-4
+	 * We dont care about media type
+	 */
+	switch (link->link_mode) {
+	case SBL_LINK_MODE_BS_200G:
+		return 42500000;
+	case SBL_LINK_MODE_BJ_100G:
+	case SBL_LINK_MODE_CD_100G:
+		return 21250000;
+	case SBL_LINK_MODE_CD_50G:
+		return 10625000;
+	default:
+		sbl_dev_err(sbl->dev, "%d: cannot determine ccw rate", port_num);
+		return 0;
+	}
+}
+EXPORT_SYMBOL(sbl_link_get_ccw_thresh_ieee);
+
+/**
+ * sbl_link_get_stp_ccw_thresh_hpe() - Get Corrected code words(hpe) threshold
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ *
+ * Get Corrected code words(hpe) threshold when STP is used
+ *
+ * Return: Threshold value on success, 0 on failure.
+ */
+u64  sbl_link_get_stp_ccw_thresh_hpe(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+
+	/* for electrical links use a threshold of 1.e-8
+	 * (we consider loopback links to be electrical)
+	 */
+	if ((link->mattr.media == SBL_LINK_MEDIA_ELECTRICAL) ||
+	    (link->loopback_mode == SBL_LOOPBACK_MODE_LOCAL)) {
+		switch (link->link_mode) {
+		case SBL_LINK_MODE_BS_200G:
+			return 2125;
+		case SBL_LINK_MODE_BJ_100G:
+			return 1031;
+		case SBL_LINK_MODE_CD_100G:
+			return 1062;
+		case SBL_LINK_MODE_CD_50G:
+			return 531;
+		default:
+			sbl_dev_err(sbl->dev, "%d: cannot determine PEC stp ccw rate", port_num);
+			return 0;
+		}
+
+	}
+
+	/* optical links seem to require a threshold of about 4e-8
+	 * (otherwise pcal can sometimes take us over the threshold)
+	 */
+	if (link->mattr.media == SBL_LINK_MEDIA_OPTICAL) {
+		switch (link->link_mode) {
+		case SBL_LINK_MODE_BS_200G:
+			return 8500;
+		case SBL_LINK_MODE_BJ_100G:
+			return 4125;
+		case SBL_LINK_MODE_CD_100G:
+			return 4250;
+		case SBL_LINK_MODE_CD_50G:
+			return 2125;
+		default:
+			sbl_dev_err(sbl->dev, "%d: cannot determine AOC stp ccw rate", port_num);
+			return 0;
+		}
+	}
+
+	/* dont recognise media */
+	sbl_dev_err(sbl->dev, "%d: cannot determine stp ccw rate - unrecognised media", port_num);
+	return 0;
+}
+EXPORT_SYMBOL(sbl_link_get_stp_ccw_thresh_hpe);
+
+/**
+ * sbl_link_get_stp_ccw_thresh_ieee() - Get corrected code word(ieee) threshold
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ *
+ * Get Corrected code words(ieee) threshold when STP is used
+ *
+ * Return: Threshold value on success, 0 on failure.
+ */
+u64  sbl_link_get_stp_ccw_thresh_ieee(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+
+	/* ieee thresholds are about 2e-8
+	 * We dont care about media type
+	 */
+	switch (link->link_mode) {
+	case SBL_LINK_MODE_BS_200G:
+		return 4250;
+	case SBL_LINK_MODE_BJ_100G:
+	case SBL_LINK_MODE_CD_100G:
+		return 2125;
+	case SBL_LINK_MODE_CD_50G:
+		return 1062;
+	default:
+		sbl_dev_err(sbl->dev, "%d: cannot determine stp ccw rate", port_num);
+		return 0;
+	}
+}
+EXPORT_SYMBOL(sbl_link_get_stp_ccw_thresh_ieee);
+
+/* Link info
+ * lets you see the current state of the link
+ *
+ * Atomic mask updates preserve concurrently changed flags.
+ */
+void sbl_link_info_set(struct sbl_inst *sbl, int port_num, u32 flag)
+{
+	switch (flag) {
+
+	case SBL_LINK_INFO_LP_DET:
+	case SBL_LINK_INFO_PCS_ANEG:
+	case SBL_LINK_INFO_PCS_TX_AM:
+	case SBL_LINK_INFO_PCS_TX_RF:
+	case SBL_LINK_INFO_PCS_ALIGN_EN:
+	case SBL_LINK_INFO_PCS_A_WAIT:
+	case SBL_LINK_INFO_PCS_F_WAIT:
+	case SBL_LINK_INFO_PCS_UP:
+	case SBL_LINK_INFO_MAC_OP:
+	case SBL_LINK_INFO_OS:
+	case SBL_LINK_INFO_LLR_LOOP:
+	case SBL_LINK_INFO_LLR_MEASURE:
+	case SBL_LINK_INFO_LLR_WAIT:
+	case SBL_LINK_INFO_LLR_RUN:
+	case SBL_LINK_INFO_LLR_DISABLED:
+	case SBL_LINK_INFO_FAULT_MON:
+	case SBL_LINK_INFO_LLR_DETECT:
+		set_mask_bits(&sbl->link[port_num].link_info, 0, flag);
+		break;
+
+	default:
+		sbl_dev_dbg(sbl->dev, "bl %d: unrecognised set info flag (%d)\n",
+			    port_num, flag);
+		break;
+	}
+}
+
+void sbl_link_info_clear(struct sbl_inst *sbl, int port_num, u32 flag)
+{
+	switch (flag) {
+
+	case SBL_LINK_INFO_LP_DET:
+	case SBL_LINK_INFO_PCS_ANEG:
+	case SBL_LINK_INFO_PCS_TX_AM:
+	case SBL_LINK_INFO_PCS_TX_RF:
+	case SBL_LINK_INFO_PCS_ALIGN_EN:
+	case SBL_LINK_INFO_PCS_A_WAIT:
+	case SBL_LINK_INFO_PCS_F_WAIT:
+	case SBL_LINK_INFO_PCS_UP:
+	case SBL_LINK_INFO_MAC_OP:
+	case SBL_LINK_INFO_OS:
+	case SBL_LINK_INFO_LLR_LOOP:
+	case SBL_LINK_INFO_LLR_MEASURE:
+	case SBL_LINK_INFO_LLR_WAIT:
+	case SBL_LINK_INFO_LLR_RUN:
+	case SBL_LINK_INFO_LLR_DISABLED:
+	case SBL_LINK_INFO_FAULT_MON:
+	case SBL_LINK_INFO_LLR_DETECT:
+		set_mask_bits(&sbl->link[port_num].link_info, flag, 0);
+		break;
+
+	default:
+		sbl_dev_dbg(sbl->dev, "bl %d: unrecognised clear info flag (%d)\n",
+			    port_num, flag);
+		break;
+	}
+}
+
+#ifdef CONFIG_SYSFS
+/**
+ * sbl_base_link_sysfs_sprint() - Format link info into buffer
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ * @buf: Destination buffer to write the data
+ * @size: Size of @buf in bytes, the output is truncated to fit
+ *
+ * Context: Process, Acquires lock and release link->lock <spin_lock>
+ *
+ * Return: Number of characters written, at most @size - 1
+ */
+int sbl_base_link_sysfs_sprint(struct sbl_inst *sbl, int port_num, char *buf, size_t size)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	bool mac_tx_op;
+	bool mac_rx_op;
+	u32 mac_ifg_mode;
+	u32 link_info;
+	u64 llr_cfg;
+	u32 llr_mode;
+	u32 llr_down_behavior;
+	u64 llr_sts;
+	int s = 0;
+
+	spin_lock(&link->lock);
+	link_info = READ_ONCE(link->link_info);
+
+	s += scnprintf(buf + s, size - s, "base link state: %s",
+			sbl_link_state_str(link->blstate));
+	if (link->blstate == SBL_BASE_LINK_STATUS_ERROR)
+		s += scnprintf(buf + s, size - s, " [%d]", link->blerr);
+	if (link->blstate == SBL_BASE_LINK_STATUS_STARTING)
+		s += scnprintf(buf + s, size - s, " (%d/%d)",
+				sbl_link_start_elapsed(sbl, port_num),
+				sbl_get_start_timeout(sbl, port_num));
+	if (link->blstate == SBL_BASE_LINK_STATUS_UP)
+		s += scnprintf(buf + s, size - s, " (%lld.%.3ld, %lld.%.3ld)",
+				(long long)link->start_time.tv_sec,
+				link->start_time.tv_nsec / 1000000,
+				(long long)link->up_time.tv_sec,
+				link->up_time.tv_nsec / 1000000);
+	s += scnprintf(buf + s, size - s, "\n");
+
+	if (link_info) {
+		s += scnprintf(buf + s, size - s, "base link info: ");
+		if (link_info & SBL_LINK_INFO_PCS_ANEG)
+			s += scnprintf(buf + s, size - s, "pcs-aneg ");
+		if (link_info & SBL_LINK_INFO_PCS_TX_AM)
+			s += scnprintf(buf + s, size - s, "pcs-tx-am ");
+		if (link_info & SBL_LINK_INFO_PCS_ALIGN_EN)
+			s += scnprintf(buf + s, size - s, "pcs-a-en ");
+		if (link_info & SBL_LINK_INFO_PCS_A_WAIT)
+			s += scnprintf(buf + s, size - s, "pcs-a-wait ");
+		if (link_info & SBL_LINK_INFO_PCS_TX_RF)
+			s += scnprintf(buf + s, size - s, "pcs-tx-rf ");
+		if (link_info & SBL_LINK_INFO_PCS_F_WAIT)
+			s += scnprintf(buf + s, size - s, "pcs-f-wait ");
+		if (link_info & SBL_LINK_INFO_PCS_UP)
+			s += scnprintf(buf + s, size - s, "pcs-up ");
+		if (link_info & SBL_LINK_INFO_LP_DET)
+			s += scnprintf(buf + s, size - s, "lp-det ");
+		if (link_info & SBL_LINK_INFO_MAC_OP)
+			s += scnprintf(buf + s, size - s, "mac ");
+		if (link_info & SBL_LINK_INFO_OS)
+			s += scnprintf(buf + s, size - s, "os ");
+		if (link_info & SBL_LINK_INFO_LLR_LOOP)
+			s += scnprintf(buf + s, size - s, "llr-loop-en ");
+		if (link_info & SBL_LINK_INFO_LLR_DETECT)
+			s += scnprintf(buf + s, size - s, "llr-detect ");
+		if (link_info & SBL_LINK_INFO_LLR_MEASURE)
+			s += scnprintf(buf + s, size - s, "llr-measure ");
+		if (link_info & SBL_LINK_INFO_LLR_WAIT)
+			s += scnprintf(buf + s, size - s, "llr-wait ");
+		if (link_info & SBL_LINK_INFO_LLR_RUN)
+			s += scnprintf(buf + s, size - s, "llr ");
+		if (link_info & SBL_LINK_INFO_LLR_DISABLED)
+			s += scnprintf(buf + s, size - s, "llr-dis ");
+		if (link_info & SBL_LINK_INFO_FAULT_MON)
+			s += scnprintf(buf + s, size - s, "fm ");
+		s += scnprintf(buf + s, size - s, "\n");
+	}
+
+	if (link->blconfigured) {
+
+		if (link->blattr.config_target == SBL_BASE_LINK_CONFIG_PEC) {
+			s += scnprintf(buf + s, size - s, "base link: an: mode %s",
+					sbl_an_mode_str(link->blattr.pec.an_mode));
+			if (link_info & SBL_LINK_INFO_PCS_ANEG) {
+				if (link->blattr.pec.an_mode == SBL_AN_MODE_FIXED)
+					s += scnprintf(buf + s, size - s, "(%s)",
+							sbl_link_mode_str(link->blattr.link_mode));
+				s += scnprintf(buf + s, size - s, ", tries %d, nonce %x, state %s",
+						link->an_try_count, link->an_nonce,
+						sbl_an_get_sm_state(sbl, port_num));
+			}
+			if ((link->blattr.pec.an_mode != SBL_AN_MODE_OFF) && (link->an_rx_count))
+				s += scnprintf(buf + s, size - s, ", received %d",
+					       link->an_rx_count);
+			if (link->an_100cr4_fixup_applied)
+				s += scnprintf(buf + s, size - s, ", 100cr4-fixup");
+			if (link->an_options & AN_OPT_LLR)
+				s += scnprintf(buf + s, size - s, ", llr");
+
+			s += scnprintf(buf + s, size - s, "\n");
+		}
+		sbl_pml_mac_hw_status(sbl, port_num, &mac_tx_op, &mac_rx_op, &mac_ifg_mode, NULL);
+		if (mac_tx_op || mac_rx_op) {
+			s += scnprintf(buf + s, size - s, "base link: mac: tx %d, rx %d, ifg %s\n",
+					mac_tx_op, mac_rx_op, sbl_ifg_config_str(link->ifg_config));
+		}
+
+		llr_cfg = sbl_read64(sbl, SBL_PML_BASE(port_num) | SBL_PML_CFG_LLR_OFFSET);
+		switch (SBL_PML_CFG_LLR_LLR_MODE_GET(llr_cfg)) {
+		case 0:
+			llr_mode = SBL_LLR_MODE_OFF;
+			break;
+		case 1:
+			llr_mode = SBL_LLR_MODE_MONITOR;
+			break;
+		case 2:
+			llr_mode = SBL_LLR_MODE_ON;
+			break;
+		default:
+			llr_mode = SBL_LLR_MODE_INVALID;
+		}
+		switch (SBL_PML_CFG_LLR_LINK_DOWN_BEHAVIOR_GET(llr_cfg)) {
+		case 0:
+			llr_down_behavior = SBL_LLR_LINK_DOWN_DISCARD;
+			break;
+		case 1:
+			llr_down_behavior = SBL_LLR_LINK_DOWN_BLOCK;
+			break;
+		case 2:
+			llr_down_behavior = SBL_LLR_LINK_DOWN_BEST_EFFORT;
+			break;
+		default:
+			llr_down_behavior = SBL_LLR_LINK_DOWN_INVALID;
+		}
+		llr_sts = sbl_read64(sbl, SBL_PML_BASE(port_num) |
+				     SBL_PML_STS_LLR_MAX_USAGE_OFFSET);
+		s += scnprintf(buf + s, size - s,
+			       "base link: llr: mode %s, down %s, loop %lld %s %s\n",
+			       sbl_llr_mode_str(llr_mode),
+			       sbl_llr_down_behaviour_str(llr_down_behavior),
+			       link->llr_loop_time,
+			       SBL_PML_STS_LLR_MAX_USAGE_BUFF_SPC_STARVED_GET(llr_sts) ?
+			       "buf starved" : "",
+			       SBL_PML_STS_LLR_MAX_USAGE_SEQ_STARVED_GET(llr_sts) ?
+			       "seq starved" : "");
+
+		if (link->blattr.options & SBL_DISABLE_PML_RECOVERY)
+			s += scnprintf(buf + s, size - s, "base link: pml rec: disabled\n");
+		else
+			s += scnprintf(buf + s, size - s,
+				       "base link: pml rec: enabled, to %u, rl %u/%u\n",
+				       link->blattr.pml_recovery.timeout,
+				       link->blattr.pml_recovery.rl_max_duration,
+				       link->blattr.pml_recovery.rl_window_size);
+	}
+
+	spin_unlock(&link->lock);
+
+	s += sbl_debug_sysfs_sprint(sbl, port_num, buf + s, size - s);
+
+	return s;
+}
+EXPORT_SYMBOL(sbl_base_link_sysfs_sprint);
+#endif
+
+/**
+ * sbl_base_link_dump_attr() - Format all link attributes into buffer
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ * @buf: Destination buffer to write the data
+ * @size: Size of @buf in bytes, the output is truncated to fit
+ *
+ * Return: Number of characters written, at most @size - 1
+ */
+int sbl_base_link_dump_attr(struct sbl_inst *sbl, int port_num, char *buf, size_t size)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	struct sbl_base_link_attr *attr = &link->blattr;
+	int s = 0;
+
+	s += scnprintf(buf + s, size - s, "%d: base link attributes:\n", port_num);
+
+	if (!link->blconfigured) {
+		s += scnprintf(buf + s, size - s, "not configured\n");
+		return s;
+	}
+
+	s += scnprintf(buf + s, size - s, "options 0x%x", attr->options);
+	if (attr->options) {
+		s += scnprintf(buf + s, size - s, " -");
+		if (attr->options & SBL_OPT_FABRIC_LINK)
+			s += scnprintf(buf + s, size - s, " fabric");
+		if (attr->options & SBL_OPT_SERDES_LPD)
+			s += scnprintf(buf + s, size - s, " serdes-lpd");
+		if (attr->options & SBL_OPT_DFE_SAVE_PARAMS)
+			s += scnprintf(buf + s, size - s, " save-params");
+		if (attr->options & SBL_OPT_USE_SAVED_PARAMS)
+			s += scnprintf(buf + s, size - s, " use-params");
+		if (attr->options & SBL_OPT_RESET_CLEAR_PARAMS)
+			s += scnprintf(buf + s, size - s, " reset-clear-params");
+		if (attr->options & SBL_OPT_ENABLE_PCAL)
+			s += scnprintf(buf + s, size - s, " pcal");
+		if (attr->options & SBL_OPT_DFE_ALWAYS_MAX_EFFORT)
+			s += scnprintf(buf + s, size - s, " max-effort");
+		if (attr->options & SBL_OPT_DFE_ALWAYS_MED_EFFORT)
+			s += scnprintf(buf + s, size - s, " med-effort");
+		if (attr->options & SBL_OPT_DFE_ALWAYS_MIN_EFFORT)
+			s += scnprintf(buf + s, size - s, " min-effort");
+		if (attr->options & SBL_OPT_AUTONEG_TIMEOUT_IEEE)
+			s += scnprintf(buf + s, size - s, " an-timeout-ieee");
+		if (attr->options & SBL_OPT_AUTONEG_TIMEOUT_SSHOT)
+			s += scnprintf(buf + s, size - s, " an-timeout-sshot");
+		if (attr->options & SBL_OPT_AUTONEG_100CR4_FIXUP)
+			s += scnprintf(buf + s, size - s, " an-100cr4-fixup");
+		if (attr->options & SBL_OPT_RELOAD_FW_ON_TIMEOUT)
+			s += scnprintf(buf + s, size - s, " timeout-reload-fw");
+		if (attr->options & SBL_OPT_ALLOW_MEDIA_BAD_MODE)
+			s += scnprintf(buf + s, size - s, " allow-media-bad-mode");
+		if (attr->options & SBL_OPT_ALLOW_MEDIA_BAD_LEN)
+			s += scnprintf(buf + s, size - s, " allow-media-bad-len");
+		if (attr->options & SBL_OPT_ENABLE_ETHER_LLR)
+			s += scnprintf(buf + s, size - s, " enable-ether-llr");
+		if (attr->options & SBL_OPT_ENABLE_IFG_HPC_WITH_LLR)
+			s += scnprintf(buf + s, size - s, " enable-ifg-hpc-with-llr");
+		if (attr->options & SBL_OPT_ENABLE_IFG_CONFIG)
+			s += scnprintf(buf + s, size - s, " enable-ifg-config");
+		if (attr->options & SBL_OPT_DISABLE_AN_LLR)
+			s += scnprintf(buf + s, size - s, " disable-an-llr");
+		if (attr->options & SBL_OPT_LANE_DEGRADE)
+			s += scnprintf(buf + s, size - s, " enable-lane-degrade");
+		if (attr->options & SBL_DISABLE_PML_RECOVERY)
+			s += scnprintf(buf + s, size - s, " disable-pml-recovery");
+	}
+	s += scnprintf(buf + s, size - s, "\n");
+	s += scnprintf(buf + s, size - s, "start_timeout %d\n", attr->start_timeout);
+	if (attr->config_target == SBL_BASE_LINK_CONFIG_PEC) {
+		s += scnprintf(buf + s, size - s, "config_target PEC\n");
+		s += scnprintf(buf + s, size - s, "an_mode %d (%s)\n",
+			       attr->pec.an_mode,
+			       sbl_an_mode_str(attr->pec.an_mode));
+		s += scnprintf(buf + s, size - s, "an_retry_timeout %d\n",
+			       attr->pec.an_retry_timeout);
+		s += scnprintf(buf + s, size - s, "an_max_retry %d\n", attr->pec.an_max_retry);
+	}
+	if (attr->config_target == SBL_BASE_LINK_CONFIG_AOC) {
+		s += scnprintf(buf + s, size - s, "config_target AOC\n");
+		s += scnprintf(buf + s, size - s, "optical_lock_delay %d\n",
+			       attr->aoc.optical_lock_delay);
+		s += scnprintf(buf + s, size - s, "optical_lock_interval %d\n",
+			       attr->aoc.optical_lock_interval);
+	}
+	s += scnprintf(buf + s, size - s, "lpd_timeout %d\n", attr->lpd_timeout);
+	s += scnprintf(buf + s, size - s, "lpd_poll_interval %d\n", attr->lpd_poll_interval);
+	s += scnprintf(buf + s, size - s, "link_mode %d (%s)\n",
+		       attr->link_mode, sbl_link_mode_str(attr->link_mode));
+	s += scnprintf(buf + s, size - s, "loopback_mode %d (%s)\n",
+		       attr->loopback_mode,
+		       sbl_loopback_mode_str(attr->loopback_mode));
+	s += scnprintf(buf + s, size - s, "link_partner %d\n", attr->link_partner);
+	s += scnprintf(buf + s, size - s, "tuning_pattern %d\n", attr->tuning_pattern);
+	s += scnprintf(buf + s, size - s, "precoding %d\n", attr->precoding);
+	s += scnprintf(buf + s, size - s, "dfe_pre_delay %d\n", attr->dfe_pre_delay);
+	s += scnprintf(buf + s, size - s, "dfe_timeout %d\n", attr->dfe_timeout);
+	s += scnprintf(buf + s, size - s, "dfe_poll_interval %d\n", attr->dfe_poll_interval);
+	s += scnprintf(buf + s, size - s, "pcal_eyecheck_holdoff %d\n",
+		       attr->pcal_eyecheck_holdoff);
+	s += scnprintf(buf + s, size - s, "nrz_min_eye_height 0x%x\n", attr->nrz_min_eye_height);
+	s += scnprintf(buf + s, size - s, "nrz_max_eye_height 0x%x\n", attr->nrz_max_eye_height);
+	s += scnprintf(buf + s, size - s, "pam4_min_eye_height 0x%x\n", attr->pam4_min_eye_height);
+	s += scnprintf(buf + s, size - s, "pam4_max_eye_height 0x%x\n", attr->pam4_max_eye_height);
+	s += scnprintf(buf + s, size - s, "fec_mode %d\n", attr->fec_mode);
+	s += scnprintf(buf + s, size - s, "enable_autodegrade %d\n", attr->enable_autodegrade);
+	s += scnprintf(buf + s, size - s, "llr_mode %d (%s)\n",
+		       attr->llr_mode, sbl_llr_mode_str(attr->llr_mode));
+	s += scnprintf(buf + s, size - s, "ifg_config %d (%s)\n",
+		       attr->ifg_config, sbl_ifg_config_str(attr->ifg_config));
+	s += scnprintf(buf + s, size - s, "pml_recovery.timeout %u\n", attr->pml_recovery.timeout);
+	s += scnprintf(buf + s, size - s, "pml_recovery.rl_max_duration %u\n",
+		       attr->pml_recovery.rl_max_duration);
+	s += scnprintf(buf + s, size - s, "pml_recovery.rl_window_size %u\n",
+		       attr->pml_recovery.rl_window_size);
+
+	return s;
+}
+EXPORT_SYMBOL(sbl_base_link_dump_attr);
diff --git a/drivers/net/ethernet/hpe/sbl/sbl_link_an.c b/drivers/net/ethernet/hpe/sbl/sbl_link_an.c
new file mode 100644
index 000000000000..aecadbceb593
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sbl/sbl_link_an.c
@@ -0,0 +1,1010 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* Copyright 2019-2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/random.h>
+#include <linux/delay.h>
+
+#include <linux/hpe/sbl/sbl.h>
+#include <linux/hpe/sbl/sbl_an.h>
+
+#include <linux/hpe/sbl/sbl_pml.h>
+
+#include "sbl_pml_fn.h"
+#include "sbl_link.h"
+#include "sbl_serdes.h"
+#include "sbl_constants.h"
+#include "sbl_serdes_map.h"
+#include "sbl_internal.h"
+
+/* for debug purposes we can add an extra null message page for fabric links */
+#define SBL_SEND_EXTRA_FABRIC_NULL_PAGE                 0
+
+/* set the reset state */
+static void sbl_an_pml_an_reset(struct sbl_inst *sbl, int port_num, u64 reset_state)
+{
+	u32 base = SBL_PML_BASE(port_num);
+	u64 cfg_pcs_autoneg_reg;
+
+	/* reset */
+	cfg_pcs_autoneg_reg = sbl_read64(sbl, base | SBL_PML_CFG_PCS_AUTONEG_OFFSET);
+	cfg_pcs_autoneg_reg = SBL_PML_CFG_PCS_AUTONEG_RESET_UPDATE(cfg_pcs_autoneg_reg, reset_state);
+	sbl_write64(sbl, base | SBL_PML_CFG_PCS_AUTONEG_OFFSET,
+		    cfg_pcs_autoneg_reg);
+	sbl_read64(sbl, base | SBL_PML_CFG_PCS_AUTONEG_OFFSET);
+}
+
+static void sbl_an_send_base_page(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	u32 base = SBL_PML_BASE(port_num);
+
+	/* first page is the base page (whole reg) */
+	sbl_write64(sbl, base | SBL_PML_CFG_PCS_AUTONEG_BASE_PAGE_OFFSET, link->an_tx_page[0]);
+	sbl_read64(sbl, base | SBL_PML_CFG_PCS_AUTONEG_BASE_PAGE_OFFSET);
+
+	sbl_dev_dbg(sbl->dev, "an %d: tx base page: 0x%llx", port_num, link->an_tx_page[0]);
+
+	/* start autoneg by taking an sm out of reset*/
+	sbl_an_pml_an_reset(sbl, port_num, 0);
+}
+
+static u32 sbl_an_get_nonce(void)
+{
+	u16 buf;
+
+	while (1) {
+		get_random_bytes(&buf, 2);
+		buf &= 0x1f;
+		if (buf)
+			return buf;
+	}
+}
+
+static bool sbl_an_base_is_complete(struct sbl_inst *sbl, int port_num)
+{
+	u32 base = SBL_PML_BASE(port_num);
+	u64 sts_autoneg_base_reg;
+
+	sts_autoneg_base_reg = sbl_read64(sbl, base | SBL_PML_STS_PCS_AUTONEG_BASE_PAGE_OFFSET);
+
+	return SBL_PML_STS_PCS_AUTONEG_BASE_PAGE_COMPLETE_GET(sts_autoneg_base_reg);
+}
+
+static bool sbl_an_base_is_page_recv(struct sbl_inst *sbl, int port_num)
+{
+	u32 base = SBL_PML_BASE(port_num);
+	u64 sts_autoneg_base_reg;
+	bool val;
+
+	sts_autoneg_base_reg = sbl_read64(sbl, base | SBL_PML_STS_PCS_AUTONEG_BASE_PAGE_OFFSET);
+
+	val = (SBL_PML_STS_PCS_AUTONEG_BASE_PAGE_LP_ABILITY_GET(sts_autoneg_base_reg)) &&
+	      (SBL_PML_STS_PCS_AUTONEG_BASE_PAGE_PAGE_RECEIVED_GET(sts_autoneg_base_reg));
+
+	return val;
+}
+
+static bool sbl_an_is_base_page(struct sbl_inst *sbl, int port_num)
+{
+	u32 base = SBL_PML_BASE(port_num);
+	u64 sts_autoneg_base_reg;
+	u64 state;
+	bool val;
+
+	sts_autoneg_base_reg = sbl_read64(sbl, base | SBL_PML_STS_PCS_AUTONEG_BASE_PAGE_OFFSET);
+
+	state = SBL_PML_STS_PCS_AUTONEG_BASE_PAGE_STATE_GET(sts_autoneg_base_reg);
+
+	val = (state == SBL_PML_AUTONEG_STATE_COMPLETE_ACK) ||
+	      (state == SBL_PML_AUTONEG_STATE_AN_GOOD_CHECK);
+
+	val = val && (SBL_PML_STS_PCS_AUTONEG_BASE_PAGE_PAGE_RECEIVED_GET(sts_autoneg_base_reg)) &&
+	      (SBL_PML_STS_PCS_AUTONEG_BASE_PAGE_BASE_PAGE_GET(sts_autoneg_base_reg)) &&
+	      (SBL_PML_STS_PCS_AUTONEG_BASE_PAGE_LP_ABILITY_GET(sts_autoneg_base_reg));
+
+	return val;
+}
+
+/* Setup the pages */
+static int sbl_an_setup_tx_pages(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+
+	sbl_dev_dbg(sbl->dev, "an %d: run setup tx pages", port_num);
+
+	/* init to known non-zero value so it's easy to tell used pages from init pages */
+	memset(link->an_tx_page, 0xAA, sizeof(link->an_tx_page));
+
+	/* build the base page */
+
+	link->an_tx_page[0] = 0;
+	link->an_tx_page[0] |= AN_CW_S_802_3;
+
+	if (link->blattr.pec.an_mode == SBL_AN_MODE_FIXED) {
+
+		switch (link->blattr.link_mode) {
+
+		case SBL_LINK_MODE_BS_200G:
+			link->an_tx_page[0] |= (AN_CW_A_200GBASE_CR4) << AN_CW_A_BASE_BIT;
+			break;
+
+		case SBL_LINK_MODE_BJ_100G:
+			link->an_tx_page[0] |= (AN_CW_A_100GBASE_CR4) << AN_CW_A_BASE_BIT;
+			break;
+
+		case SBL_LINK_MODE_CD_100G:
+			link->an_tx_page[0] |= (AN_CW_A_100GBASE_CR2) << AN_CW_A_BASE_BIT;
+			break;
+
+		case SBL_LINK_MODE_CD_50G:
+			link->an_tx_page[0] |= (AN_CW_A_50GBASE_CR) << AN_CW_A_BASE_BIT;
+			break;
+
+		default:
+			sbl_dev_err(sbl->dev, "an %d: bad an blattr mode", port_num);
+			return -EINVAL;
+		}
+	} else {
+		/* all modes we support */
+		link->an_tx_page[0] |= (AN_CW_A_200GBASE_CR4) << AN_CW_A_BASE_BIT;
+		link->an_tx_page[0] |= (AN_CW_A_100GBASE_CR4) << AN_CW_A_BASE_BIT;
+		link->an_tx_page[0] |= (AN_CW_A_100GBASE_CR2) << AN_CW_A_BASE_BIT;
+		link->an_tx_page[0] |= (AN_CW_A_50GBASE_CR)   << AN_CW_A_BASE_BIT;
+	}
+
+	/* Not sure what to set here - both Arista and Mellanox say zero so for
+	 * now we will do the same and set nothing
+	 */
+
+	/* TODO: Enhance PAUSE support. Currently only symmetric PAUSE is advertised.
+	 * Should support: asymmetric PAUSE modes, flow control negotiation per standard,
+	 * and link partner capability reporting.
+	 */
+	link->an_tx_page[0] |= (AN_CW_C_SYMMETRIC) << AN_CW_C_BASE_BIT;
+
+	sbl_dev_dbg(sbl->dev, "an %d: bp = 0x%llx", port_num, link->an_tx_page[0]);
+
+	/* check for disabled next pages */
+	if (sbl_debug_option(sbl, port_num, SBL_DEBUG_DISABLE_AN_NEXT_PAGES)) {
+		sbl_dev_dbg(sbl->dev, "an %d: next pages disabled", port_num);
+		link->an_tx_count = 1;
+		return 0;
+	}
+
+	/* build HPE OUI next pages */
+
+	/* have next page (set in previous page) */
+	link->an_tx_page[0] |= AN_CW_NP_MASK;
+
+	/* OUI message page */
+	link->an_tx_page[1] = 0ULL;
+	link->an_tx_page[1] |= AN_NP_MP_MASK;
+	link->an_tx_page[1] |= AN_NP_CODE_OUI_EXTENDED_MSG;
+	link->an_tx_page[1] |= AN_NP_OUI_HPE;
+
+	sbl_dev_dbg(sbl->dev, "an %d: np mp = 0x%llx", port_num, link->an_tx_page[1]);
+
+	/* have next page (set in previous page) */
+	link->an_tx_page[1] |= AN_CW_NP_MASK;
+
+	/* unformatted page with OUI message page */
+	link->an_tx_page[2] = 0ULL;
+	link->an_tx_page[2] |= AN_NP_OUI_VER_0_1;
+	/* LLR options here */
+	if (link->blattr.llr_mode == SBL_LLR_MODE_AUTO) {
+		if (!(link->blattr.options & SBL_OPT_DISABLE_AN_LLR)) {
+			link->an_tx_page[2] |= (AN_OPT_LLR << AN_OPT_BASE_BIT);
+			if (link->blattr.options & SBL_OPT_ENABLE_ETHER_LLR)
+				link->an_tx_page[2] |= (AN_OPT_ETHER_LLR << AN_OPT_BASE_BIT);
+
+			if (link->blattr.options & SBL_OPT_ENABLE_IFG_HPC_WITH_LLR)
+				link->an_tx_page[2] |= (AN_OPT_HPC_WITH_LLR << AN_OPT_BASE_BIT);
+			/* TODO: add IPV4 option */
+		}
+	}
+	sbl_an_version_read(sbl, port_num);
+
+	sbl_dev_dbg(sbl->dev, "an %d: np ufp = 0x%llx", port_num, link->an_tx_page[2]);
+
+	link->an_tx_count = SBL_AN_MAX_TX_PAGES;
+
+	return 0;
+}
+
+static int sbl_an_pml_setup(struct sbl_inst *sbl, int port_num)
+{
+	u32 base = SBL_PML_BASE(port_num);
+	u64 cfg_pcs_autoneg_reg;
+	u64 cfg_pcs_reg;
+	u64 cfg_rx_pcs_reg;
+	u64 val64;
+
+	/* disable pcs autoneg
+	 * as pcs is also disabled this will reset the pcs-serdes CDC logic
+	 */
+	cfg_pcs_reg = sbl_read64(sbl, base | SBL_PML_CFG_PCS_OFFSET);
+	cfg_pcs_reg = SBL_PML_CFG_PCS_ENABLE_AUTO_NEG_UPDATE(cfg_pcs_reg, 0ULL);
+	sbl_write64(sbl, base | SBL_PML_CFG_PCS_OFFSET, cfg_pcs_reg);
+	sbl_read64(sbl, base | SBL_PML_CFG_PCS_OFFSET);
+
+	/* configure an */
+	cfg_pcs_autoneg_reg = SBL_PML_CFG_PCS_AUTONEG_RX_LANE_SET(sbl->switch_info->ports[port_num].rx_an_swizzle) |
+			      SBL_PML_CFG_PCS_AUTONEG_TX_LANE_SET(sbl->switch_info->ports[port_num].tx_an_swizzle) |
+			      SBL_PML_CFG_PCS_AUTONEG_RESET_SET(1ULL) |       /* start held in reset */
+			      SBL_PML_CFG_PCS_AUTONEG_RESTART_SET(0ULL) |     /* not used - always zero */
+			      SBL_PML_CFG_PCS_AUTONEG_NEXT_PAGE_LOADED_SET(0ULL);
+	sbl_write64(sbl, base | SBL_PML_CFG_PCS_AUTONEG_OFFSET,
+		    cfg_pcs_autoneg_reg);
+	sbl_read64(sbl, base | SBL_PML_CFG_PCS_AUTONEG_OFFSET);
+
+	/* reset alignment locking */
+	cfg_rx_pcs_reg = sbl_read64(sbl, base | SBL_PML_CFG_RX_PCS_OFFSET);
+	cfg_rx_pcs_reg = SBL_PML_CFG_RX_PCS_ACTIVE_LANES_UPDATE(cfg_rx_pcs_reg, 0ULL);
+	cfg_rx_pcs_reg = SBL_PML_CFG_RX_PCS_ENABLE_LOCK_UPDATE(cfg_rx_pcs_reg, 0ULL);
+	sbl_write64(sbl, base | SBL_PML_CFG_RX_PCS_OFFSET, cfg_rx_pcs_reg);
+	sbl_read64(sbl, base | SBL_PML_CFG_RX_PCS_OFFSET);
+
+	/* config an timers */
+	val64 = SBL_PML_CFG_PCS_AUTONEG_TIMERS_DFLT;
+	/* disable fault timeout by setting it to its max value  */
+	val64 = SBL_PML_CFG_PCS_AUTONEG_TIMERS_LINK_FAIL_INHIBIT_TIMER_MAX_UPDATE(val64, 0xffffffffULL);
+
+	sbl_write64(sbl, base | SBL_PML_CFG_PCS_AUTONEG_TIMERS_OFFSET, val64);
+
+	/* clear err flags */
+	sbl_pml_err_flgs_clear_all(sbl, port_num);
+
+	/* enable autoneg
+	 * this will take CDC logic out of reset
+	 */
+	cfg_pcs_reg = sbl_read64(sbl, base | SBL_PML_CFG_PCS_OFFSET);
+	cfg_pcs_reg = SBL_PML_CFG_PCS_ENABLE_AUTO_NEG_UPDATE(cfg_pcs_reg, 1ULL);
+	sbl_write64(sbl, base | SBL_PML_CFG_PCS_OFFSET, cfg_pcs_reg);
+
+	/* an reset is still asserted, it will be deasserted after base page is loaded */
+
+	sbl_link_info_set(sbl, port_num, SBL_LINK_INFO_PCS_ANEG);
+
+	return 0;
+}
+
+/* perform page exchange
+ *
+ *   Rosetta has a hw bug whereby some error flags cannot be cleared by the normal method
+ *   as the an state machine will continually reassert them. (The failed, complete and
+ *   next page received err flags) so instead we disable intrs for these flags when they
+ *   are received and reset them in wait prepare.
+ *
+ *   For next pages we would like to do:
+ *
+ *      wait_prepare()
+ *      send_next_page()
+ *      wait_for_completion()
+ *
+ *   However this sequence will cause the err flags to be immediately set in the wait
+ *   prepare and the intr fire.
+ *
+ *   The best we can do is
+ *
+ *      preempt_disable()
+ *      send_next_page()
+ *      wait_prepare()
+ *      preempt_enable()
+ *      wait_for_completion()
+ *
+ *     But we can still miss intrs
+ *     There would seem to be nothing we can do about this
+ *
+ *    26 Feb 2021 - added SM exchange to work around rosetta interrupt bug
+ *
+ */
+static int sbl_an_exchange(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	u32 base = SBL_PML_BASE(port_num);
+	unsigned long timeout = msecs_to_jiffies(1000 * link->blattr.pec.an_retry_timeout);
+	unsigned long remaining_jiffies;
+	u64 sts_autoneg_base_reg;
+	int err;
+
+	sbl_dev_dbg(sbl->dev, "an %d: exchange start", port_num);
+
+	if (sbl_base_link_start_cancelled(sbl, port_num))
+		return -ECANCELED;
+	if (sbl_start_timeout(sbl, port_num))
+		return -ETIMEDOUT;
+
+	if (!sbl->is_hw)
+		return 0;
+
+	/* clear any previous pages */
+	memset(link->an_rx_page, 0, SBL_AN_MAX_RX_PAGES * sizeof(u64));
+	link->an_rx_count = 0;
+
+	/* update the nonce */
+	link->an_nonce = sbl_an_get_nonce();
+	link->an_tx_page[0] &= ~AN_CW_T_MASK;
+	link->an_tx_page[0] |= ((link->an_nonce << AN_CW_T_BASE_BIT) & AN_CW_T_MASK);
+
+	/* base page exchange */
+
+	err = sbl_an_hw_wait_prepare(sbl, port_num);
+	if (err)
+		return err;
+
+	sbl_an_send_base_page(sbl, port_num);
+
+	remaining_jiffies = wait_for_completion_timeout(&link->an_hw_change, timeout);
+	if (sbl_base_link_start_cancelled(sbl, port_num))
+		return -ECANCELED;
+	if (remaining_jiffies == 0) {
+		sbl_dev_dbg(sbl->dev, "an %d: base page exchange timeout (nonce %.2x, sm_state %s)",
+			    port_num, link->an_nonce, sbl_an_get_sm_state(sbl, port_num));
+		sbl_an_dump_state(sbl, port_num);
+
+		/* check we have not missed the err flg */
+		if (sbl_an_base_is_complete(sbl, port_num) || sbl_an_base_is_page_recv(sbl, port_num))
+			sbl_dev_err(sbl->dev, "an %d: MISSED A BASE PAGE!!!!", port_num);
+
+		return -ETIME;
+	}
+
+	/* check it is a base page */
+	if (!sbl_an_is_base_page(sbl, port_num)) {
+		sbl_dev_err(sbl->dev, "an %d: missing base page indication", port_num);
+		sbl_an_dump_state(sbl, port_num);
+		return -EBADE;
+	}
+
+	/* copy page to return buffer */
+	sts_autoneg_base_reg = sbl_read64(sbl, base | SBL_PML_STS_PCS_AUTONEG_BASE_PAGE_OFFSET);
+	link->an_rx_page[0] = SBL_PML_STS_PCS_AUTONEG_BASE_PAGE_LP_BASE_PAGE_GET(sts_autoneg_base_reg);
+	link->an_rx_count = 1;
+
+	/* check if an is complete i.e. no one has more to send */
+	if (sbl_an_base_is_complete(sbl, port_num))
+		goto out_success;
+
+	/* since not complete, we must have received a page - check this */
+	if (!sbl_an_base_is_page_recv(sbl, port_num)) {
+		sbl_dev_err(sbl->dev, "an %d: expected page received indication", port_num);
+		sbl_an_dump_state(sbl, port_num);
+		return -EBADE;
+	}
+
+	/* next page exchange */
+	err = sbl_an_page_exchange(sbl, port_num, remaining_jiffies);
+
+	if (err)
+		return err;
+
+out_success:
+
+	/* dump the final state on the way out */
+	sbl_an_dump_state(sbl, port_num);
+
+	sbl_dev_dbg(sbl->dev, "an %d: exchange complete", port_num);
+
+	return 0;
+}
+
+/* save away the LLR options here */
+static void sbl_an_save_llr_options(struct sbl_link *link, int x)
+{
+	if (link->blattr.llr_mode == SBL_LLR_MODE_AUTO) {
+		if (!(link->blattr.options & SBL_OPT_DISABLE_AN_LLR)) {
+			if (link->an_rx_page[x] & (AN_OPT_LLR << AN_OPT_BASE_BIT))
+				link->an_options |= AN_OPT_LLR;
+			if (link->an_rx_page[x] & (AN_OPT_ETHER_LLR << AN_OPT_BASE_BIT)) {
+				if (link->blattr.options & SBL_OPT_ENABLE_ETHER_LLR)
+					link->an_options |= AN_OPT_ETHER_LLR;
+			}
+			if (link->an_rx_page[x] & (AN_OPT_HPC_WITH_LLR << AN_OPT_BASE_BIT)) {
+				if (link->blattr.options & SBL_OPT_ENABLE_IFG_HPC_WITH_LLR)
+					link->an_options |= AN_OPT_HPC_WITH_LLR;
+			}
+			/* TODO: add IPV4 option */
+		}
+	}
+
+}
+
+static int sbl_an_ability_match(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	u32 fec_ability;
+	u32 tech_ability;
+	u32 pause_ability;
+	u64  last_msg_code = 0;
+	bool expect_hpe    = false;
+	int  x             = 0;
+
+	sbl_dev_dbg(sbl->dev, "an %d: rx count = %d", port_num, link->an_rx_count);
+
+	if (!sbl->is_hw) {
+		/* Netsim/Z1: No AN happening, so just force the response data to the
+		 * tx data to ensure capability match
+		 */
+		link->an_rx_page[0] = link->an_tx_page[0];
+	}
+	/* abilities */
+	tech_ability = (link->an_tx_page[0] & link->an_rx_page[0] & AN_CW_A_MASK)
+			>> AN_CW_A_BASE_BIT;
+	fec_ability = (link->an_tx_page[0] & link->an_rx_page[0] & AN_CW_F_MASK)
+					>> AN_CW_F_BASE_BIT;
+	pause_ability = (link->an_tx_page[0] & link->an_rx_page[0] & AN_CW_C_MASK)
+					>> AN_CW_C_BASE_BIT;
+	sbl_dev_dbg(sbl->dev, "an %d: tech 0x%x, fec 0x%x, pause %d", port_num,
+		    tech_ability, fec_ability, pause_ability);
+
+	/* FEC mode (we only do RS) */
+	if (fec_ability & AN_CW_F_25G_RS_REQ) {
+		/* ignore for now - set in config */
+	} else if (fec_ability & AN_CW_F_25G_BASER_REQ) {
+		sbl_dev_warn(sbl->dev, "an %d: cannot do fec mode baser",
+			     port_num);
+	} else {
+		sbl_dev_dbg(sbl->dev, "an %d: no matching fec mode (partner fec 0x%x)",
+			    port_num, fec_ability);
+	}
+
+	/* TODO pause */
+
+	/* link mode (speed) */
+	if (tech_ability & AN_CW_A_200GBASE_CR4) {
+		link->link_mode = SBL_LINK_MODE_BS_200G;
+	} else if (tech_ability & AN_CW_A_100GBASE_CR4) {
+		link->link_mode = SBL_LINK_MODE_BJ_100G;
+	} else if (tech_ability & AN_CW_A_100GBASE_CR2) {
+		link->link_mode = SBL_LINK_MODE_CD_100G;
+	} else if (tech_ability & AN_CW_A_50GBASE_KR) {
+		link->link_mode = SBL_LINK_MODE_CD_50G;
+	} else {
+		sbl_dev_err(sbl->dev, "an %d: no matching mode (partner ability 0x%x)",
+			    port_num, tech_ability);
+		return -ENOENT;
+	}
+
+	/* look at next page(s) */
+	link->lp_subtype = SBL_LP_SUBTYPE_UNKNOWN;
+	for (x = 1; x < link->an_rx_count; ++x) {
+
+		/* do message page */
+		if (link->an_rx_page[x] & AN_NP_MP_MASK) {
+			last_msg_code = link->an_rx_page[x] & AN_NP_MSG_MASK;
+			sbl_dev_dbg(sbl->dev, "an %d: msg_code = %llu", port_num, last_msg_code);
+			switch (last_msg_code) {
+			case AN_NP_CODE_NULL_MSG:
+			case AN_NP_CODE_OUI_MSG:
+				/* nothing to do */
+				break;
+			case AN_NP_CODE_OUI_EXTENDED_MSG:
+				switch (link->an_rx_page[x] & AN_NP_OUI_MASK) {
+				case AN_NP_OUI_HPE:
+					/* have HPE OUI message - expect an unformatted page next */
+					expect_hpe = true;
+					break;
+				default:
+					sbl_dev_dbg(sbl->dev, "an %d: unknown OUI = 0x%llX", port_num, (link->an_rx_page[x] & AN_NP_OUI_MASK) >> AN_NP_OUI_BASE_BIT);
+					expect_hpe = false;
+					break;
+				}
+				break;
+			default:
+				sbl_dev_dbg(sbl->dev, "an %d: unknown msg_code = 0x%llX", port_num, last_msg_code);
+				break;
+			}
+			/* go on to next page */
+			continue;
+		}
+
+		/* do unformatted page */
+		switch (last_msg_code) {
+		case AN_NP_CODE_OUI_EXTENDED_MSG:
+			if (!expect_hpe)
+				break;
+
+			/* got a HPE OUI message - check the unformatted page and set options */
+			switch (link->an_rx_page[x] & AN_NP_OUI_VER_MASK) {
+			case AN_NP_OUI_VER_0_1:
+				sbl_an_save_llr_options(link, x);
+				/* save away cassini version here */
+				link->lp_subtype = ((link->an_rx_page[x] >> AN_LP_SUBTYPE_BASE_BIT) & AN_LP_SUBTYPE_MASK);
+				sbl_dev_dbg(sbl->dev, "an %d: HPE an_options = 0x%X, lp_subtype = %d", port_num, link->an_options, link->lp_subtype);
+				break;
+			default:
+				sbl_dev_dbg(sbl->dev, "an %d: unknown OUI version 0x%llX", port_num, link->an_rx_page[x] & AN_NP_OUI_VER_MASK);
+				break;
+			}
+			expect_hpe = false;
+			break;
+		default:
+			sbl_dev_dbg(sbl->dev, "an %d: unknown ufp = 0x%llX", port_num, link->an_rx_page[x]);
+			break;
+		}
+	}
+
+	return 0;
+}
+
+static void sbl_an_update_timeout(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	unsigned int new_timeout = 0;
+
+	if (link->blattr.options & SBL_OPT_AUTONEG_TIMEOUT_SSHOT) {
+		/* use slingshot timeouts - which are longer than the IEEE defaults */
+		switch (link->link_mode) {
+		case SBL_LINK_MODE_BS_200G:
+			new_timeout = SBL_LINK_AUTONEG_TIMEOUT_SSHOT_200;
+			break;
+		case SBL_LINK_MODE_BJ_100G:
+		case SBL_LINK_MODE_CD_100G:
+			new_timeout = SBL_LINK_AUTONEG_TIMEOUT_SSHOT_100;
+			break;
+		case SBL_LINK_MODE_CD_50G:
+			new_timeout = SBL_LINK_AUTONEG_TIMEOUT_SSHOT_50;
+			break;
+		default:
+			sbl_dev_warn(sbl->dev, "an %d: bad mode in update_timeout",
+				     port_num);
+		}
+	}
+
+	if (link->blattr.options & SBL_OPT_AUTONEG_TIMEOUT_IEEE) {
+		/* use IEEE timeouts */
+		switch (link->link_mode) {
+		case SBL_LINK_MODE_BS_200G:
+			new_timeout = SBL_LINK_AUTONEG_TIMEOUT_IEEE_200;
+			break;
+		case SBL_LINK_MODE_BJ_100G:
+		case SBL_LINK_MODE_CD_100G:
+			new_timeout = SBL_LINK_AUTONEG_TIMEOUT_IEEE_100;
+			break;
+		case SBL_LINK_MODE_CD_50G:
+			new_timeout = SBL_LINK_AUTONEG_TIMEOUT_IEEE_50;
+			break;
+		default:
+			sbl_dev_warn(sbl->dev, "an %d: bad mode in update_timeout",
+				     port_num);
+		}
+	}
+
+	if (new_timeout) {
+		sbl_dev_dbg(sbl->dev, "an %d: update start timeout to %d ms",
+			    port_num, new_timeout);
+		link->an_timeout_active = true;
+		sbl_link_update_start_timeout(sbl, port_num, new_timeout);
+	}
+}
+
+/* If there is no common mode between this port and our link partner
+ * and if the lp advertises 100KR4 and we advertise 100CR4 then add 100CR4
+ * to the lp's abilities.
+ *
+ * This is necessary because recent Mellanox software no longer advertises
+ * 100CR even though it seems to be able to tune in this mode. Adding 100CR4
+ * to the lp abilities means that we will resolve 100CR4 and start using this
+ * mode.
+ */
+#define SBL_AN_KR4_BIT (1ULL << (AN_CW_A_BASE_BIT + AN_CW_A_100GBASE_KR4_BIT))
+#define SBL_AN_CR4_BIT (1ULL << (AN_CW_A_BASE_BIT + AN_CW_A_100GBASE_CR4_BIT))
+
+static bool sbl_an_100cr4_fixup(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+
+	/* check no match */
+	if (link->an_tx_page[0] & link->an_rx_page[0] & AN_CW_A_MASK)
+		return false;
+
+	/* check we want cr4 */
+	if (!(link->an_tx_page[0] & SBL_AN_CR4_BIT))
+		return false;
+
+	/* check lp wants kr4 */
+	if (!(link->an_rx_page[0] & SBL_AN_KR4_BIT))
+		return false;
+
+	/* add cr4 to lp abilities */
+	link->an_rx_page[0] |= SBL_AN_CR4_BIT;
+
+	/* fixup applied */
+	sbl_dev_info(sbl->dev, "an %d: 100cr4 fixup applied", port_num);
+	return true;
+}
+
+int sbl_link_autoneg(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link;
+	u32 base = SBL_PML_BASE(port_num);
+	u32 random;
+	u64 cfg_pcs_reg;
+	int err;
+
+	err = sbl_validate_instance(sbl);
+	if (err)
+		return err;
+
+	err = sbl_validate_port_num(sbl, port_num);
+	if (err)
+		return err;
+
+	/* set starting point */
+	link = sbl->link + port_num;
+	link->an_options = 0;
+	link->link_mode  = link->blattr.link_mode;
+
+	switch (link->blattr.pec.an_mode) {
+
+	case SBL_AN_MODE_OFF:
+		sbl_dev_dbg(sbl->dev, "an %d: AN off", port_num);
+		/* nothing more to do here */
+		return 0;
+
+	case SBL_AN_MODE_ON:
+	case SBL_AN_MODE_FIXED:
+		/* ok */
+		break;
+
+	default:
+		sbl_dev_err(sbl->dev, "an %d: invalid AN mode (%s)", port_num,
+			    sbl_an_mode_str(link->blattr.pec.an_mode));
+		return -EINVAL;
+	}
+
+	/* we can never be in loopback mode as the nonce will be the same! */
+	if (link->blattr.loopback_mode != SBL_LOOPBACK_MODE_OFF) {
+		sbl_dev_err(sbl->dev, "an %d: cannot autoneg in loopback mode", port_num);
+		return -ENOTUNIQ;
+	}
+
+	/* pcs must not be enabled and autoneg must be off */
+	cfg_pcs_reg = sbl_read64(sbl, base | SBL_PML_CFG_PCS_OFFSET);
+	if (SBL_PML_CFG_PCS_PCS_ENABLE_GET(cfg_pcs_reg)) {
+		sbl_dev_err(sbl->dev, "an %d: pcs is enabled", port_num);
+		err = -EBUSY;
+		goto out;
+	}
+	if (SBL_PML_CFG_PCS_ENABLE_AUTO_NEG_GET(cfg_pcs_reg)) {
+		sbl_dev_err(sbl->dev, "an %d: autoneg already enabled", port_num);
+		err = -EBUSY;
+		goto out;
+	}
+
+	/* sort out the data to send/receive */
+	err = sbl_an_setup_tx_pages(sbl, port_num);
+	if (err) {
+		sbl_dev_err(sbl->dev, "an %d, page setup failed [%d]", port_num, err);
+		goto out;
+	}
+
+	/* setup */
+	err = sbl_pml_install_intr_handler(sbl, port_num, SBL_AUTONEG_ERR_FLGS);
+	if (err)
+		goto out;
+	link->an_100cr4_fixup_applied = false;
+
+	/* try to negotiate */
+	link->an_try_count = 0;
+	while (1) {
+
+		link->an_try_count++;
+
+		/* keep trying until up timeout expires or cancelled */
+		if (sbl_start_timeout(sbl, port_num)) {
+			err = -ETIMEDOUT;
+			break;
+		}
+		if (sbl_base_link_start_cancelled(sbl, port_num)) {
+			err = -ECANCELED;
+			break;
+		}
+
+		/* setup the serdes and pml */
+		err = sbl_an_serdes_start(sbl, port_num);
+		if (err)
+			break;
+		usleep_range(1000, 2000);
+
+		err = sbl_an_pml_setup(sbl, port_num);
+		if (err)
+			break;
+
+		/* try to exchange pages */
+		err = sbl_an_exchange(sbl, port_num);
+		if (err == -EPROTO) {
+			/* we have received an unexpected base page
+			 * The lp must have restarted autoneg and we should too
+			 *
+			 * However we know that some Mellanox cards will do this if there is no
+			 * ability match - particularly only supporting 100KR4 not 100CR4
+			 * See if we can try to fix this up
+			 */
+			if (link->blattr.options & SBL_OPT_AUTONEG_100CR4_FIXUP) {
+				if (sbl_an_100cr4_fixup(sbl, port_num)) {
+					/* fixup applied */
+					link->an_100cr4_fixup_applied = true;
+					/* carry on to ability match */
+				} else {
+					/* fixup failed - retry exchange */
+					sbl_an_serdes_stop(sbl, port_num);
+					continue;
+				}
+			} else {
+				sbl_an_serdes_stop(sbl, port_num);
+				continue;
+			}
+		} else if (err == -ETIME) {
+			/* we have timed out */
+			if (link->an_try_count < link->blattr.pec.an_max_retry) {
+				/* retry */
+				sbl_an_serdes_stop(sbl, port_num);
+				/* Random delay of 1-5 before retry */
+				get_random_bytes(&random, sizeof(random));
+				random = 1u + (random % 5u);
+				msleep(random);
+				continue;
+			} else {
+				/* give up */
+				break;
+			}
+		} else if (err) {
+			/* other error */
+			sbl_dev_dbg(sbl->dev, "an %d: exchange failed [%d] (sm_state %s)",
+				    port_num, err, sbl_an_get_sm_state(sbl, port_num));
+			break;
+		}
+
+		/* pages have been exchanged - try to resolve the mode etc */
+		err = sbl_an_ability_match(sbl, port_num);
+		if (err) {
+			/* no match - try again (in case they change) */
+			sbl_an_serdes_stop(sbl, port_num);
+			continue;
+		}
+
+		/* see if we need to update the start timeout */
+		sbl_an_update_timeout(sbl, port_num);
+
+		/* we know the lp is there */
+		link->lp_detected = true;
+		break;
+	}
+
+	/* cleanup */
+	if (link->sstate == SBL_SERDES_STATUS_AUTONEG)
+		sbl_an_serdes_stop(sbl, port_num);
+	sbl_pml_disable_intr_handler(sbl, port_num, SBL_AUTONEG_ERR_FLGS);
+	sbl_pml_remove_intr_handler(sbl, port_num);
+
+out:
+	sbl_pml_err_flgs_clear_all(sbl, port_num);
+	sbl_link_info_clear(sbl, port_num, SBL_LINK_INFO_PCS_ANEG);
+
+	return err;
+}
+
+void sbl_an_send_next_page(struct sbl_inst *sbl, int port_num)
+{
+	u32 base = SBL_PML_BASE(port_num);
+	u64 cfg_pcs_autoneg_reg;
+
+	cfg_pcs_autoneg_reg = sbl_read64(sbl, base | SBL_PML_CFG_PCS_AUTONEG_OFFSET);
+	cfg_pcs_autoneg_reg = SBL_PML_CFG_PCS_AUTONEG_NEXT_PAGE_LOADED_UPDATE(cfg_pcs_autoneg_reg, 1ULL);
+	sbl_write64(sbl, base | SBL_PML_CFG_PCS_AUTONEG_OFFSET, cfg_pcs_autoneg_reg);
+}
+
+bool sbl_an_next_is_complete(struct sbl_inst *sbl, int port_num)
+{
+	u32 base = SBL_PML_BASE(port_num);
+	u64 sts_autoneg_next_reg;
+
+	sts_autoneg_next_reg = sbl_read64(sbl, base | SBL_PML_STS_PCS_AUTONEG_NEXT_PAGE_OFFSET);
+
+	return SBL_PML_STS_PCS_AUTONEG_NEXT_PAGE_COMPLETE_GET(sts_autoneg_next_reg);
+}
+
+bool sbl_an_is_next_page(struct sbl_inst *sbl, int port_num)
+{
+	u32 base = SBL_PML_BASE(port_num);
+	u64 sts_autoneg_next_reg;
+	u64 state;
+	bool value;
+
+	sts_autoneg_next_reg = sbl_read64(sbl, base | SBL_PML_STS_PCS_AUTONEG_NEXT_PAGE_OFFSET);
+
+	state = SBL_PML_STS_PCS_AUTONEG_NEXT_PAGE_STATE_GET(sts_autoneg_next_reg);
+
+	value =	 (state == SBL_PML_AUTONEG_STATE_COMPLETE_ACK) ||
+		(state == SBL_PML_AUTONEG_STATE_AN_GOOD_CHECK);
+
+	value = value && (SBL_PML_STS_PCS_AUTONEG_NEXT_PAGE_LP_ABILITY_GET(sts_autoneg_next_reg)) &&
+		(!SBL_PML_STS_PCS_AUTONEG_NEXT_PAGE_BASE_PAGE_GET(sts_autoneg_next_reg));
+
+	return value;
+}
+
+void sbl_an_setup_next_page(struct sbl_inst *sbl, int port_num, int page_idx)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	u32 base = SBL_PML_BASE(port_num);
+
+	sbl_write64(sbl, base | SBL_PML_CFG_PCS_AUTONEG_NEXT_PAGE_OFFSET,
+		    link->an_tx_page[page_idx]);
+	sbl_dev_dbg(sbl->dev, "an %d: tx next page: 0x%llx", port_num,
+		    link->an_tx_page[page_idx]);
+	sbl_read64(sbl, base | SBL_PML_CFG_PCS_AUTONEG_NEXT_PAGE_OFFSET);
+}
+
+void sbl_an_setup_null_page(struct sbl_inst *sbl, int port_num)
+{
+	u32 base = SBL_PML_BASE(port_num);
+	u64 null_page;
+
+	/* Construct a null message page as in 802.3-2015: 28.2.3.4.1 & annex 28C */
+	null_page  = sbl_read64(sbl, base | SBL_PML_CFG_PCS_AUTONEG_NEXT_PAGE_OFFSET);
+	null_page ^= AN_NP_T_MASK;          /* toggle bit 11 */
+	null_page &= ~AN_NP_NP_MASK;        /* clear next page bit */
+	null_page |= AN_NP_MP_MASK;         /* set this is msg page */
+	null_page &= ~AN_NP_MSG_MASK;       /* clear msg code */
+	null_page |= AN_NP_CODE_NULL_MSG;   /* set null msg code */
+	null_page &= ~AN_NP_UCF_MASK;       /* clear unformatted code field code */
+	sbl_write64(sbl, base | SBL_PML_CFG_PCS_AUTONEG_NEXT_PAGE_OFFSET, null_page);
+	sbl_dev_dbg(sbl->dev, "an %d: tx null next page: 0x%llx", port_num,
+		    null_page);
+	sbl_read64(sbl, base | SBL_PML_CFG_PCS_AUTONEG_NEXT_PAGE_OFFSET);
+}
+
+/* setup to detect complete or page received error flags become set */
+int sbl_an_hw_wait_prepare(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	unsigned long flags;
+	int err;
+
+	spin_lock_irqsave(&link->lock, flags);
+	if (link->start_cancelled) {
+		spin_unlock_irqrestore(&link->lock, flags);
+		return -ECANCELED;
+	}
+	reinit_completion(&link->an_hw_change);
+	spin_unlock_irqrestore(&link->lock, flags);
+
+	sbl_pml_err_flgs_clear(sbl, port_num, SBL_AUTONEG_ERR_FLGS);
+
+	err = sbl_pml_enable_intr_handler(sbl, port_num, SBL_AUTONEG_ERR_FLGS);
+	if (err) {
+		sbl_dev_err(sbl->dev, "an %d: intr enable failed [%d]", port_num, err);
+		return err;
+	}
+
+	return 0;
+}
+
+const char *sbl_an_get_sm_state(struct sbl_inst *sbl, int port_num)
+{
+	u32 base = SBL_PML_BASE(port_num);
+	u64 sts_pcs_autoneg_reg;
+	u64 sm_state;
+
+	sts_pcs_autoneg_reg = sbl_read64(sbl, base | SBL_PML_STS_PCS_AUTONEG_BASE_PAGE_OFFSET);
+	sm_state = SBL_PML_STS_PCS_AUTONEG_BASE_PAGE_STATE_GET(sts_pcs_autoneg_reg);
+
+	return  sbl_an_state_str(sm_state);
+}
+
+/**
+ * sbl_get_an_pages() - Get an pages
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ * @count: number of pages
+ * @pages: Pointer to max rx pages
+ *
+ * Get number of an pages 'count' and rx pages 'pages'
+ * by reading 'an_rx_count' and 'an_rx_page'
+ *
+ * Return: 0 on success, negative error code on failure
+ */
+int sbl_get_an_pages(struct sbl_inst *sbl, int port_num, int *count, u64 *pages)
+{
+	struct sbl_link *link;
+	int i;
+	int err;
+
+	err = sbl_validate_instance(sbl);
+	if (err)
+		return err;
+
+	err = sbl_validate_port_num(sbl, port_num);
+	if (err)
+		return err;
+
+	if (!count || !pages)
+		return -EINVAL;
+
+	link = sbl->link + port_num;
+
+	/* check we did autoneg successfully */
+	if ((link->blattr.pec.an_mode != SBL_AN_MODE_ON) &&
+	    (link->blattr.pec.an_mode != SBL_AN_MODE_FIXED)) {
+		sbl_dev_info(sbl->dev, "%d: not autoneg mode - no pages to get", port_num);
+		return -ENODATA;
+	}
+	if (!link->an_rx_count) {
+		sbl_dev_info(sbl->dev, "%d: no an pages to get", port_num);
+		return -ENODATA;
+	}
+
+	if (link->an_rx_count > *count) {
+		/* insufficient space
+		 * update size to say how much we need and return
+		 */
+		*count = link->an_rx_count;
+		return -ENOSPC;
+	}
+
+	for (i = 0; i < link->an_rx_count; ++i)
+		*pages++ = link->an_rx_page[i];
+	*count = link->an_rx_count;
+
+	return 0;
+}
+EXPORT_SYMBOL(sbl_get_an_pages);
+
+void sbl_an_dump_state(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	u32 base = SBL_PML_BASE(port_num);
+	u64 val64;
+	int i;
+
+	val64 = sbl_read64(sbl, base | SBL_PML_ERR_FLG_OFFSET);
+	sbl_dev_dbg(sbl->dev, "an %d: dump: err flgs       0x%llx", port_num, val64);
+
+	val64 = sbl_read64(sbl, base | SBL_PML_CFG_PCS_OFFSET);
+	sbl_dev_dbg(sbl->dev, "an %d: dump: cfg pcs        0x%llx", port_num, val64);
+
+	val64 = sbl_read64(sbl, base | SBL_PML_CFG_PCS_AUTONEG_OFFSET);
+	sbl_dev_dbg(sbl->dev, "an %d: dump: cfg pcs an     0x%llx", port_num, val64);
+
+	val64 = sbl_read64(sbl, base | SBL_PML_STS_PCS_AUTONEG_BASE_PAGE_OFFSET);
+	sbl_dev_dbg(sbl->dev, "an %d: dump: sts an base pg 0x%llx", port_num, val64);
+
+	sbl_dev_dbg(sbl->dev, "%d base, complete (%lld), state (%lld) (%s), received (%lld) , base page (%lld), lp (%lld), lp_base (%lld) ",
+		    port_num,
+			SBL_PML_STS_PCS_AUTONEG_BASE_PAGE_COMPLETE_GET(val64),
+			SBL_PML_STS_PCS_AUTONEG_BASE_PAGE_STATE_GET(val64),
+			sbl_an_get_sm_state(sbl, port_num),
+			SBL_PML_STS_PCS_AUTONEG_BASE_PAGE_PAGE_RECEIVED_GET(val64),
+			SBL_PML_STS_PCS_AUTONEG_BASE_PAGE_BASE_PAGE_GET(val64),
+			SBL_PML_STS_PCS_AUTONEG_BASE_PAGE_LP_ABILITY_GET(val64),
+			SBL_PML_STS_PCS_AUTONEG_BASE_PAGE_LP_BASE_PAGE_GET(val64));
+
+	val64 = sbl_read64(sbl, base | SBL_PML_STS_PCS_AUTONEG_NEXT_PAGE_OFFSET);
+
+	sbl_dev_dbg(sbl->dev, "%d next, complete (%lld), state (%lld) (%s), received (%lld) , base page (%lld), lp (%lld), lp_next (%lld) ",
+		    port_num,
+			SBL_PML_STS_PCS_AUTONEG_NEXT_PAGE_COMPLETE_GET(val64),
+			SBL_PML_STS_PCS_AUTONEG_NEXT_PAGE_STATE_GET(val64),
+			sbl_an_get_sm_state(sbl, port_num),
+			SBL_PML_STS_PCS_AUTONEG_NEXT_PAGE_PAGE_RECEIVED_GET(val64),
+			SBL_PML_STS_PCS_AUTONEG_NEXT_PAGE_BASE_PAGE_GET(val64),
+			SBL_PML_STS_PCS_AUTONEG_NEXT_PAGE_LP_ABILITY_GET(val64),
+			SBL_PML_STS_PCS_AUTONEG_NEXT_PAGE_LP_NEXT_PAGE_GET(val64));
+
+	sbl_dev_dbg(sbl->dev, "an %d: dump: sts an next pg 0x%llx", port_num, val64);
+
+	for (i = 0; i < link->an_tx_count; ++i) {
+		sbl_dev_dbg(sbl->dev, "an %d: dump: tx pg %d: 0x%llx", port_num,
+			    i, link->an_tx_page[i]);
+	}
+	for (i = 0; i < link->an_rx_count; ++i) {
+		sbl_dev_dbg(sbl->dev, "an %d: dump: rx pg %d: 0x%llx", port_num,
+			    i, link->an_rx_page[i]);
+	}
+}
diff --git a/drivers/net/ethernet/hpe/sbl/sbl_link_an_nic.c b/drivers/net/ethernet/hpe/sbl/sbl_link_an_nic.c
new file mode 100644
index 000000000000..e9536283c47a
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sbl/sbl_link_an_nic.c
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/random.h>
+#include <linux/delay.h>
+
+#include <linux/hpe/sbl/sbl.h>
+#include <linux/hpe/sbl/sbl_an.h>
+
+#include <linux/hpe/sbl/sbl_pml.h>
+
+#include "sbl_pml_fn.h"
+#include "sbl_link.h"
+#include "sbl_serdes.h"
+#include "sbl_constants.h"
+#include "sbl_serdes_map.h"
+#include "sbl_internal.h"
+
+int sbl_an_page_exchange(struct sbl_inst *sbl, int port_num, unsigned long remaining_jiffies)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	int xcng_count = 1;
+	u64 sts_autoneg_next_reg;
+	u32 base = SBL_PML_BASE(port_num);
+	int err;
+
+	/* -- Interrupt based next page exchange sequence -- */
+	do {
+		/* Too many Rx pages ?*/
+		if (xcng_count >= SBL_AN_MAX_RX_PAGES) {
+			sbl_dev_err_ratelimited(sbl->dev, "an %d: rx next page: too many pages %d",
+						port_num, xcng_count);
+			sbl_an_dump_state(sbl, port_num);
+			return -EPROTO;
+		}
+
+		sbl_dev_dbg(sbl->dev, "an %d: next page %d: start", port_num, xcng_count);
+
+		if (sbl_base_link_start_cancelled(sbl, port_num))
+			return -ECANCELED;
+		if (sbl_start_timeout(sbl, port_num))
+			return -ETIMEDOUT;
+
+		/* setup the next page (real or null) */
+		if (xcng_count < link->an_tx_count)
+			sbl_an_setup_next_page(sbl, port_num, xcng_count);
+		else
+			sbl_an_setup_null_page(sbl, port_num);
+
+		/* setup and enable interrupt */
+		err = sbl_an_hw_wait_prepare(sbl, port_num);
+		if (err)
+			return err;
+
+		/* send the next page */
+		sbl_an_send_next_page(sbl, port_num);
+
+		/* wait for next page interrupt */
+		remaining_jiffies = wait_for_completion_timeout(&link->an_hw_change, remaining_jiffies);
+		if (sbl_base_link_start_cancelled(sbl, port_num))
+			return -ECANCELED;
+		if (!remaining_jiffies) {
+			sbl_dev_err(sbl->dev, "an %d: next page %d: exchange timeout", port_num, xcng_count);
+			sbl_an_dump_state(sbl, port_num);
+			return -ETIME;
+		}
+
+		/* check if received page is a next page */
+		if (!sbl_an_is_next_page(sbl, port_num)) {
+			sbl_dev_dbg_ratelimited(sbl->dev, "an %d: next page %d: missing next page indication, resend next-page",
+						port_num, xcng_count);
+			sbl_an_dump_state(sbl, port_num);
+			continue;
+
+		}
+
+		/* put the received page in the buffer if indicated */
+		if (link->an_rx_page[xcng_count - 1] & AN_NP_NP_MASK) {
+			sts_autoneg_next_reg = sbl_read64(sbl, base |
+						  SBL_PML_STS_PCS_AUTONEG_NEXT_PAGE_OFFSET);
+			link->an_rx_page[xcng_count] =
+				SBL_PML_STS_PCS_AUTONEG_NEXT_PAGE_LP_NEXT_PAGE_GET(sts_autoneg_next_reg);
+			sbl_dev_dbg(sbl->dev, "an %d: rx next page: 0x%llx",
+				    port_num, link->an_rx_page[xcng_count]);
+			link->an_rx_count++;
+		}
+
+		/* go to the additional next page */
+		xcng_count++;
+
+		/* check to see if the exchange is done */
+	} while (!sbl_an_next_is_complete(sbl, port_num));
+
+	return 0;
+}
+
+void sbl_an_version_read(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+
+	/* cassini version here */
+	/* TODO: Implement dynamic version detection from HW device tree or runtime detection.
+	 * Currently hardcoded to CASSINI_V1. Should query actual hardware version
+	 * during autonegotiation setup to properly report link partner capability.
+	 */
+	link->an_tx_page[2] |= ((SBL_LP_SUBTYPE_CASSINI_V1 & AN_LP_SUBTYPE_MASK) << AN_LP_SUBTYPE_BASE_BIT);
+}
diff --git a/drivers/net/ethernet/hpe/sbl/sbl_link_nic.c b/drivers/net/ethernet/hpe/sbl/sbl_link_nic.c
new file mode 100644
index 000000000000..2c0be275d019
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sbl/sbl_link_nic.c
@@ -0,0 +1,196 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+
+#include <linux/hpe/sbl/sbl.h>
+#include <linux/hpe/sbl/sbl_an.h>
+#include <linux/hpe/sbl/sbl_fec.h>
+#include <linux/hpe/sbl/sbl_kconfig.h>
+
+#include <linux/hpe/sbl/sbl_pml.h>
+
+#include "sbl_serdes_map.h"
+#include "sbl_pml_fn.h"
+#include "sbl_link.h"
+#include "sbl_serdes.h"
+#include "sbl_serdes_fn.h"
+#include "sbl_internal.h"
+
+/**
+ * sbl_link_get_fec_thresholds() - Get fec thresholds
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ * @ucw_bad: Pointer to an int where output is stored(ucw threshold value)
+ * @ccw_bad: Pointer to an int where output is stored(ccw threshold value)
+ * @fecl_warn: Pointer to an int where output is stored(warn threshold value)
+ *
+ * Get threshold values based on link mode used.
+ * @ucw_bad, @ucw_bad and @fecl_warn holds the values and
+ * returns through provided pointers to the caller.
+ *
+ * Return the failure and warning thresholds for fec metrics
+ * monitoring
+ *
+ * The ccw values used here corresponds to a BER of 1.e-4
+ * The ucw values correspond to a little less than 1e-10
+ * The single lane fec warning threshold is the ccw rate divided by
+ * the number of fec lanes in use for the mode.
+ *
+ *
+ * 200G LINK (BS) (CD)
+ *   212500000000 bits/second over a 4-lane link @ 200G
+ *   39062500 cw/s (5440 bits/codeword)
+ *
+ *   (Post)Pre-FEC BER
+ *  21250000.000000 (un)corrected cw/s => 1e-04 BER (1 bad bit per codeword)
+ *   2125000.000000 (un)corrected cw/s => 1e-05 BER
+ *    212500.000000 (un)corrected cw/s => 1e-06 BER
+ *     21250.000000 (un)corrected cw/s => 1e-07 BER
+ *      2125.000000 (un)corrected cw/s => 1e-08 BER
+ *       212.500000 (un)corrected cw/s => 1e-09 BER
+ *        21.250000 (un)corrected cw/s => 1e-10 BER
+ *         2.125000 (un)corrected cw/s => 1e-11 BER
+ *         0.212500 (un)corrected cw/s => 1e-12 BER
+ *         0.021250 (un)corrected cw/s => 1e-13 BER
+ *         0.002125 (un)corrected cw/s => 1e-13 BER
+ *
+ * 100G LINK (BJ)
+ *   103125000000 bits/second over a 4-lane link @ 100G
+ *   19531250 cw/s (5280 bits/codeword)
+ *
+ *   (Post) Pre-FEC BER
+ *   1031250.000000 (un)corrected cw/s => 1e-05 BER (1 bad bit per codeword)
+ *    103125.000000 (un)corrected cw/s => 1e-06 BER
+ *     10312.500000 (un)corrected cw/s => 1e-07 BER
+ *      1031.250000 (un)corrected cw/s => 1e-08 BER
+ *       103.125000 (un)corrected cw/s => 1e-09 BER
+ *        10.312500 (un)corrected cw/s => 1e-10 BER
+ *         1.031250 (un)corrected cw/s => 1e-11 BER
+ *         0.103125 (un)corrected cw/s => 1e-12 BER
+ *
+ * Cassini uses the old
+ *    sbl_link_get_fec_thresholds()
+ * Rosetta uses the newer
+ *    sbl_link_get_ucw_thresh_ieee()
+ *    sbl_link_get_ucw_thresh_hpe()
+ *    sbl_link_get_ccw_thresh_ieee()
+ *    sbl_link_get_ccw_thresh_hpe()
+ *
+ * Return: 0 on success, negative error code on failure
+ */
+int sbl_link_get_fec_thresholds(struct sbl_inst *sbl, int port_num,
+				int *ucw_bad, int *ccw_bad, int *fecl_warn)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	int ucw;
+	int ccw;
+	int warn;
+
+	if (link->sstate != SBL_SERDES_STATUS_RUNNING)
+		return -ENAVAIL;
+
+	switch (link->link_mode) {
+	case SBL_LINK_MODE_BS_200G:
+		ucw = 21;
+		ccw = 21250000;
+		warn = ccw / 8;
+		break;
+	case SBL_LINK_MODE_BJ_100G:
+		ucw = 11;
+		ccw = 10312500;
+		warn = ccw / 8;
+		break;
+	case SBL_LINK_MODE_CD_100G:
+		ucw = 11;
+		ccw = 10625000;
+		warn = ccw / 4;
+		break;
+	case SBL_LINK_MODE_CD_50G:
+		ucw = 5;
+		ccw = 5312500;
+		warn = ccw / 2;
+		break;
+	default:
+		sbl_dev_err(sbl->dev, "%d: bad mode for fec thresh", port_num);
+		return -ENAVAIL;
+	}
+
+	if (ucw_bad)
+		*ucw_bad = ucw;
+	if (ccw_bad)
+		*ccw_bad = ccw;
+	if (fecl_warn)
+		*fecl_warn = warn;
+
+	return 0;
+}
+EXPORT_SYMBOL(sbl_link_get_fec_thresholds);
+
+#ifdef CONFIG_SYSFS
+/**
+ * sbl_base_link_llr_sysfs_sprint() - Report LLR on/off status into buffer
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ * @buf: Destination buffer to write the data
+ * @size: Size of @buf in bytes, the output is truncated to fit
+ *
+ * This function checks the state info flags of LLR.
+ * Based on this flag, it formats the string indicating
+ * whether LLR is on/off and writes it into provided buffer
+ *
+ * Context: Process context, Acquires lock and release link->lock <spin_lock>
+ *
+ * Return: Number of characters written, at most @size - 1
+ */
+int sbl_base_link_llr_sysfs_sprint(struct sbl_inst *sbl, int port_num, char *buf, size_t size)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	int s = 0;
+
+	spin_lock(&link->lock);
+
+	if (READ_ONCE(link->link_info) & SBL_LINK_INFO_LLR_RUN)
+		s += scnprintf(buf + s, size - s, "on");
+	else
+		s += scnprintf(buf + s, size - s, "off");
+
+	spin_unlock(&link->lock);
+
+	return s;
+}
+EXPORT_SYMBOL(sbl_base_link_llr_sysfs_sprint);
+
+/**
+ * sbl_base_link_loopback_sysfs_sprint() - Report loopback mode status into buffer
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ * @buf: Destination buffer to write the data
+ * @size: Size of @buf in bytes, the output is truncated to fit
+ *
+ * This function gets the loopback mode status and
+ * formats the string into the provided buffer
+ *
+ * Context: Process context, Acquires lock and release link->lock <spin_lock>
+ *
+ * Return: Number of characters written, at most @size - 1
+ */
+int sbl_base_link_loopback_sysfs_sprint(struct sbl_inst *sbl, int port_num, char *buf, size_t size)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	int s = 0;
+
+	spin_lock(&link->lock);
+
+	s += scnprintf(buf + s, size - s, sbl_loopback_mode_str(link->loopback_mode));
+
+	spin_unlock(&link->lock);
+
+	return s;
+}
+EXPORT_SYMBOL(sbl_base_link_loopback_sysfs_sprint);
+#endif

-- 
2.56.0


^ permalink raw reply	[flat|nested] 25+ messages in thread
* [PATCH 07/23] net: hpe: sbl: add the SBM serial bus layer
  2026-10-30 20:58 [PATCH 00/23] Subject: [PATCH net-next 00/23] net/hpe: add HPE Slingshot NIC drivers Doug Ledford
                   ` (5 preceding siblings ...)
  2026-10-30 20:59 ` [PATCH 06/23] net: hpe: sbl: add link state management Doug Ledford
@ 2026-10-30 20:59 ` Doug Ledford
  2026-10-30 20:59 ` [PATCH 08/23] net: hpe: sbl: add media, FEC and counter support Doug Ledford
                   ` (16 subsequent siblings)
  23 siblings, 0 replies; 25+ messages in thread
From: Doug Ledford @ 2026-10-30 20:59 UTC (permalink / raw)
  To: Slingshot Open Source Team, Nathan Chancellor, Nicolas Schier,
	Richard Cochran, Andrew Lunn, David S. Miller, Eric Dumazet,
	Jakub Kicinski, Paolo Abeni, Sumit Semwal, Christian König,
	Guenter Roeck
  Cc: linux-kernel, netdev, linux-kbuild, Doug Ledford

Add the SBM (serial bus master) layer used to reach SerDes and PMI
registers, and its NIC specific SerDes accessors.

checkpatch --strict (100 columns) still reports the following in this
patch. They need coordination with the internal repositories this code
is maintained in and will be fixed in V2:
- WARNING: BLOCK_COMMENT_STYLE (2), LONG_LINE_STRING (2), LONG_LINE (1),
  TYPO_SPELLING (1)
- CHECK: UNNECESSARY_PARENTHESES (16), BRACES (3), COMPARISON_TO_NULL
  (1)

Signed-off-by: Doug Ledford <doug.ledford@hpe.com>
---
 drivers/net/ethernet/hpe/sbl/sbl_sbm_serdes.c     | 1114 +++++++++++++++++++++
 drivers/net/ethernet/hpe/sbl/sbl_sbm_serdes_nic.c |  138 +++
 2 files changed, 1252 insertions(+)

diff --git a/drivers/net/ethernet/hpe/sbl/sbl_sbm_serdes.c b/drivers/net/ethernet/hpe/sbl/sbl_sbm_serdes.c
new file mode 100644
index 000000000000..1d1c4d01e159
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sbl/sbl_sbm_serdes.c
@@ -0,0 +1,1114 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* Copyright 2025-2026 Hewlett Packard Enterprise Development LP. All Rights Reserved. */
+
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+
+#include <uapi/ethernet/sbl_sbm_constants.h>
+
+#include "sbl_sbm_serdes.h"
+#include "sbl_serdes_map.h"
+#include "sbl_sbm.h"
+
+static void
+sbus_reg_addr_to_string(u32 sbus_addr, u8 reg_addr, char *reg_addr_str)
+{
+	if (is_sbm_spico_addr(sbus_addr)) {
+		switch (reg_addr) {
+		case SPICO_SBR_ADDR_SRAM_BIST:
+			sprintf(reg_addr_str, "SRAM_BIST");
+			break;
+		case SPICO_SBR_ADDR_CTL:
+			sprintf(reg_addr_str, "CTL");
+			break;
+		case SPICO_SBR_ADDR_DMEM_IN:
+			sprintf(reg_addr_str, "DMEM_IN");
+			break;
+		case SPICO_SBR_ADDR_IMEM:
+			sprintf(reg_addr_str, "IMEM");
+			break;
+		case SPICO_SBR_ADDR_DMEM:
+			sprintf(reg_addr_str, "DMEM");
+			break;
+		case SPICO_SBR_ADDR_STEP_BP:
+			sprintf(reg_addr_str, "STEP_BP");
+			break;
+		case SPICO_SBR_ADDR_BP_ADDR:
+			sprintf(reg_addr_str, "BP_ADDR");
+			break;
+		case SPICO_SBR_ADDR_INTR:
+			sprintf(reg_addr_str, "INTR");
+			break;
+		case SPICO_SBR_ADDR_DMEM_OUT:
+			sprintf(reg_addr_str, "DMEM_OUT");
+			break;
+		case SPICO_SBR_ADDR_RDATA:
+			sprintf(reg_addr_str, "RDATA");
+			break;
+		case SPICO_SBR_ADDR_PC:
+			sprintf(reg_addr_str, "PC");
+			break;
+		case SPICO_SBR_ADDR_PC_OVERRIDE:
+			sprintf(reg_addr_str, "PC_OVERRIDE");
+			break;
+		case SPICO_SBR_ADDR_FLAG:
+			sprintf(reg_addr_str, "FLAG");
+			break;
+		case SPICO_SBR_ADDR_OP:
+			sprintf(reg_addr_str, "OP");
+			break;
+		case SPICO_SBR_ADDR_SP_EC:
+			sprintf(reg_addr_str, "SP_EC");
+			break;
+		case SPICO_SBR_ADDR_STATE:
+			sprintf(reg_addr_str, "STATE");
+			break;
+		case SPICO_SBR_ADDR_RESULT:
+			sprintf(reg_addr_str, "RESULT");
+			break;
+		case SPICO_SBR_ADDR_A_B_REG:
+			sprintf(reg_addr_str, "A_B_REG");
+			break;
+		case SPICO_SBR_ADDR_IMEM_BURST_DATA:
+			sprintf(reg_addr_str, "IMEM_BURST_DATA");
+			break;
+		case SPICO_SBR_ADDR_IMEM_BURST_ADDR:
+			sprintf(reg_addr_str, "IMEM_BURST_ADDR");
+			break;
+		case SPICO_SBR_ADDR_ECC:
+			sprintf(reg_addr_str, "ECC");
+			break;
+		case SPICO_SBR_ADDR_UNNAMED_0:
+			sprintf(reg_addr_str, "UNNAMED_0");
+			break;
+		case SPICO_SBR_ADDR_UNNAMED_1:
+			sprintf(reg_addr_str, "UNNAMED_1");
+			break;
+		case SPICO_SBR_ADDR_UNNAMED_2:
+			sprintf(reg_addr_str, "UNNAMED_2");
+			break;
+		case SPICO_SBR_ADDR_UNNAMED_3:
+			sprintf(reg_addr_str, "UNNAMED_3");
+			break;
+		case SPICO_SBR_ADDR_UNNAMED_4:
+			sprintf(reg_addr_str, "UNNAMED_4");
+			break;
+		default:
+			sprintf(reg_addr_str, "SPICO_SBR_UNKNOWN");
+			break;
+		}
+	} else if (is_sbm_crm_addr(sbus_addr)) {
+		switch (reg_addr) {
+		case SBM_CRM_ADDR_CISM0:
+			sprintf(reg_addr_str, "CISM0");
+			break;
+		case SBM_CRM_ADDR_CISM1:
+			sprintf(reg_addr_str, "CISM1");
+			break;
+		case SBM_CRM_ADDR_LAST_ADDR:
+			sprintf(reg_addr_str, "LAST_ADDR");
+			break;
+		case SBM_CRM_ADDR_CLK_DIV:
+			sprintf(reg_addr_str, "CLK_DIV");
+			break;
+		case SBM_CRM_ADDR_CLK_DIV_RST:
+			sprintf(reg_addr_str, "CLK_DIV_RST");
+			break;
+		case SBM_CRM_ADDR_CLK_DIV_RST_P0:
+			sprintf(reg_addr_str, "CLK_DIV_RST_P0");
+			break;
+		case SBM_CRM_ADDR_CLK_DIV_RST_P1:
+			sprintf(reg_addr_str, "CLK_DIV_RST_P1");
+			break;
+		case SBM_CRM_ADDR_CISM_RX_ADDR:
+			sprintf(reg_addr_str, "CISM_RX_ADDR");
+			break;
+		case SBM_CRM_ADDR_CISM_CMD1:
+			sprintf(reg_addr_str, "CISM_CMD1");
+			break;
+		case SBM_CRM_ADDR_CISM_DATA_ADDR1:
+			sprintf(reg_addr_str, "CISM_DATA_ADDR1");
+			break;
+		case SBM_CRM_ADDR_CISM_DATA_WORD1:
+			sprintf(reg_addr_str, "CISM_DATA_WORD1");
+			break;
+		case SBM_CRM_ADDR_CISM_CMD2:
+			sprintf(reg_addr_str, "CISM_CMD2");
+			break;
+		case SBM_CRM_ADDR_CISM_DATA_ADDR2:
+			sprintf(reg_addr_str, "CISM_DATA_ADDR2");
+			break;
+		case SBM_CRM_ADDR_CISM_DATA_WORD2:
+			sprintf(reg_addr_str, "CISM_DATA_WORD2");
+			break;
+		case SBM_CRM_ADDR_DATA_OUT_SEL:
+			sprintf(reg_addr_str, "DATA_OUT_SEL");
+			break;
+		case SBM_CRM_ADDR_BIST:
+			sprintf(reg_addr_str, "BIST");
+			break;
+		case SBM_CRM_ADDR_ROM_EN:
+			sprintf(reg_addr_str, "ROM_EN");
+			break;
+		case SBM_CRM_ADDR_ROM_FAILED_ADDR:
+			sprintf(reg_addr_str, "ROM_FAILED_ADDR");
+			break;
+		case SBM_CRM_ADDR_ROM_DATA_VAL_CNT:
+			sprintf(reg_addr_str, "ROM_DATA_VAL_CNT");
+			break;
+		case SBM_CRM_ADDR_ROM_ACK:
+			sprintf(reg_addr_str, "ROM_ACK");
+			break;
+		case SBM_CRM_ADDR_ROM_STOP_ADDR:
+			sprintf(reg_addr_str, "ROM_STOP_ADDR");
+			break;
+		case SBM_CRM_ADDR_ROM_OUTPUT:
+			sprintf(reg_addr_str, "ROM_OUTPUT");
+			break;
+		case SBM_CRM_ADDR_ROM_DATA0:
+			sprintf(reg_addr_str, "ROM_DATA0");
+			break;
+		case SBM_CRM_ADDR_ROM_DATA1:
+			sprintf(reg_addr_str, "ROM_DATA1");
+			break;
+		case SBM_CRM_ADDR_CLK_HALT:
+			sprintf(reg_addr_str, "CLK_HALT");
+			break;
+		case SBM_CRM_ADDR_GEN_WRITE:
+			sprintf(reg_addr_str, "GEN_WRITE");
+			break;
+		case SBM_CRM_ADDR_GEN_READ:
+			sprintf(reg_addr_str, "GEN_READ");
+			break;
+		case SBM_CRM_ADDR_GEN_WRITE_P0:
+			sprintf(reg_addr_str, "GEN_WRITE_P0");
+			break;
+		case SBM_CRM_ADDR_GEN_WRITE_P1:
+			sprintf(reg_addr_str, "GEN_WRITE_P1");
+			break;
+		case SBM_CRM_ADDR_GEN_WRITE_P2:
+			sprintf(reg_addr_str, "GEN_WRITE_P2");
+			break;
+		case SBM_CRM_ADDR_GEN_WRITE_P3:
+			sprintf(reg_addr_str, "GEN_WRITE_P3");
+			break;
+		case SBM_CRM_ADDR_GEN_READ_P0:
+			sprintf(reg_addr_str, "GEN_READ_P0");
+			break;
+		case SBM_CRM_ADDR_GEN_READ_P1:
+			sprintf(reg_addr_str, "GEN_READ_P1");
+			break;
+		case SBM_CRM_ADDR_GEN_READ_P2:
+			sprintf(reg_addr_str, "GEN_READ_P2");
+			break;
+		case SBM_CRM_ADDR_GEN_READ_P3:
+			sprintf(reg_addr_str, "GEN_READ_P3");
+			break;
+		case SBM_CRM_ADDR_SBUS_ID:
+			sprintf(reg_addr_str, "SBUS_ID");
+			break;
+		case SBM_CRM_ADDR_IP_IDCODE:
+			sprintf(reg_addr_str, "IP_IDCODE");
+			break;
+		default:
+			sprintf(reg_addr_str, "SBM_CRM_UNKNOWN");
+			break;
+		}
+	} else if (is_cm4_serdes_addr(sbus_addr)) {
+		switch (reg_addr) {
+		case SPICO_SERDES_ADDR_IMEM:
+			sprintf(reg_addr_str, "IMEM");
+			break;
+		case SPICO_SERDES_ADDR_INTR0:
+			sprintf(reg_addr_str, "INTR0");
+			break;
+		case SPICO_SERDES_ADDR_INTR1:
+			sprintf(reg_addr_str, "INTR1");
+			break;
+		case SPICO_SERDES_ADDR_RESET_EN:
+			sprintf(reg_addr_str, "RESET_EN");
+			break;
+		case SPICO_SERDES_ADDR_INTR_DIS:
+			sprintf(reg_addr_str, "INTR_DIS");
+			break;
+		case SPICO_SERDES_ADDR_BIST:
+			sprintf(reg_addr_str, "BIST");
+			break;
+		case SPICO_SERDES_ADDR_IMEM_BURST:
+			sprintf(reg_addr_str, "IMEM_BURST");
+			break;
+		case SPICO_SERDES_ADDR_ECC:
+			sprintf(reg_addr_str, "ECC");
+			break;
+		case SPICO_SERDES_ADDR_ECCLOG:
+			sprintf(reg_addr_str, "ECCLOG");
+			break;
+		case SPICO_SERDES_ADDR_BCAST:
+			sprintf(reg_addr_str, "BCAST");
+			break;
+		case SPICO_SERDES_ADDR_IP_IDCODE:
+			sprintf(reg_addr_str, "IP_IDCODE");
+			break;
+		default:
+			sprintf(reg_addr_str, "UNKNOWN");
+			break;
+		}
+	} else {
+		sprintf(reg_addr_str, "UNKNOWN");
+	}
+}
+
+static void
+sbus_cmd_to_string(u8 command, char *cmd_str)
+{
+	char str0[SBL_MAX_STR_LEN], str1[SBL_MAX_STR_LEN], str2[SBL_MAX_STR_LEN];
+
+	switch (command & SBUS_CMD_MODE_MASK) {
+	case SBUS_CMD_MODE_CTLR:
+		sprintf(str0, "CM_CTLR");
+		break;
+	case SBUS_CMD_MODE_RCVR:
+		sprintf(str0, "CM_RCVR");
+		break;
+	default:
+		sprintf(str0, "CM_UNKNOWN");
+		break;
+	}
+	switch (command & SBUS_IFACE_DST_MASK) {
+	case SBUS_IFACE_DST_TAP:
+		sprintf(str1, "ID_TAP");
+		break;
+	case SBUS_IFACE_DST_CORE:
+		sprintf(str1, "ID_CORE");
+		break;
+	case SBUS_IFACE_DST_SPICO:
+		sprintf(str1, "ID_SPICO");
+		break;
+	case SBUS_IFACE_DST_SPARE:
+		sprintf(str1, "ID_SPARE");
+		break;
+	default:
+		sprintf(str1, "ID_UNKNOWN");
+		break;
+	}
+	switch (command & SBUS_CMD_MASK) {
+	case SBUS_CMD_RESET:
+		sprintf(str2, "CMD_RESET");
+		break;
+	case SBUS_CMD_WRITE:
+		sprintf(str2, "CMD_WRITE");
+		break;
+	case SBUS_CMD_READ:
+		sprintf(str2, "CMD_READ");
+		break;
+	case SBUS_CMD_READ_RESULT:
+		sprintf(str2, "CMD_READ_RESULT");
+		break;
+	default:
+		sprintf(str2, "CMD_UNKNOWN");
+		break;
+	}
+	sprintf(cmd_str, "%s:%s:%s", str0, str1, str2);
+}
+
+static void
+sbus_result_code_to_string(u8 result_code, char *rc_string)
+{
+	switch (result_code) {
+	case SBUS_RC_RESET:
+		sprintf(rc_string, "RESET");
+		break;
+	case SBUS_RC_WRITE_COMPLETE:
+		sprintf(rc_string, "WRITE_COMPLETE");
+		break;
+	case SBUS_RC_WRITE_FAILED:
+		sprintf(rc_string, "WRITE_FAILED");
+		break;
+	case SBUS_RC_READ_ALL_COMPLETE:
+		sprintf(rc_string, "READ_ALL_COMPLETE");
+		break;
+	case SBUS_RC_READ_COMPLETE:
+		sprintf(rc_string, "READ_COMPLETE");
+		break;
+	case SBUS_RC_READ_FAILED:
+		sprintf(rc_string, "READ_FAILED");
+		break;
+	case SBUS_RC_CMD_ISSUE_DONE:
+		sprintf(rc_string, "CMD_ISSUE_DONE");
+		break;
+	case SBUS_RC_MODE_CHANGE_COMPLETE:
+		sprintf(rc_string, "MODE_CHANGE_COMPLETE");
+		break;
+	default:
+		sprintf(rc_string, "UNKNOWN");
+		break;
+	}
+}
+
+static void
+spico_interrupt_to_string(u32 sbus_addr, u16 interrupt, char *intr_str)
+{
+	if (is_sbm_spico_addr(sbus_addr)) {
+		switch (interrupt) {
+		case SPICO_INT_SBMS_REV_ID:
+			sprintf(intr_str, "SBMS_REV_ID");
+			break;
+		case SPICO_INT_SBMS_BUILD_ID:
+			sprintf(intr_str, "SBMS_BUILD_ID");
+			break;
+		case SPICO_INT_SBMS_DO_CRC:
+			sprintf(intr_str, "SBMS_DO_CRC");
+			break;
+		case SPICO_INT_SBMS_READ_DMEM_VAL:
+			sprintf(intr_str, "SBMS_READ_DMEM_VAL");
+			break;
+		case SPICO_INT_SBMS_DO_XDMEM_CRC:
+			sprintf(intr_str, "SBMS_DO_XDMEM_CRC");
+			break;
+		case SPICO_INT_SBMS_GET_PMRO_DATA:
+			sprintf(intr_str, "SBMS_GET_PMRO_DATA");
+			break;
+		case SPICO_INT_SBMS_GET_TEMP_DATA:
+			sprintf(intr_str, "SBMS_GET_TEMP_DATA");
+			break;
+		case SPICO_INT_SBMS_GET_VOLT_DATA:
+			sprintf(intr_str, "SBMS_GET_VOLT_DATA");
+			break;
+		case SPICO_INT_SBMS_IMEM_CRC_CHECK:
+			sprintf(intr_str, "SBMS_IMEM_CRC_CHECK");
+			break;
+		case SPICO_INT_SBMS_IMEM_SWP_SA:
+			sprintf(intr_str, "SBMS_IMEM_SWP_SA");
+			break;
+		case SPICO_INT_SBMS_PCIE3_SWP:
+			sprintf(intr_str, "SBMS_PCIE3_SWP");
+			break;
+		case SPICO_INT_SBMS_DRMON_SETUP:
+			sprintf(intr_str, "SBMS_DRMON_SETUP");
+			break;
+		case SPICO_INT_SBMS_TEMP_SETUP:
+			sprintf(intr_str, "SBMS_TEMP_SETUP");
+			break;
+		case SPICO_INT_SBMS_RR_PCAL:
+			sprintf(intr_str, "SBMS_RR_PCAL");
+			break;
+		default:
+			if ((interrupt >= SPICO_INT_SBMS_DDR_HMB_FIRST) &&
+			    (interrupt <= SPICO_INT_SBMS_DDR_HMB_LAST)) {
+				sprintf(intr_str, "SBMS_DDR_HMB");
+			} else {
+				sprintf(intr_str, "SBMS_UNKNOWN");
+			}
+			break;
+		}
+	} else if (is_cm4_serdes_addr(sbus_addr)) {
+		switch (interrupt) {
+		case SPICO_INT_CM4_REV_ID:
+			sprintf(intr_str, "CM4_REV_ID");
+			break;
+		case SPICO_INT_CM4_SERDES_EN:
+			sprintf(intr_str, "CM4_SERDES_EN");
+			break;
+		case SPICO_INT_CM4_PRBS_CTRL:
+			sprintf(intr_str, "CM4_PRBS_CTRL");
+			break;
+		case SPICO_INT_CM4_COMPARE_CTRL:
+			sprintf(intr_str, "CM4_COMPARE_CTRL");
+			break;
+		case SPICO_INT_CM4_PMD_CTRL:
+			sprintf(intr_str, "CM4_PMD_CTRL");
+			break;
+		case SPICO_INT_CM4_TX_BAUD:
+			sprintf(intr_str, "CM4_TX_BAUD");
+			break;
+		case SPICO_INT_CM4_RX_BAUD:
+			sprintf(intr_str, "CM4_RX_BAUD");
+			break;
+		case SPICO_INT_CM4_AN_CONFIG:
+			sprintf(intr_str, "CM4_AN_CONFIG");
+			break;
+		case SPICO_INT_CM4_LOOPBACK:
+			sprintf(intr_str, "CM4_LOOPBACK");
+			break;
+		case SPICO_INT_CM4_DFE_CTRL:
+			sprintf(intr_str, "CM4_DFE_CTRL");
+			break;
+		case SPICO_INT_CM4_TX_PHASE_CAL:
+			sprintf(intr_str, "CM4_TX_PHASE_CAL");
+			break;
+		case SPICO_INT_CM4_BIT_SLIP:
+			sprintf(intr_str, "CM4_BIT_SLIP");
+			break;
+		case SPICO_INT_CM4_TX_PHASE_SLIP:
+			sprintf(intr_str, "CM4_TX_PHASE_SLIP");
+			break;
+		case SPICO_INT_CM4_RX_PHASE_SLIP:
+			sprintf(intr_str, "CM4_RX_PHASE_SLIP");
+			break;
+		case SPICO_INT_CM4_PCIE_PD:
+			sprintf(intr_str, "CM4_PCIE_PD");
+			break;
+		case SPICO_INT_CM4_PLL_RECAL:
+			sprintf(intr_str, "CM4_PLL_RECAL");
+			break;
+		case SPICO_INT_CM4_SAS_APTA_CTRL:
+			sprintf(intr_str, "CM4_SAS_APTA_CTRL");
+			break;
+		case SPICO_INT_CM4_POLARITY_CTRL:
+			sprintf(intr_str, "CM4_POLARITY_CTRL");
+			break;
+		case SPICO_INT_CM4_WIDTH_MODE:
+			sprintf(intr_str, "CM4_WIDTH_MODE");
+			break;
+		case SPICO_INT_CM4_TXEQ_LOAD:
+			sprintf(intr_str, "CM4_TXEQ_LOAD");
+			break;
+		case SPICO_INT_CM4_ERROR_RST:
+			sprintf(intr_str, "CM4_ERROR_RST");
+			break;
+		case SPICO_INT_CM4_BIG_REG_SEL:
+			sprintf(intr_str, "CM4_BIG_REG_SEL");
+			break;
+		case SPICO_INT_CM4_BIG_REG_WR:
+			sprintf(intr_str, "CM4_BIG_REG_WR");
+			break;
+		case SPICO_INT_CM4_BIG_REG_RD:
+			sprintf(intr_str, "CM4_BIG_REG_RD");
+			break;
+		case SPICO_INT_CM4_ERR_INJECT:
+			sprintf(intr_str, "CM4_ERR_INJECT");
+			break;
+		case SPICO_INT_CM4_DO_DATA_CAP:
+			sprintf(intr_str, "CM4_DO_DATA_CAP");
+			break;
+		case SPICO_INT_CM4_WAIT_TTD:
+			sprintf(intr_str, "CM4_WAIT_TTD");
+			break;
+		case SPICO_INT_CM4_ERR_STS:
+			sprintf(intr_str, "CM4_ERR_STS");
+			break;
+		case SPICO_INT_CM4_ERR_TIMER_STS:
+			sprintf(intr_str, "CM4_ERR_TIMER_STS");
+			break;
+		case SPICO_INT_CM4_PCIE_SLICES:
+			sprintf(intr_str, "CM4_PCIE_SLICES");
+			break;
+		case SPICO_INT_CM4_PCIE3_RX_EQ:
+			sprintf(intr_str, "CM4_PCIE3_RX_EQ");
+			break;
+		case SPICO_INT_CM4_SET_RX_EQ:
+			sprintf(intr_str, "CM4_SET_RX_EQ");
+			break;
+		case SPICO_INT_CM4_GET_RX_EQ:
+			sprintf(intr_str, "CM4_GET_RX_EQ");
+			break;
+		case SPICO_INT_CM4_CORE_TO_CNTL_EN:
+			sprintf(intr_str, "CM4_CORE_TO_CNTL_EN");
+			break;
+		case SPICO_INT_CM4_AN_DME_PAGE:
+			sprintf(intr_str, "CM4_AN_DME_PAGE");
+			break;
+		case SPICO_INT_CM4_INT_RX_TERM:
+			sprintf(intr_str, "CM4_INT_RX_TERM");
+			break;
+		case SPICO_INT_CM4_HAL_READ:
+			sprintf(intr_str, "CM4_HAL_READ");
+			break;
+		case SPICO_INT_CM4_HAL_WRITE:
+			sprintf(intr_str, "CM4_HAL_WRITE");
+			break;
+		case SPICO_INT_CM4_HAL_CALL:
+			sprintf(intr_str, "CM4_HAL_CALL");
+			break;
+		case SPICO_INT_CM4_SPICO_CLK_SWP:
+			sprintf(intr_str, "CM4_SPICO_CLK_SWP");
+			break;
+		case SPICO_INT_CM4_PCIE3_TX_MRG1:
+			sprintf(intr_str, "CM4_PCIE3_TX_MRG1");
+			break;
+		case SPICO_INT_CM4_PCIE3_TX_MRG2:
+			sprintf(intr_str, "CM4_PCIE3_TX_MRG2");
+			break;
+		case SPICO_INT_CM4_PCIE3_TX_MRG3:
+			sprintf(intr_str, "CM4_PCIE3_TX_MRG3");
+			break;
+		case SPICO_INT_CM4_PCIE3_TX_MRG4:
+			sprintf(intr_str, "CM4_PCIE3_TX_MRG4");
+			break;
+		case SPICO_INT_CM4_PCIE3_TX_MRG5:
+			sprintf(intr_str, "CM4_PCIE3_TX_MRG5");
+			break;
+		case SPICO_INT_CM4_PROC_RESET:
+			sprintf(intr_str, "CM4_PROC_RESET");
+			break;
+		case SPICO_INT_CM4_PCIE_SWP_SETUP:
+			sprintf(intr_str, "CM4_PCIE_SWP_SETUP");
+			break;
+		case SPICO_INT_CM4_IP_STAT_INFO:
+			sprintf(intr_str, "CM4_IP_STAT_INFO");
+			break;
+		case SPICO_INT_CM4_CRC:
+			sprintf(intr_str, "CM4_CRC");
+			break;
+		case SPICO_INT_CM4_PMD_CONFIG:
+			sprintf(intr_str, "CM4_PMD_CONFIG");
+			break;
+		case SPICO_INT_CM4_BUILD_ID:
+			sprintf(intr_str, "CM4_BUILD_ID");
+			break;
+		case SPICO_INT_CM4_O_CORE_STS_15_0:
+			sprintf(intr_str, "CM4_O_CORE_STS_15_0");
+			break;
+		case SPICO_INT_CM4_O_CORE_STS_31_16:
+			sprintf(intr_str, "CM4_O_CORE_STS_31_16");
+			break;
+		default:
+			if (interrupt & SPICO_INT_CM4_MEM_READ) {
+				sprintf(intr_str, "CM4_MEM_READ_0x%03X",
+					interrupt & ~SPICO_INT_CM4_MEM_READ);
+			} else if (interrupt & SPICO_INT_CM4_MEM_WRITE) {
+				sprintf(intr_str, "CM4_MEM_WRITE_0x%03X",
+					interrupt & ~SPICO_INT_CM4_MEM_WRITE);
+			} else {
+				sprintf(intr_str, "CM4_UNKNOWN");
+			}
+			break;
+		}
+	} else {
+		sprintf(intr_str, "UNKNOWN");
+	}
+}
+
+static void sbus_msg_print(void *inst, int severity, const char *message)
+{
+	struct sbl_inst *sbl = inst;
+
+	if (!sbl || !message)
+		return;
+	if (severity >= LEVEL_ERR)
+		SBL_ERR(sbl->dev, "%s", message);
+	else if (severity >= LEVEL_WARN)
+		SBL_WARN(sbl->dev, "%s", message);
+	else if (severity >= LEVEL_INFO)
+		SBL_INFO(sbl->dev, "%s", message);
+	else
+		SBL_TRACE1(sbl->dev, "%s", message);
+}
+
+static void sbus_msg(void *inst, u32 sbus_addr, u32 req_data,
+		     u8 reg_addr, u8 command, u32 rsp_data,
+		u8 result_code, u8 overrun, int timeout,
+		u32 flags, int rc, int severity)
+{
+	struct sbl_inst *sbl = inst;
+	char sbus_addr_str[SBL_HALF_MAX_STR_LEN];
+	char reg_addr_str[SBL_HALF_MAX_STR_LEN];
+	char cmd_str[SBL_HALF_MAX_STR_LEN];
+	char rc_str[SBL_HALF_MAX_STR_LEN];
+	char message[SBL_MAX_STR_LEN];
+
+	if (!sbl)
+		return;
+
+	sbus_addr_to_string(sbus_addr, sbus_addr_str);
+	sbus_reg_addr_to_string(sbus_addr, reg_addr, reg_addr_str);
+	sbus_cmd_to_string(command, cmd_str);
+	sbus_result_code_to_string(result_code, rc_str);
+
+	snprintf(message, SBL_MAX_STR_LEN, "SBUS_OP: addr:0x%03x(%-20s) req_data:0x%08x reg_addr:0x%04x(%-15s)",
+		 sbus_addr, sbus_addr_str, req_data, reg_addr, reg_addr_str);
+	sbus_msg_print(inst, severity, message);
+
+	snprintf(message, SBL_MAX_STR_LEN, "SBUS_OP: command:0x%02x(%-24s), rsp_data:0x%08x result_code:0x%01x(%-14s)",
+		 command, cmd_str, rsp_data, result_code, rc_str);
+	sbus_msg_print(inst, severity, message);
+
+	snprintf(message, SBL_MAX_STR_LEN, "SBUS_OP: overrun:%d timeout:0x%04x flags:0x%04x rc:%d",
+		 overrun, timeout, flags, rc);
+	sbus_msg_print(inst, severity, message);
+}
+
+/**
+ * sbl_sbus_wr() - Write to sbus
+ * @inst: Generic pointer used by various frameworks
+ * @sbus_addr: address describing a serdes ring and rxaddr
+ * @reg_addr: target sbus register address
+ * @sbus_data: target sbus data
+ *
+ * Convenience function to issue an SBus op and check the result_code
+ *
+ * Return: 0 on success, negative error code on failure
+ */
+int sbl_sbus_wr(void *inst, u32 sbus_addr, u8 reg_addr,
+		u32 sbus_data)
+{
+	struct sbl_inst *sbl = inst;
+	u32 unused;
+
+	return sbl_sbus_op_aux(sbl, sbus_addr, reg_addr, SBUS_IFACE_DST_CORE |
+			       SBUS_CMD_WRITE, sbus_data, &unused);
+}
+EXPORT_SYMBOL(sbl_sbus_wr);
+
+/**
+ * sbl_sbus_rd() - Read from sbus
+ * @inst: Generic pointer used by various frameworks
+ * @sbus_addr: address describing a serdes ring and rxaddr
+ * @reg_addr: target sbus register address
+ * @result: location to store result of command
+ *
+ * Convenience function to issue an SBus op and check the result_code
+ *
+ * Return: 0 on success, negative error code on failure
+ */
+int sbl_sbus_rd(void *inst, u32 sbus_addr, u8 reg_addr,
+		u32 *result)
+{
+	struct sbl_inst *sbl = inst;
+
+	return sbl_sbus_op_aux(sbl, sbus_addr, reg_addr, SBUS_IFACE_DST_CORE |
+			       SBUS_CMD_READ, 0, result);
+}
+EXPORT_SYMBOL(sbl_sbus_rd);
+
+int sbl_serdes_mem_rd(void *inst, u32 port_num, u32 serdes,
+		      u32 addr, u16 *data)
+{
+	struct sbl_inst *sbl = inst;
+	int err;
+
+	SBL_TRACE2(sbl->dev, "p%ds%d: addr:0x%x", port_num, serdes, addr);
+	addr &= SPICO_INT_MEM_READ_ADDR_MASK;
+
+	err = sbl_serdes_spico_int(sbl, port_num, serdes,
+				   SPICO_INT_CM4_MEM_READ | addr,
+					SPICO_INT_DATA_NONE, data,
+					SPICO_INT_RETURN_RESULT);
+	if (err)
+		return err;
+
+	SBL_TRACE2(sbl->dev, "p%ds%d: addr:0x%x data:0x%x", port_num, serdes, addr, *data);
+
+	return 0;
+}
+
+int sbl_serdes_mem_wr(void *inst, u32 port_num, u32 serdes,
+		      u32 addr, u16 data)
+{
+	struct sbl_inst *sbl = inst;
+	int err;
+
+	SBL_TRACE2(sbl->dev, "p%ds%d: addr:0x%x", port_num, serdes, addr);
+	addr &= SPICO_INT_MEM_READ_ADDR_MASK;
+	err = sbl_serdes_spico_int(sbl, port_num, serdes,
+				   SPICO_INT_CM4_MEM_WRITE | addr,
+					data, NULL, SPICO_INT_IGNORE_RESULT);
+	if (err)
+		return err;
+
+	SBL_TRACE2(sbl->dev, "p%ds%d: addr:0x%x data:0x%x", port_num, serdes, addr,
+		   data);
+
+	return 0;
+}
+
+int sbl_serdes_mem_rmw(void *inst, u32 port_num, u32 serdes,
+		       u32 addr, u16 data, u16 mask)
+{
+	struct sbl_inst *sbl = inst;
+	int err;
+	u16 rdata, wdata;
+
+	SBL_TRACE2(sbl->dev, "p%ds%d: addr:0x%x data:0x%x mask:0x%x", port_num,
+		   serdes, addr, data, mask);
+	err = sbl_serdes_mem_rd(sbl, port_num, serdes, addr, &rdata);
+	if (err)
+		return err;
+
+	wdata = (rdata & ~mask) | (data & mask);
+	err = sbl_serdes_mem_wr(sbl, port_num, serdes, addr, wdata);
+	if (err)
+		return err;
+
+	SBL_TRACE2(sbl->dev, "p%ds%d: addr:0x%x rmw_data:0x%x", port_num, serdes,
+		   addr, wdata);
+
+	return 0;
+}
+
+int sbl_spico_burst_upload(void *inst, u32 sbus, u32 reg,
+			   size_t fw_size, const u8 *fw_data)
+{
+	struct sbl_inst *sbl = inst;
+	int err;
+	size_t byte;
+
+	if (!fw_data || !fw_size || fw_size % 2) {
+		SBL_ERR(sbl->dev,
+			"Bad firmware for sbus:0x%02x reg:0x%x fw->size:%zd!",
+			sbus, reg, fw_size);
+		return -EINVAL;
+	}
+
+	SBL_TRACE1(sbl->dev, "sbus:0x%02x reg:0x%x fw->size:%zd", sbus, reg,
+		   fw_size);
+	for (byte = 0; fw_size - byte >= 6; byte += 6) {
+		err = sbl_sbus_wr(sbl, sbus, reg, SPICO_SBR_DATA_BE_012 |
+				       (fw_data[byte + 0] << 8 | fw_data[byte + 1]) <<
+				       SPICO_SBR_DATA_W0_OFFSET |
+				       (fw_data[byte + 2] << 8 | fw_data[byte + 3]) <<
+				       SPICO_SBR_DATA_W1_OFFSET |
+				       (fw_data[byte + 4] << 8 | fw_data[byte + 5]) <<
+				       SPICO_SBR_DATA_W2_OFFSET);
+		if (err)
+			return err;
+
+	}
+	if (fw_size - byte == 4) {
+		err = sbl_sbus_wr(sbl, sbus, reg, SPICO_SBR_DATA_BE_01 |
+				       (fw_data[byte + 0] << 8 | fw_data[byte + 1]) <<
+				       SPICO_SBR_DATA_W0_OFFSET |
+				       (fw_data[byte + 2] << 8 | fw_data[byte + 3]) <<
+				       SPICO_SBR_DATA_W1_OFFSET);
+		if (err)
+			return err;
+
+	} else if (fw_size - byte == 2) {
+		err = sbl_sbus_wr(sbl, sbus, reg, SPICO_SBR_DATA_BE_0 |
+				       (fw_data[byte + 0] << 8 | fw_data[byte + 1]) <<
+				       SPICO_SBR_DATA_W0_OFFSET);
+		if (err)
+			return err;
+
+	}
+	return 0;
+}
+
+int sbl_sbus_op_aux(void *inst, u32 sbus_addr, u8 reg_addr,
+		    u8 command, u32 sbus_data, u32 *result)
+{
+	struct sbl_inst *sbl = inst;
+	u8 result_code = 0, overrun = 0;
+	int err = -1;
+	int retry_cnt = 0;
+	int retry_limit = 5;
+	u32 sbus_ring = SBUS_RING(sbus_addr);
+	u32 rx_addr = SBUS_RX_ADDR(sbus_addr);
+	bool valid_result = false;
+	int sbus_op_timeout_ms = sbl_sbm_get_sbus_op_timeout_ms(sbl);
+	int sbus_op_flags = sbl_sbm_get_sbus_op_flags(sbl);
+	void *accessor = sbl;
+
+	if (!sbl->is_hw) {
+		*result = 0;
+		return 0;
+	}
+	/* Safety check */
+	if (!mutex_is_locked(SBUS_RING_MTX(sbl, sbus_ring))) {
+		sbus_msg(sbl, sbus_addr, sbus_data, reg_addr, command,
+			 0, result_code, overrun, sbus_op_timeout_ms,
+			 sbus_op_flags, err, LEVEL_WARN);
+		WARN(1, "%s: Unlocked SBUS ring %d!", __func__, sbus_ring);
+	}
+
+	/* Perform SBus operation */
+	while (retry_cnt++ < retry_limit) {
+		err = sbl_sbm_sbus_op(accessor, sbus_ring, sbus_data,
+				      reg_addr, rx_addr, command, result,
+					     &result_code, &overrun,
+					     sbus_op_timeout_ms,
+					     sbus_op_flags);
+		if (err) {
+			sbus_msg(sbl, sbus_addr, sbus_data, reg_addr, command,
+				 0, result_code, overrun, sbus_op_timeout_ms,
+				 sbus_op_flags, err, LEVEL_WARN);
+		}
+		if (err || overrun) {
+			SBL_INFO(sbl->dev, "Resetting SBUS ring %d!", sbus_ring);
+			err = sbl_sbm_sbus_op_reset(sbl, sbus_ring);
+			if (err) {
+				SBL_WARN(sbl->dev,
+					 "sbl_sbm_sbus_op_reset failed! sbus_ring:%d rc:%d",
+					 sbus_ring, err);
+				return err;
+			}
+		} else {
+			break;
+		}
+	}
+
+	/* Validate results */
+	if (err || overrun) {
+		SBL_WARN(sbl->dev, "roshms_sbus_op failed!");
+		return -EIO;
+	}
+	switch (command & 0x3) {
+	case SBUS_CMD_RESET:
+		if (result_code == SBUS_RC_RESET)
+			valid_result = true;
+
+		break;
+	case SBUS_CMD_WRITE:
+		if (result_code == SBUS_RC_WRITE_COMPLETE)
+			valid_result = true;
+
+		break;
+	case SBUS_CMD_READ:
+		if (result_code == SBUS_RC_READ_COMPLETE)
+			valid_result = true;
+
+		break;
+	case SBUS_CMD_READ_RESULT:
+		if (result_code == SBUS_RC_READ_ALL_COMPLETE)
+			valid_result = true;
+
+		break;
+	}
+
+	if (!valid_result) {
+		SBL_WARN(sbl->dev, "Unexpected result code (%d) 0x%x!",
+			 result_code, command);
+		sbus_msg(sbl, sbus_addr, sbus_data, reg_addr, command,
+			 *result, result_code, overrun, sbus_op_timeout_ms,
+				sbus_op_flags, err, LEVEL_WARN);
+		return -ENOMSG;
+	}
+	sbus_msg(sbl, sbus_addr, sbus_data, reg_addr, command,
+		 *result, result_code, overrun, sbus_op_timeout_ms,
+			sbus_op_flags, err, LEVEL_DBG);
+
+	return 0;
+}
+
+/**
+ * sbl_sbm_spico_int() - spico intilization
+ * @inst: Generic pointer used by various framework
+ * @sbus_addr: address describing a serdes ring and rxaddr
+ * @code: interrupt command
+ * @data: interrupt data
+ * @result: location to store result of interrupt
+ *
+ * Write an interrupt request to a target SBM Spico
+ *
+ * Return: 0 on success, negative error code on failure
+ */
+int sbl_sbm_spico_int(void *inst, u32 sbus_addr, int code, int data,
+		      u32 *result)
+{
+	struct sbl_inst *sbl = inst;
+	int err;
+	u32 intr_out;
+	u32 intr_in;
+	char intr_str[SBL_MAX_STR_LEN];
+	int sbus_int_timeout = sbl_sbm_get_sbus_int_timeout(sbl);
+	int sbus_int_poll_interval = sbl_sbm_get_sbus_int_poll_interval(sbl);
+	unsigned long last_jiffy;
+	u32 sbus_ring = SBUS_RING(sbus_addr);
+
+	if (!sbl->is_hw) {
+		*result = 0;
+		return 0;
+	}
+	/* Safety check */
+	if (!mutex_is_locked(SBUS_RING_MTX(sbl, sbus_ring))) {
+		SBL_WARN(sbl->dev, "%s: Unlocked SBUS ring %d!", __func__, sbus_ring);
+		WARN(1, "sbl_sbus_op_aux: Unlocked SBUS ring %d!", sbus_ring);
+	}
+
+	spico_interrupt_to_string(sbus_addr, code, intr_str);
+
+	/* Inject the interrupt via SBus writes */
+	intr_in = ((data & SBMS_INTERRUPT_DATA_MASK) << SBMS_INTERRUPT_DATA_OFFSET) |
+		((code & SBMS_INTERRUPT_CODE_MASK) << SBMS_INTERRUPT_CODE_OFFSET);
+
+	err = sbl_sbus_wr(sbl, sbus_addr, SPICO_SBR_ADDR_DMEM_IN, intr_in);
+	if (err)
+		return err;
+
+	err = sbl_sbus_rd(sbl, sbus_addr, SPICO_SBR_ADDR_INTR, &intr_out);
+	if (err)
+		return err;
+
+	intr_out |= SBMS_INTERRUPT_STATUS_OK;
+	err = sbl_sbus_wr(sbl, sbus_addr, SPICO_SBR_ADDR_INTR, intr_out);
+	if (err)
+		return err;
+
+	intr_out ^= SBMS_INTERRUPT_STATUS_OK;
+	err = sbl_sbus_wr(sbl, sbus_addr, SPICO_SBR_ADDR_INTR, intr_out);
+	if (err)
+		return err;
+
+	/* Poll for interrupt completion */
+	last_jiffy = jiffies + msecs_to_jiffies(1000 * sbus_int_timeout);
+	do {
+		err = sbl_sbus_rd(sbl, sbus_addr, SPICO_SBR_ADDR_DMEM_OUT,
+				  &intr_out);
+		if (err)
+			return err;
+
+		/* Check in progress bit */
+		if ((intr_out & SBMS_INTERRUPT_IN_PROGRESSS_MASK) == 0)
+			break;
+
+		msleep(sbus_int_poll_interval);
+	} while (time_is_after_jiffies(last_jiffy));
+	if (intr_out & SBMS_INTERRUPT_IN_PROGRESSS_MASK) {
+		SBL_ERR(sbl->dev,
+			"SBM_INT: sbus_addr:0x%03x int:0x%x(%s) data:0x%x timed out (timeout:%ds)!",
+			sbus_addr, code, intr_str, data, sbus_int_timeout);
+		return -ETIME;
+	}
+
+	/* Reread to ensure result is valid */
+	err = sbl_sbus_rd(sbl, sbus_addr, SPICO_SBR_ADDR_DMEM_OUT,
+			  &intr_out);
+	if (err) {
+		SBL_ERR(sbl->dev,
+			"SBM_INT: sbus_addr:0x%03x int:0x%x(%s) data:0x%x failed!",
+			sbus_addr, code, intr_str, data);
+		return err;
+	}
+
+	/* Extract interrupt result */
+	if ((intr_out & SBMS_INTERRUPT_STATUS_MASK) == 1) {
+		*result = (intr_out & SBMS_INTERRUPT_DATA_MASK) >>
+			SBMS_INTERRUPT_DATA_OFFSET;
+	} else {
+		SBL_ERR(sbl->dev,
+			"SBM_INT: sbus_addr:0x%03x int:0x%x(%s) data:0x%x Failed with status 0x%x!",
+			sbus_addr, code, intr_str, data, (intr_out & SBMS_INTERRUPT_STATUS_MASK));
+		return -EBADE;
+	}
+
+	SBL_TRACE1(sbl->dev,
+		   "SBM_INT: sbus_addr:0x%03x int:0x%x(%s) data:0x%x -> 0x%x",
+		sbus_addr, code, intr_str, data, *result);
+	return 0;
+}
+EXPORT_SYMBOL(sbl_sbm_spico_int);
+
+/* Returns a SBUS master address based on a ring number */
+static int sbl_chip_ring_sbus_to_port_serdes(void *inst, int chip,
+					     int ring, int sbus,
+					     int *port_out, int *serdes_out)
+{
+	struct sbl_inst *sbl = inst;
+	int port, serdes;
+
+	for (port = 0; port < sbl->switch_info->num_ports; ++port) {
+		for (serdes = 0; serdes < sbl->switch_info->num_serdes; ++serdes) {
+			if (chip != sbl->switch_info->ports[port].serdes[serdes].device)
+				continue;
+
+			if (ring != sbl->switch_info->ports[port].serdes[serdes].sbus_ring)
+				continue;
+
+			if (sbus != sbl->switch_info->ports[port].serdes[serdes].rx_addr)
+				continue;
+
+			*port_out = port;
+			*serdes_out = serdes;
+			return 0;
+		}
+	}
+
+	SBL_WARN(sbl->dev,
+		 "Unable to determine port/serdes for chip %d ring %d sbus %d",
+		 chip, ring, sbus);
+	return -1;
+}
+
+int sbl_serdes_spico_int2(void *inst, u32 sbus_addr,
+			  int code, int data, u16 *result, u8 result_action)
+{
+	struct sbl_inst *sbl = inst;
+	int port_num, serdes;
+
+	if (sbl_chip_ring_sbus_to_port_serdes(sbl, 0,
+					      SBUS_RING(sbus_addr),
+						SBUS_RX_ADDR(sbus_addr),
+						&port_num, &serdes)) {
+		SBL_ERR(sbl->dev,
+			"Failed converting %d:%d:%d to port/serdes!",
+				0, SBUS_RING(sbus_addr), SBUS_RX_ADDR(sbus_addr));
+	return -1;
+	}
+
+	return sbl_serdes_spico_int(sbl, port_num, serdes, code, data, result,
+				    result_action);
+}
+
+/**
+ * sbl_serdes_spico_int() - serdes spico initilization
+ * @inst: Generic pointer used by various frameworks
+ * @port_num: port number
+ * @serdes: address list describing SerDes lanes
+ * @code: interrupt command
+ * @data: interrupt data
+ * @result: pointer to store result in
+ * @result_action: ignore the interrupt result, store it to the result
+ *                 pointer, or validate it matches code
+ *
+ * Write an interrupt request to a set of SerDes Spicos
+ *
+ * Return: 0 if all results are the same, else -1
+ */
+int sbl_serdes_spico_int(void *inst, u32 port_num, u32 serdes,
+			 int code, int data, u16 *result, u8 result_action)
+{
+	struct sbl_inst *sbl = inst;
+	int err;
+	char intr_str[SBL_MAX_STR_LEN];
+	u16 result_out = 0;
+	u16 *p_result;
+	u32 sbus_addr;
+	int serdes_op_timeout_ms = sbl_sbm_get_serdes_op_timeout_ms(sbl);
+	int serdes_op_flags = sbl_sbm_get_serdes_op_flags(sbl);
+	void *accessor = sbl;
+
+	if ((result_action == SPICO_INT_RETURN_RESULT) && (result == NULL)) {
+		SBL_ERR(sbl->dev, "result pointer was NULL!");
+		return -1;
+	}
+	if (result_action != SPICO_INT_RETURN_RESULT)
+		p_result = &result_out;
+	else
+		p_result = result;
+
+	if (!sbl->is_hw) {
+		*p_result = code;
+		return 0;
+	}
+	/* Make a fake SerDes sbus_addr so spico_interrupt_to_string gives us the
+	   right debug string. This function is only called for CM4 SerDes, so this
+	   will always give the correct string. */
+	sbl_sbus_addr_get(&sbus_addr);
+	spico_interrupt_to_string(sbus_addr, code, intr_str);
+
+	err = sbl_sbm_pml_serdes_op(accessor, port_num, serdes, code,
+				    data, p_result, serdes_op_timeout_ms,
+					   serdes_op_flags);
+	if (err) {
+		SBL_ERR(sbl->dev,
+			"SERDES_INT: p%ds%d sbl_serdes_op failed! (rc:%d) int:0x%02x(%s) data:0x%04x",
+				port_num, serdes, err, code, intr_str, data);
+		return err;
+	}
+	SBL_TRACE1(sbl->dev,
+		   "SERDES_INT: p%ds%d int:0x%02x(%s) data:0x%04x -> 0x%04x",
+			port_num, serdes, code, intr_str, data, *p_result);
+
+	if ((result_action == SPICO_INT_VALIDATE_RESULT) &&
+	    ((*p_result & SPICO_INT_RESULT_CODE_MASK) != code)) {
+		SBL_ERR(sbl->dev,
+			"SERDES_INT: p%ds%d int:0x%02x(%s) data:0x%04x -> 0x%04x Unexpected result! Expected 0x%04x!",
+			port_num, serdes, code, intr_str, data, *p_result & SPICO_INT_RESULT_CODE_MASK, code);
+		return -EBADE;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(sbl_serdes_spico_int);
diff --git a/drivers/net/ethernet/hpe/sbl/sbl_sbm_serdes_nic.c b/drivers/net/ethernet/hpe/sbl/sbl_sbm_serdes_nic.c
new file mode 100644
index 000000000000..a49dc39cc37d
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sbl/sbl_sbm_serdes_nic.c
@@ -0,0 +1,138 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* Copyright 2025 Hewlett Packard Enterprise Development LP. All Rights Reserved. */
+
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+
+#include <uapi/ethernet/sbl_sbm_constants.h>
+
+#include "sbl_sbm_serdes.h"
+#include "sbl_serdes_map.h"
+
+bool is_cm4_serdes_addr(u32 sbus_addr)
+{
+	u8 ring     = SBUS_RING(sbus_addr);
+	u16 rx_addr = SBUS_RX_ADDR(sbus_addr);
+
+	if (((ring == 0 || ring == 1) &&
+	     ((rx_addr >= SBUS_RINGX_CM4_SERDES_FIRST) &&
+	      (rx_addr <= SBUS_RINGX_CM4_SERDES_LAST))) ||
+	    (rx_addr == SBUS_BCAST_CM4_SERDES_SPICO)) {
+		return true;
+	}
+	return false;
+}
+
+bool is_pcie_serdes_addr(u32 sbus_addr)
+{
+	u8 ring     = SBUS_RING(sbus_addr);
+	u16 rx_addr = SBUS_RX_ADDR(sbus_addr);
+
+	if ((ring == 0 || ring == 1) &&
+	    ((rx_addr >= SBUS_RINGX_PCIE_SERDES_SPICO_FIRST) &&
+	      (rx_addr <= SBUS_RINGX_PCIE_SERDES_SPICO_LAST) &&
+	      ((rx_addr & 0x1) == SBUS_RINGX_PCIE_SERDES_SPICO_LSB))) {
+		return true;
+	}
+	return false;
+}
+
+bool is_pcie_serdes_pcs_addr(u32 sbus_addr)
+{
+	u8 ring     = SBUS_RING(sbus_addr);
+	u16 rx_addr = SBUS_RX_ADDR(sbus_addr);
+
+	if ((ring == 0 || ring == 1) &&
+	    ((rx_addr >= SBUS_RINGX_PCIE_SERDES_PCS_FIRST) &&
+	      (rx_addr <= SBUS_RINGX_PCIE_SERDES_PCS_LAST) &&
+	      ((rx_addr & 0x1) == SBUS_RINGX_PCIE_SERDES_PCS_LSB))) {
+		return true;
+	}
+	return false;
+}
+
+bool is_sbm_crm_addr(u32 sbus_addr)
+{
+	u8 ring     = SBUS_RING(sbus_addr);
+	u16 rx_addr = SBUS_RX_ADDR(sbus_addr);
+
+	if (((ring == 0 || ring == 1) && (rx_addr == SBUS_RINGX_SBM)) ||
+	    (rx_addr == SBUS_BCAST_SBM)) {
+
+		return true;
+	}
+	return false;
+}
+
+bool is_sbm_spico_addr(u32 sbus_addr)
+{
+	u8 ring     = SBUS_RING(sbus_addr);
+	u16 rx_addr = SBUS_RX_ADDR(sbus_addr);
+
+	if (((ring == 0 || ring == 1) && (rx_addr == SBUS_RINGX_SBM_SPICO)) ||
+	    (rx_addr == SBUS_BCAST_SBM_SPICO)) {
+		return true;
+	}
+	return false;
+}
+
+void
+sbus_addr_to_string(u32 sbus_addr, char *data_str)
+{
+	u8 ring     = SBUS_RING(sbus_addr);
+	u16 rx_addr = SBUS_RX_ADDR(sbus_addr);
+
+	/* Valid for any sbus master */
+	if (rx_addr == SBUS_BCAST_PCIE_SERDES_SPICO) {
+		sprintf(data_str, "PCIE_SERDES_SPICO(BROADCAST)");
+	} else if (rx_addr == SBUS_BCAST_PCIE_SERDES_PCS) {
+		sprintf(data_str, "PCIE_SERDES_PCS(BROADCAST)");
+	} else if (rx_addr == SBUS_BCAST_CM4_SERDES_SPICO) {
+		sprintf(data_str, "CM4_SERDES_SPICO(BROADCAST)");
+	} else if (rx_addr == SBUS_BCAST_SBM_SPICO) {
+		sprintf(data_str, "SBM_SPICO(BROADCAST)");
+	} else if (rx_addr == SBUS_BCAST_SBM) {
+		sprintf(data_str, "SBM(BROADCAST)");
+	} else if (rx_addr == SBUS_BCAST_PLL) {
+		sprintf(data_str, "PLL(BROADCAST)");
+	} else if (rx_addr == SBUS_BCAST_PMRO) {
+		sprintf(data_str, "PMRO(BROADCAST)");
+	} else if (rx_addr == SBUS_BCAST_THERMVOLT) {
+		sprintf(data_str, "THERMVOLT(BROADCAST)");
+    /* Valid for Cassini - rings 0 and 1 are the same */
+	} else if (ring == 0 || ring == 1) {
+		if (rx_addr == SBUS_RINGX_PCIE_PLL0)
+			sprintf(data_str, "PCIE_PLL0");
+		else if (rx_addr == SBUS_RINGX_PCIE_PLL1)
+			sprintf(data_str, "PCIE_PLL1");
+		else if (rx_addr == SBUS_RINGX_PCIE_PLL2)
+			sprintf(data_str, "PCIE_PLL2");
+		else if (rx_addr == SBUS_RINGX_CORE_PLL)
+			sprintf(data_str, "CORE_PLL");
+		else if (rx_addr == SBUS_RINGX_PMRO0)
+			sprintf(data_str, "PMRO0");
+		else if (rx_addr == SBUS_RINGX_PMRO1)
+			sprintf(data_str, "PMRO1");
+		else if (is_pcie_serdes_addr(sbus_addr))
+			sprintf(data_str, "PCIE_SERDES_SPICO");
+		else if (is_pcie_serdes_pcs_addr(sbus_addr))
+			sprintf(data_str, "PCIE_SERDES_PCS0");
+		else if (rx_addr == SBUS_RINGX_SBM)
+			sprintf(data_str, "SBM");
+		else if (rx_addr == SBUS_RINGX_SBM_SPICO)
+			sprintf(data_str, "SBM_SPICO");
+		else if (is_cm4_serdes_addr(sbus_addr))
+			sprintf(data_str, "CM4_SERDES");
+		else
+			sprintf(data_str, "UNKNOWN");
+	} else {
+		sprintf(data_str, "UNKNOWN");
+	}
+}
+
+void sbl_sbus_addr_get(u32 *sbus_addr)
+{
+	*sbus_addr = SBUS_ADDR(0, SBUS_RINGX_CM4_SERDES_FIRST);
+}

-- 
2.56.0


^ permalink raw reply	[flat|nested] 25+ messages in thread
* [PATCH 08/23] net: hpe: sbl: add media, FEC and counter support
  2026-10-30 20:58 [PATCH 00/23] Subject: [PATCH net-next 00/23] net/hpe: add HPE Slingshot NIC drivers Doug Ledford
                   ` (6 preceding siblings ...)
  2026-10-30 20:59 ` [PATCH 07/23] net: hpe: sbl: add the SBM serial bus layer Doug Ledford
@ 2026-10-30 20:59 ` Doug Ledford
  2026-10-30 20:59 ` [PATCH 09/23] net: hpe: sl: add the Slingshot Link headers Doug Ledford
                   ` (15 subsequent siblings)
  23 siblings, 0 replies; 25+ messages in thread
From: Doug Ledford @ 2026-10-30 20:59 UTC (permalink / raw)
  To: Slingshot Open Source Team, Nathan Chancellor, Nicolas Schier,
	Richard Cochran, Andrew Lunn, David S. Miller, Eric Dumazet,
	Jakub Kicinski, Paolo Abeni, Sumit Semwal, Christian König,
	Guenter Roeck
  Cc: linux-kernel, netdev, linux-kbuild, Doug Ledford, Sandeep Bhoot,
	Mamila Santosh

Add media detection, FEC (forward error correction) configuration and
the link counters.  sbl_platform.h is updated for the media fields
added here.

checkpatch --strict (100 columns) still reports the following in this
patch. They need coordination with the internal repositories this code
is maintained in and will be fixed in V2:
- WARNING: LONG_LINE (5)
- CHECK: BRACES (16), UNNECESSARY_PARENTHESES (10)

Co-developed-by: Sandeep Bhoot <sandeep.bhoot@hpe.com>
Signed-off-by: Sandeep Bhoot <sandeep.bhoot@hpe.com>
Co-developed-by: Mamila Santosh <santosh-kumar.mamila@hpe.com>
Signed-off-by: Mamila Santosh <santosh-kumar.mamila@hpe.com>
Signed-off-by: Doug Ledford <doug.ledford@hpe.com>
---
 drivers/net/ethernet/hpe/sbl/sbl_counters.c  | 137 ++++
 drivers/net/ethernet/hpe/sbl/sbl_fec.c       | 971 +++++++++++++++++++++++++++
 drivers/net/ethernet/hpe/sbl/sbl_fec_nic.c   |  36 +
 drivers/net/ethernet/hpe/sbl/sbl_media.c     | 482 +++++++++++++
 drivers/net/ethernet/hpe/sbl/sbl_media_nic.c |  47 ++
 5 files changed, 1673 insertions(+)

diff --git a/drivers/net/ethernet/hpe/sbl/sbl_counters.c b/drivers/net/ethernet/hpe/sbl/sbl_counters.c
new file mode 100644
index 000000000000..90feb6436105
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sbl/sbl_counters.c
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* Copyright 2019, 2022 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/device.h>
+
+#include <linux/hpe/sbl/sbl.h>
+
+#include "sbl_internal.h"
+
+/* create and initialise the SBL link's counter array */
+int sbl_link_counters_init(struct sbl_link *link)
+{
+	int i;
+
+	if (!link->counters) {
+		link->counters = kzalloc(sizeof(atomic_t) * SBL_LINK_NUM_COUNTERS,
+					 GFP_KERNEL);
+		if (!link->counters)
+			return -ENOMEM;
+	}
+
+	for (i = 0; i < SBL_LINK_NUM_COUNTERS; ++i)
+		atomic_set(link->counters + i, 0);
+
+	return 0;
+}
+
+/* destroy the SBL link's counter array */
+void sbl_link_counters_term(struct sbl_link *link)
+{
+	kfree(link->counters);
+	link->counters = NULL;
+}
+
+/**
+ * sbl_link_counters_get() - Get a block of SBL link counters
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ * @counters: Number of counters to read from 'first'
+ * @first: Index of the first counter to read
+ * @count: Number of consecutive counters to read starting from 'first'
+ *
+ * Reads a sequence of counters starting from index 'first'
+ * until the given 'count' and stores them to output
+ * pointed by 'counters'
+ *
+ * Return: 0 on success, negative error code on failure
+ */
+int sbl_link_counters_get(struct sbl_inst *sbl, int port_num,
+			  int *counters, u16 first, u16 count)
+{
+	struct sbl_link *link;
+	int i;
+	int err;
+
+	err = sbl_validate_instance(sbl);
+	if (err)
+		return -EINVAL;
+
+	err = sbl_validate_port_num(sbl, port_num);
+	if (err)
+		return -EINVAL;
+
+	link = sbl->link + port_num;
+
+	if ((first + count) > SBL_LINK_NUM_COUNTERS)
+		return -EINVAL;
+
+	if (!counters)
+		return -EINVAL;
+
+	for (i = first; i < first + count; ++i)
+		*counters++ = atomic_read(link->counters + i);
+
+	return 0;
+}
+EXPORT_SYMBOL(sbl_link_counters_get);
+
+/**
+ * sbl_link_counters_read() - Read value of a SBL link counter
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ * @counter: Index at which reads the counter value
+ *
+ * Read link count value based on the 'counter' index
+ *
+ * Return: value of a SBL link counter on success, 0 on failure
+ */
+int sbl_link_counters_read(struct sbl_inst *sbl, int port_num, u16 counter)
+{
+	struct sbl_link *link;
+	int err;
+
+	err = sbl_validate_instance(sbl);
+	if (err)
+		return 0;
+
+	err = sbl_validate_port_num(sbl, port_num);
+	if (err)
+		return 0;
+
+	link = sbl->link + port_num;
+
+	if (counter >= SBL_LINK_NUM_COUNTERS)
+		return 0;
+
+	return atomic_read(link->counters + counter);
+}
+EXPORT_SYMBOL(sbl_link_counters_read);
+
+/* Increment a SBL link counter */
+int sbl_link_counters_incr(struct sbl_inst *sbl, int port_num, u16 counter)
+{
+	struct sbl_link *link;
+	int err;
+
+	err = sbl_validate_instance(sbl);
+	if (err)
+		return -EINVAL;
+
+	err = sbl_validate_port_num(sbl, port_num);
+	if (err)
+		return -EINVAL;
+
+	link = sbl->link + port_num;
+
+	if (counter >= SBL_LINK_NUM_COUNTERS)
+		return -EINVAL;
+
+	atomic_inc(link->counters + counter);
+
+	return 0;
+}
diff --git a/drivers/net/ethernet/hpe/sbl/sbl_fec.c b/drivers/net/ethernet/hpe/sbl/sbl_fec.c
new file mode 100644
index 000000000000..d458ca5e1269
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sbl/sbl_fec.c
@@ -0,0 +1,971 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* Copyright 2024-2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/workqueue.h>
+#include <linux/spinlock.h>
+
+#include <linux/hpe/sbl/sbl.h>
+#include <linux/hpe/sbl/sbl_an.h>
+#include <linux/hpe/sbl/sbl_fec.h>
+#include <linux/hpe/sbl/sbl_kconfig.h>
+
+#include <linux/hpe/sbl/sbl_pml.h>
+
+#include "sbl_serdes_map.h"
+#include "sbl_pml_fn.h"
+#include "sbl_link.h"
+#include "sbl_serdes.h"
+#include "sbl_serdes_fn.h"
+#include "sbl_internal.h"
+
+static void sbl_fec_counts_zero(struct sbl_inst *sbl, int port_num,
+				struct sbl_pcs_fec_cntrs *cntrs)
+{
+	memset(cntrs, 0, sizeof(struct sbl_pcs_fec_cntrs));
+}
+
+static u64 sbl_fec_rate_calc(struct sbl_inst *sbl, int port_num,
+			     u64 curr, u64 prev, unsigned long tdiff)
+{
+	if (curr < prev) {
+		sbl_dev_err(sbl->dev, "%d: fec counter went backwards", port_num);
+
+		return 0;
+	} else
+		return (curr - prev) * HZ / tdiff;
+}
+
+static int sbl_fec_rates_update(struct sbl_inst *sbl, int port_num,
+				u32 window)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	struct fec_data *fec_data = link->fec_data;
+	struct sbl_fec *fec_prmts = fec_data->fec_prmts;
+	struct sbl_pcs_fec_cntrs *temp;
+	unsigned long tdiff;
+	int i;
+	bool discard_rates;
+	enum sbl_fec_discard_type reason;
+	unsigned long irq_flags;
+
+	spin_lock(&fec_prmts->fec_cnt_lock);
+
+	/* make sure the period is sufficient to update rates
+	 * otherwise zero rates so nothing fires
+	 */
+	if (time_is_after_jiffies(fec_prmts->fec_curr_cnts->time + msecs_to_jiffies(window))) {
+		sbl_fec_counts_zero(sbl, port_num, fec_prmts->fec_rates);
+		spin_unlock(&fec_prmts->fec_cnt_lock);
+
+		return -EINPROGRESS;
+	}
+
+	temp = fec_prmts->fec_prev_cnts;
+	fec_prmts->fec_prev_cnts = fec_prmts->fec_curr_cnts;
+	fec_prmts->fec_curr_cnts = temp;
+	sbl_fec_counts_get(sbl, port_num, fec_prmts->fec_curr_cnts);
+
+	spin_lock_irqsave(&link->fec_discard_lock, irq_flags);
+	discard_rates = (link->fec_discard_time >= fec_prmts->fec_prev_cnts->time) &&
+			(link->fec_discard_time < fec_prmts->fec_curr_cnts->time);
+	reason = link->fec_discard_type;
+	spin_unlock_irqrestore(&link->fec_discard_lock, irq_flags);
+
+	if (discard_rates) {
+		sbl_dev_dbg(sbl->dev, "%d: %s - ignoring FEC rates for the current window", port_num,
+			    sbl_fec_discard_str(reason));
+		sbl_fec_counts_zero(sbl, port_num, fec_prmts->fec_rates);
+		spin_unlock(&fec_prmts->fec_cnt_lock);
+		return -EINTR;
+	}
+
+	/* calc time difference  (HZ)
+	 * (unsigned so rollover ok)
+	 */
+	tdiff = fec_prmts->fec_curr_cnts->time - fec_prmts->fec_prev_cnts->time;
+
+	/* calculate rates */
+	fec_prmts->fec_rates->ccw =
+		sbl_fec_rate_calc(sbl, port_num,
+				  fec_prmts->fec_curr_cnts->ccw,
+				  fec_prmts->fec_prev_cnts->ccw, tdiff);
+	fec_prmts->fec_rates->ucw =
+		sbl_fec_rate_calc(sbl, port_num,
+				  fec_prmts->fec_curr_cnts->ucw,
+				  fec_prmts->fec_prev_cnts->ucw, tdiff);
+	fec_prmts->fec_rates->llr_tx_replay =
+		sbl_fec_rate_calc(sbl, port_num,
+				  fec_prmts->fec_curr_cnts->llr_tx_replay,
+				  fec_prmts->fec_prev_cnts->llr_tx_replay, tdiff);
+
+	for (i = 0; i < SBL_PCS_NUM_FECL_CNTRS; ++i)
+		fec_prmts->fec_rates->fecl[i] =
+			sbl_fec_rate_calc(sbl, port_num,
+					  fec_prmts->fec_curr_cnts->fecl[i],
+					  fec_prmts->fec_prev_cnts->fecl[i], tdiff);
+
+	fec_prmts->fec_rates->time = jiffies_to_msecs(tdiff);
+
+	spin_unlock(&fec_prmts->fec_cnt_lock);
+
+	return 0;
+
+}
+
+/* returns true if the corrected code word rate is bad */
+static bool sbl_fec_ccw_rate_bad(struct sbl_inst *sbl, int port_num,
+				 u32 thresh_adj, bool use_stp_thresh)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	struct fec_data *fec_data = link->fec_data;
+	struct sbl_fec *fec_prmts = fec_data->fec_prmts;
+
+	u64 ccw_bad;
+	bool ignore_err;
+	u64 ccw_hwm;
+
+	sbl_fec_ccw_bad_get(fec_prmts, use_stp_thresh, &ccw_bad, &ccw_hwm);
+
+	/* update high water mark
+	 * we record this even if no test is performed so we can use it for
+	 * debug/calibration
+	 */
+	if (fec_prmts->fec_rates->ccw > ccw_hwm) {
+		spin_lock(&fec_prmts->fec_cw_lock);
+		fec_prmts->fec_ccw_hwm = fec_prmts->fec_rates->ccw;
+		spin_unlock(&fec_prmts->fec_cw_lock);
+	}
+
+	/* apply percentage adjustment */
+	ccw_bad = ccw_bad * thresh_adj / 100;
+
+	if (ccw_bad == 0) {
+		sbl_dev_dbg(sbl->dev, "%d: fec ccw test ignored, threshold is zero", port_num);
+
+		return false;
+	}
+
+	/* check corrected code words */
+	if (fec_prmts->fec_rates->ccw > ccw_bad) {
+		sbl_link_counters_incr(sbl, port_num, fec_ccw_err);
+		ignore_err = sbl_debug_option(sbl, port_num, SBL_DEBUG_IGNORE_HIGH_FEC_CCW);
+
+		sbl_dev_err(sbl->dev, "%d: bad ccw, ccw %lld (>%lld), ucw %lld, (%lld %lld %lld %lld %lld %lld %lld %lld), window %ldms%s\n",
+			    port_num, fec_prmts->fec_rates->ccw, ccw_bad,
+				fec_prmts->fec_rates->ucw,
+				fec_prmts->fec_rates->fecl[0], fec_prmts->fec_rates->fecl[1],
+				fec_prmts->fec_rates->fecl[2], fec_prmts->fec_rates->fecl[3],
+				fec_prmts->fec_rates->fecl[4], fec_prmts->fec_rates->fecl[5],
+				fec_prmts->fec_rates->fecl[6], fec_prmts->fec_rates->fecl[7],
+				fec_prmts->fec_rates->time,
+				ignore_err ? " -ignored" : "");
+		if (ignore_err)
+			return false;
+		else
+			return true;
+	}
+	return false;
+}
+
+/* returns true if the uncorrected code word rate is bad
+ * threshold adjustment is a percentage
+ */
+static bool sbl_fec_ucw_rate_bad(struct sbl_inst *sbl, int port_num,
+				 u32 thresh_adj)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	struct fec_data *fec_data = link->fec_data;
+	struct sbl_fec *fec_prmts = fec_data->fec_prmts;
+
+	bool ignore_err;
+	u64 ucw_bad;
+	u64 ucw_hwm;
+
+	sbl_fec_ucw_bad_get(fec_prmts, &ucw_bad, &ucw_hwm);
+
+	/* update high water mark
+	 * we record this even if no test is performed so we can use it for
+	 * debug/calibration
+	 */
+	if (fec_prmts->fec_rates->ucw > ucw_hwm) {
+		spin_lock(&fec_prmts->fec_cw_lock);
+		fec_prmts->fec_ucw_hwm = fec_prmts->fec_rates->ucw;
+		spin_unlock(&fec_prmts->fec_cw_lock);
+	}
+
+	/* apply percentage adjustment */
+	ucw_bad = ucw_bad * thresh_adj / 100;
+
+	if (ucw_bad == 0) {
+		sbl_dev_dbg(sbl->dev, "%d: fec ucw test ignored, threshold is zero", port_num);
+		return false;
+	}
+
+	/* check uncorrected code words */
+	if (fec_prmts->fec_rates->ucw > ucw_bad) {
+		sbl_link_counters_incr(sbl, port_num, fec_ucw_err);
+		ignore_err = sbl_debug_option(sbl, port_num, SBL_DEBUG_IGNORE_HIGH_FEC_UCW);
+
+		sbl_dev_err(sbl->dev, "%d: bad ucw, ccw %lld, ucw %lld (>%lld), (%lld %lld %lld %lld %lld %lld %lld %lld), window %ldms%s\n",
+			    port_num, fec_prmts->fec_rates->ccw,
+				    fec_prmts->fec_rates->ucw, ucw_bad,
+				    fec_prmts->fec_rates->fecl[0], fec_prmts->fec_rates->fecl[1],
+				    fec_prmts->fec_rates->fecl[2], fec_prmts->fec_rates->fecl[3],
+				    fec_prmts->fec_rates->fecl[4], fec_prmts->fec_rates->fecl[5],
+				    fec_prmts->fec_rates->fecl[6], fec_prmts->fec_rates->fecl[7],
+				    fec_prmts->fec_rates->time,
+				    ignore_err ? " -ignored" : "");
+		if (ignore_err)
+			return false;
+		else
+			return true;
+	}
+	return false;
+
+}
+
+static bool sbl_fec_txr_rate_bad(struct sbl_inst *sbl, int port_num,
+				 u32 thresh_adj)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	struct fec_data *fec_data = link->fec_data;
+	struct sbl_fec *fec_prmts = fec_data->fec_prmts;
+
+	u64 llr_tx_replay_bad;
+	u64 llr_tx_replay_hwm;
+	bool ignore_err;
+
+	spin_lock(&fec_prmts->fec_cw_lock);
+	llr_tx_replay_bad = fec_prmts->fec_llr_tx_replay_thresh;
+	llr_tx_replay_hwm = fec_prmts->fec_llr_tx_replay_hwm;
+	spin_unlock(&fec_prmts->fec_cw_lock);
+
+	/* update high water mark
+	 * we record this even if no test is performed so we can use it for
+	 * debug/calibration
+	 */
+	if (fec_prmts->fec_rates->llr_tx_replay > llr_tx_replay_hwm) {
+		spin_lock(&fec_prmts->fec_cw_lock);
+		fec_prmts->fec_llr_tx_replay_hwm = fec_prmts->fec_rates->llr_tx_replay;
+		spin_unlock(&fec_prmts->fec_cw_lock);
+	}
+	if (llr_tx_replay_bad == 0) {
+		sbl_dev_dbg(sbl->dev, "%d: fec llr_tx_replay test ignored, threshold is zero", port_num);
+		return false;
+	}
+
+	/* check llr_tx_replay rate */
+	if (fec_prmts->fec_rates->llr_tx_replay > llr_tx_replay_bad) {
+		sbl_link_counters_incr(sbl, port_num, fec_txr_err);
+		ignore_err = sbl_debug_option(sbl, port_num, SBL_DEBUG_IGNORE_HIGH_FEC_TXR);
+
+		sbl_dev_err(sbl->dev, "%d: bad llr_tx_replay, llr_tx_replay %lld (>%lld), window %ldms%s\n",
+			    port_num,
+				fec_prmts->fec_rates->llr_tx_replay, llr_tx_replay_bad,
+				fec_prmts->fec_rates->time,
+				ignore_err ? " -ignored" : "");
+
+		if (ignore_err)
+			return false;
+		else
+			return true;
+	}
+	return false;
+}
+
+/* print a few warnings (so we can see how things are changing) about high
+ * fec lane error rates
+ */
+static void sbl_fec_rates_warnings(struct sbl_inst *sbl, int port_num,
+				   int *warning_count)
+{
+
+	struct sbl_link *link = sbl->link + port_num;
+	struct fec_data *fec_data = link->fec_data;
+	struct sbl_fec *fec_prmts = fec_data->fec_prmts;
+	int fecl_warn;
+	int i;
+
+	spin_lock(&fec_prmts->fec_cw_lock);
+	fecl_warn = fec_prmts->fecl_warn;
+	spin_unlock(&fec_prmts->fec_cw_lock);
+
+	if (fecl_warn == 0) {
+		dev_dbg(sbl->dev, "%d: fec ccw warn ignored, threshold is zero", port_num);
+
+		return;
+	}
+
+	for (i = 0; i < SBL_PCS_NUM_FECL_CNTRS; ++i) {
+		if (fec_prmts->fec_rates->fecl[i] > fecl_warn) {
+			sbl_link_counters_incr(sbl, port_num, fec_warn);
+
+			if (*warning_count > 0) {
+				dev_warn(sbl->dev,
+					 "sbl %d: warning, ccw %lld, (%lld %lld %lld %lld %lld %lld %lld %lld)%s\n",
+					 port_num, fec_prmts->fec_rates->ccw,
+					 fec_prmts->fec_rates->fecl[0],
+					 fec_prmts->fec_rates->fecl[1],
+					 fec_prmts->fec_rates->fecl[2],
+					 fec_prmts->fec_rates->fecl[3],
+					 fec_prmts->fec_rates->fecl[4],
+					 fec_prmts->fec_rates->fecl[5],
+					 fec_prmts->fec_rates->fecl[6],
+					 fec_prmts->fec_rates->fecl[7],
+					 (*warning_count == 1) ? " - last" : "");
+				--*warning_count;
+			} else {
+				dev_dbg(sbl->dev,
+					"sbl %d: warning, ccw %lld, (%lld %lld %lld %lld %lld %lld %lld %lld)\n",
+					port_num, fec_prmts->fec_rates->ccw,
+					fec_prmts->fec_rates->fecl[0],
+					fec_prmts->fec_rates->fecl[1],
+					fec_prmts->fec_rates->fecl[2],
+					fec_prmts->fec_rates->fecl[3],
+					fec_prmts->fec_rates->fecl[4],
+					fec_prmts->fec_rates->fecl[5],
+					fec_prmts->fec_rates->fecl[6],
+					fec_prmts->fec_rates->fecl[7]);
+			}
+			return;
+		}
+	}
+}
+
+/**
+ * sbl_fec_thresholds_clear() - Clear fec ccw/ucw/warn thresholds to zero
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ *
+ * Clears fec ccw/ucw/warn parameters to zero. This update is performed
+ * while holding a spinlock to ensure safe concurrent access.
+ *
+ * Context: Process context, Acquires lock and release fec_cw_lock <spin_lock>
+ */
+void sbl_fec_thresholds_clear(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	struct fec_data *fec_data = link->fec_data;
+	struct sbl_fec *fec_prmts = fec_data->fec_prmts;
+
+	sbl_dev_dbg(sbl->dev, "%d: clearing fec thresholds", port_num);
+
+	spin_lock(&fec_prmts->fec_cw_lock);
+	fec_prmts->fec_ucw_thresh = 0;
+	fec_prmts->fec_ccw_thresh = 0;
+	fec_prmts->fec_stp_ccw_thresh = 0;
+	fec_prmts->fecl_warn  = 0;
+	spin_unlock(&fec_prmts->fec_cw_lock);
+}
+EXPORT_SYMBOL(sbl_fec_thresholds_clear);
+
+/**
+ * sbl_fec_thresholds_set() - setup the fec thresholds
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ * @ucw_in: value for link mode and media
+ * @ccw_in: value for link mode and media
+ *
+ * This function gets ccw/ucw/ccw warning values using arguments
+ * provided and copies it to the fec parameters.
+ *
+ * Context: Process context, Acquires lock and release fec_cw_lock <spin_lock>
+ *
+ * Return: 0 on success, negative error code on failure
+ */
+int sbl_fec_thresholds_set(struct sbl_inst *sbl, int port_num,
+			   s32 ucw_in, s32 ccw_in)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	struct fec_data *fec_data = link->fec_data;
+	struct sbl_fec *fec_prmts = fec_data->fec_prmts;
+
+	int link_mode;
+	u64 ucw;
+	u64 ccw;
+	u64 stp_ccw;
+	u64 fecl_warn  = 0;
+	int err = 0;
+
+	/* Uncorrected codeword threshold */
+	switch (ucw_in) {
+	case SBL_LINK_FEC_INVALID:
+		sbl_dev_err(sbl->dev, "%d: link ucw invalid", port_num);
+		goto fail;
+
+	case SBL_LINK_FEC_OFF:
+		ucw = 0;
+		break;
+
+	case SBL_LINK_FEC_IEEE:
+		ucw = sbl_link_get_ucw_thresh_ieee(sbl, port_num);
+		break;
+
+	case SBL_LINK_FEC_HPE:
+		ucw = sbl_link_get_ucw_thresh_hpe(sbl, port_num);
+		break;
+
+	default:
+
+		if (ucw_in < 0) {
+			sbl_dev_err(sbl->dev, "%d: bad link attr ucw (%d)", port_num,
+				    ucw_in);
+			goto fail;
+		}
+
+		/* explicit number, just use it */
+		ucw = ucw_in;
+		break;
+	}
+
+	/* Corrected codeword threshold */
+	switch (ccw_in) {
+	case SBL_LINK_FEC_INVALID:
+		sbl_dev_err(sbl->dev, "%d: attr ccw invalid", port_num);
+		goto fail;
+
+	case SBL_LINK_FEC_OFF:
+		ccw = 0;
+		stp_ccw = 0;
+		break;
+
+	case SBL_LINK_FEC_IEEE:
+		ccw = sbl_link_get_ccw_thresh_ieee(sbl, port_num);
+		stp_ccw = sbl_link_get_stp_ccw_thresh_ieee(sbl, port_num);
+		break;
+
+	case SBL_LINK_FEC_HPE:
+		ccw = sbl_link_get_ccw_thresh_hpe(sbl, port_num);
+		stp_ccw = sbl_link_get_stp_ccw_thresh_hpe(sbl, port_num);
+		break;
+
+	default:
+
+		if (ccw_in < 0) {
+			sbl_dev_err(sbl->dev, "%d:bad link attr ccw (%d)", port_num,
+				    ccw_in);
+			goto fail;
+		}
+
+		/* explicit number, just use it */
+		ccw = ccw_in;
+		stp_ccw = ccw_in;
+		break;
+	}
+
+	/* ccw warning thresholds */
+	err = sbl_base_link_get_status(sbl, port_num,
+				       NULL, NULL, NULL, NULL, NULL, &link_mode);
+
+	if (err) {
+		sbl_dev_warn(sbl->dev, "%d:thresh, get mode failed [%d]-warnings disabled", port_num, err);
+		fecl_warn = 0;
+	} else {
+
+		switch (link_mode) {
+		case SBL_LINK_MODE_BS_200G:
+			fecl_warn = ccw / 8;
+			break;
+		case SBL_LINK_MODE_BJ_100G:
+			fecl_warn = ccw / 8;
+			break;
+		case SBL_LINK_MODE_CD_100G:
+			fecl_warn = ccw / 4;
+			break;
+		case SBL_LINK_MODE_CD_50G:
+			fecl_warn = ccw / 2;
+			break;
+		default:
+			fecl_warn = 0;
+			break;
+		}
+	}
+
+	sbl_dev_dbg(sbl->dev, "%d: Setting fec thresh ucw %lld, ccw %lld, warn %lld",
+		    port_num, ucw, ccw, fecl_warn);
+
+	spin_lock(&fec_prmts->fec_cw_lock);
+	fec_prmts->fec_ucw_thresh = ucw;
+	fec_prmts->fec_ccw_thresh = ccw;
+	fec_prmts->fec_stp_ccw_thresh = stp_ccw;
+	fec_prmts->fec_llr_tx_replay_thresh = SBL_FEC_LLR_TX_REPLAY_THRESH;
+	fec_prmts->fecl_warn = fecl_warn;
+	spin_unlock(&fec_prmts->fec_cw_lock);
+
+	return 0;
+fail:
+	sbl_dev_warn(sbl->dev, "%d: fec monitoring disabled", port_num);
+	sbl_fec_thresholds_clear(sbl, port_num);
+	return -ENAVAIL;
+}
+EXPORT_SYMBOL(sbl_fec_thresholds_set);
+
+/**
+ * sbl_fec_adjustments_set() - setup the fec threshold adjustments
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ * @ucw_adj: Value (An adjustment of zero means disable the test)
+ * @ccw_adj: Value (An adjustment of zero means disable the test)
+ *
+ * This function copies provided parameters(ucw adj/ccw adj) from caller
+ * into fec parameters of fec_ucw_down_thresh_adj and fec_ccw_down_thresh_adj
+ *
+ * Context: Process context, Acquires lock and release fec_cw_lock <spin_lock>
+ *
+ * Return: 0 on success
+ */
+int sbl_fec_adjustments_set(struct sbl_inst *sbl, int port_num,
+			    u32 ucw_adj, u32 ccw_adj)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	struct fec_data *fec_data = link->fec_data;
+	struct sbl_fec *fec_prmts = fec_data->fec_prmts;
+
+	spin_lock(&fec_prmts->fec_cw_lock);
+	fec_prmts->fec_ucw_down_thresh_adj = ucw_adj;
+	fec_prmts->fec_ccw_down_thresh_adj = ccw_adj;
+	spin_unlock(&fec_prmts->fec_cw_lock);
+
+	sbl_dev_dbg(sbl->dev, "%d: Setting fec thresh adjustments ucw_adj %d, ccw_adj %d",
+		    port_num, ucw_adj, ccw_adj);
+
+	return 0;
+}
+EXPORT_SYMBOL(sbl_fec_adjustments_set);
+
+int sbl_fec_up_check(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	struct fec_data *fec_data = link->fec_data;
+	struct sbl_fec *fec_prmts = fec_data->fec_prmts;
+	bool ucw_err;
+	bool ccw_err	 = false;
+	bool stp_ccw_err = false;
+	u32 ucw_thresh_adj;
+	u32 ccw_thresh_adj;
+	u32 stp_ccw_thresh_adj;
+	int i;
+
+	spin_lock(&fec_prmts->fec_cw_lock);
+	ucw_thresh_adj = fec_prmts->fec_ucw_up_thresh_adj;
+	ccw_thresh_adj = fec_prmts->fec_ccw_up_thresh_adj;
+	stp_ccw_thresh_adj = fec_prmts->fec_stp_ccw_up_thresh_adj;
+	spin_unlock(&fec_prmts->fec_cw_lock);
+
+	/* initial measurement */
+	msleep(SBL_FEC_UP_SETTLE_PERIOD); /* time for fec rates to settle */
+	sbl_fec_counts_get(sbl, port_num, fec_prmts->fec_curr_cnts);
+
+	for (i = 0; i < (link->blattr.options & SBL_OPT_FABRIC_LINK ?
+			 SBL_FEC_UP_COUNT_FABRIC : SBL_FEC_UP_COUNT_EDGE); ++i) {
+
+		msleep(SBL_FEC_UP_WINDOW);
+		sbl_fec_rates_update(sbl, port_num, SBL_FEC_UP_WINDOW);
+
+		ucw_err = sbl_fec_ucw_rate_bad(sbl, port_num, ucw_thresh_adj);
+		if (ucw_err)
+			sbl_dev_err(sbl->dev, "%d: fec up check: ucw fail", port_num);
+
+		if ((link->dfe_tune_count == SBL_DFE_USED_SAVED_PARAMS) && (stp_ccw_thresh_adj > 0))
+			stp_ccw_err = sbl_fec_ccw_rate_bad(sbl, port_num, stp_ccw_thresh_adj, true);
+		else
+			ccw_err = sbl_fec_ccw_rate_bad(sbl, port_num, ccw_thresh_adj, false);
+
+		if (ccw_err)
+			sbl_dev_err(sbl->dev, "%d: fec up check: ccw fail", port_num);
+		else if (stp_ccw_err)
+			sbl_dev_err(sbl->dev, "%d: fec up check: stp ccw fail", port_num);
+
+		if (ucw_err || ccw_err || stp_ccw_err) {
+			sbl_link_counters_incr(sbl, port_num, fec_up_fail);
+			return -EOVERFLOW;
+		}
+	}
+
+	return 0;
+}
+
+void sbl_fec_counts_get(struct sbl_inst *sbl, int port_num,
+			struct sbl_pcs_fec_cntrs *cntrs)
+{
+	cntrs->fecl[0] = sbl_read64(sbl, SBL_PCS_FECL_ERRORS_00_ADDR(port_num));
+	cntrs->fecl[1] = sbl_read64(sbl, SBL_PCS_FECL_ERRORS_01_ADDR(port_num));
+	cntrs->fecl[2] = sbl_read64(sbl, SBL_PCS_FECL_ERRORS_02_ADDR(port_num));
+	cntrs->fecl[3] = sbl_read64(sbl, SBL_PCS_FECL_ERRORS_03_ADDR(port_num));
+	cntrs->fecl[4] = sbl_read64(sbl, SBL_PCS_FECL_ERRORS_04_ADDR(port_num));
+	cntrs->fecl[5] = sbl_read64(sbl, SBL_PCS_FECL_ERRORS_05_ADDR(port_num));
+	cntrs->fecl[6] = sbl_read64(sbl, SBL_PCS_FECL_ERRORS_06_ADDR(port_num));
+	cntrs->fecl[7] = sbl_read64(sbl, SBL_PCS_FECL_ERRORS_07_ADDR(port_num));
+
+	cntrs->ccw = sbl_read64(sbl, SBL_PCS_CORRECTED_CW_ADDR(port_num));
+	cntrs->ucw = sbl_read64(sbl, SBL_PCS_UNCORRECTED_CW_ADDR(port_num));
+
+	cntrs->llr_tx_replay = sbl_read64(sbl, SBL_LLR_TX_REPLAY_EVENT_ADDR(port_num));
+
+	cntrs->time = jiffies;
+}
+
+void sbl_fec_monitor_start(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	unsigned long flags;
+
+	spin_lock_irqsave(&link->lock, flags);
+	if (!link->start_cancelled) {
+		link->fec_monitor_enabled = true;
+		mod_timer(&link->fec_data->fec_timer,
+			  jiffies + msecs_to_jiffies(SBL_FEC_MON_PERIOD));
+	}
+	spin_unlock_irqrestore(&link->lock, flags);
+}
+
+void sbl_fec_monitor_stop(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	unsigned long flags;
+
+	spin_lock_irqsave(&link->lock, flags);
+	link->fec_monitor_enabled = false;
+	spin_unlock_irqrestore(&link->lock, flags);
+
+	timer_delete_sync(&link->fec_data->fec_timer);
+	cancel_work_sync(&link->fec_data->fec_timer_work);
+}
+
+static void sbl_fec_monitor_rearm(struct sbl_link *link)
+{
+	unsigned long flags;
+
+	spin_lock_irqsave(&link->lock, flags);
+	if (link->fec_monitor_enabled)
+		mod_timer(&link->fec_data->fec_timer,
+			  jiffies + msecs_to_jiffies(SBL_FEC_MON_PERIOD));
+	spin_unlock_irqrestore(&link->lock, flags);
+}
+
+void sbl_fec_timer_work(struct work_struct *work)
+{
+	u32 ucw_thresh_adj;
+	u32 ccw_thresh_adj;
+	int port_num;
+	unsigned long irq_flags;
+	struct sbl_link *link;
+	enum sbl_link_down_origin down_origin = SBL_LINK_DOWN_ORIGIN_UNKNOWN;
+	struct sbl_fec *fec_prmts;
+	int warning_count = SBL_MAX_FEC_WARNINGS;
+	int err;
+	struct fec_data *fec_data = container_of(work, struct fec_data, fec_timer_work);
+	struct sbl_inst *sbl = fec_data->sbl;
+
+	port_num = fec_data->port_num;
+	link = sbl->link + port_num;
+	fec_prmts = fec_data->fec_prmts;
+
+	if ((link->blstate == SBL_BASE_LINK_STATUS_UP) && (sbl_pml_pcs_aligned(sbl, port_num))) {
+		err = sbl_fec_rates_update(sbl, port_num, SBL_FEC_MON_PERIOD);
+
+		if (!err) {
+			spin_lock_irqsave(&fec_prmts->fec_cw_lock, irq_flags);
+			ucw_thresh_adj = fec_prmts->fec_ucw_down_thresh_adj;
+			ccw_thresh_adj = fec_prmts->fec_ccw_down_thresh_adj;
+			spin_unlock_irqrestore(&fec_prmts->fec_cw_lock, irq_flags);
+
+			if (sbl_fec_ucw_rate_bad(sbl, port_num, ucw_thresh_adj)) {
+				/* take the link down */
+				down_origin = SBL_LINK_DOWN_ORIGIN_UCW;
+				sbl_pml_link_down_async_alert(sbl, port_num, down_origin);
+				return;
+			}
+
+			if (sbl_fec_ccw_rate_bad(sbl, port_num, ccw_thresh_adj, false)) {
+				/* take the link down */
+				down_origin = SBL_LINK_DOWN_ORIGIN_CCW;
+				sbl_pml_link_down_async_alert(sbl, port_num, down_origin);
+				return;
+			}
+
+			if (sbl_fec_txr_rate_bad(sbl, port_num, 0)) {
+				/* take the link down */
+				down_origin = SBL_LINK_DOWN_ORIGIN_LLR_TX_REPLAY;
+				sbl_pml_link_down_async_alert(sbl, port_num, down_origin);
+				return;
+			}
+			sbl_fec_rates_warnings(sbl, port_num, &warning_count);
+
+		}
+
+	}
+	sbl_fec_monitor_rearm(link);
+}
+
+void sbl_zero_all_fec_counts(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	struct fec_data *fec_data = link->fec_data;
+	struct sbl_fec *fec_prmts = fec_data->fec_prmts;
+
+	spin_lock(&fec_prmts->fec_cnt_lock);
+	memset(fec_prmts->fec_curr_cnts, 0, sizeof(struct sbl_pcs_fec_cntrs));
+	memset(fec_prmts->fec_prev_cnts, 0, sizeof(struct sbl_pcs_fec_cntrs));
+	memset(fec_prmts->fec_rates, 0, sizeof(struct sbl_pcs_fec_cntrs));
+	spin_unlock(&fec_prmts->fec_cnt_lock);
+}
+
+void sbl_fec_timer(struct timer_list *timer)
+{
+	int port_num;
+	struct sbl_link *link;
+	struct fec_data *fec_data = timer_container_of(fec_data, timer,
+						       fec_timer);
+	struct sbl_inst *sbl = fec_data->sbl;
+
+	port_num = fec_data->port_num;
+	link = sbl->link + port_num;
+
+	if (!queue_work(sbl->workq, &(link->fec_data->fec_timer_work)))
+		sbl_dev_warn(sbl->dev, "fec timer work already queued");
+}
+
+#ifdef CONFIG_SYSFS
+/**
+ * sbl_fec_sysfs_sprint() - Format FEC parameters status into buffer
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ * @buf: Destination buffer to write the data
+ * @size: Size of @buf in bytes, the output is truncated to fit
+ *
+ * This function formats FEC parameters and writes the result into the
+ * provided buffer typically for use in sysfs output.
+ *
+ * Context: Process context, Acquires lock and release fec_cw_lock <spin_lock>
+ *
+ * Return: Number of characters written, at most @size - 1
+ */
+int sbl_fec_sysfs_sprint(struct sbl_inst *sbl, int port_num, char *buf, size_t size)
+{
+	u64 ucw_thresh;
+	u64 ucw_hwm;
+	u64 ccw_thresh;
+	u64 ccw_hwm;
+	u64 llr_tx_replay_thresh;
+	u64 llr_tx_replay_hwm;
+	u64 fecl_warn;
+	int s = 0;
+	struct sbl_link *link = sbl->link + port_num;
+	struct fec_data *fec_data = link->fec_data;
+	struct sbl_fec *fec_prmts = fec_data->fec_prmts;
+
+	spin_lock(&fec_prmts->fec_cw_lock);
+	if (link->blstate == SBL_BASE_LINK_STATUS_STARTING) {
+		ucw_thresh = fec_prmts->fec_ucw_thresh * fec_prmts->fec_ucw_up_thresh_adj / 100;
+		ccw_thresh = fec_prmts->fec_ccw_thresh * fec_prmts->fec_ccw_up_thresh_adj / 100;
+	} else {
+		ucw_thresh = fec_prmts->fec_ucw_thresh * fec_prmts->fec_ucw_down_thresh_adj / 100;
+		ccw_thresh = fec_prmts->fec_ccw_thresh * fec_prmts->fec_ccw_down_thresh_adj / 100;
+	}
+
+	llr_tx_replay_thresh = fec_prmts->fec_llr_tx_replay_thresh;
+	ucw_hwm = fec_prmts->fec_ucw_hwm;
+	ccw_hwm = fec_prmts->fec_ccw_hwm;
+	llr_tx_replay_hwm = fec_prmts->fec_llr_tx_replay_hwm;
+	fecl_warn = fec_prmts->fecl_warn;
+	spin_unlock(&fec_prmts->fec_cw_lock);
+	if (link->blstate == SBL_BASE_LINK_STATUS_UP) {
+
+		s += scnprintf(buf + s, size - s,
+			       "fec monitor: hwm- ccw %lld/%lld, ucw %lld/%lld",
+			       ccw_hwm, ccw_thresh, ucw_hwm, ucw_thresh);
+		s += scnprintf(buf + s, size - s,
+			       ", llr_tx_replay %lld/%lld, warn %lld",
+			       llr_tx_replay_hwm, llr_tx_replay_thresh, fecl_warn);
+
+		if (ucw_thresh == 0)
+			s += scnprintf(buf + s, size - s, ", ucw-off");
+
+		if (ccw_thresh == 0)
+			s += scnprintf(buf + s, size - s, ", ccw-off");
+
+		s += scnprintf(buf + s, size - s, "\n");
+
+		if (sbl_pml_pcs_aligned(sbl, port_num)) {
+			spin_lock(&fec_prmts->fec_cnt_lock);
+			if (fec_prmts->fec_rates) {
+				s += scnprintf(buf + s, size - s,
+					       "fec monitor: rates- ccw %lld",
+					       fec_prmts->fec_rates->ccw);
+				s += scnprintf(buf + s, size - s, ", ucw %lld/%lld",
+					       fec_prmts->fec_rates->ucw,
+					       fec_prmts->fec_curr_cnts->ucw);
+				s += scnprintf(buf + s, size - s,
+					       ", llr_tx_replay %lld, window %ld",
+					       fec_prmts->fec_rates->llr_tx_replay,
+					       fec_prmts->fec_rates->time);
+				s += scnprintf(buf + s, size - s,
+					       ", (%lld %lld %lld %lld %lld %lld %lld %lld)\n",
+					       fec_prmts->fec_rates->fecl[0],
+					       fec_prmts->fec_rates->fecl[1],
+					       fec_prmts->fec_rates->fecl[2],
+					       fec_prmts->fec_rates->fecl[3],
+					       fec_prmts->fec_rates->fecl[4],
+					       fec_prmts->fec_rates->fecl[5],
+					       fec_prmts->fec_rates->fecl[6],
+					       fec_prmts->fec_rates->fecl[7]);
+			}
+			spin_unlock(&fec_prmts->fec_cnt_lock);
+		}
+	}
+	return s;
+}
+EXPORT_SYMBOL(sbl_fec_sysfs_sprint);
+#endif
+
+/**
+ * sbl_fec_txr_rate_set() - set the llr replay threshold
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ * @txr_rate: Value - An adjustment of zero means disable the test
+ *
+ * This function sets the LLR (Link-Level Retry) replay threshold
+ * used by the FEC logic. The threshold value is provided by the caller.
+ *
+ * Context: Process context, Acquires lock and release fec_cw_lock <spin_lock>
+ *
+ * Return: 0 on success
+ */
+int sbl_fec_txr_rate_set(struct sbl_inst *sbl, int port_num,
+			 u32 txr_rate)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	struct fec_data *fec_data = link->fec_data;
+	struct sbl_fec *fec_prmts = fec_data->fec_prmts;
+
+	spin_lock(&fec_prmts->fec_cw_lock);
+	fec_prmts->fec_llr_tx_replay_thresh = txr_rate;
+	spin_unlock(&fec_prmts->fec_cw_lock);
+
+	sbl_dev_dbg(sbl->dev, "%d: Setting txr_rate %d",
+		    port_num, txr_rate);
+
+	return 0;
+}
+EXPORT_SYMBOL(sbl_fec_txr_rate_set);
+
+/**
+ * sbl_fec_modify_adjustments() - Update FEC threshold adjustments
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ * @ucw_up_adj: Adjusting un-corrected code word thresholds
+ * @ccw_up_adj: Adjusting corrected code word thresholds
+ * @ucw_down_adj: Adjusting un-corrected code word thresholds
+ * @ccw_down_adj: Adjusting corrected code word thresholds
+ * @stp_ccw_up_adj: stp un-corrected code word thresholds
+ *
+ * This function adjusts max/min of uncorrected/corrected
+ * words for tuning/debug/test purposes at various levels.
+ * Used at test/debug/tuning interface.
+ *
+ * Context: Process context, Acquires lock and release fec_cw_lock <spin_lock>
+ */
+void sbl_fec_modify_adjustments(struct sbl_inst *sbl, int port_num,
+				u32 *ucw_up_adj, u32 *ccw_up_adj,
+				u32 *ucw_down_adj, u32 *ccw_down_adj,
+				u32 *stp_ccw_up_adj)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	struct fec_data *fec_data = link->fec_data;
+	struct sbl_fec *fec_prmts = fec_data->fec_prmts;
+
+	spin_lock(&fec_prmts->fec_cw_lock);
+	if (ucw_up_adj)
+		fec_prmts->fec_ucw_up_thresh_adj = *ucw_up_adj;
+	if (ccw_up_adj)
+		fec_prmts->fec_ccw_up_thresh_adj = *ccw_up_adj;
+	if (ucw_down_adj)
+		fec_prmts->fec_ucw_down_thresh_adj = *ucw_down_adj;
+	if (ccw_down_adj)
+		fec_prmts->fec_ccw_down_thresh_adj = *ccw_down_adj;
+	if (stp_ccw_up_adj)
+		fec_prmts->fec_stp_ccw_up_thresh_adj = *stp_ccw_up_adj;
+	spin_unlock(&fec_prmts->fec_cw_lock);
+}
+EXPORT_SYMBOL(sbl_fec_modify_adjustments);
+
+/**
+ * sbl_fec_dump() - Print FEC info
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ *
+ * Context: Process context, Acquires lock and release fec_cw_lock <spin_lock>
+ */
+void sbl_fec_dump(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	struct fec_data *fec_data = link->fec_data;
+	struct sbl_fec *fec_prmts = fec_data->fec_prmts;
+
+	u64 ucw_thresh;
+	u64 ccw_thresh;
+	u64 stp_ccw_thresh;
+	u32 ucw_up_adj;
+	u32 ccw_up_adj;
+	u32 stp_ccw_up_adj;
+	u32 ucw_down_adj;
+	u32 ccw_down_adj;
+
+	spin_lock(&fec_prmts->fec_cw_lock);
+	ucw_thresh     = fec_prmts->fec_ucw_thresh;
+	ccw_thresh     = fec_prmts->fec_ccw_thresh;
+	stp_ccw_thresh = fec_prmts->fec_stp_ccw_thresh;
+	ucw_up_adj     = fec_prmts->fec_ucw_up_thresh_adj;
+	ccw_up_adj     = fec_prmts->fec_ccw_up_thresh_adj;
+	stp_ccw_up_adj = fec_prmts->fec_stp_ccw_up_thresh_adj;
+	ucw_down_adj   = fec_prmts->fec_ucw_down_thresh_adj;
+	ccw_down_adj   = fec_prmts->fec_ccw_down_thresh_adj;
+	spin_unlock(&fec_prmts->fec_cw_lock);
+
+	sbl_dev_info(sbl->dev, "%d: ucw : thresh %lld", port_num, ucw_thresh);
+	sbl_dev_info(sbl->dev, "%d: ucw up: x%d%%, %lld", port_num,
+		     ucw_up_adj, ucw_thresh * ucw_up_adj / 100);
+	sbl_dev_info(sbl->dev, "%d: ucw down: x%d%%, %lld", port_num,
+		     ucw_down_adj, ucw_thresh * ucw_down_adj / 100);
+
+	sbl_dev_info(sbl->dev, "%d: ccw : thresh %lld", port_num, ccw_thresh);
+	sbl_dev_info(sbl->dev, "%d: stp ccw : thresh %lld", port_num, stp_ccw_thresh);
+	sbl_dev_info(sbl->dev, "%d: ccw up: x%d%%, %lld", port_num,
+		     ccw_up_adj, ccw_thresh * ccw_up_adj / 100);
+	sbl_dev_info(sbl->dev, "%d: stp ccw up: x%d%%, %lld", port_num,
+		     stp_ccw_up_adj, stp_ccw_thresh * stp_ccw_up_adj / 100);
+	sbl_dev_info(sbl->dev, "%d: ccw down: x%d%%, %lld", port_num,
+		     ccw_down_adj, ccw_thresh * ccw_down_adj / 100);
+}
+EXPORT_SYMBOL(sbl_fec_dump);
+
+/**
+ * sbl_fec_hwms_clear() - Clear fec HW management config
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ *
+ * This function clears the FEC HWM configuration
+ *
+ * Context: Process context, Acquires lock and release fec_cw_lock <spin_lock>
+ */
+void sbl_fec_hwms_clear(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	struct fec_data *fec_data = link->fec_data;
+	struct sbl_fec *fec_prmts = fec_data->fec_prmts;
+
+	sbl_dev_dbg(sbl->dev, "%d: clearing fec thresholds", port_num);
+
+	spin_lock(&fec_prmts->fec_cw_lock);
+	fec_prmts->fec_ucw_hwm = 0;
+	fec_prmts->fec_ccw_hwm = 0;
+	fec_prmts->fec_llr_tx_replay_hwm = 0;
+	spin_unlock(&fec_prmts->fec_cw_lock);
+}
+EXPORT_SYMBOL(sbl_fec_hwms_clear);
diff --git a/drivers/net/ethernet/hpe/sbl/sbl_fec_nic.c b/drivers/net/ethernet/hpe/sbl/sbl_fec_nic.c
new file mode 100644
index 000000000000..e7a06c8895d7
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sbl/sbl_fec_nic.c
@@ -0,0 +1,36 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/delay.h>
+#include <linux/workqueue.h>
+#include <linux/spinlock.h>
+
+#include <linux/hpe/sbl/sbl.h>
+#include <linux/hpe/sbl/sbl_fec.h>
+#include <linux/hpe/sbl/sbl_kconfig.h>
+
+#include <linux/hpe/sbl/sbl_pml.h>
+
+#include "sbl_internal.h"
+
+void sbl_fec_ucw_bad_get(struct sbl_fec *fec_prmts, u64 *ucw_bad, u64 *ucw_hwm)
+{
+	spin_lock(&fec_prmts->fec_cw_lock);
+	*ucw_hwm = fec_prmts->fec_ucw_hwm;
+	*ucw_bad = fec_prmts->fec_ucw_thresh;
+	spin_unlock(&fec_prmts->fec_cw_lock);
+}
+
+void sbl_fec_ccw_bad_get(struct sbl_fec *fec_prmts, bool use_stp_thresh,
+			 u64 *ccw_bad, u64 *ccw_hwm)
+{
+	spin_lock(&fec_prmts->fec_cw_lock);
+	*ccw_hwm = fec_prmts->fec_ccw_hwm;
+	*ccw_bad = use_stp_thresh ? fec_prmts->fec_stp_ccw_thresh :
+		fec_prmts->fec_ccw_thresh;
+	spin_unlock(&fec_prmts->fec_cw_lock);
+}
diff --git a/drivers/net/ethernet/hpe/sbl/sbl_media.c b/drivers/net/ethernet/hpe/sbl/sbl_media.c
new file mode 100644
index 000000000000..ec2b4574565e
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sbl/sbl_media.c
@@ -0,0 +1,482 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* Copyright 2019, 2021-2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+
+#include <linux/hpe/sbl/sbl.h>
+#include <linux/hpe/sbl/sbl_kconfig.h>
+
+#include <linux/hpe/sbl/sbl_pml.h>
+
+#include "sbl_internal.h"
+
+/**
+ * sbl_media_config() - Config media
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ * @mattr: media attributes
+ *
+ * This function sets the media attributes for the link
+ * and sets the state as configured.
+ *
+ * Context: Process, Acquires locks and releases link->lock <spin_lock>
+ *
+ * Return: 0 on success, negative error code on failure
+ */
+int sbl_media_config(struct sbl_inst *sbl, int port_num,
+		     struct sbl_media_attr *mattr)
+{
+	struct sbl_link *link;
+	int err;
+
+	err = sbl_validate_instance(sbl);
+	if (err)
+		return err;
+
+	sbl_dev_dbg(sbl->dev, "media config\n");
+
+	err = sbl_validate_port_num(sbl, port_num);
+	if (err)
+		return err;
+
+	if (!mattr)
+		return -EINVAL;
+
+	if (mattr->magic != SBL_MEDIA_ATTR_MAGIC)
+		return -EINVAL;
+
+	link = sbl->link + port_num;
+
+	spin_lock(&link->lock);
+
+	if (!(link->blstate & (SBL_BASE_LINK_STATUS_UNCONFIGURED | SBL_BASE_LINK_STATUS_DOWN))) {
+
+		sbl_dev_err(sbl->dev, "%d: wrong state (%s) to configure media\n", port_num,
+			    sbl_link_state_str(link->blstate));
+		spin_unlock(&link->lock);
+		return -EUCLEAN;
+	}
+
+	memcpy(&link->mattr, mattr, sizeof(struct sbl_media_attr));
+	link->mconfigured = true;
+
+	if (link->blconfigured)
+		link->blstate = SBL_BASE_LINK_STATUS_DOWN;
+
+	/* the media might have changed so invalidate the llr loop time */
+	link->llr_loop_time = 0;
+
+	spin_unlock(&link->lock);
+
+	return 0;
+}
+EXPORT_SYMBOL(sbl_media_config);
+
+/**
+ * sbl_media_unconfig() - Unconfig media
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ *
+ * Clear media attributes and set base link status to unconfigure.
+ *
+ * Context: Process, Acquires Lock and releases link->lock <spin_lock>
+ *
+ * Return: negative error code on failure
+ */
+int sbl_media_unconfig(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link;
+	int err = 0;
+
+	err = sbl_validate_instance(sbl);
+	if (err)
+		return err;
+
+	sbl_dev_dbg(sbl->dev, "media unconfig\n");
+
+	err = sbl_validate_port_num(sbl, port_num);
+	if (err)
+		return err;
+
+	link = sbl->link + port_num;
+
+	spin_lock(&link->lock);
+
+	if (!(link->blstate & (SBL_BASE_LINK_STATUS_UNCONFIGURED |
+			SBL_BASE_LINK_STATUS_DOWN |
+			SBL_BASE_LINK_STATUS_STOPPING))) {
+
+		sbl_dev_err(sbl->dev, "%d: wrong state (%s) to unconfigure media\n", port_num,
+			    sbl_link_state_str(link->blstate));
+		spin_unlock(&link->lock);
+		return -EUCLEAN;
+	}
+
+	memset(&link->mattr, 0, sizeof(struct sbl_media_attr));
+	link->mconfigured = false;
+
+	link->blstate = SBL_BASE_LINK_STATUS_UNCONFIGURED;
+
+	spin_unlock(&link->lock);
+
+	return err;
+}
+EXPORT_SYMBOL(sbl_media_unconfig);
+
+bool sbl_media_check_mode_supported(struct sbl_inst *sbl, int port_num, u32 link_mode)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	u32 info_mode_bit = 0;
+	u32 media_info;
+	bool allow_bad_mode;
+	unsigned long flags;
+
+	spin_lock_irqsave(&link->lock, flags);
+	media_info = link->mattr.info;
+	allow_bad_mode = link->blattr.options & SBL_OPT_ALLOW_MEDIA_BAD_MODE;
+	spin_unlock_irqrestore(&link->lock, flags);
+
+	if (!media_info) {
+		/* We have no info about media
+		 * assume its OK so we can carry on
+		 * if its not we will fail later anyway
+		 */
+		sbl_dev_warn(sbl->dev, "%d: no media info - assuming link mode OK", port_num);
+		return true;
+	}
+
+	switch (link_mode) {
+	case SBL_LINK_MODE_BS_200G:
+		info_mode_bit = SBL_MEDIA_INFO_SUPPORTS_BS_200G;
+		break;
+	case SBL_LINK_MODE_BJ_100G:
+		info_mode_bit = SBL_MEDIA_INFO_SUPPORTS_BJ_100G;
+		break;
+	case SBL_LINK_MODE_CD_100G:
+		info_mode_bit = SBL_MEDIA_INFO_SUPPORTS_CD_100G;
+		break;
+	case SBL_LINK_MODE_CD_50G:
+		info_mode_bit = SBL_MEDIA_INFO_SUPPORTS_CD_50G;
+		break;
+	default:
+		/* do nothing here - below will catch invalid link mode */
+		break;
+	}
+
+	if (media_info & info_mode_bit)
+		return true;
+
+	if (allow_bad_mode ||
+	    sbl_debug_option(sbl, port_num, SBL_DEBUG_ALLOW_MEDIA_BAD_MODE)) {
+		sbl_dev_warn(sbl->dev, "%d: link mode (%s) not supported by media - ignored",
+			     port_num, sbl_link_mode_str(link_mode));
+		return true;
+	}
+	sbl_dev_err(sbl->dev, "%d: link mode (%s) not supported by media",
+		    port_num, sbl_link_mode_str(link_mode));
+	return false;
+}
+
+/**
+ * sbl_media_check_headshell_reset_supported() - Check headshell based on media info
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ *
+ * Return: True if reset is supported else false
+ */
+bool sbl_media_check_headshell_reset_supported(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+
+	if (!link->mattr.info) {
+		/* We have no info about media */
+		sbl_dev_dbg(sbl->dev, "%d: no media info available to check headshell reset supported bit", port_num);
+		return false;
+	}
+
+	if (link->mattr.info & SBL_MEDIA_INFO_SUPPORTS_HEADSHELL_RESET)
+		return true;
+
+	return false;
+}
+EXPORT_SYMBOL(sbl_media_check_headshell_reset_supported);
+
+static bool sbl_media_check_len_supported(struct sbl_inst *sbl, int port_num, u64 len)
+{
+	struct sbl_link *link = sbl->link + port_num;
+
+	switch (len) {
+	case SBL_LINK_LEN_BACKPLANE:
+	case SBL_LINK_LEN_000_300:
+	case SBL_LINK_LEN_000_400:
+	case SBL_LINK_LEN_000_750:
+	case SBL_LINK_LEN_000_800:
+	case SBL_LINK_LEN_001_000:
+	case SBL_LINK_LEN_001_100:
+	case SBL_LINK_LEN_001_150:
+	case SBL_LINK_LEN_001_200:
+	case SBL_LINK_LEN_001_400:
+	case SBL_LINK_LEN_001_420:
+	case SBL_LINK_LEN_001_500:
+	case SBL_LINK_LEN_001_600:
+	case SBL_LINK_LEN_001_640:
+	case SBL_LINK_LEN_001_700:
+	case SBL_LINK_LEN_001_800:
+	case SBL_LINK_LEN_001_900:
+	case SBL_LINK_LEN_001_910:
+	case SBL_LINK_LEN_002_000:
+	case SBL_LINK_LEN_002_100:
+	case SBL_LINK_LEN_002_130:
+	case SBL_LINK_LEN_002_200:
+	case SBL_LINK_LEN_002_300:
+	case SBL_LINK_LEN_002_390:
+	case SBL_LINK_LEN_002_400:
+	case SBL_LINK_LEN_002_500:
+	case SBL_LINK_LEN_002_600:
+	case SBL_LINK_LEN_002_620:
+	case SBL_LINK_LEN_002_700:
+	case SBL_LINK_LEN_002_800:
+	case SBL_LINK_LEN_002_900:
+	case SBL_LINK_LEN_002_990:
+	case SBL_LINK_LEN_003_000:
+	case SBL_LINK_LEN_004_000:
+	case SBL_LINK_LEN_005_000:
+	case SBL_LINK_LEN_006_000:
+	case SBL_LINK_LEN_007_000:
+	case SBL_LINK_LEN_008_000:
+	case SBL_LINK_LEN_010_000:
+	case SBL_LINK_LEN_014_000:
+	case SBL_LINK_LEN_015_000:
+	case SBL_LINK_LEN_019_000:
+	case SBL_LINK_LEN_025_000:
+	case SBL_LINK_LEN_030_000:
+	case SBL_LINK_LEN_035_000:
+	case SBL_LINK_LEN_050_000:
+	case SBL_LINK_LEN_075_000:
+	case SBL_LINK_LEN_100_000:
+		return true;
+	default:
+		if ((link->blattr.options & SBL_OPT_ALLOW_MEDIA_BAD_LEN) ||
+		    sbl_debug_option(sbl, port_num, SBL_DEBUG_ALLOW_MEDIA_BAD_LEN)) {
+			sbl_dev_warn(sbl->dev, "%d: unsupported media len (%lld) - ignored", port_num, len);
+			return true;
+		}
+		sbl_dev_err(sbl->dev, "%d: unsupported media len (%lld)", port_num, len);
+		return false;
+	}
+}
+
+/* return valid length in cm or 0 */
+u32 sbl_media_get_len_cm(struct sbl_inst *sbl, int port_num, u64 len)
+{
+	if (sbl_media_check_len_supported(sbl, port_num, len)) {
+		switch (len) {
+		case SBL_LINK_LEN_BACKPLANE: return 25;
+		case SBL_LINK_LEN_000_300:   return 30;
+		case SBL_LINK_LEN_000_400:   return 40;
+		case SBL_LINK_LEN_000_750:   return 75;
+		case SBL_LINK_LEN_000_800:   return 80;
+		case SBL_LINK_LEN_001_000:   return 100;
+		case SBL_LINK_LEN_001_100:   return 110;
+		case SBL_LINK_LEN_001_150:   return 115;
+		case SBL_LINK_LEN_001_200:   return 120;
+		case SBL_LINK_LEN_001_400:   return 140;
+		case SBL_LINK_LEN_001_420:   return 142;
+		case SBL_LINK_LEN_001_500:   return 150;
+		case SBL_LINK_LEN_001_600:   return 160;
+		case SBL_LINK_LEN_001_640:   return 164;
+		case SBL_LINK_LEN_001_700:   return 170;
+		case SBL_LINK_LEN_001_800:   return 180;
+		case SBL_LINK_LEN_001_900:   return 190;
+		case SBL_LINK_LEN_001_910:   return 191;
+		case SBL_LINK_LEN_002_000:   return 200;
+		case SBL_LINK_LEN_002_100:   return 210;
+		case SBL_LINK_LEN_002_130:   return 213;
+		case SBL_LINK_LEN_002_200:   return 220;
+		case SBL_LINK_LEN_002_300:   return 230;
+		case SBL_LINK_LEN_002_390:   return 239;
+		case SBL_LINK_LEN_002_400:   return 240;
+		case SBL_LINK_LEN_002_500:   return 250;
+		case SBL_LINK_LEN_002_600:   return 260;
+		case SBL_LINK_LEN_002_620:   return 262;
+		case SBL_LINK_LEN_002_700:   return 270;
+		case SBL_LINK_LEN_002_800:   return 280;
+		case SBL_LINK_LEN_002_900:   return 290;
+		case SBL_LINK_LEN_002_990:   return 299;
+		case SBL_LINK_LEN_003_000:   return 300;
+		case SBL_LINK_LEN_004_000:   return 400;
+		case SBL_LINK_LEN_005_000:   return 500;
+		case SBL_LINK_LEN_006_000:   return 600;
+		case SBL_LINK_LEN_007_000:   return 700;
+		case SBL_LINK_LEN_008_000:   return 800;
+		case SBL_LINK_LEN_010_000:   return 1000;
+		case SBL_LINK_LEN_014_000:   return 1400;
+		case SBL_LINK_LEN_015_000:   return 1500;
+		case SBL_LINK_LEN_019_000:   return 1900;
+		case SBL_LINK_LEN_025_000:   return 2500;
+		case SBL_LINK_LEN_030_000:   return 3000;
+		case SBL_LINK_LEN_035_000:   return 3500;
+		case SBL_LINK_LEN_050_000:   return 5000;
+		case SBL_LINK_LEN_075_000:   return 7500;
+		case SBL_LINK_LEN_100_000:   return 10000;
+		}
+	}
+
+	return 0;
+}
+
+/* calc loop time based on cable length */
+int sbl_media_calc_loop_time(struct sbl_inst *sbl, int port_num, u64 *calc_loop_time)
+{
+	struct sbl_link *link;
+	u32 len;
+	int err;
+
+	err = sbl_validate_instance(sbl);
+	if (err)
+		return err;
+
+	err = sbl_validate_port_num(sbl, port_num);
+	if (err)
+		return err;
+
+	if (!calc_loop_time)
+		return -EINVAL;
+
+	link = sbl->link + port_num;
+	*calc_loop_time = 0;
+
+	if ((link->blattr.loopback_mode == SBL_LOOPBACK_MODE_OFF) ||
+	    (link->blattr.loopback_mode == SBL_LOOPBACK_MODE_INVALID)) {
+		len = sbl_media_get_len_cm(sbl, port_num, link->mattr.len);
+		if (!len)
+			return -EBADRQC;
+	} else
+		len = 0;
+
+	sbl_dev_dbg(sbl->dev, "%d: len = %d, lb = %s",
+		    port_num, len, sbl_loopback_mode_str(link->blattr.loopback_mode));
+
+	if (link->mattr.media == SBL_LINK_MEDIA_ELECTRICAL)
+		*calc_loop_time = 2 * len * SBL_MEDIA_NS_PER_M / 100;
+	else
+		*calc_loop_time = (2 * len * SBL_MEDIA_OPTICAL_NS_PER_M / 100) +
+			(4 * SBL_MEDIA_OPTICAL_TRANCEIVER_DELAY);
+	*calc_loop_time += 2 * (SBL_ASIC_TX_DELAY + SBL_ASIC_RX_DELAY);
+
+	sbl_dev_dbg(sbl->dev, "%d: calc loop time %lld cm %lld ns",
+		    port_num, link->mattr.len, *calc_loop_time);
+
+	return 0;
+}
+
+/**
+ * sbl_media_get_loop_time_ns() - Get loop time in ns
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ * @measurement_only: set to false when reading
+ *
+ * This function returns available loop time. If not and
+ * 'measurement_only' is true, returns 0 with a warning.
+ * Otherwise attempts to calculate the loop time.
+ *
+ * Return: calculate loop time on success, 0 on failure
+ */
+u64 sbl_media_get_loop_time_ns(struct sbl_inst *sbl, int port_num,
+			       bool measurement_only)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	u64 calc_loop_time;
+	int err;
+
+	if (!link->mconfigured)
+		return 0;
+
+	if (link->llr_loop_time)
+		return link->llr_loop_time;
+
+	if (measurement_only) {
+		sbl_dev_warn(sbl->dev, "%d: measured loop time not found", port_num);
+		return 0;
+	}
+
+	if (!sbl_media_check_len_supported(sbl, port_num, link->mattr.len))
+		return 0;
+
+	err = sbl_media_calc_loop_time(sbl, port_num, &calc_loop_time);
+	if (err)
+		return 0;
+
+	return calc_loop_time;
+}
+EXPORT_SYMBOL(sbl_media_get_loop_time_ns);
+
+int sbl_media_validate_config(struct sbl_inst *sbl, int port_num)
+{
+	struct sbl_link *link = sbl->link + port_num;
+
+	if (!(link->mconfigured && link->blconfigured))
+		return -EUCLEAN;
+
+	if ((link->mattr.media == SBL_LINK_MEDIA_ELECTRICAL) &&
+	    (link->blattr.config_target == SBL_BASE_LINK_CONFIG_PEC))
+		return 0;
+
+	if ((link->mattr.media == SBL_LINK_MEDIA_OPTICAL) &&
+	    (link->blattr.config_target == SBL_BASE_LINK_CONFIG_AOC))
+		return 0;
+
+	return -EMEDIUMTYPE;
+}
+
+#ifdef CONFIG_SYSFS
+/**
+ * sbl_media_sysfs_sprint() - Format media info into buffer
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ * @buf: Destination buffer to write the data
+ * @size: Size of @buf in bytes, the output is truncated to fit
+ *
+ * This function checks the state of media configuration and info.
+ * Based on that it will format the string and write into the
+ * provided buffer.
+ *
+ * Return: Number of characters written, at most @size - 1
+ */
+int sbl_media_sysfs_sprint(struct sbl_inst *sbl, int port_num, char *buf, size_t size)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	int s = 0;
+
+	spin_lock(&link->lock);
+	if (link->mconfigured) {
+		s += scnprintf(buf + s, size - s, "media: %s, %s, (%s), info ",
+			       sbl_link_media_str(link->mattr.media),
+			       sbl_link_len_str(link->mattr.len),
+			       sbl_link_vendor_str(link->mattr.vendor));
+		if (link->mattr.info) {
+			if (link->mattr.info & SBL_MEDIA_INFO_SUPPORTS_BS_200G)
+				s += scnprintf(buf + s, size - s, "200 ");
+			if (link->mattr.info & SBL_MEDIA_INFO_SUPPORTS_BJ_100G)
+				s += scnprintf(buf + s, size - s, "100bj ");
+			if (link->mattr.info & SBL_MEDIA_INFO_SUPPORTS_CD_100G)
+				s += scnprintf(buf + s, size - s, "100cd ");
+			if (link->mattr.info & SBL_MEDIA_INFO_SUPPORTS_CD_50G)
+				s += scnprintf(buf + s, size - s, "50 ");
+			if (link->mattr.info & SBL_MEDIA_INFO_ANALOG)
+				s += scnprintf(buf + s, size - s, "analog ");
+			if (link->mattr.info & SBL_MEDIA_INFO_DIGITAL)
+				s += scnprintf(buf + s, size - s, "digital ");
+		} else
+			s += scnprintf(buf + s, size - s, "none");
+		s += scnprintf(buf + s, size - s, "\n");
+	}
+	spin_unlock(&link->lock);
+
+	return s;
+}
+EXPORT_SYMBOL(sbl_media_sysfs_sprint);
+#endif
diff --git a/drivers/net/ethernet/hpe/sbl/sbl_media_nic.c b/drivers/net/ethernet/hpe/sbl/sbl_media_nic.c
new file mode 100644
index 000000000000..dc462e17dd72
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sbl/sbl_media_nic.c
@@ -0,0 +1,47 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+
+#include <linux/hpe/sbl/sbl.h>
+#include <linux/hpe/sbl/sbl_kconfig.h>
+
+#include <linux/hpe/sbl/sbl_pml.h>
+
+#include "sbl_internal.h"
+
+#ifdef CONFIG_SYSFS
+
+/**
+ * sbl_media_type_sysfs_sprint() - Report media type into buffer
+ * @sbl: A slingshot base link device instance
+ * @port_num: port number
+ * @buf: Destination buffer to write the data
+ * @size: Size of @buf in bytes, the output is truncated to fit
+ *
+ * This function reads the physical type of media used based on mconfigured
+ * and writes a formatted description of the type into the provided buffer
+ *
+ * Return: Number of characters written, at most @size - 1
+ */
+int sbl_media_type_sysfs_sprint(struct sbl_inst *sbl, int port_num, char *buf, size_t size)
+{
+	struct sbl_link *link = sbl->link + port_num;
+	int s = 0;
+
+	spin_lock(&link->lock);
+
+	if (link->mconfigured)
+		s += scnprintf(buf + s, size - s, "%s", sbl_link_media_str(link->mattr.media));
+	else
+		s += scnprintf(buf + s, size - s, "NA");
+
+	spin_unlock(&link->lock);
+
+	return s;
+}
+EXPORT_SYMBOL(sbl_media_type_sysfs_sprint);
+#endif

-- 
2.56.0


^ permalink raw reply	[flat|nested] 25+ messages in thread
* [PATCH 09/23] net: hpe: sl: add the Slingshot Link headers
  2026-10-30 20:58 [PATCH 00/23] Subject: [PATCH net-next 00/23] net/hpe: add HPE Slingshot NIC drivers Doug Ledford
                   ` (7 preceding siblings ...)
  2026-10-30 20:59 ` [PATCH 08/23] net: hpe: sbl: add media, FEC and counter support Doug Ledford
@ 2026-10-30 20:59 ` Doug Ledford
  2026-10-30 20:59 ` [PATCH 10/23] net: hpe: sl: add the module entry points Doug Ledford
                   ` (14 subsequent siblings)
  23 siblings, 0 replies; 25+ messages in thread
From: Doug Ledford @ 2026-10-30 20:59 UTC (permalink / raw)
  To: Slingshot Open Source Team, Nathan Chancellor, Nicolas Schier,
	Richard Cochran, Andrew Lunn, David S. Miller, Eric Dumazet,
	Jakub Kicinski, Paolo Abeni, Sumit Semwal, Christian König,
	Guenter Roeck
  Cc: linux-kernel, netdev, linux-kbuild, Doug Ledford, Sandeep Bhoot,
	Iraimani P, Mamila Santosh

Add the public headers for the Slingshot Link (SL) driver, the 400 Gb/s
link layer used by the second generation Cassini NIC.  SL is an
independent driver from SBL; a NIC uses one or the other depending on
its generation, so the two do not share code.

As for SBL, every header of the driver, including those private to one
layer, is added here so that each later patch compiles on its own.

The Kconfig and Makefile hookup for this driver is deliberately the
last patch of the driver group, so that every earlier patch adds
sources without changing what the tree builds.

checkpatch --strict (100 columns) still reports the following in this
patch. They need coordination with the internal repositories this code
is maintained in and will be fixed in V2:
- ERROR: CODE_INDENT (4)
- WARNING: LEADING_SPACE (19005), LONG_LINE (301), LONG_LINE_COMMENT
  (33), MACRO_WITH_FLOW_CONTROL (11), SPDX_LICENSE_TAG (2)
- CHECK: UNCOMMENTED_DEFINITION (25), OPEN_ENDED_LINE (20),
  MACRO_ARG_REUSE (19), MACRO_ARG_PRECEDENCE (8), LINE_SPACING (3),
  PARENTHESIS_ALIGNMENT (2), PREFER_KERNEL_TYPES (2)

Co-developed-by: Sandeep Bhoot <sandeep.bhoot@hpe.com>
Signed-off-by: Sandeep Bhoot <sandeep.bhoot@hpe.com>
Co-developed-by: Iraimani P <iraimani.pavadai@hpe.com>
Signed-off-by: Iraimani P <iraimani.pavadai@hpe.com>
Co-developed-by: Mamila Santosh <santosh-kumar.mamila@hpe.com>
Signed-off-by: Mamila Santosh <santosh-kumar.mamila@hpe.com>
Signed-off-by: Doug Ledford <doug.ledford@hpe.com>
---
 .../net/ethernet/hpe/sl/core/base/sl_core_log.h    |   70 +
 .../ethernet/hpe/sl/core/base/sl_core_timer_link.h |   41 +
 .../ethernet/hpe/sl/core/base/sl_core_timer_llr.h  |   37 +
 .../ethernet/hpe/sl/core/base/sl_core_work_link.h  |   41 +
 .../ethernet/hpe/sl/core/base/sl_core_work_llr.h   |   19 +
 .../ethernet/hpe/sl/core/data/sl_core_data_ldev.h  |   19 +
 .../ethernet/hpe/sl/core/data/sl_core_data_lgrp.h  |   26 +
 .../hpe/sl/core/data/sl_core_data_lgrp_trace.h     |   13 +
 .../ethernet/hpe/sl/core/data/sl_core_data_link.h  |   91 +
 .../ethernet/hpe/sl/core/data/sl_core_data_llr.h   |   49 +
 .../ethernet/hpe/sl/core/data/sl_core_data_mac.h   |   24 +
 .../hpe/sl/core/hw/nic/sl_core_hw_intr_flgs.h      |   70 +
 .../hpe/sl/core/hw/nic/sl_core_hw_intr_flgs_llr.h  |   37 +
 .../sl/core/hw/nic/sl_core_hw_serdes_firmware.h    |   11 +
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_an.h    |  112 +
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_an_lp.h |   23 +
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_an_up.h |   15 +
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_fec.h   |   23 +
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_intr.h  |   52 +
 .../ethernet/hpe/sl/core/hw/sl_core_hw_intr_llr.h  |   48 +
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_io.h    |  308 +
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_link.h  |   35 +
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_llr.h   |   38 +
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_mac.h   |   20 +
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_pcs.h   |   25 +
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_pmi.h   |   43 +
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_reset.h |   13 +
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_sbus.h  |   52 +
 .../ethernet/hpe/sl/core/hw/sl_core_hw_sbus_pmi.h  |   28 +
 .../ethernet/hpe/sl/core/hw/sl_core_hw_serdes.h    |   23 +
 .../hpe/sl/core/hw/sl_core_hw_serdes_addrs.h       |   87 +
 .../hpe/sl/core/hw/sl_core_hw_serdes_condor.h      |   12 +
 .../hpe/sl/core/hw/sl_core_hw_serdes_core.h        |   12 +
 .../ethernet/hpe/sl/core/hw/sl_core_hw_serdes_fw.h |   15 +
 .../hpe/sl/core/hw/sl_core_hw_serdes_lane.h        |  125 +
 .../hpe/sl/core/hw/sl_core_hw_serdes_link.h        |   13 +
 .../hpe/sl/core/hw/sl_core_hw_serdes_osprey.h      |   89 +
 .../ethernet/hpe/sl/core/hw/sl_core_hw_settings.h  |   40 +
 .../ethernet/hpe/sl/core/hw/sl_core_hw_uc_ram.h    |   28 +
 drivers/net/ethernet/hpe/sl/core/hw/ucode/octet.h  | 9605 ++++++++++++++++++++
 drivers/net/ethernet/hpe/sl/core/hw/ucode/quad.h   | 9410 +++++++++++++++++++
 drivers/net/ethernet/hpe/sl/core/sl_core_ldev.h    |   73 +
 drivers/net/ethernet/hpe/sl/core/sl_core_lgrp.h    |  214 +
 drivers/net/ethernet/hpe/sl/core/sl_core_link.h    |  534 ++
 drivers/net/ethernet/hpe/sl/core/sl_core_link_an.h |   31 +
 .../net/ethernet/hpe/sl/core/sl_core_link_fec.h    |   45 +
 drivers/net/ethernet/hpe/sl/core/sl_core_llr.h     |  138 +
 drivers/net/ethernet/hpe/sl/core/sl_core_mac.h     |   62 +
 drivers/net/ethernet/hpe/sl/core/sl_core_str.h     |   28 +
 .../net/ethernet/hpe/sl/ctrl/base/sl_ctrl_log.h    |   34 +
 .../ethernet/hpe/sl/ctrl/data/sl_ctrl_data_lgrp.h  |   20 +
 .../hpe/sl/ctrl/data/sl_ctrl_data_lgrp_trace.h     |   13 +
 .../ethernet/hpe/sl/ctrl/data/sl_ctrl_data_link.h  |   48 +
 .../ethernet/hpe/sl/ctrl/data/sl_ctrl_data_llr.h   |   15 +
 drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_ldev.h    |   91 +
 drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_lgrp.h    |   93 +
 .../net/ethernet/hpe/sl/ctrl/sl_ctrl_lgrp_notif.h  |   40 +
 drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_link.h    |  161 +
 .../ethernet/hpe/sl/ctrl/sl_ctrl_link_counters.h   |  125 +
 .../net/ethernet/hpe/sl/ctrl/sl_ctrl_link_fec.h    |   33 +
 .../ethernet/hpe/sl/ctrl/sl_ctrl_link_fec_priv.h   |   94 +
 .../net/ethernet/hpe/sl/ctrl/sl_ctrl_link_priv.h   |   47 +
 drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_llr.h     |   69 +
 .../ethernet/hpe/sl/ctrl/sl_ctrl_llr_counters.h    |   57 +
 drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_mac.h     |   57 +
 .../ethernet/hpe/sl/ctrl/sl_ctrl_mac_counters.h    |   43 +
 .../ethernet/hpe/sl/ctrl/sl_ctrl_media_counters.h  |   53 +
 drivers/net/ethernet/hpe/sl/log/sl_log.h           |   67 +
 .../ethernet/hpe/sl/media/base/sl_media_eeprom.h   |   16 +
 .../net/ethernet/hpe/sl/media/base/sl_media_log.h  |   36 +
 .../net/ethernet/hpe/sl/media/base/sl_media_work.h |   13 +
 .../hpe/sl/media/data/sl_media_data_cable_db.h     | 6896 ++++++++++++++
 .../hpe/sl/media/data/sl_media_data_cable_db_ops.h |   13 +
 .../hpe/sl/media/data/sl_media_data_jack.h         |   92 +
 .../hpe/sl/media/data/sl_media_data_ldev.h         |   20 +
 .../hpe/sl/media/data/sl_media_data_lgrp.h         |   20 +
 .../hpe/sl/media/data/sl_media_data_lgrp_trace.h   |   12 +
 drivers/net/ethernet/hpe/sl/media/sl_media_io.h    |   17 +
 drivers/net/ethernet/hpe/sl/media/sl_media_jack.h  |  319 +
 drivers/net/ethernet/hpe/sl/media/sl_media_ldev.h  |   33 +
 drivers/net/ethernet/hpe/sl/media/sl_media_lgrp.h  |   99 +
 drivers/net/ethernet/hpe/sl/nic/sl_asic.h          |   35 +
 drivers/net/ethernet/hpe/sl/nic/sl_asic_csrs.h     |  215 +
 drivers/net/ethernet/hpe/sl/sl.h                   |   14 +
 drivers/net/ethernet/hpe/sl/sl_ldev.h              |   25 +
 drivers/net/ethernet/hpe/sl/sl_lgrp.h              |   21 +
 drivers/net/ethernet/hpe/sl/sl_link.h              |   22 +
 drivers/net/ethernet/hpe/sl/sl_llr.h               |   20 +
 drivers/net/ethernet/hpe/sl/sl_mac.h               |   20 +
 drivers/net/ethernet/hpe/sl/sl_module.h            |   14 +
 drivers/net/ethernet/hpe/sl/sl_platform.h          |   16 +
 drivers/net/ethernet/hpe/sl/sl_test_common.h       |  105 +
 drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs.h       |  116 +
 .../net/ethernet/hpe/sl/sysfs/sl_sysfs_link_fec.h  |   12 +
 .../hpe/sl/sysfs/sl_sysfs_link_fec_current.h       |   12 +
 .../ethernet/hpe/sl/sysfs/sl_sysfs_link_fec_down.h |   12 +
 .../hpe/sl/sysfs/sl_sysfs_link_fec_mon_check.h     |   12 +
 .../ethernet/hpe/sl/sysfs/sl_sysfs_link_fec_up.h   |   12 +
 .../hpe/sl/sysfs/sl_sysfs_link_fec_up_check.h      |   12 +
 .../ethernet/hpe/sl/sysfs/sl_sysfs_serdes_eye.h    |   12 +
 .../ethernet/hpe/sl/sysfs/sl_sysfs_serdes_lol.h    |   12 +
 .../ethernet/hpe/sl/sysfs/sl_sysfs_serdes_los.h    |   12 +
 .../hpe/sl/sysfs/sl_sysfs_serdes_settings.h        |   12 +
 .../ethernet/hpe/sl/sysfs/sl_sysfs_serdes_state.h  |   12 +
 .../hpe/sl/sysfs/sl_sysfs_serdes_swizzle.h         |   14 +
 include/linux/hpe/sl/sl_fec.h                      |   39 +
 include/linux/hpe/sl/sl_ldev.h                     |  140 +
 include/linux/hpe/sl/sl_lgrp.h                     |  213 +
 include/linux/hpe/sl/sl_link.h                     |  244 +
 include/linux/hpe/sl/sl_llr.h                      |   84 +
 include/linux/hpe/sl/sl_mac.h                      |   32 +
 include/linux/hpe/sl/sl_media.h                    |  191 +
 112 files changed, 32425 insertions(+)

diff --git a/drivers/net/ethernet/hpe/sl/core/base/sl_core_log.h b/drivers/net/ethernet/hpe/sl/core/base/sl_core_log.h
new file mode 100644
index 000000000000..ba7fdfe5d059
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/base/sl_core_log.h
@@ -0,0 +1,70 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023-2026 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_LOG_H_
+#define _SL_CORE_LOG_H_
+
+#include "sl_log.h"
+
+#define SL_CORE_LOG_BLOCK                 "core"
+
+#define SL_CORE_LDEV_LOG_NAME             "ldev"
+
+#define SL_CORE_LGRP_LOG_NAME             "lgrp"
+
+#define SL_CORE_LINK_LOG_NAME             "link"
+#define SL_CORE_LINK_AN_LOG_NAME          "link-an"
+#define SL_CORE_LINK_FEC_LOG_NAME         "link-fec"
+
+#define SL_CORE_MAC_LOG_NAME              "mac"
+#define SL_CORE_LLR_LOG_NAME              "llr"
+
+#define SL_CORE_DATA_LDEV_LOG_NAME        "d-ldev"
+#define SL_CORE_DATA_LGRP_LOG_NAME        "d-lgrp"
+#define SL_CORE_DATA_LINK_LOG_NAME        "d-link"
+#define SL_CORE_DATA_MAC_LOG_NAME         "d-mac"
+#define SL_CORE_DATA_LLR_LOG_NAME         "d-llr"
+
+#define SL_CORE_TIMER_LINK_LOG_NAME       "timr-lnk"
+#define SL_CORE_TIMER_LLR_LOG_NAME        "timr-llr"
+
+#define SL_CORE_WORK_LINK_LOG_NAME        "work-lnk"
+#define SL_CORE_WORK_LLR_LOG_NAME         "work-llr"
+
+#define SL_CORE_HW_LOG_NAME               "hw"
+#define SL_CORE_HW_INTR_LOG_NAME          "hw-intr"
+#define SL_CORE_HW_INTR_LLR_LOG_NAME      "hw-i-llr"
+#define SL_CORE_HW_LINK_LOG_NAME          "hw-link"
+#define SL_CORE_HW_PCS_LOG_NAME           "hw-pcs"
+#define SL_CORE_HW_MAC_LOG_NAME           "hw-mac"
+#define SL_CORE_HW_LLR_LOG_NAME           "hw-llr"
+#define SL_CORE_HW_AN_LOG_NAME            "hw-an"
+#define SL_CORE_HW_FEC_LOG_NAME           "hw-fec"
+#define SL_CORE_HW_IO_LOG_NAME            "hw-io"
+#define SL_CORE_HW_SBUS_LOG_NAME          "hw-sbus"
+#define SL_CORE_HW_SBUS_PMI_LOG_NAME      "hw-sbpmi"
+#define SL_CORE_HW_PMI_LOG_NAME           "hw-pmi"
+
+#define SL_CORE_TEST_FEC_LOG_NAME         "test-fec"
+#define SL_CORE_TEST_AN_LOG_NAME          "test-an"
+#define SL_CORE_TEST_SERDES_LOG_NAME      "test-ser"
+
+#define SL_CORE_SERDES_LOG_NAME           "serdes"
+#define SL_CORE_RESET_LOG_NAME            "reset"
+
+#define sl_core_log_dbg(_ptr, _name, _text, ...) \
+	sl_log_dbg((_ptr), SL_CORE_LOG_BLOCK, (_name), (_text), ##__VA_ARGS__)
+#define sl_core_log_info(_ptr, _name, _text, ...) \
+	sl_log_info((_ptr), SL_CORE_LOG_BLOCK, (_name), (_text), ##__VA_ARGS__)
+#define sl_core_log_warn(_ptr, _name, _text, ...) \
+	sl_log_warn((_ptr), SL_CORE_LOG_BLOCK, (_name), (_text), ##__VA_ARGS__)
+#define sl_core_log_warn_trace(_ptr, _name, _text, ...) \
+	sl_log_warn_trace((_ptr), SL_CORE_LOG_BLOCK, (_name), (_text), ##__VA_ARGS__)
+#define sl_core_log_err(_ptr, _name, _text, ...) \
+	sl_log_err((_ptr), SL_CORE_LOG_BLOCK, (_name), (_text), ##__VA_ARGS__)
+#define sl_core_log_err_trace(_ptr, _name, _text, ...) \
+	sl_log_err_trace((_ptr), SL_CORE_LOG_BLOCK, (_name), (_text), ##__VA_ARGS__)
+#define sl_core_log_io_trace(_ptr, _name, _text, ...) \
+	sl_log_io_trace((_ptr), SL_CORE_LOG_BLOCK, (_name), (_text), ##__VA_ARGS__)
+
+#endif /* _SL_CORE_LOG_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/base/sl_core_timer_link.h b/drivers/net/ethernet/hpe/sl/core/base/sl_core_timer_link.h
new file mode 100644
index 000000000000..1fefe07e9f24
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/base/sl_core_timer_link.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2022,2023,2024 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_TIMER_LINK_H_
+#define _SL_CORE_TIMER_LINK_H_
+
+#include <linux/timer.h>
+
+struct sl_core_link;
+
+enum {
+	SL_CORE_TIMER_LINK_UP         = 0,
+	SL_CORE_TIMER_LINK_UP_CHECK,
+	SL_CORE_TIMER_LINK_UP_FEC_SETTLE,
+	SL_CORE_TIMER_LINK_UP_FEC_CHECK,
+	SL_CORE_TIMER_LINK_UP_HIGH_POWER,
+	SL_CORE_TIMER_LINK_AN_LP_CAPS_GET,
+
+	SL_CORE_TIMER_LINK_COUNT           /* must be last */
+};
+
+#define SL_CORE_TIMER_LINK_LOG_SIZE 30
+
+struct sl_core_timer_link_data {
+	struct sl_core_link *link;
+	u32                  timer_num;
+	u32                  work_num;
+	u32                  timeout_ms;
+	char                 log[SL_CORE_TIMER_LINK_LOG_SIZE + 1];
+};
+
+struct sl_core_timer_link_info {
+	struct timer_list              timer;
+	struct sl_core_timer_link_data data;
+};
+
+void sl_core_timer_link_begin(struct sl_core_link *link, u32 timer_num);
+void sl_core_timer_link_timeout(struct timer_list *timer);
+void sl_core_timer_link_end(struct sl_core_link *core_link, u32 timer_num);
+
+#endif /* _SL_CORE_TIMER_LINK_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/base/sl_core_timer_llr.h b/drivers/net/ethernet/hpe/sl/core/base/sl_core_timer_llr.h
new file mode 100644
index 000000000000..182284ffb1ef
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/base/sl_core_timer_llr.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2024 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_TIMER_LLR_H_
+#define _SL_CORE_TIMER_LLR_H_
+
+#include <linux/timer.h>
+
+struct sl_core_llr;
+
+enum {
+	SL_CORE_TIMER_LLR_SETUP = 0,
+	SL_CORE_TIMER_LLR_START,
+
+	SL_CORE_TIMER_LLR_COUNT           /* must be last */
+};
+
+#define SL_CORE_TIMER_LLR_LOG_SIZE 30
+
+struct sl_core_timer_llr_data {
+	struct sl_core_llr *core_llr;
+	u32                 timer_num;
+	u32                 work_num;
+	u32                 timeout_ms;
+	char                log[SL_CORE_TIMER_LLR_LOG_SIZE + 1];
+};
+
+struct sl_core_timer_llr_info {
+	struct timer_list             timer;
+	struct sl_core_timer_llr_data data;
+};
+
+void sl_core_timer_llr_begin(struct sl_core_llr *core_llr, u32 timer_num);
+void sl_core_timer_llr_timeout(struct timer_list *timer);
+void sl_core_timer_llr_end(struct sl_core_llr *core_llr, u32 timer_num);
+
+#endif /* _SL_CORE_TIMER_LLR_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/base/sl_core_work_link.h b/drivers/net/ethernet/hpe/sl/core/base/sl_core_work_link.h
new file mode 100644
index 000000000000..59bb461ef796
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/base/sl_core_work_link.h
@@ -0,0 +1,41 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2024,2025,2026 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_WORK_LINK_H_
+#define _SL_CORE_WORK_LINK_H_
+
+struct sl_core_link;
+
+enum {
+	SL_CORE_WORK_LINK_AN_LP_CAPS_GET            = 0,
+	SL_CORE_WORK_LINK_AN_LP_CAPS_GET_TIMEOUT,
+	SL_CORE_WORK_LINK_AN_LP_CAPS_GET_DONE,
+	SL_CORE_WORK_LINK_AN_UP_START,
+	SL_CORE_WORK_LINK_AN_UP,
+	SL_CORE_WORK_LINK_AN_UP_DONE,
+
+	SL_CORE_WORK_LINK_UP_START,
+	SL_CORE_WORK_LINK_UP,
+	SL_CORE_WORK_LINK_UP_INTR,
+	SL_CORE_WORK_LINK_UP_TIMEOUT,
+	SL_CORE_WORK_LINK_UP_CHECK,
+	SL_CORE_WORK_LINK_UP_FEC_SETTLE,
+	SL_CORE_WORK_LINK_UP_FEC_CHECK,
+	SL_CORE_WORK_LINK_UP_FAIL,
+
+	SL_CORE_WORK_LINK_HIGH_SER_INTR,
+	SL_CORE_WORK_LINK_LLR_MAX_STARVATION_INTR,
+	SL_CORE_WORK_LINK_LLR_STARVED_INTR,
+	SL_CORE_WORK_LINK_FAULT_INTR,
+
+	SL_CORE_WORK_LINK_UP_CANCEL,
+	SL_CORE_WORK_LINK_DOWN,
+
+	SL_CORE_WORK_LINK_LANE_DEGRADE_INTR,
+
+	SL_CORE_WORK_LINK_PML_REC_POLL,
+
+	SL_CORE_WORK_LINK_COUNT                         /* must be last */
+};
+
+#endif /* _SL_CORE_WORK_LINK_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/base/sl_core_work_llr.h b/drivers/net/ethernet/hpe/sl/core/base/sl_core_work_llr.h
new file mode 100644
index 000000000000..96e7546219c8
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/base/sl_core_work_llr.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2024 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_WORK_LLR_H_
+#define _SL_CORE_WORK_LLR_H_
+
+enum {
+	SL_CORE_WORK_LLR_SETUP                  = 0,
+	SL_CORE_WORK_LLR_SETUP_TIMEOUT,
+	SL_CORE_WORK_LLR_SETUP_LOOP_TIME_INTR,
+	SL_CORE_WORK_LLR_SETUP_UNEXP_LOOP_TIME_INTR,
+	SL_CORE_WORK_LLR_START,
+	SL_CORE_WORK_LLR_START_TIMEOUT,
+	SL_CORE_WORK_LLR_START_INIT_COMPLETE_INTR,
+
+	SL_CORE_WORK_LLR_COUNT                         /* must be last */
+};
+
+#endif /* _SL_CORE_WORK_LLR_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/data/sl_core_data_ldev.h b/drivers/net/ethernet/hpe/sl/core/data/sl_core_data_ldev.h
new file mode 100644
index 000000000000..0315fa995c4b
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/data/sl_core_data_ldev.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2022,2023,2024 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_DATA_LDEV_H_
+#define _SL_CORE_DATA_LDEV_H_
+
+struct sl_accessors;
+struct sl_ops;
+struct sl_core_ldev;
+struct workqueue_struct;
+
+int		     sl_core_data_ldev_new(u8 ldev_num,
+					   struct sl_accessors *accessors,
+					   struct sl_ops *ops,
+					   struct workqueue_struct *workqueue);
+int		     sl_core_data_ldev_del(u8 ldev_num);
+struct sl_core_ldev *sl_core_data_ldev_get(u8 ldev_num);
+
+#endif /* _SL_CORE_DATA_LDEV_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/data/sl_core_data_lgrp.h b/drivers/net/ethernet/hpe/sl/core/data/sl_core_data_lgrp.h
new file mode 100644
index 000000000000..8a549ffda119
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/data/sl_core_data_lgrp.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2022-2026 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_DATA_LGRP_H_
+#define _SL_CORE_DATA_LGRP_H_
+
+#include "sl_core_lgrp.h"
+
+struct sl_hw_attr;
+struct sl_lgrp_config;
+
+int		     sl_core_data_lgrp_new(u8 ldev_num, u8 lgrp_num);
+void		     sl_core_data_lgrp_connect_id_set(u8 ldev_num, u8 lgrp_num, const char *connect_id);
+int		     sl_core_data_lgrp_del(u8 ldev_num, u8 lgrp_num);
+struct sl_core_lgrp *sl_core_data_lgrp_get(u8 ldev_num, u8 lgrp_num);
+
+int  sl_core_data_lgrp_link_config_check(struct sl_core_lgrp *core_lgrp);
+void sl_core_data_lgrp_hw_attr_set(struct sl_core_lgrp *core_lgrp, struct sl_hw_attr *hw_attr);
+void sl_core_data_lgrp_config_set(struct sl_core_lgrp *core_lgrp, struct sl_lgrp_config *lgrp_config);
+int  sl_core_data_lgrp_err_trace_enable_set(struct sl_core_lgrp *core_lgrp, bool err_trace_enable);
+int  sl_core_data_lgrp_warn_trace_enable_set(struct sl_core_lgrp *core_lgrp, bool warn_trace_enable);
+int  sl_core_data_lgrp_io_trace_set(struct sl_core_lgrp *core_lgrp, bool io_trace);
+
+u32  sl_core_data_lgrp_config_flags_get(struct sl_core_lgrp *core_lgrp);
+
+#endif /* _SL_CORE_DATA_LGRP_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/data/sl_core_data_lgrp_trace.h b/drivers/net/ethernet/hpe/sl/core/data/sl_core_data_lgrp_trace.h
new file mode 100644
index 000000000000..a431a3010ffa
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/data/sl_core_data_lgrp_trace.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2025-2026 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_DATA_LGRP_TRACE_H_
+#define _SL_CORE_DATA_LGRP_TRACE_H_
+
+#include "sl_core_lgrp.h"
+
+int  sl_core_data_lgrp_is_err_trace_enabled(struct sl_core_lgrp *core_lgrp, bool *err_trace_enable);
+int  sl_core_data_lgrp_is_warn_trace_enabled(struct sl_core_lgrp *core_lgrp, bool *warn_trace_enable);
+bool sl_core_data_lgrp_is_io_trace_enabled(struct sl_core_lgrp *core_lgrp);
+
+#endif /* _SL_CORE_DATA_LGRP_TRACE_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/data/sl_core_data_link.h b/drivers/net/ethernet/hpe/sl/core/data/sl_core_data_link.h
new file mode 100644
index 000000000000..3ed99c75a024
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/data/sl_core_data_link.h
@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2022-2026 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_DATA_LINK_H_
+#define _SL_CORE_DATA_LINK_H_
+
+#include <linux/types.h>
+#include <linux/time64.h>
+
+#include "sl_core_link.h"
+
+struct sl_core_link_config;
+
+int		     sl_core_data_link_new(u8 ldev_num, u8 lgrp_num, u8 link_num);
+int		     sl_core_data_link_del(u8 ldev_num, u8 lgrp_num, u8 link_num);
+struct sl_core_link *sl_core_data_link_get(u8 ldev_num, u8 lgrp_num, u8 link_num);
+struct sl_core_link *sl_core_data_link_get_pinned(u8 ldev_num, u8 lgrp_num, u8 link_num);
+void		     sl_core_data_link_put_pinned(struct sl_core_link *core_link);
+
+void sl_core_data_link_config_set(struct sl_core_link *core_link,
+				  struct sl_core_link_config *link_config);
+int  sl_core_data_link_settings(struct sl_core_link *core_link);
+u16  sl_core_data_link_clock_period_get(void);
+void sl_core_data_link_timeouts(struct sl_core_link *core_link);
+
+void sl_core_data_link_state_set(struct sl_core_link *core_link,
+				 enum sl_core_link_state link_state);
+int  sl_core_data_link_state_get(struct sl_core_link *core_link,
+				 enum sl_core_link_state *link_state);
+
+int  sl_core_data_link_speed_get(struct sl_core_link *core_link, u32 *link_speed);
+u16  sl_core_data_link_clocking_get(struct sl_core_link *core_link);
+
+void sl_core_data_link_info_map_clr(struct sl_core_link *core_link, u32 bit_num);
+void sl_core_data_link_info_map_set(struct sl_core_link *core_link, u32 bit_num);
+u64  sl_core_data_link_info_map_get(struct sl_core_link *core_link);
+
+void sl_core_data_link_is_last_down_new_set(struct sl_core_link *core_link, bool is_last_down_new);
+void sl_core_data_link_last_down_cause_map_set(struct sl_core_link *core_link, u64 down_cause_map);
+int  sl_core_data_link_last_down_cause_map_info_get(struct sl_core_link *core_link, u8 entry_num,
+						    u64 *down_cause_map, time64_t *down_time);
+u64  sl_core_data_link_last_down_cause_map_get(struct sl_core_link *core_link);
+
+void sl_core_data_link_is_last_up_fail_new_set(struct sl_core_link *core_link, bool is_last_up_fail_new);
+void sl_core_data_link_last_up_fail_cause_map_set(struct sl_core_link *core_link, u64 up_fail_cause_map);
+int  sl_core_data_link_last_up_fail_cause_map_info_get(struct sl_core_link *core_link, u8 entry_num,
+						       u64 *up_fail_cause_map, time64_t *up_fail_time);
+u64  sl_core_data_link_last_up_fail_cause_map_get(struct sl_core_link *core_link);
+
+void sl_core_data_link_ccw_warn_limit_crossed_set(struct sl_core_link *core_link, bool is_limit_crossed);
+int  sl_core_data_link_ccw_warn_limit_crossed_get(struct sl_core_link *core_link, bool *is_limit_crossed,
+						  time64_t *limit_crossed_time);
+void sl_core_data_link_ucw_warn_limit_crossed_set(struct sl_core_link *core_link, bool is_limit_crossed);
+int  sl_core_data_link_ucw_warn_limit_crossed_get(struct sl_core_link *core_link, bool *is_limit_crossed,
+						  time64_t *limit_crossed_time);
+
+u32 sl_core_data_link_fec_mode_get(struct sl_core_link *core_link);
+u32 sl_core_data_link_fec_type_get(struct sl_core_link *core_link);
+
+u32  sl_core_data_link_an_lp_caps_state_get(struct sl_core_link *core_link);
+void sl_core_data_link_an_lp_caps_state_set(struct sl_core_link *core_link, u32 lp_caps_state);
+
+int  sl_core_data_link_an_fail_cause_get(struct sl_core_link *core_link, u32 *fail_cause, time64_t *fail_time);
+void sl_core_data_link_an_fail_cause_set(struct sl_core_link *core_link, u32 fail_cause);
+
+u32 sl_core_data_link_an_retry_count_get(struct sl_core_link *core_link);
+u32 sl_core_data_link_config_flags_get(struct sl_core_link *core_link);
+
+int sl_core_data_link_fec_up_settle_wait_ms_get(struct sl_core_link *core_link, u32 *fec_settle_wait_ms);
+int sl_core_data_link_fec_up_check_wait_ms_get(struct sl_core_link *core_link, u32 *fec_check_wait_ms);
+int sl_core_data_link_fec_up_ucw_limit_get(struct sl_core_link *core_link, s32 *fec_up_ucw_limit);
+int sl_core_data_link_fec_up_ccw_limit_get(struct sl_core_link *core_link, s32 *fec_up_ccw_limit);
+
+int sl_core_data_link_degrade_state_get(struct sl_core_link *core_link, int *state);
+int sl_core_data_link_is_rx_degrade_get(struct sl_core_link *core_link, bool *is_rx_degrade);
+int sl_core_data_link_is_tx_degrade_get(struct sl_core_link *core_link, bool *is_tx_degrade);
+int sl_core_data_link_degrade_tx_link_speed_get(struct sl_core_link *core_link, u16 *tx_link_speed);
+int sl_core_data_link_degrade_rx_link_speed_get(struct sl_core_link *core_link, u16 *rx_link_speed);
+int sl_core_data_link_degrade_tx_degrade_map_get(struct sl_core_link *core_link, u8 *tx_degrade_map);
+int sl_core_data_link_degrade_rx_degrade_map_get(struct sl_core_link *core_link, u8 *rx_degrade_map);
+int sl_core_data_link_degrade_is_recoverable_get(struct sl_core_link *core_link, bool *is_recoverable);
+
+int sl_core_data_link_pml_rec_attempts_get(struct sl_core_link *core_link, int *attempts);
+int sl_core_data_link_pml_rec_successes_get(struct sl_core_link *core_link, int *successes);
+int sl_core_data_link_pml_rec_link_fault_cause_get(struct sl_core_link *core_link, int *fault_cause);
+int sl_core_data_link_pml_rec_link_down_cause_get(struct sl_core_link *core_link, int *down_cause);
+int sl_core_data_link_pml_rec_link_fault_failed_cause_get(struct sl_core_link *core_link, int *fault_failed_cause);
+int sl_core_data_link_pml_rec_link_down_failed_cause_get(struct sl_core_link *core_link, int *down_failed_cause);
+int sl_core_data_link_pml_rec_rate_limit_exceeded_get(struct sl_core_link *core_link, int *rate_limit_exceeded);
+
+#endif /* _SL_CORE_DATA_LINK_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/data/sl_core_data_llr.h b/drivers/net/ethernet/hpe/sl/core/data/sl_core_data_llr.h
new file mode 100644
index 000000000000..f3d338363566
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/data/sl_core_data_llr.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2022,2023,2024 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_DATA_LLR_H_
+#define _SL_CORE_DATA_LLR_H_
+
+#include <linux/hpe/sl/sl_llr.h>
+
+#include "sl_core_llr.h"
+
+struct sl_llr_config;
+
+int                 sl_core_data_llr_new(u8 ldev_num, u8 lgrp_num, u8 llr_num);
+void                sl_core_data_llr_del(u8 ldev_num, u8 lgrp_num, u8 llr_num);
+struct sl_core_llr *sl_core_data_llr_get(u8 ldev_num, u8 lgrp_num, u8 llr_num);
+
+int sl_core_data_llr_config_set(struct sl_core_llr *core_llr, struct sl_llr_config *llr_config);
+int sl_core_data_llr_policy_set(struct sl_core_llr *core_llr, struct sl_llr_policy *llr_policy);
+int sl_core_data_llr_policy_get(struct sl_core_llr *core_llr, struct sl_llr_policy *llr_policy);
+
+int sl_core_data_llr_settings(struct sl_core_llr *core_llr);
+
+void sl_core_data_llr_state_set(struct sl_core_llr *core_llr,
+				enum sl_core_llr_state llr_state);
+int  sl_core_data_llr_state_get(struct sl_core_llr *core_llr,
+				enum sl_core_llr_state *llr_state);
+
+void               sl_core_data_llr_data_set(struct sl_core_llr *core_llr,
+					     struct sl_llr_data llr_data);
+struct sl_llr_data sl_core_data_llr_data_get(struct sl_core_llr *core_llr);
+void               sl_core_data_llr_data_clr(struct sl_core_llr *core_llr);
+bool               sl_core_data_llr_data_is_valid(struct sl_core_llr *core_llr);
+
+void sl_core_data_llr_info_map_clr(struct sl_core_llr *core_llr, u32 bit_num);
+void sl_core_data_llr_info_map_set(struct sl_core_llr *core_llr, u32 bit_num);
+int  sl_core_data_llr_info_map_get(struct sl_core_llr *core_llr, u64 *info_map);
+
+void sl_core_data_llr_last_fail_cause_set(struct sl_core_llr *core_llr, u32 llr_fail_cause);
+int  sl_core_data_llr_last_fail_cause_get(struct sl_core_llr *core_llr, u32 *llr_fail_cause, time64_t *llr_fail_time);
+
+int sl_core_data_llr_policy_options_get(struct sl_core_llr *core_llr, u32 *options);
+
+int sl_core_data_llr_loop_time_get(struct sl_core_llr *core_llr, u64 *loop_time);
+int sl_core_data_llr_loop_calculated_ns_get(struct sl_core_llr *core_llr, u64 *calculated);
+int sl_core_data_llr_loop_min_ns_get(struct sl_core_llr *core_llr, u64 *min_ns);
+int sl_core_data_llr_loop_max_ns_get(struct sl_core_llr *core_llr, u64 *max_ns);
+int sl_core_data_llr_loop_average_ns_get(struct sl_core_llr *core_llr, u64 *average_ns);
+
+#endif /* _SL_CORE_DATA_LLR_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/data/sl_core_data_mac.h b/drivers/net/ethernet/hpe/sl/core/data/sl_core_data_mac.h
new file mode 100644
index 000000000000..a7d739b64506
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/data/sl_core_data_mac.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2022,2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_DATA_MAC_H_
+#define _SL_CORE_DATA_MAC_H_
+
+struct sl_core_mac;
+
+int                 sl_core_data_mac_new(u8 ldev_num, u8 lgrp_num, u8 mac_num);
+void                sl_core_data_mac_del(u8 ldev_num, u8 lgrp_num, u8 mac_num);
+struct sl_core_mac *sl_core_data_mac_get(u8 ldev_num, u8 lgrp_num, u8 mac_num);
+
+int  sl_core_data_mac_tx_settings(struct sl_core_mac *core_mac);
+u8   sl_core_data_mac_tx_cdt_init_get(void);
+int  sl_core_data_mac_rx_settings(struct sl_core_mac *core_mac);
+
+u32  sl_core_data_mac_tx_state_get(struct sl_core_mac *core_mac);
+u32  sl_core_data_mac_rx_state_get(struct sl_core_mac *core_mac);
+
+void sl_core_data_mac_info_map_clr(struct sl_core_mac *core_mac, u32 bit_num);
+void sl_core_data_mac_info_map_set(struct sl_core_mac *core_mac, u32 bit_num);
+u64  sl_core_data_mac_info_map_get(struct sl_core_mac *core_mac);
+
+#endif /* _SL_CORE_DATA_MAC_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/nic/sl_core_hw_intr_flgs.h b/drivers/net/ethernet/hpe/sl/core/hw/nic/sl_core_hw_intr_flgs.h
new file mode 100644
index 000000000000..72c380dad595
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/nic/sl_core_hw_intr_flgs.h
@@ -0,0 +1,70 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023-2026 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_HW_INTR_FLGS_H_
+#define _SL_CORE_HW_INTR_FLGS_H_
+
+#include "sl_asic.h"
+
+#define SL_CORE_HW_INTR_FLGS_LINK_UP(_link_num)                                        \
+	static union ss2_port_pml_err_flg sl_core_hw_intr_flgs_link_up_##_link_num = { \
+		.pcs_link_up_##_link_num = 1,                                          \
+	}
+SL_CORE_HW_INTR_FLGS_LINK_UP(0);
+
+#define SL_CORE_HW_INTR_FLGS_LINK_HIGH_SER(_link_num)                                        \
+	static union ss2_port_pml_err_flg sl_core_hw_intr_flgs_link_high_ser_##_link_num = { \
+		.pcs_hi_ser_##_link_num               = 1,                                   \
+	}
+SL_CORE_HW_INTR_FLGS_LINK_HIGH_SER(0);
+
+#define SL_CORE_HW_INTR_FLGS_LINK_LLR_MAX_STARVATION(_link_num)                                        \
+	static union ss2_port_pml_err_flg sl_core_hw_intr_flgs_link_llr_max_starvation_##_link_num = { \
+		.llr_max_starvation_limit_##_link_num = 1,                                             \
+	}
+SL_CORE_HW_INTR_FLGS_LINK_LLR_MAX_STARVATION(0);
+
+#define SL_CORE_HW_INTR_FLGS_LINK_LLR_STARVED(_link_num)                                        \
+	static union ss2_port_pml_err_flg sl_core_hw_intr_flgs_link_llr_starved_##_link_num = { \
+		.llr_starved_##_link_num              = 1,                                      \
+	}
+SL_CORE_HW_INTR_FLGS_LINK_LLR_STARVED(0);
+
+#define SL_CORE_HW_INTR_FLGS_LINK_FAULT(_link_num)                                        \
+	static union ss2_port_pml_err_flg sl_core_hw_intr_flgs_link_fault_##_link_num = { \
+		.llr_replay_at_max_##_link_num = 1,                                       \
+		.pcs_link_down_##_link_num     = 1,                                       \
+		.pcs_link_down_lf_##_link_num  = 1,                                       \
+		.pcs_link_down_rf_##_link_num  = 1,                                       \
+	}
+SL_CORE_HW_INTR_FLGS_LINK_FAULT(0);
+
+#define SL_CORE_HW_INTR_FLGS_AN_PAGE_RECV(_link_num)                                        \
+	static union ss2_port_pml_err_flg sl_core_hw_intr_flgs_an_page_recv_##_link_num = { \
+		.autoneg_page_received_##_link_num = 1,                                     \
+	}
+SL_CORE_HW_INTR_FLGS_AN_PAGE_RECV(0);
+
+#define SL_CORE_HW_INTR_FLGS_LANE_DEGRADE(_link_num)                                        \
+	static union ss2_port_pml_err_flg sl_core_hw_intr_flgs_lane_degrade_##_link_num = { \
+		.pcs_tx_degrade = 1,                                                        \
+		.pcs_rx_degrade = 1,                                                        \
+	}
+SL_CORE_HW_INTR_FLGS_LANE_DEGRADE(0);
+
+#define SL_CORE_HW_INTR_FLGS_ITEM(_num, _which)       \
+	[_num] = {                                    \
+		sl_core_hw_intr_flgs_##_which##_0.qw, \
+	}
+
+static u64 *sl_core_hw_intr_flgs[SL_CORE_HW_INTR_COUNT][SL_ASIC_MAX_LINKS] = {
+	SL_CORE_HW_INTR_FLGS_ITEM(SL_CORE_HW_INTR_LINK_UP,                 link_up),
+	SL_CORE_HW_INTR_FLGS_ITEM(SL_CORE_HW_INTR_LINK_HIGH_SER,           link_high_ser),
+	SL_CORE_HW_INTR_FLGS_ITEM(SL_CORE_HW_INTR_LINK_LLR_MAX_STARVATION, link_llr_max_starvation),
+	SL_CORE_HW_INTR_FLGS_ITEM(SL_CORE_HW_INTR_LINK_LLR_STARVED,        link_llr_starved),
+	SL_CORE_HW_INTR_FLGS_ITEM(SL_CORE_HW_INTR_LINK_FAULT,              link_fault),
+	SL_CORE_HW_INTR_FLGS_ITEM(SL_CORE_HW_INTR_AN_PAGE_RECV,            an_page_recv),
+	SL_CORE_HW_INTR_FLGS_ITEM(SL_CORE_HW_INTR_LANE_DEGRADE,            lane_degrade),
+};
+
+#endif /* _SL_CORE_HW_INTR_FLGS_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/nic/sl_core_hw_intr_flgs_llr.h b/drivers/net/ethernet/hpe/sl/core/hw/nic/sl_core_hw_intr_flgs_llr.h
new file mode 100644
index 000000000000..b078808adc80
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/nic/sl_core_hw_intr_flgs_llr.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2024,2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_HW_INTR_FLGS_LLR_H_
+#define _SL_CORE_HW_INTR_FLGS_LLR_H_
+
+#include "sl_asic.h"
+
+#define SL_CORE_HW_INTR_FLGS_LLR_UNEXP_LOOP_TIME(_llr_num)                                              \
+	static union ss2_port_pml_err_flg sl_core_hw_intr_flgs_llr_setup_unexp_loop_time_##_llr_num = { \
+	}
+SL_CORE_HW_INTR_FLGS_LLR_UNEXP_LOOP_TIME(0);
+
+#define SL_CORE_HW_INTR_FLGS_LLR_LOOP_TIME(_llr_num)                                              \
+	static union ss2_port_pml_err_flg sl_core_hw_intr_flgs_llr_setup_loop_time_##_llr_num = { \
+		.llr_loop_time_##_llr_num = 1,                                                    \
+	}
+SL_CORE_HW_INTR_FLGS_LLR_LOOP_TIME(0);
+
+#define SL_CORE_HW_INTR_FLGS_LLR_INIT_COMPLETE(_llr_num)                                              \
+	static union ss2_port_pml_err_flg sl_core_hw_intr_flgs_llr_start_init_complete_##_llr_num = { \
+		.llr_init_complete_##_llr_num = 1,                                                    \
+	}
+SL_CORE_HW_INTR_FLGS_LLR_INIT_COMPLETE(0);
+
+#define SL_CORE_HW_INTR_FLGS_LLR_ITEM(_num, _which)       \
+	[_num] = {                                        \
+		sl_core_hw_intr_flgs_llr_##_which##_0.qw, \
+	}
+
+static u64 *sl_core_hw_intr_flgs_llr[SL_CORE_HW_INTR_LLR_COUNT][SL_ASIC_MAX_LINKS] = {
+	SL_CORE_HW_INTR_FLGS_LLR_ITEM(SL_CORE_HW_INTR_LLR_SETUP_UNEXP_LOOP_TIME, setup_unexp_loop_time),
+	SL_CORE_HW_INTR_FLGS_LLR_ITEM(SL_CORE_HW_INTR_LLR_SETUP_LOOP_TIME,       setup_loop_time),
+	SL_CORE_HW_INTR_FLGS_LLR_ITEM(SL_CORE_HW_INTR_LLR_START_INIT_COMPLETE,   start_init_complete),
+};
+
+#endif /* _SL_CORE_HW_INTR_FLGS_LLR_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/nic/sl_core_hw_serdes_firmware.h b/drivers/net/ethernet/hpe/sl/core/hw/nic/sl_core_hw_serdes_firmware.h
new file mode 100644
index 000000000000..d17b640755e1
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/nic/sl_core_hw_serdes_firmware.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_HW_SERDES_FIRMWARE_H_
+#define _SL_CORE_HW_SERDES_FIRMWARE_H_
+
+#define SL_HW_SERDES_FW_FILE          "sl_fw_quad_3.04.bin"
+#define SL_HW_SERDES_FW_IMAGE_CRC     0xA744 /* from the ucode file */
+#define SL_HW_SERDES_FW_STACK_SIZE    0x13E4 /* from the ucode file */
+
+#endif /* _SL_CORE_HW_SERDES_FIRMWARE_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_an.h b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_an.h
new file mode 100644
index 000000000000..827113c62f81
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_an.h
@@ -0,0 +1,112 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2022,2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_HW_AN_H_
+#define _SL_CORE_HW_AN_H_
+
+struct sl_core_link;
+struct work_struct;
+
+/* base page */
+#define SL_CORE_HW_AN_BP_BIT_FEC_10G_REQUESTED     47 /* F1 */
+#define SL_CORE_HW_AN_BP_BIT_FEC_10G_ABILITY       46 /* F0 */
+#define SL_CORE_HW_AN_BP_BIT_FEC_25G_BASE_R        45 /* F3 */
+#define SL_CORE_HW_AN_BP_BIT_FEC_25G_RS            44 /* F2 */
+/* bits [43:40] other technology */
+#define SL_CORE_HW_AN_BP_BIT_400G_BASE_xR_4        39
+#define SL_CORE_HW_AN_BP_BIT_200G_BASE_xR_2        38
+#define SL_CORE_HW_AN_BP_BIT_100G_BASE_xR_1        37
+#define SL_CORE_HW_AN_BP_BIT_200G_BASE_xR_4        36
+#define SL_CORE_HW_AN_BP_BIT_100G_BASE_xR_2        35
+#define SL_CORE_HW_AN_BP_BIT_50G_BASE_xR           34
+/* bits [33:32] other technology */
+#define SL_CORE_HW_AN_BP_BIT_25G_BASE_KR           31
+#define SL_CORE_HW_AN_BP_BIT_25G_BASE_KR_S         30
+#define SL_CORE_HW_AN_BP_BIT_100G_BASE_CR_4        29
+#define SL_CORE_HW_AN_BP_BIT_100G_BASE_KR_4        28
+/* bits [27:21] other technology */
+#define SL_CORE_HW_AN_BP_BIT_TRANS_NONCE           16 /* [20:16] */
+#define SL_CORE_HW_AN_BP_BIT_NP                    15
+#define SL_CORE_HW_AN_BP_BIT_ACK                   14
+#define SL_CORE_HW_AN_BP_BIT_RF                    13
+/* bit 12 PAUSE_reserved */
+#define SL_CORE_HW_AN_BP_BIT_PAUSE_ASYMETRIC       11
+#define SL_CORE_HW_AN_BP_BIT_PAUSE_SYMETRIC        10
+/* bits [9:5] ECHO_NONCE */
+#define SL_CORE_HW_AN_BP_BIT_SELECTOR               0 /* [4:0] */
+#define SL_CORE_HW_AN_BP_802_3                     (BIT_ULL(0) << SL_CORE_HW_AN_BP_BIT_SELECTOR)
+
+/* next page */
+#define SL_CORE_HW_AN_NP_BIT_OUI_ASIC_VER          32
+#define SL_CORE_HW_AN_NP_BIT_OUI_OPTS              24
+#define SL_CORE_HW_AN_NP_BIT_OUI_OPT_LLR           (0 + SL_CORE_HW_AN_NP_BIT_OUI_OPTS)
+#define SL_CORE_HW_AN_NP_BIT_OUI_OPT_ETHER_LLR     (1 + SL_CORE_HW_AN_NP_BIT_OUI_OPTS)
+#define SL_CORE_HW_AN_NP_BIT_OUI_OPT_HPC_WITH_LLR  (2 + SL_CORE_HW_AN_NP_BIT_OUI_OPTS)
+#define SL_CORE_HW_AN_NP_BIT_OUI                   16
+#define SL_CORE_HW_AN_NP_BIT_NP                    15
+#define SL_CORE_HW_AN_NP_BIT_ACK                   14
+#define SL_CORE_HW_AN_NP_BIT_MP                    13
+#define SL_CORE_HW_AN_NP_BIT_ACK2                  12
+#define SL_CORE_HW_AN_NP_BIT_T                     11
+#define SL_CORE_HW_AN_NP_MSG_NULL                  (BIT_ULL(0) | (BIT_ULL(0) << SL_CORE_HW_AN_NP_BIT_MP))
+#define SL_CORE_HW_AN_NP_MSG_OUI                   0x5ULL
+#define SL_CORE_HW_AN_NP_MSG_OUI_EXTD              0xBULL
+#define SL_CORE_HW_AN_NP_MSG_MASK                  0x7FFULL
+#define SL_CORE_HW_AN_NP_OUI_HPE                   (0xEC9B8BULL << SL_CORE_HW_AN_NP_BIT_OUI)
+#define SL_CORE_HW_AN_NP_OUI_HPE_MASK              (0xFFFFFFULL << SL_CORE_HW_AN_NP_BIT_OUI)
+#define SL_CORE_HW_AN_NP_OUI_VER_0_1               (0x01ULL << SL_CORE_HW_AN_NP_BIT_OUI)
+#define SL_CORE_HW_AN_NP_OUI_VER_0_2               (0x02ULL << SL_CORE_HW_AN_NP_BIT_OUI)
+#define SL_CORE_HW_AN_NP_OUI_VER_MASK              (0xFFULL << SL_CORE_HW_AN_NP_BIT_OUI)
+
+/* link caps */
+#define SL_CORE_HW_AN_BP_PAUSE_SHIFT 10
+#define SL_CORE_HW_AN_BP_TECH_SHIFT  21
+#define SL_CORE_HW_AN_BP_FEC_SHIFT   44
+#define SL_CORE_HW_AN_NP_HPE_SHIFT   24
+
+enum sl_core_hw_an_state {
+	SL_CORE_HW_AN_STATE_START     = 0,
+	SL_CORE_HW_AN_STATE_BASE,
+	SL_CORE_HW_AN_STATE_NEXT,
+	SL_CORE_HW_AN_STATE_RETRY,
+	SL_CORE_HW_AN_STATE_COMPLETE,
+	SL_CORE_HW_AN_STATE_LP_DONE,
+	SL_CORE_HW_AN_STATE_ERROR,
+};
+
+#define SL_CORE_HW_AN_FAIL_CAUSE_NONE                           0
+#define SL_CORE_HW_AN_FAIL_CAUSE_LP_CAPS_SERDES_LINK_UP_FAIL    BIT(0)
+#define SL_CORE_HW_AN_FAIL_CAUSE_LP_CAPS_NOT_COMPLETE           BIT(1)
+#define SL_CORE_HW_AN_FAIL_CAUSE_NOT_COMPLETE                   BIT(2)
+#define SL_CORE_HW_AN_FAIL_CAUSE_TEST_CAPS_NOMATCH              BIT(3)
+#define SL_CORE_HW_AN_FAIL_CAUSE_SERDES_LINK_UP_FAIL            BIT(4)
+#define SL_CORE_HW_AN_FAIL_CAUSE_BP_STORE_STATE_BAD             BIT(5)
+#define SL_CORE_HW_AN_FAIL_CAUSE_BP_STORE_LP_ABILITY_NOT_SET    BIT(6)
+#define SL_CORE_HW_AN_FAIL_CAUSE_BP_STORE_STATE_ERROR           BIT(7)
+#define SL_CORE_HW_AN_FAIL_CAUSE_BP_STORE_BP_NOT_SET            BIT(8)
+#define SL_CORE_HW_AN_FAIL_CAUSE_BP_SEND_INTR_ENABLE_FAIL       BIT(9)
+#define SL_CORE_HW_AN_FAIL_CAUSE_NP_STORE_STATE_BAD             BIT(10)
+#define SL_CORE_HW_AN_FAIL_CAUSE_NP_STORE_BP_SET                BIT(11)
+#define SL_CORE_HW_AN_FAIL_CAUSE_NP_CHECK_STATE_BAD             BIT(12)
+#define SL_CORE_HW_AN_FAIL_CAUSE_INTR_STATE_INVALID             BIT(13)
+#define SL_CORE_HW_AN_FAIL_CAUSE_INTR_AN_RETRY_NP_SEND_FAIL     BIT(14)
+#define SL_CORE_HW_AN_FAIL_CAUSE_INTR_OUT_OF_PAGES              BIT(15)
+#define SL_CORE_HW_AN_FAIL_CAUSE_INTR_NP_SEND_FAIL              BIT(16)
+#define SL_CORE_HW_AN_FAIL_CAUSE_PAGES_DECODE_FAIL              BIT(17)
+#define SL_CORE_HW_AN_FAIL_CAUSE_PAGES_DECODE_NO_BP             BIT(18)
+#define SL_CORE_HW_AN_FAIL_CAUSE_PAGES_DECODE_OUI_INVALID       BIT(19)
+
+void sl_core_hw_an_intr_hdlr(u64 *err_flgs, int num_err_flgs, void *data);
+
+void sl_core_hw_an_tx_pages_encode(struct sl_core_link *core_link,
+				   struct sl_link_caps *my_caps);
+void sl_core_hw_an_stop(struct sl_core_link *core_link);
+void sl_core_hw_an_init(struct sl_core_link *core_link);
+void sl_core_hw_an_config(struct sl_core_link *core_link);
+void sl_core_hw_an_config_timers(struct sl_core_link *core_link);
+int  sl_core_hw_an_base_page_send(struct sl_core_link *core_link);
+int  sl_core_hw_an_rx_pages_decode(struct sl_core_link *core_link,
+				   struct sl_link_caps *my_caps,
+				   struct sl_link_caps *link_caps);
+
+#endif /* _SL_CORE_HW_AN_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_an_lp.h b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_an_lp.h
new file mode 100644
index 000000000000..31d349abb75f
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_an_lp.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2022,2023,2024 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_HW_AN_LP_H_
+#define _SL_CORE_HW_AN_LP_H_
+
+#include "sl_core_link_an.h"
+
+struct sl_core_link;
+struct sl_link_caps;
+struct work_struct;
+
+void sl_core_hw_an_lp_caps_get_cmd(struct sl_core_link *core_link,
+				   enum sl_core_link_state link_state,
+				   sl_core_link_an_callback_t callback, void *tag,
+				   struct sl_link_caps *caps, u32 timeout_ms, u32 flags);
+void sl_core_hw_an_lp_caps_stop_cmd(struct sl_core_link *core_link);
+
+void sl_core_hw_an_lp_caps_get_work(struct work_struct *work);
+void sl_core_hw_an_lp_caps_get_timeout_work(struct work_struct *work);
+void sl_core_hw_an_lp_caps_get_done_work(struct work_struct *work);
+
+#endif /* _SL_CORE_HW_AN_LP_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_an_up.h b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_an_up.h
new file mode 100644
index 000000000000..b6dda5d0ec36
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_an_up.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2022,2023,2024 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_HW_AN_UP_H_
+#define _SL_CORE_HW_AN_UP_H_
+
+struct sl_core_link;
+struct work_struct;
+
+void sl_core_hw_an_up_start_work(struct work_struct *work);
+
+void sl_core_hw_an_up_work(struct work_struct *work);
+void sl_core_hw_an_up_done_work(struct work_struct *work);
+
+#endif /* _SL_CORE_HW_AN_UP_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_fec.h b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_fec.h
new file mode 100644
index 000000000000..9647b3d6ff19
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_fec.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023,2024 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_HW_FEC_H_
+#define _SL_CORE_HW_FEC_H_
+
+struct sl_core_link;
+struct sl_core_link_fec_cw_cntrs;
+struct sl_core_link_fec_lane_cntrs;
+struct sl_core_link_fec_tail_cntrs;
+
+int sl_core_hw_fec_cw_cntrs_get(struct sl_core_link *core_link,
+				struct sl_core_link_fec_cw_cntrs *cw_cntrs);
+int sl_core_hw_fec_lane_cntrs_get(struct sl_core_link *core_link,
+				  struct sl_core_link_fec_lane_cntrs *lane_cntrs);
+int sl_core_hw_fec_tail_cntrs_get(struct sl_core_link *core_link,
+				  struct sl_core_link_fec_tail_cntrs *tail_cntrs);
+int sl_core_hw_fec_data_get(struct sl_core_link *core_link,
+			    struct sl_core_link_fec_cw_cntrs *cw_cntrs,
+			    struct sl_core_link_fec_lane_cntrs *lane_cntrs,
+			    struct sl_core_link_fec_tail_cntrs *tail_cntrs);
+
+#endif /* _SL_CORE_HW_FEC_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_intr.h b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_intr.h
new file mode 100644
index 000000000000..135f2e902f76
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_intr.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2022,2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_HW_INTR_H_
+#define _SL_CORE_HW_INTR_H_
+
+#include "sl_asic.h"
+
+struct sl_core_link;
+
+enum {
+	SL_CORE_HW_INTR_LINK_UP                  = 0,
+	SL_CORE_HW_INTR_LINK_HIGH_SER,
+	SL_CORE_HW_INTR_LINK_LLR_MAX_STARVATION,
+	SL_CORE_HW_INTR_LINK_LLR_STARVED,
+	SL_CORE_HW_INTR_LINK_FAULT,
+	SL_CORE_HW_INTR_AN_PAGE_RECV,
+	SL_CORE_HW_INTR_LANE_DEGRADE,
+
+	SL_CORE_HW_INTR_COUNT                    /* must be last */
+};
+
+#define SL_CORE_HW_INTR_FLGS_COUNT ((int)(SS2_PORT_PML_ERR_FLG_SIZE / sizeof(u64)))
+
+typedef void (*sl_core_hw_intr_hdlr_t)(u64 *err_flgs, int num_err_flgs, void *data);
+
+#define SL_CORE_HW_INTR_LOG_SIZE 30
+
+struct sl_core_hw_intr_data {
+	struct sl_core_link *link;
+	u32                  intr_num;
+	u32                  work_num;
+	char                 log[SL_CORE_HW_INTR_LOG_SIZE + 1];
+};
+
+struct sl_core_hw_intr_info {
+	u64                         *flgs;
+	struct sl_core_hw_intr_data  data;
+	u64                          source[SL_CORE_HW_INTR_FLGS_COUNT];
+};
+
+void sl_core_hw_intr_hdlr(u64 *err_flgs, int num_err_flgs, void *data);
+
+int  sl_core_hw_intr_hdlr_register(struct sl_core_link *link);
+void sl_core_hw_intr_hdlr_unregister(struct sl_core_link *link);
+
+void sl_core_hw_intr_flgs_check(struct sl_core_link *link, u32 which);
+void sl_core_hw_intr_flgs_clr(struct sl_core_link *link, u32 which);
+int  sl_core_hw_intr_flgs_enable(struct sl_core_link *link, u32 which);
+int  sl_core_hw_intr_flgs_disable(struct sl_core_link *link, u32 which);
+
+#endif /* _SL_CORE_HW_INTR_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_intr_llr.h b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_intr_llr.h
new file mode 100644
index 000000000000..82f5d5344a29
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_intr_llr.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2024 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_HW_INTR_LLR_H_
+#define _SL_CORE_HW_INTR_LLR_H_
+
+#include "sl_asic.h"
+
+struct sl_core_llr;
+
+enum {
+	SL_CORE_HW_INTR_LLR_SETUP_UNEXP_LOOP_TIME   = 0,
+	SL_CORE_HW_INTR_LLR_SETUP_LOOP_TIME,
+	SL_CORE_HW_INTR_LLR_START_INIT_COMPLETE,
+
+	SL_CORE_HW_INTR_LLR_COUNT                    /* must be last */
+};
+
+#define SL_CORE_HW_INTR_LLR_FLGS_COUNT ((int)(SS2_PORT_PML_ERR_FLG_SIZE / sizeof(u64)))
+
+typedef void (*sl_core_hw_intr_llr_hdlr_t)(u64 *err_flgs, int num_err_flgs, void *data);
+
+#define SL_CORE_HW_INTR_LLR_LOG_SIZE 30
+
+struct sl_core_hw_intr_llr_data {
+	struct sl_core_llr *core_llr;
+	u32                 intr_num;
+	u32                 work_num;
+	char                log[SL_CORE_HW_INTR_LLR_LOG_SIZE + 1];
+};
+
+struct sl_core_hw_intr_llr_info {
+	u64                             *flgs;
+	struct sl_core_hw_intr_llr_data  data;
+	u64                              source[SL_CORE_HW_INTR_LLR_FLGS_COUNT];
+};
+
+void sl_core_hw_intr_llr_hdlr(u64 *err_flgs, int num_err_flgs, void *data);
+
+int  sl_core_hw_intr_llr_hdlr_register(struct sl_core_llr *core_llr);
+void sl_core_hw_intr_llr_hdlr_unregister(struct sl_core_llr *core_llr);
+
+void sl_core_hw_intr_llr_flgs_check(struct sl_core_llr *core_llr, u32 which);
+void sl_core_hw_intr_llr_flgs_clr(struct sl_core_llr *core_llr, u32 which);
+int  sl_core_hw_intr_llr_flgs_enable(struct sl_core_llr *core_llr, u32 which);
+int  sl_core_hw_intr_llr_flgs_disable(struct sl_core_llr *core_llr, u32 which);
+
+#endif /* _SL_CORE_HW_INTR_LLR_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_io.h b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_io.h
new file mode 100644
index 000000000000..455e533fdfaf
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_io.h
@@ -0,0 +1,308 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2022-2026 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_HW_IO_H_
+#define _SL_CORE_HW_IO_H_
+
+#include <linux/hpe/sl/sl_ldev.h>
+
+#include "sl_core_ldev.h"
+#include "sl_core_lgrp.h"
+#include "sl_core_link.h"
+#include "sl_core_mac.h"
+#include "sl_core_llr.h"
+
+static inline void sl_core_lgrp_flush64(struct sl_core_lgrp *core_lgrp, u64 addr)
+{
+	(void)core_lgrp->core_ldev->ops.read64(
+		core_lgrp->core_ldev->accessors.pci, addr);
+
+	sl_core_log_dbg(core_lgrp, SL_CORE_HW_IO_LOG_NAME,
+			"FLSH (addr = 0x%016llX)", addr);
+}
+
+static inline void sl_core_lgrp_read64(struct sl_core_lgrp *core_lgrp, u64 addr, u64 *data64)
+{
+	*data64 = core_lgrp->core_ldev->ops.read64(
+		core_lgrp->core_ldev->accessors.pci, addr);
+
+	sl_core_log_dbg(core_lgrp, SL_CORE_HW_IO_LOG_NAME,
+			"RD64 (addr = 0x%016llX, data = 0x%016llX)", addr, *data64);
+}
+
+static inline void sl_core_lgrp_write64(struct sl_core_lgrp *core_lgrp, u64 addr, u64 data64)
+{
+	core_lgrp->core_ldev->ops.write64(
+		core_lgrp->core_ldev->accessors.pci, addr, data64);
+
+	sl_core_log_dbg(core_lgrp, SL_CORE_HW_IO_LOG_NAME,
+			"WR64 (addr = 0x%016llX, data = 0x%016llX)", addr, data64);
+}
+
+static inline void sl_core_flush64(struct sl_core_link *core_link, u64 addr)
+{
+	(void)core_link->core_lgrp->core_ldev->ops.read64(
+		core_link->core_lgrp->core_ldev->accessors.pci, addr);
+
+	sl_core_log_dbg(core_link, SL_CORE_HW_IO_LOG_NAME,
+			"FLSH (addr = 0x%016llX)", addr);
+}
+
+static inline void sl_core_read64(struct sl_core_link *core_link, u64 addr, u64 *data64)
+{
+	*data64 = core_link->core_lgrp->core_ldev->ops.read64(
+		core_link->core_lgrp->core_ldev->accessors.pci, addr);
+
+	sl_core_log_dbg(core_link, SL_CORE_HW_IO_LOG_NAME,
+			"RD64 (addr = 0x%016llX, data = 0x%016llX)", addr, *data64);
+}
+
+static inline void sl_core_write64(struct sl_core_link *core_link, u64 addr, u64 data64)
+{
+	core_link->core_lgrp->core_ldev->ops.write64(
+		core_link->core_lgrp->core_ldev->accessors.pci, addr, data64);
+
+	sl_core_log_dbg(core_link, SL_CORE_HW_IO_LOG_NAME,
+			"WR64 (addr = 0x%016llX, data = 0x%016llX)", addr, data64);
+}
+
+static inline void sl_core_mac_flush64(struct sl_core_mac *core_mac, u64 addr)
+{
+	(void)core_mac->core_lgrp->core_ldev->ops.read64(
+		core_mac->core_lgrp->core_ldev->accessors.pci, addr);
+
+	sl_core_log_dbg(core_mac, SL_CORE_HW_IO_LOG_NAME,
+			"FLSH (addr = 0x%016llX)", addr);
+}
+
+static inline void sl_core_mac_read64(struct sl_core_mac *core_mac, u64 addr, u64 *data64)
+{
+	*data64 = core_mac->core_lgrp->core_ldev->ops.read64(
+		core_mac->core_lgrp->core_ldev->accessors.pci, addr);
+
+	sl_core_log_dbg(core_mac, SL_CORE_HW_IO_LOG_NAME,
+			"RD64 (addr = 0x%016llX, data = 0x%016llX)", addr, *data64);
+}
+
+static inline void sl_core_mac_write64(struct sl_core_mac *core_mac, u64 addr, u64 data64)
+{
+	core_mac->core_lgrp->core_ldev->ops.write64(
+		core_mac->core_lgrp->core_ldev->accessors.pci, addr, data64);
+
+	sl_core_log_dbg(core_mac, SL_CORE_HW_IO_LOG_NAME,
+			"WR64 (addr = 0x%016llX, data = 0x%016llX)", addr, data64);
+}
+
+static inline void sl_core_llr_write64(struct sl_core_llr *core_llr, u64 addr, u64 data64)
+{
+	core_llr->core_lgrp->core_ldev->ops.write64(
+		core_llr->core_lgrp->core_ldev->accessors.pci, addr, data64);
+
+	sl_core_log_dbg(core_llr, SL_CORE_HW_IO_LOG_NAME,
+			"WR64 (addr = 0x%016llX, data = 0x%016llX)", addr, data64);
+}
+
+static inline void sl_core_llr_flush64(struct sl_core_llr *core_llr, u64 addr)
+{
+	(void)core_llr->core_lgrp->core_ldev->ops.read64(
+		core_llr->core_lgrp->core_ldev->accessors.pci, addr);
+
+	sl_core_log_dbg(core_llr, SL_CORE_HW_IO_LOG_NAME,
+			"FLSH (addr = 0x%016llX)", addr);
+}
+
+static inline void sl_core_llr_read64(struct sl_core_llr *core_llr, u64 addr, u64 *data64)
+{
+	*data64 = core_llr->core_lgrp->core_ldev->ops.read64(
+		core_llr->core_lgrp->core_ldev->accessors.pci, addr);
+
+	sl_core_log_dbg(core_llr, SL_CORE_HW_IO_LOG_NAME,
+			"RD64 (addr = 0x%016llX, data = 0x%016llX)", addr, *data64);
+}
+
+static inline int sl_core_pmi_rd(struct sl_core_lgrp *core_lgrp, u32 addr, u16 *data)
+{
+	int rtn;
+
+	rtn = core_lgrp->core_ldev->ops.pmi_op(core_lgrp->core_ldev->accessors.pmi,
+					       core_lgrp->num, SL_PMI_OP_RD, addr, data, 0, 0);
+
+	sl_core_log_io_trace(core_lgrp, SL_CORE_HW_IO_LOG_NAME,
+			     "PMI RD (rtn = %d, addr = 0x%08X, data = 0x%04X)", rtn, addr, *data);
+
+	return rtn;
+}
+
+static inline int sl_core_pmi_wr(struct sl_core_lgrp *core_lgrp, u32 addr, u16 data, u16 mask)
+{
+	int rtn;
+
+	rtn = core_lgrp->core_ldev->ops.pmi_op(core_lgrp->core_ldev->accessors.pmi,
+					       core_lgrp->num, SL_PMI_OP_WR, addr, NULL, data, mask);
+
+	sl_core_log_io_trace(core_lgrp, SL_CORE_HW_IO_LOG_NAME,
+			     "PMI WR (rtn = %d, addr = 0x%08X, data = 0x%04X, mask = 0x%04X)",
+			     rtn, addr, data, mask);
+
+	return rtn;
+}
+
+static inline int sl_core_sbus_wr(struct sl_core_lgrp *core_lgrp, u32 dev_addr, u8 reg, u32 data)
+{
+	int rtn;
+
+	rtn = core_lgrp->core_ldev->ops.sbus_op(core_lgrp->core_ldev->accessors.sbus, SL_SBUS_OP_WR,
+						core_lgrp->serdes.dt.sbus_ring, dev_addr, reg, NULL, data);
+
+	sl_core_log_io_trace(core_lgrp, SL_CORE_HW_IO_LOG_NAME,
+			     "SBUS WR (rtn = %d, dev_addr = 0x%02X, reg = 0x%02X, data = 0x%08X)",
+			     rtn, dev_addr, reg, data);
+
+	return rtn;
+}
+
+static inline int sl_core_sbus_rd(struct sl_core_lgrp *core_lgrp, u32 dev_addr, u8 reg, u32 *data)
+{
+	int rtn;
+
+	rtn = core_lgrp->core_ldev->ops.sbus_op(core_lgrp->core_ldev->accessors.sbus, SL_SBUS_OP_RD,
+						core_lgrp->serdes.dt.sbus_ring, dev_addr, reg, data, 0);
+
+	sl_core_log_io_trace(core_lgrp, SL_CORE_HW_IO_LOG_NAME,
+			     "SBUS RD (rtn = %d, dev_addr = 0x%02X, reg = 0x%02X, data = 0x%08X)",
+			     rtn, dev_addr, reg, *data);
+
+	return rtn;
+}
+
+static inline int sl_core_sbus_rst(struct sl_core_lgrp *core_lgrp, u32 dev_addr)
+{
+	int rtn;
+
+	rtn = core_lgrp->core_ldev->ops.sbus_op(core_lgrp->core_ldev->accessors.sbus, SL_SBUS_OP_RST,
+						core_lgrp->serdes.dt.sbus_ring, dev_addr, 0, NULL, 0);
+
+	sl_core_log_io_trace(core_lgrp, SL_CORE_HW_IO_LOG_NAME,
+			     "SBUS RST (rtn = %d, dev_addr = 0x%02X", rtn, dev_addr);
+
+	return rtn;
+}
+
+static inline int sl_core_hw_intr_register(struct sl_core_link *link,
+					   u64 *err_flgs, sl_intr_handler_t handler, void *data)
+{
+	sl_core_log_dbg(link, SL_CORE_HW_IO_LOG_NAME,
+			"REG (hdlr = 0x%p, ptr = 0x%p, flgs = 0x%016llX, 0x%016llX, 0x%016llX, 0x%016llX)",
+		handler, err_flgs, err_flgs[0], err_flgs[1], err_flgs[2], err_flgs[3]);
+
+	return link->core_lgrp->core_ldev->ops.pml_intr_register(
+		link->core_lgrp->core_ldev->accessors.intr,
+		link->core_lgrp->num, "link", err_flgs, handler, data);
+}
+
+static inline int sl_core_hw_intr_unregister(struct sl_core_link *link,
+					     u64 *err_flgs, sl_intr_handler_t handler)
+{
+	sl_core_log_dbg(link, SL_CORE_HW_IO_LOG_NAME,
+			"UNREG (hdlr = 0x%p, ptr = 0x%p, flgs = 0x%016llX, 0x%016llX, 0x%016llX, 0x%016llX)",
+		handler, err_flgs, err_flgs[0], err_flgs[1], err_flgs[2], err_flgs[3]);
+
+	return link->core_lgrp->core_ldev->ops.pml_intr_unregister(
+		link->core_lgrp->core_ldev->accessors.intr,
+		link->core_lgrp->num, err_flgs, handler);
+}
+
+static inline int sl_core_hw_intr_enable(struct sl_core_link *core_link,
+					 u64 *err_flgs, sl_intr_handler_t handler)
+{
+	int  rtn;
+	bool is_canceled_or_timed_out;
+
+	sl_core_log_dbg(core_link, SL_CORE_HW_IO_LOG_NAME,
+			"EN (hdlr = 0x%p, ptr = 0x%p, flgs = 0x%016llX, 0x%016llX, 0x%016llX, 0x%016llX)",
+		handler, err_flgs, err_flgs[0], err_flgs[1], err_flgs[2], err_flgs[3]);
+
+	rtn = sl_core_link_is_canceled_or_timed_out(core_link, &is_canceled_or_timed_out);
+	if (rtn) {
+		sl_core_log_err_trace(core_link, SL_CORE_HW_IO_LOG_NAME,
+				      "intr enable - is_canceled_or_timed_out failed [%d]",
+				      rtn);
+		return rtn;
+	}
+
+	if (is_canceled_or_timed_out) {
+		sl_core_log_dbg(core_link, SL_CORE_HW_IO_LOG_NAME, "canceled");
+		return 0;
+	}
+
+	return core_link->core_lgrp->core_ldev->ops.pml_intr_enable(
+		core_link->core_lgrp->core_ldev->accessors.intr,
+		core_link->core_lgrp->num, err_flgs, handler);
+}
+
+static inline int sl_core_hw_intr_disable(struct sl_core_link *link,
+					  u64 *err_flgs, sl_intr_handler_t handler)
+{
+	sl_core_log_dbg(link, SL_CORE_HW_IO_LOG_NAME,
+			"DIS (hdlr = 0x%p, ptr = 0x%p, flgs = 0x%016llX, 0x%016llX, 0x%016llX, 0x%016llX)",
+		handler, err_flgs, err_flgs[0], err_flgs[1], err_flgs[2], err_flgs[3]);
+
+	return link->core_lgrp->core_ldev->ops.pml_intr_disable(
+		link->core_lgrp->core_ldev->accessors.intr,
+		link->core_lgrp->num, err_flgs, handler);
+}
+
+static inline int sl_core_hw_intr_llr_register(struct sl_core_llr *core_llr,
+					       u64 *err_flgs, sl_intr_handler_t handler, void *data)
+{
+	sl_core_log_dbg(core_llr, SL_CORE_HW_IO_LOG_NAME,
+			"REG (hdlr = 0x%p, ptr = 0x%p, flgs = 0x%016llX, 0x%016llX, 0x%016llX, 0x%016llX)",
+		handler, err_flgs, err_flgs[0], err_flgs[1], err_flgs[2], err_flgs[3]);
+
+	return core_llr->core_lgrp->core_ldev->ops.pml_intr_register(
+		core_llr->core_lgrp->core_ldev->accessors.intr,
+		core_llr->core_lgrp->num, "llr", err_flgs, handler, data);
+}
+
+static inline int sl_core_hw_intr_llr_unregister(struct sl_core_llr *core_llr,
+						 u64 *err_flgs, sl_intr_handler_t handler)
+{
+	sl_core_log_dbg(core_llr, SL_CORE_HW_IO_LOG_NAME,
+			"UNREG (hdlr = 0x%p, ptr = 0x%p, flgs = 0x%016llX, 0x%016llX, 0x%016llX, 0x%016llX)",
+		handler, err_flgs, err_flgs[0], err_flgs[1], err_flgs[2], err_flgs[3]);
+
+	return core_llr->core_lgrp->core_ldev->ops.pml_intr_unregister(
+		core_llr->core_lgrp->core_ldev->accessors.intr,
+		core_llr->core_lgrp->num, err_flgs, handler);
+}
+
+static inline int sl_core_hw_intr_llr_enable(struct sl_core_llr *core_llr,
+					     u64 *err_flgs, sl_intr_handler_t handler)
+{
+	sl_core_log_dbg(core_llr, SL_CORE_HW_IO_LOG_NAME,
+			"EN (hdlr = 0x%p, ptr = 0x%p, flgs = 0x%016llX, 0x%016llX, 0x%016llX, 0x%016llX)",
+		handler, err_flgs, err_flgs[0], err_flgs[1], err_flgs[2], err_flgs[3]);
+
+	if (sl_core_llr_should_stop(core_llr)) {
+		sl_core_log_dbg(core_llr, SL_CORE_HW_IO_LOG_NAME, "canceled");
+		return 0;
+	}
+
+	return core_llr->core_lgrp->core_ldev->ops.pml_intr_enable(
+		core_llr->core_lgrp->core_ldev->accessors.intr,
+		core_llr->core_lgrp->num, err_flgs, handler);
+}
+
+static inline int sl_core_hw_intr_llr_disable(struct sl_core_llr *core_llr,
+					      u64 *err_flgs, sl_intr_handler_t handler)
+{
+	sl_core_log_dbg(core_llr, SL_CORE_HW_IO_LOG_NAME,
+			"DIS (hdlr = 0x%p, ptr = 0x%p, flgs = 0x%016llX, 0x%016llX, 0x%016llX, 0x%016llX)",
+		handler, err_flgs, err_flgs[0], err_flgs[1], err_flgs[2], err_flgs[3]);
+
+	return core_llr->core_lgrp->core_ldev->ops.pml_intr_disable(
+		core_llr->core_lgrp->core_ldev->accessors.intr,
+		core_llr->core_lgrp->num, err_flgs, handler);
+}
+
+#endif /* _SL_CORE_HW_IO_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_link.h b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_link.h
new file mode 100644
index 000000000000..6ef4302ec6a5
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_link.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2022,2023,2024,2025,2026 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_HW_LINK_H_
+#define _SL_CORE_HW_LINK_H_
+
+struct work_struct;
+
+#include "sl_core_link.h"
+
+void sl_core_hw_link_up_callback(struct sl_core_link *core_link,
+	struct sl_core_link_up_info *core_link_up_info);
+void sl_core_hw_link_up_cmd(struct sl_core_link *link,
+	sl_core_link_up_callback_t callback, void *tag);
+void sl_core_hw_link_up_start_work(struct work_struct *work);
+void sl_core_hw_link_up_after_an_start(struct sl_core_link *core_link);
+void sl_core_hw_link_up_work(struct work_struct *work);
+void sl_core_hw_link_up_intr_work(struct work_struct *work);
+void sl_core_hw_link_up_check_work(struct work_struct *work);
+void sl_core_hw_link_up_fec_settle_work(struct work_struct *work);
+void sl_core_hw_link_up_fec_check_work(struct work_struct *work);
+void sl_core_hw_link_up_timeout_work(struct work_struct *work);
+void sl_core_hw_link_up_cancel_work(struct work_struct *work);
+void sl_core_hw_link_up_fail_work(struct work_struct *work);
+
+void sl_core_hw_link_down_work(struct work_struct *work);
+
+void sl_core_hw_link_high_ser_intr_work(struct work_struct *work);
+void sl_core_hw_link_llr_max_starvation_intr_work(struct work_struct *work);
+void sl_core_hw_link_llr_starved_intr_work(struct work_struct *work);
+void sl_core_hw_link_fault_intr_work(struct work_struct *work);
+void sl_core_hw_link_lane_degrade_intr_work(struct work_struct *work);
+void sl_core_hw_link_pml_rec_poll_work(struct work_struct *work);
+
+#endif /* _SL_CORE_HW_LINK_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_llr.h b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_llr.h
new file mode 100644
index 000000000000..e1abcb79b294
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_llr.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2022,2023,2024 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_HW_LLR_H_
+#define _SL_CORE_HW_LLR_H_
+
+#include "sl_core_llr.h"
+
+struct work_struct;
+struct sl_core_link;
+struct sl_core_llr;
+
+void sl_core_hw_llr_link_init(struct sl_core_link *core_link);
+
+void sl_core_hw_llr_setup_cmd(struct sl_core_llr *core_llr,
+			      sl_core_llr_setup_callback_t callback, void *tag, u32 flags);
+void sl_core_hw_llr_setup_work(struct work_struct *work);
+void sl_core_hw_llr_setup_loop_time_intr_work(struct work_struct *work);
+void sl_core_hw_llr_setup_unexp_loop_time_intr_work(struct work_struct *work);
+void sl_core_hw_llr_setup_timeout_work(struct work_struct *work);
+void sl_core_hw_llr_settingup_cancel_cmd(struct sl_core_llr *core_llr);
+
+void sl_core_hw_llr_start_cmd(struct sl_core_llr *core_llr,
+			      sl_core_llr_start_callback_t callback, void *tag, u32 flags);
+void sl_core_hw_llr_start_work(struct work_struct *work);
+void sl_core_hw_llr_start_init_complete_intr_work(struct work_struct *work);
+void sl_core_hw_llr_start_timeout_work(struct work_struct *work);
+void sl_core_hw_llr_starting_cancel_cmd(struct sl_core_llr *core_llr);
+
+void sl_core_hw_llr_stop(struct sl_core_llr *core_llr);
+void sl_core_hw_llr_setup_stop_cmd(struct sl_core_llr *core_llr);
+void sl_core_hw_llr_running_stop_cmd(struct sl_core_llr *core_llr);
+
+int  sl_core_hw_llr_stop_wait(struct sl_core_llr *core_llr);
+
+void sl_core_hw_llr_config_timeouts(struct sl_core_llr *core_llr);
+
+#endif /* _SL_CORE_HW_LLR_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_mac.h b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_mac.h
new file mode 100644
index 000000000000..a3ea784274f0
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_mac.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2022,2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_HW_MAC_H_
+#define _SL_CORE_HW_MAC_H_
+
+struct sl_core_mac;
+
+void sl_core_hw_mac_tx_config(struct sl_core_mac *core_mac);
+void sl_core_hw_mac_tx_config_subport(struct sl_core_mac *core_mac);
+void sl_core_hw_mac_tx_start(struct sl_core_mac *core_mac);
+void sl_core_hw_mac_tx_stop(struct sl_core_mac *core_mac);
+u64  sl_core_hw_mac_tx_state_get(struct sl_core_mac *core_mac);
+
+void sl_core_hw_mac_rx_config(struct sl_core_mac *core_mac);
+void sl_core_hw_mac_rx_start(struct sl_core_mac *core_mac);
+void sl_core_hw_mac_rx_stop(struct sl_core_mac *core_mac);
+u64  sl_core_hw_mac_rx_state_get(struct sl_core_mac *core_mac);
+
+#endif /* _SL_CORE_HW_MAC_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_pcs.h b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_pcs.h
new file mode 100644
index 000000000000..3867a2b51990
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_pcs.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2022-2026 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_HW_PCS_H_
+#define _SL_CORE_HW_PCS_H_
+
+struct sl_core_link;
+
+void sl_core_hw_pcs_config(struct sl_core_link *link);
+void sl_core_hw_pcs_config_swizzles(struct sl_core_link *core_link);
+
+void sl_core_hw_pcs_tx_start(struct sl_core_link *link);
+void sl_core_hw_pcs_rx_start(struct sl_core_link *link);
+void sl_core_hw_pcs_stop(struct sl_core_link *link);
+void sl_core_hw_pcs_toggle(struct sl_core_link *core_link);
+
+bool sl_core_hw_pcs_is_pml_rec_success(struct sl_core_link *core_link);
+
+bool sl_core_hw_pcs_is_ok(struct sl_core_link *link);
+
+int  sl_core_hw_pcs_enable_auto_lane_degrade(struct sl_core_link *core_link);
+
+void sl_core_hw_pcs_keep_all_lanes_active_set(struct sl_core_link *core_link, u64 value);
+
+#endif /* _SL_CORE_HW_PCS_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_pmi.h b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_pmi.h
new file mode 100644
index 000000000000..2031cc212088
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_pmi.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_HW_PMI_H_
+#define _SL_CORE_HW_PMI_H_
+
+#define PMI_DEV_ID_MASK  0x1F
+#define PMI_DEV_ID_SHIFT 27
+#define PMI_SEL_MASK     0x07
+#define PMI_SEL_SHIFT    24
+#define PMI_LANE_MASK    0xFF
+#define PMI_LANE_SHIFT   16
+#define PMI_ADDR_MASK    0xFFFF
+
+#define PMI_ADDR32(_dev_id, _sel, _lane, _addr)              \
+	(((_dev_id & PMI_DEV_ID_MASK) << PMI_DEV_ID_SHIFT) | \
+	 ((_sel & PMI_SEL_MASK) << PMI_SEL_SHIFT) | \
+	 ((_lane & PMI_LANE_MASK) << PMI_LANE_SHIFT) | \
+	 (_addr & PMI_ADDR_MASK))
+
+#define SL_CORE_HW_PMI_RD(_lgrp, _dev_id, _lane, _sel, _addr, _data) \
+	do {                                                               \
+		rtn = pmi_rd((_lgrp), (_dev_id), (_lane), (_sel), (_addr), (_data)); \
+		if (rtn)                                                       \
+			goto out;                                                   \
+	} while (0)
+
+#define SL_CORE_HW_PMI_WR(_lgrp, _dev_id, _lane, _sel, _addr, _data, _mask) \
+	do {                                                                    \
+		rtn = pmi_wr((_lgrp), (_dev_id), (_lane), (_sel), (_addr), (_data), (_mask)); \
+		if (rtn)                                                            \
+			goto out;                                                        \
+	} while (0)
+
+struct sl_core_lgrp;
+
+int pmi_rd(struct sl_core_lgrp *core_lgrp, u8 dev_id, u8 lane,
+	   u8 sel, u16 addr, u16 *data);
+
+int pmi_wr(struct sl_core_lgrp *core_lgrp, u8 dev_id, u8 lane,
+	   u8 sel, u16 addr, u16 data, u16 mask);
+
+#endif /* _SL_CORE_HW_PMI_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_reset.h b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_reset.h
new file mode 100644
index 000000000000..4d4bb8fd615f
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_reset.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2022,2023 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_HW_RESET_H_
+#define _SL_CORE_HW_RESET_H_
+
+struct sl_core_link;
+struct sl_core_lgrp;
+
+void sl_core_hw_reset_link(struct sl_core_link *core_link);
+void sl_core_hw_reset_lgrp(struct sl_core_lgrp *core_lgrp);
+
+#endif /* _SL_CORE_HW_RESET_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_sbus.h b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_sbus.h
new file mode 100644
index 000000000000..33d865eef9a7
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_sbus.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023,2024 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_HW_SBUS_H_
+#define _SL_CORE_HW_SBUS_H_
+
+#define SL_CORE_HW_SBUS_WR(_lgrp, _dev_addr, _reg, _data)             \
+	do {                                                          \
+		rtn = sbus_wr((_lgrp), (_dev_addr), (_reg), (_data)); \
+		if (rtn != 0)                                         \
+			goto out;                                     \
+	} while (0)
+
+#define SL_CORE_HW_SBUS_FIELD_WR(_lgrp, _dev_addr, _reg, _data, _lsb, _mask)                 \
+	do {                                                                                 \
+		rtn = sbus_field_wr((_lgrp), (_dev_addr), (_reg), (_lsb), (_mask), (_data)); \
+		if (rtn != 0)                                                                \
+			goto out;                                                            \
+	} while (0)
+
+#define SL_CORE_HW_SBUS_RD(_lgrp, _dev_addr, _reg, _data)             \
+	do {                                                          \
+		rtn = sbus_rd((_lgrp), (_dev_addr), (_reg), (_data)); \
+		if (rtn != 0)                                         \
+			goto out;                                     \
+	} while (0)
+
+#define SL_CORE_HW_SBUS_FIELD_RD(_lgrp, _dev_addr, _reg, _lsb, _mask, _data)                 \
+	do {                                                                                 \
+		rtn = sbus_field_rd((_lgrp), (_dev_addr), (_reg), (_lsb), (_mask), (_data)); \
+		if (rtn != 0)                                                                \
+			goto out;                                                            \
+	} while (0)
+
+#define SL_CORE_HW_SBUS_RST(_lgrp, _dev_addr)         \
+	do {                                          \
+		rtn = sbus_rst((_lgrp), (_dev_addr)); \
+		if (rtn != 0)                         \
+			goto out;                     \
+	} while (0)
+
+#define SBUS_BROADCAST_ADDR 0xFA
+
+struct sl_core_lgrp;
+
+int sbus_wr(struct sl_core_lgrp *core_lgrp, u8 dev_addr, u8 reg, u32 data);
+int sbus_field_wr(struct sl_core_lgrp *core_lgrp, u8 dev_addr, u8 reg, u8 lsb, u32 mask, u32 data);
+int sbus_rd(struct sl_core_lgrp *core_lgrp, u8 dev_addr, u8 reg, u32 *data);
+int sbus_field_rd(struct sl_core_lgrp *core_lgrp, u8 dev_addr, u8 reg, u8 lsb, u32 mask, u32 *data);
+int sbus_rst(struct sl_core_lgrp *core_lgrp, u8 dev_addr);
+
+#endif /* _SL_CORE_HW_SBUS_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_sbus_pmi.h b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_sbus_pmi.h
new file mode 100644
index 000000000000..54bc21be4e59
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_sbus_pmi.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_HW_SBUS_PMI_H_
+#define _SL_CORE_HW_SBUS_PMI_H_
+
+#define SL_CORE_HW_SBUS_PMI_RD(_lgrp, _dev_addr, _dev_id, _lane, _sel, _addr, _mask, _data)                     \
+	do {                                                                                                    \
+		rtn = sbus_pmi_rd((_lgrp), (_dev_addr), (_dev_id), (_lane), (_sel), (_addr), (_mask), (_data)); \
+		if (rtn != 0)                                                                                   \
+			goto out;                                                                               \
+	} while (0)
+
+#define SL_CORE_HW_SBUS_PMI_WR(_lgrp, _dev_addr, _dev_id, _lane, _sel, _addr, _data, _mask)                     \
+	do {                                                                                                    \
+		rtn = sbus_pmi_wr((_lgrp), (_dev_addr), (_dev_id), (_lane), (_sel), (_addr), (_data), (_mask)); \
+		if (rtn != 0)                                                                                   \
+			goto out;                                                                               \
+	} while (0)
+
+struct sl_core_lgrp;
+
+int sbus_pmi_rd(struct sl_core_lgrp *core_lgrp, u8 dev_addr, u8 dev_id, u8 lane,
+		u8 sel, u16 addr, u16 mask, u16 *data);
+int sbus_pmi_wr(struct sl_core_lgrp *core_lgrp, u8 dev_addr, u8 dev_id, u8 lane,
+		u8 sel, u16 addr, u16 data, u16 mask);
+
+#endif /* _SL_CORE_HW_SBUS_PMI_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes.h b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes.h
new file mode 100644
index 000000000000..242ba6451913
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2022,2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_HW_SERDES_H_
+#define _SL_CORE_HW_SERDES_H_
+
+struct sl_core_link;
+struct sl_core_lgrp;
+
+#define SL_CORE_HW_SERDES_TX_PLL_BW_DEFAULT      0x30
+#define SL_CORE_HW_SERDES_TX_PLL_BW_100Glane_AEC 0x24
+#define SL_CORE_HW_SERDES_TX_PLL_BW_100Glane_AOC 0x00
+
+#define LGRP_TO_SERDES(_lgrp_num) ((_lgrp_num) >> 1)
+
+int  sl_core_hw_serdes_init(struct sl_core_lgrp *core_lgrp);
+int  sl_core_hw_serdes_swizzles(struct sl_core_lgrp *core_lgrp);
+int  sl_core_hw_serdes_hw_info_get(struct sl_core_lgrp *core_lgrp);
+int  sl_core_hw_serdes_fw_info_get(struct sl_core_lgrp *core_lgrp);
+void sl_core_hw_serdes_state_set(struct sl_core_link *core_link, u8 state);
+u8   sl_core_hw_serdes_state_get(struct sl_core_link *core_link);
+
+#endif /* _SL_CORE_HW_SERDES_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes_addrs.h b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes_addrs.h
new file mode 100644
index 000000000000..0f38301a8712
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes_addrs.h
@@ -0,0 +1,87 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_HW_SERDES_ADDRS_H_
+#define _SL_CORE_HW_SERDES_ADDRS_H_
+
+enum {
+	SERDES_DIG_COM_B_LANE_ADDR_0,
+	SERDES_MICRO_B_COM_RMI_MICRO_SDK_STATUS0,
+	SERDES_DIG_COM_REVID0,
+	SERDES_DIG_COM_REVID1,
+	SERDES_DIG_COM_REVID2,
+	SERDES_HW_VERSION,
+	SERDES_MICRO_E_COM_MICRO_CORE_CLOCK_CONTROL0,
+	SERDES_MICRO_E_COM_MICRO_CORE_RESET_CONTROL0,
+	SERDES_MICRO_C_COM_RAM_CONTROL0,
+	SERDES_MICRO_A_COM_CLOCK_CONTROL0,
+	SERDES_MICRO_A_COM_RESET_CONTROL0,
+	SERDES_MICRO_A_COM_AHB_CONTROL0,
+	SERDES_MICRO_A_COM_AHB_STATUS0,
+	SERDES_MICRO_B_COM_RMI_RAM_CR_CRCCONTROL0,
+	SERDES_MICRO_B_COM_RMI_RAM_CR_CRCSTATUS0,
+	SERDES_MICRO_A_COM_PRAMIF_CONTROL0,
+	SERDES_MICRO_A_COM_PRAMIF_AHB_WRADDR_LSW,
+	SERDES_MICRO_A_COM_PRAMIF_AHB_WRADDR_MSW,
+	SERDES_MICRO_D_COM_RMI_MICRO_CONTROL0,
+	SERDES_MICRO_C_COM_RAM_CONTROL2,
+	SERDES_COMMON_CLOCK,
+	SERDES_MDIO_MMDSEL_AER_COM_MDIO_BRCST_PORT_ADDR,
+	SERDES_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL,
+	SERDES_CORE_PLL_COM_TOP_USER_CONTROL,
+	SERDES_DIG_COM_RESET_CONTROL_PMD,
+	SERDES_CORE_PLL_COM_RESET_CONTROL_PLL_DP,
+	SERDES_PLL_RESET2,
+	SERDES_AMS_PLL_COM_PLL_CONTROL_10,
+	SERDES_AMS_PLL_COM_PLL_CONTROL_11,
+	SERDES_AMS_PLL_COM_PLL_CONTROL_12,
+	SERDES_PLL_CAL_COM_STS_0,
+	SERDES_TXCOM_CKRST_CTRL_TXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL,
+	SERDES_TXCOM_CKRST_CTRL_TXCOM_LN_S_RSTB_CONTROL,
+	SERDES_RXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL,
+	SERDES_RXCOM_CKRST_CTRL_RXCOM_LN_S_RSTB_CONTROL,
+	SERDES_PLL_COM_PLL_CONTROL_2,
+	SERDES_PLL_COM_PLL_CONTROL_1,
+	SERDES_PLL_COM_PLL_CONTROL_4,
+	SERDES_PLL_POWER_DOWN,
+	SERDES_PLL_COM_B_PLL_CTRL_0,
+	SERDES_PLL_COM_B_PLL_CTRL_2,
+	SERDES_PLL_COM_B_PLL_CTRL_1,
+	SERDES_PLL_CONTROL,
+	SERDES_PLL_COM_PLL_CONTROL_3,
+	SERDES_PLL_COM_B_PLL_CTRL_3,
+	SERDES_PLL_SELECT,
+	SERDES_PLL_FW_API_DATA0,
+	SERDES_TX_FED_TXFIR_TAP_CONTROL0,
+	SERDES_TX_FED_TXFIR_TAP_CONTROL1,
+	SERDES_TX_FED_TXFIR_TAP_CONTROL2,
+	SERDES_TX_FED_TXFIR_TAP_CONTROL3,
+	SERDES_TX_FED_TXFIR_TAP_CONTROL4,
+	SERDES_TX_FED_TXFIR_TAP_CONTROL5,
+	SERDES_CDR_CONTROL_0,
+	SERDES_FW_API_DATA0,
+	SERDES_AMS_TX_TXCONTROL_3,
+	SERDES_TX_PI_TXPICONTROL_5,
+	SERDES_TX_PI_TXPICONTROL_0,
+	SERDES_RX_MISC_CONFIG,
+	SERDES_TLB_TX_TLB_TX_PAM4_CONFIG_0,
+	SERDES_RX_CKRST_CTRL_RX_CLOCK_N_RESET_DEBUG_CONTROL,
+	SERDES_RX_CKRST_CTRL_RX_LANE_CLK_RESET_N_POWERDOWN_CONTROL,
+	SERDES_LINKTRN_IEEE_TX_LINKTRNIT_BASE_R_PMD_CONTROL,
+	SERDES_LINKTRN_IEEE_TX_LINKTRNIT_BASE_R_PMD_STATUS,
+	SERDES_TLB_RX_DIG_LPBK_CONFIG,
+	SERDES_TX_CKRST_CTRL_TX_CLOCK_N_RESET_DEBUG_CONTROL,
+	SERDES_TX_CKRST_CTRL_TX_LANE_CLK_RESET_N_POWERDOWN_CONTROL,
+	SERDES_TX_FED_TXFIR_MISC_CONTROL0,
+	SERDES_TLB_TX_TXMISC_CONFIG,
+	SERDES_TLB_TX_RMT_LPBK_CONFIG,
+	SERDES_TLB_TX_PRBS_GEN_CONFIG,
+	SERDES_TLB_TX_PATT_GEN_CONFIG,
+	SERDES_TLB_RX_PRBS_CHK_CONFIG,
+	SERDES_MICRO_A_COM_AHB_RDADDR_MSW,
+	SERDES_MICRO_A_COM_AHB_RDADDR_LSW,
+	SERDES_MICRO_A_COM_AHB_RDDATA_LSW,
+	SERDES_DIG_COM_TOP_USER_CONTROL_0,
+};
+
+#endif /* _SL_CORE_HW_SERDES_ADDRS_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes_condor.h b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes_condor.h
new file mode 100644
index 000000000000..eede082a1a8c
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes_condor.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_HW_SERDES_CONDOR_H_
+#define _SL_CORE_HW_SERDES_CONDOR_H_
+
+#include "hw/sl_core_hw_serdes_addrs.h"
+
+static u16 serdes_addrs_condor[] = {
+};
+
+#endif /* _SL_CORE_HW_SERDES_CONDOR_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes_core.h b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes_core.h
new file mode 100644
index 000000000000..05cea9e36a8a
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes_core.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_HW_SERDES_CORE_H_
+#define _SL_CORE_HW_SERDES_CORE_H_
+
+struct sl_core_lgrp;
+
+int  sl_core_hw_serdes_core_init(struct sl_core_lgrp *core_lgrp);
+int  sl_core_hw_serdes_core_pll(struct sl_core_lgrp *core_lgrp, u16 clocking, u16 tx_pll_bw);
+
+#endif /* _SL_CORE_HW_SERDES_CORE_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes_fw.h b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes_fw.h
new file mode 100644
index 000000000000..f116c02161d5
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes_fw.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_HW_SERDES_FW_H_
+#define _SL_CORE_HW_SERDES_FW_H_
+
+#include "sl_core_hw_serdes_firmware.h"
+
+struct sl_core_lgrp;
+
+int  sl_core_hw_serdes_fw_setup(struct sl_core_lgrp *core_lgrp);
+int  sl_core_hw_serdes_fw_write(struct sl_core_lgrp *core_lgrp);
+int  sl_core_hw_serdes_fw_finish(struct sl_core_lgrp *core_lgrp);
+
+#endif /* _SL_CORE_HW_SERDES_FW_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes_lane.h b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes_lane.h
new file mode 100644
index 000000000000..1c081f0f057a
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes_lane.h
@@ -0,0 +1,125 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2024-2026 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_HW_SERDES_LANE_H_
+#define _SL_CORE_HW_SERDES_LANE_H_
+
+#define SL_CORE_HW_SERDES_LANE_STATE_INVALID  0
+#define SL_CORE_HW_SERDES_LANE_STATE_DOWN     1
+#define SL_CORE_HW_SERDES_LANE_STATE_SETUP    2
+#define SL_CORE_HW_SERDES_LANE_STATE_CONFIG   3
+#define SL_CORE_HW_SERDES_LANE_STATE_START    4
+#define SL_CORE_HW_SERDES_LANE_STATE_CHECK    5
+#define SL_CORE_HW_SERDES_LANE_STATE_STOP     6
+#define SL_CORE_HW_SERDES_LANE_STATE_UP       7
+#define SL_CORE_HW_SERDES_LANE_STATE_DEGRADED 8
+
+#define SL_CORE_HW_SERDES_ENCODING_NRZ     2
+#define SL_CORE_HW_SERDES_ENCODING_PAM4_NR 4
+#define SL_CORE_HW_SERDES_ENCODING_PAM4_ER 8
+
+#define SL_CORE_HW_SERDES_CLOCKING_82P5 BIT(0)
+#define SL_CORE_HW_SERDES_CLOCKING_85   BIT(1)
+
+#define SL_CORE_HW_SERDES_OSR_OSX1    0
+#define SL_CORE_HW_SERDES_OSR_OSX2    1
+#define SL_CORE_HW_SERDES_OSR_OSX4    2
+#define SL_CORE_HW_SERDES_OSR_OSX42P5 33
+
+#define SL_CORE_HW_SERDES_WIDTH_40  0
+#define SL_CORE_HW_SERDES_WIDTH_80  1
+#define SL_CORE_HW_SERDES_WIDTH_160 2
+
+#define SL_CORE_HW_SERDES_SCRAMBLE_DIS_SET    1
+#define SL_CORE_HW_SERDES_SCRAMBLE_DIS_NOTSET 0
+
+#define SL_CORE_HW_SERDES_DFE_DISABLE 0
+#define SL_CORE_HW_SERDES_DFE_ENABLE  1
+
+#define SL_CORE_HW_SERDES_AUTONEG true
+#define SL_CORE_HW_SERDES_ATSPEED false
+
+/* NOTES
+ *   asic_lane_num   = lane indicated on the asic (0-3)
+ *   serdes_lane_num = lane indicated on the serdes (0-8)
+ */
+
+struct sl_core_link;
+struct sl_core_lgrp;
+struct sl_core_serdes_settings;
+struct sl_media_serdes_settings;
+
+#define SL_CORE_HW_SERDES_LANE_ADDR(_addr, _lane_num, _lgrp)                                                 \
+	((_lgrp)->core_ldev->serdes.fw_info[LGRP_TO_SERDES((_lgrp)->num)].lane_var_ram_base +                \
+	(_addr) +                                                                                            \
+	(((_lane_num) % (_lgrp)->core_ldev->serdes.fw_info[LGRP_TO_SERDES((_lgrp)->num)].lane_count) *       \
+		(_lgrp)->core_ldev->serdes.fw_info[LGRP_TO_SERDES((_lgrp)->num)].lane_var_ram_size) +        \
+	((_lgrp)->core_ldev->serdes.fw_info[LGRP_TO_SERDES((_lgrp)->num)].grp_ram_size * ((_lane_num) >> 1)))
+
+#define SL_CORE_HW_SERDES_LOOPBACK_SERDES_SETTINGS_SET(_core_link)        \
+	do {                                                              \
+		(_core_link)->serdes.media_serdes_settings.pre3   = 0;    \
+		(_core_link)->serdes.media_serdes_settings.pre2   = 0;    \
+		(_core_link)->serdes.media_serdes_settings.pre1   = 0;    \
+		(_core_link)->serdes.media_serdes_settings.cursor = 168;  \
+		(_core_link)->serdes.media_serdes_settings.post1  = 0;    \
+		(_core_link)->serdes.media_serdes_settings.post2  = 0;    \
+		(_core_link)->serdes.media_serdes_settings.media  = 1;    \
+	} while (0)
+
+u8   sl_core_hw_serdes_rx_asic_lane_num_get(struct sl_core_link *core_link, u8 serdes_lane_num);
+u8   sl_core_hw_serdes_tx_asic_lane_num_get(struct sl_core_link *core_link, u8 serdes_lane_num);
+
+int  sl_core_hw_serdes_lane_pre1_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, s16 *pre1);
+int  sl_core_hw_serdes_lane_pre2_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, s16 *pre2);
+int  sl_core_hw_serdes_lane_pre3_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, s16 *pre3);
+int  sl_core_hw_serdes_lane_cursor_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, s16 *cursor);
+int  sl_core_hw_serdes_lane_post1_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, s16 *post1);
+int  sl_core_hw_serdes_lane_post2_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, s16 *post2);
+
+u16  sl_core_hw_serdes_mode(struct sl_core_lgrp *core_lgrp,
+			    struct sl_core_serdes_settings *settings);
+int  sl_core_hw_serdes_lane_osr_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, u8 *osr);
+int  sl_core_hw_serdes_lane_encoding_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, u8 *encoding);
+int  sl_core_hw_serdes_lane_width_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, u8 *width);
+u16  sl_core_hw_serdes_config(struct sl_core_lgrp *core_lgrp,
+			      struct sl_core_serdes_settings *core_serdes_settings,
+			      struct sl_media_serdes_settings *media_serdes_settings);
+int  sl_core_hw_serdes_lane_dfe_get(struct sl_core_lgrp *core_lgrp, u8 lane_num, u8 *dfe);
+int  sl_core_hw_serdes_lane_scramble_dis_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, u8 *scramble_dis);
+
+int  sl_core_hw_serdes_lanes_up(struct sl_core_link *core_link, bool is_autoneg);
+int  sl_core_hw_serdes_lanes_up_prbs(struct sl_core_link *core_link, u8 tx_degrade_map, u8 rx_degrade_map);
+int  sl_core_hw_serdes_lane_up_tx_setup(struct sl_core_link *core_link, u8 serdes_lane_num, bool is_autoneg);
+int  sl_core_hw_serdes_lane_up_tx_config(struct sl_core_link *core_link, u8 serdes_lane_num);
+int  sl_core_hw_serdes_lane_up_tx_start(struct sl_core_link *core_link, u8 serdes_lane_num);
+int  sl_core_hw_serdes_lane_up_rx_setup(struct sl_core_link *core_link, u8 serdes_lane_num);
+int  sl_core_hw_serdes_lane_up_rx_config(struct sl_core_link *core_link, u8 serdes_lane_num);
+int  sl_core_hw_serdes_lane_up_rx_start(struct sl_core_link *core_link, u8 serdes_lane_num);
+
+void sl_core_hw_serdes_lanes_down(struct sl_core_link *core_link);
+void sl_core_hw_serdes_lane_down_rx_stop(struct sl_core_link *core_link, u8 serdes_lane_num);
+void sl_core_hw_serdes_lane_down_tx_stop(struct sl_core_link *core_link, u8 serdes_lane_num);
+
+int  sl_core_hw_serdes_eye_upper_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, u8 *eye_upper);
+int  sl_core_hw_serdes_eye_lower_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, u8 *eye_lower);
+
+void sl_core_hw_serdes_tx_lane_state_set(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, u32 state);
+int  sl_core_hw_serdes_tx_lane_state_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, u32 *state);
+void sl_core_hw_serdes_rx_lane_state_set(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, u32 state);
+int  sl_core_hw_serdes_rx_lane_state_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, u32 *state);
+
+void sl_core_hw_serdes_degraded_lanes_state_set(struct sl_core_link *core_link, u8 tx_degrade_map, u8 rx_degrade_map);
+
+int sl_core_hw_serdes_tx_lane_is_lol(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, bool *is_tx_lol);
+int sl_core_hw_serdes_rx_lane_is_lol(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, bool *is_rx_lol);
+int sl_core_hw_serdes_tx_lane_is_los(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, bool *is_tx_los);
+int sl_core_hw_serdes_rx_lane_is_los(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, bool *is_rx_los);
+
+int sl_core_hw_serdes_lane_tx_prbs_config(struct sl_core_link *core_link, u8 serdes_lane_num);
+int sl_core_hw_serdes_lane_tx_prbs_enable(struct sl_core_link *core_link, u8 serdes_lane_num);
+int sl_core_hw_serdes_lane_tx_prbs_shrd_patt_gen_disable(struct sl_core_link *core_link, u8 serdes_lane_num);
+int sl_core_hw_serdes_lane_tx_prbs_remote_loopback_disable(struct sl_core_link *core_link, u8 serdes_lane_num);
+int sl_core_hw_serdes_lane_tx_prbs_checker_enable(struct sl_core_link *core_link, u8 serdes_lane_num);
+
+#endif /* _SL_CORE_HW_SERDES_LANE_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes_link.h b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes_link.h
new file mode 100644
index 000000000000..fd0783b81ba3
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes_link.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_HW_SERDES_LINK_H_
+#define _SL_CORE_HW_SERDES_LINK_H_
+
+struct sl_core_link;
+
+int  sl_core_hw_serdes_link_up_an(struct sl_core_link *core_link);
+int  sl_core_hw_serdes_link_up(struct sl_core_link *core_link);
+void sl_core_hw_serdes_link_down(struct sl_core_link *core_link);
+
+#endif /* _SL_CORE_HW_SERDES_LINK_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes_osprey.h b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes_osprey.h
new file mode 100644
index 000000000000..b5f6725204d0
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes_osprey.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_HW_SERDES_OSPREY_H_
+#define _SL_CORE_HW_SERDES_OSPREY_H_
+
+#include "hw/sl_core_hw_serdes_addrs.h"
+
+static u16 serdes_addrs_osprey[] = {
+	[SERDES_DIG_COM_B_LANE_ADDR_0]                                         = 0xD190,
+	[SERDES_MICRO_B_COM_RMI_MICRO_SDK_STATUS0]                             = 0xD21A,
+	[SERDES_DIG_COM_REVID0]                                                = 0xD100,
+	[SERDES_DIG_COM_REVID1]                                                = 0xD10A,
+	[SERDES_DIG_COM_REVID2]                                                = 0xD10E,
+	[SERDES_HW_VERSION]                                                    = 0xD0D8,
+	[SERDES_MICRO_E_COM_MICRO_CORE_CLOCK_CONTROL0]                         = 0xD240,
+	[SERDES_MICRO_E_COM_MICRO_CORE_RESET_CONTROL0]                         = 0xD241,
+	[SERDES_MICRO_C_COM_RAM_CONTROL0]                                      = 0xD227,
+	[SERDES_MICRO_A_COM_CLOCK_CONTROL0]                                    = 0xD200,
+	[SERDES_MICRO_A_COM_RESET_CONTROL0]                                    = 0xD201,
+	[SERDES_MICRO_A_COM_AHB_CONTROL0]                                      = 0xD202,
+	[SERDES_MICRO_A_COM_AHB_STATUS0]                                       = 0xD203,
+	[SERDES_MICRO_B_COM_RMI_RAM_CR_CRCCONTROL0]                            = 0xD217,
+	[SERDES_MICRO_B_COM_RMI_RAM_CR_CRCSTATUS0]                             = 0xD218,
+	[SERDES_MICRO_A_COM_PRAMIF_CONTROL0]                                   = 0xD20C,
+	[SERDES_MICRO_A_COM_PRAMIF_AHB_WRADDR_LSW]                             = 0xD20D,
+	[SERDES_MICRO_A_COM_PRAMIF_AHB_WRADDR_MSW]                             = 0xD20E,
+	[SERDES_MICRO_D_COM_RMI_MICRO_CONTROL0]                                = 0xD23E,
+	[SERDES_MICRO_C_COM_RAM_CONTROL2]                                      = 0xD22E,
+	[SERDES_COMMON_CLOCK]                                                  = 0xD19D,
+	[SERDES_MDIO_MMDSEL_AER_COM_MDIO_BRCST_PORT_ADDR]                      = 0xFFDC,
+	[SERDES_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL] = 0xD0B1,
+	[SERDES_CORE_PLL_COM_TOP_USER_CONTROL]                                 = 0xD184,
+	[SERDES_DIG_COM_RESET_CONTROL_PMD]                                     = 0xD101,
+	[SERDES_CORE_PLL_COM_RESET_CONTROL_PLL_DP]                             = 0xD182,
+	[SERDES_PLL_RESET2]                                                    = 0xD119,
+	[SERDES_AMS_PLL_COM_PLL_CONTROL_10]                                    = 0xD11A,
+	[SERDES_AMS_PLL_COM_PLL_CONTROL_11]                                    = 0xD11B,
+	[SERDES_AMS_PLL_COM_PLL_CONTROL_12]                                    = 0xD11C,
+	[SERDES_PLL_CAL_COM_STS_0]                                             = 0xD148,
+	[SERDES_TXCOM_CKRST_CTRL_TXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL]     = 0xD1D1,
+	[SERDES_TXCOM_CKRST_CTRL_TXCOM_LN_S_RSTB_CONTROL]                      = 0xD1DE,
+	[SERDES_RXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL]                      = 0xD1C1,
+	[SERDES_RXCOM_CKRST_CTRL_RXCOM_LN_S_RSTB_CONTROL]                      = 0xD1CE,
+	[SERDES_PLL_COM_PLL_CONTROL_2]                                         = 0xD112,
+	[SERDES_PLL_COM_PLL_CONTROL_1]                                         = 0xD111,
+	[SERDES_PLL_COM_PLL_CONTROL_4]                                         = 0xD114,
+	[SERDES_PLL_POWER_DOWN]                                                = 0xD327,
+	[SERDES_PLL_COM_B_PLL_CTRL_0]                                          = 0xD320,
+	[SERDES_PLL_COM_B_PLL_CTRL_2]                                          = 0xD322,
+	[SERDES_PLL_COM_B_PLL_CTRL_1]                                          = 0xD321,
+	[SERDES_PLL_CONTROL]                                                   = 0xD110,
+	[SERDES_PLL_COM_PLL_CONTROL_3]                                         = 0xD113,
+	[SERDES_PLL_COM_B_PLL_CTRL_3]                                          = 0xD323,
+	[SERDES_PLL_SELECT]                                                    = 0xD11D,
+	[SERDES_PLL_FW_API_DATA0]                                              = 0xD18D,
+	[SERDES_TX_FED_TXFIR_TAP_CONTROL0]                                     = 0xD133,
+	[SERDES_TX_FED_TXFIR_TAP_CONTROL1]                                     = 0xD134,
+	[SERDES_TX_FED_TXFIR_TAP_CONTROL2]                                     = 0xD135,
+	[SERDES_TX_FED_TXFIR_TAP_CONTROL3]                                     = 0xD136,
+	[SERDES_TX_FED_TXFIR_TAP_CONTROL4]                                     = 0xD137,
+	[SERDES_TX_FED_TXFIR_TAP_CONTROL5]                                     = 0xD138,
+	[SERDES_CDR_CONTROL_0]                                                 = 0xD590,
+	[SERDES_FW_API_DATA0]                                                  = 0xD1AD,
+	[SERDES_AMS_TX_TXCONTROL_3]                                            = 0xD0D3,
+	[SERDES_TX_PI_TXPICONTROL_5]                                           = 0xD0A5,
+	[SERDES_TX_PI_TXPICONTROL_0]                                           = 0xD0A0,
+	[SERDES_RX_MISC_CONFIG]                                                = 0xD163,
+	[SERDES_TLB_TX_TLB_TX_PAM4_CONFIG_0]                                   = 0xD175,
+	[SERDES_RX_CKRST_CTRL_RX_CLOCK_N_RESET_DEBUG_CONTROL]                  = 0xD1A7,
+	[SERDES_RX_CKRST_CTRL_RX_LANE_CLK_RESET_N_POWERDOWN_CONTROL]           = 0xD1A1,
+	[SERDES_LINKTRN_IEEE_TX_LINKTRNIT_BASE_R_PMD_CONTROL]                  = 0x0096,
+	[SERDES_LINKTRN_IEEE_TX_LINKTRNIT_BASE_R_PMD_STATUS]                   = 0x0097,
+	[SERDES_TLB_RX_DIG_LPBK_CONFIG]                                        = 0xD162,
+	[SERDES_TX_CKRST_CTRL_TX_CLOCK_N_RESET_DEBUG_CONTROL]                  = 0xD1B7,
+	[SERDES_TX_CKRST_CTRL_TX_LANE_CLK_RESET_N_POWERDOWN_CONTROL]           = 0xD1B1,
+	[SERDES_TX_FED_TXFIR_MISC_CONTROL0]                                    = 0xD131,
+	[SERDES_TLB_TX_TXMISC_CONFIG]                                          = 0xD173,
+	[SERDES_TLB_TX_RMT_LPBK_CONFIG]                                        = 0xD172,
+	[SERDES_TLB_TX_PRBS_GEN_CONFIG]                                        = 0xD171,
+	[SERDES_TLB_TX_PATT_GEN_CONFIG]                                        = 0xD170,
+	[SERDES_TLB_RX_PRBS_CHK_CONFIG]                                        = 0xD161,
+	[SERDES_MICRO_A_COM_AHB_RDADDR_MSW]                                    = 0xD209,
+	[SERDES_MICRO_A_COM_AHB_RDADDR_LSW]                                    = 0xD208,
+	[SERDES_MICRO_A_COM_AHB_RDDATA_LSW]                                    = 0xD20A,
+	[SERDES_DIG_COM_TOP_USER_CONTROL_0]                                    = 0xD104,
+};
+
+#endif /* _SL_CORE_HW_SERDES_OSPREY_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_settings.h b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_settings.h
new file mode 100644
index 000000000000..07b0b5b8eab0
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_settings.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2022,2023,2024,2026 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_HW_SETTINGS_H_
+#define _SL_CORE_HW_SETTINGS_H_
+
+#define SL_CORE_HW_RS_MODE_OFF                           0x0
+#define SL_CORE_HW_RS_MODE_CORRECT                       0x5
+
+#define SL_CORE_HW_PCS_MODE_BS_200G                      0x0
+#define SL_CORE_HW_PCS_MODE_BJ_100G                      0x1
+#define SL_CORE_HW_PCS_MODE_CD_100G                      0x2
+#define SL_CORE_HW_PCS_MODE_CD_50G                       0x3
+#define SL_CORE_HW_PCS_MODE_CK_400G                      0x4
+#define SL_CORE_HW_PCS_MODE_CK_200G                      0x5
+#define SL_CORE_HW_PCS_MODE_CK_100G                      0x6
+
+#define SL_CORE_HW_IFG_ADJ_200G                          0x0
+#define SL_CORE_HW_IFG_ADJ_100G                          0x1
+#define SL_CORE_HW_IFG_ADJ_50G                           0x2
+#define SL_CORE_HW_IFG_ADJ_NONE                          0x3
+#define SL_CORE_HW_IFG_ADJ_400G                          0x4
+
+#define SL_CORE_HW_ACTIVE_LANES_BS_200G                  0xF
+#define SL_CORE_HW_ACTIVE_LANES_BJ_100G                  0xF
+#define SL_CORE_HW_ACTIVE_LANES_CD_100G(_link_num)       (0x3 << ((_link_num) * 2))
+#define SL_CORE_HW_ACTIVE_LANES_CD_50G(_link_num)        (0x1 << (_link_num))
+#define SL_CORE_HW_ACTIVE_LANES_CK_400G                  0xF
+#define SL_CORE_HW_ACTIVE_LANES_CK_200G(_link_num)       (0x3 << ((_link_num) * 2))
+#define SL_CORE_HW_ACTIVE_LANES_CK_100G(_link_num)       (0x1 << (_link_num))
+
+#define SL_CORE_HW_AM_LOCK_LANES_BS_200G                 0xFF
+#define SL_CORE_HW_AM_LOCK_LANES_BJ_100G                 0xF
+#define SL_CORE_HW_AM_LOCK_LANES_CD_100G(_link_num)      (0xF << ((_link_num) * 4))
+#define SL_CORE_HW_AM_LOCK_LANES_CD_50G(_link_num)       (0x3 << ((_link_num) * 2))
+#define SL_CORE_HW_AM_LOCK_LANES_CK_400G                 0xFFFF
+#define SL_CORE_HW_AM_LOCK_LANES_CK_200G(_link_num)      (0xFF << ((_link_num) * 8))
+#define SL_CORE_HW_AM_LOCK_LANES_CK_100G(_link_num)      (0xF << ((_link_num) * 4))
+
+#endif /* _SL_CORE_HW_SETTINGS_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_uc_ram.h b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_uc_ram.h
new file mode 100644
index 000000000000..b10b5227d38b
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_uc_ram.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2024,2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_HW_UC_RAM_H_
+#define _SL_CORE_HW_UC_RAM_H_
+
+#define SL_CORE_HW_UC_RAM_RD8(_lgrp, _dev_addr, _dev_id, _lane, _addr, _data)                            \
+	do {                                                                                             \
+		rtn = sl_core_hw_uc_ram_rd8((_lgrp), (_dev_addr), (_dev_id), (_lane), (_addr), (_data)); \
+		if (rtn != 0)                                                                            \
+			goto out;                                                                        \
+	} while (0)
+
+#define SL_CORE_HW_UC_RAM_RD_BLK(_lgrp, _dev_addr, _dev_id, _addr, _size, _buff)                            \
+	do {                                                                                                \
+		rtn = sl_core_hw_uc_ram_rd_blk((_lgrp), (_dev_addr), (_dev_id), (_addr), (_size), (_buff)); \
+		if (rtn != 0)                                                                               \
+			goto out;                                                                           \
+	} while (0)
+
+struct sl_core_lgrp;
+
+int sl_core_hw_uc_ram_rd8(struct sl_core_lgrp *core_lgrp, u8 dev_addr,
+			  u8 dev_id, u8 lane_num, u32 addr, u8 *data);
+int sl_core_hw_uc_ram_rd_blk(struct sl_core_lgrp *core_lgrp, u8 dev_addr,
+			     u8 dev_id, u32 start_addr, u8 rd_size, u8 *rd_buff);
+
+#endif /* _SL_CORE_HW_UC_RAM_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/ucode/octet.h b/drivers/net/ethernet/hpe/sl/core/hw/ucode/octet.h
new file mode 100644
index 000000000000..77f857a9abc4
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/ucode/octet.h
@@ -0,0 +1,9605 @@
+#define OSPREY7_V2L8P1_UCODE_IMAGE_VERSION "D003_08"  /* matches the version number from microcode */
+#define OSPREY7_V2L8P1_UCODE_IMAGE_SIZE    153568
+#define OSPREY7_V2L8P1_UCODE_STACK_SIZE    0x13F2
+#define OSPREY7_V2L8P1_UCODE_IMAGE_CRC     0x39AA
+
+unsigned char osprey7_v2l8p1_ucode_image[OSPREY7_V2L8P1_UCODE_IMAGE_SIZE] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd5, 0x83, 0xac, 0x40, 0x00, 0x00, 0x00, 0x00,
+ 0xd5, 0x60, 0x7c, 0x40, 0x00, 0x00, 0x00, 0x00, 0xd5, 0x1a, 0x7c, 0x40, 0x00, 0x00, 0x00, 0x00,
+ 0xd5, 0x55, 0x7c, 0x40, 0x00, 0x00, 0x00, 0x00, 0xd5, 0x3f, 0x7c, 0x40, 0x00, 0x00, 0x00, 0x00,
+ 0xd5, 0x72, 0xfc, 0x40, 0x00, 0x00, 0x00, 0x00, 0xd5, 0x05, 0xfc, 0x40, 0x00, 0x00, 0x00, 0x00,
+ 0xd5, 0x9d, 0xac, 0x40, 0x00, 0x00, 0x00, 0x00, 0xd5, 0x57, 0xfc, 0x40, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0xd5, 0x34, 0x02, 0x40, 0x00, 0x00, 0x00, 0x00, 0xd5, 0x7e, 0x02, 0x40, 0x00, 0x00, 0x00, 0x00,
+ 0xd5, 0x0b, 0x02, 0x40, 0x00, 0x00, 0x00, 0x00, 0xd5, 0x44, 0x82, 0x40, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x49, 0x4e, 0x46, 0x42, 0x08, 0x03, 0xd0, 0x00, 0x0c, 0x1e, 0x68, 0x08, 0x02, 0x40, 0x00, 0x01,
+ 0x9c, 0x1d, 0x00, 0x20, 0x80, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0xb4, 0x01, 0x00, 0x20,
+ 0x08, 0x00, 0x00, 0x00, 0x80, 0x01, 0x80, 0x01, 0x10, 0x01, 0x00, 0x20, 0xa8, 0x4a, 0x00, 0x20,
+ 0xa8, 0x3e, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x01, 0x00, 0x20,
+ 0x00, 0x01, 0x00, 0x00, 0xb4, 0x4f, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x04, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x20, 0xc8, 0x4f, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0xa8, 0x3c, 0x00, 0x20, 0x84, 0x12, 0x00, 0x20, 0x8c, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x47, 0xa7, 0x38, 0xcc, 0xe3, 0x60, 0x5f, 0x9d, 0xc7, 0x75, 0x7b, 0xb5, 0x7b, 0xd7, 0x69, 0xc4,
+ 0x00, 0x00, 0x68, 0x4b, 0x37, 0x32, 0x8d, 0xe2, 0x5d, 0x60, 0x40, 0x07, 0x39, 0xa0, 0x90, 0x39,
+ 0xc0, 0x10, 0x01, 0x44, 0x06, 0x2f, 0xcc, 0xe2, 0x79, 0xff, 0x2c, 0xe7, 0x54, 0x34, 0xe7, 0x40,
+ 0x40, 0x07, 0x50, 0x38, 0x60, 0x70, 0xd4, 0xd5, 0xe0, 0x40, 0x00, 0x66, 0x49, 0xcb, 0x1e, 0x38,
+ 0x60, 0x88, 0xd4, 0xf9, 0xe0, 0x40, 0xcd, 0x62, 0x59, 0xff, 0xc4, 0xeb, 0x9d, 0x20, 0x00, 0xf8,
+ 0xc0, 0xeb, 0x9d, 0x20, 0xcc, 0xe2, 0x79, 0xff, 0x2c, 0xc7, 0x43, 0x94, 0xc6, 0x00, 0x00, 0x00,
+ 0x40, 0x40, 0x06, 0xe0, 0xc1, 0x4b, 0x4e, 0x20, 0xc4, 0xcb, 0x4e, 0x20, 0x3c, 0xa6, 0x04, 0x47,
+ 0x29, 0x90, 0x8c, 0xa2, 0x6d, 0x60, 0x40, 0x07, 0x6c, 0xc6, 0x40, 0x08, 0xc5, 0x2c, 0xc6, 0x40,
+ 0x47, 0xd2, 0x30, 0x00, 0x8c, 0x02, 0x00, 0x00, 0xfa, 0x0b, 0x00, 0x00, 0x79, 0x0c, 0x00, 0x00,
+ 0x30, 0x0d, 0x00, 0x00, 0x4b, 0x0d, 0x00, 0x00, 0x51, 0x19, 0x00, 0x00, 0x72, 0x19, 0x00, 0x00,
+ 0x99, 0x08, 0x00, 0x00, 0x37, 0x1b, 0x00, 0x00, 0xc1, 0x1e, 0x00, 0x00, 0xf3, 0x21, 0x00, 0x00,
+ 0x62, 0x21, 0x00, 0x00, 0x76, 0x22, 0x00, 0x00, 0x88, 0x02, 0x00, 0x00, 0x91, 0x05, 0x00, 0x00,
+ 0xb8, 0x05, 0x00, 0x00, 0x88, 0x02, 0x00, 0x00, 0x21, 0x09, 0x00, 0x00, 0x23, 0x0d, 0x00, 0x00,
+ 0x88, 0x02, 0x00, 0x00, 0xe9, 0x04, 0x00, 0x00, 0xd7, 0x1f, 0x00, 0x00, 0x65, 0x08, 0x00, 0x00,
+ 0xcb, 0x0e, 0x00, 0x00, 0x58, 0x12, 0x00, 0x00, 0x37, 0x14, 0x00, 0x00, 0x7a, 0x0d, 0x00, 0x00,
+ 0x9f, 0x0d, 0x00, 0x00, 0x6a, 0x17, 0x00, 0x00, 0x2a, 0x19, 0x00, 0x00, 0xd1, 0x1f, 0x00, 0x00,
+ 0xe5, 0x1f, 0x00, 0x00, 0xe5, 0x02, 0x00, 0x00, 0xc0, 0x0b, 0x4e, 0x20, 0x8c, 0xc0, 0x49, 0x00,
+ 0x00, 0x04, 0xc0, 0x07, 0xaa, 0x80, 0x34, 0xc6, 0x08, 0x40, 0x06, 0x98, 0xcc, 0xe2, 0x59, 0xff,
+ 0x84, 0xc0, 0x31, 0x00, 0x00, 0x04, 0x20, 0xc7, 0x44, 0x38, 0xc0, 0x04, 0xc0, 0xc7, 0x4e, 0x20,
+ 0x0e, 0xb0, 0x2c, 0xc7, 0x40, 0x34, 0xc6, 0x40, 0x41, 0x06, 0x27, 0xcc, 0xe7, 0x61, 0x80, 0x94,
+ 0xe7, 0x00, 0x04, 0x00, 0x00, 0x41, 0x07, 0xeb, 0x8d, 0x60, 0x50, 0x80, 0x00, 0x0c, 0x8c, 0xe0,
+ 0x50, 0x80, 0x00, 0x0c, 0x60, 0xe7, 0x5d, 0x9f, 0x47, 0xfe, 0x30, 0x00, 0x00, 0x47, 0x3f, 0xdf,
+ 0x48, 0x8e, 0x48, 0x0f, 0x5f, 0x38, 0x60, 0x30, 0xd4, 0x9e, 0x60, 0x40, 0xd4, 0xe4, 0x98, 0x40,
+ 0x48, 0xdc, 0xd2, 0x00, 0x64, 0xd4, 0x36, 0x60, 0x40, 0x88, 0xe0, 0xdd, 0x00, 0x00, 0x04, 0xd0,
+ 0x00, 0x75, 0x78, 0xcc, 0xe2, 0x79, 0xff, 0x24, 0xc7, 0xf8, 0x2c, 0x07, 0x23, 0x94, 0xc6, 0xdf,
+ 0xff, 0xff, 0xff, 0x30, 0xa7, 0x30, 0x28, 0x07, 0x13, 0x20, 0xc7, 0xf8, 0x04, 0xc7, 0x20, 0x06,
+ 0x53, 0x00, 0xd8, 0xd2, 0xca, 0x6d, 0xff, 0x33, 0x00, 0x0f, 0x00, 0xa0, 0x8b, 0x00, 0x28, 0x00,
+ 0x00, 0x0c, 0x3e, 0x05, 0x22, 0xcc, 0xc2, 0x69, 0xff, 0x88, 0x86, 0x14, 0x35, 0x80, 0x00, 0xcc,
+ 0xc2, 0x69, 0xff, 0x88, 0x86, 0xa5, 0x65, 0x80, 0x00, 0xcc, 0xc2, 0x69, 0xff, 0x34, 0x84, 0xf0,
+ 0x88, 0xc6, 0x94, 0x35, 0x80, 0x00, 0x34, 0xc6, 0xf0, 0x3e, 0x06, 0xb8, 0x6e, 0xf7, 0x81, 0x60,
+ 0xd7, 0x32, 0x3e, 0x06, 0x30, 0xd2, 0x88, 0x6b, 0x00, 0x28, 0xc7, 0x93, 0x38, 0xc6, 0x80, 0x28,
+ 0xc7, 0x13, 0x00, 0xb8, 0x3c, 0x25, 0x08, 0x47, 0x2a, 0xdf, 0x32, 0xe0, 0x03, 0x00, 0xa0, 0x8a,
+ 0xe0, 0x28, 0x00, 0x00, 0x0c, 0x3e, 0x05, 0x22, 0xcc, 0xc2, 0x69, 0xff, 0x88, 0x86, 0x3b, 0xd5,
+ 0x80, 0x00, 0xcc, 0xc2, 0x69, 0xff, 0x88, 0x86, 0xbb, 0xd5, 0x80, 0x00, 0xcc, 0xc2, 0x69, 0xff,
+ 0x34, 0x84, 0xfc, 0x88, 0xc6, 0xd8, 0xd5, 0x80, 0x00, 0x94, 0xc6, 0xff, 0xfc, 0x00, 0x00, 0x6c,
+ 0xc6, 0x12, 0xd2, 0x88, 0x6b, 0x00, 0x28, 0xc7, 0x93, 0x38, 0xc6, 0x40, 0x28, 0xc7, 0x13, 0x00,
+ 0xb8, 0x3c, 0x25, 0x02, 0x47, 0x2d, 0xdf, 0x8c, 0xe0, 0x5d, 0x00, 0x00, 0x04, 0x94, 0xe7, 0x00,
+ 0x00, 0x80, 0x00, 0x40, 0x07, 0x30, 0x00, 0xa0, 0x00, 0x8e, 0x00, 0x60, 0x49, 0x3f, 0x16, 0x8c,
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+ 0x00, 0x00, 0xe0, 0x01, 0xe0, 0x01, 0x00, 0x00, 0x40, 0x01, 0x00, 0x01, 0x00, 0x00, 0xe0, 0x01,
+ 0xe0, 0x01, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x01, 0xe0, 0x01, 0x00, 0x00,
+ 0xc0, 0x00, 0x00, 0x01, 0xc0, 0x01, 0xc0, 0x01, 0xc0, 0x01, 0xc0, 0x01, 0xc0, 0x01, 0x00, 0x01,
+ 0xc0, 0x00, 0xc0, 0x01, 0xc0, 0x01, 0xc0, 0x01, 0xc0, 0x01, 0x00, 0x01, 0x00, 0x00, 0xc0, 0x01,
+ 0xc0, 0x01, 0xc0, 0x01, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0x01, 0xc0, 0x01, 0xc0, 0x01,
+ 0x00, 0x1a, 0x41, 0x62, 0x90, 0xbe, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x1a, 0x30, 0x41, 0x52, 0x5f, 0x6c, 0x82, 0x93, 0xa4, 0xb1, 0xc7, 0xd8, 0xe6, 0xf3, 0xff,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x17, 0x3a, 0x74, 0x74, 0x74, 0x74, 0x74, 0x8b, 0xae, 0xff, 0xff,
+ 0xff, 0xbc, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff,
+ 0xff, 0xa4, 0x70, 0x48, 0x31, 0x1f, 0x0d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x0c, 0x18, 0x30, 0x60, 0x9c, 0xd9, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x19, 0x2f, 0x45, 0x58, 0x6b, 0x7e, 0x91, 0xa0, 0xaf, 0xbe, 0xcd, 0xdc, 0xe8, 0xf5, 0xff,
+ 0x00, 0x16, 0x3d, 0x3f, 0x41, 0x45, 0x4e, 0x57, 0x64, 0x79, 0x8a, 0xa0, 0xb0, 0xc4, 0xdc, 0xff,
+ 0x00, 0x24, 0x49, 0x6d, 0x92, 0xb6, 0xdb, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x16, 0x2f, 0x50, 0x73, 0xa0, 0xcb, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x16, 0x54, 0x02, 0x00, 0xf8, 0x53, 0x02, 0x00, 0xf4, 0x53, 0x02, 0x00, 0xf0, 0x53, 0x02, 0x00,
+ 0x40, 0x01, 0x50, 0x00, 0x80, 0x07, 0x60, 0x09, 0xc9, 0xc4, 0xbe, 0xb9, 0xb4, 0xae, 0xa9, 0xa3,
+ 0x9d, 0x97, 0x91, 0x8b, 0x85, 0x7e, 0x78, 0xc9, 0xc4, 0xbe, 0xb9, 0xb4, 0xae, 0xa9, 0xa3, 0x9d,
+ 0x97, 0x91, 0x8b, 0x85, 0x7e, 0x78, 0xd6, 0xd1, 0xcb, 0xc6, 0xc0, 0xbb, 0xb5, 0xaf, 0xa9, 0xa3,
+ 0x9c, 0x96, 0x8f, 0x88, 0x82, 0xd6, 0xd1, 0xcb, 0xc6, 0xc0, 0xbb, 0xb5, 0xaf, 0xa9, 0xa3, 0x9c,
+ 0x96, 0x8f, 0x88, 0x82, 0x00, 0xfc, 0xf8, 0xf4, 0xf0, 0xec, 0xe8, 0xe0, 0xdc, 0xd8, 0x28, 0x21,
+ 0x1b, 0x14, 0x10, 0x0c, 0x08, 0x04, 0x00, 0xfc, 0xf8, 0xf4, 0xf0, 0xec, 0xe2, 0xd8, 0x1f, 0x1e,
+ 0x1c, 0x1b, 0x1a, 0x19, 0x18, 0x17, 0x15, 0x14, 0x13, 0x12, 0x11, 0x0f, 0x0e, 0x0d, 0x08, 0x08,
+ 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x1f, 0x1f,
+ 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1f, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x1e, 0x0f, 0x0e,
+ 0x0e, 0x0d, 0x0d, 0x0d, 0x0c, 0x0c, 0x0b, 0x0b, 0x0a, 0x0a, 0x09, 0x09, 0x08, 0x08, 0x1f, 0x1f,
+ 0x1e, 0x1d, 0x1c, 0x1b, 0x19, 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x0f, 0x08, 0x08,
+ 0x08, 0x08, 0x07, 0x07, 0x07, 0x07, 0x07, 0x06, 0x06, 0x06, 0x06, 0x05, 0x05, 0x05, 0x1f, 0x1f,
+ 0x1f, 0x1f, 0x1e, 0x1e, 0x1e, 0x1d, 0x1d, 0x1c, 0x1c, 0x1b, 0x1b, 0x1b, 0x1a, 0x1a, 0x0d, 0x0d,
+ 0x0c, 0x0c, 0x0b, 0x0b, 0x0a, 0x0a, 0x0a, 0x09, 0x09, 0x08, 0x08, 0x07, 0x07, 0x06, 0x1a, 0x19,
+ 0x19, 0x19, 0x18, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16, 0x16, 0x16, 0x15, 0x15, 0x15, 0x1a, 0x19,
+ 0x19, 0x19, 0x18, 0x18, 0x17, 0x17, 0x17, 0x16, 0x16, 0x15, 0x15, 0x15, 0x14, 0x14, 0x13, 0x13,
+ 0x12, 0x12, 0x11, 0x10, 0x10, 0x0f, 0x0f, 0x0e, 0x0d, 0x0d, 0x0c, 0x0c, 0x0b, 0x0a, 0x0c, 0x0c,
+ 0x0b, 0x0b, 0x0b, 0x0b, 0x0a, 0x0a, 0x0a, 0x09, 0x09, 0x09, 0x09, 0x08, 0x08, 0x08, 0x1b, 0x1a,
+ 0x1a, 0x19, 0x19, 0x18, 0x18, 0x17, 0x16, 0x16, 0x15, 0x15, 0x14, 0x14, 0x13, 0x13, 0x17, 0x16,
+ 0x16, 0x15, 0x14, 0x13, 0x13, 0x12, 0x11, 0x10, 0x10, 0x0f, 0x0e, 0x0d, 0x0d, 0x0c, 0x0e, 0x0d,
+ 0x0d, 0x0d, 0x0d, 0x0c, 0x0c, 0x0c, 0x0b, 0x0b, 0x0b, 0x0b, 0x0a, 0x0a, 0x0a, 0x0a, 0x1d, 0x1c,
+ 0x1b, 0x1b, 0x1a, 0x19, 0x19, 0x18, 0x17, 0x17, 0x16, 0x15, 0x15, 0x14, 0x13, 0x13, 0x00, 0x00,
+ 0x34, 0x54, 0x02, 0x00, 0x3e, 0x54, 0x02, 0x00, 0xce, 0x54, 0x02, 0x00, 0xee, 0x54, 0x02, 0x00,
+ 0xde, 0x54, 0x02, 0x00, 0x1e, 0x55, 0x02, 0x00, 0x90, 0xc8, 0x01, 0x00, 0x7c, 0x55, 0x02, 0x00,
+ 0xb4, 0xe3, 0x01, 0x00, 0xc0, 0xe4, 0x01, 0x00, 0x68, 0xe7, 0x01, 0x00, 0x00, 0x01, 0x00, 0x01,
+ 0x24, 0xf9, 0x01, 0x00, 0xf1, 0xff, 0xf1, 0xff, 0xe8, 0xff, 0xf1, 0xff, 0x0f, 0x00, 0x0f, 0x00,
+ 0x18, 0x00, 0x0f, 0x00, 0x05, 0x06, 0x07, 0x48, 0x10, 0x10, 0x08, 0x08, 0x05, 0x06, 0x07, 0x62,
+ 0x80, 0x00, 0x20, 0x00, 0x60, 0x00, 0x20, 0x00, 0x80, 0x00, 0xc0, 0x00, 0x20, 0x00, 0x40, 0x00,
+ 0x20, 0x00, 0x80, 0x00, 0x40, 0x00, 0x80, 0x00, 0x40, 0x00, 0x60, 0x00, 0x20, 0x00, 0x40, 0x00,
+ 0xc0, 0x00, 0x80, 0x00, 0x40, 0x00, 0x60, 0x00, 0x20, 0x00, 0x40, 0x00, 0xc0, 0x00, 0x80, 0x00,
+ 0x20, 0x00, 0x60, 0x00, 0x00, 0x00, 0x80, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x60, 0x00, 0x20, 0x00,
+ 0x00, 0x00, 0xc0, 0x00, 0x80, 0x00, 0x00, 0x00, 0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0x80, 0x00,
+ 0x80, 0x00, 0x00, 0x00, 0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00,
+ 0xb8, 0x55, 0x02, 0x00, 0x84, 0x55, 0x02, 0x00, 0x8c, 0x55, 0x02, 0x00, 0x94, 0x55, 0x02, 0x00,
+ 0x98, 0x55, 0x02, 0x00, 0x9c, 0x55, 0x02, 0x00, 0xb4, 0x01, 0x00, 0x20, 0x84, 0x12, 0x00, 0x20,
+ 0xb4, 0x01, 0x00, 0x20, 0x84, 0x12, 0x00, 0x20, 0xb4, 0x01, 0x00, 0x20, 0x84, 0x12, 0x00, 0x20,
+ 0x9c, 0x1d, 0x00, 0x20, 0x00, 0x01, 0x00, 0x20, 0x10, 0x01, 0x00, 0x20, 0x30, 0x01, 0x00, 0x20,
+ 0xb4, 0x01, 0x00, 0x20, 0x84, 0x12, 0x00, 0x20, 0x5a, 0x36, 0x02, 0x00, 0xb4, 0x36, 0x02, 0x00,
+ 0x0e, 0x37, 0x02, 0x00, 0xbc, 0x3d, 0x02, 0x00, 0x68, 0x37, 0x02, 0x00, 0xc2, 0x37, 0x02, 0x00,
+ 0x1c, 0x38, 0x02, 0x00, 0x76, 0x38, 0x02, 0x00, 0xd0, 0x38, 0x02, 0x00, 0x2a, 0x39, 0x02, 0x00,
+ 0x84, 0x39, 0x02, 0x00, 0xde, 0x39, 0x02, 0x00, 0x38, 0x3a, 0x02, 0x00, 0x92, 0x3a, 0x02, 0x00,
+ 0xec, 0x3a, 0x02, 0x00, 0x46, 0x3b, 0x02, 0x00, 0xa0, 0x3b, 0x02, 0x00, 0xfa, 0x3b, 0x02, 0x00,
+ 0x54, 0x3c, 0x02, 0x00, 0xae, 0x3c, 0x02, 0x00, 0x08, 0x3d, 0x02, 0x00, 0x62, 0x3d, 0x02, 0x00,
+ 0xa8, 0x3e, 0x00, 0x20, 0xac, 0x56, 0x02, 0x00, 0xde, 0x56, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0xf4, 0xff, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0xe0, 0xff,
+ 0x80, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x0c, 0x00, 0xd8, 0xff, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe8, 0xff, 0x80, 0x00,
+ 0xf0, 0xff, 0x00, 0x00, 0x00, 0x00, 0xd6, 0xff, 0x7e, 0x00, 0x00, 0x00, 0xa0, 0x00, 0x00, 0x20,
+ 0x6c, 0x1f, 0x02, 0x00, 0x80, 0x02, 0xc0, 0x02, 0x00, 0x00, 0xc0, 0x03, 0xc0, 0x03, 0x00, 0x00,
+ 0x80, 0x00, 0xc0, 0x00, 0x00, 0x00, 0xc0, 0x03, 0xc0, 0x03, 0x00, 0x00, 0x40, 0x03, 0x00, 0x03,
+ 0x00, 0x00, 0xc0, 0x03, 0xc0, 0x03, 0x00, 0x00, 0x40, 0x01, 0x00, 0x01, 0x00, 0x00, 0xc0, 0x03,
+ 0xc0, 0x03, 0x00, 0x00, 0xc0, 0x03, 0x00, 0x03, 0xc0, 0x00, 0xc0, 0x03, 0xc0, 0x03, 0xc0, 0x03,
+ 0xc0, 0x01, 0x00, 0x01, 0xc0, 0x00, 0xc0, 0x03, 0xc0, 0x03, 0xc0, 0x03, 0xc0, 0x01, 0x00, 0x03,
+ 0x00, 0x02, 0xc0, 0x03, 0xc0, 0x03, 0xc0, 0x03, 0xc0, 0x03, 0x00, 0x03, 0x00, 0x00, 0xc0, 0x03,
+ 0xc0, 0x03, 0xc0, 0x03, 0x00, 0x00, 0x48, 0x00, 0x78, 0x00, 0x78, 0x00, 0x78, 0x00, 0x78, 0x00,
+ 0x10, 0x00, 0x40, 0x00, 0x60, 0x00, 0x78, 0x00, 0x78, 0x00, 0x78, 0x00, 0x10, 0x00, 0x28, 0x00,
+ 0x18, 0x00, 0x78, 0x00, 0x78, 0x00, 0x78, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x78, 0x00,
+ 0x78, 0x00, 0x78, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0xb0, 0x01, 0x00, 0x00, 0x00, 0x00,
+ 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0xb0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x30, 0x00,
+ 0x00, 0x00, 0xb0, 0x01, 0xb0, 0x01, 0x00, 0x00, 0x80, 0x01, 0x80, 0x01, 0x00, 0x00, 0xb0, 0x01,
+ 0xb0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x30, 0x00, 0xb0, 0x01, 0xb0, 0x01, 0xb0, 0x01,
+ 0x00, 0x00, 0x80, 0x01, 0x80, 0x01, 0xb0, 0x01, 0xb0, 0x01, 0xb0, 0x01, 0x94, 0x57, 0x02, 0x00
+};
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/ucode/quad.h b/drivers/net/ethernet/hpe/sl/core/hw/ucode/quad.h
new file mode 100644
index 000000000000..8aa7479db01e
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/ucode/quad.h
@@ -0,0 +1,9410 @@
+#define OSPREY7_V2L4P1_UCODE_IMAGE_VERSION "D003_04"  /* matches the version number from microcode */
+#define OSPREY7_V2L4P1_UCODE_IMAGE_SIZE    150448
+#define OSPREY7_V2L4P1_UCODE_STACK_SIZE    0x13E4
+#define OSPREY7_V2L4P1_UCODE_IMAGE_CRC     0xA744
+
+static unsigned char osprey7_v2l4p1_ucode_image[OSPREY7_V2L4P1_UCODE_IMAGE_SIZE] = {
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd5, 0x52, 0x54, 0x40, 0x00, 0x00, 0x00, 0x00,
+ 0xd5, 0xf1, 0x4c, 0x40, 0x00, 0x00, 0x00, 0x00, 0xd5, 0x87, 0x4c, 0x40, 0x00, 0x00, 0x00, 0x00,
+ 0xd5, 0xcc, 0xcc, 0x40, 0x00, 0x00, 0x00, 0x00, 0xd5, 0xa1, 0xcc, 0x40, 0x00, 0x00, 0x00, 0x00,
+ 0xd5, 0xeb, 0xcc, 0x40, 0x00, 0x00, 0x00, 0x00, 0xd5, 0x94, 0x2c, 0x40, 0x00, 0x00, 0x00, 0x00,
+ 0xd5, 0x42, 0x54, 0x40, 0x00, 0x00, 0x00, 0x00, 0xd5, 0xce, 0x2c, 0x40, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0xd5, 0xad, 0x2c, 0x40, 0x00, 0x00, 0x00, 0x00, 0xd5, 0xe0, 0xac, 0x40, 0x00, 0x00, 0x00, 0x00,
+ 0xd5, 0x9a, 0xac, 0x40, 0x00, 0x00, 0x00, 0x00, 0xd5, 0xd5, 0xac, 0x40, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x49, 0x4e, 0x46, 0x42, 0x04, 0x03, 0xd0, 0x00, 0xd4, 0x1d, 0x68, 0x08, 0x02, 0x40, 0x00, 0x01,
+ 0x9c, 0x1d, 0x00, 0x20, 0x80, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0xb4, 0x01, 0x00, 0x20,
+ 0x08, 0x00, 0x00, 0x00, 0x80, 0x01, 0x80, 0x01, 0x10, 0x01, 0x00, 0x20, 0x70, 0x4a, 0x00, 0x20,
+ 0x70, 0x3e, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x01, 0x00, 0x20,
+ 0x00, 0x01, 0x00, 0x00, 0x50, 0x44, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x02, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x20, 0x90, 0x4f, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
+ 0x70, 0x3c, 0x00, 0x20, 0x84, 0x12, 0x00, 0x20, 0x8c, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x47, 0xa7, 0x38, 0xcc, 0xe3, 0x60, 0x5f, 0x9d, 0xc7, 0x75, 0x7b, 0xb5, 0x7b, 0xd7, 0x58, 0xc4,
+ 0x00, 0x00, 0x68, 0x49, 0xe0, 0xf2, 0x8d, 0xc2, 0x5e, 0xdf, 0x80, 0x07, 0x39, 0xa0, 0x90, 0x01,
+ 0x44, 0x06, 0x2e, 0xcc, 0xe2, 0x79, 0xff, 0x2c, 0xe7, 0x54, 0x34, 0xe7, 0x40, 0x40, 0x07, 0x50,
+ 0x38, 0x60, 0x70, 0xd4, 0x9d, 0x40, 0x40, 0x00, 0x66, 0x48, 0x48, 0xfc, 0x38, 0x60, 0x88, 0xd4,
+ 0xb5, 0x40, 0x40, 0xcd, 0x62, 0x59, 0xff, 0xc4, 0xeb, 0x9d, 0x20, 0x00, 0xf8, 0xc0, 0xeb, 0x9d,
+ 0x20, 0xcc, 0xe2, 0x79, 0xff, 0xcc, 0xc7, 0x51, 0x80, 0x34, 0xc6, 0x40, 0x40, 0x06, 0xe0, 0xc1,
+ 0x4b, 0x4e, 0x20, 0xc4, 0xcb, 0x4e, 0x20, 0x3c, 0xa6, 0x04, 0x47, 0x25, 0x90, 0x8c, 0xa2, 0x6e,
+ 0xdf, 0x80, 0x07, 0x6c, 0xc6, 0x40, 0x08, 0xc5, 0x2c, 0xc6, 0x40, 0x47, 0xd2, 0x30, 0x00, 0x00,
+ 0x88, 0x02, 0x00, 0x00, 0x1d, 0x09, 0x00, 0x00, 0x9a, 0x09, 0x00, 0x00, 0x36, 0x0a, 0x00, 0x00,
+ 0x51, 0x0a, 0x00, 0x00, 0x51, 0x16, 0x00, 0x00, 0x72, 0x16, 0x00, 0x00, 0xc0, 0x05, 0x00, 0x00,
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+ 0x20, 0x00, 0x60, 0x00, 0x00, 0x00, 0x80, 0x00, 0xc0, 0x00, 0x00, 0x00, 0x60, 0x00, 0x20, 0x00,
+ 0x00, 0x00, 0xc0, 0x00, 0x80, 0x00, 0x00, 0x00, 0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0x80, 0x00,
+ 0x80, 0x00, 0x00, 0x00, 0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0x80, 0x00, 0x80, 0x00, 0x00, 0x00,
+ 0x08, 0x4a, 0x02, 0x00, 0xd4, 0x49, 0x02, 0x00, 0xdc, 0x49, 0x02, 0x00, 0xe4, 0x49, 0x02, 0x00,
+ 0xe8, 0x49, 0x02, 0x00, 0xec, 0x49, 0x02, 0x00, 0xb4, 0x01, 0x00, 0x20, 0x84, 0x12, 0x00, 0x20,
+ 0xb4, 0x01, 0x00, 0x20, 0x84, 0x12, 0x00, 0x20, 0xb4, 0x01, 0x00, 0x20, 0x84, 0x12, 0x00, 0x20,
+ 0x9c, 0x1d, 0x00, 0x20, 0x00, 0x01, 0x00, 0x20, 0x10, 0x01, 0x00, 0x20, 0x30, 0x01, 0x00, 0x20,
+ 0xb4, 0x01, 0x00, 0x20, 0x84, 0x12, 0x00, 0x20, 0xe3, 0x2a, 0x02, 0x00, 0x3d, 0x2b, 0x02, 0x00,
+ 0x97, 0x2b, 0x02, 0x00, 0x45, 0x32, 0x02, 0x00, 0xf1, 0x2b, 0x02, 0x00, 0x4b, 0x2c, 0x02, 0x00,
+ 0xa5, 0x2c, 0x02, 0x00, 0xff, 0x2c, 0x02, 0x00, 0x59, 0x2d, 0x02, 0x00, 0xb3, 0x2d, 0x02, 0x00,
+ 0x0d, 0x2e, 0x02, 0x00, 0x67, 0x2e, 0x02, 0x00, 0xc1, 0x2e, 0x02, 0x00, 0x1b, 0x2f, 0x02, 0x00,
+ 0x75, 0x2f, 0x02, 0x00, 0xcf, 0x2f, 0x02, 0x00, 0x29, 0x30, 0x02, 0x00, 0x83, 0x30, 0x02, 0x00,
+ 0xdd, 0x30, 0x02, 0x00, 0x37, 0x31, 0x02, 0x00, 0x91, 0x31, 0x02, 0x00, 0xeb, 0x31, 0x02, 0x00,
+ 0x70, 0x3e, 0x00, 0x20, 0xfc, 0x4a, 0x02, 0x00, 0x2e, 0x4b, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x54, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0xf4, 0xff, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0xe0, 0xff,
+ 0x80, 0x00, 0x00, 0x00, 0xfc, 0xff, 0x0c, 0x00, 0xd8, 0xff, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0xa8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe8, 0xff, 0x80, 0x00,
+ 0xf0, 0xff, 0x00, 0x00, 0x00, 0x00, 0xd6, 0xff, 0x7e, 0x00, 0x00, 0x00, 0x94, 0x10, 0x02, 0x00,
+ 0xb4, 0x01, 0x00, 0x20, 0x84, 0x12, 0x00, 0x20, 0x64, 0x14, 0x02, 0x00, 0xf4, 0x19, 0x02, 0x00,
+ 0x2c, 0x19, 0x02, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0xb0, 0x01, 0x00, 0x00, 0x00, 0x00,
+ 0x80, 0x01, 0x00, 0x00, 0x00, 0x00, 0xb0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x30, 0x00,
+ 0x00, 0x00, 0xb0, 0x01, 0xb0, 0x01, 0x00, 0x00, 0x80, 0x01, 0x80, 0x01, 0x00, 0x00, 0xb0, 0x01,
+ 0xb0, 0x01, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x30, 0x00, 0xb0, 0x01, 0xb0, 0x01, 0xb0, 0x01,
+ 0x00, 0x00, 0x80, 0x01, 0x80, 0x01, 0xb0, 0x01, 0xb0, 0x01, 0xb0, 0x01, 0x64, 0x4b, 0x02, 0x00
+};
diff --git a/drivers/net/ethernet/hpe/sl/core/sl_core_ldev.h b/drivers/net/ethernet/hpe/sl/core/sl_core_ldev.h
new file mode 100644
index 000000000000..f9736d41bf9a
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/sl_core_ldev.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2021,2022,2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_LDEV_H_
+#define _SL_CORE_LDEV_H_
+
+#include <linux/spinlock.h>
+#include <linux/workqueue.h>
+
+#include <linux/hpe/sl/sl_ldev.h>
+
+#include "sl_asic.h"
+
+struct sl_accessors;
+struct sl_ops;
+
+struct sl_serdes_fw_info {
+	u32 signature;
+	u8  version;
+	u32 lane_static_var_ram_base;
+	u32 lane_static_var_ram_size;
+	u32 lane_var_ram_base;
+	u16 lane_var_ram_size;
+	u16 grp_ram_size;
+	u8  lane_count;
+};
+
+struct sl_serdes_hw_info {
+	u8 num_cores;
+	u8 rev_id_1;
+	u8 rev_id_2;
+	u8 version;
+	u8 num_micros;
+	u8 num_lanes;
+	u8 num_plls;
+};
+
+#define SL_CORE_LDEV_MAGIC 0x73734c44
+struct sl_core_ldev {
+	u32                       magic;
+	u8                        num;
+
+	u8                        platform;
+	u16                       revision;
+
+	struct sl_accessors       accessors;
+	struct sl_ops             ops;
+
+	spinlock_t                data_lock;
+
+	struct {
+		const struct firmware    *fw;
+		struct sl_serdes_hw_info  hw_info[SL_ASIC_MAX_SERDES];
+		struct sl_serdes_fw_info  fw_info[SL_ASIC_MAX_SERDES];
+		bool                      is_ready;
+		u16                      *addrs;
+	} serdes;
+
+	struct workqueue_struct  *workqueue;
+};
+
+int                  sl_core_ldev_new(u8 ldev_num,
+				      struct sl_accessors *assessors,
+				      struct sl_ops *ops,
+				      struct workqueue_struct *workqueue);
+int                  sl_core_ldev_serdes_init(u8 ldev_num);
+int                  sl_core_ldev_del(u8 ldev_num);
+struct sl_core_ldev *sl_core_ldev_get(u8 ldev_num);
+
+void sl_core_ldev_serdes_is_ready_set(struct sl_core_ldev *core_ldev, bool ready);
+bool sl_core_ldev_serdes_is_ready(struct sl_core_ldev *core_ldev);
+
+#endif /* _SL_CORE_LDEV_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/sl_core_lgrp.h b/drivers/net/ethernet/hpe/sl/core/sl_core_lgrp.h
new file mode 100644
index 000000000000..c424e1224e40
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/sl_core_lgrp.h
@@ -0,0 +1,214 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2021-2026 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_LGRP_H_
+#define _SL_CORE_LGRP_H_
+
+#include <linux/spinlock.h>
+#include <linux/cleanup.h>
+#include <linux/kref.h>
+
+#include <linux/hpe/sl/sl_lgrp.h>
+
+#include "sl_asic.h"
+#include "base/sl_core_log.h"
+#include "sl_core_ldev.h"
+
+enum sl_dt_jack_type {
+	SL_DT_JACK_TYPE_LEGACY,
+	SL_DT_JACK_TYPE_DD,
+	SL_DT_JACK_TYPE_EXAMAX_LEFT,
+	SL_DT_JACK_TYPE_EXAMAX_RIGHT,
+	SL_DT_JACK_TYPE_LOW,
+	SL_DT_JACK_TYPE_HIGH,
+};
+
+#define SL_CORE_LGRP_MAGIC 0x736c474D
+struct sl_core_lgrp {
+	u32                             magic;
+	u32                             num;
+
+	struct sl_core_ldev            *core_ldev;
+
+	spinlock_t                      data_lock;
+
+	spinlock_t                      log_lock;
+	char                            log_connect_id[SL_LOG_CONNECT_ID_LEN + 1];
+
+	u8                              is_configuring;
+	struct kref                     ref;
+	/* Protected by data_lock; excludes new lookups and configuration. */
+	u8                              is_deleting;
+	struct sl_hw_attr               hw_attr;
+	struct sl_lgrp_config           config;
+
+	struct sl_link_caps             link_caps[SL_ASIC_MAX_LINKS];
+
+	struct {
+		struct sl_dt_lgrp_info  dt;
+		u32                     clocking;
+		struct {
+			u32             tx;
+			u32             rx;
+		} lane_state[SL_MAX_LANES];
+		struct {
+			u8              low;
+			u8              high;
+		} eye_limits[SL_MAX_LANES];
+	} serdes;
+
+	struct {
+		struct {
+			u16             addr;
+			u16             data;
+			u8              dev_id;
+			u8              lane;
+			u8              pll;
+			int             result;
+		} rd;
+		struct {
+			u16             addr;
+			u16             data;
+			u16             mask;
+			u8              dev_id;
+			u8              lane;
+			u8              pll;
+			int             result;
+		} wr;
+	} pmi;
+
+	struct {
+		struct {
+			u8              dev_addr;
+			u32             data;
+			u32             mask;
+			u8              reg;
+			u8              lsb;
+			int             result;
+		} rd;
+		struct {
+			u8              dev_addr;
+			u32             data;
+			u32             mask;
+			u8              reg;
+			u8              lsb;
+			int             result;
+		} wr;
+		struct {
+			u8              dev_addr;
+			int             result;
+		} rst;
+	} sbus;
+
+	struct {
+		struct {
+			u8              dev_addr;
+			u16             addr;
+			u16             data;
+			u16             mask;
+			u8              dev_id;
+			u8              lane;
+			u8              pll;
+			int             result;
+		} rd;
+		struct {
+			u8              dev_addr;
+			u16             addr;
+			u16             data;
+			u16             mask;
+			u8              dev_id;
+			u8              lane;
+			u8              pll;
+			int             result;
+		} wr;
+	} sbus_pmi;
+
+	bool err_trace_enable;
+	bool warn_trace_enable;
+	bool io_trace;
+};
+
+int		     sl_core_lgrp_new(u8 ldev_num, u8 lgrp_num);
+void		     sl_core_lgrp_connect_id_set(u8 ldev_num, u8 lgrp_num, const char *connect_id);
+int		     sl_core_lgrp_del(u8 ldev_num, u8 lgrp_num);
+struct sl_core_lgrp *sl_core_lgrp_get(u8 ldev_num, u8 lgrp_num);
+void                sl_core_lgrp_put(struct sl_core_lgrp *core_lgrp);
+DEFINE_FREE(sl_core_lgrp_put, struct sl_core_lgrp *, sl_core_lgrp_put(_T))
+
+int sl_core_lgrp_hw_attr_set(u8 ldev_num, u8 lgrp_num, struct sl_hw_attr *hw_attr);
+int sl_core_lgrp_config_set(u8 ldev_num, u8 lgrp_num, struct sl_lgrp_config *lgrp_config);
+
+int sl_core_lgrp_pre1_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, s16 *pre1);
+int sl_core_lgrp_pre2_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, s16 *pre2);
+int sl_core_lgrp_pre3_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, s16 *pre3);
+int sl_core_lgrp_cursor_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, s16 *cursor);
+int sl_core_lgrp_post1_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, s16 *post1);
+int sl_core_lgrp_post2_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, s16 *post2);
+
+int sl_core_lgrp_osr_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, u8 *osr);
+int sl_core_lgrp_encoding_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, u8 *encoding);
+int sl_core_lgrp_width_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, u8 *width);
+int sl_core_lgrp_dfe_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, u8 *width);
+int sl_core_lgrp_scramble_dis_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, u8 *scramble_dis);
+int sl_core_lgrp_eye_upper_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, u8 *eye_upper);
+int sl_core_lgrp_eye_lower_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, u8 *eye_lower);
+
+bool sl_core_lgrp_media_lane_data_swap(u8 ldev_num, u8 lgrp_num);
+u32  sl_core_lgrp_jack_part_get(u8 ldev_num, u8 lgrp_num);
+
+int sl_core_lgrp_tx_lane_is_lol(u8 ldev_num, u8 lgrp_num, u8 asic_lane_num, bool *is_tx_lol);
+int sl_core_lgrp_rx_lane_is_lol(u8 ldev_num, u8 lgrp_num, u8 asic_lane_num, bool *is_rx_lol);
+int sl_core_lgrp_tx_lane_is_los(u8 ldev_num, u8 lgrp_num, u8 asic_lane_num, bool *is_tx_los);
+int sl_core_lgrp_rx_lane_is_los(u8 ldev_num, u8 lgrp_num, u8 asic_lane_num, bool *is_rx_los);
+
+int sl_core_lgrp_pmi_rd_addr_get(struct sl_core_lgrp *core_lgrp, u16 *addr);
+int sl_core_lgrp_pmi_rd_data_get(struct sl_core_lgrp *core_lgrp, u16 *data);
+int sl_core_lgrp_pmi_rd_dev_id_get(struct sl_core_lgrp *core_lgrp, u8 *dev_id);
+int sl_core_lgrp_pmi_rd_lane_get(struct sl_core_lgrp *core_lgrp, u8 *lane);
+int sl_core_lgrp_pmi_rd_pll_get(struct sl_core_lgrp *core_lgrp, u8 *pll);
+int sl_core_lgrp_pmi_rd_result_get(struct sl_core_lgrp *core_lgrp, int *result);
+
+int sl_core_lgrp_pmi_wr_addr_get(struct sl_core_lgrp *core_lgrp, u16 *addr);
+int sl_core_lgrp_pmi_wr_data_get(struct sl_core_lgrp *core_lgrp, u16 *data);
+int sl_core_lgrp_pmi_wr_mask_get(struct sl_core_lgrp *core_lgrp, u16 *mask);
+int sl_core_lgrp_pmi_wr_dev_id_get(struct sl_core_lgrp *core_lgrp, u8 *dev_id);
+int sl_core_lgrp_pmi_wr_lane_get(struct sl_core_lgrp *core_lgrp, u8 *lane);
+int sl_core_lgrp_pmi_wr_pll_get(struct sl_core_lgrp *core_lgrp, u8 *pll);
+int sl_core_lgrp_pmi_wr_result_get(struct sl_core_lgrp *core_lgrp, int *result);
+
+int sl_core_lgrp_sbus_rd_dev_addr_get(struct sl_core_lgrp *core_lgrp, u8 *dev_addr);
+int sl_core_lgrp_sbus_rd_data_get(struct sl_core_lgrp *core_lgrp, u32 *data);
+int sl_core_lgrp_sbus_rd_mask_get(struct sl_core_lgrp *core_lgrp, u32 *mask);
+int sl_core_lgrp_sbus_rd_reg_get(struct sl_core_lgrp *core_lgrp, u8 *reg);
+int sl_core_lgrp_sbus_rd_lsb_get(struct sl_core_lgrp *core_lgrp, u8 *lsb);
+int sl_core_lgrp_sbus_rd_result_get(struct sl_core_lgrp *core_lgrp, int *result);
+
+int sl_core_lgrp_sbus_wr_dev_addr_get(struct sl_core_lgrp *core_lgrp, u8 *dev_addr);
+int sl_core_lgrp_sbus_wr_data_get(struct sl_core_lgrp *core_lgrp, u32 *data);
+int sl_core_lgrp_sbus_wr_mask_get(struct sl_core_lgrp *core_lgrp, u32 *mask);
+int sl_core_lgrp_sbus_wr_reg_get(struct sl_core_lgrp *core_lgrp, u8 *reg);
+int sl_core_lgrp_sbus_wr_lsb_get(struct sl_core_lgrp *core_lgrp, u8 *lsb);
+int sl_core_lgrp_sbus_wr_result_get(struct sl_core_lgrp *core_lgrp, int *result);
+
+int sl_core_lgrp_sbus_rst_dev_addr_get(struct sl_core_lgrp *core_lgrp, u8 *dev_addr);
+int sl_core_lgrp_sbus_rst_result_get(struct sl_core_lgrp *core_lgrp, int *result);
+
+int sl_core_lgrp_sbus_pmi_rd_dev_addr_get(struct sl_core_lgrp *core_lgrp, u8 *dev_addr);
+int sl_core_lgrp_sbus_pmi_rd_addr_get(struct sl_core_lgrp *core_lgrp, u16 *addr);
+int sl_core_lgrp_sbus_pmi_rd_data_get(struct sl_core_lgrp *core_lgrp, u16 *data);
+int sl_core_lgrp_sbus_pmi_rd_mask_get(struct sl_core_lgrp *core_lgrp, u16 *mask);
+int sl_core_lgrp_sbus_pmi_rd_dev_id_get(struct sl_core_lgrp *core_lgrp, u8 *dev_id);
+int sl_core_lgrp_sbus_pmi_rd_lane_get(struct sl_core_lgrp *core_lgrp, u8 *lane);
+int sl_core_lgrp_sbus_pmi_rd_pll_get(struct sl_core_lgrp *core_lgrp, u8 *pll);
+int sl_core_lgrp_sbus_pmi_rd_result_get(struct sl_core_lgrp *core_lgrp, int *result);
+
+int sl_core_lgrp_sbus_pmi_wr_dev_addr_get(struct sl_core_lgrp *core_lgrp, u8 *dev_addr);
+int sl_core_lgrp_sbus_pmi_wr_addr_get(struct sl_core_lgrp *core_lgrp, u16 *addr);
+int sl_core_lgrp_sbus_pmi_wr_data_get(struct sl_core_lgrp *core_lgrp, u16 *data);
+int sl_core_lgrp_sbus_pmi_wr_mask_get(struct sl_core_lgrp *core_lgrp, u16 *mask);
+int sl_core_lgrp_sbus_pmi_wr_dev_id_get(struct sl_core_lgrp *core_lgrp, u8 *dev_id);
+int sl_core_lgrp_sbus_pmi_wr_lane_get(struct sl_core_lgrp *core_lgrp, u8 *lane);
+int sl_core_lgrp_sbus_pmi_wr_pll_get(struct sl_core_lgrp *core_lgrp, u8 *pll);
+int sl_core_lgrp_sbus_pmi_wr_result_get(struct sl_core_lgrp *core_lgrp, int *result);
+
+#endif /* _SL_CORE_LGRP_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/sl_core_link.h b/drivers/net/ethernet/hpe/sl/core/sl_core_link.h
new file mode 100644
index 000000000000..f11b63b5f831
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/sl_core_link.h
@@ -0,0 +1,534 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2021-2026 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_LINK_H_
+#define _SL_CORE_LINK_H_
+
+#include <linux/spinlock.h>
+#include <linux/kref.h>
+#include <linux/cleanup.h>
+#include <linux/ktime.h>
+
+#include <linux/hpe/sl/sl_link.h>
+#include <linux/hpe/sl/sl_lgrp.h>
+
+#include "sl_ctrl_link.h"
+#include "sl_ctrl_link_fec_priv.h"
+#include "sl_core_lgrp.h"
+#include "sl_core_link_an.h"
+#include "sl_core_link_fec.h"
+#include "hw/sl_core_hw_an.h"
+#include "hw/sl_core_hw_intr.h"
+#include "hw/sl_core_hw_serdes.h"
+#include "hw/sl_core_hw_reset.h"
+#include "base/sl_core_timer_link.h"
+#include "base/sl_core_work_link.h"
+
+#include "sl_media_jack.h"
+
+struct work_struct;
+
+#define is_flag_set(_flags, _flag) ((_flags & _flag) == _flag)
+
+#define SL_LINK_DOWN_CAUSE_SERDES_PLL_MAP (            \
+		SL_LINK_DOWN_CAUSE_SERDES_PLL        | \
+		SL_LINK_DOWN_ORIGIN_LINK_UP          | \
+		SL_LINK_DOWN_RETRYABLE)
+#define SL_LINK_DOWN_CAUSE_SERDES_CONFIG_MAP (         \
+		SL_LINK_DOWN_CAUSE_SERDES_CONFIG     | \
+		SL_LINK_DOWN_ORIGIN_LINK_UP          | \
+		SL_LINK_DOWN_RETRYABLE)
+#define SL_LINK_DOWN_CAUSE_SERDES_SIGNAL_MAP (         \
+		SL_LINK_DOWN_CAUSE_SERDES_SIGNAL     | \
+		SL_LINK_DOWN_ORIGIN_LINK_UP          | \
+		SL_LINK_DOWN_RETRYABLE)
+#define SL_LINK_DOWN_CAUSE_SERDES_QUALITY_MAP (        \
+		SL_LINK_DOWN_CAUSE_SERDES_QUALITY    | \
+		SL_LINK_DOWN_ORIGIN_LINK_UP          | \
+		SL_LINK_DOWN_RETRYABLE)
+#define SL_LINK_DOWN_CAUSE_INTR_ENABLE_MAP (           \
+		SL_LINK_DOWN_CAUSE_INTR_ENABLE       | \
+		SL_LINK_DOWN_ORIGIN_LINK_UP          | \
+		SL_LINK_DOWN_RETRYABLE)
+#define SL_LINK_DOWN_CAUSE_AUTONEG_NOMATCH_MAP (       \
+		SL_LINK_DOWN_CAUSE_AUTONEG_NOMATCH   | \
+		SL_LINK_DOWN_ORIGIN_LINK_UP          | \
+		SL_LINK_DOWN_RETRYABLE)
+#define SL_LINK_DOWN_CAUSE_CONFIG_MAP (                \
+		SL_LINK_DOWN_CAUSE_CONFIG            | \
+		SL_LINK_DOWN_ORIGIN_LINK_UP          | \
+		SL_LINK_DOWN_RETRYABLE)
+#define SL_LINK_DOWN_CAUSE_AUTONEG_MAP (               \
+		SL_LINK_DOWN_CAUSE_AUTONEG           | \
+		SL_LINK_DOWN_ORIGIN_LINK_UP          | \
+		SL_LINK_DOWN_RETRYABLE)
+#define SL_LINK_DOWN_CAUSE_TIMEOUT_MAP (               \
+		SL_LINK_DOWN_CAUSE_TIMEOUT           | \
+		SL_LINK_DOWN_ORIGIN_LINK_UP          | \
+		SL_LINK_DOWN_RETRYABLE)
+#define SL_LINK_DOWN_CAUSE_UNSUPPORTED_CABLE_MAP (     \
+		SL_LINK_DOWN_CAUSE_UNSUPPORTED_CABLE | \
+		SL_LINK_DOWN_ORIGIN_LINK_UP          | \
+		SL_LINK_DOWN_RETRYABLE)
+#define SL_LINK_DOWN_CAUSE_SS200_CABLE_MAP (           \
+		SL_LINK_DOWN_CAUSE_SS200_CABLE       | \
+		SL_LINK_DOWN_ORIGIN_LINK_UP          | \
+		SL_LINK_DOWN_RETRYABLE)
+#define SL_LINK_DOWN_CAUSE_MEDIA_ERROR_MAP (           \
+		SL_LINK_DOWN_CAUSE_MEDIA_ERROR       | \
+		SL_LINK_DOWN_ORIGIN_LINK_UP          | \
+		SL_LINK_DOWN_RETRYABLE)
+#define SL_LINK_DOWN_CAUSE_UNSUPPORTED_SPEED_MAP (     \
+		SL_LINK_DOWN_CAUSE_UNSUPPORTED_SPEED | \
+		SL_LINK_DOWN_ORIGIN_LINK_UP          | \
+		SL_LINK_DOWN_RETRYABLE)
+#define SL_LINK_DOWN_CAUSE_DOWNSHIFT_MAP (             \
+		SL_LINK_DOWN_CAUSE_DOWNSHIFT         | \
+		SL_LINK_DOWN_ORIGIN_LINK_UP          | \
+		SL_LINK_DOWN_RETRYABLE)
+#define SL_LINK_DOWN_CAUSE_UPSHIFT_MAP (               \
+		SL_LINK_DOWN_CAUSE_UPSHIFT           | \
+		SL_LINK_DOWN_ORIGIN_LINK_UP          | \
+		SL_LINK_DOWN_RETRYABLE)
+#define SL_LINK_DOWN_CAUSE_AUTONEG_CONFIG_MAP (        \
+		SL_LINK_DOWN_CAUSE_AUTONEG_CONFIG    | \
+		SL_LINK_DOWN_ORIGIN_LINK_UP          | \
+		SL_LINK_DOWN_RETRYABLE)
+#define SL_LINK_DOWN_CAUSE_AUTONEG_CONFIG_MAP (        \
+		SL_LINK_DOWN_CAUSE_AUTONEG_CONFIG    | \
+		SL_LINK_DOWN_ORIGIN_LINK_UP          | \
+		SL_LINK_DOWN_RETRYABLE)
+#define SL_LINK_DOWN_CAUSE_PCS_FAULT_MAP (             \
+		SL_LINK_DOWN_CAUSE_PCS_FAULT         | \
+		SL_LINK_DOWN_ORIGIN_LINK_UP          | \
+		SL_LINK_DOWN_RETRYABLE)
+#define SL_LINK_DOWN_CAUSE_UCW_UP_CHECK_MAP (          \
+		SL_LINK_DOWN_CAUSE_UCW               | \
+		SL_LINK_DOWN_RETRYABLE               | \
+		SL_LINK_DOWN_ORIGIN_LINK_UP)
+#define SL_LINK_DOWN_CAUSE_CCW_UP_CHECK_MAP (          \
+		SL_LINK_DOWN_CAUSE_CCW               | \
+		SL_LINK_DOWN_RETRYABLE               | \
+		SL_LINK_DOWN_ORIGIN_LINK_UP)
+#define SL_LINK_DOWN_CAUSE_TX_LOL_UP_MAP (             \
+		SL_LINK_DOWN_CAUSE_TX_LOL            | \
+		SL_LINK_DOWN_RETRYABLE               | \
+		SL_LINK_DOWN_ORIGIN_LINK_UP)
+#define SL_LINK_DOWN_CAUSE_RX_LOL_UP_MAP (             \
+		SL_LINK_DOWN_CAUSE_RX_LOL            | \
+		SL_LINK_DOWN_RETRYABLE               | \
+		SL_LINK_DOWN_ORIGIN_LINK_UP)
+#define SL_LINK_DOWN_CAUSE_TX_LOS_UP_MAP (             \
+		SL_LINK_DOWN_CAUSE_TX_LOS            | \
+		SL_LINK_DOWN_RETRYABLE               | \
+		SL_LINK_DOWN_ORIGIN_LINK_UP)
+#define SL_LINK_DOWN_CAUSE_RX_LOS_UP_MAP (             \
+		SL_LINK_DOWN_CAUSE_RX_LOS            | \
+		SL_LINK_DOWN_RETRYABLE               | \
+		SL_LINK_DOWN_ORIGIN_LINK_UP)
+#define SL_LINK_DOWN_CAUSE_LF_MAP (                    \
+		SL_LINK_DOWN_CAUSE_LF                | \
+		SL_LINK_DOWN_RETRYABLE               | \
+		SL_LINK_DOWN_ORIGIN_ASYNC)
+#define SL_LINK_DOWN_CAUSE_RF_MAP (                    \
+		SL_LINK_DOWN_CAUSE_RF                | \
+		SL_LINK_DOWN_RETRYABLE               | \
+		SL_LINK_DOWN_ORIGIN_ASYNC)
+#define SL_LINK_DOWN_CAUSE_DOWN_MAP (                  \
+		SL_LINK_DOWN_CAUSE_DOWN              | \
+		SL_LINK_DOWN_RETRYABLE               | \
+		SL_LINK_DOWN_ORIGIN_ASYNC)
+#define SL_LINK_DOWN_CAUSE_LLR_REPLAY_MAX_MAP (        \
+		SL_LINK_DOWN_CAUSE_LLR_REPLAY_MAX    | \
+		SL_LINK_DOWN_RETRYABLE               | \
+		SL_LINK_DOWN_ORIGIN_ASYNC)
+#define SL_LINK_DOWN_CAUSE_CANCELED_MAP (              \
+		SL_LINK_DOWN_CAUSE_CANCELED          | \
+		SL_LINK_DOWN_ORIGIN_LINK_UP          | \
+		SL_LINK_DOWN_RETRYABLE)
+#define SL_LINK_DOWN_CAUSE_UP_CANCELED_MAP (           \
+		SL_LINK_DOWN_CAUSE_UP_CANCELED       | \
+		SL_LINK_DOWN_RETRYABLE               | \
+		SL_LINK_DOWN_ORIGIN_LINK_UP)
+#define SL_LINK_DOWN_CAUSE_MEDIA_HOT_LINK_UP_MAP (     \
+		SL_LINK_DOWN_CAUSE_MEDIA_HOT         | \
+		SL_LINK_DOWN_ORIGIN_LINK_UP)
+#define SL_LINK_DOWN_CAUSE_MEDIA_WARM_LINK_UP_MAP (    \
+		SL_LINK_DOWN_CAUSE_MEDIA_WARM        | \
+		SL_LINK_DOWN_ORIGIN_LINK_UP          | \
+		SL_LINK_DOWN_RETRYABLE)
+#define SL_LINK_DOWN_CAUSE_MEDIA_HOT_FAULT_MAP (       \
+		SL_LINK_DOWN_CAUSE_MEDIA_HOT         | \
+		SL_LINK_DOWN_ORIGIN_ASYNC)
+
+#define SL_LINK_DEGRADE_STATE_INVALID   0
+#define SL_LINK_DEGRADE_STATE_ACTIVE    1
+#define SL_LINK_DEGRADE_STATE_INACTIVE  2
+#define SL_LINK_DEGRADE_STATE_FAILED    3
+
+enum sl_core_info_map_bits {
+	/* Media */
+	SL_CORE_INFO_MAP_MEDIA_CHECK,        /* link up process is checking media */
+	SL_CORE_INFO_MAP_MEDIA_OK,           /* link up media check completed successfully */
+
+	/* SerDes */
+	SL_CORE_INFO_MAP_SERDES_START,       /* SerDes is starting */
+	SL_CORE_INFO_MAP_SERDES_CHECK,       /* SerDes is being checked */
+	SL_CORE_INFO_MAP_SERDES_OK,          /* SerDes check is complete */
+	SL_CORE_INFO_MAP_SERDES_LOOPBACK_ON, /* SerDes loopback is ON */
+
+	/* PCS */
+	SL_CORE_INFO_MAP_PCS_LOCAL_FAULT,    /* link is going down from a local fault interrupt */
+	SL_CORE_INFO_MAP_PCS_REMOTE_FAULT,   /* link is going down from a remote fault interrupt */
+	SL_CORE_INFO_MAP_PCS_LINK_DOWN,      /* link is going down from a link down interrupt */
+	SL_CORE_INFO_MAP_PCS_CHECK,          /* PCS is being checked */
+	SL_CORE_INFO_MAP_PCS_OK,             /* PCS check is complete */
+
+	/* Link Quality */
+	SL_CORE_INFO_MAP_FEC_CHECK,          /* link up process is checking FEC */
+	SL_CORE_INFO_MAP_FEC_OK,             /* link up FEC check completed successfully */
+	SL_CORE_INFO_MAP_LINK_DEGRADED,      /* link degradation process started */
+
+	/* Link Forward Progress */
+	SL_CORE_INFO_MAP_LINK_DOWN,          /* link has been commanded down */
+	SL_CORE_INFO_MAP_LINK_UP_CANCEL,     /* link up process has been canceled */
+	SL_CORE_INFO_MAP_LINK_UP_TIMEOUT,    /* link up process has timed out */
+	SL_CORE_INFO_MAP_LINK_UP_FAIL,       /* link up process has failed */
+	SL_CORE_INFO_MAP_LINK_UP,            /* link up process completed successfully */
+
+	/* MAC */
+	SL_CORE_INFO_MAP_MAC_RX_CONFIG,      /* MAC RX configuration is in progress */
+	SL_CORE_INFO_MAP_MAC_TX_CONFIG,      /* MAC TX configuration is in progress */
+	SL_CORE_INFO_MAP_MAC_RX,             /* MAC RX is operational */
+	SL_CORE_INFO_MAP_MAC_TX,             /* MAC TX is operational */
+
+	/* Autoneg */
+	SL_CORE_INFO_MAP_AN_BASE_PAGE,       /* base page of autonegotiation is being sent */
+	SL_CORE_INFO_MAP_AN_NEXT_PAGE,       /* next page of autonegotiation is being sent */
+	SL_CORE_INFO_MAP_AN_ERROR,           /* autonegotiation error */
+	SL_CORE_INFO_MAP_AN_DONE,            /* autonegotiation completed successfully */
+
+	/* LLR */
+	SL_CORE_INFO_MAP_LLR_CONFIG,         /* LLR is being configured */
+	SL_CORE_INFO_MAP_LLR_SETTING_UP,     /* LLR is setting up */
+	SL_CORE_INFO_MAP_LLR_SETUP,          /* LLR setup completed successfully */
+	SL_CORE_INFO_MAP_LLR_SETUP_TIMEOUT,  /* LLR setup has timed out */
+	SL_CORE_INFO_MAP_LLR_STARTING,       /* LLR is starting */
+	SL_CORE_INFO_MAP_LLR_RUNNING,        /* LLR is running */
+	SL_CORE_INFO_MAP_LLR_START_TIMEOUT,  /* LLR start process timed out */
+	SL_CORE_INFO_MAP_LLR_MAX_STARVATION, /* LLR Max Starvation work started */
+	SL_CORE_INFO_MAP_LLR_STARVED,        /* LLR starved work started */
+	SL_CORE_INFO_MAP_LLR_REPLAY_MAX,     /* LLR replay at max */
+
+	/* fault */
+	SL_CORE_INFO_MAP_HIGH_SER,           /* High Symbol Error ratio work started */
+
+	SL_CORE_INFO_MAP_NUM_BITS            /* must be last */
+};
+
+struct sl_core_link_up_info {
+	u32 state;
+	u64 cause_map;
+	u64 info_map;
+	u32 speed;
+	u32 fec_mode;
+	u32 fec_type;
+};
+
+typedef int (*sl_core_link_up_callback_t)(void *tag, struct sl_core_link_up_info *core_link_up_info);
+typedef int (*sl_core_link_down_callback_t)(void *tag, u32 state, u64 cause_map, u64 info_map);
+typedef int (*sl_core_link_fault_start_callback_t)(u8 ldev_num, u8 lgrp_num, u8 link_num);
+typedef int (*sl_core_link_fault_callback_t)(void *tag, u32 state, u64 cause_map, u64 info_map);
+
+#define SL_CORE_LINK_CONFIG_MAGIC 0x736c4C43
+struct sl_core_link_config {
+	u32                                 magic;
+
+	u32                                 link_up_timeout_ms;
+	sl_core_link_fault_start_callback_t fault_start_callback;
+	sl_core_link_fault_callback_t       fault_callback;
+
+	s32                                 fec_up_settle_wait_ms;
+	s32                                 fec_up_check_wait_ms;
+	s32                                 fec_up_ucw_limit;
+	s32                                 fec_up_ccw_limit;
+
+	u32                                 pml_rec_timeout_ms;
+	u32                                 pml_rec_rate_limit_max_time_ms;     /* Max Recovery time per window */
+	u32                                 pml_rec_rate_limit_window_size_ms;  /* Rate Limiter window */
+
+	u32                                 pause_map;
+	u32                                 hpe_map;
+
+	u32                                 flags;
+};
+
+struct sl_core_link_policy {
+	u32 options;
+};
+
+struct sl_core_serdes_settings {
+	u16 osr;
+	u16 encoding;
+	u16 clocking;
+	u16 width;
+	u16 dfe;
+	u16 scramble_dis;
+	u16 tx_pll_bw;
+};
+
+struct sl_core_link_fecl_kobj {
+	struct sl_core_link *core_link;
+	u8                   lane_num;
+	struct kobject       kobj;
+};
+
+#define PML_REC_DOWN_CAUSE_INVALID       0
+#define PML_REC_DOWN_CAUSE_LINK_DOWN     1
+#define PML_REC_DOWN_CAUSE_LOCAL_FAULT   2
+#define PML_REC_DOWN_CAUSE_REMOTE_FAULT  3
+
+#define SL_CORE_LINK_MAGIC 0x736c4C4E
+
+enum sl_core_link_state {
+	SL_CORE_LINK_STATE_INVALID = 0,
+	SL_CORE_LINK_STATE_UNCONFIGURED,
+	SL_CORE_LINK_STATE_CONFIGURING,
+	SL_CORE_LINK_STATE_CONFIGURED,
+	SL_CORE_LINK_STATE_DOWN,
+	SL_CORE_LINK_STATE_AN,
+	SL_CORE_LINK_STATE_GOING_UP,
+	SL_CORE_LINK_STATE_UP,
+	SL_CORE_LINK_STATE_CANCELING,
+	SL_CORE_LINK_STATE_GOING_DOWN,
+	SL_CORE_LINK_STATE_TIMEOUT,
+};
+
+struct sl_core_link {
+	u32                              magic;
+	u8                               num;
+
+	spinlock_t                       data_lock;
+	struct sl_core_lgrp             *core_lgrp;
+	struct sl_core_link_config       config;
+	struct sl_core_link_policy       policy;
+	u32                              degrade_state;
+	struct sl_link_degrade_info      degrade_info;
+	struct kobject                   degrade_kobj;
+	u64                              info_map;
+
+	/* The core links table holds the initial reference until the link is deleted */
+	struct kref                      ref;
+	bool                             is_deleting;
+
+	spinlock_t                       irq_data_lock;
+
+	struct {
+		spinlock_t                            data_lock;
+		enum sl_core_link_state                state;
+		bool                                  is_last_down_new;
+		u8                                    last_down_entry_num;
+		u64                                   last_down_cause_map[SL_CTRL_LAST_DOWN_NUM_ENTRIES];
+		time64_t                              last_down_time[SL_CTRL_LAST_DOWN_NUM_ENTRIES];
+		bool                                  is_last_up_fail_new;
+		u8                                    last_up_fail_entry_num;
+		u64                                   last_up_fail_cause_map[SL_CTRL_LAST_UP_FAIL_NUM_ENTRIES];
+		time64_t                              last_up_fail_time[SL_CTRL_LAST_UP_FAIL_NUM_ENTRIES];
+		struct {
+			void                         *up;
+			void                         *down;
+		} tags;
+		struct {
+			sl_core_link_up_callback_t    up;
+			sl_core_link_down_callback_t  down;
+		} callbacks;
+		struct {
+			u32                           up;
+		} flags;
+		bool                                  is_ccw_warn_limit_crossed;
+		time64_t                              last_ccw_warn_limit_crossed_time;
+		bool                                  is_ucw_warn_limit_crossed;
+		time64_t                              last_ucw_warn_limit_crossed_time;
+	} link;
+
+	struct kobject pml_rec_kobj;
+	struct {
+		struct sl_link_pml_rec_info  pml_rec_info;
+		atomic_t                     pml_rec_running;
+		atomic_t                     pml_rec_rate_limit_exceeded;
+		atomic_t                     pml_rec_down_cause_remote_fault;
+		ktime_t                      pml_rec_window_start_time;
+		ktime_t                      pml_rec_attempt_start_time;
+		ktime_t                      pml_rec_attempts_total_time;
+		ktime_t                      pml_rec_poll_start_time;
+		u8                           pml_rec_last_down_cause;
+	} pml_rec;
+
+	struct {
+		spinlock_t                            data_lock;
+		enum sl_core_link_state link_state;
+		void                                 *tag;
+		struct {
+			sl_core_link_an_callback_t    lp_caps_get;
+		} callbacks;
+		struct sl_link_caps                   my_caps;
+		struct sl_link_caps                   lp_caps;
+		u32                                   lp_caps_state;
+		enum sl_core_hw_an_state              state;
+		u32                                   fail_cause;
+		time64_t                              fail_time;
+		u8                                    page_num;
+		u8                                    tx_count;
+		u64                                   tx_pages[SL_CORE_LINK_AN_MAX_PAGES];
+		u8                                    rx_count;
+		u64                                   rx_pages[SL_CORE_LINK_AN_MAX_PAGES];
+		bool                                  toggle;
+		u32                                   done_work_num;
+		struct sl_link_caps                   test_caps;
+		bool                                  use_test_caps;
+		u16                                   restart_sleep_ms;
+		atomic_t                              retry_count;
+	} an;
+
+	struct {
+		struct {
+			u32     speed;
+			u8      pcs_mode;
+			u8      tx_cdc_ready_level;
+			u8      tx_en_pk_bw_limiter;
+			u8      tx_gearbox_credits;
+			u8      rx_active_lanes;
+			u16     rx_am_lock_lanes;
+			u8      rs_mode;
+			u16     clock_period;
+			u8      mac_tx_credits;
+			u8      underrun_clr;
+			u8      cw_gap;
+		} settings;
+	} pcs;
+
+	struct {
+		u8                               lane_map;
+		struct sl_media_serdes_settings  media_serdes_settings;
+		struct sl_core_serdes_settings   core_serdes_settings;
+		bool                             use_test_settings;
+		spinlock_t                       data_lock;
+		u8                               serdes_state;
+		struct {
+			/* media settings */
+			s16 pre1;
+			s16 pre2;
+			s16 pre3;
+			s16 cursor;
+			s16 post1;
+			s16 post2;
+			u16 media;
+			/* core settings */
+			u16 osr;
+			u16 encoding;
+			u16 clocking;
+			u16 width;
+			u16 dfe;
+			u16 scramble_dis;
+			/* options */
+			u32 options;
+		} test_settings;
+	} serdes;
+
+	struct {
+		struct kobject                up_check_kobj;
+		struct kobject                current_kobj;
+		struct kobject                current_lane_kobj;
+		struct sl_core_link_fecl_kobj current_fecl_kobjs[SL_MAX_LANES];
+		struct kobject                current_tail_kobj;
+
+		struct sl_core_link_fec_cw_cntrs test_cntrs;
+		struct sl_core_link_fec_cw_cntrs mock_cntr;
+		spinlock_t                       test_lock;
+		struct {
+			u32     mode;
+			u32     type;
+			u32     up_settle_wait_ms;
+			u32     up_check_wait_ms;
+			s32     up_ucw_limit;
+			s32     up_ccw_limit;
+		} settings;
+		struct {
+			struct sl_core_link_fec_cw_cntrs   cw;
+			struct sl_core_link_fec_lane_cntrs lane;
+			struct sl_core_link_fec_tail_cntrs tail;
+		} up_cntrs_cache;
+		struct {
+			struct sl_core_link_fec_cw_cntrs   cw;
+			struct sl_core_link_fec_lane_cntrs lane;
+			struct sl_core_link_fec_tail_cntrs tail;
+		} down_cntrs_cache;
+	} fec;
+
+	struct work_struct                            work[SL_CORE_WORK_LINK_COUNT];
+	struct sl_core_timer_link_info                timers[SL_CORE_TIMER_LINK_COUNT];
+	struct sl_core_hw_intr_info                   intrs[SL_CORE_HW_INTR_COUNT];
+};
+
+int		     sl_core_link_new(u8 ldev_num, u8 lgrp_num, u8 link_num);
+int		     sl_core_link_del(u8 ldev_num, u8 lgrp_num, u8 link_num);
+struct sl_core_link *sl_core_link_get(u8 ldev_num, u8 lgrp_num, u8 link_num);
+void                sl_core_link_put(struct sl_core_link *core_link);
+DEFINE_FREE(sl_core_link_put, struct sl_core_link *, sl_core_link_put(_T))
+struct sl_core_link *sl_core_link_get_pinned(u8 ldev_num, u8 lgrp_num, u8 link_num);
+void		     sl_core_link_put_pinned(struct sl_core_link *core_link);
+
+int sl_core_link_up(u8 ldev_num, u8 lgrp_num, u8 link_num,
+		    sl_core_link_up_callback_t callback, void *tag);
+int sl_core_link_up_fail(struct sl_core_link *core_link);
+int sl_core_link_cancel(u8 ldev_num, u8 lgrp_num, u8 link_num,
+			sl_core_link_down_callback_t callback, void *tag);
+int sl_core_link_down(u8 ldev_num, u8 lgrp_num, u8 link_num,
+		      sl_core_link_down_callback_t callback, void *tag, u64 down_cause_map);
+int sl_core_link_down_request(u8 ldev_num, u8 lgrp_num, u8 link_num,
+			      sl_core_link_down_callback_t callback, void *tag,
+			      u64 down_cause_map, bool *accepted);
+int sl_core_link_reset(u8 ldev_num, u8 lgrp_num, u8 link_num);
+
+int sl_core_link_state_get(u8 ldev_num, u8 lgrp_num, u8 link_num,
+			   enum sl_core_link_state *link_state);
+u64 sl_core_link_info_map_get(u8 ldev_num, u8 lgrp_num, u8 link_num);
+int sl_core_info_map_get(u8 ldev_num, u8 lgrp_num, u8 link_num, u64 *info_map);
+int sl_core_link_config_set(u8 ldev_num, u8 lgrp_num, u8 link_num, struct sl_core_link_config *link_config);
+int sl_core_link_policy_set(u8 ldev_num, u8 lgrp_num, u8 link_num, struct sl_core_link_policy *link_policy);
+int sl_core_link_caps_get(u8 ldev_num, u8 lgrp_num, u8 link_num, struct sl_link_caps *link_caps);
+
+bool sl_core_link_config_is_enable_ald_set(struct sl_core_link *core_link);
+bool sl_core_link_is_degrade_state_active(struct sl_core_link *core_link);
+
+bool        sl_core_link_config_is_enable_pml_recovery_set(struct sl_core_link *core_link);
+bool        sl_core_link_is_pml_recovery_running(struct sl_core_link *core_link);
+const char *sl_core_link_pml_rec_down_cause_str(u8 down_cause);
+
+int  sl_core_link_is_canceled_or_timed_out(struct sl_core_link *core_link, bool *is_canceled_or_timed_out);
+
+int  sl_core_link_speed_get(u8 ldev_num, u8 lgrp_num, u8 link_num, u32 *link_speed);
+int  sl_core_link_clocking_get(struct sl_core_link *core_link, u16 *clocking);
+
+int  sl_core_link_last_down_cause_map_info_get(u8 ldev_num, u8 lgrp_num, u8 link_num, u8 entry_num,
+					       u64 *down_cause_map, time64_t *down_time);
+int  sl_core_link_last_up_fail_cause_map_info_get(u8 ldev_num, u8 lgrp_num, u8 link_num, u8 entry_num,
+						  u64 *up_fail_cause_map, time64_t *up_fail_time);
+void sl_core_link_last_up_fail_cause_map_set(u8 ldev_num, u8 lgrp_num, u8 link_num, u64 up_fail_cause_map);
+
+int  sl_core_link_ucw_warn_limit_crossed_get(u8 ldev_num, u8 lgrp_num, u8 link_num, bool *is_limit_crossed,
+					     time64_t *limit_crossed_time);
+void sl_core_link_ucw_warn_limit_crossed_set(u8 ldev_num, u8 lgrp_num, u8 link_num, bool is_limit_crossed);
+int  sl_core_link_ccw_warn_limit_crossed_get(u8 ldev_num, u8 lgrp_num, u8 link_num, bool *is_limit_crossed,
+					     time64_t *limit_crossed_time);
+void sl_core_link_ccw_warn_limit_crossed_set(u8 ldev_num, u8 lgrp_num, u8 link_num, bool is_limit_crossed);
+
+bool sl_core_link_policy_is_keep_serdes_up_set(struct sl_core_link *core_link);
+bool sl_core_link_policy_is_use_unsupported_cable_set(struct sl_core_link *core_link);
+bool sl_core_link_policy_is_use_supported_ss200_cable_set(struct sl_core_link *core_link);
+bool sl_core_link_policy_is_ignore_media_errors_set(struct sl_core_link *core_link);
+
+struct sl_core_link_up_info *sl_core_link_up_info_get(struct sl_core_link *core_link,
+						      struct sl_core_link_up_info *link_up_info);
+
+#endif /* _SL_CORE_LINK_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/sl_core_link_an.h b/drivers/net/ethernet/hpe/sl/core/sl_core_link_an.h
new file mode 100644
index 000000000000..a12903801b56
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/sl_core_link_an.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_LINK_AN_H_
+#define _SL_CORE_LINK_AN_H_
+
+struct sl_link_caps;
+
+#define SL_CORE_LINK_LP_CAPS_RUNNING     BIT(0)
+#define SL_CORE_LINK_LP_CAPS_DATA        BIT(1)
+#define SL_CORE_LINK_LP_CAPS_TIMEOUT     BIT(2)
+#define SL_CORE_LINK_LP_CAPS_ERROR       BIT(3)
+#define SL_CORE_LINK_LP_CAPS_NOT_RUNNING BIT(4)
+
+#define SL_CORE_LINK_AN_MAX_PAGES 10
+
+#define SL_CORE_LINK_AN_MAGIC 0x736c414E
+
+typedef int (*sl_core_link_an_callback_t)(void *tag, struct sl_link_caps *caps, u32 result);
+
+int  sl_core_link_an_lp_caps_get(u8 ldev_num, u8 lgrp_num, u8 link_num,
+				 sl_core_link_an_callback_t callback, void *tag,
+				 struct sl_link_caps *caps, u32 timeout_ms, u32 flags);
+int  sl_core_link_an_lp_caps_stop(u8 ldev_num, u8 lgrp_num, u8 link_num);
+
+u32  sl_core_link_an_lp_caps_state_get(u8 ldev_num, u8 lgrp_num, u8 link_num);
+int  sl_core_link_an_fail_cause_get(u8 ldev_num, u8 lgrp_num, u8 link_num, u32 *fail_cause, time64_t *fail_time);
+u32  sl_core_link_an_retry_count_get(u8 ldev_num, u8 lgrp_num, u8 link_num);
+const char *sl_core_link_an_fail_cause_str(u32 fail_cause);
+
+#endif /* _SL_CORE_LINK_AN_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/sl_core_link_fec.h b/drivers/net/ethernet/hpe/sl/core/sl_core_link_fec.h
new file mode 100644
index 000000000000..bc65e9bec3df
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/sl_core_link_fec.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_LINK_FEC_H_
+#define _SL_CORE_LINK_FEC_H_
+
+#include <linux/hpe/sl/sl_fec.h>
+
+struct sl_core_link;
+
+#define SL_CORE_LINK_FEC_NUM_LANES    SL_CTRL_NUM_FEC_LANES
+#define SL_CORE_LINK_FEC_NUM_CCW_BINS SL_CTRL_NUM_CCW_BINS
+
+struct sl_core_link_fec_cw_cntrs {
+	u64 ccw;
+	u64 ucw;
+	u64 gcw;
+};
+
+struct sl_core_link_fec_lane_cntrs {
+	u64 lanes[SL_CORE_LINK_FEC_NUM_LANES];
+};
+
+struct sl_core_link_fec_tail_cntrs {
+	u64 ccw_bins[SL_CORE_LINK_FEC_NUM_CCW_BINS];
+};
+
+struct sl_core_link_fec_data_cntrs {
+	struct sl_core_link_fec_cw_cntrs cw_cntrs;
+	struct sl_core_link_fec_lane_cntrs lane_cntrs;
+	struct sl_core_link_fec_tail_cntrs tail_cntrs;
+};
+
+int sl_core_link_fec_ccw_get(struct sl_core_link *core_link, u64 *ccw);
+int sl_core_link_fec_ucw_get(struct sl_core_link *core_link, u64 *ucw);
+int sl_core_link_fec_gcw_get(struct sl_core_link *core_link, u64 *gcw);
+int sl_core_link_fec_lane_cntr_get(struct sl_core_link *core_link, u8 lane_num, u64 *lane_cntr);
+int sl_core_link_fec_tail_cntr_get(struct sl_core_link *core_link, u8 tail_cntr_num, u64 *tail_cntr);
+
+int sl_core_link_fec_data_get(struct sl_core_link *core_link,
+			      struct sl_core_link_fec_cw_cntrs *cw_cntrs,
+			      struct sl_core_link_fec_lane_cntrs *lane_cntrs,
+			      struct sl_core_link_fec_tail_cntrs *tail_cntrs);
+
+#endif /* _SL_CORE_LINK_FEC_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/sl_core_llr.h b/drivers/net/ethernet/hpe/sl/core/sl_core_llr.h
new file mode 100644
index 000000000000..9ab4bd6a72f7
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/sl_core_llr.h
@@ -0,0 +1,138 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_LLR_H_
+#define _SL_CORE_LLR_H_
+
+#include <linux/spinlock.h>
+#include <linux/completion.h>
+
+#include <linux/hpe/sl/sl_llr.h>
+
+#include "sl_core_lgrp.h"
+#include "base/sl_core_timer_llr.h"
+#include "base/sl_core_work_llr.h"
+#include "hw/sl_core_hw_intr_llr.h"
+
+struct sl_llr_data;
+struct sl_llr_config;
+
+struct work_struct;
+
+#define SL_CORE_LLR_MAX_LOOP_TIME_COUNT 10
+
+#define SL_CORE_LLR_DATA_MAGIC 0x736c4C52
+
+enum sl_core_llr_state {
+	SL_CORE_LLR_STATE_INVALID         = 0,     /* Invalid State */
+	SL_CORE_LLR_STATE_NEW,                     /* next: CONFIGURED                */
+	SL_CORE_LLR_STATE_CONFIGURED,              /* next: SETTING_UP                */
+	SL_CORE_LLR_STATE_SETTING_UP,              /* -- BUSY --                      */
+	SL_CORE_LLR_STATE_SETUP_TIMEOUT,           /* next: CONFIGURED                */
+	SL_CORE_LLR_STATE_SETUP_CANCELING,         /* next: CONFIGURED                */
+	SL_CORE_LLR_STATE_SETUP_STOPPING,          /* next: CONFIGURED                */
+	SL_CORE_LLR_STATE_SETUP,                   /* next: STARTING | SETUP_STOPPING */
+	SL_CORE_LLR_STATE_STARTING,                /* -- BUSY --                      */
+	SL_CORE_LLR_STATE_START_TIMEOUT,           /* next: SETUP                     */
+	SL_CORE_LLR_STATE_START_CANCELING,         /* next: SETUP                     */
+	SL_CORE_LLR_STATE_RUNNING,                 /* next: STOPPING                  */
+	SL_CORE_LLR_STATE_STOPPING,                /* next: SETUP                     */
+};
+
+#define SL_LLR_FAIL_CAUSE_NONE                   0
+#define SL_LLR_FAIL_CAUSE_SETUP_CONFIG           BIT(0) /* llr setup config invalid             */
+#define SL_LLR_FAIL_CAUSE_SETUP_INTR_ENABLE      BIT(1) /* llr setup interrupt enable failed    */
+#define SL_LLR_FAIL_CAUSE_SETUP_TIMEOUT          BIT(2) /* llr setup timeout                    */
+#define SL_LLR_FAIL_CAUSE_START_INTR_ENABLE      BIT(3) /* llr start interrupt enable failed    */
+#define SL_LLR_FAIL_CAUSE_START_TIMEOUT          BIT(4) /* llr start timeout                    */
+#define SL_LLR_FAIL_CAUSE_COMMAND                BIT(5) /* running llr was commanded to stop    */
+#define SL_LLR_FAIL_CAUSE_CANCELED               BIT(6) /* llr operation was canceled by client */
+
+#define SL_LLR_FAIL_CAUSE_STR_SIZE 128
+
+typedef void (*sl_core_llr_setup_callback_t)(void *tag,
+					    enum sl_core_llr_state llr_state,
+					    u64 info_map, struct sl_llr_data llr_data);
+typedef void (*sl_core_llr_start_callback_t)(void *tag,
+					    enum sl_core_llr_state llr_state,
+					    u64 info_map);
+
+#define SL_CORE_LLR_MAGIC 0x756c5C4E
+struct sl_core_llr {
+	u32                              magic;
+	u8                               num;
+
+	struct sl_core_lgrp             *core_lgrp;
+
+	struct kobject                             kobj;
+	spinlock_t                                 data_lock;
+	u32                                        last_fail_cause;
+	time64_t                                   last_fail_time;
+	bool                                       is_canceled;
+	enum sl_core_llr_state			state;
+	u64                                        info_map;
+	void                                      *tag;
+	u64                                        loop_time[SL_CORE_LLR_MAX_LOOP_TIME_COUNT];
+	struct kobject                             loop_time_kobj;
+	bool                                       is_data_valid;
+	struct sl_llr_data                         data;
+	struct {
+		sl_core_llr_setup_callback_t       setup;
+		sl_core_llr_start_callback_t       start;
+	} callbacks;
+	struct {
+		u32                                setup;
+		u32                                start;
+	} flags;
+	struct sl_llr_policy                       policy;
+	struct kobject                             policy_kobj;
+	struct {
+		u8      size;
+		u8      lossless_when_off;
+		u8      link_down_behavior;
+		u8      filter_ctl_frames;
+		u8      ctl_frame_smac;
+		u16     ctl_frame_ethertype;
+		u8      retry_threshold;
+		u8      allow_re_init;
+		u8      replay_ct_max;
+		u16     replay_timer_max;
+		u16     max_cap_data;
+		u16     max_cap_seq;
+		u8      bytes_per_ns;
+	} settings;
+
+	struct work_struct                         work[SL_CORE_WORK_LLR_COUNT];
+	struct sl_core_timer_llr_info              timers[SL_CORE_TIMER_LLR_COUNT];
+	struct sl_core_hw_intr_llr_info            intrs[SL_CORE_HW_INTR_LLR_FLGS_COUNT];
+	struct completion                          stop_complete;
+};
+
+int                 sl_core_llr_new(u8 ldev_num, u8 lgrp_num, u8 llr_num);
+void                sl_core_llr_del(u8 ldev_num, u8 lgrp_num, u8 llr_num);
+struct sl_core_llr *sl_core_llr_get(u8 ldev_num, u8 lgrp_num, u8 llr_num);
+
+int  sl_core_llr_config_set(u8 ldev_num, u8 lgrp_num, u8 llr_num,
+			    struct sl_llr_config *llr_config);
+int  sl_core_llr_policy_set(u8 ldev_num, u8 lgrp_num, u8 llr_num,
+			    struct sl_llr_policy *llr_policy);
+int  sl_core_llr_policy_get(u8 ldev_num, u8 lgrp_num, u8 llr_num,
+			    struct sl_llr_policy *llr_policy);
+int  sl_core_llr_setup(u8 ldev_num, u8 lgrp_num, u8 llr_num,
+		       sl_core_llr_setup_callback_t callback, void *tag, u32 flags);
+int  sl_core_llr_start(u8 ldev_num, u8 lgrp_num, u8 llr_num,
+		       sl_core_llr_start_callback_t callback, void *tag, u32 flags);
+int  sl_core_llr_stop(u8 ldev_num, u8 lgrp_num, u8 llr_num);
+
+int  sl_core_llr_state_get(u8 ldev_num, u8 lgrp_num, u8 llr_num,
+			   enum sl_core_llr_state *llr_state);
+
+bool sl_core_llr_setup_should_stop(struct sl_core_llr *core_llr);
+bool sl_core_llr_start_should_stop(struct sl_core_llr *core_llr);
+bool sl_core_llr_should_stop(struct sl_core_llr *core_llr);
+
+void sl_core_llr_last_fail_cause_set(u8 ldev_num, u8 lgrp_num, u8 llr_num, u32 llr_fail_cause);
+
+const char *sl_core_llr_fail_cause_str(u32 llr_fail_cause);
+
+#endif /* _SL_CORE_LLR_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/sl_core_mac.h b/drivers/net/ethernet/hpe/sl/core/sl_core_mac.h
new file mode 100644
index 000000000000..0e347bde8531
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/sl_core_mac.h
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_MAC_H_
+#define _SL_CORE_MAC_H_
+
+#include <linux/spinlock.h>
+
+struct sl_core_lgrp;
+
+enum sl_core_mac_state {
+	SL_CORE_MAC_STATE_INVALID = 0,
+	SL_CORE_MAC_STATE_OFF,
+	SL_CORE_MAC_STATE_ON,
+};
+
+#define SL_CORE_MAC_MAGIC 0x736d4C5E
+struct sl_core_mac {
+	u32                              magic;
+	u8                               num;
+
+	struct sl_core_lgrp             *core_lgrp;
+
+	spinlock_t                       data_lock;
+	u64                              info_map;
+	int                              tx_last_start_result;
+	int                              rx_last_start_result;
+
+	struct {
+		u8      tx_ifg_adj;
+		u8      tx_ifg_mode;
+		u8      tx_pad_idle_thresh;
+		u8      tx_idle_delay;
+		u8      tx_priority_thresh;
+		u8      tx_cdt_thresh_2;
+		u8      tx_cdt_thresh;
+		u8      tx_cdt_init_val;
+		u8      tx_pcs_credits;
+		u8      tx_short_preamble;
+		u8      rx_flit_packing_cnt;
+		u8      rx_short_preamble;
+		u8      llr_if_credits;
+	} settings;
+};
+
+int                 sl_core_mac_new(u8 ldev_num, u8 lgrp_num, u8 mac_num);
+void                sl_core_mac_del(u8 ldev_num, u8 lgrp_num, u8 mac_num);
+struct sl_core_mac *sl_core_mac_get(u8 ldev_num, u8 lgrp_num, u8 mac_num);
+
+int sl_core_mac_tx_start(u8 ldev_num, u8 lgrp_num, u8 mac_num);
+int sl_core_mac_tx_stop(u8 ldev_num, u8 lgrp_num, u8 mac_num);
+int sl_core_mac_tx_state_get(u8 ldev_num, u8 lgrp_num, u8 mac_num, u32 *state);
+int sl_core_mac_tx_last_start_result_get(u8 ldev_num, u8 lgrp_num, u8 mac_num, int *last_start_result);
+
+int sl_core_mac_rx_start(u8 ldev_num, u8 lgrp_num, u8 mac_num);
+int sl_core_mac_rx_stop(u8 ldev_num, u8 lgrp_num, u8 mac_num);
+int sl_core_mac_rx_state_get(u8 ldev_num, u8 lgrp_num, u8 mac_num, u32 *state);
+int sl_core_mac_rx_last_start_result_get(u8 ldev_num, u8 lgrp_num, u8 mac_num, int *last_start_result);
+
+u64 sl_core_mac_info_map_get(u8 ldev_num, u8 lgrp_num, u8 mac_num);
+
+#endif /* _SL_CORE_MAC_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/core/sl_core_str.h b/drivers/net/ethernet/hpe/sl/core/sl_core_str.h
new file mode 100644
index 000000000000..21da0dd9ccb6
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/sl_core_str.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CORE_STR_H_
+#define _SL_CORE_STR_H_
+
+#include "sl_core_link.h"
+#include "sl_core_llr.h"
+#include "sl_core_mac.h"
+
+int sl_core_info_map_str(u64 info_map, char *info_map_str, unsigned int info_map_str_size);
+
+const char *sl_core_lgrp_dt_jack_part_str(u32 jack_type);
+
+const char *sl_core_link_state_str(enum sl_core_link_state link_state);
+
+const char *sl_core_mac_state_str(enum sl_core_mac_state mac_state);
+
+const char *sl_core_llr_state_str(enum sl_core_llr_state llr_state);
+const char *sl_core_llr_flag_str(unsigned int llr_flag);
+
+const char *sl_core_serdes_lane_state_str(u8 lane_state);
+const char *sl_core_serdes_lane_encoding_str(u16 encoding);
+const char *sl_core_serdes_lane_clocking_str(u16 clocking);
+const char *sl_core_serdes_lane_osr_str(u16 osr);
+const char *sl_core_serdes_lane_width_str(u16 width);
+
+#endif /* _SL_CORE_STR_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/ctrl/base/sl_ctrl_log.h b/drivers/net/ethernet/hpe/sl/ctrl/base/sl_ctrl_log.h
new file mode 100644
index 000000000000..6f3fe03eabe9
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/ctrl/base/sl_ctrl_log.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CTRL_LOG_H_
+#define _SL_CTRL_LOG_H_
+
+#include "sl_log.h"
+
+#define SL_CTRL_LOG_BLOCK           "ctrl"
+
+#define SL_CTRL_MEDIA_LOG_NAME      "media"
+#define SL_CTRL_LDEV_LOG_NAME       "ldev"
+#define SL_CTRL_LGRP_LOG_NAME       "lgrp"
+#define SL_CTRL_LGRP_NOTIF_LOG_NAME "lgrp-ntf"
+#define SL_CTRL_LINK_LOG_NAME       "link"
+#define SL_CTRL_LINK_FEC_LOG_NAME   "link-fec"
+#define SL_CTRL_MAC_LOG_NAME        "mac"
+#define SL_CTRL_LLR_LOG_NAME        "llr"
+#define SL_CTRL_TEST_FEC_LOG_NAME   "test-fec"
+
+#define sl_ctrl_log_dbg(_ptr, _name, _text, ...) \
+	sl_log_dbg((_ptr), SL_CTRL_LOG_BLOCK, (_name), (_text), ##__VA_ARGS__)
+#define sl_ctrl_log_info(_ptr, _name, _text, ...) \
+	sl_log_info((_ptr), SL_CTRL_LOG_BLOCK, (_name), (_text), ##__VA_ARGS__)
+#define sl_ctrl_log_warn(_ptr, _name, _text, ...) \
+	sl_log_warn((_ptr), SL_CTRL_LOG_BLOCK, (_name), (_text), ##__VA_ARGS__)
+#define sl_ctrl_log_warn_trace(_ptr, _name, _text, ...) \
+	sl_log_warn_trace((_ptr), SL_CTRL_LOG_BLOCK, (_name), (_text), ##__VA_ARGS__)
+#define sl_ctrl_log_err(_ptr, _name, _text, ...) \
+	sl_log_err((_ptr), SL_CTRL_LOG_BLOCK, (_name), (_text), ##__VA_ARGS__)
+#define sl_ctrl_log_err_trace(_ptr, _name, _text, ...) \
+	sl_log_err_trace((_ptr), SL_CTRL_LOG_BLOCK, (_name), (_text), ##__VA_ARGS__)
+
+#endif /* _SL_CTRL_LOG_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/ctrl/data/sl_ctrl_data_lgrp.h b/drivers/net/ethernet/hpe/sl/ctrl/data/sl_ctrl_data_lgrp.h
new file mode 100644
index 000000000000..fa3057adefdd
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/ctrl/data/sl_ctrl_data_lgrp.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2025-2026 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CTRL_DATA_LGRP_H_
+#define _SL_CTRL_DATA_LGRP_H_
+
+#include "sl_ctrl_lgrp.h"
+
+int sl_ctrl_data_lgrp_err_trace_enable_set(struct sl_ctrl_lgrp *ctrl_lgrp, bool err_trace_enable);
+int sl_ctrl_data_lgrp_warn_trace_set(struct sl_ctrl_lgrp *ctrl_lgrp, bool err_trace_enable);
+int sl_ctrl_data_lgrp_serdes_lane_io_trace_set(struct sl_ctrl_lgrp *ctrl_lgrp, bool serdes_lane_io_trace);
+
+int sl_ctrl_data_lgrp_mfs_get(struct sl_ctrl_lgrp *ctrl_lgrp, u32 *mfs);
+int sl_ctrl_data_lgrp_furcation_get(struct sl_ctrl_lgrp *ctrl_lgrp, u32 *furcation);
+int sl_ctrl_data_lgrp_fec_mode_get(struct sl_ctrl_lgrp *ctrl_lgrp, u32 *fec_mode);
+int sl_ctrl_data_lgrp_tech_map_get(struct sl_ctrl_lgrp *ctrl_lgrp, u32 *tech_map);
+int sl_ctrl_data_lgrp_fec_map_get(struct sl_ctrl_lgrp *ctrl_lgrp, u32 *fec_map);
+int sl_ctrl_data_lgrp_options_get(struct sl_ctrl_lgrp *ctrl_lgrp, u32 *options);
+
+#endif /* _SL_CTRL_DATA_LGRP_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/ctrl/data/sl_ctrl_data_lgrp_trace.h b/drivers/net/ethernet/hpe/sl/ctrl/data/sl_ctrl_data_lgrp_trace.h
new file mode 100644
index 000000000000..5da1a0d82760
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/ctrl/data/sl_ctrl_data_lgrp_trace.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2025-2026 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CTRL_DATA_LGRP_TRACE_H_
+#define _SL_CTRL_DATA_LGRP_TRACE_H_
+
+#include "sl_ctrl_lgrp.h"
+
+int sl_ctrl_data_lgrp_is_err_trace_enabled(struct sl_ctrl_lgrp *ctrl_lgrp, bool *err_trace_enable);
+int sl_ctrl_data_lgrp_is_warn_trace_enabled(struct sl_ctrl_lgrp *ctrl_lgrp, bool *warn_trace_enable);
+bool sl_ctrl_data_lgrp_is_serdes_lane_io_trace_enabled(struct sl_ctrl_lgrp *ctrl_lgrp);
+
+#endif /* _SL_CTRL_DATA_LGRP_TRACE_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/ctrl/data/sl_ctrl_data_link.h b/drivers/net/ethernet/hpe/sl/ctrl/data/sl_ctrl_data_link.h
new file mode 100644
index 000000000000..fe5a132e6f49
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/ctrl/data/sl_ctrl_data_link.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CTRL_DATA_LINK_H_
+#define _SL_CTRL_DATA_LINK_H_
+
+#include "sl_ctrl_link.h"
+
+int sl_ctrl_data_link_state_get(struct sl_ctrl_link *ctrl_link, u32 *link_state);
+
+int sl_ctrl_data_link_fec_up_settle_wait_ms_get(struct sl_ctrl_link *ctrl_link, u32 *fec_up_settle_wait_ms);
+int sl_ctrl_data_link_fec_up_check_wait_ms_get(struct sl_ctrl_link *ctrl_link, s32 *fec_up_check_wait_ms);
+int sl_ctrl_data_link_fec_up_ucw_limit_get(struct sl_ctrl_link *ctrl_link, s32 *fec_up_ucw_limit);
+int sl_ctrl_data_link_fec_up_ccw_limit_get(struct sl_ctrl_link *ctrl_link, s32 *fec_up_ccw_limit);
+
+int sl_ctrl_data_link_policy_options_get(struct sl_ctrl_link *ctrl_link, u32 *options);
+int sl_ctrl_data_link_policy_fec_mon_period_ms_get(struct sl_ctrl_link *ctrl_link, s32 *mon_period_ms);
+int sl_ctrl_data_link_policy_fec_mon_ucw_warn_limit_get(struct sl_ctrl_link *ctrl_link, s32 *mon_ucw_warn_limit);
+int sl_ctrl_data_link_policy_fec_mon_ucw_down_limit_get(struct sl_ctrl_link *ctrl_link, s32 *mon_ucw_down_limit);
+int sl_ctrl_data_link_policy_fec_mon_ccw_down_limit_get(struct sl_ctrl_link *ctrl_link, s32 *mon_ccw_down_limit);
+int sl_ctrl_data_link_policy_fec_mon_ccw_warn_limit_get(struct sl_ctrl_link *ctrl_link, s32 *mon_ccw_warn_limit);
+
+int sl_ctrl_data_link_fec_mon_period_ms_get(struct sl_ctrl_link *ctrl_link, u32 *fec_mon_period_ms);
+int sl_ctrl_data_link_fec_mon_ucw_down_limit_get(struct sl_ctrl_link *ctrl_link, s32 *fec_mon_ucw_down_limit);
+int sl_ctrl_data_link_fec_mon_ucw_warn_limit_get(struct sl_ctrl_link *ctrl_link, s32 *fec_mon_ucw_warn_limit);
+int sl_ctrl_data_link_fec_mon_ccw_down_limit_get(struct sl_ctrl_link *ctrl_link, s32 *fec_mon_ccw_down_limit);
+int sl_ctrl_data_link_fec_mon_ccw_warn_limit_get(struct sl_ctrl_link *ctrl_link, s32 *fec_mon_ccw_warn_limit);
+
+int sl_ctrl_data_link_fec_down_cache_ucw_cntr_get(struct sl_ctrl_link *ctrl_link, u64 *ucw);
+int sl_ctrl_data_link_fec_down_cache_ccw_cntr_get(struct sl_ctrl_link *ctrl_link, u64 *ccw);
+int sl_ctrl_data_link_fec_down_cache_gcw_cntr_get(struct sl_ctrl_link *ctrl_link, u64 *gcw);
+int sl_ctrl_data_link_fec_down_cache_lane_cntr_get(struct sl_ctrl_link *ctrl_link, u8 lane_num, u64 *lane_cntr);
+int sl_ctrl_data_link_fec_down_cache_tail_cntr_get(struct sl_ctrl_link *ctrl_link, u8 lane_num, u64 *tail_cntr);
+
+int sl_ctrl_data_link_fec_up_cache_ucw_cntr_get(struct sl_ctrl_link *ctrl_link, u64 *ucw);
+int sl_ctrl_data_link_fec_up_cache_ccw_cntr_get(struct sl_ctrl_link *ctrl_link, u64 *ccw);
+int sl_ctrl_data_link_fec_up_cache_gcw_cntr_get(struct sl_ctrl_link *ctrl_link, u64 *gcw);
+int sl_ctrl_data_link_fec_up_cache_lane_cntr_get(struct sl_ctrl_link *ctrl_link, u8 lane_num, u64 *lane_cntr);
+int sl_ctrl_data_link_fec_up_cache_tail_cntr_get(struct sl_ctrl_link *ctrl_link, u8 bin_num, u64 *tail_cntr);
+
+int sl_ctrl_data_link_up_timeout_ms_get(struct sl_ctrl_link *ctrl_link, u32 *link_up_timeout_ms);
+int sl_ctrl_data_link_up_tries_max_get(struct sl_ctrl_link *ctrl_link, u32 *link_up_tries_max);
+
+int sl_ctrl_data_link_config_options_get(struct sl_ctrl_link *ctrl_link, u32 *options);
+int sl_ctrl_data_link_pause_map_get(struct sl_ctrl_link *ctrl_link, u32 *pause_map);
+int sl_ctrl_data_link_hpe_map_get(struct sl_ctrl_link *ctrl_link, u32 *hpe_map);
+
+#endif /* _SL_CTRL_DATA_LINK_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/ctrl/data/sl_ctrl_data_llr.h b/drivers/net/ethernet/hpe/sl/ctrl/data/sl_ctrl_data_llr.h
new file mode 100644
index 000000000000..18d2ce831861
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/ctrl/data/sl_ctrl_data_llr.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CTRL_DATA_LLR_H_
+#define _SL_CTRL_DATA_LLR_H_
+
+#include "sl_ctrl_llr.h"
+
+int sl_ctrl_data_llr_config_mode_get(struct sl_ctrl_llr *ctrl_llr, u32 *mode);
+int sl_ctrl_data_llr_config_setup_timeout_ms_get(struct sl_ctrl_llr *ctrl_llr, u32 *setup_timeout_ms);
+int sl_ctrl_data_llr_config_start_timeout_ms_get(struct sl_ctrl_llr *ctrl_llr, u32 *start_timeout_ms);
+int sl_ctrl_data_llr_config_link_dn_behavior_get(struct sl_ctrl_llr *ctrl_llr, u32 *link_dn_behavior);
+int sl_ctrl_data_llr_config_options_get(struct sl_ctrl_llr *ctrl_llr, u32 *options);
+
+#endif /* _SL_CTRL_DATA_LLR_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_ldev.h b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_ldev.h
new file mode 100644
index 000000000000..44b77cc718ce
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_ldev.h
@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CTRL_LDEV_H_
+#define _SL_CTRL_LDEV_H_
+
+#include <linux/kobject.h>
+#include <linux/workqueue.h>
+#include <linux/completion.h>
+
+#include <linux/hpe/sl/sl_ldev.h>
+#include <linux/hpe/sl/sl_media.h>
+
+#include "data/sl_media_data_cable_db.h"
+
+#define SL_CTRL_LDEV_MAGIC 0x736c6382
+#define SL_CTRL_LDEV_VER   2
+
+enum sl_cable_types {
+	SL_CABLE_TYPE_PEC    = 0,
+	SL_CABLE_TYPE_AOC,
+	SL_CABLE_TYPE_AEC,
+	SL_CABLE_TYPE_POC,
+
+	SL_CABLE_TYPES_NUM
+};
+
+enum sl_cable_vendors {
+	SL_CABLE_VENDOR_TE            = 0,
+	SL_CABLE_VENDOR_HISENSE,
+	SL_CABLE_VENDOR_LEONI,
+	SL_CABLE_VENDOR_FINISAR,
+	SL_CABLE_VENDOR_MOLEX,
+	SL_CABLE_VENDOR_BIZLINK,
+	SL_CABLE_VENDOR_HPE,
+	SL_CABLE_VENDOR_CLOUD_LIGHT,
+	SL_CABLE_VENDOR_MULTILANE,
+	SL_CABLE_VENDOR_AMPHENOL,
+
+	SL_CABLE_VENDORS_NUM
+};
+
+struct sl_ctrl_ldev_cable_hpe_pn_kobj {
+	struct sl_ctrl_ldev *ctrl_ldev;
+	u32                  cable_idx;
+	struct kobject       kobj;
+};
+
+struct sl_ctrl_ldev {
+	u32                       magic;
+	u32                       ver;
+
+	u8                        num;
+
+	struct sl_ldev_attr       attr;
+	struct workqueue_struct  *workq;
+	struct workqueue_struct  *notif_workq;
+	bool                      create_workq;
+	u64                       lgrp_map;
+
+	struct kobject           *parent_kobj;
+	bool                      is_sysfs_ok;
+	struct kobject            sl_info_kobj;
+
+	spinlock_t                data_lock;
+
+	struct kobject            supported_cables_kobj;
+	struct kobject            cable_types_kobj[SL_CABLE_TYPES_NUM];
+	struct kobject            cable_vendors_kobj[SL_CABLE_TYPES_NUM][SL_CABLE_VENDORS_NUM];
+	struct sl_ctrl_ldev_cable_hpe_pn_kobj cable_hpe_pns_kobj[ARRAY_SIZE(cable_db)];
+
+	struct kref               ref_cnt;
+	struct completion         del_complete;
+
+	/* Set once the ctrl lgrps and sysfs are gone, so a retried release skips them. */
+	bool                      children_deleted;
+	bool                      sysfs_deleted;
+};
+
+int                  sl_ctrl_ldev_new(u8 ldev_num,
+				      struct workqueue_struct *workq,
+				      struct sl_ldev_attr *ldev_attr);
+int                  sl_ctrl_ldev_serdes_init(u8 ldev_num);
+int                  sl_ctrl_ldev_del(u8 ldev_num);
+bool                 sl_ctrl_ldev_kref_get_unless_zero(struct sl_ctrl_ldev *ctrl_ldev);
+int                  sl_ctrl_ldev_put(struct sl_ctrl_ldev *ctrl_ldev);
+struct sl_ctrl_ldev *sl_ctrl_ldev_get(u8 ldev_num);
+
+void                 sl_ctrl_ldev_exit(void);
+
+#endif /* _SL_CTRL_LDEV_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_lgrp.h b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_lgrp.h
new file mode 100644
index 000000000000..f96c4735a626
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_lgrp.h
@@ -0,0 +1,93 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023-2026 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CTRL_LGRP_H_
+#define _SL_CTRL_LGRP_H_
+
+#include <linux/workqueue.h>
+#include <linux/spinlock.h>
+#include <linux/kobject.h>
+#include <linux/wait.h>
+#include <linux/completion.h>
+
+#include "sl_asic.h"
+#include "base/sl_ctrl_log.h"
+#include "sl_ctrl_lgrp_notif.h"
+
+struct sl_ctrl_ldev;
+struct sl_lgrp_config;
+struct sl_lgrp_policy;
+
+struct sl_lgrp_serdes_lane_kobj {
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	u8                   asic_lane_num;
+	struct kobject       kobj;
+};
+
+#define SL_CTRL_LGRP_MAGIC 0x5c677270
+#define SL_CTRL_LGRP_VER   3
+struct sl_ctrl_lgrp {
+	u32                              magic;
+	u32                              ver;
+
+	u8                               num;
+
+	struct sl_lgrp_config            config;
+	struct sl_lgrp_policy            policy;
+	spinlock_t                       config_lock;
+
+	char                             log_connect_id[SL_LOG_CONNECT_ID_LEN + 1];
+	spinlock_t                       log_lock;
+
+	struct sl_ctrl_ldev             *ctrl_ldev;
+
+	struct sl_ctrl_lgrp_notif        ctrl_notif;
+	struct work_struct               notif_work;
+
+	struct kobject                  *parent_kobj;
+	struct kobject                   pmi_kobj;
+	struct kobject                   pmi_rd_kobj;
+	struct kobject                   pmi_wr_kobj;
+	struct kobject                   sbus_kobj;
+	struct kobject                   sbus_rd_kobj;
+	struct kobject                   sbus_wr_kobj;
+	struct kobject                   sbus_rst_kobj;
+	struct kobject                   sbus_pmi_kobj;
+	struct kobject                   sbus_pmi_rd_kobj;
+	struct kobject                   sbus_pmi_wr_kobj;
+	struct kobject                   policy_kobj;
+	struct kobject                   config_kobj;
+	struct kobject                   serdes_kobj;
+	struct kobject                   serdes_lane_kobj;
+	struct kobject                   serdes_lane_kobjs[SL_ASIC_MAX_LANES];
+	struct sl_lgrp_serdes_lane_kobj  serdes_lane_state_kobjs[SL_ASIC_MAX_LANES];
+	struct sl_lgrp_serdes_lane_kobj  serdes_lane_swizzle_kobjs[SL_ASIC_MAX_LANES];
+	struct sl_lgrp_serdes_lane_kobj  serdes_lane_settings_kobjs[SL_ASIC_MAX_LANES];
+	struct sl_lgrp_serdes_lane_kobj  serdes_lane_eye_kobjs[SL_ASIC_MAX_LANES];
+	struct sl_lgrp_serdes_lane_kobj  serdes_lane_los_kobjs[SL_ASIC_MAX_LANES];
+	struct sl_lgrp_serdes_lane_kobj  serdes_lane_lol_kobjs[SL_ASIC_MAX_LANES];
+
+	bool                             err_trace_enable;
+	bool                             warn_trace_enable;
+	bool                             serdes_lane_io_trace_enable;
+
+	spinlock_t                       data_lock;
+
+	struct kref                      ref_cnt;
+	struct completion                del_complete;
+	bool                             children_deleted;
+	bool                             sysfs_deleted;
+};
+
+int		     sl_ctrl_lgrp_new(u8 ldev_num, u8 lgrp_num, struct kobject *sysfs_parent);
+int		     sl_ctrl_lgrp_del(u8 ldev_num, u8 lgrp_num);
+bool		     sl_ctrl_lgrp_kref_get_unless_zero(struct sl_ctrl_lgrp *ctrl_lgrp);
+int		     sl_ctrl_lgrp_put(struct sl_ctrl_lgrp *ctrl_lgrp);
+struct sl_ctrl_lgrp *sl_ctrl_lgrp_get(u8 ldev_num, u8 lgrp_num);
+
+int sl_ctrl_lgrp_connect_id_set(u8 ldev_num, u8 lgrp_num, const char *connect_id);
+
+int sl_ctrl_lgrp_config_set(u8 ldev_num, u8 lgrp_num, struct sl_lgrp_config *lgrp_config);
+int sl_ctrl_lgrp_policy_set(u8 ldev_num, u8 lgrp_num, struct sl_lgrp_policy *lgrp_policy);
+
+#endif /* _SL_CTRL_LGRP_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_lgrp_notif.h b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_lgrp_notif.h
new file mode 100644
index 000000000000..3c7ff3c2894a
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_lgrp_notif.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CTRL_LGRP_NOTIF_H_
+#define _SL_CTRL_LGRP_NOTIF_H_
+
+#include <linux/kfifo.h>
+
+#include <linux/hpe/sl/sl_lgrp.h>
+#include <linux/hpe/sl/sl_llr.h>
+
+struct sl_ctrl_lgrp;
+
+struct sl_ctrl_lgrp_notif_reg_entry {
+	sl_lgrp_notif_t  callback;
+	void            *tag;
+	u32              types;
+};
+
+#define SL_CTRL_LGRP_NOTIF_MSG_COUNT  8
+#define SL_CTRL_LGRP_NOTIF_REG_COUNT 16
+
+struct sl_ctrl_lgrp_notif {
+	u8                                  list_state;
+	struct sl_ctrl_lgrp_notif_reg_entry reg_entry[SL_CTRL_LGRP_NOTIF_REG_COUNT];
+	struct kfifo                        fifo;
+	spinlock_t                          lock;
+};
+
+int  sl_ctrl_lgrp_notif_callback_reg(u8 ldev_num, u8 lgrp_num, sl_lgrp_notif_t callback,
+				     u32 types, void *tag);
+int  sl_ctrl_lgrp_notif_callback_unreg(u8 ldev_num, u8 lgrp_num, sl_lgrp_notif_t callback,
+				       u32 types);
+
+int  sl_ctrl_lgrp_notif_enqueue(struct sl_ctrl_lgrp *ctrl_lgrp, u8 link_num,
+				u32 type, union sl_lgrp_notif_info *info, u64 info_map);
+
+void sl_ctrl_lgrp_notif_work(struct work_struct *notif_work);
+
+#endif /* _SL_CTRL_LGRP_NOTIF_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_link.h b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_link.h
new file mode 100644
index 000000000000..a9b5d4993929
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_link.h
@@ -0,0 +1,161 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023,2024,2025,2026 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CTRL_LINK_H_
+#define _SL_CTRL_LINK_H_
+
+#include <linux/spinlock.h>
+#include <linux/timer.h>
+#include <linux/workqueue.h>
+#include <linux/kobject.h>
+#include <linux/cleanup.h>
+#include <linux/mutex.h>
+
+#include <linux/hpe/sl/sl_link.h>
+#include <linux/hpe/sl/sl_lgrp.h>
+
+#include "sl_ctrl_link_fec_priv.h"
+
+#define SL_LINK_DOWN_CAUSE_COMMAND_MAP (      \
+		SL_LINK_DOWN_ORIGIN_ASYNC   | \
+		SL_LINK_DOWN_CAUSE_COMMAND  | \
+		SL_LINK_DOWN_RETRYABLE)
+#define SL_LINK_DOWN_CAUSE_UP_TRIES_MAP (     \
+		SL_LINK_DOWN_CAUSE_UP_TRIES | \
+		SL_LINK_DOWN_ORIGIN_LINK_UP | \
+		SL_LINK_DOWN_RETRYABLE)
+#define SL_LINK_DOWN_CAUSE_UCW_MAP (          \
+		SL_LINK_DOWN_CAUSE_UCW      | \
+		SL_LINK_DOWN_RETRYABLE      | \
+		SL_LINK_DOWN_ORIGIN_ASYNC)
+#define SL_LINK_DOWN_CAUSE_CCW_MAP (          \
+		SL_LINK_DOWN_CAUSE_CCW      | \
+		SL_LINK_DOWN_RETRYABLE      | \
+		SL_LINK_DOWN_ORIGIN_ASYNC)
+
+struct sl_ctrl_link_fecl_kobj {
+	struct sl_ctrl_link *ctrl_link;
+	u8                   lane_num;
+	struct kobject       kobj;
+};
+
+#define SL_CTRL_LAST_DOWN_NUM_ENTRIES    10
+#define SL_CTRL_LAST_UP_FAIL_NUM_ENTRIES 10
+
+#define SL_CTRL_LINK_MAGIC     0x536c6c6b
+#define SL_CTRL_LINK_VER       1
+struct sl_ctrl_link {
+	u32                          magic;
+	u32                          ver;
+
+	u8                           num;
+
+	struct sl_link_config        config;
+	struct sl_link_policy        policy;
+	spinlock_t                   config_lock;
+
+	spinlock_t                   data_lock;
+	bool                         is_canceled;
+
+	struct sl_ctrl_link_counter *counters;
+	struct sl_ctrl_link_counter *cause_counters;
+	struct sl_ctrl_link_counter *an_cause_counters;
+
+	struct {
+		ktime_t              start;
+		ktime_t              elapsed;
+		u32                  attempt_count;
+		ktime_t              attempt_start;
+		ktime_t              attempt_elapsed;
+		ktime_t              up;
+		spinlock_t           lock;
+	} up_clock;
+
+	struct sl_ctrl_link_fec_data  fec_data;
+	u32                           fec_mon_state;
+	struct timer_list             fec_mon_timer;
+	bool                          fec_mon_timer_stop;
+	spinlock_t                    fec_mon_timer_lock;
+	struct work_struct            fec_mon_timer_work;
+	struct sl_ctrl_link_fec_cache fec_up_cache;
+	struct sl_ctrl_link_fec_cache fec_down_cache;
+	u8                            fec_ucw_chance;
+	u8                            fec_ccw_chance;
+
+	struct sl_ctrl_lgrp         *ctrl_lgrp;
+
+	struct kobject              *parent_kobj;
+	struct kobject               kobj;
+	struct kobject               last_down_kobj;
+	struct kobject               last_up_fail_kobj;
+	struct kobject               policy_kobj;
+	struct kobject               config_kobj;
+	struct kobject               caps_kobj;
+	struct kobject               counters_kobj;
+	struct {
+		struct kobject                kobj;
+
+		struct kobject                mon_check_kobj;
+
+		struct kobject                down_kobj;
+		struct kobject                down_lane_kobj;
+		struct sl_ctrl_link_fecl_kobj down_fecl_kobjs[SL_MAX_LANES];
+		struct kobject                down_tail_kobj;
+
+		struct kobject                up_kobj;
+		struct kobject                up_lane_kobj;
+		struct sl_ctrl_link_fecl_kobj up_fecl_kobjs[SL_MAX_LANES];
+		struct kobject                up_tail_kobj;
+	} fec;
+
+	u32               state;
+	struct completion down_complete;
+	struct kref       ref_cnt;
+	struct kref       mem_ref;
+	struct work_struct release_work;
+	/* Serializes delete attempts while completion storage is retained. */
+	struct mutex      delete_lock;
+	bool              delete_requested;
+	int               delete_result;
+	struct completion del_complete;
+	bool              sysfs_deleted;
+	u64               last_up_fail_cause_map;
+	time64_t          last_up_fail_time;
+};
+
+int		     sl_ctrl_link_new(u8 ldev_num, u8 lgrp_num, u8 link_num, struct kobject *sysfs_parent);
+int                  sl_ctrl_link_put(struct sl_ctrl_link *ctrl_link);
+int		     sl_ctrl_link_del(u8 ldev_num, u8 lgrp_num, u8 link_num);
+struct sl_ctrl_link *sl_ctrl_link_get(u8 ldev_num, u8 lgrp_num, u8 link_num);
+bool                 sl_ctrl_link_kref_get_unless_zero(struct sl_ctrl_link *ctrl_link);
+DEFINE_FREE(sl_ctrl_link_put, struct sl_ctrl_link *,
+	    sl_ctrl_link_put(_T))
+
+int sl_ctrl_link_config_set(u8 ldev_num, u8 lgrp_num, u8 link_num,
+			    struct sl_link_config *link_config);
+int sl_ctrl_link_policy_set(u8 ldev_num, u8 lgrp_num, u8 link_num,
+			    struct sl_link_policy *link_policy);
+
+int sl_ctrl_link_an_lp_caps_get(u8 ldev_num, u8 lgrp_num, u8 link_num,
+				struct sl_link_caps *caps, u32 timeout_ms, u32 flags);
+int sl_ctrl_link_an_lp_caps_stop(u8 ldev_num, u8 lgrp_num, u8 link_num);
+
+int sl_ctrl_link_up(u8 ldev_num, u8 lgrp_num, u8 link_num);
+int sl_ctrl_link_down(u8 ldev_num, u8 lgrp_num, u8 link_num);
+int sl_ctrl_link_reset(u8 ldev_num, u8 lgrp_num, u8 link_num);
+
+int sl_ctrl_link_up_clocks_get(u8 ldev_num, u8 lgrp_num, u8 link_num,
+			       s64 *attempt_time, s64 *total_time, s64 *up_time);
+int sl_ctrl_link_up_count_get(u8 ldev_num, u8 lgrp_num, u8 link_num, u32 *up_count);
+
+int sl_ctrl_link_state_get_cmd(u8 ldev_num, u8 lgrp_num, u8 link_num, u32 *state);
+
+int sl_ctrl_link_an_lp_caps_state_get(u8 ldev_num, u8 lgrp_num, u8 link_num, u32 *state);
+
+int sl_ctrl_link_an_fail_cause_get(u8 ldev_num, u8 lgrp_num, u8 link_num, u32 *fail_cause, time64_t *fail_time);
+
+u32 sl_ctrl_link_an_retry_count_get(struct sl_ctrl_link *ctrl_link, int *count);
+
+int sl_ctrl_link_info_map_get(u8 ldev_num, u8 lgrp_num, u8 link_num, u64 *info_map);
+
+#endif /* _SL_CTRL_LINK_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_link_counters.h b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_link_counters.h
new file mode 100644
index 000000000000..4931b67454b4
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_link_counters.h
@@ -0,0 +1,125 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023-2026 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CTRL_LINK_COUNTERS_H_
+#define _SL_CTRL_LINK_COUNTERS_H_
+
+struct sl_ctrl_link;
+
+enum sl_ctrl_link_counters {
+	LINK_UP_CMD,                    /* command to bring the link up                       */
+	LINK_UP_RETRY,                  /* link up retry                                      */
+	LINK_UP,                        /* link is up                                         */
+	LINK_UP_FAIL,                   /* link up failed                                     */
+	LINK_DOWN_CMD,                  /* command to bring the link down                     */
+	LINK_DOWN,                      /* link is down                                       */
+	LINK_UP_CANCEL_CMD,             /* link up cancel commanded                           */
+	LINK_UP_CANCELED,               /* link up cancel completed                           */
+	LINK_RESET_CMD,                 /* command to reset the link                          */
+	LINK_FAULT_ASYNC,               /* link fault async                                   */
+	LINK_RECOVERING,                /* need to implement this                             */
+	LINK_CCW_WARN_CROSSED,          /* ccw warn limit crossed                             */
+	LINK_UCW_WARN_CROSSED,          /* ucw warn limit crossed                             */
+	LINK_DOWN_CCW_LIMIT_CROSSED,    /* link down ccw limit crossed                        */
+	LINK_DOWN_UCW_LIMIT_CROSSED,    /* link down ucw limit crossed                        */
+	LINK_DOWN_CCW_CAUSE,            /* ccw max chance crossed causing the link to go down */
+	LINK_DOWN_UCW_CAUSE,            /* ucw max chance crossed causing the link to go down */
+	LINK_UP_FAIL_CCW_LIMIT_CROSSED, /* link up failed, ucw limit crossed                  */
+	LINK_UP_FAIL_UCW_LIMIT_CROSSED, /* link up failed, ccw limit crossed                  */
+	LINK_HW_AN_ATTEMPT,             /* link an attempt                                    */
+	SL_CTRL_LINK_COUNTERS_COUNT
+};
+
+enum sl_ctrl_link_cause_counters {
+	LINK_CAUSE_UCW,               /* link up or fec mon UCW limit crossed */
+	LINK_CAUSE_LF,                /* link local fault                     */
+	LINK_CAUSE_RF,                /* link remote fault                    */
+	LINK_CAUSE_DOWN,              /* link down fault                      */
+	LINK_CAUSE_UP_TRIES,          /* link up tries exhaused               */
+	LINK_CAUSE_AUTONEG_NOMATCH,   /* lp_caps autoneg no match             */
+	LINK_CAUSE_AUTONEG,           /* autoneg failure                      */
+	LINK_CAUSE_CONFIG,            /* link up bad config                   */
+	LINK_CAUSE_INTR_ENABLE,       /* link up interrupt enable failure     */
+	LINK_CAUSE_TIMEOUT,           /* link up timeout                      */
+	LINK_CAUSE_CANCELED,          /* link up cancelled                    */
+	LINK_CAUSE_UNSUPPORTED_CABLE, /* unsuppported cable                   */
+	LINK_CAUSE_COMMAND,           /* client command                       */
+	LINK_CAUSE_DOWNSHIFT,         /* link up cable downshift failed       */
+	LINK_CAUSE_LLR_REPLAY_MAX,    /* LLR replay at max fault              */
+	LINK_CAUSE_UPSHIFT,           /* link up cable upshift failed         */
+	LINK_CAUSE_AUTONEG_CONFIG,    /* link up config after an failed       */
+	LINK_CAUSE_PCS_FAULT,         /* link up PCS is not ok                */
+	LINK_CAUSE_SERDES_PLL,        /* link up serdes problems              */
+	LINK_CAUSE_SERDES_CONFIG,     /* link up serdes config problems       */
+	LINK_CAUSE_SERDES_SIGNAL,     /* link up serdes signal problems       */
+	LINK_CAUSE_SERDES_QUALITY,    /* link up serdes quality problems      */
+	LINK_CAUSE_NO_MEDIA,          /* no media present                     */
+	LINK_CAUSE_CCW,               /* link up or fec mon CCW limit crossed */
+	LINK_CAUSE_MEDIA_HOT,         /* active cable hot                     */
+	LINK_CAUSE_MEDIA_WARM,        /* active cable warm                    */
+	LINK_CAUSE_INTR_REGISTER,     /* link up interrupt register failure   */
+	LINK_CAUSE_MEDIA_ERROR,       /* media has errors                     */
+	LINK_CAUSE_UP_CANCELED,       /* link up canceled, link down          */
+	LINK_CAUSE_UNSUPPORTED_SPEED, /* unsupported speed                    */
+	LINK_CAUSE_SS200_CABLE,       /* SS200 cable                          */
+	LINK_CAUSE_TX_LOL,            /* TX Loss of Lock                      */
+	LINK_CAUSE_RX_LOL,            /* RX Loss of Lock                      */
+	LINK_CAUSE_TX_LOS,            /* TX Loss of Signal                    */
+	LINK_CAUSE_RX_LOS,            /* RX Loss of Signal                    */
+	SL_CTRL_LINK_CAUSE_COUNTERS_COUNT
+};
+
+enum sl_ctrl_link_an_cause_counters {
+	LINK_AN_CAUSE_LP_CAPS_SERDES_LINK_UP_FAIL,
+	LINK_AN_CAUSE_LP_CAPS_NOT_COMPLETE,
+	LINK_AN_CAUSE_NOT_COMPLETE,
+	LINK_AN_CAUSE_TEST_CAPS_NOMATCH,
+	LINK_AN_CAUSE_SERDES_LINK_UP_FAIL,
+	LINK_AN_CAUSE_BP_STORE_STATE_BAD,
+	LINK_AN_CAUSE_BP_STORE_LP_ABILITY_NOT_SET,
+	LINK_AN_CAUSE_BP_STORE_STATE_ERROR,
+	LINK_AN_CAUSE_BP_STORE_BP_NOT_SET,
+	LINK_AN_CAUSE_BP_SEND_INTR_ENABLE_FAIL,
+	LINK_AN_CAUSE_NP_STORE_STATE_BAD,
+	LINK_AN_CAUSE_NP_STORE_BP_SET,
+	LINK_AN_CAUSE_NP_CHECK_STATE_BAD,
+	LINK_AN_CAUSE_INTR_STATE_INVALID,
+	LINK_AN_CAUSE_INTR_AN_RETRY_NP_SEND_FAIL,
+	LINK_AN_CAUSE_INTR_OUT_OF_PAGES,
+	LINK_AN_CAUSE_INTR_NP_SEND_FAIL,
+	LINK_AN_CAUSE_PAGES_DECODE_FAIL,
+	LINK_AN_CAUSE_PAGES_DECODE_NO_BP,
+	LINK_AN_CAUSE_PAGES_DECODE_OUI_INVALID,
+	SL_CTRL_LINK_AN_CAUSE_COUNTERS_COUNT
+};
+
+struct sl_ctrl_link_counter {
+	atomic_t  count;
+	char     *name;
+};
+
+#define SL_CTRL_LINK_COUNTER_INC(_link, _counter) \
+	atomic_inc(&(_link)->counters[_counter].count)
+
+#define SL_CTRL_LINK_CAUSE_COUNTER_INC(_link, _counter) \
+	atomic_inc(&(_link)->cause_counters[_counter].count)
+
+#define SL_CTRL_LINK_AN_CAUSE_COUNTER_INC(_link, _counter) \
+	atomic_inc(&(_link)->an_cause_counters[_counter].count)
+
+int  sl_ctrl_link_counters_init(struct sl_ctrl_link *ctrl_link);
+void sl_ctrl_link_counters_del(struct sl_ctrl_link *ctrl_link);
+int  sl_ctrl_link_counters_get(struct sl_ctrl_link *ctrl_link, u32 counter, int *count);
+
+int  sl_ctrl_link_cause_counters_init(struct sl_ctrl_link *ctrl_link);
+void sl_ctrl_link_cause_counters_del(struct sl_ctrl_link *ctrl_link);
+int  sl_ctrl_link_cause_counters_get(struct sl_ctrl_link *ctrl_link, u32 counter, int *count);
+
+int  sl_ctrl_link_an_cause_counters_init(struct sl_ctrl_link *ctrl_link);
+void sl_ctrl_link_an_cause_counters_del(struct sl_ctrl_link *ctrl_link);
+int  sl_ctrl_link_an_cause_counters_get(struct sl_ctrl_link *ctrl_link, u32 counter, int *count);
+
+void sl_ctrl_link_cause_counter_inc(struct sl_ctrl_link *ctrl_link, u64 cause_map);
+void sl_ctrl_link_an_cause_counter_inc(struct sl_ctrl_link *ctrl_link, unsigned long cause_map);
+
+#endif /* _SL_CTRL_LINK_COUNTERS_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_link_fec.h b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_link_fec.h
new file mode 100644
index 000000000000..f15c8f12c369
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_link_fec.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CTRL_LINK_FEC_H_
+#define _SL_CTRL_LINK_FEC_H_
+
+struct sl_ber;
+struct sl_fec_info;
+struct sl_fec_tail;
+struct sl_core_link_fec_cw_cntrs;
+struct sl_core_link_fec_lane_cntrs;
+struct sl_core_link_fec_tail_cntrs;
+struct sl_ctrl_link;
+
+enum {
+	SL_CTRL_LINK_FEC_MON_OFF,
+	SL_CTRL_LINK_FEC_MON_ON
+};
+
+int sl_ctrl_link_fec_info_get(u8 ldev_num, u8 lgrp_num, u8 link_num,
+			      struct sl_fec_info *fec_info);
+int sl_ctrl_link_fec_tail_get(u8 ldev_num, u8 lgrp_num, u8 link_num,
+			      struct sl_fec_tail *fec_tail);
+int sl_ctrl_link_fec_data_get(u8 ldev_num, u8 lgrp_num, u8 link_num,
+			      struct sl_core_link_fec_cw_cntrs *cw_cntrs,
+			      struct sl_core_link_fec_lane_cntrs *lane_cntrs,
+			      struct sl_core_link_fec_tail_cntrs *tail_cntrs);
+int sl_ctrl_link_fec_mon_state_get(struct sl_ctrl_link *ctrl_link, u32 *state);
+const char *sl_ctrl_link_fec_mon_state_str(u32 state);
+int sl_ctrl_link_fec_ber_calc(struct sl_fec_info *fec_info,
+			      struct sl_ber *ucw_ber, struct sl_ber *ccw_ber);
+
+#endif /* _SL_CTRL_LINK_FEC_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_link_fec_priv.h b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_link_fec_priv.h
new file mode 100644
index 000000000000..e3a813a6b324
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_link_fec_priv.h
@@ -0,0 +1,94 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CTRL_LINK_FEC_PRIV_H_
+#define _SL_CTRL_LINK_FEC_PRIV_H_
+
+#include <linux/timer.h>
+#include <linux/spinlock.h>
+#include <linux/workqueue.h>
+
+#include "sl_core_link_fec.h"
+
+struct sl_ctrl_link;
+
+#define SL_CTRL_LINK_FEC_UCW_MANT   1
+#define SL_CTRL_LINK_FEC_UCW_EXP  -10
+#define SL_CTRL_LINK_FEC_CCW_MANT   2
+#define SL_CTRL_LINK_FEC_CCW_EXP   -5
+
+/* Normalize the rate, and check limit
+ * l = limit
+ * p = period_ms
+ * c = [U/C]CW delta (count)
+ * t = time = (p / 1000)
+ *
+ * l < (c / t); l * t < c; (l * p) < (c * 1000)
+ */
+#define SL_CTRL_LINK_FEC_LIMIT_CHECK(_limit, _count, _period) \
+	((_limit && _period) ? (((u64)(_limit) * (_period)) <= ((_count) * 1000)) : 0)
+#define SL_CTRL_LINK_FEC_UCW_LIMIT_CHECK(_limit, _info) \
+	SL_CTRL_LINK_FEC_LIMIT_CHECK(_limit, (_info)->ucw, (_info)->period_ms)
+#define SL_CTRL_LINK_FEC_CCW_LIMIT_CHECK(_limit, _info) \
+	SL_CTRL_LINK_FEC_LIMIT_CHECK(_limit, (_info)->ccw, (_info)->period_ms)
+
+struct sl_ctrl_link_fec_cntrs {
+	struct sl_core_link_fec_cw_cntrs   cw_cntrs;
+	struct sl_core_link_fec_lane_cntrs lane_cntrs;
+	struct sl_core_link_fec_tail_cntrs tail_cntrs;
+	unsigned long                      timestamp;
+};
+
+struct sl_ctrl_link_fec_data {
+	struct sl_ctrl_link_fec_cntrs  cntrs[2];
+	struct sl_ctrl_link_fec_cntrs *curr_ptr;
+	struct sl_ctrl_link_fec_cntrs *prev_ptr;
+	struct sl_fec_info             info;
+	struct sl_fec_tail             tail;
+	spinlock_t                     lock;
+};
+
+struct sl_ctrl_link_fec_cache {
+	struct sl_core_link_fec_cw_cntrs   cw_cntrs;
+	struct sl_core_link_fec_lane_cntrs lane_cntrs;
+	struct sl_core_link_fec_tail_cntrs tail_cntrs;
+	spinlock_t                         lock;
+};
+
+void                sl_ctrl_link_fec_data_store(struct sl_ctrl_link *ctrl_link,
+						struct sl_core_link_fec_cw_cntrs *cw_cntrs,
+						struct sl_core_link_fec_lane_cntrs *lane_cntrs,
+						struct sl_core_link_fec_tail_cntrs *tail_cntrs);
+void                sl_ctrl_link_fec_up_cache_clear(struct sl_ctrl_link *ctrl_link);
+void                sl_ctrl_link_fec_up_cache_store(struct sl_ctrl_link *ctrl_link,
+						    struct sl_core_link_fec_cw_cntrs *cw_cntrs,
+						    struct sl_core_link_fec_lane_cntrs *lane_cntrs,
+						    struct sl_core_link_fec_tail_cntrs *tail_cntrs);
+void                sl_ctrl_link_fec_down_cache_clear(struct sl_ctrl_link *ctrl_link);
+void                sl_ctrl_link_fec_down_cache_store(struct sl_ctrl_link *ctrl_link,
+						      struct sl_core_link_fec_cw_cntrs *cw_cntrs,
+						      struct sl_core_link_fec_lane_cntrs *lane_cntrs,
+						      struct sl_core_link_fec_tail_cntrs *tail_cntrs);
+void                sl_ctrl_link_fec_data_calc(struct sl_ctrl_link *ctrl_link);
+int                 sl_ctrl_link_fec_data_check(struct sl_ctrl_link *ctrl_link);
+struct sl_fec_info  sl_ctrl_link_fec_data_info_get(struct sl_ctrl_link *ctrl_link);
+struct sl_fec_tail  sl_ctrl_link_fec_data_tail_get(struct sl_ctrl_link *ctrl_link);
+
+int sl_ctrl_link_fec_up_cache_cw_cntrs_get(struct sl_ctrl_link *ctrl_link,
+					   struct sl_core_link_fec_cw_cntrs *cw_cntrs);
+int sl_ctrl_link_fec_up_cache_lane_cntrs_get(struct sl_ctrl_link *ctrl_link,
+					     struct sl_core_link_fec_lane_cntrs *lane_cntrs);
+int sl_ctrl_link_fec_up_cache_tail_cntrs_get(struct sl_ctrl_link *ctrl_link,
+					     struct sl_core_link_fec_tail_cntrs *tail_cntrs);
+
+int sl_ctrl_link_fec_down_cache_tail_cntrs_get(struct sl_ctrl_link *ctrl_link,
+					       struct sl_core_link_fec_tail_cntrs *tail_cntrs);
+
+void sl_ctrl_link_fec_mon_start(struct sl_ctrl_link *ctrl_link);
+void sl_ctrl_link_fec_mon_timer_work(struct work_struct *work);
+void sl_ctrl_link_fec_mon_timer(struct timer_list *timer);
+void sl_ctrl_link_fec_mon_stop(struct sl_ctrl_link *ctrl_link);
+
+u32 sl_ctrl_link_fec_limit_calc(struct sl_ctrl_link *ctrl_link, u32 mant, int exp);
+
+#endif /* _SL_CTRL_LINK_FEC_PRIV_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_link_priv.h b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_link_priv.h
new file mode 100644
index 000000000000..6ecd980481ed
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_link_priv.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023-2026 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CTRL_LINK_PRIV_H_
+#define _SL_CTRL_LINK_PRIV_H_
+
+#include <linux/workqueue.h>
+
+struct sl_ctrl_link;
+struct sl_link_config;
+struct sl_link_policy;
+struct sl_link_caps;
+struct sl_core_link_up_info;
+
+s32 sl_ctrl_link_policy_fec_mon_ucw_down_limit_get(struct sl_ctrl_link *ctrl_link);
+s32 sl_ctrl_link_policy_fec_mon_ucw_warn_limit_get(struct sl_ctrl_link *ctrl_link);
+s32 sl_ctrl_link_policy_fec_mon_ccw_down_limit_get(struct sl_ctrl_link *ctrl_link);
+s32 sl_ctrl_link_policy_fec_mon_ccw_warn_limit_get(struct sl_ctrl_link *ctrl_link);
+s32 sl_ctrl_link_policy_fec_mon_period_ms_get(struct sl_ctrl_link *ctrl_link);
+u32 sl_ctrl_link_policy_options_get(struct sl_ctrl_link *ctrl_link);
+u32 sl_ctrl_link_state_get(struct sl_ctrl_link *ctrl_link);
+
+void sl_ctrl_link_up_callback_work(struct work_struct *work);
+int  sl_ctrl_link_fault_start_callback(u8 ldev_num, u8 lgrp_num, u8 link_num);
+int  sl_ctrl_link_fault_callback(void *tag, u32 core_state, u64 core_cause_map, u64 core_info_map);
+int  sl_ctrl_link_an_lp_caps_get_callback(void *tag, struct sl_link_caps *caps, u32 result);
+int  sl_ctrl_link_up_callback(void *tag, struct sl_core_link_up_info *core_link_up_info);
+int  sl_ctrl_link_down_callback(void *tag, u32 core_state, u64 core_cause_map, u64 core_info_map);
+int  sl_ctrl_link_async_down(struct sl_ctrl_link *ctrl_link, u64 down_cause_map, bool force_down);
+
+void sl_ctrl_link_up_clock_start(struct sl_ctrl_link *ctrl_link);
+void sl_ctrl_link_up_clock_reset(struct sl_ctrl_link *ctrl_link);
+void sl_ctrl_link_up_clock_attempt_start(struct sl_ctrl_link *ctrl_link);
+
+void sl_ctrl_link_config_get(struct sl_ctrl_link *ctrl_link, struct sl_link_config *link_config);
+void sl_ctrl_link_policy_get(struct sl_ctrl_link *ctrl_link, struct sl_link_policy *link_policy);
+
+void sl_ctrl_link_state_set(struct sl_ctrl_link *ctrl_link, u32 link_state);
+
+bool sl_ctrl_link_is_canceled(struct sl_ctrl_link *ctrl_link);
+void sl_ctrl_link_is_canceled_set(struct sl_ctrl_link *ctrl_link, bool canceled);
+
+int  sl_ctrl_link_last_up_fail_cause_map_get(struct sl_ctrl_link *ctrl_link, u64 *last_up_fail_cause_map);
+int  sl_ctrl_link_last_up_fail_cause_info_get(struct sl_ctrl_link *ctrl_link, u64 *last_up_fail_cause_map,
+					      time64_t *last_up_fail_time);
+
+#endif /* _SL_CTRL_LINK_PRIV_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_llr.h b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_llr.h
new file mode 100644
index 000000000000..1d9e48625920
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_llr.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023,2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CTRL_LLR_H_
+#define _SL_CTRL_LLR_H_
+
+#include <linux/workqueue.h>
+#include <linux/spinlock.h>
+#include <linux/kobject.h>
+
+#include <linux/hpe/sl/sl_llr.h>
+
+#include "sl_core_llr.h"
+
+#define SL_LLR_DATA_MAGIC 0x636c6c72
+#define SL_LLR_DATA_VER   2
+
+#define SL_CTRL_LLR_MAGIC 0x606c6c72
+#define SL_CTRL_LLR_VER   1
+struct sl_ctrl_llr {
+	u32                         magic;
+	u32                         ver;
+
+	u8                          num;
+
+	spinlock_t                  data_lock;
+
+	struct sl_ctrl_llr_counter *counters;
+	struct sl_ctrl_llr_counter *cause_counters;
+
+	struct sl_llr_config        config;
+	struct sl_llr_policy        policy;
+	struct {
+		u32                 state;
+		u64                 imap;
+		struct sl_llr_data  data;
+	} setup;
+	struct {
+		u32                 state;
+		u64                 imap;
+	} start;
+
+	struct sl_ctrl_lgrp        *ctrl_lgrp;
+
+	struct kobject             *parent_kobj;
+	struct kobject              config_kobj;
+	struct kobject              counters_kobj;
+
+	struct kref                 ref_cnt;
+	struct completion           del_complete;
+};
+
+int		    sl_ctrl_llr_new(u8 ldev_num, u8 lgrp_num, u8 llr_num, struct kobject *sysfs_parent);
+int		    sl_ctrl_llr_del(u8 ldev_num, u8 lgrp_num, u8 llr_num);
+struct sl_ctrl_llr *sl_ctrl_llr_get(u8 ldev_num, u8 lgrp_num, u8 llr_num);
+
+int sl_ctrl_llr_config_set(u8 ldev_num, u8 lgrp_num, u8 llr_num, struct sl_llr_config *llr_config);
+int sl_ctrl_llr_policy_set(u8 ldev_num, u8 lgrp_num, u8 llr_num, struct sl_llr_policy *llr_policy);
+
+int sl_ctrl_llr_setup(u8 ldev_num, u8 lgrp_num, u8 llr_num);
+int sl_ctrl_llr_start(u8 ldev_num, u8 lgrp_num, u8 llr_num);
+int sl_ctrl_llr_stop(u8 ldev_num, u8 lgrp_num, u8 llr_num);
+
+enum sl_llr_state sl_ctrl_llr_state_from_core_llr_state(enum sl_core_llr_state core_llr_state);
+int sl_ctrl_llr_state_get(u8 ldev_num, u8 lgrp_num, u8 llr_num, enum sl_llr_state *state);
+
+int sl_ctrl_llr_info_map_get(u8 ldev_num, u8 lgrp_num, u8 llr_num, u64 *info_map);
+
+#endif /* _SL_CTRL_LLR_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_llr_counters.h b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_llr_counters.h
new file mode 100644
index 000000000000..2427b5ba0508
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_llr_counters.h
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CTRL_LLR_COUNTERS_H_
+#define _SL_CTRL_LLR_COUNTERS_H_
+
+#include <linux/types.h>
+#include <linux/atomic.h>
+
+struct sl_ctrl_llr;
+
+enum sl_ctrl_llr_counters {
+	LLR_SETUP_CMD,            /* command to setup llr   */
+	LLR_SETUP,                /* llr setup is succeeded */
+	LLR_SETUP_TIMEOUT,        /* llr setup is timed out */
+	LLR_SETUP_FAIL,           /* llr setup is failed    */
+	LLR_CONFIGURED,           /* llr is configured      */
+	LLR_START_CMD,            /* command to start llr   */
+	LLR_RUNNING,              /* llr is running         */
+	LLR_START_TIMEOUT,        /* llr start is timed out */
+	LLR_START_FAIL,           /* llr start is failed    */
+	LLR_STOP_CMD,             /* command to stop llr    */
+	LLR_STOP_FAIL,            /* llr stop is failed     */
+	SL_CTRL_LLR_COUNTERS_COUNT
+};
+
+enum sl_ctrl_llr_cause_counters {
+	LLR_CAUSE_SETUP_CONFIG,         /* llr setup config invalid             */
+	LLR_CAUSE_SETUP_INTR_ENABLE,    /* llr setup interrupt enable failed    */
+	LLR_CAUSE_SETUP_TIMEOUT,        /* llr setup timeout                    */
+	LLR_CAUSE_START_INTR_ENABLE,    /* llr start interrupt enable failed    */
+	LLR_CAUSE_START_TIMEOUT,        /* llr start timeout                    */
+	LLR_CAUSE_COMMAND,              /* running llr was commanded to stop    */
+	LLR_CAUSE_CANCELED,             /* llr operation was canceled by client */
+	SL_CTRL_LLR_CAUSE_COUNTERS_COUNT
+};
+
+struct sl_ctrl_llr_counter {
+	atomic_t  count;
+	char     *name;
+};
+
+#define SL_CTRL_LLR_COUNTER_INC(_llr, _counter) \
+	atomic_inc(&(_llr)->counters[_counter].count)
+
+int  sl_ctrl_llr_counters_init(struct sl_ctrl_llr *ctrl_llr);
+void sl_ctrl_llr_counters_del(struct sl_ctrl_llr *ctrl_llr);
+int  sl_ctrl_llr_counter_get(struct sl_ctrl_llr *ctrl_llr, u32 counter, int *count);
+
+int  sl_ctrl_llr_cause_counters_init(struct sl_ctrl_llr *ctrl_llr);
+void sl_ctrl_llr_cause_counters_del(struct sl_ctrl_llr *ctrl_llr);
+int  sl_ctrl_llr_cause_counter_get(struct sl_ctrl_llr *ctrl_llr, u32 counter, int *count);
+
+void sl_ctrl_llr_cause_counters_inc(struct sl_ctrl_llr *ctrl_llr, unsigned long cause_map);
+void sl_ctrl_llr_cause_counter_inc(struct sl_core_llr *core_llr, unsigned long cause_map);
+
+#endif /* _SL_CTRL_LLR_COUNTERS_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_mac.h b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_mac.h
new file mode 100644
index 000000000000..9b544c33a7e4
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_mac.h
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CTRL_MAC_H_
+#define _SL_CTRL_MAC_H_
+
+#include "linux/kref.h"
+#include <linux/spinlock.h>
+#include <linux/kobject.h>
+
+struct sl_ctrl_lgrp;
+
+#define SL_CTRL_MAC_MAGIC 0x646c6c79
+#define SL_CTRL_MAC_VER   1
+struct sl_ctrl_mac {
+	u32                         magic;
+	u32                         ver;
+
+	u8                          num;
+
+	spinlock_t                  data_lock; /* data lock for mac object  */
+
+	struct sl_ctrl_mac_counter *counters;
+	struct sl_ctrl_lgrp        *ctrl_lgrp;
+
+	struct kobject             *parent_kobj;
+	struct kobject              kobj;
+	struct kobject              counters_kobj;
+
+	struct kref                 ref_cnt;
+	/*
+	 * Owns the memory, not the logical object: ref_cnt reaching zero runs
+	 * the release, which signals del_complete. A deleter that waits on
+	 * del_complete holds a reference here, so the completion embedded in
+	 * this object cannot be freed while it is still being used.
+	 */
+	struct kref                 mem_ref;
+	struct completion           del_complete;
+};
+
+int		    sl_ctrl_mac_new(u8 ldev_num, u8 lgrp_num, u8 mac_num, struct kobject *sysfs_parent);
+int		    sl_ctrl_mac_del(u8 ldev_num, u8 lgrp_num, u8 mac_num);
+struct sl_ctrl_mac *sl_ctrl_mac_get(u8 ldev_num, u8 lgrp_num, u8 mac_num);
+
+int sl_ctrl_mac_tx_start(u8 ldev_num, u8 lgrp_num, u8 mac_num);
+int sl_ctrl_mac_tx_stop(u8 ldev_num, u8 lgrp_num, u8 mac_num);
+int sl_ctrl_mac_tx_state_get(u8 ldev_num, u8 lgrp_num, u8 mac_num, u32 *state);
+
+int sl_ctrl_mac_rx_start(u8 ldev_num, u8 lgrp_num, u8 mac_num);
+int sl_ctrl_mac_rx_stop(u8 ldev_num, u8 lgrp_num, u8 mac_num);
+int sl_ctrl_mac_rx_state_get(u8 ldev_num, u8 lgrp_num, u8 mac_num, u32 *state);
+
+int sl_ctrl_mac_reset(u8 ldev_num, u8 lgrp_num, u8 mac_num);
+
+int sl_ctrl_mac_info_map_get(u8 ldev_num, u8 lgrp_num, u8 mac_num, u64 *info_map);
+
+#endif /* _SL_CTRL_MAC_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_mac_counters.h b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_mac_counters.h
new file mode 100644
index 000000000000..90dd65267f10
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_mac_counters.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2025-2026 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CTRL_MAC_COUNTERS_H_
+#define _SL_CTRL_MAC_COUNTERS_H_
+
+#include <linux/types.h>
+#include <linux/atomic.h>
+
+struct sl_ctrl_mac;
+
+enum sl_ctrl_mac_counters {
+	MAC_TX_START_CMD,         /* command to start mac tx   */
+	MAC_TX_STARTED,           /* mac tx is started         */
+	MAC_TX_START_FAIL,        /* mac tx start is failed    */
+	MAC_TX_STOP_CMD,          /* comamnd to stop mac tx    */
+	MAC_TX_STOPPED,           /* mac tx is stopped         */
+	MAC_TX_STOP_FAIL,         /* mac tx stop is failed     */
+	MAC_RX_START_CMD,         /* command to start mac rx   */
+	MAC_RX_STARTED,           /* mac rx is started         */
+	MAC_RX_START_FAIL,        /* mac rx start is failed    */
+	MAC_RX_STOP_CMD,          /* command to stop mac rx    */
+	MAC_RX_STOPPED,           /* mac rx is stopped         */
+	MAC_RX_STOP_FAIL,         /* mac rx stop is failed     */
+	MAC_RESET_CMD,            /* command to reset mac      */
+	MAC_RESET,                /* mac reset is succeeded    */
+	MAC_RESET_FAIL,           /* mac reset is failed       */
+	SL_CTRL_MAC_COUNTERS_COUNT
+};
+
+struct sl_ctrl_mac_counter {
+	atomic_t  count;
+	char     *name;
+};
+
+#define SL_CTRL_MAC_COUNTER_INC(_mac, _counter) \
+	atomic_inc(&(_mac)->counters[_counter].count)
+
+int  sl_ctrl_mac_counters_init(struct sl_ctrl_mac *ctrl_mac);
+void sl_ctrl_mac_counters_del(struct sl_ctrl_mac *ctrl_mac);
+int  sl_ctrl_mac_counter_get(struct sl_ctrl_mac *ctrl_mac, u32 counter, int *count);
+
+#endif /* _SL_CTRL_MAC_COUNTERS_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_media_counters.h b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_media_counters.h
new file mode 100644
index 000000000000..6b3fbc5acdf1
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_media_counters.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2025,2026 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_CTRL_MEDIA_COUNTERS_H_
+#define _SL_CTRL_MEDIA_COUNTERS_H_
+
+#include <linux/types.h>
+#include <linux/atomic.h>
+
+struct sl_media_jack;
+
+enum sl_ctrl_media_cause_counters {
+	MEDIA_CAUSE_EEPROM_FORMAT_UNSUPPORTED,         /* media eeprom format is unsupported            */
+	MEDIA_CAUSE_EEPROM_VENDOR_UNSUPPORTED,         /* media eeprom vendor is unsupported            */
+	MEDIA_CAUSE_EEPROM_JACK_IO,                    /* media eeprom jack io error                    */
+	MEDIA_CAUSE_ONLINE_STATUS_GET,                 /* media online status get error                 */
+	MEDIA_CAUSE_ONLINE_TIMEDOUT,                   /* media online timedout                         */
+	MEDIA_CAUSE_ONLINE_JACK_IO,                    /* media online jack io error                    */
+	MEDIA_CAUSE_ONLINE_JACK_GET,                   /* media online jack get error                   */
+	MEDIA_CAUSE_SERDES_SETTINGS_GET,               /* media serdes settings get error               */
+	MEDIA_CAUSE_SCAN_STATUS_GET,                   /* media scan status get error                   */
+	MEDIA_CAUSE_SCAN_HDL_GET,                      /* media scan hdl get error                      */
+	MEDIA_CAUSE_SCAN_JACK_GET,                     /* media scan jack get error                     */
+	MEDIA_CAUSE_MEDIA_ATTR_SET,                    /* media attribute set error                     */
+	MEDIA_CAUSE_INTR_EVENT_JACK_IO,                /* media interrupt event jack io error           */
+	MEDIA_CAUSE_POWER_SET,                         /* media power set error                         */
+	MEDIA_CAUSE_SHIFT_DOWN_JACK_IO,                /* media shift down jack io error                */
+	MEDIA_CAUSE_SHIFT_DOWN_JACK_IO_LOW_POWER_SET,  /* media shift down jack io low power set error  */
+	MEDIA_CAUSE_SHIFT_DOWN_JACK_IO_HIGH_POWER_SET, /* media shift down jack io high power set error */
+	MEDIA_CAUSE_SHIFT_UP_JACK_IO,                  /* media shift up jack io error                  */
+	MEDIA_CAUSE_SHIFT_UP_JACK_IO_LOW_POWER_SET,    /* media shift up jack io low power set error    */
+	MEDIA_CAUSE_SHIFT_UP_JACK_IO_HIGH_POWER_SET,   /* media shift up jack io high power ser error   */
+	MEDIA_CAUSE_SHIFT_STATE_JACK_IO,               /* media shift state jack io error               */
+	MEDIA_CAUSE_OFFLINE,                           /* media is offline                              */
+	MEDIA_CAUSE_HOT,                               /* media hot detected                            */
+	MEDIA_CAUSE_WARM,                              /* media warm detected                           */
+	SL_CTRL_MEDIA_CAUSE_COUNTERS_COUNT
+};
+
+struct sl_ctrl_media_counter {
+	atomic_t  count;
+	char     *name;
+};
+
+#define SL_CTRL_MEDIA_CAUSE_COUNTER_INC(_media, _counter) \
+	atomic_inc(&(_media)->cause_counters[_counter].count)
+
+int  sl_ctrl_media_cause_counters_init(struct sl_media_jack *media_jack);
+void sl_ctrl_media_cause_counters_del(struct sl_media_jack *media_jack);
+int  sl_ctrl_media_cause_counter_get(struct sl_media_jack *media_jack, u32 counter, int *count);
+void sl_ctrl_media_cause_counter_inc(struct sl_media_jack *media_jack, unsigned long cause_map);
+
+#endif /* _SL_CTRL_MEDIA_COUNTERS_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/log/sl_log.h b/drivers/net/ethernet/hpe/sl/log/sl_log.h
new file mode 100644
index 000000000000..ca1a8743ec76
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/log/sl_log.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2022-2026 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_LOG_H_
+#define _SL_LOG_H_
+
+#include <linux/kern_levels.h>
+#include <linux/dynamic_debug.h>
+
+#define SL_LOG_CONNECT_ID_LEN 12
+
+#define SL_LOG_BLOCK             "sl"
+#define SL_LOG_LDEV_LOG_NAME     "ldev"
+#define SL_LOG_LGRP_LOG_NAME     "lgrp"
+#define SL_LOG_LINK_LOG_NAME     "link"
+#define SL_LOG_FEC_LOG_NAME      "fec"
+#define SL_LOG_MAC_LOG_NAME      "mac"
+#define SL_LOG_LLR_LOG_NAME      "llr"
+#define SL_LOG_MEDIA_LOG_NAME    "media"
+#define SL_LOG_SYSFS_LOG_NAME    "sysfs"
+#define SL_LOG_DEBUGFS_LOG_NAME  "debugfs"
+#define SL_LOG_TEST_LOG_NAME     "test"
+
+void sl_log(void *ptr, const char *level, const char *block, const char *name, const char *text, ...) __printf(5, 6);
+void sl_log_err_trace(void *ptr, const char *block, const char *name, const char *text, ...) __printf(4, 5);
+void sl_log_warn_trace(void *ptr, const char *block, const char *name, const char *text, ...) __printf(4, 5);
+void sl_log_io_trace(void *ptr, const char *block, const char *name, const char *text, ...) __printf(4, 5);
+
+#if defined(CONFIG_DYNAMIC_DEBUG) || \
+	(defined(CONFIG_DYNAMIC_DEBUG_CORE) && defined(DYNAMIC_DEBUG_MODULE))
+
+void __sl_log_dynamic_dbg(struct _ddebug *desc, void *ptr,
+			  const char *block, const char *name, const char *text, ...) __printf(5, 6);
+
+#define __sl_log_dynamic_func_call(_id, _ptr, _block, _name, _text, _func, ...) \
+	do {                                                                    \
+		DEFINE_DYNAMIC_DEBUG_METADATA(_id, _text);                      \
+		if (DYNAMIC_DEBUG_BRANCH(_id))                                  \
+			_func(&_id, _ptr, _block, _name, _text, ##__VA_ARGS__); \
+	} while (0)
+
+#define _sl_log_dynamic_func_call(_ptr, _block, _name, _text, _func, ...)    \
+	__sl_log_dynamic_func_call(__UNIQUE_ID(ddebug), _ptr, _block, _name, \
+	_text, _func, ##__VA_ARGS__)
+
+#define sl_log_dynamic_dbg(_ptr, _block, _name, _text, ...)   \
+	_sl_log_dynamic_func_call(_ptr, _block, _name, _text, \
+	__sl_log_dynamic_dbg, ##__VA_ARGS__)
+
+#define sl_log_dbg(_ptr, _block, _name, _text, ...) \
+	sl_log_dynamic_dbg((_ptr), (_block), (_name), (_text), ##__VA_ARGS__)
+
+#else
+
+#define sl_log_dbg(_ptr, _block, _name, _text, ...) \
+	sl_log((_ptr), KERN_DEBUG, (_block), (_name), (_text), ##__VA_ARGS__)
+
+#endif
+
+#define sl_log_info(_ptr, _block, _name, _text, ...) \
+	sl_log((_ptr), KERN_INFO, (_block), (_name), (_text), ##__VA_ARGS__)
+#define sl_log_warn(_ptr, _block, _name, _text, ...) \
+	sl_log((_ptr), KERN_WARNING, (_block), (_name), (_text), ##__VA_ARGS__)
+#define sl_log_err(_ptr, _block, _name, _text, ...) \
+	sl_log((_ptr), KERN_ERR, (_block), (_name), (_text), ##__VA_ARGS__)
+
+#endif /* _SL_LOG_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/media/base/sl_media_eeprom.h b/drivers/net/ethernet/hpe/sl/media/base/sl_media_eeprom.h
new file mode 100644
index 000000000000..662fa04f9a59
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/media/base/sl_media_eeprom.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023-2026 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_MEDIA_EEPROM_H
+#define _SL_MEDIA_EEPROM_H
+
+struct sl_media_jack;
+struct sl_media_attr;
+
+void sl_media_eeprom_parse(struct sl_media_jack *media_jack, struct sl_media_attr *media_attr);
+int  sl_media_eeprom_format_get(struct sl_media_jack *media_jack, u8 *format);
+int  sl_media_eeprom_media_interface_get(struct sl_media_jack *media_jack, u8 *media_interface);
+int  sl_media_eeprom_target_fw_ver_str_get(struct sl_media_jack *media_jack, char *target_fw_str, size_t target_fw_size);
+bool sl_media_eeprom_is_fw_version_supported(struct sl_media_jack *media_jack, struct sl_media_attr *media_attr);
+
+#endif /* _SL_MEDIA_EEPROM_H */
diff --git a/drivers/net/ethernet/hpe/sl/media/base/sl_media_log.h b/drivers/net/ethernet/hpe/sl/media/base/sl_media_log.h
new file mode 100644
index 000000000000..78a04dc53b95
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/media/base/sl_media_log.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023,2024 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_MEDIA_LOG_H_
+#define _SL_MEDIA_LOG_H_
+
+#include "sl_log.h"
+
+#define SL_MEDIA_LOG_BLOCK          "media"
+
+#define SL_MEDIA_LDEV_LOG_NAME      "ldev"
+#define SL_MEDIA_LGRP_LOG_NAME      "lgrp"
+#define SL_MEDIA_DATA_LOG_NAME      "data"
+#define SL_MEDIA_DATA_LDEV_LOG_NAME "d-ldev"
+#define SL_MEDIA_DATA_LGRP_LOG_NAME "d-lgrp"
+#define SL_MEDIA_JACK_LOG_NAME      "jack"
+#define SL_MEDIA_DATA_JACK_LOG_NAME "d-jack"
+#define SL_MEDIA_CABLE_LOG_NAME     "cable"
+#define SL_MEDIA_EEPROM_LOG_NAME    "eeprom"
+#define SL_MEDIA_TEST_LOG_NAME      "test"
+#define SL_MEDIA_IO_LOG_NAME        "media-io"
+
+#define sl_media_log_dbg(_ptr, _name, _text, ...) \
+	sl_log_dbg((_ptr), SL_MEDIA_LOG_BLOCK, (_name), (_text), ##__VA_ARGS__)
+#define sl_media_log_info(_ptr, _name, _text, ...) \
+	sl_log_info((_ptr), SL_MEDIA_LOG_BLOCK, (_name), (_text), ##__VA_ARGS__)
+#define sl_media_log_warn(_ptr, _name, _text, ...) \
+	sl_log_warn((_ptr), SL_MEDIA_LOG_BLOCK, (_name), (_text), ##__VA_ARGS__)
+#define sl_media_log_warn_trace(_ptr, _name, _text, ...) \
+	sl_log_warn_trace((_ptr), SL_MEDIA_LOG_BLOCK, (_name), (_text), ##__VA_ARGS__)
+#define sl_media_log_err(_ptr, _name, _text, ...) \
+	sl_log_err((_ptr), SL_MEDIA_LOG_BLOCK, (_name), (_text), ##__VA_ARGS__)
+#define sl_media_log_err_trace(_ptr, _name, _text, ...) \
+	sl_log_err_trace((_ptr), SL_MEDIA_LOG_BLOCK, (_name), (_text), ##__VA_ARGS__)
+
+#endif /* _SL_MEDIA_LOG_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/media/base/sl_media_work.h b/drivers/net/ethernet/hpe/sl/media/base/sl_media_work.h
new file mode 100644
index 000000000000..6943a54e81d1
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/media/base/sl_media_work.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_MEDIA_WORK_H_
+#define _SL_MEDIA_WORK_H_
+
+enum {
+	SL_MEDIA_WORK_CABLE_MON_TEMP = 0,
+
+	SL_MEDIA_WORK_COUNT      /* must be last */
+};
+
+#endif /* _SL_MEDIA_WORK_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/media/data/sl_media_data_cable_db.h b/drivers/net/ethernet/hpe/sl/media/data/sl_media_data_cable_db.h
new file mode 100644
index 000000000000..181db14e893e
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/media/data/sl_media_data_cable_db.h
@@ -0,0 +1,6896 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023-2026 Hewlett Packard Enterprise Development LP */
+
+/* This file is auto-generated through script and should not be modified */
+/* source1 = S1 S2 QSFP Cable List */
+/* source2 = S2 S3 OSFP Cable List */
+
+#ifndef _SL_MEDIA_DATA_CABLE_DB_H_
+#define _SL_MEDIA_DATA_CABLE_DB_H_
+
+#include "sl_media_jack.h"
+
+static struct sl_media_cable_attr cable_db[] = {
+	{
+		.hpe_pn                   = 42668001,
+		.vendor                   = SL_MEDIA_VENDOR_CLOUD_LIGHT,
+		.vendor_pn_str            = "8363-K2-2030",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 3000,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 42668001,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DME8811A-EC30-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 3000,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 43548001,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DEF8504-2C05-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 500,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_200G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 43839001,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DEF8504-2C10-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 1000,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_200G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 43840001,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DEF8504-2C30-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 3000,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_200G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 45033001,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DEF8504-2C50-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 5000,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_200G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 45070001,
+		.vendor                   = SL_MEDIA_VENDOR_CLOUD_LIGHT,
+		.vendor_pn_str            = "8363-K2-2050",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 5000,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 45070001,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DME8811A-EC50-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 5000,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54408001,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "L45593-K812-C100",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 100,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54408001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "3025249101",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 100,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54408001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2409709-1",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 100,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54410001,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "L45593-K812-C150",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 150,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54410001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "3025249102",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 150,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54410001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2409709-2",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 150,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54411001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "2202933001",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 150,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 1,
+		.fw_ver.minor             = 5,
+		.fw_ver.split_major       = 1,
+		.fw_ver.split_minor       = 0,
+	},
+	{
+		.hpe_pn                   = 54411001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2480869-1",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 150,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 0,
+		.fw_ver.minor             = 4,
+		.fw_ver.split_major       = 0,
+		.fw_ver.split_minor       = 4,
+	},
+	{
+		.hpe_pn                   = 54412001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "2202933002",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 200,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 1,
+		.fw_ver.minor             = 5,
+		.fw_ver.split_major       = 1,
+		.fw_ver.split_minor       = 0,
+	},
+	{
+		.hpe_pn                   = 54412001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2480869-2",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 200,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 0,
+		.fw_ver.minor             = 4,
+		.fw_ver.split_major       = 0,
+		.fw_ver.split_minor       = 4,
+	},
+	{
+		.hpe_pn                   = 54415001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "2202933003",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 250,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 1,
+		.fw_ver.minor             = 5,
+		.fw_ver.split_major       = 1,
+		.fw_ver.split_minor       = 0,
+	},
+	{
+		.hpe_pn                   = 54415001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2480869-3",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 250,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 0,
+		.fw_ver.minor             = 4,
+		.fw_ver.split_major       = 0,
+		.fw_ver.split_minor       = 4,
+	},
+	{
+		.hpe_pn                   = 54416001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "2202933004",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 300,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 1,
+		.fw_ver.minor             = 5,
+		.fw_ver.split_major       = 1,
+		.fw_ver.split_minor       = 0,
+	},
+	{
+		.hpe_pn                   = 54416001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2480869-4",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 300,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 0,
+		.fw_ver.minor             = 4,
+		.fw_ver.split_major       = 0,
+		.fw_ver.split_minor       = 4,
+	},
+	{
+		.hpe_pn                   = 54417001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "2202933005",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 400,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 1,
+		.fw_ver.minor             = 5,
+		.fw_ver.split_major       = 1,
+		.fw_ver.split_minor       = 0,
+	},
+	{
+		.hpe_pn                   = 54417001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2480869-5",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 400,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 0,
+		.fw_ver.minor             = 4,
+		.fw_ver.split_major       = 0,
+		.fw_ver.split_minor       = 4,
+	},
+	{
+		.hpe_pn                   = 54418001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "2202933006",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 500,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 1,
+		.fw_ver.minor             = 5,
+		.fw_ver.split_major       = 1,
+		.fw_ver.split_minor       = 0,
+	},
+	{
+		.hpe_pn                   = 54418001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2480869-6",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 500,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 0,
+		.fw_ver.minor             = 4,
+		.fw_ver.split_major       = 0,
+		.fw_ver.split_minor       = 4,
+	},
+	{
+		.hpe_pn                   = 54419001,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "L45593-K810-C80",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 80,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54419001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "2126759001",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 80,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54419001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2500268-1",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 80,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54419001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2409706-1",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 80,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54420001,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "L45593-K810-C140",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 140,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54420001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "2126759004",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 140,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54420001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2500268-4",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 140,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54420001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2409706-3",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 140,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54421001,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "L45593-K810-C160",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 160,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54421001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "2126759005",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 160,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54421001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2500268-5",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 160,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54421001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2409706-4",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 160,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54422001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "1-2476833-0",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 160,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 0,
+		.fw_ver.minor             = 7,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54422001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "2178123001",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 160,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 1,
+		.fw_ver.minor             = 5,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54423001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2476833-3",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 200,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 0,
+		.fw_ver.minor             = 7,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54423001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "2178123003",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 200,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 1,
+		.fw_ver.minor             = 5,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54424001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2476833-8",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 225,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 0,
+		.fw_ver.minor             = 7,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54424001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "2178123004",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 225,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 1,
+		.fw_ver.minor             = 5,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54425001,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "L45593-K810-C120",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 120,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54425001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "2126759003",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 120,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54425001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2500268-3",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 120,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54425001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2409706-2",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 120,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54426001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2476833-4",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 250,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 0,
+		.fw_ver.minor             = 7,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54426001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "2178123005",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 250,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 1,
+		.fw_ver.minor             = 5,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54427001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2476833-9",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 275,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 0,
+		.fw_ver.minor             = 7,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54427001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "2178123006",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 275,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 1,
+		.fw_ver.minor             = 5,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54428001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "2178123007",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 300,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 1,
+		.fw_ver.minor             = 5,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54428001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2476833-5",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 300,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 0,
+		.fw_ver.minor             = 7,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54429001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "1-2476833-1",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 400,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 0,
+		.fw_ver.minor             = 7,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54429001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "2178123008",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 400,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 1,
+		.fw_ver.minor             = 5,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54430001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "1-2476833-2",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 500,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 0,
+		.fw_ver.minor             = 7,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54430001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "2178123009",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 500,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 1,
+		.fw_ver.minor             = 5,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54431001,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "L45593-K814-C80",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 80,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54431001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "3039169001",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 80,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54431001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2493257-1",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 80,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54431001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2459248-1",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 80,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54432001,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "L45593-K814-C120",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 120,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54432001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "3039169003",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 120,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54432001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2493257-3",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 120,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54432001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2459248-3",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 120,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54433001,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "L45593-K814-C160",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 160,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54433001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "3039169005",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 160,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54433001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2493257-5",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 160,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54433001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2459248-5",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 160,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54434001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "3026491001",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 160,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 1,
+		.fw_ver.minor             = 5,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54434001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2480871-1",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 160,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 0,
+		.fw_ver.minor             = 7,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54435001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "3026491003",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 200,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 1,
+		.fw_ver.minor             = 5,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54435001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2480871-3",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 200,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 0,
+		.fw_ver.minor             = 7,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54436001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "3026491004",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 225,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 1,
+		.fw_ver.minor             = 5,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54436001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2480871-4",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 225,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 0,
+		.fw_ver.minor             = 7,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54437001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "3026491008",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 400,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 1,
+		.fw_ver.minor             = 5,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54437001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2480871-8",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 400,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 0,
+		.fw_ver.minor             = 7,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54438001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "3026491009",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 500,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 1,
+		.fw_ver.minor             = 5,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54438001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2480871-9",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 500,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 0,
+		.fw_ver.minor             = 7,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54439001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2477317-1",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 500,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 4,
+		.fw_ver.minor             = 5,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54439001,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "FCBN8X0QE2C05-CU", /* manually truncated 1 char */
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 500,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 0,
+		.fw_ver.minor             = 18,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54439001,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DMQ8821-EC05-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 500,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 3,
+		.fw_ver.minor             = 1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54440001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "1-2477317-2",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 10000,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 4,
+		.fw_ver.minor             = 5,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54440001,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "FCBN8X0QE2C100-C", /* manually truncated 1 char */
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 10000,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 0,
+		.fw_ver.minor             = 18,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54440001,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DMQ8821-ECA0-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 10000,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 3,
+		.fw_ver.minor             = 1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54442001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "1-2477317-0",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 5000,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 4,
+		.fw_ver.minor             = 5,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54442001,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "FCBN8X0QE2C50-CU", /* manually truncated 1 char */
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 5000,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 0,
+		.fw_ver.minor             = 18,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54442001,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DMQ8821-EC50-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 5000,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 3,
+		.fw_ver.minor             = 1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54443001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "1-2477317-1",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 7500,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 4,
+		.fw_ver.minor             = 5,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54443001,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "FCBN8X0QE2C75-CU",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 7500,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 0,
+		.fw_ver.minor             = 18,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54443001,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DMQ8821-EC75-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 7500,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 3,
+		.fw_ver.minor             = 1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54444001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2477317-7",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 3000,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 4,
+		.fw_ver.minor             = 5,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54444001,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "FCBN8X0QE2C30-CU", /* manually truncated 1 char */
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 3000,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 0,
+		.fw_ver.minor             = 18,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54444001,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DMQ8821-EC30-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 3000,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 3,
+		.fw_ver.minor             = 1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54445001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2477317-6",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 2500,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 4,
+		.fw_ver.minor             = 5,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54445001,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "FCBN8X0QE2C25-CU",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 2500,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 0,
+		.fw_ver.minor             = 18,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54445001,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DMQ8821-EC25-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 2500,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 3,
+		.fw_ver.minor             = 1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54446001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2477317-5",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 1900,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 4,
+		.fw_ver.minor             = 5,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54446001,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "FCBN8X0QE2C19-CU",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 1900,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 0,
+		.fw_ver.minor             = 18,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54446001,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DMQ8821-EC19-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 1900,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 3,
+		.fw_ver.minor             = 1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54447001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2477317-8",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 3500,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 4,
+		.fw_ver.minor             = 5,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54447001,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "FCBN8X0QE2C35-CU",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 3500,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 0,
+		.fw_ver.minor             = 18,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54447001,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DMQ8821-EC35-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 3500,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 3,
+		.fw_ver.minor             = 1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54455001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "3026491005",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 250,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 1,
+		.fw_ver.minor             = 5,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54455001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2480871-5",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 250,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 0,
+		.fw_ver.minor             = 7,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54456001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "3026491006",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 275,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 1,
+		.fw_ver.minor             = 5,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54456001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2480871-6",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 275,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 0,
+		.fw_ver.minor             = 7,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54457001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "3026491007",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 300,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 1,
+		.fw_ver.minor             = 5,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54457001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2480871-7",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 300,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 0,
+		.fw_ver.minor             = 7,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54458001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2477317-2",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 700,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 4,
+		.fw_ver.minor             = 5,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54458001,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "FCBN8X0QE2C07-CU", /* manually truncated 1 char */
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 700,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 0,
+		.fw_ver.minor             = 18,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54458001,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DMQ8821-EC07-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 700,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 3,
+		.fw_ver.minor             = 1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54459001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2477317-3",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 1000,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 4,
+		.fw_ver.minor             = 5,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54459001,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "FCBN8X0QE2C10-CU",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 1000,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 0,
+		.fw_ver.minor             = 18,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54459001,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DMQ8821-EC10-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 1000,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 3,
+		.fw_ver.minor             = 1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54460001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2477317-4",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 1400,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 4,
+		.fw_ver.minor             = 5,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54460001,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "FCBN8X0QE2C14-CU",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 1400,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 0,
+		.fw_ver.minor             = 18,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54460001,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DMQ8821-EC14-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 1400,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 3,
+		.fw_ver.minor             = 1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54463001,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "L45593-K814-C140",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 140,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54463001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "3039169004",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 140,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54463001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2493257-4",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 140,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54463001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2459248-4",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 140,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54473001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2477317-9",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 4000,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 4,
+		.fw_ver.minor             = 5,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54473001,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "FCBN8X0QE2C40-CU",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 4000,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 0,
+		.fw_ver.minor             = 18,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 54473001,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DMQ8821-EC40-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 4000,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 3,
+		.fw_ver.minor             = 1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 58327001,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "L45593-K810-C100",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 100,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 58327001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "2126759002",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 100,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 58327001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2500268-2",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 100,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 58327001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2409706-6",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 100,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 58328001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2476833-7",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 180,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 0,
+		.fw_ver.minor             = 7,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 58328001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "2178123002",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 180,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 1,
+		.fw_ver.minor             = 5,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 58665001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2480871-2",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 180,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 0,
+		.fw_ver.minor             = 7,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 58665001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "3026491002",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 180,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 1,
+		.fw_ver.minor             = 5,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 58666001,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "L45593-K814-C100",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 100,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 58666001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "3039169002",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 100,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 58666001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2493257-2",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 100,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 58666001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2459248-2",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 100,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 65068001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2495759-1",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 500,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 4,
+		.fw_ver.minor             = 5,
+		.fw_ver.split_major       = 4,
+		.fw_ver.split_minor       = 5,
+	},
+	{
+		.hpe_pn                   = 65068001,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "FCBN9X0QE2C05-CU",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 500,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 0,
+		.fw_ver.minor             = 18,
+		.fw_ver.split_major       = 0,
+		.fw_ver.split_minor       = 15,
+	},
+	{
+		.hpe_pn                   = 65068001,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DME8821-EC05-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 500,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 3,
+		.fw_ver.minor             = 1,
+		.fw_ver.split_major       = 3,
+		.fw_ver.split_minor       = 1,
+	},
+	{
+		.hpe_pn                   = 65070001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2495759-2",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 700,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 4,
+		.fw_ver.minor             = 5,
+		.fw_ver.split_major       = 4,
+		.fw_ver.split_minor       = 5,
+	},
+	{
+		.hpe_pn                   = 65070001,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "1", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 700,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 0,
+		.fw_ver.minor             = 18,
+		.fw_ver.split_major       = 0,
+		.fw_ver.split_minor       = 15,
+	},
+	{
+		.hpe_pn                   = 65070001,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "2", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 700,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 3,
+		.fw_ver.minor             = 1,
+		.fw_ver.split_major       = 3,
+		.fw_ver.split_minor       = 1,
+	},
+	{
+		.hpe_pn                   = 65072001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2495759-3",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 1000,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 4,
+		.fw_ver.minor             = 5,
+		.fw_ver.split_major       = 4,
+		.fw_ver.split_minor       = 5,
+	},
+	{
+		.hpe_pn                   = 65072001,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "FCBN9X0QE2C10-CU",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 1000,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 0,
+		.fw_ver.minor             = 18,
+		.fw_ver.split_major       = 0,
+		.fw_ver.split_minor       = 15,
+	},
+	{
+		.hpe_pn                   = 65072001,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DME8821-EC10-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 1000,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 3,
+		.fw_ver.minor             = 1,
+		.fw_ver.split_major       = 3,
+		.fw_ver.split_minor       = 1,
+	},
+	{
+		.hpe_pn                   = 66805001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2495759-5",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 3000,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 4,
+		.fw_ver.minor             = 5,
+		.fw_ver.split_major       = 4,
+		.fw_ver.split_minor       = 5,
+	},
+	{
+		.hpe_pn                   = 66805001,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "FCBN9X0QE2C30-CU",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 3000,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 0,
+		.fw_ver.minor             = 18,
+		.fw_ver.split_major       = 0,
+		.fw_ver.split_minor       = 15,
+	},
+	{
+		.hpe_pn                   = 66805001,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DME8821-EC30-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 3000,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 3,
+		.fw_ver.minor             = 1,
+		.fw_ver.split_major       = 3,
+		.fw_ver.split_minor       = 1,
+	},
+	{
+		.hpe_pn                   = 72814001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2499036-1",
+		.type                     = SL_MEDIA_TYPE_POC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 0,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_200G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 72814001,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "LMQ8611-PC+",
+		.type                     = SL_MEDIA_TYPE_POC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 0,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_200G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 72814001,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "FTCC8612E2PCM",
+		.type                     = SL_MEDIA_TYPE_POC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 0,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_200G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 72815001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2499038-1",
+		.type                     = SL_MEDIA_TYPE_POC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 0,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 72815001,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "LMQ8811-PC+",
+		.type                     = SL_MEDIA_TYPE_POC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 0,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 72815001,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "FTCD8613E2PCM-1A",
+		.type                     = SL_MEDIA_TYPE_POC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 0,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 79382001,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DMQ8621-QC05",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 500,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 3,
+		.fw_ver.minor             = 1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 79383001,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DMQ8621-QC07",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 700,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 3,
+		.fw_ver.minor             = 1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 80489001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2499037-1",
+		.type                     = SL_MEDIA_TYPE_POC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 0,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 80489001,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "3", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_POC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 0,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 80489001,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "4", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_POC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 0,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 80490001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2499039-1",
+		.type                     = SL_MEDIA_TYPE_POC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 0,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 80490001,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "5", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_POC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 0,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 82013001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2495759-1",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 500,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 4,
+		.fw_ver.minor             = 5,
+		.fw_ver.split_major       = 4,
+		.fw_ver.split_minor       = 5,
+	},
+	{
+		.hpe_pn                   = 82013001,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "FCBN9X0QE2C05-CU",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 500,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 0,
+		.fw_ver.minor             = 18,
+		.fw_ver.split_major       = 0,
+		.fw_ver.split_minor       = 15,
+	},
+	{
+		.hpe_pn                   = 82013001,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DME8821-EC05-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 500,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = 3,
+		.fw_ver.minor             = 1,
+		.fw_ver.split_major       = 3,
+		.fw_ver.split_minor       = 1,
+	},
+	{
+		.hpe_pn                   = 101792700,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "L45593-K410-D75",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 80,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101792700,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2370728-1",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 80,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101792701,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "L45593-K410-D115",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 120,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101792701,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2370728-2",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 120,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101792702,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "L45593-K410-D142",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 140,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101792702,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2370728-3",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 140,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101792703,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "L45593-K410-D164",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 160,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101792703,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2370728-4",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 160,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101792704,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "L45593-K410-C191",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 190,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101792704,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2370728-5",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 190,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101792705,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "L45593-K410-C213",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 210,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101792705,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2370728-6",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 210,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101792706,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "L45593-K410-C239",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 229,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101792706,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2370728-7",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 229,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101792707,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "L45593-K410-C262",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 260,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101792707,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2370728-8",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 260,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101792708,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "L45593-K410-C299",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 290,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101792708,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2370728-9",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 290,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101793100,
+		.vendor                   = SL_MEDIA_VENDOR_CLOUD_LIGHT,
+		.vendor_pn_str            = "7123-G11-05",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 500,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101793100,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DMQ8811A-EC05-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 500,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101793101,
+		.vendor                   = SL_MEDIA_VENDOR_CLOUD_LIGHT,
+		.vendor_pn_str            = "7123-G11-07",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 700,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101793101,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DMQ8811A-EC07-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 700,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101793102,
+		.vendor                   = SL_MEDIA_VENDOR_CLOUD_LIGHT,
+		.vendor_pn_str            = "7123-G11-10",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 1000,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101793102,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DMQ8811A-EC10-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 1000,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101793103,
+		.vendor                   = SL_MEDIA_VENDOR_CLOUD_LIGHT,
+		.vendor_pn_str            = "7123-G11-14",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 1400,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101793103,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DMQ8811A-EC14-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 1400,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101793104,
+		.vendor                   = SL_MEDIA_VENDOR_CLOUD_LIGHT,
+		.vendor_pn_str            = "7123-G11-19",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 1900,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101793104,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DMQ8811A-EC19-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 1900,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101793105,
+		.vendor                   = SL_MEDIA_VENDOR_CLOUD_LIGHT,
+		.vendor_pn_str            = "7123-G11-25",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 2500,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101793105,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DMQ8811A-EC25-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 2500,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101793106,
+		.vendor                   = SL_MEDIA_VENDOR_CLOUD_LIGHT,
+		.vendor_pn_str            = "7123-G11-35",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 3500,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101793106,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DMQ8811A-EC35-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 3500,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101793107,
+		.vendor                   = SL_MEDIA_VENDOR_CLOUD_LIGHT,
+		.vendor_pn_str            = "7123-G11-50",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 5000,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101793107,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DMQ8811A-EC50-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 5000,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101793108,
+		.vendor                   = SL_MEDIA_VENDOR_CLOUD_LIGHT,
+		.vendor_pn_str            = "7123-G11-75",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 7500,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101793108,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DMQ8811A-EC75-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 7500,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101793109,
+		.vendor                   = SL_MEDIA_VENDOR_CLOUD_LIGHT,
+		.vendor_pn_str            = "7123-G11-A0",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 10000,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101793109,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DMQ8811A-ECAO-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 10000,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101798700,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "FCBN950QE1C04-CY",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 400,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101798700,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DME8811-DC04-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 400,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101798705,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "FCBN950QE1C10-CY",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 1000,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101798705,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DME8811-DC10-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 1000,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101821100,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "FCBNX50QE1C05-CU",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 500,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101821101,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "FCBNX50QE1C07-CU",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 700,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 101821102,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "FCBNX50QE1C10-CU",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_BIFURCATED,
+		.length_cm                = 1000,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102234300,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "L45593-K210-D40",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 40,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102234300,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "1-2333532-0",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 40,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102234301,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "L45593-K210-D75",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 80,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102234301,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2333532-1",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 80,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102234302,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "L45593-K210-D115",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 120,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102234302,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2333532-2",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 120,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102234303,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "L45593-K210-D142",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 140,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102234303,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2333532-3",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 140,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102234304,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "L45593-K210-D164",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 160,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102234304,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2333532-4",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 160,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102234305,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "L45593-K210-C191",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 190,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102234305,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2333532-5",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 190,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102234306,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "L45593-K210-C213",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 210,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102234306,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2333532-6",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 210,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102234307,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "L45593-K210-C239",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 240,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102234307,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2333532-7",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 240,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102234308,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "L45593-K210-C262",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 260,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102234308,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2333532-8",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 260,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102234309,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "L45593-K210-C299",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 290,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102234309,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2333532-9",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 290,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102234600,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "L45593-K310-D100",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 100,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102234600,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2333542-4",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 100,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102234601,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "L45593-K310-D150",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 150,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102234601,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2333542-2",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 150,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102234602,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "L45593-K310-C200",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 200,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102234602,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2333542-1",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 200,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102234603,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "L45593-K310-C250",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 250,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102234603,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2333542-3",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 250,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102234604,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "L45593-K310-C300",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 300,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102234604,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2333542-5",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 300,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102253300,
+		.vendor                   = SL_MEDIA_VENDOR_CLOUD_LIGHT,
+		.vendor_pn_str            = "7123-G12-05",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 500,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102253300,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "FCBN850QE1C05-CY",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 500,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102253300,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DMQ8811-EC05-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 500,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102253301,
+		.vendor                   = SL_MEDIA_VENDOR_CLOUD_LIGHT,
+		.vendor_pn_str            = "7123-G12-07",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 700,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102253301,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "FCBN850QE1C07-CY",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 700,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102253301,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DMQ8811-EC07-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 700,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102253302,
+		.vendor                   = SL_MEDIA_VENDOR_CLOUD_LIGHT,
+		.vendor_pn_str            = "7123-G12-10",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 1000,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102253302,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "FCBN850QE1C10-CY",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 1000,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102253302,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DMQ8811-EC10-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 1000,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102253303,
+		.vendor                   = SL_MEDIA_VENDOR_CLOUD_LIGHT,
+		.vendor_pn_str            = "7123-G12-14",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 1400,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102253303,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "FCBN850QE1C14-CY",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 1400,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102253303,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DMQ8811-EC14-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 1400,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102253304,
+		.vendor                   = SL_MEDIA_VENDOR_CLOUD_LIGHT,
+		.vendor_pn_str            = "7123-G12-19",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 1900,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102253304,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "FCBN850QE1C19-CY",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 1900,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102253304,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DMQ8811-EC19-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 1900,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102253305,
+		.vendor                   = SL_MEDIA_VENDOR_CLOUD_LIGHT,
+		.vendor_pn_str            = "7123-G12-25",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 2500,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102253305,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "FCBN850QE1C25-CY",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 2500,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102253305,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DMQ8811-EC25-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 2500,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102253306,
+		.vendor                   = SL_MEDIA_VENDOR_CLOUD_LIGHT,
+		.vendor_pn_str            = "7123-G12-35",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 3500,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102253306,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "FCBN850QE1C35-CY",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 3500,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102253306,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DMQ8811-EC35-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 3500,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102253307,
+		.vendor                   = SL_MEDIA_VENDOR_CLOUD_LIGHT,
+		.vendor_pn_str            = "7123-G12-50",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 5000,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102253307,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "FCBN850QE1C50-CY",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 5000,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102253307,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DMQ8811-EC50-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 5000,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102253308,
+		.vendor                   = SL_MEDIA_VENDOR_CLOUD_LIGHT,
+		.vendor_pn_str            = "7123-G12-75",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 7500,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102253308,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "FCBN850QE1C75-CY",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 7500,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102253308,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DMQ8811-EC75-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 7500,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102253309,
+		.vendor                   = SL_MEDIA_VENDOR_CLOUD_LIGHT,
+		.vendor_pn_str            = "7123-G12-A0",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 10000,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102253309,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "FCBN850QE1CX0-CY",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 10000,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102253309,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DMQ8811-ECA0-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 10000,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102443300,
+		.vendor                   = SL_MEDIA_VENDOR_CLOUD_LIGHT,
+		.vendor_pn_str            = "8363-K2-2004",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 400,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102443300,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DME8811A-EC04-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 400,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102443305,
+		.vendor                   = SL_MEDIA_VENDOR_CLOUD_LIGHT,
+		.vendor_pn_str            = "8363-K2-2010",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 1000,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 102443305,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "DME8811A-EC10-CR",
+		.type                     = SL_MEDIA_TYPE_AOC,
+		.shape                    = SL_MEDIA_SHAPE_SPLITTER,
+		.length_cm                = 1000,
+		.is_supported_ss200_cable = true,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_400G,
+		.serdes_settings.pre1     = -12,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = -4,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 85091001,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "L45593-L884-C80",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 80,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 85091001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "2111661508",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 80,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 85091001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2505170-1",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 80,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 85092001,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "L45593-L884-C100",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 100,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 85092001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "6", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 100,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 85092001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2505170-2",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 100,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 85093001,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "L45593-L884-C120",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 120,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 85093001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "7", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 120,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 85093001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2505170-3",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 120,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 85094001,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "L45593-L884-C140",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 140,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 85094001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "8", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 140,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 85094001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2505170-4",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 140,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 85095001,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "L45593-L884-C160",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 160,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 85095001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "2111663516",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 160,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 85095001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2505170-5",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 160,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 85096001,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "9", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 180,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 85096001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "2111664518",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 180,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 85096001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2505170-6",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 180,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 85097001,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "10", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 200,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 85097001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "2111664520",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 200,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 85097001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2505170-7",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 200,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 85098001,
+		.vendor                   = SL_MEDIA_VENDOR_BIZLINK,
+		.vendor_pn_str            = "11", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 220,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 85098001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "2111664220",
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 220,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 85098001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "12", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_PEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 220,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = 0,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 100,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 86997001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "13", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 160,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 86997001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "14", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 160,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 86998001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "2253619502",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 180,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 86998001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "15", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 180,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 86999001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "16", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 200,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 86999001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "17", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 200,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 87000001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "18", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 225,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 87000001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "19", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 225,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 87001001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "2253619505",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 250,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 87001001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "20", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 250,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 87002001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "21", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 275,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 87002001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "22", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 275,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 87003001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "2253619507",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 300,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 87003001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "23", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 300,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 87004001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "24", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 400,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 87004001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "25", /* manually_numbered */
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 400,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 87005001,
+		.vendor                   = SL_MEDIA_VENDOR_MOLEX,
+		.vendor_pn_str            = "2253619509",
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 500,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 87005001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "26", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_AEC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 500,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 87655001,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "27", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_POC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 0,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 87655001,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "28", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_POC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 0,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 87655001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2499365-1",
+		.type                     = SL_MEDIA_TYPE_POC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 0,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 87656001,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "2486895-1",
+		.type                     = SL_MEDIA_TYPE_POC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 0,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 87656001,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "2486895-1",
+		.type                     = SL_MEDIA_TYPE_POC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 0,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 87656001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2486895-1",
+		.type                     = SL_MEDIA_TYPE_POC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 0,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 88993001,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "29", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_POC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 0,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 88993001,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "30", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_POC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 0,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 88993001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "31", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_POC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 0,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 89361001,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "32", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_POC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 0,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 89361001,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "33", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_POC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 0,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 89361001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "2506674-1",
+		.type                     = SL_MEDIA_TYPE_POC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 0,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 90105001,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "FTCE8627E1PCA",
+		.type                     = SL_MEDIA_TYPE_POC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 0,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 90105001,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "34", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_POC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 0,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 90105001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "35", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_POC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 0,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 93284001,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "36", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_POC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 0,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 93284001,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "37", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_POC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 0,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 93284001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "38", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_POC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 0,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 93284001,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "39", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_POC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 0,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 93284001,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "40", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_POC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 0,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 93284001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "41", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_POC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 0,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 93285001,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "42", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_POC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 0,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 93285001,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "43", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_POC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 0,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 93285001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "44", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_POC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 0,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 93286001,
+		.vendor                   = SL_MEDIA_VENDOR_FINISAR,
+		.vendor_pn_str            = "45", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_POC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 0,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 93286001,
+		.vendor                   = SL_MEDIA_VENDOR_HISENSE,
+		.vendor_pn_str            = "46", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_POC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 0,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+	{
+		.hpe_pn                   = 93286001,
+		.vendor                   = SL_MEDIA_VENDOR_TE,
+		.vendor_pn_str            = "47", /* manually numbered */
+		.type                     = SL_MEDIA_TYPE_POC,
+		.shape                    = SL_MEDIA_SHAPE_STRAIGHT,
+		.length_cm                = 0,
+		.is_supported_ss200_cable = false,
+		.max_speed                = SL_MEDIA_SPEEDS_SUPPORT_CK_800G,
+		.serdes_settings.pre1     = -4,
+		.serdes_settings.pre2     = 0,
+		.serdes_settings.pre3     = 0,
+		.serdes_settings.cursor   = 98,
+		.serdes_settings.post1    = 0,
+		.serdes_settings.post2    = 0,
+		.fw_ver.major             = -1,
+		.fw_ver.minor             = -1,
+		.fw_ver.split_major       = -1,
+		.fw_ver.split_minor       = -1,
+	},
+};
+
+#endif /* _SL_MEDIA_DATA_CABLE_DB_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/media/data/sl_media_data_cable_db_ops.h b/drivers/net/ethernet/hpe/sl/media/data/sl_media_data_cable_db_ops.h
new file mode 100644
index 000000000000..e86471b8deb8
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/media/data/sl_media_data_cable_db_ops.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2024,2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_MEDIA_DATA_CABLE_DB_OPS_H_
+#define _SL_MEDIA_DATA_CABLE_DB_OPS_H_
+
+struct sl_media_attr;
+struct sl_media_jack;
+
+int sl_media_data_cable_db_ops_cable_validate(struct sl_media_attr *media_attr, struct sl_media_jack *media_jack);
+int sl_media_data_cable_db_ops_serdes_settings_get(struct sl_media_jack *media_jack, u32 media_type, u32 flags);
+
+#endif /* _SL_MEDIA_DATA_CABLE_DB_OPS_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/media/data/sl_media_data_jack.h b/drivers/net/ethernet/hpe/sl/media/data/sl_media_data_jack.h
new file mode 100644
index 000000000000..ce4d648c604a
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/media/data/sl_media_data_jack.h
@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2022,2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_MEDIA_DATA_JACK_H_
+#define _SL_MEDIA_DATA_JACK_H_
+
+#include "sl_media_lgrp.h"
+#include "sl_media_ldev.h"
+#include "sl_media_jack.h"
+
+/*
+ * These states reflect the state of media attr for both real and fake cables
+ */
+#define CABLE_MEDIA_ATTR_REMOVED  0
+#define CABLE_MEDIA_ATTR_ADDED    1
+#define CABLE_MEDIA_ATTR_STASHED  2
+
+void                  sl_media_data_jack_del(u8 ldev_num, u8 jack_num);
+int                   sl_media_data_jack_new(struct sl_media_ldev *media_ldev, u8 jack_num);
+struct sl_media_jack *sl_media_data_jack_get(u8 ldev_num, u8 jack_num);
+
+void sl_media_data_jack_unregister_event_notifier(void);
+void sl_media_data_cable_serdes_settings_clr(struct sl_media_jack *media_jack);
+void sl_media_data_jack_eeprom_clr(struct sl_media_jack *media_jack);
+void sl_media_data_jack_cable_state_clr(struct sl_media_jack *media_jack);
+int  sl_media_data_jack_media_attr_set(struct sl_media_jack *media_jack,
+				       struct sl_media_lgrp_cable_info *cable_info, struct sl_media_attr *media_attr);
+void sl_media_data_jack_media_attr_clr(struct sl_media_jack *media_jack,
+				       struct sl_media_lgrp_cable_info *cable_info);
+bool sl_media_data_jack_media_is_format_cmis(struct sl_media_jack *media_jack);
+
+void sl_media_data_jack_cable_if_present_send(struct sl_media_lgrp *media_lgrp);
+void sl_media_data_jack_cable_if_not_present_send(struct sl_media_lgrp *media_lgrp);
+
+int  sl_media_data_jack_cable_high_power_set(struct sl_media_jack *media_jack);
+int  sl_media_data_jack_cable_low_power_set(struct sl_media_jack *media_jack);
+int  sl_media_data_jack_cable_hw_shift_state_get(struct sl_media_jack *media_jack);
+int  sl_media_data_jack_cable_downshift(struct sl_media_jack *media_jack);
+int  sl_media_data_jack_cable_upshift(struct sl_media_jack *media_jack);
+
+int  sl_media_data_jack_scan(u8 ldev_num);
+int  sl_media_data_jack_lgrp_connect(struct sl_media_lgrp *media_lgrp);
+
+int  sl_media_data_jack_fake_media_attr_set(struct sl_media_jack *media_jack,
+					    struct sl_media_lgrp_cable_info *cable_info, struct sl_media_attr *fake_media_attr);
+void sl_media_data_jack_fake_media_attr_clr(struct sl_media_jack *media_jack,
+					    struct sl_media_lgrp_cable_info *cable_info);
+
+int  sl_media_data_jack_online(void *hdl, u8 ldev_num, u8 jack_num);
+
+int  sl_media_data_jack_cable_soft_reset(struct sl_media_jack *media_jack);
+
+void sl_media_data_jack_led_set(struct sl_media_jack *media_jack);
+void sl_media_data_jack_headshell_led_set(struct sl_media_jack *media_jack, u8 jack_state);
+void sl_media_data_jack_cable_temp_state_init(struct sl_media_jack *media_jack);
+void sl_media_data_jack_cable_temp_state_set(struct sl_media_jack *media_jack, u8 temperature_state);
+int  sl_media_data_jack_cable_temp_state_get(struct sl_media_jack *media_jack, u8 *temperature_state);
+int  sl_media_data_jack_cable_temp_prev_state_get(struct sl_media_jack *media_jack, u8 *temperature_prev_state);
+int  sl_media_data_jack_cable_temp_hw_check(struct sl_media_jack *media_jack);
+bool sl_media_data_jack_cable_is_hot_client_ready(struct sl_media_jack *media_jack,
+						  struct sl_media_lgrp_cable_info *cable_info);
+bool sl_media_data_jack_cable_is_hot_notif_sent(struct sl_media_jack *media_jack,
+						struct sl_media_lgrp_cable_info *cable_info);
+bool sl_media_data_jack_cable_is_warm_client_ready(struct sl_media_jack *media_jack,
+						   struct sl_media_lgrp_cable_info *cable_info);
+bool sl_media_data_jack_cable_is_warm_notif_sent(struct sl_media_jack *media_jack,
+						 struct sl_media_lgrp_cable_info *cable_info);
+bool sl_media_data_jack_cable_is_cold_client_ready(struct sl_media_jack *media_jack,
+						   struct sl_media_lgrp_cable_info *cable_info);
+bool sl_media_data_jack_cable_is_cold_notif_sent(struct sl_media_jack *media_jack,
+						 struct sl_media_lgrp_cable_info *cable_info);
+int  sl_media_data_jack_cable_temp_get(struct sl_media_jack *media_jack, u8 *temp);
+int  sl_media_data_jack_cable_temp_warn_limit_get(struct sl_media_jack *media_jack, u8 *temp_warn_limit_c);
+int  sl_media_data_jack_cable_temp_down_limit_get(struct sl_media_jack *media_jack, u8 *temp_down_limit_c);
+void sl_media_data_jack_cable_hot_notif_send(struct sl_media_jack *media_jack);
+void sl_media_data_jack_cable_warm_notif_send(struct sl_media_jack *media_jack);
+void sl_media_data_jack_cable_cold_notif_send(struct sl_media_jack *media_jack);
+void sl_media_data_jack_cable_hot_notif_sent_set(struct sl_media_jack *media_jack,
+						 struct sl_media_lgrp_cable_info *cable_info, bool value);
+void sl_media_data_jack_cable_warm_notif_sent_set(struct sl_media_jack *media_jack,
+						  struct sl_media_lgrp_cable_info *cable_info, bool value);
+void sl_media_data_jack_cable_cold_notif_sent_set(struct sl_media_jack *media_jack,
+						  struct sl_media_lgrp_cable_info *cable_info, bool value);
+void sl_media_data_jack_cable_temp_monitor_start(struct sl_media_ldev *media_ldev);
+void sl_media_data_jack_cable_temp_monitor_stop(struct sl_media_ldev *media_ldev);
+
+#define SL_MEDIA_JACK_HEADSHELL_BUSY 1
+#define SL_MEDIA_JACK_HEADSHELL_IDLE 0
+void sl_media_data_jack_headshell_busy_set(struct sl_media_jack *media_jack, int value);
+bool sl_media_data_jack_is_headshell_busy(struct sl_media_jack *media_jack);
+
+#endif /* _SL_MEDIA_DATA_JACK_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/media/data/sl_media_data_ldev.h b/drivers/net/ethernet/hpe/sl/media/data/sl_media_data_ldev.h
new file mode 100644
index 000000000000..ad9a3c5ec23c
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/media/data/sl_media_data_ldev.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_MEDIA_DATA_LDEV_H_
+#define _SL_MEDIA_DATA_LDEV_H_
+
+#include <linux/types.h>
+
+struct sl_media_ldev;
+struct sl_uc_ops;
+struct sl_uc_accessor;
+
+int                   sl_media_data_ldev_new(u8 ldev_num, struct workqueue_struct *workqueue);
+void                  sl_media_data_ldev_del(u8 ldev_num);
+struct sl_media_ldev *sl_media_data_ldev_get(u8 ldev_num);
+
+int sl_media_data_ldev_uc_ops_set(u8 ldev_num, struct sl_uc_ops *uc_ops,
+				  struct sl_uc_accessor *uc_accessor);
+
+#endif /* _SL_MEDIA_DATA_LDEV_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/media/data/sl_media_data_lgrp.h b/drivers/net/ethernet/hpe/sl/media/data/sl_media_data_lgrp.h
new file mode 100644
index 000000000000..3bedf2501ad7
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/media/data/sl_media_data_lgrp.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_MEDIA_DATA_LGRP_H_
+#define _SL_MEDIA_DATA_LGRP_H_
+
+struct sl_media_lgrp;
+
+int                   sl_media_data_lgrp_new(u8 ldev_num, u8 lgrp_num);
+void                  sl_media_data_lgrp_del(u8 ldev_num, u8 lgrp_num);
+struct sl_media_lgrp *sl_media_data_lgrp_get(u8 ldev_num, u8 lgrp_num);
+
+void                  sl_media_data_lgrp_connect_id_set(struct sl_media_lgrp *lgrp, const char *connect_id);
+
+int                   sl_media_data_lgrp_err_trace_enable_set(struct sl_media_lgrp *media_lgrp,
+							      bool err_trace_enable);
+int                   sl_media_data_lgrp_warn_trace_enable_set(struct sl_media_lgrp *media_lgrp,
+							       bool warn_trace_enable);
+
+#endif
diff --git a/drivers/net/ethernet/hpe/sl/media/data/sl_media_data_lgrp_trace.h b/drivers/net/ethernet/hpe/sl/media/data/sl_media_data_lgrp_trace.h
new file mode 100644
index 000000000000..fd2fb11168f3
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/media/data/sl_media_data_lgrp_trace.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_MEDIA_DATA_LGRP_TRACE_H_
+#define _SL_MEDIA_DATA_LGRP_TRACE_H_
+
+#include "sl_media_lgrp.h"
+
+int sl_media_data_lgrp_is_err_trace_enabled(struct sl_media_lgrp *media_lgrp, bool *err_trace_enable);
+int sl_media_data_lgrp_is_warn_trace_enabled(struct sl_media_lgrp *media_lgrp, bool *warn_trace_enable);
+
+#endif /* _SL_MEDIA_DATA_LGRP_TRACE_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/media/sl_media_io.h b/drivers/net/ethernet/hpe/sl/media/sl_media_io.h
new file mode 100644
index 000000000000..ab45d90e29de
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/media/sl_media_io.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2024,2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_MEDIA_IO_H_
+#define _SL_MEDIA_IO_H_
+
+#include "linux/types.h"
+
+struct sl_media_jack;
+
+int sl_media_io_write8(struct sl_media_jack *media_jack, u8 page, u8 offset, u8 data);
+int sl_media_io_read8(struct sl_media_jack *media_jack, u8 page, u8 offset, u8 *data);
+int sl_media_io_read(struct sl_media_jack *media_jack, u8 page, u8 offset, u8 *data, size_t len);
+
+void sl_media_io_led_set(struct sl_media_jack *media_jack, u8 led_pattern);
+
+#endif /* _SL_MEDIA_IO_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/media/sl_media_jack.h b/drivers/net/ethernet/hpe/sl/media/sl_media_jack.h
new file mode 100644
index 000000000000..b71912797492
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/media/sl_media_jack.h
@@ -0,0 +1,319 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2024-2026 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_MEDIA_JACK_H_
+#define _SL_MEDIA_JACK_H_
+
+#include <linux/completion.h>
+#include <linux/spinlock.h>
+#include <linux/wait.h>
+#include <linux/time64.h>
+#include <linux/atomic.h>
+
+#include <linux/hpe/sl/sl_media.h>
+
+#include "sl_asic.h"
+#include "sl_media_ldev.h"
+#include "sl_ctrl_media_counters.h"
+/*
+ * These states reflect whether a physical module is inserted in
+ * a jack or not. And if it is inserted, can it be talked to or not.
+ */
+#define SL_MEDIA_JACK_CABLE_REMOVED          1
+#define SL_MEDIA_JACK_CABLE_INSERTED         2
+#define SL_MEDIA_JACK_CABLE_GOING_ONLINE     3
+#define SL_MEDIA_JACK_CABLE_ONLINE           4
+#define SL_MEDIA_JACK_CABLE_ERROR            5
+
+/*
+ * GAUI interface is for AEC/AOC and GBASE interface is for PEC
+ */
+#define SL_MEDIA_SS1_HOST_INTERFACE_50GAUI_1_C2M     0x0A
+#define SL_MEDIA_SS1_HOST_INTERFACE_100GAUI_2_C2M    0x0D
+#define SL_MEDIA_SS2_HOST_INTERFACE_100GAUI_1_L_C2M  0x4C
+#define SL_MEDIA_SS1_HOST_INTERFACE_200GAUI_4_C2M    0x0F
+#define SL_MEDIA_SS2_HOST_INTERFACE_200GAUI_2_S_C2M  0x4D
+#define SL_MEDIA_SS2_HOST_INTERFACE_400GAUI_4_S_C2M  0x4F
+#define SL_MEDIA_SS1_HOST_INTERFACE_400GAUI_4_L_C2M  0x50 /* SS1 AOC/AEC default */
+#define SL_MEDIA_SS2_HOST_INTERFACE_800GAUI_8_S_C2M  0x51 /* SS2 AOC/AEC default */
+#define SL_MEDIA_SS1_HOST_INTERFACE_CAUI_4_C2M       0x41 /* BJ mode */
+#define SL_MEDIA_SS1_HOST_INTERFACE_50GBASE_CR       0x18
+#define SL_MEDIA_SS1_HOST_INTERFACE_100GBASE_CR2     0x1B
+#define SL_MEDIA_SS2_HOST_INTERFACE_100GBASE_CR1     0x46
+#define SL_MEDIA_SS1_HOST_INTERFACE_200GBASE_CR4     0x1C
+#define SL_MEDIA_SS2_HOST_INTERFACE_200GBASE_CR2     0x47
+#define SL_MEDIA_SS1_HOST_INTERFACE_400GBASE_CR8     0x1D /* SS1 PEC default */
+#define SL_MEDIA_SS2_HOST_INTERFACE_400GBASE_CR4     0x48
+#define SL_MEDIA_SS2_HOST_INTERFACE_800GBASE_CR8     0x49 /* SS2 PEC default */
+
+/*
+ * These states reflect the state of cable shifting for active cables.
+ * For non-active cables, the cable shift state always reflects "invalid"
+ */
+#define SL_MEDIA_JACK_CABLE_SHIFT_STATE_UPSHIFTED           1
+#define SL_MEDIA_JACK_CABLE_SHIFT_STATE_DOWNSHIFTED         2
+#define SL_MEDIA_JACK_CABLE_SHIFT_STATE_FAILED_NO_CABLE     3
+#define SL_MEDIA_JACK_CABLE_SHIFT_STATE_FAILED_FAKE_CABLE   4
+#define SL_MEDIA_JACK_CABLE_SHIFT_STATE_FAILED_NO_SUPPORT   5
+#define SL_MEDIA_JACK_CABLE_SHIFT_STATE_FAILED_CHECK        6
+#define SL_MEDIA_JACK_CABLE_SHIFT_STATE_FAILED_UPSHIFT      7
+#define SL_MEDIA_JACK_CABLE_SHIFT_STATE_FAILED_DOWNSHIFT    8
+#define SL_MEDIA_JACK_CABLE_SHIFT_STATE_NOTSHIFTED          9
+
+/*
+ * These states reflect the state of cable shifting in the hardware.
+ * These states might be different than driver states since hardware
+ * state can change while driver is not loaded
+ */
+#define SL_MEDIA_JACK_CABLE_HW_SHIFT_STATE_UPSHIFTED   1
+#define SL_MEDIA_JACK_CABLE_HW_SHIFT_STATE_DOWNSHIFTED 2
+#define SL_MEDIA_JACK_CABLE_HW_SHIFT_STATE_UNKNOWN     3
+#define SL_MEDIA_JACK_CABLE_HW_SHIFT_IO_ERROR          4
+
+#define SL_MEDIA_JACK_CABLE_HOT_ALARM_MASK BIT(0) /* TempMonHighAlarmFlag */
+
+#define SL_MEDIA_JACK_ATTR_ERR_STR_SIZE 128
+
+enum sl_media_jack_temp_state {
+	SL_MEDIA_JACK_TEMP_STATE_INIT = 0,
+	SL_MEDIA_JACK_TEMP_STATE_COLD,
+	SL_MEDIA_JACK_TEMP_STATE_WARM,
+	SL_MEDIA_JACK_TEMP_STATE_HOT,
+	SL_MEDIA_JACK_TEMP_STATE_UNKNOWN,
+};
+
+enum sl_media_jack_dp_state {
+	SL_MEDIA_JACK_DP_STATE_DEACTIVATED = 1,
+	SL_MEDIA_JACK_DP_STATE_INIT,
+	SL_MEDIA_JACK_DP_STATE_DEINIT,
+	SL_MEDIA_JACK_DP_STATE_ACTIVATED,
+	SL_MEDIA_JACK_DP_STATE_TX_TURN_ON,
+	SL_MEDIA_JACK_DP_STATE_TX_TURN_OFF,
+	SL_MEDIA_JACK_DP_STATE_INITIALIZED,
+};
+
+enum sl_media_jack_lane_data_read_state {
+	SL_MEDIA_JACK_LANE_DATA_READ_STATE_IDLE = 0,
+	SL_MEDIA_JACK_LANE_DATA_READ_STATE_BUSY,
+};
+
+struct sl_media_jack_signal {
+	struct {
+		u8 los_map;
+		u8 lol_map;
+	} tx;
+	struct {
+		u8 los_map;
+		u8 lol_map;
+	} rx;
+};
+
+struct sl_media_jack_lane_data {
+	u8                          dp_states[4];
+	u8                          dp_states_changed;
+	struct sl_media_jack_signal signal;
+};
+
+struct sl_media_serdes_settings {
+	s16 pre1;
+	s16 pre2;
+	s16 pre3;
+	s16 cursor;
+	s16 post1;
+	s16 post2;
+	s16 media;
+};
+
+struct sl_media_cable_attr {
+	u32                             type;
+	u32                             vendor;
+	char                            vendor_pn_str[SL_MEDIA_VENDOR_PN_SIZE];
+	u32                             length_cm;
+	u32                             hpe_pn;      /* HPE part number */
+	u32                             max_speed;
+	u32                             shape;
+	bool                            is_supported_ss200_cable;
+
+	struct sl_media_serdes_settings serdes_settings;
+
+	struct {
+		s8 major;
+		s8 minor;
+		s8 split_major;
+		s8 split_minor;
+	} fw_ver;
+};
+
+struct sl_media_lgrp_cable_info {
+	u8                   ldev_num;
+	u8                   lgrp_num;
+
+	struct sl_media_attr media_attr;
+	struct sl_media_attr stashed_media_attr;
+
+	int                  real_cable_status;
+	int                  fake_cable_status;
+
+	bool                 hot_client_ready;
+	bool                 hot_notif_sent;
+	bool                 warm_client_ready;
+	bool                 warm_notif_sent;
+	bool                 cold_client_ready;
+	bool                 cold_notif_sent;
+};
+
+#define SL_MEDIA_EEPROM_PAGE_SIZE 256
+#define SL_MEDIA_JACK_MAGIC       0xAD91C879
+struct sl_media_jack {
+	u32                             magic;
+	u8                              num;
+	u8                              physical_num; /* number printed on jack */
+	u8                              state;
+	struct sl_media_ldev           *media_ldev;
+
+	int                             cable_db_idx;
+	struct sl_media_lgrp_cable_info cable_info[SL_MEDIA_MAX_LGRPS_PER_JACK];
+	u32                             cable_end;
+
+	u8                              eeprom_page0[SL_MEDIA_EEPROM_PAGE_SIZE];
+	u8                              eeprom_page1[SL_MEDIA_EEPROM_PAGE_SIZE];
+
+	struct sl_media_serdes_settings serdes_settings;
+
+	spinlock_t                      data_lock; /* data lock for jack object */
+	spinlock_t                      log_lock;  /* log lock for jack object  */
+
+	bool                            is_cable_unsupported;
+	bool                            is_cable_format_unsupported;
+	bool                            is_supported_ss200_cable;
+	bool                            is_high_powered;
+	u8                              temperature_state;
+	u8                              temperature_prev_state;
+	unsigned long                   cable_high_power_wait_time_end;
+	u32                             fault_cause;
+	time64_t                        fault_time;
+	u8                              cable_shift_state;
+	u8                              appsel_num_200_gaui; /* used for downshifting */
+	u8                              lane_count_200_gaui; /* used for downshifting */
+	u8                              host_interface_200_gaui; /* used for downshifting */
+	u8                              appsel_num_400_gaui; /* used for upshifting */
+	u8                              lane_count_400_gaui; /* used for upshifting */
+	u8                              host_interface_400_gaui; /* used for upshifting */
+
+	atomic_t                        is_headshell_busy;
+
+	struct {
+		u32               read_state;
+		u32               read_generation;
+		wait_queue_head_t read_wait;
+		int               last_read_rtn;
+		struct {
+			struct sl_media_jack_lane_data data;
+			time64_t                       timestamp_s;
+			bool                           cached;
+		} cache;
+	} lane_data;
+
+	void                           *hdl;
+	u8                              port_count;
+	u16                             asic_port[4];
+	u32                             status;
+
+	int                             temperature_value_c;
+	int                             temperature_warn_limit_c;
+	int                             temperature_down_limit_c;
+
+	struct sl_ctrl_media_counter   *cause_counters;
+};
+
+#define SL_MEDIA_FAULT_CAUSE_NONE                              0
+#define SL_MEDIA_FAULT_CAUSE_EEPROM_FORMAT_UNSUPPORTED         BIT(0)
+#define SL_MEDIA_FAULT_CAUSE_EEPROM_VENDOR_UNSUPPORTED         BIT(1)
+#define SL_MEDIA_FAULT_CAUSE_EEPROM_JACK_IO                    BIT(2)
+#define SL_MEDIA_FAULT_CAUSE_ONLINE_STATUS_GET                 BIT(3)
+#define SL_MEDIA_FAULT_CAUSE_ONLINE_TIMEDOUT                   BIT(4)
+#define SL_MEDIA_FAULT_CAUSE_ONLINE_JACK_IO                    BIT(5)
+#define SL_MEDIA_FAULT_CAUSE_ONLINE_JACK_GET                   BIT(6)
+#define SL_MEDIA_FAULT_CAUSE_SERDES_SETTINGS_GET               BIT(7)
+#define SL_MEDIA_FAULT_CAUSE_SCAN_STATUS_GET                   BIT(8)
+#define SL_MEDIA_FAULT_CAUSE_SCAN_HDL_GET                      BIT(9)
+#define SL_MEDIA_FAULT_CAUSE_SCAN_JACK_GET                     BIT(10)
+#define SL_MEDIA_FAULT_CAUSE_MEDIA_ATTR_SET                    BIT(11)
+#define SL_MEDIA_FAULT_CAUSE_INTR_EVENT_JACK_IO                BIT(12)
+#define SL_MEDIA_FAULT_CAUSE_POWER_SET                         BIT(13)
+#define SL_MEDIA_FAULT_CAUSE_SHIFT_DOWN_JACK_IO                BIT(14)
+#define SL_MEDIA_FAULT_CAUSE_SHIFT_DOWN_JACK_IO_LOW_POWER_SET  BIT(15)
+#define SL_MEDIA_FAULT_CAUSE_SHIFT_DOWN_JACK_IO_HIGH_POWER_SET BIT(16)
+#define SL_MEDIA_FAULT_CAUSE_SHIFT_UP_JACK_IO                  BIT(17)
+#define SL_MEDIA_FAULT_CAUSE_SHIFT_UP_JACK_IO_LOW_POWER_SET    BIT(18)
+#define SL_MEDIA_FAULT_CAUSE_SHIFT_UP_JACK_IO_HIGH_POWER_SET   BIT(19)
+#define SL_MEDIA_FAULT_CAUSE_SHIFT_STATE_JACK_IO               BIT(20)
+#define SL_MEDIA_FAULT_CAUSE_OFFLINE                           BIT(21)
+#define SL_MEDIA_FAULT_CAUSE_HOT                               BIT(22)
+#define SL_MEDIA_FAULT_CAUSE_WARM                              BIT(23)
+
+int                   sl_media_jack_new(struct sl_media_ldev *media_ldev, u8 jack_num);
+void                  sl_media_jack_del(u8 ldev_num, u8 jack_num);
+struct sl_media_jack *sl_media_jack_get(u8 ldev_num, u8 jack_num);
+void                  sl_media_jack_state_set(struct sl_media_jack *media_jack, u8 state);
+int                   sl_media_jack_state_get(struct sl_media_jack *media_jack, u8 *state);
+int                   sl_media_jack_cable_end_get(struct sl_media_jack *media_jack, u8 *cable_end);
+bool                  sl_media_jack_is_high_powered(struct sl_media_jack *media_jack);
+void                  sl_media_jack_cable_shift_state_set(struct sl_media_jack *media_jack, u8 state);
+int                   sl_media_jack_cable_shift_state_get(struct sl_media_jack *media_jack, u8 *cable_shift_state);
+bool                  sl_media_jack_is_cable_online(struct sl_media_jack *media_jack);
+bool                  sl_media_jack_is_cable_format_unsupported(struct sl_media_jack *media_jack);
+
+int sl_media_jack_active_cable_200g_host_interface_get(struct sl_media_jack *media_jack, u8 *host_interface_200_gaui);
+int sl_media_jack_active_cable_200g_appsel_num_get(struct sl_media_jack *media_jack, u8 *appsel_num_200_gaui);
+int sl_media_jack_active_cable_200g_lane_count_get(struct sl_media_jack *media_jack, u8 *lane_count_200_gaui);
+int sl_media_jack_active_cable_400g_host_interface_get(struct sl_media_jack *media_jack, u8 *host_interface_400_gaui);
+int sl_media_jack_active_cable_400g_appsel_num_get(struct sl_media_jack *media_jack, u8 *appsel_num_400_gaui);
+int sl_media_jack_active_cable_400g_lane_count_get(struct sl_media_jack *media_jack, u8 *lane_count_400_gaui);
+
+int  sl_media_jack_cable_high_power_set(u8 ldev_num, u8 jack_num);
+int  sl_media_jack_cable_downshift(u8 ldev_num, u8 lgrp_num, u8 link_num);
+int  sl_media_jack_cable_upshift(u8 ldev_num, u8 lgrp_num, u8 link_num);
+void sl_media_jack_fault_cause_set(struct sl_media_jack *media_jack, u32 fault_cause);
+int  sl_media_jack_fault_cause_get(struct sl_media_jack *media_jack, u32 *fault_cause,
+				   time64_t *fault_time);
+
+int  sl_media_jack_cable_temp_state_get(struct sl_media_jack *media_jack, u8 *temperature_state);
+int  sl_media_jack_cable_temp_prev_state_get(struct sl_media_jack *media_jack, u8 *temperature_prev_state);
+int  sl_media_jack_cable_temp_get(u8 ldev_num, u8 lgrp_num, u8 *temp);
+int  sl_media_jack_cable_temp_warn_limit_get(u8 ldev_num, u8 lgrp_num, u8 *temp_warn_limit_c);
+int  sl_media_jack_cable_temp_down_limit_get(u8 ldev_num, u8 lgrp_num, u8 *temp_down_limit_c);
+int  sl_media_jack_cable_temp_hw_check(struct sl_media_jack *media_jack);
+void sl_media_jack_cable_hot_notif_send(struct sl_media_jack *media_jack);
+void sl_media_jack_cable_warm_notif_send(struct sl_media_jack *media_jack);
+void sl_media_jack_cable_cold_notif_send(struct sl_media_jack *media_jack);
+void sl_media_jack_cable_hot_notif_sent_set(struct sl_media_jack *media_jack,
+					    struct sl_media_lgrp_cable_info *cable_info, bool value);
+void sl_media_jack_cable_warm_notif_sent_set(struct sl_media_jack *media_jack,
+					     struct sl_media_lgrp_cable_info *cable_info, bool value);
+void sl_media_jack_cable_cold_notif_sent_set(struct sl_media_jack *media_jack,
+					     struct sl_media_lgrp_cable_info *cable_info, bool value);
+
+const char *sl_media_fault_cause_str(u32 fault_cause);
+const char *sl_media_temp_state_str(u8 temperature_state);
+
+int  sl_media_jack_cable_low_power_set(struct sl_media_jack *media_jack);
+
+void sl_media_jack_led_set(u8 ldev_num, u8 lgrp_num);
+
+int sl_media_jack_cable_insert(u8 ldev_num, u8 lgrp_num, u8 jack_num,
+			       u8 *eeprom_page0, u8 *eeprom_page1, u32 flags);
+int sl_media_jack_cable_remove(u8 ldev_num, u8 lgrp_num, u8 jack_num);
+
+int  sl_media_jack_fake_cable_insert(u8 ldev_num, u8 lgrp_num, struct sl_media_attr *media_attr);
+void sl_media_jack_fake_cable_remove(u8 ldev_num, u8 lgrp_num);
+
+int sl_media_jack_signal_get(u8 ldev_num, u8 lgrp_num, u8 serdes_lane_map, struct sl_media_jack_signal *media_signal);
+int sl_media_jack_signal_cache_time_s_get(u8 ldev_num, u8 lgrp_num, time64_t *cache_time);
+int sl_media_jack_signal_cache_get(u8 ldev_num, u8 lgrp_num, u8 serdes_lane_map,
+				   struct sl_media_jack_signal *media_signal);
+
+int sl_media_jack_attr_error_map_str(unsigned long error_map, char *error_str, unsigned int error_str_size);
+int sl_media_jack_attr_error_map_get(struct sl_media_jack *media_jack, u32 *error_map);
+
+#endif /* _SL_MEDIA_JACK_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/media/sl_media_ldev.h b/drivers/net/ethernet/hpe/sl/media/sl_media_ldev.h
new file mode 100644
index 000000000000..e575e8bdd634
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/media/sl_media_ldev.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2024,2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_MEDIA_LDEV_H_
+#define _SL_MEDIA_LDEV_H_
+
+#include <linux/types.h>
+#include <linux/workqueue.h>
+
+#include "base/sl_media_work.h"
+
+#define SL_MEDIA_LDEV_MAGIC 0x736c4D44
+
+struct sl_uc_ops;
+struct sl_uc_accessor;
+
+struct sl_media_ldev {
+	u32                      magic;
+	u8                       num;
+	struct delayed_work      delayed_work[SL_MEDIA_WORK_COUNT];
+	struct sl_uc_ops        *uc_ops;
+	struct sl_uc_accessor   *uc_accessor;
+	struct workqueue_struct *workqueue;
+};
+
+int                   sl_media_ldev_new(u8 ldev_num, struct workqueue_struct *workqueue);
+void                  sl_media_ldev_del(u8 ldev_num);
+struct sl_media_ldev *sl_media_ldev_get(u8 ldev_num);
+
+int sl_media_ldev_uc_ops_set(u8 ldev_num, struct sl_uc_ops *uc_ops,
+			     struct sl_uc_accessor *uc_accessor);
+
+#endif /* _SL_MEDIA_LDEV_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/media/sl_media_lgrp.h b/drivers/net/ethernet/hpe/sl/media/sl_media_lgrp.h
new file mode 100644
index 000000000000..8b0ca1930819
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/media/sl_media_lgrp.h
@@ -0,0 +1,99 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023-2026 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_MEDIA_LGRP_H_
+#define _SL_MEDIA_LGRP_H_
+
+#include <linux/spinlock.h>
+#include <linux/kobject.h>
+
+#include <linux/hpe/sl/sl_media.h>
+
+#include "sl_lgrp.h"
+#include "sl_media_ldev.h"
+#include "base/sl_media_log.h"
+
+#define SL_MEDIA_MAX_SUPPORTED_SPEEDS 8
+
+struct sl_media_serdes_settings;
+
+struct sl_media_lgrp_speed_kobject {
+	struct sl_media_lgrp *media_lgrp;
+	u32                   speed;
+	struct kobject        kobj;
+};
+
+#define SL_MEDIA_LGRP_MAGIC 0x736c4D47
+struct sl_media_lgrp {
+	u32                                 magic;
+	u8                                  num;
+	struct sl_media_ldev               *media_ldev;
+
+	struct sl_media_jack               *media_jack;
+	struct sl_media_lgrp_cable_info    *cable_info;
+
+	struct kobject                      kobj;
+	struct kobject                      parent_speed_kobj;
+	struct sl_media_lgrp_speed_kobject  speeds_kobj[SL_MEDIA_MAX_SUPPORTED_SPEEDS];
+	struct kobject                      counters_kobj;
+	u8                                  supported_speeds_num;
+	bool                                speeds_kobj_init;
+
+	spinlock_t                          log_lock;
+	char                                connect_id[SL_LOG_CONNECT_ID_LEN + 1];
+
+	spinlock_t                          data_lock;
+	bool                                err_trace_enable;
+	bool                                warn_trace_enable;
+};
+
+int                   sl_media_lgrp_new(u8 ldev_num, u8 lgrp_num);
+void                  sl_media_lgrp_del(u8 ldev_num, u8 lgrp_num);
+struct sl_media_lgrp *sl_media_lgrp_get(u8 ldev_num, u8 lgrp_num);
+
+void sl_media_lgrp_connect_id_set(u8 ldev_num, u8 lgrp_num, const char *connect_id);
+
+void sl_media_lgrp_real_cable_if_present_send(u8 ldev_num, u8 lgrp_num);
+void sl_media_lgrp_real_cable_if_not_present_send(u8 ldev_num, u8 lgrp_num);
+void sl_media_lgrp_cable_hot_send(u8 ldev_num, u8 lgrp_num);
+void sl_media_lgrp_cable_warm_send(u8 ldev_num, u8 lgrp_num);
+void sl_media_lgrp_cable_cold_send(u8 ldev_num, u8 lgrp_num);
+void sl_media_lgrp_cable_temp_flags_clr(u8 ldev_num, u8 lgrp_num);
+void sl_media_lgrp_hot_client_ready_set(u8 ldev_num, u8 lgrp_num, bool value);
+void sl_media_lgrp_warm_client_ready_set(u8 ldev_num, u8 lgrp_num, bool value);
+void sl_media_lgrp_cold_client_ready_set(u8 ldev_num, u8 lgrp_num, bool value);
+
+void sl_media_lgrp_media_attr_get(u8 ldev_num, u8 lgrp_num, struct sl_media_attr *media_attr);
+bool sl_media_lgrp_media_has_error(struct sl_media_lgrp *media_lgrp);
+
+static inline bool SL_MEDIA_LGRP_MEDIA_TYPE_IS_ACTIVE(u32 type)
+{
+	return (type == SL_MEDIA_TYPE_AEC ||
+		type == SL_MEDIA_TYPE_ACC ||
+		type == SL_MEDIA_TYPE_AOC ||
+		type == SL_MEDIA_TYPE_POC);
+}
+
+bool sl_media_lgrp_media_type_is_active(u8 ldev_num, u8 lgrp_num);
+
+void sl_media_lgrp_media_serdes_settings_get(u8 ldev_num, u8 lgrp_num,
+					     struct sl_media_serdes_settings *media_serdes_settings);
+
+int  sl_media_lgrp_vendor_get(struct sl_media_lgrp *media_lgrp, u32 *vendor);
+int  sl_media_lgrp_vendor_pn_str_get(struct sl_media_lgrp *media_lgrp, char *vendor_pn_str);
+int  sl_media_lgrp_type_get(struct sl_media_lgrp *media_lgrp, u32 *type);
+int  sl_media_lgrp_shape_get(struct sl_media_lgrp *media_lgrp, u32 *shape);
+int  sl_media_lgrp_length_get(struct sl_media_lgrp *media_lgrp, u32 *length_cm);
+int  sl_media_lgrp_max_speed_get(struct sl_media_lgrp *media_lgrp, u32 *max_speed);
+int  sl_media_lgrp_serial_num_str_get(struct sl_media_lgrp *media_lgrp, char *serial_num_str);
+int  sl_media_lgrp_hpe_pn_str_get(struct sl_media_lgrp *media_lgrp, char *hpe_pn_str);
+int  sl_media_lgrp_jack_type_get(struct sl_media_lgrp *media_lgrp, u32 *jack_type);
+int  sl_media_lgrp_jack_type_qsfp_density_get(struct sl_media_lgrp *media_lgrp, u32 *density);
+int  sl_media_lgrp_furcation_get(struct sl_media_lgrp *media_lgrp, u32 *furcation);
+bool sl_media_lgrp_is_cable_unsupported(struct sl_media_lgrp *media_lgrp);
+int  sl_media_lgrp_date_code_str_get(struct sl_media_lgrp *media_lgrp, char *date_code_str);
+int  sl_media_lgrp_fw_ver_str_get(struct sl_media_lgrp *media_lgrp, u8 *fw_ver);
+
+bool sl_media_lgrp_is_signal_status_supported(u8 ldev_num, u8 lgrp_num);
+
+#endif /* _SL_MEDIA_LGRP_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/nic/sl_asic.h b/drivers/net/ethernet/hpe/sl/nic/sl_asic.h
new file mode 100644
index 000000000000..185e76b326af
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/nic/sl_asic.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_ASIC_H_
+#define _SL_ASIC_H_
+
+#include "sl_asic_csrs.h"
+
+#define PORT_PML_CFG_PORT_GROUP	SS2_PORT_PML_CFG_PORT_GROUP
+
+#define PLATFORM_ASIC   C_PLATFORM_ASIC
+#define PLATFORM_NETSIM C_PLATFORM_NETSIM
+#define PLATFORM_Z1     C_PLATFORM_Z1
+
+#define SL_MAX_SERDES_LANES 4
+
+#define SL_ASIC_MAX_LDEVS  16
+#define SL_ASIC_MAX_LGRPS  1
+#define SL_ASIC_MAX_LINKS  1
+#define SL_ASIC_MAX_LANES  4
+#define SL_ASIC_MAX_SERDES 1
+
+#define SL_MEDIA_MAX_JACK_NUM          1
+#define SL_MEDIA_MAX_LGRPS_PER_JACK    1
+#define SL_MEDIA_LGRPS_PER_PORT        1
+#define SL_MEDIA_LGRPS_DIVIDE_PER_PORT 0
+
+#define SL_SERDES_NUM_MICROS    2
+#define SL_SERDES_ACTIVE_MICROS (BIT(1) | BIT(0))
+#define SL_SERDES_NUM_PLLS      1
+#define SL_SERDES_NUM_LANES     4
+
+#define PLATFORM_NIC (SL_MAX_SERDES_LANES == 4)
+
+#endif /* _SL_ASIC_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/nic/sl_asic_csrs.h b/drivers/net/ethernet/hpe/sl/nic/sl_asic_csrs.h
new file mode 100644
index 000000000000..1f8b9feba660
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/nic/sl_asic_csrs.h
@@ -0,0 +1,215 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_ASIC_CSRS_H_
+#define _SL_ASIC_CSRS_H_
+
+#include <uapi/ethernet/cassini_user_defs.h>
+
+//==============================================================================
+
+#define SL_CSR_MASK(_type, _bitfield) \
+	({                            \
+	uint64_t mask = 0;            \
+	union _type t = {0};          \
+	t._bitfield = -1;             \
+	mask = t.qw;                  \
+	mask;                         \
+	})
+#define SL_CSR_WORD_MASK(_type, _bitfield, _word) \
+	({                                        \
+	uint64_t mask = 0;                        \
+	union _type t = {0};                      \
+	t._bitfield = -1;                         \
+	mask = t.qw[_word];                       \
+	mask;                                     \
+	})
+#define SL_CSR_SHIFT(_type, _bitfield)     \
+	({                                 \
+	int lsb = 0;                       \
+	union _type t = {0};               \
+	t._bitfield = 1;                   \
+	while (((t.qw >> lsb) & 1) == 0) { \
+		lsb++;                     \
+	}                                  \
+	lsb;                               \
+	})
+#define SL_CSR_WORD_SHIFT(_type, _bitfield, _word)  \
+	({                                          \
+	int lsb = 0;                                \
+	union _type t = {0};                        \
+	t._bitfield = 1;                            \
+	while (((t.qw[_word] >> lsb) & 1) == 0) {   \
+		lsb++;                              \
+	}                                           \
+	lsb;                                        \
+	})
+
+#define SL_CSR_SET(value, _type, _bitfield) \
+	((((unsigned long long)(value)) << SL_CSR_SHIFT(_type, _bitfield)) & SL_CSR_MASK(_type, _bitfield))
+#define SL_CSR_UPDATE(val, value, _type, _bitfield) \
+	(((val) & (~SL_CSR_MASK(_type, _bitfield))) | SL_CSR_SET(value, _type, _bitfield))
+#define SL_CSR_GET(value, _type, _bitfield) \
+	(((value) & SL_CSR_MASK(_type, _bitfield)) >> SL_CSR_SHIFT(_type, _bitfield))
+#define SL_CSR_WORD_GET(value, _type, _bitfield, _word) \
+	(((value) & SL_CSR_WORD_MASK(_type, _bitfield, _word)) >> SL_CSR_WORD_SHIFT(_type, _bitfield, _word))
+
+//==============================================================================
+
+#define SS2_PORT_PML_CFG_PORT_GROUP_PG_CFG_UPDATE(a, b)                              SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_port_group, pg_cfg)
+
+#define SS2_PORT_PML_CFG_SUBPORT_RESET_WARM_RST_FROM_CSR_SET(a)                      SL_CSR_SET(a, ss2_port_pml_cfg_subport_reset, warm_rst_from_csr)
+
+#define SS2_PORT_PML_CFG_GENERAL_CLOCK_PERIOD_PS_UPDATE(a, b)                        SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_general, clock_period_ps)
+
+#define SS2_PORT_PML_CFG_LLR_CAPACITY_MAX_DATA_UPDATE(a, b)                          SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_llr_capacity, max_data)
+#define SS2_PORT_PML_CFG_LLR_CAPACITY_MAX_SEQ_UPDATE(a, b)                           SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_llr_capacity, max_seq)
+#define SS2_PORT_PML_CFG_LLR_SIZE_UPDATE(a, b)                                       SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_llr, size)
+#define SS2_PORT_PML_CFG_LLR_ACK_NACK_ERR_CHECK_UPDATE(a, b)                         SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_llr, ack_nack_err_check)
+#define SS2_PORT_PML_CFG_LLR_PREAMBLE_SEQ_CHECK_UPDATE(a, b)                         SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_llr, preamble_seq_check)
+#define SS2_PORT_PML_CFG_LLR_CF_RATES_LOOP_TIMING_PERIOD_UPDATE(a, b)                SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_llr_cf_rates, loop_timing_period)
+#define SS2_PORT_PML_CFG_LLR_CF_SMAC_CTL_FRAME_SMAC_UPDATE(a, b)                     SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_llr_cf_smac, ctl_frame_smac)
+#define SS2_PORT_PML_CFG_LLR_CF_ETYPE_CTL_FRAME_ETHERTYPE_UPDATE(a, b)               SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_llr_cf_etype, ctl_frame_ethertype)
+#define SS2_PORT_PML_CFG_LLR_SM_REPLAY_CT_MAX_GET(a)                                 SL_CSR_GET(a, ss2_port_pml_cfg_llr_sm, replay_ct_max)
+#define SS2_PORT_PML_CFG_LLR_SM_REPLAY_CT_MAX_UPDATE(a, b)                           SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_llr_sm, replay_ct_max)
+#define SS2_PORT_PML_CFG_LLR_SM_REPLAY_TIMER_MAX_UPDATE(a, b)                        SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_llr_sm, replay_timer_max)
+#define SS2_PORT_PML_CFG_LLR_SM_RETRY_THRESHOLD_UPDATE(a, b)                         SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_llr_sm, retry_threshold)
+#define SS2_PORT_PML_CFG_LLR_SM_ALLOW_RE_INIT_UPDATE(a, b)                           SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_llr_sm, allow_re_init)
+#define SS2_PORT_PML_CFG_LLR_SUBPORT_FILTER_LOSSLESS_WHEN_OFF_UPDATE(a, b)           SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_llr_subport, filter_lossless_when_off)
+#define SS2_PORT_PML_CFG_LLR_SUBPORT_MAX_STARVATION_LIMIT_UPDATE(a, b)               SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_llr_subport, max_starvation_limit)
+#define SS2_PORT_PML_CFG_LLR_SUBPORT_LINK_DOWN_BEHAVIOR_UPDATE(a, b)                 SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_llr_subport, link_down_behavior)
+#define SS2_PORT_PML_CFG_LLR_SUBPORT_MAC_IF_CREDITS_UPDATE(a, b)                     SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_llr_subport, mac_if_credits)
+#define SS2_PORT_PML_CFG_LLR_SUBPORT_FILTER_CTL_FRAMES_UPDATE(a, b)                  SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_llr_subport, filter_ctl_frames)
+#define SS2_PORT_PML_CFG_LLR_SUBPORT_ENABLE_LOOP_TIMING_UPDATE(a, b)                 SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_llr_subport, enable_loop_timing)
+#define SS2_PORT_PML_CFG_LLR_SUBPORT_LLR_MODE_UPDATE(a, b)                           SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_llr_subport, llr_mode)
+#define SS2_PORT_PML_CFG_LLR_TIMEOUTS_DATA_AGE_TIMER_MAX_UPDATE(a, b)                SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_llr_timeouts, data_age_timer_max)
+#define SS2_PORT_PML_CFG_LLR_TIMEOUTS_PCS_LINK_DN_TIMER_MAX_UPDATE(a, b)             SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_llr_timeouts, pcs_link_dn_timer_max)
+
+#define SS2_PORT_PML_CFG_PCS_ENABLE_AUTO_LANE_DEGRADE_GET(a)                         SL_CSR_GET(a, ss2_port_pml_cfg_pcs, enable_auto_lane_degrade)
+
+#define SS2_PORT_PML_CFG_PCS_AUTONEG_RESET_UPDATE(a, b)                              SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_pcs_autoneg, reset)
+#define SS2_PORT_PML_CFG_PCS_AUTONEG_RESTART_UPDATE(a, b)                            SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_pcs_autoneg, restart)
+#define SS2_PORT_PML_CFG_PCS_AUTONEG_NEXT_PAGE_LOADED_UPDATE(a, b)                   SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_pcs_autoneg, next_page_loaded)
+#define SS2_PORT_PML_CFG_PCS_ENABLE_AUTO_LANE_DEGRADE_UPDATE(a, b)                   SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_pcs, enable_auto_lane_degrade)
+#define SS2_PORT_PML_CFG_PCS_PCS_MODE_UPDATE(a, b)                                   SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_pcs, pcs_mode)
+#define SS2_PORT_PML_CFG_PCS_TIMESTAMP_SHIFT_UPDATE(a, b)                            SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_pcs, timestamp_shift)
+#define SS2_PORT_PML_CFG_PCS_SUBPORT_PCS_ENABLE_UPDATE(a, b)                         SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_pcs_subport, pcs_enable)
+#define SS2_PORT_PML_CFG_PCS_SUBPORT_ENABLE_AUTO_NEG_UPDATE(a, b)                    SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_pcs_subport, enable_auto_neg)
+
+#define SS2_PORT_PML_CFG_RX_PCS_SUBPORT_ENABLE_CTL_OS_UPDATE(a, b)                   SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_rx_pcs_subport, enable_ctl_os)
+#define SS2_PORT_PML_CFG_RX_PCS_SUBPORT_ENABLE_LOCK_UPDATE(a, b)                     SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_rx_pcs_subport, enable_lock)
+#define SS2_PORT_PML_CFG_RX_PCS_SUBPORT_ENABLE_RX_SM_UPDATE(a, b)                    SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_rx_pcs_subport, enable_rx_sm)
+#define SS2_PORT_PML_CFG_RX_PCS_SUBPORT_RS_MODE_UPDATE(a, b)                         SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_rx_pcs_subport, rs_mode)
+#define SS2_PORT_PML_CFG_RX_PCS_ACTIVE_LANES_GET(a)                                  SL_CSR_GET(a, ss2_port_pml_cfg_rx_pcs, active_lanes)
+#define SS2_PORT_PML_CFG_RX_PCS_ACTIVE_LANES_UPDATE(a, b)                            SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_rx_pcs, active_lanes)
+#define SS2_PORT_PML_CFG_RX_PCS_CW_GAP_544_UPDATE(a, b)                              SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_rx_pcs, cw_gap_544)
+#define SS2_PORT_PML_CFG_RX_PCS_RESTART_LOCK_ON_BAD_AMS_UPDATE(a, b)                 SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_rx_pcs, restart_lock_on_bad_ams)
+#define SS2_PORT_PML_CFG_RX_PCS_RESTART_LOCK_ON_BAD_CWS_UPDATE(a, b)                 SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_rx_pcs, restart_lock_on_bad_cws)
+#define SS2_PORT_PML_CFG_RX_PCS_ALLOW_AUTO_DEGRADE_UPDATE(a, b)                      SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_rx_pcs, allow_auto_degrade)
+#define SS2_PORT_PML_CFG_RX_PCS_LANE_0_SOURCE_UPDATE(a, b)                           SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_rx_pcs, lane_0_source)
+#define SS2_PORT_PML_CFG_RX_PCS_LANE_1_SOURCE_UPDATE(a, b)                           SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_rx_pcs, lane_1_source)
+#define SS2_PORT_PML_CFG_RX_PCS_LANE_2_SOURCE_UPDATE(a, b)                           SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_rx_pcs, lane_2_source)
+#define SS2_PORT_PML_CFG_RX_PCS_LANE_3_SOURCE_UPDATE(a, b)                           SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_rx_pcs, lane_3_source)
+
+#define SS2_PORT_PML_CFG_TX_PCS_SUBPORT_ENABLE_CTL_OS_UPDATE(a, b)                   SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_tx_pcs_subport, enable_ctl_os)
+#define SS2_PORT_PML_CFG_TX_PCS_CDC_READY_LEVEL_UPDATE(a, b)                         SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_tx_pcs, cdc_ready_level)
+#define SS2_PORT_PML_CFG_TX_PCS_EN_PK_BW_LIMITER_UPDATE(a, b)                        SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_tx_pcs, en_pk_bw_limiter)
+#define SS2_PORT_PML_CFG_TX_PCS_LANE_0_SOURCE_UPDATE(a, b)                           SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_tx_pcs, lane_0_source)
+#define SS2_PORT_PML_CFG_TX_PCS_LANE_1_SOURCE_UPDATE(a, b)                           SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_tx_pcs, lane_1_source)
+#define SS2_PORT_PML_CFG_TX_PCS_LANE_2_SOURCE_UPDATE(a, b)                           SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_tx_pcs, lane_2_source)
+#define SS2_PORT_PML_CFG_TX_PCS_LANE_3_SOURCE_UPDATE(a, b)                           SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_tx_pcs, lane_3_source)
+#define SS2_PORT_PML_CFG_TX_PCS_ALLOW_AUTO_DEGRADE_UPDATE(a, b)                      SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_tx_pcs, allow_auto_degrade)
+#define SS2_PORT_PML_CFG_TX_PCS_SUBPORT_GEARBOX_CREDITS_UPDATE(a, b)                 SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_tx_pcs_subport, gearbox_credits)
+
+#define SS2_PORT_PML_CFG_RX_MAC_FLIT_PACKING_CNT_UPDATE(a, b)                        SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_rx_mac, flit_packing_cnt)
+#define SS2_PORT_PML_CFG_RX_MAC_SUBPORT_MAC_OPERATIONAL_UPDATE(a, b)                 SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_rx_mac_subport, mac_operational)
+#define SS2_PORT_PML_CFG_RX_MAC_SUBPORT_MAC_OPERATIONAL_GET(a)                       SL_CSR_GET(a, ss2_port_pml_cfg_rx_mac_subport, mac_operational)
+#define SS2_PORT_PML_CFG_RX_MAC_SUBPORT_SHORT_PREAMBLE_UPDATE(a, b)                  SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_rx_mac_subport, short_preamble)
+
+#define SS2_PORT_PML_CFG_TX_MAC_IEEE_IFG_ADJUSTMENT_UPDATE(a, b)                     SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_tx_mac, ieee_ifg_adjustment)
+#define SS2_PORT_PML_CFG_TX_MAC_MAC_PAD_IDLE_THRESH_UPDATE(a, b)                     SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_tx_mac, mac_pad_idle_thresh)
+#define SS2_PORT_PML_CFG_TX_MAC_IFG_MODE_UPDATE(a, b)                                SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_tx_mac, ifg_mode)
+#define SS2_PORT_PML_CFG_TX_MAC_SUBPORT_MAC_OPERATIONAL_UPDATE(a, b)                 SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_tx_mac_subport, mac_operational)
+#define SS2_PORT_PML_CFG_TX_MAC_SUBPORT_MAC_OPERATIONAL_GET(a)                       SL_CSR_GET(a, ss2_port_pml_cfg_tx_mac_subport, mac_operational)
+#define SS2_PORT_PML_CFG_TX_MAC_SUBPORT_MAC_CDT_THRESH_UPDATE(a, b)                  SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_tx_mac_subport, mac_cdt_thresh)
+#define SS2_PORT_PML_CFG_TX_MAC_SUBPORT_MAC_CDT_INIT_VAL_UPDATE(a, b)                SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_tx_mac_subport, mac_cdt_init_val)
+#define SS2_PORT_PML_CFG_TX_MAC_SUBPORT_PCS_CREDITS_UPDATE(a, b)                     SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_tx_mac_subport, pcs_credits)
+#define SS2_PORT_PML_CFG_TX_MAC_SUBPORT_SHORT_PREAMBLE_UPDATE(a, b)                  SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_tx_mac_subport, short_preamble)
+
+#define SS2_PORT_PML_CFG_SERDES_RX_PMD_RX_LANE_MODE_UPDATE(a, b)                     SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_serdes_rx, pmd_rx_lane_mode)
+#define SS2_PORT_PML_CFG_SERDES_RX_PMD_RX_OSR_MODE_GET(a)                            SL_CSR_GET(a, ss2_port_pml_cfg_serdes_rx, pmd_rx_osr_mode)
+#define SS2_PORT_PML_CFG_SERDES_RX_PMD_RX_OSR_MODE_UPDATE(a, b)                      SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_serdes_rx, pmd_rx_osr_mode)
+#define SS2_PORT_PML_CFG_SERDES_RX_PMD_EXT_LOS_UPDATE(a, b)                          SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_serdes_rx, pmd_ext_los)
+#define SS2_PORT_PML_CFG_SERDES_RX_PMD_LN_RX_H_PWRDN_UPDATE(a, b)                    SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_serdes_rx, pmd_ln_rx_h_pwrdn)
+#define SS2_PORT_PML_CFG_SERDES_RX_PMD_LN_RX_DP_H_RSTB_UPDATE(a, b)                  SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_serdes_rx, pmd_ln_rx_dp_h_rstb)
+#define SS2_PORT_PML_CFG_SERDES_RX_PMD_LN_RX_H_RSTB_UPDATE(a, b)                     SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_serdes_rx, pmd_ln_rx_h_rstb)
+
+#define SS2_PORT_PML_CFG_SERDES_TX_PMD_TX_LANE_MODE_UPDATE(a, b)                     SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_serdes_tx, pmd_tx_lane_mode)
+#define SS2_PORT_PML_CFG_SERDES_TX_PMD_TX_OSR_MODE_UPDATE(a, b)                      SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_serdes_tx, pmd_tx_osr_mode)
+#define SS2_PORT_PML_CFG_SERDES_TX_PMD_TX_DISABLE_UPDATE(a, b)                       SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_serdes_tx, pmd_tx_disable)
+#define SS2_PORT_PML_CFG_SERDES_TX_PMD_LN_TX_H_PWRDN_UPDATE(a, b)                    SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_serdes_tx, pmd_ln_tx_h_pwrdn)
+#define SS2_PORT_PML_CFG_SERDES_TX_PMD_LN_TX_DP_H_RSTB_UPDATE(a, b)                  SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_serdes_tx, pmd_ln_tx_dp_h_rstb)
+#define SS2_PORT_PML_CFG_SERDES_TX_PMD_LN_TX_H_RSTB_UPDATE(a, b)                     SL_CSR_UPDATE(a, b, ss2_port_pml_cfg_serdes_tx, pmd_ln_tx_h_rstb)
+#define SS2_PORT_PML_CFG_SERDES_TX_PMD_TX_OSR_MODE_GET(a)                            SL_CSR_GET(a, ss2_port_pml_cfg_serdes_tx, pmd_tx_osr_mode)
+
+#define SS2_PORT_PML_STS_LLR_LOOP_TIME_LOOP_TIME_GET(a)                              SL_CSR_GET(a, ss2_port_pml_sts_llr_loop_time, loop_time)
+#define SS2_PORT_PML_STS_LLR_LLR_STATE_GET(a)                                        SL_CSR_GET(a, ss2_port_pml_sts_llr, llr_state)
+
+#define SS2_PORT_PML_STS_RX_PCS_SUBPORT_ALIGN_STATUS_GET(a)                          SL_CSR_GET(a, ss2_port_pml_sts_rx_pcs_subport, align_status)
+#define SS2_PORT_PML_STS_RX_PCS_SUBPORT_FAULT_GET(a)                                 SL_CSR_GET(a, ss2_port_pml_sts_rx_pcs_subport, fault)
+#define SS2_PORT_PML_STS_RX_PCS_SUBPORT_LOCAL_FAULT_GET(a)                           SL_CSR_GET(a, ss2_port_pml_sts_rx_pcs_subport, local_fault)
+#define SS2_PORT_PML_STS_RX_PCS_SUBPORT_HI_SER_GET(a)                                SL_CSR_GET(a, ss2_port_pml_sts_rx_pcs_subport, hi_ser)
+
+#define SS2_PORT_PML_STS_RX_PCS_AM_LOCK_AM_LOCK_GET(a)                               SL_CSR_GET(a, ss2_port_pml_sts_rx_pcs_am_lock, am_lock)
+
+#define SS2_PORT_PML_STS_PCS_AUTONEG_BASE_PAGE_LP_BASE_PAGE_GET(a)                   SL_CSR_GET(a, ss2_port_pml_sts_pcs_autoneg_base_page, lp_base_page)
+#define SS2_PORT_PML_STS_PCS_AUTONEG_BASE_PAGE_LP_ABILITY_GET(a)                     SL_CSR_GET(a, ss2_port_pml_sts_pcs_autoneg_base_page, lp_ability)
+#define SS2_PORT_PML_STS_PCS_AUTONEG_BASE_PAGE_BASE_PAGE_GET(a)                      SL_CSR_GET(a, ss2_port_pml_sts_pcs_autoneg_base_page, base_page)
+#define SS2_PORT_PML_STS_PCS_AUTONEG_BASE_PAGE_COMPLETE_GET(a)                       SL_CSR_GET(a, ss2_port_pml_sts_pcs_autoneg_base_page, complete)
+#define SS2_PORT_PML_STS_PCS_AUTONEG_BASE_PAGE_STATE_GET(a)                          SL_CSR_GET(a, ss2_port_pml_sts_pcs_autoneg_base_page, state)
+#define SS2_PORT_PML_STS_PCS_AUTONEG_NEXT_PAGE_LP_NEXT_PAGE_GET(a)                   SL_CSR_GET(a, ss2_port_pml_sts_pcs_autoneg_next_page, lp_next_page)
+#define SS2_PORT_PML_STS_PCS_AUTONEG_NEXT_PAGE_LP_ABILITY_GET(a)                     SL_CSR_GET(a, ss2_port_pml_sts_pcs_autoneg_next_page, lp_ability)
+#define SS2_PORT_PML_STS_PCS_AUTONEG_NEXT_PAGE_BASE_PAGE_GET(a)                      SL_CSR_GET(a, ss2_port_pml_sts_pcs_autoneg_next_page, base_page)
+#define SS2_PORT_PML_STS_PCS_AUTONEG_NEXT_PAGE_COMPLETE_GET(a)                       SL_CSR_GET(a, ss2_port_pml_sts_pcs_autoneg_next_page, complete)
+#define SS2_PORT_PML_STS_PCS_AUTONEG_NEXT_PAGE_STATE_GET(a)                          SL_CSR_GET(a, ss2_port_pml_sts_pcs_autoneg_next_page, state)
+
+#define SS2_PORT_PML_STS_PCS_LANE_DEGRADE_WORD0_LP_PLS_AVAILABLE_GET(a)              SL_CSR_WORD_GET(a, ss2_port_pml_sts_pcs_lane_degrade, lp_pls_available, 0)
+#define SS2_PORT_PML_STS_PCS_LANE_DEGRADE_WORD0_RX_PLS_AVAILABLE_GET(a)              SL_CSR_WORD_GET(a, ss2_port_pml_sts_pcs_lane_degrade, rx_pls_available, 0)
+
+#define SS2_PORT_PML_STS_SERDES_PMD_TX_DATA_VLD_GET(a)                               SL_CSR_GET(a, ss2_port_pml_sts_serdes, pmd_tx_data_vld)
+#define SS2_PORT_PML_STS_SERDES_PMD_TX_CLK_VLD_GET(a)                                SL_CSR_GET(a, ss2_port_pml_sts_serdes, pmd_tx_clk_vld)
+#define SS2_PORT_PML_STS_SERDES_PMD_RX_DATA_VLD_GET(a)                               SL_CSR_GET(a, ss2_port_pml_sts_serdes, pmd_rx_data_vld)
+#define SS2_PORT_PML_STS_SERDES_PMD_RX_CLK_VLD_GET(a)                                SL_CSR_GET(a, ss2_port_pml_sts_serdes, pmd_rx_clk_vld)
+#define SS2_PORT_PML_STS_SERDES_PMD_RX_LOCK_GET(a)                                   SL_CSR_GET(a, ss2_port_pml_sts_serdes, pmd_rx_lock)
+#define SS2_PORT_PML_STS_SERDES_PMD_SIGNAL_DETECTGET(a)                              SL_CSR_GET(a, ss2_port_pml_sts_serdes, pmd_signal_detect)
+
+#define SS2_PORT_PML_LINK_DN_BEHAVIOR_T_LD_DISCARD                                   C2_HNI_PML_LD_DISCARD
+#define SS2_PORT_PML_LINK_DN_BEHAVIOR_T_LD_BLOCK                                     C2_HNI_PML_LD_BLOCK
+#define SS2_PORT_PML_LINK_DN_BEHAVIOR_T_LD_BEST_EFFORT                               C2_HNI_PML_LD_BEST_EFFORT
+
+#define SS2_PORT_PML_ERR_INFO_PCS_TX_DP_TX_CDC_UNDERRUN_UPDATE(a, b)                 SL_CSR_UPDATE(a, b, ss2_port_pml_err_info_pcs_tx_dp, tx_cdc_underrun)
+
+#define SS2_PORT_PML_ERR_FLG_WORD1_PCS_TX_DEGRADE_FAILURE_GET(a)                     SL_CSR_WORD_GET(a, ss2_port_pml_err_flg, pcs_tx_degrade_failure, 1)
+#define SS2_PORT_PML_ERR_FLG_WORD1_PCS_RX_DEGRADE_FAILURE_GET(a)                     SL_CSR_WORD_GET(a, ss2_port_pml_err_flg, pcs_rx_degrade_failure, 1)
+
+#define SS2_PORT_PML_ERR_FLG_WORD1_LLR_REPLAY_AT_MAX_0_GET(a)                        SL_CSR_WORD_GET(a, ss2_port_pml_err_flg, llr_replay_at_max_0, 1)
+#define SS2_PORT_PML_ERR_FLG_WORD1_LLR_REPLAY_AT_MAX_1_GET(a)                        SL_CSR_WORD_GET(a, ss2_port_pml_err_flg, llr_replay_at_max_1, 1)
+#define SS2_PORT_PML_ERR_FLG_WORD1_LLR_REPLAY_AT_MAX_2_GET(a)                        SL_CSR_WORD_GET(a, ss2_port_pml_err_flg, llr_replay_at_max_2, 1)
+#define SS2_PORT_PML_ERR_FLG_WORD1_LLR_REPLAY_AT_MAX_3_GET(a)                        SL_CSR_WORD_GET(a, ss2_port_pml_err_flg, llr_replay_at_max_3, 1)
+
+#define SS2_PORT_PML_ERR_FLG_WORD1_PCS_LINK_DOWN_0_GET(a)                            SL_CSR_WORD_GET(a, ss2_port_pml_err_flg, pcs_link_down_0, 1)
+#define SS2_PORT_PML_ERR_FLG_WORD1_PCS_LINK_DOWN_1_GET(a)                            SL_CSR_WORD_GET(a, ss2_port_pml_err_flg, pcs_link_down_1, 1)
+#define SS2_PORT_PML_ERR_FLG_WORD1_PCS_LINK_DOWN_2_GET(a)                            SL_CSR_WORD_GET(a, ss2_port_pml_err_flg, pcs_link_down_2, 1)
+#define SS2_PORT_PML_ERR_FLG_WORD1_PCS_LINK_DOWN_3_GET(a)                            SL_CSR_WORD_GET(a, ss2_port_pml_err_flg, pcs_link_down_3, 1)
+
+#define SS2_PORT_PML_ERR_FLG_WORD1_PCS_LINK_DOWN_LF_0_GET(a)                         SL_CSR_WORD_GET(a, ss2_port_pml_err_flg, pcs_link_down_lf_0, 1)
+#define SS2_PORT_PML_ERR_FLG_WORD1_PCS_LINK_DOWN_LF_1_GET(a)                         SL_CSR_WORD_GET(a, ss2_port_pml_err_flg, pcs_link_down_lf_1, 1)
+#define SS2_PORT_PML_ERR_FLG_WORD1_PCS_LINK_DOWN_LF_2_GET(a)                         SL_CSR_WORD_GET(a, ss2_port_pml_err_flg, pcs_link_down_lf_2, 1)
+#define SS2_PORT_PML_ERR_FLG_WORD1_PCS_LINK_DOWN_LF_3_GET(a)                         SL_CSR_WORD_GET(a, ss2_port_pml_err_flg, pcs_link_down_lf_3, 1)
+
+#define SS2_PORT_PML_ERR_FLG_WORD1_PCS_LINK_DOWN_RF_0_GET(a)                         SL_CSR_WORD_GET(a, ss2_port_pml_err_flg, pcs_link_down_rf_0, 1)
+#define SS2_PORT_PML_ERR_FLG_WORD1_PCS_LINK_DOWN_RF_1_GET(a)                         SL_CSR_WORD_GET(a, ss2_port_pml_err_flg, pcs_link_down_rf_1, 1)
+#define SS2_PORT_PML_ERR_FLG_WORD1_PCS_LINK_DOWN_RF_2_GET(a)                         SL_CSR_WORD_GET(a, ss2_port_pml_err_flg, pcs_link_down_rf_2, 1)
+#define SS2_PORT_PML_ERR_FLG_WORD1_PCS_LINK_DOWN_RF_3_GET(a)                         SL_CSR_WORD_GET(a, ss2_port_pml_err_flg, pcs_link_down_rf_3, 1)
+
+#endif /* _SL_ASIC_CSRS_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/sl.h b/drivers/net/ethernet/hpe/sl/sl.h
new file mode 100644
index 000000000000..20e1c8e28e9f
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sl.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023-2026 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_H_
+#define _SL_H_
+
+#define SL_VERSION_MAJOR 1
+#define SL_VERSION_MINOR 33
+#define SL_VERSION_INC   43
+
+void  sl_version_get(int *major, int *minor, int *inc);
+char *sl_git_hash_str_get(void);
+
+#endif /* _SL_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/sl_ldev.h b/drivers/net/ethernet/hpe/sl/sl_ldev.h
new file mode 100644
index 000000000000..77375b37cc2e
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sl_ldev.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023,2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_LDEV_H_
+#define _SL_LDEV_H_
+
+struct sl_ldev_attr;
+
+#define SL_LDEV_MAGIC 0x736c636f
+#define SL_LDEV_VER   1
+struct sl_ldev {
+	u32 magic;
+	u32 ver;
+	u32 size;
+
+	u8  num;
+};
+
+int sl_ldev_attr_check(struct sl_ldev_attr *ldev_attr);
+
+void sl_ldev_init(void);
+int  sl_ldev_check(struct sl_ldev *ldev);
+void sl_ldev_exit(void);
+
+#endif /* _SL_LDEV_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/sl_lgrp.h b/drivers/net/ethernet/hpe/sl/sl_lgrp.h
new file mode 100644
index 000000000000..32e522d1fd41
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sl_lgrp.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_LGRP_H_
+#define _SL_LGRP_H_
+
+#define SL_LGRP_MAGIC 0x6c677270
+#define SL_LGRP_VER   2
+struct sl_lgrp {
+	u32 magic;
+	u32 ver;
+	u32 size;
+
+	u8  num;
+	u8  ldev_num;
+};
+
+void sl_lgrp_init(void);
+int  sl_lgrp_check(struct sl_lgrp *lgrp);
+
+#endif /* _SL_LGRP_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/sl_link.h b/drivers/net/ethernet/hpe/sl/sl_link.h
new file mode 100644
index 000000000000..152034e4e04f
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sl_link.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_LINK_H_
+#define _SL_LINK_H_
+
+#define SL_LINK_MAGIC 0x736c6c6b
+#define SL_LINK_VER   1
+struct sl_link {
+	u32 magic;
+	u32 ver;
+	u32 size;
+
+	u8  num;
+	u8  lgrp_num;
+	u8  ldev_num;
+};
+
+void sl_link_init(void);
+int  sl_link_check(struct sl_link *link);
+
+#endif /* _SL_LINK_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/sl_llr.h b/drivers/net/ethernet/hpe/sl/sl_llr.h
new file mode 100644
index 000000000000..2077e5c4be07
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sl_llr.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_LLR_H_
+#define _SL_LLR_H_
+
+#define SL_LLR_MAGIC 0x636c6c72
+#define SL_LLR_VER   2
+struct sl_llr {
+	u32 magic;
+	u32 ver;
+
+	u8  num;
+	u8  lgrp_num;
+	u8  ldev_num;
+};
+
+void sl_llr_init(void);
+
+#endif /* _SL_LLR_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/sl_mac.h b/drivers/net/ethernet/hpe/sl/sl_mac.h
new file mode 100644
index 000000000000..032ec400bddc
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sl_mac.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_MAC_H_
+#define _SL_MAC_H_
+
+#define SL_MAC_MAGIC 0x636c6c79
+#define SL_MAC_VER   3
+struct sl_mac {
+	u32 magic;
+	u32 ver;
+
+	u8  num;
+	u8  lgrp_num;
+	u8  ldev_num;
+};
+
+void sl_mac_init(void);
+
+#endif /* _SL_MAC_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/sl_module.h b/drivers/net/ethernet/hpe/sl/sl_module.h
new file mode 100644
index 000000000000..477d197555dd
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sl_module.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_MODULE_COMMON_H_
+#define _SL_MODULE_COMMON_H_
+
+struct device;
+
+u64 sl_serdes_core_io_trace_lgrp_map_get(void);
+
+char          *sl_version_str_get(void);
+struct device *sl_device_get(void);
+
+#endif /* _SL_MODULE_COMMON_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/sl_platform.h b/drivers/net/ethernet/hpe/sl/sl_platform.h
new file mode 100644
index 000000000000..201504c22e90
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sl_platform.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_PLATFORM_H_
+#define _SL_PLATFORM_H_
+
+#define SL_PLATFORM_IS_HARDWARE(_ldev) \
+	((_ldev)->platform == PLATFORM_ASIC)
+
+#define SL_PLATFORM_IS_NETSIM(_ldev)   \
+	((_ldev)->platform == PLATFORM_NETSIM)
+
+#define SL_PLATFORM_IS_EMULATOR(_ldev) \
+	((_ldev)->platform == PLATFORM_Z1)
+
+#endif /* _SL_PLATFORM_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/sl_test_common.h b/drivers/net/ethernet/hpe/sl/sl_test_common.h
new file mode 100644
index 000000000000..0ef5370dbedc
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sl_test_common.h
@@ -0,0 +1,105 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2024,2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_TEST_COMMON_H_
+#define _SL_TEST_COMMON_H_
+
+#define CMD_LEN      32
+#define CMD_DESC_LEN 128
+
+struct cmd_entry {
+	const char cmd[CMD_LEN];
+	const char desc[CMD_DESC_LEN];
+};
+
+struct cmd_entries {
+	struct cmd_entry *entries;
+	size_t            num_entries;
+};
+
+struct options_field_entry {
+	u32 *options;
+	u32  field;
+};
+
+struct str_conv_u16 {
+	int (*to_u16)(const char *str, u16 *value);
+	const char* (*to_str)(u16 value);
+	void (*opts)(char *buf, size_t size);
+	u16 *value;
+
+};
+
+struct str_conv_u32 {
+	int (*to_u32)(const char *str, u32 *value);
+	const char* (*to_str)(u32 value);
+	void (*opts)(char *buf, size_t size);
+	u32 *value;
+};
+
+/* Config Admin Options */
+#define SL_LINK_CONFIG_OPT_LOCK        BIT(30) /* Lock configuration from modification */
+#define SL_LINK_CONFIG_OPT_ADMIN       BIT(31) /* Perform admin level operation        */
+
+#define SL_LGRP_OPT_LOCK               BIT(30) /* Lock configuration from modification */
+#define SL_LGRP_OPT_ADMIN              BIT(31) /* Perform admin level operation        */
+
+#define SL_LLR_CONFIG_OPT_LOCK         BIT(30) /* Lock configuration from modification */
+#define SL_LLR_CONFIG_OPT_ADMIN        BIT(31) /* Perform admin level operation        */
+
+/* Policy Admin Options */
+#define SL_LINK_POLICY_OPT_LOCK        BIT(30) /* Lock configuration from modification */
+#define SL_LINK_POLICY_OPT_ADMIN       BIT(31) /* Perform admin level operation        */
+
+#define SL_LLR_POLICY_OPT_LOCK         BIT(30) /* Lock configuration from modification */
+#define SL_LLR_POLICY_OPT_ADMIN        BIT(31) /* Perform admin level operation        */
+
+int sl_test_serdes_params_set(u8 ldev_num, u8 lgrp_num, u8 link_num,
+			      s16 pre1, s16 pre2, s16 pre3, s16 cursor,
+			      s16 post1, s16 post2, u16 media, u16 osr, u16 encoding,
+			      u16 clocking, u16 width, u16 dfe, u16 scramble_dis, u32 options);
+int sl_test_serdes_params_unset(u8 ldev_num, u8 lgrp_num, u8 link_num);
+
+void        sl_test_state_opts(char *buf, size_t size);
+const char *sl_test_state_str(u16 state);
+int         sl_test_state_from_str(const char *str, u16 *state);
+
+const char *sl_test_serdes_lane_encoding_str(u16 encoding);
+const char *sl_test_serdes_lane_clocking_str(u16 clocking);
+const char *sl_test_serdes_lane_osr_str(u16 osr);
+const char *sl_test_serdes_lane_width_str(u16 width);
+
+int sl_test_serdes_lane_encoding_from_str(const char *str, u16 *encoding);
+int sl_test_serdes_lane_clocking_from_str(const char *str, u16 *clocking);
+int sl_test_serdes_lane_osr_from_str(const char *str, u16 *osr);
+int sl_test_serdes_lane_width_from_str(const char *str, u16 *width);
+int sl_test_media_type_from_str(const char *str, u32 *type);
+
+void        sl_test_scramble_dis_opts(char *buf, size_t size);
+const char *sl_test_scramble_dis_str(u16 scramble_dis);
+int         sl_test_scramble_dis_from_str(const char *str, u16 *scramble_dis);
+
+struct kobject *sl_test_ldev_kobj_get(u8 ldev_num);
+struct kobject *sl_test_lgrp_kobj_get(u8 ldev_num, u8 lgrp_num);
+
+struct sl_ctrl_ldev *sl_test_ctrl_ldev_get(u8 ldev_num);
+struct sl_ctrl_lgrp *sl_test_ctrl_lgrp_get(u8 ldev_num, u8 lgrp_num);
+
+int sl_test_debugfs_create_opt(const char *name, umode_t mode, struct dentry *parent,
+			       struct options_field_entry *value);
+
+int sl_test_cmds_show(struct seq_file *s, struct cmd_entry *cmd_list, size_t num_cmds);
+
+int sl_test_debugfs_create_s32(const char *name, umode_t mode, struct dentry *parent, s32 *value);
+int sl_test_debugfs_create_s16(const char *name, umode_t mode, struct dentry *parent, s16 *value);
+
+int sl_test_debugfs_create_str_conv_u16(const char *name, umode_t mode, struct dentry *parent,
+					struct str_conv_u16 *option);
+int sl_test_debugfs_create_str_conv_u32(const char *name, umode_t mode, struct dentry *parent,
+					struct str_conv_u32 *option);
+
+int sl_test_furcation_from_str(const char *str, u32 *furcation);
+
+void sl_test_pg_cfg_set(u8 ldev_num, u8 lgrp_num, u8 data);
+
+#endif /* _SL_TEST_COMMON_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs.h b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs.h
new file mode 100644
index 000000000000..a9449db3d042
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs.h
@@ -0,0 +1,116 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023,2024,2025,2026 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_SYSFS_H_
+#define _SL_SYSFS_H_
+
+#include <linux/kobject.h>
+
+struct sl_core_link;
+struct sl_core_llr;
+struct sl_ctrl_ldev;
+struct sl_ctrl_lgrp;
+struct sl_ctrl_link;
+struct sl_ctrl_llr;
+struct sl_ctrl_mac;
+
+u8 lane_num_to_link_num(struct sl_ctrl_lgrp *ctrl_lgrp, u8 lane_num);
+
+int  sl_sysfs_ldev_create(u8 ldev_num, struct kobject *parent_kobj);
+void sl_sysfs_ldev_delete(struct sl_ctrl_ldev *ctrl_ldev);
+
+int  sl_sysfs_lgrp_create(struct sl_ctrl_lgrp *ctrl_lgrp);
+void sl_sysfs_lgrp_delete(struct sl_ctrl_lgrp *ctrl_lgrp);
+
+int  sl_sysfs_lgrp_config_create(struct sl_ctrl_lgrp *ctrl_lgrp);
+void sl_sysfs_lgrp_config_delete(struct sl_ctrl_lgrp *ctrl_lgrp);
+
+int  sl_sysfs_lgrp_policy_create(struct sl_ctrl_lgrp *ctrl_lgrp);
+void sl_sysfs_lgrp_policy_delete(struct sl_ctrl_lgrp *ctrl_lgrp);
+
+int  sl_sysfs_serdes_create(struct sl_ctrl_lgrp *ctrl_lgrp);
+void sl_sysfs_serdes_delete(struct sl_ctrl_lgrp *ctrl_lgrp);
+
+int  sl_sysfs_media_create(struct sl_ctrl_lgrp *ctrl_lgrp);
+void sl_sysfs_media_delete(struct sl_ctrl_lgrp *ctrl_lgrp);
+int  sl_sysfs_media_speeds_create(u8 ldev_num, u8 lgrp_num);
+void sl_sysfs_media_speeds_delete(u8 ldev_num, u8 lgrp_num);
+
+int  sl_sysfs_pmi_create(struct sl_ctrl_lgrp *ctrl_lgrp);
+void sl_sysfs_pmi_delete(struct sl_ctrl_lgrp *ctrl_lgrp);
+
+int  sl_sysfs_pmi_rd_create(struct sl_ctrl_lgrp *ctrl_lgrp, struct kobject *parent_kobj);
+void sl_sysfs_pmi_rd_delete(struct sl_ctrl_lgrp *ctrl_lgrp);
+
+int  sl_sysfs_pmi_wr_create(struct sl_ctrl_lgrp *ctrl_lgrp, struct kobject *parent_kobj);
+void sl_sysfs_pmi_wr_delete(struct sl_ctrl_lgrp *ctrl_lgrp);
+
+int  sl_sysfs_sbus_create(struct sl_ctrl_lgrp *ctrl_lgrp);
+void sl_sysfs_sbus_delete(struct sl_ctrl_lgrp *ctrl_lgrp);
+
+int  sl_sysfs_sbus_rd_create(struct sl_ctrl_lgrp *ctrl_lgrp, struct kobject *parent_kobj);
+void sl_sysfs_sbus_rd_delete(struct sl_ctrl_lgrp *ctrl_lgrp);
+
+int  sl_sysfs_sbus_wr_create(struct sl_ctrl_lgrp *ctrl_lgrp, struct kobject *parent_kobj);
+void sl_sysfs_sbus_wr_delete(struct sl_ctrl_lgrp *ctrl_lgrp);
+
+int  sl_sysfs_sbus_rst_create(struct sl_ctrl_lgrp *ctrl_lgrp, struct kobject *parent_kobj);
+void sl_sysfs_sbus_rst_delete(struct sl_ctrl_lgrp *ctrl_lgrp);
+
+int  sl_sysfs_sbus_pmi_create(struct sl_ctrl_lgrp *ctrl_lgrp);
+void sl_sysfs_sbus_pmi_delete(struct sl_ctrl_lgrp *ctrl_lgrp);
+
+int  sl_sysfs_sbus_pmi_rd_create(struct sl_ctrl_lgrp *ctrl_lgrp, struct kobject *parent_kobj);
+void sl_sysfs_sbus_pmi_rd_delete(struct sl_ctrl_lgrp *ctrl_lgrp);
+
+int  sl_sysfs_sbus_pmi_wr_create(struct sl_ctrl_lgrp *ctrl_lgrp, struct kobject *parent_kobj);
+void sl_sysfs_sbus_pmi_wr_delete(struct sl_ctrl_lgrp *ctrl_lgrp);
+
+int  sl_sysfs_link_create(struct sl_ctrl_link *ctrl_link);
+void sl_sysfs_link_delete(struct sl_ctrl_link *ctrl_link);
+
+int  sl_sysfs_link_config_create(struct sl_ctrl_link *ctrl_link);
+void sl_sysfs_link_config_delete(struct sl_ctrl_link *ctrl_link);
+
+int  sl_sysfs_link_policy_create(struct sl_ctrl_link *ctrl_link);
+void sl_sysfs_link_policy_delete(struct sl_ctrl_link *ctrl_link);
+
+int  sl_sysfs_link_degrade_create(struct sl_core_link *core_link, struct kobject *parent_kobj);
+void sl_sysfs_link_degrade_delete(struct sl_core_link *core_link);
+
+int  sl_sysfs_link_pml_rec_create(struct sl_core_link *core_link, struct kobject *parent_kobj);
+void sl_sysfs_link_pml_rec_delete(struct sl_core_link *core_link);
+
+int  sl_sysfs_link_fec_create(struct sl_ctrl_link *ctrl_link);
+void sl_sysfs_link_fec_delete(struct sl_ctrl_link *ctrl_link);
+
+int  sl_sysfs_link_caps_create(struct sl_ctrl_link *ctrl_link);
+void sl_sysfs_link_caps_delete(struct sl_ctrl_link *ctrl_link);
+
+int  sl_sysfs_link_counters_create(struct sl_ctrl_link *ctrl_link);
+void sl_sysfs_link_counters_delete(struct sl_ctrl_link *ctrl_link);
+
+int  sl_sysfs_llr_create(struct sl_ctrl_llr *ctrl_llr);
+void sl_sysfs_llr_delete(struct sl_ctrl_llr *ctrl_llr);
+
+int  sl_sysfs_llr_counters_create(struct sl_ctrl_llr *ctrl_llr, struct kobject *parent_kobj);
+void sl_sysfs_llr_counters_delete(struct sl_ctrl_llr *ctrl_llr);
+
+int sl_sysfs_llr_config_create(struct sl_ctrl_llr *ctrl_llr, struct kobject *parent_kobj);
+void sl_sysfs_llr_config_delete(struct sl_ctrl_llr *ctrl_llr);
+
+int  sl_sysfs_llr_policy_create(struct sl_core_llr *core_llr, struct kobject *parent_kobj);
+void sl_sysfs_llr_policy_delete(struct sl_core_llr *core_llr);
+
+int  sl_sysfs_llr_loop_time_create(struct sl_core_llr *core_llr, struct kobject *parent_kobj);
+void sl_sysfs_llr_loop_time_delete(struct sl_core_llr *core_llr);
+
+int  sl_sysfs_mac_create(struct sl_ctrl_mac *ctrl_mac);
+void sl_sysfs_mac_delete(struct sl_ctrl_mac *ctrl_mac);
+
+int  sl_sysfs_mac_counters_create(struct sl_ctrl_mac *ctrl_mac);
+void sl_sysfs_mac_counters_delete(struct sl_ctrl_mac *ctrl_mac);
+
+int  sl_sysfs_media_counters_create(struct sl_ctrl_lgrp *ctrl_lgrp);
+void sl_sysfs_media_counters_delete(struct sl_ctrl_lgrp *ctrl_lgrp);
+#endif /* _SL_SYSFS_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_fec.h b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_fec.h
new file mode 100644
index 000000000000..05e8b6464875
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_fec.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2024,2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_SYSFS_LINK_FEC_H_
+#define _SL_SYSFS_LINK_FEC_H_
+
+struct sl_ctrl_link;
+
+int  sl_sysfs_link_fec_create(struct sl_ctrl_link *ctrl_link);
+void sl_sysfs_link_fec_delete(struct sl_ctrl_link *ctrl_link);
+
+#endif /* _SL_SYSFS_LINK_FEC_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_fec_current.h b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_fec_current.h
new file mode 100644
index 000000000000..2ff1d38be222
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_fec_current.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_SYSFS_LINK_FEC_CURRENT_H_
+#define _SL_SYSFS_LINK_FEC_CURRENT_H_
+
+struct sl_core_link;
+
+int  sl_sysfs_link_fec_current_create(struct sl_core_link *core_link, struct kobject *parent_kobj);
+void sl_sysfs_link_fec_current_delete(struct sl_core_link *core_link);
+
+#endif /* _SL_SYSFS_LINK_FEC_CURRENT_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_fec_down.h b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_fec_down.h
new file mode 100644
index 000000000000..1c672b2bdce9
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_fec_down.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_SYSFS_LINK_FEC_DOWN_H_
+#define _SL_SYSFS_LINK_FEC_DOWN_H_
+
+struct sl_ctrl_link;
+
+int  sl_sysfs_link_fec_down_create(struct sl_ctrl_link *ctrl_link);
+void sl_sysfs_link_fec_down_delete(struct sl_ctrl_link *ctrl_link);
+
+#endif /* _SL_SYSFS_LINK_FEC_DOWN_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_fec_mon_check.h b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_fec_mon_check.h
new file mode 100644
index 000000000000..85d40e73ebf7
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_fec_mon_check.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_SYSFS_LINK_FEC_MON_CHECK_H_
+#define _SL_SYSFS_LINK_FEC_MON_CHECK_H_
+
+struct sl_ctrl_link;
+
+int  sl_sysfs_link_fec_mon_check_create(struct sl_ctrl_link *ctrl_link);
+void sl_sysfs_link_fec_mon_check_delete(struct sl_ctrl_link *ctrl_link);
+
+#endif /* _SL_SYSFS_LINK_FEC_MON_CHECK_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_fec_up.h b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_fec_up.h
new file mode 100644
index 000000000000..5a06893437cf
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_fec_up.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_SYSFS_LINK_FEC_UP_H_
+#define _SL_SYSFS_LINK_FEC_UP_H_
+
+struct sl_ctrl_link;
+
+int  sl_sysfs_link_fec_up_create(struct sl_ctrl_link *ctrl_link);
+void sl_sysfs_link_fec_up_delete(struct sl_ctrl_link *ctrl_link);
+
+#endif /* _SL_SYSFS_LINK_FEC_UP_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_fec_up_check.h b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_fec_up_check.h
new file mode 100644
index 000000000000..89f5ffa11b51
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_fec_up_check.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_SYSFS_LINK_FEC_UP_CHECK_H_
+#define _SL_SYSFS_LINK_FEC_UP_CHECK_H_
+
+struct sl_core_link;
+
+int  sl_sysfs_link_fec_up_check_create(struct sl_core_link *core_link, struct kobject *parent_kobj);
+void sl_sysfs_link_fec_up_check_delete(struct sl_core_link *core_link);
+
+#endif /* _SL_SYSFS_LINK_FEC_UP_CHECK_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_serdes_eye.h b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_serdes_eye.h
new file mode 100644
index 000000000000..4011fbc7858e
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_serdes_eye.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2024,2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_SYSFS_SERDES_EYE_H_
+#define _SL_SYSFS_SERDES_EYE_H_
+
+struct sl_ctrl_lgrp;
+
+int  sl_sysfs_serdes_lane_eye_create(struct sl_ctrl_lgrp *ctrl_lgrp, u8 lane_num);
+void sl_sysfs_serdes_lane_eye_delete(struct sl_ctrl_lgrp *ctrl_lgrp, u8 lane_num);
+
+#endif /* _SL_SYSFS_SERDES_EYE_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_serdes_lol.h b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_serdes_lol.h
new file mode 100644
index 000000000000..352860b1952f
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_serdes_lol.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_SYSFS_SERDES_LOL_H_
+#define _SL_SYSFS_SERDES_LOL_H_
+
+struct sl_ctrl_lgrp;
+
+int  sl_sysfs_serdes_lane_lol_create(struct sl_ctrl_lgrp *ctrl_lgrp, u8 asic_lane_num);
+void sl_sysfs_serdes_lane_lol_delete(struct sl_ctrl_lgrp *ctrl_lgrp, u8 asic_lane_num);
+
+#endif /* _SL_SYSFS_SERDES_LOL_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_serdes_los.h b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_serdes_los.h
new file mode 100644
index 000000000000..8a422c997219
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_serdes_los.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_SYSFS_SERDES_LOS_H_
+#define _SL_SYSFS_SERDES_LOS_H_
+
+struct sl_ctrl_lgrp;
+
+int  sl_sysfs_serdes_lane_los_create(struct sl_ctrl_lgrp *ctrl_lgrp, u8 asic_lane_num);
+void sl_sysfs_serdes_lane_los_delete(struct sl_ctrl_lgrp *ctrl_lgrp, u8 asic_lane_num);
+
+#endif /* _SL_SYSFS_SERDES_LOS_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_serdes_settings.h b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_serdes_settings.h
new file mode 100644
index 000000000000..f15f42ea3b32
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_serdes_settings.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2024,2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_SYSFS_SERDES_SETTINGS_H_
+#define _SL_SYSFS_SERDES_SETTINGS_H_
+
+struct sl_ctrl_lgrp;
+
+int  sl_sysfs_serdes_lane_settings_create(struct sl_ctrl_lgrp *ctrl_lgrp, u8 lane_num);
+void sl_sysfs_serdes_lane_settings_delete(struct sl_ctrl_lgrp *ctrl_lgrp, u8 lane_num);
+
+#endif /* _SL_SYSFS_SERDES_SETTINGS_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_serdes_state.h b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_serdes_state.h
new file mode 100644
index 000000000000..5628f2068011
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_serdes_state.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2024,2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_SYSFS_SERDES_STATE_H_
+#define _SL_SYSFS_SERDES_STATE_H_
+
+struct sl_ctrl_lgrp;
+
+int  sl_sysfs_serdes_lane_state_create(struct sl_ctrl_lgrp *ctrl_lgrp, u8 lane_num);
+void sl_sysfs_serdes_lane_state_delete(struct sl_ctrl_lgrp *ctrl_lgrp, u8 lane_num);
+
+#endif /* _SL_SYSFS_SERDES_STATE_H_ */
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_serdes_swizzle.h b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_serdes_swizzle.h
new file mode 100644
index 000000000000..365b73c365e5
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_serdes_swizzle.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _SL_SYSFS_SERDES_SWIZZLE_H_
+#define _SL_SYSFS_SERDES_SWIZZLE_H_
+
+#include <linux/types.h>
+
+struct sl_ctrl_lgrp;
+
+int  sl_sysfs_serdes_lane_swizzle_create(struct sl_ctrl_lgrp *ctrl_lgrp, u8 lane_num);
+void sl_sysfs_serdes_lane_swizzle_delete(struct sl_ctrl_lgrp *ctrl_lgrp, u8 lane_num);
+
+#endif /* _SL_SYSFS_SERDES_SWIZZLE_H_ */
diff --git a/include/linux/hpe/sl/sl_fec.h b/include/linux/hpe/sl/sl_fec.h
new file mode 100644
index 000000000000..4afd6275d1fc
--- /dev/null
+++ b/include/linux/hpe/sl/sl_fec.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _LINUX_SL_FEC_H_
+#define _LINUX_SL_FEC_H_
+
+struct sl_link;
+
+#define SL_CTRL_NUM_FEC_LANES 16
+struct sl_fec_info {
+	u64 ucw;                          /* uncorrected code word count */
+	u64 ccw;                          /* corrected code word count   */
+	u64 gcw;                          /* good code word count        */
+	u64 lanes[SL_CTRL_NUM_FEC_LANES]; /* error count per lane        */
+	u32 period_ms;                    /* actual collection period    */
+	struct {
+		s32 ccw_down_limit;       /* ccw down limit used in the monitor    */
+		s32 ccw_warn_limit;       /* ccw warn limit used in the monitor    */
+		s32 ucw_down_limit;       /* ucw down limit used in the monitor    */
+		s32 ucw_warn_limit;       /* ucw warn limit used in the monitor    */
+		u32 period_ms;            /* collection period used in the monitor */
+	} monitor;
+};
+int sl_fec_info_get(struct sl_link *link, struct sl_fec_info *fec_info);
+
+#define SL_CTRL_NUM_CCW_BINS 15
+struct sl_fec_tail {
+	u64 ccw_bins[SL_CTRL_NUM_CCW_BINS];
+	u32 period_ms;                    /* collection period */
+};
+int sl_fec_tail_get(struct sl_link *link, struct sl_fec_tail *fec_tail);
+
+struct sl_ber {
+	u32 mant;
+	s32 exp;
+};
+int sl_fec_ber_calc(struct sl_fec_info *fec_info, struct sl_ber *ucw_ber, struct sl_ber *ccw_ber);
+
+#endif /* _LINUX_SL_FEC_H_ */
diff --git a/include/linux/hpe/sl/sl_ldev.h b/include/linux/hpe/sl/sl_ldev.h
new file mode 100644
index 000000000000..43a11673f205
--- /dev/null
+++ b/include/linux/hpe/sl/sl_ldev.h
@@ -0,0 +1,140 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _LINUX_SL_LDEV_H_
+#define _LINUX_SL_LDEV_H_
+
+#include <linux/kobject.h>
+#include <linux/workqueue.h>
+
+struct sl_dt_lgrp_info;
+
+#define SL_LDEV_POLICY_MAGIC 0x736c6470
+#define SL_LDEV_POLICY_VER   1
+struct sl_ldev_policy {
+	u32 magic;
+	u32 ver;
+	u32 size;
+
+	u32 options;
+};
+
+typedef void (*sl_intr_handler_t)(u64 *err_flags, int flag_count, void *data);
+
+/* ASIC types */
+typedef u64 (*sl_read64_t)(void *pci_accessor, long addr);
+typedef void (*sl_write64_t)(void *pci_accessor, long addr, u64 data);
+
+/* Sbus types */
+#define SL_SBUS_OP_RST  1
+#define SL_SBUS_OP_RD   2
+#define SL_SBUS_OP_WR   3
+typedef int (*sl_sbus_op_t)(void *sbus_accessor, u8 op,
+			    u8 ring, u8 dev_addr, u8 reg, u32 *rd_data, u32 wr_data);
+
+/* PMI types */
+#define SL_PMI_OP_RST  1
+#define SL_PMI_OP_RD   2
+#define SL_PMI_OP_WR   3
+typedef int (*sl_pmi_op_t)(void *pmi_accessor, u8 lgrp_num, u8 op,
+			   u32 addr, u16 *rd_data, u16 wr_data, u16 wr_data_mask);
+
+/* PML Intr types */
+typedef int (*sl_pml_intr_register_t)(void *intr_accessor, u32 lgrp_num, char *tag,
+				      u64 *err_flgs, sl_intr_handler_t handler, void *data);
+typedef int (*sl_pml_intr_unregister_t)(void *intr_accessor, u32 lgrp_num,
+				      u64 *err_flgs, sl_intr_handler_t handler);
+typedef int (*sl_pml_intr_enable_t)(void *intr_accessor, u32 lgrp_num,
+				    u64 *err_flgs, sl_intr_handler_t handler);
+typedef int (*sl_pml_intr_disable_t)(void *intr_accessor, u32 lgrp_num,
+				     u64 *err_flgs, sl_intr_handler_t handler);
+
+/* DT types */
+typedef int (*sl_dt_info_get_t)(void *dt_accessor, u8 ldev_num, u8 lgrp_num,
+				struct sl_dt_lgrp_info *info);
+
+/* UC types */
+typedef int (*sl_uc_rd_t)(void *uc_accessor, u32 offset, u32 page, u8 *data, u32 len);
+typedef int (*sl_uc_wr8_t)(void *uc_accessor, u8 page, u8 addr, u8 data);
+
+typedef void (*sl_uc_led_set_t)(void *uc_accessor, u8 led_pattern);
+
+/* MB types */
+typedef int (*sl_mb_info_get_t)(void *mb_accessor, u8 *platform, u16 *revision, u16 *proto);
+
+/* DMAC types */
+typedef int  (*sl_dmac_alloc_t)(void *dmac_accessor, u32 offset, size_t size);
+typedef int  (*sl_dmac_xfer_t)(void *dmac_accessor, void *data);
+typedef void (*sl_dmac_free_t)(void *dmac_accessor);
+
+struct sl_accessors {
+	void *pci;
+	void *sbus;
+	void *pmi;
+	void *intr;
+	void *dt;
+	void *mb;
+	void *dmac;
+};
+
+struct sl_uc_accessor {
+	void *uc;
+};
+
+struct sl_uc_ops {
+	sl_uc_rd_t      uc_read;
+	sl_uc_wr8_t     uc_write8;
+	sl_uc_led_set_t uc_led_set;
+};
+
+struct sl_ops {
+	/* ASIC */
+	sl_read64_t  read64;
+	sl_write64_t write64;
+
+	/* Sbus */
+	sl_sbus_op_t sbus_op;
+
+	/* PMI */
+	sl_pmi_op_t pmi_op;
+
+	/* PML interrupts */
+	sl_pml_intr_register_t   pml_intr_register;
+	sl_pml_intr_unregister_t pml_intr_unregister;
+	sl_pml_intr_enable_t     pml_intr_enable;
+	sl_pml_intr_disable_t    pml_intr_disable;
+
+	/* DT */
+	sl_dt_info_get_t dt_info_get;
+
+	/* MB */
+	sl_mb_info_get_t mb_info_get;
+
+	sl_dmac_alloc_t dmac_alloc;
+	sl_dmac_xfer_t  dmac_xfer;
+	sl_dmac_free_t  dmac_free;
+};
+
+#define SL_LDEV_ATTR_MAGIC 0x736c6461
+#define SL_LDEV_ATTR_VER   1
+struct sl_ldev_attr {
+	u32 magic;
+	u32 ver;
+	u32 size;
+
+	struct sl_ops       *ops;
+	struct sl_accessors *accessors;
+
+	u32 options;
+};
+
+struct sl_ldev *sl_ldev_new(u8 ldev_num, struct workqueue_struct *workq,
+			    struct sl_ldev_attr *ldev_attr);
+int             sl_ldev_sysfs_parent_set(struct sl_ldev *ldev, struct kobject *parent);
+int             sl_ldev_serdes_init(struct sl_ldev *ldev);
+int             sl_ldev_del(struct sl_ldev *ldev);
+int             sl_ldev_uc_ops_set(struct sl_ldev *ldev, struct sl_uc_ops *uc_ops,
+				   struct sl_uc_accessor *uc_accessor);
+
+#endif /* _LINUX_SL_LDEV_H_ */
+
diff --git a/include/linux/hpe/sl/sl_lgrp.h b/include/linux/hpe/sl/sl_lgrp.h
new file mode 100644
index 000000000000..5fe8a6786eb7
--- /dev/null
+++ b/include/linux/hpe/sl/sl_lgrp.h
@@ -0,0 +1,213 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023-2026 Hewlett Packard Enterprise Development LP */
+
+#ifndef _LINUX_SL_LGRP_H_
+#define _LINUX_SL_LGRP_H_
+
+#include <linux/bitops.h>
+#include <linux/kobject.h>
+
+#include <linux/hpe/sl/sl_link.h>
+#include <linux/hpe/sl/sl_llr.h>
+#include <linux/hpe/sl/sl_media.h>
+
+struct sl_ldev;
+struct sl_lgrp;
+struct sl_lgrp_config;
+
+#define SL_LGRP_NOTIF_INVALID               0
+#define SL_LGRP_NOTIF_ALL                  ~0        /* all notifications                  */
+#define SL_LGRP_NOTIF_LINK_UP               BIT(1)   /* link up                            */
+#define SL_LGRP_NOTIF_LINK_UP_FAIL          BIT(2)   /* link up fail                       */
+#define SL_LGRP_NOTIF_LINK_DOWN             BIT(3)   /* link down                          */
+#define SL_LGRP_NOTIF_LINK_ASYNC_DOWN       BIT(4)   /* link down asynchronously           */
+#define SL_LGRP_NOTIF_LINK_ERROR            BIT(5)   /* link error                         */
+#define SL_LGRP_NOTIF_LINK_UCW_WARN         BIT(6)   /* UCW count crossed warning limit    */
+#define SL_LGRP_NOTIF_LINK_CCW_WARN         BIT(7)   /* CCW count crossed warning limit    */
+#define SL_LGRP_NOTIF_LLR_SETUP             BIT(8)   /* LLR is setup + data                */
+#define SL_LGRP_NOTIF_LLR_SETUP_TIMEOUT     BIT(9)   /* LLR setup timeout                  */
+#define SL_LGRP_NOTIF_LLR_RUNNING           BIT(10)  /* LLR running                        */
+#define SL_LGRP_NOTIF_LLR_START_TIMEOUT     BIT(11)  /* LLR start timeout                  */
+#define SL_LGRP_NOTIF_LLR_CANCELED          BIT(12)  /* LLR canceled                       */
+#define SL_LGRP_NOTIF_LLR_ERROR             BIT(13)  /* LLR error                          */
+#define SL_LGRP_NOTIF_MEDIA_PRESENT         BIT(14)  /* media/cable present                */
+#define SL_LGRP_NOTIF_MEDIA_NOT_PRESENT     BIT(15)  /* media/cable not present            */
+#define SL_LGRP_NOTIF_MEDIA_ERROR           BIT(16)  /* media/cable error                  */
+#define SL_LGRP_NOTIF_MEDIA_HOT             BIT(17)  /* media/cable hot detected           */
+#define SL_LGRP_NOTIF_MEDIA_COLD            BIT(18)  /* media/cable cold detected          */
+#define SL_LGRP_NOTIF_MEDIA_WARM            BIT(19)  /* media/cable warm detected          */
+#define SL_LGRP_NOTIF_AN_DATA               BIT(20)  /* autoneg data                       */
+#define SL_LGRP_NOTIF_AN_TIMEOUT            BIT(21)  /* autoneg timeout                    */
+#define SL_LGRP_NOTIF_AN_ERROR              BIT(22)  /* autoneg error                      */
+#define SL_LGRP_NOTIF_LANE_DEGRADE          BIT(23)  /* auto lane degrade                  */
+#define SL_LGRP_NOTIF_LANE_DEGRADE_RECOVERY BIT(24)  /* auto lane degrade can be recovered */
+#define SL_LGRP_NOTIF_PML_RECOVERY          BIT(25)  /* pml recovery                       */
+#define SL_LGRP_NOTIF_LINK_DOWN_REQ         BIT(26)  /* link down request                  */
+
+#define SL_LGRP_NOTIF_NO_LINK 0xFF
+
+#define SL_LGRP_NOTIF_LINK     (SL_LGRP_NOTIF_LINK_UP         | \
+				SL_LGRP_NOTIF_LINK_UP_FAIL    | \
+				SL_LGRP_NOTIF_LINK_DOWN       | \
+				SL_LGRP_NOTIF_LINK_ASYNC_DOWN | \
+				SL_LGRP_NOTIF_LINK_ERROR      | \
+				SL_LGRP_NOTIF_LINK_UCW_WARN   | \
+				SL_LGRP_NOTIF_LINK_CCW_WARN)
+
+#define SL_LGRP_NOTIF_LLR      (SL_LGRP_NOTIF_LLR_SETUP         | \
+				SL_LGRP_NOTIF_LLR_SETUP_TIMEOUT | \
+				SL_LGRP_NOTIF_LLR_RUNNING       | \
+				SL_LGRP_NOTIF_LLR_START_TIMEOUT | \
+				SL_LGRP_NOTIF_LLR_CANCELED      | \
+				SL_LGRP_NOTIF_LLR_ERROR)
+
+#define SL_LGRP_NOTIF_MEDIA    (SL_LGRP_NOTIF_MEDIA_PRESENT     | \
+				SL_LGRP_NOTIF_MEDIA_NOT_PRESENT | \
+				SL_LGRP_NOTIF_MEDIA_HOT         | \
+				SL_LGRP_NOTIF_MEDIA_COLD        | \
+				SL_LGRP_NOTIF_MEDIA_WARM        | \
+				SL_LGRP_NOTIF_MEDIA_ERROR)
+
+#define SL_LGRP_NOTIF_AN       (SL_LGRP_NOTIF_AN_DATA    | \
+				SL_LGRP_NOTIF_AN_TIMEOUT | \
+				SL_LGRP_NOTIF_AN_ERROR)
+
+#define SL_LGRP_CONFIG_TECH_CK_400G      BIT(18)
+#define SL_LGRP_CONFIG_TECH_CK_200G      BIT(17)
+#define SL_LGRP_CONFIG_TECH_CK_100G      BIT(16)
+#define SL_LGRP_CONFIG_TECH_BS_200G      BIT(15)
+#define SL_LGRP_CONFIG_TECH_CD_100G      BIT(14)
+#define SL_LGRP_CONFIG_TECH_CD_50G       BIT(13)
+#define SL_LGRP_CONFIG_TECH_BJ_100G      BIT(8)
+
+#define SL_LGRP_CONFIG_TECH_MASK (SL_LGRP_CONFIG_TECH_CK_400G | \
+				  SL_LGRP_CONFIG_TECH_CK_200G | \
+				  SL_LGRP_CONFIG_TECH_CK_100G | \
+				  SL_LGRP_CONFIG_TECH_BS_200G | \
+				  SL_LGRP_CONFIG_TECH_CD_100G | \
+				  SL_LGRP_CONFIG_TECH_CD_50G  | \
+				  SL_LGRP_CONFIG_TECH_BJ_100G)
+
+#define SL_LGRP_CONFIG_FEC_RS_LL         BIT(1)
+#define SL_LGRP_CONFIG_FEC_RS            BIT(0)
+
+#define SL_LGRP_CONFIG_FEC_MASK (SL_LGRP_CONFIG_FEC_RS_LL | \
+				 SL_LGRP_CONFIG_FEC_RS)
+
+#define SL_LGRP_FEC_MODE_OFF     BIT(0)
+#define SL_LGRP_FEC_MODE_MONITOR BIT(1)
+#define SL_LGRP_FEC_MODE_CORRECT BIT(2)
+
+#define SL_LGRP_LLR_MODE_OFF     BIT(0)
+#define SL_LGRP_LLR_MODE_MONITOR BIT(1)
+#define SL_LGRP_LLR_MODE_ON      BIT(2)
+
+#define SL_LGRP_CONFIG_OPT_FABRIC                 BIT(0) /* fabric link     */
+#define SL_LGRP_CONFIG_OPT_R1                     BIT(1) /* connected to R1 */
+#define SL_LGRP_CONFIG_OPT_SERDES_LOOPBACK_ENABLE BIT(2) /* serdes loopback */
+#define SL_LGRP_CONFIG_OPT_8BYTE_PREAMBLE         BIT(3) /* 4 byte preamble */
+
+#define SL_LGRP_CONFIG_MAGIC 0x6c676366
+#define SL_LGRP_CONFIG_VER   1
+struct sl_lgrp_config {
+	u32 magic;
+	u32 ver;
+	u32 size;
+
+	u32 mfs;
+	u32 furcation;
+	u32 fec_mode;
+
+	u32 tech_map;
+	u32 fec_map;
+
+	u32 options;
+};
+
+#define SL_LGRP_POLICY_MAGIC 0x6c67706f
+#define SL_LGRP_POLICY_VER   1
+struct sl_lgrp_policy {
+	u32 magic;
+	u32 ver;
+	u32 size;
+
+	u32 options;
+};
+
+#define SL_HW_ATTR_MAGIC 0x73736861
+#define SL_HW_ATTR_VER   1
+struct sl_hw_attr {
+        u32 magic;
+        u32 ver;
+
+        u8 cxi_num;
+        u8 nic_num;
+};
+
+int sl_lgrp_hw_attr_set(struct sl_lgrp *lgrp, struct sl_hw_attr *hw_attr);
+
+struct sl_lgrp_notif_info_link_up {
+	u32 mode;
+	u32 fec_type;
+	u32 fec_mode;
+};
+
+union sl_lgrp_notif_info {
+	struct sl_lgrp_notif_info_link_up         link_up;
+	struct sl_link_caps                       lp_link_caps;
+	struct sl_llr_data                        llr_data;
+	struct sl_media_attr                      media_attr;
+	struct sl_link_degrade_info               degrade_info;
+	struct sl_link_pml_rec_info               pml_rec_info;
+	bool                                      is_degrade_recoverable;
+	int                                       error;
+	u64                                       cause_map;
+};
+
+struct sl_lgrp_notif_msg {
+	u8                       ldev_num;
+	u8                       lgrp_num;
+	u8                       link_num;
+	u32                      type;
+	union sl_lgrp_notif_info info;
+	u64                      info_map;
+};
+
+#define SL_MAX_LANES 4
+struct sl_dt_lgrp_info {
+	u8 sbus_ring;
+	u8 dev_id;
+	u8 dev_addr;
+	struct {
+		u8 tx_source;
+		u8 tx_invert;
+		u8 rx_source;
+		u8 rx_invert;
+	} lane_info[SL_MAX_LANES];
+	u32 jack_type;
+};
+
+struct sl_lgrp *sl_lgrp_new(struct sl_ldev *ldev, u8 lgrp_num, struct kobject *sysfs_parent);
+int             sl_lgrp_del(struct sl_lgrp *lgrp);
+
+int sl_lgrp_config_set(struct sl_lgrp *lgrp, struct sl_lgrp_config *lgrp_config);
+int sl_lgrp_policy_set(struct sl_lgrp *lgrp, struct sl_lgrp_policy *lgrp_policy);
+
+typedef void (*sl_lgrp_notif_t)(void *tag, struct sl_lgrp_notif_msg *msg);
+
+int sl_lgrp_notif_callback_reg(struct sl_lgrp *lgrp, sl_lgrp_notif_t callback,
+			       u32 types, void *tag);
+int sl_lgrp_notif_callback_unreg(struct sl_lgrp *lgrp, sl_lgrp_notif_t callback,
+				 u32 types);
+
+int sl_lgrp_connect_id_set(struct sl_lgrp *lgrp, const char *connect_id);
+
+const char *sl_lgrp_config_tech_str(u32 config);
+const char *sl_lgrp_config_fec_str(u32 config);
+const char *sl_lgrp_furcation_str(u32 furcation);
+const char *sl_lgrp_notif_str(u32 notif);
+const char *sl_lgrp_config_opt_str(u32 option);
+const char *sl_lgrp_fec_mode_str(u32 mode);
+const char *sl_lgrp_llr_mode_str(u32 mode);
+
+#endif /* _LINUX_SL_LGRP_H_ */
diff --git a/include/linux/hpe/sl/sl_link.h b/include/linux/hpe/sl/sl_link.h
new file mode 100644
index 000000000000..9153235d9d71
--- /dev/null
+++ b/include/linux/hpe/sl/sl_link.h
@@ -0,0 +1,244 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023-2026 Hewlett Packard Enterprise Development LP */
+
+#ifndef _LINUX_SL_LINK_H_
+#define _LINUX_SL_LINK_H_
+
+#include <linux/bitops.h>
+#include <linux/kobject.h>
+#include <linux/atomic.h>
+
+struct sl_lgrp;
+struct sl_link;
+
+#define SL_LINK_INFO_STRLEN 128
+
+enum sl_link_state {
+	SL_LINK_STATE_INVALID,
+	SL_LINK_STATE_DOWN,
+	SL_LINK_STATE_AN,
+	SL_LINK_STATE_STARTING,
+	SL_LINK_STATE_UP,
+	SL_LINK_STATE_UP_DOWN_REQ,
+	SL_LINK_STATE_STOPPING,
+};
+
+#define SL_LINK_CAPS_MAGIC 0x6D676774
+#define SL_LINK_CAPS_VER   1
+struct sl_link_caps {
+	u32 magic;
+	u32 ver;
+	u32 size;
+
+	u32 pause_map;
+	u32 tech_map;
+	u32 fec_map;
+	u32 hpe_map;
+};
+
+#define SL_LINK_CONFIG_PAUSE_ASYM        BIT(1)
+#define SL_LINK_CONFIG_PAUSE_SYM         BIT(0)
+
+#define SL_LINK_CONFIG_PAUSE_MASK (SL_LINK_CONFIG_PAUSE_ASYM | \
+				   SL_LINK_CONFIG_PAUSE_SYM)
+
+#define SL_LINK_CONFIG_HPE_LINKTRAIN     BIT(18)  /* link train              */
+#define SL_LINK_CONFIG_HPE_PRECODING     BIT(17)  /* precoding               */
+#define SL_LINK_CONFIG_HPE_PCAL          BIT(16)  /* progressive calibration */
+/* SWITCH versions */
+#define SL_LINK_CONFIG_HPE_R3            BIT(10)
+#define SL_LINK_CONFIG_HPE_R2            BIT(9)
+#define SL_LINK_CONFIG_HPE_R1            BIT(8)
+/* NIC versions */
+#define SL_LINK_CONFIG_HPE_C3            BIT(6)
+#define SL_LINK_CONFIG_HPE_C2            BIT(5)
+#define SL_LINK_CONFIG_HPE_C1            BIT(4)
+/* bit 3 used for credits */
+/* bit 2 used for v1 */
+/* bit 1 used for v1 */
+#define SL_LINK_CONFIG_HPE_LLR           BIT(0)
+
+#define SL_LINK_CONFIG_HPE_MASK (SL_LINK_CONFIG_HPE_LINKTRAIN | \
+				 SL_LINK_CONFIG_HPE_PRECODING | \
+				 SL_LINK_CONFIG_HPE_PCAL      | \
+				 SL_LINK_CONFIG_HPE_R3        | \
+				 SL_LINK_CONFIG_HPE_R2        | \
+				 SL_LINK_CONFIG_HPE_R1        | \
+				 SL_LINK_CONFIG_HPE_C3        | \
+				 SL_LINK_CONFIG_HPE_C2        | \
+				 SL_LINK_CONFIG_HPE_C1        | \
+				 SL_LINK_CONFIG_HPE_LLR)
+
+#define SL_LINK_CONFIG_MAGIC 0x6c6b6366
+#define SL_LINK_CONFIG_VER   2
+struct sl_link_config {
+	u32 magic;
+	u32 ver;
+	u32 size;
+
+	u32 link_up_timeout_ms;
+	u32 link_up_tries_max;
+
+	s32 fec_up_settle_wait_ms;
+	s32 fec_up_check_wait_ms;
+	s32 fec_up_ucw_limit;
+	s32 fec_up_ccw_limit;
+
+	u32 pml_rec_timeout_ms;
+	u32 pml_rec_rate_limit_max_time_ms;
+	u32 pml_rec_rate_limit_window_size_ms;
+
+	u32 pause_map;
+	u32 hpe_map;
+
+	u32 options;
+};
+
+#define SL_LINK_CONFIG_OPT_AUTONEG_ENABLE            BIT(0) /* Autoneg                     */
+#define SL_LINK_CONFIG_OPT_AUTONEG_CONTINUOUS_ENABLE BIT(1) /* Continuous autoneg attempts */
+#define SL_LINK_CONFIG_OPT_HEADSHELL_LOOPBACK_ENABLE BIT(2) /* Headshell loopback          */
+#define SL_LINK_CONFIG_OPT_REMOTE_LOOPBACK_ENABLE    BIT(3) /* Remote loopback             */
+#define SL_LINK_CONFIG_OPT_ALD_ENABLE                BIT(4) /* Auto Lane Degrade           */
+#define SL_LINK_CONFIG_OPT_LOS_LOL_UP_FAIL_HIDE      BIT(5) /* Hide los and lol reporting  */
+#define SL_LINK_CONFIG_OPT_PML_REC_ENABLE            BIT(6) /* PML Recovery                */
+/* BIT 30 Reserved */
+/* BIT 31 Reserved */
+
+#define SL_LINK_POLICY_MAGIC 0x6c6b706f
+#define SL_LINK_POLICY_VER   2
+struct sl_link_policy {
+	u32 magic;
+	u32 ver;
+	u32 size;
+
+	s32 fec_mon_ucw_down_limit;
+	s32 fec_mon_ucw_warn_limit;
+	s32 fec_mon_ccw_down_limit;
+	s32 fec_mon_ccw_warn_limit;
+	s32 fec_mon_period_ms;
+
+	u32 options;
+};
+
+#define SL_LINK_DEGRADE_INFO_MAGIC 0x0130bb03
+#define SL_LINK_DEGRADE_INFO_VER   1
+struct sl_link_degrade_info {
+	u32  magic;
+	u32  size;
+	u32  ver;
+
+	u16  tx_link_speed;  /* in Gbps */
+	u16  rx_link_speed;  /* in Gbps */
+	u8   tx_degrade_map;
+	u8   rx_degrade_map;
+	bool is_tx_degrade;
+	bool is_rx_degrade;
+	bool is_recoverable; /* whether we can recover from ALD via bouncing the link */
+};
+
+enum sl_link_pml_rec_counters {
+	SL_LINK_PML_REC_ATTEMPTS,
+	SL_LINK_PML_REC_SUCCESSES,
+	SL_LINK_PML_REC_LINK_LOCAL_FAULT_CAUSE,
+	SL_LINK_PML_REC_LINK_DOWN_CAUSE,
+	SL_LINK_PML_REC_LINK_LOCAL_FAULT_FAILED_CAUSE,
+	SL_LINK_PML_REC_LINK_DOWN_FAILED_CAUSE,
+	SL_LINK_PML_REC_RATE_LIMIT_EXCEEDED,
+
+	SL_LINK_PML_REC_NUM_COUNTERS,
+};
+
+#define SL_LINK_PML_REC_MAGIC 0x013309a9
+#define SL_LINK_PML_REC_VER   1
+struct sl_link_pml_rec_info {
+	u32      magic;
+	u32      size;
+	u32      ver;
+
+	atomic_t pml_rec_counters[SL_LINK_PML_REC_NUM_COUNTERS];
+};
+
+#define SL_LINK_POLICY_OPT_KEEP_SERDES_UP            BIT(0) /* Keep serdes running when link is down                   */
+#define SL_LINK_POLICY_OPT_USE_UNSUPPORTED_CABLE     BIT(1) /* Try to bring the link up even if cable is unsupported   */
+#define SL_LINK_POLICY_OPT_IGNORE_MEDIA_ERROR        BIT(2) /* Try to bring the link up even if media has errors       */
+#define SL_LINK_POLICY_OPT_USE_SUPPORTED_SS200_CABLE BIT(3) /* Bring the link up with supported SS200 cables           */
+#define SL_LINK_POLICY_OPT_LINK_DOWN_REQ             BIT(4) /* Request link down from client                           */
+/* BIT 30 Reserved */
+/* BIT 31 Reserved */
+
+#define SL_LINK_INFINITE_UP_TRIES ~0
+
+#define SL_LINK_DOWN_CAUSE_NONE              0
+#define SL_LINK_DOWN_CAUSE_UCW               BIT(1)  /* link up or fec mon UCW limit crossed */
+#define SL_LINK_DOWN_CAUSE_LF                BIT(2)  /* link local fault                     */
+#define SL_LINK_DOWN_CAUSE_RF                BIT(3)  /* link remote fault                    */
+#define SL_LINK_DOWN_CAUSE_DOWN              BIT(4)  /* link down fault                      */
+#define SL_LINK_DOWN_CAUSE_UP_TRIES          BIT(5)  /* link up tries exhausted              */
+#define SL_LINK_DOWN_CAUSE_AUTONEG_NOMATCH   BIT(6)  /* lp_caps autoneg no match             */
+#define SL_LINK_DOWN_CAUSE_AUTONEG           BIT(7)  /* autoneg failure                      */
+#define SL_LINK_DOWN_CAUSE_CONFIG            BIT(8)  /* link up bad config                   */
+#define SL_LINK_DOWN_CAUSE_INTR_ENABLE       BIT(9)  /* link up interrupt enable failure     */
+#define SL_LINK_DOWN_CAUSE_TIMEOUT           BIT(10) /* link up timeout                      */
+#define SL_LINK_DOWN_CAUSE_CANCELED          BIT(11) /* link up cancelled                    */
+#define SL_LINK_DOWN_CAUSE_UNSUPPORTED_CABLE BIT(12) /* unsupported cable                    */
+#define SL_LINK_DOWN_CAUSE_COMMAND           BIT(13) /* client command                       */
+#define SL_LINK_DOWN_CAUSE_DOWNSHIFT         BIT(14) /* link up cable downshift failed       */
+#define SL_LINK_DOWN_CAUSE_LLR_REPLAY_MAX    BIT(15) /* LLR replay at max fault              */
+#define SL_LINK_DOWN_CAUSE_UPSHIFT           BIT(16) /* link up cable upshift failed         */
+#define SL_LINK_DOWN_CAUSE_AUTONEG_CONFIG    BIT(17) /* link up config after an failed       */
+#define SL_LINK_DOWN_CAUSE_PCS_FAULT         BIT(18) /* link up PCS is not ok                */
+#define SL_LINK_DOWN_CAUSE_SERDES_PLL        BIT(19) /* link up serdes problems              */
+#define SL_LINK_DOWN_CAUSE_SERDES_CONFIG     BIT(20) /* link up serdes config problems       */
+#define SL_LINK_DOWN_CAUSE_SERDES_SIGNAL     BIT(21) /* link up serdes signal problems       */
+#define SL_LINK_DOWN_CAUSE_SERDES_QUALITY    BIT(22) /* link up serdes quality problems      */
+#define SL_LINK_DOWN_CAUSE_NO_MEDIA          BIT(23) /* no media present                     */
+#define SL_LINK_DOWN_CAUSE_CCW               BIT(24) /* link up or fec mon CCW limit crossed */
+#define SL_LINK_DOWN_CAUSE_MEDIA_HOT         BIT(25) /* active cable hot                     */
+#define SL_LINK_DOWN_CAUSE_MEDIA_WARM        BIT(26) /* active cable warm                    */
+#define SL_LINK_DOWN_CAUSE_INTR_REGISTER     BIT(27) /* link up interrupt register failure   */
+#define SL_LINK_DOWN_CAUSE_MEDIA_ERROR       BIT(28) /* media has errors                     */
+#define SL_LINK_DOWN_CAUSE_UP_CANCELED       BIT(29) /* link up canceled, link down          */
+#define SL_LINK_DOWN_CAUSE_UNSUPPORTED_SPEED BIT(30) /* unsupported speed                    */
+#define SL_LINK_DOWN_CAUSE_SS200_CABLE       BIT(31) /* SS200 cable                          */
+#define SL_LINK_DOWN_CAUSE_TX_LOL            BIT(32) /* TX Loss of Lock                      */
+#define SL_LINK_DOWN_CAUSE_RX_LOL            BIT(33) /* RX Loss of Lock                      */
+#define SL_LINK_DOWN_CAUSE_TX_LOS            BIT(34) /* TX Loss of Signal                    */
+#define SL_LINK_DOWN_CAUSE_RX_LOS            BIT(35) /* RX Loss of Signal                    */
+
+#define SL_LINK_DOWN_RETRYABLE               BIT(61) /* client retry possible                */
+#define SL_LINK_DOWN_ORIGIN_ASYNC            BIT(62) /* link down cause was asynchronous     */
+#define SL_LINK_DOWN_ORIGIN_LINK_UP          BIT(63) /* link down before reaching up         */
+
+#define SL_LINK_DOWN_CAUSE_STR_SIZE     128
+#define SL_LINK_UP_FAIL_CAUSE_STR_SIZE  128
+#define SL_LINK_DOWN_CAUSE_STR_SIZE_MIN 4
+
+struct sl_link *sl_link_new(struct sl_lgrp *lgrp, u8 link_num, struct kobject *sysfs_parent);
+int             sl_link_del(struct sl_link *link);
+
+int sl_link_state_get(struct sl_link *link, u32 *state);
+
+int sl_link_config_set(struct sl_link *link, struct sl_link_config *link_config);
+int sl_link_policy_set(struct sl_link *link, struct sl_link_policy *link_policy);
+
+int sl_link_an_lp_caps_get(struct sl_link *link, struct sl_link_caps *caps, u32 timeout_ms, u32 flags);
+int sl_link_an_lp_caps_stop(struct sl_link *link);
+
+int sl_link_up(struct sl_link *link);
+int sl_link_down(struct sl_link *link);
+int sl_link_reset(struct sl_link *link);
+
+int sl_link_clocks_get(struct sl_link *link, u32 *up_count, s64 *up_time, s64 *total_time);
+
+const char *sl_link_state_str(u32 state);
+const char *sl_link_degrade_state_str(u32 degrade_state);
+const char *sl_link_an_lp_caps_state_str(u32 lp_caps_state);
+const char *sl_link_config_opt_str(u32 option);
+const char *sl_link_policy_opt_str(u32 option);
+int         sl_link_down_cause_map_str(u64 cause_map, char *cause_str, unsigned int cause_str_size);
+int         sl_link_down_cause_map_with_info_str(u64 cause_map, char *cause_str, unsigned int cause_str_size);
+int         sl_link_info_map_str(u64 info_map, char *info_map_str, unsigned int info_map_str_size);
+const char *sl_link_config_pause_str(u32 config);
+const char *sl_link_config_hpe_str(u32 config);
+
+#endif /* _LINUX_SL_LINK_H_ */
diff --git a/include/linux/hpe/sl/sl_llr.h b/include/linux/hpe/sl/sl_llr.h
new file mode 100644
index 000000000000..f259de054bbd
--- /dev/null
+++ b/include/linux/hpe/sl/sl_llr.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _LINUX_SL_LLR_H_
+#define _LINUX_SL_LLR_H_
+
+#include <linux/bitops.h>
+#include <linux/kobject.h>
+
+struct sl_lgrp;
+struct sl_llr;
+
+#define SL_LLR_LINK_DN_BEHAVIOR_DISCARD     BIT(0)
+#define SL_LLR_LINK_DN_BEHAVIOR_BLOCK       BIT(1)
+#define SL_LLR_LINK_DN_BEHAVIOR_BEST_EFFORT BIT(2)
+
+#define SL_LLR_CONFIG_MAGIC 0x636c6c72
+#define SL_LLR_CONFIG_VER   1
+struct sl_llr_config {
+	u32 magic;
+	u32 ver;
+	u32 size;
+
+	u32 mode;
+	u32 setup_timeout_ms;
+	u32 start_timeout_ms;
+	u32 link_dn_behavior;
+
+	u32 options;
+};
+
+#define SL_LLR_POLICY_OPT_CONTINUOUS_START_TRIES BIT(0)
+
+#define SL_LLR_POLICY_MAGIC 0x636c6c72
+#define SL_LLR_POLICY_VER   1
+struct sl_llr_policy {
+	u32 magic;
+	u32 ver;
+	u32 size;
+
+	u32 options;
+};
+
+enum sl_llr_state {
+	SL_LLR_STATE_INVALID     = 0,
+	SL_LLR_STATE_OFF,
+	SL_LLR_STATE_CONFIGURED,
+	SL_LLR_STATE_SETUP_BUSY,
+	SL_LLR_STATE_SETUP,
+	SL_LLR_STATE_START_BUSY,
+	SL_LLR_STATE_RUNNING,
+	SL_LLR_STATE_CANCELING,
+	SL_LLR_STATE_STOP_BUSY,
+};
+
+struct sl_llr_data {
+	u32 magic;
+	u32 ver;
+	u32 size;
+
+	struct {
+		u64 calculated;
+		u64 min;
+		u64 max;
+		u64 average;
+	} loop;
+};
+
+struct sl_llr *sl_llr_new(struct sl_lgrp *lgrp, u8 llr_num, struct kobject *sysfs_parent);
+int            sl_llr_del(struct sl_llr *llr);
+
+int sl_llr_config_set(struct sl_llr *llr, struct sl_llr_config *llr_config);
+int sl_llr_policy_set(struct sl_llr *llr, struct sl_llr_policy *llr_policy);
+
+int sl_llr_setup(struct sl_llr *llr);
+int sl_llr_start(struct sl_llr *llr);
+int sl_llr_stop(struct sl_llr *llr);
+
+int sl_llr_state_get(struct sl_llr *llr, enum sl_llr_state *state);
+
+const char *sl_llr_state_str(u32 state);
+const char *sl_llr_link_dn_behavior_str(u32 behavior);
+
+#endif /* _LINUX_SL_LLR_H_ */
diff --git a/include/linux/hpe/sl/sl_mac.h b/include/linux/hpe/sl/sl_mac.h
new file mode 100644
index 000000000000..b145b31dbdb7
--- /dev/null
+++ b/include/linux/hpe/sl/sl_mac.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _LINUX_SL_MAC_H_
+#define _LINUX_SL_MAC_H_
+
+#include <linux/kobject.h>
+
+struct sl_lgrp;
+struct sl_mac;
+
+enum sl_mac_state {
+	SL_MAC_STATE_OFF,
+	SL_MAC_STATE_ON,
+};
+
+struct sl_mac *sl_mac_new(struct sl_lgrp *lgrp, u8 mac_num, struct kobject *sysfs_parent);
+int            sl_mac_del(struct sl_mac *mac);
+
+int sl_mac_tx_start(struct sl_mac *mac);
+int sl_mac_tx_stop(struct sl_mac *mac);
+int sl_mac_tx_state_get(struct sl_mac *mac, u32 *state);
+
+int sl_mac_rx_start(struct sl_mac *mac);
+int sl_mac_rx_stop(struct sl_mac *mac);
+int sl_mac_rx_state_get(struct sl_mac *mac, u32 *state);
+
+int sl_mac_reset(struct sl_mac *mac);
+
+const char *sl_mac_state_str(u32 state);
+
+#endif /* _LINUX_SL_MAC_H_ */
diff --git a/include/linux/hpe/sl/sl_media.h b/include/linux/hpe/sl/sl_media.h
new file mode 100644
index 000000000000..37984352f223
--- /dev/null
+++ b/include/linux/hpe/sl/sl_media.h
@@ -0,0 +1,191 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2021-2023,2024,2025,2026 Hewlett Packard Enterprise Development LP */
+
+#ifndef _LINUX_SL_MEDIA_H_
+#define _LINUX_SL_MEDIA_H_
+
+#include <linux/bitops.h>
+
+struct sl_lgrp;
+
+#define SL_MEDIA_FURCATION_UNKNOWN 0
+#define SL_MEDIA_FURCATION_X1      0x1 /* Unfurcated   */
+#define SL_MEDIA_FURCATION_X2      0x3 /* Bifurcated   */
+#define SL_MEDIA_FURCATION_X4      0xF /* Quadfurcated */
+
+#define SL_MEDIA_TYPE_HEADSHELL     BIT(0)
+#define SL_MEDIA_TYPE_BACKPLANE     BIT(1)
+#define SL_MEDIA_TYPE_ELECTRICAL    BIT(8)
+#define SL_MEDIA_TYPE_OPTICAL       BIT(9)
+#define SL_MEDIA_TYPE_PASSIVE       BIT(16)
+#define SL_MEDIA_TYPE_ACTIVE        BIT(17)
+#define SL_MEDIA_TYPE_ANALOG        BIT(24)
+#define SL_MEDIA_TYPE_DIGITAL       BIT(25)
+#define SL_MEDIA_SIGNAL_RETIME      BIT(26)
+#define SL_MEDIA_SIGNAL_REDRIVE     BIT(27)
+#define SL_MEDIA_TYPE_LOOPBACK      BIT(28)
+#define SL_MEDIA_TYPE_UNSUPPORTED   BIT(29)
+#define SL_MEDIA_TYPE_UNKNOWN       BIT(30)
+
+#define SL_MEDIA_TYPE_AOC		(SL_MEDIA_TYPE_HEADSHELL  | \
+					 SL_MEDIA_TYPE_OPTICAL    | \
+					 SL_MEDIA_TYPE_ACTIVE)
+/* POC is same type as POF and XCVR */
+#define SL_MEDIA_TYPE_POC		(SL_MEDIA_TYPE_HEADSHELL  | \
+					 SL_MEDIA_TYPE_OPTICAL    | \
+					 SL_MEDIA_TYPE_PASSIVE)
+/* PEC is same type as DAC */
+#define SL_MEDIA_TYPE_PEC		(SL_MEDIA_TYPE_HEADSHELL  | \
+					 SL_MEDIA_TYPE_ELECTRICAL | \
+					 SL_MEDIA_TYPE_PASSIVE)
+#define SL_MEDIA_TYPE_AEC		(SL_MEDIA_TYPE_HEADSHELL  | \
+					 SL_MEDIA_TYPE_ELECTRICAL | \
+					 SL_MEDIA_TYPE_ACTIVE     | \
+					 SL_MEDIA_SIGNAL_RETIME)
+#define SL_MEDIA_TYPE_ACC		(SL_MEDIA_TYPE_HEADSHELL  | \
+					 SL_MEDIA_TYPE_ELECTRICAL | \
+					 SL_MEDIA_TYPE_ACTIVE     | \
+					 SL_MEDIA_SIGNAL_REDRIVE)
+#define SL_MEDIA_TYPE_BKP		(SL_MEDIA_TYPE_BACKPLANE  | \
+					 SL_MEDIA_TYPE_ELECTRICAL | \
+					 SL_MEDIA_TYPE_PASSIVE)
+
+enum sl_media_vendor {
+	SL_MEDIA_VENDOR_TE           = 1,
+	SL_MEDIA_VENDOR_HISENSE,
+	SL_MEDIA_VENDOR_LEONI,
+	SL_MEDIA_VENDOR_FINISAR,
+	SL_MEDIA_VENDOR_MOLEX,
+	SL_MEDIA_VENDOR_BIZLINK,
+	SL_MEDIA_VENDOR_HPE,
+	SL_MEDIA_VENDOR_CLOUD_LIGHT,
+	SL_MEDIA_VENDOR_MULTILANE,
+	SL_MEDIA_VENDOR_AMPHENOL,
+	SL_MEDIA_VENDOR_UNKNOWN,
+};
+
+enum sl_media_shape {
+	SL_MEDIA_SHAPE_STRAIGHT    = 1,
+	SL_MEDIA_SHAPE_SPLITTER,
+	SL_MEDIA_SHAPE_BIFURCATED,
+	SL_MEDIA_SHAPE_UNKNOWN,
+};
+
+#define SL_MEDIA_CABLE_END_DD      0x41
+#define SL_MEDIA_CABLE_END_END1    0x42
+#define SL_MEDIA_CABLE_END_END2    0x43
+
+#define SL_MEDIA_SPEEDS_SUPPORT_CK_400G BIT(0)
+#define SL_MEDIA_SPEEDS_SUPPORT_CK_200G BIT(1)
+#define SL_MEDIA_SPEEDS_SUPPORT_CK_100G BIT(2)
+#define SL_MEDIA_SPEEDS_SUPPORT_BS_200G BIT(3)
+#define SL_MEDIA_SPEEDS_SUPPORT_BJ_100G BIT(4)
+#define SL_MEDIA_SPEEDS_SUPPORT_CD_100G BIT(5)
+#define SL_MEDIA_SPEEDS_SUPPORT_CD_50G  BIT(6)
+#define SL_MEDIA_SPEEDS_SUPPORT_CK_800G BIT(7)
+
+#define SL_MEDIA_INFO_AUTONEG                BIT(0)
+#define SL_MEDIA_INFO_FAKE                   BIT(1)
+#define SL_MEDIA_INFO_RESETTABLE             BIT(2)
+#define SL_MEDIA_INFO_LINKTRAIN              BIT(3)
+#define SL_MEDIA_INFO_SUPPORTED_SS200_CABLE  BIT(4)
+
+#define SL_MEDIA_ERROR_CABLE_UNSUPPORTED        BIT(0)
+#define SL_MEDIA_ERROR_CABLE_FORMAT_UNSUPPORTED BIT(1)
+#define SL_MEDIA_ERROR_CABLE_FW_UNSUPPORTED     BIT(2)
+#define SL_MEDIA_ERROR_CABLE_HEADSHELL_FAULT    BIT(3)
+#define SL_MEDIA_ERROR_TEMP_DOWN_LIMIT_DEFAULT  BIT(4)
+#define SL_MEDIA_ERROR_TEMP_WARN_LIMIT_DEFAULT  BIT(5)
+#define SL_MEDIA_ERROR_TRYABLE                  BIT(31)
+
+#define SL_MEDIA_QSFP_DENSITY_SINGLE   1
+#define SL_MEDIA_QSFP_DENSITY_DOUBLE   2
+#define SL_MEDIA_QSFP_DENSITY_EXTENDED 3
+#define SL_MEDIA_QSFP_DENSITY_UNKNOWN  4
+
+#define SL_MEDIA_JACK_TYPE_BACKPLANE   1
+#define SL_MEDIA_JACK_TYPE_SFP         2
+#define SL_MEDIA_JACK_TYPE_QSFP        3
+#define SL_MEDIA_JACK_TYPE_OSFP        4
+#define SL_MEDIA_JACK_TYPE_UNKNOWN     5
+#define SL_MEDIA_JACK_TYPE_UNSUPPORTED 6
+
+#define SL_MEDIA_ADVERTISED_FLAGS_TX_LOS BIT(1)
+#define SL_MEDIA_ADVERTISED_FLAGS_TX_LOL BIT(2)
+#define SL_MEDIA_ADVERTISED_FLAGS_RX_LOS BIT(1)
+#define SL_MEDIA_ADVERTISED_FLAGS_RX_LOL BIT(2)
+
+enum sl_media_mgmt_if {
+	SL_MEDIA_MGMT_IF_UNKNOWN = 0,
+	SL_MEDIA_MGMT_IF_SFF8636,
+	SL_MEDIA_MGMT_IF_CMIS,
+};
+
+struct sl_media_qsfp {
+	u32 density;
+};
+
+#define SL_MEDIA_SERIAL_NUM_SIZE                 17
+#define SL_MEDIA_HPE_PN_SIZE                     10
+#define SL_MEDIA_DATE_CODE_SIZE                  9
+#define SL_MEDIA_FIRMWARE_VERSION_SIZE           2
+#define SL_MEDIA_VENDOR_PN_SIZE                  17
+#define SL_MEDIA_SUPPORTED_FLAGS_ADVERTISED_SIZE 2
+
+#define SL_MEDIA_ATTR_MAGIC 0x6c6d6d61
+#define SL_MEDIA_ATTR_VER   11
+struct sl_media_attr {
+	u32           magic;
+	u32           ver;
+	u32           size;
+
+	u8            format;
+	u32           type;
+	u32           vendor;
+	char          vendor_pn_str[SL_MEDIA_VENDOR_PN_SIZE];
+	u32           length_cm;
+	unsigned long speeds_map;      /* Supported speeds on cable */
+	u32           hpe_pn;          /* HPE part number */
+	u32           shape;
+	char          hpe_pn_str[SL_MEDIA_HPE_PN_SIZE];
+	char          serial_num_str[SL_MEDIA_SERIAL_NUM_SIZE];
+	char          date_code_str[SL_MEDIA_DATE_CODE_SIZE];
+	u8            fw_ver[SL_MEDIA_FIRMWARE_VERSION_SIZE];
+	u32           max_speed;
+	u32           furcation;
+	u32           jack_type;
+	union {
+		struct sl_media_qsfp qsfp;
+	} jack_type_info;
+	u8            supported_flags_advertised[SL_MEDIA_SUPPORTED_FLAGS_ADVERTISED_SIZE];
+	u32           info;
+	u32           errors;
+};
+
+struct sl_lgrp;
+
+int sl_media_cable_insert(struct sl_lgrp *lgrp, u8 *eeprom_page0,
+			  u8 *eeprom_page1, u32 flags);
+int sl_media_cable_remove(struct sl_lgrp *lgrp);
+
+int sl_media_fake_headshell_insert(struct sl_lgrp *lgrp,  struct sl_media_attr *media_attr);
+int sl_media_fake_headshell_remove(struct sl_lgrp *lgrp);
+
+int sl_media_headshell_temp_get(struct sl_lgrp *lgrp, u8 *temp);
+
+const char *sl_media_furcation_str(u32 furcation);
+const char *sl_media_state_str(u8 state);
+const char *sl_media_cable_speed_state_str(u8 cable_shift_state);
+const char *sl_media_type_str(u32 type);
+const char *sl_media_shape_str(u32 shape);
+const char *sl_media_cable_end_str(u8 cable_end);
+const char *sl_media_vendor_str(u32 vendor);
+const char *sl_media_speed_str(u32 speed);
+const char *sl_media_ber_str(u8 media_interface);
+const char *sl_media_host_interface_str(u32 speed, u32 type);
+const char *sl_media_info_str(u32 info);
+const char *sl_media_opt_str(u32 option);
+const char *sl_media_error_str(u32 error);
+const char *sl_media_jack_type_str(u32 jack_type, u32 density);
+
+#endif /* _LINUX_SL_MEDIA_H_ */

-- 
2.56.0


^ permalink raw reply	[flat|nested] 25+ messages in thread
* [PATCH 10/23] net: hpe: sl: add the module entry points
  2026-10-30 20:58 [PATCH 00/23] Subject: [PATCH net-next 00/23] net/hpe: add HPE Slingshot NIC drivers Doug Ledford
                   ` (8 preceding siblings ...)
  2026-10-30 20:59 ` [PATCH 09/23] net: hpe: sl: add the Slingshot Link headers Doug Ledford
@ 2026-10-30 20:59 ` Doug Ledford
  2026-10-30 20:59 ` [PATCH 11/23] net: hpe: sl: add the core link state machines Doug Ledford
                   ` (13 subsequent siblings)
  23 siblings, 0 replies; 25+ messages in thread
From: Doug Ledford @ 2026-10-30 20:59 UTC (permalink / raw)
  To: Slingshot Open Source Team, Nathan Chancellor, Nicolas Schier,
	Richard Cochran, Andrew Lunn, David S. Miller, Eric Dumazet,
	Jakub Kicinski, Paolo Abeni, Sumit Semwal, Christian König,
	Guenter Roeck
  Cc: linux-kernel, netdev, linux-kbuild, Doug Ledford, Sandeep Bhoot

Add the module entry points and the logical device, link group, link,
MAC, LLR, FEC and media objects that make up the SL API used by the
NIC driver.

checkpatch --strict (100 columns) still reports the following in this
patch. They need coordination with the internal repositories this code
is maintained in and will be fixed in V2:
- WARNING: LONG_LINE_STRING (17), LONG_LINE (6)
- CHECK: BRACES (2), UNNECESSARY_PARENTHESES (2)

Co-developed-by: Sandeep Bhoot <sandeep.bhoot@hpe.com>
Signed-off-by: Sandeep Bhoot <sandeep.bhoot@hpe.com>
Signed-off-by: Doug Ledford <doug.ledford@hpe.com>
---
 drivers/net/ethernet/hpe/sl/sl_fec.c       |  68 ++++
 drivers/net/ethernet/hpe/sl/sl_ldev.c      | 133 ++++++
 drivers/net/ethernet/hpe/sl/sl_lgrp.c      | 409 +++++++++++++++++++
 drivers/net/ethernet/hpe/sl/sl_link.c      | 632 +++++++++++++++++++++++++++++
 drivers/net/ethernet/hpe/sl/sl_llr.c       | 289 +++++++++++++
 drivers/net/ethernet/hpe/sl/sl_mac.c       | 220 ++++++++++
 drivers/net/ethernet/hpe/sl/sl_media.c     | 356 ++++++++++++++++
 drivers/net/ethernet/hpe/sl/sl_media_nic.c |  23 ++
 drivers/net/ethernet/hpe/sl/sl_module.c    | 129 ++++++
 9 files changed, 2259 insertions(+)

diff --git a/drivers/net/ethernet/hpe/sl/sl_fec.c b/drivers/net/ethernet/hpe/sl/sl_fec.c
new file mode 100644
index 000000000000..af438c9443f7
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sl_fec.c
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/module.h>
+
+#include <linux/hpe/sl/sl_fec.h>
+
+#include "sl_log.h"
+#include "sl_link.h"
+#include "sl_ctrl_link_fec.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_FEC_LOG_NAME
+
+int sl_fec_info_get(struct sl_link *link, struct sl_fec_info *fec_info)
+{
+	int rtn;
+
+	rtn = sl_link_check(link);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "fec info get fail");
+		return rtn;
+	}
+	if (!fec_info) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL fec_info");
+		return -EINVAL;
+	}
+
+	return sl_ctrl_link_fec_info_get(link->ldev_num, link->lgrp_num, link->num, fec_info);
+}
+EXPORT_SYMBOL(sl_fec_info_get);
+
+int sl_fec_tail_get(struct sl_link *link, struct sl_fec_tail *fec_tail)
+{
+	int rtn;
+
+	rtn = sl_link_check(link);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "fec tail get fail");
+		return rtn;
+	}
+	if (!fec_tail) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL fec_tail");
+		return -EINVAL;
+	}
+
+	return sl_ctrl_link_fec_tail_get(link->ldev_num, link->lgrp_num, link->num, fec_tail);
+}
+EXPORT_SYMBOL(sl_fec_tail_get);
+
+int sl_fec_ber_calc(struct sl_fec_info *fec_info, struct sl_ber *ucw_ber, struct sl_ber *ccw_ber)
+{
+	if (!fec_info) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL fec_info");
+		return -EINVAL;
+	}
+	if (!ucw_ber) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL ucw_ber");
+		return -EINVAL;
+	}
+	if (!ccw_ber) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL ccw_ber");
+		return -EINVAL;
+	}
+
+	return sl_ctrl_link_fec_ber_calc(fec_info, ucw_ber, ccw_ber);
+}
+EXPORT_SYMBOL(sl_fec_ber_calc);
diff --git a/drivers/net/ethernet/hpe/sl/sl_ldev.c b/drivers/net/ethernet/hpe/sl/sl_ldev.c
new file mode 100644
index 000000000000..631d215fb7f4
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sl_ldev.c
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/module.h>
+#include <linux/workqueue.h>
+#include <linux/err.h>
+
+#include <linux/hpe/sl/sl_ldev.h>
+
+#include "sl_asic.h"
+#include "sl_log.h"
+#include "sl_ldev.h"
+#include "sl_sysfs.h"
+#include "sl_ctrl_ldev.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_LDEV_LOG_NAME
+
+static struct sl_ldev ldevs[SL_ASIC_MAX_LDEVS];
+
+void sl_ldev_init(void)
+{
+	u8 ldev_num;
+
+	for (ldev_num = 0; ldev_num < SL_ASIC_MAX_LDEVS; ++ldev_num) {
+		ldevs[ldev_num].magic = SL_LDEV_MAGIC;
+		ldevs[ldev_num].ver   = SL_LDEV_VER;
+		ldevs[ldev_num].size  = sizeof(struct sl_ldev);
+		ldevs[ldev_num].num   = ldev_num;
+	}
+}
+
+int sl_ldev_check(struct sl_ldev *ldev)
+{
+	if (!ldev) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL ldev");
+		return -EINVAL;
+	}
+	if (IS_ERR(ldev)) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "ldev pointer error");
+		return -EINVAL;
+	}
+	if (ldev->magic != SL_LDEV_MAGIC) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "bad ldev magic");
+		return -EINVAL;
+	}
+	if (ldev->ver != SL_LDEV_VER) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "bad ldev version");
+		return -EINVAL;
+	}
+	if (ldev->num >= SL_ASIC_MAX_LDEVS) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "bad ldev num");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+struct sl_ldev *sl_ldev_new(u8 ldev_num,
+			    struct workqueue_struct *workq, struct sl_ldev_attr *ldev_attr)
+{
+	int rtn;
+
+	if (ldev_num >= SL_ASIC_MAX_LDEVS) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "invalid (ldev_num = %u)", ldev_num);
+		return ERR_PTR(-EINVAL);
+	}
+	rtn = sl_ldev_attr_check(ldev_attr);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "new fail");
+		return ERR_PTR(rtn);
+	}
+
+	rtn = sl_ctrl_ldev_new(ldev_num, workq, ldev_attr);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "new fail");
+		return ERR_PTR(rtn);
+	}
+
+	return &ldevs[ldev_num];
+}
+EXPORT_SYMBOL(sl_ldev_new);
+
+int sl_ldev_sysfs_parent_set(struct sl_ldev *ldev, struct kobject *parent)
+{
+	int rtn;
+
+	rtn = sl_ldev_check(ldev);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "parent set fail");
+		return rtn;
+	}
+	if (!parent) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL parent");
+		return -EINVAL;
+	}
+
+	return sl_sysfs_ldev_create(ldev->num, parent);
+}
+EXPORT_SYMBOL(sl_ldev_sysfs_parent_set);
+
+int sl_ldev_serdes_init(struct sl_ldev *ldev)
+{
+	int rtn;
+
+	rtn = sl_ldev_check(ldev);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "serdes init fail");
+		return rtn;
+	}
+
+	return sl_ctrl_ldev_serdes_init(ldev->num);
+}
+EXPORT_SYMBOL(sl_ldev_serdes_init);
+
+int sl_ldev_del(struct sl_ldev *ldev)
+{
+	int rtn;
+
+	rtn = sl_ldev_check(ldev);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "del fail");
+		return rtn;
+	}
+
+	return sl_ctrl_ldev_del(ldev->num);
+}
+EXPORT_SYMBOL(sl_ldev_del);
+
+void sl_ldev_exit(void)
+{
+	sl_ctrl_ldev_exit();
+}
diff --git a/drivers/net/ethernet/hpe/sl/sl_lgrp.c b/drivers/net/ethernet/hpe/sl/sl_lgrp.c
new file mode 100644
index 000000000000..bb2dc68f4198
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sl_lgrp.c
@@ -0,0 +1,409 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2023-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+
+#include <linux/hpe/sl/sl_lgrp.h>
+
+#include "sl_asic.h"
+#include "sl_log.h"
+#include "sl_ldev.h"
+#include "sl_lgrp.h"
+#include "sl_core_lgrp.h"
+#include "sl_core_link.h"
+#include "sl_ctrl_lgrp.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_LGRP_LOG_NAME
+
+static struct sl_lgrp lgrps[SL_ASIC_MAX_LDEVS][SL_ASIC_MAX_LGRPS];
+
+void sl_lgrp_init(void)
+{
+	u8 ldev_num;
+	u8 lgrp_num;
+
+	for (ldev_num = 0; ldev_num < SL_ASIC_MAX_LDEVS; ++ldev_num) {
+		for (lgrp_num = 0; lgrp_num < SL_ASIC_MAX_LGRPS; ++lgrp_num) {
+			lgrps[ldev_num][lgrp_num].magic    = SL_LGRP_MAGIC;
+			lgrps[ldev_num][lgrp_num].ver      = SL_LGRP_VER;
+			lgrps[ldev_num][lgrp_num].num      = lgrp_num;
+			lgrps[ldev_num][lgrp_num].ldev_num = ldev_num;
+		}
+	}
+}
+
+int sl_lgrp_check(struct sl_lgrp *lgrp)
+{
+	if (!lgrp) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL lgrp");
+		return -EINVAL;
+	}
+	if (IS_ERR(lgrp)) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "lgrp pointer error");
+		return -EINVAL;
+	}
+	if (lgrp->magic != SL_LGRP_MAGIC) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "bad lgrp magic");
+		return -EINVAL;
+	}
+	if (lgrp->ver != SL_LGRP_VER) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "bad lgrp version");
+		return -EINVAL;
+	}
+	if (lgrp->num >= SL_ASIC_MAX_LGRPS) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "bad lgrp num");
+		return -EINVAL;
+	}
+	if (lgrp->ldev_num >= SL_ASIC_MAX_LDEVS) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "bad ldev num");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int sl_lgrp_config_check(struct sl_lgrp_config *lgrp_config)
+{
+	if (!lgrp_config) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL lgrp_config");
+		return -EINVAL;
+	}
+	if (IS_ERR(lgrp_config)) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "lgrp_config pointer error");
+		return -EINVAL;
+	}
+	if (lgrp_config->magic != SL_LGRP_CONFIG_MAGIC) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "bad lgrp_config magic");
+		return -EINVAL;
+	}
+	if (lgrp_config->ver != SL_LGRP_CONFIG_VER) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "bad lgrp_config version");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int sl_lgrp_policy_check(struct sl_lgrp_policy *lgrp_policy)
+{
+	if (!lgrp_policy) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL lgrp_policy");
+		return -EINVAL;
+	}
+	if (IS_ERR(lgrp_policy)) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "lgrp_policy pointer error");
+		return -EINVAL;
+	}
+	if (lgrp_policy->magic != SL_LGRP_POLICY_MAGIC) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "bad lgrp_policy magic");
+		return -EINVAL;
+	}
+	if (lgrp_policy->ver != SL_LGRP_POLICY_VER) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "bad lgrp_policy version");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int sl_lgrp_hw_attr_set(struct sl_lgrp *lgrp, struct sl_hw_attr *hw_attr)
+{
+	int rtn;
+
+	rtn = sl_lgrp_check(lgrp);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "hw attr set fail");
+		return rtn;
+	}
+	if (!hw_attr) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL hw_attr");
+		return -EINVAL;
+	}
+
+	return sl_core_lgrp_hw_attr_set(lgrp->ldev_num, lgrp->num, hw_attr);
+}
+EXPORT_SYMBOL(sl_lgrp_hw_attr_set);
+
+struct sl_lgrp *sl_lgrp_new(struct sl_ldev *ldev, u8 lgrp_num, struct kobject *sysfs_parent)
+{
+	int rtn;
+
+	rtn = sl_ldev_check(ldev);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "new fail");
+		return ERR_PTR(rtn);
+	}
+	if (lgrp_num >= SL_ASIC_MAX_LGRPS) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "invalid (lgrp_num = %u)", lgrp_num);
+		return ERR_PTR(-EINVAL);
+	}
+
+	rtn = sl_ctrl_lgrp_new(ldev->num, lgrp_num, sysfs_parent);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "new fail");
+		return ERR_PTR(rtn);
+	}
+
+	return &lgrps[ldev->num][lgrp_num];
+}
+EXPORT_SYMBOL(sl_lgrp_new);
+
+int sl_lgrp_del(struct sl_lgrp *lgrp)
+{
+	int rtn;
+
+	rtn = sl_lgrp_check(lgrp);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "del fail");
+		return rtn;
+	}
+
+	return sl_ctrl_lgrp_del(lgrp->ldev_num, lgrp->num);
+}
+EXPORT_SYMBOL(sl_lgrp_del);
+
+int sl_lgrp_config_set(struct sl_lgrp *lgrp, struct sl_lgrp_config *lgrp_config)
+{
+	int rtn;
+
+	rtn = sl_lgrp_check(lgrp);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "config set fail");
+		return rtn;
+	}
+	rtn = sl_lgrp_config_check(lgrp_config);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "config set fail");
+		return rtn;
+	}
+
+	return sl_ctrl_lgrp_config_set(lgrp->ldev_num, lgrp->num, lgrp_config);
+}
+EXPORT_SYMBOL(sl_lgrp_config_set);
+
+int sl_lgrp_policy_set(struct sl_lgrp *lgrp, struct sl_lgrp_policy *lgrp_policy)
+{
+	int rtn;
+
+	rtn = sl_lgrp_check(lgrp);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "policy set fail");
+		return rtn;
+	}
+	rtn = sl_lgrp_policy_check(lgrp_policy);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "policy set fail");
+		return rtn;
+	}
+
+	return sl_ctrl_lgrp_policy_set(lgrp->ldev_num, lgrp->num, lgrp_policy);
+}
+EXPORT_SYMBOL(sl_lgrp_policy_set);
+
+int sl_lgrp_notif_callback_reg(struct sl_lgrp *lgrp, sl_lgrp_notif_t callback,
+			       u32 types, void *tag)
+{
+	int rtn;
+
+	rtn = sl_lgrp_check(lgrp);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "callback reg fail");
+		return rtn;
+	}
+	if (!callback) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL callback");
+		return -EINVAL;
+	}
+
+	return sl_ctrl_lgrp_notif_callback_reg(lgrp->ldev_num, lgrp->num, callback, types, tag);
+}
+EXPORT_SYMBOL(sl_lgrp_notif_callback_reg);
+
+int sl_lgrp_notif_callback_unreg(struct sl_lgrp *lgrp, sl_lgrp_notif_t callback,
+				 u32 types)
+{
+	int rtn;
+
+	rtn = sl_lgrp_check(lgrp);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "callback unreg fail");
+		return rtn;
+	}
+	if (!callback) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL callback");
+		return -EINVAL;
+	}
+
+	return sl_ctrl_lgrp_notif_callback_unreg(lgrp->ldev_num, lgrp->num, callback, types);
+}
+EXPORT_SYMBOL(sl_lgrp_notif_callback_unreg);
+
+int sl_lgrp_connect_id_set(struct sl_lgrp *lgrp, const char *connect_id)
+{
+	int rtn;
+
+	rtn = sl_lgrp_check(lgrp);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "id set fail");
+		return rtn;
+	}
+	if (!connect_id) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL connect_id");
+		return -EINVAL;
+	}
+
+	return sl_ctrl_lgrp_connect_id_set(lgrp->ldev_num, lgrp->num, connect_id);
+}
+EXPORT_SYMBOL(sl_lgrp_connect_id_set);
+
+const char *sl_lgrp_config_tech_str(u32 config)
+{
+	if (config == SL_LGRP_CONFIG_TECH_CK_400G)
+		return "ck400G";
+	if (config == SL_LGRP_CONFIG_TECH_CK_200G)
+		return "ck200G";
+	if (config == SL_LGRP_CONFIG_TECH_CK_100G)
+		return "ck100G";
+	if (config == SL_LGRP_CONFIG_TECH_BS_200G)
+		return "bs200G";
+	if (config == SL_LGRP_CONFIG_TECH_CD_100G)
+		return "cd100G";
+	if (config == SL_LGRP_CONFIG_TECH_CD_50G)
+		return "cd50G";
+	if (config == SL_LGRP_CONFIG_TECH_BJ_100G)
+		return "bj100G";
+
+	return "unknown";
+}
+EXPORT_SYMBOL(sl_lgrp_config_tech_str);
+
+const char *sl_lgrp_config_fec_str(u32 config)
+{
+	if (config == SL_LGRP_CONFIG_FEC_RS_LL)
+		return "reed-solomon-low-latency";
+	if (config == SL_LGRP_CONFIG_FEC_RS)
+		return "reed-solomon";
+
+	return "unknown";
+}
+EXPORT_SYMBOL(sl_lgrp_config_fec_str);
+
+const char *sl_lgrp_furcation_str(u32 furcation)
+{
+	if (furcation == SL_MEDIA_FURCATION_X1)
+		return "unfurcated";
+	if (furcation == SL_MEDIA_FURCATION_X2)
+		return "bifurcated";
+	if (furcation == SL_MEDIA_FURCATION_X4)
+		return "quadfurcated";
+
+	return "unknown";
+}
+EXPORT_SYMBOL(sl_lgrp_furcation_str);
+
+const char *sl_lgrp_notif_str(u32 notif)
+{
+	switch (notif) {
+	case SL_LGRP_NOTIF_INVALID:
+		return "invalid";
+	case SL_LGRP_NOTIF_LINK_UP:
+		return "link-up";
+	case SL_LGRP_NOTIF_LINK_UP_FAIL:
+		return "link-up-fail";
+	case SL_LGRP_NOTIF_LINK_DOWN:
+		return "link-down";
+	case SL_LGRP_NOTIF_LINK_ASYNC_DOWN:
+		return "link-async-down";
+	case SL_LGRP_NOTIF_LINK_ERROR:
+		return "link-error";
+	case SL_LGRP_NOTIF_LINK_UCW_WARN:
+		return "link-ucw-warn";
+	case SL_LGRP_NOTIF_LINK_CCW_WARN:
+		return "link-ccw-warn";
+	case SL_LGRP_NOTIF_LLR_SETUP:
+		return "llr-setup";
+	case SL_LGRP_NOTIF_LLR_SETUP_TIMEOUT:
+		return "llr-setup-timeout";
+	case SL_LGRP_NOTIF_LLR_RUNNING:
+		return "llr-running";
+	case SL_LGRP_NOTIF_LLR_START_TIMEOUT:
+		return "llr-start-timeout";
+	case SL_LGRP_NOTIF_LLR_CANCELED:
+		return "llr-canceled";
+	case SL_LGRP_NOTIF_LLR_ERROR:
+		return "llr-error";
+	case SL_LGRP_NOTIF_MEDIA_PRESENT:
+		return "media-present";
+	case SL_LGRP_NOTIF_MEDIA_NOT_PRESENT:
+		return "media-not-present";
+	case SL_LGRP_NOTIF_MEDIA_ERROR:
+		return "media-error";
+	case SL_LGRP_NOTIF_MEDIA_HOT:
+		return "media-hot";
+	case SL_LGRP_NOTIF_MEDIA_COLD:
+		return "media-cold";
+	case SL_LGRP_NOTIF_MEDIA_WARM:
+		return "media-warm";
+	case SL_LGRP_NOTIF_AN_DATA:
+		return "an-data";
+	case SL_LGRP_NOTIF_AN_TIMEOUT:
+		return "an-timeout";
+	case SL_LGRP_NOTIF_AN_ERROR:
+		return "an-error";
+	case SL_LGRP_NOTIF_LANE_DEGRADE:
+		return "auto-lane-degrade";
+	case SL_LGRP_NOTIF_LANE_DEGRADE_RECOVERY:
+		return "auto-lane-degrade-recovery";
+	case SL_LGRP_NOTIF_PML_RECOVERY:
+		return "pml-recovery";
+	case SL_LGRP_NOTIF_LINK_DOWN_REQ:
+		return "link-down-request";
+	default:
+		return "unknown";
+	}
+}
+EXPORT_SYMBOL(sl_lgrp_notif_str);
+
+const char *sl_lgrp_config_opt_str(u32 option)
+{
+	switch (option) {
+	case SL_LGRP_CONFIG_OPT_SERDES_LOOPBACK_ENABLE:
+		return "loopback-serdes-enable";
+	default:
+		return "unknown";
+	}
+}
+EXPORT_SYMBOL(sl_lgrp_config_opt_str);
+
+const char *sl_lgrp_fec_mode_str(u32 mode)
+{
+	switch (mode) {
+	case SL_LGRP_FEC_MODE_OFF:
+		return "off";
+	case SL_LGRP_FEC_MODE_MONITOR:
+		return "monitor";
+	case SL_LGRP_FEC_MODE_CORRECT:
+		return "correct";
+	default:
+		return "unknown";
+	}
+}
+EXPORT_SYMBOL(sl_lgrp_fec_mode_str);
+
+const char *sl_lgrp_llr_mode_str(u32 mode)
+{
+	switch (mode) {
+	case SL_LGRP_LLR_MODE_OFF:
+		return "off";
+	case SL_LGRP_LLR_MODE_MONITOR:
+		return "monitor";
+	case SL_LGRP_LLR_MODE_ON:
+		return "on";
+	default:
+		return "unknown";
+	}
+}
+EXPORT_SYMBOL(sl_lgrp_llr_mode_str);
diff --git a/drivers/net/ethernet/hpe/sl/sl_link.c b/drivers/net/ethernet/hpe/sl/sl_link.c
new file mode 100644
index 000000000000..c66e48a62748
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sl_link.c
@@ -0,0 +1,632 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2023-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/module.h>
+#include <linux/err.h>
+
+#include <linux/hpe/sl/sl_link.h>
+
+#include "sl_asic.h"
+#include "sl_log.h"
+#include "sl_lgrp.h"
+#include "sl_link.h"
+#include "sl_core_str.h"
+#include "sl_ctrl_link.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_LINK_LOG_NAME
+
+static struct sl_link links[SL_ASIC_MAX_LDEVS][SL_ASIC_MAX_LGRPS][SL_ASIC_MAX_LINKS];
+
+void sl_link_init(void)
+{
+	u8 ldev_num;
+	u8 lgrp_num;
+	u8 link_num;
+
+	for (ldev_num = 0; ldev_num < SL_ASIC_MAX_LDEVS; ++ldev_num) {
+		for (lgrp_num = 0; lgrp_num < SL_ASIC_MAX_LGRPS; ++lgrp_num) {
+			for (link_num = 0; link_num < SL_ASIC_MAX_LINKS; ++link_num) {
+				links[ldev_num][lgrp_num][link_num].magic    = SL_LINK_MAGIC;
+				links[ldev_num][lgrp_num][link_num].ver      = SL_LINK_VER;
+				links[ldev_num][lgrp_num][link_num].num      = link_num;
+				links[ldev_num][lgrp_num][link_num].lgrp_num = lgrp_num;
+				links[ldev_num][lgrp_num][link_num].ldev_num = ldev_num;
+			}
+		}
+	}
+}
+
+int sl_link_check(struct sl_link *link)
+{
+	if (!link) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL link");
+		return -EINVAL;
+	}
+	if (IS_ERR(link)) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "link pointer error");
+		return -EINVAL;
+	}
+	if (link->magic != SL_LINK_MAGIC) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "bad link magic");
+		return -EINVAL;
+	}
+	if (link->ver != SL_LINK_VER) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "bad link version");
+		return -EINVAL;
+	}
+	if (link->num >= SL_ASIC_MAX_LINKS) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "bad link num");
+		return -EINVAL;
+	}
+	if (link->lgrp_num >= SL_ASIC_MAX_LGRPS) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "bad lgrp num");
+		return -EINVAL;
+	}
+	if (link->ldev_num >= SL_ASIC_MAX_LDEVS) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "bad ldev num");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int sl_link_config_check(struct sl_link_config *link_config)
+{
+	if (!link_config) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL link_config");
+		return -EINVAL;
+	}
+	if (IS_ERR(link_config)) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "link_config pointer error");
+		return -EINVAL;
+	}
+	if (link_config->magic != SL_LINK_CONFIG_MAGIC) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "bad link_config magic");
+		return -EINVAL;
+	}
+	if (link_config->ver != SL_LINK_CONFIG_VER) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "bad link_config version");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int sl_link_policy_check(struct sl_link_policy *link_policy)
+{
+	if (!link_policy) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL link_policy");
+		return -EINVAL;
+	}
+	if (IS_ERR(link_policy)) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "link_policy pointer error");
+		return -EINVAL;
+	}
+	if (link_policy->magic != SL_LINK_POLICY_MAGIC) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "bad link_policy magic");
+		return -EINVAL;
+	}
+	if (link_policy->ver != SL_LINK_POLICY_VER) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "bad link_policy version");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+struct sl_link *sl_link_new(struct sl_lgrp *lgrp, u8 link_num, struct kobject *sysfs_parent)
+{
+	int rtn;
+
+	rtn = sl_lgrp_check(lgrp);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "new fail");
+		return ERR_PTR(rtn);
+	}
+	if (link_num >= SL_ASIC_MAX_LINKS) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "invalid (link_num = %u)", link_num);
+		return ERR_PTR(-EINVAL);
+	}
+
+	rtn = sl_ctrl_link_new(lgrp->ldev_num, lgrp->num, link_num, sysfs_parent);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "new fail");
+		return ERR_PTR(rtn);
+	}
+
+	return &links[lgrp->ldev_num][lgrp->num][link_num];
+}
+EXPORT_SYMBOL(sl_link_new);
+
+int sl_link_del(struct sl_link *link)
+{
+	int rtn;
+
+	rtn = sl_link_check(link);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "del fail");
+		return rtn;
+	}
+
+	return sl_ctrl_link_del(link->ldev_num, link->lgrp_num, link->num);
+}
+EXPORT_SYMBOL(sl_link_del);
+
+int sl_link_config_set(struct sl_link *link, struct sl_link_config *link_config)
+{
+	int rtn;
+
+	rtn = sl_link_check(link);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "link config set fail");
+		return rtn;
+	}
+	rtn = sl_link_config_check(link_config);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "link config set fail");
+		return rtn;
+	}
+
+	return sl_ctrl_link_config_set(link->ldev_num, link->lgrp_num, link->num, link_config);
+}
+EXPORT_SYMBOL(sl_link_config_set);
+
+int sl_link_policy_set(struct sl_link *link, struct sl_link_policy *link_policy)
+{
+	int rtn;
+
+	rtn = sl_link_check(link);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "policy set fail");
+		return rtn;
+	}
+	rtn = sl_link_policy_check(link_policy);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "policy set fail");
+		return rtn;
+	}
+
+	return sl_ctrl_link_policy_set(link->ldev_num, link->lgrp_num, link->num, link_policy);
+}
+EXPORT_SYMBOL(sl_link_policy_set);
+
+int sl_link_an_lp_caps_get(struct sl_link *link, struct sl_link_caps *caps, u32 timeout_ms, u32 flags)
+{
+	int rtn;
+
+	rtn = sl_link_check(link);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "lp caps get fail");
+		return rtn;
+	}
+	if (!caps) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL caps");
+		return -EINVAL;
+	}
+	if (timeout_ms == 0) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "0 timeout");
+		return -EINVAL;
+	}
+
+	return sl_ctrl_link_an_lp_caps_get(link->ldev_num, link->lgrp_num, link->num, caps, timeout_ms, flags);
+}
+EXPORT_SYMBOL(sl_link_an_lp_caps_get);
+
+int sl_link_an_lp_caps_stop(struct sl_link *link)
+{
+	int rtn;
+
+	rtn = sl_link_check(link);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "lp caps stop fail");
+		return rtn;
+	}
+
+	return sl_ctrl_link_an_lp_caps_stop(link->ldev_num, link->lgrp_num, link->num);
+}
+EXPORT_SYMBOL(sl_link_an_lp_caps_stop);
+
+int sl_link_up(struct sl_link *link)
+{
+	int rtn;
+
+	rtn = sl_link_check(link);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "link up fail");
+		return rtn;
+	}
+
+	return sl_ctrl_link_up(link->ldev_num, link->lgrp_num, link->num);
+}
+EXPORT_SYMBOL(sl_link_up);
+
+int sl_link_down(struct sl_link *link)
+{
+	int rtn;
+
+	rtn = sl_link_check(link);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "link down fail");
+		return rtn;
+	}
+
+	return sl_ctrl_link_down(link->ldev_num, link->lgrp_num, link->num);
+}
+EXPORT_SYMBOL(sl_link_down);
+
+int sl_link_reset(struct sl_link *link)
+{
+	int rtn;
+
+	rtn = sl_link_check(link);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "link reset fail");
+		return rtn;
+	}
+
+	return sl_ctrl_link_reset(link->ldev_num, link->lgrp_num, link->num);
+}
+EXPORT_SYMBOL(sl_link_reset);
+
+int sl_link_clocks_get(struct sl_link *link, u32 *up_count, s64 *up_time, s64 *total_time)
+{
+	int rtn;
+	s64 up;
+
+	rtn = sl_link_check(link);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "link clocks get fail");
+		return rtn;
+	}
+
+	rtn = sl_ctrl_link_up_clocks_get(link->ldev_num, link->lgrp_num, link->num, up_time, total_time, &up);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "link_up_clocks_get failed [%d]", rtn);
+		return rtn;
+	}
+
+	rtn = sl_ctrl_link_up_count_get(link->ldev_num, link->lgrp_num, link->num, up_count);
+	if (rtn)
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "link_up_count_get failed [%d]", rtn);
+
+	return rtn;
+}
+EXPORT_SYMBOL(sl_link_clocks_get);
+
+int sl_link_state_get(struct sl_link *link, u32 *state)
+{
+	int rtn;
+
+	rtn = sl_link_check(link);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "link state get fail");
+		return rtn;
+	}
+	if (!state) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL state");
+		return -EINVAL;
+	}
+
+	return sl_ctrl_link_state_get_cmd(link->ldev_num, link->lgrp_num, link->num, state);
+}
+EXPORT_SYMBOL(sl_link_state_get);
+
+const char *sl_link_state_str(u32 state)
+{
+	switch (state) {
+	case SL_LINK_STATE_INVALID:
+		return "invalid";
+	case SL_LINK_STATE_DOWN:
+		return "down";
+	case SL_LINK_STATE_AN:
+		return "autoneg";
+	case SL_LINK_STATE_STARTING:
+		return "starting";
+	case SL_LINK_STATE_UP:
+		return "up";
+	case SL_LINK_STATE_UP_DOWN_REQ:
+		return "up-requested-down";
+	case SL_LINK_STATE_STOPPING:
+		return "stopping";
+	default:
+		return "unknown";
+	}
+}
+EXPORT_SYMBOL(sl_link_state_str);
+
+const char *sl_link_degrade_state_str(u32 degrade_state)
+{
+	switch (degrade_state) {
+	case SL_LINK_DEGRADE_STATE_ACTIVE:
+		return "active";
+	case SL_LINK_DEGRADE_STATE_INACTIVE:
+		return "inactive";
+	case SL_LINK_DEGRADE_STATE_FAILED:
+		return "error";
+	case SL_LINK_DEGRADE_STATE_INVALID:
+		return "invalid";
+	default:
+		return "unknown";
+	}
+}
+EXPORT_SYMBOL(sl_link_degrade_state_str);
+
+const char *sl_link_an_lp_caps_state_str(u32 lp_caps_state)
+{
+	switch (lp_caps_state) {
+	case SL_CORE_LINK_LP_CAPS_NOT_RUNNING:
+		return "not_running";
+	case SL_CORE_LINK_LP_CAPS_RUNNING:
+		return "running";
+	case SL_CORE_LINK_LP_CAPS_DATA:
+		return "data";
+	case SL_CORE_LINK_LP_CAPS_TIMEOUT:
+		return "timeout";
+	case SL_CORE_LINK_LP_CAPS_ERROR:
+		return "error";
+	default:
+		return "unknown";
+	}
+}
+EXPORT_SYMBOL(sl_link_an_lp_caps_state_str);
+
+const char *sl_link_config_opt_str(u32 option)
+{
+	switch (option) {
+	case SL_LINK_CONFIG_OPT_AUTONEG_ENABLE:
+		return "autoneg-enable";
+	case SL_LINK_CONFIG_OPT_AUTONEG_CONTINUOUS_ENABLE:
+		return "autoneg-continuous";
+	case SL_LINK_CONFIG_OPT_HEADSHELL_LOOPBACK_ENABLE:
+		return "loopback-headshell-enable";
+	case SL_LINK_CONFIG_OPT_REMOTE_LOOPBACK_ENABLE:
+		return "loopback-remote-enable";
+	default:
+		return "unknown";
+	}
+}
+EXPORT_SYMBOL(sl_link_config_opt_str);
+
+const char *sl_link_policy_opt_str(u32 option)
+{
+	switch (option) {
+	case SL_LINK_POLICY_OPT_KEEP_SERDES_UP:
+		return "keep-serdes-up";
+	case SL_LINK_POLICY_OPT_USE_UNSUPPORTED_CABLE:
+		return "use-unsupported-cable";
+	case SL_LINK_POLICY_OPT_IGNORE_MEDIA_ERROR:
+		return "ignore-media-error";
+	case SL_LINK_POLICY_OPT_USE_SUPPORTED_SS200_CABLE:
+		return "use-supported-ss200-cable";
+	case SL_LINK_POLICY_OPT_LINK_DOWN_REQ:
+		return "link-down-request";
+	default:
+		return "unknown";
+	}
+}
+EXPORT_SYMBOL(sl_link_policy_opt_str);
+
+#define SL_LINK_DOWN_INFO_MASK (     \
+	SL_LINK_DOWN_RETRYABLE      |\
+	SL_LINK_DOWN_ORIGIN_ASYNC   |\
+	SL_LINK_DOWN_ORIGIN_LINK_UP)
+
+static int sl_link_down_cause_map_masked_str(unsigned long cause_map, char *cause_str, unsigned int cause_str_size,
+					     u64 mask)
+{
+	int rtn;
+	int str_pos;
+	int which;
+
+	if (!cause_str)
+		return -EINVAL;
+
+	if (cause_str_size < SL_LINK_DOWN_CAUSE_STR_SIZE_MIN)
+		return -EINVAL;
+
+	cause_map &= mask;
+
+	if (cause_map == SL_LINK_DOWN_CAUSE_NONE) {
+		scnprintf(cause_str, cause_str_size, "none");
+		return 0;
+	}
+
+	str_pos = 0;
+
+	for_each_set_bit(which, &cause_map, sizeof(cause_map) * BITS_PER_BYTE) {
+
+		switch (BIT(which)) {
+		case SL_LINK_DOWN_CAUSE_UCW:
+			rtn = snprintf(cause_str + str_pos, cause_str_size - str_pos, "ucw ");
+			break;
+		case SL_LINK_DOWN_CAUSE_LF:
+			rtn = snprintf(cause_str + str_pos, cause_str_size - str_pos, "lcl-fault ");
+			break;
+		case SL_LINK_DOWN_CAUSE_RF:
+			rtn = snprintf(cause_str + str_pos, cause_str_size - str_pos, "rmt-fault ");
+			break;
+		case SL_LINK_DOWN_CAUSE_DOWN:
+			rtn = snprintf(cause_str + str_pos, cause_str_size - str_pos, "link-down ");
+			break;
+		case SL_LINK_DOWN_CAUSE_UP_TRIES:
+			rtn = snprintf(cause_str + str_pos, cause_str_size - str_pos, "up-tries ");
+			break;
+		case SL_LINK_DOWN_CAUSE_AUTONEG_NOMATCH:
+			rtn = snprintf(cause_str + str_pos, cause_str_size - str_pos, "autoneg-nomatch ");
+			break;
+		case SL_LINK_DOWN_CAUSE_AUTONEG:
+			rtn = snprintf(cause_str + str_pos, cause_str_size - str_pos, "autoneg-fail ");
+			break;
+		case SL_LINK_DOWN_CAUSE_CONFIG:
+			rtn = snprintf(cause_str + str_pos, cause_str_size - str_pos, "config ");
+			break;
+		case SL_LINK_DOWN_CAUSE_INTR_ENABLE:
+			rtn = snprintf(cause_str + str_pos, cause_str_size - str_pos, "intr-enable ");
+			break;
+		case SL_LINK_DOWN_CAUSE_TIMEOUT:
+			rtn = snprintf(cause_str + str_pos, cause_str_size - str_pos, "timeout ");
+			break;
+		case SL_LINK_DOWN_CAUSE_CANCELED:
+			rtn = snprintf(cause_str + str_pos, cause_str_size - str_pos, "canceled ");
+			break;
+		case SL_LINK_DOWN_CAUSE_COMMAND:
+			rtn = snprintf(cause_str + str_pos, cause_str_size - str_pos, "command ");
+			break;
+		case SL_LINK_DOWN_CAUSE_DOWNSHIFT:
+			rtn = snprintf(cause_str + str_pos, cause_str_size - str_pos, "downshift-fail ");
+			break;
+		case SL_LINK_DOWN_CAUSE_LLR_REPLAY_MAX:
+			rtn = snprintf(cause_str + str_pos, cause_str_size - str_pos, "llr-replay-at-max ");
+			break;
+		case SL_LINK_DOWN_CAUSE_UPSHIFT:
+			rtn = snprintf(cause_str + str_pos, cause_str_size - str_pos, "upshift-fail ");
+			break;
+		case SL_LINK_DOWN_CAUSE_AUTONEG_CONFIG:
+			rtn = snprintf(cause_str + str_pos, cause_str_size - str_pos, "an-config ");
+			break;
+		case SL_LINK_DOWN_CAUSE_PCS_FAULT:
+			rtn = snprintf(cause_str + str_pos, cause_str_size - str_pos, "pcs-fault ");
+			break;
+		case SL_LINK_DOWN_CAUSE_SERDES_PLL:
+			rtn = snprintf(cause_str + str_pos, cause_str_size - str_pos, "serdes-pll ");
+			break;
+		case SL_LINK_DOWN_CAUSE_SERDES_CONFIG:
+			rtn = snprintf(cause_str + str_pos, cause_str_size - str_pos, "serdes-config ");
+			break;
+		case SL_LINK_DOWN_CAUSE_SERDES_SIGNAL:
+			rtn = snprintf(cause_str + str_pos, cause_str_size - str_pos, "serdes-signal ");
+			break;
+		case SL_LINK_DOWN_CAUSE_SERDES_QUALITY:
+			rtn = snprintf(cause_str + str_pos, cause_str_size - str_pos, "serdes-quality ");
+			break;
+		case SL_LINK_DOWN_CAUSE_NO_MEDIA:
+			rtn = snprintf(cause_str + str_pos, cause_str_size - str_pos, "no-media ");
+			break;
+		case SL_LINK_DOWN_CAUSE_CCW:
+			rtn = snprintf(cause_str + str_pos, cause_str_size - str_pos, "ccw ");
+			break;
+		case SL_LINK_DOWN_CAUSE_MEDIA_HOT:
+			rtn = snprintf(cause_str + str_pos, cause_str_size - str_pos, "media-hot ");
+			break;
+		case SL_LINK_DOWN_CAUSE_MEDIA_WARM:
+			rtn = snprintf(cause_str + str_pos, cause_str_size - str_pos, "media-warm ");
+			break;
+		case SL_LINK_DOWN_CAUSE_INTR_REGISTER:
+			rtn = snprintf(cause_str + str_pos, cause_str_size - str_pos, "interrupt-reg ");
+			break;
+		case SL_LINK_DOWN_CAUSE_MEDIA_ERROR:
+			rtn = snprintf(cause_str + str_pos, cause_str_size - str_pos, "media-error ");
+			break;
+		case SL_LINK_DOWN_CAUSE_UP_CANCELED:
+			rtn = snprintf(cause_str + str_pos, cause_str_size - str_pos, "up-canceled ");
+			break;
+		case SL_LINK_DOWN_CAUSE_UNSUPPORTED_SPEED:
+			rtn = snprintf(cause_str + str_pos, cause_str_size - str_pos, "unsupported-speed ");
+			break;
+		case SL_LINK_DOWN_CAUSE_SS200_CABLE:
+			rtn = snprintf(cause_str + str_pos, cause_str_size - str_pos, "ss200-cable ");
+			break;
+		case SL_LINK_DOWN_CAUSE_TX_LOL:
+			rtn = snprintf(cause_str + str_pos, cause_str_size - str_pos, "tx-lol ");
+			break;
+		case SL_LINK_DOWN_CAUSE_RX_LOL:
+			rtn = snprintf(cause_str + str_pos, cause_str_size - str_pos, "rx-lol ");
+			break;
+		case SL_LINK_DOWN_CAUSE_TX_LOS:
+			rtn = snprintf(cause_str + str_pos, cause_str_size - str_pos, "tx-los ");
+			break;
+		case SL_LINK_DOWN_CAUSE_RX_LOS:
+			rtn = snprintf(cause_str + str_pos, cause_str_size - str_pos, "rx-los ");
+			break;
+
+		case SL_LINK_DOWN_RETRYABLE:
+			rtn = snprintf(cause_str + str_pos, cause_str_size - str_pos, "retryable ");
+			break;
+		case SL_LINK_DOWN_ORIGIN_ASYNC:
+			rtn = snprintf(cause_str + str_pos, cause_str_size - str_pos, "origin-async ");
+			break;
+		case SL_LINK_DOWN_ORIGIN_LINK_UP:
+			rtn = snprintf(cause_str + str_pos, cause_str_size - str_pos, "origin-up ");
+			break;
+
+		default:
+			rtn = snprintf(cause_str + str_pos, cause_str_size - str_pos, "unknown ");
+			break;
+		}
+
+		if (rtn < 0) {
+			scnprintf(cause_str, cause_str_size, "error");
+			return 0;
+		}
+		if (str_pos + rtn >= cause_str_size) {
+			str_pos = cause_str_size - 1;
+			cause_str[str_pos - 3] = '.';
+			cause_str[str_pos - 2] = '.';
+			cause_str[str_pos - 1] = '.';
+			cause_str[str_pos] = '\0';
+			return 0;
+		}
+		str_pos += rtn;
+	}
+
+	cause_str[str_pos - 1] = '\0';
+
+	return 0;
+}
+
+int sl_link_down_cause_map_str(u64 cause_map, char *cause_str, unsigned int cause_str_size)
+{
+	return sl_link_down_cause_map_masked_str(cause_map, cause_str, cause_str_size, ~SL_LINK_DOWN_INFO_MASK);
+}
+EXPORT_SYMBOL(sl_link_down_cause_map_str);
+
+int sl_link_down_cause_map_with_info_str(u64 cause_map, char *cause_str, unsigned int cause_str_size)
+{
+	return sl_link_down_cause_map_masked_str(cause_map, cause_str, cause_str_size, ~0ULL);
+}
+EXPORT_SYMBOL(sl_link_down_cause_map_with_info_str);
+
+int sl_link_info_map_str(u64 info_map, char *info_map_str, unsigned int info_map_str_size)
+{
+	return sl_core_info_map_str(info_map, info_map_str, info_map_str_size);
+}
+EXPORT_SYMBOL(sl_link_info_map_str);
+
+const char *sl_link_config_pause_str(u32 config)
+{
+	if (config == SL_LINK_CONFIG_PAUSE_ASYM)
+		return "pause-asym";
+	if (config == SL_LINK_CONFIG_PAUSE_SYM)
+		return "pause-sym";
+
+	return "unknown";
+}
+EXPORT_SYMBOL(sl_link_config_pause_str);
+
+const char *sl_link_config_hpe_str(u32 config)
+{
+	if (config == SL_LINK_CONFIG_HPE_LINKTRAIN)
+		return "link-train";
+	if (config == SL_LINK_CONFIG_HPE_PRECODING)
+		return "precode";
+	if (config == SL_LINK_CONFIG_HPE_PCAL)
+		return "progressive-cal";
+	if (config == SL_LINK_CONFIG_HPE_R3)
+		return "R3";
+	if (config == SL_LINK_CONFIG_HPE_R2)
+		return "R2";
+	if (config == SL_LINK_CONFIG_HPE_R1)
+		return "R1";
+	if (config == SL_LINK_CONFIG_HPE_C3)
+		return "C3";
+	if (config == SL_LINK_CONFIG_HPE_C2)
+		return "C2";
+	if (config == SL_LINK_CONFIG_HPE_C1)
+		return "C1";
+	if (config == SL_LINK_CONFIG_HPE_LLR)
+		return "llr";
+
+	return "unknown";
+}
+EXPORT_SYMBOL(sl_link_config_hpe_str);
diff --git a/drivers/net/ethernet/hpe/sl/sl_llr.c b/drivers/net/ethernet/hpe/sl/sl_llr.c
new file mode 100644
index 000000000000..539574d4e428
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sl_llr.c
@@ -0,0 +1,289 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/module.h>
+#include <linux/err.h>
+
+#include <linux/hpe/sl/sl_llr.h>
+
+#include "sl_asic.h"
+#include "sl_log.h"
+#include "sl_lgrp.h"
+#include "sl_llr.h"
+#include "sl_ctrl_llr.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_LLR_LOG_NAME
+
+static struct sl_llr llrs[SL_ASIC_MAX_LDEVS][SL_ASIC_MAX_LGRPS][SL_ASIC_MAX_LINKS];
+
+void sl_llr_init(void)
+{
+	u8 ldev_num;
+	u8 lgrp_num;
+	u8 link_num;
+
+	for (ldev_num = 0; ldev_num < SL_ASIC_MAX_LDEVS; ++ldev_num) {
+		for (lgrp_num = 0; lgrp_num < SL_ASIC_MAX_LGRPS; ++lgrp_num) {
+			for (link_num = 0; link_num < SL_ASIC_MAX_LINKS; ++link_num) {
+				llrs[ldev_num][lgrp_num][link_num].magic    = SL_LLR_MAGIC;
+				llrs[ldev_num][lgrp_num][link_num].ver      = SL_LLR_VER;
+				llrs[ldev_num][lgrp_num][link_num].num      = link_num;
+				llrs[ldev_num][lgrp_num][link_num].lgrp_num = lgrp_num;
+				llrs[ldev_num][lgrp_num][link_num].ldev_num = ldev_num;
+			}
+		}
+	}
+}
+
+static int sl_llr_check(struct sl_llr *llr)
+{
+	if (!llr) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL llr");
+		return -EINVAL;
+	}
+	if (IS_ERR(llr)) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "llr pointer error");
+		return -EINVAL;
+	}
+	if (llr->magic != SL_LLR_MAGIC) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "bad llr magic");
+		return -EINVAL;
+	}
+	if (llr->ver != SL_LLR_VER) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "wrong llr version");
+		return -EINVAL;
+	}
+	if (llr->num >= SL_ASIC_MAX_LINKS) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "bad llr num");
+		return -EINVAL;
+	}
+	if (llr->lgrp_num >= SL_ASIC_MAX_LGRPS) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "bad lgrp num");
+		return -EINVAL;
+	}
+	if (llr->ldev_num >= SL_ASIC_MAX_LDEVS) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "bad ldev num");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int sl_llr_config_check(struct sl_llr_config *llr_config)
+{
+	if (!llr_config) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL llr_config");
+		return -EINVAL;
+	}
+	if (IS_ERR(llr_config)) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "llr_config pointer error");
+		return -EINVAL;
+	}
+	if (llr_config->magic != SL_LLR_CONFIG_MAGIC) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "bad llr_config magic");
+		return -EINVAL;
+	}
+	if (llr_config->ver != SL_LLR_CONFIG_VER) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "wrong llr_config version");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int sl_llr_policy_check(struct sl_llr_policy *llr_policy)
+{
+	if (!llr_policy) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL llr_policy");
+		return -EINVAL;
+	}
+	if (IS_ERR(llr_policy)) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "llr_policy pointer error");
+		return -EINVAL;
+	}
+	if (llr_policy->magic != SL_LLR_POLICY_MAGIC) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "bad llr_policy magic");
+		return -EINVAL;
+	}
+	if (llr_policy->ver != SL_LLR_POLICY_VER) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "wrong llr_policy version");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+struct sl_llr *sl_llr_new(struct sl_lgrp *lgrp, u8 llr_num, struct kobject *sysfs_parent)
+{
+	int rtn;
+
+	rtn = sl_lgrp_check(lgrp);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "new fail");
+		return ERR_PTR(rtn);
+	}
+	if (llr_num >= SL_ASIC_MAX_LINKS) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "invalid (llr_num = %u)", llr_num);
+		return ERR_PTR(-EINVAL);
+	}
+
+	rtn = sl_ctrl_llr_new(lgrp->ldev_num, lgrp->num, llr_num, sysfs_parent);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "new fail");
+		return ERR_PTR(rtn);
+	}
+
+	return &llrs[lgrp->ldev_num][lgrp->num][llr_num];
+}
+EXPORT_SYMBOL(sl_llr_new);
+
+int sl_llr_del(struct sl_llr *llr)
+{
+	int rtn;
+
+	rtn = sl_llr_check(llr);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "del fail");
+		return rtn;
+	}
+
+	return sl_ctrl_llr_del(llr->ldev_num, llr->lgrp_num, llr->num);
+}
+EXPORT_SYMBOL(sl_llr_del);
+
+int sl_llr_config_set(struct sl_llr *llr, struct sl_llr_config *llr_config)
+{
+	int rtn;
+
+	rtn = sl_llr_check(llr);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "config set fail");
+		return rtn;
+	}
+	rtn = sl_llr_config_check(llr_config);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "config set fail");
+		return rtn;
+	}
+
+	return sl_ctrl_llr_config_set(llr->ldev_num, llr->lgrp_num, llr->num, llr_config);
+}
+EXPORT_SYMBOL(sl_llr_config_set);
+
+int sl_llr_policy_set(struct sl_llr *llr, struct sl_llr_policy *llr_policy)
+{
+	int rtn;
+
+	rtn = sl_llr_check(llr);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "policy set fail");
+		return rtn;
+	}
+	rtn = sl_llr_policy_check(llr_policy);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "policy set fail");
+		return rtn;
+	}
+
+	return sl_ctrl_llr_policy_set(llr->ldev_num, llr->lgrp_num, llr->num, llr_policy);
+}
+EXPORT_SYMBOL(sl_llr_policy_set);
+
+int sl_llr_setup(struct sl_llr *llr)
+{
+	int rtn;
+
+	rtn = sl_llr_check(llr);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "setup fail");
+		return rtn;
+	}
+
+	return sl_ctrl_llr_setup(llr->ldev_num, llr->lgrp_num, llr->num);
+}
+EXPORT_SYMBOL(sl_llr_setup);
+
+int sl_llr_start(struct sl_llr *llr)
+{
+	int rtn;
+
+	rtn = sl_llr_check(llr);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "start fail");
+		return rtn;
+	}
+
+	return sl_ctrl_llr_start(llr->ldev_num, llr->lgrp_num, llr->num);
+}
+EXPORT_SYMBOL(sl_llr_start);
+
+int sl_llr_stop(struct sl_llr *llr)
+{
+	int rtn;
+
+	rtn = sl_llr_check(llr);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "stop fail");
+		return rtn;
+	}
+
+	return sl_ctrl_llr_stop(llr->ldev_num, llr->lgrp_num, llr->num);
+}
+EXPORT_SYMBOL(sl_llr_stop);
+
+int sl_llr_state_get(struct sl_llr *llr, enum sl_llr_state *state)
+{
+	int rtn;
+
+	rtn = sl_llr_check(llr);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "state get fail");
+		return rtn;
+	}
+
+	return sl_ctrl_llr_state_get(llr->ldev_num, llr->lgrp_num, llr->num, state);
+}
+EXPORT_SYMBOL(sl_llr_state_get);
+
+const char *sl_llr_state_str(u32 state)
+{
+	switch (state) {
+	case SL_LLR_STATE_INVALID:
+		return "invalid";
+	case SL_LLR_STATE_OFF:
+		return "off";
+	case SL_LLR_STATE_CONFIGURED:
+		return "configured";
+	case SL_LLR_STATE_SETUP_BUSY:
+		return "setup-busy";
+	case SL_LLR_STATE_SETUP:
+		return "setup";
+	case SL_LLR_STATE_START_BUSY:
+		return "start-busy";
+	case SL_LLR_STATE_RUNNING:
+		return "running";
+	case SL_LLR_STATE_CANCELING:
+		return "canceling";
+	case SL_LLR_STATE_STOP_BUSY:
+		return "stop-busy";
+	default:
+		return "unknown";
+	}
+}
+EXPORT_SYMBOL(sl_llr_state_str);
+
+const char *sl_llr_link_dn_behavior_str(u32 behavior)
+{
+	switch (behavior) {
+	case SL_LLR_LINK_DN_BEHAVIOR_DISCARD:
+		return "discard";
+	case SL_LLR_LINK_DN_BEHAVIOR_BLOCK:
+		return "block";
+	case SL_LLR_LINK_DN_BEHAVIOR_BEST_EFFORT:
+		return "best-effort";
+	default:
+		return "unknown";
+	}
+}
+EXPORT_SYMBOL(sl_llr_link_dn_behavior_str);
diff --git a/drivers/net/ethernet/hpe/sl/sl_mac.c b/drivers/net/ethernet/hpe/sl/sl_mac.c
new file mode 100644
index 000000000000..a8c6ee46721e
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sl_mac.c
@@ -0,0 +1,220 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/module.h>
+#include <linux/err.h>
+
+#include <linux/hpe/sl/sl_mac.h>
+
+#include "sl_asic.h"
+#include "sl_log.h"
+#include "sl_lgrp.h"
+#include "sl_mac.h"
+#include "sl_ctrl_mac.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_MAC_LOG_NAME
+
+static struct sl_mac macs[SL_ASIC_MAX_LDEVS][SL_ASIC_MAX_LGRPS][SL_ASIC_MAX_LINKS];
+
+void sl_mac_init(void)
+{
+	u8 ldev_num;
+	u8 lgrp_num;
+	u8 link_num;
+
+	for (ldev_num = 0; ldev_num < SL_ASIC_MAX_LDEVS; ++ldev_num) {
+		for (lgrp_num = 0; lgrp_num < SL_ASIC_MAX_LGRPS; ++lgrp_num) {
+			for (link_num = 0; link_num < SL_ASIC_MAX_LINKS; ++link_num) {
+				macs[ldev_num][lgrp_num][link_num].magic    = SL_MAC_MAGIC;
+				macs[ldev_num][lgrp_num][link_num].ver      = SL_MAC_VER;
+				macs[ldev_num][lgrp_num][link_num].num      = link_num;
+				macs[ldev_num][lgrp_num][link_num].lgrp_num = lgrp_num;
+				macs[ldev_num][lgrp_num][link_num].ldev_num = ldev_num;
+			}
+		}
+	}
+}
+
+static int sl_mac_check(struct sl_mac *mac)
+{
+	if (!mac) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL mac");
+		return -EINVAL;
+	}
+	if (IS_ERR(mac)) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "mac pointer error");
+		return -EINVAL;
+	}
+	if (mac->magic != SL_MAC_MAGIC) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "bad mac magic");
+		return -EINVAL;
+	}
+	if (mac->ver != SL_MAC_VER) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "bad mac version");
+		return -EINVAL;
+	}
+	if (mac->num >= SL_ASIC_MAX_LINKS) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "bad mac num");
+		return -EINVAL;
+	}
+	if (mac->lgrp_num >= SL_ASIC_MAX_LGRPS) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "bad lgrp num");
+		return -EINVAL;
+	}
+	if (mac->ldev_num >= SL_ASIC_MAX_LDEVS) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "bad ldev num");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+struct sl_mac *sl_mac_new(struct sl_lgrp *lgrp, u8 mac_num, struct kobject *sysfs_parent)
+{
+	int rtn;
+
+	rtn = sl_lgrp_check(lgrp);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "new fail");
+		return ERR_PTR(rtn);
+	}
+	if (mac_num >= SL_ASIC_MAX_LINKS) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "invalid (mac_num = %u)", mac_num);
+		return ERR_PTR(-EINVAL);
+	}
+
+	rtn = sl_ctrl_mac_new(lgrp->ldev_num, lgrp->num, mac_num, sysfs_parent);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "new fail");
+		return ERR_PTR(rtn);
+	}
+
+	return &macs[lgrp->ldev_num][lgrp->num][mac_num];
+}
+EXPORT_SYMBOL(sl_mac_new);
+
+int sl_mac_del(struct sl_mac *mac)
+{
+	int rtn;
+
+	rtn = sl_mac_check(mac);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "del fail");
+		return rtn;
+	}
+
+	return sl_ctrl_mac_del(mac->ldev_num, mac->lgrp_num, mac->num);
+}
+EXPORT_SYMBOL(sl_mac_del);
+
+int sl_mac_tx_start(struct sl_mac *mac)
+{
+	int rtn;
+
+	rtn = sl_mac_check(mac);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "tx start fail");
+		return rtn;
+	}
+
+	return sl_ctrl_mac_tx_start(mac->ldev_num, mac->lgrp_num, mac->num);
+}
+EXPORT_SYMBOL(sl_mac_tx_start);
+
+int sl_mac_tx_stop(struct sl_mac *mac)
+{
+	int rtn;
+
+	rtn = sl_mac_check(mac);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "tx stop fail");
+		return rtn;
+	}
+
+	return sl_ctrl_mac_tx_stop(mac->ldev_num, mac->lgrp_num, mac->num);
+}
+EXPORT_SYMBOL(sl_mac_tx_stop);
+
+int sl_mac_tx_state_get(struct sl_mac *mac, u32 *state)
+{
+	int rtn;
+
+	rtn = sl_mac_check(mac);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "tx state get fail");
+		return rtn;
+	}
+
+	return sl_ctrl_mac_tx_state_get(mac->ldev_num, mac->lgrp_num, mac->num, state);
+}
+EXPORT_SYMBOL(sl_mac_tx_state_get);
+
+int sl_mac_rx_start(struct sl_mac *mac)
+{
+	int rtn;
+
+	rtn = sl_mac_check(mac);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "rx start fail");
+		return rtn;
+	}
+
+	return sl_ctrl_mac_rx_start(mac->ldev_num, mac->lgrp_num, mac->num);
+}
+EXPORT_SYMBOL(sl_mac_rx_start);
+
+int sl_mac_rx_stop(struct sl_mac *mac)
+{
+	int rtn;
+
+	rtn = sl_mac_check(mac);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "rx stop fail");
+		return rtn;
+	}
+
+	return sl_ctrl_mac_rx_stop(mac->ldev_num, mac->lgrp_num, mac->num);
+}
+EXPORT_SYMBOL(sl_mac_rx_stop);
+
+int sl_mac_rx_state_get(struct sl_mac *mac, u32 *state)
+{
+	int rtn;
+
+	rtn = sl_mac_check(mac);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "rx state get fail");
+		return rtn;
+	}
+
+	return sl_ctrl_mac_rx_state_get(mac->ldev_num, mac->lgrp_num, mac->num, state);
+}
+EXPORT_SYMBOL(sl_mac_rx_state_get);
+
+int sl_mac_reset(struct sl_mac *mac)
+{
+	int rtn;
+
+	rtn = sl_mac_check(mac);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "reset fail");
+		return rtn;
+	}
+
+	return sl_ctrl_mac_reset(mac->ldev_num, mac->lgrp_num, mac->num);
+}
+EXPORT_SYMBOL(sl_mac_reset);
+
+const char *sl_mac_state_str(u32 state)
+{
+	switch (state) {
+	case SL_MAC_STATE_OFF:
+		return "off";
+	case SL_MAC_STATE_ON:
+		return "on";
+	default:
+		return "unknown";
+	}
+}
+EXPORT_SYMBOL(sl_mac_state_str);
diff --git a/drivers/net/ethernet/hpe/sl/sl_media.c b/drivers/net/ethernet/hpe/sl/sl_media.c
new file mode 100644
index 000000000000..50f60e36645c
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sl_media.c
@@ -0,0 +1,356 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2022,2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/module.h>
+
+#include <linux/hpe/sl/sl_media.h>
+
+#include "sl_log.h"
+#include "sl_lgrp.h"
+#include "sl_media_jack.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_MEDIA_LOG_NAME
+
+int sl_media_headshell_temp_get(struct sl_lgrp *lgrp, u8 *temp)
+{
+	int rtn;
+
+	rtn = sl_lgrp_check(lgrp);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "headshell temp get fail");
+		return rtn;
+	}
+	if (!temp) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL temp");
+		return -EINVAL;
+	}
+
+	return sl_media_jack_cable_temp_get(lgrp->ldev_num, lgrp->num, temp);
+}
+EXPORT_SYMBOL(sl_media_headshell_temp_get);
+
+const char *sl_media_furcation_str(u32 furcation)
+{
+	switch (furcation) {
+	case SL_MEDIA_FURCATION_X1:
+		return "unfurcated";
+	case SL_MEDIA_FURCATION_X2:
+		return "bifurcated";
+	case SL_MEDIA_FURCATION_X4:
+		return "quadfurcated";
+	case SL_MEDIA_FURCATION_UNKNOWN:
+		return "unknown";
+	default:
+		return "invalid";
+	}
+}
+EXPORT_SYMBOL(sl_media_furcation_str);
+
+const char *sl_media_state_str(u8 state)
+{
+	switch (state) {
+	case SL_MEDIA_JACK_CABLE_REMOVED:
+		return "removed";
+	case SL_MEDIA_JACK_CABLE_INSERTED:
+		return "inserted";
+	case SL_MEDIA_JACK_CABLE_GOING_ONLINE:
+		return "going-online";
+	case SL_MEDIA_JACK_CABLE_ONLINE:
+		return "online";
+	case SL_MEDIA_JACK_CABLE_ERROR:
+		return "error";
+	default:
+		return "invalid";
+	}
+}
+EXPORT_SYMBOL(sl_media_state_str);
+
+const char *sl_media_cable_speed_state_str(u8 cable_speed_state)
+{
+	switch (cable_speed_state) {
+	case SL_MEDIA_JACK_CABLE_SHIFT_STATE_UPSHIFTED:
+		return "400G";
+	case SL_MEDIA_JACK_CABLE_SHIFT_STATE_DOWNSHIFTED:
+		return "200G";
+	case SL_MEDIA_JACK_CABLE_SHIFT_STATE_FAILED_NO_CABLE:
+		return "failed-no-cable";
+	case SL_MEDIA_JACK_CABLE_SHIFT_STATE_FAILED_FAKE_CABLE:
+		return "failed-fake-cable";
+	case SL_MEDIA_JACK_CABLE_SHIFT_STATE_FAILED_NO_SUPPORT:
+		return "failed-no-support";
+	case SL_MEDIA_JACK_CABLE_SHIFT_STATE_FAILED_CHECK:
+		return "failed-check";
+	case SL_MEDIA_JACK_CABLE_SHIFT_STATE_FAILED_UPSHIFT:
+		return "failed-up";
+	case SL_MEDIA_JACK_CABLE_SHIFT_STATE_FAILED_DOWNSHIFT:
+		return "failed-down";
+	case SL_MEDIA_JACK_CABLE_SHIFT_STATE_NOTSHIFTED:
+		return "none";
+	default:
+		return "invalid";
+	}
+}
+EXPORT_SYMBOL(sl_media_cable_speed_state_str);
+
+const char *sl_media_type_str(u32 type)
+{
+	switch (type) {
+	case SL_MEDIA_TYPE_HEADSHELL:
+		return "headshell";
+	case SL_MEDIA_TYPE_BACKPLANE:
+		return "backplane";
+	case SL_MEDIA_TYPE_ELECTRICAL:
+		return "electrical";
+	case SL_MEDIA_TYPE_OPTICAL:
+		return "optical";
+	case SL_MEDIA_TYPE_PASSIVE:
+		return "passive";
+	case SL_MEDIA_TYPE_ACTIVE:
+		return "active";
+	case SL_MEDIA_TYPE_ANALOG:
+		return "analog";
+	case SL_MEDIA_TYPE_DIGITAL:
+		return "digital";
+	case SL_MEDIA_TYPE_LOOPBACK:
+		return "loopback";
+	case SL_MEDIA_TYPE_UNSUPPORTED:
+		return "unsupported";
+	case SL_MEDIA_TYPE_UNKNOWN:
+		return "unknown";
+	case SL_MEDIA_TYPE_AOC:
+		return "AOC";
+	case SL_MEDIA_TYPE_POC:
+		return "POC";
+	case SL_MEDIA_TYPE_PEC:
+		return "PEC";
+	case SL_MEDIA_TYPE_AEC:
+		return "AEC";
+	case SL_MEDIA_TYPE_ACC:
+		return "ACC";
+	case SL_MEDIA_TYPE_BKP:
+		return "BKP";
+	default:
+		return "invalid";
+	}
+}
+EXPORT_SYMBOL(sl_media_type_str);
+
+const char *sl_media_shape_str(u32 shape)
+{
+	switch (shape) {
+	case SL_MEDIA_SHAPE_UNKNOWN:
+		return "unknown";
+	case SL_MEDIA_SHAPE_STRAIGHT:
+		return "straight";
+	case SL_MEDIA_SHAPE_SPLITTER:
+		return "splitter(y)";
+	case SL_MEDIA_SHAPE_BIFURCATED:
+		return "bifurcated(H)";
+	default:
+		return "invalid";
+	}
+}
+EXPORT_SYMBOL(sl_media_shape_str);
+
+const char *sl_media_cable_end_str(u8 cable_end)
+{
+	switch (cable_end) {
+	case SL_MEDIA_CABLE_END_DD:
+		return "qsfp_dd";
+	case SL_MEDIA_CABLE_END_END1:
+		return "qsfp_end1";
+	case SL_MEDIA_CABLE_END_END2:
+		return "qsfp_end2";
+	default:
+		return "invalid";
+	}
+}
+EXPORT_SYMBOL(sl_media_cable_end_str);
+
+const char *sl_media_vendor_str(u32 vendor)
+{
+	switch (vendor) {
+	case SL_MEDIA_VENDOR_UNKNOWN:
+		return "unknown";
+	case SL_MEDIA_VENDOR_TE:
+		return "te";
+	case SL_MEDIA_VENDOR_HISENSE:
+		return "hisense";
+	case SL_MEDIA_VENDOR_LEONI:
+		return "leoni";
+	case SL_MEDIA_VENDOR_FINISAR:
+		return "finisar";
+	case SL_MEDIA_VENDOR_MOLEX:
+		return "molex";
+	case SL_MEDIA_VENDOR_BIZLINK:
+		return "bizlink";
+	case SL_MEDIA_VENDOR_HPE:
+		return "hpe";
+	case SL_MEDIA_VENDOR_CLOUD_LIGHT:
+		return "cloud-light";
+	case SL_MEDIA_VENDOR_MULTILANE:
+		return "multilane";
+	case SL_MEDIA_VENDOR_AMPHENOL:
+		return "amphenol";
+	default:
+		return "invalid";
+	}
+}
+EXPORT_SYMBOL(sl_media_vendor_str);
+
+const char *sl_media_speed_str(u32 speed)
+{
+	switch (speed) {
+	case SL_MEDIA_SPEEDS_SUPPORT_CK_800G:
+		return "ck800G";
+	case SL_MEDIA_SPEEDS_SUPPORT_CK_400G:
+		return "ck400G";
+	case SL_MEDIA_SPEEDS_SUPPORT_CK_200G:
+		return "ck200G";
+	case SL_MEDIA_SPEEDS_SUPPORT_CK_100G:
+		return "ck100G";
+	case SL_MEDIA_SPEEDS_SUPPORT_BS_200G:
+		return "bs200G";
+	case SL_MEDIA_SPEEDS_SUPPORT_BJ_100G:
+		return "bj100G";
+	case SL_MEDIA_SPEEDS_SUPPORT_CD_100G:
+		return "cd100G";
+	case SL_MEDIA_SPEEDS_SUPPORT_CD_50G:
+		return "cd50G";
+	default:
+		return "invalid";
+	}
+}
+EXPORT_SYMBOL(sl_media_speed_str);
+
+const char *sl_media_ber_str(u8 media_interface)
+{
+	switch (media_interface) {
+	case 1:
+		return "<1E-12";
+	case 2:
+		return "<5E-5";
+	case 3:
+		return "<2.6E-4";
+	case 4:
+		return "<1E-6";
+	default:
+		return "invalid";
+	}
+}
+EXPORT_SYMBOL(sl_media_ber_str);
+
+const char *sl_media_host_interface_str(u32 speed, u32 type)
+{
+	if ((type == SL_MEDIA_TYPE_PEC) || (type == SL_MEDIA_TYPE_BKP)) {
+		switch (speed) {
+		case SL_MEDIA_SPEEDS_SUPPORT_CD_50G:
+			return "50GBASE-CR";
+		case SL_MEDIA_SPEEDS_SUPPORT_CD_100G:
+			return "100GBASE-CR2";
+		case SL_MEDIA_SPEEDS_SUPPORT_CK_100G:
+			return "100GBASE-CR1";
+		case SL_MEDIA_SPEEDS_SUPPORT_BS_200G:
+			return "200GBASE-CR4";
+		case SL_MEDIA_SPEEDS_SUPPORT_CK_200G:
+			return "200GBASE-CR2";
+		case SL_MEDIA_SPEEDS_SUPPORT_CK_400G:
+			return "400GBASE-CR4";
+		case SL_MEDIA_SPEEDS_SUPPORT_CK_800G:
+			return "800GBASE-CR8";
+		case SL_MEDIA_SPEEDS_SUPPORT_BJ_100G:
+			return "BJ-100G";
+		default:
+			return "invalid";
+		}
+	}
+
+	switch (speed) {
+	case SL_MEDIA_SPEEDS_SUPPORT_CD_50G:
+		return "50GAUI-1-C2M";
+	case SL_MEDIA_SPEEDS_SUPPORT_CD_100G:
+		return "100GAUI-2-C2M";
+	case SL_MEDIA_SPEEDS_SUPPORT_CK_100G:
+		return "100GAUI-1-L-C2M";
+	case SL_MEDIA_SPEEDS_SUPPORT_BS_200G:
+		return "200GAUI-4-C2M";
+	case SL_MEDIA_SPEEDS_SUPPORT_CK_200G:
+		return "200GAUI-2-S-C2M";
+	case SL_MEDIA_SPEEDS_SUPPORT_CK_400G:
+		return "400GAUI-4-S-C2M";
+	case SL_MEDIA_SPEEDS_SUPPORT_CK_800G:
+		return "800GAUI-8-S-C2M";
+	case SL_MEDIA_SPEEDS_SUPPORT_BJ_100G:
+		return "BJ-100G";
+	default:
+		return "invalid";
+	}
+
+}
+EXPORT_SYMBOL(sl_media_host_interface_str);
+
+const char *sl_media_info_str(u32 info)
+{
+	switch (info) {
+	case SL_MEDIA_INFO_AUTONEG:
+		return "autoneg";
+	case SL_MEDIA_INFO_FAKE:
+		return "fake";
+	case SL_MEDIA_INFO_RESETTABLE:
+		return "resettable";
+	case SL_MEDIA_INFO_LINKTRAIN:
+		return "linktrain";
+	case SL_MEDIA_INFO_SUPPORTED_SS200_CABLE:
+		return "supported-ss200-cable";
+	default:
+		return "invalid";
+	}
+}
+EXPORT_SYMBOL(sl_media_info_str);
+
+const char *sl_media_error_str(u32 error)
+{
+	switch (error) {
+	case SL_MEDIA_ERROR_CABLE_UNSUPPORTED:
+		return "unsupported";
+	case SL_MEDIA_ERROR_CABLE_FORMAT_UNSUPPORTED:
+		return "unsupported-format";
+	case SL_MEDIA_ERROR_CABLE_FW_UNSUPPORTED:
+		return "unsupported-fw";
+	case SL_MEDIA_ERROR_CABLE_HEADSHELL_FAULT:
+		return "headshell-fault";
+	case SL_MEDIA_ERROR_TEMP_DOWN_LIMIT_DEFAULT:
+		return "temperature-down-limit-default";
+	case SL_MEDIA_ERROR_TEMP_WARN_LIMIT_DEFAULT:
+		return "temperature-warn-limit-default";
+	case SL_MEDIA_ERROR_TRYABLE:
+		return "tryable";
+	default:
+		return "invalid";
+	}
+}
+EXPORT_SYMBOL(sl_media_error_str);
+
+const char *sl_media_jack_type_str(u32 jack_type, u32 density)
+{
+	switch (jack_type) {
+	case SL_MEDIA_JACK_TYPE_BACKPLANE:
+		return "backplane";
+	case SL_MEDIA_JACK_TYPE_SFP:
+		return "sfp";
+	case SL_MEDIA_JACK_TYPE_QSFP:
+		if (density == SL_MEDIA_QSFP_DENSITY_DOUBLE)
+			return "qsfp-dd";
+		return "qsfp";
+	case SL_MEDIA_JACK_TYPE_OSFP:
+		return "osfp";
+	case SL_MEDIA_JACK_TYPE_UNKNOWN:
+		return "unknown";
+	case SL_MEDIA_JACK_TYPE_UNSUPPORTED:
+		return "unsupported";
+	default:
+		return "invalid";
+	}
+}
+EXPORT_SYMBOL(sl_media_jack_type_str);
diff --git a/drivers/net/ethernet/hpe/sl/sl_media_nic.c b/drivers/net/ethernet/hpe/sl/sl_media_nic.c
new file mode 100644
index 000000000000..23af513e6bd9
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sl_media_nic.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/module.h>
+#include <linux/types.h>
+
+#include <linux/hpe/sl/sl_lgrp.h>
+
+#include "sl_lgrp.h"
+
+int sl_media_cable_insert(struct sl_lgrp *lgrp, u8 *eeprom_page0, u8 *eeprom_page1, u32 flags)
+{
+	/* placeholder for future functionality */
+	return 0;
+}
+EXPORT_SYMBOL(sl_media_cable_insert);
+
+int sl_media_cable_remove(struct sl_lgrp *lgrp)
+{
+	/* placeholder for future functionality */
+	return 0;
+}
+EXPORT_SYMBOL(sl_media_cable_remove);
diff --git a/drivers/net/ethernet/hpe/sl/sl_module.c b/drivers/net/ethernet/hpe/sl/sl_module.c
new file mode 100644
index 000000000000..b63efedf94ff
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sl_module.c
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2023-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/device.h>
+#include <linux/cdev.h>
+#include <linux/fs.h>
+#include <linux/version.h>
+
+#include "sl_module.h"
+
+#include "sl.h"
+#include "sl_ldev.h"
+#include "sl_lgrp.h"
+#include "sl_link.h"
+#include "sl_llr.h"
+#include "sl_mac.h"
+
+static unsigned long serdes_core_io_trace_lgrp_map;
+module_param(serdes_core_io_trace_lgrp_map, ulong, 0644);
+MODULE_PARM_DESC(serdes_core_io_trace_lgrp_map, "serdes core io trace enable link group map");
+
+u64 sl_serdes_core_io_trace_lgrp_map_get(void)
+{
+	return serdes_core_io_trace_lgrp_map;
+}
+
+#define SL_DEVICE_NAME "sl"
+
+#define tostr(x)             #x
+#define version_str(a, b, c) tostr(a.b.c)
+#define SL_VERSION_STR       version_str(SL_VERSION_MAJOR, SL_VERSION_MINOR, SL_VERSION_INC)
+#define hash_str(h)          tostr(h)
+#define SL_GIT_HASH_STR      hash_str(GIT_HASH)
+
+void sl_version_get(int *major, int *minor, int *inc)
+{
+	if (major)
+		*major = SL_VERSION_MAJOR;
+	if (minor)
+		*minor = SL_VERSION_MINOR;
+	if (inc)
+		*inc = SL_VERSION_INC;
+}
+EXPORT_SYMBOL(sl_version_get);
+
+char *sl_version_str_get(void)
+{
+	return SL_VERSION_STR;
+}
+
+char *sl_git_hash_str_get(void)
+{
+	return (strlen(SL_GIT_HASH_STR) == 0) ? "unavailable" : SL_GIT_HASH_STR;
+}
+EXPORT_SYMBOL(sl_git_hash_str_get);
+
+static dev_t          sl_dev;
+static struct class  *sl_class;
+static struct device *sl_device;
+
+static int __init sl_init(void)
+{
+	int rtn;
+
+	pr_info("%s: init v" SL_VERSION_STR "\n", module_name(THIS_MODULE));
+	pr_info("%s: hash " SL_GIT_HASH_STR "\n", module_name(THIS_MODULE));
+
+	rtn = alloc_chrdev_region(&sl_dev, 0, 1, SL_DEVICE_NAME);
+	if (rtn) {
+		pr_err("alloc_chrdev_region failed [%d]", rtn);
+		return -EIO;
+	}
+
+	sl_class = class_create(SL_DEVICE_NAME);
+
+	if (IS_ERR(sl_class)) {
+		rtn = PTR_ERR(sl_class);
+		pr_err("class_create \"%s\" failed [%d]", SL_DEVICE_NAME, rtn);
+		goto out_region;
+	}
+
+	sl_device = device_create(sl_class, NULL, sl_dev, NULL, SL_DEVICE_NAME);
+	if (IS_ERR(sl_device)) {
+		rtn = PTR_ERR(sl_device);
+		pr_err("device_create failed [%d]", rtn);
+		goto out_class;
+	}
+
+	sl_ldev_init();
+	sl_lgrp_init();
+	sl_link_init();
+	sl_llr_init();
+	sl_mac_init();
+
+	return 0;
+
+out_class:
+	class_destroy(sl_class);
+out_region:
+	unregister_chrdev_region(sl_dev, 1);
+
+	return rtn;
+}
+module_init(sl_init);
+
+struct device *sl_device_get(void)
+{
+	return sl_device;
+}
+
+static void __exit sl_exit(void)
+{
+	pr_info("%s: exit\n", module_name(THIS_MODULE));
+
+	device_destroy(sl_class, sl_dev);
+	class_destroy(sl_class);
+	unregister_chrdev_region(sl_dev, 1);
+
+	sl_ldev_exit();
+}
+module_exit(sl_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Slingshot Platform Team <hpcdev_ss_plat@hpe.com>");
+MODULE_DESCRIPTION("Slingshot Link Module");
+MODULE_VERSION(SL_VERSION_STR);

-- 
2.56.0


^ permalink raw reply	[flat|nested] 25+ messages in thread
* [PATCH 11/23] net: hpe: sl: add the core link state machines
  2026-10-30 20:58 [PATCH 00/23] Subject: [PATCH net-next 00/23] net/hpe: add HPE Slingshot NIC drivers Doug Ledford
                   ` (9 preceding siblings ...)
  2026-10-30 20:59 ` [PATCH 10/23] net: hpe: sl: add the module entry points Doug Ledford
@ 2026-10-30 20:59 ` Doug Ledford
  2026-10-30 20:59 ` [PATCH 12/23] net: hpe: sl: add the control layer Doug Ledford
                   ` (12 subsequent siblings)
  23 siblings, 0 replies; 25+ messages in thread
From: Doug Ledford @ 2026-10-30 20:59 UTC (permalink / raw)
  To: Slingshot Open Source Team, Nathan Chancellor, Nicolas Schier,
	Richard Cochran, Andrew Lunn, David S. Miller, Eric Dumazet,
	Jakub Kicinski, Paolo Abeni, Sumit Semwal, Christian König,
	Guenter Roeck
  Cc: linux-kernel, netdev, linux-kbuild, Doug Ledford, Mamila Santosh,
	Sandeep Bhoot

Add the SL core: the link, LLR and MAC state machines, their timers
and work items, and the hardware access layer including auto-
negotiation, FEC, PCS and SerDes firmware handling.

sl_core_data_lgrp_del() returns early, without deleting the link group,
while the group is still being configured.  The function returns void,
so callers cannot learn this and may go on to tear down the parent
logical device.  The early return is documented in the code.

If creating a link fails after its interrupt handlers are registered,
sl_core_data_link_new() now runs the normal link cleanup before freeing
the link, so no handler, timer or work item can reference freed memory.

Known open issue (Sashiko M23, deferred):
sl_core_hw_pcs_keep_all_lanes_active_set() is an empty hook marked with
a TODO. It belongs to graceful lane-degrade support, which SL does not
implement yet; it is low priority and will be addressed after this
series.

checkpatch --strict (100 columns) still reports the following in this
patch. They need coordination with the internal repositories this code
is maintained in and will be fixed in V2:
- WARNING: LONG_LINE (595), LONG_LINE_COMMENT (101), LONG_LINE_STRING
  (57), SPLIT_STRING (8), LEADING_SPACE (1)
- CHECK: UNNECESSARY_PARENTHESES (240), MACRO_ARG_REUSE (8), BRACES (6),
  ALLOC_SIZEOF_STRUCT (5), COMPARISON_TO_NULL (3), CAMELCASE (2),
  OPEN_ENDED_LINE (1), USLEEP_RANGE (1)

Co-developed-by: Mamila Santosh <santosh-kumar.mamila@hpe.com>
Signed-off-by: Mamila Santosh <santosh-kumar.mamila@hpe.com>
Co-developed-by: Sandeep Bhoot <sandeep.bhoot@hpe.com>
Signed-off-by: Sandeep Bhoot <sandeep.bhoot@hpe.com>
Signed-off-by: Doug Ledford <doug.ledford@hpe.com>
---
 .../ethernet/hpe/sl/core/base/sl_core_timer_link.c |  109 +
 .../ethernet/hpe/sl/core/base/sl_core_timer_llr.c  |   84 +
 .../hpe/sl/core/data/nic/sl_core_data_link.c       |   11 +
 .../hpe/sl/core/data/nic/sl_core_data_mac.c        |   11 +
 .../ethernet/hpe/sl/core/data/sl_core_data_ldev.c  |  122 ++
 .../ethernet/hpe/sl/core/data/sl_core_data_lgrp.c  |  351 ++++
 .../hpe/sl/core/data/sl_core_data_lgrp_trace.c     |   50 +
 .../ethernet/hpe/sl/core/data/sl_core_data_link.c  | 1343 ++++++++++++
 .../ethernet/hpe/sl/core/data/sl_core_data_llr.c   |  526 +++++
 .../ethernet/hpe/sl/core/data/sl_core_data_mac.c   |  273 +++
 .../ethernet/hpe/sl/core/hw/nic/sl_core_hw_an.c    |   26 +
 .../ethernet/hpe/sl/core/hw/nic/sl_core_hw_fec.c   |  113 +
 .../ethernet/hpe/sl/core/hw/nic/sl_core_hw_llr.c   |   44 +
 .../ethernet/hpe/sl/core/hw/nic/sl_core_hw_mac.c   |   32 +
 .../ethernet/hpe/sl/core/hw/nic/sl_core_hw_pcs.c   |   14 +
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_an.c    |  602 ++++++
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_an_lp.c |  254 +++
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_an_up.c |  270 +++
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_intr.c  |  222 ++
 .../ethernet/hpe/sl/core/hw/sl_core_hw_intr_llr.c  |  181 ++
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_link.c  | 2172 ++++++++++++++++++++
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_llr.c   |  905 ++++++++
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_mac.c   |  172 ++
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_pcs.c   |  365 ++++
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_pmi.c   |   54 +
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_reset.c |   67 +
 .../net/ethernet/hpe/sl/core/hw/sl_core_hw_sbus.c  |  125 ++
 .../ethernet/hpe/sl/core/hw/sl_core_hw_sbus_pmi.c  |  112 +
 .../ethernet/hpe/sl/core/hw/sl_core_hw_serdes.c    |  212 ++
 .../hpe/sl/core/hw/sl_core_hw_serdes_core.c        |  439 ++++
 .../ethernet/hpe/sl/core/hw/sl_core_hw_serdes_fw.c |  191 ++
 .../hpe/sl/core/hw/sl_core_hw_serdes_lane.c        | 1085 ++++++++++
 .../hpe/sl/core/hw/sl_core_hw_serdes_lane_rx.c     |  241 +++
 .../hpe/sl/core/hw/sl_core_hw_serdes_lane_tx.c     |  394 ++++
 .../hpe/sl/core/hw/sl_core_hw_serdes_link.c        |  349 ++++
 .../ethernet/hpe/sl/core/hw/sl_core_hw_uc_ram.c    |   84 +
 drivers/net/ethernet/hpe/sl/core/sl_core_ldev.c    |  192 ++
 drivers/net/ethernet/hpe/sl/core/sl_core_lgrp.c    |  659 ++++++
 drivers/net/ethernet/hpe/sl/core/sl_core_link.c    |  623 ++++++
 drivers/net/ethernet/hpe/sl/core/sl_core_link_an.c |  166 ++
 .../net/ethernet/hpe/sl/core/sl_core_link_fec.c    |  233 +++
 drivers/net/ethernet/hpe/sl/core/sl_core_llr.c     |  350 ++++
 drivers/net/ethernet/hpe/sl/core/sl_core_mac.c     |  183 ++
 drivers/net/ethernet/hpe/sl/core/sl_core_str.c     |  283 +++
 44 files changed, 14294 insertions(+)

diff --git a/drivers/net/ethernet/hpe/sl/core/base/sl_core_timer_link.c b/drivers/net/ethernet/hpe/sl/core/base/sl_core_timer_link.c
new file mode 100644
index 000000000000..4b0af513afb6
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/base/sl_core_timer_link.c
@@ -0,0 +1,109 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2022,2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/spinlock.h>
+#include <linux/timer.h>
+#include <linux/workqueue.h>
+
+#include "sl_core_link.h"
+#include "sl_core_str.h"
+#include "sl_platform.h"
+#include "base/sl_core_timer_link.h"
+#include "base/sl_core_log.h"
+
+#include "hw/sl_core_hw_intr.h"
+
+#define LOG_NAME SL_CORE_TIMER_LINK_LOG_NAME
+
+void sl_core_timer_link_begin(struct sl_core_link *core_link, u32 timer_num)
+{
+	int  rtn;
+	enum sl_core_link_state link_state;
+	bool is_canceled_or_timed_out;
+
+	if (core_link->timers[timer_num].data.timeout_ms == 0) {
+		sl_core_log_warn_trace(core_link, LOG_NAME,
+				       "begin %s timeout is 0 (timer_num = %u)",
+				      core_link->timers[timer_num].data.log, timer_num);
+		return;
+	}
+
+	core_link->timers[timer_num].timer.expires =
+		jiffies + msecs_to_jiffies(core_link->timers[timer_num].data.timeout_ms);
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"begin %s (core_link = 0x%p, timer_num = %u, timeout = %dms, jiffies = %ld)",
+			core_link->timers[timer_num].data.log, core_link, timer_num,
+			core_link->timers[timer_num].data.timeout_ms,
+			core_link->timers[timer_num].timer.expires);
+
+	rtn = sl_core_link_is_canceled_or_timed_out(core_link, &is_canceled_or_timed_out);
+	if (rtn) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "begin %s is_canceled_or_timed_out failed (timer_num = %u) [%d]",
+				      core_link->timers[timer_num].data.log, timer_num, rtn);
+		return;
+	}
+
+	if (is_canceled_or_timed_out) {
+		sl_core_log_dbg(core_link, LOG_NAME,
+				"begin %s canceled (timer_num = %u)",
+				      core_link->timers[timer_num].data.log, timer_num);
+		return;
+	}
+
+	spin_lock(&core_link->link.data_lock);
+	link_state = core_link->link.state;
+	switch (link_state) {
+	case SL_CORE_LINK_STATE_UNCONFIGURED:
+	case SL_CORE_LINK_STATE_CONFIGURING:
+	case SL_CORE_LINK_STATE_CONFIGURED:
+	case SL_CORE_LINK_STATE_DOWN:
+	case SL_CORE_LINK_STATE_AN:
+	case SL_CORE_LINK_STATE_GOING_UP:
+	case SL_CORE_LINK_STATE_UP:
+		add_timer(&core_link->timers[timer_num].timer);
+		spin_unlock(&core_link->link.data_lock);
+		return;
+	default:
+		sl_core_log_err(core_link, LOG_NAME,
+				"begin %s invalid state (link_state = %u %s, timer_num = %u)",
+				core_link->timers[timer_num].data.log,
+				link_state, sl_core_link_state_str(link_state), timer_num);
+		spin_unlock(&core_link->link.data_lock);
+		return;
+	}
+}
+
+/**
+ * sl_core_timer_link_timeout - Timer callback function executed in interrupt context.
+ * @timer: Pointer to the timer_list structure associated with the timer.
+ *
+ * Context: Interrupt context.
+ */
+void sl_core_timer_link_timeout(struct timer_list *timer)
+{
+	struct sl_core_timer_link_info *info;
+	struct sl_core_link            *core_link;
+
+	info = timer_container_of(info, timer, timer);
+	core_link = info->data.link;
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"timeout %s (core_link = 0x%p, timer_num = %u, work_num = %u)",
+			info->data.log, core_link, info->data.timer_num,
+			info->data.work_num);
+
+	queue_work(core_link->core_lgrp->core_ldev->workqueue,
+		   &core_link->work[info->data.work_num]);
+}
+
+void sl_core_timer_link_end(struct sl_core_link *core_link, u32 timer_num)
+{
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"end %s (core_link = 0x%p, timer_num = %u)",
+			core_link->timers[timer_num].data.log, core_link, timer_num);
+
+	timer_delete_sync(&core_link->timers[timer_num].timer);
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/base/sl_core_timer_llr.c b/drivers/net/ethernet/hpe/sl/core/base/sl_core_timer_llr.c
new file mode 100644
index 000000000000..3f5a13470b92
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/base/sl_core_timer_llr.c
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2024,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/timer.h>
+#include <linux/workqueue.h>
+
+#include "sl_core_str.h"
+#include "sl_core_llr.h"
+#include "sl_platform.h"
+#include "base/sl_core_timer_llr.h"
+#include "base/sl_core_log.h"
+
+#define LOG_NAME SL_CORE_TIMER_LLR_LOG_NAME
+
+void sl_core_timer_llr_begin(struct sl_core_llr *core_llr, u32 timer_num)
+{
+	enum sl_core_llr_state llr_state;
+
+	if (core_llr->timers[timer_num].data.timeout_ms == 0) {
+		sl_core_log_warn_trace(core_llr, LOG_NAME,
+				       "begin %s timeout is 0 (timer_num = %u)",
+				      core_llr->timers[timer_num].data.log, timer_num);
+		return;
+	}
+
+	core_llr->timers[timer_num].timer.expires =
+		jiffies + msecs_to_jiffies(core_llr->timers[timer_num].data.timeout_ms);
+
+	sl_core_log_dbg(core_llr, LOG_NAME,
+			"begin %s (core_llr = 0x%p, timer_num = %u, timeout = %dms, jiffies = %ld)",
+			core_llr->timers[timer_num].data.log, core_llr, timer_num,
+			core_llr->timers[timer_num].data.timeout_ms,
+			core_llr->timers[timer_num].timer.expires);
+
+	spin_lock(&core_llr->data_lock);
+	llr_state = core_llr->state;
+	switch (llr_state) {
+	case SL_CORE_LLR_STATE_SETTING_UP:
+	case SL_CORE_LLR_STATE_STARTING:
+		add_timer(&core_llr->timers[timer_num].timer);
+		spin_unlock(&core_llr->data_lock);
+		return;
+	default:
+		sl_core_log_err(core_llr, LOG_NAME,
+				"begin %s invalid state (llr_state = %u %s, timer_num = %u)",
+				core_llr->timers[timer_num].data.log,
+				llr_state, sl_core_llr_state_str(llr_state), timer_num);
+		spin_unlock(&core_llr->data_lock);
+		return;
+	}
+}
+
+/**
+ * sl_core_timer_llr_timeout - Timer callback function executed in interrupt context.
+ * @timer: Pointer to the timer_list structure associated with the timer.
+ *
+ * Context: Interrupt context.
+ */
+void sl_core_timer_llr_timeout(struct timer_list *timer)
+{
+	struct sl_core_timer_llr_info *info;
+	struct sl_core_llr            *core_llr;
+
+	info = timer_container_of(info, timer, timer);
+	core_llr = info->data.core_llr;
+
+	sl_core_log_dbg(core_llr, LOG_NAME,
+			"timeout %s (core_llr = 0x%p, timer_num = %u, work_num = %u)",
+			info->data.log, core_llr,
+			info->data.timer_num, info->data.work_num);
+
+	queue_work(core_llr->core_lgrp->core_ldev->workqueue,
+		   &core_llr->work[info->data.work_num]);
+}
+
+void sl_core_timer_llr_end(struct sl_core_llr *core_llr, u32 timer_num)
+{
+	sl_core_log_dbg(core_llr, LOG_NAME,
+			"end %s (core_llr = 0x%p, timer_num = %u)",
+			core_llr->timers[timer_num].data.log, core_llr, timer_num);
+
+	timer_delete_sync(&core_llr->timers[timer_num].timer);
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/data/nic/sl_core_data_link.c b/drivers/net/ethernet/hpe/sl/core/data/nic/sl_core_data_link.c
new file mode 100644
index 000000000000..e4f6b7800e6c
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/data/nic/sl_core_data_link.c
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+
+#include "data/sl_core_data_link.h"
+
+u16 sl_core_data_link_clock_period_get(void)
+{
+	return 0x38D;
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/data/nic/sl_core_data_mac.c b/drivers/net/ethernet/hpe/sl/core/data/nic/sl_core_data_mac.c
new file mode 100644
index 000000000000..cb3ce36ff124
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/data/nic/sl_core_data_mac.c
@@ -0,0 +1,11 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+
+#include "data/sl_core_data_mac.h"
+
+u8 sl_core_data_mac_tx_cdt_init_get(void)
+{
+	return 64;
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/data/sl_core_data_ldev.c b/drivers/net/ethernet/hpe/sl/core/data/sl_core_data_ldev.c
new file mode 100644
index 000000000000..1d1dc0f73b17
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/data/sl_core_data_ldev.c
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2022,2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/spinlock.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <linux/workqueue.h>
+
+#include <linux/hpe/sl/sl_ldev.h>
+
+#include "sl_asic.h"
+#include "base/sl_core_log.h"
+#include "sl_core_ldev.h"
+#include "data/sl_core_data_ldev.h"
+#include "data/sl_core_data_lgrp.h"
+#include "hw/sl_core_hw_serdes_osprey.h"
+
+static struct sl_core_ldev *core_ldevs[SL_ASIC_MAX_LDEVS];
+static DEFINE_SPINLOCK(core_ldevs_lock);
+
+#define LOG_NAME SL_CORE_DATA_LDEV_LOG_NAME
+
+int sl_core_data_ldev_new(u8 ldev_num, struct sl_accessors *accessors,
+			  struct sl_ops *ops, struct workqueue_struct *workqueue)
+{
+	int                  rtn;
+	struct sl_core_ldev *core_ldev;
+	u16                  proto;
+
+	core_ldev = sl_core_ldev_get(ldev_num);
+	if (core_ldev) {
+		sl_core_log_err(NULL, LOG_NAME, "exists (ldev = 0x%p)", core_ldev);
+		return -EBADRQC;
+	}
+
+	core_ldev = kzalloc(sizeof(struct sl_core_ldev), GFP_KERNEL);
+	if (core_ldev == NULL)
+		return -ENOMEM;
+
+	core_ldev->magic           = SL_CORE_LDEV_MAGIC;
+	core_ldev->num             = ldev_num;
+	core_ldev->accessors       = *accessors;
+	core_ldev->ops             = *ops;
+	spin_lock_init(&(core_ldev->data_lock));
+
+	rtn = core_ldev->ops.mb_info_get(core_ldev->accessors.mb,
+		&(core_ldev->platform), &(core_ldev->revision), &proto);
+	if (rtn) {
+		sl_core_log_err(core_ldev, LOG_NAME, "mb_info_get failed [%d]", rtn);
+		kfree(core_ldev);
+		return -EIO;
+	}
+
+	core_ldev->workqueue = workqueue;
+
+	core_ldev->serdes.addrs = serdes_addrs_osprey;
+
+	sl_core_log_dbg(core_ldev, LOG_NAME, "new (ldev = 0x%p, platform = %u, revision = %u)",
+			core_ldev, core_ldev->platform, core_ldev->revision);
+
+	spin_lock(&core_ldevs_lock);
+	core_ldevs[ldev_num] = core_ldev;
+	spin_unlock(&core_ldevs_lock);
+
+	return 0;
+}
+
+int sl_core_data_ldev_del(u8 ldev_num)
+{
+	struct sl_core_ldev *core_ldev;
+	int                  lgrp_num;
+	int                  rtn;
+	int                  err = 0;
+
+	core_ldev = sl_core_ldev_get(ldev_num);
+	if (!core_ldev) {
+		sl_core_log_dbg(NULL, LOG_NAME, "not found (ldev_num = %u)", ldev_num);
+		return 0;
+	}
+
+	/*
+	 * The lgrps and links look this ldev up and point back at it, so they
+	 * must be deleted while it is still published and allocated. Try every
+	 * lgrp so as much as possible is deleted, and keep the first error.
+	 */
+	for (lgrp_num = 0; lgrp_num < SL_ASIC_MAX_LGRPS; ++lgrp_num) {
+		rtn = sl_core_data_lgrp_del(ldev_num, lgrp_num);
+		if (rtn && !err)
+			err = rtn;
+	}
+
+	/* An lgrp that could not be deleted still points at this ldev, so keep it. */
+	if (err) {
+		sl_core_log_err(core_ldev, LOG_NAME, "del - lgrp_del failed [%d]", err);
+		return err;
+	}
+
+	spin_lock(&core_ldevs_lock);
+	core_ldevs[ldev_num] = NULL;
+	spin_unlock(&core_ldevs_lock);
+
+	sl_core_log_dbg(core_ldev, LOG_NAME, "del (ldev = 0x%p)", core_ldev);
+
+	kfree(core_ldev);
+
+	return 0;
+}
+
+struct sl_core_ldev *sl_core_data_ldev_get(u8 ldev_num)
+{
+	struct sl_core_ldev *core_ldev;
+
+	spin_lock(&core_ldevs_lock);
+	core_ldev = core_ldevs[ldev_num];
+	spin_unlock(&core_ldevs_lock);
+
+	sl_core_log_dbg(NULL, LOG_NAME, "get (ldev_num = %u, ldev = 0x%p)",
+			ldev_num, core_ldev);
+
+	return core_ldev;
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/data/sl_core_data_lgrp.c b/drivers/net/ethernet/hpe/sl/core/data/sl_core_data_lgrp.c
new file mode 100644
index 000000000000..a1485787965b
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/data/sl_core_data_lgrp.c
@@ -0,0 +1,351 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2022-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/spinlock.h>
+#include <linux/slab.h>
+#include <linux/bitops.h>
+
+#include "sl_asic.h"
+#include "sl_platform.h"
+#include "base/sl_core_log.h"
+#include "sl_core_lgrp.h"
+#include "sl_core_link.h"
+#include "sl_core_str.h"
+#include "data/sl_core_data_ldev.h"
+#include "data/sl_core_data_lgrp.h"
+#include "data/sl_core_data_link.h"
+#include "hw/sl_core_hw_reset.h"
+#include "hw/sl_core_hw_serdes.h"
+
+static struct sl_core_lgrp *core_lgrps[SL_ASIC_MAX_LDEVS][SL_ASIC_MAX_LGRPS];
+static DEFINE_SPINLOCK(core_lgrps_lock);
+
+#define LOG_NAME SL_CORE_DATA_LGRP_LOG_NAME
+
+int sl_core_data_lgrp_new(u8 ldev_num, u8 lgrp_num)
+{
+	int                  rtn;
+	struct sl_core_lgrp *core_lgrp;
+
+	spin_lock(&core_lgrps_lock);
+	core_lgrp = core_lgrps[ldev_num][lgrp_num];
+	spin_unlock(&core_lgrps_lock);
+	if (core_lgrp) {
+		sl_core_log_err(NULL, LOG_NAME, "new - lgrp exists");
+		return -EBADRQC;
+	}
+
+	core_lgrp = kzalloc(sizeof(struct sl_core_lgrp), GFP_KERNEL);
+	if (core_lgrp == NULL)
+		return -ENOMEM;
+
+	core_lgrp->magic     = SL_CORE_LGRP_MAGIC;
+	core_lgrp->core_ldev = sl_core_data_ldev_get(ldev_num);
+	core_lgrp->num       = lgrp_num;
+	kref_init(&core_lgrp->ref);
+	snprintf(core_lgrp->log_connect_id, sizeof(core_lgrp->log_connect_id), "core-lgrp%02u", lgrp_num);
+	spin_lock_init(&(core_lgrp->log_lock));
+	spin_lock_init(&(core_lgrp->data_lock));
+
+	if (SL_PLATFORM_IS_HARDWARE(core_lgrp->core_ldev)) {
+		rtn = core_lgrp->core_ldev->ops.dt_info_get(core_lgrp->core_ldev->accessors.dt,
+			ldev_num, lgrp_num, &(core_lgrp->serdes.dt));
+		if (rtn)
+			sl_core_log_dbg(core_lgrp, LOG_NAME, "new - dt_info_get failed [%d]", rtn);
+		sl_core_log_dbg(core_lgrp, LOG_NAME, "DT lane = 0 tx = %u tx_inv = %u rx = %u rx_inv = %u",
+				core_lgrp->serdes.dt.lane_info[0].tx_source, core_lgrp->serdes.dt.lane_info[0].tx_invert,
+			core_lgrp->serdes.dt.lane_info[0].rx_source, core_lgrp->serdes.dt.lane_info[0].rx_invert);
+		sl_core_log_dbg(core_lgrp, LOG_NAME, "DT lane = 1 tx = %u tx_inv = %u rx = %u rx_inv = %u",
+				core_lgrp->serdes.dt.lane_info[1].tx_source, core_lgrp->serdes.dt.lane_info[1].tx_invert,
+			core_lgrp->serdes.dt.lane_info[1].rx_source, core_lgrp->serdes.dt.lane_info[1].rx_invert);
+		sl_core_log_dbg(core_lgrp, LOG_NAME, "DT lane = 2 tx = %u tx_inv = %u rx = %u rx_inv = %u",
+				core_lgrp->serdes.dt.lane_info[2].tx_source, core_lgrp->serdes.dt.lane_info[2].tx_invert,
+			core_lgrp->serdes.dt.lane_info[2].rx_source, core_lgrp->serdes.dt.lane_info[2].rx_invert);
+		sl_core_log_dbg(core_lgrp, LOG_NAME, "DT lane = 3 tx = %u tx_inv = %u rx = %u rx_inv = %u",
+				core_lgrp->serdes.dt.lane_info[3].tx_source, core_lgrp->serdes.dt.lane_info[3].tx_invert,
+			core_lgrp->serdes.dt.lane_info[3].rx_source, core_lgrp->serdes.dt.lane_info[3].rx_invert);
+		sl_core_log_dbg(core_lgrp, LOG_NAME, "DT jack_type = %u %s", core_lgrp->serdes.dt.jack_type,
+				sl_core_lgrp_dt_jack_part_str(core_lgrp->serdes.dt.jack_type));
+	} else {
+		/* straight for emulator */
+		core_lgrp->serdes.dt.lane_info[0].tx_source = 0;
+		core_lgrp->serdes.dt.lane_info[1].tx_source = 1;
+		core_lgrp->serdes.dt.lane_info[2].tx_source = 2;
+		core_lgrp->serdes.dt.lane_info[3].tx_source = 3;
+		core_lgrp->serdes.dt.lane_info[0].rx_source = 0;
+		core_lgrp->serdes.dt.lane_info[1].rx_source = 1;
+		core_lgrp->serdes.dt.lane_info[2].rx_source = 2;
+		core_lgrp->serdes.dt.lane_info[3].rx_source = 3;
+
+		/* No swap for emulator */
+		core_lgrp->serdes.dt.jack_type = lgrp_num % 2 ? SL_DT_JACK_TYPE_DD : SL_DT_JACK_TYPE_LEGACY;
+	}
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "new - dt info (id = %u, addr = 0x%X)",
+			core_lgrp->serdes.dt.dev_id, core_lgrp->serdes.dt.dev_addr);
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "new (lgrp = 0x%p)", core_lgrp);
+
+	spin_lock(&core_lgrps_lock);
+	if (core_lgrps[ldev_num][lgrp_num]) {
+		spin_unlock(&core_lgrps_lock);
+		sl_core_lgrp_put(core_lgrp);
+		return -EBADRQC;
+	}
+	core_lgrps[ldev_num][lgrp_num] = core_lgrp;
+	spin_unlock(&core_lgrps_lock);
+
+	return 0;
+}
+
+void sl_core_data_lgrp_connect_id_set(u8 ldev_num, u8 lgrp_num, const char *connect_id)
+{
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	unsigned long        irq_flags;
+
+	core_lgrp = sl_core_lgrp_get(ldev_num, lgrp_num);
+	if (!core_lgrp)
+		return;
+
+	spin_lock_irqsave(&(core_lgrp->log_lock), irq_flags);
+	strscpy_pad(core_lgrp->log_connect_id, connect_id,
+		    sizeof(core_lgrp->log_connect_id));
+	spin_unlock_irqrestore(&(core_lgrp->log_lock), irq_flags);
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "connect_id = %s", connect_id);
+}
+
+int sl_core_data_lgrp_del(u8 ldev_num, u8 lgrp_num)
+{
+	struct sl_core_lgrp *core_lgrp;
+	u8                   link_num;
+	bool                 is_configuring = false;
+	bool                 is_deleting = false;
+	int                  rtn;
+	int                  err = 0;
+
+	/*
+	 * Look the lgrp up, check it and claim it for deletion in one step.
+	 * core_lgrps_lock, with data_lock taken inside it, keeps another
+	 * deleter from finding the same lgrp and freeing it too. Only the
+	 * caller that sets is_deleting goes on to free it.
+	 */
+	spin_lock(&core_lgrps_lock);
+	core_lgrp = core_lgrps[ldev_num][lgrp_num];
+	if (core_lgrp) {
+		spin_lock(&core_lgrp->data_lock);
+		is_configuring = core_lgrp->is_configuring;
+		is_deleting = core_lgrp->is_deleting;
+		if (!is_configuring && !is_deleting)
+			core_lgrp->is_deleting = true;
+		spin_unlock(&core_lgrp->data_lock);
+	}
+	spin_unlock(&core_lgrps_lock);
+
+	if (!core_lgrp) {
+		sl_core_log_dbg(NULL, LOG_NAME, "del - not found (lgrp_num = %u)", lgrp_num);
+		return 0;
+	}
+
+	if (is_configuring) {
+		sl_core_log_err(NULL, LOG_NAME, "del - lgrp is configuring");
+		return -EBUSY;
+	}
+
+	if (is_deleting) {
+		sl_core_log_err(NULL, LOG_NAME, "del - lgrp is already being deleted");
+		return -EBUSY;
+	}
+
+	/*
+	 * A configuration that starts after the claim above is not stopped
+	 * here, as before, and a caller that looked the lgrp up earlier and
+	 * uses it after the free below is not covered either: the lookup does
+	 * not pin the lgrp.
+	 */
+
+	/* Try every link so as much as possible is deleted, and keep the first error. */
+	for (link_num = 0; link_num < SL_ASIC_MAX_LINKS; ++link_num) {
+		rtn = sl_core_data_link_del(ldev_num, lgrp_num, link_num);
+		if (rtn && !err)
+			err = rtn;
+	}
+
+	/*
+	 * A link that could not be deleted still points at this lgrp, so keep
+	 * it, and release the claim so that the delete can be retried.
+	 */
+	if (err)
+		goto out_retry;
+
+	spin_lock(&core_lgrps_lock);
+	if (refcount_read(&core_lgrp->ref.refcount) != 1) {
+		spin_unlock(&core_lgrps_lock);
+		err = -EBUSY;
+		goto out_retry;
+	}
+	core_lgrps[ldev_num][lgrp_num] = NULL;
+	spin_unlock(&core_lgrps_lock);
+
+	sl_core_lgrp_put(core_lgrp);
+	return 0;
+
+out_retry:
+	spin_lock(&core_lgrp->data_lock);
+	core_lgrp->is_deleting = false;
+	spin_unlock(&core_lgrp->data_lock);
+	sl_core_log_err(NULL, LOG_NAME, "del - busy or child failure [%d]", err);
+	return err;
+}
+
+struct sl_core_lgrp *sl_core_data_lgrp_get(u8 ldev_num, u8 lgrp_num)
+{
+	struct sl_core_lgrp *core_lgrp;
+
+	spin_lock(&core_lgrps_lock);
+	core_lgrp = core_lgrps[ldev_num][lgrp_num];
+	if (core_lgrp) {
+		spin_lock(&core_lgrp->data_lock);
+		if (core_lgrp->is_deleting) {
+			spin_unlock(&core_lgrp->data_lock);
+			core_lgrp = NULL;
+		} else {
+			kref_get(&core_lgrp->ref);
+			spin_unlock(&core_lgrp->data_lock);
+		}
+	}
+	spin_unlock(&core_lgrps_lock);
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "get (lgrp = 0x%p)", core_lgrp);
+
+	return core_lgrp;
+}
+
+static void sl_core_data_lgrp_release(struct kref *ref)
+{
+	kfree(container_of(ref, struct sl_core_lgrp, ref));
+}
+
+void sl_core_lgrp_put(struct sl_core_lgrp *core_lgrp)
+{
+	if (core_lgrp)
+		kref_put(&core_lgrp->ref, sl_core_data_lgrp_release);
+}
+
+int sl_core_data_lgrp_link_config_check(struct sl_core_lgrp *core_lgrp)
+{
+	int                  rtn;
+	int                  link_num;
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+	enum sl_core_link_state link_state;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "link config check");
+
+	for (link_num = 0; link_num < SL_ASIC_MAX_LINKS; ++link_num) {
+		core_link = sl_core_link_get(core_lgrp->core_ldev->num, core_lgrp->num, link_num);
+		if (!core_link)
+			continue;
+
+		rtn = sl_core_data_link_state_get(core_link, &link_state);
+		if (rtn) {
+			sl_core_log_err_trace(core_lgrp, LOG_NAME,
+					      "lgrp link config check - link_state_get failed [%d]", rtn);
+			return rtn;
+		}
+
+		switch (link_state) {
+		case SL_CORE_LINK_STATE_UNCONFIGURED:
+		case SL_CORE_LINK_STATE_CONFIGURING:
+		case SL_CORE_LINK_STATE_CONFIGURED:
+		case SL_CORE_LINK_STATE_DOWN:
+			continue;
+		default:
+			sl_core_log_err(core_lgrp, LOG_NAME,
+					"lgrp link config check wrong state (link_num = %u, state = %u %s)",
+					link_num, link_state, sl_core_link_state_str(link_state));
+			return -EBADRQC;
+		}
+	}
+
+	return 0;
+}
+
+void sl_core_data_lgrp_hw_attr_set(struct sl_core_lgrp *core_lgrp, struct sl_hw_attr *hw_attr)
+{
+	sl_core_log_dbg(core_lgrp, LOG_NAME,
+			"hw attr set (cxi = %u, nic = %u)", hw_attr->cxi_num, hw_attr->nic_num);
+
+	core_lgrp->hw_attr = *hw_attr;
+}
+
+void sl_core_data_lgrp_config_set(struct sl_core_lgrp *core_lgrp, struct sl_lgrp_config *lgrp_config)
+{
+	int  rtn;
+	bool need_swizzled;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "config set");
+
+	/* if furcation changes, then we have to reset */
+	if (lgrp_config->furcation != core_lgrp->config.furcation)
+		sl_core_hw_reset_lgrp(core_lgrp);
+
+	/* if loopback enable changes, then we have to swizzle */
+	need_swizzled = false;
+	if ((lgrp_config->options & SL_LGRP_CONFIG_OPT_SERDES_LOOPBACK_ENABLE) !=
+		(core_lgrp->config.options & SL_LGRP_CONFIG_OPT_SERDES_LOOPBACK_ENABLE))
+		need_swizzled = true;
+
+	core_lgrp->config = *lgrp_config;
+
+	if (need_swizzled) {
+		rtn = sl_core_hw_serdes_swizzles(core_lgrp);
+		if (rtn)
+			sl_core_log_warn_trace(core_lgrp, LOG_NAME,
+					       "hw_serdes_swizzles failed [%d]", rtn);
+	}
+}
+
+u32 sl_core_data_lgrp_config_flags_get(struct sl_core_lgrp *core_lgrp)
+{
+	u32 flags;
+
+	spin_lock(&core_lgrp->data_lock);
+	flags = core_lgrp->config.options;
+	spin_unlock(&core_lgrp->data_lock);
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "config flags get (flags = 0x%X)", flags);
+
+	return flags;
+}
+
+int sl_core_data_lgrp_err_trace_enable_set(struct sl_core_lgrp *core_lgrp, bool err_trace_enable)
+{
+	spin_lock(&core_lgrp->data_lock);
+	core_lgrp->err_trace_enable = err_trace_enable;
+	spin_unlock(&core_lgrp->data_lock);
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "set (err_trace_enable = %s)", err_trace_enable ? "true" : "false");
+
+	return 0;
+}
+
+int sl_core_data_lgrp_warn_trace_enable_set(struct sl_core_lgrp *core_lgrp, bool warn_trace_enable)
+{
+	spin_lock(&core_lgrp->data_lock);
+	core_lgrp->warn_trace_enable = warn_trace_enable;
+	spin_unlock(&core_lgrp->data_lock);
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "set (warn_trace_enable = %s)", warn_trace_enable ? "true" : "false");
+
+	return 0;
+}
+
+int sl_core_data_lgrp_io_trace_set(struct sl_core_lgrp *core_lgrp, bool io_trace)
+{
+	spin_lock(&core_lgrp->data_lock);
+	core_lgrp->io_trace = io_trace;
+	spin_unlock(&core_lgrp->data_lock);
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "set (io_trace = %s)", io_trace ? "enabled" : "disabled");
+
+	return 0;
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/data/sl_core_data_lgrp_trace.c b/drivers/net/ethernet/hpe/sl/core/data/sl_core_data_lgrp_trace.c
new file mode 100644
index 000000000000..00a7f5490625
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/data/sl_core_data_lgrp_trace.c
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2025-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/spinlock.h>
+
+#include "data/sl_core_data_lgrp_trace.h"
+
+#define LOG_NAME SL_CORE_DATA_LGRP_LOG_NAME
+
+int sl_core_data_lgrp_is_err_trace_enabled(struct sl_core_lgrp *core_lgrp, bool *err_trace_enable)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*err_trace_enable = core_lgrp->err_trace_enable;
+	spin_unlock(&core_lgrp->data_lock);
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME,
+			"is err trace enabled (err_trace_enable = %s)",
+			*err_trace_enable ? "true" : "false");
+
+	return 0;
+}
+
+int sl_core_data_lgrp_is_warn_trace_enabled(struct sl_core_lgrp *core_lgrp, bool *warn_trace_enable)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*warn_trace_enable = core_lgrp->warn_trace_enable;
+	spin_unlock(&core_lgrp->data_lock);
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME,
+			"is warn trace enabled (warn_trace_enable = %s)",
+			*warn_trace_enable ? "true" : "false");
+
+	return 0;
+}
+
+bool sl_core_data_lgrp_is_io_trace_enabled(struct sl_core_lgrp *core_lgrp)
+{
+	bool io_trace;
+
+	spin_lock(&core_lgrp->data_lock);
+	io_trace = core_lgrp->io_trace;
+	spin_unlock(&core_lgrp->data_lock);
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME,
+			"is io trace enabled (io_trace = %s)",
+			io_trace ? "enabled" : "disabled");
+
+	return io_trace;
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/data/sl_core_data_link.c b/drivers/net/ethernet/hpe/sl/core/data/sl_core_data_link.c
new file mode 100644
index 000000000000..6cc97e7f9230
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/data/sl_core_data_link.c
@@ -0,0 +1,1343 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2022-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/spinlock.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/workqueue.h>
+#include <linux/ktime.h>
+
+#include "base/sl_core_log.h"
+#include "sl_core_ldev.h"
+#include "sl_core_lgrp.h"
+#include "sl_core_link.h"
+#include "sl_core_str.h"
+#include "sl_ctrl_link.h"
+#include "sl_ctrl_link_counters.h"
+#include "data/sl_core_data_link.h"
+#include "hw/sl_core_hw_intr.h"
+#include "hw/sl_core_hw_link.h"
+#include "hw/sl_core_hw_an.h"
+#include "hw/sl_core_hw_an_up.h"
+#include "hw/sl_core_hw_an_lp.h"
+#include "sl_core_hw_intr_flgs.h"
+#include "hw/sl_core_hw_settings.h"
+#include "hw/sl_core_hw_llr.h"
+#include "hw/sl_core_hw_io.h"
+
+/* 0x01002510 (hni_pcs_corrected_cw)
+ * 0x01002618 (hni_pcs_corrected_cw_bin_14)
+ * (0x01002618 + 0x8) - 0x01002510 = 0x110 = Size
+ */
+#define SL_CORE_HW_FEC_CNTRS_OFFSET 0x01002510
+#define SL_CORE_HW_FEC_CNTRS_SIZE   0x110
+
+#define SL_CORE_HW_FEC_UP_SETTLE_WAIT_MS 250
+#define SL_CORE_HW_FEC_UP_CHECK_WAIT_MS  500
+
+static struct sl_core_link *core_links[SL_ASIC_MAX_LDEVS][SL_ASIC_MAX_LGRPS][SL_ASIC_MAX_LINKS];
+static DEFINE_SPINLOCK(core_links_lock);
+
+#define LOG_NAME SL_CORE_DATA_LINK_LOG_NAME
+
+static void sl_core_data_link_free(struct sl_core_link *core_link);
+
+#define SL_CORE_TIMER_INIT(_link, _timer_num, _work_num, _log)           \
+	do {                                                             \
+		(_link)->timers[_timer_num].data.link      = _link;      \
+		(_link)->timers[_timer_num].data.timer_num = _timer_num; \
+		(_link)->timers[_timer_num].data.work_num  = _work_num;  \
+		strscpy_pad((_link)->timers[_timer_num].data.log, _log, \
+			sizeof((_link)->timers[_timer_num].data.log));   \
+	} while (0)
+#define SL_CORE_INTR_INIT(_link, _intr_num, _work_num, _log)           \
+	do {                                                           \
+		(_link)->intrs[_intr_num].flgs =                       \
+			sl_core_hw_intr_flgs[_intr_num][(_link)->num]; \
+		(_link)->intrs[_intr_num].data.link     = _link;       \
+		(_link)->intrs[_intr_num].data.intr_num = _intr_num;   \
+		(_link)->intrs[_intr_num].data.work_num = _work_num;   \
+		strscpy_pad((_link)->intrs[_intr_num].data.log, _log, \
+			sizeof((_link)->intrs[_intr_num].data.log));   \
+	} while (0)
+
+static int sl_core_data_link_init(struct sl_core_lgrp *core_lgrp, u8 link_num, struct sl_core_link *core_link)
+{
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"link init (link = 0x%p, lgrp = 0x%p)", core_link, core_lgrp);
+
+	/* ----- general ----- */
+
+	core_link->magic         = SL_CORE_LINK_MAGIC;
+	core_link->num           = link_num;
+	core_link->core_lgrp     = core_lgrp;
+	kref_get(&core_lgrp->ref);
+	core_link->an.fail_cause = SL_CORE_HW_AN_FAIL_CAUSE_NONE;
+	spin_lock_init(&(core_link->data_lock));
+	kref_init(&core_link->ref);
+	spin_lock_init(&(core_link->irq_data_lock));
+	spin_lock_init(&(core_link->serdes.data_lock));
+
+	/* ----- link ----- */
+
+	spin_lock_init(&(core_link->link.data_lock));
+
+	timer_setup(&(core_link->timers[SL_CORE_TIMER_LINK_UP].timer),
+		    sl_core_timer_link_timeout, 0);
+	SL_CORE_TIMER_INIT(core_link, SL_CORE_TIMER_LINK_UP,
+			   SL_CORE_WORK_LINK_UP_TIMEOUT, "link up");
+	timer_setup(&(core_link->timers[SL_CORE_TIMER_LINK_UP_CHECK].timer),
+		    sl_core_timer_link_timeout, 0);
+	SL_CORE_TIMER_INIT(core_link, SL_CORE_TIMER_LINK_UP_CHECK,
+			   SL_CORE_WORK_LINK_UP_CHECK, "link up check");
+	timer_setup(&(core_link->timers[SL_CORE_TIMER_LINK_UP_HIGH_POWER].timer),
+		    sl_core_timer_link_timeout, 0);
+	SL_CORE_TIMER_INIT(core_link, SL_CORE_TIMER_LINK_UP_HIGH_POWER,
+			   SL_CORE_WORK_LINK_UP, "link up high power");
+
+	SL_CORE_INTR_INIT(core_link, SL_CORE_HW_INTR_LINK_UP,
+			  SL_CORE_WORK_LINK_UP_INTR, "link up");
+	SL_CORE_INTR_INIT(core_link, SL_CORE_HW_INTR_LINK_HIGH_SER,
+			  SL_CORE_WORK_LINK_HIGH_SER_INTR, "link high SER");
+	SL_CORE_INTR_INIT(core_link, SL_CORE_HW_INTR_LINK_LLR_MAX_STARVATION,
+			  SL_CORE_WORK_LINK_LLR_MAX_STARVATION_INTR, "link llr max starvation");
+	SL_CORE_INTR_INIT(core_link, SL_CORE_HW_INTR_LINK_LLR_STARVED,
+			  SL_CORE_WORK_LINK_LLR_STARVED_INTR, "link llr starved");
+	SL_CORE_INTR_INIT(core_link, SL_CORE_HW_INTR_LINK_FAULT,
+			  SL_CORE_WORK_LINK_FAULT_INTR, "link fault");
+
+	INIT_WORK(&(core_link->work[SL_CORE_WORK_LINK_AN_UP_START]),
+		  sl_core_hw_an_up_start_work);
+	INIT_WORK(&(core_link->work[SL_CORE_WORK_LINK_UP_START]),
+		  sl_core_hw_link_up_start_work);
+	INIT_WORK(&(core_link->work[SL_CORE_WORK_LINK_UP]),
+		  sl_core_hw_link_up_work);
+	INIT_WORK(&(core_link->work[SL_CORE_WORK_LINK_UP_INTR]),
+		  sl_core_hw_link_up_intr_work);
+	INIT_WORK(&(core_link->work[SL_CORE_WORK_LINK_UP_TIMEOUT]),
+		  sl_core_hw_link_up_timeout_work);
+	INIT_WORK(&(core_link->work[SL_CORE_WORK_LINK_UP_CHECK]),
+		  sl_core_hw_link_up_check_work);
+	INIT_WORK(&(core_link->work[SL_CORE_WORK_LINK_HIGH_SER_INTR]),
+		  sl_core_hw_link_high_ser_intr_work);
+	INIT_WORK(&(core_link->work[SL_CORE_WORK_LINK_LLR_MAX_STARVATION_INTR]),
+		  sl_core_hw_link_llr_max_starvation_intr_work);
+	INIT_WORK(&(core_link->work[SL_CORE_WORK_LINK_LLR_STARVED_INTR]),
+		  sl_core_hw_link_llr_starved_intr_work);
+	INIT_WORK(&(core_link->work[SL_CORE_WORK_LINK_FAULT_INTR]),
+		  sl_core_hw_link_fault_intr_work);
+	INIT_WORK(&(core_link->work[SL_CORE_WORK_LINK_UP_CANCEL]),
+		  sl_core_hw_link_up_cancel_work);
+	INIT_WORK(&(core_link->work[SL_CORE_WORK_LINK_UP_FAIL]),
+		  sl_core_hw_link_up_fail_work);
+	INIT_WORK(&(core_link->work[SL_CORE_WORK_LINK_DOWN]),
+		  sl_core_hw_link_down_work);
+
+	/* ----- pml recovery ----- */
+
+	INIT_WORK(&(core_link->work[SL_CORE_WORK_LINK_PML_REC_POLL]),
+		  sl_core_hw_link_pml_rec_poll_work);
+
+	/* ----- an ----- */
+
+	spin_lock_init(&(core_link->an.data_lock));
+	core_link->an.lp_caps_state = SL_CORE_LINK_LP_CAPS_NOT_RUNNING;
+
+	timer_setup(&(core_link->timers[SL_CORE_TIMER_LINK_AN_LP_CAPS_GET].timer),
+		    sl_core_timer_link_timeout, 0);
+	SL_CORE_TIMER_INIT(core_link, SL_CORE_TIMER_LINK_AN_LP_CAPS_GET,
+			   SL_CORE_WORK_LINK_AN_LP_CAPS_GET_TIMEOUT, "an lp caps get");
+
+	SL_CORE_INTR_INIT(core_link, SL_CORE_HW_INTR_AN_PAGE_RECV, 0, "an page recv");
+
+	INIT_WORK(&(core_link->work[SL_CORE_WORK_LINK_AN_LP_CAPS_GET]),
+		  sl_core_hw_an_lp_caps_get_work);
+	INIT_WORK(&(core_link->work[SL_CORE_WORK_LINK_AN_LP_CAPS_GET_TIMEOUT]),
+		  sl_core_hw_an_lp_caps_get_timeout_work);
+	INIT_WORK(&(core_link->work[SL_CORE_WORK_LINK_AN_LP_CAPS_GET_DONE]),
+		  sl_core_hw_an_lp_caps_get_done_work);
+	INIT_WORK(&(core_link->work[SL_CORE_WORK_LINK_AN_UP]),
+		  sl_core_hw_an_up_work);
+	INIT_WORK(&(core_link->work[SL_CORE_WORK_LINK_AN_UP_DONE]),
+		  sl_core_hw_an_up_done_work);
+
+	/* ----- fec ----- */
+
+	timer_setup(&(core_link->timers[SL_CORE_TIMER_LINK_UP_FEC_SETTLE].timer),
+		    sl_core_timer_link_timeout, 0);
+	SL_CORE_TIMER_INIT(core_link, SL_CORE_TIMER_LINK_UP_FEC_SETTLE,
+			   SL_CORE_WORK_LINK_UP_FEC_SETTLE, "link up fec settle");
+	timer_setup(&(core_link->timers[SL_CORE_TIMER_LINK_UP_FEC_CHECK].timer),
+		    sl_core_timer_link_timeout, 0);
+	SL_CORE_TIMER_INIT(core_link, SL_CORE_TIMER_LINK_UP_FEC_CHECK,
+			   SL_CORE_WORK_LINK_UP_FEC_CHECK, "link up fec check");
+
+	INIT_WORK(&(core_link->work[SL_CORE_WORK_LINK_UP_FEC_SETTLE]),
+		  sl_core_hw_link_up_fec_settle_work);
+	INIT_WORK(&(core_link->work[SL_CORE_WORK_LINK_UP_FEC_CHECK]),
+		  sl_core_hw_link_up_fec_check_work);
+
+	spin_lock_init(&core_link->fec.test_lock);
+
+	atomic_set(&core_link->an.retry_count, 0);
+
+	/* ----- ald ----- */
+
+	SL_CORE_INTR_INIT(core_link, SL_CORE_HW_INTR_LANE_DEGRADE,
+			  SL_CORE_WORK_LINK_LANE_DEGRADE_INTR, "lane degrade");
+
+	INIT_WORK(&(core_link->work[SL_CORE_WORK_LINK_LANE_DEGRADE_INTR]),
+		  sl_core_hw_link_lane_degrade_intr_work);
+
+	/* do very last thing */
+	core_link->link.state = SL_CORE_LINK_STATE_UNCONFIGURED;
+	sl_media_jack_led_set(core_link->core_lgrp->core_ldev->num, core_link->core_lgrp->num);
+
+	return 0;
+}
+
+int sl_core_data_link_new(u8 ldev_num, u8 lgrp_num, u8 link_num)
+{
+	int                  rtn;
+	struct sl_core_link *core_link;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	struct sl_core_ldev *core_ldev;
+	u8                   is_configuring;
+
+	core_ldev = sl_core_ldev_get(ldev_num);
+	core_lgrp = sl_core_lgrp_get(ldev_num, lgrp_num);
+	if (!core_lgrp)
+		return -ENODEV;
+	spin_lock(&core_lgrp->data_lock);
+	is_configuring = core_lgrp->is_configuring;
+	spin_unlock(&core_lgrp->data_lock);
+	if (is_configuring) {
+		sl_core_log_err(core_lgrp, LOG_NAME, "lgrp is configuring");
+		return -EBADRQC;
+	}
+
+	spin_lock(&core_links_lock);
+	core_link = core_links[ldev_num][lgrp_num][link_num];
+	spin_unlock(&core_links_lock);
+	if (core_link) {
+		sl_core_log_err(NULL, LOG_NAME, "link exists");
+		return -EBADRQC;
+	}
+
+	core_link = kzalloc(sizeof(struct sl_core_link), GFP_KERNEL);
+	if (core_link == NULL)
+		return -ENOMEM;
+
+	rtn = sl_core_data_link_init(core_lgrp, link_num, core_link);
+	if (rtn != 0) {
+		sl_core_log_err(core_link, LOG_NAME, "core_data_link_init failed [%d]", rtn);
+		kfree(core_link);
+		return rtn;
+	}
+
+	core_link->is_deleting = true;
+	spin_lock(&core_links_lock);
+	if (core_links[ldev_num][lgrp_num][link_num]) {
+		spin_unlock(&core_links_lock);
+		sl_core_data_link_put_pinned(core_link);
+		return -EBADRQC;
+	}
+	core_links[ldev_num][lgrp_num][link_num] = core_link;
+	spin_unlock(&core_links_lock);
+
+	rtn = sl_core_hw_intr_hdlr_register(core_link);
+	if (rtn != 0) {
+		sl_core_log_err_trace(core_link, LOG_NAME, "core_hw_intr_hdlr_register failed [%d]", rtn);
+		goto out_unwind;
+	}
+
+	if (link_num == 0) {
+		rtn = sl_core_hw_intr_register(core_link, core_link->intrs[SL_CORE_HW_INTR_LANE_DEGRADE].flgs,
+					       sl_core_hw_intr_hdlr, &(core_link->intrs[SL_CORE_HW_INTR_LANE_DEGRADE].data));
+		if (rtn != 0) {
+			sl_core_log_err_trace(core_link, LOG_NAME, "intr register degrade failed [%d]", rtn);
+			goto out_unwind;
+		}
+	}
+
+	sl_core_hw_llr_link_init(core_link);
+
+	if (core_ldev->ops.dmac_alloc) {
+		rtn = core_ldev->ops.dmac_alloc(
+			core_ldev->accessors.dmac,
+			SL_CORE_HW_FEC_CNTRS_OFFSET,
+			SL_CORE_HW_FEC_CNTRS_SIZE);
+		if (rtn) {
+			sl_core_log_err(core_link, LOG_NAME, "dmac_alloc failed [%d]", rtn);
+			goto out_unwind;
+		}
+	}
+
+	sl_core_log_dbg(core_link, LOG_NAME, "new (link = 0x%p)", core_link);
+
+	spin_lock(&core_links_lock);
+	core_link->is_deleting = false;
+	spin_unlock(&core_links_lock);
+
+	return 0;
+
+out_unwind:
+	spin_lock(&core_links_lock);
+	core_links[ldev_num][lgrp_num][link_num] = NULL;
+	spin_unlock(&core_links_lock);
+	/* Registration may be partial; unregistering a never-registered handler only warns. */
+	sl_core_hw_intr_hdlr_unregister(core_link);
+	sl_core_data_link_free(core_link);
+	sl_core_data_link_put_pinned(core_link);
+	return rtn;
+}
+
+static void sl_core_data_link_free(struct sl_core_link *core_link)
+{
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"link free (link = 0x%p, lgrp = 0x%p)", core_link, core_link->core_lgrp);
+
+	sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_AN_LP_CAPS_GET);
+	sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP_FEC_SETTLE);
+	sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP_FEC_CHECK);
+	sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP);
+	sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP_CHECK);
+	sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP_HIGH_POWER);
+
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_AN_LP_CAPS_GET]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_AN_LP_CAPS_GET_TIMEOUT]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_AN_LP_CAPS_GET_DONE]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_AN_UP_START]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_AN_UP]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_AN_UP_DONE]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_UP_START]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_UP]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_UP_TIMEOUT]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_UP_CHECK]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_UP_FEC_SETTLE]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_UP_FEC_CHECK]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_UP_FAIL]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_UP_CANCEL]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_DOWN]));
+
+	sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_LINK_UP);
+	sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_LINK_HIGH_SER);
+	sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_LINK_LLR_MAX_STARVATION);
+	sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_LINK_LLR_STARVED);
+	sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_LINK_FAULT);
+
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_UP_INTR]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_HIGH_SER_INTR]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_LLR_MAX_STARVATION_INTR]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_LLR_STARVED_INTR]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_FAULT_INTR]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_LANE_DEGRADE_INTR]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_PML_REC_POLL]));
+}
+
+int sl_core_data_link_del(u8 ldev_num, u8 lgrp_num, u8 link_num)
+{
+	struct sl_core_link *core_link;
+	struct sl_core_lgrp *core_lgrp;
+	struct sl_core_ldev *core_ldev;
+
+	spin_lock(&core_links_lock);
+	core_link = core_links[ldev_num][lgrp_num][link_num];
+	if (!core_link) {
+		spin_unlock(&core_links_lock);
+		sl_core_log_dbg(NULL, LOG_NAME,
+				"not found (ldev_num = %u, lgrp_num = %u, link_num = %u)",
+			ldev_num, lgrp_num, link_num);
+		return 0;
+	}
+
+	/* A link is deleted before its lgrp and ldev, so both must still be published. */
+	core_lgrp = core_link->core_lgrp;
+	core_ldev = core_lgrp->core_ldev;
+
+	spin_lock(&core_lgrp->data_lock);
+	if (core_lgrp->is_configuring || core_link->is_deleting ||
+	    refcount_read(&core_link->ref.refcount) != 1) {
+		spin_unlock(&core_lgrp->data_lock);
+		spin_unlock(&core_links_lock);
+		return -EBUSY;
+	}
+	core_link->is_deleting = true;
+	spin_unlock(&core_lgrp->data_lock);
+	spin_unlock(&core_links_lock);
+
+	sl_core_log_dbg(core_link, LOG_NAME, "del (link = 0x%p)", core_link);
+
+	sl_core_hw_intr_hdlr_unregister(core_link);
+
+	sl_core_data_link_free(core_link);
+
+	if (core_ldev->ops.dmac_free)
+		core_ldev->ops.dmac_free(core_ldev->accessors.dmac);
+
+	spin_lock(&core_links_lock);
+	core_links[ldev_num][lgrp_num][link_num] = NULL;
+	spin_unlock(&core_links_lock);
+
+	/* Drop the table's reference; the memory stays until pinned users are done. */
+	sl_core_data_link_put_pinned(core_link);
+
+	return 0;
+}
+
+struct sl_core_link *sl_core_data_link_get(u8 ldev_num, u8 lgrp_num, u8 link_num)
+{
+	struct sl_core_link *core_link;
+
+	spin_lock(&core_links_lock);
+	core_link = core_links[ldev_num][lgrp_num][link_num];
+	if (core_link && !core_link->is_deleting)
+		kref_get(&core_link->ref);
+	else
+		core_link = NULL;
+	spin_unlock(&core_links_lock);
+
+	sl_core_log_dbg(core_link, LOG_NAME, "get (link = 0x%p)", core_link);
+
+	return core_link;
+}
+
+/*
+ * Both lookup variants retain the link, its resources and its parent until
+ * the matching put. Deletion returns -EBUSY while lookup references remain.
+ * Returns NULL if the link is absent, initializing or being deleted.
+ */
+struct sl_core_link *sl_core_data_link_get_pinned(u8 ldev_num, u8 lgrp_num, u8 link_num)
+{
+	return sl_core_data_link_get(ldev_num, lgrp_num, link_num);
+}
+
+static void sl_core_data_link_release(struct kref *ref)
+{
+	struct sl_core_link *core_link = container_of(ref, struct sl_core_link, ref);
+
+	sl_core_lgrp_put(core_link->core_lgrp);
+	kfree(core_link);
+}
+
+void sl_core_data_link_put_pinned(struct sl_core_link *core_link)
+{
+	kref_put(&core_link->ref, sl_core_data_link_release);
+}
+
+void sl_core_data_link_config_set(struct sl_core_link *core_link,
+				  struct sl_core_link_config *link_config)
+{
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"config set (flags = 0x%X, hpe_map = 0x%X, pause_map = 0x%X)",
+		link_config->flags, link_config->hpe_map, link_config->pause_map);
+
+	spin_lock(&core_link->data_lock);
+	core_link->config = *link_config;
+	if (!is_flag_set(core_link->config.flags, SL_LINK_CONFIG_OPT_AUTONEG_ENABLE))
+		memset(core_link->core_lgrp->link_caps, 0, sizeof(core_link->core_lgrp->link_caps));
+	spin_unlock(&core_link->data_lock);
+
+	sl_core_data_link_state_set(core_link, SL_CORE_LINK_STATE_CONFIGURED);
+}
+
+int sl_core_data_link_settings(struct sl_core_link *core_link)
+{
+	struct sl_ctrl_link *held_link_1 __free(sl_ctrl_link_put) = NULL;
+	struct sl_lgrp_config *lgrp_config;
+	struct sl_link_caps   *link_caps;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "settings");
+
+	lgrp_config = &(core_link->core_lgrp->config);
+	link_caps   = &(core_link->core_lgrp->link_caps[core_link->num]);
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"settings - tech map  = 0x%08X", link_caps->tech_map);
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"settings - fec map   = 0x%08X", link_caps->fec_map);
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"settings - pause map = 0x%08X", link_caps->pause_map);
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"settings - hpe map   = 0x%08X", link_caps->hpe_map);
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"settings - furcation = %u", lgrp_config->furcation);
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"settings - options   = %u", lgrp_config->options);
+
+	/* abilities */
+	if (hweight_long(link_caps->tech_map) != 1) {
+		sl_core_log_err_trace(core_link, LOG_NAME, "settings - tech map invalid (map = 0x%08X)",
+				      link_caps->tech_map);
+		return -EINVAL;
+	}
+	if (hweight_long(link_caps->fec_map) > 1) {
+		sl_core_log_err_trace(core_link, LOG_NAME, "settings - fec map invalid (map = 0x%08X)",
+				      link_caps->fec_map);
+		return -EINVAL;
+	}
+
+	/* PCS */
+	core_link->pcs.settings.clock_period = sl_core_data_link_clock_period_get();
+	if (SL_LGRP_CONFIG_TECH_CK_400G & link_caps->tech_map) {
+		core_link->pcs.settings.speed                      = SL_LGRP_CONFIG_TECH_CK_400G;
+		core_link->pcs.settings.pcs_mode                   = SL_CORE_HW_PCS_MODE_CK_400G;
+		core_link->pcs.settings.rx_active_lanes            = SL_CORE_HW_ACTIVE_LANES_CK_400G;
+		core_link->pcs.settings.rx_am_lock_lanes           = SL_CORE_HW_AM_LOCK_LANES_CK_400G;
+		if (is_flag_set(lgrp_config->options, SL_LGRP_CONFIG_OPT_FABRIC)) {
+			core_link->pcs.settings.tx_cdc_ready_level         = 8;
+			core_link->pcs.settings.tx_en_pk_bw_limiter        = 1;
+			core_link->pcs.settings.tx_gearbox_credits         = 12;
+			core_link->pcs.settings.cw_gap                     = 6;
+		} else {
+			core_link->pcs.settings.tx_cdc_ready_level         = 8;
+			core_link->pcs.settings.tx_en_pk_bw_limiter        = 1;
+			core_link->pcs.settings.tx_gearbox_credits         = 8;
+			core_link->pcs.settings.cw_gap                     = 6;
+		}
+		if (sl_core_link_config_is_enable_ald_set(core_link))
+			core_link->pcs.settings.tx_gearbox_credits = 12;
+	}
+	if (SL_LGRP_CONFIG_TECH_CK_200G & link_caps->tech_map) {
+		core_link->pcs.settings.speed                      = SL_LGRP_CONFIG_TECH_CK_200G;
+		core_link->pcs.settings.pcs_mode                   = SL_CORE_HW_PCS_MODE_CK_200G;
+		core_link->pcs.settings.rx_active_lanes            = SL_CORE_HW_ACTIVE_LANES_CK_200G(core_link->num);
+		core_link->pcs.settings.rx_am_lock_lanes           = SL_CORE_HW_AM_LOCK_LANES_CK_200G(core_link->num);
+		core_link->pcs.settings.tx_cdc_ready_level         = 8;
+		core_link->pcs.settings.tx_en_pk_bw_limiter        = 1;
+		core_link->pcs.settings.tx_gearbox_credits         = 8;
+		core_link->pcs.settings.cw_gap                     = 6;
+	}
+	if (SL_LGRP_CONFIG_TECH_CK_100G & link_caps->tech_map) {
+		core_link->pcs.settings.speed                      = SL_LGRP_CONFIG_TECH_CK_100G;
+		core_link->pcs.settings.pcs_mode                   = SL_CORE_HW_PCS_MODE_CK_100G;
+		core_link->pcs.settings.rx_active_lanes            = SL_CORE_HW_ACTIVE_LANES_CK_100G(core_link->num);
+		core_link->pcs.settings.rx_am_lock_lanes           = SL_CORE_HW_AM_LOCK_LANES_CK_100G(core_link->num);
+		core_link->pcs.settings.tx_cdc_ready_level         = 8;
+		core_link->pcs.settings.tx_en_pk_bw_limiter        = 1;
+		core_link->pcs.settings.tx_gearbox_credits         = 4;
+		core_link->pcs.settings.cw_gap                     = 16;
+	}
+	if (SL_LGRP_CONFIG_TECH_BS_200G & link_caps->tech_map) {
+		core_link->pcs.settings.speed                      = SL_LGRP_CONFIG_TECH_BS_200G;
+		core_link->pcs.settings.pcs_mode                   = SL_CORE_HW_PCS_MODE_BS_200G;
+		core_link->pcs.settings.rx_active_lanes            = SL_CORE_HW_ACTIVE_LANES_BS_200G;
+		core_link->pcs.settings.rx_am_lock_lanes           = SL_CORE_HW_AM_LOCK_LANES_BS_200G;
+		if (is_flag_set(lgrp_config->options, SL_LGRP_CONFIG_OPT_FABRIC)) {
+			core_link->pcs.settings.tx_cdc_ready_level         = 8;
+			core_link->pcs.settings.tx_en_pk_bw_limiter        = 0;
+			core_link->pcs.settings.tx_gearbox_credits         = 12;
+			core_link->pcs.settings.cw_gap                     = 6;
+		} else {
+			core_link->pcs.settings.tx_cdc_ready_level         = 8;
+			core_link->pcs.settings.tx_en_pk_bw_limiter        = 0;
+			core_link->pcs.settings.tx_gearbox_credits         = 8;
+			if (is_flag_set(lgrp_config->options, SL_LGRP_CONFIG_OPT_R1))
+				core_link->pcs.settings.cw_gap             = 24;
+			else
+				core_link->pcs.settings.cw_gap             = 6;
+		}
+		if (sl_core_link_config_is_enable_ald_set(core_link))
+			core_link->pcs.settings.tx_gearbox_credits = 12;
+	}
+	if (SL_LGRP_CONFIG_TECH_CD_100G & link_caps->tech_map) {
+		core_link->pcs.settings.speed                      = SL_LGRP_CONFIG_TECH_CD_100G;
+		core_link->pcs.settings.pcs_mode                   = SL_CORE_HW_PCS_MODE_CD_100G;
+		core_link->pcs.settings.rx_active_lanes            = SL_CORE_HW_ACTIVE_LANES_CD_100G(core_link->num);
+		core_link->pcs.settings.rx_am_lock_lanes           = SL_CORE_HW_AM_LOCK_LANES_CD_100G(core_link->num);
+		core_link->pcs.settings.tx_cdc_ready_level         = 8;
+		core_link->pcs.settings.tx_en_pk_bw_limiter        = 1;
+		core_link->pcs.settings.tx_gearbox_credits         = 4;
+		core_link->pcs.settings.cw_gap                     = 6;
+	}
+	if (SL_LGRP_CONFIG_TECH_CD_50G & link_caps->tech_map) {
+		core_link->pcs.settings.speed                      = SL_LGRP_CONFIG_TECH_CD_50G;
+		core_link->pcs.settings.pcs_mode                   = SL_CORE_HW_PCS_MODE_CD_50G;
+		core_link->pcs.settings.rx_active_lanes            = SL_CORE_HW_ACTIVE_LANES_CD_50G(core_link->num);
+		core_link->pcs.settings.rx_am_lock_lanes           = SL_CORE_HW_AM_LOCK_LANES_CD_50G(core_link->num);
+		core_link->pcs.settings.tx_cdc_ready_level         = 8;
+		core_link->pcs.settings.tx_en_pk_bw_limiter        = 1;
+		core_link->pcs.settings.tx_gearbox_credits         = 2;
+		core_link->pcs.settings.cw_gap                     = 12;
+	}
+	if (SL_LGRP_CONFIG_TECH_BJ_100G & link_caps->tech_map) {
+		core_link->pcs.settings.speed                      = SL_LGRP_CONFIG_TECH_BJ_100G;
+		core_link->pcs.settings.pcs_mode                   = SL_CORE_HW_PCS_MODE_BJ_100G;
+		core_link->pcs.settings.rx_active_lanes            = SL_CORE_HW_ACTIVE_LANES_BJ_100G;
+		core_link->pcs.settings.rx_am_lock_lanes           = SL_CORE_HW_AM_LOCK_LANES_BJ_100G;
+		core_link->pcs.settings.tx_cdc_ready_level         = 8;
+		core_link->pcs.settings.tx_en_pk_bw_limiter        = 0;
+		core_link->pcs.settings.tx_gearbox_credits         = 8;
+		core_link->pcs.settings.cw_gap                     = 6;
+	}
+
+	if (is_flag_set(lgrp_config->options, SL_LGRP_CONFIG_OPT_FABRIC)) {
+		core_link->pcs.settings.mac_tx_credits = 8;
+	} else {
+		switch (lgrp_config->furcation) {
+		case SL_MEDIA_FURCATION_X1:
+			core_link->pcs.settings.mac_tx_credits = 8;
+			break;
+		case SL_MEDIA_FURCATION_X2:
+			core_link->pcs.settings.mac_tx_credits = 4;
+			break;
+		case SL_MEDIA_FURCATION_X4:
+			core_link->pcs.settings.mac_tx_credits = 2;
+			break;
+		}
+	}
+
+	switch (lgrp_config->furcation) {
+	case SL_MEDIA_FURCATION_X1:
+		core_link->pcs.settings.underrun_clr = 0;
+		break;
+	case SL_MEDIA_FURCATION_X2:
+		core_link->pcs.settings.underrun_clr = (~(3 << (core_link->num * 2)) & 0xF);
+		break;
+	case SL_MEDIA_FURCATION_X4:
+		core_link->pcs.settings.underrun_clr = (~(1 << core_link->num) & 0xF);
+		break;
+	}
+
+	/* FEC */
+	if (SL_LGRP_CONFIG_FEC_RS_LL & link_caps->fec_map) {
+		core_link->pcs.settings.rs_mode  = SL_CORE_HW_RS_MODE_CORRECT;
+		core_link->fec.settings.mode     = SL_LGRP_FEC_MODE_CORRECT;
+		core_link->fec.settings.type     = SL_LGRP_CONFIG_FEC_RS_LL;
+	} else if (SL_LGRP_CONFIG_FEC_RS & link_caps->fec_map) {
+		core_link->pcs.settings.rs_mode  = SL_CORE_HW_RS_MODE_CORRECT;
+		core_link->fec.settings.mode     = SL_LGRP_FEC_MODE_CORRECT;
+		core_link->fec.settings.type     = SL_LGRP_CONFIG_FEC_RS;
+	} else {
+		core_link->pcs.settings.rs_mode  = SL_CORE_HW_RS_MODE_OFF;
+		core_link->fec.settings.mode     = SL_LGRP_FEC_MODE_OFF;
+		core_link->fec.settings.type     = 0;
+	}
+
+	core_link->fec.settings.up_settle_wait_ms = (core_link->config.fec_up_settle_wait_ms < 0) ?
+		SL_CORE_HW_FEC_UP_SETTLE_WAIT_MS : core_link->config.fec_up_settle_wait_ms;
+	core_link->fec.settings.up_check_wait_ms  = (core_link->config.fec_up_check_wait_ms < 0) ?
+		SL_CORE_HW_FEC_UP_CHECK_WAIT_MS : core_link->config.fec_up_check_wait_ms;
+
+	if (core_link->config.fec_up_ucw_limit < 0) {
+		held_link_1 = sl_ctrl_link_get(core_link->core_lgrp->core_ldev->num,
+					       core_link->core_lgrp->num, core_link->num);
+		if (!held_link_1)
+			return -ENODEV;
+		core_link->fec.settings.up_ucw_limit =
+			sl_ctrl_link_fec_limit_calc(held_link_1,
+						    SL_CTRL_LINK_FEC_UCW_MANT,
+						    SL_CTRL_LINK_FEC_UCW_EXP);
+	} else {
+		core_link->fec.settings.up_ucw_limit = core_link->config.fec_up_ucw_limit;
+	}
+
+	if (core_link->config.fec_up_ccw_limit < 0)
+		core_link->fec.settings.up_ccw_limit = 0;
+	else
+		core_link->fec.settings.up_ccw_limit = core_link->config.fec_up_ccw_limit;
+
+	return 0;
+}
+
+void sl_core_data_link_timeouts(struct sl_core_link *core_link)
+{
+	sl_core_log_dbg(core_link, LOG_NAME, "timeouts");
+
+	if (core_link->config.link_up_timeout_ms == 0) {
+		sl_core_log_warn_trace(core_link, LOG_NAME,
+				       "timeouts - link up timeout is 0, setting to default");
+		core_link->timers[SL_CORE_TIMER_LINK_UP].data.timeout_ms = 10000;
+	} else {
+		core_link->timers[SL_CORE_TIMER_LINK_UP].data.timeout_ms = core_link->config.link_up_timeout_ms;
+	}
+
+	core_link->timers[SL_CORE_TIMER_LINK_UP_CHECK].data.timeout_ms = 100;
+
+	core_link->timers[SL_CORE_TIMER_LINK_UP_FEC_SETTLE].data.timeout_ms = core_link->fec.settings.up_settle_wait_ms;
+	core_link->timers[SL_CORE_TIMER_LINK_UP_FEC_CHECK].data.timeout_ms  = core_link->fec.settings.up_check_wait_ms;
+}
+
+void sl_core_data_link_state_set(struct sl_core_link *core_link,
+				 enum sl_core_link_state link_state)
+{
+	spin_lock(&core_link->link.data_lock);
+	core_link->link.state = link_state;
+	spin_unlock(&core_link->link.data_lock);
+
+	sl_media_jack_led_set(core_link->core_lgrp->core_ldev->num, core_link->core_lgrp->num);
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"set (link_state = %u %s)",
+			link_state, sl_core_link_state_str(link_state));
+}
+
+int sl_core_data_link_state_get(struct sl_core_link *core_link,
+				enum sl_core_link_state *link_state)
+{
+	spin_lock(&core_link->link.data_lock);
+	*link_state = core_link->link.state;
+	spin_unlock(&core_link->link.data_lock);
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"get (link_state = %u %s)",
+			*link_state, sl_core_link_state_str(*link_state));
+
+	return 0;
+}
+
+int sl_core_data_link_speed_get(struct sl_core_link *core_link, u32 *link_speed)
+{
+	u32 state;
+
+	spin_lock(&core_link->link.data_lock);
+	state       = core_link->link.state;
+	*link_speed = core_link->pcs.settings.speed;
+	spin_unlock(&core_link->link.data_lock);
+
+	if (state != SL_CORE_LINK_STATE_UP &&
+	    state != SL_CORE_LINK_STATE_GOING_DOWN) {
+		sl_core_log_warn_trace(core_link, LOG_NAME,
+				       "get speed no link (state = %u %s)",
+				       state, sl_core_link_state_str(state));
+		return -ENOLINK;
+	}
+
+	sl_core_log_dbg(core_link, LOG_NAME, "get speed = %u", *link_speed);
+
+	return 0;
+}
+
+u16 sl_core_data_link_clocking_get(struct sl_core_link *core_link)
+{
+	u16 link_clocking;
+
+	spin_lock(&core_link->link.data_lock);
+	link_clocking = core_link->serdes.core_serdes_settings.clocking;
+	spin_unlock(&core_link->link.data_lock);
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"get clocking = %u", link_clocking);
+
+	return link_clocking;
+}
+
+void sl_core_data_link_info_map_clr(struct sl_core_link *core_link, u32 bit_num)
+{
+	unsigned long irq_flags;
+
+	spin_lock_irqsave(&core_link->irq_data_lock, irq_flags);
+
+	if (bit_num == SL_CORE_INFO_MAP_NUM_BITS)
+		bitmap_zero((unsigned long *)&(core_link->info_map), SL_CORE_INFO_MAP_NUM_BITS);
+	else
+		clear_bit(bit_num, (unsigned long *)&(core_link->info_map));
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"clr info map 0x%016llX", core_link->info_map);
+
+	spin_unlock_irqrestore(&core_link->irq_data_lock, irq_flags);
+}
+
+void sl_core_data_link_info_map_set(struct sl_core_link *core_link, u32 bit_num)
+{
+	unsigned long irq_flags;
+
+	spin_lock_irqsave(&core_link->irq_data_lock, irq_flags);
+
+	set_bit(bit_num, (unsigned long *)&(core_link->info_map));
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"set info map 0x%016llX", core_link->info_map);
+
+	spin_unlock_irqrestore(&core_link->irq_data_lock, irq_flags);
+}
+
+u64 sl_core_data_link_info_map_get(struct sl_core_link *core_link)
+{
+	u64           info_map;
+	unsigned long irq_flags;
+
+	spin_lock_irqsave(&core_link->irq_data_lock, irq_flags);
+	info_map = core_link->info_map;
+	spin_unlock_irqrestore(&core_link->irq_data_lock, irq_flags);
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"get info map 0x%016llX", info_map);
+
+	return info_map;
+}
+
+void sl_core_data_link_is_last_down_new_set(struct sl_core_link *core_link, bool is_last_down_new)
+{
+	spin_lock(&core_link->link.data_lock);
+	core_link->link.is_last_down_new = is_last_down_new;
+	spin_unlock(&core_link->link.data_lock);
+}
+
+void sl_core_data_link_last_down_cause_map_set(struct sl_core_link *core_link, u64 down_cause_map)
+{
+	struct sl_ctrl_link *held_link_1 __free(sl_ctrl_link_put) = NULL;
+	spin_lock(&core_link->link.data_lock);
+
+	if (core_link->link.is_last_down_new) {
+		core_link->link.last_down_entry_num++;
+		if (core_link->link.last_down_entry_num >= SL_CTRL_LAST_DOWN_NUM_ENTRIES)
+			core_link->link.last_down_entry_num = 0;
+
+		core_link->link.last_down_cause_map[core_link->link.last_down_entry_num] = down_cause_map;
+		core_link->link.last_down_time[core_link->link.last_down_entry_num]      = ktime_get_real_seconds();
+
+		core_link->link.is_last_down_new = false;
+	} else {
+		core_link->link.last_down_cause_map[core_link->link.last_down_entry_num] |= down_cause_map;
+	}
+
+	spin_unlock(&core_link->link.data_lock);
+
+	held_link_1 = sl_ctrl_link_get(core_link->core_lgrp->core_ldev->num,
+				       core_link->core_lgrp->num, core_link->num);
+	if (!held_link_1)
+		return;
+	sl_ctrl_link_cause_counter_inc(held_link_1, down_cause_map);
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"last down cause map set (num = %u, down_cause_map = 0x%llX)",
+			core_link->link.last_down_entry_num, down_cause_map);
+}
+
+int sl_core_data_link_last_down_cause_map_info_get(struct sl_core_link *core_link,
+						   u8                   entry_num,
+						    u64                 *down_cause_map,
+						    time64_t            *down_time)
+{
+	u8 actual_entry_num;
+
+	spin_lock(&core_link->link.data_lock);
+
+	if (entry_num > core_link->link.last_down_entry_num)
+		actual_entry_num = SL_CTRL_LAST_DOWN_NUM_ENTRIES - (entry_num - core_link->link.last_down_entry_num);
+	else
+		actual_entry_num = core_link->link.last_down_entry_num - entry_num;
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"last down cause map info get (entry_num = %u, last_down_num = %u, actual_num = %u",
+			entry_num, core_link->link.last_down_entry_num, actual_entry_num);
+
+	*down_cause_map = core_link->link.last_down_cause_map[actual_entry_num];
+	*down_time      = core_link->link.last_down_time[actual_entry_num];
+
+	spin_unlock(&core_link->link.data_lock);
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"last down cause map info get (down_cause_map = 0x%llX, down_time = %lld %ptTt %ptTd)",
+			*down_cause_map, *down_time, down_time, down_time);
+
+	return 0;
+}
+
+u64 sl_core_data_link_last_down_cause_map_get(struct sl_core_link *core_link)
+{
+	u64 down_cause_map;
+
+	spin_lock(&core_link->link.data_lock);
+	down_cause_map = core_link->link.last_down_cause_map[core_link->link.last_down_entry_num];
+	spin_unlock(&core_link->link.data_lock);
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"last down cause map get (down_cause_map = 0x%llX)", down_cause_map);
+
+	return down_cause_map;
+}
+
+void sl_core_data_link_is_last_up_fail_new_set(struct sl_core_link *core_link, bool is_last_up_fail_new)
+{
+	spin_lock(&core_link->link.data_lock);
+	core_link->link.is_last_up_fail_new = is_last_up_fail_new;
+	spin_unlock(&core_link->link.data_lock);
+}
+
+void sl_core_data_link_last_up_fail_cause_map_set(struct sl_core_link *core_link, u64 up_fail_cause_map)
+{
+	struct sl_ctrl_link *held_link_1 __free(sl_ctrl_link_put) = NULL;
+	spin_lock(&core_link->link.data_lock);
+
+	if (core_link->link.is_last_up_fail_new) {
+		core_link->link.last_up_fail_entry_num++;
+		if (core_link->link.last_up_fail_entry_num >= SL_CTRL_LAST_UP_FAIL_NUM_ENTRIES)
+			core_link->link.last_up_fail_entry_num = 0;
+
+		core_link->link.last_up_fail_cause_map[core_link->link.last_up_fail_entry_num] = up_fail_cause_map;
+		core_link->link.last_up_fail_time[core_link->link.last_up_fail_entry_num]      = ktime_get_real_seconds();
+
+		core_link->link.is_last_up_fail_new = false;
+	} else {
+		core_link->link.last_up_fail_cause_map[core_link->link.last_up_fail_entry_num] |= up_fail_cause_map;
+	}
+
+	spin_unlock(&core_link->link.data_lock);
+
+	held_link_1 = sl_ctrl_link_get(core_link->core_lgrp->core_ldev->num,
+				       core_link->core_lgrp->num, core_link->num);
+	if (!held_link_1)
+		return;
+	sl_ctrl_link_cause_counter_inc(held_link_1, up_fail_cause_map);
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"last up_fail cause map set (num = %u, up_fail_cause_map = 0x%llX)",
+			core_link->link.last_up_fail_entry_num, up_fail_cause_map);
+}
+
+int sl_core_data_link_last_up_fail_cause_map_info_get(struct sl_core_link *core_link,
+						      u8                   entry_num,
+						       u64                 *up_fail_cause_map,
+						       time64_t            *up_fail_time)
+{
+	u8 actual_entry_num;
+
+	spin_lock(&core_link->link.data_lock);
+
+	if (entry_num > core_link->link.last_up_fail_entry_num)
+		actual_entry_num = SL_CTRL_LAST_UP_FAIL_NUM_ENTRIES - (entry_num - core_link->link.last_up_fail_entry_num);
+	else
+		actual_entry_num = core_link->link.last_up_fail_entry_num - entry_num;
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"last up_fail cause map info get (entry_num = %u, last_up_fail_num = %u, actual_num = %u",
+			entry_num, core_link->link.last_up_fail_entry_num, actual_entry_num);
+
+	*up_fail_cause_map = core_link->link.last_up_fail_cause_map[actual_entry_num];
+	*up_fail_time      = core_link->link.last_up_fail_time[actual_entry_num];
+
+	spin_unlock(&core_link->link.data_lock);
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"last up_fail cause map info get (up_fail_cause_map = 0x%llX, up_fail_time = %lld %ptTt %ptTd)",
+			*up_fail_cause_map, *up_fail_time, up_fail_time, up_fail_time);
+
+	return 0;
+}
+
+u64 sl_core_data_link_last_up_fail_cause_map_get(struct sl_core_link *core_link)
+{
+	u64 up_fail_cause_map;
+
+	spin_lock(&core_link->link.data_lock);
+	up_fail_cause_map = core_link->link.last_up_fail_cause_map[core_link->link.last_up_fail_entry_num];
+	spin_unlock(&core_link->link.data_lock);
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"last up_fail cause map get (up_fail_cause_map = 0x%llX)", up_fail_cause_map);
+
+	return up_fail_cause_map;
+}
+
+void sl_core_data_link_ccw_warn_limit_crossed_set(struct sl_core_link *core_link, bool is_limit_crossed)
+{
+	spin_lock(&core_link->link.data_lock);
+	core_link->link.is_ccw_warn_limit_crossed = is_limit_crossed;
+	core_link->link.last_ccw_warn_limit_crossed_time  = ktime_get_real_seconds();
+	spin_unlock(&core_link->link.data_lock);
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"ccw warn limit crossed set (is_limit_crossed = %d %s)", core_link->link.is_ccw_warn_limit_crossed,
+		core_link->link.is_ccw_warn_limit_crossed ? "yes" : "no");
+}
+
+int sl_core_data_link_ccw_warn_limit_crossed_get(struct sl_core_link *core_link, bool *is_limit_crossed,
+						 time64_t *limit_crossed_time)
+{
+	spin_lock(&core_link->link.data_lock);
+	*is_limit_crossed = core_link->link.is_ccw_warn_limit_crossed;
+	*limit_crossed_time = core_link->link.last_ccw_warn_limit_crossed_time;
+	spin_unlock(&core_link->link.data_lock);
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"ccw warn limit crossed get (is_limit_crossed = %d %s)", *is_limit_crossed,
+			*is_limit_crossed ? "yes" : "no");
+
+	return 0;
+}
+
+void sl_core_data_link_ucw_warn_limit_crossed_set(struct sl_core_link *core_link, bool is_limit_crossed)
+{
+	spin_lock(&core_link->link.data_lock);
+	core_link->link.is_ucw_warn_limit_crossed = is_limit_crossed;
+	core_link->link.last_ucw_warn_limit_crossed_time  = ktime_get_real_seconds();
+	spin_unlock(&core_link->link.data_lock);
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"ucw warn limit crossed set (is_limit_crossed = %d %s)", core_link->link.is_ucw_warn_limit_crossed,
+		core_link->link.is_ucw_warn_limit_crossed ? "yes" : "no");
+}
+
+int sl_core_data_link_ucw_warn_limit_crossed_get(struct sl_core_link *core_link, bool *is_limit_crossed,
+						 time64_t *limit_crossed_time)
+{
+	spin_lock(&core_link->link.data_lock);
+	*is_limit_crossed = core_link->link.is_ucw_warn_limit_crossed;
+	*limit_crossed_time = core_link->link.last_ucw_warn_limit_crossed_time;
+	spin_unlock(&core_link->link.data_lock);
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"ucw warn limit crossed get (is_limit_crossed = %d %s)", *is_limit_crossed,
+			*is_limit_crossed ? "yes" : "no");
+
+	return 0;
+}
+
+u32 sl_core_data_link_fec_mode_get(struct sl_core_link *core_link)
+{
+	u32 fec_mode;
+
+	spin_lock(&core_link->link.data_lock);
+	fec_mode = core_link->fec.settings.mode;
+	spin_unlock(&core_link->link.data_lock);
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"fec_mode get = %u %s", fec_mode, sl_lgrp_fec_mode_str(fec_mode));
+
+	return fec_mode;
+}
+
+u32 sl_core_data_link_fec_type_get(struct sl_core_link *core_link)
+{
+	u32 fec_type;
+
+	spin_lock(&core_link->link.data_lock);
+	fec_type = core_link->fec.settings.type;
+	spin_unlock(&core_link->link.data_lock);
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"fec_type get = %u %s", fec_type, sl_lgrp_config_fec_str(fec_type));
+
+	return fec_type;
+}
+
+u32 sl_core_data_link_an_lp_caps_state_get(struct sl_core_link *core_link)
+{
+	u32 lp_caps_state;
+
+	spin_lock(&core_link->an.data_lock);
+	lp_caps_state = core_link->an.lp_caps_state;
+	spin_unlock(&core_link->an.data_lock);
+
+	sl_core_log_dbg(core_link, LOG_NAME, "lp caps state get (lp_caps_state = %u %s)",
+			lp_caps_state, sl_link_an_lp_caps_state_str(lp_caps_state));
+
+	return lp_caps_state;
+}
+
+void sl_core_data_link_an_lp_caps_state_set(struct sl_core_link *core_link, u32 lp_caps_state)
+{
+	spin_lock(&core_link->an.data_lock);
+	core_link->an.lp_caps_state = lp_caps_state;
+	spin_unlock(&core_link->an.data_lock);
+
+	sl_core_log_dbg(core_link, LOG_NAME, "lp caps state set (lp_caps_state = %u %s)",
+			lp_caps_state, sl_link_an_lp_caps_state_str(lp_caps_state));
+}
+
+int sl_core_data_link_an_fail_cause_get(struct sl_core_link *core_link, u32 *fail_cause, time64_t *fail_time)
+{
+	unsigned long irq_flags;
+
+	spin_lock_irqsave(&core_link->irq_data_lock, irq_flags);
+	*fail_cause = core_link->an.fail_cause;
+	*fail_time  = core_link->an.fail_time;
+	spin_unlock_irqrestore(&core_link->irq_data_lock, irq_flags);
+
+	sl_core_log_dbg(core_link, LOG_NAME, "an fail cause get (fail_cause = %u %s)",
+			*fail_cause, sl_core_link_an_fail_cause_str(*fail_cause));
+
+	return 0;
+}
+
+void sl_core_data_link_an_fail_cause_set(struct sl_core_link *core_link, u32 fail_cause)
+{
+	struct sl_ctrl_link *held_link_1 __free(sl_ctrl_link_put) = NULL;
+	unsigned long irq_flags;
+
+	spin_lock_irqsave(&core_link->irq_data_lock, irq_flags);
+	core_link->an.fail_cause = fail_cause;
+	core_link->an.fail_time  = ktime_get_real_seconds();
+	spin_unlock_irqrestore(&core_link->irq_data_lock, irq_flags);
+
+	held_link_1 = sl_ctrl_link_get(core_link->core_lgrp->core_ldev->num,
+				       core_link->core_lgrp->num, core_link->num);
+	if (!held_link_1)
+		return;
+	sl_ctrl_link_an_cause_counter_inc(held_link_1,
+					  fail_cause);
+
+	sl_core_log_dbg(core_link, LOG_NAME, "an fail cause set (fail_cause = %u %s)",
+			fail_cause, sl_core_link_an_fail_cause_str(fail_cause));
+}
+
+u32 sl_core_data_link_an_retry_count_get(struct sl_core_link *core_link)
+{
+	u32 retry_count;
+
+	retry_count = atomic_read(&core_link->an.retry_count);
+
+	sl_core_log_dbg(core_link, LOG_NAME, "an retry count get (retry_count = %u)", retry_count);
+
+	return retry_count;
+}
+
+u32 sl_core_data_link_config_flags_get(struct sl_core_link *core_link)
+{
+	u32 flags;
+
+	spin_lock(&core_link->data_lock);
+	flags = core_link->config.flags;
+	spin_unlock(&core_link->data_lock);
+
+	sl_core_log_dbg(core_link, LOG_NAME, "config flags get (flags = 0x%X)", flags);
+
+	return flags;
+}
+
+static char *sl_core_link_degrade_state_str(int degrade_state)
+{
+	switch (degrade_state) {
+	case SL_LINK_DEGRADE_STATE_INVALID:
+		return "invalid";
+	case SL_LINK_DEGRADE_STATE_ACTIVE:
+		return "active";
+	case SL_LINK_DEGRADE_STATE_INACTIVE:
+		return "inactive";
+	case SL_LINK_DEGRADE_STATE_FAILED:
+		return "failed";
+	default:
+		return "unknown";
+	}
+}
+
+int sl_core_data_link_degrade_state_get(struct sl_core_link *core_link, int *degrade_state)
+{
+	spin_lock(&core_link->link.data_lock);
+	*degrade_state = core_link->degrade_state;
+	spin_unlock(&core_link->link.data_lock);
+
+	sl_core_log_dbg(core_link, LOG_NAME, "get (degrade_state = %d %s",
+			*degrade_state, sl_core_link_degrade_state_str(*degrade_state));
+
+	return 0;
+}
+
+int sl_core_data_link_is_rx_degrade_get(struct sl_core_link *core_link, bool *is_rx_degrade)
+{
+	spin_lock(&core_link->link.data_lock);
+	*is_rx_degrade = core_link->degrade_info.is_rx_degrade;
+	spin_unlock(&core_link->link.data_lock);
+
+	sl_core_log_dbg(core_link, LOG_NAME, "get (is_rx_degrade = %s)", *is_rx_degrade ? "yes" : "no");
+
+	return 0;
+}
+
+int sl_core_data_link_is_tx_degrade_get(struct sl_core_link *core_link, bool *is_tx_degrade)
+{
+	spin_lock(&core_link->link.data_lock);
+	*is_tx_degrade = core_link->degrade_info.is_tx_degrade;
+	spin_unlock(&core_link->link.data_lock);
+
+	sl_core_log_dbg(core_link, LOG_NAME, "get (is_tx_degrade = %s)", *is_tx_degrade ? "yes" : "no");
+
+	return 0;
+}
+
+int sl_core_data_link_degrade_tx_link_speed_get(struct sl_core_link *core_link, u16 *tx_link_speed)
+{
+	int degrade_state;
+
+	spin_lock(&core_link->link.data_lock);
+	*tx_link_speed = core_link->degrade_info.tx_link_speed;
+	degrade_state = core_link->degrade_state;
+	spin_unlock(&core_link->link.data_lock);
+
+	if (degrade_state != SL_LINK_DEGRADE_STATE_ACTIVE) {
+		sl_core_log_dbg(core_link, LOG_NAME, "get tx_link_speed failed (degrade_state = %d %s)",
+				degrade_state, sl_core_link_degrade_state_str(degrade_state));
+		return -EBADRQC;
+	}
+
+	sl_core_log_dbg(core_link, LOG_NAME, "get (tx_link_speed = %u)", *tx_link_speed);
+
+	return 0;
+}
+
+int sl_core_data_link_degrade_rx_link_speed_get(struct sl_core_link *core_link, u16 *rx_link_speed)
+{
+	int degrade_state;
+
+	spin_lock(&core_link->link.data_lock);
+	*rx_link_speed = core_link->degrade_info.rx_link_speed;
+	degrade_state = core_link->degrade_state;
+	spin_unlock(&core_link->link.data_lock);
+
+	if (degrade_state != SL_LINK_DEGRADE_STATE_ACTIVE) {
+		sl_core_log_dbg(core_link, LOG_NAME, "get rx_link_speed failed (degrade_state = %d %s)",
+				degrade_state, sl_core_link_degrade_state_str(degrade_state));
+		return -EBADRQC;
+	}
+
+	sl_core_log_dbg(core_link, LOG_NAME, "get (rx_link_speed = %u)", *rx_link_speed);
+
+	return 0;
+}
+
+int sl_core_data_link_degrade_tx_degrade_map_get(struct sl_core_link *core_link, u8 *tx_degrade_map)
+{
+	int degrade_state;
+
+	spin_lock(&core_link->link.data_lock);
+	*tx_degrade_map = core_link->degrade_info.tx_degrade_map;
+	degrade_state = core_link->degrade_state;
+	spin_unlock(&core_link->link.data_lock);
+
+	if (degrade_state != SL_LINK_DEGRADE_STATE_ACTIVE) {
+		sl_core_log_dbg(core_link, LOG_NAME, "get tx_degrade_map failed (degrade_state = %d %s)",
+				degrade_state, sl_core_link_degrade_state_str(degrade_state));
+		return -EBADRQC;
+	}
+
+	sl_core_log_dbg(core_link, LOG_NAME, "get (tx_degrade_map = 0x%02X)", *tx_degrade_map);
+
+	return 0;
+}
+
+int sl_core_data_link_degrade_rx_degrade_map_get(struct sl_core_link *core_link, u8 *rx_degrade_map)
+{
+	int degrade_state;
+
+	spin_lock(&core_link->link.data_lock);
+	*rx_degrade_map = core_link->degrade_info.rx_degrade_map;
+	degrade_state = core_link->degrade_state;
+	spin_unlock(&core_link->link.data_lock);
+
+	if (degrade_state != SL_LINK_DEGRADE_STATE_ACTIVE) {
+		sl_core_log_dbg(core_link, LOG_NAME, "get rx_degrade_map failed (degrade_state = %d %s)",
+				degrade_state, sl_core_link_degrade_state_str(degrade_state));
+		return -EBADRQC;
+	}
+
+	sl_core_log_dbg(core_link, LOG_NAME, "get (rx_degrade_map = 0x%02X)", *rx_degrade_map);
+
+	return 0;
+}
+
+int sl_core_data_link_degrade_is_recoverable_get(struct sl_core_link *core_link, bool *is_recoverable)
+{
+	int degrade_state;
+
+	spin_lock(&core_link->link.data_lock);
+	*is_recoverable = core_link->degrade_info.is_recoverable;
+	degrade_state = core_link->degrade_state;
+	spin_unlock(&core_link->link.data_lock);
+
+	if (degrade_state != SL_LINK_DEGRADE_STATE_ACTIVE) {
+		sl_core_log_dbg(core_link, LOG_NAME, "get is_recoverable failed (degrade_state = %d %s)",
+				degrade_state, sl_core_link_degrade_state_str(degrade_state));
+		return -EBADRQC;
+	}
+
+	sl_core_log_dbg(core_link, LOG_NAME, "get (is_recoverable = %u)", *is_recoverable);
+
+	return 0;
+}
+
+int sl_core_data_link_pml_rec_attempts_get(struct sl_core_link *core_link, int *attempts)
+{
+	*attempts = atomic_read(&core_link->pml_rec.pml_rec_info.pml_rec_counters[SL_LINK_PML_REC_ATTEMPTS]);
+
+	return 0;
+}
+
+int sl_core_data_link_pml_rec_successes_get(struct sl_core_link *core_link, int *successes)
+{
+	*successes = atomic_read(&core_link->pml_rec.pml_rec_info.pml_rec_counters[SL_LINK_PML_REC_SUCCESSES]);
+
+	return 0;
+}
+
+int sl_core_data_link_pml_rec_link_fault_cause_get(struct sl_core_link *core_link, int *fault_cause)
+{
+	*fault_cause = atomic_read(&core_link->pml_rec.pml_rec_info.pml_rec_counters[SL_LINK_PML_REC_LINK_LOCAL_FAULT_CAUSE]);
+
+	return 0;
+}
+
+int sl_core_data_link_pml_rec_link_down_cause_get(struct sl_core_link *core_link, int *down_cause)
+{
+	*down_cause = atomic_read(&core_link->pml_rec.pml_rec_info.pml_rec_counters[SL_LINK_PML_REC_LINK_DOWN_CAUSE]);
+
+	return 0;
+}
+
+int sl_core_data_link_pml_rec_link_fault_failed_cause_get(struct sl_core_link *core_link, int *fault_failed_cause)
+{
+	*fault_failed_cause = atomic_read(&core_link->pml_rec.pml_rec_info.pml_rec_counters[SL_LINK_PML_REC_LINK_LOCAL_FAULT_FAILED_CAUSE]);
+
+	return 0;
+}
+
+int sl_core_data_link_pml_rec_link_down_failed_cause_get(struct sl_core_link *core_link, int *down_failed_cause)
+{
+	*down_failed_cause = atomic_read(&core_link->pml_rec.pml_rec_info.pml_rec_counters[SL_LINK_PML_REC_LINK_DOWN_FAILED_CAUSE]);
+
+	return 0;
+}
+
+int sl_core_data_link_pml_rec_rate_limit_exceeded_get(struct sl_core_link *core_link, int *rate_limit_exceeded)
+{
+	*rate_limit_exceeded = atomic_read(&core_link->pml_rec.pml_rec_info.pml_rec_counters[SL_LINK_PML_REC_RATE_LIMIT_EXCEEDED]);
+
+	return 0;
+}
+
+int sl_core_data_link_fec_up_settle_wait_ms_get(struct sl_core_link *core_link, u32 *fec_settle_wait_ms)
+{
+	spin_lock(&core_link->link.data_lock);
+	*fec_settle_wait_ms = core_link->fec.settings.up_settle_wait_ms;
+	spin_unlock(&core_link->link.data_lock);
+
+	sl_core_log_dbg(core_link, LOG_NAME, "get (fec_settle_wait_ms = %u)", *fec_settle_wait_ms);
+
+	return 0;
+}
+
+int sl_core_data_link_fec_up_check_wait_ms_get(struct sl_core_link *core_link, u32 *fec_check_wait_ms)
+{
+	spin_lock(&core_link->link.data_lock);
+	*fec_check_wait_ms = core_link->fec.settings.up_check_wait_ms;
+	spin_unlock(&core_link->link.data_lock);
+
+	sl_core_log_dbg(core_link, LOG_NAME, "get (fec_check_wait_ms = %u)", *fec_check_wait_ms);
+
+	return 0;
+}
+
+int sl_core_data_link_fec_up_ucw_limit_get(struct sl_core_link *core_link, s32 *fec_up_ucw_limit)
+{
+	spin_lock(&core_link->link.data_lock);
+	*fec_up_ucw_limit = core_link->fec.settings.up_ucw_limit;
+	spin_unlock(&core_link->link.data_lock);
+
+	sl_core_log_dbg(core_link, LOG_NAME, "get (fec_up_ucw_limit = %d)", *fec_up_ucw_limit);
+
+	return 0;
+}
+
+int sl_core_data_link_fec_up_ccw_limit_get(struct sl_core_link *core_link, s32 *fec_up_ccw_limit)
+{
+	spin_lock(&core_link->link.data_lock);
+	*fec_up_ccw_limit = core_link->fec.settings.up_ccw_limit;
+	spin_unlock(&core_link->link.data_lock);
+
+	sl_core_log_dbg(core_link, LOG_NAME, "get (fec_up_ccw_limit = %d)", *fec_up_ccw_limit);
+
+	return 0;
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/data/sl_core_data_llr.c b/drivers/net/ethernet/hpe/sl/core/data/sl_core_data_llr.c
new file mode 100644
index 000000000000..7ab3ca4a9f64
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/data/sl_core_data_llr.c
@@ -0,0 +1,526 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2022,2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/workqueue.h>
+
+#include <linux/hpe/sl/sl_lgrp.h>
+#include <linux/hpe/sl/sl_media.h>
+
+#include "base/sl_core_log.h"
+#include "sl_core_lgrp.h"
+#include "sl_core_llr.h"
+#include "sl_core_str.h"
+#include "hw/sl_core_hw_llr.h"
+#include "hw/sl_core_hw_intr_llr.h"
+#include "sl_core_hw_intr_flgs_llr.h"
+#include "data/sl_core_data_llr.h"
+#include "sl_ctrl_llr_counters.h"
+
+static struct sl_core_llr *core_llrs[SL_ASIC_MAX_LDEVS][SL_ASIC_MAX_LGRPS][SL_ASIC_MAX_LINKS];
+static DEFINE_SPINLOCK(core_llrs_lock);
+
+#define LOG_NAME SL_CORE_DATA_LLR_LOG_NAME
+
+#define SL_CORE_TIMER_LLR_INIT(_llr, _timer_num, _work_num, _log)        \
+	do {                                                             \
+		(_llr)->timers[_timer_num].data.core_llr   = _llr;       \
+		(_llr)->timers[_timer_num].data.timer_num  = _timer_num; \
+		(_llr)->timers[_timer_num].data.work_num   = _work_num;  \
+		strscpy_pad((_llr)->timers[_timer_num].data.log, _log,  \
+			sizeof((_llr)->timers[_timer_num].data.log));    \
+	} while (0)
+#define SL_CORE_INTR_LLR_INIT(_llr, _intr_num, _work_num, _log)           \
+	do {                                                              \
+		(_llr)->intrs[_intr_num].flgs =                           \
+			sl_core_hw_intr_flgs_llr[_intr_num][(_llr)->num]; \
+		(_llr)->intrs[_intr_num].data.core_llr = _llr;            \
+		(_llr)->intrs[_intr_num].data.intr_num = _intr_num;       \
+		(_llr)->intrs[_intr_num].data.work_num = _work_num;       \
+		strscpy_pad((_llr)->intrs[_intr_num].data.log, _log,     \
+			sizeof((_llr)->intrs[_intr_num].data.log));       \
+	} while (0)
+
+int sl_core_data_llr_new(u8 ldev_num, u8 lgrp_num, u8 llr_num)
+{
+	int                 rtn;
+	struct sl_core_llr *core_llr;
+
+	core_llr = sl_core_data_llr_get(ldev_num, lgrp_num, llr_num);
+	if (core_llr) {
+		sl_core_log_err(NULL, LOG_NAME, "exists (llr = 0x%p)", core_llr);
+		return -EBADRQC;
+	}
+
+	core_llr = kzalloc(sizeof(struct sl_core_llr), GFP_KERNEL);
+	if (!core_llr)
+		return -ENOMEM;
+
+	core_llr->magic               = SL_CORE_LLR_MAGIC;
+	core_llr->num                 = llr_num;
+	core_llr->core_lgrp           = sl_core_lgrp_get(ldev_num, lgrp_num);
+	if (!core_llr->core_lgrp) {
+		kfree(core_llr);
+		return -ENODEV;
+	}
+	core_llr->last_fail_cause     = SL_LLR_FAIL_CAUSE_NONE;
+
+	spin_lock_init(&core_llr->data_lock);
+
+	sl_core_hw_llr_stop(core_llr);
+	sl_core_data_llr_state_set(core_llr, SL_CORE_LLR_STATE_NEW);
+	init_completion(&core_llr->stop_complete);
+
+	timer_setup(&(core_llr->timers[SL_CORE_TIMER_LLR_SETUP].timer),
+		    sl_core_timer_llr_timeout, 0);
+	SL_CORE_TIMER_LLR_INIT(core_llr, SL_CORE_TIMER_LLR_SETUP,
+			       SL_CORE_WORK_LLR_SETUP_TIMEOUT, "llr setup");
+	timer_setup(&(core_llr->timers[SL_CORE_TIMER_LLR_START].timer),
+		    sl_core_timer_llr_timeout, 0);
+	SL_CORE_TIMER_LLR_INIT(core_llr, SL_CORE_TIMER_LLR_START,
+			       SL_CORE_WORK_LLR_START_TIMEOUT, "llr start");
+
+	INIT_WORK(&(core_llr->work[SL_CORE_WORK_LLR_SETUP]),
+		  sl_core_hw_llr_setup_work);
+	INIT_WORK(&(core_llr->work[SL_CORE_WORK_LLR_SETUP_TIMEOUT]),
+		  sl_core_hw_llr_setup_timeout_work);
+	INIT_WORK(&(core_llr->work[SL_CORE_WORK_LLR_SETUP_UNEXP_LOOP_TIME_INTR]),
+		  sl_core_hw_llr_setup_unexp_loop_time_intr_work);
+	INIT_WORK(&(core_llr->work[SL_CORE_WORK_LLR_SETUP_LOOP_TIME_INTR]),
+		  sl_core_hw_llr_setup_loop_time_intr_work);
+	INIT_WORK(&(core_llr->work[SL_CORE_WORK_LLR_START]),
+		  sl_core_hw_llr_start_work);
+	INIT_WORK(&(core_llr->work[SL_CORE_WORK_LLR_START_TIMEOUT]),
+		  sl_core_hw_llr_start_timeout_work);
+	INIT_WORK(&(core_llr->work[SL_CORE_WORK_LLR_START_INIT_COMPLETE_INTR]),
+		  sl_core_hw_llr_start_init_complete_intr_work);
+
+	SL_CORE_INTR_LLR_INIT(core_llr, SL_CORE_HW_INTR_LLR_SETUP_UNEXP_LOOP_TIME,
+			      SL_CORE_WORK_LLR_SETUP_UNEXP_LOOP_TIME_INTR, "llr setup unexp loop time");
+	SL_CORE_INTR_LLR_INIT(core_llr, SL_CORE_HW_INTR_LLR_SETUP_LOOP_TIME,
+			      SL_CORE_WORK_LLR_SETUP_LOOP_TIME_INTR, "llr setup loop time");
+	SL_CORE_INTR_LLR_INIT(core_llr, SL_CORE_HW_INTR_LLR_START_INIT_COMPLETE,
+			      SL_CORE_WORK_LLR_START_INIT_COMPLETE_INTR, "llr start init complete");
+
+	rtn = sl_core_hw_intr_llr_hdlr_register(core_llr);
+	if (rtn != 0) {
+		sl_core_log_err(core_llr, LOG_NAME,
+				"core_hw_intr_llr_hdlr_register failed [%d]", rtn);
+		sl_core_lgrp_put(core_llr->core_lgrp);
+		kfree(core_llr);
+		return rtn;
+	}
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "new (llr = 0x%p)", core_llr);
+
+	spin_lock(&core_llrs_lock);
+	core_llrs[ldev_num][lgrp_num][llr_num] = core_llr;
+	spin_unlock(&core_llrs_lock);
+
+	return 0;
+}
+
+void sl_core_data_llr_del(u8 ldev_num, u8 lgrp_num, u8 llr_num)
+{
+	struct sl_core_llr *core_llr;
+
+	core_llr = sl_core_llr_get(ldev_num, lgrp_num, llr_num);
+	if (!core_llr) {
+		sl_core_log_err(NULL, LOG_NAME, "not found (llr_num = %u)", llr_num);
+		return;
+	}
+
+	spin_lock(&core_llrs_lock);
+	core_llrs[ldev_num][lgrp_num][llr_num] = NULL;
+	spin_unlock(&core_llrs_lock);
+
+	sl_core_timer_llr_end(core_llr, SL_CORE_TIMER_LLR_SETUP);
+	sl_core_timer_llr_end(core_llr, SL_CORE_TIMER_LLR_START);
+
+	cancel_work_sync(&(core_llr->work[SL_CORE_WORK_LLR_SETUP]));
+	cancel_work_sync(&(core_llr->work[SL_CORE_WORK_LLR_SETUP_TIMEOUT]));
+	cancel_work_sync(&(core_llr->work[SL_CORE_WORK_LLR_START]));
+	cancel_work_sync(&(core_llr->work[SL_CORE_WORK_LLR_START_TIMEOUT]));
+
+	sl_core_hw_intr_llr_flgs_disable(core_llr, SL_CORE_HW_INTR_LLR_SETUP_UNEXP_LOOP_TIME);
+	sl_core_hw_intr_llr_flgs_disable(core_llr, SL_CORE_HW_INTR_LLR_SETUP_LOOP_TIME);
+	sl_core_hw_intr_llr_flgs_disable(core_llr, SL_CORE_HW_INTR_LLR_START_INIT_COMPLETE);
+
+	cancel_work_sync(&(core_llr->work[SL_CORE_WORK_LLR_SETUP_UNEXP_LOOP_TIME_INTR]));
+	cancel_work_sync(&(core_llr->work[SL_CORE_WORK_LLR_SETUP_LOOP_TIME_INTR]));
+	cancel_work_sync(&(core_llr->work[SL_CORE_WORK_LLR_START_INIT_COMPLETE_INTR]));
+
+	sl_core_hw_intr_llr_hdlr_unregister(core_llr);
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "del (llr = 0x%p)", core_llr);
+
+	sl_core_lgrp_put(core_llr->core_lgrp);
+	kfree(core_llr);
+}
+
+struct sl_core_llr *sl_core_data_llr_get(u8 ldev_num, u8 lgrp_num, u8 llr_num)
+{
+	struct sl_core_llr *core_llr;
+
+	spin_lock(&core_llrs_lock);
+	core_llr = core_llrs[ldev_num][lgrp_num][llr_num];
+	spin_unlock(&core_llrs_lock);
+
+	sl_core_log_dbg(NULL, LOG_NAME,
+			"get (ldev_num = %u, lgrp_num = %u, llr_num = %u, llr = 0x%p)",
+			ldev_num, lgrp_num, llr_num, core_llr);
+
+	return core_llr;
+}
+
+#define SL_CORE_DATA_LLR_CONFIG_SETUP_TIMEOUT_MS     3000
+#define SL_CORE_DATA_LLR_CONFIG_SETUP_TIMEOUT_MAX_MS 180000
+#define SL_CORE_DATA_LLR_CONFIG_START_TIMEOUT_MS     3000
+#define SL_CORE_DATA_LLR_CONFIG_START_TIMEOUT_MAX_MS 180000
+int sl_core_data_llr_config_set(struct sl_core_llr *core_llr, struct sl_llr_config *llr_config)
+{
+	core_llr->settings.size              = 1;
+	core_llr->settings.lossless_when_off = 1;
+
+	switch (llr_config->link_dn_behavior) {
+	default:
+	case SL_LLR_LINK_DN_BEHAVIOR_DISCARD:
+		core_llr->settings.link_down_behavior = SS2_PORT_PML_LINK_DN_BEHAVIOR_T_LD_DISCARD;
+		break;
+	case SL_LLR_LINK_DN_BEHAVIOR_BLOCK:
+		core_llr->settings.link_down_behavior = SS2_PORT_PML_LINK_DN_BEHAVIOR_T_LD_BLOCK;
+		break;
+	case SL_LLR_LINK_DN_BEHAVIOR_BEST_EFFORT:
+		core_llr->settings.link_down_behavior = SS2_PORT_PML_LINK_DN_BEHAVIOR_T_LD_BEST_EFFORT;
+		break;
+	}
+
+	core_llr->settings.filter_ctl_frames   = 1;
+	core_llr->settings.ctl_frame_smac      = 0;
+	core_llr->settings.ctl_frame_ethertype = 0x88B6;
+	core_llr->settings.retry_threshold     = 2;
+	core_llr->settings.allow_re_init       = 0;
+	core_llr->settings.replay_ct_max       = 0xFF;
+	core_llr->settings.replay_timer_max    = 15500;
+
+	if ((llr_config->setup_timeout_ms <= 0) ||
+	    (llr_config->setup_timeout_ms > SL_CORE_DATA_LLR_CONFIG_SETUP_TIMEOUT_MAX_MS)) {
+		sl_core_log_warn_trace(core_llr, LOG_NAME,
+				       "config set setting setup timeout to default (%ums)",
+			SL_CORE_DATA_LLR_CONFIG_SETUP_TIMEOUT_MS);
+		core_llr->timers[SL_CORE_TIMER_LLR_SETUP].data.timeout_ms = SL_CORE_DATA_LLR_CONFIG_SETUP_TIMEOUT_MS;
+	} else {
+		core_llr->timers[SL_CORE_TIMER_LLR_SETUP].data.timeout_ms = llr_config->setup_timeout_ms;
+	}
+	if ((llr_config->start_timeout_ms <= 0) ||
+	    (llr_config->start_timeout_ms > SL_CORE_DATA_LLR_CONFIG_START_TIMEOUT_MAX_MS)) {
+		sl_core_log_warn_trace(core_llr, LOG_NAME,
+				       "config set setting start timeout to default (%ums)",
+			SL_CORE_DATA_LLR_CONFIG_START_TIMEOUT_MS);
+		core_llr->timers[SL_CORE_TIMER_LLR_START].data.timeout_ms = SL_CORE_DATA_LLR_CONFIG_START_TIMEOUT_MS;
+	} else {
+		core_llr->timers[SL_CORE_TIMER_LLR_START].data.timeout_ms = llr_config->start_timeout_ms;
+	}
+
+	sl_core_log_dbg(core_llr, LOG_NAME,
+			"config set settings (link_dn_behavior %u %s = %u)",
+		llr_config->link_dn_behavior, sl_llr_link_dn_behavior_str(llr_config->link_dn_behavior),
+		core_llr->settings.link_down_behavior);
+
+	return 0;
+}
+
+int sl_core_data_llr_policy_set(struct sl_core_llr *core_llr, struct sl_llr_policy *llr_policy)
+{
+	sl_core_log_dbg(core_llr, LOG_NAME, "policy set");
+
+	spin_lock(&core_llr->data_lock);
+	core_llr->policy = *llr_policy;
+	spin_unlock(&core_llr->data_lock);
+
+	return 0;
+}
+
+int sl_core_data_llr_policy_get(struct sl_core_llr *core_llr, struct sl_llr_policy *llr_policy)
+{
+	sl_core_log_dbg(core_llr, LOG_NAME, "policy get");
+
+	spin_lock(&core_llr->data_lock);
+	*llr_policy = core_llr->policy;
+	spin_unlock(&core_llr->data_lock);
+
+	return 0;
+}
+
+int sl_core_data_llr_settings(struct sl_core_llr *core_llr)
+{
+	struct sl_lgrp_config *lgrp_config;
+	struct sl_link_caps   *link_caps;
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "settings");
+
+	sl_core_data_llr_last_fail_cause_set(core_llr, SL_LLR_FAIL_CAUSE_NONE);
+
+	lgrp_config = &(core_llr->core_lgrp->config);
+	link_caps   = &(core_llr->core_lgrp->link_caps[core_llr->num]);
+
+	if (hweight_long(link_caps->tech_map) != 1) {
+		sl_core_log_err_trace(core_llr, LOG_NAME,
+				      "settings - tech map invalid (map = 0x%08X)",
+			link_caps->tech_map);
+		sl_core_data_llr_last_fail_cause_set(core_llr, SL_LLR_FAIL_CAUSE_SETUP_CONFIG);
+		return -EINVAL;
+	}
+
+	if (SL_LGRP_CONFIG_TECH_CK_400G & link_caps->tech_map)
+		core_llr->settings.bytes_per_ns = 50;
+	if (SL_LGRP_CONFIG_TECH_CK_200G & link_caps->tech_map)
+		core_llr->settings.bytes_per_ns = 25;
+	if (SL_LGRP_CONFIG_TECH_CK_100G & link_caps->tech_map)
+		core_llr->settings.bytes_per_ns = 13;
+	if (SL_LGRP_CONFIG_TECH_BS_200G & link_caps->tech_map)
+		core_llr->settings.bytes_per_ns = 25;
+	if (SL_LGRP_CONFIG_TECH_CD_100G & link_caps->tech_map)
+		core_llr->settings.bytes_per_ns = 13;
+	if (SL_LGRP_CONFIG_TECH_CD_50G  & link_caps->tech_map)
+		core_llr->settings.bytes_per_ns = 7;
+	if (SL_LGRP_CONFIG_TECH_BJ_100G & link_caps->tech_map)
+		core_llr->settings.bytes_per_ns = 13;
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "settings (bytes = %u)", core_llr->settings.bytes_per_ns);
+
+	if (is_flag_set(lgrp_config->options, SL_LGRP_CONFIG_OPT_FABRIC)) {
+		core_llr->settings.max_cap_data   = 0x800ULL;
+		core_llr->settings.max_cap_seq    = 0x800ULL;
+	} else {
+		switch (lgrp_config->furcation) {
+		case SL_MEDIA_FURCATION_X1:
+			core_llr->settings.max_cap_data   = 0x800ULL;
+			core_llr->settings.max_cap_seq    = 0x800ULL;
+			break;
+		case SL_MEDIA_FURCATION_X2:
+			core_llr->settings.max_cap_data   = 0x400ULL;
+			core_llr->settings.max_cap_seq    = 0x400ULL;
+			break;
+		case SL_MEDIA_FURCATION_X4:
+			core_llr->settings.max_cap_data   = 0x200ULL;
+			core_llr->settings.max_cap_seq    = 0x200ULL;
+			break;
+		}
+	}
+
+	return 0;
+}
+
+void sl_core_data_llr_state_set(struct sl_core_llr *core_llr,
+				enum sl_core_llr_state llr_state)
+{
+	spin_lock(&core_llr->data_lock);
+	core_llr->state = llr_state;
+	spin_unlock(&core_llr->data_lock);
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "set (llr_state = %u %s)",
+			llr_state, sl_core_llr_state_str(llr_state));
+}
+
+int sl_core_data_llr_state_get(struct sl_core_llr *core_llr,
+			       enum sl_core_llr_state *llr_state)
+{
+	spin_lock(&core_llr->data_lock);
+	*llr_state = core_llr->state;
+	spin_unlock(&core_llr->data_lock);
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "get (llr_state = %u %s)",
+			*llr_state, sl_core_llr_state_str(*llr_state));
+
+	return 0;
+}
+
+void sl_core_data_llr_data_set(struct sl_core_llr *core_llr, struct sl_llr_data llr_data)
+{
+	spin_lock(&core_llr->data_lock);
+	core_llr->is_data_valid = true;
+	core_llr->data          = llr_data;
+	core_llr->data.magic    = SL_CORE_LLR_DATA_MAGIC;
+	spin_unlock(&core_llr->data_lock);
+
+	sl_core_log_dbg(core_llr, LOG_NAME,
+			"data set (min = %lldns, max = %lldns, average = %lldns, calc = %lldns)",
+		llr_data.loop.min, llr_data.loop.max,
+		llr_data.loop.average, llr_data.loop.calculated);
+}
+
+struct sl_llr_data sl_core_data_llr_data_get(struct sl_core_llr *core_llr)
+{
+	struct sl_llr_data llr_data;
+
+	spin_lock(&core_llr->data_lock);
+	llr_data = core_llr->data;
+	spin_unlock(&core_llr->data_lock);
+
+	sl_core_log_dbg(core_llr, LOG_NAME,
+			"data get (min = %lluns, max = %lluns, average = %lluns, calc = %lluns)",
+		llr_data.loop.min, llr_data.loop.max,
+		llr_data.loop.average, llr_data.loop.calculated);
+
+	return llr_data;
+}
+
+void sl_core_data_llr_data_clr(struct sl_core_llr *core_llr)
+{
+	sl_core_log_dbg(core_llr, LOG_NAME, "data clear");
+
+	spin_lock(&core_llr->data_lock);
+	core_llr->is_data_valid = false;
+	memset(&(core_llr->data), 0, sizeof(core_llr->data));
+	spin_unlock(&core_llr->data_lock);
+}
+
+bool sl_core_data_llr_data_is_valid(struct sl_core_llr *core_llr)
+{
+	bool is_valid;
+
+	spin_lock(&core_llr->data_lock);
+	is_valid = core_llr->is_data_valid;
+	spin_unlock(&core_llr->data_lock);
+
+	return is_valid;
+}
+
+void sl_core_data_llr_info_map_clr(struct sl_core_llr *core_llr, u32 bit_num)
+{
+	spin_lock(&core_llr->data_lock);
+
+	if (bit_num == SL_CORE_INFO_MAP_NUM_BITS)
+		bitmap_zero((unsigned long *)&(core_llr->info_map), SL_CORE_INFO_MAP_NUM_BITS);
+	else
+		clear_bit(bit_num, (unsigned long *)&(core_llr->info_map));
+
+	sl_core_log_dbg(core_llr, LOG_NAME,
+			"clr info map 0x%016llX", core_llr->info_map);
+
+	spin_unlock(&core_llr->data_lock);
+}
+
+void sl_core_data_llr_info_map_set(struct sl_core_llr *core_llr, u32 bit_num)
+{
+	spin_lock(&core_llr->data_lock);
+	set_bit(bit_num, (unsigned long *)&(core_llr->info_map));
+
+	sl_core_log_dbg(core_llr, LOG_NAME,
+			"set info map 0x%016llX", core_llr->info_map);
+
+	spin_unlock(&core_llr->data_lock);
+}
+
+int sl_core_data_llr_info_map_get(struct sl_core_llr *core_llr, u64 *info_map)
+{
+	spin_lock(&core_llr->data_lock);
+	*info_map = core_llr->info_map;
+	spin_unlock(&core_llr->data_lock);
+
+	sl_core_log_dbg(core_llr, LOG_NAME,
+			"get (info_map = 0x%016llX)", *info_map);
+
+	return 0;
+}
+
+int sl_core_data_llr_last_fail_cause_get(struct sl_core_llr *core_llr, u32 *llr_fail_cause,
+					 time64_t *llr_fail_time)
+{
+	spin_lock(&core_llr->data_lock);
+	*llr_fail_cause = core_llr->last_fail_cause;
+	*llr_fail_time  = core_llr->last_fail_time;
+	spin_unlock(&core_llr->data_lock);
+
+	sl_core_log_dbg(core_llr, LOG_NAME,
+			"last llr fail cause get (cause = %u %s)", *llr_fail_cause,
+		sl_core_llr_fail_cause_str(*llr_fail_cause));
+
+	return 0;
+}
+
+void sl_core_data_llr_last_fail_cause_set(struct sl_core_llr *core_llr, u32 llr_fail_cause)
+{
+	spin_lock(&core_llr->data_lock);
+	core_llr->last_fail_cause = llr_fail_cause;
+	core_llr->last_fail_time  = ktime_get_real_seconds();
+	spin_unlock(&core_llr->data_lock);
+
+	sl_ctrl_llr_cause_counter_inc(core_llr, llr_fail_cause);
+
+	sl_core_log_dbg(core_llr, LOG_NAME,
+			"last llr fail cause set (cause = %u %s)", llr_fail_cause, sl_core_llr_fail_cause_str(llr_fail_cause));
+}
+
+int sl_core_data_llr_policy_options_get(struct sl_core_llr *core_llr, u32 *options)
+{
+	spin_lock(&core_llr->data_lock);
+	*options = core_llr->policy.options;
+	spin_unlock(&core_llr->data_lock);
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "get (options = 0x%X)", *options);
+
+	return 0;
+}
+
+int sl_core_data_llr_loop_time_get(struct sl_core_llr *core_llr, u64 *loop_time)
+{
+	spin_lock(&core_llr->data_lock);
+	memcpy(loop_time, core_llr->loop_time, sizeof(core_llr->loop_time));
+	spin_unlock(&core_llr->data_lock);
+
+	sl_core_log_dbg(core_llr, LOG_NAME,
+			"get (loop time 0 = %lluns, 1 = %lluns, 2 = %lluns, 3 = %lluns, 4 = %lluns, "
+			"5 = %lluns, 6 = %lluns, 7 = %lluns, 8 = %lluns, 9 = %lluns)",
+			loop_time[0], loop_time[1], loop_time[2], loop_time[3], loop_time[4],
+			loop_time[5], loop_time[6], loop_time[7], loop_time[8], loop_time[9]);
+
+	return 0;
+}
+
+int sl_core_data_llr_loop_calculated_ns_get(struct sl_core_llr *core_llr, u64 *calculated_ns)
+{
+	spin_lock(&core_llr->data_lock);
+	*calculated_ns = core_llr->data.loop.calculated;
+	spin_unlock(&core_llr->data_lock);
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "get (calculated_ns = %lldns)", *calculated_ns);
+
+	return 0;
+}
+
+int sl_core_data_llr_loop_min_ns_get(struct sl_core_llr *core_llr, u64 *min_ns)
+{
+	spin_lock(&core_llr->data_lock);
+	*min_ns = core_llr->data.loop.min;
+	spin_unlock(&core_llr->data_lock);
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "get (min_ns = %lldns)", *min_ns);
+
+	return 0;
+}
+
+int sl_core_data_llr_loop_max_ns_get(struct sl_core_llr *core_llr, u64 *max_ns)
+{
+	spin_lock(&core_llr->data_lock);
+	*max_ns = core_llr->data.loop.max;
+	spin_unlock(&core_llr->data_lock);
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "get (max_ns = %lldns)", *max_ns);
+
+	return 0;
+}
+
+int sl_core_data_llr_loop_average_ns_get(struct sl_core_llr *core_llr, u64 *average_ns)
+{
+	spin_lock(&core_llr->data_lock);
+	*average_ns = core_llr->data.loop.average;
+	spin_unlock(&core_llr->data_lock);
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "get (average_ns = %lldns)", *average_ns);
+
+	return 0;
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/data/sl_core_data_mac.c b/drivers/net/ethernet/hpe/sl/core/data/sl_core_data_mac.c
new file mode 100644
index 000000000000..e058ca4f4af8
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/data/sl_core_data_mac.c
@@ -0,0 +1,273 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2022,2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+
+#include <linux/hpe/sl/sl_lgrp.h>
+#include <linux/hpe/sl/sl_media.h>
+
+#include "base/sl_core_log.h"
+#include "sl_core_lgrp.h"
+#include "sl_core_mac.h"
+#include "hw/sl_core_hw_intr.h"
+#include "data/sl_core_data_link.h"
+#include "data/sl_core_data_mac.h"
+#include "hw/sl_core_hw_mac.h"
+#include "hw/sl_core_hw_settings.h"
+
+static struct sl_core_mac *core_macs[SL_ASIC_MAX_LDEVS][SL_ASIC_MAX_LGRPS][SL_ASIC_MAX_LINKS];
+static DEFINE_SPINLOCK(core_macs_lock);
+
+#define LOG_NAME SL_CORE_DATA_MAC_LOG_NAME
+
+int sl_core_data_mac_new(u8 ldev_num, u8 lgrp_num, u8 mac_num)
+{
+	struct sl_core_mac *core_mac;
+
+	core_mac = sl_core_data_mac_get(ldev_num, lgrp_num, mac_num);
+	if (core_mac) {
+		sl_core_log_err(NULL, LOG_NAME, "exists (mac = 0x%p)", core_mac);
+		return -EBADRQC;
+	}
+
+	core_mac = kzalloc(sizeof(struct sl_core_mac), GFP_KERNEL);
+	if (!core_mac)
+		return -ENOMEM;
+
+	core_mac->magic     = SL_CORE_MAC_MAGIC;
+	core_mac->num       = mac_num;
+	core_mac->core_lgrp = sl_core_lgrp_get(ldev_num, lgrp_num);
+	if (!core_mac->core_lgrp) {
+		kfree(core_mac);
+		return -ENODEV;
+	}
+
+	spin_lock_init(&core_mac->data_lock);
+
+	sl_core_hw_mac_tx_stop(core_mac);
+	sl_core_hw_mac_rx_stop(core_mac);
+
+	sl_core_log_dbg(core_mac, LOG_NAME, "new (link = 0x%p)", core_mac);
+
+	spin_lock(&core_macs_lock);
+	core_macs[ldev_num][lgrp_num][mac_num] = core_mac;
+	spin_unlock(&core_macs_lock);
+
+	return 0;
+}
+
+void sl_core_data_mac_del(u8 ldev_num, u8 lgrp_num, u8 mac_num)
+{
+	struct sl_core_mac *core_mac;
+
+	core_mac = sl_core_mac_get(ldev_num, lgrp_num, mac_num);
+	if (!core_mac) {
+		sl_core_log_dbg(NULL, LOG_NAME, "not found (mac_num = %u)", mac_num);
+		return;
+	}
+
+	sl_core_hw_mac_tx_stop(core_mac);
+	sl_core_hw_mac_rx_stop(core_mac);
+
+	spin_lock(&core_macs_lock);
+	core_macs[ldev_num][lgrp_num][mac_num] = NULL;
+	spin_unlock(&core_macs_lock);
+
+	sl_core_log_dbg(core_mac, LOG_NAME, "del (mac = 0x%p)", core_mac);
+
+	sl_core_lgrp_put(core_mac->core_lgrp);
+	kfree(core_mac);
+}
+
+struct sl_core_mac *sl_core_data_mac_get(u8 ldev_num, u8 lgrp_num, u8 mac_num)
+{
+	struct sl_core_mac *core_mac;
+
+	spin_lock(&core_macs_lock);
+	core_mac = core_macs[ldev_num][lgrp_num][mac_num];
+	spin_unlock(&core_macs_lock);
+
+	sl_core_log_dbg(NULL, LOG_NAME,
+			"get (ldev_num = %u, lgrp_num = %u, mac_num = %u, mac = 0x%p)",
+			ldev_num, lgrp_num, mac_num, core_mac);
+
+	return core_mac;
+}
+
+int sl_core_data_mac_tx_settings(struct sl_core_mac *core_mac)
+{
+	struct sl_lgrp_config *lgrp_config;
+	struct sl_link_caps   *link_caps;
+
+	sl_core_log_dbg(core_mac, LOG_NAME, "tx settings");
+
+	lgrp_config = &(core_mac->core_lgrp->config);
+	link_caps   = &(core_mac->core_lgrp->link_caps[core_mac->num]);
+
+	if (hweight_long(link_caps->tech_map) != 1) {
+		sl_core_log_err_trace(core_mac, LOG_NAME, "tx settings - tech map invalid (map = 0x%08X)",
+				      link_caps->tech_map);
+		return -EINVAL;
+	}
+
+	if (SL_LGRP_CONFIG_TECH_CK_400G & link_caps->tech_map)
+		core_mac->settings.tx_ifg_adj = SL_CORE_HW_IFG_ADJ_400G;
+	if (SL_LGRP_CONFIG_TECH_CK_200G & link_caps->tech_map)
+		core_mac->settings.tx_ifg_adj = SL_CORE_HW_IFG_ADJ_200G;
+	if (SL_LGRP_CONFIG_TECH_CK_100G & link_caps->tech_map)
+		core_mac->settings.tx_ifg_adj = SL_CORE_HW_IFG_ADJ_100G;
+	if (SL_LGRP_CONFIG_TECH_BS_200G & link_caps->tech_map)
+		core_mac->settings.tx_ifg_adj = SL_CORE_HW_IFG_ADJ_200G;
+	if (SL_LGRP_CONFIG_TECH_CD_100G & link_caps->tech_map)
+		core_mac->settings.tx_ifg_adj = SL_CORE_HW_IFG_ADJ_100G;
+	if (SL_LGRP_CONFIG_TECH_CD_50G  & link_caps->tech_map)
+		core_mac->settings.tx_ifg_adj = SL_CORE_HW_IFG_ADJ_50G;
+	if (SL_LGRP_CONFIG_TECH_BJ_100G & link_caps->tech_map)
+		core_mac->settings.tx_ifg_adj = SL_CORE_HW_IFG_ADJ_100G;
+
+	sl_core_log_dbg(core_mac, LOG_NAME, "tx settings (ifg = %u)", core_mac->settings.tx_ifg_adj);
+
+	if (is_flag_set(lgrp_config->options, SL_LGRP_CONFIG_OPT_FABRIC)) {
+		core_mac->settings.tx_ifg_adj          = SL_CORE_HW_IFG_ADJ_NONE;
+		core_mac->settings.tx_ifg_mode         = 0;
+		core_mac->settings.tx_pad_idle_thresh  = 10;
+		core_mac->settings.tx_idle_delay       = 0;
+		core_mac->settings.tx_priority_thresh  = 0;
+		core_mac->settings.tx_cdt_thresh_2     = 0;
+		core_mac->settings.tx_cdt_thresh       = 15;
+		core_mac->settings.tx_cdt_init_val     = 72;
+		core_mac->settings.tx_pcs_credits      = 8;
+		core_mac->settings.tx_short_preamble   = 1;
+		core_mac->settings.llr_if_credits      = 8;
+	} else {
+		core_mac->settings.tx_ifg_mode         = 1;
+		core_mac->settings.tx_pad_idle_thresh  = 10;
+		switch (lgrp_config->furcation) {
+		case SL_MEDIA_FURCATION_X1:
+			core_mac->settings.tx_idle_delay      = 0;
+			core_mac->settings.tx_priority_thresh = 0;
+			core_mac->settings.tx_cdt_thresh_2    = 0;
+			core_mac->settings.tx_cdt_thresh      = 15;
+			core_mac->settings.tx_cdt_init_val    = sl_core_data_mac_tx_cdt_init_get();
+			core_mac->settings.tx_pcs_credits     = 8;
+			core_mac->settings.llr_if_credits     = 8;
+			break;
+		case SL_MEDIA_FURCATION_X2:
+			core_mac->settings.tx_idle_delay      = 0;
+			core_mac->settings.tx_priority_thresh = 32;
+			core_mac->settings.tx_cdt_thresh_2    = 32;
+			core_mac->settings.tx_cdt_thresh      = 15;
+			core_mac->settings.tx_cdt_init_val    = 72;
+			core_mac->settings.tx_pcs_credits     = 4;
+			core_mac->settings.llr_if_credits     = 4;
+			break;
+		case SL_MEDIA_FURCATION_X4:
+			core_mac->settings.tx_idle_delay      = 1;
+			core_mac->settings.tx_priority_thresh = 23;
+			core_mac->settings.tx_cdt_thresh_2    = 20;
+			core_mac->settings.tx_cdt_thresh      = 12;
+			core_mac->settings.tx_cdt_init_val    = 40;
+			core_mac->settings.tx_pcs_credits     = 2;
+			core_mac->settings.llr_if_credits     = 2;
+			break;
+		}
+		core_mac->settings.tx_short_preamble = 0;
+	}
+
+	if (is_flag_set(lgrp_config->options, SL_LGRP_CONFIG_OPT_8BYTE_PREAMBLE))
+		core_mac->settings.tx_short_preamble = 0;
+
+	return 0;
+}
+
+int sl_core_data_mac_rx_settings(struct sl_core_mac *core_mac)
+{
+	struct sl_lgrp_config *lgrp_config;
+
+	sl_core_log_dbg(core_mac, LOG_NAME, "rx settings");
+
+	lgrp_config = &(core_mac->core_lgrp->config);
+
+	if (is_flag_set(lgrp_config->options, SL_LGRP_CONFIG_OPT_FABRIC)) {
+		core_mac->settings.rx_flit_packing_cnt = 1;
+		core_mac->settings.rx_short_preamble   = 1;
+	} else {
+		core_mac->settings.rx_flit_packing_cnt = 1;
+		core_mac->settings.rx_short_preamble   = 0;
+	}
+
+	if (is_flag_set(lgrp_config->options, SL_LGRP_CONFIG_OPT_8BYTE_PREAMBLE))
+		core_mac->settings.rx_short_preamble   = 0;
+
+	return 0;
+}
+
+u32 sl_core_data_mac_tx_state_get(struct sl_core_mac *core_mac)
+{
+	switch (sl_core_hw_mac_tx_state_get(core_mac)) {
+	case 0:
+		sl_core_log_dbg(core_mac, LOG_NAME, "get TX OFF");
+		return SL_CORE_MAC_STATE_OFF;
+	case 1:
+		sl_core_log_dbg(core_mac, LOG_NAME, "get TX ON");
+		return SL_CORE_MAC_STATE_ON;
+	}
+
+	return SL_CORE_MAC_STATE_INVALID;
+}
+
+u32 sl_core_data_mac_rx_state_get(struct sl_core_mac *core_mac)
+{
+	switch (sl_core_hw_mac_rx_state_get(core_mac)) {
+	case 0:
+		sl_core_log_dbg(core_mac, LOG_NAME, "get RX OFF");
+		return SL_CORE_MAC_STATE_OFF;
+	case 1:
+		sl_core_log_dbg(core_mac, LOG_NAME, "get RX ON");
+		return SL_CORE_MAC_STATE_ON;
+	}
+
+	return SL_CORE_MAC_STATE_INVALID;
+}
+
+void sl_core_data_mac_info_map_clr(struct sl_core_mac *core_mac, u32 bit_num)
+{
+	spin_lock(&core_mac->data_lock);
+
+	if (bit_num == SL_CORE_INFO_MAP_NUM_BITS)
+		bitmap_zero((unsigned long *)&(core_mac->info_map), SL_CORE_INFO_MAP_NUM_BITS);
+	else
+		clear_bit(bit_num, (unsigned long *)&(core_mac->info_map));
+
+	sl_core_log_dbg(core_mac, LOG_NAME,
+			"clr info map 0x%016llX", core_mac->info_map);
+
+	spin_unlock(&core_mac->data_lock);
+}
+
+void sl_core_data_mac_info_map_set(struct sl_core_mac *core_mac, u32 bit_num)
+{
+	spin_lock(&core_mac->data_lock);
+	set_bit(bit_num, (unsigned long *)&(core_mac->info_map));
+
+	sl_core_log_dbg(core_mac, LOG_NAME,
+			"set info map 0x%016llX", core_mac->info_map);
+
+	spin_unlock(&core_mac->data_lock);
+}
+
+u64 sl_core_data_mac_info_map_get(struct sl_core_mac *core_mac)
+{
+	u64 info_map;
+
+	spin_lock(&core_mac->data_lock);
+	info_map = core_mac->info_map;
+	spin_unlock(&core_mac->data_lock);
+
+	sl_core_log_dbg(core_mac, LOG_NAME,
+			"get info map 0x%016llX", info_map);
+
+	return info_map;
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/nic/sl_core_hw_an.c b/drivers/net/ethernet/hpe/sl/core/hw/nic/sl_core_hw_an.c
new file mode 100644
index 000000000000..b066b2c5d437
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/nic/sl_core_hw_an.c
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+
+#include "base/sl_core_log.h"
+#include "sl_core_link.h"
+#include "hw/sl_core_hw_io.h"
+#include "hw/sl_core_hw_an.h"
+
+#define LOG_NAME SL_CORE_HW_AN_LOG_NAME
+
+void sl_core_hw_an_config_timers(struct sl_core_link *core_link)
+{
+	u32                                       port;
+	union ss2_port_pml_cfg_pcs_autoneg_timers autoneg_timers = {};
+
+	port = core_link->core_lgrp->num;
+	autoneg_timers.link_fail_inhibit_timer_max = 0x3FFFFFFFF;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "config timers (port = %d)", port);
+
+	sl_core_write64(core_link, SS2_PORT_PML_CFG_PCS_AUTONEG_TIMERS + 8, autoneg_timers.qw[1]);
+
+	sl_core_flush64(core_link, SS2_PORT_PML_CFG_PCS_AUTONEG_TIMERS + 8);
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/nic/sl_core_hw_fec.c b/drivers/net/ethernet/hpe/sl/core/hw/nic/sl_core_hw_fec.c
new file mode 100644
index 000000000000..7a6a6166eed3
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/nic/sl_core_hw_fec.c
@@ -0,0 +1,113 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2024,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+
+#include "sl_core_ldev.h"
+#include "sl_core_link.h"
+#include "sl_core_link_fec.h"
+#include "base/sl_core_log.h"
+#include "hw/sl_core_hw_fec.h"
+
+#define LOG_NAME SL_CORE_HW_FEC_LOG_NAME
+
+static int sl_core_hw_fec_dmac_xfer(struct sl_core_link *core_link, void *data)
+{
+	int                   rtn;
+	struct sl_core_ldev  *core_ldev;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "dmac_xfer");
+
+	core_ldev = core_link->core_lgrp->core_ldev;
+
+	if (!core_ldev->ops.dmac_xfer) {
+		sl_core_log_dbg(core_link, LOG_NAME, "dmac_xfer NULL");
+		return 0;
+	}
+
+	rtn = core_ldev->ops.dmac_xfer(core_ldev->accessors.dmac, data);
+	if (rtn) {
+		sl_core_log_err(core_link, LOG_NAME, "op dmac_xfer failed [%d]", rtn);
+		return rtn;
+	}
+
+	return 0;
+}
+
+int sl_core_hw_fec_cw_cntrs_get(struct sl_core_link *core_link, struct sl_core_link_fec_cw_cntrs *cw_cntrs)
+{
+	int                                rtn;
+	struct sl_core_link_fec_data_cntrs data_cntrs;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "cw_cntrs_get");
+
+	rtn = sl_core_hw_fec_dmac_xfer(core_link, &data_cntrs);
+	if (rtn) {
+		sl_core_log_err_trace(core_link, LOG_NAME, "cw_cntrs_get dmac_xfer failed [%d]", rtn);
+		return rtn;
+	}
+
+	*cw_cntrs = data_cntrs.cw_cntrs;
+
+	return 0;
+}
+
+int sl_core_hw_fec_lane_cntrs_get(struct sl_core_link *core_link, struct sl_core_link_fec_lane_cntrs *lane_cntrs)
+{
+	int                                rtn;
+	struct sl_core_link_fec_data_cntrs data_cntrs;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "lane_cntrs_get");
+
+	rtn = sl_core_hw_fec_dmac_xfer(core_link, &data_cntrs);
+	if (rtn) {
+		sl_core_log_err_trace(core_link, LOG_NAME, "lane_cntrs_get dmac_xfer failed [%d]", rtn);
+		return rtn;
+	}
+
+	*lane_cntrs = data_cntrs.lane_cntrs;
+
+	return 0;
+}
+
+int sl_core_hw_fec_tail_cntrs_get(struct sl_core_link *core_link,
+				  struct sl_core_link_fec_tail_cntrs *tail_cntrs)
+{
+	int                                rtn;
+	struct sl_core_link_fec_data_cntrs data_cntrs;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "tail_cntr_get");
+
+	rtn = sl_core_hw_fec_dmac_xfer(core_link, &data_cntrs);
+	if (rtn) {
+		sl_core_log_err_trace(core_link, LOG_NAME, "tail_cntr_get dmac_xfer failed [%d]", rtn);
+		return rtn;
+	}
+
+	*tail_cntrs = data_cntrs.tail_cntrs;
+
+	return 0;
+}
+
+int sl_core_hw_fec_data_get(struct sl_core_link *core_link,
+			    struct sl_core_link_fec_cw_cntrs *cw_cntrs,
+			    struct sl_core_link_fec_lane_cntrs *lane_cntrs,
+			    struct sl_core_link_fec_tail_cntrs *tail_cntr)
+{
+	int                                rtn;
+	struct sl_core_link_fec_data_cntrs data_cntrs;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "fec_data_get");
+
+	rtn = sl_core_hw_fec_dmac_xfer(core_link, &data_cntrs);
+	if (rtn) {
+		sl_core_log_err_trace(core_link, LOG_NAME, "fec_data_get dmac_xfer failed [%d]", rtn);
+		return rtn;
+	}
+
+	*cw_cntrs    = data_cntrs.cw_cntrs;
+	*lane_cntrs  = data_cntrs.lane_cntrs;
+	*tail_cntr   = data_cntrs.tail_cntrs;
+
+	return 0;
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/nic/sl_core_hw_llr.c b/drivers/net/ethernet/hpe/sl/core/hw/nic/sl_core_hw_llr.c
new file mode 100644
index 000000000000..dacd4729b8df
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/nic/sl_core_hw_llr.c
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2025,2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+
+#include "base/sl_core_log.h"
+#include "sl_core_link.h"
+#include "hw/sl_core_hw_io.h"
+#include "hw/sl_core_hw_llr.h"
+
+#define LOG_NAME SL_CORE_HW_LLR_LOG_NAME
+
+void sl_core_hw_llr_config_timeouts(struct sl_core_llr *core_llr)
+{
+	u32                  port;
+	u64                  data64;
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+	bool                 is_pml_rec_enabled;
+
+	port = core_llr->core_lgrp->num;
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "config timeouts (port = %d)", port);
+
+	core_link = sl_core_link_get(core_llr->core_lgrp->core_ldev->num, core_llr->core_lgrp->num, core_llr->num);
+	if (!core_link)
+		return;
+
+	is_pml_rec_enabled = sl_core_link_config_is_enable_pml_recovery_set(core_link);
+
+	sl_core_llr_read64(core_llr, SS2_PORT_PML_CFG_LLR_TIMEOUTS(core_llr->num), &data64);
+	if (is_pml_rec_enabled) {
+		data64 = SS2_PORT_PML_CFG_LLR_TIMEOUTS_DATA_AGE_TIMER_MAX_UPDATE(data64,
+										 (core_link->config.pml_rec_timeout_ms + 8) * 1000000);
+		data64 = SS2_PORT_PML_CFG_LLR_TIMEOUTS_PCS_LINK_DN_TIMER_MAX_UPDATE(data64,
+										    (core_link->config.pml_rec_timeout_ms + 8) * 1000000);
+	} else {
+		data64 = SS2_PORT_PML_CFG_LLR_TIMEOUTS_DATA_AGE_TIMER_MAX_UPDATE(data64, 0xEE6B2800);
+		data64 = SS2_PORT_PML_CFG_LLR_TIMEOUTS_PCS_LINK_DN_TIMER_MAX_UPDATE(data64, 0x389ACA00);
+	}
+
+	sl_core_llr_write64(core_llr, SS2_PORT_PML_CFG_LLR_TIMEOUTS(core_llr->num), data64);
+
+	sl_core_llr_flush64(core_llr, SS2_PORT_PML_CFG_LLR_TIMEOUTS(core_llr->num));
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/nic/sl_core_hw_mac.c b/drivers/net/ethernet/hpe/sl/core/hw/nic/sl_core_hw_mac.c
new file mode 100644
index 000000000000..6bbf76001a85
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/nic/sl_core_hw_mac.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+
+#include "base/sl_core_log.h"
+#include "sl_core_mac.h"
+#include "hw/sl_core_hw_io.h"
+#include "hw/sl_core_hw_mac.h"
+
+#define LOG_NAME SL_CORE_HW_MAC_LOG_NAME
+
+void sl_core_hw_mac_tx_config_subport(struct sl_core_mac *core_mac)
+{
+	u64 data64;
+	u32 port;
+
+	port = core_mac->core_lgrp->num;
+
+	sl_core_log_dbg(core_mac, LOG_NAME, "tx config subport (port = %d)", port);
+
+	sl_core_mac_read64(core_mac, SS2_PORT_PML_CFG_TX_MAC_SUBPORT(core_mac->num), &data64);
+	data64 = SS2_PORT_PML_CFG_TX_MAC_SUBPORT_MAC_CDT_THRESH_UPDATE(data64,
+								       core_mac->settings.tx_cdt_thresh);
+	data64 = SS2_PORT_PML_CFG_TX_MAC_SUBPORT_MAC_CDT_INIT_VAL_UPDATE(data64,
+									 core_mac->settings.tx_cdt_init_val);
+	data64 = SS2_PORT_PML_CFG_TX_MAC_SUBPORT_SHORT_PREAMBLE_UPDATE(data64,
+								       core_mac->settings.tx_short_preamble);
+	sl_core_mac_write64(core_mac, SS2_PORT_PML_CFG_TX_MAC_SUBPORT(core_mac->num), data64);
+
+	sl_core_mac_flush64(core_mac, SS2_PORT_PML_CFG_TX_MAC_SUBPORT(core_mac->num));
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/nic/sl_core_hw_pcs.c b/drivers/net/ethernet/hpe/sl/core/hw/nic/sl_core_hw_pcs.c
new file mode 100644
index 000000000000..405006239baf
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/nic/sl_core_hw_pcs.c
@@ -0,0 +1,14 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+
+#include "sl_core_link.h"
+#include "hw/sl_core_hw_pcs.h"
+
+#define LOG_NAME SL_CORE_HW_PCS_LOG_NAME
+
+void sl_core_hw_pcs_keep_all_lanes_active_set(struct sl_core_link *core_link, u64 value)
+{
+	/* TODO: Add graceful lane-degrade support, currently absent from SL. */
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_an.c b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_an.c
new file mode 100644
index 000000000000..fed65e85d5d9
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_an.c
@@ -0,0 +1,602 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2022,2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/random.h>
+#include <linux/workqueue.h>
+
+#include "sl_core_link.h"
+#include "base/sl_core_log.h"
+#include "hw/sl_core_hw_intr.h"
+#include "data/sl_core_data_link.h"
+#include "hw/sl_core_hw_io.h"
+#include "hw/sl_core_hw_an.h"
+#include "hw/sl_core_hw_pcs.h"
+
+#define LOG_NAME SL_CORE_HW_AN_LOG_NAME
+
+#define SL_CORE_HW_AN_STATE_COMPLETE_ACK  5
+#define SL_CORE_HW_AN_STATE_AN_GOOD_CHECK 9
+
+void sl_core_hw_an_tx_pages_encode(struct sl_core_link *core_link, struct sl_link_caps *my_caps)
+{
+	int x;
+
+	memset(core_link->an.tx_pages, 0, sizeof(core_link->an.tx_pages));
+
+	/* 1 - base page */
+	core_link->an.tx_pages[0] |= SL_CORE_HW_AN_BP_802_3;
+	core_link->an.tx_pages[0] |= ((u64)(my_caps->pause_map & SL_LINK_CONFIG_PAUSE_MASK) <<
+		SL_CORE_HW_AN_BP_PAUSE_SHIFT);
+	core_link->an.tx_pages[0] |= ((u64)(my_caps->tech_map & SL_LGRP_CONFIG_TECH_MASK) <<
+		SL_CORE_HW_AN_BP_TECH_SHIFT);
+	core_link->an.tx_pages[0] |= ((u64)(my_caps->fec_map & SL_LGRP_CONFIG_FEC_MASK) <<
+		SL_CORE_HW_AN_BP_FEC_SHIFT);
+
+	/* 2 - OUI message next page */
+	set_bit(SL_CORE_HW_AN_NP_BIT_MP, (unsigned long *)&(core_link->an.tx_pages[1]));
+	core_link->an.tx_pages[1] |= SL_CORE_HW_AN_NP_MSG_OUI_EXTD;
+	core_link->an.tx_pages[1] |= SL_CORE_HW_AN_NP_OUI_HPE;
+
+	/* 3 - unformatted page with OUI message next page */
+	core_link->an.tx_pages[2] |= SL_CORE_HW_AN_NP_OUI_VER_0_1;
+	core_link->an.tx_pages[2] |= ((my_caps->hpe_map & SL_LINK_CONFIG_HPE_MASK) <<
+		SL_CORE_HW_AN_NP_HPE_SHIFT);
+	core_link->an.tx_pages[2] |= (2ULL << SL_CORE_HW_AN_NP_BIT_OUI_ASIC_VER);
+
+	core_link->an.tx_count = 3;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "tx pages encode (count = %u)", core_link->an.tx_count);
+	for (x = 0; x < core_link->an.tx_count; ++x)
+		sl_core_log_dbg(core_link, LOG_NAME,
+				"tx pages encode pages (%d = 0x%016llX)", x, core_link->an.tx_pages[x]);
+}
+
+#define SL_CORE_HW_AN_NUONCE_MASK 0xF
+static u64 sl_core_hw_an_nonce_get(struct sl_core_link *core_link)
+{
+	u8 num;
+
+	do {
+		get_random_bytes(&num, sizeof(num));
+		num &= SL_CORE_HW_AN_NUONCE_MASK;
+	} while (num == 0);
+
+	sl_core_log_dbg(core_link, LOG_NAME, "nonce = 0x%X", num);
+
+	return num;
+}
+
+void sl_core_hw_an_stop(struct sl_core_link *core_link)
+{
+	u64 data64;
+	u32 port;
+
+	port = core_link->core_lgrp->num;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "stop (port = %u)", port);
+
+	sl_core_read64(core_link, SS2_PORT_PML_CFG_PCS_AUTONEG(core_link->num), &data64);
+	data64 = SS2_PORT_PML_CFG_PCS_AUTONEG_RESET_UPDATE(data64, 1);
+	sl_core_write64(core_link, SS2_PORT_PML_CFG_PCS_AUTONEG(core_link->num), data64);
+
+	sl_core_read64(core_link, SS2_PORT_PML_CFG_PCS_SUBPORT(core_link->num), &data64);
+	data64 = SS2_PORT_PML_CFG_PCS_SUBPORT_ENABLE_AUTO_NEG_UPDATE(data64, 0);
+	sl_core_write64(core_link, SS2_PORT_PML_CFG_PCS_SUBPORT(core_link->num), data64);
+
+	sl_core_flush64(core_link, SS2_PORT_PML_CFG_PCS_AUTONEG(core_link->num));
+}
+
+static void sl_core_hw_an_start(struct sl_core_link *core_link)
+{
+	u64 data64;
+	u32 port;
+
+	port = core_link->core_lgrp->num;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "start (port = %u)", port);
+
+	sl_core_read64(core_link, SS2_PORT_PML_CFG_PCS_SUBPORT(core_link->num), &data64);
+	data64 = SS2_PORT_PML_CFG_PCS_SUBPORT_ENABLE_AUTO_NEG_UPDATE(data64, 1);
+	sl_core_write64(core_link, SS2_PORT_PML_CFG_PCS_SUBPORT(core_link->num), data64);
+
+	sl_core_read64(core_link, SS2_PORT_PML_CFG_PCS_AUTONEG(core_link->num), &data64);
+	data64 = SS2_PORT_PML_CFG_PCS_AUTONEG_RESET_UPDATE(data64, 0);
+	sl_core_write64(core_link, SS2_PORT_PML_CFG_PCS_AUTONEG(core_link->num), data64);
+
+	sl_core_flush64(core_link, SS2_PORT_PML_CFG_PCS_AUTONEG(core_link->num));
+}
+
+void sl_core_hw_an_init(struct sl_core_link *core_link)
+{
+	sl_core_log_dbg(core_link, LOG_NAME, "init");
+
+	core_link->an.state    = SL_CORE_HW_AN_STATE_START;
+	core_link->an.page_num = 0;
+	core_link->an.tx_count = 0;
+	core_link->an.rx_count = 0;
+	memset(core_link->an.rx_pages, 0, sizeof(core_link->an.rx_pages));
+}
+
+void sl_core_hw_an_config(struct sl_core_link *core_link)
+{
+	u64 data64;
+	u32 port;
+
+	port = core_link->core_lgrp->num;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "config (port = %d)", port);
+
+	sl_core_read64(core_link, SS2_PORT_PML_CFG_PCS_SUBPORT(core_link->num), &data64);
+	data64 = SS2_PORT_PML_CFG_PCS_SUBPORT_PCS_ENABLE_UPDATE(data64, 0);
+	data64 = SS2_PORT_PML_CFG_PCS_SUBPORT_ENABLE_AUTO_NEG_UPDATE(data64, 0);
+	sl_core_write64(core_link, SS2_PORT_PML_CFG_PCS_SUBPORT(core_link->num), data64);
+
+	sl_core_read64(core_link, SS2_PORT_PML_CFG_PCS_AUTONEG(core_link->num), &data64);
+	data64 = SS2_PORT_PML_CFG_PCS_AUTONEG_RESET_UPDATE(data64, 1);
+	data64 = SS2_PORT_PML_CFG_PCS_AUTONEG_RESTART_UPDATE(data64, 0);
+	data64 = SS2_PORT_PML_CFG_PCS_AUTONEG_NEXT_PAGE_LOADED_UPDATE(data64, 0);
+	sl_core_write64(core_link, SS2_PORT_PML_CFG_PCS_AUTONEG(core_link->num), data64);
+
+	sl_core_hw_pcs_config_swizzles(core_link);
+
+	sl_core_read64(core_link, SS2_PORT_PML_CFG_RX_PCS_SUBPORT(core_link->num), &data64);
+	data64 = SS2_PORT_PML_CFG_RX_PCS_SUBPORT_ENABLE_LOCK_UPDATE(data64, 0);
+	sl_core_write64(core_link, SS2_PORT_PML_CFG_RX_PCS_SUBPORT(core_link->num), data64);
+
+	sl_core_hw_an_config_timers(core_link);
+
+	sl_core_flush64(core_link, SS2_PORT_PML_CFG_RX_PCS);
+}
+
+static void sl_core_hw_an_base_page_write(struct sl_core_link *core_link)
+{
+	u32 port;
+	u64 page;
+
+	port = core_link->core_lgrp->num;
+	page = core_link->an.tx_pages[core_link->an.page_num];
+
+	/* add control bits */
+	if (core_link->an.page_num < core_link->an.tx_count - 1)
+		set_bit(SL_CORE_HW_AN_BP_BIT_NP, (unsigned long *)&(page));
+	page |= (sl_core_hw_an_nonce_get(core_link) << SL_CORE_HW_AN_BP_BIT_TRANS_NONCE);
+
+	/* store toggle bit */
+	core_link->an.toggle = test_bit(SL_CORE_HW_AN_NP_BIT_T, (unsigned long *)&(page));
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"base page write (port = %u, pg %u = 0x%016llX, toggle = %d)",
+		port, core_link->an.page_num, page, core_link->an.toggle);
+
+	sl_core_write64(core_link, SS2_PORT_PML_CFG_PCS_AUTONEG_BASE_PAGE(core_link->num), page);
+
+	sl_core_flush64(core_link, SS2_PORT_PML_CFG_PCS_AUTONEG_BASE_PAGE(core_link->num));
+}
+
+static void sl_core_hw_an_next_page_write(struct sl_core_link *core_link)
+{
+	u32 port;
+	u64 page;
+
+	port = core_link->core_lgrp->num;
+	if (core_link->an.page_num < core_link->an.tx_count)
+		page = core_link->an.tx_pages[core_link->an.page_num];
+	else
+		page = SL_CORE_HW_AN_NP_MSG_NULL;
+
+	/* add control bits */
+	if (core_link->an.page_num < core_link->an.tx_count - 1)
+		set_bit(SL_CORE_HW_AN_NP_BIT_NP, (unsigned long *)&(page));
+	if (core_link->an.toggle)
+		set_bit(SL_CORE_HW_AN_NP_BIT_T, (unsigned long *)&(page));
+	core_link->an.toggle = !core_link->an.toggle;
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"next page write (port = %u, pg %u = 0x%016llX, toggle = %d)",
+		port, core_link->an.page_num, page, core_link->an.toggle);
+
+	sl_core_write64(core_link, SS2_PORT_PML_CFG_PCS_AUTONEG_NEXT_PAGE(core_link->num), page);
+
+	sl_core_flush64(core_link, SS2_PORT_PML_CFG_PCS_AUTONEG_NEXT_PAGE(core_link->num));
+}
+
+static void sl_core_hw_an_next_page_go(struct sl_core_link *core_link)
+{
+	u64 data64;
+	u32 port;
+
+	port = core_link->core_lgrp->num;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "next page go (port = %u)", port);
+
+	sl_core_read64(core_link, SS2_PORT_PML_CFG_PCS_AUTONEG(core_link->num), &data64);
+	data64 = SS2_PORT_PML_CFG_PCS_AUTONEG_NEXT_PAGE_LOADED_UPDATE(data64, 1);
+	sl_core_write64(core_link, SS2_PORT_PML_CFG_PCS_AUTONEG(core_link->num), data64);
+
+	sl_core_flush64(core_link, SS2_PORT_PML_CFG_PCS_AUTONEG(core_link->num));
+}
+
+int sl_core_hw_an_base_page_send(struct sl_core_link *core_link)
+{
+	int rtn;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "base page send (pg = %u)", core_link->an.page_num);
+
+	sl_core_data_link_info_map_clr(core_link, SL_CORE_INFO_MAP_AN_NEXT_PAGE);
+	sl_core_data_link_info_map_clr(core_link, SL_CORE_INFO_MAP_AN_ERROR);
+	sl_core_data_link_info_map_clr(core_link, SL_CORE_INFO_MAP_AN_DONE);
+	sl_core_data_link_info_map_set(core_link, SL_CORE_INFO_MAP_AN_BASE_PAGE);
+	core_link->an.state = SL_CORE_HW_AN_STATE_BASE;
+
+	sl_core_hw_an_base_page_write(core_link);
+
+	sl_core_hw_intr_flgs_clr(core_link, SL_CORE_HW_INTR_AN_PAGE_RECV);
+
+	rtn = sl_core_hw_intr_enable(core_link,
+				     core_link->intrs[SL_CORE_HW_INTR_AN_PAGE_RECV].flgs, sl_core_hw_an_intr_hdlr);
+	if (rtn != 0) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "base page send intr enable failed [%d]", rtn);
+		sl_core_data_link_an_fail_cause_set(core_link,
+						    SL_CORE_HW_AN_FAIL_CAUSE_BP_SEND_INTR_ENABLE_FAIL);
+		return rtn;
+	}
+
+	sl_core_hw_an_start(core_link);
+
+	return 0;
+}
+
+static int sl_core_hw_an_next_page_send(struct sl_core_link *core_link)
+{
+	sl_core_log_dbg(core_link, LOG_NAME, "next page send (pg = %u)", core_link->an.page_num);
+
+	sl_core_data_link_info_map_clr(core_link, SL_CORE_INFO_MAP_AN_BASE_PAGE);
+	sl_core_data_link_info_map_set(core_link, SL_CORE_INFO_MAP_AN_NEXT_PAGE);
+	core_link->an.state = SL_CORE_HW_AN_STATE_NEXT;
+
+	sl_core_hw_an_next_page_write(core_link);
+
+	sl_core_hw_an_next_page_go(core_link);
+
+	return 0;
+}
+
+static void sl_core_hw_an_base_page_store(struct sl_core_link *core_link)
+{
+	u64 data64;
+	u32 port;
+	u64 state;
+
+	port = core_link->core_lgrp->num;
+
+	sl_core_read64(core_link, SS2_PORT_PML_STS_PCS_AUTONEG_BASE_PAGE(core_link->num), &data64);
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"base page store (port = %u, pg %u = 0x%016llX, state = %llu)",
+		port, core_link->an.page_num, data64,
+		SS2_PORT_PML_STS_PCS_AUTONEG_BASE_PAGE_STATE_GET(data64));
+
+	state = SS2_PORT_PML_STS_PCS_AUTONEG_BASE_PAGE_STATE_GET(data64);
+	if ((state != SL_CORE_HW_AN_STATE_COMPLETE_ACK) &&
+	    (state != SL_CORE_HW_AN_STATE_AN_GOOD_CHECK)) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "base page store bad state (pg %u = 0x%016llX)",
+			core_link->an.page_num, data64);
+		sl_core_data_link_an_fail_cause_set(core_link, SL_CORE_HW_AN_FAIL_CAUSE_BP_STORE_STATE_BAD);
+		core_link->an.state = SL_CORE_HW_AN_STATE_ERROR;
+		return;
+	}
+
+	if (!SS2_PORT_PML_STS_PCS_AUTONEG_BASE_PAGE_LP_ABILITY_GET(data64)) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "base page store lp ability not set (pg %u = 0x%016llX)",
+			core_link->an.page_num, data64);
+		sl_core_data_link_an_fail_cause_set(core_link,
+						    SL_CORE_HW_AN_FAIL_CAUSE_BP_STORE_LP_ABILITY_NOT_SET);
+		core_link->an.state = SL_CORE_HW_AN_STATE_ERROR;
+		return;
+	}
+
+	if (!SS2_PORT_PML_STS_PCS_AUTONEG_BASE_PAGE_BASE_PAGE_GET(data64)) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "base page store base page not set (pg %u = 0x%016llX)",
+			core_link->an.page_num, data64);
+		sl_core_data_link_an_fail_cause_set(core_link,
+						    SL_CORE_HW_AN_FAIL_CAUSE_BP_STORE_BP_NOT_SET);
+		core_link->an.state = SL_CORE_HW_AN_STATE_ERROR;
+		return;
+	}
+
+	core_link->an.rx_pages[core_link->an.page_num] =
+		SS2_PORT_PML_STS_PCS_AUTONEG_BASE_PAGE_LP_BASE_PAGE_GET(data64);
+	core_link->an.rx_count++;
+
+	if (SS2_PORT_PML_STS_PCS_AUTONEG_BASE_PAGE_COMPLETE_GET(data64)) {
+		core_link->an.state = SL_CORE_HW_AN_STATE_COMPLETE;
+		return;
+	}
+
+	if (!test_bit(SL_CORE_HW_AN_BP_BIT_NP,
+		      (unsigned long *)&(core_link->an.rx_pages[core_link->an.page_num]))) {
+		core_link->an.state = SL_CORE_HW_AN_STATE_LP_DONE;
+		return;
+	}
+}
+
+static void sl_core_hw_an_next_page_store(struct sl_core_link *core_link)
+{
+	u64 data64;
+	u32 port;
+	u64 state;
+
+	port = core_link->core_lgrp->num;
+
+	sl_core_read64(core_link, SS2_PORT_PML_STS_PCS_AUTONEG_NEXT_PAGE(core_link->num), &data64);
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"next page store (port = %u, pg %u = 0x%016llX, state = %llu)",
+		port, core_link->an.page_num, data64,
+		SS2_PORT_PML_STS_PCS_AUTONEG_NEXT_PAGE_STATE_GET(data64));
+
+	state = SS2_PORT_PML_STS_PCS_AUTONEG_BASE_PAGE_STATE_GET(data64);
+	if ((state != SL_CORE_HW_AN_STATE_COMPLETE_ACK) &&
+	    (state != SL_CORE_HW_AN_STATE_AN_GOOD_CHECK)) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "next page store bad state (pg %u = 0x%016llX)",
+			core_link->an.page_num, data64);
+		sl_core_data_link_an_fail_cause_set(core_link, SL_CORE_HW_AN_FAIL_CAUSE_NP_STORE_STATE_BAD);
+		core_link->an.state = SL_CORE_HW_AN_STATE_ERROR;
+		return;
+	}
+
+	if (SS2_PORT_PML_STS_PCS_AUTONEG_NEXT_PAGE_BASE_PAGE_GET(data64)) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "next page store base page set (pg %u = 0x%016llX)",
+			core_link->an.page_num, data64);
+		sl_core_data_link_an_fail_cause_set(core_link,
+						    SL_CORE_HW_AN_FAIL_CAUSE_NP_STORE_BP_SET);
+		core_link->an.state = SL_CORE_HW_AN_STATE_RETRY;
+		return;
+	}
+
+	core_link->an.rx_pages[core_link->an.page_num] =
+		SS2_PORT_PML_STS_PCS_AUTONEG_NEXT_PAGE_LP_NEXT_PAGE_GET(data64);
+	core_link->an.rx_count++;
+
+	if (SS2_PORT_PML_STS_PCS_AUTONEG_NEXT_PAGE_COMPLETE_GET(data64)) {
+		core_link->an.state = SL_CORE_HW_AN_STATE_COMPLETE;
+		return;
+	}
+
+	if (!test_bit(SL_CORE_HW_AN_NP_BIT_NP,
+		      (unsigned long *)&(core_link->an.rx_pages[core_link->an.page_num]))) {
+		core_link->an.state = SL_CORE_HW_AN_STATE_LP_DONE;
+		return;
+	}
+}
+
+static void sl_core_hw_an_next_page_check(struct sl_core_link *core_link)
+{
+	u64 data64;
+	u32 port;
+	u64 state;
+
+	port = core_link->core_lgrp->num;
+
+	sl_core_read64(core_link, SS2_PORT_PML_STS_PCS_AUTONEG_NEXT_PAGE(core_link->num), &data64);
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"next page check (port = %u, data = 0x%016llX)", port, data64);
+
+	state = SS2_PORT_PML_STS_PCS_AUTONEG_BASE_PAGE_STATE_GET(data64);
+	if ((state != SL_CORE_HW_AN_STATE_COMPLETE_ACK) &&
+	    (state != SL_CORE_HW_AN_STATE_AN_GOOD_CHECK)) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "next page check bad state (pg %u = 0x%016llX)",
+			core_link->an.page_num, data64);
+		sl_core_data_link_an_fail_cause_set(core_link, SL_CORE_HW_AN_FAIL_CAUSE_NP_CHECK_STATE_BAD);
+		core_link->an.state = SL_CORE_HW_AN_STATE_ERROR;
+		return;
+	}
+
+	if (SS2_PORT_PML_STS_PCS_AUTONEG_NEXT_PAGE_COMPLETE_GET(data64)) {
+		core_link->an.state = SL_CORE_HW_AN_STATE_COMPLETE;
+		return;
+	}
+}
+
+#define AN_IS_OUI_HPE_EXTD(_page)                                                   \
+	(((_page) & (SL_CORE_HW_AN_NP_MSG_MASK | SL_CORE_HW_AN_NP_OUI_HPE_MASK)) == \
+		(SL_CORE_HW_AN_NP_MSG_OUI_EXTD | SL_CORE_HW_AN_NP_OUI_HPE))
+#define AN_OUI_VER_GET(_page) \
+	((_page) & SL_CORE_HW_AN_NP_OUI_VER_MASK)
+#define AN_HPE_MAP_GET(_page) \
+	(((_page) >> SL_CORE_HW_AN_NP_HPE_SHIFT) & SL_LINK_CONFIG_HPE_MASK)
+
+int sl_core_hw_an_rx_pages_decode(struct sl_core_link *core_link,
+				  struct sl_link_caps *my_caps, struct sl_link_caps *link_caps)
+{
+	int x;
+	u32 pause_map;
+	u32 tech_map;
+	u32 fec_map;
+	u32 hpe_map;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "rx pages decode (count = %u)", core_link->an.rx_count);
+	for (x = 0; x < core_link->an.rx_count; ++x)
+		sl_core_log_dbg(core_link, LOG_NAME,
+				"rx pages decode pages (%d = 0x%016llX)", x, core_link->an.rx_pages[x]);
+
+	/* base page */
+	if (!(core_link->an.rx_pages[0] & SL_CORE_HW_AN_BP_802_3)) {
+		sl_core_log_err_trace(core_link, LOG_NAME, "rx pages decode no base page");
+		sl_core_data_link_an_fail_cause_set(core_link,
+						    SL_CORE_HW_AN_FAIL_CAUSE_PAGES_DECODE_NO_BP);
+		return -EIO;
+	}
+	pause_map  = (core_link->an.rx_pages[0] >> SL_CORE_HW_AN_BP_PAUSE_SHIFT);
+	pause_map &= SL_LINK_CONFIG_PAUSE_MASK;
+	pause_map &= core_link->config.pause_map;
+	tech_map   = (core_link->an.rx_pages[0] >> SL_CORE_HW_AN_BP_TECH_SHIFT);
+	tech_map  &= SL_LGRP_CONFIG_TECH_MASK;
+	tech_map  &= core_link->core_lgrp->config.tech_map;
+	fec_map    = (core_link->an.rx_pages[0] >> SL_CORE_HW_AN_BP_FEC_SHIFT);
+	fec_map   &= SL_LGRP_CONFIG_FEC_MASK;
+	fec_map   &= core_link->core_lgrp->config.fec_map;
+
+	/* next pages */
+	hpe_map = 0;
+	for (x = 1; x < core_link->an.rx_count; ++x) {
+		if (AN_IS_OUI_HPE_EXTD(core_link->an.rx_pages[x])) {
+			x++;
+			switch (AN_OUI_VER_GET(core_link->an.rx_pages[x])) {
+			case SL_CORE_HW_AN_NP_OUI_VER_0_2:
+				sl_core_log_dbg(core_link, LOG_NAME, "rx pages decode v2 oui");
+				fallthrough;
+			case SL_CORE_HW_AN_NP_OUI_VER_0_1:
+				sl_core_log_dbg(core_link, LOG_NAME, "rx pages decode v1 oui");
+				hpe_map = AN_HPE_MAP_GET(core_link->an.rx_pages[x]);
+				break;
+			default:
+				sl_core_log_err_trace(core_link, LOG_NAME,
+						      "rx pages decode invalid oui (ver = 0x%llX)",
+						      AN_OUI_VER_GET(core_link->an.rx_pages[x]));
+				sl_core_data_link_an_fail_cause_set(core_link,
+								    SL_CORE_HW_AN_FAIL_CAUSE_PAGES_DECODE_OUI_INVALID);
+				return -EIO;
+			}
+			break;
+		}
+	}
+
+	/* common maps */
+	tech_map &= my_caps->tech_map;
+	for (x = 31; x >= 0; --x) {
+		if (tech_map & BIT(x)) {
+			link_caps->tech_map = BIT(x);
+			break;
+		}
+	}
+	link_caps->pause_map = pause_map & my_caps->pause_map;
+	link_caps->fec_map   = fec_map & my_caps->fec_map;
+	link_caps->fec_map  |= SL_LGRP_CONFIG_FEC_RS;
+	link_caps->hpe_map   = hpe_map & my_caps->hpe_map;
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"rx pages decode (pause = 0x%X, tech = 0x%X, fec = 0x%X, hpe = 0x%X)",
+			link_caps->pause_map, link_caps->tech_map, link_caps->fec_map, link_caps->hpe_map);
+
+	return 0;
+}
+
+/**
+ * sl_core_hw_an_page_recv_intr - Handle page AN receive interrupt
+ * @core_link: Pointer to the core link structure
+ *
+ * Context: Interrupt Context
+ */
+static void sl_core_hw_an_page_recv_intr(struct sl_core_link *core_link)
+{
+	int rtn;
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"page recv intr (state = %u)", core_link->an.state);
+
+	switch (core_link->an.state) {
+	case SL_CORE_HW_AN_STATE_BASE:
+		sl_core_hw_an_base_page_store(core_link);
+		break;
+	case SL_CORE_HW_AN_STATE_NEXT:
+		sl_core_hw_an_next_page_store(core_link);
+		break;
+	case SL_CORE_HW_AN_STATE_LP_DONE:
+		sl_core_hw_an_next_page_check(core_link);
+		break;
+	default:
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "page recv intr invalid (state = %u)", core_link->an.state);
+		sl_core_data_link_an_fail_cause_set(core_link, SL_CORE_HW_AN_FAIL_CAUSE_INTR_STATE_INVALID);
+		goto out;
+	}
+
+	if (core_link->an.state == SL_CORE_HW_AN_STATE_COMPLETE) {
+		sl_core_log_dbg(core_link, LOG_NAME, "page recv intr autoneg complete");
+		sl_core_data_link_an_fail_cause_set(core_link, SL_CORE_HW_AN_FAIL_CAUSE_NONE);
+		sl_core_data_link_info_map_clr(core_link, SL_CORE_INFO_MAP_AN_NEXT_PAGE);
+		sl_core_data_link_info_map_clr(core_link, SL_CORE_INFO_MAP_AN_BASE_PAGE);
+		sl_core_data_link_info_map_clr(core_link, SL_CORE_INFO_MAP_AN_ERROR);
+		sl_core_data_link_info_map_set(core_link, SL_CORE_INFO_MAP_AN_DONE);
+		goto out;
+	}
+
+	if (core_link->an.state == SL_CORE_HW_AN_STATE_ERROR) {
+		sl_core_data_link_info_map_clr(core_link, SL_CORE_INFO_MAP_AN_NEXT_PAGE);
+		sl_core_data_link_info_map_clr(core_link, SL_CORE_INFO_MAP_AN_BASE_PAGE);
+		sl_core_data_link_info_map_clr(core_link, SL_CORE_INFO_MAP_AN_DONE);
+		sl_core_data_link_info_map_set(core_link, SL_CORE_INFO_MAP_AN_ERROR);
+		goto out;
+	}
+
+	if (core_link->an.state == SL_CORE_HW_AN_STATE_RETRY) {
+		atomic_inc(&core_link->an.retry_count);
+		rtn = sl_core_hw_an_next_page_send(core_link);
+		if (rtn != 0) {
+			sl_core_log_err_trace(core_link, LOG_NAME,
+					      "page recv intr an next page send retry failed [%d]", rtn);
+			sl_core_data_link_an_fail_cause_set(core_link,
+							    SL_CORE_HW_AN_FAIL_CAUSE_INTR_AN_RETRY_NP_SEND_FAIL);
+			core_link->an.state = SL_CORE_HW_AN_STATE_ERROR;
+			goto out;
+		}
+		return;
+	}
+
+	core_link->an.page_num++;
+
+	if (core_link->an.page_num >= SL_CORE_LINK_AN_MAX_PAGES) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "page recv intr out of pages");
+		sl_core_data_link_an_fail_cause_set(core_link, SL_CORE_HW_AN_FAIL_CAUSE_INTR_OUT_OF_PAGES);
+		core_link->an.state = SL_CORE_HW_AN_STATE_ERROR;
+		goto out;
+	}
+
+	rtn = sl_core_hw_an_next_page_send(core_link);
+	if (rtn != 0) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "page recv intr an next page send failed [%d]", rtn);
+		sl_core_data_link_an_fail_cause_set(core_link,
+						    SL_CORE_HW_AN_FAIL_CAUSE_INTR_NP_SEND_FAIL);
+		core_link->an.state = SL_CORE_HW_AN_STATE_ERROR;
+		goto out;
+	}
+
+	return;
+
+out:
+	rtn = sl_core_hw_intr_disable(core_link,
+				      core_link->intrs[SL_CORE_HW_INTR_AN_PAGE_RECV].flgs, sl_core_hw_an_intr_hdlr);
+	if (rtn != 0)
+		sl_core_log_warn_trace(core_link, LOG_NAME, "page recv intr disable failed [%d]", rtn);
+
+	queue_work(core_link->core_lgrp->core_ldev->workqueue, &core_link->work[core_link->an.done_work_num]);
+}
+
+void sl_core_hw_an_intr_hdlr(u64 *err_flgs, int num_err_flgs, void *data)
+{
+	struct sl_core_hw_intr_data *info;
+	struct sl_core_link         *core_link;
+
+	info = data;
+	core_link = info->link;
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"hdlr %s (link = 0x%p, intr = %u)",
+		info->log, core_link, info->intr_num);
+
+	sl_core_hw_intr_flgs_clr(core_link, SL_CORE_HW_INTR_AN_PAGE_RECV);
+
+	sl_core_hw_an_page_recv_intr(core_link);
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_an_lp.c b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_an_lp.c
new file mode 100644
index 000000000000..75ba235c555e
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_an_lp.c
@@ -0,0 +1,254 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2022,2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/workqueue.h>
+
+#include "sl_platform.h"
+#include "sl_core_link.h"
+#include "sl_core_str.h"
+#include "base/sl_core_log.h"
+#include "hw/sl_core_hw_intr.h"
+#include "data/sl_core_data_link.h"
+#include "hw/sl_core_hw_serdes_link.h"
+#include "hw/sl_core_hw_an.h"
+#include "hw/sl_core_hw_an_lp.h"
+
+#define LOG_NAME SL_CORE_HW_AN_LOG_NAME
+
+static void sl_core_an_lp_caps_get_callback(struct sl_core_link *link)
+{
+	int rtn;
+
+	sl_core_log_dbg(link, LOG_NAME, "lp caps get callback");
+
+	rtn = link->an.callbacks.lp_caps_get(link->an.tag,
+		&(link->an.lp_caps), link->an.lp_caps_state);
+	if (rtn != 0)
+		sl_core_log_warn_trace(link, LOG_NAME,
+				       "lp caps get callback - failed [%d]", rtn);
+}
+
+void sl_core_hw_an_lp_caps_get_cmd(struct sl_core_link *core_link,
+				   enum sl_core_link_state link_state,
+				   sl_core_link_an_callback_t callback,
+				   void *tag, struct sl_link_caps *caps, u32 timeout_ms, u32 flags)
+{
+	int rtn;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "lp caps get cmd");
+
+	sl_core_hw_an_stop(core_link);
+
+	core_link->an.link_state             = link_state;
+	core_link->an.tag                    = tag;
+	core_link->an.callbacks.lp_caps_get  = callback;
+	core_link->an.done_work_num          = SL_CORE_WORK_LINK_AN_LP_CAPS_GET_DONE;
+	core_link->an.my_caps                = *caps;
+
+	sl_core_data_link_an_lp_caps_state_set(core_link, SL_CORE_LINK_LP_CAPS_RUNNING);
+
+	core_link->timers[SL_CORE_TIMER_LINK_AN_LP_CAPS_GET].data.timeout_ms = timeout_ms;
+
+	/* test check */
+	if (core_link->an.use_test_caps) {
+		sl_core_log_warn_trace(core_link, LOG_NAME,
+				       "lp caps get cmd - using test caps");
+		core_link->an.lp_caps       = core_link->an.test_caps;
+		sl_core_data_link_an_lp_caps_state_set(core_link, SL_CORE_LINK_LP_CAPS_DATA);
+		sl_core_data_link_state_set(core_link, core_link->an.link_state);
+		sl_core_an_lp_caps_get_callback(core_link);
+		return;
+	}
+
+	memset(&(core_link->an.lp_caps), 0, sizeof(core_link->an.lp_caps));
+	core_link->an.lp_caps.magic = SL_CORE_LINK_AN_MAGIC;
+
+	if (!SL_PLATFORM_IS_HARDWARE(core_link->core_lgrp->core_ldev)) {
+		sl_core_data_link_state_set(core_link, core_link->an.link_state);
+		sl_core_an_lp_caps_get_callback(core_link);
+		return;
+	}
+
+	sl_core_timer_link_begin(core_link, SL_CORE_TIMER_LINK_AN_LP_CAPS_GET);
+
+	rtn = sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_AN_PAGE_RECV);
+	if (rtn != 0)
+		sl_core_log_warn_trace(core_link, LOG_NAME,
+				       "lp caps get cmd - an page recv disable failed [%d]", rtn);
+
+	queue_work(core_link->core_lgrp->core_ldev->workqueue, &core_link->work[SL_CORE_WORK_LINK_AN_LP_CAPS_GET]);
+}
+
+void sl_core_hw_an_lp_caps_get_work(struct work_struct *work)
+{
+	int                  rtn;
+	struct sl_core_link *core_link;
+	enum sl_core_link_state link_state;
+
+	core_link = container_of(work, struct sl_core_link, work[SL_CORE_WORK_LINK_AN_LP_CAPS_GET]);
+
+	sl_core_log_dbg(core_link, LOG_NAME, "up lp caps get work");
+
+	rtn = sl_core_data_link_state_get(core_link, &link_state);
+	if (rtn) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "lp caps get work - failed to get link state [%d]", rtn);
+		return;
+	}
+
+	if (link_state != SL_CORE_LINK_STATE_AN) {
+		sl_core_log_dbg(core_link, LOG_NAME, "up lp caps get work - invalid state (link_state = %u %s)",
+				link_state, sl_core_link_state_str(link_state));
+		return;
+	}
+
+	sl_core_hw_serdes_link_down(core_link);
+
+	rtn = sl_core_hw_serdes_link_up_an(core_link);
+	if (rtn != 0) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "lp caps get work hw_serdes_link_up_an failed [%d]", rtn);
+		sl_core_data_link_an_fail_cause_set(core_link,
+						    SL_CORE_HW_AN_FAIL_CAUSE_LP_CAPS_SERDES_LINK_UP_FAIL);
+		sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_AN_LP_CAPS_GET);
+		sl_core_hw_serdes_link_down(core_link);
+		sl_core_data_link_state_set(core_link, core_link->an.link_state);
+		sl_core_data_link_an_lp_caps_state_set(core_link, SL_CORE_LINK_LP_CAPS_ERROR);
+		sl_core_an_lp_caps_get_callback(core_link);
+		return;
+	}
+
+	sl_core_hw_an_init(core_link);
+
+	sl_core_hw_an_config(core_link);
+
+	sl_core_hw_an_tx_pages_encode(core_link, &(core_link->an.my_caps));
+
+	rtn = sl_core_hw_an_base_page_send(core_link);
+	if (rtn != 0)
+		sl_core_log_warn_trace(core_link, LOG_NAME,
+				       "lp caps get work an base page send failed [%d]", rtn);
+}
+
+void sl_core_hw_an_lp_caps_stop_cmd(struct sl_core_link *core_link)
+{
+	int rtn;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "lp caps stop cmd");
+
+	if (sl_core_data_link_an_lp_caps_state_get(core_link) == SL_CORE_LINK_LP_CAPS_NOT_RUNNING) {
+		sl_core_log_dbg(core_link, LOG_NAME, "lp caps stop cmd - already stopped");
+		return;
+	}
+
+	rtn = sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_AN_PAGE_RECV);
+	if (rtn != 0)
+		sl_core_log_warn_trace(core_link, LOG_NAME,
+				       "lp caps stop cmd - an page recv disable failed [%d]", rtn);
+
+	cancel_work_sync(&core_link->work[SL_CORE_WORK_LINK_AN_LP_CAPS_GET]);
+	cancel_work_sync(&core_link->work[SL_CORE_WORK_LINK_AN_LP_CAPS_GET_TIMEOUT]);
+
+	sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_AN_LP_CAPS_GET);
+
+	sl_core_data_link_an_lp_caps_state_set(core_link, SL_CORE_LINK_LP_CAPS_NOT_RUNNING);
+	sl_core_data_link_state_set(core_link, core_link->an.link_state);
+}
+
+void sl_core_hw_an_lp_caps_get_timeout_work(struct work_struct *work)
+{
+	int                  rtn;
+	struct sl_core_link *core_link;
+	enum sl_core_link_state link_state;
+
+	core_link = container_of(work, struct sl_core_link, work[SL_CORE_WORK_LINK_AN_LP_CAPS_GET_TIMEOUT]);
+
+	sl_core_log_dbg(core_link, LOG_NAME, "lp caps get timeout work");
+
+	rtn = sl_core_data_link_state_get(core_link, &link_state);
+	if (rtn) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "lp caps get timeout work - failed to get link state [%d]", rtn);
+		return;
+	}
+
+	if (link_state != SL_CORE_LINK_STATE_AN) {
+		sl_core_log_dbg(core_link, LOG_NAME, "lp caps get timeout work - invalid state (link_state = %u %s)",
+				link_state, sl_core_link_state_str(link_state));
+		return;
+	}
+
+	rtn = sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_AN_PAGE_RECV);
+	if (rtn != 0)
+		sl_core_log_warn_trace(core_link, LOG_NAME,
+				       "lp caps get timeout work an page recv disable failed [%d]", rtn);
+
+	sl_core_hw_an_stop(core_link);
+	sl_core_hw_serdes_link_down(core_link);
+
+	sl_core_data_link_state_set(core_link, core_link->an.link_state);
+	sl_core_data_link_an_lp_caps_state_set(core_link, SL_CORE_LINK_LP_CAPS_TIMEOUT);
+
+	sl_core_an_lp_caps_get_callback(core_link);
+}
+
+void sl_core_hw_an_lp_caps_get_done_work(struct work_struct *work)
+{
+	int                  rtn;
+	int                  x;
+	struct sl_core_link *core_link;
+	enum sl_core_link_state link_state;
+
+	core_link = container_of(work, struct sl_core_link, work[SL_CORE_WORK_LINK_AN_LP_CAPS_GET_DONE]);
+
+	sl_core_log_dbg(core_link, LOG_NAME, "lp caps get done work");
+
+	rtn = sl_core_data_link_state_get(core_link, &link_state);
+	if (rtn) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "lp caps get done work - failed to get link state [%d]", rtn);
+		return;
+	}
+
+	if (link_state != SL_CORE_LINK_STATE_AN) {
+		sl_core_log_dbg(core_link, LOG_NAME, "lp caps get done work - invalid state (link_state = %u %s)",
+				link_state, sl_core_link_state_str(link_state));
+		return;
+	}
+
+	for (x = 0; x < core_link->an.rx_count; ++x)
+		sl_core_log_dbg(core_link, LOG_NAME,
+				"lp caps get done work rx pages (%d = 0x%016llX)",
+			x, core_link->an.rx_pages[x]);
+
+	sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_AN_LP_CAPS_GET);
+
+	sl_core_hw_an_stop(core_link);
+	sl_core_hw_serdes_link_down(core_link);
+	sl_core_data_link_state_set(core_link, core_link->an.link_state);
+
+	if (core_link->an.state != SL_CORE_HW_AN_STATE_COMPLETE) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "lp caps get done work not complete");
+		sl_core_data_link_an_fail_cause_set(core_link,
+						    SL_CORE_HW_AN_FAIL_CAUSE_LP_CAPS_NOT_COMPLETE);
+		sl_core_data_link_an_lp_caps_state_set(core_link, SL_CORE_LINK_LP_CAPS_ERROR);
+		goto out;
+	}
+
+	rtn = sl_core_hw_an_rx_pages_decode(core_link,
+					    &(core_link->an.my_caps), &(core_link->an.lp_caps));
+	if (rtn) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "lp caps get done work hw_an_rx_pages_decode failure [%d]", rtn);
+		sl_core_data_link_an_lp_caps_state_set(core_link, SL_CORE_LINK_LP_CAPS_ERROR);
+		goto out;
+	}
+
+	sl_core_data_link_an_lp_caps_state_set(core_link, SL_CORE_LINK_LP_CAPS_DATA);
+
+out:
+	sl_core_an_lp_caps_get_callback(core_link);
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_an_up.c b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_an_up.c
new file mode 100644
index 000000000000..8ccbb815a4b2
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_an_up.c
@@ -0,0 +1,270 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2022,2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/workqueue.h>
+#include <linux/delay.h>
+
+#include "sl_core_link.h"
+#include "sl_core_str.h"
+#include "base/sl_core_log.h"
+#include "hw/sl_core_hw_intr.h"
+#include "data/sl_core_data_link.h"
+#include "hw/sl_core_hw_serdes_link.h"
+#include "hw/sl_core_hw_an.h"
+#include "hw/sl_core_hw_an_up.h"
+#include "hw/sl_core_hw_link.h"
+#include "sl_ctrl_link_counters.h"
+#include "sl_ctrl_link.h"
+
+#define LOG_NAME SL_CORE_HW_AN_LOG_NAME
+
+#define SL_CORE_HW_AN_RESTART_DELAY_MS     200
+#define SL_CORE_HW_AN_RESTART_DELAY_MS_MAX (SL_CORE_HW_AN_RESTART_DELAY_MS * 10)
+
+static void sl_core_hw_an_up_start_test_caps(struct sl_core_link *core_link)
+{
+	int rtn;
+	int bit;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "up start test caps");
+
+	core_link->core_lgrp->link_caps[core_link->num].pause_map =
+		(core_link->config.pause_map & core_link->an.test_caps.pause_map);
+	core_link->core_lgrp->link_caps[core_link->num].tech_map  =
+		(core_link->core_lgrp->config.tech_map & core_link->an.test_caps.tech_map);
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"up start test caps input (tech map = 0x%08X, 0x%08X, 0x%08X)",
+		core_link->core_lgrp->config.tech_map,
+		core_link->an.test_caps.tech_map,
+		core_link->core_lgrp->link_caps[core_link->num].tech_map);
+	if (core_link->core_lgrp->link_caps[core_link->num].tech_map) {
+		bit = 0;
+		while (core_link->core_lgrp->link_caps[core_link->num].tech_map >>= 1)
+			bit++;
+		core_link->core_lgrp->link_caps[core_link->num].tech_map = BIT(bit);
+	}
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"up start test caps result (tech map = 0x%08X)",
+			core_link->core_lgrp->link_caps[core_link->num].tech_map);
+	core_link->core_lgrp->link_caps[core_link->num].fec_map =
+		(core_link->core_lgrp->config.fec_map & core_link->an.test_caps.fec_map);
+	core_link->core_lgrp->link_caps[core_link->num].hpe_map =
+		(core_link->config.hpe_map & core_link->an.test_caps.hpe_map);
+
+	if (core_link->core_lgrp->link_caps[core_link->num].tech_map == 0) {
+		sl_core_log_err_trace(core_link, LOG_NAME, "up start test caps no match");
+		sl_core_data_link_an_fail_cause_set(core_link,
+						    SL_CORE_HW_AN_FAIL_CAUSE_TEST_CAPS_NOMATCH);
+		sl_core_data_link_last_up_fail_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_AUTONEG_NOMATCH_MAP);
+		rtn = sl_core_link_up_fail(core_link);
+		if (rtn)
+			sl_core_log_err_trace(core_link, LOG_NAME, "link down internal failed [%d]", rtn);
+
+		return;
+	}
+
+	sl_core_hw_link_up_after_an_start(core_link);
+}
+
+void sl_core_hw_an_up_start_work(struct work_struct *work)
+{
+	int                  rtn;
+	struct sl_core_link *core_link;
+	enum sl_core_link_state link_state;
+
+	core_link = container_of(work, struct sl_core_link, work[SL_CORE_WORK_LINK_AN_UP_START]);
+
+	sl_core_log_dbg(core_link, LOG_NAME, "up start work (link = 0x%p)", core_link);
+
+	rtn = sl_core_data_link_state_get(core_link, &link_state);
+	if (rtn) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "up start work - failed to get link state [%d]", rtn);
+		return;
+	}
+
+	if (link_state != SL_CORE_LINK_STATE_AN) {
+		sl_core_log_dbg(core_link, LOG_NAME, "up start work - invalid state (link_state = %u %s)",
+				link_state, sl_core_link_state_str(link_state));
+		return;
+	}
+
+	sl_core_hw_an_stop(core_link);
+
+	/* init caps */
+	memset(&(core_link->core_lgrp->link_caps[core_link->num]), 0, sizeof(struct sl_link_caps));
+
+	core_link->an.done_work_num = SL_CORE_WORK_LINK_AN_UP_DONE;
+
+	sl_core_data_link_timeouts(core_link);
+
+	sl_core_timer_link_begin(core_link, SL_CORE_TIMER_LINK_UP);
+
+	if (core_link->an.use_test_caps) {
+		sl_core_hw_an_up_start_test_caps(core_link);
+		return;
+	}
+
+	queue_work(core_link->core_lgrp->core_ldev->workqueue, &core_link->work[SL_CORE_WORK_LINK_AN_UP]);
+}
+
+static void sl_core_hw_an_up(struct sl_core_link *core_link)
+{
+	int                  rtn;
+	struct sl_link_caps  my_caps;
+	struct sl_ctrl_link *ctrl_link __free(sl_ctrl_link_put) = NULL;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "up");
+
+	ctrl_link = sl_ctrl_link_get(core_link->core_lgrp->core_ldev->num,
+				     core_link->core_lgrp->num, core_link->num);
+	if (ctrl_link)
+		SL_CTRL_LINK_COUNTER_INC(ctrl_link, LINK_HW_AN_ATTEMPT);
+
+	sl_core_hw_an_init(core_link);
+
+	sl_core_hw_an_config(core_link);
+
+	my_caps.tech_map  = core_link->core_lgrp->config.tech_map;
+	my_caps.fec_map   = core_link->core_lgrp->config.fec_map;
+	my_caps.pause_map = core_link->config.pause_map;
+	my_caps.hpe_map   = core_link->config.hpe_map;
+	sl_core_hw_an_tx_pages_encode(core_link, &(my_caps));
+
+	rtn = sl_core_hw_an_base_page_send(core_link);
+	if (rtn != 0)
+		sl_core_log_warn_trace(core_link, LOG_NAME,
+				       "up an base page send failed [%d]", rtn);
+}
+
+void sl_core_hw_an_up_work(struct work_struct *work)
+{
+	int                  rtn;
+	struct sl_core_link *core_link;
+	enum sl_core_link_state link_state;
+
+	core_link = container_of(work, struct sl_core_link, work[SL_CORE_WORK_LINK_AN_UP]);
+
+	sl_core_log_dbg(core_link, LOG_NAME, "up work");
+
+	rtn = sl_core_data_link_state_get(core_link, &link_state);
+	if (rtn) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "up work - failed to get link state [%d]", rtn);
+		return;
+	}
+
+	if (link_state != SL_CORE_LINK_STATE_AN) {
+		sl_core_log_dbg(core_link, LOG_NAME, "up work - invalid state (link_state = %u %s)",
+				link_state, sl_core_link_state_str(link_state));
+		return;
+	}
+
+	rtn = sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_AN_PAGE_RECV);
+	if (rtn != 0)
+		sl_core_log_warn_trace(core_link, LOG_NAME,
+				       "up work an page recv disable failed [%d]", rtn);
+
+	sl_core_hw_serdes_link_down(core_link);
+
+	rtn = sl_core_hw_serdes_link_up_an(core_link);
+	if (rtn != 0) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "up work hw_serdes_link_up_an failed [%d]", rtn);
+		sl_core_data_link_an_fail_cause_set(core_link,
+						    SL_CORE_HW_AN_FAIL_CAUSE_SERDES_LINK_UP_FAIL);
+
+		sl_core_link_up_fail(core_link);
+		if (rtn)
+			sl_core_log_err_trace(core_link, LOG_NAME, "link down internal failed [%d]", rtn);
+
+		return;
+	}
+
+	core_link->an.restart_sleep_ms = SL_CORE_HW_AN_RESTART_DELAY_MS;
+
+	sl_core_hw_an_up(core_link);
+}
+
+static void sl_core_an_up_restart(struct sl_core_link *core_link)
+{
+	sl_core_log_dbg(core_link, LOG_NAME, "up restart");
+
+	sl_core_hw_an_up(core_link);
+}
+
+void sl_core_hw_an_up_done_work(struct work_struct *work)
+{
+	int                  rtn;
+	int                  x;
+	struct sl_core_link *core_link;
+	struct sl_link_caps  my_caps;
+	enum sl_core_link_state link_state;
+
+	core_link = container_of(work, struct sl_core_link, work[SL_CORE_WORK_LINK_AN_UP_DONE]);
+
+	sl_core_log_dbg(core_link, LOG_NAME, "up done work");
+
+	rtn = sl_core_data_link_state_get(core_link, &link_state);
+	if (rtn) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "up done work - failed to get link state [%d]", rtn);
+		return;
+	}
+
+	if (link_state != SL_CORE_LINK_STATE_AN) {
+		sl_core_log_dbg(core_link, LOG_NAME, "up done work - invalid state (link_state = %u %s)",
+				link_state, sl_core_link_state_str(link_state));
+		return;
+	}
+
+	sl_core_hw_an_stop(core_link);
+
+	for (x = 0; x < core_link->an.rx_count; ++x)
+		sl_core_log_dbg(core_link, LOG_NAME,
+				"up done work rx pages (%d = 0x%016llX)",
+			x, core_link->an.rx_pages[x]);
+
+	if (core_link->an.state != SL_CORE_HW_AN_STATE_COMPLETE) {
+		/* try again if asked to */
+		if (is_flag_set(core_link->config.flags, SL_LINK_CONFIG_OPT_AUTONEG_CONTINUOUS_ENABLE)) {
+			sl_core_log_dbg(core_link, LOG_NAME,
+					"up done work restart (delay = %dms)", core_link->an.restart_sleep_ms);
+			msleep(core_link->an.restart_sleep_ms);
+			if ((core_link->an.restart_sleep_ms) &&
+			    (core_link->an.restart_sleep_ms < SL_CORE_HW_AN_RESTART_DELAY_MS_MAX))
+				core_link->an.restart_sleep_ms += SL_CORE_HW_AN_RESTART_DELAY_MS;
+			sl_core_an_up_restart(core_link);
+			return;
+		}
+		sl_core_log_err_trace(core_link, LOG_NAME, "up done work auto neg not complete");
+		sl_core_data_link_an_fail_cause_set(core_link,
+						    SL_CORE_HW_AN_FAIL_CAUSE_NOT_COMPLETE);
+		goto out_down;
+	}
+
+	my_caps.tech_map  = core_link->core_lgrp->config.tech_map;
+	my_caps.fec_map   = core_link->core_lgrp->config.fec_map;
+	my_caps.pause_map = core_link->config.pause_map;
+	my_caps.hpe_map   = core_link->config.hpe_map;
+	rtn = sl_core_hw_an_rx_pages_decode(core_link, &my_caps,
+					    &(core_link->core_lgrp->link_caps[core_link->num]));
+	if (rtn) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "up done work hw_an_rx_pages_decode failure [%d]", rtn);
+		sl_core_data_link_an_fail_cause_set(core_link,
+						    SL_CORE_HW_AN_FAIL_CAUSE_PAGES_DECODE_FAIL);
+		goto out_down;
+	}
+
+	sl_core_hw_link_up_after_an_start(core_link);
+
+	return;
+
+out_down:
+
+	sl_core_data_link_last_up_fail_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_AUTONEG_MAP);
+	sl_core_link_up_fail(core_link);
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_intr.c b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_intr.c
new file mode 100644
index 000000000000..6564c9cb5613
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_intr.c
@@ -0,0 +1,222 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2022-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/workqueue.h>
+
+#include "sl_core_link.h"
+#include "base/sl_core_log.h"
+#include "hw/sl_core_hw_intr.h"
+#include "hw/sl_core_hw_io.h"
+#include "hw/sl_core_hw_intr.h"
+#include "hw/sl_core_hw_an.h"
+
+#define LOG_NAME SL_CORE_HW_INTR_LOG_NAME
+
+static void sl_core_hw_intr_flgs_clr_source(struct sl_core_link *core_link, u32 intr_num)
+{
+	int x;
+	u64 addr;
+	u32 port;
+
+	port = core_link->core_lgrp->num;
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"flgs clr source (port = %d, intr = %d, "
+		"flgs = 0x%016llX, 0x%016llX, 0x%016llX, 0x%016llX)",
+		port, intr_num,
+		core_link->intrs[intr_num].source[0],
+		core_link->intrs[intr_num].source[1],
+		core_link->intrs[intr_num].source[2],
+		core_link->intrs[intr_num].source[3]);
+
+	addr = SS2_PORT_PML_ERR_CLR;
+	for (x = 0; x < SL_CORE_HW_INTR_FLGS_COUNT; ++x, addr += 8)
+		sl_core_write64(core_link, addr, core_link->intrs[intr_num].source[x]);
+	sl_core_flush64(core_link, SS2_PORT_PML_ERR_CLR);
+}
+
+void sl_core_hw_intr_hdlr(u64 *err_flgs, int num_err_flgs, void *data)
+{
+	int                          rtn;
+	struct sl_core_hw_intr_data *info;
+	struct sl_core_link         *core_link;
+	int                          x;
+
+	info = data;
+	core_link = info->link;
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"hdlr - %s (link = 0x%p, intr = %u, work = %u)",
+		info->log, core_link, info->intr_num, info->work_num);
+
+	rtn = sl_core_hw_intr_flgs_disable(core_link, info->intr_num);
+	if (rtn != 0)
+		sl_core_log_warn_trace(core_link, LOG_NAME,
+				       "hdlr - %s - flgs disable failed [%d]",
+			info->log, rtn);
+
+	for (x = 0; x < SL_CORE_HW_INTR_FLGS_COUNT; ++x)
+		core_link->intrs[info->intr_num].source[x] |= err_flgs[x];
+
+	sl_core_hw_intr_flgs_clr_source(core_link, info->intr_num);
+
+	queue_work(core_link->core_lgrp->core_ldev->workqueue, &core_link->work[info->work_num]);
+}
+
+int sl_core_hw_intr_hdlr_register(struct sl_core_link *core_link)
+{
+	int rtn;
+	int x;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "register");
+
+	for (x = 0; x < SL_CORE_HW_INTR_COUNT; ++x) {
+		if (x == SL_CORE_HW_INTR_AN_PAGE_RECV)
+			rtn = sl_core_hw_intr_register(core_link, core_link->intrs[x].flgs,
+						       sl_core_hw_an_intr_hdlr, &(core_link->intrs[x].data));
+		else if (x == SL_CORE_HW_INTR_LANE_DEGRADE)
+			continue;
+		else
+			rtn = sl_core_hw_intr_register(core_link, core_link->intrs[x].flgs,
+						       sl_core_hw_intr_hdlr, &(core_link->intrs[x].data));
+		if (rtn != 0) {
+			sl_core_log_err(core_link, LOG_NAME,
+					"register - %d failed [%d]", x, rtn);
+			return rtn;
+		}
+	}
+
+	return 0;
+}
+
+void sl_core_hw_intr_hdlr_unregister(struct sl_core_link *core_link)
+{
+	int rtn;
+	int x;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "unregister");
+
+	for (x = 0; x < SL_CORE_HW_INTR_COUNT; ++x) {
+		if (x == SL_CORE_HW_INTR_AN_PAGE_RECV)
+			rtn = sl_core_hw_intr_unregister(core_link, core_link->intrs[x].flgs,
+							 sl_core_hw_an_intr_hdlr);
+		else
+			rtn = sl_core_hw_intr_unregister(core_link, core_link->intrs[x].flgs,
+							 sl_core_hw_intr_hdlr);
+		if (rtn != 0)
+			sl_core_log_warn_trace(core_link, LOG_NAME,
+					       "unregister - %d failed [%d]", x, rtn);
+	}
+}
+
+void sl_core_hw_intr_flgs_check(struct sl_core_link *core_link, u32 intr_num)
+{
+	int x;
+	u64 addr;
+	u64 data64;
+	u32 port;
+
+	port = core_link->core_lgrp->num;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "flgs check (port = %d)", port);
+
+	addr = SS2_PORT_PML_ERR_FLG;
+	for (x = 0; x < SL_CORE_HW_INTR_FLGS_COUNT; ++x, addr += 8) {
+		sl_core_read64(core_link, addr, &data64);
+		if ((data64 & core_link->intrs[intr_num].flgs[x]) != 0) {
+			sl_core_log_dbg(core_link, LOG_NAME,
+					"flgs check (intr = %d, 0x%016llX = 0x%016llX)",
+				intr_num, addr, data64);
+		}
+	}
+}
+
+void sl_core_hw_intr_flgs_clr(struct sl_core_link *core_link, u32 intr_num)
+{
+	int x;
+	u64 addr;
+	u32 port;
+
+	port = core_link->core_lgrp->num;
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"flgs clr (port = %d, intr = %d, "
+		"flgs = 0x%016llX, 0x%016llX, 0x%016llX, 0x%016llX)",
+		port, intr_num,
+		core_link->intrs[intr_num].flgs[0],
+		core_link->intrs[intr_num].flgs[1],
+		core_link->intrs[intr_num].flgs[2],
+		core_link->intrs[intr_num].flgs[3]);
+
+	addr = SS2_PORT_PML_ERR_CLR;
+	for (x = 0; x < SL_CORE_HW_INTR_FLGS_COUNT; ++x, addr += 8)
+		sl_core_write64(core_link, addr, core_link->intrs[intr_num].flgs[x]);
+	sl_core_flush64(core_link, SS2_PORT_PML_ERR_CLR);
+}
+
+int sl_core_hw_intr_flgs_enable(struct sl_core_link *core_link, u32 intr_num)
+{
+	int rtn;
+	u32 port;
+
+	port = core_link->core_lgrp->num;
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"flgs enable (port = %d, intr = %d, "
+		"flgs = 0x%016llX, 0x%016llX, 0x%016llX, 0x%016llX)",
+		port, intr_num,
+		core_link->intrs[intr_num].flgs[0],
+		core_link->intrs[intr_num].flgs[1],
+		core_link->intrs[intr_num].flgs[2],
+		core_link->intrs[intr_num].flgs[3]);
+
+	memset(&(core_link->intrs[intr_num].source), 0, sizeof(core_link->intrs[intr_num].source));
+
+	if (intr_num == SL_CORE_HW_INTR_AN_PAGE_RECV)
+		rtn = sl_core_hw_intr_enable(core_link,
+					     core_link->intrs[intr_num].flgs, sl_core_hw_an_intr_hdlr);
+	else
+		rtn = sl_core_hw_intr_enable(core_link,
+					     core_link->intrs[intr_num].flgs, sl_core_hw_intr_hdlr);
+	if (rtn != 0) {
+		if (rtn != -EALREADY)
+			sl_core_log_err_trace(core_link, LOG_NAME,
+					      "flgs enable failed [%d]", rtn);
+		return rtn;
+	}
+
+	return 0;
+}
+
+int sl_core_hw_intr_flgs_disable(struct sl_core_link *core_link, u32 intr_num)
+{
+	int rtn;
+	u32 port;
+
+	port = core_link->core_lgrp->num;
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"flgs disable (port = %d, intr = %d, "
+		"flgs = 0x%016llX, 0x%016llX, 0x%016llX, 0x%016llX)",
+		port, intr_num,
+		core_link->intrs[intr_num].flgs[0],
+		core_link->intrs[intr_num].flgs[1],
+		core_link->intrs[intr_num].flgs[2],
+		core_link->intrs[intr_num].flgs[3]);
+
+	if (intr_num == SL_CORE_HW_INTR_AN_PAGE_RECV)
+		rtn = sl_core_hw_intr_disable(core_link,
+					      core_link->intrs[intr_num].flgs, sl_core_hw_an_intr_hdlr);
+	else
+		rtn = sl_core_hw_intr_disable(core_link,
+					      core_link->intrs[intr_num].flgs, sl_core_hw_intr_hdlr);
+	if (rtn != 0) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "flgs disable failed [%d]", rtn);
+		return rtn;
+	}
+
+	return 0;
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_intr_llr.c b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_intr_llr.c
new file mode 100644
index 000000000000..79680a74c204
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_intr_llr.c
@@ -0,0 +1,181 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2024,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/workqueue.h>
+
+#include "sl_core_llr.h"
+#include "base/sl_core_log.h"
+#include "hw/sl_core_hw_io.h"
+#include "hw/sl_core_hw_intr_llr.h"
+
+#define LOG_NAME SL_CORE_HW_INTR_LLR_LOG_NAME
+
+/**
+ * sl_core_hw_intr_llr_hdlr - Interrupt handler for LLR error flags.
+ * @err_flgs: Pointer to an array of set error flags.
+ * @num_err_flgs: Number of error flags in the array.
+ * @data: Pointer context for handling the interrupt.
+ *
+ * Context: Interrupt context.
+ */
+void sl_core_hw_intr_llr_hdlr(u64 *err_flgs, int num_err_flgs, void *data)
+{
+	int                              rtn;
+	struct sl_core_hw_intr_llr_data *info;
+	struct sl_core_llr              *core_llr;
+
+	info = data;
+	core_llr = info->core_llr;
+
+	sl_core_log_dbg(core_llr, LOG_NAME,
+			"hdlr - %s (llr = 0x%p, intr = %d, work = %d)",
+		info->log, core_llr, info->intr_num, info->work_num);
+
+	rtn = sl_core_hw_intr_llr_flgs_disable(core_llr, info->intr_num);
+	if (rtn != 0)
+		sl_core_log_warn_trace(core_llr, LOG_NAME,
+				       "hdlr - %s - flgs disable failed [%d]",
+			info->log, rtn);
+
+	memcpy(&(core_llr->intrs[info->intr_num].source), err_flgs,
+	       sizeof(core_llr->intrs[info->intr_num].source));
+
+	queue_work(core_llr->core_lgrp->core_ldev->workqueue, &core_llr->work[info->work_num]);
+}
+
+int sl_core_hw_intr_llr_hdlr_register(struct sl_core_llr *core_llr)
+{
+	int rtn;
+	int x;
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "register");
+
+	for (x = 0; x < SL_CORE_HW_INTR_LLR_COUNT; ++x) {
+		rtn = sl_core_hw_intr_llr_register(core_llr, core_llr->intrs[x].flgs,
+						   sl_core_hw_intr_llr_hdlr, &(core_llr->intrs[x].data));
+		if (rtn != 0) {
+			sl_core_log_err_trace(core_llr, LOG_NAME, "register - %d failed [%d]", x, rtn);
+			return rtn;
+		}
+	}
+
+	return 0;
+}
+
+void sl_core_hw_intr_llr_hdlr_unregister(struct sl_core_llr *core_llr)
+{
+	int rtn;
+	int x;
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "unregister");
+
+	for (x = 0; x < SL_CORE_HW_INTR_LLR_COUNT; ++x) {
+		rtn = sl_core_hw_intr_llr_unregister(core_llr, core_llr->intrs[x].flgs,
+						     sl_core_hw_intr_llr_hdlr);
+		if (rtn != 0)
+			sl_core_log_warn_trace(core_llr, LOG_NAME,
+					       "unregister - %d failed [%d]", x, rtn);
+	}
+}
+
+void sl_core_hw_intr_llr_flgs_check(struct sl_core_llr *core_llr, u32 intr_num)
+{
+	int x;
+	u64 addr;
+	u64 data64;
+	u32 port;
+
+	port = core_llr->core_lgrp->num;
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "flgs check (port = %d)", port);
+
+	addr = SS2_PORT_PML_ERR_FLG;
+	for (x = 0; x < SL_CORE_HW_INTR_LLR_FLGS_COUNT; ++x, addr += 8) {
+		sl_core_llr_read64(core_llr, addr, &data64);
+		if ((data64 & core_llr->intrs[intr_num].flgs[x]) != 0) {
+			sl_core_log_dbg(core_llr, LOG_NAME,
+					"flgs check (intr = %d, 0x%016llX = 0x%016llX)",
+				intr_num, addr, data64);
+		}
+	}
+}
+
+void sl_core_hw_intr_llr_flgs_clr(struct sl_core_llr *core_llr, u32 intr_num)
+{
+	int x;
+	u64 addr;
+	u32 port;
+
+	port = core_llr->core_lgrp->num;
+
+	sl_core_log_dbg(core_llr, LOG_NAME,
+			"flgs clr (port = %d, intr = %d, "
+		"flgs = 0x%016llX, 0x%016llX, 0x%016llX, 0x%016llX)",
+		port, intr_num,
+		core_llr->intrs[intr_num].flgs[0],
+		core_llr->intrs[intr_num].flgs[1],
+		core_llr->intrs[intr_num].flgs[2],
+		core_llr->intrs[intr_num].flgs[3]);
+
+	addr = SS2_PORT_PML_ERR_CLR;
+	for (x = 0; x < SL_CORE_HW_INTR_LLR_FLGS_COUNT; ++x, addr += 8)
+		sl_core_llr_write64(core_llr, addr, core_llr->intrs[intr_num].flgs[x]);
+	sl_core_llr_flush64(core_llr, SS2_PORT_PML_ERR_CLR);
+}
+
+int sl_core_hw_intr_llr_flgs_enable(struct sl_core_llr *core_llr, u32 intr_num)
+{
+	int rtn;
+	u32 port;
+
+	port = core_llr->core_lgrp->num;
+
+	sl_core_log_dbg(core_llr, LOG_NAME,
+			"flgs enable (port = %d, intr = %d, "
+		"flgs = 0x%016llX, 0x%016llX, 0x%016llX, 0x%016llX)",
+		port, intr_num,
+		core_llr->intrs[intr_num].flgs[0],
+		core_llr->intrs[intr_num].flgs[1],
+		core_llr->intrs[intr_num].flgs[2],
+		core_llr->intrs[intr_num].flgs[3]);
+
+	rtn = sl_core_hw_intr_llr_enable(core_llr,
+					 core_llr->intrs[intr_num].flgs, sl_core_hw_intr_llr_hdlr);
+	if (rtn != 0) {
+		if (rtn != -EALREADY)
+			sl_core_log_err_trace(core_llr, LOG_NAME,
+					      "flgs enable failed [%d]", rtn);
+		return rtn;
+	}
+
+	return 0;
+}
+
+int sl_core_hw_intr_llr_flgs_disable(struct sl_core_llr *core_llr, u32 intr_num)
+{
+	int rtn;
+	u32 port;
+
+	port = core_llr->core_lgrp->num;
+
+	sl_core_log_dbg(core_llr, LOG_NAME,
+			"flgs disable (port = %d, intr = %d, "
+		"flgs = 0x%016llX, 0x%016llX, 0x%016llX, 0x%016llX)",
+		port, intr_num,
+		core_llr->intrs[intr_num].flgs[0],
+		core_llr->intrs[intr_num].flgs[1],
+		core_llr->intrs[intr_num].flgs[2],
+		core_llr->intrs[intr_num].flgs[3]);
+
+	rtn = sl_core_hw_intr_llr_disable(core_llr,
+					  core_llr->intrs[intr_num].flgs, sl_core_hw_intr_llr_hdlr);
+	if (rtn != 0) {
+		sl_core_log_err_trace(core_llr, LOG_NAME,
+				      "flgs disable failed [%d]", rtn);
+		return rtn;
+	}
+
+	return 0;
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_link.c b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_link.c
new file mode 100644
index 000000000000..4e6f3bdfbbbd
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_link.c
@@ -0,0 +1,2172 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2022-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/spinlock.h>
+#include <linux/workqueue.h>
+#include <linux/delay.h>
+#include <linux/ktime.h>
+
+#include "sl_platform.h"
+#include "sl_ctrl_link.h"
+#include "sl_core_link.h"
+#include "sl_core_str.h"
+#include "sl_media_jack.h"
+#include "sl_media_lgrp.h"
+#include "base/sl_core_log.h"
+#include "hw/sl_core_hw_intr.h"
+#include "data/sl_core_data_lgrp.h"
+#include "data/sl_core_data_link.h"
+#include "hw/sl_core_hw_link.h"
+#include "hw/sl_core_hw_mac.h"
+#include "hw/sl_core_hw_an.h"
+#include "hw/sl_core_hw_serdes_link.h"
+#include "hw/sl_core_hw_serdes_lane.h"
+#include "hw/sl_core_hw_settings.h"
+#include "hw/sl_core_hw_pcs.h"
+#include "hw/sl_core_hw_fec.h"
+#include "hw/sl_core_hw_io.h"
+#include "hw/sl_core_hw_reset.h"
+#include "sl_ctrl_lgrp.h"
+#include "sl_ctrl_link_counters.h"
+
+#define LOG_NAME SL_CORE_HW_LINK_LOG_NAME
+
+static void sl_core_hw_link_off(struct sl_core_link *core_link)
+{
+	struct sl_core_mac    *core_mac;
+	struct sl_core_llr    *core_llr;
+	u64                   rx_state;
+	u64                   tx_state;
+	struct sl_media_lgrp *media_lgrp;
+	u8		      temperature_state;
+	int		      rtn;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "link off");
+
+	core_mac = sl_core_mac_get(core_link->core_lgrp->core_ldev->num,
+				   core_link->core_lgrp->num, core_link->num);
+	core_llr = sl_core_llr_get(core_link->core_lgrp->core_ldev->num,
+				   core_link->core_lgrp->num, core_link->num);
+	media_lgrp = sl_media_lgrp_get(core_link->core_lgrp->core_ldev->num,
+				       core_link->core_lgrp->num);
+
+	if (core_llr)
+		sl_core_llr_stop(core_link->core_lgrp->core_ldev->num,
+				 core_link->core_lgrp->num, core_link->num);
+
+	msleep(100);
+
+	if (core_mac) {
+		rx_state = sl_core_hw_mac_rx_state_get(core_mac);
+		tx_state = sl_core_hw_mac_tx_state_get(core_mac);
+		/* stop TX mac before PCS so we don't lock up PCS */
+		sl_core_hw_mac_tx_stop(core_mac);
+	}
+
+	sl_core_hw_pcs_stop(core_link);
+
+	if (core_mac)
+		sl_core_hw_mac_rx_stop(core_mac);
+
+	sl_core_hw_serdes_link_down(core_link);
+
+	rtn  = sl_media_jack_cable_temp_state_get(media_lgrp->media_jack, &temperature_state);
+	if (rtn)
+		sl_core_log_warn_trace(core_link, LOG_NAME, "link off cable_temp_state_get failed [%d]", rtn);
+
+	if (temperature_state == SL_MEDIA_JACK_TEMP_STATE_HOT)
+		sl_media_jack_cable_low_power_set(media_lgrp->media_jack);
+
+	/* resetting the link resets the LLR which is needed to reset ordered sets */
+	sl_core_hw_reset_link(core_link);
+
+	if (core_mac) {
+		if (tx_state == SL_CORE_MAC_STATE_ON)
+			sl_core_hw_mac_tx_start(core_mac);
+		if (rx_state == SL_CORE_MAC_STATE_ON)
+			sl_core_hw_mac_rx_start(core_mac);
+	}
+}
+
+static void sl_core_hw_link_high_ser_intr_work_priv(struct sl_core_link *core_link)
+{
+	int  rtn;
+	enum sl_core_link_state link_state;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "high SER intr work priv");
+
+	sl_core_data_link_info_map_set(core_link, SL_CORE_INFO_MAP_HIGH_SER);
+
+	sl_core_log_warn_trace(core_link, LOG_NAME, "high symbol error ratio occurred");
+
+	while (sl_core_hw_intr_flgs_enable(core_link, SL_CORE_HW_INTR_LINK_HIGH_SER) == -EALREADY) {
+		rtn = sl_core_data_link_state_get(core_link, &link_state);
+		if (rtn) {
+			sl_core_log_err_trace(core_link, LOG_NAME,
+					      "high SER intr work priv link_state_get failed [%d]", rtn);
+			return;
+		}
+
+		switch (link_state) {
+		case SL_CORE_LINK_STATE_GOING_DOWN:
+		case SL_CORE_LINK_STATE_CANCELING:
+		case SL_CORE_LINK_STATE_TIMEOUT:
+			sl_core_log_err(core_link, LOG_NAME,
+					"high SER intr work priv invalid state (state = %u %s)",
+					link_state, sl_core_link_state_str(link_state));
+			return;
+		default:
+			sl_core_log_dbg(core_link, LOG_NAME,
+					"high SER intr work priv clearing flags (state = %u %s)",
+					link_state, sl_core_link_state_str(link_state));
+			usleep_range(10000, 12000);
+			sl_core_hw_intr_flgs_clr(core_link, SL_CORE_HW_INTR_LINK_HIGH_SER);
+			continue;
+		}
+	}
+
+	sl_core_data_link_info_map_clr(core_link, SL_CORE_INFO_MAP_HIGH_SER);
+}
+
+void sl_core_hw_link_up_callback(struct sl_core_link *core_link, struct sl_core_link_up_info *core_link_up_info)
+{
+	int rtn;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "up callback (callback = 0x%p, state = %d %s)",
+			core_link->link.callbacks.up, core_link_up_info->state,
+			sl_link_state_str(core_link_up_info->state));
+
+	rtn = core_link->link.callbacks.up(core_link->link.tags.up, core_link_up_info);
+	if (rtn != 0)
+		sl_core_log_warn_trace(core_link, LOG_NAME, "up callback failed [%d]", rtn);
+}
+
+static void sl_core_hw_link_down_callback(struct sl_core_link *core_link)
+{
+	sl_core_link_down_callback_t callback;
+	void *tag;
+	int rtn;
+	u64 info_map;
+	u64 down_cause_map;
+	u32 state;
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"down callback (callback = 0x%p)", core_link->link.callbacks.down);
+
+	spin_lock(&core_link->link.data_lock);
+	state          = core_link->link.state;
+	down_cause_map = core_link->link.last_down_cause_map[core_link->link.last_down_entry_num];
+	info_map       = core_link->info_map;
+	callback = core_link->link.callbacks.down;
+	tag = core_link->link.tags.down;
+	core_link->link.callbacks.down = NULL;
+	core_link->link.tags.down = NULL;
+	spin_unlock(&core_link->link.data_lock);
+
+	if (!callback)
+		return;
+
+	rtn = callback(tag, state, down_cause_map, info_map);
+	if (rtn != 0)
+		sl_core_log_warn_trace(core_link, LOG_NAME, "down callback failed [%d]", rtn);
+}
+
+static int sl_core_hw_link_media_check(struct sl_core_link *core_link)
+{
+	struct sl_media_lgrp *media_lgrp;
+	int                   rtn;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "media check (link = 0x%p)", core_link);
+
+	if (is_flag_set(sl_core_data_lgrp_config_flags_get(core_link->core_lgrp),
+			SL_LGRP_CONFIG_OPT_SERDES_LOOPBACK_ENABLE)) {
+		sl_core_log_dbg(core_link, LOG_NAME, "media check skipping serdes loopback set");
+		return 0;
+	}
+
+	sl_core_data_link_info_map_set(core_link, SL_CORE_INFO_MAP_MEDIA_CHECK);
+
+	media_lgrp = sl_media_lgrp_get(core_link->core_lgrp->core_ldev->num, core_link->core_lgrp->num);
+
+	if (sl_media_lgrp_is_cable_unsupported(media_lgrp) &&
+	    !sl_core_link_policy_is_use_unsupported_cable_set(core_link)) {
+		sl_core_log_warn_trace(core_link, LOG_NAME, "media check cable unsupported and override not set");
+		sl_core_data_link_last_up_fail_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_UNSUPPORTED_CABLE_MAP);
+		rtn = sl_core_link_up_fail(core_link);
+		if (rtn)
+			sl_core_log_err_trace(core_link, LOG_NAME, "media check link_up_fail failed [%d]", rtn);
+		rtn = -EINVAL;
+		goto out;
+	}
+
+	if (media_lgrp->media_jack->is_supported_ss200_cable &&
+	    !sl_core_link_policy_is_use_supported_ss200_cable_set(core_link)) {
+		sl_core_log_warn_trace(core_link, LOG_NAME, "media check cable supported ss200 and override not set");
+		sl_core_data_link_last_up_fail_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_SS200_CABLE_MAP);
+		rtn = sl_core_link_up_fail(core_link);
+		if (rtn)
+			sl_core_log_err_trace(core_link, LOG_NAME, "media check link_up_fail failed [%d]", rtn);
+		rtn = -EINVAL;
+		goto out;
+	}
+
+	if (sl_media_lgrp_media_has_error(media_lgrp) &&
+	    !sl_core_link_policy_is_ignore_media_errors_set(core_link) &&
+		!media_lgrp->media_jack->is_supported_ss200_cable) {
+		sl_core_log_warn_trace(core_link, LOG_NAME, "media check error and override not set");
+		sl_core_data_link_last_up_fail_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_MEDIA_ERROR_MAP);
+		rtn = sl_core_link_up_fail(core_link);
+		if (rtn)
+			sl_core_log_err_trace(core_link, LOG_NAME, "media check link_up_fail failed [%d]", rtn);
+		rtn = -EINVAL;
+		goto out;
+	}
+
+	sl_core_data_link_info_map_set(core_link, SL_CORE_INFO_MAP_MEDIA_OK);
+	rtn = 0;
+
+out:
+	sl_core_data_link_info_map_clr(core_link, SL_CORE_INFO_MAP_MEDIA_CHECK);
+
+	return rtn;
+}
+
+void sl_core_hw_link_up_cmd(struct sl_core_link *core_link,
+			    sl_core_link_up_callback_t callback, void *tag)
+{
+	int rtn;
+
+	sl_core_data_link_info_map_clr(core_link, SL_CORE_INFO_MAP_NUM_BITS);
+
+	sl_core_data_link_is_last_down_new_set(core_link, true);
+	sl_core_data_link_is_last_up_fail_new_set(core_link, true);
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"up cmd (link = 0x%p, callback = 0x%p, flags = 0x%X)",
+			core_link, callback, core_link->config.flags);
+
+	core_link->link.tags.up      = tag;
+	core_link->link.callbacks.up = callback;
+
+	rtn = sl_core_hw_link_media_check(core_link);
+	if (rtn != 0) {
+		sl_core_log_err_trace(core_link, LOG_NAME, "up cmd link_media_check failed [%d]", rtn);
+		return;
+	}
+
+	sl_core_link_ccw_warn_limit_crossed_set(core_link->core_lgrp->core_ldev->num, core_link->core_lgrp->num,
+						core_link->num, false);
+	sl_core_link_ucw_warn_limit_crossed_set(core_link->core_lgrp->core_ldev->num, core_link->core_lgrp->num,
+						core_link->num, false);
+
+	/* clear link caps */
+	memset(core_link->core_lgrp->link_caps, 0, sizeof(core_link->core_lgrp->link_caps));
+
+	if (is_flag_set(core_link->config.flags, SL_LINK_CONFIG_OPT_AUTONEG_ENABLE))
+		queue_work(core_link->core_lgrp->core_ldev->workqueue, &core_link->work[SL_CORE_WORK_LINK_AN_UP_START]);
+	else
+		queue_work(core_link->core_lgrp->core_ldev->workqueue, &core_link->work[SL_CORE_WORK_LINK_UP_START]);
+}
+
+void sl_core_hw_link_up_start_work(struct work_struct *work)
+{
+	int                   rtn;
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_core_link  *core_link;
+	enum sl_core_link_state link_state;
+
+	core_link = container_of(work, struct sl_core_link, work[SL_CORE_WORK_LINK_UP_START]);
+
+	sl_core_log_dbg(core_link, LOG_NAME, "up start work (link = 0x%p)", core_link);
+
+	rtn = sl_core_data_link_state_get(core_link, &link_state);
+	if (rtn) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "up start work link_state_get failed [%d]", rtn);
+		return;
+	}
+	if (link_state != SL_CORE_LINK_STATE_GOING_UP) {
+		sl_core_log_err_trace(core_link, LOG_NAME, "up start work invalid state (link_state = %u %s)",
+				      link_state, sl_core_link_state_str(link_state));
+		return;
+	}
+
+	spin_lock(&core_link->data_lock);
+	spin_lock(&core_link->core_lgrp->data_lock);
+	core_link->core_lgrp->link_caps[core_link->num].tech_map  = core_link->core_lgrp->config.tech_map;
+	core_link->core_lgrp->link_caps[core_link->num].fec_map   = core_link->core_lgrp->config.fec_map;
+	core_link->core_lgrp->link_caps[core_link->num].pause_map = core_link->config.pause_map;
+	core_link->core_lgrp->link_caps[core_link->num].hpe_map   = core_link->config.hpe_map;
+	spin_unlock(&core_link->core_lgrp->data_lock);
+	spin_unlock(&core_link->data_lock);
+
+	rtn = sl_core_data_link_settings(core_link);
+	if (rtn != 0) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "up start data_link_settings failed [%d]", rtn);
+		sl_core_data_link_last_up_fail_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_CONFIG_MAP);
+		rtn = sl_core_link_up_fail(core_link);
+		if (rtn)
+			sl_core_log_err_trace(core_link, LOG_NAME, "up start work link_up_fail failed [%d]", rtn);
+		return;
+	}
+
+	sl_core_data_link_timeouts(core_link);
+
+	sl_core_timer_link_begin(core_link, SL_CORE_TIMER_LINK_UP);
+
+	sl_core_hw_link_off(core_link);
+
+	rtn = sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_LINK_UP);
+	if (rtn != 0)
+		sl_core_log_warn_trace(core_link, LOG_NAME,
+				       "up start work link up disable failed [%d]", rtn);
+	rtn = sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_LINK_HIGH_SER);
+	if (rtn != 0)
+		sl_core_log_warn_trace(core_link, LOG_NAME,
+				       "up start work link high SER disable failed [%d]", rtn);
+	rtn = sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_LINK_LLR_MAX_STARVATION);
+	if (rtn != 0)
+		sl_core_log_warn_trace(core_link, LOG_NAME,
+				       "up start work link llr max starvation disable failed [%d]", rtn);
+	rtn = sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_LINK_LLR_STARVED);
+	if (rtn != 0)
+		sl_core_log_warn_trace(core_link, LOG_NAME,
+				       "up start work link llr starved disable failed [%d]", rtn);
+	rtn = sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_LINK_FAULT);
+	if (rtn != 0)
+		sl_core_log_warn_trace(core_link, LOG_NAME,
+				       "up start work link fault disable failed [%d]", rtn);
+
+	/* clear faults here to see if faults happen during up */
+	sl_core_hw_intr_flgs_clr(core_link, SL_CORE_HW_INTR_LINK_HIGH_SER);
+	sl_core_hw_intr_flgs_clr(core_link, SL_CORE_HW_INTR_LINK_LLR_MAX_STARVATION);
+	sl_core_hw_intr_flgs_clr(core_link, SL_CORE_HW_INTR_LINK_LLR_STARVED);
+	sl_core_hw_intr_flgs_clr(core_link, SL_CORE_HW_INTR_LINK_FAULT);
+
+	if (sl_media_lgrp_media_type_is_active(core_link->core_lgrp->core_ldev->num,
+					       core_link->core_lgrp->num)) {
+		media_lgrp = sl_media_lgrp_get(core_link->core_lgrp->core_ldev->num,
+					       core_link->core_lgrp->num);
+		if (time_before(jiffies, media_lgrp->media_jack->cable_high_power_wait_time_end)) {
+			core_link->timers[SL_CORE_TIMER_LINK_UP_HIGH_POWER].data.timeout_ms =
+				jiffies_to_msecs(media_lgrp->media_jack->cable_high_power_wait_time_end - jiffies);
+			sl_core_timer_link_begin(core_link, SL_CORE_TIMER_LINK_UP_HIGH_POWER);
+			return;
+		}
+	}
+
+	queue_work(core_link->core_lgrp->core_ldev->workqueue, &core_link->work[SL_CORE_WORK_LINK_UP]);
+}
+
+void sl_core_hw_link_up_after_an_start(struct sl_core_link *core_link)
+{
+	int           rtn;
+	enum sl_core_link_state link_state;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "up after an start (link = 0x%p)", core_link);
+
+	spin_lock(&core_link->link.data_lock);
+	link_state = core_link->link.state;
+	switch (link_state) {
+	case SL_CORE_LINK_STATE_AN:
+		core_link->link.state = SL_CORE_LINK_STATE_GOING_UP;
+		sl_core_log_dbg(core_link, LOG_NAME, "up after an start going up");
+		spin_unlock(&core_link->link.data_lock);
+		break;
+	case SL_CORE_LINK_STATE_CANCELING:
+		sl_core_log_dbg(core_link, LOG_NAME, "up after an start canceled");
+		spin_unlock(&core_link->link.data_lock);
+		sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP);
+		return;
+	case SL_CORE_LINK_STATE_TIMEOUT:
+		sl_core_log_dbg(core_link, LOG_NAME, "up after an start timeout");
+		spin_unlock(&core_link->link.data_lock);
+		sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP);
+		return;
+	default:
+		sl_core_log_err(core_link, LOG_NAME,
+				"up after an start invalid state (link_state = %u %s)",
+				link_state, sl_core_link_state_str(link_state));
+		spin_unlock(&core_link->link.data_lock);
+		sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP);
+		return;
+	};
+
+	rtn = sl_core_data_link_settings(core_link);
+	if (rtn != 0) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "up after an start data_link_settings failed [%d]", rtn);
+		sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP);
+		sl_core_data_link_last_up_fail_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_AUTONEG_CONFIG_MAP);
+		rtn = sl_core_link_up_fail(core_link);
+		if (rtn)
+			sl_core_log_err_trace(core_link, LOG_NAME,
+					      "up after an start link_up_fail failed [%d]", rtn);
+		return;
+	}
+
+	sl_core_data_link_timeouts(core_link);
+
+	sl_core_hw_link_off(core_link);
+
+	rtn = sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_LINK_UP);
+	if (rtn != 0)
+		sl_core_log_warn_trace(core_link, LOG_NAME,
+				       "up after an start link up disable failed [%d]", rtn);
+	rtn = sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_LINK_HIGH_SER);
+	if (rtn != 0)
+		sl_core_log_warn_trace(core_link, LOG_NAME,
+				       "up after an start link high SER disable failed [%d]", rtn);
+	rtn = sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_LINK_LLR_MAX_STARVATION);
+	if (rtn != 0)
+		sl_core_log_warn_trace(core_link, LOG_NAME,
+				       "up after an start link llr max starvation disable failed [%d]", rtn);
+	rtn = sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_LINK_LLR_STARVED);
+	if (rtn != 0)
+		sl_core_log_warn_trace(core_link, LOG_NAME,
+				       "up after an start link llr starved disable failed [%d]", rtn);
+	rtn = sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_LINK_FAULT);
+	if (rtn != 0)
+		sl_core_log_warn_trace(core_link, LOG_NAME,
+				       "up after an start link fault disable failed [%d]", rtn);
+
+	/* clear faults here to see if faults happen during up */
+	sl_core_hw_intr_flgs_clr(core_link, SL_CORE_HW_INTR_LINK_HIGH_SER);
+	sl_core_hw_intr_flgs_clr(core_link, SL_CORE_HW_INTR_LINK_LLR_MAX_STARVATION);
+	sl_core_hw_intr_flgs_clr(core_link, SL_CORE_HW_INTR_LINK_LLR_STARVED);
+	sl_core_hw_intr_flgs_clr(core_link, SL_CORE_HW_INTR_LINK_FAULT);
+
+	queue_work(core_link->core_lgrp->core_ldev->workqueue, &core_link->work[SL_CORE_WORK_LINK_UP]);
+}
+
+void sl_core_hw_link_up_work(struct work_struct *work)
+{
+	int                   rtn;
+	struct sl_core_link  *core_link;
+	enum sl_core_link_state link_state;
+	struct sl_media_lgrp *media_lgrp;
+
+	core_link = container_of(work, struct sl_core_link, work[SL_CORE_WORK_LINK_UP]);
+
+	sl_core_log_dbg(core_link, LOG_NAME, "up work (link = 0x%p)", core_link);
+
+	rtn = sl_core_data_link_state_get(core_link, &link_state);
+	if (rtn) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "up work link_state_get failed [%d]", rtn);
+		sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP);
+		return;
+	}
+	if ((link_state != SL_CORE_LINK_STATE_GOING_UP) && (link_state != SL_CORE_LINK_STATE_AN)) {
+		sl_core_log_err_trace(core_link, LOG_NAME, "up work invalid state (link_state = %u %s)",
+				      link_state, sl_core_link_state_str(link_state));
+		sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP);
+		return;
+	}
+
+	sl_core_hw_serdes_link_down(core_link);
+
+	sl_core_hw_pcs_config(core_link);
+
+	media_lgrp = sl_media_lgrp_get(core_link->core_lgrp->core_ldev->num, core_link->core_lgrp->num);
+	if ((media_lgrp->media_jack->is_supported_ss200_cable) &&
+	    ((core_link->pcs.settings.pcs_mode == SL_CORE_HW_PCS_MODE_CK_400G) ||
+		(core_link->pcs.settings.pcs_mode == SL_CORE_HW_PCS_MODE_CK_200G)  ||
+		(core_link->pcs.settings.pcs_mode == SL_CORE_HW_PCS_MODE_CK_100G))) {
+		sl_core_log_err_trace(core_link, LOG_NAME, "up work link_up failed speed unsupported [%d]", rtn);
+		sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP);
+		sl_core_data_link_last_up_fail_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_UNSUPPORTED_SPEED_MAP);
+		rtn = sl_core_link_up_fail(core_link);
+		if (rtn)
+			sl_core_log_warn_trace(core_link, LOG_NAME, "up work link_up_fail failed [%d]", rtn);
+		return;
+	}
+
+	sl_core_log_dbg(core_link, LOG_NAME, "up work (speed = %d)", core_link->pcs.settings.pcs_mode);
+
+	if (core_link->pcs.settings.pcs_mode == SL_CORE_HW_PCS_MODE_BS_200G) {
+		rtn = sl_media_jack_cable_downshift(core_link->core_lgrp->core_ldev->num,
+						    core_link->core_lgrp->num, core_link->num);
+		if (rtn) {
+			sl_core_log_err_trace(core_link, LOG_NAME, "up work downshift failed [%d]", rtn);
+			sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP);
+			sl_core_data_link_last_up_fail_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_DOWNSHIFT_MAP);
+			rtn = sl_core_link_up_fail(core_link);
+			if (rtn)
+				sl_core_log_warn_trace(core_link, LOG_NAME, "up work link_up_fail failed [%d]", rtn);
+			return;
+		}
+	} else {
+		rtn = sl_media_jack_cable_upshift(core_link->core_lgrp->core_ldev->num,
+						  core_link->core_lgrp->num, core_link->num);
+		if (rtn) {
+			sl_core_log_err_trace(core_link, LOG_NAME, "up work upshift failed [%d]", rtn);
+			sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP);
+			sl_core_data_link_last_up_fail_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_UPSHIFT_MAP);
+			rtn = sl_core_link_up_fail(core_link);
+			if (rtn)
+				sl_core_log_warn_trace(core_link, LOG_NAME, "up work link_up_fail failed [%d]", rtn);
+			return;
+		}
+	}
+
+	rtn = sl_core_hw_serdes_link_up(core_link);
+	if (rtn) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "up work hw_serdes_link_up failed [%d]", rtn);
+		sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP);
+		/* no cause set here because serdes code will set it */
+		rtn = sl_core_link_up_fail(core_link);
+		if (rtn)
+			sl_core_log_err_trace(core_link, LOG_NAME, "up work link_up_fail failed [%d]", rtn);
+		return;
+	}
+
+	sl_core_hw_intr_flgs_clr(core_link, SL_CORE_HW_INTR_LINK_UP);
+	rtn = sl_core_hw_intr_flgs_enable(core_link, SL_CORE_HW_INTR_LINK_UP);
+	if (rtn != 0) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "up work link up enable failed [%d]", rtn);
+		sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP);
+		sl_core_data_link_last_up_fail_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_INTR_ENABLE_MAP);
+		rtn = sl_core_link_up_fail(core_link);
+		if (rtn)
+			sl_core_log_err_trace(core_link, LOG_NAME, "up work link_up_fail failed [%d]", rtn);
+		return;
+	}
+
+	if (!SL_PLATFORM_IS_HARDWARE(core_link->core_lgrp->core_ldev))
+		sl_core_hw_pcs_tx_start(core_link);
+
+	sl_core_hw_pcs_rx_start(core_link);
+
+	atomic_set(&core_link->pml_rec.pml_rec_down_cause_remote_fault, 0);
+}
+
+void sl_core_hw_link_up_intr_work(struct work_struct *work)
+{
+	int                  rtn;
+	struct sl_core_link *core_link;
+	enum sl_core_link_state link_state;
+
+	core_link = container_of(work, struct sl_core_link, work[SL_CORE_WORK_LINK_UP_INTR]);
+
+	sl_core_log_dbg(core_link, LOG_NAME, "up intr work");
+
+	rtn = sl_core_data_link_state_get(core_link, &link_state);
+	if (rtn) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "up intr work link_state_get failed [%d]", rtn);
+		sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP);
+		return;
+	}
+	if ((link_state != SL_CORE_LINK_STATE_GOING_UP) && (link_state != SL_CORE_LINK_STATE_AN)) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "up intr work invalid state (link_state = %u %s)",
+				      link_state, sl_core_link_state_str(link_state));
+		sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP);
+		return;
+	}
+
+	sl_core_timer_link_begin(core_link, SL_CORE_TIMER_LINK_UP_CHECK);
+}
+
+static bool sl_core_hw_link_is_media_present(struct sl_core_link *core_link)
+{
+	u32                   flags;
+	struct sl_media_lgrp *media_lgrp;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "is media present");
+
+	flags = sl_core_data_lgrp_config_flags_get(core_link->core_lgrp);
+
+	if (is_flag_set(flags, SL_LGRP_CONFIG_OPT_SERDES_LOOPBACK_ENABLE)) {
+		sl_core_log_dbg(core_link, LOG_NAME,
+				"is media present serdes loopback set (flags = %u)", flags);
+		return true;
+	}
+
+	media_lgrp = sl_media_lgrp_get(core_link->core_lgrp->core_ldev->num, core_link->core_lgrp->num);
+
+	return sl_media_jack_is_cable_online(media_lgrp->media_jack);
+}
+
+static int sl_core_hw_link_media_signal_get(struct sl_core_link *core_link,
+					    struct sl_media_jack_signal *media_signal)
+{
+	u32 lgrp_flags;
+	u32 link_flags;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "media signal get");
+
+	lgrp_flags = sl_core_data_lgrp_config_flags_get(core_link->core_lgrp);
+	if (is_flag_set(lgrp_flags, SL_LGRP_CONFIG_OPT_SERDES_LOOPBACK_ENABLE)) {
+		sl_core_log_dbg(core_link, LOG_NAME,
+				"media signal get serdes loopback set (flags = %u)", lgrp_flags);
+		memset(media_signal, 0, sizeof(*media_signal));
+		return 0;
+	}
+
+	link_flags = sl_core_data_link_config_flags_get(core_link);
+	if (is_flag_set(link_flags, SL_LINK_CONFIG_OPT_LOS_LOL_UP_FAIL_HIDE)) {
+		sl_core_log_dbg(core_link, LOG_NAME,
+				"media signal get los lol up fail hide set (flags = %u)", link_flags);
+		memset(media_signal, 0, sizeof(*media_signal));
+		return 0;
+	}
+
+	return sl_media_jack_signal_get(core_link->core_lgrp->core_ldev->num,
+					core_link->core_lgrp->num, core_link->serdes.lane_map, media_signal);
+}
+
+static void sl_core_hw_link_up_success(struct sl_core_link *core_link)
+{
+	struct sl_ctrl_link *held_link_1 __free(sl_ctrl_link_put) = NULL;
+	struct sl_ctrl_link *held_link_2 __free(sl_ctrl_link_put) = NULL;
+	struct sl_ctrl_link *held_link_3 __free(sl_ctrl_link_put) = NULL;
+	int                                 rtn;
+	struct sl_core_link_fec_cw_cntrs    cw_cntrs;
+	struct sl_core_link_fec_lane_cntrs  lane_cntrs;
+	struct sl_core_link_fec_tail_cntrs  tail_cntrs;
+	struct sl_core_link_up_info         link_up_info;
+	enum sl_core_link_state link_state;
+	struct sl_media_lgrp               *media_lgrp;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "up success");
+
+	media_lgrp = sl_media_lgrp_get(core_link->core_lgrp->core_ldev->num, core_link->core_lgrp->num);
+
+	sl_media_jack_fault_cause_set(media_lgrp->media_jack, SL_MEDIA_FAULT_CAUSE_NONE);
+
+	rtn = sl_core_hw_intr_flgs_enable(core_link, SL_CORE_HW_INTR_LINK_HIGH_SER);
+	if (rtn == -EAGAIN) {
+		sl_core_hw_intr_flgs_clr(core_link, SL_CORE_HW_INTR_LINK_HIGH_SER);
+		sl_core_hw_link_high_ser_intr_work_priv(core_link);
+	} else if (rtn != 0) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "up success link high SER enable failed [%d]", rtn);
+		sl_core_data_link_last_up_fail_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_INTR_ENABLE_MAP);
+		rtn = sl_core_link_up_fail(core_link);
+		if (rtn)
+			sl_core_log_err_trace(core_link, LOG_NAME, "up success link_up_fail failed [%d]", rtn);
+		return;
+	}
+
+	rtn = sl_core_hw_intr_flgs_enable(core_link, SL_CORE_HW_INTR_LINK_LLR_MAX_STARVATION);
+	if (rtn) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "up success link llr max starvation enable failed [%d]", rtn);
+		sl_core_data_link_last_up_fail_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_INTR_ENABLE_MAP);
+		rtn = sl_core_link_up_fail(core_link);
+		if (rtn)
+			sl_core_log_err_trace(core_link, LOG_NAME, "up success link_up_fail failed [%d]", rtn);
+		return;
+	}
+
+	rtn = sl_core_hw_intr_flgs_enable(core_link, SL_CORE_HW_INTR_LINK_LLR_STARVED);
+	if (rtn) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "up success link llr starved enable failed [%d]", rtn);
+		sl_core_data_link_last_up_fail_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_INTR_ENABLE_MAP);
+		rtn = sl_core_link_up_fail(core_link);
+		if (rtn)
+			sl_core_log_err_trace(core_link, LOG_NAME, "link_up_fail failed [%d]", rtn);
+		return;
+	}
+
+	rtn = sl_core_hw_intr_flgs_enable(core_link, SL_CORE_HW_INTR_LINK_FAULT);
+	if (rtn) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "up success link fault enable failed [%d]", rtn);
+		sl_core_data_link_last_up_fail_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_INTR_ENABLE_MAP);
+		rtn = sl_core_link_up_fail(core_link);
+		if (rtn)
+			sl_core_log_err_trace(core_link, LOG_NAME, "up success link_up_fail failed [%d]", rtn);
+		return;
+	}
+
+	held_link_1 = sl_ctrl_link_get(core_link->core_lgrp->core_ldev->num,
+				       core_link->core_lgrp->num, core_link->num);
+	if (held_link_1)
+		sl_ctrl_link_fec_down_cache_clear(held_link_1);
+
+	rtn = sl_core_hw_fec_data_get(core_link, &cw_cntrs, &lane_cntrs, &tail_cntrs);
+	if (rtn) {
+		sl_core_log_warn_trace(core_link, LOG_NAME, "up success w_fec_data_get failed [%d]", rtn);
+		held_link_2 = sl_ctrl_link_get(core_link->core_lgrp->core_ldev->num,
+					       core_link->core_lgrp->num, core_link->num);
+		if (held_link_2)
+			sl_ctrl_link_fec_up_cache_clear(held_link_2);
+	} else {
+		held_link_3 = sl_ctrl_link_get(core_link->core_lgrp->core_ldev->num,
+					       core_link->core_lgrp->num, core_link->num);
+		if (held_link_3)
+			sl_ctrl_link_fec_up_cache_store(held_link_3,
+							&cw_cntrs, &lane_cntrs, &tail_cntrs);
+	}
+
+	spin_lock(&core_link->link.data_lock);
+	link_state = core_link->link.state;
+	switch (link_state) {
+	case SL_CORE_LINK_STATE_GOING_UP:
+		sl_core_log_dbg(core_link, LOG_NAME, "up success up");
+		set_bit(SL_CORE_INFO_MAP_LINK_UP, (unsigned long *)&(core_link->info_map));
+
+		core_link->link.state                  = SL_CORE_LINK_STATE_UP;
+
+		link_up_info.state                     = core_link->link.state;
+		link_up_info.info_map                  = core_link->info_map;
+		link_up_info.speed                     = core_link->pcs.settings.speed;
+		link_up_info.fec_mode                  = core_link->fec.settings.mode;
+		link_up_info.fec_type                  = core_link->fec.settings.type;
+
+		spin_unlock(&core_link->link.data_lock);
+		sl_core_data_link_last_up_fail_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_NONE);
+		link_up_info.cause_map                 = sl_core_data_link_last_up_fail_cause_map_get(core_link);
+		sl_media_jack_led_set(core_link->core_lgrp->core_ldev->num, core_link->core_lgrp->num);
+		sl_core_hw_link_up_callback(core_link, &link_up_info);
+		return;
+	default:
+		sl_core_log_err(core_link, LOG_NAME, "up success invalid state (link_state = %u %s)",
+				link_state, sl_core_link_state_str(link_state));
+		spin_unlock(&core_link->link.data_lock);
+		return;
+	};
+}
+
+static void sl_core_hw_link_up_ald(struct sl_core_link  *core_link)
+{
+	int rtn;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "link up ald");
+
+	if ((core_link->num != 0)                             ||
+	    !sl_core_link_config_is_enable_ald_set(core_link) ||
+	    (core_link->core_lgrp->config.furcation != SL_MEDIA_FURCATION_X1)) {
+		sl_core_log_dbg(core_link, LOG_NAME, "link up ald not configured");
+		spin_lock(&core_link->data_lock);
+		core_link->degrade_state = SL_LINK_DEGRADE_STATE_INACTIVE;
+		spin_unlock(&core_link->data_lock);
+		return;
+	}
+
+	memset(&(core_link->degrade_info), 0, sizeof(core_link->degrade_info));
+
+	rtn = sl_core_hw_pcs_enable_auto_lane_degrade(core_link);
+	if (rtn) {
+		spin_lock(&core_link->data_lock);
+		core_link->degrade_state = SL_LINK_DEGRADE_STATE_FAILED;
+		spin_unlock(&core_link->data_lock);
+		return;
+	}
+
+	sl_core_hw_intr_flgs_clr(core_link, SL_CORE_HW_INTR_LANE_DEGRADE);
+	rtn = sl_core_hw_intr_flgs_enable(core_link, SL_CORE_HW_INTR_LANE_DEGRADE);
+	if (rtn) {
+		sl_core_log_err_trace(core_link, LOG_NAME, "link up ald intr enable failed [%d]", rtn);
+		spin_lock(&core_link->data_lock);
+		core_link->degrade_state = SL_LINK_DEGRADE_STATE_FAILED;
+		spin_unlock(&core_link->data_lock);
+		sl_core_data_link_last_up_fail_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_INTR_ENABLE_MAP);
+		rtn = sl_core_link_up_fail(core_link);
+		if (rtn)
+			sl_core_log_err_trace(core_link, LOG_NAME, "link up ald link_up_fail failed [%d]", rtn);
+		return;
+	}
+
+	spin_lock(&core_link->data_lock);
+	core_link->degrade_state = SL_LINK_DEGRADE_STATE_ACTIVE;
+	spin_unlock(&core_link->data_lock);
+}
+
+void sl_core_hw_link_up_check_work(struct work_struct *work)
+{
+	int                   rtn;
+	u8                    temperature_state;
+	u8                    temperature_prev_state;
+	u32                   port;
+	enum sl_core_link_state link_state;
+	u64                   data64;
+	struct sl_core_link  *core_link;
+	struct sl_media_lgrp *media_lgrp;
+
+	core_link = container_of(work, struct sl_core_link, work[SL_CORE_WORK_LINK_UP_CHECK]);
+	media_lgrp = sl_media_lgrp_get(core_link->core_lgrp->core_ldev->num, core_link->core_lgrp->num);
+
+	port = core_link->core_lgrp->num;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "up check work (port = %u)", port);
+
+	rtn = sl_core_data_link_state_get(core_link, &link_state);
+	if (rtn) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "up check work link_state_get failed [%d]", rtn);
+		sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP);
+		return;
+	}
+
+	if ((link_state != SL_CORE_LINK_STATE_GOING_UP) && (link_state != SL_CORE_LINK_STATE_AN)) {
+		sl_core_log_err_trace(core_link, LOG_NAME, "up check work invalid state (link_state = %u %s)",
+				      link_state, sl_core_link_state_str(link_state));
+		sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP);
+		return;
+	}
+
+	if (!sl_media_lgrp_media_type_is_active(core_link->core_lgrp->core_ldev->num, core_link->core_lgrp->num) ||
+	    is_flag_set(sl_core_data_lgrp_config_flags_get(core_link->core_lgrp),
+			SL_LGRP_CONFIG_OPT_SERDES_LOOPBACK_ENABLE))
+		goto out;
+
+	rtn  = sl_media_jack_cable_temp_state_get(media_lgrp->media_jack, &temperature_state);
+	if (rtn) {
+		sl_core_log_warn_trace(core_link, LOG_NAME, "up check work cable_temp_state_get failed [%d]", rtn);
+		goto out;
+	}
+
+	if (temperature_state == SL_MEDIA_JACK_TEMP_STATE_HOT) {
+		sl_core_log_warn_trace(core_link, LOG_NAME, "up check work media hot detected (jack_num = %u)",
+				       media_lgrp->media_jack->physical_num);
+
+		sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP);
+		sl_core_data_link_last_up_fail_cause_map_set(core_link,
+							     SL_LINK_DOWN_CAUSE_MEDIA_HOT_LINK_UP_MAP);
+		rtn = sl_core_link_up_fail(core_link);
+		if (rtn)
+			sl_core_log_warn_trace(core_link, LOG_NAME,
+					       "up check work media hot link_up_fail failed [%d]", rtn);
+		return;
+	}
+
+	if (temperature_state == SL_MEDIA_JACK_TEMP_STATE_WARM) {
+		sl_core_log_warn_trace(core_link, LOG_NAME, "up check work media warm detected (jack_num = %u)",
+				       media_lgrp->media_jack->physical_num);
+
+		rtn  = sl_media_jack_cable_temp_prev_state_get(media_lgrp->media_jack, &temperature_prev_state);
+		if (rtn) {
+			sl_core_log_warn_trace(core_link, LOG_NAME,
+					       "up check work cable_temp_prev_state_get failed [%d]", rtn);
+			goto out;
+		}
+
+		if (temperature_prev_state == SL_MEDIA_JACK_TEMP_STATE_HOT) {
+			sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP);
+			sl_media_jack_fault_cause_set(media_lgrp->media_jack, SL_MEDIA_FAULT_CAUSE_WARM);
+			sl_core_data_link_last_up_fail_cause_map_set(core_link,
+								     SL_LINK_DOWN_CAUSE_MEDIA_WARM_LINK_UP_MAP);
+			rtn = sl_core_link_up_fail(core_link);
+			if (rtn)
+				sl_core_log_warn_trace(core_link, LOG_NAME,
+						       "up check work media warm link_up_fail failed [%d]", rtn);
+			return;
+		}
+	}
+
+out:
+	/* check PCS */
+	if (!sl_core_hw_pcs_is_ok(core_link)) {
+		sl_core_log_warn_trace(core_link, LOG_NAME, "up check work pcs is not ok");
+		sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP);
+		sl_core_data_link_last_up_fail_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_PCS_FAULT_MAP);
+		rtn = sl_core_link_up_fail(core_link);
+		if (rtn)
+			sl_core_log_err_trace(core_link, LOG_NAME, "up check work link_up_fail failed [%d]", rtn);
+		return;
+	}
+
+	/* check to see if there were faults during up */
+	sl_core_hw_intr_flgs_check(core_link, SL_CORE_HW_INTR_LINK_FAULT);
+	sl_core_hw_intr_flgs_clr(core_link, SL_CORE_HW_INTR_LINK_FAULT);
+
+	/* clear underrun */
+	sl_core_read64(core_link, SS2_PORT_PML_ERR_INFO_PCS_TX_DP, &data64);
+	data64 = SS2_PORT_PML_ERR_INFO_PCS_TX_DP_TX_CDC_UNDERRUN_UPDATE(data64,
+									core_link->pcs.settings.underrun_clr);
+	sl_core_write64(core_link, SS2_PORT_PML_ERR_INFO_PCS_TX_DP, data64);
+
+	if (core_link->fec.settings.up_settle_wait_ms) {
+		sl_core_timer_link_begin(core_link, SL_CORE_TIMER_LINK_UP_FEC_SETTLE);
+		return;
+	}
+
+	sl_core_hw_link_up_ald(core_link);
+
+	sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP);
+
+	sl_core_hw_link_up_success(core_link);
+}
+
+void sl_core_hw_link_up_fec_settle_work(struct work_struct *work)
+{
+	int                                 rtn;
+	struct sl_core_link_fec_cw_cntrs    cw_cntrs;
+	struct sl_core_link_fec_lane_cntrs  lane_cntrs;
+	struct sl_core_link_fec_tail_cntrs  tail_cntrs;
+	struct sl_core_link                *core_link;
+	struct sl_ctrl_link *ctrl_link __free(sl_ctrl_link_put) = NULL;
+	enum sl_core_link_state link_state;
+
+	core_link = container_of(work, struct sl_core_link, work[SL_CORE_WORK_LINK_UP_FEC_SETTLE]);
+	ctrl_link = sl_ctrl_link_get(core_link->core_lgrp->core_ldev->num,
+				     core_link->core_lgrp->num, core_link->num);
+	if (!ctrl_link)
+		return;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "up fec settle work");
+
+	rtn = sl_core_data_link_state_get(core_link, &link_state);
+	if (rtn) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "up fec settle work link_state_get failed [%d]", rtn);
+		sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP);
+		return;
+	}
+
+	if ((link_state != SL_CORE_LINK_STATE_GOING_UP) && (link_state != SL_CORE_LINK_STATE_AN)) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "up fec settle work invalid state (link_state = %u %s)",
+				      link_state, sl_core_link_state_str(link_state));
+		sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP);
+		return;
+	}
+
+	rtn = sl_core_hw_fec_data_get(core_link, &cw_cntrs, &lane_cntrs, &tail_cntrs);
+	if (rtn)
+		sl_core_log_warn_trace(core_link, LOG_NAME,
+				       "up fec settle work hw_fec_data_get failed [%d]", rtn);
+	else
+		sl_ctrl_link_fec_data_store(ctrl_link, &cw_cntrs, &lane_cntrs, &tail_cntrs);
+
+	sl_core_timer_link_begin(core_link, SL_CORE_TIMER_LINK_UP_FEC_CHECK);
+}
+
+void sl_core_hw_link_up_fec_check_work(struct work_struct *work)
+{
+	int                                 rtn;
+	struct sl_core_link_fec_cw_cntrs    cw_cntrs;
+	struct sl_core_link_fec_lane_cntrs  lane_cntrs;
+	struct sl_core_link_fec_tail_cntrs  tail_cntrs;
+	struct sl_fec_info                  fec_info;
+	struct sl_core_link                *core_link;
+	struct sl_ctrl_link *ctrl_link __free(sl_ctrl_link_put) = NULL;
+	enum sl_core_link_state link_state;
+
+	core_link = container_of(work, struct sl_core_link, work[SL_CORE_WORK_LINK_UP_FEC_CHECK]);
+	ctrl_link = sl_ctrl_link_get(core_link->core_lgrp->core_ldev->num,
+				     core_link->core_lgrp->num, core_link->num);
+	if (!ctrl_link)
+		return;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "up fec check work");
+
+	rtn = sl_core_data_link_state_get(core_link, &link_state);
+	if (rtn) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "up fec check work link_state_get failed [%d]", rtn);
+		sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP);
+		return;
+	}
+
+	if ((link_state != SL_CORE_LINK_STATE_GOING_UP) && (link_state != SL_CORE_LINK_STATE_AN)) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "up fec check work invalid state (link_state = %u %s)",
+				      link_state, sl_core_link_state_str(link_state));
+		sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP);
+		return;
+	}
+
+	sl_core_data_link_info_map_set(core_link, SL_CORE_INFO_MAP_FEC_CHECK);
+
+	rtn = sl_core_hw_fec_data_get(core_link, &cw_cntrs, &lane_cntrs, &tail_cntrs);
+	if (rtn)
+		sl_core_log_warn_trace(core_link, LOG_NAME,
+				       "up fec check work hw_fec_data_get failed [%d]", rtn);
+	else
+		sl_ctrl_link_fec_data_store(ctrl_link, &cw_cntrs, &lane_cntrs, &tail_cntrs);
+
+	sl_ctrl_link_fec_data_calc(ctrl_link);
+	fec_info = sl_ctrl_link_fec_data_info_get(ctrl_link);
+
+	if (SL_CTRL_LINK_FEC_UCW_LIMIT_CHECK(core_link->fec.settings.up_ucw_limit, &fec_info)) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "up fec check UCW exceeded up limit (UCW = %llu, CCW = %llu)",
+				      fec_info.ucw, fec_info.ccw);
+		SL_CTRL_LINK_COUNTER_INC(ctrl_link, LINK_UP_FAIL_UCW_LIMIT_CROSSED);
+		sl_core_data_link_info_map_clr(core_link, SL_CORE_INFO_MAP_FEC_OK);
+		sl_core_data_link_last_up_fail_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_UCW_UP_CHECK_MAP);
+		sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP);
+		rtn = sl_core_link_up_fail(core_link);
+		if (rtn)
+			sl_core_log_err_trace(core_link, LOG_NAME, "up fec check link_up_fail failed [%d]", rtn);
+		return;
+	}
+
+	if (SL_CTRL_LINK_FEC_CCW_LIMIT_CHECK(core_link->fec.settings.up_ccw_limit, &fec_info)) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "up fec check CCW exceeded up limit (UCW = %llu, CCW = %llu)",
+				      fec_info.ucw, fec_info.ccw);
+		SL_CTRL_LINK_COUNTER_INC(ctrl_link, LINK_UP_FAIL_CCW_LIMIT_CROSSED);
+		sl_core_data_link_last_up_fail_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_CCW_UP_CHECK_MAP);
+		sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP);
+		rtn = sl_core_link_up_fail(core_link);
+		if (rtn)
+			sl_core_log_err_trace(core_link, LOG_NAME, "up fec check link_up_fail failed [%d]", rtn);
+		return;
+	}
+
+	sl_core_data_link_info_map_clr(core_link, SL_CORE_INFO_MAP_FEC_CHECK);
+	sl_core_data_link_info_map_set(core_link, SL_CORE_INFO_MAP_FEC_OK);
+
+	sl_core_hw_link_up_ald(core_link);
+
+	sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP);
+
+	sl_core_hw_link_up_success(core_link);
+}
+
+static void sl_core_hw_link_last_up_fail_cause_map_set_from_signal(struct sl_core_link *core_link,
+								   struct sl_media_jack_signal *media_signal)
+{
+	if (media_signal->tx.lol_map & core_link->serdes.lane_map)
+		sl_core_data_link_last_up_fail_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_TX_LOL_UP_MAP);
+
+	if (media_signal->rx.lol_map & core_link->serdes.lane_map)
+		sl_core_data_link_last_up_fail_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_RX_LOL_UP_MAP);
+
+	if (media_signal->tx.los_map & core_link->serdes.lane_map)
+		sl_core_data_link_last_up_fail_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_TX_LOS_UP_MAP);
+
+	if (media_signal->rx.los_map & core_link->serdes.lane_map)
+		sl_core_data_link_last_up_fail_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_RX_LOS_UP_MAP);
+}
+
+void sl_core_hw_link_up_timeout_work(struct work_struct *work)
+{
+	struct sl_core_link         *core_link;
+	struct sl_core_link_up_info  link_up_info;
+	enum sl_core_link_state link_state;
+	int                          rtn;
+	struct sl_media_jack_signal  media_signal;
+
+	core_link = container_of(work, struct sl_core_link, work[SL_CORE_WORK_LINK_UP_TIMEOUT]);
+
+	sl_core_log_dbg(core_link, LOG_NAME, "up timeout work");
+
+	spin_lock(&core_link->link.data_lock);
+	link_state = core_link->link.state;
+	switch (link_state) {
+	case SL_CORE_LINK_STATE_GOING_UP:
+	case SL_CORE_LINK_STATE_AN:
+		sl_core_log_dbg(core_link, LOG_NAME, "up timeout work going down");
+		core_link->link.state = SL_CORE_LINK_STATE_TIMEOUT;
+		spin_unlock(&core_link->link.data_lock);
+		sl_core_data_link_last_up_fail_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_TIMEOUT_MAP);
+		break;
+	default:
+		sl_core_log_err(core_link, LOG_NAME, "up timeout work invalid state (link_state = %u %s)",
+				link_state, sl_core_link_state_str(link_state));
+		spin_unlock(&core_link->link.data_lock);
+		return;
+	}
+
+	sl_core_data_link_info_map_clr(core_link, SL_CORE_INFO_MAP_NUM_BITS);
+	sl_core_data_link_info_map_set(core_link, SL_CORE_INFO_MAP_LINK_UP_TIMEOUT);
+
+	/* stop timers */
+	sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP);
+	sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP_CHECK);
+	sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP_FEC_SETTLE);
+	sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP_FEC_CHECK);
+	sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP_HIGH_POWER);
+
+	/* cancel work - except for timeout work */
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_AN_UP_START]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_AN_UP]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_AN_UP_DONE]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_UP_START]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_UP]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_UP_CHECK]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_UP_FEC_SETTLE]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_UP_FEC_CHECK]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_UP_FAIL]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_UP_CANCEL]));
+
+	/* disable interrupts */
+	sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_LINK_UP);
+	sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_LINK_HIGH_SER);
+	sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_LINK_LLR_MAX_STARVATION);
+	sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_LINK_LLR_STARVED);
+	sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_LINK_FAULT);
+	if (core_link->num == 0)
+		sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_LANE_DEGRADE);
+
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_UP_INTR]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_HIGH_SER_INTR]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_LLR_MAX_STARVATION_INTR]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_LLR_STARVED_INTR]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_FAULT_INTR]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_PML_REC_POLL]));
+	if (core_link->num == 0)
+		cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_LANE_DEGRADE_INTR]));
+
+	/* Check media */
+	if (sl_core_hw_link_is_media_present(core_link)) {
+		/* Check signal before turning the link off */
+		rtn = sl_core_hw_link_media_signal_get(core_link, &media_signal);
+		if (rtn)
+			sl_core_log_err_trace(core_link, LOG_NAME,
+					      "up timeout work media signal get failed [%d]", rtn);
+		else
+			sl_core_hw_link_last_up_fail_cause_map_set_from_signal(core_link, &media_signal);
+	} else {
+		sl_core_data_link_last_up_fail_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_NO_MEDIA);
+	}
+
+	/* stop hardware */
+	sl_core_hw_an_stop(core_link);
+	sl_core_hw_link_off(core_link);
+
+	sl_core_data_link_state_set(core_link, SL_CORE_LINK_STATE_DOWN);
+
+	sl_core_hw_link_up_callback(core_link, sl_core_link_up_info_get(core_link, &link_up_info));
+
+	sl_core_data_link_info_map_clr(core_link, SL_CORE_INFO_MAP_NUM_BITS);
+}
+
+void sl_core_hw_link_up_cancel_work(struct work_struct *work)
+{
+	struct sl_core_link         *core_link;
+	struct sl_core_link_up_info  link_up_info;
+	enum sl_core_link_state link_state;
+	int                          rtn;
+	struct sl_media_jack_signal  media_signal;
+
+	core_link = container_of(work, struct sl_core_link, work[SL_CORE_WORK_LINK_UP_CANCEL]);
+
+	rtn = sl_core_data_link_state_get(core_link, &link_state);
+	if (rtn) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "up cancel work link_state_get failed [%d]", rtn);
+		return;
+	}
+
+	sl_core_log_dbg(core_link, LOG_NAME, "up cancel work (link_state = %u %s)", link_state,
+			sl_core_link_state_str(link_state));
+
+	if (link_state != SL_CORE_LINK_STATE_CANCELING) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "up cancel work invalid state (link_state = %u %s)",
+				      link_state, sl_core_link_state_str(link_state));
+		return;
+	}
+
+	sl_core_data_link_info_map_clr(core_link, SL_CORE_INFO_MAP_NUM_BITS);
+	sl_core_data_link_info_map_set(core_link, SL_CORE_INFO_MAP_LINK_UP_CANCEL);
+
+	/* stop timers */
+	sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP);
+	sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP_CHECK);
+	sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP_FEC_SETTLE);
+	sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP_FEC_CHECK);
+	sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP_HIGH_POWER);
+
+	/* cancel work */
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_AN_UP_START]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_AN_UP]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_AN_UP_DONE]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_UP_START]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_UP]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_UP_TIMEOUT]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_UP_CHECK]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_UP_FEC_SETTLE]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_UP_FEC_CHECK]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_UP_FAIL]));
+
+	/* disable interrupts */
+	sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_LINK_UP);
+	sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_LINK_HIGH_SER);
+	sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_LINK_LLR_MAX_STARVATION);
+	sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_LINK_LLR_STARVED);
+	sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_LINK_FAULT);
+	if (core_link->num == 0)
+		sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_LANE_DEGRADE);
+
+	/* Cancel work queued from interrupt */
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_UP_INTR]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_HIGH_SER_INTR]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_LLR_MAX_STARVATION_INTR]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_LLR_STARVED_INTR]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_FAULT_INTR]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_PML_REC_POLL]));
+	if (core_link->num == 0)
+		cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_LANE_DEGRADE_INTR]));
+
+	/* Check media */
+	if (sl_core_hw_link_is_media_present(core_link)) {
+		/* Check signal before turning the link off */
+		rtn = sl_core_hw_link_media_signal_get(core_link, &media_signal);
+		if (rtn)
+			sl_core_log_err_trace(core_link, LOG_NAME,
+					      "up timeout work media signal get failed [%d]", rtn);
+		else
+			sl_core_hw_link_last_up_fail_cause_map_set_from_signal(core_link, &media_signal);
+	} else {
+		sl_core_data_link_last_up_fail_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_NO_MEDIA);
+	}
+
+	/* stop hardware */
+	sl_core_hw_an_stop(core_link);
+	sl_core_hw_link_off(core_link);
+
+	sl_core_data_link_state_set(core_link, SL_CORE_LINK_STATE_DOWN);
+
+	sl_core_hw_link_up_callback(core_link, sl_core_link_up_info_get(core_link, &link_up_info));
+
+	sl_core_data_link_last_up_fail_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_UP_CANCELED_MAP);
+	sl_core_hw_link_down_callback(core_link);
+
+	sl_core_data_link_info_map_clr(core_link, SL_CORE_INFO_MAP_NUM_BITS);
+}
+
+void sl_core_hw_link_up_fail_work(struct work_struct *work)
+{
+	struct sl_core_link         *core_link;
+	struct sl_core_link_up_info  link_up_info;
+	enum sl_core_link_state link_state;
+	int                          rtn;
+	struct sl_media_jack_signal  media_signal;
+
+	core_link = container_of(work, struct sl_core_link, work[SL_CORE_WORK_LINK_UP_FAIL]);
+
+	sl_core_log_dbg(core_link, LOG_NAME, "up fail work");
+
+	rtn = sl_core_data_link_state_get(core_link, &link_state);
+	if (rtn) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "up fail work link_state_get failed [%d]", rtn);
+		return;
+	}
+
+	if (link_state != SL_CORE_LINK_STATE_GOING_DOWN) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "up fail work invalid state (link_state = %u %s)",
+				      link_state, sl_core_link_state_str(link_state));
+		return;
+	}
+
+	sl_core_data_link_info_map_clr(core_link, SL_CORE_INFO_MAP_NUM_BITS);
+	sl_core_data_link_info_map_set(core_link, SL_CORE_INFO_MAP_LINK_UP_FAIL);
+
+	/* stop timers */
+	sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP);
+	sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP_CHECK);
+	sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP_FEC_SETTLE);
+	sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP_FEC_CHECK);
+	sl_core_timer_link_end(core_link, SL_CORE_TIMER_LINK_UP_HIGH_POWER);
+
+	/* cancel work */
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_AN_UP_START]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_AN_UP]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_AN_UP_DONE]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_UP_START]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_UP]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_UP_TIMEOUT]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_UP_CHECK]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_UP_FEC_SETTLE]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_UP_FEC_CHECK]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_UP_CANCEL]));
+
+	/* disable interrupts */
+	sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_LINK_UP);
+	sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_LINK_HIGH_SER);
+	sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_LINK_LLR_MAX_STARVATION);
+	sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_LINK_LLR_STARVED);
+	sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_LINK_FAULT);
+	if (core_link->num == 0)
+		sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_LANE_DEGRADE);
+
+	/* Cancel work queued from interrupt */
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_UP_INTR]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_HIGH_SER_INTR]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_LLR_MAX_STARVATION_INTR]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_LLR_STARVED_INTR]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_FAULT_INTR]));
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_PML_REC_POLL]));
+	if (core_link->num == 0)
+		cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_LANE_DEGRADE_INTR]));
+
+	/* Check media */
+	if (sl_core_hw_link_is_media_present(core_link)) {
+		/* Check signal before turning the link off */
+		rtn = sl_core_hw_link_media_signal_get(core_link, &media_signal);
+		if (rtn)
+			sl_core_log_err_trace(core_link, LOG_NAME,
+					      "up timeout work media signal get failed [%d]", rtn);
+		else
+			sl_core_hw_link_last_up_fail_cause_map_set_from_signal(core_link, &media_signal);
+	} else {
+		sl_core_data_link_last_up_fail_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_NO_MEDIA);
+	}
+
+	/* stop hardware */
+	sl_core_hw_an_stop(core_link);
+	sl_core_hw_link_off(core_link);
+
+	sl_core_data_link_state_set(core_link, SL_CORE_LINK_STATE_DOWN);
+
+	sl_core_hw_link_up_callback(core_link, sl_core_link_up_info_get(core_link, &link_up_info));
+
+	sl_core_data_link_info_map_clr(core_link, SL_CORE_INFO_MAP_NUM_BITS);
+}
+
+void sl_core_hw_link_down_work(struct work_struct *work)
+{
+	struct sl_ctrl_link *held_link_1 __free(sl_ctrl_link_put) = NULL;
+	int                                 rtn;
+	struct sl_core_link_fec_cw_cntrs    cw_cntrs;
+	struct sl_core_link_fec_lane_cntrs  lane_cntrs;
+	struct sl_core_link_fec_tail_cntrs  tail_cntrs;
+	struct sl_core_link                *core_link;
+	enum sl_core_link_state link_state;
+
+	core_link = container_of(work, struct sl_core_link, work[SL_CORE_WORK_LINK_DOWN]);
+
+	sl_core_log_dbg(core_link, LOG_NAME, "down work");
+
+	rtn = sl_core_data_link_state_get(core_link, &link_state);
+	if (rtn) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "down work link_state_get failed [%d]", rtn);
+		return;
+	}
+
+	if (link_state != SL_CORE_LINK_STATE_GOING_DOWN) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "down work invalid state (link_state = %u %s)",
+				      link_state, sl_core_link_state_str(link_state));
+		return;
+	}
+
+	sl_core_data_link_info_map_clr(core_link, SL_CORE_INFO_MAP_NUM_BITS);
+	sl_core_data_link_info_map_set(core_link, SL_CORE_INFO_MAP_LINK_DOWN);
+
+	rtn = sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_LINK_HIGH_SER);
+	if (rtn != 0)
+		sl_core_log_warn_trace(core_link, LOG_NAME,
+				       "down work link high SER disable failed [%d]", rtn);
+	rtn = sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_LINK_LLR_MAX_STARVATION);
+	if (rtn != 0)
+		sl_core_log_warn_trace(core_link, LOG_NAME,
+				       "down work link llr max starvation disable failed [%d]", rtn);
+	rtn = sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_LINK_LLR_STARVED);
+	if (rtn != 0)
+		sl_core_log_warn_trace(core_link, LOG_NAME,
+				       "down work link llr starved disable failed [%d]", rtn);
+	rtn = sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_LINK_FAULT);
+	if (rtn != 0)
+		sl_core_log_warn_trace(core_link, LOG_NAME,
+				       "down work link fault disable failed [%d]", rtn);
+	if (core_link->num == 0) {
+		rtn = sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_LANE_DEGRADE);
+		if (rtn != 0)
+			sl_core_log_warn_trace(core_link, LOG_NAME,
+					       "down work lane degrade disable failed [%d]", rtn);
+	}
+
+	cancel_work_sync(&core_link->work[SL_CORE_WORK_LINK_HIGH_SER_INTR]);
+	cancel_work_sync(&core_link->work[SL_CORE_WORK_LINK_LLR_MAX_STARVATION_INTR]);
+	cancel_work_sync(&core_link->work[SL_CORE_WORK_LINK_LLR_STARVED_INTR]);
+	cancel_work_sync(&core_link->work[SL_CORE_WORK_LINK_FAULT_INTR]);
+	cancel_work_sync(&(core_link->work[SL_CORE_WORK_LINK_PML_REC_POLL]));
+	if (core_link->num == 0)
+		cancel_work_sync(&core_link->work[SL_CORE_WORK_LINK_LANE_DEGRADE_INTR]);
+
+	rtn = sl_core_hw_fec_data_get(core_link, &cw_cntrs, &lane_cntrs, &tail_cntrs);
+	if (rtn) {
+		sl_core_log_warn_trace(core_link, LOG_NAME, "down work hw_fec_data_get failed [%d]", rtn);
+	} else {
+		held_link_1 = sl_ctrl_link_get(core_link->core_lgrp->core_ldev->num,
+					       core_link->core_lgrp->num, core_link->num);
+		if (held_link_1)
+			sl_ctrl_link_fec_down_cache_store(held_link_1,
+							  &cw_cntrs, &lane_cntrs, &tail_cntrs);
+	}
+
+	/* Check media */
+	if (!sl_core_hw_link_is_media_present(core_link))
+		sl_core_data_link_last_down_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_NO_MEDIA);
+
+	sl_core_hw_link_off(core_link);
+
+	sl_core_data_link_state_set(core_link, SL_CORE_LINK_STATE_DOWN);
+
+	sl_core_hw_link_down_callback(core_link);
+
+	sl_core_data_link_info_map_clr(core_link, SL_CORE_INFO_MAP_NUM_BITS);
+}
+
+void sl_core_hw_link_high_ser_intr_work(struct work_struct *work)
+{
+	int                  rtn;
+	struct sl_core_link *core_link;
+	enum sl_core_link_state link_state;
+
+	core_link = container_of(work, struct sl_core_link, work[SL_CORE_WORK_LINK_HIGH_SER_INTR]);
+
+	sl_core_log_dbg(core_link, LOG_NAME, "high SER intr work");
+
+	rtn = sl_core_data_link_state_get(core_link, &link_state);
+	if (rtn) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "high SER intr work link_state_get failed [%d]", rtn);
+		return;
+	}
+
+	switch (link_state) {
+	case SL_CORE_LINK_STATE_UP:
+	case SL_CORE_LINK_STATE_GOING_UP:
+	case SL_CORE_LINK_STATE_AN:
+	case SL_CORE_LINK_STATE_GOING_DOWN:
+		break;
+	default:
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "high SER intr work invalid state (link_state = %u %s)",
+				      link_state, sl_core_link_state_str(link_state));
+			return;
+	}
+
+	sl_core_hw_link_high_ser_intr_work_priv(core_link);
+}
+
+void sl_core_hw_link_llr_max_starvation_intr_work(struct work_struct *work)
+{
+	int                  rtn;
+	struct sl_core_link *core_link;
+	enum sl_core_link_state link_state;
+
+	core_link = container_of(work, struct sl_core_link, work[SL_CORE_WORK_LINK_LLR_MAX_STARVATION_INTR]);
+
+	sl_core_log_dbg(core_link, LOG_NAME, "llr max starvation intr work");
+
+	rtn = sl_core_data_link_state_get(core_link, &link_state);
+	if (rtn) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "llr max starvation intr work link_state_get failed [%d]", rtn);
+		return;
+	}
+
+	if (link_state != SL_CORE_LINK_STATE_UP) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "llr max starvation intr work invalid state (link_state = %u %s)",
+				      link_state, sl_core_link_state_str(link_state));
+		return;
+	}
+
+	sl_core_data_link_info_map_set(core_link, SL_CORE_INFO_MAP_LLR_MAX_STARVATION);
+
+	sl_core_log_warn_trace(core_link, LOG_NAME, "llr max starvation occurred");
+
+	while (sl_core_hw_intr_flgs_enable(core_link, SL_CORE_HW_INTR_LINK_LLR_MAX_STARVATION) == -EALREADY) {
+		rtn = sl_core_data_link_state_get(core_link, &link_state);
+		if (rtn) {
+			sl_core_log_err_trace(core_link, LOG_NAME,
+					      "llr max starvation intr work link_state_get failed [%d]", rtn);
+			return;
+		}
+
+		switch (link_state) {
+		case SL_CORE_LINK_STATE_GOING_DOWN:
+		case SL_CORE_LINK_STATE_CANCELING:
+		case SL_CORE_LINK_STATE_TIMEOUT:
+			sl_core_log_err_trace(core_link, LOG_NAME,
+					      "llr max starvation intr work invalid state (state = %u %s)",
+					      link_state, sl_core_link_state_str(link_state));
+			return;
+		default:
+			sl_core_log_dbg(core_link, LOG_NAME,
+					"llr max starvation intr work clearing flags (state = %u %s)",
+					link_state, sl_core_link_state_str(link_state));
+			usleep_range(10000, 12000);
+			sl_core_hw_intr_flgs_clr(core_link, SL_CORE_HW_INTR_LINK_LLR_MAX_STARVATION);
+			continue;
+		}
+	}
+
+	sl_core_data_link_info_map_clr(core_link, SL_CORE_INFO_MAP_LLR_MAX_STARVATION);
+}
+
+void sl_core_hw_link_llr_starved_intr_work(struct work_struct *work)
+{
+	int                  rtn;
+	struct sl_core_link *core_link;
+	enum sl_core_link_state link_state;
+
+	core_link = container_of(work, struct sl_core_link, work[SL_CORE_WORK_LINK_LLR_STARVED_INTR]);
+
+	sl_core_log_dbg(core_link, LOG_NAME, "llr starved intr work");
+
+	rtn = sl_core_data_link_state_get(core_link, &link_state);
+	if (rtn) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "llr starved intr work failed to get link state [%d]", rtn);
+		return;
+	}
+
+	if (link_state != SL_CORE_LINK_STATE_UP) {
+		sl_core_log_dbg(core_link, LOG_NAME,
+				"llr starved intr work invalid state (link_state = %u %s)",
+				link_state, sl_core_link_state_str(link_state));
+		return;
+	}
+
+	sl_core_data_link_info_map_set(core_link, SL_CORE_INFO_MAP_LLR_STARVED);
+
+	sl_core_log_warn_trace(core_link, LOG_NAME, "llr starved occurred");
+
+	while (sl_core_hw_intr_flgs_enable(core_link, SL_CORE_HW_INTR_LINK_LLR_STARVED) == -EALREADY) {
+		rtn = sl_core_data_link_state_get(core_link, &link_state);
+		if (rtn) {
+			sl_core_log_err_trace(core_link, LOG_NAME,
+					      "llr starved intr work link_state_get failed [%d]", rtn);
+			return;
+		}
+
+		switch (link_state) {
+		case SL_CORE_LINK_STATE_GOING_DOWN:
+		case SL_CORE_LINK_STATE_CANCELING:
+		case SL_CORE_LINK_STATE_TIMEOUT:
+			sl_core_log_err_trace(core_link, LOG_NAME,
+					      "llr starved intr work invalid state (state = %u %s)",
+					      link_state, sl_core_link_state_str(link_state));
+			return;
+		default:
+			sl_core_log_dbg(core_link, LOG_NAME,
+					"llr starved intr work clearing flags (state = %u %s)",
+					link_state, sl_core_link_state_str(link_state));
+			usleep_range(10000, 12000);
+			sl_core_hw_intr_flgs_clr(core_link, SL_CORE_HW_INTR_LINK_LLR_STARVED);
+			continue;
+		}
+	}
+
+	sl_core_data_link_info_map_clr(core_link, SL_CORE_INFO_MAP_LLR_STARVED);
+}
+
+static void sl_core_hw_link_fault_callback_start(struct sl_core_link *core_link)
+{
+	enum sl_core_link_state link_state;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "fault callback start");
+
+	spin_lock(&core_link->link.data_lock);
+	link_state = core_link->link.state;
+	switch (link_state) {
+	case SL_CORE_LINK_STATE_UP:
+		core_link->link.state = SL_CORE_LINK_STATE_GOING_DOWN;
+		spin_unlock(&core_link->link.data_lock);
+		core_link->config.fault_start_callback(core_link->core_lgrp->core_ldev->num,
+						       core_link->core_lgrp->num, core_link->num);
+		break;
+	default:
+		sl_core_log_dbg(core_link, LOG_NAME,
+				"fault callback start invalid state (link_state = %u %s)",
+				link_state, sl_core_link_state_str(link_state));
+		spin_unlock(&core_link->link.data_lock);
+		return;
+	}
+}
+
+static void sl_core_hw_link_fault_link_down(struct sl_core_link *core_link)
+{
+	struct sl_ctrl_link *held_link_1 __free(sl_ctrl_link_put) = NULL;
+	int                                 rtn;
+	struct sl_core_link_fec_cw_cntrs    cw_cntrs;
+	struct sl_core_link_fec_lane_cntrs  lane_cntrs;
+	struct sl_core_link_fec_tail_cntrs  tail_cntrs;
+	struct sl_media_lgrp               *media_lgrp;
+	u8                                  temperature_state;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "fault link down");
+
+	rtn = sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_LINK_UP);
+	if (rtn != 0)
+		sl_core_log_warn_trace(core_link, LOG_NAME,
+				       "fault link down link up disable failed [%d]", rtn);
+	if (core_link->num == 0) {
+		rtn = sl_core_hw_intr_flgs_disable(core_link, SL_CORE_HW_INTR_LANE_DEGRADE);
+		if (rtn != 0)
+			sl_core_log_warn_trace(core_link, LOG_NAME,
+					       "fault link down lane degrade disable failed [%d]", rtn);
+	}
+
+	rtn = sl_core_hw_fec_data_get(core_link, &cw_cntrs, &lane_cntrs, &tail_cntrs);
+	if (rtn) {
+		sl_core_log_warn_trace(core_link, LOG_NAME,
+				       "fault link down hw_fec_data_get failed [%d]", rtn);
+	} else {
+		held_link_1 = sl_ctrl_link_get(core_link->core_lgrp->core_ldev->num,
+					       core_link->core_lgrp->num, core_link->num);
+		if (held_link_1)
+			sl_ctrl_link_fec_down_cache_store(held_link_1,
+							  &cw_cntrs, &lane_cntrs, &tail_cntrs);
+	}
+
+	sl_core_hw_link_off(core_link);
+
+	if (!sl_core_hw_link_is_media_present(core_link))
+		sl_core_data_link_last_down_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_NO_MEDIA);
+	if (!is_flag_set(sl_core_data_lgrp_config_flags_get(core_link->core_lgrp),
+			 SL_LGRP_CONFIG_OPT_SERDES_LOOPBACK_ENABLE)) {
+		if (sl_media_lgrp_media_type_is_active(core_link->core_lgrp->core_ldev->num,
+						       core_link->core_lgrp->num)) {
+			media_lgrp = sl_media_lgrp_get(core_link->core_lgrp->core_ldev->num, core_link->core_lgrp->num);
+			rtn  = sl_media_jack_cable_temp_state_get(media_lgrp->media_jack, &temperature_state);
+			if (rtn)
+				sl_core_log_warn_trace(core_link, LOG_NAME,
+						       "fault link down cable_temp_state_get failed [%d]", rtn);
+
+			if (temperature_state ==   SL_MEDIA_JACK_TEMP_STATE_HOT) {
+				sl_core_log_warn_trace(core_link, LOG_NAME,
+						       "fault link down cable hot detected");
+				sl_core_data_link_last_down_cause_map_set(core_link,
+									  SL_LINK_DOWN_CAUSE_MEDIA_HOT_FAULT_MAP);
+				sl_media_jack_cable_low_power_set(media_lgrp->media_jack);
+			}
+		}
+	}
+	sl_core_data_link_state_set(core_link, SL_CORE_LINK_STATE_DOWN);
+
+	rtn = core_link->config.fault_callback(core_link->link.tags.up, SL_CORE_LINK_STATE_DOWN,
+					       sl_core_data_link_last_down_cause_map_get(core_link),
+					       sl_core_data_link_info_map_get(core_link));
+	if (rtn != 0)
+		sl_core_log_warn_trace(core_link, LOG_NAME,
+				       "fault link down callback failed [%d]", rtn);
+
+	sl_core_data_link_info_map_clr(core_link, SL_CORE_INFO_MAP_NUM_BITS);
+}
+
+static bool sl_core_hw_link_is_pml_rec_window_valid(struct sl_core_link *core_link, ktime_t current_time)
+{
+	sl_core_log_dbg(core_link, LOG_NAME, "is pml rec window valid");
+
+	if (ktime_ms_delta(current_time, core_link->pml_rec.pml_rec_window_start_time) >
+	    core_link->config.pml_rec_rate_limit_window_size_ms)
+		return false;
+
+	return true;
+}
+
+static void sl_core_hw_link_pml_rec_success(struct sl_core_link *core_link)
+{
+	struct sl_ctrl_lgrp     *ctrl_lgrp;
+	union sl_lgrp_notif_info info;
+	int                      rtn;
+
+	ctrl_lgrp = sl_ctrl_lgrp_get(core_link->core_lgrp->core_ldev->num, core_link->core_lgrp->num);
+
+	sl_core_log_dbg(core_link, LOG_NAME, "pml recovery success work");
+
+	info.pml_rec_info = core_link->pml_rec.pml_rec_info;
+	rtn = sl_ctrl_lgrp_notif_enqueue(ctrl_lgrp, core_link->num, SL_LGRP_NOTIF_PML_RECOVERY, &info, 0);
+	if (rtn)
+		sl_core_log_warn_trace(core_link, LOG_NAME,
+				       "pml recovery success work ctrl_lgrp_notif_enqueue failed [%d]", rtn);
+
+	msleep(200);
+	sl_core_hw_intr_flgs_clr(core_link, SL_CORE_HW_INTR_LINK_FAULT);
+
+	rtn = sl_core_hw_intr_flgs_enable(core_link, SL_CORE_HW_INTR_LINK_FAULT);
+	if (rtn)
+		sl_core_log_warn_trace(core_link, LOG_NAME,
+				       "pml recovery success work intr flgs enable failed [%d]", rtn);
+}
+
+static void sl_core_hw_link_pml_rec_fail(struct sl_core_link *core_link)
+{
+	struct sl_ctrl_lgrp     *ctrl_lgrp;
+	union sl_lgrp_notif_info info;
+	int                      rtn;
+
+	ctrl_lgrp = sl_ctrl_lgrp_get(core_link->core_lgrp->core_ldev->num, core_link->core_lgrp->num);
+
+	sl_core_log_dbg(core_link, LOG_NAME, "pml recovery fail work");
+
+	info.pml_rec_info = core_link->pml_rec.pml_rec_info;
+	rtn = sl_ctrl_lgrp_notif_enqueue(ctrl_lgrp, core_link->num, SL_LGRP_NOTIF_PML_RECOVERY, &info, 0);
+	if (rtn)
+		sl_media_log_warn_trace(core_link, LOG_NAME,
+					"pml recovery fail work ctrl_lgrp_notif_enqueue failed [%d]", rtn);
+
+	sl_core_hw_link_fault_callback_start(core_link);
+
+	sl_media_jack_led_set(core_link->core_lgrp->core_ldev->num, core_link->core_lgrp->num);
+
+	sl_core_data_link_info_map_clr(core_link, SL_CORE_INFO_MAP_NUM_BITS);
+
+	if (core_link->pml_rec.pml_rec_last_down_cause == PML_REC_DOWN_CAUSE_LOCAL_FAULT) {
+		sl_core_log_err_trace(core_link, LOG_NAME, "local fault occurred");
+		sl_core_data_link_info_map_set(core_link, SL_CORE_INFO_MAP_PCS_LOCAL_FAULT);
+		if (!(sl_core_data_link_last_down_cause_map_get(core_link) & SL_LINK_DOWN_CAUSE_COMMAND))
+			sl_core_data_link_last_down_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_LF_MAP);
+	} else if (core_link->pml_rec.pml_rec_last_down_cause == PML_REC_DOWN_CAUSE_LINK_DOWN) {
+		sl_core_log_err_trace(core_link, LOG_NAME, "link down occurred");
+		sl_core_data_link_info_map_set(core_link, SL_CORE_INFO_MAP_PCS_LINK_DOWN);
+		if (!(sl_core_data_link_last_down_cause_map_get(core_link) & SL_LINK_DOWN_CAUSE_COMMAND))
+			sl_core_data_link_last_down_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_DOWN_MAP);
+	}
+
+	sl_core_hw_link_fault_link_down(core_link);
+}
+
+void sl_core_hw_link_pml_rec_poll_work(struct work_struct *work)
+{
+	struct sl_core_link *core_link;
+	ktime_t              current_time;
+	s64                  elapsed_time;
+
+	core_link = container_of(work, struct sl_core_link, work[SL_CORE_WORK_LINK_PML_REC_POLL]);
+
+	sl_core_log_dbg(core_link, LOG_NAME, "pml rec poll work");
+
+	while (1) {
+		if (atomic_read(&core_link->pml_rec.pml_rec_running) == 0)
+			return;
+
+		current_time = ktime_get();
+
+		if (!sl_core_hw_link_is_pml_rec_window_valid(core_link, current_time)) {
+			sl_core_log_dbg(core_link, LOG_NAME, "pml rec poll work window elapsed");
+			core_link->pml_rec.pml_rec_window_start_time   = current_time;
+			core_link->pml_rec.pml_rec_poll_start_time     = current_time;
+			core_link->pml_rec.pml_rec_attempts_total_time = 0;
+		}
+
+		core_link->pml_rec.pml_rec_attempts_total_time = ktime_add(core_link->pml_rec.pml_rec_attempts_total_time,
+									   ktime_sub(current_time, core_link->pml_rec.pml_rec_poll_start_time));
+
+		sl_core_log_dbg(core_link, LOG_NAME, "pml rec poll work (attempt_total_time = %lldms)",
+				ktime_to_ms(core_link->pml_rec.pml_rec_attempts_total_time));
+
+		if (sl_core_hw_pcs_is_pml_rec_success(core_link)) {
+
+			elapsed_time = ktime_ms_delta(current_time, core_link->pml_rec.pml_rec_attempt_start_time);
+			sl_core_log_warn_trace(core_link, LOG_NAME,
+					       "pml rec poll work successful (elapsed_time = %lldms, down_cause = %s)",
+					       elapsed_time,
+					       sl_core_link_pml_rec_down_cause_str(core_link->pml_rec.pml_rec_last_down_cause));
+
+			atomic_inc(&core_link->pml_rec.pml_rec_info.pml_rec_counters[SL_LINK_PML_REC_SUCCESSES]);
+			atomic_set(&core_link->pml_rec.pml_rec_running, 0);
+
+			sl_core_hw_link_pml_rec_success(core_link);
+
+			return;
+		}
+
+		if (ktime_ms_delta(current_time, core_link->pml_rec.pml_rec_attempt_start_time) >
+		    core_link->config.pml_rec_timeout_ms) {
+
+			elapsed_time = ktime_ms_delta(current_time, core_link->pml_rec.pml_rec_attempt_start_time);
+			sl_core_log_err_trace(core_link, LOG_NAME,
+					      "pml rec poll work timedout (elapsed_time = %lldms, down_cause = %s)",
+					      elapsed_time,
+					      sl_core_link_pml_rec_down_cause_str(core_link->pml_rec.pml_rec_last_down_cause));
+
+			if (core_link->pml_rec.pml_rec_last_down_cause == PML_REC_DOWN_CAUSE_LOCAL_FAULT)
+				atomic_inc(&core_link->pml_rec.pml_rec_info.pml_rec_counters[SL_LINK_PML_REC_LINK_LOCAL_FAULT_FAILED_CAUSE]);
+			else if (core_link->pml_rec.pml_rec_last_down_cause == PML_REC_DOWN_CAUSE_LINK_DOWN)
+				atomic_inc(&core_link->pml_rec.pml_rec_info.pml_rec_counters[SL_LINK_PML_REC_LINK_DOWN_FAILED_CAUSE]);
+
+			atomic_set(&core_link->pml_rec.pml_rec_running, 0);
+
+			sl_core_hw_link_pml_rec_fail(core_link);
+
+			return;
+		}
+
+		if (ktime_to_ms(core_link->pml_rec.pml_rec_attempts_total_time) >
+		    core_link->config.pml_rec_rate_limit_max_time_ms) {
+			sl_core_log_err_trace(core_link, LOG_NAME, "pml recovery rate limit exceeded");
+
+			if (core_link->pml_rec.pml_rec_last_down_cause == PML_REC_DOWN_CAUSE_LOCAL_FAULT)
+				atomic_inc(&core_link->pml_rec.pml_rec_info.pml_rec_counters[SL_LINK_PML_REC_LINK_LOCAL_FAULT_FAILED_CAUSE]);
+			else if (core_link->pml_rec.pml_rec_last_down_cause == PML_REC_DOWN_CAUSE_LINK_DOWN)
+				atomic_inc(&core_link->pml_rec.pml_rec_info.pml_rec_counters[SL_LINK_PML_REC_LINK_DOWN_FAILED_CAUSE]);
+
+			atomic_inc(&core_link->pml_rec.pml_rec_info.pml_rec_counters[SL_LINK_PML_REC_RATE_LIMIT_EXCEEDED]);
+			atomic_set(&core_link->pml_rec.pml_rec_running, 0);
+			atomic_set(&core_link->pml_rec.pml_rec_rate_limit_exceeded, 1);
+
+			sl_core_hw_link_pml_rec_fail(core_link);
+
+			return;
+		}
+
+		core_link->pml_rec.pml_rec_poll_start_time = current_time;
+
+		usleep_range(3500, 4000);
+	}
+}
+
+static void sl_core_hw_link_pml_recovery(struct sl_core_link *core_link)
+{
+	ktime_t current_time;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "pml recovery");
+
+	core_link->pml_rec.pml_rec_info.magic = SL_LINK_PML_REC_MAGIC;
+	core_link->pml_rec.pml_rec_info.ver   = SL_LINK_PML_REC_VER;
+	core_link->pml_rec.pml_rec_info.size  = sizeof(struct sl_link_pml_rec_info);
+
+	atomic_set(&core_link->pml_rec.pml_rec_running, 1);
+
+	current_time = ktime_get();
+
+	if ((core_link->pml_rec.pml_rec_window_start_time == 0) ||
+	    (!sl_core_hw_link_is_pml_rec_window_valid(core_link, current_time))) {
+
+		core_link->pml_rec.pml_rec_window_start_time   = current_time;
+		core_link->pml_rec.pml_rec_attempts_total_time = 0;
+	}
+
+	core_link->pml_rec.pml_rec_attempt_start_time = current_time;
+	core_link->pml_rec.pml_rec_poll_start_time    = current_time;
+
+	sl_core_hw_pcs_toggle(core_link);
+
+	atomic_inc(&core_link->pml_rec.pml_rec_info.pml_rec_counters[SL_LINK_PML_REC_ATTEMPTS]);
+
+	queue_work(core_link->core_lgrp->core_ldev->workqueue, &core_link->work[SL_CORE_WORK_LINK_PML_REC_POLL]);
+}
+
+static inline void sl_core_hw_link_fault_handling_start(struct sl_core_link *core_link)
+{
+	sl_core_hw_link_fault_callback_start(core_link);
+	sl_media_jack_led_set(core_link->core_lgrp->core_ldev->num,
+			      core_link->core_lgrp->num);
+}
+
+void sl_core_hw_link_fault_intr_work(struct work_struct *work)
+{
+	u64                  link_down;
+	u64                  remote_fault;
+	u64                  local_fault;
+	u64                  llr_replay_max;
+	struct sl_core_link *core_link;
+	u64                  data64;
+	u64                  replay_ct_max;
+	u32                  port;
+	int                  rtn;
+	ktime_t              current_time;
+
+	core_link = container_of(work, struct sl_core_link, work[SL_CORE_WORK_LINK_FAULT_INTR]);
+	port      = core_link->core_lgrp->num;
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"fault intr work (port = %u, flgs = 0x%016llX, 0x%016llX, 0x%016llX, 0x%016llX)",
+			port,
+			core_link->intrs[SL_CORE_HW_INTR_LINK_FAULT].source[0],
+			core_link->intrs[SL_CORE_HW_INTR_LINK_FAULT].source[1],
+			core_link->intrs[SL_CORE_HW_INTR_LINK_FAULT].source[2],
+			core_link->intrs[SL_CORE_HW_INTR_LINK_FAULT].source[3]);
+
+	switch (core_link->num) {
+	case 0:
+		link_down =
+		SS2_PORT_PML_ERR_FLG_WORD1_PCS_LINK_DOWN_0_GET(core_link->intrs[SL_CORE_HW_INTR_LINK_FAULT].source[1]);
+		remote_fault =
+		SS2_PORT_PML_ERR_FLG_WORD1_PCS_LINK_DOWN_RF_0_GET(core_link->intrs[SL_CORE_HW_INTR_LINK_FAULT].source[1]);
+		local_fault =
+		SS2_PORT_PML_ERR_FLG_WORD1_PCS_LINK_DOWN_LF_0_GET(core_link->intrs[SL_CORE_HW_INTR_LINK_FAULT].source[1]);
+		llr_replay_max =
+		SS2_PORT_PML_ERR_FLG_WORD1_LLR_REPLAY_AT_MAX_0_GET(core_link->intrs[SL_CORE_HW_INTR_LINK_FAULT].source[1]);
+		break;
+	case 1:
+		link_down =
+		SS2_PORT_PML_ERR_FLG_WORD1_PCS_LINK_DOWN_1_GET(core_link->intrs[SL_CORE_HW_INTR_LINK_FAULT].source[1]);
+		remote_fault =
+		SS2_PORT_PML_ERR_FLG_WORD1_PCS_LINK_DOWN_RF_1_GET(core_link->intrs[SL_CORE_HW_INTR_LINK_FAULT].source[1]);
+		local_fault =
+		SS2_PORT_PML_ERR_FLG_WORD1_PCS_LINK_DOWN_LF_1_GET(core_link->intrs[SL_CORE_HW_INTR_LINK_FAULT].source[1]);
+		llr_replay_max =
+		SS2_PORT_PML_ERR_FLG_WORD1_LLR_REPLAY_AT_MAX_1_GET(core_link->intrs[SL_CORE_HW_INTR_LINK_FAULT].source[1]);
+		break;
+	case 2:
+		link_down =
+		SS2_PORT_PML_ERR_FLG_WORD1_PCS_LINK_DOWN_2_GET(core_link->intrs[SL_CORE_HW_INTR_LINK_FAULT].source[1]);
+		remote_fault =
+		SS2_PORT_PML_ERR_FLG_WORD1_PCS_LINK_DOWN_RF_2_GET(core_link->intrs[SL_CORE_HW_INTR_LINK_FAULT].source[1]);
+		local_fault =
+		SS2_PORT_PML_ERR_FLG_WORD1_PCS_LINK_DOWN_LF_2_GET(core_link->intrs[SL_CORE_HW_INTR_LINK_FAULT].source[1]);
+		llr_replay_max =
+		SS2_PORT_PML_ERR_FLG_WORD1_LLR_REPLAY_AT_MAX_2_GET(core_link->intrs[SL_CORE_HW_INTR_LINK_FAULT].source[1]);
+		break;
+	case 3:
+		link_down =
+		SS2_PORT_PML_ERR_FLG_WORD1_PCS_LINK_DOWN_3_GET(core_link->intrs[SL_CORE_HW_INTR_LINK_FAULT].source[1]);
+		remote_fault =
+		SS2_PORT_PML_ERR_FLG_WORD1_PCS_LINK_DOWN_RF_3_GET(core_link->intrs[SL_CORE_HW_INTR_LINK_FAULT].source[1]);
+		local_fault =
+		SS2_PORT_PML_ERR_FLG_WORD1_PCS_LINK_DOWN_LF_3_GET(core_link->intrs[SL_CORE_HW_INTR_LINK_FAULT].source[1]);
+		llr_replay_max =
+		SS2_PORT_PML_ERR_FLG_WORD1_LLR_REPLAY_AT_MAX_3_GET(core_link->intrs[SL_CORE_HW_INTR_LINK_FAULT].source[1]);
+		break;
+	default:
+		link_down      = 0;
+		remote_fault   = 0;
+		local_fault    = 0;
+		llr_replay_max = 0;
+		break;
+	}
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"fault intr work (llr_replay = 0x%llX, local = 0x%llX, remote = 0x%llX, down = 0x%llX)",
+			llr_replay_max, local_fault, remote_fault, link_down);
+
+	if (llr_replay_max) {
+		sl_core_log_dbg(core_link, LOG_NAME, "fault intr work LLR replay max");
+		goto link_down;
+	}
+
+	if (!sl_core_link_config_is_enable_pml_recovery_set(core_link)) {
+		sl_core_log_dbg(core_link, LOG_NAME, "fault intr work PML recovery not set");
+		goto link_down;
+	}
+
+	if (sl_core_link_is_pml_recovery_running(core_link)) {
+		sl_core_log_dbg(core_link, LOG_NAME, "fault intr work PML recovery running already");
+		goto link_down;
+	}
+
+	current_time = ktime_get();
+	if (sl_core_hw_link_is_pml_rec_window_valid(core_link, current_time)) {
+		if (ktime_to_ms(core_link->pml_rec.pml_rec_attempts_total_time) >
+		    core_link->config.pml_rec_rate_limit_max_time_ms) {
+			if (atomic_read(&core_link->pml_rec.pml_rec_rate_limit_exceeded) == 0) {
+				atomic_set(&core_link->pml_rec.pml_rec_rate_limit_exceeded, 1);
+				atomic_inc(&core_link->pml_rec.pml_rec_info.pml_rec_counters[SL_LINK_PML_REC_RATE_LIMIT_EXCEEDED]);
+			}
+
+			sl_core_log_err_trace(core_link, LOG_NAME,
+					      "fault intr work rate limit exceeded for this window");
+			goto link_down;
+		}
+	}
+
+	atomic_set(&core_link->pml_rec.pml_rec_rate_limit_exceeded, 0);
+
+	if (local_fault) {
+		if (atomic_read(&core_link->pml_rec.pml_rec_down_cause_remote_fault) == 1) {
+			sl_core_log_err_trace(core_link, LOG_NAME,
+					      "fault intr work link down ignored remote fault previously");
+			goto link_down;
+		}
+
+		atomic_inc(&core_link->pml_rec.pml_rec_info.pml_rec_counters[SL_LINK_PML_REC_LINK_LOCAL_FAULT_CAUSE]);
+
+		core_link->pml_rec.pml_rec_last_down_cause = PML_REC_DOWN_CAUSE_LOCAL_FAULT;
+		sl_core_hw_link_pml_recovery(core_link);
+		return;
+	} else if (link_down) {
+		if (atomic_read(&core_link->pml_rec.pml_rec_down_cause_remote_fault) == 1) {
+			sl_core_log_err_trace(core_link, LOG_NAME,
+					      "fault intr work link down ignored remote fault previously");
+			goto link_down;
+		}
+
+		atomic_inc(&core_link->pml_rec.pml_rec_info.pml_rec_counters[SL_LINK_PML_REC_LINK_DOWN_CAUSE]);
+
+		core_link->pml_rec.pml_rec_last_down_cause = PML_REC_DOWN_CAUSE_LINK_DOWN;
+		sl_core_hw_link_pml_recovery(core_link);
+		return;
+	} else if (remote_fault) {
+		core_link->pml_rec.pml_rec_last_down_cause = PML_REC_DOWN_CAUSE_REMOTE_FAULT;
+		atomic_set(&core_link->pml_rec.pml_rec_down_cause_remote_fault, 1);
+
+		msleep(200);
+		sl_core_hw_intr_flgs_clr(core_link, SL_CORE_HW_INTR_LINK_FAULT);
+
+		rtn = sl_core_hw_intr_flgs_enable(core_link, SL_CORE_HW_INTR_LINK_FAULT);
+		if (rtn)
+			sl_core_log_warn_trace(core_link, LOG_NAME,
+					       "fault intr work intr flgs enable failed [%d]", rtn);
+		return;
+	}
+
+link_down:
+	sl_core_data_link_info_map_clr(core_link, SL_CORE_INFO_MAP_NUM_BITS);
+
+	if (sl_core_link_config_is_enable_pml_recovery_set(core_link) &&
+	    atomic_read(&core_link->pml_rec.pml_rec_down_cause_remote_fault) == 1) {
+		sl_core_log_warn_trace(core_link, LOG_NAME,
+				       "fault intr work setting down cause as remote fault because ignored previously");
+		sl_core_hw_link_fault_handling_start(core_link);
+		sl_core_data_link_info_map_set(core_link, SL_CORE_INFO_MAP_PCS_REMOTE_FAULT);
+		if (!(sl_core_data_link_last_down_cause_map_get(core_link) & SL_LINK_DOWN_CAUSE_COMMAND))
+			sl_core_data_link_last_down_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_RF_MAP);
+		goto out;
+	}
+
+	if (llr_replay_max) {
+		sl_core_read64(core_link, SS2_PORT_PML_CFG_LLR_SM(core_link->num), &data64);
+		replay_ct_max = SS2_PORT_PML_CFG_LLR_SM_REPLAY_CT_MAX_GET(data64);
+
+		if (replay_ct_max == 0xFF && !local_fault && !remote_fault && !link_down) {
+			sl_core_log_err_trace(core_link, LOG_NAME, "llr replay max occurred, ignored");
+			msleep(200);
+			sl_core_hw_intr_flgs_clr(core_link, SL_CORE_HW_INTR_LINK_FAULT);
+
+			rtn = sl_core_hw_intr_flgs_enable(core_link, SL_CORE_HW_INTR_LINK_FAULT);
+			if (rtn)
+				sl_core_log_warn_trace(core_link, LOG_NAME,
+						       "fault intr work intr flgs enable failed [%d]", rtn);
+			return;
+		}
+
+		sl_core_log_err_trace(core_link, LOG_NAME, "llr replay max occurred");
+		sl_core_hw_link_fault_handling_start(core_link);
+		sl_core_data_link_info_map_set(core_link, SL_CORE_INFO_MAP_LLR_REPLAY_MAX);
+		if (!(sl_core_data_link_last_down_cause_map_get(core_link) & SL_LINK_DOWN_CAUSE_COMMAND))
+			sl_core_data_link_last_down_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_LLR_REPLAY_MAX_MAP);
+	}
+
+	if (local_fault) {
+		sl_core_log_err_trace(core_link, LOG_NAME, "local fault occurred");
+		sl_core_hw_link_fault_handling_start(core_link);
+		sl_core_data_link_info_map_set(core_link, SL_CORE_INFO_MAP_PCS_LOCAL_FAULT);
+		if (!(sl_core_data_link_last_down_cause_map_get(core_link) & SL_LINK_DOWN_CAUSE_COMMAND))
+			sl_core_data_link_last_down_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_LF_MAP);
+	}
+
+	if (remote_fault) {
+		sl_core_log_err_trace(core_link, LOG_NAME, "remote fault occurred");
+		sl_core_hw_link_fault_handling_start(core_link);
+		sl_core_data_link_info_map_set(core_link, SL_CORE_INFO_MAP_PCS_REMOTE_FAULT);
+		if (!(sl_core_data_link_last_down_cause_map_get(core_link) & SL_LINK_DOWN_CAUSE_COMMAND))
+			sl_core_data_link_last_down_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_RF_MAP);
+	}
+
+	if (link_down) {
+		sl_core_log_err_trace(core_link, LOG_NAME, "link down occurred");
+		sl_core_hw_link_fault_handling_start(core_link);
+		sl_core_data_link_info_map_set(core_link, SL_CORE_INFO_MAP_PCS_LINK_DOWN);
+		if (!(sl_core_data_link_last_down_cause_map_get(core_link) & SL_LINK_DOWN_CAUSE_COMMAND))
+			sl_core_data_link_last_down_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_DOWN_MAP);
+	}
+
+out:
+	sl_core_hw_link_fault_link_down(core_link);
+}
+
+static inline int sl_core_hw_link_speed_get(u32 pcs_mode, int hweight)
+{
+    return hweight * (pcs_mode == SL_CORE_HW_PCS_MODE_CK_400G ? 100 : 50);
+}
+
+void sl_core_hw_link_lane_degrade_intr_work(struct work_struct *work)
+{
+	struct sl_core_link        *core_link;
+	union sl_lgrp_notif_info    info;
+	struct sl_link_degrade_info ald_info;
+	bool                        is_recoverable;
+	u32                         port;
+	u64                         val64;
+	u64                         data64;
+	int                         rtn;
+
+	core_link = container_of(work, struct sl_core_link, work[SL_CORE_WORK_LINK_LANE_DEGRADE_INTR]);
+	port      = core_link->core_lgrp->num;
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"lane degrade intr work (port = %u, source = 0x%016llX)",
+			port, core_link->intrs[SL_CORE_HW_INTR_LANE_DEGRADE].source[1]);
+
+	sl_core_data_link_info_map_set(core_link, SL_CORE_INFO_MAP_LINK_DEGRADED);
+
+	/* wait before reading CSR so the lane degrade values stabilize */
+	msleep(20);
+
+	sl_core_read64(core_link, SS2_PORT_PML_STS_PCS_LANE_DEGRADE, &data64);
+
+	val64 = SS2_PORT_PML_STS_PCS_LANE_DEGRADE_WORD0_RX_PLS_AVAILABLE_GET(data64);
+	ald_info.rx_degrade_map = (u8)val64;
+
+	val64 = SS2_PORT_PML_STS_PCS_LANE_DEGRADE_WORD0_LP_PLS_AVAILABLE_GET(data64);
+	ald_info.tx_degrade_map = (u8)val64;
+
+	if ((ald_info.rx_degrade_map != core_link->degrade_info.rx_degrade_map) &&
+	    (ald_info.rx_degrade_map != 0xF))
+		ald_info.is_rx_degrade = true;
+	else
+		ald_info.is_rx_degrade = false;
+
+	if ((ald_info.tx_degrade_map != core_link->degrade_info.tx_degrade_map) &&
+	    (ald_info.tx_degrade_map != 0xF))
+		ald_info.is_tx_degrade = true;
+	else
+		ald_info.is_tx_degrade = false;
+
+	ald_info.rx_link_speed = sl_core_hw_link_speed_get(core_link->pcs.settings.pcs_mode,
+							   hweight8(ald_info.rx_degrade_map));
+	ald_info.tx_link_speed = sl_core_hw_link_speed_get(core_link->pcs.settings.pcs_mode,
+							   hweight8(ald_info.tx_degrade_map));
+
+	core_link->degrade_info.magic = SL_LINK_DEGRADE_INFO_MAGIC;
+	core_link->degrade_info.ver   = SL_LINK_DEGRADE_INFO_VER;
+	core_link->degrade_info.size  = sizeof(struct sl_link_degrade_info);
+
+	spin_lock(&core_link->data_lock);
+	core_link->degrade_info = ald_info;
+	info.degrade_info       = ald_info;
+	spin_unlock(&core_link->data_lock);
+
+	sl_core_hw_serdes_degraded_lanes_state_set(core_link, ald_info.tx_degrade_map, ald_info.rx_degrade_map);
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"lane degrade intr work (is_rx_degrade = %s, rx_degrade_map = 0x%X, rx_link_speed = %u)",
+			info.degrade_info.is_rx_degrade ? "yes" : "no",
+			info.degrade_info.rx_degrade_map, info.degrade_info.rx_link_speed);
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"lane degrade intr work (is_tx_degrade = %s, tx_degrade_map = 0x%X, tx_link_speed = %u)",
+			info.degrade_info.is_tx_degrade ? "yes" : "no",
+			info.degrade_info.tx_degrade_map, info.degrade_info.tx_link_speed);
+
+	rtn = sl_ctrl_lgrp_notif_enqueue(sl_ctrl_lgrp_get(core_link->core_lgrp->core_ldev->num,
+							  core_link->core_lgrp->num),
+					 core_link->num, SL_LGRP_NOTIF_LANE_DEGRADE, &info, 0);
+	if (rtn)
+		sl_media_log_warn_trace(core_link, LOG_NAME,
+					"lane degrade intr work ctrl_lgrp_notif_enqueue failed [%d]", rtn);
+
+	rtn = sl_core_hw_serdes_lanes_up_prbs(core_link, ald_info.tx_degrade_map, ald_info.rx_degrade_map);
+	if (rtn) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "lane degrade intr work lanes up prbs failed [%d] (tx_degrade_map = 0x%X, rx_degrade_map = 0x%X)",
+				      rtn, ald_info.tx_degrade_map, ald_info.rx_degrade_map);
+		is_recoverable = false;
+	} else {
+		is_recoverable = true;
+	}
+
+	spin_lock(&core_link->data_lock);
+	core_link->degrade_info.is_recoverable = is_recoverable;
+	info.is_degrade_recoverable = is_recoverable;
+	spin_unlock(&core_link->data_lock);
+
+	sl_core_log_dbg(core_link, LOG_NAME, "lane degrade intr work (is_recoverable = %s)",
+			info.is_degrade_recoverable ? "yes" : "no");
+
+	rtn = sl_ctrl_lgrp_notif_enqueue(sl_ctrl_lgrp_get(core_link->core_lgrp->core_ldev->num,
+							  core_link->core_lgrp->num),
+					 core_link->num, SL_LGRP_NOTIF_LANE_DEGRADE_RECOVERY, &info, 0);
+	if (rtn)
+		sl_media_log_warn_trace(core_link, LOG_NAME,
+					"lane degrade intr work ctrl_lgrp_notif_enqueue failed [%d]", rtn);
+
+	sl_core_hw_intr_flgs_clr(core_link, SL_CORE_HW_INTR_LANE_DEGRADE);
+	rtn = sl_core_hw_intr_flgs_enable(core_link, SL_CORE_HW_INTR_LANE_DEGRADE);
+	if (rtn)
+		sl_core_log_err_trace(core_link, LOG_NAME, "lane degrade intr work ald enable failed [%d]", rtn);
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_llr.c b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_llr.c
new file mode 100644
index 000000000000..dbfc6ceff294
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_llr.c
@@ -0,0 +1,905 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2022-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/workqueue.h>
+
+#include "sl_core_str.h"
+#include "sl_core_link.h"
+#include "sl_core_llr.h"
+#include "base/sl_core_timer_llr.h"
+#include "base/sl_core_log.h"
+#include "data/sl_core_data_llr.h"
+#include "hw/sl_core_hw_io.h"
+#include "hw/sl_core_hw_llr.h"
+#include "hw/sl_core_hw_pcs.h"
+
+#define SL_CORE_LLR_BYTES_PER_FRAME    9216ULL
+#define SL_CORE_LLR_NUM_FRAMES         2ULL
+#define SL_CORE_LLR_BYTE_QUANTA        64ULL
+#define SL_CORE_LLR_FRAME_SIZE         32ULL
+#define SL_CORE_LLR_ASIC_TX_DELAY_MS   25
+#define SL_CORE_LLR_ASIC_RX_DELAY_MS   91
+
+#define SL_CORE_LLR_STOP_TIMEOUT       2000
+
+#define LOG_NAME SL_CORE_HW_LLR_LOG_NAME
+
+void sl_core_hw_llr_link_init(struct sl_core_link *core_link)
+{
+	u32 port;
+	u64 data64;
+
+	port = core_link->core_lgrp->num;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "link init (port = %u)", port);
+
+	sl_core_read64(core_link, SS2_PORT_PML_CFG_LLR_SUBPORT(core_link->num), &data64);
+	data64 = SS2_PORT_PML_CFG_LLR_SUBPORT_LINK_DOWN_BEHAVIOR_UPDATE(data64,
+									SS2_PORT_PML_LINK_DN_BEHAVIOR_T_LD_DISCARD);
+	sl_core_write64(core_link, SS2_PORT_PML_CFG_LLR_SUBPORT(core_link->num), data64);
+
+	sl_core_flush64(core_link, SS2_PORT_PML_CFG_LLR_SUBPORT(core_link->num));
+}
+
+static void sl_core_hw_llr_setup_callback(struct sl_core_llr *core_llr)
+{
+	sl_core_log_dbg(core_llr, LOG_NAME, "setup callback");
+
+	core_llr->callbacks.setup(core_llr->tag, core_llr->state,
+		core_llr->info_map, core_llr->data);
+}
+
+static void sl_core_hw_llr_start_callback(struct sl_core_llr *core_llr)
+{
+	sl_core_log_dbg(core_llr, LOG_NAME, "start callback");
+
+	core_llr->callbacks.start(core_llr->tag, core_llr->state, core_llr->info_map);
+}
+
+static void sl_core_hw_llr_loop_time_start(struct sl_core_llr *core_llr)
+{
+	u32 port;
+	u64 data64;
+
+	port = core_llr->core_lgrp->num;
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "loop time start (port = %d)", port);
+
+	sl_core_llr_read64(core_llr, SS2_PORT_PML_CFG_LLR_SUBPORT(core_llr->num), &data64);
+	data64 = SS2_PORT_PML_CFG_LLR_SUBPORT_ENABLE_LOOP_TIMING_UPDATE(data64, 1); /* enable */
+	sl_core_llr_write64(core_llr, SS2_PORT_PML_CFG_LLR_SUBPORT(core_llr->num), data64);
+
+	sl_core_llr_flush64(core_llr, SS2_PORT_PML_CFG_LLR_SUBPORT(core_llr->num));
+}
+
+static void sl_core_hw_llr_loop_time_stop(struct sl_core_llr *core_llr)
+{
+	u32 port;
+	u64 data64;
+
+	port = core_llr->core_lgrp->num;
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "loop time stop (port = %d)", port);
+
+	sl_core_llr_read64(core_llr, SS2_PORT_PML_CFG_LLR_SUBPORT(core_llr->num), &data64);
+	data64 = SS2_PORT_PML_CFG_LLR_SUBPORT_ENABLE_LOOP_TIMING_UPDATE(data64, 0); /* disable */
+	sl_core_llr_write64(core_llr, SS2_PORT_PML_CFG_LLR_SUBPORT(core_llr->num), data64);
+
+	sl_core_llr_flush64(core_llr, SS2_PORT_PML_CFG_LLR_SUBPORT(core_llr->num));
+}
+
+static void sl_core_hw_llr_ordered_sets_start(struct sl_core_llr *core_llr)
+{
+	u32 port;
+	u64 data64;
+
+	port = core_llr->core_lgrp->num;
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "ordered sets start (port = %d)", port);
+
+	sl_core_llr_read64(core_llr, SS2_PORT_PML_CFG_RX_PCS_SUBPORT(core_llr->num), &data64);
+	data64 = SS2_PORT_PML_CFG_RX_PCS_SUBPORT_ENABLE_CTL_OS_UPDATE(data64, 1); /* enable */
+	sl_core_llr_write64(core_llr, SS2_PORT_PML_CFG_RX_PCS_SUBPORT(core_llr->num), data64);
+
+	sl_core_llr_read64(core_llr, SS2_PORT_PML_CFG_TX_PCS_SUBPORT(core_llr->num), &data64);
+	data64 = SS2_PORT_PML_CFG_TX_PCS_SUBPORT_ENABLE_CTL_OS_UPDATE(data64, 1); /* enable */
+	sl_core_llr_write64(core_llr, SS2_PORT_PML_CFG_TX_PCS_SUBPORT(core_llr->num), data64);
+
+	sl_core_llr_flush64(core_llr, SS2_PORT_PML_CFG_LLR_SUBPORT(core_llr->num));
+}
+
+static void sl_core_hw_llr_ordered_sets_stop(struct sl_core_llr *core_llr)
+{
+	u32 port;
+	u64 data64;
+
+	port = core_llr->core_lgrp->num;
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "ordered sets stop (port = %d)", port);
+
+	sl_core_llr_read64(core_llr, SS2_PORT_PML_CFG_RX_PCS_SUBPORT(core_llr->num), &data64);
+	data64 = SS2_PORT_PML_CFG_RX_PCS_SUBPORT_ENABLE_CTL_OS_UPDATE(data64, 0); /* disable */
+	sl_core_llr_write64(core_llr, SS2_PORT_PML_CFG_RX_PCS_SUBPORT(core_llr->num), data64);
+
+	sl_core_llr_read64(core_llr, SS2_PORT_PML_CFG_TX_PCS_SUBPORT(core_llr->num), &data64);
+	data64 = SS2_PORT_PML_CFG_TX_PCS_SUBPORT_ENABLE_CTL_OS_UPDATE(data64, 0); /* disable */
+	sl_core_llr_write64(core_llr, SS2_PORT_PML_CFG_TX_PCS_SUBPORT(core_llr->num), data64);
+
+	sl_core_llr_flush64(core_llr, SS2_PORT_PML_CFG_LLR_SUBPORT(core_llr->num));
+}
+
+static void sl_core_hw_llr_on(struct sl_core_llr *core_llr)
+{
+	u32                  port;
+	u64                  data64;
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+
+	port = core_llr->core_lgrp->num;
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "on (port = %d)", port);
+
+	core_link = sl_core_link_get(core_llr->core_lgrp->core_ldev->num,
+				     core_llr->core_lgrp->num, core_llr->num);
+	if (!core_link)
+		return;
+
+	sl_core_llr_read64(core_llr, SS2_PORT_PML_CFG_RX_PCS, &data64);
+	/* NOTE: these need to match the restart_lock settings on the link */
+	if (sl_core_link_config_is_enable_ald_set(core_link)) {
+		data64 = SS2_PORT_PML_CFG_RX_PCS_RESTART_LOCK_ON_BAD_CWS_UPDATE(data64, 0);
+		data64 = SS2_PORT_PML_CFG_RX_PCS_RESTART_LOCK_ON_BAD_AMS_UPDATE(data64, 0);
+	} else {
+		data64 = SS2_PORT_PML_CFG_RX_PCS_RESTART_LOCK_ON_BAD_CWS_UPDATE(data64, 1);
+		data64 = SS2_PORT_PML_CFG_RX_PCS_RESTART_LOCK_ON_BAD_AMS_UPDATE(data64, 1);
+	}
+	sl_core_llr_write64(core_llr, SS2_PORT_PML_CFG_RX_PCS, data64);
+
+	if (sl_core_link_config_is_enable_ald_set(core_link))
+		sl_core_hw_pcs_keep_all_lanes_active_set(core_link, 1);
+	else
+		sl_core_hw_pcs_keep_all_lanes_active_set(core_link, 0);
+
+	sl_core_llr_read64(core_llr, SS2_PORT_PML_CFG_LLR_SUBPORT(core_llr->num), &data64);
+	data64 = SS2_PORT_PML_CFG_LLR_SUBPORT_LLR_MODE_UPDATE(data64, 2); /* ON */
+	sl_core_llr_write64(core_llr, SS2_PORT_PML_CFG_LLR_SUBPORT(core_llr->num), data64);
+
+	sl_core_llr_flush64(core_llr, SS2_PORT_PML_CFG_LLR_SUBPORT(core_llr->num));
+}
+
+static void sl_core_hw_llr_off(struct sl_core_llr *core_llr)
+{
+	u32 port;
+	u64 data64;
+
+	port = core_llr->core_lgrp->num;
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "off (port = %d)", port);
+
+	sl_core_llr_read64(core_llr, SS2_PORT_PML_CFG_LLR_SUBPORT(core_llr->num), &data64);
+	data64 = SS2_PORT_PML_CFG_LLR_SUBPORT_LLR_MODE_UPDATE(data64, 0); /* OFF */
+	sl_core_llr_write64(core_llr, SS2_PORT_PML_CFG_LLR_SUBPORT(core_llr->num), data64);
+
+	sl_core_llr_flush64(core_llr, SS2_PORT_PML_CFG_LLR_SUBPORT(core_llr->num));
+}
+
+static void sl_core_hw_llr_discard(struct sl_core_llr *core_llr)
+{
+	u32 port;
+	u64 data64;
+
+	port = core_llr->core_lgrp->num;
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "discard (port = %d)", port);
+
+	sl_core_llr_read64(core_llr, SS2_PORT_PML_CFG_LLR_SUBPORT(core_llr->num), &data64);
+	data64 = SS2_PORT_PML_CFG_LLR_SUBPORT_LINK_DOWN_BEHAVIOR_UPDATE(data64,
+									SS2_PORT_PML_LINK_DN_BEHAVIOR_T_LD_DISCARD);
+	sl_core_llr_write64(core_llr, SS2_PORT_PML_CFG_LLR_SUBPORT(core_llr->num), data64);
+
+	sl_core_llr_flush64(core_llr, SS2_PORT_PML_CFG_LLR_SUBPORT(core_llr->num));
+}
+
+#define SL_CORE_PACKET_BYTES_MAX 9000
+static void sl_core_hw_llr_capacity_set(struct sl_core_llr *core_llr)
+{
+	struct sl_core_link *held_link_1 __free(sl_core_link_put) = NULL;
+	u32                port;
+	u64                bytes;
+	u64                calc_data;
+	int                x;
+	u64                total_time;
+	u64                data64;
+	struct sl_llr_data llr_data;
+
+	port = core_llr->core_lgrp->num;
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "capacity set (port = %d)", port);
+
+	llr_data.loop.min = core_llr->loop_time[0];
+	llr_data.loop.max = core_llr->loop_time[0];
+	total_time        = core_llr->loop_time[0];
+	for (x = 1; x < SL_CORE_LLR_MAX_LOOP_TIME_COUNT; ++x) {
+		llr_data.loop.min  = min(core_llr->loop_time[x], llr_data.loop.min);
+		llr_data.loop.max  = max(core_llr->loop_time[x], llr_data.loop.max);
+		total_time        += core_llr->loop_time[x];
+	}
+	llr_data.loop.average = DIV_ROUND_UP(total_time, SL_CORE_LLR_MAX_LOOP_TIME_COUNT);
+
+	if (core_llr->core_lgrp->config.options & SL_LGRP_CONFIG_OPT_FABRIC) {
+		calc_data = 0x800; /* reset value */
+	} else {
+		bytes = (llr_data.loop.average * core_llr->settings.bytes_per_ns) +
+			(SL_CORE_LLR_BYTES_PER_FRAME * SL_CORE_LLR_NUM_FRAMES) +
+			SL_CORE_PACKET_BYTES_MAX;
+
+		sl_core_log_dbg(core_llr, LOG_NAME,
+				"capacity set (average = %lldns, byte_per_ns = %d, bytes = %lld)",
+			llr_data.loop.average, core_llr->settings.bytes_per_ns, bytes);
+
+		calc_data = DIV_ROUND_UP(bytes, SL_CORE_LLR_BYTE_QUANTA);
+		if (calc_data > core_llr->settings.max_cap_data)
+			calc_data = core_llr->settings.max_cap_data;
+	}
+	sl_core_log_dbg(core_llr, LOG_NAME, "capacity set (data = %lld)", calc_data);
+
+	held_link_1 = sl_core_link_get(core_llr->core_lgrp->core_ldev->num,
+				       core_llr->core_lgrp->num, core_llr->num);
+	if (!held_link_1)
+		return;
+	if (sl_core_link_config_is_enable_pml_recovery_set(held_link_1))
+		core_llr->settings.replay_ct_max = 0xFF;
+	else
+		core_llr->settings.replay_ct_max = 0xFE;
+
+	core_llr->settings.replay_timer_max = (3 * llr_data.loop.average + 500);
+
+	if (core_llr->settings.replay_timer_max < 1000)
+		core_llr->settings.replay_timer_max = 1000;
+
+	if (core_llr->settings.replay_timer_max > 15500)
+		core_llr->settings.replay_timer_max = 15500;
+
+	sl_core_llr_read64(core_llr, SS2_PORT_PML_CFG_LLR_CAPACITY(core_llr->num), &data64);
+	data64 = SS2_PORT_PML_CFG_LLR_CAPACITY_MAX_DATA_UPDATE(data64, calc_data);
+	sl_core_llr_write64(core_llr, SS2_PORT_PML_CFG_LLR_CAPACITY(core_llr->num), data64);
+
+	sl_core_llr_flush64(core_llr, SS2_PORT_PML_CFG_LLR_CAPACITY(core_llr->num));
+
+	{
+	u64 len  = 100;
+	u64 rate = 4;
+
+	llr_data.loop.calculated  = 2 * len * rate / 100;
+	llr_data.loop.calculated += 2 * (SL_CORE_LLR_ASIC_TX_DELAY_MS + SL_CORE_LLR_ASIC_RX_DELAY_MS);
+	}
+
+	sl_core_data_llr_data_set(core_llr, llr_data);
+}
+
+static void sl_core_hw_llr_config(struct sl_core_llr *core_llr)
+{
+	u32 port;
+	u64 data64;
+
+	port = core_llr->core_lgrp->num;
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "config (port = %d)", port);
+
+	sl_core_data_llr_info_map_set(core_llr, SL_CORE_INFO_MAP_LLR_CONFIG);
+
+	sl_core_llr_read64(core_llr, SS2_PORT_PML_CFG_LLR, &data64);
+	data64 = SS2_PORT_PML_CFG_LLR_SIZE_UPDATE(data64,
+						  core_llr->settings.size);
+	data64 = SS2_PORT_PML_CFG_LLR_ACK_NACK_ERR_CHECK_UPDATE(data64, 1);
+	data64 = SS2_PORT_PML_CFG_LLR_PREAMBLE_SEQ_CHECK_UPDATE(data64, 1);
+	sl_core_llr_write64(core_llr, SS2_PORT_PML_CFG_LLR, data64);
+
+	sl_core_llr_read64(core_llr, SS2_PORT_PML_CFG_LLR_SUBPORT(core_llr->num), &data64);
+	data64 = SS2_PORT_PML_CFG_LLR_SUBPORT_FILTER_LOSSLESS_WHEN_OFF_UPDATE(data64,
+									      core_llr->settings.lossless_when_off);
+	data64 = SS2_PORT_PML_CFG_LLR_SUBPORT_LINK_DOWN_BEHAVIOR_UPDATE(data64,
+									core_llr->settings.link_down_behavior);
+	data64 = SS2_PORT_PML_CFG_LLR_SUBPORT_FILTER_CTL_FRAMES_UPDATE(data64,
+								       core_llr->settings.filter_ctl_frames);
+	data64 = SS2_PORT_PML_CFG_LLR_SUBPORT_ENABLE_LOOP_TIMING_UPDATE(data64, 0);
+	data64 = SS2_PORT_PML_CFG_LLR_SUBPORT_LLR_MODE_UPDATE(data64, 0);
+	data64 = SS2_PORT_PML_CFG_LLR_SUBPORT_MAX_STARVATION_LIMIT_UPDATE(data64, 1550);
+	sl_core_llr_write64(core_llr, SS2_PORT_PML_CFG_LLR_SUBPORT(core_llr->num), data64);
+
+	sl_core_llr_read64(core_llr, SS2_PORT_PML_CFG_LLR_CF_SMAC, &data64);
+	data64 = SS2_PORT_PML_CFG_LLR_CF_SMAC_CTL_FRAME_SMAC_UPDATE(data64,
+								    core_llr->settings.ctl_frame_smac);
+	sl_core_llr_write64(core_llr, SS2_PORT_PML_CFG_LLR_CF_SMAC, data64);
+
+	sl_core_llr_read64(core_llr, SS2_PORT_PML_CFG_LLR_CF_ETYPE, &data64);
+	data64 = SS2_PORT_PML_CFG_LLR_CF_ETYPE_CTL_FRAME_ETHERTYPE_UPDATE(data64,
+									  core_llr->settings.ctl_frame_ethertype);
+	sl_core_llr_write64(core_llr, SS2_PORT_PML_CFG_LLR_CF_ETYPE, data64);
+
+	sl_core_llr_read64(core_llr, SS2_PORT_PML_CFG_LLR_SM(core_llr->num), &data64);
+	data64 = SS2_PORT_PML_CFG_LLR_SM_RETRY_THRESHOLD_UPDATE(data64,
+								core_llr->settings.retry_threshold);
+	data64 = SS2_PORT_PML_CFG_LLR_SM_ALLOW_RE_INIT_UPDATE(data64,
+							      core_llr->settings.allow_re_init);
+	data64 = SS2_PORT_PML_CFG_LLR_SM_REPLAY_CT_MAX_UPDATE(data64,
+							      core_llr->settings.replay_ct_max);
+	data64 = SS2_PORT_PML_CFG_LLR_SM_REPLAY_TIMER_MAX_UPDATE(data64,
+								 core_llr->settings.replay_timer_max);
+	sl_core_llr_write64(core_llr, SS2_PORT_PML_CFG_LLR_SM(core_llr->num), data64);
+
+	sl_core_hw_llr_config_timeouts(core_llr);
+}
+
+//---------------------------- SETUP
+
+void sl_core_hw_llr_setup_cmd(struct sl_core_llr *core_llr,
+			      sl_core_llr_setup_callback_t callback, void *tag, u32 flags)
+{
+	int rtn;
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "setup cmd (core_llr = 0x%p)", core_llr);
+
+	init_completion(&core_llr->stop_complete);
+
+	sl_core_data_llr_info_map_clr(core_llr, SL_CORE_INFO_MAP_LLR_CONFIG);
+	sl_core_data_llr_info_map_clr(core_llr, SL_CORE_INFO_MAP_LLR_SETUP);
+	sl_core_data_llr_info_map_clr(core_llr, SL_CORE_INFO_MAP_LLR_SETUP_TIMEOUT);
+	sl_core_data_llr_info_map_clr(core_llr, SL_CORE_INFO_MAP_LLR_STARTING);
+	sl_core_data_llr_info_map_clr(core_llr, SL_CORE_INFO_MAP_LLR_RUNNING);
+	sl_core_data_llr_info_map_clr(core_llr, SL_CORE_INFO_MAP_LLR_START_TIMEOUT);
+	sl_core_data_llr_info_map_set(core_llr, SL_CORE_INFO_MAP_LLR_SETTING_UP);
+	sl_core_data_llr_info_map_clr(core_llr, SL_CORE_INFO_MAP_LLR_REPLAY_MAX);
+
+	core_llr->tag             = tag;
+	core_llr->callbacks.setup = callback;
+	core_llr->flags.setup     = flags;
+
+	sl_core_timer_llr_begin(core_llr, SL_CORE_TIMER_LLR_SETUP);
+
+	sl_core_hw_intr_llr_flgs_disable(core_llr, SL_CORE_HW_INTR_LLR_SETUP_UNEXP_LOOP_TIME);
+
+	rtn = sl_core_hw_intr_llr_flgs_disable(core_llr, SL_CORE_HW_INTR_LLR_SETUP_LOOP_TIME);
+	if (rtn != 0)
+		sl_core_log_warn_trace(core_llr, LOG_NAME,
+				       "setup cmd llr_flgs_disable failed [%d]", rtn);
+
+	sl_core_hw_llr_loop_time_stop(core_llr);
+	sl_core_hw_llr_ordered_sets_stop(core_llr);
+	sl_core_hw_llr_config(core_llr);
+
+	queue_work(core_llr->core_lgrp->core_ldev->workqueue, &(core_llr->work[SL_CORE_WORK_LLR_SETUP]));
+}
+
+void sl_core_hw_llr_setup_work(struct work_struct *work)
+{
+	int                 rtn;
+	struct sl_core_llr *core_llr;
+	enum sl_core_llr_state llr_state;
+
+	core_llr = container_of(work, struct sl_core_llr, work[SL_CORE_WORK_LLR_SETUP]);
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "setup work");
+
+	rtn = sl_core_data_llr_state_get(core_llr, &llr_state);
+	if (rtn) {
+		sl_core_log_err(core_llr, LOG_NAME,
+				"setup work llr_state_get failed [%d]", rtn);
+		return;
+	}
+
+	if (llr_state != SL_CORE_LLR_STATE_SETTING_UP) {
+		sl_core_log_err_trace(core_llr, LOG_NAME,
+				      "setup work invalid state (link_state = %u %s)",
+				      llr_state, sl_core_llr_state_str(llr_state));
+		return;
+	}
+
+	sl_core_hw_intr_llr_flgs_clr(core_llr, SL_CORE_HW_INTR_LLR_SETUP_UNEXP_LOOP_TIME);
+	sl_core_hw_intr_llr_flgs_enable(core_llr, SL_CORE_HW_INTR_LLR_SETUP_UNEXP_LOOP_TIME);
+
+	sl_core_hw_intr_llr_flgs_clr(core_llr, SL_CORE_HW_INTR_LLR_SETUP_LOOP_TIME);
+	rtn = sl_core_hw_intr_llr_flgs_enable(core_llr, SL_CORE_HW_INTR_LLR_SETUP_LOOP_TIME);
+	if (rtn != 0) {
+		sl_core_log_err_trace(core_llr, LOG_NAME,
+				      "setup work llr_flgs_enable failed [%d]", rtn);
+		sl_core_timer_llr_end(core_llr, SL_CORE_TIMER_LLR_SETUP);
+		sl_core_data_llr_state_set(core_llr, SL_CORE_LLR_STATE_SETUP_CANCELING);
+		sl_core_data_llr_info_map_clr(core_llr, SL_CORE_INFO_MAP_LLR_SETTING_UP);
+		sl_core_hw_intr_llr_flgs_disable(core_llr, SL_CORE_HW_INTR_LLR_SETUP_UNEXP_LOOP_TIME);
+		sl_core_hw_intr_llr_flgs_disable(core_llr, SL_CORE_HW_INTR_LLR_SETUP_LOOP_TIME);
+		cancel_work_sync(&(core_llr->work[SL_CORE_WORK_LLR_SETUP_UNEXP_LOOP_TIME_INTR]));
+		cancel_work_sync(&(core_llr->work[SL_CORE_WORK_LLR_SETUP_LOOP_TIME_INTR]));
+		sl_core_data_llr_state_set(core_llr, SL_CORE_LLR_STATE_CONFIGURED);
+		sl_core_data_llr_last_fail_cause_set(core_llr, SL_LLR_FAIL_CAUSE_SETUP_INTR_ENABLE);
+		sl_core_hw_llr_setup_callback(core_llr);
+		complete_all(&core_llr->stop_complete);
+		return;
+	}
+
+	sl_core_hw_llr_ordered_sets_start(core_llr);
+	sl_core_hw_llr_loop_time_start(core_llr);
+}
+
+void sl_core_hw_llr_setup_loop_time_intr_work(struct work_struct *work)
+{
+	int                 rtn;
+	u32                 port;
+	int                 x;
+	u64                 data64;
+	u64                 loop_time;
+	struct sl_core_llr *core_llr;
+	int                 tries;
+	enum sl_core_llr_state llr_state;
+
+	core_llr = container_of(work, struct sl_core_llr, work[SL_CORE_WORK_LLR_SETUP_LOOP_TIME_INTR]);
+
+	rtn = sl_core_data_llr_state_get(core_llr, &llr_state);
+	if (rtn) {
+		sl_core_log_err(core_llr, LOG_NAME,
+				"loop time intr work - llr_state_get failed [%d]", rtn);
+		return;
+	}
+
+	if (llr_state != SL_CORE_LLR_STATE_SETTING_UP) {
+		sl_core_log_err_trace(core_llr, LOG_NAME, "loop time intr work - invalid state (link_state = %u %s)",
+				      llr_state, sl_core_llr_state_str(llr_state));
+		return;
+	}
+
+	port = core_llr->core_lgrp->num;
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "loop time intr work (port = %d)", port);
+
+	x = 0;
+	tries = 0;
+	while (x < SL_CORE_LLR_MAX_LOOP_TIME_COUNT) {
+		if (sl_core_llr_setup_should_stop(core_llr)) {
+			sl_core_log_dbg(core_llr, LOG_NAME, "loop time intr work canceled");
+			return;
+		}
+
+		sl_core_llr_write64(core_llr, SS2_PORT_PML_STS_LLR_LOOP_TIME(core_llr->num), 0);
+		sl_core_llr_flush64(core_llr, SS2_PORT_PML_STS_LLR_LOOP_TIME(core_llr->num));
+		udelay(50);
+		sl_core_llr_read64(core_llr, SS2_PORT_PML_STS_LLR_LOOP_TIME(core_llr->num), &data64);
+		loop_time = SS2_PORT_PML_STS_LLR_LOOP_TIME_LOOP_TIME_GET(data64);
+
+		sl_core_log_dbg(core_llr, LOG_NAME,
+				"loop time intr work (time %2d = %lluns)", x, loop_time);
+
+		if (tries++ > 100)
+			break;
+
+		if (loop_time == 0)
+			continue;
+
+		core_llr->loop_time[x] = loop_time;
+
+		++x;
+	}
+
+	sl_core_hw_llr_capacity_set(core_llr);
+
+	sl_core_timer_llr_end(core_llr, SL_CORE_TIMER_LLR_SETUP);
+
+	spin_lock(&core_llr->data_lock);
+	llr_state = core_llr->state;
+	switch (llr_state) {
+	case SL_CORE_LLR_STATE_SETTING_UP:
+		sl_core_log_dbg(core_llr, LOG_NAME, "setup loop time - setup");
+		core_llr->state = SL_CORE_LLR_STATE_SETUP;
+		clear_bit(SL_CORE_INFO_MAP_LLR_SETTING_UP, (unsigned long *)&(core_llr->info_map));
+		set_bit(SL_CORE_INFO_MAP_LLR_SETUP, (unsigned long *)&(core_llr->info_map));
+		spin_unlock(&core_llr->data_lock);
+
+		sl_core_hw_llr_setup_callback(core_llr);
+
+		return;
+	default:
+		sl_core_log_err(core_llr, LOG_NAME, "setup loop time - invalid state (link_state = %u %s)",
+				llr_state, sl_core_llr_state_str(llr_state));
+		spin_unlock(&core_llr->data_lock);
+		return;
+	}
+}
+
+void sl_core_hw_llr_setup_unexp_loop_time_intr_work(struct work_struct *work)
+{
+	int                 rtn;
+	struct sl_core_llr *core_llr;
+	enum sl_core_llr_state llr_state;
+
+	core_llr = container_of(work, struct sl_core_llr, work[SL_CORE_WORK_LLR_SETUP_UNEXP_LOOP_TIME_INTR]);
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "unexpected loop time received");
+
+	rtn = sl_core_data_llr_state_get(core_llr, &llr_state);
+	if (rtn) {
+		sl_core_log_err(core_llr, LOG_NAME,
+				"unexpected loop time intr work - llr_state_get failed [%d]", rtn);
+		return;
+	}
+
+	if (llr_state != SL_CORE_LLR_STATE_SETTING_UP) {
+		sl_core_log_err_trace(core_llr, LOG_NAME,
+				      "unexpected loop time intr work - invalid state (link_state = %u %s)",
+				      llr_state, sl_core_llr_state_str(llr_state));
+		return;
+	}
+}
+
+void sl_core_hw_llr_setup_timeout_work(struct work_struct *work)
+{
+	int                 rtn;
+	struct sl_core_llr *core_llr;
+	enum sl_core_llr_state llr_state;
+
+	core_llr = container_of(work, struct sl_core_llr, work[SL_CORE_WORK_LLR_SETUP_TIMEOUT]);
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "setup timeout work");
+
+	spin_lock(&core_llr->data_lock);
+	llr_state = core_llr->state;
+	switch (llr_state) {
+	case SL_CORE_LLR_STATE_SETTING_UP:
+		core_llr->state = SL_CORE_LLR_STATE_SETUP_TIMEOUT;
+		spin_unlock(&core_llr->data_lock);
+		break;
+	default:
+		sl_core_log_err(core_llr, LOG_NAME, "start timeout work - invalid state (llr_state = %u %s)",
+				llr_state, sl_core_llr_state_str(llr_state));
+		spin_unlock(&core_llr->data_lock);
+		return;
+	}
+
+	sl_core_data_llr_info_map_clr(core_llr, SL_CORE_INFO_MAP_LLR_SETTING_UP);
+	sl_core_data_llr_info_map_set(core_llr, SL_CORE_INFO_MAP_LLR_SETUP_TIMEOUT);
+
+	sl_core_hw_llr_loop_time_stop(core_llr);
+	sl_core_hw_llr_ordered_sets_stop(core_llr);
+
+	sl_core_hw_intr_llr_flgs_disable(core_llr, SL_CORE_HW_INTR_LLR_SETUP_UNEXP_LOOP_TIME);
+
+	rtn = sl_core_hw_intr_llr_flgs_disable(core_llr, SL_CORE_HW_INTR_LLR_SETUP_LOOP_TIME);
+	if (rtn != 0)
+		sl_core_log_warn_trace(core_llr, LOG_NAME,
+				       "setup timeout work llr_flgs_disable failed [%d]", rtn);
+
+	sl_core_data_llr_last_fail_cause_set(core_llr, SL_LLR_FAIL_CAUSE_SETUP_TIMEOUT);
+	sl_core_hw_llr_setup_callback(core_llr);
+	sl_core_data_llr_state_set(core_llr, SL_CORE_LLR_STATE_CONFIGURED);
+
+	complete_all(&core_llr->stop_complete);
+}
+
+void sl_core_hw_llr_settingup_cancel_cmd(struct sl_core_llr *core_llr)
+{
+	int rtn;
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "settingup cancel cmd");
+
+	sl_core_timer_llr_end(core_llr, SL_CORE_TIMER_LLR_SETUP);
+
+	cancel_work_sync(&(core_llr->work[SL_CORE_WORK_LLR_SETUP]));
+	cancel_work_sync(&(core_llr->work[SL_CORE_WORK_LLR_SETUP_TIMEOUT]));
+
+	rtn = sl_core_hw_intr_llr_flgs_disable(core_llr, SL_CORE_HW_INTR_LLR_SETUP_UNEXP_LOOP_TIME);
+	if (rtn != 0)
+		sl_core_log_warn_trace(core_llr, LOG_NAME,
+				       "settingup cancel cmd llr_flgs_disable failed [%d]", rtn);
+
+	rtn = sl_core_hw_intr_llr_flgs_disable(core_llr, SL_CORE_HW_INTR_LLR_SETUP_LOOP_TIME);
+	if (rtn != 0)
+		sl_core_log_warn_trace(core_llr, LOG_NAME,
+				       "settingup cancel cmd llr_flgs_disable failed [%d]", rtn);
+
+	cancel_work_sync(&(core_llr->work[SL_CORE_WORK_LLR_SETUP_LOOP_TIME_INTR]));
+	cancel_work_sync(&(core_llr->work[SL_CORE_WORK_LLR_SETUP_UNEXP_LOOP_TIME_INTR]));
+
+	sl_core_hw_llr_loop_time_stop(core_llr);
+	sl_core_hw_llr_ordered_sets_stop(core_llr);
+
+	sl_core_data_llr_info_map_clr(core_llr, SL_CORE_INFO_MAP_LLR_SETTING_UP);
+	sl_core_data_llr_info_map_clr(core_llr, SL_CORE_INFO_MAP_LLR_SETUP);
+	sl_core_data_llr_info_map_clr(core_llr, SL_CORE_INFO_MAP_LLR_SETUP_TIMEOUT);
+
+	sl_core_data_llr_state_set(core_llr, SL_CORE_LLR_STATE_CONFIGURED);
+
+	sl_core_hw_llr_setup_callback(core_llr);
+
+	complete_all(&core_llr->stop_complete);
+}
+
+//---------------------------- START
+
+void sl_core_hw_llr_start_cmd(struct sl_core_llr *core_llr,
+			      sl_core_llr_start_callback_t callback, void *tag, u32 flags)
+{
+	int rtn;
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "start cmd");
+
+	init_completion(&core_llr->stop_complete);
+
+	sl_core_data_llr_last_fail_cause_set(core_llr, SL_LLR_FAIL_CAUSE_NONE);
+
+	sl_core_data_llr_info_map_clr(core_llr, SL_CORE_INFO_MAP_LLR_RUNNING);
+	sl_core_data_llr_info_map_clr(core_llr, SL_CORE_INFO_MAP_LLR_START_TIMEOUT);
+	sl_core_data_llr_info_map_set(core_llr, SL_CORE_INFO_MAP_LLR_STARTING);
+
+	core_llr->tag             = tag;
+	core_llr->callbacks.start = callback;
+	core_llr->flags.start     = flags;
+
+	sl_core_timer_llr_begin(core_llr, SL_CORE_TIMER_LLR_START);
+
+	rtn = sl_core_hw_intr_llr_flgs_disable(core_llr, SL_CORE_HW_INTR_LLR_START_INIT_COMPLETE);
+	if (rtn != 0)
+		sl_core_log_warn_trace(core_llr, LOG_NAME,
+				       "start cmd llr_flgs_disable failed [%d]", rtn);
+
+	queue_work(core_llr->core_lgrp->core_ldev->workqueue, &core_llr->work[SL_CORE_WORK_LLR_START]);
+}
+
+void sl_core_hw_llr_start_work(struct work_struct *work)
+{
+	int                 rtn;
+	struct sl_core_llr *core_llr;
+	enum sl_core_llr_state llr_state;
+
+	core_llr = container_of(work, struct sl_core_llr, work[SL_CORE_WORK_LLR_START]);
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "start work");
+
+	rtn = sl_core_data_llr_state_get(core_llr, &llr_state);
+	if (rtn) {
+		sl_core_log_err(core_llr, LOG_NAME,
+				"start work llr_state_get failed [%d]", rtn);
+		return;
+	}
+
+	if (llr_state != SL_CORE_LLR_STATE_STARTING) {
+		sl_core_log_err_trace(core_llr, LOG_NAME,
+				      "start work invalid state (link_state = %u %s)",
+				      llr_state, sl_core_llr_state_str(llr_state));
+		return;
+	}
+
+	sl_core_hw_intr_llr_flgs_clr(core_llr, SL_CORE_HW_INTR_LLR_START_INIT_COMPLETE);
+	rtn = sl_core_hw_intr_llr_flgs_enable(core_llr, SL_CORE_HW_INTR_LLR_START_INIT_COMPLETE);
+	if (rtn != 0) {
+		sl_core_log_err_trace(core_llr, LOG_NAME,
+				      "start work llr_flgs_enable failed [%d]", rtn);
+		sl_core_timer_llr_end(core_llr, SL_CORE_TIMER_LLR_START);
+		sl_core_data_llr_state_set(core_llr, SL_CORE_LLR_STATE_START_CANCELING);
+		sl_core_data_llr_info_map_clr(core_llr, SL_CORE_INFO_MAP_LLR_STARTING);
+		sl_core_hw_intr_llr_flgs_disable(core_llr, SL_CORE_HW_INTR_LLR_START_INIT_COMPLETE);
+		cancel_work_sync(&(core_llr->work[SL_CORE_WORK_LLR_START_INIT_COMPLETE_INTR]));
+		sl_core_data_llr_state_set(core_llr, SL_CORE_LLR_STATE_SETUP);
+		sl_core_data_llr_last_fail_cause_set(core_llr, SL_LLR_FAIL_CAUSE_START_INTR_ENABLE);
+		sl_core_hw_llr_start_callback(core_llr);
+		complete_all(&core_llr->stop_complete);
+		return;
+	}
+
+	sl_core_hw_llr_on(core_llr);
+}
+
+void sl_core_hw_llr_start_init_complete_intr_work(struct work_struct *work)
+{
+	int                 rtn;
+	u32                 port;
+	enum sl_core_llr_state llr_state;
+	u64                 data64;
+	struct sl_core_llr *core_llr;
+
+	core_llr = container_of(work, struct sl_core_llr, work[SL_CORE_WORK_LLR_START_INIT_COMPLETE_INTR]);
+
+	rtn = sl_core_data_llr_state_get(core_llr, &llr_state);
+	if (rtn) {
+		sl_core_log_err(core_llr, LOG_NAME,
+				"start init complete intr work - llr_state_get failed [%d]", rtn);
+		return;
+	}
+
+	if (llr_state != SL_CORE_LLR_STATE_STARTING) {
+		sl_core_log_err_trace(core_llr, LOG_NAME,
+				      "start init complete intr work - invalid state (link_state = %u %s)",
+				      llr_state, sl_core_llr_state_str(llr_state));
+		return;
+	}
+
+	port = core_llr->core_lgrp->num;
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "start init complete intr work (port = %d)", port);
+
+	if (sl_core_llr_start_should_stop(core_llr)) {
+		sl_core_log_dbg(core_llr, LOG_NAME, "start init complete intr work canceled");
+		return;
+	}
+
+	sl_core_timer_llr_end(core_llr, SL_CORE_TIMER_LLR_START);
+
+	sl_core_hw_llr_loop_time_stop(core_llr);
+
+	sl_core_llr_read64(core_llr, SS2_PORT_PML_CFG_LLR_SM(core_llr->num), &data64);
+	data64 = SS2_PORT_PML_CFG_LLR_SM_REPLAY_CT_MAX_UPDATE(data64,
+							      core_llr->settings.replay_ct_max);
+	data64 = SS2_PORT_PML_CFG_LLR_SM_REPLAY_TIMER_MAX_UPDATE(data64,
+								 core_llr->settings.replay_timer_max);
+	sl_core_llr_write64(core_llr, SS2_PORT_PML_CFG_LLR_SM(core_llr->num), data64);
+	sl_core_llr_flush64(core_llr, SS2_PORT_PML_CFG_LLR_SM(core_llr->num));
+
+	spin_lock(&core_llr->data_lock);
+	llr_state = core_llr->state;
+	switch (llr_state) {
+	case SL_CORE_LLR_STATE_STARTING:
+		sl_core_log_dbg(core_llr, LOG_NAME, "start init complete - running");
+		core_llr->state = SL_CORE_LLR_STATE_RUNNING;
+		set_bit(SL_CORE_INFO_MAP_LLR_RUNNING, (unsigned long *)&(core_llr->info_map));
+		clear_bit(SL_CORE_INFO_MAP_LLR_STARTING, (unsigned long *)&(core_llr->info_map));
+		spin_unlock(&core_llr->data_lock);
+
+		sl_core_hw_llr_start_callback(core_llr);
+		return;
+	default:
+		sl_core_log_err(core_llr, LOG_NAME, "start init complete - invalid state (link_state = %u %s)",
+				llr_state, sl_core_llr_state_str(llr_state));
+		spin_unlock(&core_llr->data_lock);
+		return;
+	}
+}
+
+void sl_core_hw_llr_start_timeout_work(struct work_struct *work)
+{
+	int                 rtn;
+	struct sl_core_llr *core_llr;
+	enum sl_core_llr_state llr_state;
+
+	core_llr = container_of(work, struct sl_core_llr, work[SL_CORE_WORK_LLR_START_TIMEOUT]);
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "start timeout work");
+
+	spin_lock(&core_llr->data_lock);
+	llr_state = core_llr->state;
+	switch (llr_state) {
+	case SL_CORE_LLR_STATE_STARTING:
+		core_llr->state = SL_CORE_LLR_STATE_START_TIMEOUT;
+		spin_unlock(&core_llr->data_lock);
+		break;
+	default:
+		sl_core_log_err(core_llr, LOG_NAME, "start timeout work - invalid state (llr_state = %u %s)",
+				llr_state, sl_core_llr_state_str(llr_state));
+		spin_unlock(&core_llr->data_lock);
+		return;
+	}
+
+	cancel_work_sync(&(core_llr->work[SL_CORE_WORK_LLR_START]));
+
+	rtn = sl_core_hw_intr_llr_flgs_disable(core_llr, SL_CORE_HW_INTR_LLR_START_INIT_COMPLETE);
+	if (rtn != 0)
+		sl_core_log_warn_trace(core_llr, LOG_NAME,
+				       "start timeout work llr_flgs_disable failed [%d]", rtn);
+
+	cancel_work_sync(&(core_llr->work[SL_CORE_WORK_LLR_START_INIT_COMPLETE_INTR]));
+
+	sl_core_hw_llr_loop_time_stop(core_llr);
+	sl_core_hw_llr_ordered_sets_stop(core_llr);
+	sl_core_hw_llr_off(core_llr);
+	sl_core_hw_llr_discard(core_llr);
+
+	sl_core_data_llr_info_map_clr(core_llr, SL_CORE_INFO_MAP_LLR_STARTING);
+	sl_core_data_llr_info_map_clr(core_llr, SL_CORE_INFO_MAP_LLR_RUNNING);
+
+	sl_core_data_llr_last_fail_cause_set(core_llr, SL_LLR_FAIL_CAUSE_START_TIMEOUT);
+	sl_core_hw_llr_start_callback(core_llr);
+	sl_core_data_llr_state_set(core_llr, SL_CORE_LLR_STATE_SETUP);
+
+	complete_all(&core_llr->stop_complete);
+}
+
+void sl_core_hw_llr_starting_cancel_cmd(struct sl_core_llr *core_llr)
+{
+	int rtn;
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "starting cancel cmd");
+
+	sl_core_timer_llr_end(core_llr, SL_CORE_TIMER_LLR_START);
+
+	cancel_work_sync(&(core_llr->work[SL_CORE_WORK_LLR_START]));
+	cancel_work_sync(&(core_llr->work[SL_CORE_WORK_LLR_START_TIMEOUT]));
+
+	rtn = sl_core_hw_intr_llr_flgs_disable(core_llr, SL_CORE_HW_INTR_LLR_START_INIT_COMPLETE);
+	if (rtn != 0)
+		sl_core_log_warn_trace(core_llr, LOG_NAME,
+				       "starting cancel cmd llr_flgs_disable failed [%d]", rtn);
+
+	cancel_work_sync(&(core_llr->work[SL_CORE_WORK_LLR_START_INIT_COMPLETE_INTR]));
+
+	sl_core_hw_llr_loop_time_stop(core_llr);
+	sl_core_hw_llr_ordered_sets_stop(core_llr);
+	sl_core_hw_llr_off(core_llr);
+	sl_core_hw_llr_discard(core_llr);
+
+	sl_core_data_llr_info_map_clr(core_llr, SL_CORE_INFO_MAP_LLR_STARTING);
+	sl_core_data_llr_info_map_clr(core_llr, SL_CORE_INFO_MAP_LLR_RUNNING);
+	sl_core_data_llr_info_map_clr(core_llr, SL_CORE_INFO_MAP_LLR_START_TIMEOUT);
+
+	sl_core_data_llr_state_set(core_llr, SL_CORE_LLR_STATE_SETUP);
+
+	sl_core_hw_llr_start_callback(core_llr);
+
+	complete_all(&core_llr->stop_complete);
+}
+
+//---------------------------- STOP
+
+void sl_core_hw_llr_stop(struct sl_core_llr *core_llr)
+{
+	sl_core_log_dbg(core_llr, LOG_NAME, "stop");
+
+	sl_core_hw_llr_loop_time_stop(core_llr);
+	sl_core_hw_llr_ordered_sets_stop(core_llr);
+	sl_core_hw_llr_off(core_llr);
+	sl_core_hw_llr_discard(core_llr);
+}
+
+void sl_core_hw_llr_setup_stop_cmd(struct sl_core_llr *core_llr)
+{
+	sl_core_log_dbg(core_llr, LOG_NAME, "setup stop cmd");
+
+	sl_core_hw_llr_loop_time_stop(core_llr);
+	sl_core_hw_llr_ordered_sets_stop(core_llr);
+
+	sl_core_data_llr_data_clr(core_llr);
+
+	sl_core_data_llr_info_map_clr(core_llr, SL_CORE_INFO_MAP_LLR_SETTING_UP);
+	sl_core_data_llr_info_map_clr(core_llr, SL_CORE_INFO_MAP_LLR_SETUP);
+	sl_core_data_llr_info_map_clr(core_llr, SL_CORE_INFO_MAP_LLR_SETUP_TIMEOUT);
+	sl_core_data_llr_info_map_clr(core_llr, SL_CORE_INFO_MAP_LLR_STARTING);
+	sl_core_data_llr_info_map_clr(core_llr, SL_CORE_INFO_MAP_LLR_RUNNING);
+	sl_core_data_llr_info_map_clr(core_llr, SL_CORE_INFO_MAP_LLR_START_TIMEOUT);
+	sl_core_data_llr_info_map_clr(core_llr, SL_CORE_INFO_MAP_LLR_REPLAY_MAX);
+
+	sl_core_data_llr_state_set(core_llr, SL_CORE_LLR_STATE_CONFIGURED);
+
+	complete_all(&core_llr->stop_complete);
+}
+
+void sl_core_hw_llr_running_stop_cmd(struct sl_core_llr *core_llr)
+{
+	sl_core_log_dbg(core_llr, LOG_NAME, "running stop cmd");
+
+	sl_core_hw_llr_off(core_llr);
+	sl_core_hw_llr_discard(core_llr);
+
+	sl_core_data_llr_info_map_clr(core_llr, SL_CORE_INFO_MAP_LLR_STARTING);
+	sl_core_data_llr_info_map_clr(core_llr, SL_CORE_INFO_MAP_LLR_RUNNING);
+	sl_core_data_llr_info_map_clr(core_llr, SL_CORE_INFO_MAP_LLR_START_TIMEOUT);
+	sl_core_data_llr_info_map_clr(core_llr, SL_CORE_INFO_MAP_LLR_REPLAY_MAX);
+
+	sl_core_data_llr_state_set(core_llr, SL_CORE_LLR_STATE_SETUP);
+
+	complete_all(&core_llr->stop_complete);
+}
+
+int sl_core_hw_llr_stop_wait(struct sl_core_llr *core_llr)
+{
+	unsigned long timeleft;
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "stop wait");
+
+	timeleft = wait_for_completion_timeout(&core_llr->stop_complete,
+					       msecs_to_jiffies(SL_CORE_LLR_STOP_TIMEOUT));
+	if (timeleft == 0) {
+		sl_core_log_err(core_llr, LOG_NAME,
+				"completion_timeout (stop_complete = 0x%p, timeleft = %lu)",
+			&core_llr->stop_complete, timeleft);
+		return -ETIMEDOUT;
+	}
+
+	return 0;
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_mac.c b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_mac.c
new file mode 100644
index 000000000000..4605c00a1723
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_mac.c
@@ -0,0 +1,172 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2022,2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+
+#include "base/sl_core_log.h"
+#include "sl_core_mac.h"
+#include "sl_core_str.h"
+#include "data/sl_core_data_mac.h"
+#include "hw/sl_core_hw_io.h"
+#include "hw/sl_core_hw_mac.h"
+
+#define LOG_NAME SL_CORE_HW_MAC_LOG_NAME
+
+void sl_core_hw_mac_tx_config(struct sl_core_mac *core_mac)
+{
+	u64 data64;
+	u32 port;
+
+	port = core_mac->core_lgrp->num;
+
+	sl_core_log_dbg(core_mac, LOG_NAME, "tx - config (port = %d)", port);
+
+	sl_core_data_mac_info_map_set(core_mac, SL_CORE_INFO_MAP_MAC_TX_CONFIG);
+
+	/* need to set mac_if_credits for llr before mac is turned on */
+	sl_core_mac_read64(core_mac, SS2_PORT_PML_CFG_LLR_SUBPORT(core_mac->num), &data64);
+	data64 = SS2_PORT_PML_CFG_LLR_SUBPORT_MAC_IF_CREDITS_UPDATE(data64,
+								    core_mac->settings.llr_if_credits);
+	sl_core_mac_write64(core_mac, SS2_PORT_PML_CFG_LLR_SUBPORT(core_mac->num), data64);
+
+	sl_core_mac_read64(core_mac, SS2_PORT_PML_CFG_TX_MAC, &data64);
+	data64 = SS2_PORT_PML_CFG_TX_MAC_IEEE_IFG_ADJUSTMENT_UPDATE(data64,
+								    core_mac->settings.tx_ifg_adj);
+	data64 = SS2_PORT_PML_CFG_TX_MAC_IFG_MODE_UPDATE(data64,
+							 core_mac->settings.tx_ifg_mode);
+	data64 = SS2_PORT_PML_CFG_TX_MAC_MAC_PAD_IDLE_THRESH_UPDATE(data64,
+								    core_mac->settings.tx_pad_idle_thresh);
+	sl_core_mac_write64(core_mac, SS2_PORT_PML_CFG_TX_MAC, data64);
+
+	sl_core_mac_flush64(core_mac, SS2_PORT_PML_CFG_TX_MAC);
+
+	sl_core_hw_mac_tx_config_subport(core_mac);
+}
+
+void sl_core_hw_mac_tx_start(struct sl_core_mac *core_mac)
+{
+	u64 data64;
+	u32 port;
+
+	port = core_mac->core_lgrp->num;
+
+	sl_core_log_dbg(core_mac, LOG_NAME, "tx - start (port = %d)", port);
+
+	sl_core_mac_read64(core_mac, SS2_PORT_PML_CFG_TX_MAC_SUBPORT(core_mac->num), &data64);
+	data64 = SS2_PORT_PML_CFG_TX_MAC_SUBPORT_MAC_OPERATIONAL_UPDATE(data64, 1);
+	sl_core_mac_write64(core_mac, SS2_PORT_PML_CFG_TX_MAC_SUBPORT(core_mac->num), data64);
+
+	sl_core_mac_flush64(core_mac, SS2_PORT_PML_CFG_TX_MAC_SUBPORT(core_mac->num));
+
+	sl_core_data_mac_info_map_set(core_mac, SL_CORE_INFO_MAP_MAC_TX);
+}
+
+void sl_core_hw_mac_tx_stop(struct sl_core_mac *core_mac)
+{
+	u64 data64;
+	u32 port;
+
+	port = core_mac->core_lgrp->num;
+
+	sl_core_log_dbg(core_mac, LOG_NAME, "tx - stop (port = %d)", port);
+
+	sl_core_mac_read64(core_mac, SS2_PORT_PML_CFG_TX_MAC_SUBPORT(core_mac->num), &data64);
+	data64 = SS2_PORT_PML_CFG_TX_MAC_SUBPORT_MAC_OPERATIONAL_UPDATE(data64, 0);
+	sl_core_mac_write64(core_mac, SS2_PORT_PML_CFG_TX_MAC_SUBPORT(core_mac->num), data64);
+
+	sl_core_mac_flush64(core_mac, SS2_PORT_PML_CFG_TX_MAC_SUBPORT(core_mac->num));
+
+	sl_core_data_mac_info_map_clr(core_mac, SL_CORE_INFO_MAP_MAC_TX);
+}
+
+u64 sl_core_hw_mac_tx_state_get(struct sl_core_mac *core_mac)
+{
+	u64 data64;
+	u32 port;
+
+	port = core_mac->core_lgrp->num;
+
+	sl_core_mac_read64(core_mac, SS2_PORT_PML_CFG_TX_MAC_SUBPORT(core_mac->num), &data64);
+
+	sl_core_log_dbg(core_mac, LOG_NAME, "tx state get (port = %d, state = %llu %s)",
+			port, SS2_PORT_PML_CFG_TX_MAC_SUBPORT_MAC_OPERATIONAL_GET(data64),
+		sl_core_mac_state_str(SS2_PORT_PML_CFG_TX_MAC_SUBPORT_MAC_OPERATIONAL_GET(data64)));
+
+	return SS2_PORT_PML_CFG_TX_MAC_SUBPORT_MAC_OPERATIONAL_GET(data64);
+}
+
+void sl_core_hw_mac_rx_config(struct sl_core_mac *core_mac)
+{
+	u64 data64;
+	u32 port;
+
+	port = core_mac->core_lgrp->num;
+
+	sl_core_log_dbg(core_mac, LOG_NAME, "rx - config (port = %d)", port);
+
+	sl_core_data_mac_info_map_set(core_mac, SL_CORE_INFO_MAP_MAC_RX_CONFIG);
+
+	sl_core_mac_read64(core_mac, SS2_PORT_PML_CFG_RX_MAC, &data64);
+	data64 = SS2_PORT_PML_CFG_RX_MAC_FLIT_PACKING_CNT_UPDATE(data64,
+								 core_mac->settings.rx_flit_packing_cnt);
+	sl_core_mac_write64(core_mac, SS2_PORT_PML_CFG_RX_MAC, data64);
+
+	sl_core_mac_read64(core_mac, SS2_PORT_PML_CFG_RX_MAC_SUBPORT(core_mac->num), &data64);
+	data64 = SS2_PORT_PML_CFG_RX_MAC_SUBPORT_SHORT_PREAMBLE_UPDATE(data64,
+								       core_mac->settings.rx_short_preamble);
+	sl_core_mac_write64(core_mac, SS2_PORT_PML_CFG_RX_MAC_SUBPORT(core_mac->num), data64);
+
+	sl_core_mac_flush64(core_mac, SS2_PORT_PML_CFG_RX_MAC_SUBPORT(core_mac->num));
+}
+
+void sl_core_hw_mac_rx_start(struct sl_core_mac *core_mac)
+{
+	u64 data64;
+	u32 port;
+
+	port = core_mac->core_lgrp->num;
+
+	sl_core_log_dbg(core_mac, LOG_NAME, "rx - start (port = %d)", port);
+
+	sl_core_mac_read64(core_mac, SS2_PORT_PML_CFG_RX_MAC_SUBPORT(core_mac->num), &data64);
+	data64 = SS2_PORT_PML_CFG_RX_MAC_SUBPORT_MAC_OPERATIONAL_UPDATE(data64, 1);
+	sl_core_mac_write64(core_mac, SS2_PORT_PML_CFG_RX_MAC_SUBPORT(core_mac->num), data64);
+
+	sl_core_mac_flush64(core_mac, SS2_PORT_PML_CFG_RX_MAC_SUBPORT(core_mac->num));
+
+	sl_core_data_mac_info_map_set(core_mac, SL_CORE_INFO_MAP_MAC_RX);
+}
+
+void sl_core_hw_mac_rx_stop(struct sl_core_mac *core_mac)
+{
+	u64 data64;
+	u32 port;
+
+	port = core_mac->core_lgrp->num;
+
+	sl_core_log_dbg(core_mac, LOG_NAME, "rx - stop (port = %d)", port);
+
+	sl_core_mac_read64(core_mac, SS2_PORT_PML_CFG_RX_MAC_SUBPORT(core_mac->num), &data64);
+	data64 = SS2_PORT_PML_CFG_RX_MAC_SUBPORT_MAC_OPERATIONAL_UPDATE(data64, 0);
+	sl_core_mac_write64(core_mac, SS2_PORT_PML_CFG_RX_MAC_SUBPORT(core_mac->num), data64);
+
+	sl_core_mac_flush64(core_mac, SS2_PORT_PML_CFG_RX_MAC_SUBPORT(core_mac->num));
+
+	sl_core_data_mac_info_map_clr(core_mac, SL_CORE_INFO_MAP_MAC_RX);
+}
+
+u64 sl_core_hw_mac_rx_state_get(struct sl_core_mac *core_mac)
+{
+	u64 data64;
+	u32 port;
+
+	port = core_mac->core_lgrp->num;
+
+	sl_core_mac_read64(core_mac, SS2_PORT_PML_CFG_RX_MAC_SUBPORT(core_mac->num), &data64);
+
+	sl_core_log_dbg(core_mac, LOG_NAME, "rx state get (port = %d, state = %llu %s)",
+			port, SS2_PORT_PML_CFG_RX_MAC_SUBPORT_MAC_OPERATIONAL_GET(data64),
+		sl_core_mac_state_str(SS2_PORT_PML_CFG_RX_MAC_SUBPORT_MAC_OPERATIONAL_GET(data64)));
+
+	return SS2_PORT_PML_CFG_RX_MAC_SUBPORT_MAC_OPERATIONAL_GET(data64);
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_pcs.c b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_pcs.c
new file mode 100644
index 000000000000..a0dc85bcaf9c
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_pcs.c
@@ -0,0 +1,365 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2022-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/delay.h>
+
+#include "sl_core_link.h"
+#include "base/sl_core_log.h"
+#include "hw/sl_core_hw_intr.h"
+#include "data/sl_core_data_link.h"
+#include "hw/sl_core_hw_io.h"
+#include "hw/sl_core_hw_pcs.h"
+
+#define LOG_NAME SL_CORE_HW_PCS_LOG_NAME
+
+void sl_core_hw_pcs_config(struct sl_core_link *core_link)
+{
+	u64 data64;
+	u64 lanes;
+	u32 port;
+
+	port = core_link->core_lgrp->num;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "config (port = %u)", port);
+
+	sl_core_read64(core_link, SS2_PORT_PML_CFG_PCS, &data64);
+	data64 = SS2_PORT_PML_CFG_PCS_TIMESTAMP_SHIFT_UPDATE(data64, 0);
+
+	if (sl_core_link_config_is_enable_ald_set(core_link))
+		data64 = SS2_PORT_PML_CFG_PCS_ENABLE_AUTO_LANE_DEGRADE_UPDATE(data64, 1);
+	else
+		data64 = SS2_PORT_PML_CFG_PCS_ENABLE_AUTO_LANE_DEGRADE_UPDATE(data64, 0);
+
+	data64 = SS2_PORT_PML_CFG_PCS_PCS_MODE_UPDATE(data64,
+						      core_link->pcs.settings.pcs_mode);
+	sl_core_write64(core_link, SS2_PORT_PML_CFG_PCS, data64);
+
+	sl_core_read64(core_link, SS2_PORT_PML_CFG_GENERAL, &data64);
+	data64 = SS2_PORT_PML_CFG_GENERAL_CLOCK_PERIOD_PS_UPDATE(data64,
+								 core_link->pcs.settings.clock_period);
+	sl_core_write64(core_link, SS2_PORT_PML_CFG_GENERAL, data64);
+
+	sl_core_read64(core_link, SS2_PORT_PML_CFG_RX_PCS_SUBPORT(core_link->num), &data64);
+	data64 = SS2_PORT_PML_CFG_RX_PCS_SUBPORT_RS_MODE_UPDATE(data64,
+								core_link->pcs.settings.rs_mode);
+	data64 = SS2_PORT_PML_CFG_RX_PCS_SUBPORT_ENABLE_LOCK_UPDATE(data64, 0);
+	data64 = SS2_PORT_PML_CFG_RX_PCS_SUBPORT_ENABLE_CTL_OS_UPDATE(data64, 0);
+	data64 = SS2_PORT_PML_CFG_RX_PCS_SUBPORT_ENABLE_RX_SM_UPDATE(data64, 1);
+	sl_core_write64(core_link, SS2_PORT_PML_CFG_RX_PCS_SUBPORT(core_link->num), data64);
+
+	sl_core_read64(core_link, SS2_PORT_PML_CFG_TX_PCS_SUBPORT(core_link->num), &data64);
+	data64 = SS2_PORT_PML_CFG_TX_PCS_SUBPORT_GEARBOX_CREDITS_UPDATE(data64,
+									core_link->pcs.settings.tx_gearbox_credits);
+	data64 = SS2_PORT_PML_CFG_TX_PCS_SUBPORT_ENABLE_CTL_OS_UPDATE(data64, 0);
+	sl_core_write64(core_link, SS2_PORT_PML_CFG_TX_PCS_SUBPORT(core_link->num), data64);
+
+	sl_core_read64(core_link, SS2_PORT_PML_CFG_TX_PCS, &data64);
+	data64 = SS2_PORT_PML_CFG_TX_PCS_CDC_READY_LEVEL_UPDATE(data64,
+								core_link->pcs.settings.tx_cdc_ready_level);
+	data64 = SS2_PORT_PML_CFG_TX_PCS_EN_PK_BW_LIMITER_UPDATE(data64,
+								 core_link->pcs.settings.tx_en_pk_bw_limiter);
+	data64 = SS2_PORT_PML_CFG_TX_PCS_EN_PK_BW_LIMITER_UPDATE(data64,
+								 core_link->pcs.settings.tx_en_pk_bw_limiter);
+	data64 = SS2_PORT_PML_CFG_TX_PCS_CDC_READY_LEVEL_UPDATE(data64,
+								core_link->pcs.settings.tx_cdc_ready_level);
+	sl_core_write64(core_link, SS2_PORT_PML_CFG_TX_PCS, data64);
+
+	if (sl_core_link_config_is_enable_ald_set(core_link))
+		sl_core_hw_pcs_keep_all_lanes_active_set(core_link, 1);
+	else
+		sl_core_hw_pcs_keep_all_lanes_active_set(core_link, 0);
+
+	sl_core_read64(core_link, SS2_PORT_PML_CFG_RX_PCS, &data64);
+	data64 = SS2_PORT_PML_CFG_RX_PCS_CW_GAP_544_UPDATE(data64,
+							   core_link->pcs.settings.cw_gap);
+	if (sl_core_link_config_is_enable_ald_set(core_link)) {
+		data64 = SS2_PORT_PML_CFG_RX_PCS_RESTART_LOCK_ON_BAD_CWS_UPDATE(data64, 0);
+		data64 = SS2_PORT_PML_CFG_RX_PCS_RESTART_LOCK_ON_BAD_AMS_UPDATE(data64, 0);
+	} else {
+		data64 = SS2_PORT_PML_CFG_RX_PCS_RESTART_LOCK_ON_BAD_CWS_UPDATE(data64, 1);
+		data64 = SS2_PORT_PML_CFG_RX_PCS_RESTART_LOCK_ON_BAD_AMS_UPDATE(data64, 1);
+	}
+	lanes = SS2_PORT_PML_CFG_RX_PCS_ACTIVE_LANES_GET(data64);
+	lanes &= ~core_link->pcs.settings.rx_active_lanes;
+	data64 = SS2_PORT_PML_CFG_RX_PCS_ACTIVE_LANES_UPDATE(data64, lanes);
+	sl_core_write64(core_link, SS2_PORT_PML_CFG_RX_PCS, data64);
+
+	/* need to set mac_tx_pcs_credits before pcs is enabled */
+	sl_core_read64(core_link, SS2_PORT_PML_CFG_TX_MAC_SUBPORT(core_link->num), &data64);
+	data64 = SS2_PORT_PML_CFG_TX_MAC_SUBPORT_PCS_CREDITS_UPDATE(data64,
+								    core_link->pcs.settings.mac_tx_credits);
+	sl_core_write64(core_link, SS2_PORT_PML_CFG_TX_MAC_SUBPORT(core_link->num), data64);
+
+	sl_core_hw_pcs_config_swizzles(core_link);
+
+	sl_core_flush64(core_link, SS2_PORT_PML_CFG_RX_PCS);
+}
+
+/* Timeout for Health Markers. We'll surely receive health markers in 100 us, if any */
+#define HM_RECV_TIMEOUT_US 100
+
+/* Max number of Physical Lanes available on Tx/Rx */
+#define MAX_PLS_AVAILABLE 0xF
+
+int sl_core_hw_pcs_enable_auto_lane_degrade(struct sl_core_link *core_link)
+{
+	u64           data64;
+	u32           port;
+	unsigned long timeout;
+	int           err;
+
+	port = core_link->core_lgrp->num;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "enable ald (port = %u)", port);
+
+	err = 0;
+	sl_core_read64(core_link, SS2_PORT_PML_CFG_PCS, &data64);
+	if (SS2_PORT_PML_CFG_PCS_ENABLE_AUTO_LANE_DEGRADE_GET(data64)) {
+		timeout = jiffies + usecs_to_jiffies(HM_RECV_TIMEOUT_US);
+		do {
+			sl_core_read64(core_link, SS2_PORT_PML_STS_PCS_LANE_DEGRADE, &data64);
+			if (time_after(jiffies, timeout)) {
+				sl_core_log_err_trace(core_link, LOG_NAME, "enable ald timeout for rx pls available");
+				err = -ETIMEDOUT;
+				goto out;
+			}
+		} while (SS2_PORT_PML_STS_PCS_LANE_DEGRADE_WORD0_RX_PLS_AVAILABLE_GET(data64) != MAX_PLS_AVAILABLE);
+
+		timeout = jiffies + usecs_to_jiffies(HM_RECV_TIMEOUT_US);
+		do {
+			sl_core_read64(core_link, SS2_PORT_PML_STS_PCS_LANE_DEGRADE, &data64);
+			if (time_after(jiffies, timeout)) {
+				sl_core_log_err_trace(core_link, LOG_NAME, "enable ald timeout for lp pls available");
+				err = -ETIMEDOUT;
+				goto out;
+			}
+		} while (SS2_PORT_PML_STS_PCS_LANE_DEGRADE_WORD0_LP_PLS_AVAILABLE_GET(data64) != MAX_PLS_AVAILABLE);
+
+		/*
+		 * enable RX degrade before TX degrade
+		 */
+		sl_core_read64(core_link, SS2_PORT_PML_CFG_RX_PCS, &data64);
+		data64 = SS2_PORT_PML_CFG_RX_PCS_ALLOW_AUTO_DEGRADE_UPDATE(data64, 1);
+		sl_core_write64(core_link, SS2_PORT_PML_CFG_RX_PCS, data64);
+
+		sl_core_read64(core_link, SS2_PORT_PML_CFG_TX_PCS, &data64);
+		data64 = SS2_PORT_PML_CFG_TX_PCS_ALLOW_AUTO_DEGRADE_UPDATE(data64, 1);
+		sl_core_write64(core_link, SS2_PORT_PML_CFG_TX_PCS, data64);
+
+		sl_core_flush64(core_link, SS2_PORT_PML_CFG_TX_PCS);
+
+		sl_core_log_dbg(core_link, LOG_NAME, "enable ald success");
+	}
+out:
+	if (err) {
+		sl_core_log_err_trace(core_link, LOG_NAME, "enable ald failed");
+
+		sl_core_read64(core_link, SS2_PORT_PML_CFG_PCS, &data64);
+		data64 = SS2_PORT_PML_CFG_PCS_ENABLE_AUTO_LANE_DEGRADE_UPDATE(data64, 0);
+		sl_core_write64(core_link, SS2_PORT_PML_CFG_PCS, data64);
+
+		sl_core_read64(core_link, SS2_PORT_PML_CFG_RX_PCS, &data64);
+		data64 = SS2_PORT_PML_CFG_RX_PCS_RESTART_LOCK_ON_BAD_CWS_UPDATE(data64, 1);
+		data64 = SS2_PORT_PML_CFG_RX_PCS_RESTART_LOCK_ON_BAD_AMS_UPDATE(data64, 1);
+		sl_core_write64(core_link, SS2_PORT_PML_CFG_RX_PCS, data64);
+
+		sl_core_flush64(core_link, SS2_PORT_PML_CFG_RX_PCS);
+
+		sl_core_hw_pcs_keep_all_lanes_active_set(core_link, 0);
+	}
+
+	return err;
+}
+
+void sl_core_hw_pcs_config_swizzles(struct sl_core_link *core_link)
+{
+	u64 data64;
+	u32 port;
+	u8  lane_num;
+
+	port = core_link->core_lgrp->num;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "config swizzles (port = %u)", port);
+
+	sl_core_read64(core_link, SS2_PORT_PML_CFG_RX_PCS, &data64);
+	for (lane_num = 0; lane_num < SL_MAX_LANES; ++lane_num) {
+		switch (core_link->core_lgrp->serdes.dt.lane_info[lane_num].rx_source) {
+		case 3:
+			data64 = SS2_PORT_PML_CFG_RX_PCS_LANE_3_SOURCE_UPDATE(data64, lane_num);
+			break;
+		case 2:
+			data64 = SS2_PORT_PML_CFG_RX_PCS_LANE_2_SOURCE_UPDATE(data64, lane_num);
+			break;
+		case 1:
+			data64 = SS2_PORT_PML_CFG_RX_PCS_LANE_1_SOURCE_UPDATE(data64, lane_num);
+			break;
+		case 0:
+			data64 = SS2_PORT_PML_CFG_RX_PCS_LANE_0_SOURCE_UPDATE(data64, lane_num);
+			break;
+		}
+	}
+	sl_core_write64(core_link, SS2_PORT_PML_CFG_RX_PCS, data64);
+
+	sl_core_read64(core_link, SS2_PORT_PML_CFG_TX_PCS, &data64);
+	data64 = SS2_PORT_PML_CFG_TX_PCS_LANE_3_SOURCE_UPDATE(data64,
+							      core_link->core_lgrp->serdes.dt.lane_info[3].tx_source);
+	data64 = SS2_PORT_PML_CFG_TX_PCS_LANE_2_SOURCE_UPDATE(data64,
+							      core_link->core_lgrp->serdes.dt.lane_info[2].tx_source);
+	data64 = SS2_PORT_PML_CFG_TX_PCS_LANE_1_SOURCE_UPDATE(data64,
+							      core_link->core_lgrp->serdes.dt.lane_info[1].tx_source);
+	data64 = SS2_PORT_PML_CFG_TX_PCS_LANE_0_SOURCE_UPDATE(data64,
+							      core_link->core_lgrp->serdes.dt.lane_info[0].tx_source);
+	sl_core_write64(core_link, SS2_PORT_PML_CFG_TX_PCS, data64);
+}
+
+void sl_core_hw_pcs_tx_start(struct sl_core_link *core_link)
+{
+	u64 data64;
+	u32 port;
+
+	port = core_link->core_lgrp->num;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "tx start (port = %u)", port);
+
+	sl_core_read64(core_link, SS2_PORT_PML_CFG_PCS_SUBPORT(core_link->num), &data64);
+	data64 = SS2_PORT_PML_CFG_PCS_SUBPORT_PCS_ENABLE_UPDATE(data64, 1);
+	sl_core_write64(core_link, SS2_PORT_PML_CFG_PCS_SUBPORT(core_link->num), data64);
+
+	sl_core_flush64(core_link, SS2_PORT_PML_CFG_RX_PCS);
+}
+
+void sl_core_hw_pcs_rx_start(struct sl_core_link *core_link)
+{
+	u64 data64;
+	u64 lanes;
+	u32 port;
+
+	port = core_link->core_lgrp->num;
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"rx start (port = %u, active_lanes = 0x%X)",
+		port, core_link->pcs.settings.rx_active_lanes);
+
+	sl_core_read64(core_link, SS2_PORT_PML_CFG_RX_PCS_SUBPORT(core_link->num), &data64);
+	data64 = SS2_PORT_PML_CFG_RX_PCS_SUBPORT_ENABLE_LOCK_UPDATE(data64, 1);
+	sl_core_write64(core_link, SS2_PORT_PML_CFG_RX_PCS_SUBPORT(core_link->num), data64);
+
+	sl_core_read64(core_link, SS2_PORT_PML_CFG_RX_PCS, &data64);
+	lanes = SS2_PORT_PML_CFG_RX_PCS_ACTIVE_LANES_GET(data64);
+	lanes |= core_link->pcs.settings.rx_active_lanes;
+	data64 = SS2_PORT_PML_CFG_RX_PCS_ACTIVE_LANES_UPDATE(data64, lanes);
+	sl_core_write64(core_link, SS2_PORT_PML_CFG_RX_PCS, data64);
+
+	sl_core_flush64(core_link, SS2_PORT_PML_CFG_RX_PCS);
+}
+
+void sl_core_hw_pcs_stop(struct sl_core_link *core_link)
+{
+	u64 data64;
+	u64 lanes;
+	u32 port;
+
+	port = core_link->core_lgrp->num;
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"stop (port = %u, active_lanes = 0x%X)",
+		port, core_link->pcs.settings.rx_active_lanes);
+
+	sl_core_read64(core_link, SS2_PORT_PML_CFG_RX_PCS, &data64);
+	lanes = SS2_PORT_PML_CFG_RX_PCS_ACTIVE_LANES_GET(data64);
+	lanes &= ~core_link->pcs.settings.rx_active_lanes;
+	data64 = SS2_PORT_PML_CFG_RX_PCS_ACTIVE_LANES_UPDATE(data64, lanes);
+	sl_core_write64(core_link, SS2_PORT_PML_CFG_RX_PCS, data64);
+
+	sl_core_flush64(core_link, SS2_PORT_PML_CFG_RX_PCS);
+
+	msleep(20);
+
+	sl_core_read64(core_link, SS2_PORT_PML_CFG_PCS_SUBPORT(core_link->num), &data64);
+	data64 = SS2_PORT_PML_CFG_PCS_SUBPORT_PCS_ENABLE_UPDATE(data64, 0);
+	sl_core_write64(core_link, SS2_PORT_PML_CFG_PCS_SUBPORT(core_link->num), data64);
+
+	sl_core_read64(core_link, SS2_PORT_PML_CFG_RX_PCS_SUBPORT(core_link->num), &data64);
+	data64 = SS2_PORT_PML_CFG_RX_PCS_SUBPORT_ENABLE_LOCK_UPDATE(data64, 0);
+	data64 = SS2_PORT_PML_CFG_RX_PCS_SUBPORT_ENABLE_RX_SM_UPDATE(data64, 0);
+	sl_core_write64(core_link, SS2_PORT_PML_CFG_RX_PCS_SUBPORT(core_link->num), data64);
+
+	sl_core_flush64(core_link, SS2_PORT_PML_CFG_PCS_SUBPORT(core_link->num));
+}
+
+void sl_core_hw_pcs_toggle(struct sl_core_link *core_link)
+{
+	u64 data64;
+	u32 port;
+
+	port = core_link->core_lgrp->num;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "toggle (port = %u)", port);
+
+	sl_core_read64(core_link, SS2_PORT_PML_CFG_RX_PCS_SUBPORT(core_link->num), &data64);
+	data64 = SS2_PORT_PML_CFG_RX_PCS_SUBPORT_ENABLE_LOCK_UPDATE(data64, 0);
+	sl_core_write64(core_link, SS2_PORT_PML_CFG_RX_PCS_SUBPORT(core_link->num), data64);
+
+	sl_core_read64(core_link, SS2_PORT_PML_CFG_RX_PCS_SUBPORT(core_link->num), &data64);
+	data64 = SS2_PORT_PML_CFG_RX_PCS_SUBPORT_ENABLE_LOCK_UPDATE(data64, 1);
+	sl_core_write64(core_link, SS2_PORT_PML_CFG_RX_PCS_SUBPORT(core_link->num), data64);
+
+	sl_core_flush64(core_link, SS2_PORT_PML_CFG_RX_PCS);
+}
+
+bool sl_core_hw_pcs_is_pml_rec_success(struct sl_core_link *core_link)
+{
+	u64  data64;
+	u32  port;
+	bool is_am_locked;
+
+	port = core_link->core_lgrp->num;
+
+	sl_core_read64(core_link, SS2_PORT_PML_STS_RX_PCS_AM_LOCK, &data64);
+	is_am_locked = (SS2_PORT_PML_STS_RX_PCS_AM_LOCK_AM_LOCK_GET(data64) == core_link->pcs.settings.rx_am_lock_lanes);
+
+	sl_core_read64(core_link, SS2_PORT_PML_STS_RX_PCS_SUBPORT(core_link->num), &data64);
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"is pml rec success (port = %u, aligned = %s, locked = %s, fault = %s, local_fault = %s)",
+			 port,
+			 (SS2_PORT_PML_STS_RX_PCS_SUBPORT_ALIGN_STATUS_GET(data64) == 1) ? "yes" : "no",
+			 is_am_locked ? "yes" : "no",
+			 (SS2_PORT_PML_STS_RX_PCS_SUBPORT_FAULT_GET(data64) == 1) ? "yes" : "no",
+			 (SS2_PORT_PML_STS_RX_PCS_SUBPORT_LOCAL_FAULT_GET(data64) == 1) ? "yes" : "no");
+
+	return ((SS2_PORT_PML_STS_RX_PCS_SUBPORT_ALIGN_STATUS_GET(data64) == 1) &&
+		(is_am_locked)                                                  &&
+		(SS2_PORT_PML_STS_RX_PCS_SUBPORT_FAULT_GET(data64) == 0)        &&
+		(SS2_PORT_PML_STS_RX_PCS_SUBPORT_LOCAL_FAULT_GET(data64) == 0));
+}
+
+bool sl_core_hw_pcs_is_ok(struct sl_core_link *core_link)
+{
+	u64  data64;
+	u32  port;
+	bool pcs_is_ok;
+
+	sl_core_data_link_info_map_set(core_link, SL_CORE_INFO_MAP_PCS_CHECK);
+
+	port = core_link->core_lgrp->num;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "is ok (port = %u)", port);
+
+	sl_core_read64(core_link, SS2_PORT_PML_STS_RX_PCS_SUBPORT(core_link->num), &data64);
+
+	pcs_is_ok = ((SS2_PORT_PML_STS_RX_PCS_SUBPORT_ALIGN_STATUS_GET(data64) != 0) &&
+		(SS2_PORT_PML_STS_RX_PCS_SUBPORT_FAULT_GET(data64) == 0)             &&
+		(SS2_PORT_PML_STS_RX_PCS_SUBPORT_LOCAL_FAULT_GET(data64) == 0)       &&
+		(SS2_PORT_PML_STS_RX_PCS_SUBPORT_HI_SER_GET(data64) == 0));
+
+	sl_core_data_link_info_map_clr(core_link, SL_CORE_INFO_MAP_PCS_CHECK);
+
+	if (pcs_is_ok)
+		sl_core_data_link_info_map_set(core_link, SL_CORE_INFO_MAP_PCS_OK);
+	else
+		sl_core_data_link_info_map_clr(core_link, SL_CORE_INFO_MAP_PCS_OK);
+
+	return pcs_is_ok;
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_pmi.c b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_pmi.c
new file mode 100644
index 000000000000..65bebcbcbed9
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_pmi.c
@@ -0,0 +1,54 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/umh.h>
+
+#include "sl_core_lgrp.h"
+#include "base/sl_core_log.h"
+#include "hw/sl_core_hw_io.h"
+#include "hw/sl_core_hw_pmi.h"
+
+#define LOG_NAME SL_CORE_HW_PMI_LOG_NAME
+
+int pmi_rd(struct sl_core_lgrp *core_lgrp, u8 dev_id, u8 lane, u8 pll, u16 addr, u16 *data)
+{
+	int rtn;
+
+	rtn = sl_core_pmi_rd(core_lgrp, PMI_ADDR32(dev_id, pll, lane, addr), data);
+	if (rtn)
+		sl_core_log_err_trace(core_lgrp, LOG_NAME, "PMI RD (addr = 0x%04X, data = 0x%04X)", addr, *data);
+
+	spin_lock(&core_lgrp->data_lock);
+	core_lgrp->pmi.rd.addr   =  addr;
+	core_lgrp->pmi.rd.data   = *data;
+	core_lgrp->pmi.rd.dev_id =  dev_id;
+	core_lgrp->pmi.rd.lane   =  lane;
+	core_lgrp->pmi.rd.pll    =  pll;
+	core_lgrp->pmi.rd.result =  rtn;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return rtn;
+}
+
+int pmi_wr(struct sl_core_lgrp *core_lgrp, u8 dev_id, u8 lane, u8 pll, u16 addr, u16 data, u16 mask)
+{
+	int rtn;
+
+	rtn = sl_core_pmi_wr(core_lgrp, PMI_ADDR32(dev_id, pll, lane, addr), data, mask);
+	if (rtn)
+		sl_core_log_err_trace(core_lgrp, LOG_NAME, "PMI WR (addr = 0x%04X, data = 0x%04X, mask = 0x%04X)",
+				      addr, data, mask);
+
+	spin_lock(&core_lgrp->data_lock);
+	core_lgrp->pmi.wr.addr   = addr;
+	core_lgrp->pmi.wr.data   = data;
+	core_lgrp->pmi.wr.mask   = mask;
+	core_lgrp->pmi.wr.dev_id = dev_id;
+	core_lgrp->pmi.wr.lane   = lane;
+	core_lgrp->pmi.wr.pll    = pll;
+	core_lgrp->pmi.wr.result = rtn;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return rtn;
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_reset.c b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_reset.c
new file mode 100644
index 000000000000..dd6b5ab4b8ef
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_reset.c
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2022,2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+
+#include "sl_asic.h"
+#include "sl_core_lgrp.h"
+#include "sl_core_link.h"
+#include "base/sl_core_log.h"
+#include "hw/sl_core_hw_intr.h"
+#include "hw/sl_core_hw_reset.h"
+
+#define LOG_NAME SL_CORE_RESET_LOG_NAME
+
+static void sl_core_hw_reset_on(struct sl_core_lgrp *core_lgrp, u8 link_num)
+{
+	u32 port;
+
+	port = core_lgrp->num;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME,
+			"on (port = %u, link_num = %u)", port, link_num);
+
+	core_lgrp->core_ldev->ops.write64(core_lgrp->core_ldev->accessors.pci,
+		SS2_PORT_PML_CFG_SUBPORT_RESET(link_num),
+		SS2_PORT_PML_CFG_SUBPORT_RESET_WARM_RST_FROM_CSR_SET(1));
+
+	(void)core_lgrp->core_ldev->ops.read64(core_lgrp->core_ldev->accessors.pci,
+		SS2_PORT_PML_CFG_SUBPORT_RESET(link_num));
+}
+
+static void sl_core_hw_reset_off(struct sl_core_lgrp *core_lgrp, u8 link_num)
+{
+	u32 port;
+
+	port = core_lgrp->num;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME,
+			"off (port = %u, link_num = %u)", port, link_num);
+
+	core_lgrp->core_ldev->ops.write64(core_lgrp->core_ldev->accessors.pci,
+		SS2_PORT_PML_CFG_SUBPORT_RESET(link_num),
+		SS2_PORT_PML_CFG_SUBPORT_RESET_WARM_RST_FROM_CSR_SET(0));
+
+	(void)core_lgrp->core_ldev->ops.read64(core_lgrp->core_ldev->accessors.pci,
+		SS2_PORT_PML_CFG_SUBPORT_RESET(link_num));
+}
+
+void sl_core_hw_reset_link(struct sl_core_link *core_link)
+{
+	sl_core_log_dbg(core_link, LOG_NAME, "link");
+
+	sl_core_hw_reset_on(core_link->core_lgrp, core_link->num);
+	sl_core_hw_reset_off(core_link->core_lgrp, core_link->num);
+}
+
+void sl_core_hw_reset_lgrp(struct sl_core_lgrp *core_lgrp)
+{
+	u8 link_num;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "lgrp");
+
+	for (link_num = 0; link_num < SL_ASIC_MAX_LINKS; ++link_num)
+		sl_core_hw_reset_on(core_lgrp, link_num);
+	for (link_num = 0; link_num < SL_ASIC_MAX_LINKS; ++link_num)
+		sl_core_hw_reset_off(core_lgrp, link_num);
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_sbus.c b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_sbus.c
new file mode 100644
index 000000000000..fc1d22f8bc51
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_sbus.c
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/umh.h>
+
+#include "sl_core_lgrp.h"
+#include "base/sl_core_log.h"
+#include "hw/sl_core_hw_io.h"
+#include "hw/sl_core_hw_sbus.h"
+
+#define LOG_NAME SL_CORE_HW_SBUS_LOG_NAME
+
+int sbus_wr(struct sl_core_lgrp *core_lgrp, u8 dev_addr, u8 reg, u32 data)
+{
+	int rtn;
+
+	rtn = sl_core_sbus_wr(core_lgrp, dev_addr, reg, data);
+	if (rtn != 0)
+		sl_core_log_err_trace(core_lgrp, LOG_NAME, "SBUS WR (dev = 0x%02X, reg = 0x%02X, data = 0x%08X)",
+				      dev_addr, reg, data);
+
+	spin_lock(&core_lgrp->data_lock);
+	core_lgrp->sbus.wr.dev_addr = dev_addr;
+	core_lgrp->sbus.wr.data     = data;
+	core_lgrp->sbus.wr.mask     = 0xFFFFFFFF;
+	core_lgrp->sbus.wr.reg      = reg;
+	core_lgrp->sbus.wr.lsb      = 0;
+	core_lgrp->sbus.wr.result   = rtn;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return rtn;
+}
+
+int sbus_field_wr(struct sl_core_lgrp *core_lgrp, u8 dev_addr, u8 reg, u8 lsb, u32 mask, u32 data)
+{
+	int rtn;
+	u32 data32;
+
+	rtn = sl_core_sbus_rd(core_lgrp, dev_addr, reg, &data32);
+	if (rtn != 0) {
+		sl_core_log_err_trace(core_lgrp, LOG_NAME, "SBUS field RD (dev = 0x%02X, reg = 0x%02X)", dev_addr, reg);
+		goto out;
+	}
+
+	data32 = ((data32 & (~(mask << lsb))) | (data << lsb));
+
+	rtn = sl_core_sbus_wr(core_lgrp, dev_addr, reg, data32);
+	if (rtn != 0)
+		sl_core_log_err_trace(core_lgrp, LOG_NAME,
+				      "SBUS field WR (dev = 0x%02X, reg = 0x%02X, lsb = %u, data = 0x%08X)",
+				      dev_addr, reg, lsb, data32);
+
+out:
+	spin_lock(&core_lgrp->data_lock);
+	core_lgrp->sbus.wr.dev_addr = dev_addr;
+	core_lgrp->sbus.wr.data     = data;
+	core_lgrp->sbus.wr.mask     = mask;
+	core_lgrp->sbus.wr.reg      = reg;
+	core_lgrp->sbus.wr.lsb      = lsb;
+	core_lgrp->sbus.wr.result   = rtn;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return rtn;
+}
+
+int sbus_rd(struct sl_core_lgrp *core_lgrp, u8 dev_addr, u8 reg, u32 *data)
+{
+	int rtn;
+
+	rtn = sl_core_sbus_rd(core_lgrp, dev_addr, reg, data);
+	if (rtn != 0)
+		sl_core_log_err_trace(core_lgrp, LOG_NAME, "SBUS RD (dev = 0x%02X, reg = 0x%02X)", dev_addr, reg);
+
+	spin_lock(&core_lgrp->data_lock);
+	core_lgrp->sbus.rd.dev_addr =  dev_addr;
+	core_lgrp->sbus.rd.data     = *data;
+	core_lgrp->sbus.rd.mask     =  0xFFFFFFFF;
+	core_lgrp->sbus.rd.reg      =  reg;
+	core_lgrp->sbus.rd.lsb      =  0;
+	core_lgrp->sbus.rd.result   =  rtn;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return rtn;
+}
+
+int sbus_field_rd(struct sl_core_lgrp *core_lgrp, u8 dev_addr, u8 reg, u8 lsb, u32 mask, u32 *data)
+{
+	int rtn;
+	u32 data32;
+
+	rtn = sl_core_sbus_rd(core_lgrp, dev_addr, reg, &data32);
+	if (rtn != 0)
+		sl_core_log_err_trace(core_lgrp, LOG_NAME, "SBUS field RD (dev = 0x%02X, reg = 0x%02X, lsb = %u)",
+				      dev_addr, reg, lsb);
+
+	*data = ((data32 >> lsb) & mask);
+
+	spin_lock(&core_lgrp->data_lock);
+	core_lgrp->sbus.rd.dev_addr =  dev_addr;
+	core_lgrp->sbus.rd.data     = *data;
+	core_lgrp->sbus.rd.mask     =  mask;
+	core_lgrp->sbus.rd.reg      =  reg;
+	core_lgrp->sbus.rd.lsb      =  lsb;
+	core_lgrp->sbus.rd.result   =  rtn;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return rtn;
+}
+
+int sbus_rst(struct sl_core_lgrp *core_lgrp, u8 dev_addr)
+{
+	int rtn;
+
+	rtn = sl_core_sbus_rst(core_lgrp, dev_addr);
+	if (rtn != 0)
+		sl_core_log_err_trace(core_lgrp, LOG_NAME, "SBUS RST (dev = 0x%02X)", dev_addr);
+
+	spin_lock(&core_lgrp->data_lock);
+	core_lgrp->sbus.rst.dev_addr = dev_addr;
+	core_lgrp->sbus.rst.result   = rtn;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return rtn;
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_sbus_pmi.c b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_sbus_pmi.c
new file mode 100644
index 000000000000..c58c95e8ea4b
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_sbus_pmi.c
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/umh.h>
+
+#include "sl_core_lgrp.h"
+#include "base/sl_core_log.h"
+#include "hw/sl_core_hw_io.h"
+#include "hw/sl_core_hw_pmi.h"
+#include "hw/sl_core_hw_sbus_pmi.h"
+
+#define LOG_NAME SL_CORE_HW_SBUS_PMI_LOG_NAME
+
+#define SL_CORE_HW_SBUS_PMI_ADDR_REG      2
+#define SL_CORE_HW_SBUS_PMI_DATA_MASK_REG 3
+#define SL_CORE_HW_SBUS_PMI_DATA_OUT_REG  4
+
+int sbus_pmi_rd(struct sl_core_lgrp *core_lgrp, u8 dev_addr, u8 dev_id, u8 lane,
+		u8 pll, u16 addr, u16 mask, u16 *data)
+{
+	int rtn;
+	u32 addr32;
+	u32 data32;
+
+	addr32 = PMI_ADDR32(dev_id, pll, lane, addr);
+
+	rtn = sl_core_sbus_wr(core_lgrp, dev_addr, SL_CORE_HW_SBUS_PMI_ADDR_REG, addr32); /* PMI_ADDR */
+	if (rtn) {
+		sl_core_log_err_trace(core_lgrp, LOG_NAME,
+				      "SBUS PMI RD (dev = 0x%02X, dev_id = 0x%02X, addr = 0x%04X, mask = 0x%04X)",
+				      dev_addr, dev_id, addr, mask);
+		goto out;
+	}
+
+	rtn = sl_core_sbus_rd(core_lgrp, dev_addr, SL_CORE_HW_SBUS_PMI_DATA_OUT_REG, &data32); /* PMI DATA OUT */
+	if (rtn) {
+		sl_core_log_err_trace(core_lgrp, LOG_NAME,
+				      "SBUS PMI RD (dev = 0x%02X, dev_id = 0x%02X, addr = 0x%04X, mask = 0x%04X)",
+				      dev_addr, dev_id, addr, mask);
+		goto out;
+	}
+
+	if (data32 & BIT(17)) { /* PMI ERROR */
+		sl_core_log_err_trace(core_lgrp, LOG_NAME,
+				      "SBUS PMI RD (dev = 0x%02X, dev_id = 0x%02X, addr = 0x%04X, mask = 0x%04X)",
+				      dev_addr, dev_id, addr, mask);
+		rtn = -EIO;
+		goto out;
+	}
+
+	*data = (u16)data32 & mask;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "SBUS PMI RD (dev = 0x%02X, addr = 0x%08X, data = 0x%08X)",
+			dev_addr, addr32, *data);
+
+out:
+	spin_lock(&core_lgrp->data_lock);
+	core_lgrp->sbus_pmi.rd.dev_addr =  dev_addr;
+	core_lgrp->sbus_pmi.rd.addr     =  addr;
+	core_lgrp->sbus_pmi.rd.data     = rtn ? 0 : *data;
+	core_lgrp->sbus_pmi.rd.mask     =  mask;
+	core_lgrp->sbus_pmi.rd.dev_id   =  dev_id;
+	core_lgrp->sbus_pmi.rd.lane     =  lane;
+	core_lgrp->sbus_pmi.rd.pll      =  pll;
+	core_lgrp->sbus_pmi.rd.result   =  rtn;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return rtn;
+}
+
+int sbus_pmi_wr(struct sl_core_lgrp *core_lgrp, u8 dev_addr, u8 dev_id, u8 lane,
+		u8 pll, u16 addr, u16 data, u16 mask)
+{
+	int rtn;
+	u32 addr32;
+	u32 data32;
+
+	addr32 = PMI_ADDR32(dev_id, pll, lane, addr);
+	data32 = (~mask & 0xFFFF) | (data << 16);
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "SBUS PMI WR (dev = 0x%02X, addr = 0x%08X, data = 0x%08X)",
+			dev_addr, addr32, data32);
+
+	rtn = sl_core_sbus_wr(core_lgrp, dev_addr, SL_CORE_HW_SBUS_PMI_ADDR_REG, addr32); /* PMI_ADDR */
+	if (rtn) {
+		sl_core_log_err_trace(core_lgrp, LOG_NAME,
+				      "SBUS PMI WR (dev = 0x%02X, dev_id = 0x%02X, addr = 0x%04X, data = 0x%04X, mask = 0x%04X)",
+				      dev_addr, dev_id, addr, data, mask);
+		goto out;
+	}
+
+	rtn = sl_core_sbus_wr(core_lgrp, dev_addr, SL_CORE_HW_SBUS_PMI_DATA_MASK_REG, data32); /* PMI MASK+DATA */
+	if (rtn != 0)
+		sl_core_log_err_trace(core_lgrp, LOG_NAME,
+				      "SBUS PMI WR (dev = 0x%02X, dev_id = 0x%02X, addr = 0x%04X, data = 0x%04X, mask = 0x%04X)",
+				      dev_addr, dev_id, addr, data, mask);
+
+out:
+	spin_lock(&core_lgrp->data_lock);
+	core_lgrp->sbus_pmi.wr.dev_addr = dev_addr;
+	core_lgrp->sbus_pmi.wr.addr     = addr;
+	core_lgrp->sbus_pmi.wr.data     = data;
+	core_lgrp->sbus_pmi.wr.mask     = mask;
+	core_lgrp->sbus_pmi.wr.dev_id   = dev_id;
+	core_lgrp->sbus_pmi.wr.lane     = lane;
+	core_lgrp->sbus_pmi.wr.pll      = pll;
+	core_lgrp->sbus_pmi.wr.result   = rtn;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return rtn;
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes.c b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes.c
new file mode 100644
index 000000000000..ca2666c393cd
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes.c
@@ -0,0 +1,212 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2022,2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/umh.h>
+
+#include "sl_asic.h"
+#include "sl_platform.h"
+#include "sl_core_link.h"
+#include "sl_core_lgrp.h"
+#include "sl_core_ldev.h"
+#include "base/sl_core_log.h"
+#include "hw/sl_core_hw_serdes.h"
+#include "hw/sl_core_hw_sbus.h"
+#include "hw/sl_core_hw_pmi.h"
+#include "hw/sl_core_hw_uc_ram.h"
+#include "hw/sl_core_hw_serdes_addrs.h"
+
+#define LOG_NAME SL_CORE_SERDES_LOG_NAME
+
+int sl_core_hw_serdes_init(struct sl_core_lgrp *core_lgrp)
+{
+	int rtn;
+	u8  lane_num;
+	u8  which;
+	u32 addr;
+	u32 data;
+
+	if (!SL_PLATFORM_IS_HARDWARE(core_lgrp->core_ldev))
+		return 0;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "init");
+
+	for (lane_num = 0; lane_num < SL_ASIC_MAX_LANES; ++lane_num) {
+		which = (lane_num + ((core_lgrp->num & BIT(0)) * 4));
+		addr  = 0x08FFD190 | which;
+		data  = 0x00000000 | (which << 24) | (which << 16);
+		sl_core_log_dbg(core_lgrp, LOG_NAME,
+				"init (which = %d, reg2 = 0x%08X, reg3 = 0x%08X)", which, addr, data);
+		SL_CORE_HW_SBUS_WR(core_lgrp, core_lgrp->serdes.dt.dev_addr, 0x2, addr);
+		SL_CORE_HW_SBUS_WR(core_lgrp, core_lgrp->serdes.dt.dev_addr, 0x3, data);
+	}
+
+	rtn = 0;
+out:
+	return rtn;
+}
+
+int sl_core_hw_serdes_swizzles(struct sl_core_lgrp *core_lgrp)
+{
+	int rtn;
+	u8  lane_num;
+	u8  which;
+	u16 data;
+
+	if (!SL_PLATFORM_IS_HARDWARE(core_lgrp->core_ldev))
+		return 0;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "swizzles");
+
+	if (is_flag_set(core_lgrp->config.options, SL_LGRP_CONFIG_OPT_SERDES_LOOPBACK_ENABLE)) {
+		sl_core_log_dbg(core_lgrp, LOG_NAME, "swizzles setting for loopback");
+		core_lgrp->serdes.dt.lane_info[0].tx_source = 0;
+		core_lgrp->serdes.dt.lane_info[1].tx_source = 1;
+		core_lgrp->serdes.dt.lane_info[2].tx_source = 2;
+		core_lgrp->serdes.dt.lane_info[3].tx_source = 3;
+		core_lgrp->serdes.dt.lane_info[0].rx_source = 0;
+		core_lgrp->serdes.dt.lane_info[1].rx_source = 1;
+		core_lgrp->serdes.dt.lane_info[2].rx_source = 2;
+		core_lgrp->serdes.dt.lane_info[3].rx_source = 3;
+	} else {
+		rtn = core_lgrp->core_ldev->ops.dt_info_get(core_lgrp->core_ldev->accessors.dt,
+			core_lgrp->core_ldev->num, core_lgrp->num, &(core_lgrp->serdes.dt));
+		if (rtn)
+			sl_core_log_warn_trace(core_lgrp, LOG_NAME, "swizzles dt_info_get failed [%d]", rtn);
+	}
+
+	for (lane_num = 0; lane_num < SL_ASIC_MAX_LANES; ++lane_num) {
+		which = (lane_num + ((core_lgrp->num & BIT(0)) * 4));
+		data  = 0x0000 |
+			((core_lgrp->serdes.dt.lane_info[lane_num].tx_source + ((core_lgrp->num & BIT(0)) * 4)) << 8) |
+			(core_lgrp->serdes.dt.lane_info[lane_num].rx_source + ((core_lgrp->num & BIT(0)) * 4));
+		sl_core_log_dbg(core_lgrp, LOG_NAME,
+				"swizzles (which = %d, addr = 0x%04X, data = 0x%04X)",
+			which, core_lgrp->core_ldev->serdes.addrs[SERDES_DIG_COM_B_LANE_ADDR_0] + which, data);
+		SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+				  core_lgrp->core_ldev->serdes.addrs[SERDES_DIG_COM_B_LANE_ADDR_0] + which, data, 0x1F1F);
+	}
+
+	rtn = 0;
+out:
+	return rtn;
+}
+
+#define FW_INFO_SIGNATURE                       0x464E49
+#define FW_INFO_NUM_MICROS_OFFSET               0x60
+#define FW_INFO_NUM_LANES_OFFSET                0xC
+#define FW_INFO_LANE_STATIC_VAR_RAM_BASE_OFFSET 0x74
+#define FW_INFO_LANE_STATIC_VAR_RAM_SIZE_OFFSET 0x78
+#define FW_INFO_LANE_VAR_RAM_BASE_OFFSET        0x74
+#define FW_INFO_LANE_VAR_RAM_SIZE_OFFSET        0x78
+#define FW_INFO_GRP_RAM_SIZE_OFFSET             0x68
+#define FW_INFO_LANE_MEM_PTR_OFFSET             0x1C
+#define FW_INFO_LANE_MEM_SIZE_OFFSET            0x08
+#define FW_INFO_SIZE                            128
+
+int sl_core_hw_serdes_hw_info_get(struct sl_core_lgrp *core_lgrp)
+{
+	int                       rtn;
+	u8                        rd_buff[FW_INFO_SIZE];
+	u16                       data16;
+	u32                       data32;
+	struct sl_serdes_hw_info *hw_info;
+
+	if (!SL_PLATFORM_IS_HARDWARE(core_lgrp->core_ldev))
+		return 0;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "hw info get");
+
+	hw_info = &(core_lgrp->core_ldev->serdes.hw_info[LGRP_TO_SERDES(core_lgrp->num)]);
+
+	SL_CORE_HW_PMI_RD(core_lgrp, core_lgrp->serdes.dt.dev_id, 0, 0,
+			  core_lgrp->core_ldev->serdes.addrs[SERDES_MICRO_B_COM_RMI_MICRO_SDK_STATUS0], &data16); /* micro status */
+	hw_info->num_cores = ((data16 >> 12) & 0x000F);
+	SL_CORE_HW_PMI_RD(core_lgrp, core_lgrp->serdes.dt.dev_id, 0, 0,
+			  core_lgrp->core_ldev->serdes.addrs[SERDES_DIG_COM_REVID1], &data16); /* multiplicity */
+	hw_info->num_lanes = ((data16 >> 12) & 0x000F);
+	SL_CORE_HW_SBUS_FIELD_RD(core_lgrp, core_lgrp->serdes.dt.dev_addr, 0xFE, 24, 0xF, &data32);
+	hw_info->num_plls = (data32 & 0xFF);
+	SL_CORE_HW_PMI_RD(core_lgrp, core_lgrp->serdes.dt.dev_id, 0, 0,
+			  core_lgrp->core_ldev->serdes.addrs[SERDES_DIG_COM_REVID0], &data16); /* hardware rev 1 */
+	hw_info->rev_id_1 = (data16 & 0x003F);
+	SL_CORE_HW_PMI_RD(core_lgrp, core_lgrp->serdes.dt.dev_id, 0, 0,
+			  core_lgrp->core_ldev->serdes.addrs[SERDES_DIG_COM_REVID2], &data16); /* hardware rev 2 */
+	hw_info->rev_id_2 = (data16 & 0x000F);
+	SL_CORE_HW_PMI_RD(core_lgrp, core_lgrp->serdes.dt.dev_id, 0, 0,
+			  core_lgrp->core_ldev->serdes.addrs[SERDES_HW_VERSION], &data16); /* hardware version */
+	hw_info->version = (data16 & 0x00FF);
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "rev_id_1   = 0x%02X", hw_info->rev_id_1);
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "rev_id_2   = 0x%02X", hw_info->rev_id_2);
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "version    = 0x%02X", hw_info->version);
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "num_cores  = %u", hw_info->num_cores);
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "num_lanes  = %u", hw_info->num_lanes);
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "num_plls   = %u", hw_info->num_plls);
+
+	SL_CORE_HW_UC_RAM_RD_BLK(core_lgrp, core_lgrp->serdes.dt.dev_addr, core_lgrp->serdes.dt.dev_id, 0x100, sizeof(rd_buff), rd_buff);
+
+	hw_info->num_micros = (*(u32 *)&rd_buff[FW_INFO_NUM_MICROS_OFFSET] & 0xF);
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "num_micros = %d", hw_info->num_micros);
+
+	rtn = 0;
+out:
+	return rtn;
+}
+
+int sl_core_hw_serdes_fw_info_get(struct sl_core_lgrp *core_lgrp)
+{
+	int                       rtn;
+	u8                        rd_buff[FW_INFO_SIZE];
+	struct sl_serdes_fw_info *fw_info;
+
+	if (!SL_PLATFORM_IS_HARDWARE(core_lgrp->core_ldev))
+		return 0;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "fw info get");
+
+	fw_info = &(core_lgrp->core_ldev->serdes.fw_info[LGRP_TO_SERDES(core_lgrp->num)]);
+
+	SL_CORE_HW_UC_RAM_RD_BLK(core_lgrp, core_lgrp->serdes.dt.dev_addr, core_lgrp->serdes.dt.dev_id, 0x100, sizeof(rd_buff), rd_buff);
+
+	fw_info->signature = (*(u32 *)rd_buff & 0xFFFFFF);
+	fw_info->version   = ((*(u32 *)rd_buff >> 24) & 0xFF);
+
+	fw_info->lane_static_var_ram_base = *(u32 *)&rd_buff[FW_INFO_LANE_STATIC_VAR_RAM_BASE_OFFSET];
+	fw_info->lane_static_var_ram_size = *(u32 *)&rd_buff[FW_INFO_LANE_STATIC_VAR_RAM_SIZE_OFFSET];
+	fw_info->lane_var_ram_base        = *(u32 *)&rd_buff[FW_INFO_LANE_MEM_PTR_OFFSET];
+	fw_info->lane_var_ram_size        = (*(u32 *)&rd_buff[FW_INFO_LANE_MEM_SIZE_OFFSET] >> 16) & 0xFFFF;
+	fw_info->grp_ram_size             = *(u32 *)&rd_buff[FW_INFO_GRP_RAM_SIZE_OFFSET] & 0xFFFF;
+	fw_info->lane_count               = *(u32 *)&rd_buff[FW_INFO_NUM_LANES_OFFSET] & 0xFF;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "signature           = 0x%08X", fw_info->signature);
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "version             = 0x%02X", fw_info->version);
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "static var ram base = 0x%08X", fw_info->lane_static_var_ram_base);
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "static var ram size = 0x%08X", fw_info->lane_static_var_ram_size);
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "var ram base        = 0x%08X", fw_info->lane_var_ram_base);
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "var ram size        = 0x%04X", fw_info->lane_var_ram_size);
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "grp ram size        = 0x%04X", fw_info->grp_ram_size);
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "lane count          = %u",     fw_info->lane_count);
+
+	rtn = 0;
+out:
+	return rtn;
+}
+
+void sl_core_hw_serdes_state_set(struct sl_core_link *core_link, u8 state)
+{
+	spin_lock(&core_link->serdes.data_lock);
+	core_link->serdes.serdes_state = state;
+	spin_unlock(&core_link->serdes.data_lock);
+}
+
+u8 sl_core_hw_serdes_state_get(struct sl_core_link *core_link)
+{
+	u8 serdes_state;
+
+	spin_lock(&core_link->serdes.data_lock);
+	serdes_state = core_link->serdes.serdes_state;
+	spin_unlock(&core_link->serdes.data_lock);
+
+	return serdes_state;
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes_core.c b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes_core.c
new file mode 100644
index 000000000000..3ded5414651f
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes_core.c
@@ -0,0 +1,439 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2023-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/delay.h>
+
+#include "sl_module.h"
+#include "sl_asic.h"
+#include "sl_platform.h"
+#include "sl_core_lgrp.h"
+#include "base/sl_core_log.h"
+#include "data/sl_core_data_lgrp.h"
+#include "hw/sl_core_hw_pmi.h"
+#include "hw/sl_core_hw_serdes_fw.h"
+#include "hw/sl_core_hw_serdes_lane.h"
+#include "hw/sl_core_hw_serdes_core.h"
+#include "hw/sl_core_hw_serdes_addrs.h"
+
+#define LOG_NAME SL_CORE_SERDES_LOG_NAME
+
+#define SL_HW_SERDES_WAIT_UC_ACTIVE_TRIES 10
+static int sl_core_hw_serdes_core_proc_reset(struct sl_core_lgrp *core_lgrp)
+{
+	int  rtn;
+	u16  data16;
+	u8   x;
+	u16 *addrs;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "proc reset");
+
+	addrs = core_lgrp->core_ldev->serdes.addrs;
+
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_MICRO_D_COM_RMI_MICRO_CONTROL0], 0x0000, 0x0001); /* set micro reset */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_MICRO_D_COM_RMI_MICRO_CONTROL0], 0x0001, 0x0001); /* clear micro reset */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_MICRO_B_COM_RMI_RAM_CR_CRCCONTROL0], 0x0000, 0x0001); /* disable CRC checking */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_MICRO_C_COM_RAM_CONTROL2], (SL_HW_SERDES_FW_STACK_SIZE << 2), 0x7FFC); /* micro_core_stack_size */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_MICRO_C_COM_RAM_CONTROL2], 0x8000, 0x8000); /* stack enable */
+
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_COMMON_CLOCK], 0x0040, 0x0040); /* select common clock */
+
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_MDIO_MMDSEL_AER_COM_MDIO_BRCST_PORT_ADDR], 0x001F, 0x001F); /* broadcast port addr */
+
+	for (x = 0; x < SL_SERDES_NUM_LANES; ++x)
+		SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, x, 0,
+				  addrs[SERDES_RXTXCOM_CKRST_CTRL_RXTXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL], 0x0000, 0x0001); /* disable lane */
+
+	usleep_range(10, 20);
+
+	for (x = 0; x < SL_SERDES_NUM_PLLS; ++x)
+		SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0, x,
+				  addrs[SERDES_CORE_PLL_COM_TOP_USER_CONTROL], 0x0000, 0x2000); /* set PLL reset */
+
+	usleep_range(10, 20);
+
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0, 0,
+			  addrs[SERDES_DIG_COM_RESET_CONTROL_PMD], 0x0000, 0x0001); /* set core reset */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0, 0,
+			  addrs[SERDES_DIG_COM_RESET_CONTROL_PMD], 0x0001, 0x0001); /* clear core reset */
+
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_CORE_PLL_COM_RESET_CONTROL_PLL_DP], 0x0002, 0x0002); /* clear pll0 reset */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 1,
+			  addrs[SERDES_CORE_PLL_COM_RESET_CONTROL_PLL_DP], 0x0002, 0x0002); /* clear pll1 reset */
+
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_MICRO_D_COM_RMI_MICRO_CONTROL0], 0x0000, 0x0001); /* set micro reset */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_MICRO_D_COM_RMI_MICRO_CONTROL0], 0x0001, 0x0001); /* clear micro reset */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_MICRO_B_COM_RMI_RAM_CR_CRCCONTROL0], 0x0000, 0x0001); /* disable CRC checking */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_MICRO_C_COM_RAM_CONTROL2], (SL_HW_SERDES_FW_STACK_SIZE << 2), 0x7FFC); /* micro_core_stack_size */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_MICRO_C_COM_RAM_CONTROL2], 0x8000, 0x8000); /* stack enable */
+
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_MICRO_D_COM_RMI_MICRO_CONTROL0], 0x0001, 0x0001); /* clear micro reset */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_MICRO_A_COM_CLOCK_CONTROL0], 0x0001, 0x0001); /* enable micro subsystem clock */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_MICRO_A_COM_RESET_CONTROL0], 0x0001, 0x0001); /* clear micro subsystem reset */
+
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_MICRO_C_COM_RAM_CONTROL0], 0x0001, 0x0001); /* enable micro access to code RAM */
+
+	for (x = 0; x < SL_SERDES_NUM_MICROS; ++x) {
+		SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, x,
+				  addrs[SERDES_MICRO_E_COM_MICRO_CORE_CLOCK_CONTROL0], 0x0001, 0x0001); /* enable micro clock */
+		SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, x,
+				  addrs[SERDES_MICRO_E_COM_MICRO_CORE_RESET_CONTROL0], 0x0001, 0x0001); /* clear micro reset */
+	}
+
+	for (x = 0; x < SL_HW_SERDES_WAIT_UC_ACTIVE_TRIES; ++x) {
+		usleep_range(1000, 2000);
+		SL_CORE_HW_PMI_RD(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+				  addrs[SERDES_DIG_COM_RESET_CONTROL_PMD], &data16); /* all micros init */
+		sl_core_log_dbg(core_lgrp, LOG_NAME, "micro init D101 = 0x%X", data16);
+		if ((data16 & 0x0002) == 0)
+			continue;
+		SL_CORE_HW_PMI_RD(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+				  addrs[SERDES_MICRO_B_COM_RMI_MICRO_SDK_STATUS0], &data16); /* micro status */
+		sl_core_log_dbg(core_lgrp, LOG_NAME, "micro status D21A = 0x%X", data16);
+		if ((data16 & 0x000F) != SL_SERDES_ACTIVE_MICROS)
+			continue;
+		break;
+	}
+	if (x >= SL_HW_SERDES_WAIT_UC_ACTIVE_TRIES) {
+		sl_core_log_err_trace(core_lgrp, LOG_NAME, "uc active failed");
+		rtn = -EIO;
+		goto out;
+	}
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "uc active");
+
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, x,
+			  addrs[SERDES_DIG_COM_TOP_USER_CONTROL_0], 0x04E2, 0xFFF); /* set heartbeat_count */
+
+	rtn = 0;
+out:
+	return rtn;
+}
+
+static int sl_core_hw_serdes_core_clock_init(struct sl_core_lgrp *core_lgrp)
+{
+	int  rtn;
+	u16 *addrs;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "clock init");
+
+	addrs = core_lgrp->core_ldev->serdes.addrs;
+
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_COM_PLL_CONTROL_2], 0x0000, 0x0060); /* pll_rtl_div_en */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_COM_PLL_CONTROL_4], 0x0000, 0x0400); /* pll_i_en_ext_cml_refclk_in */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_COM_PLL_CONTROL_4], 0x0000, 0x0200); /* pll_i_en_ext_cml_refclk_out */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_COM_PLL_CONTROL_4], 0x0000, 0x0100); /* pll_i_en_ext_cmos_refclk_in */
+
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_CORE_PLL_COM_TOP_USER_CONTROL], 0x0000, 0x2000); /* set PLL reset */
+
+	/* defaults set */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_AMS_PLL_COM_PLL_CONTROL_10], 0x003B, 0x03FF); /* integer portion */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_AMS_PLL_COM_PLL_CONTROL_11], 0x0000, 0xFFFF); /* fractional portion low 16 bits */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_AMS_PLL_COM_PLL_CONTROL_12], 0x0000, 0x0003); /* fractional portion top 2 bits */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_COM_PLL_CONTROL_1], 0x0000, 0x0080); /* pll_refclk_freq2x_en */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_COM_PLL_CONTROL_1], 0x0000, 0x0020); /* pll_refdiv2 */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_COM_PLL_CONTROL_1], 0x0000, 0x0040); /* pll_refdiv4 */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_POWER_DOWN], 0x0000, 0x0002); /* pll_div4_2_sel */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_RESET2], 0x1000, 0x3000); /* pll_pll_frac_mode */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_RESET2], 0x0800, 0x0800); /* pll_resetb_mmd */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_COM_B_PLL_CTRL_0], 0x0000, 0x0008); /* pll_en_lb_res */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_COM_B_PLL_CTRL_0], 0x0000, 0x0010); /* pll_en_lb_ind */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_COM_B_PLL_CTRL_2], 0x0000, 0x0400); /* pll_lb_sel_pll0 */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_COM_B_PLL_CTRL_1], 0x0040, 0x0070); /* pll_rz_sel */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_COM_B_PLL_CTRL_1], 0x3800, 0x7800); /* pll_cp_calib_adj */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_COM_B_PLL_CTRL_2], 0x0000, 0x03C0); /* pll_cap_l_pll0 */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_COM_PLL_CONTROL_3], 0x0000, 0x000F); /* pll_cap_r_pll0 */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_COM_B_PLL_CTRL_3], 0x0002, 0x0007); /* pll_ictrl_pll0 */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_RESET2], 0x0000, 0x0010); /* pll_fracn_enable */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_SELECT], 0x0030, 0x003C); /* pll_i_en_ovrrad */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_COM_B_PLL_CTRL_1], 0x0000, 0x0180); /* pll_cp_sel */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_COM_B_PLL_CTRL_0], 0x1800, 0x1800); /* pll_fp3_r_sel */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_COM_B_PLL_CTRL_1], 0x0000, 0x000F); /* pll_fp3_c_sel */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_COM_B_PLL_CTRL_2], 0x0000, 0x0020); /* pll_en_offset_fbck */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_COM_B_PLL_CTRL_2], 0x0000, 0x0010); /* pll_en_offset_refclk */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_COM_B_PLL_CTRL_2], 0x0000, 0x000C); /* pll_fracn_offset_ctrl */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_COM_B_PLL_CTRL_2], 0x0000, 0x0003); /* pll_pfd_pulse_adj */
+
+	/* config set */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_POWER_DOWN], 0x0000, 0x0004); /* power up PLL */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_CONTROL], 0x0010, 0x0010); /* power up high band */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_CONTROL], 0x0008, 0x0008); /* power up low band */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_COM_B_PLL_CTRL_0], 0x0008, 0x0008); /* pll_en_lb_res */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_COM_B_PLL_CTRL_0], 0x0010, 0x0010); /* pll_i_en_kvh */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_CONTROL], 0x0000, 0x0008); /* power down low band */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_COM_B_PLL_CTRL_1], 0x3000, 0x7800); /* pll_cp_calib_adj */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_COM_B_PLL_CTRL_2], 0x00C0, 0x03C0); /* pll_cap_l_pll0 */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_COM_PLL_CONTROL_3], 0x0003, 0x000F); /* pll_cap_r_pll0 */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_COM_B_PLL_CTRL_3], 0x0002, 0x0007); /* pll_i_clkchnl */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_COM_B_PLL_CTRL_1], 0x0010, 0x0070); /* pll_rz_sel */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_FW_API_DATA0], 0x00C1, 0xFFFF); /* API data 0 */
+
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_CORE_PLL_COM_TOP_USER_CONTROL], 0x2000, 0x2000); /* clear PLL reset */
+
+	usleep_range(5000, 10000);
+
+	rtn = 0;
+out:
+	return rtn;
+}
+
+static int sl_core_hw_serdes_core_lgrp_reset(struct sl_core_lgrp *core_lgrp)
+{
+	int  rtn;
+	u8   lane_num;
+	u16 *addrs;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "reset");
+
+	addrs = core_lgrp->core_ldev->serdes.addrs;
+
+	for (lane_num = 0; lane_num < SL_SERDES_NUM_LANES; ++lane_num) {
+		/* TX */
+		SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, lane_num, 0,
+				  addrs[SERDES_TXCOM_CKRST_CTRL_TXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL],
+			0x0000, 0x0001); /* tx_ln_dp_s_rstb */
+		usleep_range(10, 20);
+		SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, lane_num, 0,
+				  addrs[SERDES_TXCOM_CKRST_CTRL_TXCOM_LN_S_RSTB_CONTROL], 0x0000, 0x0001); /* tx_ln_s_rstb */
+		usleep_range(10, 20);
+		SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, lane_num, 0,
+				  addrs[SERDES_TXCOM_CKRST_CTRL_TXCOM_LN_S_RSTB_CONTROL], 0x0001, 0x0001); /* tx_ln_s_rstb */
+		/* RX */
+		SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, lane_num, 0,
+				  addrs[SERDES_RXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL],
+			0x0000, 0x0001); /* rx_ln_dp_s_rstb */
+		usleep_range(10, 20);
+		SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, lane_num, 0,
+				  addrs[SERDES_RXCOM_CKRST_CTRL_RXCOM_LN_S_RSTB_CONTROL], 0x0000, 0x0001); /* rx_ln_s_rstb */
+		usleep_range(10, 20);
+		SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, lane_num, 0,
+				  addrs[SERDES_RXCOM_CKRST_CTRL_RXCOM_LN_S_RSTB_CONTROL], 0x0001, 0x0001); /* rx_ln_s_rstb */
+	}
+
+	rtn = 0;
+out:
+	return rtn;
+}
+
+int sl_core_hw_serdes_core_init(struct sl_core_lgrp *core_lgrp)
+{
+	int rtn;
+	u64 trace_map;
+
+	if (!SL_PLATFORM_IS_HARDWARE(core_lgrp->core_ldev))
+		return 0;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "core init");
+
+	trace_map = sl_serdes_core_io_trace_lgrp_map_get();
+	sl_core_data_lgrp_io_trace_set(core_lgrp, test_bit(core_lgrp->num, (unsigned long *)&trace_map));
+
+	rtn = sl_core_hw_serdes_core_proc_reset(core_lgrp);
+	if (rtn != 0) {
+		sl_core_log_err_trace(core_lgrp, LOG_NAME, "core_proc_reset failed [%d]", rtn);
+		goto out;
+	}
+	rtn = sl_core_hw_serdes_core_clock_init(core_lgrp);
+	if (rtn != 0) {
+		sl_core_log_err_trace(core_lgrp, LOG_NAME, "core_clock_init failed [%d]", rtn);
+		goto out;
+	}
+	rtn = sl_core_hw_serdes_core_lgrp_reset(core_lgrp);
+	if (rtn != 0) {
+		sl_core_log_err_trace(core_lgrp, LOG_NAME, "core_lgrp_reset failed [%d]", rtn);
+		goto out;
+	}
+
+	rtn = 0;
+out:
+	sl_core_data_lgrp_io_trace_set(core_lgrp, false);
+	return rtn;
+}
+
+static int sl_core_hw_serdes_core_pll_set(struct sl_core_lgrp *core_lgrp, u16 clocking, u16 tx_pll_bw)
+{
+	int  rtn;
+	u16 *addrs;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "pll set");
+
+	addrs = core_lgrp->core_ldev->serdes.addrs;
+
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_RESET2], 0x0000, 0x0800); /* set PLL reset */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_RESET2], 0x0800, 0x0800); /* clear PLL reset */
+
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_AMS_PLL_COM_PLL_CONTROL_12], 0x0000, 0x0008); /* update PLL ratio */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_RESET2], 0x1000, 0x3000); /* MMD 8/9 mode */
+
+	if (clocking == SL_CORE_HW_SERDES_CLOCKING_82P5) {
+		SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+				  addrs[SERDES_AMS_PLL_COM_PLL_CONTROL_10], 0x0052, 0x03FF); /* integer portion */
+		SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+				  addrs[SERDES_AMS_PLL_COM_PLL_CONTROL_11], 0x0000, 0xFFFF); /* fractional portion low 16 bits */
+		SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+				  addrs[SERDES_AMS_PLL_COM_PLL_CONTROL_12], 0x0002, 0x0003); /* fractional portion top 2 bits */
+	} else {
+		SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+				  addrs[SERDES_AMS_PLL_COM_PLL_CONTROL_10], 0x0055, 0x03FF); /* integer portion */
+		SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+				  addrs[SERDES_AMS_PLL_COM_PLL_CONTROL_11], 0x0000, 0xFFFF); /* fractional portion low 16 bits */
+		SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+				  addrs[SERDES_AMS_PLL_COM_PLL_CONTROL_12], 0x0000, 0x0003); /* fractional portion top 2 bits */
+	}
+
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_AMS_PLL_COM_PLL_CONTROL_12], 0x0008, 0x0008); /* update PLL ratio */
+	usleep_range(10, 20);
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_AMS_PLL_COM_PLL_CONTROL_12], 0x0000, 0x0008); /* update PLL ratio */
+
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_SELECT], tx_pll_bw, 0x003C); /* pll_i_en_ovrrad */
+
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_RESET2], 0x0000, 0x0800); /* set PLL reset */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_RESET2], 0x0800, 0x0800); /* clear PLL reset */
+
+	rtn = 0;
+out:
+	return rtn;
+}
+
+static int sl_core_hw_serdes_core_pll_check(struct sl_core_lgrp *core_lgrp)
+{
+	int  rtn;
+	u16  data16;
+	u16 *addrs;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "pll check");
+
+	addrs = core_lgrp->core_ldev->serdes.addrs;
+
+	SL_CORE_HW_PMI_RD(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_PLL_CAL_COM_STS_0], &data16);
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "0x%X = 0x%X", addrs[SERDES_PLL_CAL_COM_STS_0], data16);
+	if ((data16 & 0x0200) == 0) { /* PLL lock status */
+		sl_core_log_err_trace(core_lgrp, LOG_NAME, "pll lock failed");
+		rtn = -EIO;
+		goto out;
+	}
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "pll locked");
+
+	rtn = 0;
+out:
+	return rtn;
+}
+
+int sl_core_hw_serdes_core_pll(struct sl_core_lgrp *core_lgrp, u16 clocking, u16 tx_pll_bw)
+{
+	int  rtn;
+	u16 *addrs;
+	u64  trace_map;
+
+	if (!SL_PLATFORM_IS_HARDWARE(core_lgrp->core_ldev))
+		return 0;
+
+	if (core_lgrp->serdes.clocking == clocking) {
+		sl_core_log_dbg(core_lgrp, LOG_NAME, "pll clocking already set");
+		return 0;
+	}
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "pll");
+
+	trace_map = sl_serdes_core_io_trace_lgrp_map_get();
+	sl_core_data_lgrp_io_trace_set(core_lgrp, test_bit(core_lgrp->num, (unsigned long *)&trace_map));
+
+	addrs = core_lgrp->core_ldev->serdes.addrs;
+
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_CORE_PLL_COM_TOP_USER_CONTROL], 0x0000, 0x2000); /* set PLL reset */
+
+	rtn = sl_core_hw_serdes_core_pll_set(core_lgrp, clocking, tx_pll_bw);
+	if (rtn) {
+		sl_core_log_err_trace(core_lgrp, LOG_NAME, "core_pll_set failed [%d]", rtn);
+		goto out;
+	}
+
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+			  addrs[SERDES_CORE_PLL_COM_TOP_USER_CONTROL], 0x2000, 0x2000); /* clear PLL reset */
+
+	usleep_range(5000, 10000);
+
+	rtn = sl_core_hw_serdes_core_pll_check(core_lgrp);
+	if (rtn) {
+		sl_core_log_err_trace(core_lgrp, LOG_NAME, "core_pll_check failed [%d]", rtn);
+		goto out;
+	}
+
+	core_lgrp->serdes.clocking = clocking;
+
+	rtn = 0;
+out:
+	sl_core_data_lgrp_io_trace_set(core_lgrp, false);
+	return rtn;
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes_fw.c b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes_fw.c
new file mode 100644
index 000000000000..d051c40c9a66
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes_fw.c
@@ -0,0 +1,191 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/umh.h>
+#include <linux/delay.h>
+#include <linux/firmware.h>
+#include <linux/unaligned.h>
+
+#include "sl_asic.h"
+#include "sl_platform.h"
+#include "sl_core_lgrp.h"
+#include "base/sl_core_log.h"
+#include "hw/sl_core_hw_pmi.h"
+#include "hw/sl_core_hw_sbus.h"
+#include "hw/sl_core_hw_sbus_pmi.h"
+#include "hw/sl_core_hw_serdes_fw.h"
+#include "hw/sl_core_hw_serdes_addrs.h"
+
+#define LOG_NAME SL_CORE_SERDES_LOG_NAME
+
+#define SL_HW_SERDES_INIT_CHECK_TRIES 50
+int sl_core_hw_serdes_fw_setup(struct sl_core_lgrp *core_lgrp)
+{
+	int  rtn;
+	int  x;
+	u16  data16;
+	u16 *addrs;
+
+	if (!SL_PLATFORM_IS_HARDWARE(core_lgrp->core_ldev))
+		return 0;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "fw setup");
+
+	addrs = core_lgrp->core_ldev->serdes.addrs;
+
+	SL_CORE_HW_SBUS_FIELD_WR(core_lgrp, core_lgrp->serdes.dt.dev_addr, 48, 0x0, 1, 0x1); /* POR_H_RSTB_SBUS */
+	SL_CORE_HW_SBUS_FIELD_WR(core_lgrp, core_lgrp->serdes.dt.dev_addr, 48, 0x1, 2, 0x1); /* POR_H_RSTB_GATE */
+	usleep_range(1000, 2000);
+	SL_CORE_HW_SBUS_FIELD_WR(core_lgrp, core_lgrp->serdes.dt.dev_addr, 48, 0x1, 1, 0x1); /* POR_H_RSTB_SBUS */
+
+	for (x = 0; x < SL_SERDES_NUM_MICROS; ++x) {
+		SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, x,
+				  addrs[SERDES_MICRO_E_COM_MICRO_CORE_CLOCK_CONTROL0], 0x0000, 0x0001); /* disable micro clock */
+		SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, x,
+				  addrs[SERDES_MICRO_E_COM_MICRO_CORE_RESET_CONTROL0], 0x0000, 0x0001); /* set micro reset */
+	}
+
+	SL_CORE_HW_SBUS_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_addr, core_lgrp->serdes.dt.dev_id, 0, 0,
+			       addrs[SERDES_MICRO_C_COM_RAM_CONTROL0], 0x0001, 0x0001); /* enable writes to code RAM */
+
+	SL_CORE_HW_SBUS_WR(core_lgrp, core_lgrp->serdes.dt.dev_addr, 0, 0x80000000); /* enable access to PRAM */
+
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0, 0,
+			  addrs[SERDES_MICRO_A_COM_CLOCK_CONTROL0], 0x0001, 0x0001); /* enable micro master clocks */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0, 0,
+			  addrs[SERDES_MICRO_A_COM_RESET_CONTROL0], 0x0000, 0x0001); /* set micro master reset */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0, 0,
+			  addrs[SERDES_MICRO_A_COM_RESET_CONTROL0], 0x0001, 0x0001); /* remove micro master reset */
+
+	SL_CORE_HW_SBUS_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_addr, core_lgrp->serdes.dt.dev_id, 0, 0,
+			       addrs[SERDES_MICRO_C_COM_RAM_CONTROL0], 0x0000, 0x0002); /* disable micro access to code RAM */
+
+	SL_CORE_HW_SBUS_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_addr, core_lgrp->serdes.dt.dev_id, 0, 0,
+			       addrs[SERDES_MICRO_A_COM_AHB_CONTROL0], 0x0100, 0x0300); /* init code RAM */
+	for (x = 0; x < SL_HW_SERDES_INIT_CHECK_TRIES; ++x) {
+		usleep_range(1000, 2000);
+		SL_CORE_HW_PMI_RD(core_lgrp, core_lgrp->serdes.dt.dev_id, 0, 0,
+				  addrs[SERDES_MICRO_A_COM_AHB_STATUS0], &data16); /* check init done */
+		sl_core_log_dbg(core_lgrp, LOG_NAME, "code RAM init 0x%X = 0x%X",
+				addrs[SERDES_MICRO_A_COM_AHB_STATUS0], data16);
+		if ((data16 & 0x0001) != 0)
+			break;
+	}
+	SL_CORE_HW_SBUS_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_addr, core_lgrp->serdes.dt.dev_id, 0, 0,
+			       addrs[SERDES_MICRO_A_COM_AHB_CONTROL0], 0x0000, 0x0300); /* disable init */
+	if (x >= SL_HW_SERDES_INIT_CHECK_TRIES) {
+		sl_core_log_err_trace(core_lgrp, LOG_NAME, "fw setup RAM init timeout");
+		rtn = -EIO;
+		goto out;
+	}
+
+	SL_CORE_HW_SBUS_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_addr, core_lgrp->serdes.dt.dev_id, 0, 0,
+			       addrs[SERDES_MICRO_A_COM_AHB_CONTROL0], 0x0200, 0x0300); /* init data RAM */
+	for (x = 0; x < SL_HW_SERDES_INIT_CHECK_TRIES; ++x) {
+		usleep_range(1000, 2000);
+		SL_CORE_HW_PMI_RD(core_lgrp, core_lgrp->serdes.dt.dev_id, 0xFF, 0,
+				  addrs[SERDES_MICRO_A_COM_AHB_STATUS0], &data16); /* check init done */
+		sl_core_log_dbg(core_lgrp, LOG_NAME, "code RAM init 0x%X = 0x%X",
+				addrs[SERDES_MICRO_A_COM_AHB_STATUS0], data16);
+		if ((data16 & 0x0001) != 0)
+			break;
+	}
+	SL_CORE_HW_SBUS_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_addr, core_lgrp->serdes.dt.dev_id, 0, 0,
+			       addrs[SERDES_MICRO_A_COM_AHB_CONTROL0], 0x0000, 0x0300); /* disable init */
+	if (x >= SL_HW_SERDES_INIT_CHECK_TRIES) {
+		sl_core_log_err_trace(core_lgrp, LOG_NAME, "code RAM init timeout");
+		rtn = -EIO;
+		goto out;
+	}
+
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0, 0,
+			  addrs[SERDES_MICRO_B_COM_RMI_RAM_CR_CRCCONTROL0], 0x0004, 0x0004); /* set init CRC */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0, 0,
+			  addrs[SERDES_MICRO_B_COM_RMI_RAM_CR_CRCCONTROL0], 0x0000, 0x0004); /* remove init CRC */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0, 0,
+			  addrs[SERDES_MICRO_B_COM_RMI_RAM_CR_CRCCONTROL0], 0x0002, 0x0002); /* set init checksum */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0, 0,
+			  addrs[SERDES_MICRO_B_COM_RMI_RAM_CR_CRCCONTROL0], 0x0000, 0x0002); /* remove init checksum */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0, 0,
+			  addrs[SERDES_MICRO_B_COM_RMI_RAM_CR_CRCCONTROL0], 0x0001, 0x0001); /* enable CRC engine */
+
+	SL_CORE_HW_SBUS_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_addr, core_lgrp->serdes.dt.dev_id, 0, 0,
+			       addrs[SERDES_MICRO_A_COM_PRAMIF_AHB_WRADDR_LSW], 0x0000, 0xFFFC); /* start address */
+	SL_CORE_HW_SBUS_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_addr, core_lgrp->serdes.dt.dev_id, 0, 0,
+			       addrs[SERDES_MICRO_A_COM_PRAMIF_AHB_WRADDR_MSW], 0x0000, 0xFFFF); /* start address */
+
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0, 0,
+			  addrs[SERDES_MICRO_A_COM_RESET_CONTROL0], 0x8000, 0x8000); /* remove reset from PRAM */
+	SL_CORE_HW_SBUS_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_addr, core_lgrp->serdes.dt.dev_id, 0, 0,
+			       addrs[SERDES_MICRO_A_COM_PRAMIF_CONTROL0], 0x0001, 0x0001); /* enable PRAM interface */
+
+	rtn = 0;
+out:
+	return rtn;
+}
+
+int sl_core_hw_serdes_fw_write(struct sl_core_lgrp *core_lgrp)
+{
+	int                    rtn;
+	size_t                 x;
+	u32                    data32;
+	const struct firmware *fw;
+
+	fw = core_lgrp->core_ldev->serdes.fw;
+
+	if (!SL_PLATFORM_IS_HARDWARE(core_lgrp->core_ldev))
+		return 0;
+
+	if (!fw || !fw->data || !fw->size ||
+	    !IS_ALIGNED(fw->size, sizeof(data32)))
+		return -EINVAL;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "fw write (size = %lu bytes)", fw->size);
+
+	for (x = 0; x < fw->size; x += 4) {
+		data32 = get_unaligned_le32(fw->data + x);
+		SL_CORE_HW_SBUS_WR(core_lgrp, 0xFA, 10, data32);
+	}
+
+	rtn = 0;
+out:
+	return rtn;
+}
+
+int sl_core_hw_serdes_fw_finish(struct sl_core_lgrp *core_lgrp)
+{
+	int  rtn;
+	u16  data16;
+	u16 *addrs;
+
+	if (!SL_PLATFORM_IS_HARDWARE(core_lgrp->core_ldev))
+		return 0;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "fw finish");
+
+	addrs = core_lgrp->core_ldev->serdes.addrs;
+
+	SL_CORE_HW_SBUS_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_addr, core_lgrp->serdes.dt.dev_id, 0, 0,
+			       addrs[SERDES_MICRO_C_COM_RAM_CONTROL0], 0x0002, 0x0002); /* disable writes to code RAM */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, 0, 0,
+			  addrs[SERDES_MICRO_B_COM_RMI_RAM_CR_CRCCONTROL0], 0x0000, 0x0001); /* disable CRC engine */
+	SL_CORE_HW_SBUS_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_addr, core_lgrp->serdes.dt.dev_id, 0, 0,
+			       addrs[SERDES_MICRO_A_COM_PRAMIF_CONTROL0], 0x0000, 0x0001); /* disable PRAM interface */
+
+	SL_CORE_HW_SBUS_WR(core_lgrp, core_lgrp->serdes.dt.dev_addr, 0, 0x00000000); /* disable access to PRAM */
+
+	SL_CORE_HW_PMI_RD(core_lgrp, core_lgrp->serdes.dt.dev_id, 0, 0,
+			  addrs[SERDES_MICRO_B_COM_RMI_RAM_CR_CRCSTATUS0], &data16); /* read CRC */
+	if (data16 != SL_HW_SERDES_FW_IMAGE_CRC) {
+		sl_core_log_err_trace(core_lgrp, LOG_NAME,
+				      "fw finish crc check failure (crc = 0x%04X, expected = 0x%04X)",
+				      data16, SL_HW_SERDES_FW_IMAGE_CRC);
+		rtn = -EIO;
+		goto out;
+	}
+
+	rtn = 0;
+out:
+	return rtn;
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes_lane.c b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes_lane.c
new file mode 100644
index 000000000000..b27fc03ecaa2
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes_lane.c
@@ -0,0 +1,1085 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2024-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/delay.h>
+
+#include "sl_core_lgrp.h"
+#include "sl_core_link.h"
+#include "sl_core_str.h"
+#include "base/sl_core_log.h"
+#include "hw/sl_core_hw_serdes_lane.h"
+#include "hw/sl_core_hw_io.h"
+#include "hw/sl_core_hw_pmi.h"
+#include "hw/sl_core_hw_pcs.h"
+#include "hw/sl_core_hw_uc_ram.h"
+#include "hw/sl_core_hw_settings.h"
+#include "hw/sl_core_hw_serdes_addrs.h"
+#include "data/sl_core_data_link.h"
+
+#define LOG_NAME SL_CORE_SERDES_LOG_NAME
+
+u8 sl_core_hw_serdes_rx_asic_lane_num_get(struct sl_core_link *core_link, u8 serdes_lane_num)
+{
+	u8                   asic_lane_num;
+	struct sl_core_lgrp *core_lgrp;
+
+	core_lgrp = core_link->core_lgrp;
+
+	for (asic_lane_num = 0; asic_lane_num < SL_MAX_LANES; ++asic_lane_num)
+		if (core_lgrp->serdes.dt.lane_info[asic_lane_num].rx_source +
+				(4 * (core_lgrp->num & BIT(0))) == serdes_lane_num) {
+			sl_core_log_dbg(core_lgrp, LOG_NAME,
+					"RX asic lane get (asic_lane_num = %u, serdes_lane_num = %u)",
+				asic_lane_num, serdes_lane_num);
+			return asic_lane_num;
+		}
+
+	sl_core_log_err_trace(core_lgrp, LOG_NAME,
+			      "RX asic lane get not found (serdes_lane_num = %u)", serdes_lane_num);
+	return 0;
+}
+
+u8 sl_core_hw_serdes_tx_asic_lane_num_get(struct sl_core_link *core_link, u8 serdes_lane_num)
+{
+	u8                   asic_lane_num;
+	struct sl_core_lgrp *core_lgrp;
+
+	core_lgrp = core_link->core_lgrp;
+
+	for (asic_lane_num = 0; asic_lane_num < SL_MAX_LANES; ++asic_lane_num)
+		if (core_lgrp->serdes.dt.lane_info[asic_lane_num].tx_source +
+				(4 * (core_lgrp->num & BIT(0))) == serdes_lane_num) {
+			sl_core_log_dbg(core_lgrp, LOG_NAME,
+					"TX asic lane get (asic_lane_num = %u, serdes_lane_num = %u)",
+				asic_lane_num, serdes_lane_num);
+			return asic_lane_num;
+		}
+
+	sl_core_log_err_trace(core_lgrp, LOG_NAME,
+			      "TX asic lane get not found (serdes_lane_num = %u)", serdes_lane_num);
+	return 0;
+}
+
+static u8 sl_core_hw_serdes_rx_serdes_lane_num_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num)
+{
+	sl_core_log_dbg(core_lgrp, LOG_NAME,
+			"RX serdes lane get (asic_lane_num = %u, serdes_lane_num = %lu)", asic_lane_num,
+		core_lgrp->serdes.dt.lane_info[asic_lane_num].rx_source + (4 * (core_lgrp->num & BIT(0))));
+
+	return core_lgrp->serdes.dt.lane_info[asic_lane_num].rx_source + (4 * (core_lgrp->num & BIT(0)));
+}
+
+static u8 sl_core_hw_serdes_tx_serdes_lane_num_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num)
+{
+	sl_core_log_dbg(core_lgrp, LOG_NAME,
+			"TX serdes lane get (asic_lane_num = %u, serdes_lane_num = %lu)", asic_lane_num,
+		core_lgrp->serdes.dt.lane_info[asic_lane_num].tx_source + (4 * (core_lgrp->num & BIT(0))));
+
+	return core_lgrp->serdes.dt.lane_info[asic_lane_num].tx_source + (4 * (core_lgrp->num & BIT(0)));
+}
+
+int sl_core_hw_serdes_lane_pre1_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, s16 *pre1)
+{
+	int rtn;
+	u16 data16;
+	u8  serdes_lane_num;
+
+	serdes_lane_num = sl_core_hw_serdes_tx_serdes_lane_num_get(core_lgrp, asic_lane_num);
+
+	SL_CORE_HW_PMI_RD(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  core_lgrp->core_ldev->serdes.addrs[SERDES_TX_FED_TXFIR_TAP_CONTROL2], &data16);
+
+	*pre1 = (s16)((data16 & 0x01FF) << 7) >> 7;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME,
+			"pre1 get (data16 = 0x%X, pre1 = %d)", data16, *pre1);
+
+	return 0;
+out:
+	return rtn;
+}
+
+int sl_core_hw_serdes_lane_pre2_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, s16 *pre2)
+{
+	int rtn;
+	u16 data16;
+	u8  serdes_lane_num;
+
+	serdes_lane_num = sl_core_hw_serdes_tx_serdes_lane_num_get(core_lgrp, asic_lane_num);
+
+	SL_CORE_HW_PMI_RD(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  core_lgrp->core_ldev->serdes.addrs[SERDES_TX_FED_TXFIR_TAP_CONTROL1], &data16);
+
+	*pre2 = (s16)((data16 & 0x01FF) << 7) >> 7;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME,
+			"pre2 get (data16 = 0x%X, pre2 = %d)", data16, *pre2);
+
+	return 0;
+out:
+	return rtn;
+}
+
+int sl_core_hw_serdes_lane_pre3_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, s16 *pre3)
+{
+	int rtn;
+	u16 data16;
+	u8  serdes_lane_num;
+
+	serdes_lane_num = sl_core_hw_serdes_tx_serdes_lane_num_get(core_lgrp, asic_lane_num);
+
+	SL_CORE_HW_PMI_RD(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  core_lgrp->core_ldev->serdes.addrs[SERDES_TX_FED_TXFIR_TAP_CONTROL0], &data16);
+
+	*pre3 = (s16)((data16 & 0x01FF) << 7) >> 7;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME,
+			"pre3 get (data16 = 0x%X, pre3 = %d)", data16, *pre3);
+
+	return 0;
+out:
+	return rtn;
+}
+
+int sl_core_hw_serdes_lane_cursor_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, s16 *cursor)
+{
+	int rtn;
+	u16 data16;
+	u8  serdes_lane_num;
+
+	serdes_lane_num = sl_core_hw_serdes_tx_serdes_lane_num_get(core_lgrp, asic_lane_num);
+
+	SL_CORE_HW_PMI_RD(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  core_lgrp->core_ldev->serdes.addrs[SERDES_TX_FED_TXFIR_TAP_CONTROL3], &data16);
+
+	*cursor = (s16)((data16 & 0x01FF) << 7) >> 7;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME,
+			"cursor get (data16 = 0x%X, cursor = %d)", data16, *cursor);
+
+	return 0;
+out:
+	return rtn;
+}
+
+int sl_core_hw_serdes_lane_post1_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, s16 *post1)
+{
+	int rtn;
+	u16 data16;
+	u8  serdes_lane_num;
+
+	serdes_lane_num = sl_core_hw_serdes_tx_serdes_lane_num_get(core_lgrp, asic_lane_num);
+
+	SL_CORE_HW_PMI_RD(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  core_lgrp->core_ldev->serdes.addrs[SERDES_TX_FED_TXFIR_TAP_CONTROL4], &data16);
+
+	*post1 = (s16)((data16 & 0x01FF) << 7) >> 7;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME,
+			"post1 get (data16 = 0x%X, post1 = %d)", data16, *post1);
+
+	return 0;
+out:
+	return rtn;
+}
+
+int sl_core_hw_serdes_lane_post2_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, s16 *post2)
+{
+	int rtn;
+	u16 data16;
+	u8  serdes_lane_num;
+
+	serdes_lane_num = sl_core_hw_serdes_tx_serdes_lane_num_get(core_lgrp, asic_lane_num);
+
+	SL_CORE_HW_PMI_RD(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  core_lgrp->core_ldev->serdes.addrs[SERDES_TX_FED_TXFIR_TAP_CONTROL5], &data16);
+
+	*post2 = (s16)((data16 & 0x01FF) << 7) >> 7;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME,
+			"post2 get (data16 = 0x%X, post2 = %d)", data16, *post2);
+
+	return 0;
+out:
+	return rtn;
+}
+
+u16 sl_core_hw_serdes_mode(struct sl_core_lgrp *core_lgrp,
+			   struct sl_core_serdes_settings *settings)
+{
+	u16 mode;
+
+	mode = settings->osr;
+
+	if (settings->encoding != SL_CORE_HW_SERDES_ENCODING_NRZ)
+		mode |= (0x1 << 6);
+
+	mode |= (settings->width << 7);
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "serdes mode = 0x%X", mode);
+
+	return mode;
+}
+
+int sl_core_hw_serdes_lane_osr_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, u8 *osr)
+{
+	u64 data64;
+	u32 port;
+
+	port = core_lgrp->num;
+
+	sl_core_lgrp_read64(core_lgrp, SS2_PORT_PML_CFG_SERDES_TX(asic_lane_num), &data64);
+
+	*osr = (SS2_PORT_PML_CFG_SERDES_TX_PMD_TX_OSR_MODE_GET(data64) & 0x3F);
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "osr get (port = %u, osr = %u)", port, *osr);
+
+	return 0;
+}
+
+int sl_core_hw_serdes_lane_encoding_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, u8 *encoding)
+{
+	int rtn;
+	u64 data64;
+	u32 port;
+	u16 data16;
+	u8  serdes_lane_num;
+
+	port = core_lgrp->num;
+
+	sl_core_lgrp_read64(core_lgrp, SS2_PORT_PML_CFG_SERDES_TX(asic_lane_num), &data64);
+
+	if (SS2_PORT_PML_CFG_SERDES_TX_PMD_TX_OSR_MODE_GET(data64) & 0x40) {
+		serdes_lane_num = sl_core_hw_serdes_tx_serdes_lane_num_get(core_lgrp, asic_lane_num);
+		SL_CORE_HW_PMI_RD(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+				  core_lgrp->core_ldev->serdes.addrs[SERDES_CDR_CONTROL_0], &data16); /* rx_pam4_er_mode */
+		sl_core_log_dbg(core_lgrp, LOG_NAME,
+				"encoding get (serdes_lane_num = %u, encoding = 0x%X)",
+			serdes_lane_num, (data16 & 0x8000));
+		if (data16 & 0x8000)
+			*encoding = SL_CORE_HW_SERDES_ENCODING_PAM4_ER;
+		else
+			*encoding = SL_CORE_HW_SERDES_ENCODING_PAM4_NR;
+	} else {
+		*encoding = SL_CORE_HW_SERDES_ENCODING_NRZ;
+	}
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME,
+			"encoding get (port = %u, encoding = %u)", port, *encoding);
+
+	return 0;
+out:
+	return rtn;
+}
+
+int sl_core_hw_serdes_lane_width_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, u8 *width)
+{
+	u64 data64;
+	u32 port;
+
+	port = core_lgrp->num;
+
+	sl_core_lgrp_read64(core_lgrp, SS2_PORT_PML_CFG_SERDES_TX(asic_lane_num), &data64);
+
+	*width = ((SS2_PORT_PML_CFG_SERDES_TX_PMD_TX_OSR_MODE_GET(data64) >> 7) & 0x3);
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME,
+			"width get (port = %u, width = %u)", port, *width);
+
+	return 0;
+}
+
+u16 sl_core_hw_serdes_config(struct sl_core_lgrp *core_lgrp,
+			     struct sl_core_serdes_settings *core_serdes_settings,
+	struct sl_media_serdes_settings *media_serdes_settings)
+{
+	u16 config;
+
+	config = 0;
+
+	config |= ((core_serdes_settings->dfe & 0x1) << 2);
+
+	config |= ((media_serdes_settings->media & 0x3) << 5);
+
+	config |= ((core_serdes_settings->scramble_dis & 0x1) << 8);
+
+	switch (core_serdes_settings->encoding) {
+	case SL_CORE_HW_SERDES_ENCODING_PAM4_ER:
+		config |= (1 << 11);
+		break;
+	case SL_CORE_HW_SERDES_ENCODING_PAM4_NR:
+		config |= (1 << 14);
+		break;
+	case SL_CORE_HW_SERDES_ENCODING_NRZ:
+		config |= (1 << 15);
+		break;
+	}
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "serdes config = 0x%X", config);
+
+	return config;
+}
+
+int sl_core_hw_serdes_lane_dfe_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, u8 *dfe)
+{
+	int rtn;
+	u16 data16;
+	u8  serdes_lane_num;
+
+	serdes_lane_num = sl_core_hw_serdes_rx_serdes_lane_num_get(core_lgrp, asic_lane_num);
+
+	SL_CORE_HW_PMI_RD(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  core_lgrp->core_ldev->serdes.addrs[SERDES_FW_API_DATA0], &data16);
+
+	*dfe = ((data16 >> 2) & 0x1);
+
+	return 0;
+out:
+	return rtn;
+}
+
+int sl_core_hw_serdes_lane_scramble_dis_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, u8 *scramble_dis)
+{
+	int rtn;
+	u16 data16;
+	u8  serdes_lane_num;
+
+	serdes_lane_num = sl_core_hw_serdes_rx_serdes_lane_num_get(core_lgrp, asic_lane_num);
+
+	SL_CORE_HW_PMI_RD(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  core_lgrp->core_ldev->serdes.addrs[SERDES_FW_API_DATA0], &data16);
+
+	*scramble_dis = ((data16 >> 8) & 0x1);
+
+	return 0;
+out:
+	return rtn;
+}
+
+static int sl_core_hw_serdes_lane_up_clock_align(struct sl_core_lgrp *core_lgrp, u8 serdes_lane_num)
+{
+	int  rtn;
+	u16 *addrs;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME,
+			"lane up clock align (serdes_lane_num = %u)", serdes_lane_num);
+
+	addrs = core_lgrp->core_ldev->serdes.addrs;
+
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  addrs[SERDES_AMS_TX_TXCONTROL_3], 0x0000, 0x0080); /* ams_tx_sel_txmaster */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  addrs[SERDES_TX_PI_TXPICONTROL_5], 0x0000, 0x0800); /* tx_pi_pd_bypass_vco */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  addrs[SERDES_TX_PI_TXPICONTROL_5], 0x0000, 0x0400); /* tx_pi_pd_bypass_flt */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  addrs[SERDES_TX_PI_TXPICONTROL_5], 0x0000, 0x0010); /* tx_pi_hs_fifo_phserr_sel */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  addrs[SERDES_TX_PI_TXPICONTROL_5], 0x0000, 0x0008); /* tx_pi_ext_pd_sel */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  addrs[SERDES_TX_PI_TXPICONTROL_0], 0x0000, 0x0001); /* tx_pi_en */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  addrs[SERDES_TX_PI_TXPICONTROL_0], 0x0000, 0x0002); /* tx_pi_jitter_filter_en */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  addrs[SERDES_TX_PI_TXPICONTROL_0], 0x0000, 0x0004); /* tx_pi_ext_ctrl_en */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  addrs[SERDES_TX_PI_TXPICONTROL_0], 0x0000, 0x7000); /* tx_pi_ext_phase_bwsel_integ */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  addrs[SERDES_TX_PI_TXPICONTROL_5], 0x0000, 0x0800); /* tx_pi_pd_bypass_vco */
+
+	rtn = 0;
+out:
+	return rtn;
+}
+
+#define LANE_UP_TX_CHECK_NUM_TRIES 10
+#define LANE_UP_TX_DATA_VALID_BIT  BIT(20)
+#define LANE_UP_TX_CLOCK_VALID_BIT BIT(16)
+#define LANE_UP_TX_CHECK_BITS      (LANE_UP_TX_DATA_VALID_BIT | \
+				    LANE_UP_TX_CLOCK_VALID_BIT)
+static int sl_core_hw_serdes_lane_up_tx_check(struct sl_core_link *core_link, u8 serdes_lane_num)
+{
+	int                  rtn;
+	bool                 is_canceled_or_timed_out;
+	u8                   x;
+	u32                  port;
+	u64                  status;
+	u8                   asic_lane_num;
+	struct sl_core_lgrp *core_lgrp;
+
+	core_lgrp     = core_link->core_lgrp;
+	port          = core_lgrp->num;
+	asic_lane_num = sl_core_hw_serdes_tx_asic_lane_num_get(core_link, serdes_lane_num);
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME,
+			"lane up tx check (port = %u, serdes_lane_num = %u, asic_lane_num = %u)",
+		port, serdes_lane_num, asic_lane_num);
+
+	sl_core_hw_serdes_tx_lane_state_set(core_lgrp,
+					    asic_lane_num, SL_CORE_HW_SERDES_LANE_STATE_CHECK);
+
+	for (x = 0; x < LANE_UP_TX_CHECK_NUM_TRIES; ++x) {
+		rtn = sl_core_link_is_canceled_or_timed_out(core_link, &is_canceled_or_timed_out);
+		if (rtn) {
+			sl_core_log_err_trace(core_lgrp, LOG_NAME,
+					      "lane up tx check - is_canceled_or_timed_out failed [%d]", rtn);
+			return rtn;
+		}
+
+		if (is_canceled_or_timed_out) {
+			sl_core_log_dbg(core_link, LOG_NAME, "lane up tx check canceled");
+			return -ECANCELED;
+		}
+		msleep(100);
+		sl_core_lgrp_read64(core_lgrp, SS2_PORT_PML_STS_SERDES(asic_lane_num), &status);
+		sl_core_log_dbg(core_lgrp, LOG_NAME,
+				"lane up tx check (asic_lane_num = %u, status = 0x%llX)", asic_lane_num, status);
+		if ((status & LANE_UP_TX_CHECK_BITS) == LANE_UP_TX_CHECK_BITS)
+			return 0;
+	}
+
+	sl_core_log_err_trace(core_lgrp, LOG_NAME,
+			      "lane up tx check fail (lane = %u, status = 0x%llX)", asic_lane_num, status);
+	return -EIO;
+}
+
+#define LANE_UP_RX_CHECK_NUM_TRIES        70
+#define LANE_UP_RX_CHECK_DATA_VALID_BIT   BIT(12)
+#define LANE_UP_RX_CHECK_CLOCK_VALID_BIT  BIT(8)
+#define LANE_UP_RX_CHECK_LOCK_BIT         BIT(4)
+#define LANE_UP_RX_CHECK_BITS             (LANE_UP_RX_CHECK_DATA_VALID_BIT  | \
+					   LANE_UP_RX_CHECK_CLOCK_VALID_BIT | \
+					   LANE_UP_RX_CHECK_LOCK_BIT)
+/* wait for 6s for PAM4 and 1.5s for NRZ */
+static int sl_core_hw_serdes_lane_up_rx_check(struct sl_core_link *core_link, u8 serdes_lane_num)
+{
+	int                  rtn;
+	bool                 is_canceled_or_timed_out;
+	u8                   x;
+	u32                  port;
+	u64                  status;
+	u8                   asic_lane_num;
+	struct sl_core_lgrp *core_lgrp;
+
+	core_lgrp     = core_link->core_lgrp;
+	port          = core_lgrp->num;
+	asic_lane_num = sl_core_hw_serdes_rx_asic_lane_num_get(core_link, serdes_lane_num);
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME,
+			"lane up rx check (port = %u, serdes_lane_num = %u, asic_lane_num = %u)",
+		port, serdes_lane_num, asic_lane_num);
+
+	sl_core_hw_serdes_rx_lane_state_set(core_lgrp,
+					    asic_lane_num, SL_CORE_HW_SERDES_LANE_STATE_CHECK);
+
+	for (x = 0; x < LANE_UP_RX_CHECK_NUM_TRIES; ++x) {
+		rtn = sl_core_link_is_canceled_or_timed_out(core_link, &is_canceled_or_timed_out);
+		if (rtn) {
+			sl_core_log_err_trace(core_lgrp, LOG_NAME,
+					      "lane up rx check - is_canceled_or_timed_out failed [%d]", rtn);
+			return rtn;
+		}
+
+		if (is_canceled_or_timed_out) {
+			sl_core_log_dbg(core_link, LOG_NAME, "lane up rx check canceled");
+			return -ECANCELED;
+		}
+		msleep(300);
+		sl_core_lgrp_read64(core_lgrp, SS2_PORT_PML_STS_SERDES(asic_lane_num), &status);
+		sl_core_log_dbg(core_lgrp, LOG_NAME,
+				"lane up rx check (asic_lane_num = %u, status = 0x%llX)", asic_lane_num, status);
+		if ((status & LANE_UP_RX_CHECK_BITS) == LANE_UP_RX_CHECK_BITS)
+			return 0;
+	}
+
+	sl_core_log_err_trace(core_lgrp, LOG_NAME,
+			      "lane up rx check fail (asic_lane_num = %u, status = 0x%llX)", asic_lane_num, status);
+	return -EIO;
+}
+
+#define LANE_UP_QUALITY_CHECK_NUM_TRIES 20
+static int sl_core_hw_serdes_lane_up_quality_check(struct sl_core_link *core_link, u8 serdes_lane_num)
+{
+	int                  rtn;
+	u8                   x;
+	u32                  port;
+	u8                   asic_lane_num;
+	u32                  addr;
+	u8                   eye_upper;
+	u8                   eye_lower;
+	u16                  data16;
+	struct sl_core_lgrp *core_lgrp;
+	u16                  extended;
+	u64                  data64;
+	bool                 is_canceled_or_timed_out;
+
+	core_lgrp     = core_link->core_lgrp;
+	port          = core_lgrp->num;
+	asic_lane_num = sl_core_hw_serdes_rx_asic_lane_num_get(core_link, serdes_lane_num);
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME,
+			"lane up quality check (port = %u, serdes_lane_num = %u, asic_lane_num = %u)",
+		port, serdes_lane_num, asic_lane_num);
+
+	/* if link training decides extended reach, then modify eye limits */
+	if (is_flag_set(core_link->core_lgrp->link_caps[core_link->num].hpe_map, SL_LINK_CONFIG_HPE_LINKTRAIN)) {
+		sl_core_lgrp_read64(core_lgrp, SS2_PORT_PML_CFG_SERDES_TX(asic_lane_num), &data64);
+		if (SS2_PORT_PML_CFG_SERDES_TX_PMD_TX_OSR_MODE_GET(data64) & 0x40) {
+			SL_CORE_HW_PMI_RD(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+					  core_lgrp->core_ldev->serdes.addrs[SERDES_CDR_CONTROL_0], &extended);
+			sl_core_log_dbg(core_lgrp, LOG_NAME,
+					"extended get (serdes_lane_num = %u, extended = 0x%X)",
+				serdes_lane_num, (extended & 0x8000));
+			if (extended & 0x8000) {
+				sl_core_log_dbg(core_lgrp, LOG_NAME, "lane up quality check extended reach");
+				core_link->core_lgrp->serdes.eye_limits[asic_lane_num].low  = 5;
+				core_link->core_lgrp->serdes.eye_limits[asic_lane_num].high = 30;
+				if (core_link->pcs.settings.pcs_mode == SL_CORE_HW_PCS_MODE_BJ_100G) {
+					core_link->core_lgrp->serdes.eye_limits[asic_lane_num].low  = 25;
+					core_link->core_lgrp->serdes.eye_limits[asic_lane_num].high = 150;
+				}
+			}
+		}
+	}
+
+	addr = SL_CORE_HW_SERDES_LANE_ADDR(0x7, serdes_lane_num, core_lgrp);
+
+	for (x = 0; x < LANE_UP_QUALITY_CHECK_NUM_TRIES; ++x) {
+		rtn = sl_core_link_is_canceled_or_timed_out(core_link, &is_canceled_or_timed_out);
+		if (rtn) {
+			sl_core_log_err_trace(core_lgrp, LOG_NAME,
+					      "lane up quality check - is_canceled_or_timed_out failed [%d]", rtn);
+			return rtn;
+		}
+
+		if (is_canceled_or_timed_out) {
+			sl_core_log_dbg(core_lgrp, LOG_NAME, "lane up quality check canceled");
+			return -ECANCELED;
+		}
+		msleep(200);
+		SL_CORE_HW_UC_RAM_RD8(core_lgrp, core_lgrp->serdes.dt.dev_addr, core_lgrp->serdes.dt.dev_id,
+				      serdes_lane_num, addr, &eye_upper);
+		sl_core_log_dbg(core_lgrp, LOG_NAME,
+				"lane up quality check (serdes_lane_num = %u, asic_lane_num = %u, eye_upper = %u, low = %u, high = %u)",
+			serdes_lane_num, asic_lane_num, eye_upper,
+			core_lgrp->serdes.eye_limits[asic_lane_num].low,
+			core_lgrp->serdes.eye_limits[asic_lane_num].high);
+		if ((eye_upper > core_lgrp->serdes.eye_limits[asic_lane_num].low) &&
+		    (eye_upper < core_lgrp->serdes.eye_limits[asic_lane_num].high))
+			break;
+	}
+	if (x >= LANE_UP_QUALITY_CHECK_NUM_TRIES)
+		return -EIO;
+
+	addr = SL_CORE_HW_SERDES_LANE_ADDR(0x8, serdes_lane_num, core_lgrp);
+
+	for (x = 0; x < LANE_UP_QUALITY_CHECK_NUM_TRIES; ++x) {
+		rtn = sl_core_link_is_canceled_or_timed_out(core_link, &is_canceled_or_timed_out);
+		if (rtn) {
+			sl_core_log_err_trace(core_lgrp, LOG_NAME,
+					      "lane up quality check - is_canceled_or_timed_out failed [%d]", rtn);
+			return rtn;
+		}
+
+		if (is_canceled_or_timed_out) {
+			sl_core_log_dbg(core_lgrp, LOG_NAME, "lane up quality check canceled");
+			return -ECANCELED;
+		}
+		msleep(200);
+		SL_CORE_HW_UC_RAM_RD8(core_lgrp, core_lgrp->serdes.dt.dev_addr, core_lgrp->serdes.dt.dev_id,
+				      serdes_lane_num, addr, &eye_lower);
+		sl_core_log_dbg(core_lgrp, LOG_NAME,
+				"lane up quality check (serdes_lane_num = %u, asic_lane_num = %u, eye_lower = %u, low = %u, high = %u)",
+			serdes_lane_num, asic_lane_num, eye_lower,
+			core_lgrp->serdes.eye_limits[asic_lane_num].low,
+			core_lgrp->serdes.eye_limits[asic_lane_num].high);
+		if ((eye_lower > core_lgrp->serdes.eye_limits[asic_lane_num].low) &&
+		    (eye_lower < core_lgrp->serdes.eye_limits[asic_lane_num].high))
+			break;
+	}
+	if (x >= LANE_UP_QUALITY_CHECK_NUM_TRIES)
+		return -EIO;
+
+	SL_CORE_HW_PMI_RD(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  core_lgrp->core_ldev->serdes.addrs[SERDES_RX_MISC_CONFIG],  &data16);
+	sl_core_log_dbg(core_lgrp, LOG_NAME,
+			"lane up quality check (serdes_lane_num = %u, 0x%X = 0x%X)", serdes_lane_num,
+		 core_lgrp->core_ldev->serdes.addrs[SERDES_RX_MISC_CONFIG], data16);
+	SL_CORE_HW_PMI_RD(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  core_lgrp->core_ldev->serdes.addrs[SERDES_TLB_TX_TLB_TX_PAM4_CONFIG_0],  &data16);
+	sl_core_log_dbg(core_lgrp, LOG_NAME,
+			"lane up quality check (serdes_lane_num = %u, 0x%X = 0x%X)",
+		core_lgrp->core_ldev->serdes.addrs[SERDES_TLB_TX_TLB_TX_PAM4_CONFIG_0],
+		serdes_lane_num, data16);
+
+	return 0;
+out:
+	return rtn;
+}
+
+static void sl_core_hw_pmd_tx_enable(struct sl_core_link *core_link, u8 serdes_lane_num)
+{
+	u64 data64;
+	u32 port;
+	u8  asic_lane_num;
+
+	port          = core_link->core_lgrp->num;
+	asic_lane_num = sl_core_hw_serdes_tx_asic_lane_num_get(core_link, serdes_lane_num);
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"pmd_tx_enable (port = %u, serdes_lane_num = %u, asic_lane_num = %u)",
+		port, serdes_lane_num, asic_lane_num);
+
+	sl_core_lgrp_read64(core_link->core_lgrp, SS2_PORT_PML_CFG_SERDES_TX(asic_lane_num), &data64);
+	data64 = SS2_PORT_PML_CFG_SERDES_TX_PMD_TX_DISABLE_UPDATE(data64, 0);
+	sl_core_lgrp_write64(core_link->core_lgrp, SS2_PORT_PML_CFG_SERDES_TX(asic_lane_num), data64);
+	sl_core_lgrp_flush64(core_link->core_lgrp, SS2_PORT_PML_CFG_SERDES_TX(asic_lane_num));
+}
+
+int sl_core_hw_serdes_lanes_up(struct sl_core_link *core_link, bool is_autoneg)
+{
+	int           rtn;
+	unsigned long lane_map;
+	u8            serdes_lane_num;
+
+	lane_map = core_link->serdes.lane_map;
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"lanes up (lane_map = 0x%02lX, is_autoneg = %d)", lane_map, is_autoneg);
+
+	/* start */
+	for_each_set_bit(serdes_lane_num, &lane_map, SL_MAX_SERDES_LANES) {
+		sl_core_log_dbg(core_link, LOG_NAME, "lanes up (serdes_lane_num = %u)", serdes_lane_num);
+		rtn = sl_core_hw_serdes_lane_up_rx_setup(core_link, serdes_lane_num);
+		if (rtn) {
+			sl_core_log_err_trace(core_link, LOG_NAME, "lane_up_rx_setup failed [%d]", rtn);
+			sl_core_data_link_last_up_fail_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_SERDES_CONFIG_MAP);
+			goto out;
+		}
+		rtn = sl_core_hw_serdes_lane_up_tx_setup(core_link, serdes_lane_num, is_autoneg);
+		if (rtn) {
+			sl_core_log_err_trace(core_link, LOG_NAME, "lane_up_tx_setup failed [%d]", rtn);
+			sl_core_data_link_last_up_fail_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_SERDES_CONFIG_MAP);
+			goto out;
+		}
+		rtn = sl_core_hw_serdes_lane_up_rx_config(core_link, serdes_lane_num);
+		if (rtn) {
+			sl_core_log_err_trace(core_link, LOG_NAME, "lane_up_rx_config failed [%d]", rtn);
+			sl_core_data_link_last_up_fail_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_SERDES_CONFIG_MAP);
+			goto out;
+		}
+		rtn = sl_core_hw_serdes_lane_up_tx_config(core_link, serdes_lane_num);
+		if (rtn) {
+			sl_core_log_err_trace(core_link, LOG_NAME, "lane_up_tx_config failed [%d]", rtn);
+			sl_core_data_link_last_up_fail_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_SERDES_CONFIG_MAP);
+			goto out;
+		}
+		rtn = sl_core_hw_serdes_lane_up_rx_start(core_link, serdes_lane_num);
+		if (rtn) {
+			sl_core_log_err_trace(core_link, LOG_NAME, "lane_up_rx_start failed [%d]", rtn);
+			sl_core_data_link_last_up_fail_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_SERDES_CONFIG_MAP);
+			goto out;
+		}
+		rtn = sl_core_hw_serdes_lane_up_tx_start(core_link, serdes_lane_num);
+		if (rtn) {
+			sl_core_log_err_trace(core_link, LOG_NAME, "lane_up_tx_start failed [%d]", rtn);
+			sl_core_data_link_last_up_fail_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_SERDES_CONFIG_MAP);
+			goto out;
+		}
+	}
+
+	/* clock align */
+	for_each_set_bit(serdes_lane_num, &lane_map, SL_MAX_SERDES_LANES) {
+		rtn = sl_core_hw_serdes_lane_up_clock_align(core_link->core_lgrp, serdes_lane_num);
+		if (rtn) {
+			sl_core_log_err_trace(core_link, LOG_NAME, "lane_up_clock_align failed [%d]", rtn);
+			sl_core_data_link_last_up_fail_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_SERDES_CONFIG_MAP);
+			goto out;
+		}
+	}
+
+	if (!is_autoneg) {
+
+		sl_core_data_link_info_map_set(core_link, SL_CORE_INFO_MAP_SERDES_CHECK);
+
+		for_each_set_bit(serdes_lane_num, &lane_map, SL_MAX_SERDES_LANES) {
+			rtn = sl_core_hw_serdes_lane_up_tx_check(core_link, serdes_lane_num);
+			if (rtn) {
+				sl_core_log_err_trace(core_link, LOG_NAME, "lane_up_tx_check failed [%d]", rtn);
+				sl_core_data_link_last_up_fail_cause_map_set(core_link,
+									     SL_LINK_DOWN_CAUSE_SERDES_SIGNAL_MAP);
+				goto out;
+			}
+		}
+	}
+
+	/* sleep to give last lane time to settle */
+	msleep(20);
+
+	if (!is_autoneg) {
+		sl_core_hw_pcs_tx_start(core_link);
+
+		for_each_set_bit(serdes_lane_num, &lane_map, SL_MAX_SERDES_LANES)
+			sl_core_hw_pmd_tx_enable(core_link, serdes_lane_num);
+
+		for_each_set_bit(serdes_lane_num, &lane_map, SL_MAX_SERDES_LANES) {
+			rtn = sl_core_hw_serdes_lane_up_rx_check(core_link, serdes_lane_num);
+			if (rtn) {
+				sl_core_log_err_trace(core_link, LOG_NAME, "lane_up_rx_check failed [%d]", rtn);
+				sl_core_data_link_last_up_fail_cause_map_set(core_link,
+									     SL_LINK_DOWN_CAUSE_SERDES_SIGNAL_MAP);
+				goto out;
+			}
+		}
+
+		if (!is_flag_set(core_link->core_lgrp->config.options, SL_LGRP_CONFIG_OPT_SERDES_LOOPBACK_ENABLE)) {
+			sl_core_log_dbg(core_link, LOG_NAME, "loopback off so check quality");
+			for_each_set_bit(serdes_lane_num, &lane_map, SL_MAX_SERDES_LANES) {
+				rtn = sl_core_hw_serdes_lane_up_quality_check(core_link, serdes_lane_num);
+				if (rtn) {
+					sl_core_log_err_trace(core_link, LOG_NAME,
+							      "lane_up_quality_check failed [%d]", rtn);
+					sl_core_data_link_last_up_fail_cause_map_set(core_link,
+										     SL_LINK_DOWN_CAUSE_SERDES_QUALITY_MAP);
+					goto out;
+				}
+			}
+		}
+
+		sl_core_data_link_info_map_clr(core_link, SL_CORE_INFO_MAP_SERDES_CHECK);
+	}
+
+	/* up */
+	for_each_set_bit(serdes_lane_num, &lane_map, SL_MAX_SERDES_LANES) {
+		sl_core_hw_serdes_tx_lane_state_set(core_link->core_lgrp,
+						    sl_core_hw_serdes_tx_asic_lane_num_get(core_link, serdes_lane_num),
+			SL_CORE_HW_SERDES_LANE_STATE_UP);
+		sl_core_hw_serdes_rx_lane_state_set(core_link->core_lgrp,
+						    sl_core_hw_serdes_rx_asic_lane_num_get(core_link, serdes_lane_num),
+			SL_CORE_HW_SERDES_LANE_STATE_UP);
+	}
+
+	rtn = 0;
+out:
+	return rtn;
+}
+
+void sl_core_hw_serdes_lanes_down(struct sl_core_link *core_link)
+{
+	unsigned long lane_map;
+	u8            serdes_lane_num;
+
+	lane_map = core_link->serdes.lane_map;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "lanes down (lane_map = 0x%02lX)", lane_map);
+
+	for_each_set_bit(serdes_lane_num, &lane_map, SL_MAX_SERDES_LANES) {
+		sl_core_hw_serdes_lane_down_tx_stop(core_link, serdes_lane_num);
+		sl_core_hw_serdes_lane_down_rx_stop(core_link, serdes_lane_num);
+	}
+
+	for_each_set_bit(serdes_lane_num, &lane_map, SL_MAX_SERDES_LANES) {
+		sl_core_hw_serdes_tx_lane_state_set(core_link->core_lgrp,
+						    sl_core_hw_serdes_tx_asic_lane_num_get(core_link, serdes_lane_num),
+			SL_CORE_HW_SERDES_LANE_STATE_DOWN);
+		sl_core_hw_serdes_rx_lane_state_set(core_link->core_lgrp,
+						    sl_core_hw_serdes_rx_asic_lane_num_get(core_link, serdes_lane_num),
+			SL_CORE_HW_SERDES_LANE_STATE_DOWN);
+	}
+}
+
+void sl_core_hw_serdes_degraded_lanes_state_set(struct sl_core_link *core_link, u8 tx_degrade_map, u8 rx_degrade_map)
+{
+	u8            tx_asic_lane_num;
+	u8            rx_asic_lane_num;
+	unsigned long tx_degrade_lane_map_ul;
+	unsigned long rx_degrade_lane_map_ul;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "degraded lanes state set (tx_degrade_map = 0x%X, rx_degrade_map = 0x%X)",
+			tx_degrade_map, rx_degrade_map);
+
+	tx_degrade_lane_map_ul = (unsigned long)tx_degrade_map ^ 0x0F;
+	rx_degrade_lane_map_ul = (unsigned long)rx_degrade_map ^ 0x0F;
+
+	for_each_set_bit(tx_asic_lane_num, &tx_degrade_lane_map_ul, SL_MAX_SERDES_LANES)
+		sl_core_hw_serdes_tx_lane_state_set(core_link->core_lgrp, tx_asic_lane_num,
+						    SL_CORE_HW_SERDES_LANE_STATE_DEGRADED);
+
+	for_each_set_bit(rx_asic_lane_num, &rx_degrade_lane_map_ul, SL_MAX_SERDES_LANES)
+		sl_core_hw_serdes_rx_lane_state_set(core_link->core_lgrp, rx_asic_lane_num,
+						    SL_CORE_HW_SERDES_LANE_STATE_DEGRADED);
+}
+
+int sl_core_hw_serdes_lanes_up_prbs(struct sl_core_link *core_link, u8 tx_degrade_map, u8 rx_degrade_map)
+{
+	int           rtn;
+	u8            tx_asic_lane_num;
+	u8            tx_serdes_lane_num;
+	u8            rx_asic_lane_num;
+	u8            rx_serdes_lane_num;
+	unsigned long tx_degrade_lane_map_ul;
+	unsigned long rx_degrade_lane_map_ul;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "lanes up prbs (tx_degrade_map = 0x%X, rx_degrade_map = 0x%X)",
+			tx_degrade_map, rx_degrade_map);
+
+	tx_degrade_lane_map_ul = (unsigned long)tx_degrade_map ^ 0x0F;
+	rx_degrade_lane_map_ul = (unsigned long)rx_degrade_map ^ 0x0F;
+
+	for_each_set_bit(tx_asic_lane_num, &tx_degrade_lane_map_ul, SL_MAX_SERDES_LANES) {
+
+		tx_serdes_lane_num = sl_core_hw_serdes_tx_serdes_lane_num_get(core_link->core_lgrp, tx_asic_lane_num);
+
+		rtn = sl_core_hw_serdes_lane_tx_prbs_config(core_link, tx_serdes_lane_num);
+		if (rtn) {
+			sl_core_log_err_trace(core_link, LOG_NAME, "prbs config failed [%d] (asic_lane = %u, serdes_lane = %u)",
+					      rtn, tx_asic_lane_num, tx_serdes_lane_num);
+			return rtn;
+		}
+
+		rtn = sl_core_hw_serdes_lane_tx_prbs_enable(core_link, tx_serdes_lane_num);
+		if (rtn) {
+			sl_core_log_err_trace(core_link, LOG_NAME, "prbs enable failed [%d] (asic_lane = %u, serdes_lane = %u)",
+					      rtn, tx_asic_lane_num, tx_serdes_lane_num);
+			return rtn;
+		}
+
+		rtn = sl_core_hw_serdes_lane_tx_prbs_shrd_patt_gen_disable(core_link, tx_serdes_lane_num);
+		if (rtn) {
+			sl_core_log_err_trace(core_link, LOG_NAME,
+					      "prbs shared pattern gen disable failed [%d] (asic_lane = %u, serdes_lane = %u)",
+					      rtn, tx_asic_lane_num, tx_serdes_lane_num);
+			return rtn;
+		}
+
+		rtn = sl_core_hw_serdes_lane_tx_prbs_remote_loopback_disable(core_link, tx_serdes_lane_num);
+		if (rtn) {
+			sl_core_log_err_trace(core_link, LOG_NAME,
+					      "prbs remote loopback disable failed [%d] (asic_lane = %u, serdes_lane = %u)",
+					      rtn, tx_asic_lane_num, tx_serdes_lane_num);
+			return rtn;
+		}
+
+		rtn = sl_core_hw_serdes_lane_tx_prbs_checker_enable(core_link, tx_serdes_lane_num);
+		if (rtn) {
+			sl_core_log_err_trace(core_link, LOG_NAME,
+					      "prbs checker enable failed [%d] (asic_lane = %u, serdes_lane = %u)",
+					      rtn, tx_asic_lane_num, tx_serdes_lane_num);
+			return rtn;
+		}
+	}
+
+	/* sleep to give last lane time to settle */
+	msleep(20);
+
+	for_each_set_bit(rx_asic_lane_num, &rx_degrade_lane_map_ul, SL_MAX_SERDES_LANES) {
+
+		rx_serdes_lane_num = sl_core_hw_serdes_rx_serdes_lane_num_get(core_link->core_lgrp, rx_asic_lane_num);
+
+		rtn = sl_core_hw_serdes_lane_up_quality_check(core_link, rx_serdes_lane_num);
+		if (rtn) {
+			sl_core_log_err_trace(core_link, LOG_NAME, "lane_up_quality_check failed [%d] (rx_serdes_lane_num = %u)",
+					      rtn, rx_serdes_lane_num);
+			return rtn;
+		}
+	}
+
+	return 0;
+}
+
+int sl_core_hw_serdes_eye_upper_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, u8 *eye_upper)
+{
+	int rtn;
+	u32 addr;
+	u8  serdes_lane_num;
+
+	if (!sl_core_ldev_serdes_is_ready(core_lgrp->core_ldev))
+		return -EIO;
+
+	serdes_lane_num = sl_core_hw_serdes_rx_serdes_lane_num_get(core_lgrp, asic_lane_num);
+
+	addr = SL_CORE_HW_SERDES_LANE_ADDR(0x7, serdes_lane_num, core_lgrp);
+
+	SL_CORE_HW_UC_RAM_RD8(core_lgrp, core_lgrp->serdes.dt.dev_addr,
+			      core_lgrp->serdes.dt.dev_id, serdes_lane_num, addr, eye_upper);
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME,
+			"eye upper get (serdes_lane_num = %u, asic_lane_num = %u, eye_upper = %u)",
+		serdes_lane_num, asic_lane_num, *eye_upper);
+
+	rtn = 0;
+
+out:
+	return rtn;
+}
+
+int sl_core_hw_serdes_eye_lower_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, u8 *eye_lower)
+{
+	int rtn;
+	u32 addr;
+	u8  serdes_lane_num;
+
+	if (!sl_core_ldev_serdes_is_ready(core_lgrp->core_ldev))
+		return -EIO;
+
+	serdes_lane_num = sl_core_hw_serdes_rx_serdes_lane_num_get(core_lgrp, asic_lane_num);
+
+	addr = SL_CORE_HW_SERDES_LANE_ADDR(0x8, serdes_lane_num, core_lgrp);
+
+	SL_CORE_HW_UC_RAM_RD8(core_lgrp, core_lgrp->serdes.dt.dev_addr,
+			      core_lgrp->serdes.dt.dev_id, serdes_lane_num, addr, eye_lower);
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME,
+			"eye lower get (serdes_lane_num = %u, asic_lane_num = %u, eye_lower = %u)",
+		serdes_lane_num, asic_lane_num, *eye_lower);
+
+	rtn = 0;
+
+out:
+	return rtn;
+}
+
+void sl_core_hw_serdes_tx_lane_state_set(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, u32 state)
+{
+	sl_core_log_dbg(core_lgrp, LOG_NAME,
+			"tx lane state set (asic_lane_num = %u, state = %u %s)",
+		asic_lane_num, state, sl_core_serdes_lane_state_str(state));
+
+	spin_lock(&core_lgrp->data_lock);
+	core_lgrp->serdes.lane_state[asic_lane_num].tx = state;
+	spin_unlock(&core_lgrp->data_lock);
+}
+
+int sl_core_hw_serdes_tx_lane_state_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, u32 *state)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*state = core_lgrp->serdes.lane_state[asic_lane_num].tx;
+	spin_unlock(&core_lgrp->data_lock);
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME,
+			"tx lane state get (asic_lane_num = %u, state = %u %s)",
+		asic_lane_num, *state, sl_core_serdes_lane_state_str(*state));
+
+	return 0;
+}
+
+void sl_core_hw_serdes_rx_lane_state_set(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, u32 state)
+{
+	sl_core_log_dbg(core_lgrp, LOG_NAME,
+			"rx lane state set (asic_lane_num = %u, state = %u %s)",
+		asic_lane_num, state, sl_core_serdes_lane_state_str(state));
+
+	spin_lock(&core_lgrp->data_lock);
+	core_lgrp->serdes.lane_state[asic_lane_num].rx = state;
+	spin_unlock(&core_lgrp->data_lock);
+}
+
+int sl_core_hw_serdes_rx_lane_state_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, u32 *state)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*state = core_lgrp->serdes.lane_state[asic_lane_num].rx;
+	spin_unlock(&core_lgrp->data_lock);
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME,
+			"rx lane state get (asic_lane_num = %u, state = %u %s)",
+		asic_lane_num, *state, sl_core_serdes_lane_state_str(*state));
+
+	return 0;
+}
+
+int sl_core_hw_serdes_tx_lane_is_lol(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, bool *is_tx_lol)
+{
+	int                         rtn;
+	u8                          serdes_lane_map;
+	struct sl_media_jack_signal media_signal;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "tx lane is lol (asic_lane_num = %u)", asic_lane_num);
+
+	serdes_lane_map = BIT(sl_core_hw_serdes_tx_serdes_lane_num_get(core_lgrp, asic_lane_num));
+
+	rtn = sl_media_jack_signal_cache_get(core_lgrp->core_ldev->num, core_lgrp->num,
+					     serdes_lane_map, &media_signal);
+	if (rtn) {
+		sl_core_log_err_trace(core_lgrp, LOG_NAME, "signal cache get failed [%d]", rtn);
+		return rtn;
+	}
+
+	*is_tx_lol = media_signal.tx.lol_map & serdes_lane_map;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "tx lane lol check (is_tx_lol = %s)", *is_tx_lol ? "yes" : "no");
+
+	return 0;
+}
+
+int sl_core_hw_serdes_rx_lane_is_lol(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, bool *is_rx_lol)
+{
+	int                         rtn;
+	u8                          serdes_lane_map;
+	struct sl_media_jack_signal media_signal;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "rx lane is lol (asic_lane_num = %u)", asic_lane_num);
+
+	serdes_lane_map = BIT(sl_core_hw_serdes_rx_serdes_lane_num_get(core_lgrp, asic_lane_num));
+
+	rtn = sl_media_jack_signal_cache_get(core_lgrp->core_ldev->num, core_lgrp->num,
+					     serdes_lane_map, &media_signal);
+	if (rtn) {
+		sl_core_log_err_trace(core_lgrp, LOG_NAME, "signal cache get failed [%d]", rtn);
+		return rtn;
+	}
+
+	*is_rx_lol = media_signal.rx.lol_map & serdes_lane_map;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "rx lane lol check (is_rx_lol = %s)", *is_rx_lol ? "yes" : "no");
+
+	return 0;
+}
+
+int sl_core_hw_serdes_tx_lane_is_los(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, bool *is_tx_los)
+{
+	int                         rtn;
+	u8                          serdes_lane_map;
+	struct sl_media_jack_signal media_signal;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "tx lane is los (asic_lane_num = %u)", asic_lane_num);
+
+	serdes_lane_map = BIT(sl_core_hw_serdes_tx_serdes_lane_num_get(core_lgrp, asic_lane_num));
+
+	rtn = sl_media_jack_signal_cache_get(core_lgrp->core_ldev->num, core_lgrp->num,
+					     serdes_lane_map, &media_signal);
+	if (rtn) {
+		sl_core_log_err_trace(core_lgrp, LOG_NAME, "signal cache get failed [%d]", rtn);
+		return rtn;
+	}
+
+	*is_tx_los = media_signal.tx.los_map & serdes_lane_map;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "tx lane los check (is_tx_los = %s)", *is_tx_los ? "yes" : "no");
+
+	return 0;
+}
+
+int sl_core_hw_serdes_rx_lane_is_los(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, bool *is_rx_los)
+{
+	int                         rtn;
+	u8                          serdes_lane_map;
+	struct sl_media_jack_signal media_signal;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "rx lane is los (asic_lane_num = %u)", asic_lane_num);
+
+	serdes_lane_map = BIT(sl_core_hw_serdes_rx_serdes_lane_num_get(core_lgrp, asic_lane_num));
+
+	rtn = sl_media_jack_signal_cache_get(core_lgrp->core_ldev->num, core_lgrp->num,
+					     serdes_lane_map, &media_signal);
+	if (rtn) {
+		sl_core_log_err_trace(core_lgrp, LOG_NAME, "signal cache get failed [%d]", rtn);
+		return rtn;
+	}
+
+	*is_rx_los = media_signal.rx.los_map & serdes_lane_map;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "rx lane los check (is_rx_los = %s)", *is_rx_los ? "yes" : "no");
+
+	return 0;
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes_lane_rx.c b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes_lane_rx.c
new file mode 100644
index 000000000000..1999c4f8a396
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes_lane_rx.c
@@ -0,0 +1,241 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2024,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/delay.h>
+
+#include "sl_core_lgrp.h"
+#include "base/sl_core_log.h"
+#include "hw/sl_core_hw_serdes_lane.h"
+#include "hw/sl_core_hw_io.h"
+#include "hw/sl_core_hw_pmi.h"
+#include "data/sl_core_data_link.h"
+#include "hw/sl_core_hw_serdes_addrs.h"
+
+#define LOG_NAME SL_CORE_SERDES_LOG_NAME
+
+int sl_core_hw_serdes_lane_up_rx_setup(struct sl_core_link *core_link, u8 serdes_lane_num)
+{
+	int                  rtn;
+	u64                  data64;
+	u32                  port;
+	u8                   asic_lane_num;
+	struct sl_core_lgrp *core_lgrp;
+
+	core_lgrp     = core_link->core_lgrp;
+	port          = core_lgrp->num;
+	asic_lane_num = sl_core_hw_serdes_rx_asic_lane_num_get(core_link, serdes_lane_num);
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME,
+			"lane up rx setup (port = %u, serdes_lane_num = %u, asic_lane_num = %u)",
+		port, serdes_lane_num, asic_lane_num);
+
+	sl_core_hw_serdes_rx_lane_state_set(core_lgrp,
+					    asic_lane_num, SL_CORE_HW_SERDES_LANE_STATE_SETUP);
+
+	/* clock gate */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  core_lgrp->core_ldev->serdes.addrs[SERDES_RX_CKRST_CTRL_RX_CLOCK_N_RESET_DEBUG_CONTROL],
+		0x0000, 0x0010); /* rx_clk_vld_frc_val */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  core_lgrp->core_ldev->serdes.addrs[SERDES_RX_CKRST_CTRL_RX_CLOCK_N_RESET_DEBUG_CONTROL],
+		0x0000, 0x0008); /* rx_clk_vld_frc */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  core_lgrp->core_ldev->serdes.addrs[SERDES_RX_CKRST_CTRL_RX_CLOCK_N_RESET_DEBUG_CONTROL],
+		0x0000, 0x0001); /* rx_s_clkgate_frc_on */
+
+	/* power on */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  core_lgrp->core_ldev->serdes.addrs[SERDES_RX_CKRST_CTRL_RX_LANE_CLK_RESET_N_POWERDOWN_CONTROL],
+		0x0000, 0x0001); /* rx_s_pwrdn */
+
+	usleep_range(10000, 20000); /* avoid power surge */
+
+	sl_core_lgrp_read64(core_lgrp, SS2_PORT_PML_CFG_SERDES_RX(asic_lane_num), &data64);
+	data64 = SS2_PORT_PML_CFG_SERDES_RX_PMD_LN_RX_H_PWRDN_UPDATE(data64, 0); /* active high */
+	sl_core_lgrp_write64(core_lgrp, SS2_PORT_PML_CFG_SERDES_RX(asic_lane_num), data64);
+	sl_core_lgrp_flush64(core_lgrp, SS2_PORT_PML_CFG_SERDES_RX(asic_lane_num));
+
+	/* disable DP */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  core_lgrp->core_ldev->serdes.addrs[SERDES_RXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL],
+		0x0000, 0x0001); /* RX_LN_DP_EN */
+
+	/* assert DP reset */
+	sl_core_lgrp_read64(core_lgrp, SS2_PORT_PML_CFG_SERDES_RX(asic_lane_num), &data64);
+	data64 = SS2_PORT_PML_CFG_SERDES_RX_PMD_LN_RX_DP_H_RSTB_UPDATE(data64, 0); /* active low */
+	sl_core_lgrp_write64(core_lgrp, SS2_PORT_PML_CFG_SERDES_RX(asic_lane_num), data64);
+	sl_core_lgrp_flush64(core_lgrp, SS2_PORT_PML_CFG_SERDES_RX(asic_lane_num));
+
+	/* toggle reset */
+	sl_core_lgrp_read64(core_lgrp, SS2_PORT_PML_CFG_SERDES_RX(asic_lane_num), &data64);
+	data64 = SS2_PORT_PML_CFG_SERDES_RX_PMD_LN_RX_H_RSTB_UPDATE(data64, 0); /* active low */
+	sl_core_lgrp_write64(core_lgrp, SS2_PORT_PML_CFG_SERDES_RX(asic_lane_num), data64);
+	sl_core_lgrp_flush64(core_lgrp, SS2_PORT_PML_CFG_SERDES_RX(asic_lane_num));
+	usleep_range(10, 20);
+	sl_core_lgrp_read64(core_lgrp, SS2_PORT_PML_CFG_SERDES_RX(asic_lane_num), &data64);
+	data64 = SS2_PORT_PML_CFG_SERDES_RX_PMD_LN_RX_H_RSTB_UPDATE(data64, 1); /* active low */
+	sl_core_lgrp_write64(core_lgrp, SS2_PORT_PML_CFG_SERDES_RX(asic_lane_num), data64);
+	sl_core_lgrp_flush64(core_lgrp, SS2_PORT_PML_CFG_SERDES_RX(asic_lane_num));
+
+	rtn = 0;
+out:
+	return rtn;
+}
+
+int sl_core_hw_serdes_lane_up_rx_config(struct sl_core_link *core_link, u8 serdes_lane_num)
+{
+	int                  rtn;
+	u64                  data64;
+	u32                  port;
+	u8                   asic_lane_num;
+	struct sl_core_lgrp *core_lgrp;
+
+	core_lgrp     = core_link->core_lgrp;
+	port          = core_lgrp->num;
+	asic_lane_num = sl_core_hw_serdes_rx_asic_lane_num_get(core_link, serdes_lane_num);
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME,
+			"lane up rx config (port = %u, serdes_lane_num = %u, asic_lane_num = %u, hpe_map = 0x%X)",
+		port, serdes_lane_num, asic_lane_num,
+		core_link->core_lgrp->link_caps[core_link->num].hpe_map);
+
+	sl_core_hw_serdes_rx_lane_state_set(core_lgrp,
+					    asic_lane_num, SL_CORE_HW_SERDES_LANE_STATE_CONFIG);
+
+	/* OSR */
+	sl_core_lgrp_read64(core_lgrp, SS2_PORT_PML_CFG_SERDES_RX(asic_lane_num), &data64);
+	data64 = SS2_PORT_PML_CFG_SERDES_RX_PMD_RX_OSR_MODE_UPDATE(data64,
+								   sl_core_hw_serdes_mode(core_lgrp, &(core_link->serdes.core_serdes_settings)));
+	sl_core_lgrp_write64(core_lgrp, SS2_PORT_PML_CFG_SERDES_RX(asic_lane_num), data64);
+	sl_core_lgrp_flush64(core_lgrp, SS2_PORT_PML_CFG_SERDES_RX(asic_lane_num));
+
+	/* fw cfg */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  core_lgrp->core_ldev->serdes.addrs[SERDES_FW_API_DATA0],
+		sl_core_hw_serdes_config(core_lgrp,
+					 &(core_link->serdes.core_serdes_settings), &(core_link->serdes.media_serdes_settings)),
+		0xFFFF); /* LANE_CFG_FWAPI_DATA0 */
+
+	/* invert */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  core_lgrp->core_ldev->serdes.addrs[SERDES_RX_MISC_CONFIG],
+		core_lgrp->serdes.dt.lane_info[asic_lane_num].rx_invert, 0x0001); /* RX_PMD_DP_INVERT */
+
+	/* link training */
+	if (is_flag_set(core_link->core_lgrp->link_caps[core_link->num].hpe_map, SL_LINK_CONFIG_HPE_LINKTRAIN)) {
+		sl_core_log_dbg(core_lgrp, LOG_NAME,
+				"lane up rx config link train on (logical = %u)", serdes_lane_num);
+		SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+				  core_lgrp->core_ldev->serdes.addrs[SERDES_LINKTRN_IEEE_TX_LINKTRNIT_BASE_R_PMD_CONTROL],
+			0x0002, 0x0002); /* linktrn_ieee_training_enable */
+	} else {
+		sl_core_log_dbg(core_lgrp, LOG_NAME,
+				"lane up rx config link train off (logical = %u)", serdes_lane_num);
+		SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+				  core_lgrp->core_ldev->serdes.addrs[SERDES_LINKTRN_IEEE_TX_LINKTRNIT_BASE_R_PMD_CONTROL],
+			0x0000, 0x0002); /* linktrn_ieee_training_enable */
+	}
+
+	/* digital loopback */
+	if (is_flag_set(core_link->core_lgrp->config.options, SL_LGRP_CONFIG_OPT_SERDES_LOOPBACK_ENABLE)) {
+		sl_core_log_dbg(core_lgrp, LOG_NAME,
+				"lane up rx config loopback on (logical = %u)", serdes_lane_num);
+		SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+				  core_lgrp->core_ldev->serdes.addrs[SERDES_TLB_RX_DIG_LPBK_CONFIG],
+			0x0001, 0x0001); /* DIG_LPBK_EN */
+		sl_core_data_link_info_map_set(core_link, SL_CORE_INFO_MAP_SERDES_LOOPBACK_ON);
+	} else {
+		sl_core_log_dbg(core_lgrp, LOG_NAME,
+				"lane up rx config loopback off (logical = %u)", serdes_lane_num);
+		SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+				  core_lgrp->core_ldev->serdes.addrs[SERDES_TLB_RX_DIG_LPBK_CONFIG],
+			0x0000, 0x0001); /* DIG_LPBK_EN */
+		sl_core_data_link_info_map_clr(core_link, SL_CORE_INFO_MAP_SERDES_LOOPBACK_ON);
+	}
+
+	rtn = 0;
+out:
+	return rtn;
+}
+
+int sl_core_hw_serdes_lane_up_rx_start(struct sl_core_link *core_link, u8 serdes_lane_num)
+{
+	int                  rtn;
+	u64                  data64;
+	u32                  port;
+	u8                   asic_lane_num;
+	struct sl_core_lgrp *core_lgrp;
+
+	core_lgrp     = core_link->core_lgrp;
+	port          = core_lgrp->num;
+	asic_lane_num = sl_core_hw_serdes_rx_asic_lane_num_get(core_link, serdes_lane_num);
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME,
+			"lane up rx start (port = %u, serdes_lane_num = %u, asic_lane_num = %u)",
+		port, serdes_lane_num, asic_lane_num);
+
+	sl_core_hw_serdes_rx_lane_state_set(core_lgrp,
+					    asic_lane_num, SL_CORE_HW_SERDES_LANE_STATE_START);
+
+	/* enable DP */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  core_lgrp->core_ldev->serdes.addrs[SERDES_RXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL],
+		0x0001, 0x0001); /* RX_LN_DP_EN */
+
+	/* release DP reset */
+	sl_core_lgrp_read64(core_lgrp, SS2_PORT_PML_CFG_SERDES_RX(asic_lane_num), &data64);
+	data64 = SS2_PORT_PML_CFG_SERDES_RX_PMD_LN_RX_DP_H_RSTB_UPDATE(data64, 1); /* active low */
+	sl_core_lgrp_write64(core_lgrp, SS2_PORT_PML_CFG_SERDES_RX(asic_lane_num), data64);
+	sl_core_lgrp_flush64(core_lgrp, SS2_PORT_PML_CFG_SERDES_RX(asic_lane_num));
+
+	rtn = 0;
+out:
+	return rtn;
+}
+
+void sl_core_hw_serdes_lane_down_rx_stop(struct sl_core_link *core_link, u8 serdes_lane_num)
+{
+	int                  rtn;
+	u64                  data64;
+	u32                  port;
+	u8                   asic_lane_num;
+	struct sl_core_lgrp *core_lgrp;
+
+	core_lgrp     = core_link->core_lgrp;
+	port          = core_lgrp->num;
+	asic_lane_num = sl_core_hw_serdes_rx_asic_lane_num_get(core_link, serdes_lane_num);
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME,
+			"lane down rx stop (port = %u, serdes_lane_num = %u, asic_lane_num = %u)",
+		port, serdes_lane_num, asic_lane_num);
+
+	sl_core_hw_serdes_rx_lane_state_set(core_lgrp,
+					    asic_lane_num, SL_CORE_HW_SERDES_LANE_STATE_STOP);
+
+	/* disable DP */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  core_lgrp->core_ldev->serdes.addrs[SERDES_RXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL],
+		0x0000, 0x0001); /* RX_LN_DP_EN */
+
+	/* assert DP reset */
+	sl_core_lgrp_read64(core_lgrp, SS2_PORT_PML_CFG_SERDES_RX(asic_lane_num), &data64);
+	data64 = SS2_PORT_PML_CFG_SERDES_RX_PMD_LN_RX_DP_H_RSTB_UPDATE(data64, 0); /* active low */
+	sl_core_lgrp_write64(core_lgrp, SS2_PORT_PML_CFG_SERDES_RX(asic_lane_num), data64);
+	sl_core_lgrp_flush64(core_lgrp, SS2_PORT_PML_CFG_SERDES_RX(asic_lane_num));
+
+	/* power down */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  core_lgrp->core_ldev->serdes.addrs[SERDES_RX_CKRST_CTRL_RX_LANE_CLK_RESET_N_POWERDOWN_CONTROL],
+		0x0001, 0x0001); /* rx_s_pwrdn */
+
+	usleep_range(10000, 20000); /* avoid power surge */
+
+	/* clear the config */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  core_lgrp->core_ldev->serdes.addrs[SERDES_FW_API_DATA0],
+		0x0000, 0xFFFF); /* LANE_CFG_FWAPI_DATA0 */
+
+out:
+	return;
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes_lane_tx.c b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes_lane_tx.c
new file mode 100644
index 000000000000..57e40566b61a
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes_lane_tx.c
@@ -0,0 +1,394 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2024,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/delay.h>
+
+#include "sl_core_lgrp.h"
+#include "sl_core_link.h"
+#include "base/sl_core_log.h"
+#include "hw/sl_core_hw_serdes_lane.h"
+#include "hw/sl_core_hw_io.h"
+#include "hw/sl_core_hw_pmi.h"
+#include "hw/sl_core_hw_serdes_addrs.h"
+
+#define LOG_NAME SL_CORE_SERDES_LOG_NAME
+
+int sl_core_hw_serdes_lane_up_tx_setup(struct sl_core_link *core_link, u8 serdes_lane_num, bool is_autoneg)
+{
+	int                  rtn;
+	u64                  data64;
+	u32                  port;
+	u8                   asic_lane_num;
+	struct sl_core_lgrp *core_lgrp;
+
+	core_lgrp     = core_link->core_lgrp;
+	port          = core_lgrp->num;
+	asic_lane_num = sl_core_hw_serdes_tx_asic_lane_num_get(core_link, serdes_lane_num);
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME,
+			"lane up tx setup (port = %u, serdes_lane_num = %u, asic_lane_num = %u, is_autoneg = %d)",
+		port, serdes_lane_num, asic_lane_num, is_autoneg);
+
+	sl_core_hw_serdes_tx_lane_state_set(core_lgrp,
+					    asic_lane_num, SL_CORE_HW_SERDES_LANE_STATE_SETUP);
+
+	/* clock gate */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  core_lgrp->core_ldev->serdes.addrs[SERDES_TX_CKRST_CTRL_TX_CLOCK_N_RESET_DEBUG_CONTROL],
+		0x0000, 0x0010); /* tx_clk_vld_frc_val */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  core_lgrp->core_ldev->serdes.addrs[SERDES_TX_CKRST_CTRL_TX_CLOCK_N_RESET_DEBUG_CONTROL],
+		0x0000, 0x0008); /* tx_clk_vld_frc */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  core_lgrp->core_ldev->serdes.addrs[SERDES_TX_CKRST_CTRL_TX_CLOCK_N_RESET_DEBUG_CONTROL],
+		0x0000, 0x0001); /* tx_s_clkgate_frc_on */
+
+	/* power on */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  core_lgrp->core_ldev->serdes.addrs[SERDES_TX_CKRST_CTRL_TX_LANE_CLK_RESET_N_POWERDOWN_CONTROL],
+		0x0000, 0x0001); /* tx_s_pwrdn */
+
+	usleep_range(10000, 20000); /* avoid power surge */
+
+	sl_core_lgrp_read64(core_lgrp, SS2_PORT_PML_CFG_SERDES_TX(asic_lane_num), &data64);
+	data64 = SS2_PORT_PML_CFG_SERDES_TX_PMD_LN_TX_H_PWRDN_UPDATE(data64, 0); /* active high */
+	sl_core_lgrp_write64(core_lgrp, SS2_PORT_PML_CFG_SERDES_TX(asic_lane_num), data64);
+	sl_core_lgrp_flush64(core_lgrp, SS2_PORT_PML_CFG_SERDES_TX(asic_lane_num));
+	sl_core_lgrp_read64(core_lgrp, SS2_PORT_PML_CFG_SERDES_TX(asic_lane_num), &data64);
+	if (is_autoneg)
+		data64 = SS2_PORT_PML_CFG_SERDES_TX_PMD_TX_DISABLE_UPDATE(data64, 0);
+	else
+		data64 = SS2_PORT_PML_CFG_SERDES_TX_PMD_TX_DISABLE_UPDATE(data64, 1);
+	sl_core_lgrp_write64(core_lgrp, SS2_PORT_PML_CFG_SERDES_TX(asic_lane_num), data64);
+	sl_core_lgrp_flush64(core_lgrp, SS2_PORT_PML_CFG_SERDES_TX(asic_lane_num));
+
+	/* disable TX */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  core_lgrp->core_ldev->serdes.addrs[SERDES_TX_FED_TXFIR_MISC_CONTROL0],
+		0x0001, 0x0001); /* sdk_tx_disable */
+
+	/* disable DP */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  core_lgrp->core_ldev->serdes.addrs[SERDES_TXCOM_CKRST_CTRL_TXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL],
+		0x0000, 0x0001); /* TX_LN_DP_EN */
+
+	/* assert DP reset */
+	sl_core_lgrp_read64(core_lgrp, SS2_PORT_PML_CFG_SERDES_TX(asic_lane_num), &data64);
+	data64 = SS2_PORT_PML_CFG_SERDES_TX_PMD_LN_TX_DP_H_RSTB_UPDATE(data64, 0); /* active low */
+	sl_core_lgrp_write64(core_lgrp, SS2_PORT_PML_CFG_SERDES_TX(asic_lane_num), data64);
+	sl_core_lgrp_flush64(core_lgrp, SS2_PORT_PML_CFG_SERDES_TX(asic_lane_num));
+
+	/* toggle reset */
+	sl_core_lgrp_read64(core_lgrp, SS2_PORT_PML_CFG_SERDES_TX(asic_lane_num), &data64);
+	data64 = SS2_PORT_PML_CFG_SERDES_TX_PMD_LN_TX_H_RSTB_UPDATE(data64, 0); /* active low */
+	sl_core_lgrp_write64(core_lgrp, SS2_PORT_PML_CFG_SERDES_TX(asic_lane_num), data64);
+	sl_core_lgrp_flush64(core_lgrp, SS2_PORT_PML_CFG_SERDES_TX(asic_lane_num));
+	usleep_range(10, 20);
+	sl_core_lgrp_read64(core_lgrp, SS2_PORT_PML_CFG_SERDES_TX(asic_lane_num), &data64);
+	data64 = SS2_PORT_PML_CFG_SERDES_TX_PMD_LN_TX_H_RSTB_UPDATE(data64, 1); /* active low */
+	sl_core_lgrp_write64(core_lgrp, SS2_PORT_PML_CFG_SERDES_TX(asic_lane_num), data64);
+	sl_core_lgrp_flush64(core_lgrp, SS2_PORT_PML_CFG_SERDES_TX(asic_lane_num));
+
+	rtn = 0;
+out:
+	return rtn;
+}
+
+int sl_core_hw_serdes_lane_up_tx_config(struct sl_core_link *core_link, u8 serdes_lane_num)
+{
+	int                  rtn;
+	u64                  data64;
+	u32                  port;
+	u8                   asic_lane_num;
+	struct sl_core_lgrp *core_lgrp;
+	u16                 *addrs;
+
+	core_lgrp     = core_link->core_lgrp;
+	port          = core_lgrp->num;
+	asic_lane_num = sl_core_hw_serdes_tx_asic_lane_num_get(core_link, serdes_lane_num);
+	addrs         = core_lgrp->core_ldev->serdes.addrs;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME,
+			"lane up tx config (port = %u, serdes_lane_num = %u, asic_lane_num = %u, hpe_map = 0x%X)",
+		port, serdes_lane_num, asic_lane_num,
+		core_link->core_lgrp->link_caps[core_link->num].hpe_map);
+
+	sl_core_hw_serdes_tx_lane_state_set(core_lgrp,
+					    asic_lane_num, SL_CORE_HW_SERDES_LANE_STATE_CONFIG);
+
+	/* OSR */
+	sl_core_lgrp_read64(core_lgrp, SS2_PORT_PML_CFG_SERDES_TX(asic_lane_num), &data64);
+	data64 = SS2_PORT_PML_CFG_SERDES_TX_PMD_TX_OSR_MODE_UPDATE(data64,
+								   sl_core_hw_serdes_mode(core_lgrp, &(core_link->serdes.core_serdes_settings)));
+	sl_core_lgrp_write64(core_lgrp, SS2_PORT_PML_CFG_SERDES_TX(asic_lane_num), data64);
+	sl_core_lgrp_flush64(core_lgrp, SS2_PORT_PML_CFG_SERDES_TX(asic_lane_num));
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME,
+			"lane up tx config (pre3 = %d, pre2 = %d, pre1 = %d, cursor = %d, post1 = %d, post2 = %d)",
+		core_link->serdes.media_serdes_settings.pre3, core_link->serdes.media_serdes_settings.pre2,
+		core_link->serdes.media_serdes_settings.pre1, core_link->serdes.media_serdes_settings.cursor,
+		core_link->serdes.media_serdes_settings.post1, core_link->serdes.media_serdes_settings.post2);
+
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  addrs[SERDES_TLB_TX_TLB_TX_PAM4_CONFIG_0],
+		0x0000, 0x0002); /* PAM4_PRECODER_EN */
+
+	/* pre3 */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  addrs[SERDES_TX_FED_TXFIR_TAP_CONTROL0],
+		core_link->serdes.media_serdes_settings.pre3, 0x01FF);
+	/* pre2 */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  addrs[SERDES_TX_FED_TXFIR_TAP_CONTROL1],
+		core_link->serdes.media_serdes_settings.pre2, 0x01FF);
+	/* pre1 */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  addrs[SERDES_TX_FED_TXFIR_TAP_CONTROL2],
+		core_link->serdes.media_serdes_settings.pre1, 0x01FF);
+	/* cursor */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  addrs[SERDES_TX_FED_TXFIR_TAP_CONTROL3],
+		core_link->serdes.media_serdes_settings.cursor, 0x01FF);
+	/* post 1 */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  addrs[SERDES_TX_FED_TXFIR_TAP_CONTROL4],
+		core_link->serdes.media_serdes_settings.post1, 0x01FF);
+	/* post 2 */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  addrs[SERDES_TX_FED_TXFIR_TAP_CONTROL5],
+		core_link->serdes.media_serdes_settings.post2, 0x01FF);
+	/* tap enable */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  addrs[SERDES_TX_FED_TXFIR_TAP_CONTROL0], 0x1000, 0x7000);
+	/* load coefficients */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  addrs[SERDES_TX_FED_TXFIR_TAP_CONTROL0], 0x0800, 0x0800); /* TXFIR_TAP_LOAD */
+
+	/* invert */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  addrs[SERDES_TLB_TX_TXMISC_CONFIG],
+		core_lgrp->serdes.dt.lane_info[asic_lane_num].tx_invert, 0x0001);
+
+	/* link training */
+	if (is_flag_set(core_link->core_lgrp->link_caps[core_link->num].hpe_map, SL_LINK_CONFIG_HPE_LINKTRAIN)) {
+		sl_core_log_dbg(core_lgrp, LOG_NAME,
+				"lane up tx config link train on (serdes = %u)", serdes_lane_num);
+		SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+				  addrs[SERDES_LINKTRN_IEEE_TX_LINKTRNIT_BASE_R_PMD_CONTROL], 0x0002, 0x0002);
+	} else {
+		sl_core_log_dbg(core_lgrp, LOG_NAME,
+				"lane up tx config link train off (serdes = %u)", serdes_lane_num);
+		SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+				  addrs[SERDES_LINKTRN_IEEE_TX_LINKTRNIT_BASE_R_PMD_CONTROL], 0x0000, 0x0002);
+	}
+
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  addrs[SERDES_TLB_TX_RMT_LPBK_CONFIG], 0x0000, 0x0001); /* RMT_LPBK_EN */
+
+	/* set core mode */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  addrs[SERDES_TLB_TX_PRBS_GEN_CONFIG], 0x0000, 0x0001); /* PRBS_GEN_EN */
+
+	/* patern generator disable */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  addrs[SERDES_TLB_TX_PATT_GEN_CONFIG], 0x0000, 0x0001); /* PATT_GEN_EN */
+
+	/* PRBS check enable */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  addrs[SERDES_TLB_RX_PRBS_CHK_CONFIG], 0x0000, 0x0001); /* PRBS_CHK_EN */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  addrs[SERDES_TLB_RX_PRBS_CHK_CONFIG], 0x0001, 0x0001); /* PRBS_CHK_EN */
+
+	rtn = 0;
+out:
+	return rtn;
+}
+
+int sl_core_hw_serdes_lane_up_tx_start(struct sl_core_link *core_link, u8 serdes_lane_num)
+{
+	int                  rtn;
+	u64                  data64;
+	u32                  port;
+	u8                   asic_lane_num;
+	struct sl_core_lgrp *core_lgrp;
+
+	core_lgrp     = core_link->core_lgrp;
+	port          = core_lgrp->num;
+	asic_lane_num = sl_core_hw_serdes_tx_asic_lane_num_get(core_link, serdes_lane_num);
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME,
+			"lane up tx start (port = %u, serdes_lane_num = %u, asic_lane_num = %u)",
+		port, serdes_lane_num, asic_lane_num);
+
+	sl_core_hw_serdes_tx_lane_state_set(core_lgrp,
+					    asic_lane_num, SL_CORE_HW_SERDES_LANE_STATE_START);
+
+	/* enable DP */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  core_lgrp->core_ldev->serdes.addrs[SERDES_TXCOM_CKRST_CTRL_TXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL],
+		0x0001, 0x0001); /* TX_LN_DP_EN */
+
+	/* release DP reset */
+	sl_core_lgrp_read64(core_lgrp, SS2_PORT_PML_CFG_SERDES_TX(asic_lane_num), &data64);
+	data64 = SS2_PORT_PML_CFG_SERDES_TX_PMD_LN_TX_DP_H_RSTB_UPDATE(data64, 1); /* active low */
+	sl_core_lgrp_write64(core_lgrp, SS2_PORT_PML_CFG_SERDES_TX(asic_lane_num), data64);
+	sl_core_lgrp_flush64(core_lgrp, SS2_PORT_PML_CFG_SERDES_TX(asic_lane_num));
+
+	/* enable TX */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  core_lgrp->core_ldev->serdes.addrs[SERDES_TX_FED_TXFIR_MISC_CONTROL0],
+		0x0000, 0x0001); /* TX_DISABLE */
+
+	rtn = 0;
+out:
+	return rtn;
+}
+
+void sl_core_hw_serdes_lane_down_tx_stop(struct sl_core_link *core_link, u8 serdes_lane_num)
+{
+	int                  rtn;
+	u64                  data64;
+	u32                  port;
+	u8                   asic_lane_num;
+	struct sl_core_lgrp *core_lgrp;
+
+	core_lgrp     = core_link->core_lgrp;
+	port          = core_lgrp->num;
+	asic_lane_num = sl_core_hw_serdes_tx_asic_lane_num_get(core_link, serdes_lane_num);
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME,
+			"lane down tx stop (port = %u, serdes_lane_num = %u, asic_lane_num = %u)",
+		port, serdes_lane_num, asic_lane_num);
+
+	sl_core_hw_serdes_tx_lane_state_set(core_lgrp,
+					    asic_lane_num, SL_CORE_HW_SERDES_LANE_STATE_STOP);
+
+	/* disable TX */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  core_lgrp->core_ldev->serdes.addrs[SERDES_TX_FED_TXFIR_MISC_CONTROL0],
+		0x0001, 0x0001); /* TX_DISABLE */
+
+	/* disable DP */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  core_lgrp->core_ldev->serdes.addrs[SERDES_TXCOM_CKRST_CTRL_TXCOM_LANE_CLK_RESET_N_POWERDOWN_CONTROL],
+		0x0000, 0x0001); /* TX_LN_DP_EN */
+
+	/* assert DP reset */
+	sl_core_lgrp_read64(core_lgrp, SS2_PORT_PML_CFG_SERDES_TX(asic_lane_num), &data64);
+	data64 = SS2_PORT_PML_CFG_SERDES_TX_PMD_LN_TX_DP_H_RSTB_UPDATE(data64, 0); /* active low */
+	sl_core_lgrp_write64(core_lgrp, SS2_PORT_PML_CFG_SERDES_TX(asic_lane_num), data64);
+	sl_core_lgrp_flush64(core_lgrp, SS2_PORT_PML_CFG_SERDES_TX(asic_lane_num));
+
+	/* power down */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  core_lgrp->core_ldev->serdes.addrs[SERDES_TX_CKRST_CTRL_TX_LANE_CLK_RESET_N_POWERDOWN_CONTROL],
+		0x0001, 0x0001); /* tx_s_pwrdn */
+
+	usleep_range(10000, 20000);  /* avoid power surge */
+
+out:
+	return;
+}
+
+int sl_core_hw_serdes_lane_tx_prbs_config(struct sl_core_link *core_link, u8 serdes_lane_num)
+{
+	int                  rtn;
+	struct sl_core_lgrp *core_lgrp;
+
+	core_lgrp = core_link->core_lgrp;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "tx prbs config (serdes_lane_num = %u)", serdes_lane_num);
+
+	/* PRBS Gen Mode Select */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  0xD171, 0x000A, 0x000E);
+
+	/* Set MSB for PRBS Mode Selection */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  0xD171, 0x0000, 0x1000);
+
+	/* PRBS Invert Disable*/
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  0xD171, 0x0000, 0x0010);
+
+	rtn = 0;
+out:
+	return rtn;
+}
+
+int sl_core_hw_serdes_lane_tx_prbs_enable(struct sl_core_link *core_link, u8 serdes_lane_num)
+{
+	int                  rtn;
+	struct sl_core_lgrp *core_lgrp;
+
+	core_lgrp = core_link->core_lgrp;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "tx prbs enable (serdes_lane_num = %u)", serdes_lane_num);
+
+	/* Enable PRBS Generator */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  0xD171, 0x0001, 0x0001);
+
+	rtn = 0;
+out:
+	return rtn;
+}
+
+int sl_core_hw_serdes_lane_tx_prbs_shrd_patt_gen_disable(struct sl_core_link *core_link, u8 serdes_lane_num)
+{
+	int                  rtn;
+	struct sl_core_lgrp *core_lgrp;
+
+	core_lgrp = core_link->core_lgrp;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "tx prbs shared pattern gen disable (serdes_lane_num = %u)", serdes_lane_num);
+
+	/* Disable Fixed Pattern Generation */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  0xD170, 0x0000, 0x0001);
+
+	rtn = 0;
+out:
+	return rtn;
+}
+
+int sl_core_hw_serdes_lane_tx_prbs_remote_loopback_disable(struct sl_core_link *core_link, u8 serdes_lane_num)
+{
+	int                  rtn;
+	struct sl_core_lgrp *core_lgrp;
+
+	core_lgrp = core_link->core_lgrp;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "tx prbs remote loopback disable (serdes_lane_num = %u)", serdes_lane_num);
+
+	/* Disable Loopback */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  0xD172, 0x0000, 0x0001);
+
+	rtn = 0;
+out:
+	return rtn;
+}
+
+int sl_core_hw_serdes_lane_tx_prbs_checker_enable(struct sl_core_link *core_link, u8 serdes_lane_num)
+{
+	int                  rtn;
+	struct sl_core_lgrp *core_lgrp;
+
+	core_lgrp = core_link->core_lgrp;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "tx prbs checker enable (serdes_lane_num = %u)", serdes_lane_num);
+
+	/* Disable PRBS checker */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  0xD161, 0x0000, 0x0001);
+
+	/* Enable PRBS checker */
+	SL_CORE_HW_PMI_WR(core_lgrp, core_lgrp->serdes.dt.dev_id, serdes_lane_num, 0,
+			  0xD161, 0x0001, 0x0001);
+
+	rtn = 0;
+out:
+	return rtn;
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes_link.c b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes_link.c
new file mode 100644
index 000000000000..1c8211efe2d5
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_serdes_link.c
@@ -0,0 +1,349 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2025-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/umh.h>
+
+#include <linux/hpe/sl/sl_media.h>
+#include <linux/hpe/sl/sl_link.h>
+
+#include "sl_platform.h"
+#include "sl_ctrl_lgrp.h"
+#include "sl_core_link.h"
+#include "base/sl_core_log.h"
+#include "hw/sl_core_hw_serdes_core.h"
+#include "hw/sl_core_hw_serdes_link.h"
+#include "hw/sl_core_hw_serdes_lane.h"
+#include "hw/sl_core_hw_settings.h"
+#include "sl_media_lgrp.h"
+#include "sl_media_jack.h"
+#include "data/sl_core_data_link.h"
+#include "data/sl_core_data_lgrp.h"
+#include "data/sl_ctrl_data_lgrp_trace.h"
+
+#define LOG_NAME SL_CORE_SERDES_LOG_NAME
+
+#define SL_CORE_HW_SERDES_STATE_DOWN 0
+#define SL_CORE_HW_SERDES_STATE_UP   1
+
+static int sl_core_hw_serdes_link_up_an_settings(struct sl_core_link *core_link)
+{
+	struct sl_media_lgrp *media_lgrp;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "link up an settings");
+
+	media_lgrp = sl_media_lgrp_get(core_link->core_lgrp->core_ldev->num, core_link->core_lgrp->num);
+	if (sl_media_lgrp_is_cable_unsupported(media_lgrp))
+		sl_core_log_warn_trace(core_link, LOG_NAME,
+				       "cable unsupported - using default serdes settings");
+
+	sl_media_lgrp_media_serdes_settings_get(core_link->core_lgrp->core_ldev->num,
+						core_link->core_lgrp->num, &core_link->serdes.media_serdes_settings);
+
+	core_link->serdes.core_serdes_settings.dfe          = SL_CORE_HW_SERDES_DFE_DISABLE;
+	core_link->serdes.core_serdes_settings.scramble_dis = SL_CORE_HW_SERDES_SCRAMBLE_DIS_SET;
+	core_link->serdes.core_serdes_settings.osr          = SL_CORE_HW_SERDES_OSR_OSX42P5;
+	core_link->serdes.core_serdes_settings.encoding     = SL_CORE_HW_SERDES_ENCODING_NRZ;
+	core_link->serdes.core_serdes_settings.clocking     = SL_CORE_HW_SERDES_CLOCKING_85;
+	core_link->serdes.core_serdes_settings.width        = SL_CORE_HW_SERDES_WIDTH_40;
+
+	switch (core_link->core_lgrp->config.furcation) {
+	case SL_MEDIA_FURCATION_X1:
+		core_link->serdes.lane_map = BIT(0);
+		break;
+	case SL_MEDIA_FURCATION_X2:
+		core_link->serdes.lane_map = BIT(0) << (core_link->num * 2);
+		break;
+	case SL_MEDIA_FURCATION_X4:
+		core_link->serdes.lane_map = BIT(core_link->num);
+		break;
+	default:
+		core_link->serdes.lane_map = 0;
+	}
+	core_link->serdes.lane_map <<= (4 * (core_link->core_lgrp->num & BIT(0)));
+	sl_core_log_dbg(core_link, LOG_NAME, "link up an settings (lane_map = 0x%02X)",
+			core_link->serdes.lane_map);
+
+	return 0;
+}
+
+int sl_core_hw_serdes_link_up_an(struct sl_core_link *core_link)
+{
+	int rtn;
+
+	if (!SL_PLATFORM_IS_HARDWARE(core_link->core_lgrp->core_ldev))
+		return 0;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "link up an");
+
+	rtn = sl_core_hw_serdes_link_up_an_settings(core_link);
+	if (rtn != 0) {
+		sl_core_data_link_last_up_fail_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_SERDES_CONFIG_MAP);
+		sl_core_log_err_trace(core_link, LOG_NAME, "serdes_link_up_an_settings failed [%d]", rtn);
+		return rtn;
+	}
+
+	rtn = sl_core_hw_serdes_core_pll(core_link->core_lgrp,
+					 core_link->serdes.core_serdes_settings.clocking, SL_CORE_HW_SERDES_TX_PLL_BW_DEFAULT);
+	if (rtn) {
+		sl_core_data_link_last_up_fail_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_SERDES_PLL_MAP);
+		sl_core_log_err_trace(core_link, LOG_NAME, "serdes_core_pll failed [%d]", rtn);
+		return -EIO;
+	}
+
+	rtn = sl_core_hw_serdes_lanes_up(core_link, SL_CORE_HW_SERDES_AUTONEG);
+	if (rtn != 0) {
+		sl_core_log_err_trace(core_link, LOG_NAME, "serdes_lanes_up failed [%d]", rtn);
+		return rtn;
+	}
+
+	return 0;
+}
+
+static int sl_core_hw_serdes_link_up_settings(struct sl_core_link *core_link)
+{
+	struct sl_media_lgrp *media_lgrp;
+	u8		      cable_shift_state;
+	int		      rtn;
+
+	media_lgrp = sl_media_lgrp_get(core_link->core_lgrp->core_ldev->num, core_link->core_lgrp->num);
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"link up settings (config.flags = 0x%X, pcs_mode = %u, is_active = %s)",
+			core_link->config.flags, core_link->pcs.settings.pcs_mode,
+			sl_media_lgrp_media_type_is_active(media_lgrp->media_ldev->num, media_lgrp->num) ? "yes" : " no");
+
+	if (is_flag_set(core_link->core_lgrp->config.options, SL_LGRP_CONFIG_OPT_SERDES_LOOPBACK_ENABLE)) {
+		sl_core_log_dbg(core_link, LOG_NAME, "link up settings loopback");
+		SL_CORE_HW_SERDES_LOOPBACK_SERDES_SETTINGS_SET(core_link);
+	} else {
+		sl_core_log_dbg(core_link, LOG_NAME, "link up settings normal");
+		sl_media_lgrp_media_serdes_settings_get(core_link->core_lgrp->core_ldev->num,
+							core_link->core_lgrp->num, &core_link->serdes.media_serdes_settings);
+	}
+
+	switch (core_link->pcs.settings.pcs_mode) {
+	case SL_CORE_HW_PCS_MODE_BJ_100G:
+		core_link->serdes.core_serdes_settings.encoding  = SL_CORE_HW_SERDES_ENCODING_NRZ;
+		core_link->serdes.core_serdes_settings.clocking  = SL_CORE_HW_SERDES_CLOCKING_82P5;
+		core_link->serdes.core_serdes_settings.width     = SL_CORE_HW_SERDES_WIDTH_40;
+		core_link->serdes.core_serdes_settings.osr       = SL_CORE_HW_SERDES_OSR_OSX2;
+		core_link->serdes.core_serdes_settings.tx_pll_bw = SL_CORE_HW_SERDES_TX_PLL_BW_DEFAULT;
+		break;
+	case SL_CORE_HW_PCS_MODE_CD_50G:
+	case SL_CORE_HW_PCS_MODE_CD_100G:
+	case SL_CORE_HW_PCS_MODE_BS_200G:
+		core_link->serdes.core_serdes_settings.encoding  = SL_CORE_HW_SERDES_ENCODING_PAM4_NR;
+		core_link->serdes.core_serdes_settings.clocking  = SL_CORE_HW_SERDES_CLOCKING_85;
+		core_link->serdes.core_serdes_settings.width     = SL_CORE_HW_SERDES_WIDTH_80;
+		core_link->serdes.core_serdes_settings.osr       = SL_CORE_HW_SERDES_OSR_OSX2;
+		core_link->serdes.core_serdes_settings.tx_pll_bw = SL_CORE_HW_SERDES_TX_PLL_BW_DEFAULT;
+		break;
+	case SL_CORE_HW_PCS_MODE_CK_100G:
+	case SL_CORE_HW_PCS_MODE_CK_200G:
+	case SL_CORE_HW_PCS_MODE_CK_400G:
+		core_link->serdes.core_serdes_settings.encoding  = SL_CORE_HW_SERDES_ENCODING_PAM4_NR;
+		core_link->serdes.core_serdes_settings.clocking  = SL_CORE_HW_SERDES_CLOCKING_85;
+		core_link->serdes.core_serdes_settings.width     = SL_CORE_HW_SERDES_WIDTH_160;
+		core_link->serdes.core_serdes_settings.osr       = SL_CORE_HW_SERDES_OSR_OSX1;
+		if (media_lgrp->cable_info->media_attr.type == SL_MEDIA_TYPE_AEC)
+			core_link->serdes.core_serdes_settings.tx_pll_bw = SL_CORE_HW_SERDES_TX_PLL_BW_100Glane_AEC;
+		else if (media_lgrp->cable_info->media_attr.type == SL_MEDIA_TYPE_AOC ||
+			 media_lgrp->cable_info->media_attr.type == SL_MEDIA_TYPE_POC)
+			core_link->serdes.core_serdes_settings.tx_pll_bw = SL_CORE_HW_SERDES_TX_PLL_BW_100Glane_AOC;
+		else
+			core_link->serdes.core_serdes_settings.tx_pll_bw = SL_CORE_HW_SERDES_TX_PLL_BW_DEFAULT;
+		break;
+	}
+
+	core_link->serdes.core_serdes_settings.dfe = SL_CORE_HW_SERDES_DFE_ENABLE;
+	rtn = sl_media_jack_cable_shift_state_get(media_lgrp->media_jack, &cable_shift_state);
+	if (rtn)
+		sl_core_log_warn_trace(core_link, LOG_NAME, "cable_shift_state_get failed [%d]", rtn);
+
+	if (cable_shift_state == SL_MEDIA_JACK_CABLE_SHIFT_STATE_DOWNSHIFTED)
+		core_link->serdes.core_serdes_settings.scramble_dis = SL_CORE_HW_SERDES_SCRAMBLE_DIS_SET;
+	else
+		core_link->serdes.core_serdes_settings.scramble_dis = SL_CORE_HW_SERDES_SCRAMBLE_DIS_NOTSET;
+
+	switch (core_link->core_lgrp->config.furcation) {
+	case SL_MEDIA_FURCATION_X1:
+		core_link->serdes.lane_map = (BIT(0) | BIT(1) | BIT(2) | BIT(3));
+		break;
+	case SL_MEDIA_FURCATION_X2:
+		core_link->serdes.lane_map = ((BIT(0) | BIT(1)) << (core_link->num * 2));
+		break;
+	case SL_MEDIA_FURCATION_X4:
+		core_link->serdes.lane_map = BIT(core_link->num);
+		break;
+	default:
+		core_link->serdes.lane_map = 0;
+	}
+	core_link->serdes.lane_map <<= (4 * (core_link->core_lgrp->num & BIT(0)));
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"link up settings (config.furcation = %u, lane_map = 0x%02X)",
+			core_link->core_lgrp->config.furcation, core_link->serdes.lane_map);
+
+	core_link->core_lgrp->serdes.eye_limits[0].low  = 15;
+	core_link->core_lgrp->serdes.eye_limits[0].high = 60;
+	core_link->core_lgrp->serdes.eye_limits[1].low  = 15;
+	core_link->core_lgrp->serdes.eye_limits[1].high = 60;
+	core_link->core_lgrp->serdes.eye_limits[2].low  = 15;
+	core_link->core_lgrp->serdes.eye_limits[2].high = 60;
+	core_link->core_lgrp->serdes.eye_limits[3].low  = 15;
+	core_link->core_lgrp->serdes.eye_limits[3].high = 60;
+	if (core_link->pcs.settings.pcs_mode == SL_CORE_HW_PCS_MODE_BJ_100G) {
+		core_link->core_lgrp->serdes.eye_limits[0].low  = 25;
+		core_link->core_lgrp->serdes.eye_limits[0].high = 150;
+		core_link->core_lgrp->serdes.eye_limits[1].low  = 25;
+		core_link->core_lgrp->serdes.eye_limits[1].high = 150;
+		core_link->core_lgrp->serdes.eye_limits[2].low  = 25;
+		core_link->core_lgrp->serdes.eye_limits[2].high = 150;
+		core_link->core_lgrp->serdes.eye_limits[3].low  = 25;
+		core_link->core_lgrp->serdes.eye_limits[3].high = 150;
+	}
+
+	if (core_link->pcs.settings.pcs_mode == SL_CORE_HW_PCS_MODE_BS_200G &&
+	    sl_media_lgrp_media_type_is_active(media_lgrp->media_ldev->num, media_lgrp->num)) {
+		sl_core_log_dbg(core_link, LOG_NAME, "link up settings 200G half rate");
+		core_link->serdes.media_serdes_settings.pre1   = 0;
+		core_link->serdes.media_serdes_settings.cursor = 80;
+		core_link->serdes.media_serdes_settings.post1  = 0;
+	}
+
+	/* test settings must be last */
+	if (core_link->serdes.use_test_settings) {
+		sl_core_log_warn(core_link, LOG_NAME, "link up settings test");
+		// media settings
+		core_link->serdes.media_serdes_settings.pre1        = core_link->serdes.test_settings.pre1;
+		core_link->serdes.media_serdes_settings.pre2        = core_link->serdes.test_settings.pre2;
+		core_link->serdes.media_serdes_settings.pre3        = core_link->serdes.test_settings.pre3;
+		core_link->serdes.media_serdes_settings.cursor      = core_link->serdes.test_settings.cursor;
+		core_link->serdes.media_serdes_settings.post1       = core_link->serdes.test_settings.post1;
+		core_link->serdes.media_serdes_settings.post2       = core_link->serdes.test_settings.post2;
+		core_link->serdes.media_serdes_settings.media       = core_link->serdes.test_settings.media;
+		// core settings
+		core_link->serdes.core_serdes_settings.osr          = core_link->serdes.test_settings.osr;
+		core_link->serdes.core_serdes_settings.encoding     = core_link->serdes.test_settings.encoding;
+		core_link->serdes.core_serdes_settings.clocking     = core_link->serdes.test_settings.clocking;
+		core_link->serdes.core_serdes_settings.width        = core_link->serdes.test_settings.width;
+		core_link->serdes.core_serdes_settings.dfe          = core_link->serdes.test_settings.dfe;
+		core_link->serdes.core_serdes_settings.scramble_dis = core_link->serdes.test_settings.scramble_dis;
+	}
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"link up settings (pre1 = %d, pre2 = %d, pre3 = %d, cursor = %d, post1 = %d, post2 = %d, media = %d)",
+			core_link->serdes.test_settings.pre1, core_link->serdes.test_settings.pre2,
+			core_link->serdes.test_settings.pre3, core_link->serdes.test_settings.cursor,
+			core_link->serdes.test_settings.post1, core_link->serdes.test_settings.post2,
+			core_link->serdes.test_settings.media);
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"link up settings (osr = %u, encoding = %u, clocking = %u, width = %u, dfe = %u, scramble_dis = %u)",
+			core_link->serdes.test_settings.osr, core_link->serdes.test_settings.encoding,
+			core_link->serdes.test_settings.clocking, core_link->serdes.test_settings.width,
+			core_link->serdes.test_settings.dfe, core_link->serdes.test_settings.scramble_dis);
+
+	return 0;
+}
+
+int sl_core_hw_serdes_link_up(struct sl_core_link *core_link)
+{
+	int                  rtn;
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+
+	if (!SL_PLATFORM_IS_HARDWARE(core_link->core_lgrp->core_ldev))
+		return 0;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "link up");
+
+	sl_core_data_link_info_map_set(core_link, SL_CORE_INFO_MAP_SERDES_START);
+
+	ctrl_lgrp = sl_ctrl_lgrp_get(core_link->core_lgrp->core_ldev->num, core_link->core_lgrp->num);
+
+	rtn = sl_core_hw_serdes_link_up_settings(core_link);
+	if (rtn != 0) {
+		sl_core_data_link_last_up_fail_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_SERDES_CONFIG_MAP);
+		sl_core_log_err_trace(core_link, LOG_NAME, "serdes_link_up_settings failed [%d]", rtn);
+		return rtn;
+	}
+
+	sl_core_data_lgrp_io_trace_set(core_link->core_lgrp,
+				       sl_ctrl_data_lgrp_is_serdes_lane_io_trace_enabled(ctrl_lgrp));
+
+	rtn = sl_core_hw_serdes_core_pll(core_link->core_lgrp,
+					 core_link->serdes.core_serdes_settings.clocking, core_link->serdes.core_serdes_settings.tx_pll_bw);
+	if (rtn) {
+		sl_core_data_link_last_up_fail_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_SERDES_PLL_MAP);
+		sl_core_log_err_trace(core_link, LOG_NAME, "serdes_core_pll failed [%d]", rtn);
+		sl_core_data_lgrp_io_trace_set(core_link->core_lgrp, false);
+		return -EIO;
+	}
+
+	rtn = sl_core_hw_serdes_lanes_up(core_link, SL_CORE_HW_SERDES_ATSPEED);
+	if (rtn != 0) {
+		sl_core_log_err_trace(core_link, LOG_NAME, "serdes_lanes_up failed [%d]", rtn);
+		sl_core_data_lgrp_io_trace_set(core_link->core_lgrp, false);
+		return rtn;
+	}
+
+	sl_core_hw_serdes_state_set(core_link, SL_CORE_HW_SERDES_STATE_UP);
+	sl_core_data_link_info_map_clr(core_link, SL_CORE_INFO_MAP_SERDES_START);
+	sl_core_data_link_info_map_set(core_link, SL_CORE_INFO_MAP_SERDES_OK);
+
+	sl_core_data_lgrp_io_trace_set(core_link->core_lgrp, false);
+	return 0;
+}
+
+static int sl_core_hw_serdes_link_down_settings(struct sl_core_link *core_link)
+{
+	sl_core_log_dbg(core_link, LOG_NAME, "link down settings");
+
+	switch (core_link->core_lgrp->config.furcation) {
+	case SL_MEDIA_FURCATION_X1:
+		core_link->serdes.lane_map = (BIT(0) | BIT(1) | BIT(2) | BIT(3));
+		break;
+	case SL_MEDIA_FURCATION_X2:
+		core_link->serdes.lane_map = ((BIT(0) | BIT(1)) << (core_link->num * 2));
+		break;
+	case SL_MEDIA_FURCATION_X4:
+		core_link->serdes.lane_map = BIT(core_link->num);
+		break;
+	}
+	core_link->serdes.lane_map <<= (4 * (core_link->core_lgrp->num & BIT(0)));
+	sl_core_log_dbg(core_link, LOG_NAME, "link down settings (lane_map = 0x%X)",
+			core_link->serdes.lane_map);
+
+	return 0;
+}
+
+void sl_core_hw_serdes_link_down(struct sl_core_link *core_link)
+{
+	int                  rtn;
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+
+	if (!SL_PLATFORM_IS_HARDWARE(core_link->core_lgrp->core_ldev))
+		return;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "link down");
+
+	ctrl_lgrp = sl_ctrl_lgrp_get(core_link->core_lgrp->core_ldev->num, core_link->core_lgrp->num);
+
+	rtn = sl_core_hw_serdes_link_down_settings(core_link);
+	if (rtn)
+		sl_core_log_warn_trace(core_link, LOG_NAME, "serdes_link_down_settings failed [%d]", rtn);
+
+	sl_core_data_lgrp_io_trace_set(core_link->core_lgrp,
+				       sl_ctrl_data_lgrp_is_serdes_lane_io_trace_enabled(ctrl_lgrp));
+
+	sl_core_hw_serdes_lanes_down(core_link);
+
+	sl_core_data_lgrp_io_trace_set(core_link->core_lgrp, false);
+
+	memset(&(core_link->serdes.core_serdes_settings), 0, sizeof(struct sl_core_serdes_settings));
+	memset(&(core_link->serdes.media_serdes_settings), 0, sizeof(struct sl_media_serdes_settings));
+
+	sl_core_data_link_info_map_clr(core_link, SL_CORE_INFO_MAP_SERDES_LOOPBACK_ON);
+	sl_core_hw_serdes_state_set(core_link, SL_CORE_HW_SERDES_STATE_DOWN);
+	sl_core_data_link_info_map_clr(core_link, SL_CORE_INFO_MAP_SERDES_CHECK);
+	sl_core_data_link_info_map_clr(core_link, SL_CORE_INFO_MAP_SERDES_OK);
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_uc_ram.c b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_uc_ram.c
new file mode 100644
index 000000000000..22e4436c1da0
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/hw/sl_core_hw_uc_ram.c
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2024,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+
+#include "sl_core_lgrp.h"
+#include "base/sl_core_log.h"
+#include "hw/sl_core_hw_sbus_pmi.h"
+#include "hw/sl_core_hw_pmi.h"
+#include "hw/sl_core_hw_uc_ram.h"
+#include "hw/sl_core_hw_serdes_addrs.h"
+
+#define LOG_NAME SL_CORE_HW_LOG_NAME
+
+int sl_core_hw_uc_ram_rd8(struct sl_core_lgrp *core_lgrp, u8 dev_addr,
+			  u8 dev_id, u8 lane_num, u32 addr, u8 *data)
+{
+	int  rtn;
+	u16  data16;
+	u16 *addrs;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "uc ram rd");
+
+	addrs = core_lgrp->core_ldev->serdes.addrs;
+
+	SL_CORE_HW_SBUS_PMI_WR(core_lgrp, dev_addr, dev_id, lane_num, 0,
+			       addrs[SERDES_MICRO_A_COM_AHB_CONTROL0], 0x0000, 0x2000); /* micro_autoinc_rdaddr_en */
+	SL_CORE_HW_SBUS_PMI_WR(core_lgrp, dev_addr, dev_id, lane_num, 0,
+			       addrs[SERDES_MICRO_A_COM_AHB_CONTROL0], 0x0000, 0x0030); /* micro_ra_rddatasize */
+	SL_CORE_HW_PMI_WR(core_lgrp, dev_id, lane_num, 0,
+			  addrs[SERDES_MICRO_A_COM_AHB_RDADDR_MSW], ((addr >> 16) & 0xFFFF), 0xFFFF); /* micro_ra_rdaddr_msw */
+	SL_CORE_HW_PMI_WR(core_lgrp, dev_id, lane_num, 0,
+			  addrs[SERDES_MICRO_A_COM_AHB_RDADDR_LSW], (addr & 0xFFFF), 0xFFFF); /* micro_ra_rdaddr_lsw */
+
+	/* rd data */
+	SL_CORE_HW_PMI_RD(core_lgrp, dev_id, lane_num, 0,
+			  addrs[SERDES_MICRO_A_COM_AHB_RDDATA_LSW], &data16); /* micro_ra_rddata_lsw */
+	*data = (data16 & 0x00FF);
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME,
+			"uc ram rd8 (lane_num = %u, addr = 0x%08X, data = 0x%02X)",
+		lane_num, addr, *data);
+
+	rtn = 0;
+out:
+	return rtn;
+}
+
+int sl_core_hw_uc_ram_rd_blk(struct sl_core_lgrp *core_lgrp, u8 dev_addr,
+			     u8 dev_id, u32 start_addr, u8 rd_size, u8 *rd_buff)
+{
+	int  rtn;
+	u8   idx;
+	u16  data16;
+	u16 *addrs;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "uc ram rd blk");
+
+	addrs = core_lgrp->core_ldev->serdes.addrs;
+
+	SL_CORE_HW_SBUS_PMI_WR(core_lgrp, dev_addr, dev_id, 0xFF, 0,
+			       addrs[SERDES_MICRO_A_COM_AHB_CONTROL0], 0x2000, 0x2000); /* micro_autoinc_rdaddr_en */
+	SL_CORE_HW_SBUS_PMI_WR(core_lgrp, dev_addr, dev_id, 0xFF, 0,
+			       addrs[SERDES_MICRO_A_COM_AHB_CONTROL0], 0x0010, 0x0030); /* micro_ra_rddatasize */
+	SL_CORE_HW_PMI_WR(core_lgrp, dev_id, 0xFF, 0,
+			  addrs[SERDES_MICRO_A_COM_AHB_RDADDR_MSW], ((start_addr >> 16) & 0xFFFF), 0xFFFF); /* micro_ra_rdaddr_msw */
+	SL_CORE_HW_PMI_WR(core_lgrp, dev_id, 0xFF, 0,
+			  addrs[SERDES_MICRO_A_COM_AHB_RDADDR_LSW], (start_addr & 0xFFFE), 0xFFFF); /* micro_ra_rdaddr_lsw */
+
+	idx = 0;
+	while (rd_size > 0) {
+		SL_CORE_HW_PMI_RD(core_lgrp, dev_id, 0xFF, 0,
+				  addrs[SERDES_MICRO_A_COM_AHB_RDDATA_LSW], &data16); /* micro_ra_rddata_lsw */
+
+		rd_buff[idx] = (data16 & 0xFF);
+		rd_buff[idx + 1] = ((data16 >> 8) & 0xFF);
+		rd_size -= 2;
+		idx += 2;
+	}
+
+	rtn = 0;
+out:
+	return rtn;
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/sl_core_ldev.c b/drivers/net/ethernet/hpe/sl/core/sl_core_ldev.c
new file mode 100644
index 000000000000..f5d92db587b4
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/sl_core_ldev.c
@@ -0,0 +1,192 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2022,2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/workqueue.h>
+#include <linux/firmware.h>
+
+#include "sl_asic.h"
+#include "sl_module.h"
+#include "sl_core_ldev.h"
+#include "sl_core_lgrp.h"
+#include "data/sl_core_data_ldev.h"
+#include "hw/sl_core_hw_serdes.h"
+#include "hw/sl_core_hw_serdes_fw.h"
+#include "hw/sl_core_hw_serdes_core.h"
+#include "hw/sl_core_hw_serdes_lane.h"
+
+#define LOG_NAME SL_CORE_LDEV_LOG_NAME
+
+int sl_core_ldev_new(u8 ldev_num, struct sl_accessors *accessors,
+		     struct sl_ops *ops, struct workqueue_struct *workqueue)
+{
+	return sl_core_data_ldev_new(ldev_num, accessors, ops, workqueue);
+}
+
+int sl_core_ldev_serdes_init(u8 ldev_num)
+{
+	int                  rtn;
+	int                  lgrp_num;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	struct sl_core_ldev *core_ldev;
+
+	core_ldev = sl_core_ldev_get(ldev_num);
+	if (!core_ldev) {
+		sl_core_log_err(core_ldev, LOG_NAME,
+				"ldev invalid (ldev_num = %u)", ldev_num);
+		return -EIO;
+	}
+
+	sl_core_log_dbg(core_ldev, LOG_NAME, "serdes_init");
+
+	sl_core_ldev_serdes_is_ready_set(core_ldev, false);
+
+	rtn = request_firmware(&(core_ldev->serdes.fw), SL_HW_SERDES_FW_FILE, sl_device_get());
+	if (rtn) {
+		sl_core_log_err(core_ldev, LOG_NAME, "request_firmware failed [%d]", rtn);
+		return -EIO;
+	}
+
+	for (lgrp_num = 0; lgrp_num < SL_ASIC_MAX_LGRPS; ++lgrp_num) {
+		sl_core_lgrp_put(core_lgrp);
+		core_lgrp = sl_core_lgrp_get(ldev_num, lgrp_num);
+		if (!core_lgrp)
+			continue;
+		rtn = sl_core_hw_serdes_init(core_lgrp);
+		if (rtn) {
+			sl_core_log_err(core_ldev, LOG_NAME,
+					"serdes_init (lgrp_num = %u) failed [%d]", lgrp_num, rtn);
+			goto out;
+		}
+	}
+
+	/* setup for firmware load per serdes ip */
+	for (lgrp_num = 0; lgrp_num < SL_ASIC_MAX_LGRPS; lgrp_num += 2) {
+		sl_core_lgrp_put(core_lgrp);
+		core_lgrp = sl_core_lgrp_get(ldev_num, lgrp_num);
+		if (!core_lgrp) {
+			sl_core_lgrp_put(core_lgrp);
+			core_lgrp = sl_core_lgrp_get(ldev_num, lgrp_num + 1);
+			if (!core_lgrp)
+				continue;
+		}
+		rtn = sl_core_hw_serdes_fw_setup(core_lgrp);
+		if (rtn) {
+			sl_core_log_err(core_ldev, LOG_NAME,
+					"serdes_fw_setup (lgrp_num = %u) failed [%d]", lgrp_num, rtn);
+			goto out;
+		}
+	}
+
+	/* broadcast write the firmware to all serdes */
+	for (lgrp_num = 0; lgrp_num < SL_ASIC_MAX_LGRPS; lgrp_num += 2) {
+		sl_core_lgrp_put(core_lgrp);
+		core_lgrp = sl_core_lgrp_get(ldev_num, lgrp_num);
+		if (!core_lgrp)
+			continue;
+		rtn = sl_core_hw_serdes_fw_write(core_lgrp);
+		if (rtn) {
+			sl_core_log_err(core_ldev, LOG_NAME,
+					"serdes_fw_write (lgrp_num = %u) failed [%d]", lgrp_num, rtn);
+			goto out;
+		}
+		break;
+	}
+
+	/* finish firmware load and start the micros per serdes ip */
+	for (lgrp_num = 0; lgrp_num < SL_ASIC_MAX_LGRPS; lgrp_num += 2) {
+		sl_core_lgrp_put(core_lgrp);
+		core_lgrp = sl_core_lgrp_get(ldev_num, lgrp_num);
+		if (!core_lgrp) {
+			sl_core_lgrp_put(core_lgrp);
+			core_lgrp = sl_core_lgrp_get(ldev_num, lgrp_num + 1);
+			if (!core_lgrp)
+				continue;
+		}
+		rtn = sl_core_hw_serdes_fw_finish(core_lgrp);
+		if (rtn) {
+			sl_core_log_err(core_ldev, LOG_NAME,
+					"serdes_fw_finish (lgrp_num = %u) failed [%d]", lgrp_num, rtn);
+			goto out;
+		}
+		rtn = sl_core_hw_serdes_fw_info_get(core_lgrp);
+		if (rtn) {
+			sl_core_log_err(core_ldev, LOG_NAME,
+					"serdes_fw_info_get (lgrp_num = %u) failed [%d]", lgrp_num, rtn);
+			goto out;
+		}
+		rtn = sl_core_hw_serdes_hw_info_get(core_lgrp);
+		if (rtn) {
+			sl_core_log_err(core_ldev, LOG_NAME,
+					"serdes_hw_info_get (lgrp_num = %u) failed [%d]", lgrp_num, rtn);
+			goto out;
+		}
+		rtn = sl_core_hw_serdes_core_init(core_lgrp);
+		if (rtn) {
+			sl_core_log_err(core_ldev, LOG_NAME,
+					"serdes_core_init (lgrp_num = %u) failed [%d]", lgrp_num, rtn);
+			goto out;
+		}
+		rtn = sl_core_hw_serdes_core_pll(core_lgrp,
+						 SL_CORE_HW_SERDES_CLOCKING_85, SL_CORE_HW_SERDES_TX_PLL_BW_DEFAULT);
+		if (rtn) {
+			sl_core_log_err(core_ldev, LOG_NAME,
+					"serdes_core_pll (lgrp_num = %u) failed [%d]", lgrp_num, rtn);
+			goto out;
+		}
+	}
+
+	for (lgrp_num = 0; lgrp_num < SL_ASIC_MAX_LGRPS; ++lgrp_num) {
+		sl_core_lgrp_put(core_lgrp);
+		core_lgrp = sl_core_lgrp_get(ldev_num, lgrp_num);
+		if (!core_lgrp)
+			continue;
+		rtn = sl_core_hw_serdes_swizzles(core_lgrp);
+		if (rtn) {
+			sl_core_log_err(core_ldev, LOG_NAME,
+					"serdes_swizzles (lgrp_num = %u) failed [%d]", lgrp_num, rtn);
+			goto out;
+		}
+	}
+
+	sl_core_ldev_serdes_is_ready_set(core_ldev, true);
+
+	rtn = 0;
+out:
+	release_firmware(core_ldev->serdes.fw);
+
+	return rtn;
+}
+
+int sl_core_ldev_del(u8 ldev_num)
+{
+	return sl_core_data_ldev_del(ldev_num);
+}
+
+struct sl_core_ldev *sl_core_ldev_get(u8 ldev_num)
+{
+	return sl_core_data_ldev_get(ldev_num);
+}
+
+void sl_core_ldev_serdes_is_ready_set(struct sl_core_ldev *core_ldev, bool is_ready)
+{
+	sl_core_log_dbg(core_ldev, LOG_NAME,
+			"set is_ready to %s", is_ready ? "true" : "false");
+
+	spin_lock(&core_ldev->data_lock);
+	core_ldev->serdes.is_ready = is_ready;
+	spin_unlock(&core_ldev->data_lock);
+}
+
+bool sl_core_ldev_serdes_is_ready(struct sl_core_ldev *core_ldev)
+{
+	bool is_ready;
+
+	spin_lock(&core_ldev->data_lock);
+	is_ready = core_ldev->serdes.is_ready;
+	spin_unlock(&core_ldev->data_lock);
+
+	sl_core_log_dbg(core_ldev, LOG_NAME,
+			"is_ready = %s", is_ready ? "true" : "false");
+
+	return is_ready;
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/sl_core_lgrp.c b/drivers/net/ethernet/hpe/sl/core/sl_core_lgrp.c
new file mode 100644
index 000000000000..eff2625f5430
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/sl_core_lgrp.c
@@ -0,0 +1,659 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2022,2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/spinlock.h>
+
+#include <linux/hpe/sl/sl_lgrp.h>
+
+#include "sl_core_lgrp.h"
+#include "data/sl_core_data_lgrp.h"
+#include "hw/sl_core_hw_serdes_lane.h"
+
+#define LOG_NAME SL_CORE_LGRP_LOG_NAME
+
+int sl_core_lgrp_new(u8 ldev_num, u8 lgrp_num)
+{
+	return sl_core_data_lgrp_new(ldev_num, lgrp_num);
+}
+
+void sl_core_lgrp_connect_id_set(u8 ldev_num, u8 lgrp_num, const char *connect_id)
+{
+	sl_core_data_lgrp_connect_id_set(ldev_num, lgrp_num, connect_id);
+}
+
+int sl_core_lgrp_del(u8 ldev_num, u8 lgrp_num)
+{
+	return sl_core_data_lgrp_del(ldev_num, lgrp_num);
+}
+
+struct sl_core_lgrp *sl_core_lgrp_get(u8 ldev_num, u8 lgrp_num)
+{
+	return sl_core_data_lgrp_get(ldev_num, lgrp_num);
+}
+
+int sl_core_lgrp_hw_attr_set(u8 ldev_num, u8 lgrp_num, struct sl_hw_attr *hw_attr)
+{
+	int                  rtn;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+
+	core_lgrp = sl_core_lgrp_get(ldev_num, lgrp_num);
+	if (!core_lgrp)
+		return -EBADRQC;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "hw attr set");
+
+	spin_lock(&(core_lgrp->data_lock));
+	if (core_lgrp->is_configuring || core_lgrp->is_deleting) {
+		sl_core_log_err(core_lgrp, LOG_NAME, "hw attr set - lgrp is configuring");
+		spin_unlock(&(core_lgrp->data_lock));
+		return -EBADRQC;
+	}
+	core_lgrp->is_configuring = 1;
+	spin_unlock(&(core_lgrp->data_lock));
+
+	rtn = sl_core_data_lgrp_link_config_check(core_lgrp);
+	if (rtn != 0) {
+		sl_core_log_err_trace(core_lgrp, LOG_NAME,
+				      "hw attr set - core_data_lgrp_link_config_check failed [%d]", rtn);
+		rtn = -EBADRQC;
+		goto out;
+	}
+
+	sl_core_data_lgrp_hw_attr_set(core_lgrp, hw_attr);
+
+	rtn = 0;
+
+out:
+	spin_lock(&(core_lgrp->data_lock));
+	core_lgrp->is_configuring = 0;
+	spin_unlock(&(core_lgrp->data_lock));
+
+	return rtn;
+}
+
+int sl_core_lgrp_config_set(u8 ldev_num, u8 lgrp_num, struct sl_lgrp_config *lgrp_config)
+{
+	int                  rtn;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+
+	core_lgrp = sl_core_lgrp_get(ldev_num, lgrp_num);
+	if (!core_lgrp)
+		return -EBADRQC;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "config set");
+
+	spin_lock(&(core_lgrp->data_lock));
+	if (core_lgrp->is_configuring || core_lgrp->is_deleting) {
+		sl_core_log_err(core_lgrp, LOG_NAME, "config set - lgrp is configuring");
+		spin_unlock(&(core_lgrp->data_lock));
+		return -EBADRQC;
+	}
+	core_lgrp->is_configuring = 1;
+	spin_unlock(&(core_lgrp->data_lock));
+
+	rtn = sl_core_data_lgrp_link_config_check(core_lgrp);
+	if (rtn != 0) {
+		sl_core_log_err_trace(core_lgrp, LOG_NAME,
+				      "config set - core_data_lgrp_link_config_check failed [%d]", rtn);
+		rtn = -EBADRQC;
+		goto out;
+	}
+
+	sl_core_data_lgrp_config_set(core_lgrp, lgrp_config);
+
+	rtn = 0;
+
+out:
+	spin_lock(&(core_lgrp->data_lock));
+	core_lgrp->is_configuring = 0;
+	spin_unlock(&(core_lgrp->data_lock));
+
+	return rtn;
+}
+
+int sl_core_lgrp_pre1_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, s16 *pre1)
+{
+	return sl_core_hw_serdes_lane_pre1_get(core_lgrp, asic_lane_num, pre1);
+}
+
+int sl_core_lgrp_pre2_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, s16 *pre2)
+{
+	return sl_core_hw_serdes_lane_pre2_get(core_lgrp, asic_lane_num, pre2);
+}
+
+int sl_core_lgrp_pre3_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, s16 *pre3)
+{
+	return sl_core_hw_serdes_lane_pre3_get(core_lgrp, asic_lane_num, pre3);
+}
+
+int sl_core_lgrp_cursor_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, s16 *cursor)
+{
+	return sl_core_hw_serdes_lane_cursor_get(core_lgrp, asic_lane_num, cursor);
+}
+
+int sl_core_lgrp_post1_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, s16 *post1)
+{
+	return sl_core_hw_serdes_lane_post1_get(core_lgrp, asic_lane_num, post1);
+}
+
+int sl_core_lgrp_post2_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, s16 *post2)
+{
+	return sl_core_hw_serdes_lane_post2_get(core_lgrp, asic_lane_num, post2);
+}
+
+int sl_core_lgrp_osr_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, u8 *osr)
+{
+	return sl_core_hw_serdes_lane_osr_get(core_lgrp, asic_lane_num, osr);
+}
+
+int sl_core_lgrp_encoding_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, u8 *encoding)
+{
+	return sl_core_hw_serdes_lane_encoding_get(core_lgrp, asic_lane_num, encoding);
+}
+
+int sl_core_lgrp_width_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, u8 *width)
+{
+	return sl_core_hw_serdes_lane_width_get(core_lgrp, asic_lane_num, width);
+}
+
+int sl_core_lgrp_dfe_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, u8 *dfe)
+{
+	return sl_core_hw_serdes_lane_dfe_get(core_lgrp, asic_lane_num, dfe);
+}
+
+int sl_core_lgrp_scramble_dis_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, u8 *scramble_dis)
+{
+	return sl_core_hw_serdes_lane_scramble_dis_get(core_lgrp, asic_lane_num, scramble_dis);
+}
+
+int sl_core_lgrp_eye_upper_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, u8 *eye_upper)
+{
+	return sl_core_hw_serdes_eye_upper_get(core_lgrp, asic_lane_num, eye_upper);
+}
+
+int sl_core_lgrp_eye_lower_get(struct sl_core_lgrp *core_lgrp, u8 asic_lane_num, u8 *eye_lower)
+{
+	return sl_core_hw_serdes_eye_lower_get(core_lgrp, asic_lane_num, eye_lower);
+}
+
+/* Shift media lane data based on the table below,
+ *
+ * | pgrp num | jack type | Swap Nibble |
+ * | -------- | --------- | ----------- |
+ * | even     | legacy    | no          |
+ * | even     | DD        | yes         |
+ * | odd      | legacy    | yes         |
+ * | odd      | DD        | no          |
+ */
+bool sl_core_lgrp_media_lane_data_swap(u8 ldev_num, u8 lgrp_num)
+{
+	u32                  jack_type;
+	bool                 swap;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+
+	core_lgrp = sl_core_lgrp_get(ldev_num, lgrp_num);
+	if (!core_lgrp)
+		return 0;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "media lane data swap");
+
+	if (PLATFORM_NIC) {
+		sl_core_log_dbg(core_lgrp, LOG_NAME,
+				"media lane data swap - NIC platform, no swap");
+		return false;
+	}
+
+	jack_type    = core_lgrp->serdes.dt.jack_type;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME,
+			"media lane data swap (jack_type = %u)", jack_type);
+
+	if (jack_type == SL_DT_JACK_TYPE_EXAMAX_LEFT || jack_type == SL_DT_JACK_TYPE_EXAMAX_RIGHT ||
+	    jack_type == SL_DT_JACK_TYPE_LOW || jack_type == SL_DT_JACK_TYPE_HIGH) {
+		sl_core_log_dbg(core_lgrp, LOG_NAME, "media lane data swap (Examax jack - no shift)");
+		return false;
+	}
+
+	swap = (((core_lgrp->num & 1) && jack_type == SL_DT_JACK_TYPE_LEGACY) ||
+		(!(core_lgrp->num & 1) && jack_type == SL_DT_JACK_TYPE_DD));
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "media lane data swap (swap = %s)", swap ? "yes" : "no");
+
+	return swap;
+}
+
+u32 sl_core_lgrp_jack_part_get(u8 ldev_num, u8 lgrp_num)
+{
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+
+	core_lgrp = sl_core_lgrp_get(ldev_num, lgrp_num);
+	if (!core_lgrp)
+		return 0;
+
+	sl_core_log_dbg(core_lgrp, LOG_NAME, "jack part get");
+
+	return core_lgrp->serdes.dt.jack_type;
+}
+
+int sl_core_lgrp_tx_lane_is_lol(u8 ldev_num, u8 lgrp_num, u8 asic_lane_num, bool *is_tx_lol)
+{
+	struct sl_core_lgrp *held_lgrp_1 __free(sl_core_lgrp_put) = NULL;
+	held_lgrp_1 = sl_core_lgrp_get(ldev_num, lgrp_num);
+	if (!held_lgrp_1)
+		return -ENODEV;
+	return sl_core_hw_serdes_tx_lane_is_lol(held_lgrp_1, asic_lane_num, is_tx_lol);
+}
+
+int sl_core_lgrp_rx_lane_is_lol(u8 ldev_num, u8 lgrp_num, u8 asic_lane_num, bool *is_rx_lol)
+{
+	struct sl_core_lgrp *held_lgrp_1 __free(sl_core_lgrp_put) = NULL;
+	held_lgrp_1 = sl_core_lgrp_get(ldev_num, lgrp_num);
+	if (!held_lgrp_1)
+		return -ENODEV;
+	return sl_core_hw_serdes_rx_lane_is_lol(held_lgrp_1, asic_lane_num, is_rx_lol);
+}
+
+int sl_core_lgrp_tx_lane_is_los(u8 ldev_num, u8 lgrp_num, u8 asic_lane_num, bool *is_tx_los)
+{
+	struct sl_core_lgrp *held_lgrp_1 __free(sl_core_lgrp_put) = NULL;
+	held_lgrp_1 = sl_core_lgrp_get(ldev_num, lgrp_num);
+	if (!held_lgrp_1)
+		return -ENODEV;
+	return sl_core_hw_serdes_tx_lane_is_los(held_lgrp_1, asic_lane_num, is_tx_los);
+}
+
+int sl_core_lgrp_rx_lane_is_los(u8 ldev_num, u8 lgrp_num, u8 asic_lane_num, bool *is_rx_los)
+{
+	struct sl_core_lgrp *held_lgrp_1 __free(sl_core_lgrp_put) = NULL;
+	held_lgrp_1 = sl_core_lgrp_get(ldev_num, lgrp_num);
+	if (!held_lgrp_1)
+		return -ENODEV;
+	return sl_core_hw_serdes_rx_lane_is_los(held_lgrp_1, asic_lane_num, is_rx_los);
+}
+
+int sl_core_lgrp_pmi_rd_addr_get(struct sl_core_lgrp *core_lgrp, u16 *addr)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*addr = core_lgrp->pmi.rd.addr;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_pmi_rd_data_get(struct sl_core_lgrp *core_lgrp, u16 *data)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*data = core_lgrp->pmi.rd.data;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_pmi_rd_dev_id_get(struct sl_core_lgrp *core_lgrp, u8 *dev_id)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*dev_id = core_lgrp->pmi.rd.dev_id;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_pmi_rd_lane_get(struct sl_core_lgrp *core_lgrp, u8 *lane)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*lane = core_lgrp->pmi.rd.lane;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_pmi_rd_pll_get(struct sl_core_lgrp *core_lgrp, u8 *pll)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*pll = core_lgrp->pmi.rd.pll;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_pmi_rd_result_get(struct sl_core_lgrp *core_lgrp, int *result)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*result = core_lgrp->pmi.rd.result;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_pmi_wr_addr_get(struct sl_core_lgrp *core_lgrp, u16 *addr)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*addr = core_lgrp->pmi.wr.addr;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_pmi_wr_data_get(struct sl_core_lgrp *core_lgrp, u16 *data)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*data = core_lgrp->pmi.wr.data;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_pmi_wr_mask_get(struct sl_core_lgrp *core_lgrp, u16 *mask)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*mask = core_lgrp->pmi.wr.mask;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_pmi_wr_dev_id_get(struct sl_core_lgrp *core_lgrp, u8 *dev_id)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*dev_id = core_lgrp->pmi.wr.dev_id;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_pmi_wr_lane_get(struct sl_core_lgrp *core_lgrp, u8 *lane)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*lane = core_lgrp->pmi.wr.lane;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_pmi_wr_pll_get(struct sl_core_lgrp *core_lgrp, u8 *pll)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*pll = core_lgrp->pmi.wr.pll;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_pmi_wr_result_get(struct sl_core_lgrp *core_lgrp, int *result)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*result = core_lgrp->pmi.wr.result;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_sbus_rd_dev_addr_get(struct sl_core_lgrp *core_lgrp, u8 *dev_addr)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*dev_addr = core_lgrp->sbus.rd.dev_addr;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_sbus_rd_data_get(struct sl_core_lgrp *core_lgrp, u32 *data)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*data = core_lgrp->sbus.rd.data;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_sbus_rd_mask_get(struct sl_core_lgrp *core_lgrp, u32 *mask)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*mask = core_lgrp->sbus.rd.mask;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_sbus_rd_reg_get(struct sl_core_lgrp *core_lgrp, u8 *reg)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*reg = core_lgrp->sbus.rd.reg;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_sbus_rd_lsb_get(struct sl_core_lgrp *core_lgrp, u8 *lsb)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*lsb = core_lgrp->sbus.rd.lsb;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_sbus_rd_result_get(struct sl_core_lgrp *core_lgrp, int *result)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*result = core_lgrp->sbus.rd.result;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_sbus_wr_dev_addr_get(struct sl_core_lgrp *core_lgrp, u8 *dev_addr)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*dev_addr = core_lgrp->sbus.wr.dev_addr;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_sbus_wr_data_get(struct sl_core_lgrp *core_lgrp, u32 *data)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*data = core_lgrp->sbus.wr.data;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_sbus_wr_mask_get(struct sl_core_lgrp *core_lgrp, u32 *mask)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*mask = core_lgrp->sbus.wr.mask;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_sbus_wr_reg_get(struct sl_core_lgrp *core_lgrp, u8 *reg)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*reg = core_lgrp->sbus.wr.reg;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_sbus_wr_lsb_get(struct sl_core_lgrp *core_lgrp, u8 *lsb)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*lsb = core_lgrp->sbus.wr.lsb;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_sbus_wr_result_get(struct sl_core_lgrp *core_lgrp, int *result)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*result = core_lgrp->sbus.wr.result;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_sbus_rst_dev_addr_get(struct sl_core_lgrp *core_lgrp, u8 *dev_addr)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*dev_addr = core_lgrp->sbus.rst.dev_addr;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_sbus_rst_result_get(struct sl_core_lgrp *core_lgrp, int *result)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*result = core_lgrp->sbus.rst.result;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_sbus_pmi_rd_dev_addr_get(struct sl_core_lgrp *core_lgrp, u8 *dev_addr)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*dev_addr = core_lgrp->sbus_pmi.rd.dev_addr;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_sbus_pmi_rd_addr_get(struct sl_core_lgrp *core_lgrp, u16 *addr)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*addr = core_lgrp->sbus_pmi.rd.addr;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_sbus_pmi_rd_data_get(struct sl_core_lgrp *core_lgrp, u16 *data)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*data = core_lgrp->sbus_pmi.rd.data;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_sbus_pmi_rd_mask_get(struct sl_core_lgrp *core_lgrp, u16 *mask)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*mask = core_lgrp->sbus_pmi.rd.mask;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_sbus_pmi_rd_dev_id_get(struct sl_core_lgrp *core_lgrp, u8 *dev_id)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*dev_id = core_lgrp->sbus_pmi.rd.dev_id;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_sbus_pmi_rd_lane_get(struct sl_core_lgrp *core_lgrp, u8 *lane)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*lane = core_lgrp->sbus_pmi.rd.lane;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_sbus_pmi_rd_pll_get(struct sl_core_lgrp *core_lgrp, u8 *pll)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*pll = core_lgrp->sbus_pmi.rd.pll;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_sbus_pmi_rd_result_get(struct sl_core_lgrp *core_lgrp, int *result)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*result = core_lgrp->sbus_pmi.rd.result;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_sbus_pmi_wr_dev_addr_get(struct sl_core_lgrp *core_lgrp, u8 *dev_addr)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*dev_addr = core_lgrp->sbus_pmi.wr.dev_addr;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_sbus_pmi_wr_addr_get(struct sl_core_lgrp *core_lgrp, u16 *addr)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*addr = core_lgrp->sbus_pmi.wr.addr;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_sbus_pmi_wr_data_get(struct sl_core_lgrp *core_lgrp, u16 *data)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*data = core_lgrp->sbus_pmi.wr.data;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_sbus_pmi_wr_mask_get(struct sl_core_lgrp *core_lgrp, u16 *mask)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*mask = core_lgrp->sbus_pmi.wr.mask;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_sbus_pmi_wr_dev_id_get(struct sl_core_lgrp *core_lgrp, u8 *dev_id)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*dev_id = core_lgrp->sbus_pmi.wr.dev_id;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_sbus_pmi_wr_lane_get(struct sl_core_lgrp *core_lgrp, u8 *lane)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*lane = core_lgrp->sbus_pmi.wr.lane;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_sbus_pmi_wr_pll_get(struct sl_core_lgrp *core_lgrp, u8 *pll)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*pll = core_lgrp->sbus_pmi.wr.pll;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
+
+int sl_core_lgrp_sbus_pmi_wr_result_get(struct sl_core_lgrp *core_lgrp, int *result)
+{
+	spin_lock(&core_lgrp->data_lock);
+	*result = core_lgrp->sbus_pmi.wr.result;
+	spin_unlock(&core_lgrp->data_lock);
+
+	return 0;
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/sl_core_link.c b/drivers/net/ethernet/hpe/sl/core/sl_core_link.c
new file mode 100644
index 000000000000..7404d3b607fb
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/sl_core_link.c
@@ -0,0 +1,623 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2022-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/spinlock.h>
+
+#include "sl_core_link.h"
+#include "sl_core_str.h"
+#include "base/sl_core_log.h"
+#include "data/sl_core_data_link.h"
+#include "data/sl_core_data_mac.h"
+#include "data/sl_core_data_llr.h"
+#include "hw/sl_core_hw_link.h"
+
+#define LOG_NAME SL_CORE_LINK_LOG_NAME
+
+int sl_core_link_new(u8 ldev_num, u8 lgrp_num, u8 link_num)
+{
+	return sl_core_data_link_new(ldev_num, lgrp_num, link_num);
+}
+
+int sl_core_link_del(u8 ldev_num, u8 lgrp_num, u8 link_num)
+{
+	return sl_core_data_link_del(ldev_num, lgrp_num, link_num);
+}
+
+struct sl_core_link *sl_core_link_get(u8 ldev_num, u8 lgrp_num, u8 link_num)
+{
+	return sl_core_data_link_get(ldev_num, lgrp_num, link_num);
+}
+
+void sl_core_link_put(struct sl_core_link *core_link)
+{
+	if (core_link)
+		sl_core_data_link_put_pinned(core_link);
+}
+
+struct sl_core_link *sl_core_link_get_pinned(u8 ldev_num, u8 lgrp_num, u8 link_num)
+{
+	return sl_core_data_link_get_pinned(ldev_num, lgrp_num, link_num);
+}
+
+void sl_core_link_put_pinned(struct sl_core_link *core_link)
+{
+	sl_core_data_link_put_pinned(core_link);
+}
+
+int sl_core_link_up(u8 ldev_num, u8 lgrp_num, u8 link_num,
+		    sl_core_link_up_callback_t callback, void *tag)
+{
+	enum sl_core_link_state link_state;
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+
+	core_link = sl_core_link_get(ldev_num, lgrp_num, link_num);
+	if (!core_link)
+		return -ENODEV;
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"up (link = 0x%p, flags = 0x%08X)", core_link, core_link->config.flags);
+
+	if (!sl_core_ldev_serdes_is_ready(core_link->core_lgrp->core_ldev)) {
+		sl_core_log_dbg(core_link, LOG_NAME, "up serdes isn't ready");
+		return -EIO;
+	}
+
+	spin_lock(&core_link->link.data_lock);
+	link_state = core_link->link.state;
+	switch (link_state) {
+	case SL_CORE_LINK_STATE_GOING_UP:
+	case SL_CORE_LINK_STATE_AN:
+		sl_core_log_dbg(core_link, LOG_NAME, "up - already going up");
+		spin_unlock(&core_link->link.data_lock);
+		return 0;
+	case SL_CORE_LINK_STATE_UP:
+		sl_core_log_dbg(core_link, LOG_NAME, "up - already up");
+		spin_unlock(&core_link->link.data_lock);
+		return 0;
+	case SL_CORE_LINK_STATE_CONFIGURED:
+	case SL_CORE_LINK_STATE_DOWN:
+		sl_core_log_dbg(core_link, LOG_NAME, "up - going up");
+		core_link->link.state = is_flag_set(core_link->config.flags, SL_LINK_CONFIG_OPT_AUTONEG_ENABLE) ?
+			SL_CORE_LINK_STATE_AN : SL_CORE_LINK_STATE_GOING_UP;
+		link_state = core_link->link.state;
+		spin_unlock(&core_link->link.data_lock);
+		sl_media_jack_led_set(core_link->core_lgrp->core_ldev->num, core_link->core_lgrp->num);
+		sl_core_hw_link_up_cmd(core_link, callback, tag);
+		return 0;
+	default:
+		sl_core_log_err(core_link, LOG_NAME,
+				"up - invalid (link_state = %u %s)",
+			link_state, sl_core_link_state_str(link_state));
+		spin_unlock(&core_link->link.data_lock);
+		return -EBADRQC;
+	}
+}
+
+int sl_core_link_up_fail(struct sl_core_link *core_link)
+{
+	enum sl_core_link_state link_state;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "up fail");
+
+	spin_lock(&core_link->link.data_lock);
+	link_state = core_link->link.state;
+	switch (link_state) {
+	case SL_CORE_LINK_STATE_CANCELING:
+	case SL_CORE_LINK_STATE_GOING_DOWN:
+	case SL_CORE_LINK_STATE_TIMEOUT:
+		sl_core_log_dbg(core_link, LOG_NAME, "up fail - already going down");
+		spin_unlock(&core_link->link.data_lock);
+		return 0;
+	case SL_CORE_LINK_STATE_GOING_UP:
+	case SL_CORE_LINK_STATE_AN:
+		sl_core_log_dbg(core_link, LOG_NAME, "up fail - going down");
+		core_link->link.state = SL_CORE_LINK_STATE_GOING_DOWN;
+		queue_work(core_link->core_lgrp->core_ldev->workqueue, &core_link->work[SL_CORE_WORK_LINK_UP_FAIL]);
+		spin_unlock(&core_link->link.data_lock);
+		sl_media_jack_led_set(core_link->core_lgrp->core_ldev->num, core_link->core_lgrp->num);
+		return 0;
+	default:
+		sl_core_log_err(core_link, LOG_NAME,
+				"up fail - invalid (link_state = %u %s)",
+			link_state, sl_core_link_state_str(link_state));
+		spin_unlock(&core_link->link.data_lock);
+		return -EBADRQC;
+	}
+}
+
+int sl_core_link_cancel(u8 ldev_num, u8 lgrp_num, u8 link_num,
+			sl_core_link_down_callback_t callback, void *tag)
+{
+	enum sl_core_link_state link_state;
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+
+	core_link = sl_core_link_get(ldev_num, lgrp_num, link_num);
+	if (!core_link)
+		return -ENODEV;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "cancel");
+
+	if (!callback) {
+		sl_core_log_err_trace(core_link, LOG_NAME, "cancel - NULL callback");
+		return -EINVAL;
+	}
+
+	spin_lock(&core_link->link.data_lock);
+	link_state = core_link->link.state;
+	switch (link_state) {
+	case SL_CORE_LINK_STATE_CANCELING:
+	case SL_CORE_LINK_STATE_GOING_DOWN:
+	case SL_CORE_LINK_STATE_TIMEOUT:
+		sl_core_log_dbg(core_link, LOG_NAME, "cancel - already going down");
+		spin_unlock(&core_link->link.data_lock);
+		return 0;
+	case SL_CORE_LINK_STATE_GOING_UP:
+	case SL_CORE_LINK_STATE_AN:
+		sl_core_log_dbg(core_link, LOG_NAME, "canceling");
+		core_link->link.tags.down       = tag;
+		core_link->link.callbacks.down  = callback;
+		core_link->link.state           = SL_CORE_LINK_STATE_CANCELING;
+		spin_unlock(&core_link->link.data_lock);
+		sl_core_data_link_last_up_fail_cause_map_set(core_link, SL_LINK_DOWN_CAUSE_CANCELED_MAP);
+		queue_work(core_link->core_lgrp->core_ldev->workqueue, &core_link->work[SL_CORE_WORK_LINK_UP_CANCEL]);
+		return 0;
+	default:
+		sl_core_log_err(core_link, LOG_NAME,
+				"cancel - invalid (link_state = %u %s)",
+			link_state, sl_core_link_state_str(link_state));
+		spin_unlock(&core_link->link.data_lock);
+		return -EBADRQC;
+	}
+}
+
+int sl_core_link_down_request(u8 ldev_num, u8 lgrp_num, u8 link_num,
+			      sl_core_link_down_callback_t callback, void *tag,
+			      u64 down_cause_map, bool *accepted)
+{
+	enum sl_core_link_state link_state;
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+
+	*accepted = false;
+	core_link = sl_core_link_get(ldev_num, lgrp_num, link_num);
+	if (!core_link)
+		return -ENODEV;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "down");
+
+	if (!callback) {
+		sl_core_log_err_trace(core_link, LOG_NAME, "down - NULL callback");
+		return -EINVAL;
+	}
+
+	spin_lock(&core_link->link.data_lock);
+	link_state = core_link->link.state;
+	switch (link_state) {
+	case SL_CORE_LINK_STATE_CANCELING:
+	case SL_CORE_LINK_STATE_GOING_DOWN:
+	case SL_CORE_LINK_STATE_TIMEOUT:
+		sl_core_log_dbg(core_link, LOG_NAME, "down - already going down");
+		spin_unlock(&core_link->link.data_lock);
+		return 0;
+	case SL_CORE_LINK_STATE_UP:
+		sl_core_log_dbg(core_link, LOG_NAME, "down - going down");
+		spin_unlock(&core_link->link.data_lock);
+		sl_core_data_link_last_down_cause_map_set(core_link, down_cause_map);
+		spin_lock(&core_link->link.data_lock);
+		if (core_link->link.state != SL_CORE_LINK_STATE_UP) {
+			spin_unlock(&core_link->link.data_lock);
+			return 0;
+		}
+		core_link->link.tags.down      = tag;
+		core_link->link.callbacks.down = callback;
+		core_link->link.state          = SL_CORE_LINK_STATE_GOING_DOWN;
+		if (!queue_work(core_link->core_lgrp->core_ldev->workqueue,
+				&core_link->work[SL_CORE_WORK_LINK_DOWN])) {
+			core_link->link.state = SL_CORE_LINK_STATE_UP;
+			core_link->link.tags.down = NULL;
+			core_link->link.callbacks.down = NULL;
+			spin_unlock(&core_link->link.data_lock);
+			return -EBUSY;
+		}
+		*accepted = true;
+		spin_unlock(&core_link->link.data_lock);
+		sl_media_jack_led_set(core_link->core_lgrp->core_ldev->num, core_link->core_lgrp->num);
+		return 0;
+	default:
+		sl_core_log_err(core_link, LOG_NAME,
+				"down - invalid (link_state = %u %s)",
+			link_state, sl_core_link_state_str(link_state));
+		spin_unlock(&core_link->link.data_lock);
+		return -EBADRQC;
+	}
+}
+
+int sl_core_link_down(u8 ldev_num, u8 lgrp_num, u8 link_num,
+		      sl_core_link_down_callback_t callback, void *tag, u64 down_cause_map)
+{
+	bool accepted;
+
+	return sl_core_link_down_request(ldev_num, lgrp_num, link_num, callback,
+					tag, down_cause_map, &accepted);
+}
+
+int sl_core_link_reset(u8 ldev_num, u8 lgrp_num, u8 link_num)
+{
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+
+	core_link = sl_core_link_get(ldev_num, lgrp_num, link_num);
+	if (!core_link)
+		return 0;
+
+	sl_core_hw_reset_link(core_link);
+
+	return 0;
+}
+
+int sl_core_link_state_get(u8 ldev_num, u8 lgrp_num, u8 link_num,
+			   enum sl_core_link_state *link_state)
+{
+	int                  rtn;
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+
+	core_link = sl_core_link_get(ldev_num, lgrp_num, link_num);
+	if (!core_link)
+		return -ENODEV;
+
+	rtn = sl_core_data_link_state_get(core_link, link_state);
+	if (rtn) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "state get - failed to get link state [%d]", rtn);
+		return rtn;
+	}
+
+	sl_core_log_dbg(core_link, LOG_NAME, "state get (link_state = %u %s)",
+			*link_state, sl_core_link_state_str(*link_state));
+
+	return 0;
+}
+
+u64 sl_core_link_info_map_get(u8 ldev_num, u8 lgrp_num, u8 link_num)
+{
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+	u64                  info_map;
+
+	core_link = sl_core_link_get(ldev_num, lgrp_num, link_num);
+	if (!core_link)
+		return 0;
+
+	info_map = sl_core_data_link_info_map_get(core_link);
+
+	sl_core_log_dbg(core_link, LOG_NAME, "info map get (map = 0x%llX)", info_map);
+
+	return info_map;
+}
+
+int sl_core_info_map_get(u8 ldev_num, u8 lgrp_num, u8 link_num, u64 *info_map)
+{
+	int                  rtn = 0;
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+	struct sl_core_mac  *core_mac;
+	struct sl_core_llr  *core_llr;
+	u64                  llr_info_map;
+
+	BUILD_BUG_ON(SL_CORE_INFO_MAP_NUM_BITS >= 64);
+
+	core_link = sl_core_link_get(ldev_num, lgrp_num, link_num);
+	if (!core_link)
+		return -ENODEV;
+	core_mac  = sl_core_mac_get(ldev_num, lgrp_num, link_num);
+
+	*info_map = sl_core_data_link_info_map_get(core_link);
+	if (core_mac)
+		*info_map |= sl_core_data_mac_info_map_get(core_mac);
+
+	core_llr  = sl_core_llr_get(ldev_num, lgrp_num, link_num);
+	if (!core_llr)
+		goto out;
+
+	rtn = sl_core_data_llr_info_map_get(core_llr, &llr_info_map);
+	if (rtn) {
+		sl_core_log_dbg(core_link, LOG_NAME,
+				"info map get - llr info map get failed (rtn = %d)", rtn);
+		goto out;
+	}
+
+	*info_map |= llr_info_map;
+
+out:
+	sl_core_log_dbg(core_link, LOG_NAME, "info map get (map = 0x%llX)", *info_map);
+
+	return rtn;
+}
+
+int sl_core_link_config_set(u8 ldev_num, u8 lgrp_num, u8 link_num,
+			    struct sl_core_link_config *link_config)
+{
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+	enum sl_core_link_state link_state;
+
+	core_link = sl_core_link_get(ldev_num, lgrp_num, link_num);
+	if (!core_link)
+		return -ENODEV;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "config set");
+
+	spin_lock(&core_link->link.data_lock);
+	link_state = core_link->link.state;
+	switch (link_state) {
+	case SL_CORE_LINK_STATE_UNCONFIGURED:
+	case SL_CORE_LINK_STATE_CONFIGURED:
+	case SL_CORE_LINK_STATE_DOWN:
+		core_link->link.state = SL_CORE_LINK_STATE_CONFIGURING;
+		spin_unlock(&core_link->link.data_lock);
+		sl_core_data_link_config_set(core_link, link_config);
+		return 0;
+	default:
+		sl_core_log_err(core_link, LOG_NAME,
+				"config set invalid (link_state = %u %s)",
+			link_state, sl_core_link_state_str(link_state));
+		spin_unlock(&core_link->link.data_lock);
+		return -EBADRQC;
+	}
+}
+
+bool sl_core_link_config_is_enable_ald_set(struct sl_core_link *core_link)
+{
+	bool is_config_set;
+
+	spin_lock(&core_link->serdes.data_lock);
+	is_config_set = is_flag_set(core_link->config.flags, SL_LINK_CONFIG_OPT_ALD_ENABLE);
+	spin_unlock(&core_link->serdes.data_lock);
+
+	return is_config_set;
+}
+
+bool sl_core_link_is_degrade_state_active(struct sl_core_link *core_link)
+{
+	u32 degrade_state;
+
+	spin_lock(&core_link->data_lock);
+	degrade_state = core_link->degrade_state;
+	spin_unlock(&core_link->data_lock);
+
+	return degrade_state == SL_LINK_DEGRADE_STATE_ACTIVE;
+}
+
+bool sl_core_link_config_is_enable_pml_recovery_set(struct sl_core_link *core_link)
+{
+	bool is_config_set;
+
+	spin_lock(&core_link->serdes.data_lock);
+	is_config_set = is_flag_set(core_link->config.flags, SL_LINK_CONFIG_OPT_PML_REC_ENABLE);
+	spin_unlock(&core_link->serdes.data_lock);
+
+	return is_config_set;
+}
+
+bool sl_core_link_is_pml_recovery_running(struct sl_core_link *core_link)
+{
+	if (atomic_read(&core_link->pml_rec.pml_rec_running) == 1) {
+		sl_core_log_err_trace(core_link, LOG_NAME, "pml recovery already running");
+		return true;
+	}
+
+	return false;
+}
+
+const char *sl_core_link_pml_rec_down_cause_str(u8 down_cause)
+{
+	switch (down_cause) {
+	case PML_REC_DOWN_CAUSE_INVALID:
+		return "invalid";
+	case PML_REC_DOWN_CAUSE_LINK_DOWN:
+		return "link-down";
+	case PML_REC_DOWN_CAUSE_LOCAL_FAULT:
+		return "local-fault";
+	case PML_REC_DOWN_CAUSE_REMOTE_FAULT:
+		return "remote-fault";
+	default:
+		return "unknown";
+	}
+}
+
+int sl_core_link_policy_set(u8 ldev_num, u8 lgrp_num, u8 link_num, struct sl_core_link_policy *link_policy)
+{
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+
+	core_link = sl_core_link_get(ldev_num, lgrp_num, link_num);
+	if (!core_link)
+		return -ENODEV;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "policy set");
+
+	spin_lock(&core_link->link.data_lock);
+	core_link->policy = *link_policy;
+	spin_unlock(&core_link->link.data_lock);
+
+	return 0;
+}
+
+int sl_core_link_caps_get(u8 ldev_num, u8 lgrp_num, u8 link_num, struct sl_link_caps *link_caps)
+{
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+
+	core_link = sl_core_link_get(ldev_num, lgrp_num, link_num);
+	if (!core_link)
+		return -ENODEV;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "caps get");
+
+	*link_caps = core_link->core_lgrp->link_caps[core_link->num];
+
+	return 0;
+}
+
+int sl_core_link_is_canceled_or_timed_out(struct sl_core_link *core_link, bool *is_canceled_or_timed_out)
+{
+	int  rtn;
+	u32  state;
+
+	rtn = sl_core_data_link_state_get(core_link, &state);
+	if (rtn) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "is canceled or timed out - failed to get link state [%d]", rtn);
+		return rtn;
+	}
+
+	sl_core_log_dbg(core_link, LOG_NAME, "is_canceled_or_timed_out (state %u %s)",
+			state, sl_core_link_state_str(state));
+
+	*is_canceled_or_timed_out = ((state == SL_CORE_LINK_STATE_CANCELING) || (state == SL_CORE_LINK_STATE_TIMEOUT));
+
+	sl_core_log_dbg(core_link, LOG_NAME, "get (is_canceled_or_timed_out = %s)",
+			*is_canceled_or_timed_out ? "true" : "false");
+
+	return 0;
+}
+
+int sl_core_link_speed_get(u8 ldev_num, u8 lgrp_num, u8 link_num, u32 *link_speed)
+{
+	struct sl_core_link *held_link_1 __free(sl_core_link_put) = NULL;
+	held_link_1 = sl_core_link_get(ldev_num, lgrp_num, link_num);
+	if (!held_link_1)
+		return -ENODEV;
+	return sl_core_data_link_speed_get(held_link_1, link_speed);
+}
+
+int sl_core_link_clocking_get(struct sl_core_link *core_link, u16 *clocking)
+{
+	*clocking = sl_core_data_link_clocking_get(core_link);
+
+	return 0;
+}
+
+int sl_core_link_last_down_cause_map_info_get(u8 ldev_num, u8 lgrp_num, u8 link_num, u8 entry_num,
+					      u64 *down_cause_map, time64_t *down_time)
+{
+	struct sl_core_link *held_link_1 __free(sl_core_link_put) = NULL;
+	held_link_1 = sl_core_link_get(ldev_num, lgrp_num, link_num);
+	if (!held_link_1)
+		return -ENODEV;
+	return sl_core_data_link_last_down_cause_map_info_get(held_link_1,
+							      entry_num, down_cause_map, down_time);
+}
+
+void sl_core_link_last_up_fail_cause_map_set(u8 ldev_num, u8 lgrp_num, u8 link_num, u64 up_fail_cause_map)
+{
+	struct sl_core_link *held_link_1 __free(sl_core_link_put) = NULL;
+	held_link_1 = sl_core_link_get(ldev_num, lgrp_num, link_num);
+	if (!held_link_1)
+		return;
+	sl_core_data_link_last_up_fail_cause_map_set(held_link_1,
+						     up_fail_cause_map);
+}
+
+int  sl_core_link_last_up_fail_cause_map_info_get(u8 ldev_num, u8 lgrp_num, u8 link_num, u8 entry_num,
+						  u64 *up_fail_cause_map, time64_t *up_fail_time)
+{
+	struct sl_core_link *held_link_1 __free(sl_core_link_put) = NULL;
+	held_link_1 = sl_core_link_get(ldev_num, lgrp_num, link_num);
+	if (!held_link_1)
+		return -ENODEV;
+	return sl_core_data_link_last_up_fail_cause_map_info_get(held_link_1,
+						 entry_num, up_fail_cause_map, up_fail_time);
+}
+
+int sl_core_link_ucw_warn_limit_crossed_get(u8 ldev_num, u8 lgrp_num, u8 link_num, bool *is_limit_crossed,
+					    time64_t *limit_crossed_time)
+{
+	struct sl_core_link *held_link_1 __free(sl_core_link_put) = NULL;
+	held_link_1 = sl_core_link_get(ldev_num, lgrp_num, link_num);
+	if (!held_link_1)
+		return -ENODEV;
+	return sl_core_data_link_ucw_warn_limit_crossed_get(held_link_1,
+							    is_limit_crossed, limit_crossed_time);
+}
+
+void sl_core_link_ucw_warn_limit_crossed_set(u8 ldev_num, u8 lgrp_num, u8 link_num, bool is_limit_crossed)
+{
+	struct sl_core_link *held_link_1 __free(sl_core_link_put) = NULL;
+	held_link_1 = sl_core_link_get(ldev_num, lgrp_num, link_num);
+	if (!held_link_1)
+		return;
+	sl_core_data_link_ucw_warn_limit_crossed_set(held_link_1, is_limit_crossed);
+}
+
+int sl_core_link_ccw_warn_limit_crossed_get(u8 ldev_num, u8 lgrp_num, u8 link_num, bool *is_limit_crossed,
+					    time64_t *limit_crossed_time)
+{
+	struct sl_core_link *held_link_1 __free(sl_core_link_put) = NULL;
+	held_link_1 = sl_core_link_get(ldev_num, lgrp_num, link_num);
+	if (!held_link_1)
+		return -ENODEV;
+	return sl_core_data_link_ccw_warn_limit_crossed_get(held_link_1,
+							    is_limit_crossed, limit_crossed_time);
+}
+
+void sl_core_link_ccw_warn_limit_crossed_set(u8 ldev_num, u8 lgrp_num, u8 link_num, bool is_limit_crossed)
+{
+	struct sl_core_link *held_link_1 __free(sl_core_link_put) = NULL;
+	held_link_1 = sl_core_link_get(ldev_num, lgrp_num, link_num);
+	if (!held_link_1)
+		return;
+	sl_core_data_link_ccw_warn_limit_crossed_set(held_link_1, is_limit_crossed);
+}
+
+bool sl_core_link_policy_is_keep_serdes_up_set(struct sl_core_link *core_link)
+{
+	bool is_policy_set;
+
+	spin_lock(&core_link->serdes.data_lock);
+	is_policy_set = (core_link->policy.options & SL_LINK_POLICY_OPT_KEEP_SERDES_UP) != 0;
+	spin_unlock(&core_link->serdes.data_lock);
+
+	return is_policy_set;
+}
+
+bool sl_core_link_policy_is_use_unsupported_cable_set(struct sl_core_link *core_link)
+{
+	bool is_policy_set;
+
+	spin_lock(&core_link->serdes.data_lock);
+	is_policy_set = is_flag_set(core_link->policy.options, SL_LINK_POLICY_OPT_USE_UNSUPPORTED_CABLE);
+	spin_unlock(&core_link->serdes.data_lock);
+
+	return is_policy_set;
+}
+
+bool sl_core_link_policy_is_use_supported_ss200_cable_set(struct sl_core_link *core_link)
+{
+	bool is_policy_set;
+
+	spin_lock(&core_link->serdes.data_lock);
+	is_policy_set = is_flag_set(core_link->policy.options, SL_LINK_POLICY_OPT_USE_SUPPORTED_SS200_CABLE);
+	spin_unlock(&core_link->serdes.data_lock);
+
+	return is_policy_set;
+}
+
+bool sl_core_link_policy_is_ignore_media_errors_set(struct sl_core_link *core_link)
+{
+	bool is_policy_set;
+
+	spin_lock(&core_link->serdes.data_lock);
+	is_policy_set = is_flag_set(core_link->policy.options, SL_LINK_POLICY_OPT_IGNORE_MEDIA_ERROR);
+	spin_unlock(&core_link->serdes.data_lock);
+
+	return is_policy_set;
+}
+
+struct sl_core_link_up_info *sl_core_link_up_info_get(struct sl_core_link *core_link,
+						      struct sl_core_link_up_info *link_up_info)
+{
+	spin_lock(&core_link->link.data_lock);
+	link_up_info->state     = core_link->link.state;
+	link_up_info->info_map  = core_link->info_map;
+	link_up_info->speed     = core_link->pcs.settings.speed;
+	link_up_info->fec_mode  = core_link->fec.settings.mode;
+	link_up_info->fec_type  = core_link->fec.settings.type;
+	spin_unlock(&core_link->link.data_lock);
+	link_up_info->cause_map = sl_core_data_link_last_up_fail_cause_map_get(core_link);
+
+	return link_up_info;
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/sl_core_link_an.c b/drivers/net/ethernet/hpe/sl/core/sl_core_link_an.c
new file mode 100644
index 000000000000..eb69fd41d10a
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/sl_core_link_an.c
@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2022-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/spinlock.h>
+#include <linux/slab.h>
+
+#include "data/sl_core_data_link.h"
+#include "sl_core_link.h"
+#include "sl_core_str.h"
+#include "base/sl_core_log.h"
+#include "data/sl_core_data_link.h"
+#include "hw/sl_core_hw_an_lp.h"
+#include "hw/sl_core_hw_an.h"
+
+#define LOG_NAME SL_CORE_LINK_AN_LOG_NAME
+
+int sl_core_link_an_lp_caps_get(u8 ldev_num, u8 lgrp_num, u8 link_num,
+				sl_core_link_an_callback_t callback, void *tag, struct sl_link_caps *caps,
+	u32 timeout_ms, u32 flags)
+{
+	enum sl_core_link_state link_state;
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+
+	core_link = sl_core_link_get(ldev_num, lgrp_num, link_num);
+	if (!core_link)
+		return -ENODEV;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "lp caps get");
+
+	spin_lock(&core_link->link.data_lock);
+	link_state = core_link->link.state;
+	switch (link_state) {
+	case SL_CORE_LINK_STATE_UNCONFIGURED:
+	case SL_CORE_LINK_STATE_CONFIGURED:
+	case SL_CORE_LINK_STATE_DOWN:
+		core_link->link.state = SL_CORE_LINK_STATE_AN;
+		spin_unlock(&core_link->link.data_lock);
+		sl_core_hw_an_lp_caps_get_cmd(core_link, link_state, callback, tag, caps, timeout_ms, flags);
+		return 0;
+	default:
+		sl_core_log_err(core_link, LOG_NAME,
+				"lp caps get - invalid (link_state = %u %s)",
+			link_state, sl_core_link_state_str(link_state));
+		spin_unlock(&core_link->link.data_lock);
+		return -EBADRQC;
+	}
+}
+
+u32 sl_core_link_an_lp_caps_state_get(u8 ldev_num, u8 lgrp_num, u8 link_num)
+{
+	struct sl_core_link *held_link_1 __free(sl_core_link_put) = NULL;
+	held_link_1 = sl_core_link_get(ldev_num, lgrp_num, link_num);
+	if (!held_link_1)
+		return 0;
+	return sl_core_data_link_an_lp_caps_state_get(held_link_1);
+}
+
+int sl_core_link_an_lp_caps_stop(u8 ldev_num, u8 lgrp_num, u8 link_num)
+{
+	int                  rtn;
+	enum sl_core_link_state link_state;
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+
+	core_link = sl_core_link_get(ldev_num, lgrp_num, link_num);
+	if (!core_link)
+		return -ENODEV;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "lp caps stop");
+
+	rtn = sl_core_data_link_state_get(core_link, &link_state);
+	if (rtn) {
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "lp caps stop - failed to get link state [%d]", rtn);
+		return rtn;
+	}
+
+	switch (link_state) {
+	case SL_CORE_LINK_STATE_UNCONFIGURED:
+	case SL_CORE_LINK_STATE_CONFIGURED:
+	case SL_CORE_LINK_STATE_DOWN:
+		return 0;
+	case SL_CORE_LINK_STATE_AN:
+		sl_core_hw_an_lp_caps_stop_cmd(core_link);
+		return 0;
+	case SL_CORE_LINK_STATE_UP:
+		sl_core_log_dbg(core_link, LOG_NAME, "lp caps stop - link is up");
+		return 0;
+	case SL_CORE_LINK_STATE_GOING_UP:
+	case SL_CORE_LINK_STATE_GOING_DOWN:
+	case SL_CORE_LINK_STATE_TIMEOUT:
+		sl_core_log_dbg(core_link, LOG_NAME, "lp caps stop - in transition");
+		return 0;
+	default:
+		sl_core_log_err(core_link, LOG_NAME,
+				"lp caps stop - invalid (link_state = %u %s)",
+			link_state, sl_core_link_state_str(link_state));
+		return -EBADRQC;
+	}
+}
+
+int sl_core_link_an_fail_cause_get(u8 ldev_num, u8 lgrp_num, u8 link_num, u32 *fail_cause, time64_t *fail_time)
+{
+	struct sl_core_link *held_link_1 __free(sl_core_link_put) = NULL;
+	held_link_1 = sl_core_link_get(ldev_num, lgrp_num, link_num);
+	if (!held_link_1)
+		return -ENODEV;
+	return sl_core_data_link_an_fail_cause_get(held_link_1, fail_cause, fail_time);
+}
+
+u32 sl_core_link_an_retry_count_get(u8 ldev_num, u8 lgrp_num, u8 link_num)
+{
+	struct sl_core_link *held_link_1 __free(sl_core_link_put) = NULL;
+	held_link_1 = sl_core_link_get(ldev_num, lgrp_num, link_num);
+	if (!held_link_1)
+		return 0;
+	return sl_core_data_link_an_retry_count_get(held_link_1);
+}
+
+const char *sl_core_link_an_fail_cause_str(u32 fail_cause)
+{
+	switch (fail_cause) {
+	case SL_CORE_HW_AN_FAIL_CAUSE_LP_CAPS_SERDES_LINK_UP_FAIL:
+		return "lp-caps-serdes-link-up-fail";
+	case SL_CORE_HW_AN_FAIL_CAUSE_LP_CAPS_NOT_COMPLETE:
+		return "lp-caps-not-complete";
+	case SL_CORE_HW_AN_FAIL_CAUSE_NOT_COMPLETE:
+		return "not-complete";
+	case SL_CORE_HW_AN_FAIL_CAUSE_PAGES_DECODE_FAIL:
+		return "pages-decode-fail";
+	case SL_CORE_HW_AN_FAIL_CAUSE_TEST_CAPS_NOMATCH:
+		return "test-caps-nomatch";
+	case SL_CORE_HW_AN_FAIL_CAUSE_SERDES_LINK_UP_FAIL:
+		return "serdes-link-up-fail";
+	case SL_CORE_HW_AN_FAIL_CAUSE_BP_STORE_STATE_BAD:
+		return "bp-store-state-bad";
+	case SL_CORE_HW_AN_FAIL_CAUSE_BP_STORE_LP_ABILITY_NOT_SET:
+		return "bp-store-lp-ability-not-set";
+	case SL_CORE_HW_AN_FAIL_CAUSE_BP_STORE_STATE_ERROR:
+		return "bp-store-state-error";
+	case SL_CORE_HW_AN_FAIL_CAUSE_BP_STORE_BP_NOT_SET:
+		return "bp-store-bp-not-set";
+	case SL_CORE_HW_AN_FAIL_CAUSE_BP_SEND_INTR_ENABLE_FAIL:
+		return "bp-send-intr-enable-fail";
+	case SL_CORE_HW_AN_FAIL_CAUSE_NP_STORE_STATE_BAD:
+		return "np-store-state-bad";
+	case SL_CORE_HW_AN_FAIL_CAUSE_NP_STORE_BP_SET:
+		return "np-store-bp-set";
+	case SL_CORE_HW_AN_FAIL_CAUSE_NP_CHECK_STATE_BAD:
+		return "np-check-state-bad";
+	case SL_CORE_HW_AN_FAIL_CAUSE_INTR_STATE_INVALID:
+		return "intr-state-invalid";
+	case SL_CORE_HW_AN_FAIL_CAUSE_INTR_AN_RETRY_NP_SEND_FAIL:
+		return "intr-an-retry-np-send-fail";
+	case SL_CORE_HW_AN_FAIL_CAUSE_INTR_OUT_OF_PAGES:
+		return "intr-out-of-pages";
+	case SL_CORE_HW_AN_FAIL_CAUSE_INTR_NP_SEND_FAIL:
+		return "intr-np-send-fail";
+	case SL_CORE_HW_AN_FAIL_CAUSE_PAGES_DECODE_NO_BP:
+		return "pages-decode-no-bp";
+	case SL_CORE_HW_AN_FAIL_CAUSE_PAGES_DECODE_OUI_INVALID:
+		return "pages-decode-oui-invalid";
+	default:
+		return "unknown";
+	}
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/sl_core_link_fec.c b/drivers/net/ethernet/hpe/sl/core/sl_core_link_fec.c
new file mode 100644
index 000000000000..ed238cf830d0
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/sl_core_link_fec.c
@@ -0,0 +1,233 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2023-2026 Hewlett Packard Enterprise Development LP */
+
+#include "sl_core_link.h"
+#include "sl_core_str.h"
+#include "base/sl_core_log.h"
+#include "hw/sl_core_hw_fec.h"
+
+#define LOG_NAME SL_CORE_LINK_FEC_LOG_NAME
+
+static int sl_core_link_fec_cw_cntrs_get(struct sl_core_link *core_link,
+					 struct sl_core_link_fec_cw_cntrs *cw_cntrs)
+{
+	int rtn;
+	enum sl_core_link_state link_state;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "fec_cw_cntrs_get");
+
+	spin_lock(&core_link->data_lock);
+	link_state = core_link->link.state;
+	spin_unlock(&core_link->data_lock);
+	switch (link_state) {
+	case SL_CORE_LINK_STATE_UP:
+		rtn = sl_core_hw_fec_cw_cntrs_get(core_link, cw_cntrs);
+		if (rtn) {
+			sl_core_log_err_trace(core_link, LOG_NAME,
+					      "fec_cw_cntrs_get failed (link_state = %u %s) [%d]",
+					      link_state, sl_core_link_state_str(link_state), rtn);
+			return rtn;
+		}
+		sl_core_log_dbg(core_link, LOG_NAME,
+				"fec_cw_cntrs_get (ccw = %llu, ucw = %llu, gcw = %llu)",
+				cw_cntrs->ccw, cw_cntrs->ucw, cw_cntrs->gcw);
+		return 0;
+	default:
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "fec_cw_cntrs_get incorrect state (link_state = %u %s)",
+				      link_state, sl_core_link_state_str(link_state));
+		return -ENOLINK;
+	}
+}
+
+static int sl_core_link_fec_lane_cntrs_get(struct sl_core_link *core_link,
+					   struct sl_core_link_fec_lane_cntrs *lane_cntrs)
+{
+	int rtn;
+	enum sl_core_link_state link_state;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "fec_lane_cntrs_get");
+
+	spin_lock(&core_link->data_lock);
+	link_state = core_link->link.state;
+	spin_unlock(&core_link->data_lock);
+	switch (link_state) {
+	case SL_CORE_LINK_STATE_UP:
+		rtn = sl_core_hw_fec_lane_cntrs_get(core_link, lane_cntrs);
+		if (rtn) {
+			sl_core_log_err_trace(core_link, LOG_NAME,
+					      "fec_lane_cntrs_get failed (link_state = %u %s) [%d]",
+					      link_state, sl_core_link_state_str(link_state), rtn);
+			return rtn;
+		}
+		sl_core_log_dbg(core_link, LOG_NAME,
+				"fec_lane_cntrs_get (lane0 = %llu, lane1 = %llu, lane2 = %llu, lane3 = %llu)",
+				lane_cntrs->lanes[0], lane_cntrs->lanes[1],
+				lane_cntrs->lanes[2], lane_cntrs->lanes[3]);
+		return 0;
+	default:
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "fec_lane_cntrs_get incorrect state (link_state = %u %s)",
+				      link_state, sl_core_link_state_str(link_state));
+		return -ENOLINK;
+	}
+}
+
+static int sl_core_link_fec_tail_cntrs_get(struct sl_core_link *core_link,
+					   struct sl_core_link_fec_tail_cntrs *tail_cntrs)
+{
+	int rtn;
+	enum sl_core_link_state link_state;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "fec_tail_cntrs_get");
+
+	spin_lock(&core_link->data_lock);
+	link_state = core_link->link.state;
+	spin_unlock(&core_link->data_lock);
+	switch (link_state) {
+	case SL_CORE_LINK_STATE_UP:
+		rtn = sl_core_hw_fec_tail_cntrs_get(core_link, tail_cntrs);
+		if (rtn) {
+			sl_core_log_err_trace(core_link, LOG_NAME,
+					      "fec_tail_cntrs_get failed (link_state = %u %s) [%d]",
+					      link_state, sl_core_link_state_str(link_state), rtn);
+			return rtn;
+		}
+		sl_core_log_dbg(core_link, LOG_NAME,
+				"fec_tail_cntrs_get (ccw_bin0 = %llu, ccw_bin1 = %llu, ccw_bin2 = %llu, ccw_bin3 = %llu)",
+				tail_cntrs->ccw_bins[0], tail_cntrs->ccw_bins[1],
+				tail_cntrs->ccw_bins[2], tail_cntrs->ccw_bins[3]);
+		sl_core_log_dbg(core_link, LOG_NAME,
+				"fec_tail_cntrs_get (ccw_bin4 = %llu, ccw_bin5 = %llu, ccw_bin6 = %llu, ccw_bin7 = %llu)",
+				tail_cntrs->ccw_bins[4], tail_cntrs->ccw_bins[5],
+				tail_cntrs->ccw_bins[6], tail_cntrs->ccw_bins[7]);
+		return 0;
+	default:
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "fec_tail_cntrs_get incorrect state (link_state = %u %s)",
+				      link_state, sl_core_link_state_str(link_state));
+		return -ENOLINK;
+	}
+}
+
+int sl_core_link_fec_ccw_get(struct sl_core_link *core_link, u64 *ccw)
+{
+	int                              rtn;
+	struct sl_core_link_fec_cw_cntrs cw_cntrs;
+
+	rtn = sl_core_link_fec_cw_cntrs_get(core_link, &cw_cntrs);
+	if (rtn) {
+		sl_core_log_err_trace(core_link, LOG_NAME, "fec_ccw_get failed [%d]", rtn);
+		return rtn;
+	}
+
+	*ccw = cw_cntrs.ccw;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "fec_ccw_get (ccw = %llu)", *ccw);
+
+	return 0;
+}
+
+int sl_core_link_fec_ucw_get(struct sl_core_link *core_link, u64 *ucw)
+{
+	int                              rtn;
+	struct sl_core_link_fec_cw_cntrs cw_cntrs;
+
+	rtn = sl_core_link_fec_cw_cntrs_get(core_link, &cw_cntrs);
+	if (rtn) {
+		sl_core_log_err_trace(core_link, LOG_NAME, "fec_ucw_get failed [%d]", rtn);
+		return rtn;
+	}
+
+	*ucw = cw_cntrs.ucw;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "fec_ucw_get (ucw = %llu)", *ucw);
+
+	return 0;
+}
+
+int sl_core_link_fec_gcw_get(struct sl_core_link *core_link, u64 *gcw)
+{
+	int                              rtn;
+	struct sl_core_link_fec_cw_cntrs cw_cntrs;
+
+	rtn = sl_core_link_fec_cw_cntrs_get(core_link, &cw_cntrs);
+	if (rtn) {
+		sl_core_log_err_trace(core_link, LOG_NAME, "fec_gcw_get failed [%d]", rtn);
+		return rtn;
+	}
+
+	*gcw = cw_cntrs.gcw;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "fec_gcw_get (gcw = %llu)", *gcw);
+
+	return 0;
+}
+
+int sl_core_link_fec_lane_cntr_get(struct sl_core_link *core_link, u8 lane_num, u64 *lane_cntr)
+{
+	int                                rtn;
+	struct sl_core_link_fec_lane_cntrs lane_cntrs;
+
+	rtn = sl_core_link_fec_lane_cntrs_get(core_link, &lane_cntrs);
+	if (rtn) {
+		sl_core_log_err_trace(core_link, LOG_NAME, "fec_lane_cntr_get failed [%d]", rtn);
+		return rtn;
+	}
+
+	*lane_cntr = lane_cntrs.lanes[lane_num];
+
+	sl_core_log_dbg(core_link, LOG_NAME, "fec_lane_cntr_get (lane %u = %llu)", lane_num, *lane_cntr);
+
+	return 0;
+}
+
+int sl_core_link_fec_tail_cntr_get(struct sl_core_link *core_link, u8 tail_cntr_num, u64 *tail_cntr)
+{
+	int                               rtn;
+	struct sl_core_link_fec_tail_cntrs tail_cntrs;
+
+	rtn = sl_core_link_fec_tail_cntrs_get(core_link, &tail_cntrs);
+	if (rtn) {
+		sl_core_log_err_trace(core_link, LOG_NAME, "fec_tail_cntr_get failed [%d]", rtn);
+		return rtn;
+	}
+
+	*tail_cntr = tail_cntrs.ccw_bins[tail_cntr_num];
+
+	sl_core_log_dbg(core_link, LOG_NAME,
+			"fec_tail_cntr_get (tail_cntr %u = %llu)", tail_cntr_num, *tail_cntr);
+
+	return 0;
+}
+
+int sl_core_link_fec_data_get(struct sl_core_link *core_link,
+			      struct sl_core_link_fec_cw_cntrs *cw_cntrs,
+			      struct sl_core_link_fec_lane_cntrs *lane_cntrs,
+			      struct sl_core_link_fec_tail_cntrs *tail_cntr)
+{
+	int rtn;
+	enum sl_core_link_state link_state;
+
+	sl_core_log_dbg(core_link, LOG_NAME, "fec_data_get");
+
+	spin_lock(&core_link->data_lock);
+	link_state = core_link->link.state;
+	spin_unlock(&core_link->data_lock);
+	switch (link_state) {
+	case SL_CORE_LINK_STATE_UP:
+		rtn = sl_core_hw_fec_data_get(core_link, cw_cntrs, lane_cntrs, tail_cntr);
+		if (rtn) {
+			sl_core_log_err_trace(core_link, LOG_NAME,
+					      "fec_data_get failed (link_state = %u %s) [%d]",
+					      link_state, sl_core_link_state_str(link_state), rtn);
+			return rtn;
+		}
+		return 0;
+	default:
+		sl_core_log_err_trace(core_link, LOG_NAME,
+				      "fec_data_get incorrect state (link_state = %u %s)",
+				      link_state, sl_core_link_state_str(link_state));
+		return -ENOLINK;
+	}
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/sl_core_llr.c b/drivers/net/ethernet/hpe/sl/core/sl_core_llr.c
new file mode 100644
index 000000000000..a099770cb8e6
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/sl_core_llr.c
@@ -0,0 +1,350 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2022,2023,2024,2025,2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/spinlock.h>
+#include <linux/slab.h>
+
+#include "base/sl_core_log.h"
+#include "sl_core_llr.h"
+#include "sl_core_str.h"
+#include "data/sl_core_data_llr.h"
+#include "hw/sl_core_hw_llr.h"
+
+#define LOG_NAME SL_CORE_LLR_LOG_NAME
+
+int sl_core_llr_new(u8 ldev_num, u8 lgrp_num, u8 llr_num)
+{
+	return sl_core_data_llr_new(ldev_num, lgrp_num, llr_num);
+}
+
+void sl_core_llr_del(u8 ldev_num, u8 lgrp_num, u8 llr_num)
+{
+	sl_core_data_llr_del(ldev_num, lgrp_num, llr_num);
+}
+
+struct sl_core_llr *sl_core_llr_get(u8 ldev_num, u8 lgrp_num, u8 llr_num)
+{
+	return sl_core_data_llr_get(ldev_num, lgrp_num, llr_num);
+}
+
+int sl_core_llr_config_set(u8 ldev_num, u8 lgrp_num, u8 llr_num, struct sl_llr_config *llr_config)
+{
+	int                 rtn;
+	struct sl_core_llr *core_llr;
+	enum sl_core_llr_state llr_state;
+
+	core_llr = sl_core_llr_get(ldev_num, lgrp_num, llr_num);
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "config set");
+
+	spin_lock(&core_llr->data_lock);
+	llr_state = core_llr->state;
+	switch (llr_state) {
+	case SL_CORE_LLR_STATE_NEW:
+	case SL_CORE_LLR_STATE_CONFIGURED:
+		rtn = sl_core_data_llr_config_set(core_llr, llr_config);
+		if (rtn) {
+			sl_core_log_err_trace(core_llr, LOG_NAME, "config set - llr_config_set failed [%d]", rtn);
+			spin_unlock(&core_llr->data_lock);
+			return rtn;
+		}
+		core_llr->state = SL_CORE_LLR_STATE_CONFIGURED;
+		spin_unlock(&core_llr->data_lock);
+		return 0;
+	default:
+		sl_core_log_err(core_llr, LOG_NAME, "config set - invalid (llr_state = %u %s)",
+				llr_state, sl_core_llr_state_str(llr_state));
+		spin_unlock(&core_llr->data_lock);
+		return -EBADRQC;
+	}
+}
+
+int sl_core_llr_policy_set(u8 ldev_num, u8 lgrp_num, u8 llr_num, struct sl_llr_policy *llr_policy)
+{
+	int                 rtn;
+	struct sl_core_llr *core_llr;
+
+	core_llr = sl_core_llr_get(ldev_num, lgrp_num, llr_num);
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "policy set");
+
+	rtn = sl_core_data_llr_policy_set(core_llr, llr_policy);
+	if (rtn) {
+		sl_core_log_err_trace(core_llr, LOG_NAME, "policy set - llr_policy_set failed [%d]", rtn);
+		return rtn;
+	}
+	return 0;
+}
+
+int sl_core_llr_policy_get(u8 ldev_num, u8 lgrp_num, u8 llr_num, struct sl_llr_policy *llr_policy)
+{
+	struct sl_core_llr *core_llr;
+
+	core_llr = sl_core_llr_get(ldev_num, lgrp_num, llr_num);
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "policy get");
+
+	return sl_core_data_llr_policy_get(core_llr, llr_policy);
+}
+
+int sl_core_llr_setup(u8 ldev_num, u8 lgrp_num, u8 llr_num,
+		      sl_core_llr_setup_callback_t callback, void *tag, u32 flags)
+{
+	int                 rtn;
+	enum sl_core_llr_state llr_state;
+	struct sl_core_llr *core_llr;
+
+	core_llr = sl_core_llr_get(ldev_num, lgrp_num, llr_num);
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "setup");
+
+	spin_lock(&core_llr->data_lock);
+	llr_state = core_llr->state;
+	switch (llr_state) {
+	case SL_CORE_LLR_STATE_SETUP:
+		sl_core_log_dbg(core_llr, LOG_NAME, "setup - already setup");
+		spin_unlock(&core_llr->data_lock);
+		return -EALREADY;
+	case SL_CORE_LLR_STATE_CONFIGURED:
+		sl_core_log_dbg(core_llr, LOG_NAME, "setup - in configured");
+		core_llr->state = SL_CORE_LLR_STATE_SETTING_UP;
+		spin_unlock(&core_llr->data_lock);
+		rtn = sl_core_data_llr_settings(core_llr);
+		if (rtn) {
+			sl_core_log_err_trace(core_llr, LOG_NAME,
+					      "setup - llr_settings failed [%d]", rtn);
+			return -EBADRQC;
+		}
+		sl_core_hw_llr_setup_cmd(core_llr, callback, tag, flags);
+		return 0;
+	default:
+		sl_core_log_err(core_llr, LOG_NAME,
+				"setup - invalid (llr_state = %u %s)",
+				llr_state, sl_core_llr_state_str(llr_state));
+		spin_unlock(&core_llr->data_lock);
+		return -EBADRQC;
+	}
+}
+
+int sl_core_llr_start(u8 ldev_num, u8 lgrp_num, u8 llr_num,
+		      sl_core_llr_start_callback_t callback, void *tag, u32 flags)
+{
+	enum sl_core_llr_state llr_state;
+	struct sl_core_llr *core_llr;
+
+	core_llr = sl_core_llr_get(ldev_num, lgrp_num, llr_num);
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "start");
+
+	spin_lock(&core_llr->data_lock);
+	llr_state = core_llr->state;
+	switch (llr_state) {
+	case SL_CORE_LLR_STATE_RUNNING:
+		sl_core_log_dbg(core_llr, LOG_NAME, "start - already started");
+		spin_unlock(&core_llr->data_lock);
+		return -EALREADY;
+	case SL_CORE_LLR_STATE_SETUP:
+		sl_core_log_dbg(core_llr, LOG_NAME, "start - in setup");
+		core_llr->state = SL_CORE_LLR_STATE_STARTING;
+		spin_unlock(&core_llr->data_lock);
+		sl_core_hw_llr_start_cmd(core_llr, callback, tag, flags);
+		return 0;
+	default:
+		sl_core_log_err(core_llr, LOG_NAME,
+				"start - invalid (llr_state = %u %s)",
+				llr_state, sl_core_llr_state_str(llr_state));
+		spin_unlock(&core_llr->data_lock);
+		return -EBADRQC;
+	}
+}
+
+int sl_core_llr_stop(u8 ldev_num, u8 lgrp_num, u8 llr_num)
+{
+	enum sl_core_llr_state llr_state;
+	struct sl_core_llr *core_llr;
+
+	core_llr = sl_core_llr_get(ldev_num, lgrp_num, llr_num);
+	if (!core_llr)
+		return 0;
+
+	spin_lock(&core_llr->data_lock);
+	llr_state = core_llr->state;
+	sl_core_log_dbg(core_llr, LOG_NAME, "stop (state = %u)", core_llr->state);
+	switch (llr_state) {
+	case SL_CORE_LLR_STATE_NEW:
+	case SL_CORE_LLR_STATE_CONFIGURED:
+		sl_core_log_dbg(core_llr, LOG_NAME, "stop - already off");
+		spin_unlock(&core_llr->data_lock);
+		return 0;
+	case SL_CORE_LLR_STATE_SETTING_UP:
+		sl_core_log_dbg(core_llr, LOG_NAME, "stop - cancel setting up");
+		core_llr->state = SL_CORE_LLR_STATE_SETUP_CANCELING;
+		spin_unlock(&core_llr->data_lock);
+		sl_core_data_llr_last_fail_cause_set(core_llr, SL_LLR_FAIL_CAUSE_CANCELED);
+		sl_core_hw_llr_settingup_cancel_cmd(core_llr);
+		return 0;
+	case SL_CORE_LLR_STATE_SETUP:
+		sl_core_log_dbg(core_llr, LOG_NAME, "stop - in setup");
+		core_llr->state = SL_CORE_LLR_STATE_SETUP_STOPPING;
+		spin_unlock(&core_llr->data_lock);
+		sl_core_data_llr_last_fail_cause_set(core_llr, SL_LLR_FAIL_CAUSE_COMMAND);
+		sl_core_hw_llr_setup_stop_cmd(core_llr);
+		return 0;
+	case SL_CORE_LLR_STATE_STARTING:
+		sl_core_log_dbg(core_llr, LOG_NAME, "stop - cancel starting");
+		core_llr->state = SL_CORE_LLR_STATE_START_CANCELING;
+		spin_unlock(&core_llr->data_lock);
+		sl_core_data_llr_last_fail_cause_set(core_llr, SL_LLR_FAIL_CAUSE_CANCELED);
+		sl_core_hw_llr_starting_cancel_cmd(core_llr);
+		return 0;
+	case SL_CORE_LLR_STATE_RUNNING:
+		sl_core_log_dbg(core_llr, LOG_NAME, "stop - in running");
+		core_llr->state = SL_CORE_LLR_STATE_STOPPING;
+		spin_unlock(&core_llr->data_lock);
+		sl_core_data_llr_last_fail_cause_set(core_llr, SL_LLR_FAIL_CAUSE_COMMAND);
+		sl_core_hw_llr_running_stop_cmd(core_llr);
+		return 0;
+	case SL_CORE_LLR_STATE_SETUP_CANCELING:
+	case SL_CORE_LLR_STATE_SETUP_STOPPING:
+	case SL_CORE_LLR_STATE_SETUP_TIMEOUT:
+	case SL_CORE_LLR_STATE_START_CANCELING:
+	case SL_CORE_LLR_STATE_STOPPING:
+	case SL_CORE_LLR_STATE_START_TIMEOUT:
+		sl_core_log_dbg(core_llr, LOG_NAME, "stop - waiting (llr_state = %u %s)",
+				llr_state, sl_core_llr_state_str(llr_state));
+		spin_unlock(&core_llr->data_lock);
+		return sl_core_hw_llr_stop_wait(core_llr);
+	default:
+		sl_core_log_err(core_llr, LOG_NAME,
+				"stop - invalid (llr_state = %u %s)",
+			llr_state, sl_core_llr_state_str(llr_state));
+		spin_unlock(&core_llr->data_lock);
+		return -EBADRQC;
+	}
+}
+
+int sl_core_llr_state_get(u8 ldev_num, u8 lgrp_num, u8 llr_num,
+			  enum sl_core_llr_state *llr_state)
+{
+	int                 rtn;
+	struct sl_core_llr *core_llr;
+
+	core_llr = sl_core_llr_get(ldev_num, lgrp_num, llr_num);
+
+	rtn = sl_core_data_llr_state_get(core_llr, llr_state);
+	if (rtn) {
+		sl_core_log_err(core_llr, LOG_NAME,
+				"state get - llr_state_get failed [%d]", rtn);
+		return rtn;
+	}
+
+	sl_core_log_dbg(core_llr, LOG_NAME, "state get (llr_state = %u %s)",
+			*llr_state, sl_core_llr_state_str(*llr_state));
+
+	return 0;
+}
+
+bool sl_core_llr_start_should_stop(struct sl_core_llr *core_llr)
+{
+	enum sl_core_llr_state llr_state;
+	bool start_should_stop;
+
+	spin_lock(&core_llr->data_lock);
+	llr_state = core_llr->state;
+	switch (llr_state) {
+	case SL_CORE_LLR_STATE_SETUP_CANCELING:
+	case SL_CORE_LLR_STATE_START_CANCELING:
+	case SL_CORE_LLR_STATE_SETUP_TIMEOUT:
+	case SL_CORE_LLR_STATE_START_TIMEOUT:
+	case SL_CORE_LLR_STATE_SETUP_STOPPING:
+	case SL_CORE_LLR_STATE_STOPPING:
+		start_should_stop = true;
+		sl_core_log_dbg(core_llr, LOG_NAME,
+				"start_should_stop = %s", start_should_stop ? "true" : "false");
+		spin_unlock(&core_llr->data_lock);
+		return start_should_stop;
+	default:
+		start_should_stop = false;
+		sl_core_log_dbg(core_llr, LOG_NAME,
+				"start_should_stop = %s", start_should_stop ? "true" : "false");
+		spin_unlock(&core_llr->data_lock);
+		return start_should_stop;
+	}
+}
+
+bool sl_core_llr_setup_should_stop(struct sl_core_llr *core_llr)
+{
+	enum sl_core_llr_state llr_state;
+	bool setup_should_stop;
+
+	spin_lock(&core_llr->data_lock);
+	llr_state = core_llr->state;
+	switch (llr_state) {
+	case SL_CORE_LLR_STATE_SETUP_CANCELING:
+	case SL_CORE_LLR_STATE_SETUP_TIMEOUT:
+	case SL_CORE_LLR_STATE_SETUP_STOPPING:
+		setup_should_stop = true;
+		sl_core_log_dbg(core_llr, LOG_NAME,
+				"setup_should_stop = %s", setup_should_stop ? "true" : "false");
+		spin_unlock(&core_llr->data_lock);
+		return setup_should_stop;
+	default:
+		setup_should_stop = false;
+		sl_core_log_dbg(core_llr, LOG_NAME,
+				"setup_should_stop = %s", setup_should_stop ? "true" : "false");
+		spin_unlock(&core_llr->data_lock);
+		return setup_should_stop;
+	}
+}
+
+bool sl_core_llr_should_stop(struct sl_core_llr *core_llr)
+{
+	enum sl_core_llr_state llr_state;
+	bool should_stop;
+
+	spin_lock(&core_llr->data_lock);
+	llr_state = core_llr->state;
+	switch (llr_state) {
+	case SL_CORE_LLR_STATE_SETUP_CANCELING:
+	case SL_CORE_LLR_STATE_START_CANCELING:
+	case SL_CORE_LLR_STATE_SETUP_TIMEOUT:
+	case SL_CORE_LLR_STATE_START_TIMEOUT:
+	case SL_CORE_LLR_STATE_SETUP_STOPPING:
+	case SL_CORE_LLR_STATE_STOPPING:
+		should_stop = true;
+		sl_core_log_dbg(core_llr, LOG_NAME,
+				"should_stop = %s", should_stop ? "true" : "false");
+		spin_unlock(&core_llr->data_lock);
+		return should_stop;
+	default:
+		should_stop = false;
+		sl_core_log_dbg(core_llr, LOG_NAME,
+				"should_stop = %s", should_stop ? "true" : "false");
+		spin_unlock(&core_llr->data_lock);
+		return should_stop;
+	}
+}
+
+void sl_core_llr_last_fail_cause_set(u8 ldev_num, u8 lgrp_num, u8 llr_num, u32 llr_fail_cause)
+{
+	sl_core_data_llr_last_fail_cause_set(sl_core_llr_get(ldev_num, lgrp_num, llr_num), llr_fail_cause);
+}
+
+const char *sl_core_llr_fail_cause_str(u32 llr_fail_cause)
+{
+	switch (llr_fail_cause) {
+	case SL_LLR_FAIL_CAUSE_SETUP_CONFIG:
+		return "setup-config";
+	case SL_LLR_FAIL_CAUSE_SETUP_INTR_ENABLE:
+		return "setup-intr-enable";
+	case SL_LLR_FAIL_CAUSE_SETUP_TIMEOUT:
+		return "setup-timeout";
+	case SL_LLR_FAIL_CAUSE_START_INTR_ENABLE:
+		return "start-intr-enable";
+	case SL_LLR_FAIL_CAUSE_START_TIMEOUT:
+		return "start-timeout";
+	default:
+		return "unknown";
+	}
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/sl_core_mac.c b/drivers/net/ethernet/hpe/sl/core/sl_core_mac.c
new file mode 100644
index 000000000000..cfa11304e4cb
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/sl_core_mac.c
@@ -0,0 +1,183 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2022,2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+
+#include "base/sl_core_log.h"
+#include "sl_core_mac.h"
+#include "sl_core_str.h"
+#include "data/sl_core_data_mac.h"
+#include "hw/sl_core_hw_mac.h"
+
+#define LOG_NAME SL_CORE_MAC_LOG_NAME
+
+int sl_core_mac_new(u8 ldev_num, u8 lgrp_num, u8 mac_num)
+{
+	return sl_core_data_mac_new(ldev_num, lgrp_num, mac_num);
+}
+
+void sl_core_mac_del(u8 ldev_num, u8 lgrp_num, u8 mac_num)
+{
+	sl_core_data_mac_del(ldev_num, lgrp_num, mac_num);
+}
+
+struct sl_core_mac *sl_core_mac_get(u8 ldev_num, u8 lgrp_num, u8 mac_num)
+{
+	return sl_core_data_mac_get(ldev_num, lgrp_num, mac_num);
+}
+
+int sl_core_mac_tx_start(u8 ldev_num, u8 lgrp_num, u8 mac_num)
+{
+	int                 rtn;
+	struct sl_core_mac *core_mac;
+
+	core_mac = sl_core_mac_get(ldev_num, lgrp_num, mac_num);
+
+	sl_core_log_dbg(core_mac, LOG_NAME, "tx start");
+
+	rtn = sl_core_data_mac_tx_settings(core_mac);
+	if (rtn) {
+		sl_core_log_err_trace(core_mac, LOG_NAME, "tx start - mac_tx_settings failed [%d]", rtn);
+		rtn = -EBADRQC;
+		goto out;
+	}
+	sl_core_hw_mac_tx_config(core_mac);
+	sl_core_hw_mac_tx_start(core_mac);
+
+out:
+	spin_lock(&core_mac->data_lock);
+	core_mac->tx_last_start_result = rtn;
+	spin_unlock(&core_mac->data_lock);
+
+	return rtn;
+}
+
+int sl_core_mac_tx_stop(u8 ldev_num, u8 lgrp_num, u8 mac_num)
+{
+	struct sl_core_mac *core_mac;
+
+	core_mac = sl_core_mac_get(ldev_num, lgrp_num, mac_num);
+	if (!core_mac)
+		return 0;
+
+	sl_core_log_dbg(core_mac, LOG_NAME, "tx stop");
+
+	sl_core_hw_mac_tx_stop(core_mac);
+
+	return 0;
+}
+
+int sl_core_mac_tx_state_get(u8 ldev_num, u8 lgrp_num, u8 mac_num, u32 *mac_state)
+{
+	struct sl_core_mac *core_mac;
+
+	core_mac = sl_core_mac_get(ldev_num, lgrp_num, mac_num);
+
+	*mac_state = sl_core_data_mac_tx_state_get(core_mac);
+
+	sl_core_log_dbg(core_mac, LOG_NAME,
+			"state get (tx_state = %u %s)", *mac_state, sl_core_mac_state_str(*mac_state));
+
+	return 0;
+}
+
+int sl_core_mac_tx_last_start_result_get(u8 ldev_num, u8 lgrp_num, u8 mac_num, int *last_start_result)
+{
+	struct sl_core_mac *core_mac;
+
+	core_mac = sl_core_mac_get(ldev_num, lgrp_num, mac_num);
+
+	spin_lock(&core_mac->data_lock);
+	*last_start_result = core_mac->tx_last_start_result;
+	spin_unlock(&core_mac->data_lock);
+
+	sl_core_log_dbg(core_mac, LOG_NAME,
+			"tx last start result get (last_start_result = %d)", *last_start_result);
+
+	return 0;
+}
+
+int sl_core_mac_rx_start(u8 ldev_num, u8 lgrp_num, u8 mac_num)
+{
+	int                 rtn;
+	struct sl_core_mac *core_mac;
+
+	core_mac = sl_core_mac_get(ldev_num, lgrp_num, mac_num);
+
+	sl_core_log_dbg(core_mac, LOG_NAME, "rx start");
+
+	rtn = sl_core_data_mac_rx_settings(core_mac);
+	if (rtn) {
+		sl_core_log_err_trace(core_mac, LOG_NAME, "rx start - mac_rx_settings failed [%d]", rtn);
+		rtn = -EBADRQC;
+		goto out;
+	}
+	sl_core_hw_mac_rx_config(core_mac);
+	sl_core_hw_mac_rx_start(core_mac);
+
+out:
+	spin_lock(&core_mac->data_lock);
+	core_mac->rx_last_start_result = rtn;
+	spin_unlock(&core_mac->data_lock);
+
+	return rtn;
+}
+
+int sl_core_mac_rx_stop(u8 ldev_num, u8 lgrp_num, u8 mac_num)
+{
+	struct sl_core_mac *core_mac;
+
+	core_mac = sl_core_mac_get(ldev_num, lgrp_num, mac_num);
+	if (!core_mac)
+		return 0;
+
+	sl_core_log_dbg(core_mac, LOG_NAME, "rx stop");
+
+	sl_core_hw_mac_rx_stop(core_mac);
+
+	return 0;
+}
+
+int sl_core_mac_rx_state_get(u8 ldev_num, u8 lgrp_num, u8 mac_num, u32 *mac_state)
+{
+	struct sl_core_mac *core_mac;
+
+	core_mac = sl_core_mac_get(ldev_num, lgrp_num, mac_num);
+
+	*mac_state = sl_core_data_mac_rx_state_get(core_mac);
+
+	sl_core_log_dbg(core_mac, LOG_NAME,
+			"state get (rx_state = %u %s)", *mac_state, sl_core_mac_state_str(*mac_state));
+
+	return 0;
+}
+
+int sl_core_mac_rx_last_start_result_get(u8 ldev_num, u8 lgrp_num, u8 mac_num, int *last_start_result)
+{
+	struct sl_core_mac *core_mac;
+
+	core_mac = sl_core_mac_get(ldev_num, lgrp_num, mac_num);
+
+	spin_lock(&core_mac->data_lock);
+	*last_start_result = core_mac->rx_last_start_result;
+	spin_unlock(&core_mac->data_lock);
+
+	sl_core_log_dbg(core_mac, LOG_NAME,
+			"rx last start result get (last_start_result = %d)", *last_start_result);
+
+	return 0;
+}
+
+u64 sl_core_mac_info_map_get(u8 ldev_num, u8 lgrp_num, u8 mac_num)
+{
+	struct sl_core_mac *core_mac;
+	u64                 info_map;
+
+	core_mac = sl_core_mac_get(ldev_num, lgrp_num, mac_num);
+
+	info_map = sl_core_data_mac_info_map_get(core_mac);
+
+	sl_core_log_dbg(core_mac, LOG_NAME, "info map get (map = 0x%llX)", info_map);
+
+	return info_map;
+}
diff --git a/drivers/net/ethernet/hpe/sl/core/sl_core_str.c b/drivers/net/ethernet/hpe/sl/core/sl_core_str.c
new file mode 100644
index 000000000000..4f5975eeeeb5
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/core/sl_core_str.c
@@ -0,0 +1,283 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2022-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/module.h>
+#include <linux/bitops.h>
+
+#include "sl_core_link.h"
+#include "hw/sl_core_hw_serdes_lane.h"
+#include "sl_core_str.h"
+
+#define SL_CORE_INFO_MAP_DESC_SIZE 20
+struct sl_core_info_map_str_item {
+	char desc[SL_CORE_INFO_MAP_DESC_SIZE];
+};
+
+static struct sl_core_info_map_str_item sl_core_info_map_str_list[] = {
+	[SL_CORE_INFO_MAP_MEDIA_CHECK]        = { .desc = "media-check"        },
+	[SL_CORE_INFO_MAP_MEDIA_OK]           = { .desc = "media-ok"           },
+
+	[SL_CORE_INFO_MAP_SERDES_START]       = { .desc = "serdes-start"       },
+	[SL_CORE_INFO_MAP_SERDES_CHECK]       = { .desc = "serdes-check"       },
+	[SL_CORE_INFO_MAP_SERDES_OK]          = { .desc = "serdes-ok"          },
+	[SL_CORE_INFO_MAP_SERDES_LOOPBACK_ON] = { .desc = "serdes-loopback-on" },
+
+	[SL_CORE_INFO_MAP_PCS_LOCAL_FAULT]    = { .desc = "pcs-local-fault"    },
+	[SL_CORE_INFO_MAP_PCS_REMOTE_FAULT]   = { .desc = "pcs-remote-fault"   },
+	[SL_CORE_INFO_MAP_PCS_LINK_DOWN]      = { .desc = "pcs-link-down"      },
+	[SL_CORE_INFO_MAP_PCS_CHECK]          = { .desc = "pcs-check"          },
+	[SL_CORE_INFO_MAP_PCS_OK]             = { .desc = "pcs-ok"             },
+
+	[SL_CORE_INFO_MAP_FEC_CHECK]          = { .desc = "fec-check"          },
+	[SL_CORE_INFO_MAP_FEC_OK]             = { .desc = "fec-ok"             },
+	[SL_CORE_INFO_MAP_LINK_DEGRADED]      = { .desc = "link-degraded"      },
+
+	[SL_CORE_INFO_MAP_LINK_DOWN]          = { .desc = "link-down"          },
+	[SL_CORE_INFO_MAP_LINK_UP_CANCEL]     = { .desc = "link-up-cancel"     },
+	[SL_CORE_INFO_MAP_LINK_UP_TIMEOUT]    = { .desc = "link-up-timeout"    },
+	[SL_CORE_INFO_MAP_LINK_UP_FAIL]       = { .desc = "link-up-fail"       },
+	[SL_CORE_INFO_MAP_LINK_UP]            = { .desc = "link-up"            },
+
+	[SL_CORE_INFO_MAP_MAC_RX_CONFIG]      = { .desc = "mac-rx-config"      },
+	[SL_CORE_INFO_MAP_MAC_TX_CONFIG]      = { .desc = "mac-tx-config"      },
+	[SL_CORE_INFO_MAP_MAC_RX]             = { .desc = "mac-rx"             },
+	[SL_CORE_INFO_MAP_MAC_TX]             = { .desc = "mac-tx"             },
+
+	[SL_CORE_INFO_MAP_AN_BASE_PAGE]       = { .desc = "an-base-page"       },
+	[SL_CORE_INFO_MAP_AN_NEXT_PAGE]       = { .desc = "an-next-page"       },
+	[SL_CORE_INFO_MAP_AN_ERROR]           = { .desc = "an-error"           },
+	[SL_CORE_INFO_MAP_AN_DONE]            = { .desc = "an-done"            },
+
+	[SL_CORE_INFO_MAP_LLR_CONFIG]         = { .desc = "llr-config"         },
+	[SL_CORE_INFO_MAP_LLR_SETTING_UP]     = { .desc = "llr-setting-up"     },
+	[SL_CORE_INFO_MAP_LLR_SETUP]          = { .desc = "llr-setup"          },
+	[SL_CORE_INFO_MAP_LLR_SETUP_TIMEOUT]  = { .desc = "llr-setup-timeout"  },
+	[SL_CORE_INFO_MAP_LLR_STARTING]       = { .desc = "llr-starting"       },
+	[SL_CORE_INFO_MAP_LLR_RUNNING]        = { .desc = "llr-running"        },
+	[SL_CORE_INFO_MAP_LLR_START_TIMEOUT]  = { .desc = "llr-start-timeout"  },
+	[SL_CORE_INFO_MAP_LLR_MAX_STARVATION] = { .desc = "llr-max-starvation" },
+	[SL_CORE_INFO_MAP_LLR_STARVED]        = { .desc = "llr-starved"        },
+	[SL_CORE_INFO_MAP_LLR_REPLAY_MAX]     = { .desc = "llr-replay-max"     },
+
+	[SL_CORE_INFO_MAP_HIGH_SER]           = { .desc = "high-ser"           },
+};
+
+#define SL_CORE_INFO_MAP_STR_MIN 10
+int sl_core_info_map_str(u64 info_map, char *info_map_str, unsigned int info_map_str_size)
+{
+	int          rtn;
+	unsigned int x;
+	unsigned int str_pos;
+
+	if (!info_map_str)
+		return -EINVAL;
+
+	if (info_map_str_size < SL_CORE_INFO_MAP_STR_MIN)
+		return -EINVAL;
+
+	str_pos = 0;
+
+	for (x = 0; x < SL_CORE_INFO_MAP_NUM_BITS; ++x) {
+		if (!test_bit(x, (unsigned long *)&(info_map)))
+			continue;
+		rtn = snprintf(info_map_str + str_pos,
+			       info_map_str_size - str_pos, "%s ",
+			sl_core_info_map_str_list[x].desc);
+		if (rtn < 0) {
+			str_pos = snprintf(info_map_str, info_map_str_size, "error ");
+			break;
+		}
+		if (str_pos + rtn >= info_map_str_size) {
+			info_map_str[str_pos - 2] = '.';
+			info_map_str[str_pos - 3] = '.';
+			info_map_str[str_pos - 4] = '.';
+			break;
+		}
+		str_pos += rtn;
+	}
+
+	if (str_pos == 0)
+		str_pos = snprintf(info_map_str, info_map_str_size, "none ");
+
+	info_map_str[str_pos - 1] = '\0';
+
+	return 0;
+}
+
+const char *sl_core_link_state_str(enum sl_core_link_state link_state)
+{
+	switch (link_state) {
+	case SL_CORE_LINK_STATE_UNCONFIGURED:
+		return "unconfigured";
+	case SL_CORE_LINK_STATE_CONFIGURING:
+		return "configuring";
+	case SL_CORE_LINK_STATE_CONFIGURED:
+		return "configured";
+	case SL_CORE_LINK_STATE_DOWN:
+		return "down";
+	case SL_CORE_LINK_STATE_AN:
+		return "an";
+	case SL_CORE_LINK_STATE_GOING_UP:
+		return "going-up";
+	case SL_CORE_LINK_STATE_UP:
+		return "up";
+	case SL_CORE_LINK_STATE_CANCELING:
+		return "canceling";
+	case SL_CORE_LINK_STATE_GOING_DOWN:
+		return "going-down";
+	case SL_CORE_LINK_STATE_TIMEOUT:
+		return "timeout";
+	default:
+		return "unknown";
+	}
+}
+
+const char *sl_core_mac_state_str(enum sl_core_mac_state mac_state)
+{
+	switch (mac_state) {
+	case SL_CORE_MAC_STATE_INVALID:
+		return "invalid";
+	case SL_CORE_MAC_STATE_OFF:
+		return "off";
+	case SL_CORE_MAC_STATE_ON:
+		return "on";
+	default:
+		return "unknown";
+	}
+}
+
+const char *sl_core_llr_state_str(enum sl_core_llr_state llr_state)
+{
+	switch (llr_state) {
+	case SL_CORE_LLR_STATE_INVALID:
+		return "invalid";
+	case SL_CORE_LLR_STATE_NEW:
+		return "new";
+	case SL_CORE_LLR_STATE_CONFIGURED:
+		return "configured";
+	case SL_CORE_LLR_STATE_SETTING_UP:
+		return "setting-up";
+	case SL_CORE_LLR_STATE_SETUP_TIMEOUT:
+		return "setup-timeout";
+	case SL_CORE_LLR_STATE_SETUP_CANCELING:
+		return "setup-canceling";
+	case SL_CORE_LLR_STATE_SETUP_STOPPING:
+		return "setup-stopping";
+	case SL_CORE_LLR_STATE_SETUP:
+		return "setup";
+	case SL_CORE_LLR_STATE_STARTING:
+		return "starting";
+	case SL_CORE_LLR_STATE_START_TIMEOUT:
+		return "start-timeout";
+	case SL_CORE_LLR_STATE_START_CANCELING:
+		return "start-canceling";
+	case SL_CORE_LLR_STATE_RUNNING:
+		return "running";
+	case SL_CORE_LLR_STATE_STOPPING:
+		return "stopping";
+	default:
+		return "unknown";
+	}
+}
+
+const char *sl_core_llr_flag_str(unsigned int llr_flag)
+{
+	switch (llr_flag) {
+	default:
+		return "unknown";
+	}
+}
+
+const char *sl_core_serdes_lane_state_str(u8 lane_state)
+{
+	switch (lane_state) {
+	case SL_CORE_HW_SERDES_LANE_STATE_DOWN:
+		return "down";
+	case SL_CORE_HW_SERDES_LANE_STATE_SETUP:
+		return "setup";
+	case SL_CORE_HW_SERDES_LANE_STATE_CONFIG:
+		return "config";
+	case SL_CORE_HW_SERDES_LANE_STATE_START:
+		return "start";
+	case SL_CORE_HW_SERDES_LANE_STATE_CHECK:
+		return "check";
+	case SL_CORE_HW_SERDES_LANE_STATE_STOP:
+		return "stop";
+	case SL_CORE_HW_SERDES_LANE_STATE_UP:
+		return "up";
+	default:
+		return "unknown";
+	}
+}
+
+const char *sl_core_serdes_lane_encoding_str(u16 encoding)
+{
+	switch (encoding) {
+	case SL_CORE_HW_SERDES_ENCODING_NRZ:
+		return "NRZ";
+	case SL_CORE_HW_SERDES_ENCODING_PAM4_NR:
+		return "PAM4_normal";
+	case SL_CORE_HW_SERDES_ENCODING_PAM4_ER:
+		return "PAM4_extended";
+	default:
+		return "unknown";
+	}
+}
+
+const char *sl_core_serdes_lane_clocking_str(u16 clocking)
+{
+	switch (clocking) {
+	case SL_CORE_HW_SERDES_CLOCKING_82P5:
+		return "82.5/165";
+	case SL_CORE_HW_SERDES_CLOCKING_85:
+		return "85/170";
+	default:
+		return "unknown";
+	}
+}
+
+const char *sl_core_serdes_lane_osr_str(u16 osr)
+{
+	switch (osr) {
+	case SL_CORE_HW_SERDES_OSR_OSX1:
+		return "OSX1";
+	case SL_CORE_HW_SERDES_OSR_OSX2:
+		return "OSX2";
+	case SL_CORE_HW_SERDES_OSR_OSX4:
+		return "OSX4";
+	case SL_CORE_HW_SERDES_OSR_OSX42P5:
+		return "OSX42P5";
+	default:
+		return "unknown";
+	}
+}
+
+const char *sl_core_serdes_lane_width_str(u16 width)
+{
+	switch (width) {
+	case SL_CORE_HW_SERDES_WIDTH_40:
+		return "40";
+	case SL_CORE_HW_SERDES_WIDTH_80:
+		return "80";
+	case SL_CORE_HW_SERDES_WIDTH_160:
+		return "160";
+	default:
+		return "unknown";
+	}
+}
+
+const char *sl_core_lgrp_dt_jack_part_str(u32 jack_type)
+{
+	switch (jack_type) {
+	case SL_DT_JACK_TYPE_LEGACY:
+		return "legacy";
+	case SL_DT_JACK_TYPE_DD:
+		return "double-density";
+	case SL_DT_JACK_TYPE_EXAMAX_LEFT:
+		return "examax-left";
+	case SL_DT_JACK_TYPE_EXAMAX_RIGHT:
+		return "examax-right";
+	default:
+		return "unknown";
+	}
+}

-- 
2.56.0


^ permalink raw reply	[flat|nested] 25+ messages in thread
* [PATCH 12/23] net: hpe: sl: add the control layer
  2026-10-30 20:58 [PATCH 00/23] Subject: [PATCH net-next 00/23] net/hpe: add HPE Slingshot NIC drivers Doug Ledford
                   ` (10 preceding siblings ...)
  2026-10-30 20:59 ` [PATCH 11/23] net: hpe: sl: add the core link state machines Doug Ledford
@ 2026-10-30 20:59 ` Doug Ledford
  2026-10-30 20:59 ` [PATCH 13/23] net: hpe: sl: add media and cable handling Doug Ledford
                   ` (11 subsequent siblings)
  23 siblings, 0 replies; 25+ messages in thread
From: Doug Ledford @ 2026-10-30 20:59 UTC (permalink / raw)
  To: Slingshot Open Source Team, Nathan Chancellor, Nicolas Schier,
	Richard Cochran, Andrew Lunn, David S. Miller, Eric Dumazet,
	Jakub Kicinski, Paolo Abeni, Sumit Semwal, Christian König,
	Guenter Roeck
  Cc: linux-kernel, netdev, linux-kbuild, Doug Ledford, Sandeep Bhoot,
	Mamila Santosh, Iraimani P

Add the SL control layer, which validates and serialises requests from
the NIC driver and sysfs onto the core state machines, and delivers
link group notifications back.

checkpatch --strict (100 columns) still reports the following in this
patch. They need coordination with the internal repositories this code
is maintained in and will be fixed in V2:
- WARNING: LONG_LINE (239), LONG_LINE_STRING (18), LONG_LINE_COMMENT (2)
- CHECK: UNNECESSARY_PARENTHESES (21), ALLOC_SIZEOF_STRUCT (4)

Co-developed-by: Sandeep Bhoot <sandeep.bhoot@hpe.com>
Signed-off-by: Sandeep Bhoot <sandeep.bhoot@hpe.com>
Co-developed-by: Mamila Santosh <santosh-kumar.mamila@hpe.com>
Signed-off-by: Mamila Santosh <santosh-kumar.mamila@hpe.com>
Co-developed-by: Iraimani P <iraimani.pavadai@hpe.com>
Signed-off-by: Iraimani P <iraimani.pavadai@hpe.com>
Signed-off-by: Doug Ledford <doug.ledford@hpe.com>
---
 .../ethernet/hpe/sl/ctrl/data/sl_ctrl_data_lgrp.c  |  164 +++
 .../hpe/sl/ctrl/data/sl_ctrl_data_lgrp_trace.c     |   50 +
 .../ethernet/hpe/sl/ctrl/data/sl_ctrl_data_link.c  |  424 +++++++
 .../ethernet/hpe/sl/ctrl/data/sl_ctrl_data_llr.c   |   64 +
 drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_ldev.c    |  290 +++++
 drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_lgrp.c    |  351 ++++++
 .../net/ethernet/hpe/sl/ctrl/sl_ctrl_lgrp_notif.c  |  258 ++++
 drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_link.c    | 1230 ++++++++++++++++++++
 .../ethernet/hpe/sl/ctrl/sl_ctrl_link_counters.c   |  388 ++++++
 .../net/ethernet/hpe/sl/ctrl/sl_ctrl_link_fec.c    |  202 ++++
 .../ethernet/hpe/sl/ctrl/sl_ctrl_link_fec_priv.c   |  539 +++++++++
 .../net/ethernet/hpe/sl/ctrl/sl_ctrl_link_priv.c   |  865 ++++++++++++++
 drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_llr.c     |  630 ++++++++++
 .../ethernet/hpe/sl/ctrl/sl_ctrl_llr_counters.c    |  136 +++
 drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_mac.c     |  536 +++++++++
 .../ethernet/hpe/sl/ctrl/sl_ctrl_mac_counters.c    |   56 +
 .../ethernet/hpe/sl/ctrl/sl_ctrl_media_counters.c  |  157 +++
 17 files changed, 6340 insertions(+)

diff --git a/drivers/net/ethernet/hpe/sl/ctrl/data/sl_ctrl_data_lgrp.c b/drivers/net/ethernet/hpe/sl/ctrl/data/sl_ctrl_data_lgrp.c
new file mode 100644
index 000000000000..279e41770f48
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/ctrl/data/sl_ctrl_data_lgrp.c
@@ -0,0 +1,164 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2025-2026 Hewlett Packard Enterprise Development LP */
+
+#include "base/sl_ctrl_log.h"
+#include "sl_ctrl_ldev.h"
+#include "sl_media_lgrp.h"
+#include "sl_core_lgrp.h"
+
+#include "data/sl_core_data_lgrp.h"
+#include "data/sl_media_data_lgrp.h"
+
+#include "sl_ctrl_data_lgrp.h"
+
+#define LOG_NAME SL_CTRL_LGRP_LOG_NAME
+
+int sl_ctrl_data_lgrp_err_trace_enable_set(struct sl_ctrl_lgrp *ctrl_lgrp, bool err_trace_enable)
+{
+	struct sl_core_lgrp *held_lgrp_1 __free(sl_core_lgrp_put) = NULL;
+	int rtn;
+
+	sl_ctrl_log_dbg(ctrl_lgrp, LOG_NAME, "set (err_trace_enable = %s)", err_trace_enable ? "true" : "false");
+
+	held_lgrp_1 = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!held_lgrp_1)
+		return -ENODEV;
+	spin_lock(&ctrl_lgrp->config_lock);
+	rtn = sl_core_data_lgrp_err_trace_enable_set(held_lgrp_1,
+						     err_trace_enable);
+	if (rtn) {
+		sl_ctrl_log_err_trace(ctrl_lgrp, LOG_NAME,
+				      "core trace enable set failed [%d]", rtn);
+		spin_unlock(&ctrl_lgrp->config_lock);
+		return rtn;
+	}
+
+	rtn = sl_media_data_lgrp_err_trace_enable_set(sl_media_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num),
+						      err_trace_enable);
+	if (rtn) {
+		sl_ctrl_log_err_trace(ctrl_lgrp, LOG_NAME,
+				      "media trace enable set failed [%d]", rtn);
+		spin_unlock(&ctrl_lgrp->config_lock);
+		return rtn;
+	}
+
+	ctrl_lgrp->err_trace_enable = err_trace_enable;
+
+	spin_unlock(&ctrl_lgrp->config_lock);
+
+	return 0;
+}
+
+int sl_ctrl_data_lgrp_warn_trace_set(struct sl_ctrl_lgrp *ctrl_lgrp, bool err_trace_enable)
+{
+	struct sl_core_lgrp *held_lgrp_1 __free(sl_core_lgrp_put) = NULL;
+	int rtn;
+
+	sl_ctrl_log_dbg(ctrl_lgrp, LOG_NAME, "set (warn_trace_enable = %s)", err_trace_enable ? "true" : "false");
+
+	held_lgrp_1 = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!held_lgrp_1)
+		return -ENODEV;
+	spin_lock(&ctrl_lgrp->config_lock);
+	rtn = sl_core_data_lgrp_warn_trace_enable_set(held_lgrp_1,
+						      err_trace_enable);
+	if (rtn) {
+		sl_ctrl_log_err_trace(ctrl_lgrp, LOG_NAME,
+				      "core trace enable set failed [%d]", rtn);
+		spin_unlock(&ctrl_lgrp->config_lock);
+		return rtn;
+	}
+
+	rtn = sl_media_data_lgrp_warn_trace_enable_set(sl_media_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num),
+						       err_trace_enable);
+	if (rtn) {
+		sl_ctrl_log_err_trace(ctrl_lgrp, LOG_NAME,
+				      "media trace enable set failed [%d]", rtn);
+		spin_unlock(&ctrl_lgrp->config_lock);
+		return rtn;
+	}
+
+	ctrl_lgrp->warn_trace_enable = err_trace_enable;
+
+	spin_unlock(&ctrl_lgrp->config_lock);
+
+	return 0;
+}
+
+int sl_ctrl_data_lgrp_serdes_lane_io_trace_set(struct sl_ctrl_lgrp *ctrl_lgrp, bool serdes_lane_io_trace)
+{
+	sl_ctrl_log_dbg(ctrl_lgrp, LOG_NAME,
+			"set (serdes_lane_io_trace = %s)", serdes_lane_io_trace ? "enable" : "disable");
+
+	spin_lock(&ctrl_lgrp->config_lock);
+	ctrl_lgrp->serdes_lane_io_trace_enable = serdes_lane_io_trace;
+	spin_unlock(&ctrl_lgrp->config_lock);
+
+	return 0;
+}
+
+int sl_ctrl_data_lgrp_mfs_get(struct sl_ctrl_lgrp *ctrl_lgrp, u32 *mfs)
+{
+	spin_lock(&ctrl_lgrp->config_lock);
+	*mfs = ctrl_lgrp->config.mfs;
+	spin_unlock(&ctrl_lgrp->config_lock);
+
+	sl_ctrl_log_dbg(ctrl_lgrp, LOG_NAME, "get (mfs = %u)", *mfs);
+
+	return 0;
+}
+
+int sl_ctrl_data_lgrp_furcation_get(struct sl_ctrl_lgrp *ctrl_lgrp, u32 *furcation)
+{
+	spin_lock(&ctrl_lgrp->config_lock);
+	*furcation = ctrl_lgrp->config.furcation;
+	spin_unlock(&ctrl_lgrp->config_lock);
+
+	sl_ctrl_log_dbg(ctrl_lgrp, LOG_NAME, "get (furcation = %u)", *furcation);
+
+	return 0;
+}
+
+int sl_ctrl_data_lgrp_fec_mode_get(struct sl_ctrl_lgrp *ctrl_lgrp, u32 *fec_mode)
+{
+	spin_lock(&ctrl_lgrp->config_lock);
+	*fec_mode = ctrl_lgrp->config.fec_mode;
+	spin_unlock(&ctrl_lgrp->config_lock);
+
+	sl_ctrl_log_dbg(ctrl_lgrp, LOG_NAME, "get (fec_mode = %u)", *fec_mode);
+
+	return 0;
+}
+
+int sl_ctrl_data_lgrp_tech_map_get(struct sl_ctrl_lgrp *ctrl_lgrp, u32 *tech_map)
+{
+	spin_lock(&ctrl_lgrp->config_lock);
+	*tech_map = ctrl_lgrp->config.tech_map;
+	spin_unlock(&ctrl_lgrp->config_lock);
+
+	sl_ctrl_log_dbg(ctrl_lgrp, LOG_NAME, "get (tech_map = 0x%X)", *tech_map);
+
+	return 0;
+}
+
+int sl_ctrl_data_lgrp_fec_map_get(struct sl_ctrl_lgrp *ctrl_lgrp, u32 *fec_map)
+{
+	spin_lock(&ctrl_lgrp->config_lock);
+	*fec_map = ctrl_lgrp->config.fec_map;
+	spin_unlock(&ctrl_lgrp->config_lock);
+
+	sl_ctrl_log_dbg(ctrl_lgrp, LOG_NAME, "get (fec_map = 0x%X)", *fec_map);
+
+	return 0;
+}
+
+int sl_ctrl_data_lgrp_options_get(struct sl_ctrl_lgrp *ctrl_lgrp, u32 *options)
+{
+	spin_lock(&ctrl_lgrp->config_lock);
+	*options = ctrl_lgrp->config.options;
+	spin_unlock(&ctrl_lgrp->config_lock);
+
+	sl_ctrl_log_dbg(ctrl_lgrp, LOG_NAME, "get (options = 0x%X)", *options);
+
+	return 0;
+}
diff --git a/drivers/net/ethernet/hpe/sl/ctrl/data/sl_ctrl_data_lgrp_trace.c b/drivers/net/ethernet/hpe/sl/ctrl/data/sl_ctrl_data_lgrp_trace.c
new file mode 100644
index 000000000000..5b6dfe73495e
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/ctrl/data/sl_ctrl_data_lgrp_trace.c
@@ -0,0 +1,50 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2025-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/spinlock.h>
+
+#include "data/sl_ctrl_data_lgrp_trace.h"
+
+#define LOG_NAME SL_CTRL_LGRP_LOG_NAME
+
+int sl_ctrl_data_lgrp_is_err_trace_enabled(struct sl_ctrl_lgrp *ctrl_lgrp, bool *err_trace_enable)
+{
+	spin_lock(&ctrl_lgrp->config_lock);
+	*err_trace_enable = ctrl_lgrp->err_trace_enable;
+	spin_unlock(&ctrl_lgrp->config_lock);
+
+	sl_ctrl_log_dbg(ctrl_lgrp, LOG_NAME,
+			"is err trace enabled (err_trace_enable = %s)",
+			*err_trace_enable ? "true" : "false");
+
+	return 0;
+}
+
+int sl_ctrl_data_lgrp_is_warn_trace_enabled(struct sl_ctrl_lgrp *ctrl_lgrp, bool *warn_trace_enable)
+{
+	spin_lock(&ctrl_lgrp->config_lock);
+	*warn_trace_enable = ctrl_lgrp->warn_trace_enable;
+	spin_unlock(&ctrl_lgrp->config_lock);
+
+	sl_ctrl_log_dbg(ctrl_lgrp, LOG_NAME,
+			"is warn trace enabled (warn_trace_enable = %s)",
+			*warn_trace_enable ? "true" : "false");
+
+	return 0;
+}
+
+bool sl_ctrl_data_lgrp_is_serdes_lane_io_trace_enabled(struct sl_ctrl_lgrp *ctrl_lgrp)
+{
+	bool serdes_lane_io_trace;
+
+	spin_lock(&ctrl_lgrp->config_lock);
+	serdes_lane_io_trace = ctrl_lgrp->serdes_lane_io_trace_enable;
+	spin_unlock(&ctrl_lgrp->config_lock);
+
+	sl_ctrl_log_dbg(ctrl_lgrp, LOG_NAME,
+			"is serdes lane io trace enabled (serdes_lane_io_trace = %s)",
+			serdes_lane_io_trace ? "enabled" : "disabled");
+
+	return serdes_lane_io_trace;
+}
diff --git a/drivers/net/ethernet/hpe/sl/ctrl/data/sl_ctrl_data_link.c b/drivers/net/ethernet/hpe/sl/ctrl/data/sl_ctrl_data_link.c
new file mode 100644
index 000000000000..dfb1b820d5ef
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/ctrl/data/sl_ctrl_data_link.c
@@ -0,0 +1,424 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#include "base/sl_ctrl_log.h"
+#include "sl_ctrl_ldev.h"
+#include "sl_ctrl_lgrp.h"
+#include "sl_ctrl_link.h"
+#include "data/sl_core_data_link.h"
+
+#include "data/sl_ctrl_data_link.h"
+
+#define LOG_NAME SL_CTRL_LINK_LOG_NAME
+
+int sl_ctrl_data_link_state_get(struct sl_ctrl_link *ctrl_link, u32 *link_state)
+{
+	struct sl_core_link *held_link_1 __free(sl_core_link_put) = NULL;
+	int rtn;
+	u32 core_link_state;
+	u32 ctrl_link_state;
+
+	held_link_1 = sl_core_link_get(ctrl_link->ctrl_lgrp->ctrl_ldev->num,
+				       ctrl_link->ctrl_lgrp->num, ctrl_link->num);
+	if (!held_link_1)
+		return -ENODEV;
+	spin_lock(&ctrl_link->data_lock);
+	rtn = sl_core_data_link_state_get(held_link_1, &core_link_state);
+	ctrl_link_state = ctrl_link->state;
+	spin_unlock(&ctrl_link->data_lock);
+
+	if (rtn) {
+		sl_ctrl_log_err_trace(ctrl_link, LOG_NAME,
+				      "sl_core_data_link_state_get failed (rtn = %d)", rtn);
+		return rtn;
+	}
+
+	*link_state = (core_link_state == SL_CORE_LINK_STATE_AN) ? SL_LINK_STATE_AN : ctrl_link_state;
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"get (link_state = %u %s)",
+			*link_state,
+			sl_link_state_str(*link_state));
+
+	return 0;
+}
+
+int sl_ctrl_data_link_fec_up_settle_wait_ms_get(struct sl_ctrl_link *ctrl_link, u32 *fec_up_settle_wait_ms)
+{
+	spin_lock(&ctrl_link->data_lock);
+	*fec_up_settle_wait_ms = ctrl_link->config.fec_up_settle_wait_ms;
+	spin_unlock(&ctrl_link->data_lock);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"get (fec_up_settle_wait_ms = %d)", *fec_up_settle_wait_ms);
+
+	return 0;
+}
+
+int sl_ctrl_data_link_fec_up_check_wait_ms_get(struct sl_ctrl_link *ctrl_link, s32 *fec_up_check_wait_ms)
+{
+	spin_lock(&ctrl_link->data_lock);
+	*fec_up_check_wait_ms = ctrl_link->config.fec_up_check_wait_ms;
+	spin_unlock(&ctrl_link->data_lock);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"get (fec_up_check_wait_ms = %d)", *fec_up_check_wait_ms);
+
+	return 0;
+}
+
+int sl_ctrl_data_link_fec_up_ucw_limit_get(struct sl_ctrl_link *ctrl_link, s32 *fec_up_ucw_limit)
+{
+	spin_lock(&ctrl_link->data_lock);
+	*fec_up_ucw_limit = ctrl_link->config.fec_up_ucw_limit;
+	spin_unlock(&ctrl_link->data_lock);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"get (fec_up_ucw_limit = %d)", *fec_up_ucw_limit);
+
+	return 0;
+}
+
+int sl_ctrl_data_link_fec_up_ccw_limit_get(struct sl_ctrl_link *ctrl_link, s32 *fec_up_ccw_limit)
+{
+	spin_lock(&ctrl_link->data_lock);
+	*fec_up_ccw_limit = ctrl_link->config.fec_up_ccw_limit;
+	spin_unlock(&ctrl_link->data_lock);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"get (fec_up_ccw_limit = %d)", *fec_up_ccw_limit);
+
+	return 0;
+}
+
+int sl_ctrl_data_link_policy_fec_mon_period_ms_get(struct sl_ctrl_link *ctrl_link, s32 *mon_period_ms)
+{
+	spin_lock(&ctrl_link->config_lock);
+	*mon_period_ms = ctrl_link->policy.fec_mon_period_ms;
+	spin_unlock(&ctrl_link->config_lock);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"get (mon_period_ms = %d)", *mon_period_ms);
+
+	return 0;
+}
+
+int sl_ctrl_data_link_policy_fec_mon_ucw_down_limit_get(struct sl_ctrl_link *ctrl_link, s32 *mon_ucw_down_limit)
+{
+	spin_lock(&ctrl_link->config_lock);
+	*mon_ucw_down_limit = ctrl_link->policy.fec_mon_ucw_down_limit;
+	spin_unlock(&ctrl_link->config_lock);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"get (mon_ucw_down_limit = %d)", *mon_ucw_down_limit);
+
+	return 0;
+}
+
+int sl_ctrl_data_link_policy_fec_mon_ucw_warn_limit_get(struct sl_ctrl_link *ctrl_link, s32 *mon_ucw_warn_limit)
+{
+	spin_lock(&ctrl_link->config_lock);
+	*mon_ucw_warn_limit = ctrl_link->policy.fec_mon_ucw_warn_limit;
+	spin_unlock(&ctrl_link->config_lock);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"get (mon_ucw_warn_limit = %d)", *mon_ucw_warn_limit);
+
+	return 0;
+}
+
+int sl_ctrl_data_link_policy_fec_mon_ccw_down_limit_get(struct sl_ctrl_link *ctrl_link, s32 *mon_ccw_down_limit)
+{
+	spin_lock(&ctrl_link->config_lock);
+	*mon_ccw_down_limit = ctrl_link->policy.fec_mon_ccw_down_limit;
+	spin_unlock(&ctrl_link->config_lock);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"get (mon_ccw_down_limit = %d)", *mon_ccw_down_limit);
+
+	return 0;
+}
+
+int sl_ctrl_data_link_policy_fec_mon_ccw_warn_limit_get(struct sl_ctrl_link *ctrl_link, s32 *mon_ccw_warn_limit)
+{
+	spin_lock(&ctrl_link->config_lock);
+	*mon_ccw_warn_limit = ctrl_link->policy.fec_mon_ccw_warn_limit;
+	spin_unlock(&ctrl_link->config_lock);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"get (mon_ccw_warn_limit = %d)", *mon_ccw_warn_limit);
+
+	return 0;
+}
+
+int sl_ctrl_data_link_fec_down_cache_ucw_cntr_get(struct sl_ctrl_link *ctrl_link, u64 *ucw)
+{
+	spin_lock(&ctrl_link->fec_down_cache.lock);
+	*ucw = ctrl_link->fec_down_cache.cw_cntrs.ucw;
+	spin_unlock(&ctrl_link->fec_down_cache.lock);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"get (ucw = %llu)", *ucw);
+
+	return 0;
+}
+
+int sl_ctrl_data_link_fec_down_cache_ccw_cntr_get(struct sl_ctrl_link *ctrl_link, u64 *ccw)
+{
+	spin_lock(&ctrl_link->fec_down_cache.lock);
+	*ccw = ctrl_link->fec_down_cache.cw_cntrs.ccw;
+	spin_unlock(&ctrl_link->fec_down_cache.lock);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"get (ccw = %llu)", *ccw);
+
+	return 0;
+}
+
+int sl_ctrl_data_link_fec_down_cache_gcw_cntr_get(struct sl_ctrl_link *ctrl_link, u64 *gcw)
+{
+	spin_lock(&ctrl_link->fec_down_cache.lock);
+	*gcw = ctrl_link->fec_down_cache.cw_cntrs.gcw;
+	spin_unlock(&ctrl_link->fec_down_cache.lock);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"get (gcw = %llu)", *gcw);
+
+	return 0;
+}
+
+int sl_ctrl_data_link_fec_down_cache_lane_cntr_get(struct sl_ctrl_link *ctrl_link, u8 lane_num, u64 *lane_cntr)
+{
+	spin_lock(&ctrl_link->fec_down_cache.lock);
+	*lane_cntr = ctrl_link->fec_down_cache.lane_cntrs.lanes[lane_num];
+	spin_unlock(&ctrl_link->fec_down_cache.lock);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"get (lane_num = %d, lane_cntr = %llu)", lane_num, *lane_cntr);
+
+	return 0;
+}
+
+int sl_ctrl_data_link_fec_down_cache_tail_cntr_get(struct sl_ctrl_link *ctrl_link, u8 bin_num, u64 *tail_cntr)
+{
+	spin_lock(&ctrl_link->fec_down_cache.lock);
+	*tail_cntr = ctrl_link->fec_down_cache.tail_cntrs.ccw_bins[bin_num];
+	spin_unlock(&ctrl_link->fec_down_cache.lock);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"get (bin_num = %d, tail_cntr = %llu)", bin_num, *tail_cntr);
+
+	return 0;
+}
+
+int sl_ctrl_data_link_fec_mon_period_ms_get(struct sl_ctrl_link *ctrl_link, u32 *mon_period_get)
+
+{
+	spin_lock(&ctrl_link->fec_data.lock);
+	*mon_period_get = ctrl_link->fec_data.info.monitor.period_ms;
+	spin_unlock(&ctrl_link->fec_data.lock);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"get (mon_period_get = %u)", *mon_period_get);
+
+	return 0;
+}
+
+int sl_ctrl_data_link_fec_mon_ucw_down_limit_get(struct sl_ctrl_link *ctrl_link, s32 *ucw_down_limit)
+{
+	u32 period_ms;
+
+	spin_lock(&ctrl_link->fec_data.lock);
+	period_ms = ctrl_link->fec_data.info.monitor.period_ms;
+	*ucw_down_limit = ctrl_link->fec_data.info.monitor.ucw_down_limit;
+	spin_unlock(&ctrl_link->fec_data.lock);
+
+	if (!period_ms) {
+		sl_ctrl_log_warn_trace(ctrl_link, LOG_NAME,
+				       "fec_mon_ucw_down_limit_get failed (monitoring disabled)");
+		return -EBADRQC;
+	}
+
+	return 0;
+}
+
+int sl_ctrl_data_link_fec_mon_ccw_down_limit_get(struct sl_ctrl_link *ctrl_link, s32 *ccw_down_limit)
+{
+	u32 period_ms;
+
+	spin_lock(&ctrl_link->fec_data.lock);
+	period_ms = ctrl_link->fec_data.info.monitor.period_ms;
+	*ccw_down_limit = ctrl_link->fec_data.info.monitor.ccw_down_limit;
+	spin_unlock(&ctrl_link->fec_data.lock);
+
+	if (!period_ms) {
+		sl_ctrl_log_warn_trace(ctrl_link, LOG_NAME,
+				       "fec_mon_ccw_down_limit_get failed (monitoring disabled)");
+		return -EBADRQC;
+	}
+
+	return 0;
+}
+
+int sl_ctrl_data_link_fec_mon_ccw_warn_limit_get(struct sl_ctrl_link *ctrl_link, s32 *ccw_warn_limit)
+{
+	u32 period_ms;
+
+	spin_lock(&ctrl_link->fec_data.lock);
+	period_ms = ctrl_link->fec_data.info.monitor.period_ms;
+	*ccw_warn_limit = ctrl_link->fec_data.info.monitor.ccw_warn_limit;
+	spin_unlock(&ctrl_link->fec_data.lock);
+
+	if (!period_ms) {
+		sl_ctrl_log_warn_trace(ctrl_link, LOG_NAME,
+				       "fec_mon_ccw_warn_limit_get failed (monitoring disabled)");
+		return -EBADRQC;
+	}
+
+	return 0;
+}
+
+int sl_ctrl_data_link_fec_mon_ucw_warn_limit_get(struct sl_ctrl_link *ctrl_link, s32 *ucw_warn_limit)
+{
+	u32 period_ms;
+
+	spin_lock(&ctrl_link->fec_data.lock);
+	period_ms = ctrl_link->fec_data.info.monitor.period_ms;
+	*ucw_warn_limit = ctrl_link->fec_data.info.monitor.ucw_warn_limit;
+	spin_unlock(&ctrl_link->fec_data.lock);
+
+	if (!period_ms) {
+		sl_ctrl_log_warn_trace(ctrl_link, LOG_NAME,
+				       "fec_mon_ucw_warn_limit_get failed (monitoring disabled)");
+		return -EBADRQC;
+	}
+
+	return 0;
+}
+
+int sl_ctrl_data_link_fec_up_cache_ucw_cntr_get(struct sl_ctrl_link *ctrl_link, u64 *ucw)
+{
+	spin_lock(&ctrl_link->fec_up_cache.lock);
+	*ucw = ctrl_link->fec_up_cache.cw_cntrs.ucw;
+	spin_unlock(&ctrl_link->fec_up_cache.lock);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "get (ucw = %llu)", *ucw);
+
+	return 0;
+}
+
+int sl_ctrl_data_link_fec_up_cache_ccw_cntr_get(struct sl_ctrl_link *ctrl_link, u64 *ccw)
+{
+	spin_lock(&ctrl_link->fec_up_cache.lock);
+	*ccw = ctrl_link->fec_up_cache.cw_cntrs.ccw;
+	spin_unlock(&ctrl_link->fec_up_cache.lock);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "get (ccw = %llu)", *ccw);
+
+	return 0;
+}
+
+int sl_ctrl_data_link_fec_up_cache_gcw_cntr_get(struct sl_ctrl_link *ctrl_link, u64 *gcw)
+{
+	spin_lock(&ctrl_link->fec_up_cache.lock);
+	*gcw = ctrl_link->fec_up_cache.cw_cntrs.gcw;
+	spin_unlock(&ctrl_link->fec_up_cache.lock);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "get (gcw = %llu)", *gcw);
+
+	return 0;
+}
+
+int sl_ctrl_data_link_fec_up_cache_lane_cntr_get(struct sl_ctrl_link *ctrl_link, u8 lane_num, u64 *lane_cntr)
+{
+	spin_lock(&ctrl_link->fec_up_cache.lock);
+	*lane_cntr = ctrl_link->fec_up_cache.lane_cntrs.lanes[lane_num];
+	spin_unlock(&ctrl_link->fec_up_cache.lock);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "get (lane_num = %d, lane_cntr = %llu)", lane_num, *lane_cntr);
+
+	return 0;
+}
+
+int sl_ctrl_data_link_fec_up_cache_tail_cntr_get(struct sl_ctrl_link *ctrl_link, u8 bin_num, u64 *tail_cntr)
+{
+	spin_lock(&ctrl_link->fec_up_cache.lock);
+	*tail_cntr = ctrl_link->fec_up_cache.tail_cntrs.ccw_bins[bin_num];
+	spin_unlock(&ctrl_link->fec_up_cache.lock);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "get (bin_num = %d, tail_cntr = %llu)", bin_num, *tail_cntr);
+
+	return 0;
+}
+
+int sl_ctrl_data_link_policy_options_get(struct sl_ctrl_link *ctrl_link, u32 *options)
+{
+	spin_lock(&ctrl_link->config_lock);
+	*options = ctrl_link->policy.options;
+	spin_unlock(&ctrl_link->config_lock);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"get (options = 0x%08x)", *options);
+
+	return 0;
+}
+
+int sl_ctrl_data_link_up_timeout_ms_get(struct sl_ctrl_link *ctrl_link, u32 *link_up_timeout_ms)
+{
+	spin_lock(&ctrl_link->data_lock);
+	*link_up_timeout_ms = ctrl_link->config.link_up_timeout_ms;
+	spin_unlock(&ctrl_link->data_lock);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"get (link_up_timeout_ms = %d)", *link_up_timeout_ms);
+
+	return 0;
+}
+
+int sl_ctrl_data_link_up_tries_max_get(struct sl_ctrl_link *ctrl_link, u32 *link_up_tries_max)
+{
+	spin_lock(&ctrl_link->data_lock);
+	*link_up_tries_max = ctrl_link->config.link_up_tries_max;
+	spin_unlock(&ctrl_link->data_lock);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"get (link_up_tries_max = %d)", *link_up_tries_max);
+
+	return 0;
+}
+
+int sl_ctrl_data_link_config_options_get(struct sl_ctrl_link *ctrl_link, u32 *options)
+{
+	spin_lock(&ctrl_link->data_lock);
+	*options = ctrl_link->config.options;
+	spin_unlock(&ctrl_link->data_lock);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"get (options = 0x%08x)", *options);
+
+	return 0;
+}
+
+int sl_ctrl_data_link_pause_map_get(struct sl_ctrl_link *ctrl_link, u32 *pause_map)
+{
+	spin_lock(&ctrl_link->data_lock);
+	*pause_map = ctrl_link->config.pause_map;
+	spin_unlock(&ctrl_link->data_lock);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"get (pause_map = 0x%x)", *pause_map);
+
+	return 0;
+}
+
+int sl_ctrl_data_link_hpe_map_get(struct sl_ctrl_link *ctrl_link, u32 *hpe_map)
+{
+	spin_lock(&ctrl_link->data_lock);
+	*hpe_map = ctrl_link->config.hpe_map;
+	spin_unlock(&ctrl_link->data_lock);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"get (hpe_map = 0x%x)", *hpe_map);
+
+	return 0;
+}
diff --git a/drivers/net/ethernet/hpe/sl/ctrl/data/sl_ctrl_data_llr.c b/drivers/net/ethernet/hpe/sl/ctrl/data/sl_ctrl_data_llr.c
new file mode 100644
index 000000000000..be742b146a0a
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/ctrl/data/sl_ctrl_data_llr.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/spinlock.h>
+
+#include "base/sl_ctrl_log.h"
+#include "sl_ctrl_data_llr.h"
+
+#define LOG_NAME SL_CTRL_LLR_LOG_NAME
+
+int sl_ctrl_data_llr_config_mode_get(struct sl_ctrl_llr *ctrl_llr, u32 *mode)
+{
+	spin_lock(&ctrl_llr->data_lock);
+	*mode = ctrl_llr->config.mode;
+	spin_unlock(&ctrl_llr->data_lock);
+
+	sl_ctrl_log_dbg(ctrl_llr, LOG_NAME, "get (mode = %u)\n", *mode);
+
+	return 0;
+}
+
+int sl_ctrl_data_llr_config_setup_timeout_ms_get(struct sl_ctrl_llr *ctrl_llr, u32 *setup_timeout_ms)
+{
+	spin_lock(&ctrl_llr->data_lock);
+	*setup_timeout_ms = ctrl_llr->config.setup_timeout_ms;
+	spin_unlock(&ctrl_llr->data_lock);
+
+	sl_ctrl_log_dbg(ctrl_llr, LOG_NAME, "get (setup_timeout_ms = %u)\n", *setup_timeout_ms);
+
+	return 0;
+}
+
+int sl_ctrl_data_llr_config_start_timeout_ms_get(struct sl_ctrl_llr *ctrl_llr, u32 *start_timeout_ms)
+{
+	spin_lock(&ctrl_llr->data_lock);
+	*start_timeout_ms = ctrl_llr->config.start_timeout_ms;
+	spin_unlock(&ctrl_llr->data_lock);
+
+	sl_ctrl_log_dbg(ctrl_llr, LOG_NAME, "get (start_timeout_ms = %u)\n", *start_timeout_ms);
+
+	return 0;
+}
+
+int sl_ctrl_data_llr_config_link_dn_behavior_get(struct sl_ctrl_llr *ctrl_llr, u32 *link_dn_behavior)
+{
+	spin_lock(&ctrl_llr->data_lock);
+	*link_dn_behavior = ctrl_llr->config.link_dn_behavior;
+	spin_unlock(&ctrl_llr->data_lock);
+
+	sl_ctrl_log_dbg(ctrl_llr, LOG_NAME, "get (link_dn_behavior = %u)\n", *link_dn_behavior);
+
+	return 0;
+}
+
+int sl_ctrl_data_llr_config_options_get(struct sl_ctrl_llr *ctrl_llr, u32 *options)
+{
+	spin_lock(&ctrl_llr->data_lock);
+	*options = ctrl_llr->config.options;
+	spin_unlock(&ctrl_llr->data_lock);
+
+	sl_ctrl_log_dbg(ctrl_llr, LOG_NAME, "get (options = 0x%08x)\n", *options);
+
+	return 0;
+}
diff --git a/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_ldev.c b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_ldev.c
new file mode 100644
index 000000000000..0295dd902d6d
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_ldev.c
@@ -0,0 +1,290 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2021-2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/spinlock.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+#include <linux/completion.h>
+#include <linux/delay.h>
+
+#include "sl_asic.h"
+#include "sl_sysfs.h"
+#include "base/sl_ctrl_log.h"
+#include "sl_core_ldev.h"
+#include "sl_media_ldev.h"
+#include "sl_ctrl_ldev.h"
+#include "sl_ctrl_lgrp.h"
+
+#define LOG_NAME SL_CTRL_LDEV_LOG_NAME
+
+#define SL_CTRL_LDEV_DEL_TIMEOUT_MS 2000
+
+static struct sl_ctrl_ldev *ctrl_ldevs[SL_ASIC_MAX_LDEVS];
+static DEFINE_SPINLOCK(ctrl_ldevs_lock);
+
+#define CONFIG_SL_DEFAULT_WQ_MAX_ACTIVE  0 /* 0 is default (256 work items in queue). */
+int sl_ctrl_ldev_new(u8 ldev_num, struct workqueue_struct *workq,
+		     struct sl_ldev_attr *ldev_attr)
+{
+	int                   rtn;
+	struct sl_ctrl_ldev   *ctrl_ldev;
+
+	ctrl_ldev = sl_ctrl_ldev_get(ldev_num);
+	if (ctrl_ldev) {
+		sl_ctrl_log_err(NULL, LOG_NAME, "exists (ldev = 0x%p)", ctrl_ldev);
+		return -EBADRQC;
+	}
+
+	ctrl_ldev = kzalloc(sizeof(struct sl_ctrl_ldev), GFP_KERNEL);
+	if (!ctrl_ldev)
+		return -ENOMEM;
+
+	ctrl_ldev->magic = SL_CTRL_LDEV_MAGIC;
+	ctrl_ldev->ver   = SL_CTRL_LDEV_VER;
+	ctrl_ldev->num   = ldev_num;
+	ctrl_ldev->attr  = *ldev_attr;
+
+	kref_init(&ctrl_ldev->ref_cnt);
+	init_completion(&ctrl_ldev->del_complete);
+
+	spin_lock_init(&ctrl_ldev->data_lock);
+
+	if (IS_ERR_OR_NULL(workq)) {
+		ctrl_ldev->workq = alloc_workqueue("%s%u",
+						   WQ_MEM_RECLAIM | WQ_PERCPU,
+						   CONFIG_SL_DEFAULT_WQ_MAX_ACTIVE, "sl-ldev", ldev_num);
+		if (!ctrl_ldev->workq) {
+			rtn = -ENOMEM;
+			sl_ctrl_log_err(ctrl_ldev, LOG_NAME, "alloc_workqueue failed [%d]", rtn);
+			goto out;
+		}
+
+		sl_ctrl_log_dbg(ctrl_ldev, LOG_NAME, "created workqueue (workq = 0x%p)", ctrl_ldev->workq);
+		ctrl_ldev->create_workq = true;
+	} else {
+		ctrl_ldev->workq = workq;
+		sl_ctrl_log_dbg(ctrl_ldev, LOG_NAME, "client workqueue (workq = 0x%p)", ctrl_ldev->workq);
+	}
+
+	ctrl_ldev->notif_workq = alloc_workqueue("%s%u-notif",
+						 WQ_MEM_RECLAIM | WQ_PERCPU,
+						 CONFIG_SL_DEFAULT_WQ_MAX_ACTIVE, "sl-ldev", ldev_num);
+	if (!ctrl_ldev->notif_workq) {
+		rtn = -ENOMEM;
+		sl_ctrl_log_err(ctrl_ldev, LOG_NAME, "alloc_workqueue notif failed [%d]", rtn);
+		goto out_del_wq;
+	}
+
+	rtn = sl_core_ldev_new(ldev_num, ctrl_ldev->attr.accessors,
+			       ctrl_ldev->attr.ops, ctrl_ldev->workq);
+	if (rtn) {
+		sl_ctrl_log_err_trace(ctrl_ldev, LOG_NAME, "core_ldev_new failed [%d]", rtn);
+		goto out_del_notif_wq;
+	}
+
+	rtn = sl_media_ldev_new(ldev_num, ctrl_ldev->workq);
+	if (rtn) {
+		sl_ctrl_log_err_trace(ctrl_ldev, LOG_NAME, "media_ldev_new failed [%d]", rtn);
+		goto out_del_core;
+	}
+
+	sl_ctrl_log_dbg(ctrl_ldev, LOG_NAME, "new (ldev = 0x%p)", ctrl_ldev);
+
+	spin_lock(&ctrl_ldevs_lock);
+	ctrl_ldevs[ldev_num] = ctrl_ldev;
+	spin_unlock(&ctrl_ldevs_lock);
+
+	return 0;
+
+out_del_core:
+	sl_core_ldev_del(ldev_num);
+out_del_notif_wq:
+	destroy_workqueue(ctrl_ldev->notif_workq);
+
+out_del_wq:
+	if (ctrl_ldev->create_workq)
+		destroy_workqueue(ctrl_ldev->workq);
+out:
+	kfree(ctrl_ldev);
+
+	return rtn;
+}
+
+#define SERDES_INIT_MAX_TRIES 3
+#define SERDES_INIT_DELAY_MS  1000
+int sl_ctrl_ldev_serdes_init(u8 ldev_num)
+{
+	int rtn;
+	int tries;
+	struct sl_ctrl_ldev *ctrl_ldev;
+
+	ctrl_ldev = sl_ctrl_ldev_get(ldev_num);
+	if (!ctrl_ldev) {
+		sl_ctrl_log_err(NULL, LOG_NAME, "ldev not found (ldev_num = %u)", ldev_num);
+		return -EBADRQC;
+	}
+
+	if (!sl_ctrl_ldev_kref_get_unless_zero(ctrl_ldev)) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"kref_get_unless_zero failed (ldev = 0x%p)", ctrl_ldev);
+		return -EBADRQC;
+	}
+
+	sl_ctrl_log_dbg(ctrl_ldev, LOG_NAME, "serdes init (ldev = 0x%p)", ctrl_ldev);
+
+	tries = SERDES_INIT_MAX_TRIES;
+	do {
+		rtn = sl_core_ldev_serdes_init(ldev_num);
+		if (rtn == 0)
+			goto out;
+		tries--;
+		if (tries)
+			msleep(SERDES_INIT_DELAY_MS);
+	} while (tries);
+
+out:
+	if (sl_ctrl_ldev_put(ctrl_ldev))
+		sl_ctrl_log_dbg(NULL, LOG_NAME,
+				"serdes init - ldev removed (ldev = 0x%p)", ctrl_ldev);
+
+	return rtn;
+}
+
+static void sl_ctrl_ldev_release(struct kref *ref)
+{
+	struct sl_ctrl_ldev *ctrl_ldev;
+	u8                  ldev_num;
+	u8                  lgrp_num;
+	int                 rtn;
+
+	ctrl_ldev = container_of(ref, struct sl_ctrl_ldev, ref_cnt);
+	ldev_num = ctrl_ldev->num;
+
+	sl_ctrl_log_dbg(ctrl_ldev, LOG_NAME, "release (ldev = 0x%p)", ctrl_ldev);
+
+	/* Not repeated on a retry: the sysfs delete drops kobject references. */
+	if (!ctrl_ldev->children_deleted) {
+		for (lgrp_num = 0; lgrp_num < SL_ASIC_MAX_LGRPS; ++lgrp_num) {
+			rtn = sl_ctrl_lgrp_del(ldev_num, lgrp_num);
+			if (rtn && rtn != -EBADRQC)
+				goto retry;
+		}
+		ctrl_ldev->children_deleted = true;
+	}
+
+	if (!ctrl_ldev->sysfs_deleted) {
+		/* Must delete sysfs first to guarantee nobody is reading */
+		sl_sysfs_ldev_delete(ctrl_ldev);
+		ctrl_ldev->sysfs_deleted = true;
+	}
+
+	rtn = sl_core_ldev_del(ldev_num);
+	if (rtn) {
+		/*
+		 * A core lgrp or link refused deletion, so the core ldev is
+		 * still published and uses the workqueue and ldev state.
+		 * Nobody holds a reference any more, so re-arm one for the
+		 * next sl_ctrl_ldev_del() to retry, and wake the waiter so it
+		 * can report the failure.
+		 */
+		sl_ctrl_log_err_trace(ctrl_ldev, LOG_NAME,
+				      "release - core_ldev_del failed, ldev kept [%d]", rtn);
+		goto retry;
+	}
+	sl_media_ldev_del(ldev_num);
+
+	destroy_workqueue(ctrl_ldev->notif_workq);
+
+	if (ctrl_ldev->create_workq)
+		destroy_workqueue(ctrl_ldev->workq);
+
+	spin_lock(&ctrl_ldevs_lock);
+	ctrl_ldevs[ldev_num] = NULL;
+	spin_unlock(&ctrl_ldevs_lock);
+
+	complete_all(&ctrl_ldev->del_complete);
+
+	kfree(ctrl_ldev);
+	return;
+
+retry:
+	kref_init(&ctrl_ldev->ref_cnt);
+	complete_all(&ctrl_ldev->del_complete);
+}
+
+int sl_ctrl_ldev_put(struct sl_ctrl_ldev *ctrl_ldev)
+{
+	return kref_put(&ctrl_ldev->ref_cnt, sl_ctrl_ldev_release);
+}
+
+int sl_ctrl_ldev_del(u8 ldev_num)
+{
+	struct sl_ctrl_ldev *ctrl_ldev;
+	unsigned long       timeleft;
+
+	ctrl_ldev = sl_ctrl_ldev_get(ldev_num);
+	if (!ctrl_ldev) {
+		sl_ctrl_log_err_trace(NULL, LOG_NAME,
+				      "del not found (ldev_num = %u)", ldev_num);
+		return -EBADRQC;
+	}
+
+	sl_ctrl_log_dbg(ctrl_ldev, LOG_NAME, "del (ldev = 0x%p)", ctrl_ldev);
+
+	/*
+	 * Release cannot run before the put below, so rearming a completion
+	 * left over from an earlier failed del is safe.
+	 */
+	reinit_completion(&ctrl_ldev->del_complete);
+
+	if (!sl_ctrl_ldev_put(ctrl_ldev)) {
+		timeleft = wait_for_completion_timeout(&ctrl_ldev->del_complete,
+						       msecs_to_jiffies(SL_CTRL_LDEV_DEL_TIMEOUT_MS));
+
+		sl_ctrl_log_dbg(NULL, LOG_NAME,
+				"del completion_timeout (timeleft = %lums)", timeleft);
+
+		if (timeleft == 0) {
+			sl_ctrl_log_err(NULL, LOG_NAME,
+					"del timed out (ctrl_ldev = 0x%p)", ctrl_ldev);
+			return -ETIMEDOUT;
+		}
+	}
+
+	/*
+	 * A successful release unpublishes and frees the ldev. If it is still
+	 * published, the core ldev refused deletion and was kept for a retry.
+	 * Only the pointer value is compared, the ldev is not dereferenced.
+	 */
+	if (sl_ctrl_ldev_get(ldev_num) == ctrl_ldev)
+		return -EBUSY;
+
+	return 0;
+}
+
+bool sl_ctrl_ldev_kref_get_unless_zero(struct sl_ctrl_ldev *ctrl_ldev)
+{
+	return (kref_get_unless_zero(&ctrl_ldev->ref_cnt) != 0);
+}
+
+struct sl_ctrl_ldev *sl_ctrl_ldev_get(u8 ldev_num)
+{
+	struct sl_ctrl_ldev *ctrl_ldev;
+
+	spin_lock(&ctrl_ldevs_lock);
+	ctrl_ldev = ctrl_ldevs[ldev_num];
+	spin_unlock(&ctrl_ldevs_lock);
+
+	sl_ctrl_log_dbg(NULL, LOG_NAME, "get (ldev_num = %u, ldev = 0x%p)",
+			ldev_num, ctrl_ldev);
+
+	return ctrl_ldev;
+}
+
+void sl_ctrl_ldev_exit(void)
+{
+	u8 ldev_num;
+
+	for (ldev_num = 0; ldev_num < SL_ASIC_MAX_LDEVS; ++ldev_num)
+		sl_ctrl_ldev_del(ldev_num);
+}
diff --git a/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_lgrp.c b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_lgrp.c
new file mode 100644
index 000000000000..1e7240325fcc
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_lgrp.c
@@ -0,0 +1,351 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2021-2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kobject.h>
+#include <linux/spinlock.h>
+#include <linux/slab.h>
+
+#include "sl_asic.h"
+#include "sl_sysfs.h"
+#include "base/sl_ctrl_log.h"
+#include "sl_ctrl_ldev.h"
+#include "sl_ctrl_lgrp.h"
+#include "sl_ctrl_lgrp_notif.h"
+#include "sl_ctrl_link.h"
+#include "sl_ctrl_llr.h"
+#include "sl_ctrl_mac.h"
+#include "sl_media_lgrp.h"
+#include "sl_core_lgrp.h"
+
+#define LOG_NAME SL_CTRL_LGRP_LOG_NAME
+
+#define SL_CTRL_LGRP_DEL_TIMEOUT_MS 2000
+
+static struct sl_ctrl_lgrp *ctrl_lgrps[SL_ASIC_MAX_LDEVS][SL_ASIC_MAX_LGRPS];
+static DEFINE_SPINLOCK(ctrl_lgrps_lock);
+
+int sl_ctrl_lgrp_new(u8 ldev_num, u8 lgrp_num, struct kobject *sysfs_parent)
+{
+	int                  rtn;
+	struct sl_ctrl_ldev *ctrl_ldev;
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+
+	ctrl_ldev = sl_ctrl_ldev_get(ldev_num);
+	if (!ctrl_ldev) {
+		sl_ctrl_log_err(NULL, LOG_NAME, "missing ldev (ldev_num = %u)", ldev_num);
+		return -EBADRQC;
+	}
+
+	ctrl_lgrp = sl_ctrl_lgrp_get(ldev_num, lgrp_num);
+	if (ctrl_lgrp) {
+		sl_ctrl_log_err(NULL, LOG_NAME, "exists (lgrp = 0x%p)", ctrl_lgrp);
+		return -EBADRQC;
+	}
+
+	ctrl_lgrp = kzalloc(sizeof(struct sl_ctrl_lgrp), GFP_KERNEL);
+	if (!ctrl_lgrp)
+		return -ENOMEM;
+
+	snprintf(ctrl_lgrp->log_connect_id,
+		 sizeof(ctrl_lgrp->log_connect_id), "ctrl-lgrp%02u", lgrp_num);
+
+	ctrl_lgrp->magic     = SL_CTRL_LGRP_MAGIC;
+	ctrl_lgrp->ver       = SL_CTRL_LGRP_VER;
+	ctrl_lgrp->num       = lgrp_num;
+	ctrl_lgrp->ctrl_ldev = sl_ctrl_ldev_get(ldev_num);
+
+	kref_init(&ctrl_lgrp->ref_cnt);
+	init_completion(&ctrl_lgrp->del_complete);
+
+	spin_lock_init(&ctrl_lgrp->data_lock);
+	spin_lock_init(&ctrl_lgrp->config_lock);
+	spin_lock_init(&ctrl_lgrp->log_lock);
+
+	spin_lock_init(&(ctrl_lgrp->ctrl_notif.lock));
+
+	rtn = kfifo_alloc(&ctrl_lgrp->ctrl_notif.fifo,
+			  SL_CTRL_LGRP_NOTIF_MSG_COUNT * sizeof(struct sl_lgrp_notif_msg),
+			  GFP_KERNEL);
+	if (rtn) {
+		sl_ctrl_log_err(ctrl_lgrp, LOG_NAME, "create notif fifo failed");
+		rtn = -ENOMEM;
+		goto out_free;
+	}
+	INIT_WORK(&ctrl_lgrp->notif_work, sl_ctrl_lgrp_notif_work);
+
+	rtn = sl_core_lgrp_new(ldev_num, lgrp_num);
+	if (rtn) {
+		sl_ctrl_log_err_trace(ctrl_lgrp, LOG_NAME, "core_lgrp_new failed [%d]", rtn);
+		goto out_kfifo_free;
+	}
+
+	rtn = sl_media_lgrp_new(ldev_num, lgrp_num);
+	if (rtn) {
+		sl_ctrl_log_err_trace(ctrl_lgrp, LOG_NAME, "media_lgrp_new failed [%d]", rtn);
+		goto out_core_lgrp;
+	}
+
+	if (sysfs_parent) {
+		ctrl_lgrp->parent_kobj = sysfs_parent;
+
+		rtn = sl_sysfs_lgrp_create(ctrl_lgrp);
+		if (rtn) {
+			sl_ctrl_log_err_trace(ctrl_lgrp, LOG_NAME,
+					      "sysfs_lgrp_create failed");
+			goto out_media_lgrp;
+		}
+	}
+
+	sl_ctrl_log_dbg(ctrl_lgrp, LOG_NAME, "new (lgrp = 0x%p)", ctrl_lgrp);
+
+	spin_lock(&ctrl_lgrps_lock);
+	ctrl_lgrps[ldev_num][lgrp_num] = ctrl_lgrp;
+	spin_unlock(&ctrl_lgrps_lock);
+
+	return 0;
+
+out_media_lgrp:
+	sl_media_lgrp_del(ldev_num, lgrp_num);
+out_core_lgrp:
+	sl_core_lgrp_del(ldev_num, lgrp_num);
+out_kfifo_free:
+	kfifo_free(&ctrl_lgrp->ctrl_notif.fifo);
+out_free:
+	kfree(ctrl_lgrp);
+
+	return rtn;
+}
+
+static void sl_ctrl_lgrp_release(struct kref *ref)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	u8                   ldev_num;
+	u8                   lgrp_num;
+	u8                   link_num;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(ref, struct sl_ctrl_lgrp, ref_cnt);
+	ldev_num = ctrl_lgrp->ctrl_ldev->num;
+	lgrp_num = ctrl_lgrp->num;
+
+	ctrl_lgrp = sl_ctrl_lgrp_get(ldev_num, lgrp_num);
+	if (!ctrl_lgrp) {
+		sl_ctrl_log_err_trace(NULL, LOG_NAME,
+				      "release lgrp not found (lgrp_num = %u)", lgrp_num);
+		return;
+	}
+
+	sl_ctrl_log_dbg(ctrl_lgrp, LOG_NAME, "del (lgrp = 0x%p)", ctrl_lgrp);
+
+	if (!ctrl_lgrp->children_deleted) {
+		for (link_num = 0; link_num < SL_ASIC_MAX_LINKS; ++link_num) {
+			rtn = sl_ctrl_link_del(ldev_num, lgrp_num, link_num);
+			if (rtn && rtn != -EBADRQC)
+				goto retry;
+
+			rtn = sl_ctrl_llr_del(ldev_num, lgrp_num, link_num);
+			if (rtn && rtn != -EBADRQC)
+				goto retry;
+
+			rtn = sl_ctrl_mac_del(ldev_num, lgrp_num, link_num);
+			if (rtn && rtn != -EBADRQC)
+				goto retry;
+		}
+		ctrl_lgrp->children_deleted = true;
+	}
+
+	if (!ctrl_lgrp->sysfs_deleted) {
+		/* Must delete sysfs first to guarantee nobody is reading */
+		sl_sysfs_lgrp_delete(ctrl_lgrp);
+		ctrl_lgrp->sysfs_deleted = true;
+	}
+
+	rtn = sl_core_lgrp_del(ldev_num, lgrp_num);
+	if (rtn) {
+		sl_ctrl_log_err_trace(ctrl_lgrp, LOG_NAME,
+				      "release - core_lgrp_del failed [%d]", rtn);
+		goto retry;
+	}
+
+	sl_media_lgrp_del(ldev_num, lgrp_num);
+
+	cancel_work_sync(&ctrl_lgrp->notif_work);
+	kfifo_free(&ctrl_lgrp->ctrl_notif.fifo);
+
+	spin_lock(&ctrl_lgrps_lock);
+	ctrl_lgrps[ldev_num][lgrp_num] = NULL;
+	spin_unlock(&ctrl_lgrps_lock);
+
+	complete_all(&ctrl_lgrp->del_complete);
+
+	kfree(ctrl_lgrp);
+	return;
+
+retry:
+	sl_ctrl_log_err_trace(ctrl_lgrp, LOG_NAME,
+			      "release - child/core deletion failed [%d]", rtn);
+	kref_init(&ctrl_lgrp->ref_cnt);
+	complete_all(&ctrl_lgrp->del_complete);
+}
+
+int sl_ctrl_lgrp_put(struct sl_ctrl_lgrp *ctrl_lgrp)
+{
+	return kref_put(&ctrl_lgrp->ref_cnt, sl_ctrl_lgrp_release);
+}
+
+int sl_ctrl_lgrp_del(u8 ldev_num, u8 lgrp_num)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	unsigned long        timeleft;
+
+	ctrl_lgrp = sl_ctrl_lgrp_get(ldev_num, lgrp_num);
+	if (!ctrl_lgrp) {
+		sl_ctrl_log_err_trace(NULL, LOG_NAME,
+				      "del not found (ldev_num = %u, lgrp_num = %u)", ldev_num, lgrp_num);
+		return -EBADRQC;
+	}
+
+	sl_ctrl_log_dbg(ctrl_lgrp, LOG_NAME, "del (lgrp = 0x%p)", ctrl_lgrp);
+	reinit_completion(&ctrl_lgrp->del_complete);
+
+	if (!sl_ctrl_lgrp_put(ctrl_lgrp)) {
+		timeleft = wait_for_completion_timeout(&ctrl_lgrp->del_complete,
+						       msecs_to_jiffies(SL_CTRL_LGRP_DEL_TIMEOUT_MS));
+
+		sl_ctrl_log_dbg(NULL, LOG_NAME,
+				"del completion_timeout (timeleft = %lums)", timeleft);
+
+		if (timeleft == 0) {
+			sl_ctrl_log_err(NULL, LOG_NAME,
+					"del timed out (ctrl_lgrp = 0x%p)", ctrl_lgrp);
+			return -ETIMEDOUT;
+		}
+	}
+	if (sl_ctrl_lgrp_get(ldev_num, lgrp_num) == ctrl_lgrp)
+		return -EBUSY;
+
+	return 0;
+}
+
+bool sl_ctrl_lgrp_kref_get_unless_zero(struct sl_ctrl_lgrp *ctrl_lgrp)
+{
+	return (kref_get_unless_zero(&ctrl_lgrp->ref_cnt) != 0);
+}
+
+struct sl_ctrl_lgrp *sl_ctrl_lgrp_get(u8 ldev_num, u8 lgrp_num)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+
+	spin_lock(&ctrl_lgrps_lock);
+	ctrl_lgrp = ctrl_lgrps[ldev_num][lgrp_num];
+	spin_unlock(&ctrl_lgrps_lock);
+
+	return ctrl_lgrp;
+}
+
+int sl_ctrl_lgrp_connect_id_set(u8 ldev_num, u8 lgrp_num, const char *connect_id)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	unsigned long       irq_flags;
+
+	ctrl_lgrp = sl_ctrl_lgrp_get(ldev_num, lgrp_num);
+	if (!ctrl_lgrp) {
+		sl_ctrl_log_err(NULL, LOG_NAME, "NULL lgrp");
+		return -EBADRQC;
+	}
+
+	if (!sl_ctrl_lgrp_kref_get_unless_zero(ctrl_lgrp)) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"kref_get_unless_zero failed (ctrl_lgrp = 0x%p)", ctrl_lgrp);
+		return -EBADRQC;
+	}
+
+	spin_lock_irqsave(&ctrl_lgrp->log_lock, irq_flags);
+	strscpy_pad(ctrl_lgrp->log_connect_id, connect_id,
+		    sizeof(ctrl_lgrp->log_connect_id));
+	spin_unlock_irqrestore(&ctrl_lgrp->log_lock, irq_flags);
+
+	sl_media_lgrp_connect_id_set(ldev_num, lgrp_num, connect_id);
+
+	sl_core_lgrp_connect_id_set(ldev_num, lgrp_num, connect_id);
+
+	if (sl_ctrl_lgrp_put(ctrl_lgrp))
+		sl_ctrl_log_dbg(NULL, LOG_NAME,
+				"connect_id set - lgrp removed (ctrl_lgrp = 0x%p)", ctrl_lgrp);
+
+	return 0;
+}
+
+int sl_ctrl_lgrp_config_set(u8 ldev_num, u8 lgrp_num, struct sl_lgrp_config *lgrp_config)
+{
+	int                 rtn;
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+
+	ctrl_lgrp = sl_ctrl_lgrp_get(ldev_num, lgrp_num);
+	if (!ctrl_lgrp) {
+		sl_ctrl_log_err(NULL, LOG_NAME, "NULL lgrp");
+		return -EBADRQC;
+	}
+
+	if (!sl_ctrl_lgrp_kref_get_unless_zero(ctrl_lgrp)) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"kref_get_unless_zero failed (ctrl_lgrp = 0x%p)", ctrl_lgrp);
+		return -EBADRQC;
+	}
+
+	sl_ctrl_log_dbg(ctrl_lgrp, LOG_NAME, "config set:");
+	sl_ctrl_log_dbg(ctrl_lgrp, LOG_NAME, "  mfs       = %d",   lgrp_config->mfs);
+	sl_ctrl_log_dbg(ctrl_lgrp, LOG_NAME, "  furcation = 0x%X", lgrp_config->furcation);
+	sl_ctrl_log_dbg(ctrl_lgrp, LOG_NAME, "  fec_mode  = 0x%X", lgrp_config->fec_mode);
+	sl_ctrl_log_dbg(ctrl_lgrp, LOG_NAME, "  tech_map  = 0x%X", lgrp_config->tech_map);
+	sl_ctrl_log_dbg(ctrl_lgrp, LOG_NAME, "  fec_map   = 0x%X", lgrp_config->fec_map);
+	sl_ctrl_log_dbg(ctrl_lgrp, LOG_NAME, "  options   = 0x%X", lgrp_config->options);
+
+	rtn = sl_core_lgrp_config_set(ldev_num, lgrp_num, lgrp_config);
+	if (rtn) {
+		sl_ctrl_log_err_trace(ctrl_lgrp, LOG_NAME, "core_lgrp_config_set failed [%d]", rtn);
+		goto out;
+	}
+
+	spin_lock(&(ctrl_lgrp->config_lock));
+	ctrl_lgrp->config = *lgrp_config;
+	spin_unlock(&(ctrl_lgrp->config_lock));
+
+	rtn = 0;
+
+out:
+	if (sl_ctrl_lgrp_put(ctrl_lgrp))
+		sl_ctrl_log_dbg(NULL, LOG_NAME,
+				"config set - lgrp removed (ctrl_lgrp = 0x%p)", ctrl_lgrp);
+
+	return rtn;
+}
+
+int sl_ctrl_lgrp_policy_set(u8 ldev_num, u8 lgrp_num, struct sl_lgrp_policy *lgrp_policy)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+
+	ctrl_lgrp = sl_ctrl_lgrp_get(ldev_num, lgrp_num);
+	if (!ctrl_lgrp) {
+		sl_ctrl_log_err(NULL, LOG_NAME, "NULL lgrp");
+		return -EBADRQC;
+	}
+
+	if (!sl_ctrl_lgrp_kref_get_unless_zero(ctrl_lgrp)) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"kref_get_unless_zero failed (lgrp = 0x%p)", ctrl_lgrp);
+		return -EBADRQC;
+	}
+
+	sl_ctrl_log_dbg(ctrl_lgrp, LOG_NAME, "policy set");
+
+	spin_lock(&(ctrl_lgrp->config_lock));
+	ctrl_lgrp->policy = *lgrp_policy;
+	spin_unlock(&(ctrl_lgrp->config_lock));
+
+	if (sl_ctrl_lgrp_put(ctrl_lgrp))
+		sl_ctrl_log_dbg(NULL, LOG_NAME,
+				"policy set - lgrp removed (ctrl_lgrp = 0x%p)", ctrl_lgrp);
+
+	return 0;
+}
diff --git a/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_lgrp_notif.c b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_lgrp_notif.c
new file mode 100644
index 000000000000..298b8ab0306c
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_lgrp_notif.c
@@ -0,0 +1,258 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2021-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/err.h>
+
+#include "base/sl_ctrl_log.h"
+#include "sl_ctrl_ldev.h"
+#include "sl_ctrl_lgrp.h"
+#include "sl_ctrl_lgrp_notif.h"
+#include "sl_media_lgrp.h"
+
+#define LOG_NAME SL_CTRL_LGRP_NOTIF_LOG_NAME
+
+#define SL_CTRL_LGRP_NOTIF_LIST_STATE_IDLE    0
+#define SL_CTRL_LGRP_NOTIF_LIST_STATE_SENDING 1
+
+static int sl_ctrl_lgrp_notif_list_state_get(struct sl_ctrl_lgrp *ctrl_lgrp)
+{
+	int notif_list_state;
+
+	spin_lock(&ctrl_lgrp->ctrl_notif.lock);
+	notif_list_state = ctrl_lgrp->ctrl_notif.list_state;
+	spin_unlock(&ctrl_lgrp->ctrl_notif.lock);
+
+	return notif_list_state;
+}
+
+int sl_ctrl_lgrp_notif_callback_reg(u8 ldev_num, u8 lgrp_num, sl_lgrp_notif_t callback,
+				    u32 types, void *tag)
+{
+	int                   rtn;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u8                    reg_idx;
+	u8                    counter;
+
+	ctrl_lgrp = sl_ctrl_lgrp_get(ldev_num, lgrp_num);
+	if (!ctrl_lgrp) {
+		sl_ctrl_log_err(NULL, LOG_NAME, "NULL ctrl_lgrp");
+		return -EBADRQC;
+	}
+
+	if (!sl_ctrl_lgrp_kref_get_unless_zero(ctrl_lgrp)) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"kref_get_unless_zero failed (ctrl_lgrp = 0x%p)", ctrl_lgrp);
+		return -EBADRQC;
+	}
+
+	sl_ctrl_log_dbg(ctrl_lgrp, LOG_NAME,
+			"notif callback reg (types = 0x%X, tag = 0x%p)",
+			types, tag);
+
+	counter = 0;
+	while (sl_ctrl_lgrp_notif_list_state_get(ctrl_lgrp) == SL_CTRL_LGRP_NOTIF_LIST_STATE_SENDING) {
+		msleep(20);
+		counter++;
+		if (counter >= 10) {
+			sl_ctrl_log_err(ctrl_lgrp, LOG_NAME, "registration timed out");
+			rtn = -ETIMEDOUT;
+			goto out;
+		}
+	}
+
+	spin_lock(&ctrl_lgrp->ctrl_notif.lock);
+	if (ctrl_lgrp->ctrl_notif.list_state == SL_CTRL_LGRP_NOTIF_LIST_STATE_SENDING) {
+		spin_unlock(&ctrl_lgrp->ctrl_notif.lock);
+		sl_ctrl_log_err(ctrl_lgrp, LOG_NAME, "notif list is currently being used");
+		rtn = -EBUSY;
+		goto out;
+	}
+	for (reg_idx = 0; reg_idx < ARRAY_SIZE(ctrl_lgrp->ctrl_notif.reg_entry); ++reg_idx) {
+		if (ctrl_lgrp->ctrl_notif.reg_entry[reg_idx].types == 0) {
+			ctrl_lgrp->ctrl_notif.reg_entry[reg_idx].callback = callback;
+			ctrl_lgrp->ctrl_notif.reg_entry[reg_idx].tag = tag;
+			ctrl_lgrp->ctrl_notif.reg_entry[reg_idx].types = types;
+			break;
+		}
+	}
+	spin_unlock(&ctrl_lgrp->ctrl_notif.lock);
+
+	if (reg_idx >= ARRAY_SIZE(ctrl_lgrp->ctrl_notif.reg_entry)) {
+		sl_ctrl_log_err(ctrl_lgrp, LOG_NAME, "registration list is full");
+		rtn = -ENOSPC;
+		goto out;
+	}
+
+	if (types & SL_LGRP_NOTIF_MEDIA_PRESENT)
+		sl_media_lgrp_real_cable_if_present_send(ldev_num, lgrp_num);
+
+	if (types & SL_LGRP_NOTIF_MEDIA_NOT_PRESENT)
+		sl_media_lgrp_real_cable_if_not_present_send(ldev_num, lgrp_num);
+
+	if (types & SL_LGRP_NOTIF_MEDIA_HOT)
+		sl_media_lgrp_cable_hot_send(ldev_num, lgrp_num);
+
+	if (types & SL_LGRP_NOTIF_MEDIA_WARM)
+		sl_media_lgrp_cable_warm_send(ldev_num, lgrp_num);
+
+	if (types & SL_LGRP_NOTIF_MEDIA_COLD)
+		sl_media_lgrp_cable_cold_send(ldev_num, lgrp_num);
+
+	rtn = 0;
+out:
+	if (sl_ctrl_lgrp_put(ctrl_lgrp))
+		sl_ctrl_log_dbg(NULL, LOG_NAME,
+				"notif callback reg - lgrp removed (ctrl_lgrp = 0x%p)", ctrl_lgrp);
+
+	return rtn;
+}
+
+int sl_ctrl_lgrp_notif_callback_unreg(u8 ldev_num, u8 lgrp_num, sl_lgrp_notif_t callback,
+				      u32 types)
+{
+	int                   rtn;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u8                    reg_idx;
+	u8                    counter;
+
+	ctrl_lgrp = sl_ctrl_lgrp_get(ldev_num, lgrp_num);
+	if (!ctrl_lgrp) {
+		sl_ctrl_log_err(NULL, LOG_NAME, "NULL ctrl_lgrp");
+		return -EBADRQC;
+	}
+
+	if (!sl_ctrl_lgrp_kref_get_unless_zero(ctrl_lgrp)) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"kref_get_unless_zero failed (ctrl_lgrp = 0x%p)", ctrl_lgrp);
+		return -EBADRQC;
+	}
+
+	sl_media_lgrp_cable_temp_flags_clr(ldev_num, lgrp_num);
+
+	counter = 0;
+	while (sl_ctrl_lgrp_notif_list_state_get(ctrl_lgrp) == SL_CTRL_LGRP_NOTIF_LIST_STATE_SENDING) {
+		msleep(20);
+		counter++;
+		if (counter >= 10) {
+			sl_ctrl_log_err(ctrl_lgrp, LOG_NAME, "unregistration timed out");
+			rtn = -ETIMEDOUT;
+			goto out;
+		}
+	}
+
+	spin_lock(&ctrl_lgrp->ctrl_notif.lock);
+	if (ctrl_lgrp->ctrl_notif.list_state == SL_CTRL_LGRP_NOTIF_LIST_STATE_SENDING) {
+		spin_unlock(&ctrl_lgrp->ctrl_notif.lock);
+		sl_ctrl_log_err(ctrl_lgrp, LOG_NAME, "notif list is currently being used");
+		rtn = -EBUSY;
+		goto out;
+	}
+	for (reg_idx = 0; reg_idx < ARRAY_SIZE(ctrl_lgrp->ctrl_notif.reg_entry); ++reg_idx) {
+		if ((ctrl_lgrp->ctrl_notif.reg_entry[reg_idx].types == types) &&
+		    (ctrl_lgrp->ctrl_notif.reg_entry[reg_idx].callback == callback)) {
+			ctrl_lgrp->ctrl_notif.reg_entry[reg_idx].callback = NULL;
+			ctrl_lgrp->ctrl_notif.reg_entry[reg_idx].tag = NULL;
+			ctrl_lgrp->ctrl_notif.reg_entry[reg_idx].types = 0;
+			break;
+		}
+	}
+	spin_unlock(&ctrl_lgrp->ctrl_notif.lock);
+
+	sl_ctrl_log_dbg(ctrl_lgrp, LOG_NAME, "notif callback unreg (types = 0x%X)", types);
+
+	rtn = 0;
+
+out:
+	if (sl_ctrl_lgrp_put(ctrl_lgrp))
+		sl_ctrl_log_dbg(NULL, LOG_NAME,
+				"notif callback unreg - lgrp removed (ctrl_lgrp = 0x%p)", ctrl_lgrp);
+
+	return rtn;
+}
+
+int sl_ctrl_lgrp_notif_enqueue(struct sl_ctrl_lgrp *ctrl_lgrp, u8 link_num,
+			       u32 type, union sl_lgrp_notif_info *info, u64 info_map)
+{
+	struct sl_lgrp_notif_msg notif_msg;
+	int                      rtn;
+
+	if (!ctrl_lgrp)
+		return 0;
+
+	sl_ctrl_log_dbg(ctrl_lgrp, LOG_NAME,
+			"notif enqueue (link_num = %d, type = 0x%X)", link_num, type);
+
+	spin_lock(&ctrl_lgrp->ctrl_notif.lock);
+	if (kfifo_is_full(&ctrl_lgrp->ctrl_notif.fifo)) {
+		spin_unlock(&ctrl_lgrp->ctrl_notif.lock);
+		sl_ctrl_log_err(ctrl_lgrp, LOG_NAME, "notification fifo is full");
+		return -ENOSPC;
+	}
+	spin_unlock(&ctrl_lgrp->ctrl_notif.lock);
+
+	if (info)
+		notif_msg.info = *info;
+	else
+		memset(&notif_msg.info, 0, sizeof(notif_msg.info));
+
+	notif_msg.ldev_num = ctrl_lgrp->ctrl_ldev->num;
+	notif_msg.lgrp_num = ctrl_lgrp->num;
+	notif_msg.link_num = link_num;
+	notif_msg.type     = type;
+	notif_msg.info_map = info_map;
+
+	rtn = kfifo_in_spinlocked(&ctrl_lgrp->ctrl_notif.fifo, &notif_msg, sizeof(notif_msg),
+				  &ctrl_lgrp->ctrl_notif.lock);
+	if (rtn != sizeof(notif_msg)) {
+		sl_ctrl_log_err(ctrl_lgrp, LOG_NAME, "write to kfifo failed");
+		return -EFAULT;
+	}
+
+	/* Don't catch the return as it might already be running.  This is ok */
+	queue_work(ctrl_lgrp->ctrl_ldev->notif_workq, &ctrl_lgrp->notif_work);
+
+	return 0;
+}
+
+void sl_ctrl_lgrp_notif_work(struct work_struct *notif_work)
+{
+	struct sl_ctrl_lgrp      *ctrl_lgrp;
+	struct sl_lgrp_notif_msg  notif_msg;
+	u8                        reg_idx;
+	int                       rtn;
+	bool                      is_empty;
+
+	ctrl_lgrp = container_of(notif_work, struct sl_ctrl_lgrp, notif_work);
+
+	sl_ctrl_log_dbg(ctrl_lgrp, LOG_NAME, "notif work");
+
+	spin_lock(&ctrl_lgrp->ctrl_notif.lock);
+	ctrl_lgrp->ctrl_notif.list_state = SL_CTRL_LGRP_NOTIF_LIST_STATE_SENDING;
+	spin_unlock(&ctrl_lgrp->ctrl_notif.lock);
+
+	do {
+		rtn = kfifo_out_spinlocked(&ctrl_lgrp->ctrl_notif.fifo,
+					   &notif_msg, sizeof(notif_msg),
+					   &ctrl_lgrp->ctrl_notif.lock);
+		if (rtn != sizeof(notif_msg)) {
+			sl_ctrl_log_err(ctrl_lgrp, LOG_NAME, "read from kfifo failed");
+			goto out;
+		}
+		for (reg_idx = 0; reg_idx < SL_CTRL_LGRP_NOTIF_REG_COUNT; ++reg_idx) {
+			if (notif_msg.type & ctrl_lgrp->ctrl_notif.reg_entry[reg_idx].types)
+				(ctrl_lgrp->ctrl_notif.reg_entry[reg_idx].callback)
+				(ctrl_lgrp->ctrl_notif.reg_entry[reg_idx].tag, &notif_msg);
+		}
+		spin_lock(&ctrl_lgrp->ctrl_notif.lock);
+		is_empty = kfifo_is_empty(&ctrl_lgrp->ctrl_notif.fifo);
+		spin_unlock(&ctrl_lgrp->ctrl_notif.lock);
+	} while (!is_empty);
+
+out:
+	spin_lock(&ctrl_lgrp->ctrl_notif.lock);
+	ctrl_lgrp->ctrl_notif.list_state = SL_CTRL_LGRP_NOTIF_LIST_STATE_IDLE;
+	spin_unlock(&ctrl_lgrp->ctrl_notif.lock);
+}
diff --git a/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_link.c b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_link.c
new file mode 100644
index 000000000000..f3a8246fcb67
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_link.c
@@ -0,0 +1,1230 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2021-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kobject.h>
+#include <linux/spinlock.h>
+#include <linux/slab.h>
+#include <linux/completion.h>
+
+#include "sl_asic.h"
+#include "sl_sysfs.h"
+#include "base/sl_ctrl_log.h"
+#include "sl_ctrl_ldev.h"
+#include "sl_ctrl_lgrp.h"
+#include "sl_ctrl_link.h"
+#include "data/sl_ctrl_data_link.h"
+#include "sl_ctrl_link_priv.h"
+#include "sl_ctrl_link_counters.h"
+#include "sl_core_str.h"
+#include "sl_core_link.h"
+#include "sl_core_link_an.h"
+#include "sl_core_mac.h"
+#include "sl_core_llr.h"
+#include "sl_core_link_an.h"
+#include "sl_test_common.h"
+
+#define LOG_NAME SL_CTRL_LINK_LOG_NAME
+
+#define SL_CTRL_LINK_DOWN_WAIT_TIMEOUT_MS 2000
+#define SL_CTRL_LINK_DEL_WAIT_TIMEOUT_MS  2000
+
+static struct sl_ctrl_link *ctrl_links[SL_ASIC_MAX_LDEVS][SL_ASIC_MAX_LGRPS][SL_ASIC_MAX_LINKS];
+static DEFINE_SPINLOCK(ctrl_links_lock);
+
+static void sl_ctrl_link_release_work(struct work_struct *work);
+
+int sl_ctrl_link_new(u8 ldev_num, u8 lgrp_num, u8 link_num, struct kobject *sysfs_parent)
+{
+	int                  rtn;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	struct sl_ctrl_link *ctrl_link;
+
+	ctrl_lgrp = sl_ctrl_lgrp_get(ldev_num, lgrp_num);
+	if (!ctrl_lgrp) {
+		sl_ctrl_log_err(NULL, LOG_NAME, "missing lgrp (lgrp_num = %u)", lgrp_num);
+		return -EBADRQC;
+	}
+
+	spin_lock(&ctrl_links_lock);
+	ctrl_link = ctrl_links[ldev_num][lgrp_num][link_num];
+	spin_unlock(&ctrl_links_lock);
+	if (ctrl_link) {
+		sl_ctrl_log_err(NULL, LOG_NAME, "new - link exists");
+		return -EBADRQC;
+	}
+
+	ctrl_link = kzalloc(sizeof(struct sl_ctrl_link), GFP_KERNEL);
+	if (!ctrl_link)
+		return -ENOMEM;
+
+	ctrl_link->magic    = SL_CTRL_LINK_MAGIC;
+	ctrl_link->ver      = SL_CTRL_LINK_VER;
+	ctrl_link->num      = link_num;
+	ctrl_link->ctrl_lgrp = sl_ctrl_lgrp_get(ldev_num, lgrp_num);
+
+	kref_init(&ctrl_link->ref_cnt);
+	kref_init(&ctrl_link->mem_ref);
+	INIT_WORK(&ctrl_link->release_work, sl_ctrl_link_release_work);
+	mutex_init(&ctrl_link->delete_lock);
+	init_completion(&ctrl_link->del_complete);
+
+	spin_lock_init(&ctrl_link->config_lock);
+	spin_lock_init(&ctrl_link->data_lock);
+
+	rtn = sl_ctrl_link_counters_init(ctrl_link);
+	if (rtn) {
+		sl_ctrl_log_err(ctrl_link, LOG_NAME,
+				"ctrl_link_counters_init failed [%d]", rtn);
+		goto out;
+	}
+
+	rtn = sl_ctrl_link_cause_counters_init(ctrl_link);
+	if (rtn) {
+		sl_ctrl_log_err(ctrl_link, LOG_NAME,
+				"ctrl_link_cause_counters_init failed [%d]", rtn);
+		goto out_counters;
+	}
+
+	rtn = sl_ctrl_link_an_cause_counters_init(ctrl_link);
+	if (rtn) {
+		sl_ctrl_log_err(ctrl_link, LOG_NAME,
+				"ctrl_link_an_cause_counters_init failed [%d]", rtn);
+		goto out_cause_counters;
+	}
+
+	ctrl_link->up_clock.start           = ktime_set(0, 0);
+	ctrl_link->up_clock.elapsed         = ktime_set(0, 0);
+	ctrl_link->up_clock.attempt_count   = 0;
+	ctrl_link->up_clock.attempt_start   = ktime_set(0, 0);
+	ctrl_link->up_clock.attempt_elapsed = ktime_set(0, 0);
+	spin_lock_init(&ctrl_link->up_clock.lock);
+
+	spin_lock_init(&ctrl_link->fec_data.lock);
+	timer_setup(&ctrl_link->fec_mon_timer, sl_ctrl_link_fec_mon_timer, 0);
+	spin_lock_init(&ctrl_link->fec_mon_timer_lock);
+	ctrl_link->fec_data.curr_ptr = &ctrl_link->fec_data.cntrs[0];
+	ctrl_link->fec_data.prev_ptr = &ctrl_link->fec_data.cntrs[1];
+	INIT_WORK(&ctrl_link->fec_mon_timer_work, sl_ctrl_link_fec_mon_timer_work);
+
+	spin_lock_init(&ctrl_link->fec_up_cache.lock);
+	spin_lock_init(&ctrl_link->fec_down_cache.lock);
+
+	ctrl_link->state = SL_LINK_STATE_DOWN;
+
+	rtn = sl_core_link_new(ldev_num, lgrp_num, link_num);
+	if (rtn) {
+		sl_ctrl_log_err_trace(ctrl_link, LOG_NAME,
+				      "core_link_new failed [%d]", rtn);
+		goto out_an_counters;
+	}
+
+	if (sysfs_parent) {
+		ctrl_link->parent_kobj = sysfs_parent;
+
+		rtn = sl_sysfs_link_create(ctrl_link);
+		if (rtn) {
+			sl_ctrl_log_err_trace(ctrl_link, LOG_NAME,
+					      "sysfs_link_create failed [%d]", rtn);
+			goto out_core_link;
+		}
+	}
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "new (link = 0x%p)", ctrl_link);
+
+	spin_lock(&ctrl_links_lock);
+	ctrl_links[ldev_num][lgrp_num][link_num] = ctrl_link;
+	spin_unlock(&ctrl_links_lock);
+
+	return 0;
+
+out_core_link:
+	sl_core_link_del(ldev_num, lgrp_num, link_num);
+out_an_counters:
+	sl_ctrl_link_an_cause_counters_del(ctrl_link);
+out_cause_counters:
+	sl_ctrl_link_cause_counters_del(ctrl_link);
+out_counters:
+	sl_ctrl_link_counters_del(ctrl_link);
+out:
+	kfree(ctrl_link);
+	return rtn;
+}
+
+static int sl_ctrl_link_down_cmd(struct sl_ctrl_link *ctrl_link)
+{
+	int rtn;
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "down cmd");
+
+	SL_CTRL_LINK_COUNTER_INC(ctrl_link, LINK_DOWN_CMD);
+
+	sl_ctrl_link_up_clock_reset(ctrl_link);
+
+	sl_ctrl_link_fec_mon_stop(ctrl_link);
+	cancel_work_sync(&ctrl_link->fec_mon_timer_work);
+
+	rtn = sl_core_link_an_lp_caps_stop(ctrl_link->ctrl_lgrp->ctrl_ldev->num,
+					   ctrl_link->ctrl_lgrp->num, ctrl_link->num);
+	if (rtn)
+		sl_ctrl_log_warn_trace(ctrl_link, LOG_NAME,
+				       "del core_link_an_lp_caps_stop failed [%d]", rtn);
+
+	rtn = sl_core_link_down(ctrl_link->ctrl_lgrp->ctrl_ldev->num, ctrl_link->ctrl_lgrp->num, ctrl_link->num,
+				sl_ctrl_link_down_callback, ctrl_link, SL_LINK_DOWN_CAUSE_COMMAND_MAP);
+	if (rtn) {
+		sl_ctrl_log_err(ctrl_link, LOG_NAME, "core_link_down failed [%d]", rtn);
+		return rtn;
+	}
+
+	return 0;
+}
+
+static int sl_ctrl_link_cancel_cmd(struct sl_ctrl_link *ctrl_link)
+{
+	int rtn;
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "cancel cmd");
+
+	SL_CTRL_LINK_COUNTER_INC(ctrl_link, LINK_UP_CANCEL_CMD);
+
+	sl_ctrl_link_fec_mon_stop(ctrl_link);
+	cancel_work_sync(&ctrl_link->fec_mon_timer_work);
+
+	rtn = sl_core_link_an_lp_caps_stop(ctrl_link->ctrl_lgrp->ctrl_ldev->num,
+					   ctrl_link->ctrl_lgrp->num, ctrl_link->num);
+	if (rtn)
+		sl_ctrl_log_warn_trace(ctrl_link, LOG_NAME,
+				       "del core_link_an_lp_caps_stop failed [%d]", rtn);
+
+	rtn = sl_core_link_cancel(ctrl_link->ctrl_lgrp->ctrl_ldev->num, ctrl_link->ctrl_lgrp->num, ctrl_link->num,
+				  sl_ctrl_link_down_callback, ctrl_link);
+	if (rtn) {
+		sl_ctrl_log_err(ctrl_link, LOG_NAME, "core_link_down failed [%d]", rtn);
+		return rtn;
+	}
+
+	return 0;
+}
+
+static void sl_ctrl_link_down_wait(struct sl_ctrl_link *ctrl_link)
+{
+	unsigned long timeleft;
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "down wait");
+
+	timeleft = wait_for_completion_timeout(&ctrl_link->down_complete,
+					       msecs_to_jiffies(SL_CTRL_LINK_DOWN_WAIT_TIMEOUT_MS));
+	if (timeleft == 0)
+		sl_ctrl_log_err(ctrl_link, LOG_NAME,
+				"del completion_timeout (down_complete = 0x%p)",
+			&ctrl_link->down_complete);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "del completion (timeleft = %lu)", timeleft);
+}
+
+static void sl_ctrl_link_free(struct kref *kref)
+{
+	kfree(container_of(kref, struct sl_ctrl_link, mem_ref));
+}
+
+static void sl_ctrl_link_release_work(struct work_struct *work)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  link_state;
+	u8                   ldev_num;
+	u8                   lgrp_num;
+	u8                   link_num;
+	int                  rtn;
+
+	ctrl_link = container_of(work, struct sl_ctrl_link, release_work);
+	ldev_num = ctrl_link->ctrl_lgrp->ctrl_ldev->num;
+	lgrp_num = ctrl_link->ctrl_lgrp->num;
+	link_num = ctrl_link->num;
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "release (link = 0x%p)", ctrl_link);
+
+	spin_lock(&ctrl_link->data_lock);
+	link_state = ctrl_link->state;
+	switch (link_state) {
+	case SL_LINK_STATE_STARTING:
+		ctrl_link->is_canceled = true;
+		spin_unlock(&ctrl_link->data_lock);
+		SL_CTRL_LINK_COUNTER_INC(ctrl_link, LINK_UP_CANCEL_CMD);
+		sl_ctrl_link_cancel_cmd(ctrl_link);
+		sl_ctrl_link_down_wait(ctrl_link);
+		break;
+	case SL_LINK_STATE_UP:
+	case SL_LINK_STATE_UP_DOWN_REQ:
+		ctrl_link->state = SL_LINK_STATE_STOPPING;
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "release stopping");
+		spin_unlock(&ctrl_link->data_lock);
+		sl_ctrl_link_down_cmd(ctrl_link);
+		sl_ctrl_link_down_wait(ctrl_link);
+		break;
+	case SL_LINK_STATE_STOPPING:
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "release already stopping");
+		spin_unlock(&ctrl_link->data_lock);
+		sl_ctrl_link_down_wait(ctrl_link);
+		break;
+	case SL_LINK_STATE_DOWN:
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "release already down");
+		spin_unlock(&ctrl_link->data_lock);
+		break;
+	case SL_LINK_STATE_INVALID:
+	default:
+		sl_ctrl_log_err(ctrl_link, LOG_NAME, "release invalid state (link_state = %u %s)",
+				link_state, sl_link_state_str(link_state));
+		spin_unlock(&ctrl_link->data_lock);
+		rtn = -EBUSY;
+		goto out_retry;
+	}
+
+	spin_lock(&ctrl_link->data_lock);
+	link_state = ctrl_link->state;
+	spin_unlock(&ctrl_link->data_lock);
+	if (link_state != SL_LINK_STATE_DOWN) {
+		rtn = -EBUSY;
+		goto out_retry;
+	}
+
+	if (!ctrl_link->sysfs_deleted) {
+		/* Must delete sysfs first to guarantee nobody is reading */
+		sl_sysfs_link_delete(ctrl_link);
+		ctrl_link->sysfs_deleted = true;
+	}
+
+	rtn = sl_core_link_del(ldev_num, lgrp_num, link_num);
+	if (rtn) {
+		sl_ctrl_log_err_trace(ctrl_link, LOG_NAME,
+				      "release - core_link_del failed [%d]", rtn);
+		goto out_retry;
+	}
+
+	sl_ctrl_link_counters_del(ctrl_link);
+	sl_ctrl_link_cause_counters_del(ctrl_link);
+	sl_ctrl_link_an_cause_counters_del(ctrl_link);
+
+	spin_lock(&ctrl_links_lock);
+	ctrl_links[ldev_num][lgrp_num][link_num] = NULL;
+	spin_unlock(&ctrl_links_lock);
+
+	ctrl_link->delete_result = 0;
+	complete_all(&ctrl_link->del_complete);
+
+	kref_put(&ctrl_link->mem_ref, sl_ctrl_link_free);
+	return;
+
+out_retry:
+	spin_lock(&ctrl_links_lock);
+	ctrl_link->delete_result = rtn;
+	kref_init(&ctrl_link->ref_cnt);
+	ctrl_link->delete_requested = false;
+	complete_all(&ctrl_link->del_complete);
+	spin_unlock(&ctrl_links_lock);
+}
+
+static void sl_ctrl_link_release(struct kref *kref)
+{
+	struct sl_ctrl_link *ctrl_link = container_of(kref, struct sl_ctrl_link, ref_cnt);
+
+	queue_work(system_unbound_wq, &ctrl_link->release_work);
+}
+
+int sl_ctrl_link_put(struct sl_ctrl_link *ctrl_link)
+{
+	return ctrl_link ? kref_put(&ctrl_link->ref_cnt, sl_ctrl_link_release) : 0;
+}
+
+int sl_ctrl_link_del(u8 ldev_num, u8 lgrp_num, u8 link_num)
+{
+	struct sl_ctrl_link *ctrl_link;
+	unsigned long        timeleft;
+	bool                 drop_owner = false;
+	int                  rtn;
+
+	sl_ctrl_log_dbg(NULL, LOG_NAME, "link del (ldev_num = %u, lgrp_num = %u, link_num = %u)",
+			ldev_num, lgrp_num, link_num);
+
+	spin_lock(&ctrl_links_lock);
+	ctrl_link = ctrl_links[ldev_num][lgrp_num][link_num];
+	if (ctrl_link)
+		kref_get(&ctrl_link->mem_ref);
+	spin_unlock(&ctrl_links_lock);
+	if (!ctrl_link) {
+		sl_ctrl_log_err_trace(NULL, LOG_NAME,
+				      "link del link not found (ldev_num = %u, lgrp_num = %u, link_num = %u)",
+			ldev_num, lgrp_num, link_num);
+		return -EBADRQC;
+	}
+
+	mutex_lock(&ctrl_link->delete_lock);
+	spin_lock(&ctrl_links_lock);
+	if (!ctrl_link->delete_requested) {
+		ctrl_link->delete_requested = true;
+		reinit_completion(&ctrl_link->del_complete);
+		drop_owner = true;
+	}
+	spin_unlock(&ctrl_links_lock);
+	if (drop_owner)
+		sl_ctrl_link_put(ctrl_link);
+
+	timeleft = wait_for_completion_timeout(&ctrl_link->del_complete,
+					       msecs_to_jiffies(SL_CTRL_LINK_DEL_WAIT_TIMEOUT_MS));
+	rtn = timeleft ? ctrl_link->delete_result : -ETIMEDOUT;
+	mutex_unlock(&ctrl_link->delete_lock);
+	kref_put(&ctrl_link->mem_ref, sl_ctrl_link_free);
+	return rtn;
+}
+
+bool sl_ctrl_link_kref_get_unless_zero(struct sl_ctrl_link *ctrl_link)
+{
+	return (kref_get_unless_zero(&ctrl_link->ref_cnt) != 0);
+}
+
+struct sl_ctrl_link *sl_ctrl_link_get(u8 ldev_num, u8 lgrp_num, u8 link_num)
+{
+	struct sl_ctrl_link *ctrl_link;
+
+	spin_lock(&ctrl_links_lock);
+	ctrl_link = ctrl_links[ldev_num][lgrp_num][link_num];
+	if (ctrl_link && (ctrl_link->delete_requested ||
+			  !kref_get_unless_zero(&ctrl_link->ref_cnt)))
+		ctrl_link = NULL;
+	spin_unlock(&ctrl_links_lock);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "get (link = 0x%p)", ctrl_link);
+
+	return ctrl_link;
+}
+
+static int sl_ctrl_link_config_set_cmd(struct sl_ctrl_link *ctrl_link, struct sl_link_config *link_config)
+{
+	struct sl_core_link_config core_link_config;
+	int                        rtn;
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "config set cmd");
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "  link_up_timeout                = %ums",
+			link_config->link_up_timeout_ms);
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "  link_up_tries_max              = %d",
+			link_config->link_up_tries_max);
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "  fec_up_settle_wait             = %dms",
+			link_config->fec_up_settle_wait_ms);
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "  fec_up_check_wait              = %dms",
+			link_config->fec_up_check_wait_ms);
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "  fec_up_ucw_limit               = %d",
+			link_config->fec_up_ucw_limit);
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "  fec_up_ccw_limit               = %d",
+			link_config->fec_up_ccw_limit);
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "  pml_rec_timeout                = %ums",
+			link_config->pml_rec_timeout_ms);
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "  pml_rec_rate_limit_max_time    = %ums",
+			link_config->pml_rec_rate_limit_max_time_ms);
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "  pml_rec_rate_limit_window_size = %ums",
+			link_config->pml_rec_rate_limit_window_size_ms);
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "  pause_map                      = 0x%X",
+			link_config->pause_map);
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "  hpe_map                        = 0x%X",
+			link_config->hpe_map);
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "  options                        = 0x%X",
+			link_config->options);
+
+	/* Check if the configuration is locked. If we are performing an admin operation, then we can ignore the
+	 * lock bit and continue to write the config.
+	 */
+	spin_lock(&ctrl_link->config_lock);
+	if (!(link_config->options & SL_LINK_CONFIG_OPT_ADMIN) &&
+	    (ctrl_link->config.options & SL_LINK_CONFIG_OPT_LOCK)) {
+		sl_ctrl_log_info(ctrl_link, LOG_NAME, "link config locked (options: 0x%X)", ctrl_link->config.options);
+		spin_unlock(&ctrl_link->config_lock);
+		return 0;
+	}
+	spin_unlock(&ctrl_link->config_lock);
+
+	/* Admin bit is transient */
+	link_config->options &= ~SL_LINK_CONFIG_OPT_ADMIN;
+
+	if ((!link_config->fec_up_settle_wait_ms && link_config->fec_up_check_wait_ms) ||
+	    (link_config->fec_up_settle_wait_ms && !link_config->fec_up_check_wait_ms)) {
+		sl_ctrl_log_err(ctrl_link, LOG_NAME, "fec_up invalid (settle_wait = %ums, check_wait = %ums)",
+				link_config->fec_up_settle_wait_ms, link_config->fec_up_check_wait_ms);
+		return -EINVAL;
+	}
+
+	core_link_config.magic                = SL_CORE_LINK_CONFIG_MAGIC;
+	core_link_config.fault_start_callback = sl_ctrl_link_fault_start_callback;
+	core_link_config.fault_callback       = sl_ctrl_link_fault_callback;
+
+	/* timeouts */
+	core_link_config.link_up_timeout_ms = link_config->link_up_timeout_ms;
+
+	/* fec config */
+	core_link_config.fec_up_settle_wait_ms = link_config->fec_up_settle_wait_ms;
+	core_link_config.fec_up_check_wait_ms  = link_config->fec_up_check_wait_ms;
+	core_link_config.fec_up_ucw_limit      = link_config->fec_up_ucw_limit;
+	core_link_config.fec_up_ccw_limit      = link_config->fec_up_ccw_limit;
+
+	/* pml recovery config */
+	core_link_config.pml_rec_timeout_ms                = link_config->pml_rec_timeout_ms;
+	core_link_config.pml_rec_rate_limit_max_time_ms    = link_config->pml_rec_rate_limit_max_time_ms;
+	core_link_config.pml_rec_rate_limit_window_size_ms = link_config->pml_rec_rate_limit_window_size_ms;
+
+	/* maps */
+	core_link_config.hpe_map   = link_config->hpe_map;
+	core_link_config.pause_map = link_config->pause_map;
+
+	/* flags */
+	core_link_config.flags = link_config->options;
+
+	rtn = sl_core_link_config_set(ctrl_link->ctrl_lgrp->ctrl_ldev->num,
+				      ctrl_link->ctrl_lgrp->num, ctrl_link->num, &core_link_config);
+	if (rtn) {
+		sl_ctrl_log_err_trace(ctrl_link, LOG_NAME,
+				      "core_link_config_set failed [%d]", rtn);
+		return rtn;
+	}
+
+	spin_lock(&ctrl_link->config_lock);
+	ctrl_link->config = *link_config;
+	spin_unlock(&ctrl_link->config_lock);
+
+	if (ctrl_link->config.link_up_tries_max == SL_LINK_INFINITE_UP_TRIES)
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "link up tries set to infinite");
+
+	return 0;
+}
+
+int sl_ctrl_link_config_set(u8 ldev_num, u8 lgrp_num, u8 link_num,
+			    struct sl_link_config *link_config)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link __free(sl_ctrl_link_put) = NULL;
+	u32                  link_state;
+
+	ctrl_link = sl_ctrl_link_get(ldev_num, lgrp_num, link_num);
+	if (!ctrl_link)
+		return -ENODEV;
+	if (!ctrl_link) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"config set NULL link (ldev_num = %u, lgrp_num = %u, link_num = %u)",
+			ldev_num, lgrp_num, link_num);
+		return -EBADRQC;
+	}
+
+	if (!sl_ctrl_link_kref_get_unless_zero(ctrl_link)) {
+		sl_ctrl_log_err(ctrl_link, LOG_NAME, "config set link ref unavailable (ctrl_link = 0x%p)",
+				ctrl_link);
+		return -EBADRQC;
+	}
+
+	rtn = sl_ctrl_data_link_state_get(ctrl_link, &link_state);
+	if (rtn) {
+		sl_ctrl_log_err_trace(ctrl_link, LOG_NAME, "data_link_state_get failed [%d]", rtn);
+		goto out;
+	}
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "config set (link_state = %u %s)",
+			link_state, sl_link_state_str(link_state));
+
+	switch (link_state) {
+	case SL_LINK_STATE_DOWN:
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "config - set");
+		rtn = sl_ctrl_link_config_set_cmd(ctrl_link, link_config);
+		if (rtn) {
+			sl_ctrl_log_err_trace(ctrl_link, LOG_NAME, "link_config_set_cmd failed [%d]", rtn);
+			goto out;
+		}
+
+		rtn = 0;
+		goto out;
+	case SL_LINK_STATE_STARTING:
+	case SL_LINK_STATE_INVALID:
+	case SL_LINK_STATE_STOPPING:
+	case SL_LINK_STATE_UP:
+	case SL_LINK_STATE_UP_DOWN_REQ:
+	default:
+		sl_ctrl_log_err(ctrl_link, LOG_NAME, "config - invalid (link_state = %u %s)",
+				link_state, sl_link_state_str(link_state));
+		rtn = -EBADRQC;
+		goto out;
+	}
+
+out:
+	if (sl_ctrl_link_put(ctrl_link))
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "config - link removed (link = 0x%p)", ctrl_link);
+
+	return rtn;
+}
+
+int sl_ctrl_link_policy_set(u8 ldev_num, u8 lgrp_num, u8 link_num,
+			    struct sl_link_policy *link_policy)
+{
+	int                         rtn;
+	u32                         link_state;
+	struct sl_ctrl_link *ctrl_link __free(sl_ctrl_link_put) = NULL;
+	struct sl_core_link_policy  core_link_policy;
+
+	ctrl_link = sl_ctrl_link_get(ldev_num, lgrp_num, link_num);
+	if (!ctrl_link)
+		return -ENODEV;
+	if (!ctrl_link) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"policy set NULL link (ldev_num = %u, lgrp_num = %u, link_num = %u)",
+			ldev_num, lgrp_num, link_num);
+		return -EBADRQC;
+	}
+
+	if (!sl_ctrl_link_kref_get_unless_zero(ctrl_link)) {
+		sl_ctrl_log_err(ctrl_link, LOG_NAME, "policy set link ref unavailable (ctrl_link = 0x%p)",
+				ctrl_link);
+		return -EBADRQC;
+	}
+
+	/* Check if the policy is locked. If we are performing an admin operation, then we can ignore the
+	 * lock bit and continue to write the config.
+	 */
+	spin_lock(&ctrl_link->config_lock);
+	if (!(link_policy->options & SL_LINK_POLICY_OPT_ADMIN) &&
+	    (ctrl_link->policy.options & SL_LINK_POLICY_OPT_LOCK)) {
+		sl_ctrl_log_info(ctrl_link, LOG_NAME, "link policy locked (options: 0x%X)", ctrl_link->policy.options);
+		spin_unlock(&ctrl_link->config_lock);
+		rtn = 0;
+		goto out;
+	}
+	spin_unlock(&ctrl_link->config_lock);
+
+	/* Admin bit is transient */
+	link_policy->options &= ~SL_LINK_POLICY_OPT_ADMIN;
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "policy set");
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "  fec_mon_ucw_down_limit = %d", link_policy->fec_mon_ucw_down_limit);
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "  fec_mon_ucw_warn_limit = %d", link_policy->fec_mon_ucw_warn_limit);
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "  fec_mon_ccw_down_limit = %d", link_policy->fec_mon_ccw_down_limit);
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "  fec_mon_ccw_warn_limit = %d", link_policy->fec_mon_ccw_warn_limit);
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "  fec_mon_period         = %dms", link_policy->fec_mon_period_ms);
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "  options                = 0x%X", link_policy->options);
+
+	spin_lock(&ctrl_link->config_lock);
+	ctrl_link->policy = *link_policy;
+	spin_unlock(&ctrl_link->config_lock);
+
+	core_link_policy.options = link_policy->options;
+	rtn = sl_core_link_policy_set(ctrl_link->ctrl_lgrp->ctrl_ldev->num, ctrl_link->ctrl_lgrp->num, ctrl_link->num,
+				      &core_link_policy);
+	if (rtn) {
+		sl_core_log_err(ctrl_link, LOG_NAME, "core link policy set failed [%d]", rtn);
+		rtn = -EBADRQC;
+		goto out;
+	}
+
+	rtn = sl_ctrl_data_link_state_get(ctrl_link, &link_state);
+	if (rtn) {
+		sl_ctrl_log_err_trace(ctrl_link, LOG_NAME, "data link state get failed [%d]", rtn);
+		goto out;
+	}
+
+	if ((link_state != SL_LINK_STATE_UP) && (link_state != SL_LINK_STATE_UP_DOWN_REQ)) {
+		sl_core_log_dbg(ctrl_link, LOG_NAME, "link_policy_set not up (link_state = %u %s)", link_state,
+				sl_core_link_state_str(link_state));
+		rtn = 0;
+		goto out;
+	}
+
+	sl_ctrl_link_fec_mon_start(ctrl_link);
+
+	rtn = 0;
+
+out:
+	if (sl_ctrl_link_put(ctrl_link))
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "policy set - link removed (link = 0x%p)", ctrl_link);
+
+	return rtn;
+}
+
+int sl_ctrl_link_an_lp_caps_get(u8 ldev_num, u8 lgrp_num, u8 link_num,
+				struct sl_link_caps *caps, u32 timeout_ms, u32 flags)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link __free(sl_ctrl_link_put) = NULL;
+
+	ctrl_link = sl_ctrl_link_get(ldev_num, lgrp_num, link_num);
+	if (!ctrl_link)
+		return -ENODEV;
+	if (!ctrl_link) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"caps get NULL link (ldev_num = %u, lgrp_num = %u, link_num = %u)",
+			ldev_num, lgrp_num, link_num);
+		return -EBADRQC;
+	}
+
+	if (!sl_ctrl_link_kref_get_unless_zero(ctrl_link)) {
+		sl_ctrl_log_err(ctrl_link, LOG_NAME, "caps get link ref unavailable (ctrl_link = 0x%p)",
+				ctrl_link);
+		return -EBADRQC;
+	}
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "an lp caps get");
+
+	rtn = sl_core_link_an_lp_caps_get(ldev_num, lgrp_num, link_num,
+					  sl_ctrl_link_an_lp_caps_get_callback, ctrl_link, caps, timeout_ms, flags);
+	if (rtn)
+		sl_ctrl_log_err_trace(ctrl_link, LOG_NAME,
+				      "core_link_an_lp_caps_get failed [%d]", rtn);
+
+	if (sl_ctrl_link_put(ctrl_link))
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "an lp caps get - link removed (link = 0x%p)", ctrl_link);
+
+	return rtn;
+}
+
+int sl_ctrl_link_an_lp_caps_stop(u8 ldev_num, u8 lgrp_num, u8 link_num)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link __free(sl_ctrl_link_put) = NULL;
+
+	ctrl_link = sl_ctrl_link_get(ldev_num, lgrp_num, link_num);
+	if (!ctrl_link)
+		return -ENODEV;
+	if (!ctrl_link) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"caps stop NULL link (ldev_num = %u, lgrp_num = %u, link_num = %u)",
+			ldev_num, lgrp_num, link_num);
+		return -EBADRQC;
+	}
+
+	if (!sl_ctrl_link_kref_get_unless_zero(ctrl_link)) {
+		sl_ctrl_log_err(ctrl_link, LOG_NAME, "caps stop link ref unavailable (ctrl_link = 0x%p)",
+				ctrl_link);
+		return -EBADRQC;
+	}
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "an lp caps stop");
+
+	rtn = sl_core_link_an_lp_caps_stop(ldev_num, lgrp_num, link_num);
+	if (rtn)
+		sl_ctrl_log_err_trace(ctrl_link, LOG_NAME,
+				      "core_link_an_lp_caps_stop failed [%d]", rtn);
+
+	if (sl_ctrl_link_put(ctrl_link))
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "an lp caps stop - link removed (link = 0x%p)", ctrl_link);
+
+	return rtn;
+}
+
+static int sl_ctrl_link_up_cmd(struct sl_ctrl_link *ctrl_link)
+{
+	int rtn;
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "up cmd");
+
+	SL_CTRL_LINK_COUNTER_INC(ctrl_link, LINK_UP_CMD);
+
+	sl_ctrl_link_up_clock_start(ctrl_link);
+
+	sl_ctrl_link_is_canceled_set(ctrl_link, false);
+
+	init_completion(&ctrl_link->down_complete);
+
+	sl_ctrl_link_up_clock_attempt_start(ctrl_link);
+
+	rtn = sl_core_link_up(ctrl_link->ctrl_lgrp->ctrl_ldev->num, ctrl_link->ctrl_lgrp->num, ctrl_link->num,
+			      sl_ctrl_link_up_callback, ctrl_link);
+	if (rtn) {
+		sl_ctrl_link_state_set(ctrl_link, SL_LINK_STATE_STOPPING);
+
+		sl_ctrl_log_err_trace(ctrl_link, LOG_NAME, "core_link_up failed [%d]", rtn);
+
+		sl_ctrl_link_up_clock_reset(ctrl_link);
+
+		sl_ctrl_link_state_set(ctrl_link, SL_LINK_STATE_DOWN);
+
+		return rtn;
+	}
+
+	return 0;
+}
+
+int sl_ctrl_link_up(u8 ldev_num, u8 lgrp_num, u8 link_num)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link __free(sl_ctrl_link_put) = NULL;
+	u32                  link_state;
+
+	ctrl_link = sl_ctrl_link_get(ldev_num, lgrp_num, link_num);
+	if (!ctrl_link)
+		return -ENODEV;
+	if (!ctrl_link) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"link up NULL link (ldev_num = %u, lgrp_num = %u, link_num = %u)",
+			ldev_num, lgrp_num, link_num);
+		return -EBADRQC;
+	}
+
+	if (!sl_ctrl_link_kref_get_unless_zero(ctrl_link)) {
+		sl_ctrl_log_err(ctrl_link, LOG_NAME, "link up ref unavailable (ctrl_link = 0x%p)",
+				ctrl_link);
+		return -EBADRQC;
+	}
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "up");
+
+	spin_lock(&ctrl_link->data_lock);
+	link_state = ctrl_link->state;
+	switch (link_state) {
+	case SL_LINK_STATE_DOWN:
+		ctrl_link->state = SL_LINK_STATE_STARTING;
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "up - starting");
+		spin_unlock(&ctrl_link->data_lock);
+		rtn = sl_ctrl_link_up_cmd(ctrl_link);
+		if (rtn) {
+			sl_ctrl_log_err_trace(ctrl_link, LOG_NAME, "link_up_cmd failed [%d]", rtn);
+			goto out;
+		}
+
+		rtn = 0;
+		goto out;
+	case SL_LINK_STATE_STARTING:
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "up - already starting");
+		spin_unlock(&ctrl_link->data_lock);
+		rtn = -EINPROGRESS;
+		goto out;
+	case SL_LINK_STATE_UP:
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "up - already up");
+		spin_unlock(&ctrl_link->data_lock);
+		rtn = -EALREADY;
+		goto out;
+	case SL_LINK_STATE_UP_DOWN_REQ:
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "up - already up down requested");
+		spin_unlock(&ctrl_link->data_lock);
+		rtn = -EALREADY;
+		goto out;
+	case SL_LINK_STATE_STOPPING:
+	case SL_LINK_STATE_INVALID:
+	default:
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "up - invalid (link_state = %u %s)",
+				link_state, sl_link_state_str(link_state));
+		spin_unlock(&ctrl_link->data_lock);
+		rtn = -EBADRQC;
+		goto out;
+	}
+
+out:
+	if (sl_ctrl_link_put(ctrl_link))
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "up - link removed (link = 0x%p)", ctrl_link);
+
+	return rtn;
+}
+
+int sl_ctrl_link_down(u8 ldev_num, u8 lgrp_num, u8 link_num)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link __free(sl_ctrl_link_put) = NULL;
+	u32                  link_state;
+
+	ctrl_link = sl_ctrl_link_get(ldev_num, lgrp_num, link_num);
+	if (!ctrl_link)
+		return -ENODEV;
+	if (!ctrl_link) {
+		sl_ctrl_log_dbg(NULL, LOG_NAME,
+				"link down NULL link (ldev_num = %u, lgrp_num = %u, link_num = %u)",
+			ldev_num, lgrp_num, link_num);
+		return -EBADRQC;
+	}
+
+	if (!sl_ctrl_link_kref_get_unless_zero(ctrl_link)) {
+		sl_ctrl_log_err(ctrl_link, LOG_NAME, "link down ref unavailable (ctrl_link = 0x%p)",
+				ctrl_link);
+		return -EBADRQC;
+	}
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "down");
+
+	spin_lock(&ctrl_link->data_lock);
+	link_state = ctrl_link->state;
+	switch (link_state) {
+	case SL_LINK_STATE_STARTING:
+		ctrl_link->state = SL_LINK_STATE_STOPPING;
+		ctrl_link->is_canceled = true;
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "down - canceling");
+		spin_unlock(&ctrl_link->data_lock);
+		rtn = sl_ctrl_link_cancel_cmd(ctrl_link);
+		if (rtn) {
+			sl_ctrl_log_err_trace(ctrl_link, LOG_NAME, "cancel_cmd failed [%d]", rtn);
+			goto out;
+		}
+
+		rtn = 0;
+		goto out;
+	case SL_LINK_STATE_UP:
+	case SL_LINK_STATE_UP_DOWN_REQ:
+		ctrl_link->state = SL_LINK_STATE_STOPPING;
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "down - stopping");
+		spin_unlock(&ctrl_link->data_lock);
+		rtn = sl_ctrl_link_down_cmd(ctrl_link);
+		if (rtn) {
+			sl_ctrl_log_err_trace(ctrl_link, LOG_NAME, "down_cmd failed [%d]", rtn);
+			goto out;
+		}
+
+		rtn = 0;
+		goto out;
+	case SL_LINK_STATE_DOWN:
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "down - already down");
+		spin_unlock(&ctrl_link->data_lock);
+		rtn = -EALREADY;
+		goto out;
+	case SL_LINK_STATE_STOPPING:
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "down - already stopping");
+		spin_unlock(&ctrl_link->data_lock);
+		rtn = -EINPROGRESS;
+		goto out;
+	case SL_LINK_STATE_INVALID:
+	default:
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "down - invalid (link_state = %u %s)",
+				link_state, sl_link_state_str(link_state));
+		spin_unlock(&ctrl_link->data_lock);
+		rtn = -EBADRQC;
+		goto out;
+	}
+
+out:
+	if (sl_ctrl_link_put(ctrl_link))
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "down - link removed (link = 0x%p)", ctrl_link);
+
+	return rtn;
+}
+
+static int sl_ctrl_link_reset_cmd(struct sl_ctrl_link *ctrl_link)
+{
+	int           rtn;
+	u8            ldev_num;
+	u8            lgrp_num;
+	u8            link_num;
+	unsigned long timeleft;
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "reset cmd");
+
+	SL_CTRL_LINK_COUNTER_INC(ctrl_link, LINK_RESET_CMD);
+
+	sl_ctrl_link_up_clock_reset(ctrl_link);
+
+	sl_ctrl_link_fec_mon_stop(ctrl_link);
+	cancel_work_sync(&ctrl_link->fec_mon_timer_work);
+
+	ldev_num = ctrl_link->ctrl_lgrp->ctrl_ldev->num;
+	lgrp_num = ctrl_link->ctrl_lgrp->num;
+	link_num = ctrl_link->num;
+
+	rtn = sl_core_llr_stop(ldev_num, lgrp_num, link_num);
+	if (rtn)
+		sl_ctrl_log_warn_trace(ctrl_link, LOG_NAME, "core_llr_stop failed [%d]", rtn);
+
+	rtn = sl_core_mac_tx_stop(ldev_num, lgrp_num, link_num);
+	if (rtn)
+		sl_ctrl_log_warn_trace(ctrl_link, LOG_NAME, "core_mac_tx_stop failed [%d]", rtn);
+
+	rtn = sl_core_mac_rx_stop(ldev_num, lgrp_num, link_num);
+	if (rtn)
+		sl_ctrl_log_warn_trace(ctrl_link, LOG_NAME, "core_mac_rx_stop failed [%d]", rtn);
+
+	rtn = sl_core_link_down(ldev_num, lgrp_num, link_num, sl_ctrl_link_down_callback,
+				ctrl_link, SL_LINK_DOWN_CAUSE_COMMAND_MAP);
+	if (rtn)
+		sl_ctrl_log_warn(ctrl_link, LOG_NAME, "core_link_down failed [%d]", rtn);
+
+	timeleft = wait_for_completion_timeout(&ctrl_link->down_complete,
+					       msecs_to_jiffies(SL_CTRL_LINK_DOWN_WAIT_TIMEOUT_MS));
+	if (timeleft == 0)
+		sl_ctrl_log_err(ctrl_link, LOG_NAME,
+				"completion_timeout (down_complete = 0x%p)", &ctrl_link->down_complete);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "completion (timeleft = %lu)", timeleft);
+
+	sl_core_link_reset(ldev_num, lgrp_num, link_num);
+
+	return 0;
+}
+
+int sl_ctrl_link_reset(u8 ldev_num, u8 lgrp_num, u8 link_num)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link __free(sl_ctrl_link_put) = NULL;
+	u32                  link_state;
+
+	ctrl_link = sl_ctrl_link_get(ldev_num, lgrp_num, link_num);
+	if (!ctrl_link)
+		return -ENODEV;
+	if (!ctrl_link) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"link reset NULL link (ldev_num = %u, lgrp_num = %u, link_num = %u)",
+			ldev_num, lgrp_num, link_num);
+		return -EBADRQC;
+	}
+
+	if (!sl_ctrl_link_kref_get_unless_zero(ctrl_link)) {
+		sl_ctrl_log_err(ctrl_link, LOG_NAME, "link reset ref unavailable (ctrl_link = 0x%p)",
+				ctrl_link);
+		return -EBADRQC;
+	}
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "reset");
+
+	spin_lock(&ctrl_link->data_lock);
+	link_state = ctrl_link->state;
+	switch (link_state) {
+	case SL_LINK_STATE_STARTING:
+		ctrl_link->is_canceled = true;
+		SL_CTRL_LINK_COUNTER_INC(ctrl_link, LINK_UP_CANCEL_CMD);
+		fallthrough;
+	case SL_LINK_STATE_UP:
+	case SL_LINK_STATE_UP_DOWN_REQ:
+		ctrl_link->state = SL_LINK_STATE_STOPPING;
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "reset - stopping");
+		spin_unlock(&ctrl_link->data_lock);
+		rtn = sl_ctrl_link_reset_cmd(ctrl_link);
+		if (rtn) {
+			sl_ctrl_log_err_trace(ctrl_link, LOG_NAME, "link_reset_cmd failed [%d]", rtn);
+			goto out;
+		}
+
+		rtn = 0;
+		goto out;
+	case SL_LINK_STATE_DOWN:
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "reset - already down");
+		spin_unlock(&ctrl_link->data_lock);
+		rtn = 0;
+		goto out;
+	case SL_LINK_STATE_STOPPING:
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "down - already stopping");
+		spin_unlock(&ctrl_link->data_lock);
+
+		rtn = 0;
+		goto out;
+	case SL_LINK_STATE_INVALID:
+	default:
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "reset - invalid (link_state = %u %s)",
+				link_state, sl_link_state_str(link_state));
+		spin_unlock(&ctrl_link->data_lock);
+		rtn = -EBADRQC;
+		goto out;
+	}
+
+out:
+	if (sl_ctrl_link_put(ctrl_link))
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "reset - link removed (link = 0x%p)", ctrl_link);
+
+	return rtn;
+}
+
+int sl_ctrl_link_up_clocks_get(u8 ldev_num, u8 lgrp_num, u8 link_num,
+			       s64 *attempt_time, s64 *total_time, s64 *up_time)
+{
+	struct sl_ctrl_link *ctrl_link __free(sl_ctrl_link_put) = NULL;
+
+	ctrl_link = sl_ctrl_link_get(ldev_num, lgrp_num, link_num);
+	if (!ctrl_link)
+		return -ENODEV;
+	if (!ctrl_link) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"clocks get NULL link (ldev_num = %u, lgrp_num = %u, link_num = %u)",
+				ldev_num, lgrp_num, link_num);
+		return -EBADRQC;
+	}
+
+	if (!sl_ctrl_link_kref_get_unless_zero(ctrl_link)) {
+		sl_ctrl_log_err(ctrl_link, LOG_NAME, "clocks get link ref unavailable (ctrl_link = 0x%p)",
+				ctrl_link);
+		return -EBADRQC;
+	}
+
+	spin_lock(&ctrl_link->up_clock.lock);
+
+	if (!ktime_compare(ctrl_link->up_clock.attempt_start, ktime_set(0, 0)))
+		*attempt_time = ktime_to_ms(ctrl_link->up_clock.attempt_elapsed);
+	else
+		*attempt_time = ktime_to_ms(ktime_sub(ktime_get(), ctrl_link->up_clock.attempt_start));
+
+	if (!ktime_compare(ctrl_link->up_clock.start, ktime_set(0, 0)))
+		*total_time = ktime_to_ms(ctrl_link->up_clock.elapsed);
+	else
+		*total_time = ktime_to_ms(ktime_sub(ktime_get(), ctrl_link->up_clock.start));
+
+	if (!ktime_compare(ctrl_link->up_clock.up, ktime_set(0, 0)))
+		*up_time = 0;
+	else
+		*up_time = ktime_to_ms(ktime_sub(ktime_get(), ctrl_link->up_clock.up));
+
+	spin_unlock(&ctrl_link->up_clock.lock);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"clocks get (attempt_time = %lld, total_time = %lld)", *attempt_time, *total_time);
+
+	if (sl_ctrl_link_put(ctrl_link))
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "clocks get - link removed (link = 0x%p)", ctrl_link);
+
+	return 0;
+}
+
+int sl_ctrl_link_up_count_get(u8 ldev_num, u8 lgrp_num, u8 link_num, u32 *attempt_count)
+{
+	struct sl_ctrl_link *ctrl_link __free(sl_ctrl_link_put) = NULL;
+
+	ctrl_link = sl_ctrl_link_get(ldev_num, lgrp_num, link_num);
+	if (!ctrl_link)
+		return -ENODEV;
+	if (!ctrl_link) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"count get NULL link (ldev_num = %u, lgrp_num = %u, link_num = %u)",
+				ldev_num, lgrp_num, link_num);
+		return -EBADRQC;
+	}
+
+	if (!sl_ctrl_link_kref_get_unless_zero(ctrl_link)) {
+		sl_ctrl_log_err(ctrl_link, LOG_NAME, "count get link ref unavailable (ctrl_link = 0x%p)",
+				ctrl_link);
+		return -EBADRQC;
+	}
+
+	spin_lock(&ctrl_link->up_clock.lock);
+	*attempt_count = ctrl_link->up_clock.attempt_count;
+	spin_unlock(&ctrl_link->up_clock.lock);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "count get (attempt_count = %u)", *attempt_count);
+
+	if (sl_ctrl_link_put(ctrl_link))
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "count get - link removed (link = 0x%p)", ctrl_link);
+
+	return 0;
+}
+
+int sl_ctrl_link_state_get_cmd(u8 ldev_num, u8 lgrp_num, u8 link_num, u32 *state)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link __free(sl_ctrl_link_put) = NULL;
+
+	*state = SL_LINK_STATE_INVALID;
+	ctrl_link = sl_ctrl_link_get(ldev_num, lgrp_num, link_num);
+	if (!ctrl_link)
+		return -ENODEV;
+	if (!ctrl_link) {
+		sl_ctrl_log_dbg(NULL, LOG_NAME,
+				"state get NULL link (ldev_num = %u, lgrp_num = %u, link_num = %u)",
+			ldev_num, lgrp_num, link_num);
+		return 0;
+	}
+
+	if (!sl_ctrl_link_kref_get_unless_zero(ctrl_link)) {
+		sl_ctrl_log_err(ctrl_link, LOG_NAME, "state get kref unavailable (ctrl_link = 0x%p)", ctrl_link);
+		return -EBADRQC;
+	}
+
+	rtn = sl_ctrl_data_link_state_get(ctrl_link, state);
+	if (rtn) {
+		sl_ctrl_log_err_trace(ctrl_link, LOG_NAME, "data_link_state_get failed [%d]", rtn);
+		goto out;
+	}
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"state get (state = %u %s)",
+		*state, sl_link_state_str(*state));
+
+out:
+	sl_ctrl_link_put(ctrl_link);
+
+	return rtn;
+}
+
+int sl_ctrl_link_an_lp_caps_state_get(u8 ldev_num, u8 lgrp_num, u8 link_num, u32 *state)
+{
+	struct sl_ctrl_link *ctrl_link __free(sl_ctrl_link_put) = NULL;
+
+	ctrl_link = sl_ctrl_link_get(ldev_num, lgrp_num, link_num);
+	if (!ctrl_link)
+		return -ENODEV;
+	if (!ctrl_link) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"an lp caps state get NULL link (ldev_num = %u, lgrp_num = %u, link_num = %u)",
+			ldev_num, lgrp_num, link_num);
+		return -EINVAL;
+	}
+
+	if (!sl_ctrl_link_kref_get_unless_zero(ctrl_link)) {
+		sl_ctrl_log_err(ctrl_link, LOG_NAME,
+				"an lp caps state get kref unavailable (ctrl_link = 0x%p)", ctrl_link);
+		return -EBADRQC;
+	}
+
+	*state = sl_core_link_an_lp_caps_state_get(ldev_num, lgrp_num, link_num);
+
+	if (sl_ctrl_link_put(ctrl_link))
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "an lp caps state get - link removed (link = 0x%p)", ctrl_link);
+
+	return 0;
+}
+
+int sl_ctrl_link_an_fail_cause_get(u8 ldev_num, u8 lgrp_num, u8 link_num, u32 *fail_cause, time64_t *fail_time)
+{
+	int    rtn;
+	struct sl_ctrl_link *ctrl_link __free(sl_ctrl_link_put) = NULL;
+
+	ctrl_link = sl_ctrl_link_get(ldev_num, lgrp_num, link_num);
+	if (!ctrl_link)
+		return -ENODEV;
+	if (!ctrl_link) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"an fail cause get NULL link (ldev_num = %u, lgrp_num = %u, link_num = %u)",
+				ldev_num, lgrp_num, link_num);
+		return -EBADRQC;
+	}
+
+	if (!sl_ctrl_link_kref_get_unless_zero(ctrl_link)) {
+		sl_ctrl_log_err(ctrl_link, LOG_NAME,
+				"an fail cause get kref unavailable (ctrl_link = 0x%p)", ctrl_link);
+		return -EBADRQC;
+	}
+
+	rtn = sl_core_link_an_fail_cause_get(ldev_num, lgrp_num, link_num, fail_cause, fail_time);
+
+	if (sl_ctrl_link_put(ctrl_link))
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "an fail cause get - link removed (link = 0x%p)", ctrl_link);
+
+	return rtn;
+}
+
+u32 sl_ctrl_link_an_retry_count_get(struct sl_ctrl_link *ctrl_link, int *count)
+{
+	*count = sl_core_link_an_retry_count_get(ctrl_link->ctrl_lgrp->ctrl_ldev->num,
+						 ctrl_link->ctrl_lgrp->num, ctrl_link->num);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "an retry get (count = %d)", *count);
+
+	return 0;
+}
+
+int sl_ctrl_link_info_map_get(u8 ldev_num, u8 lgrp_num, u8 link_num, u64 *info_map)
+{
+	struct sl_ctrl_link *ctrl_link __free(sl_ctrl_link_put) = NULL;
+
+	ctrl_link = sl_ctrl_link_get(ldev_num, lgrp_num, link_num);
+	if (!ctrl_link)
+		return -ENODEV;
+	if (!ctrl_link) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"info map get NULL link (ldev_num = %u, lgrp_num = %u, link_num = %u)",
+			ldev_num, lgrp_num, link_num);
+		return -EBADRQC;
+	}
+
+	if (!sl_ctrl_link_kref_get_unless_zero(ctrl_link)) {
+		sl_ctrl_log_err(ctrl_link, LOG_NAME, "info map get ref unavailable (ctrl_link = 0x%p)",
+				ctrl_link);
+		return -EBADRQC;
+	}
+
+	*info_map = sl_core_link_info_map_get(ldev_num, lgrp_num, link_num);
+
+	if (sl_ctrl_link_put(ctrl_link))
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "info map get - link removed (link = 0x%p)", ctrl_link);
+
+	return 0;
+}
diff --git a/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_link_counters.c b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_link_counters.c
new file mode 100644
index 000000000000..1de7d93033b9
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_link_counters.c
@@ -0,0 +1,388 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2023-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/slab.h>
+
+#include "sl_ctrl_link.h"
+#include "sl_ctrl_link_counters.h"
+#include "base/sl_ctrl_log.h"
+#include "hw/sl_core_hw_an.h"
+
+#define LOG_NAME SL_CTRL_LINK_LOG_NAME
+
+#define SL_CTRL_LINK_COUNTER_INIT(_link, _counter) \
+	(_link)->counters[_counter].name = #_counter
+
+#define SL_CTRL_LINK_CAUSE_COUNTER_INIT(_link, _counter) \
+	(_link)->cause_counters[_counter].name = #_counter
+
+#define SL_CTRL_LINK_AN_CAUSE_COUNTER_INIT(_link, _counter) \
+	(_link)->an_cause_counters[_counter].name = #_counter
+
+int sl_ctrl_link_counters_init(struct sl_ctrl_link *ctrl_link)
+{
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "link counters init");
+
+	ctrl_link->counters = kzalloc(sizeof(struct sl_ctrl_link_counter) * SL_CTRL_LINK_COUNTERS_COUNT, GFP_KERNEL);
+	if (!ctrl_link->counters)
+		return -ENOMEM;
+
+	SL_CTRL_LINK_COUNTER_INIT(ctrl_link, LINK_UP_CMD);
+	SL_CTRL_LINK_COUNTER_INIT(ctrl_link, LINK_UP_RETRY);
+	SL_CTRL_LINK_COUNTER_INIT(ctrl_link, LINK_UP);
+	SL_CTRL_LINK_COUNTER_INIT(ctrl_link, LINK_UP_FAIL);
+
+	SL_CTRL_LINK_COUNTER_INIT(ctrl_link, LINK_DOWN_CMD);
+	SL_CTRL_LINK_COUNTER_INIT(ctrl_link, LINK_DOWN);
+
+	SL_CTRL_LINK_COUNTER_INIT(ctrl_link, LINK_UP_CANCEL_CMD);
+	SL_CTRL_LINK_COUNTER_INIT(ctrl_link, LINK_UP_CANCELED);
+	SL_CTRL_LINK_COUNTER_INIT(ctrl_link, LINK_RESET_CMD);
+
+	SL_CTRL_LINK_COUNTER_INIT(ctrl_link, LINK_FAULT_ASYNC);
+	SL_CTRL_LINK_COUNTER_INIT(ctrl_link, LINK_RECOVERING);
+
+	SL_CTRL_LINK_COUNTER_INIT(ctrl_link, LINK_CCW_WARN_CROSSED);
+	SL_CTRL_LINK_COUNTER_INIT(ctrl_link, LINK_UCW_WARN_CROSSED);
+
+	SL_CTRL_LINK_COUNTER_INIT(ctrl_link, LINK_DOWN_CCW_LIMIT_CROSSED);
+	SL_CTRL_LINK_COUNTER_INIT(ctrl_link, LINK_DOWN_UCW_LIMIT_CROSSED);
+	SL_CTRL_LINK_COUNTER_INIT(ctrl_link, LINK_DOWN_CCW_CAUSE);
+	SL_CTRL_LINK_COUNTER_INIT(ctrl_link, LINK_DOWN_UCW_CAUSE);
+
+	SL_CTRL_LINK_COUNTER_INIT(ctrl_link, LINK_UP_FAIL_CCW_LIMIT_CROSSED);
+	SL_CTRL_LINK_COUNTER_INIT(ctrl_link, LINK_UP_FAIL_UCW_LIMIT_CROSSED);
+
+	SL_CTRL_LINK_COUNTER_INIT(ctrl_link, LINK_HW_AN_ATTEMPT);
+
+	return 0;
+}
+
+int sl_ctrl_link_counters_get(struct sl_ctrl_link *ctrl_link, u32 counter, int *count)
+{
+	*count = atomic_read(&ctrl_link->counters[counter].count);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "get (counter = %u %s, count = %d)", counter,
+			ctrl_link->counters[counter].name, *count);
+
+	return 0;
+}
+
+void sl_ctrl_link_counters_del(struct sl_ctrl_link *ctrl_link)
+{
+	kfree(ctrl_link->counters);
+}
+
+int sl_ctrl_link_cause_counters_init(struct sl_ctrl_link *ctrl_link)
+{
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "link cause counters init");
+
+	ctrl_link->cause_counters = kzalloc(sizeof(*ctrl_link->cause_counters) *
+					    SL_CTRL_LINK_CAUSE_COUNTERS_COUNT, GFP_KERNEL);
+	if (!ctrl_link->cause_counters)
+		return -ENOMEM;
+
+	SL_CTRL_LINK_CAUSE_COUNTER_INIT(ctrl_link, LINK_CAUSE_UCW);
+	SL_CTRL_LINK_CAUSE_COUNTER_INIT(ctrl_link, LINK_CAUSE_LF);
+	SL_CTRL_LINK_CAUSE_COUNTER_INIT(ctrl_link, LINK_CAUSE_RF);
+	SL_CTRL_LINK_CAUSE_COUNTER_INIT(ctrl_link, LINK_CAUSE_DOWN);
+	SL_CTRL_LINK_CAUSE_COUNTER_INIT(ctrl_link, LINK_CAUSE_UP_TRIES);
+	SL_CTRL_LINK_CAUSE_COUNTER_INIT(ctrl_link, LINK_CAUSE_AUTONEG_NOMATCH);
+	SL_CTRL_LINK_CAUSE_COUNTER_INIT(ctrl_link, LINK_CAUSE_AUTONEG);
+	SL_CTRL_LINK_CAUSE_COUNTER_INIT(ctrl_link, LINK_CAUSE_CONFIG);
+	SL_CTRL_LINK_CAUSE_COUNTER_INIT(ctrl_link, LINK_CAUSE_INTR_ENABLE);
+	SL_CTRL_LINK_CAUSE_COUNTER_INIT(ctrl_link, LINK_CAUSE_TIMEOUT);
+	SL_CTRL_LINK_CAUSE_COUNTER_INIT(ctrl_link, LINK_CAUSE_CANCELED);
+	SL_CTRL_LINK_CAUSE_COUNTER_INIT(ctrl_link, LINK_CAUSE_UNSUPPORTED_CABLE);
+	SL_CTRL_LINK_CAUSE_COUNTER_INIT(ctrl_link, LINK_CAUSE_COMMAND);
+	SL_CTRL_LINK_CAUSE_COUNTER_INIT(ctrl_link, LINK_CAUSE_DOWNSHIFT);
+	SL_CTRL_LINK_CAUSE_COUNTER_INIT(ctrl_link, LINK_CAUSE_LLR_REPLAY_MAX);
+	SL_CTRL_LINK_CAUSE_COUNTER_INIT(ctrl_link, LINK_CAUSE_UPSHIFT);
+	SL_CTRL_LINK_CAUSE_COUNTER_INIT(ctrl_link, LINK_CAUSE_AUTONEG_CONFIG);
+	SL_CTRL_LINK_CAUSE_COUNTER_INIT(ctrl_link, LINK_CAUSE_PCS_FAULT);
+	SL_CTRL_LINK_CAUSE_COUNTER_INIT(ctrl_link, LINK_CAUSE_SERDES_PLL);
+	SL_CTRL_LINK_CAUSE_COUNTER_INIT(ctrl_link, LINK_CAUSE_SERDES_CONFIG);
+	SL_CTRL_LINK_CAUSE_COUNTER_INIT(ctrl_link, LINK_CAUSE_SERDES_SIGNAL);
+	SL_CTRL_LINK_CAUSE_COUNTER_INIT(ctrl_link, LINK_CAUSE_SERDES_QUALITY);
+	SL_CTRL_LINK_CAUSE_COUNTER_INIT(ctrl_link, LINK_CAUSE_NO_MEDIA);
+	SL_CTRL_LINK_CAUSE_COUNTER_INIT(ctrl_link, LINK_CAUSE_CCW);
+	SL_CTRL_LINK_CAUSE_COUNTER_INIT(ctrl_link, LINK_CAUSE_MEDIA_HOT);
+	SL_CTRL_LINK_CAUSE_COUNTER_INIT(ctrl_link, LINK_CAUSE_MEDIA_WARM);
+	SL_CTRL_LINK_CAUSE_COUNTER_INIT(ctrl_link, LINK_CAUSE_INTR_REGISTER);
+	SL_CTRL_LINK_CAUSE_COUNTER_INIT(ctrl_link, LINK_CAUSE_MEDIA_ERROR);
+	SL_CTRL_LINK_CAUSE_COUNTER_INIT(ctrl_link, LINK_CAUSE_UP_CANCELED);
+	SL_CTRL_LINK_CAUSE_COUNTER_INIT(ctrl_link, LINK_CAUSE_UNSUPPORTED_SPEED);
+	SL_CTRL_LINK_CAUSE_COUNTER_INIT(ctrl_link, LINK_CAUSE_SS200_CABLE);
+	SL_CTRL_LINK_CAUSE_COUNTER_INIT(ctrl_link, LINK_CAUSE_TX_LOL);
+	SL_CTRL_LINK_CAUSE_COUNTER_INIT(ctrl_link, LINK_CAUSE_RX_LOL);
+	SL_CTRL_LINK_CAUSE_COUNTER_INIT(ctrl_link, LINK_CAUSE_TX_LOS);
+	SL_CTRL_LINK_CAUSE_COUNTER_INIT(ctrl_link, LINK_CAUSE_RX_LOS);
+
+	return 0;
+}
+
+int sl_ctrl_link_cause_counters_get(struct sl_ctrl_link *ctrl_link, u32 counter, int *count)
+{
+	*count = atomic_read(&ctrl_link->cause_counters[counter].count);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "get (cause counter = %u %s, count = %d)", counter,
+			ctrl_link->cause_counters[counter].name, *count);
+
+	return 0;
+}
+
+void sl_ctrl_link_cause_counters_del(struct sl_ctrl_link *ctrl_link)
+{
+	kfree(ctrl_link->cause_counters);
+}
+
+int sl_ctrl_link_an_cause_counters_init(struct sl_ctrl_link *ctrl_link)
+{
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "link an cause counters init");
+
+	ctrl_link->an_cause_counters = kzalloc(sizeof(*ctrl_link->an_cause_counters) *
+					    SL_CTRL_LINK_AN_CAUSE_COUNTERS_COUNT, GFP_KERNEL);
+	if (!ctrl_link->an_cause_counters)
+		return -ENOMEM;
+
+	SL_CTRL_LINK_AN_CAUSE_COUNTER_INIT(ctrl_link, LINK_AN_CAUSE_LP_CAPS_SERDES_LINK_UP_FAIL);
+	SL_CTRL_LINK_AN_CAUSE_COUNTER_INIT(ctrl_link, LINK_AN_CAUSE_LP_CAPS_NOT_COMPLETE);
+	SL_CTRL_LINK_AN_CAUSE_COUNTER_INIT(ctrl_link, LINK_AN_CAUSE_NOT_COMPLETE);
+	SL_CTRL_LINK_AN_CAUSE_COUNTER_INIT(ctrl_link, LINK_AN_CAUSE_TEST_CAPS_NOMATCH);
+	SL_CTRL_LINK_AN_CAUSE_COUNTER_INIT(ctrl_link, LINK_AN_CAUSE_SERDES_LINK_UP_FAIL);
+	SL_CTRL_LINK_AN_CAUSE_COUNTER_INIT(ctrl_link, LINK_AN_CAUSE_BP_STORE_STATE_BAD);
+	SL_CTRL_LINK_AN_CAUSE_COUNTER_INIT(ctrl_link, LINK_AN_CAUSE_BP_STORE_LP_ABILITY_NOT_SET);
+	SL_CTRL_LINK_AN_CAUSE_COUNTER_INIT(ctrl_link, LINK_AN_CAUSE_BP_STORE_STATE_ERROR);
+	SL_CTRL_LINK_AN_CAUSE_COUNTER_INIT(ctrl_link, LINK_AN_CAUSE_BP_STORE_BP_NOT_SET);
+	SL_CTRL_LINK_AN_CAUSE_COUNTER_INIT(ctrl_link, LINK_AN_CAUSE_BP_SEND_INTR_ENABLE_FAIL);
+	SL_CTRL_LINK_AN_CAUSE_COUNTER_INIT(ctrl_link, LINK_AN_CAUSE_NP_STORE_STATE_BAD);
+	SL_CTRL_LINK_AN_CAUSE_COUNTER_INIT(ctrl_link, LINK_AN_CAUSE_NP_STORE_BP_SET);
+	SL_CTRL_LINK_AN_CAUSE_COUNTER_INIT(ctrl_link, LINK_AN_CAUSE_NP_CHECK_STATE_BAD);
+	SL_CTRL_LINK_AN_CAUSE_COUNTER_INIT(ctrl_link, LINK_AN_CAUSE_INTR_STATE_INVALID);
+	SL_CTRL_LINK_AN_CAUSE_COUNTER_INIT(ctrl_link, LINK_AN_CAUSE_INTR_AN_RETRY_NP_SEND_FAIL);
+	SL_CTRL_LINK_AN_CAUSE_COUNTER_INIT(ctrl_link, LINK_AN_CAUSE_INTR_OUT_OF_PAGES);
+	SL_CTRL_LINK_AN_CAUSE_COUNTER_INIT(ctrl_link, LINK_AN_CAUSE_INTR_NP_SEND_FAIL);
+	SL_CTRL_LINK_AN_CAUSE_COUNTER_INIT(ctrl_link, LINK_AN_CAUSE_PAGES_DECODE_FAIL);
+	SL_CTRL_LINK_AN_CAUSE_COUNTER_INIT(ctrl_link, LINK_AN_CAUSE_PAGES_DECODE_NO_BP);
+	SL_CTRL_LINK_AN_CAUSE_COUNTER_INIT(ctrl_link, LINK_AN_CAUSE_PAGES_DECODE_OUI_INVALID);
+
+	return 0;
+}
+
+int sl_ctrl_link_an_cause_counters_get(struct sl_ctrl_link *ctrl_link, u32 counter, int *count)
+{
+	*count = atomic_read(&ctrl_link->an_cause_counters[counter].count);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "get (an cause counter = %u %s, count = %d)", counter,
+			ctrl_link->an_cause_counters[counter].name, *count);
+
+	return 0;
+}
+
+void sl_ctrl_link_an_cause_counters_del(struct sl_ctrl_link *ctrl_link)
+{
+	kfree(ctrl_link->an_cause_counters);
+}
+
+void sl_ctrl_link_cause_counter_inc(struct sl_ctrl_link *ctrl_link, u64 cause_map)
+{
+	unsigned long which;
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "link cause counter inc");
+
+	for_each_set_bit(which, (unsigned long *)&cause_map, sizeof(cause_map) * BITS_PER_BYTE) {
+		switch (BIT(which)) {
+		case SL_LINK_DOWN_CAUSE_UCW:
+			SL_CTRL_LINK_CAUSE_COUNTER_INC(ctrl_link, LINK_CAUSE_UCW);
+			break;
+		case SL_LINK_DOWN_CAUSE_LF:
+			SL_CTRL_LINK_CAUSE_COUNTER_INC(ctrl_link, LINK_CAUSE_LF);
+			break;
+		case SL_LINK_DOWN_CAUSE_RF:
+			SL_CTRL_LINK_CAUSE_COUNTER_INC(ctrl_link, LINK_CAUSE_RF);
+			break;
+		case SL_LINK_DOWN_CAUSE_DOWN:
+			SL_CTRL_LINK_CAUSE_COUNTER_INC(ctrl_link, LINK_CAUSE_DOWN);
+			break;
+		case SL_LINK_DOWN_CAUSE_UP_TRIES:
+			SL_CTRL_LINK_CAUSE_COUNTER_INC(ctrl_link, LINK_CAUSE_UP_TRIES);
+			break;
+		case SL_LINK_DOWN_CAUSE_AUTONEG_NOMATCH:
+			SL_CTRL_LINK_CAUSE_COUNTER_INC(ctrl_link, LINK_CAUSE_AUTONEG_NOMATCH);
+			break;
+		case SL_LINK_DOWN_CAUSE_AUTONEG:
+			SL_CTRL_LINK_CAUSE_COUNTER_INC(ctrl_link, LINK_CAUSE_AUTONEG);
+			break;
+		case SL_LINK_DOWN_CAUSE_CONFIG:
+			SL_CTRL_LINK_CAUSE_COUNTER_INC(ctrl_link, LINK_CAUSE_CONFIG);
+			break;
+		case SL_LINK_DOWN_CAUSE_INTR_ENABLE:
+			SL_CTRL_LINK_CAUSE_COUNTER_INC(ctrl_link, LINK_CAUSE_INTR_ENABLE);
+			break;
+		case SL_LINK_DOWN_CAUSE_TIMEOUT:
+			SL_CTRL_LINK_CAUSE_COUNTER_INC(ctrl_link, LINK_CAUSE_TIMEOUT);
+			break;
+		case SL_LINK_DOWN_CAUSE_CANCELED:
+			SL_CTRL_LINK_CAUSE_COUNTER_INC(ctrl_link, LINK_CAUSE_CANCELED);
+			break;
+		case SL_LINK_DOWN_CAUSE_UNSUPPORTED_CABLE:
+			SL_CTRL_LINK_CAUSE_COUNTER_INC(ctrl_link, LINK_CAUSE_UNSUPPORTED_CABLE);
+			break;
+		case SL_LINK_DOWN_CAUSE_COMMAND:
+			SL_CTRL_LINK_CAUSE_COUNTER_INC(ctrl_link, LINK_CAUSE_COMMAND);
+			break;
+		case SL_LINK_DOWN_CAUSE_DOWNSHIFT:
+			SL_CTRL_LINK_CAUSE_COUNTER_INC(ctrl_link, LINK_CAUSE_DOWNSHIFT);
+			break;
+		case SL_LINK_DOWN_CAUSE_LLR_REPLAY_MAX:
+			SL_CTRL_LINK_CAUSE_COUNTER_INC(ctrl_link, LINK_CAUSE_LLR_REPLAY_MAX);
+			break;
+		case SL_LINK_DOWN_CAUSE_UPSHIFT:
+			SL_CTRL_LINK_CAUSE_COUNTER_INC(ctrl_link, LINK_CAUSE_UPSHIFT);
+			break;
+		case SL_LINK_DOWN_CAUSE_AUTONEG_CONFIG:
+			SL_CTRL_LINK_CAUSE_COUNTER_INC(ctrl_link, LINK_CAUSE_AUTONEG_CONFIG);
+			break;
+		case SL_LINK_DOWN_CAUSE_PCS_FAULT:
+			SL_CTRL_LINK_CAUSE_COUNTER_INC(ctrl_link, LINK_CAUSE_PCS_FAULT);
+			break;
+		case SL_LINK_DOWN_CAUSE_SERDES_PLL:
+			SL_CTRL_LINK_CAUSE_COUNTER_INC(ctrl_link, LINK_CAUSE_SERDES_PLL);
+			break;
+		case SL_LINK_DOWN_CAUSE_SERDES_CONFIG:
+			SL_CTRL_LINK_CAUSE_COUNTER_INC(ctrl_link, LINK_CAUSE_SERDES_CONFIG);
+			break;
+		case SL_LINK_DOWN_CAUSE_SERDES_SIGNAL:
+			SL_CTRL_LINK_CAUSE_COUNTER_INC(ctrl_link, LINK_CAUSE_SERDES_SIGNAL);
+			break;
+		case SL_LINK_DOWN_CAUSE_SERDES_QUALITY:
+			SL_CTRL_LINK_CAUSE_COUNTER_INC(ctrl_link, LINK_CAUSE_SERDES_QUALITY);
+			break;
+		case SL_LINK_DOWN_CAUSE_NO_MEDIA:
+			SL_CTRL_LINK_CAUSE_COUNTER_INC(ctrl_link, LINK_CAUSE_NO_MEDIA);
+			break;
+		case SL_LINK_DOWN_CAUSE_CCW:
+			SL_CTRL_LINK_CAUSE_COUNTER_INC(ctrl_link, LINK_CAUSE_CCW);
+			break;
+		case SL_LINK_DOWN_CAUSE_MEDIA_HOT:
+			SL_CTRL_LINK_CAUSE_COUNTER_INC(ctrl_link, LINK_CAUSE_MEDIA_HOT);
+			break;
+		case SL_LINK_DOWN_CAUSE_MEDIA_WARM:
+			SL_CTRL_LINK_CAUSE_COUNTER_INC(ctrl_link, LINK_CAUSE_MEDIA_WARM);
+			break;
+		case SL_LINK_DOWN_CAUSE_INTR_REGISTER:
+			SL_CTRL_LINK_CAUSE_COUNTER_INC(ctrl_link, LINK_CAUSE_INTR_REGISTER);
+			break;
+		case SL_LINK_DOWN_CAUSE_MEDIA_ERROR:
+			SL_CTRL_LINK_CAUSE_COUNTER_INC(ctrl_link, LINK_CAUSE_MEDIA_ERROR);
+			break;
+		case SL_LINK_DOWN_CAUSE_UP_CANCELED:
+			SL_CTRL_LINK_CAUSE_COUNTER_INC(ctrl_link, LINK_CAUSE_UP_CANCELED);
+			break;
+		case SL_LINK_DOWN_CAUSE_UNSUPPORTED_SPEED:
+			SL_CTRL_LINK_CAUSE_COUNTER_INC(ctrl_link, LINK_CAUSE_UNSUPPORTED_SPEED);
+			break;
+		case SL_LINK_DOWN_CAUSE_SS200_CABLE:
+			SL_CTRL_LINK_CAUSE_COUNTER_INC(ctrl_link, LINK_CAUSE_SS200_CABLE);
+			break;
+		case SL_LINK_DOWN_CAUSE_TX_LOL:
+			SL_CTRL_LINK_CAUSE_COUNTER_INC(ctrl_link, LINK_CAUSE_TX_LOL);
+			break;
+		case SL_LINK_DOWN_CAUSE_RX_LOL:
+			SL_CTRL_LINK_CAUSE_COUNTER_INC(ctrl_link, LINK_CAUSE_RX_LOL);
+			break;
+		case SL_LINK_DOWN_CAUSE_TX_LOS:
+			SL_CTRL_LINK_CAUSE_COUNTER_INC(ctrl_link, LINK_CAUSE_TX_LOS);
+			break;
+		case SL_LINK_DOWN_CAUSE_RX_LOS:
+			SL_CTRL_LINK_CAUSE_COUNTER_INC(ctrl_link, LINK_CAUSE_RX_LOS);
+			break;
+		case SL_LINK_DOWN_RETRYABLE:
+		case SL_LINK_DOWN_ORIGIN_ASYNC:
+		case SL_LINK_DOWN_ORIGIN_LINK_UP:
+			break;
+		default:
+			sl_ctrl_log_warn_trace(ctrl_link, LOG_NAME,
+					       "cause_counter_inc unknown cause (bit = %lu)", which);
+			break;
+		}
+	}
+}
+
+void sl_ctrl_link_an_cause_counter_inc(struct sl_ctrl_link *ctrl_link, unsigned long cause_map)
+{
+	unsigned long which;
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "link an cause counter inc");
+
+	BUILD_BUG_ON(SL_CTRL_LINK_AN_CAUSE_COUNTERS_COUNT > 32);
+
+	for_each_set_bit(which, &cause_map, sizeof(cause_map) * BITS_PER_BYTE) {
+		switch (BIT(which)) {
+		case SL_CORE_HW_AN_FAIL_CAUSE_LP_CAPS_SERDES_LINK_UP_FAIL:
+			SL_CTRL_LINK_AN_CAUSE_COUNTER_INC(ctrl_link, LINK_AN_CAUSE_LP_CAPS_SERDES_LINK_UP_FAIL);
+			break;
+		case SL_CORE_HW_AN_FAIL_CAUSE_LP_CAPS_NOT_COMPLETE:
+			SL_CTRL_LINK_AN_CAUSE_COUNTER_INC(ctrl_link, LINK_AN_CAUSE_LP_CAPS_NOT_COMPLETE);
+			break;
+		case SL_CORE_HW_AN_FAIL_CAUSE_NOT_COMPLETE:
+			SL_CTRL_LINK_AN_CAUSE_COUNTER_INC(ctrl_link, LINK_AN_CAUSE_NOT_COMPLETE);
+			break;
+		case SL_CORE_HW_AN_FAIL_CAUSE_TEST_CAPS_NOMATCH:
+			SL_CTRL_LINK_AN_CAUSE_COUNTER_INC(ctrl_link, LINK_AN_CAUSE_TEST_CAPS_NOMATCH);
+			break;
+		case SL_CORE_HW_AN_FAIL_CAUSE_SERDES_LINK_UP_FAIL:
+			SL_CTRL_LINK_AN_CAUSE_COUNTER_INC(ctrl_link, LINK_AN_CAUSE_SERDES_LINK_UP_FAIL);
+			break;
+		case SL_CORE_HW_AN_FAIL_CAUSE_BP_STORE_STATE_BAD:
+			SL_CTRL_LINK_AN_CAUSE_COUNTER_INC(ctrl_link, LINK_AN_CAUSE_BP_STORE_STATE_BAD);
+			break;
+		case SL_CORE_HW_AN_FAIL_CAUSE_BP_STORE_LP_ABILITY_NOT_SET:
+			SL_CTRL_LINK_AN_CAUSE_COUNTER_INC(ctrl_link, LINK_AN_CAUSE_BP_STORE_LP_ABILITY_NOT_SET);
+			break;
+		case SL_CORE_HW_AN_FAIL_CAUSE_BP_STORE_STATE_ERROR:
+			SL_CTRL_LINK_AN_CAUSE_COUNTER_INC(ctrl_link, LINK_AN_CAUSE_BP_STORE_STATE_ERROR);
+			break;
+		case SL_CORE_HW_AN_FAIL_CAUSE_BP_STORE_BP_NOT_SET:
+			SL_CTRL_LINK_AN_CAUSE_COUNTER_INC(ctrl_link, LINK_AN_CAUSE_BP_STORE_BP_NOT_SET);
+			break;
+		case SL_CORE_HW_AN_FAIL_CAUSE_BP_SEND_INTR_ENABLE_FAIL:
+			SL_CTRL_LINK_AN_CAUSE_COUNTER_INC(ctrl_link, LINK_AN_CAUSE_BP_SEND_INTR_ENABLE_FAIL);
+			break;
+		case SL_CORE_HW_AN_FAIL_CAUSE_NP_STORE_STATE_BAD:
+			SL_CTRL_LINK_AN_CAUSE_COUNTER_INC(ctrl_link, LINK_AN_CAUSE_NP_STORE_STATE_BAD);
+			break;
+		case SL_CORE_HW_AN_FAIL_CAUSE_NP_STORE_BP_SET:
+			SL_CTRL_LINK_AN_CAUSE_COUNTER_INC(ctrl_link, LINK_AN_CAUSE_NP_STORE_BP_SET);
+			break;
+		case SL_CORE_HW_AN_FAIL_CAUSE_NP_CHECK_STATE_BAD:
+			SL_CTRL_LINK_AN_CAUSE_COUNTER_INC(ctrl_link, LINK_AN_CAUSE_NP_CHECK_STATE_BAD);
+			break;
+		case SL_CORE_HW_AN_FAIL_CAUSE_INTR_STATE_INVALID:
+			SL_CTRL_LINK_AN_CAUSE_COUNTER_INC(ctrl_link, LINK_AN_CAUSE_INTR_STATE_INVALID);
+			break;
+		case SL_CORE_HW_AN_FAIL_CAUSE_INTR_AN_RETRY_NP_SEND_FAIL:
+			SL_CTRL_LINK_AN_CAUSE_COUNTER_INC(ctrl_link, LINK_AN_CAUSE_INTR_AN_RETRY_NP_SEND_FAIL);
+			break;
+		case SL_CORE_HW_AN_FAIL_CAUSE_INTR_OUT_OF_PAGES:
+			SL_CTRL_LINK_AN_CAUSE_COUNTER_INC(ctrl_link, LINK_AN_CAUSE_INTR_OUT_OF_PAGES);
+			break;
+		case SL_CORE_HW_AN_FAIL_CAUSE_INTR_NP_SEND_FAIL:
+			SL_CTRL_LINK_AN_CAUSE_COUNTER_INC(ctrl_link, LINK_AN_CAUSE_INTR_NP_SEND_FAIL);
+			break;
+		case SL_CORE_HW_AN_FAIL_CAUSE_PAGES_DECODE_FAIL:
+			SL_CTRL_LINK_AN_CAUSE_COUNTER_INC(ctrl_link, LINK_AN_CAUSE_PAGES_DECODE_FAIL);
+			break;
+		case SL_CORE_HW_AN_FAIL_CAUSE_PAGES_DECODE_NO_BP:
+			SL_CTRL_LINK_AN_CAUSE_COUNTER_INC(ctrl_link, LINK_AN_CAUSE_PAGES_DECODE_NO_BP);
+			break;
+		case SL_CORE_HW_AN_FAIL_CAUSE_PAGES_DECODE_OUI_INVALID:
+			SL_CTRL_LINK_AN_CAUSE_COUNTER_INC(ctrl_link, LINK_AN_CAUSE_PAGES_DECODE_OUI_INVALID);
+			break;
+		default:
+			sl_ctrl_log_warn_trace(ctrl_link, LOG_NAME,
+					       "an cause_counter_inc unknown fault cause (bit = %lu)", which);
+			break;
+		}
+	}
+}
diff --git a/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_link_fec.c b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_link_fec.c
new file mode 100644
index 000000000000..2c54795281e0
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_link_fec.c
@@ -0,0 +1,202 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#include "base/sl_ctrl_log.h"
+#include "sl_ctrl_link.h"
+#include "sl_ctrl_link_fec.h"
+#include "sl_core_link.h"
+
+#define LOG_NAME SL_CTRL_LINK_FEC_LOG_NAME
+
+int sl_ctrl_link_fec_info_get(u8 ldev_num, u8 lgrp_num, u8 link_num, struct sl_fec_info *fec_info)
+{
+	struct sl_ctrl_link *ctrl_link __free(sl_ctrl_link_put) = NULL;
+	int                 x;
+
+	ctrl_link = sl_ctrl_link_get(ldev_num, lgrp_num, link_num);
+	if (!ctrl_link)
+		return -ENODEV;
+	if (!ctrl_link) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"info get NULL link (ldev_num = %u, lgrp_num = %u, link_num = %u)",
+			ldev_num, lgrp_num, link_num);
+		return -EBADRQC;
+	}
+
+	if (!sl_ctrl_link_kref_get_unless_zero(ctrl_link)) {
+		sl_ctrl_log_err(ctrl_link, LOG_NAME,
+				"fec info get kref unavailable (ctrl_link = 0x%p)", ctrl_link);
+		return -EBADRQC;
+	}
+
+	*fec_info = sl_ctrl_link_fec_data_info_get(ctrl_link);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"info get (ucw = %llu, ccw = %llu, gcw = %llu, period = %ums)",
+		fec_info->ucw, fec_info->ccw, fec_info->gcw, fec_info->period_ms);
+	for (x = 0; x < SL_CTRL_NUM_FEC_LANES; ++x)
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "info get (lane %d = 0x%llX)", x, fec_info->lanes[x]);
+
+	if (sl_ctrl_link_put(ctrl_link))
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "fec info get - link removed (link = 0x%p)", ctrl_link);
+
+	return 0;
+}
+
+int sl_ctrl_link_fec_tail_get(u8 ldev_num, u8 lgrp_num, u8 link_num, struct sl_fec_tail *fec_tail)
+{
+	struct sl_ctrl_link *ctrl_link __free(sl_ctrl_link_put) = NULL;
+	int                 x;
+
+	ctrl_link = sl_ctrl_link_get(ldev_num, lgrp_num, link_num);
+	if (!ctrl_link)
+		return -ENODEV;
+	if (!ctrl_link) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"tail get NULL link (ldev_num = %u, lgrp_num = %u, link_num = %u)",
+			ldev_num, lgrp_num, link_num);
+		return -EBADRQC;
+	}
+
+	if (!sl_ctrl_link_kref_get_unless_zero(ctrl_link)) {
+		sl_ctrl_log_err(ctrl_link, LOG_NAME,
+				"fec tail get kref unavailable (ctrl_link = 0x%p)", ctrl_link);
+		return -EBADRQC;
+	}
+
+	*fec_tail = sl_ctrl_link_fec_data_tail_get(ctrl_link);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "tail get (period = %ums))", fec_tail->period_ms);
+	for (x = 0; x < SL_CTRL_NUM_CCW_BINS; ++x)
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "tail get (bin %d = %llu)", x, fec_tail->ccw_bins[x]);
+
+	if (sl_ctrl_link_put(ctrl_link))
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "fec tail get - link removed (link = 0x%p)", ctrl_link);
+
+	return 0;
+}
+
+int sl_ctrl_link_fec_data_get(u8 ldev_num, u8 lgrp_num, u8 link_num,
+			      struct sl_core_link_fec_cw_cntrs *cw_cntrs,
+			      struct sl_core_link_fec_lane_cntrs *lane_cntrs,
+			      struct sl_core_link_fec_tail_cntrs *tail_cntrs)
+{
+	struct sl_core_link *held_link_1 __free(sl_core_link_put) = NULL;
+	held_link_1 = sl_core_link_get(ldev_num, lgrp_num, link_num);
+	if (!held_link_1)
+		return -ENODEV;
+	return sl_core_link_fec_data_get(held_link_1, cw_cntrs, lane_cntrs,
+					 tail_cntrs);
+}
+
+int sl_ctrl_link_fec_mon_state_get(struct sl_ctrl_link *ctrl_link, u32 *state)
+{
+	spin_lock(&ctrl_link->fec_mon_timer_lock);
+	*state = ctrl_link->fec_mon_state;
+	spin_unlock(&ctrl_link->fec_mon_timer_lock);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "fec monitor (state = %u, %s)", *state,
+			sl_ctrl_link_fec_mon_state_str(*state));
+
+	return 0;
+}
+
+const char *sl_ctrl_link_fec_mon_state_str(u32 state)
+{
+	switch (state) {
+	case SL_CTRL_LINK_FEC_MON_OFF:
+		return "off";
+	case SL_CTRL_LINK_FEC_MON_ON:
+		return "on";
+	default:
+		return "unknown";
+	}
+}
+
+//#define SL_CTRL_SERDES_RATE_25	25781250000
+//#define SL_CTRL_SERDES_RATE_50	53125000000
+//#define SL_CTRL_SERDES_RATE_100	106250000000
+
+/* CCW BER Calculation Multiplier (10^6). */
+#define SL_CTRL_LINK_FEC_CCW_BER_MULT 1000000
+#define SL_CTRL_LINK_FEC_CCW_BER_EXP 6
+
+/* UCW BER Calculation Multiplier (10^12). */
+#define SL_CTRL_LINK_FEC_UCW_BER_MULT 1000000000000
+#define SL_CTRL_LINK_FEC_UCW_BER_EXP 12
+
+#define MAX_CCW_COUNT (U64_MAX / (HZ * SL_CTRL_LINK_FEC_CCW_BER_MULT))
+#define MAX_UCW_COUNT (U64_MAX / (HZ * SL_CTRL_LINK_FEC_UCW_BER_MULT))
+
+int sl_ctrl_link_fec_ber_calc(struct sl_fec_info *fec_info, struct sl_ber *ucw_ber, struct sl_ber *ccw_ber)
+{
+	u64 total;
+	u64 ccw_rate;	/* Rate * 10^10 */
+	u64 ucw_rate;	/* Rate * 10^10 */
+	int mag;
+
+	sl_ctrl_log_dbg(NULL, LOG_NAME, "fec_ber_calc");
+
+	/* Total must be > 0 to calculate */
+	total = fec_info->ccw + fec_info->gcw;
+	if (total == 0) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"fec invalid (total = %llu)", total);
+		return -EINVAL;
+	}
+
+	if (fec_info->ccw > MAX_CCW_COUNT) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"fec ccw invalid (%llu > %llu)", fec_info->ccw, MAX_CCW_COUNT);
+		return -EINVAL;
+	}
+
+	if (fec_info->ucw > MAX_UCW_COUNT) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"fec ucw invalid (%llu > %llu)", fec_info->ucw, MAX_UCW_COUNT);
+		return -EINVAL;
+	}
+
+	/* B = BER
+	 * n = [U/C]CW count
+	 * g = Good CW count
+	 * T = total CW = ccw_count + g
+	 * t = time = (jiffies / HZ)
+	 *
+	 * B = (n/T) / t; B = (n * HZ) / (T * jiffies)
+	 */
+
+	/* We use RS(544/514) with 10 bit symbols which is a total of 5440 bits per CW. */
+	total = fec_info->ccw + (fec_info->gcw * 5440);
+
+	/* CCW count * CCW multiplier */
+	ccw_rate = (fec_info->ccw * HZ * SL_CTRL_LINK_FEC_CCW_BER_MULT) / (total * fec_info->period_ms);
+
+	/* Keep at least 2 significant digits */
+	mag = 0;
+	while ((ccw_rate / 100) > 9) {
+		ccw_rate /= 100;
+		mag += 2;
+	}
+
+	ccw_ber->mant = ccw_rate;
+	ccw_ber->exp = mag - SL_CTRL_LINK_FEC_CCW_BER_EXP;	/* Divide by CCW multiplier */
+
+	/* UCW count * UCW multiplier */
+	ucw_rate = (fec_info->ucw * HZ * SL_CTRL_LINK_FEC_UCW_BER_MULT) / (total * fec_info->period_ms);
+
+	/* Keep at least 2 significant digits */
+	mag = 0;
+	while ((ucw_rate / 100) > 9) {
+		ucw_rate /= 100;
+		mag += 2;
+	}
+
+	ucw_ber->mant = ucw_rate;
+	ucw_ber->exp = mag - SL_CTRL_LINK_FEC_UCW_BER_EXP;	/* Divide by UCW multiplier */
+
+	sl_ctrl_log_dbg(NULL, LOG_NAME, "fec_ber_calc (CCW = %ue%d, UCW = %ue%d)",
+			ccw_ber->mant, ccw_ber->exp, ucw_ber->mant, ucw_ber->exp);
+
+	return 0;
+}
diff --git a/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_link_fec_priv.c b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_link_fec_priv.c
new file mode 100644
index 000000000000..a1f50d1a3b3c
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_link_fec_priv.c
@@ -0,0 +1,539 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2023-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/string.h>
+#include <linux/spinlock.h>
+#include <linux/time.h>
+#include <linux/workqueue.h>
+
+#include "base/sl_ctrl_log.h"
+#include "sl_ctrl_ldev.h"
+#include "sl_ctrl_lgrp.h"
+#include "sl_ctrl_lgrp_notif.h"
+#include "sl_ctrl_link.h"
+#include "sl_ctrl_link_priv.h"
+#include "sl_ctrl_link_counters.h"
+#include "sl_ctrl_link_fec.h"
+#include "sl_ctrl_link_fec_priv.h"
+#include "sl_core_link.h"
+#include "sl_platform.h"
+
+#define SL_CTRL_LINK_UCW_LIMIT_MAX_CHANCES 2
+#define SL_CTRL_LINK_CCW_LIMIT_MAX_CHANCES 2
+#define SL_CTRL_LINK_FEC_MON_PERIOD_MS     500
+#define LOG_NAME SL_CTRL_LINK_FEC_LOG_NAME
+
+void sl_ctrl_link_fec_data_store(struct sl_ctrl_link *ctrl_link,
+				 struct sl_core_link_fec_cw_cntrs   *cw_cntrs,
+	struct sl_core_link_fec_lane_cntrs *lane_cntrs,
+	struct sl_core_link_fec_tail_cntrs *tail_cntrs)
+{
+	struct sl_ctrl_link_fec_cntrs *tmp_cntrs_ptr;
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "data_store");
+
+	spin_lock(&ctrl_link->fec_data.lock);
+
+	tmp_cntrs_ptr = ctrl_link->fec_data.prev_ptr;
+	ctrl_link->fec_data.prev_ptr = ctrl_link->fec_data.curr_ptr;
+	ctrl_link->fec_data.curr_ptr = tmp_cntrs_ptr;
+
+	ctrl_link->fec_data.curr_ptr->cw_cntrs   = *cw_cntrs;
+	ctrl_link->fec_data.curr_ptr->lane_cntrs = *lane_cntrs;
+	ctrl_link->fec_data.curr_ptr->tail_cntrs = *tail_cntrs;
+	ctrl_link->fec_data.curr_ptr->timestamp  = jiffies;
+
+	spin_unlock(&ctrl_link->fec_data.lock);
+}
+
+void sl_ctrl_link_fec_up_cache_clear(struct sl_ctrl_link *ctrl_link)
+{
+	spin_lock(&ctrl_link->fec_up_cache.lock);
+	memset(&(ctrl_link->fec_up_cache.cw_cntrs),   0, sizeof(struct sl_core_link_fec_cw_cntrs));
+	memset(&(ctrl_link->fec_up_cache.lane_cntrs), 0, sizeof(struct sl_core_link_fec_lane_cntrs));
+	memset(&(ctrl_link->fec_up_cache.tail_cntrs), 0, sizeof(struct sl_core_link_fec_tail_cntrs));
+	spin_unlock(&ctrl_link->fec_up_cache.lock);
+}
+
+void sl_ctrl_link_fec_up_cache_store(struct sl_ctrl_link *ctrl_link,
+				     struct sl_core_link_fec_cw_cntrs   *cw_cntrs,
+	struct sl_core_link_fec_lane_cntrs *lane_cntrs,
+	struct sl_core_link_fec_tail_cntrs *tail_cntrs)
+{
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "up_cache_store");
+
+	spin_lock(&ctrl_link->fec_up_cache.lock);
+	ctrl_link->fec_up_cache.cw_cntrs   = *cw_cntrs;
+	ctrl_link->fec_up_cache.lane_cntrs = *lane_cntrs;
+	ctrl_link->fec_up_cache.tail_cntrs = *tail_cntrs;
+	spin_unlock(&ctrl_link->fec_up_cache.lock);
+}
+
+void sl_ctrl_link_fec_down_cache_clear(struct sl_ctrl_link *ctrl_link)
+{
+	spin_lock(&ctrl_link->fec_down_cache.lock);
+	memset(&(ctrl_link->fec_down_cache.cw_cntrs),   0, sizeof(struct sl_core_link_fec_cw_cntrs));
+	memset(&(ctrl_link->fec_down_cache.lane_cntrs), 0, sizeof(struct sl_core_link_fec_lane_cntrs));
+	memset(&(ctrl_link->fec_down_cache.tail_cntrs), 0, sizeof(struct sl_core_link_fec_tail_cntrs));
+	spin_unlock(&ctrl_link->fec_down_cache.lock);
+}
+
+void sl_ctrl_link_fec_down_cache_store(struct sl_ctrl_link *ctrl_link,
+				       struct sl_core_link_fec_cw_cntrs   *cw_cntrs,
+	struct sl_core_link_fec_lane_cntrs *lane_cntrs,
+	struct sl_core_link_fec_tail_cntrs *tail_cntrs)
+{
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "down_cache_store");
+
+	spin_lock(&ctrl_link->fec_down_cache.lock);
+	ctrl_link->fec_down_cache.cw_cntrs   = *cw_cntrs;
+	ctrl_link->fec_down_cache.lane_cntrs = *lane_cntrs;
+	ctrl_link->fec_down_cache.tail_cntrs = *tail_cntrs;
+	spin_unlock(&ctrl_link->fec_down_cache.lock);
+}
+
+static void sl_ctrl_link_fec_mon_limits_calc(struct sl_ctrl_link *ctrl_link)
+{
+	struct sl_link_policy link_policy;
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "mon limits calc");
+
+	sl_ctrl_link_policy_get(ctrl_link, &link_policy);
+
+	spin_lock(&ctrl_link->fec_data.lock);
+
+	ctrl_link->fec_data.info.monitor.period_ms = (link_policy.fec_mon_period_ms < 0) ?
+		SL_CTRL_LINK_FEC_MON_PERIOD_MS : link_policy.fec_mon_period_ms;
+
+	if (link_policy.fec_mon_ccw_down_limit < 0)
+		ctrl_link->fec_data.info.monitor.ccw_down_limit = 0;
+	else
+		ctrl_link->fec_data.info.monitor.ccw_down_limit = link_policy.fec_mon_ccw_down_limit;
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"mon limits calc (ccw_down_limit = %d)",
+		ctrl_link->fec_data.info.monitor.ccw_down_limit);
+
+	if (link_policy.fec_mon_ccw_warn_limit < 0)
+		ctrl_link->fec_data.info.monitor.ccw_warn_limit =
+			sl_ctrl_link_fec_limit_calc(ctrl_link,
+						    SL_CTRL_LINK_FEC_CCW_MANT, SL_CTRL_LINK_FEC_CCW_EXP) >> 1;
+	else
+		ctrl_link->fec_data.info.monitor.ccw_warn_limit = link_policy.fec_mon_ccw_warn_limit;
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"mon limits calc (ccw_warn_limit = %d)",
+		ctrl_link->fec_data.info.monitor.ccw_warn_limit);
+
+	if (ctrl_link->fec_data.info.monitor.ccw_down_limit &&
+	    (ctrl_link->fec_data.info.monitor.ccw_warn_limit > ctrl_link->fec_data.info.monitor.ccw_down_limit))
+		sl_ctrl_log_warn(ctrl_link, LOG_NAME,
+				 "CCW warning limit set greater than down limit (%d > %d)",
+			ctrl_link->fec_data.info.monitor.ccw_warn_limit,
+			ctrl_link->fec_data.info.monitor.ccw_down_limit);
+
+	if (link_policy.fec_mon_ucw_down_limit < 0) {
+		ctrl_link->fec_data.info.monitor.ucw_down_limit =
+			sl_ctrl_link_fec_limit_calc(ctrl_link, SL_CTRL_LINK_FEC_UCW_MANT, SL_CTRL_LINK_FEC_UCW_EXP);
+	} else {
+		ctrl_link->fec_data.info.monitor.ucw_down_limit = link_policy.fec_mon_ucw_down_limit;
+	}
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"mon limits calc (ucw_down_limit = %d)",
+		ctrl_link->fec_data.info.monitor.ucw_down_limit);
+
+	if (link_policy.fec_mon_ucw_warn_limit < 0)
+		ctrl_link->fec_data.info.monitor.ucw_warn_limit =
+			sl_ctrl_link_fec_limit_calc(ctrl_link, SL_CTRL_LINK_FEC_UCW_MANT,
+						    SL_CTRL_LINK_FEC_UCW_EXP) >> 1;
+	else
+		ctrl_link->fec_data.info.monitor.ucw_warn_limit = link_policy.fec_mon_ucw_warn_limit;
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"mon limits calc (ucw_warn_limit = %d)",
+		ctrl_link->fec_data.info.monitor.ucw_warn_limit);
+
+	if (ctrl_link->fec_data.info.monitor.ucw_down_limit &&
+	    (ctrl_link->fec_data.info.monitor.ucw_warn_limit > ctrl_link->fec_data.info.monitor.ucw_down_limit))
+		sl_ctrl_log_warn(ctrl_link, LOG_NAME,
+				 "CCW warning limit set greater than down limit (%d > %d)",
+			ctrl_link->fec_data.info.monitor.ucw_warn_limit,
+			ctrl_link->fec_data.info.monitor.ucw_down_limit);
+
+	spin_unlock(&ctrl_link->fec_data.lock);
+}
+
+void sl_ctrl_link_fec_mon_start(struct sl_ctrl_link *ctrl_link)
+{
+	u32 period;
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "mon_start");
+
+	sl_ctrl_link_fec_mon_limits_calc(ctrl_link);
+
+	spin_lock(&ctrl_link->fec_data.lock);
+	period = ctrl_link->fec_data.info.monitor.period_ms;
+	spin_unlock(&ctrl_link->fec_data.lock);
+	if (!period) {
+		sl_ctrl_link_fec_mon_stop(ctrl_link);
+		cancel_work_sync(&ctrl_link->fec_mon_timer_work);
+		return;
+	}
+
+	spin_lock(&ctrl_link->fec_mon_timer_lock);
+	ctrl_link->fec_mon_timer_stop = false;
+	ctrl_link->fec_mon_state = SL_CTRL_LINK_FEC_MON_ON;
+	mod_timer(&ctrl_link->fec_mon_timer, jiffies + msecs_to_jiffies(period));
+	spin_unlock(&ctrl_link->fec_mon_timer_lock);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "monitor timer started (period = %ums)", period);
+}
+
+void sl_ctrl_link_fec_data_calc(struct sl_ctrl_link *ctrl_link)
+{
+	int x;
+
+	spin_lock(&ctrl_link->fec_data.lock);
+
+	ctrl_link->fec_data.info.ccw =
+		ctrl_link->fec_data.curr_ptr->cw_cntrs.ccw - ctrl_link->fec_data.prev_ptr->cw_cntrs.ccw;
+	ctrl_link->fec_data.info.ucw =
+		ctrl_link->fec_data.curr_ptr->cw_cntrs.ucw - ctrl_link->fec_data.prev_ptr->cw_cntrs.ucw;
+	ctrl_link->fec_data.info.gcw =
+		ctrl_link->fec_data.curr_ptr->cw_cntrs.gcw - ctrl_link->fec_data.prev_ptr->cw_cntrs.gcw;
+	for (x = 0; x < SL_CORE_LINK_FEC_NUM_LANES; ++x)
+		ctrl_link->fec_data.info.lanes[x] = ctrl_link->fec_data.curr_ptr->lane_cntrs.lanes[x] -
+			ctrl_link->fec_data.prev_ptr->lane_cntrs.lanes[x];
+	ctrl_link->fec_data.info.period_ms =
+		jiffies_to_msecs(ctrl_link->fec_data.curr_ptr->timestamp - ctrl_link->fec_data.prev_ptr->timestamp);
+
+	for (x = 0; x < SL_CTRL_NUM_CCW_BINS; ++x)
+		ctrl_link->fec_data.tail.ccw_bins[x] = ctrl_link->fec_data.curr_ptr->tail_cntrs.ccw_bins[x] -
+			ctrl_link->fec_data.prev_ptr->tail_cntrs.ccw_bins[x];
+	ctrl_link->fec_data.tail.period_ms = ctrl_link->fec_data.info.period_ms;
+
+	spin_unlock(&ctrl_link->fec_data.lock);
+
+	if ((ctrl_link->fec_data.info.ccw > 0) || (ctrl_link->fec_data.info.ucw > 0)) {
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+				"data_calc (ccw = %llu, ucw = %llu, gcw = %llu, period = %ums)",
+			ctrl_link->fec_data.info.ccw, ctrl_link->fec_data.info.ucw,
+			ctrl_link->fec_data.info.gcw, ctrl_link->fec_data.info.period_ms);
+		for (x = 0; x < SL_CTRL_NUM_CCW_BINS; ++x)
+			sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+					"data_calc (bin %d = %llu)", x, ctrl_link->fec_data.tail.ccw_bins[x]);
+	}
+}
+
+struct sl_fec_info sl_ctrl_link_fec_data_info_get(struct sl_ctrl_link *ctrl_link)
+{
+	struct sl_fec_info fec_info;
+
+	spin_lock(&ctrl_link->fec_data.lock);
+	fec_info = ctrl_link->fec_data.info;
+	spin_unlock(&ctrl_link->fec_data.lock);
+
+	return fec_info;
+}
+
+struct sl_fec_tail sl_ctrl_link_fec_data_tail_get(struct sl_ctrl_link *ctrl_link)
+{
+	struct sl_fec_tail fec_tail;
+
+	spin_lock(&ctrl_link->fec_data.lock);
+	fec_tail = ctrl_link->fec_data.tail;
+	spin_unlock(&ctrl_link->fec_data.lock);
+
+	return fec_tail;
+}
+
+static bool sl_ctrl_link_fec_ucw_chance_limit_check(struct sl_ctrl_link *ctrl_link, s32 limit, struct sl_fec_info *info)
+{
+	if (SL_CTRL_LINK_FEC_UCW_LIMIT_CHECK(limit, info)) {
+		SL_CTRL_LINK_COUNTER_INC(ctrl_link, LINK_DOWN_UCW_LIMIT_CROSSED);
+		ctrl_link->fec_ucw_chance = ctrl_link->fec_ucw_chance + 1;
+	} else {
+		ctrl_link->fec_ucw_chance = 0;
+	}
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "fec_ucw_chance_limit_check (limit = %d, UCW = %llu, ucw_chance = %u)",
+			limit, info->ucw, ctrl_link->fec_ucw_chance);
+
+	return ctrl_link->fec_ucw_chance > SL_CTRL_LINK_UCW_LIMIT_MAX_CHANCES;
+}
+
+static bool sl_ctrl_link_fec_ccw_chance_limit_check(struct sl_ctrl_link *ctrl_link, s32 limit, struct sl_fec_info *info)
+{
+	if (SL_CTRL_LINK_FEC_CCW_LIMIT_CHECK(limit, info)) {
+		SL_CTRL_LINK_COUNTER_INC(ctrl_link, LINK_DOWN_CCW_LIMIT_CROSSED);
+		ctrl_link->fec_ccw_chance = ctrl_link->fec_ccw_chance + 1;
+	} else {
+		ctrl_link->fec_ccw_chance = 0;
+	}
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "fec_ccw_chance_limit_check (limit = %d, CCW = %llu, ccw_chance = %u)",
+			limit, info->ccw, ctrl_link->fec_ccw_chance);
+
+	return ctrl_link->fec_ccw_chance > SL_CTRL_LINK_CCW_LIMIT_MAX_CHANCES;
+}
+
+int sl_ctrl_link_fec_data_check(struct sl_ctrl_link *ctrl_link)
+{
+	int                rtn;
+	s32                ccw_down_limit;
+	s32                ccw_warn_limit;
+	s32                ucw_down_limit;
+	s32                ucw_warn_limit;
+	struct sl_fec_info fec_info;
+	bool               is_limit_crossed;
+	time64_t           limit_crossed_time;
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "data check");
+
+	spin_lock(&ctrl_link->fec_data.lock);
+	ccw_down_limit = ctrl_link->fec_data.info.monitor.ccw_down_limit;
+	ccw_warn_limit = ctrl_link->fec_data.info.monitor.ccw_warn_limit;
+	ucw_down_limit = ctrl_link->fec_data.info.monitor.ucw_down_limit;
+	ucw_warn_limit = ctrl_link->fec_data.info.monitor.ucw_warn_limit;
+	spin_unlock(&ctrl_link->fec_data.lock);
+
+	fec_info = ctrl_link->fec_data.info;
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"data check config (ccw_down = %d, ucw_down = %d, ccw_warn = %d, ucw_warn = %d)",
+		ccw_down_limit, ucw_down_limit, ccw_warn_limit, ucw_warn_limit);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"data check info (UCW = %llu, CCW = %llu, GCW = %llu, period = %ums)",
+		fec_info.ucw, fec_info.ccw, fec_info.gcw, fec_info.period_ms);
+
+	if (sl_ctrl_link_fec_ucw_chance_limit_check(ctrl_link, ucw_down_limit, &fec_info)) {
+		sl_ctrl_log_err(ctrl_link, LOG_NAME,
+				"UCW exceeded down limit (UCW = %llu, CCW = %llu, ucw_chance = %u)",
+			fec_info.ucw, fec_info.ccw, ctrl_link->fec_ucw_chance);
+		ctrl_link->fec_ucw_chance = 0;
+		rtn = sl_ctrl_link_async_down(ctrl_link, SL_LINK_DOWN_CAUSE_UCW_MAP, false);
+		if (rtn) {
+			sl_ctrl_log_err_trace(ctrl_link, LOG_NAME,
+					      "data check UCW ctrl_link_async_down failed [%d]", rtn);
+			return rtn;
+		}
+		return -EIO;
+	}
+
+	if (sl_ctrl_link_fec_ccw_chance_limit_check(ctrl_link, ccw_down_limit, &fec_info)) {
+		sl_ctrl_log_err(ctrl_link, LOG_NAME,
+				"CCW exceeded down limit (UCW = %llu, CCW = %llu, ccw_chance = %u)",
+			fec_info.ucw, fec_info.ccw, ctrl_link->fec_ccw_chance);
+		ctrl_link->fec_ccw_chance = 0;
+		rtn = sl_ctrl_link_async_down(ctrl_link, SL_LINK_DOWN_CAUSE_CCW_MAP, false);
+		if (rtn) {
+			sl_ctrl_log_err_trace(ctrl_link, LOG_NAME,
+					      "data check CCW ctrl_link_async_down failed [%d]", rtn);
+			return rtn;
+		}
+		return -EIO;
+	}
+
+	if (SL_CTRL_LINK_FEC_UCW_LIMIT_CHECK(ucw_warn_limit, &fec_info)) {
+		rtn = sl_core_link_ucw_warn_limit_crossed_get(ctrl_link->ctrl_lgrp->ctrl_ldev->num,
+							      ctrl_link->ctrl_lgrp->num, ctrl_link->num, &is_limit_crossed, &limit_crossed_time);
+		if (rtn)
+			sl_core_log_warn_trace(ctrl_link, LOG_NAME, "ucw_warn_limit_crossed_get failed [%d]", rtn);
+
+		if (!is_limit_crossed) {
+			sl_ctrl_log_warn_trace(ctrl_link, LOG_NAME,
+					       "UCW exceeded warn limit (UCW = %llu, CCW = %llu)",
+					       fec_info.ucw, fec_info.ccw);
+			rtn = sl_ctrl_lgrp_notif_enqueue(ctrl_link->ctrl_lgrp, ctrl_link->num,
+							 SL_LGRP_NOTIF_LINK_UCW_WARN, NULL, 0);
+			if (rtn)
+				sl_ctrl_log_warn_trace(ctrl_link, LOG_NAME,
+						       "data check ctrl_lgrp_notif_enqueue failed [%d]", rtn);
+		}
+		sl_core_link_ucw_warn_limit_crossed_set(ctrl_link->ctrl_lgrp->ctrl_ldev->num,
+							ctrl_link->ctrl_lgrp->num, ctrl_link->num, true);
+		SL_CTRL_LINK_COUNTER_INC(ctrl_link, LINK_UCW_WARN_CROSSED);
+	}
+
+	if (SL_CTRL_LINK_FEC_CCW_LIMIT_CHECK(ccw_warn_limit, &fec_info)) {
+		rtn = sl_core_link_ccw_warn_limit_crossed_get(ctrl_link->ctrl_lgrp->ctrl_ldev->num,
+							      ctrl_link->ctrl_lgrp->num, ctrl_link->num, &is_limit_crossed, &limit_crossed_time);
+		if (rtn)
+			sl_ctrl_log_warn_trace(ctrl_link, LOG_NAME, "ccw_warn_limit_crossed_get failed [%d]", rtn);
+
+		if (!is_limit_crossed) {
+			sl_ctrl_log_warn_trace(ctrl_link, LOG_NAME,
+					       "CCW exceeded warn limit (UCW = %llu, CCW = %llu)",
+					       fec_info.ucw, fec_info.ccw);
+			rtn = sl_ctrl_lgrp_notif_enqueue(ctrl_link->ctrl_lgrp, ctrl_link->num,
+							 SL_LGRP_NOTIF_LINK_CCW_WARN, NULL, 0);
+			if (rtn)
+				sl_ctrl_log_warn_trace(ctrl_link, LOG_NAME,
+						       "data check ctrl_lgrp_notif_enqueue failed [%d]", rtn);
+		}
+		sl_core_link_ccw_warn_limit_crossed_set(ctrl_link->ctrl_lgrp->ctrl_ldev->num,
+							ctrl_link->ctrl_lgrp->num, ctrl_link->num, true);
+		SL_CTRL_LINK_COUNTER_INC(ctrl_link, LINK_CCW_WARN_CROSSED);
+	}
+
+	return 0;
+}
+
+void sl_ctrl_link_fec_mon_timer_work(struct work_struct *work)
+{
+	struct sl_core_link *held_link_1 __free(sl_core_link_put) = NULL;
+	int                                  rtn;
+	struct sl_ctrl_link                 *ctrl_link;
+	u32                                  period;
+	bool                                 stop;
+	struct sl_core_link_fec_cw_cntrs     cw_cntrs;
+	struct sl_core_link_fec_lane_cntrs   lane_cntrs;
+	struct sl_core_link_fec_tail_cntrs   tail_cntrs;
+
+	ctrl_link = container_of(work, struct sl_ctrl_link, fec_mon_timer_work);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "monitor timer work");
+
+	spin_lock(&ctrl_link->fec_data.lock);
+	period = ctrl_link->fec_data.info.monitor.period_ms;
+	spin_unlock(&ctrl_link->fec_data.lock);
+	if (!period) {
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "monitor period zero");
+		return;
+	}
+
+	held_link_1 = sl_core_link_get(ctrl_link->ctrl_lgrp->ctrl_ldev->num,
+				       ctrl_link->ctrl_lgrp->num, ctrl_link->num);
+	if (!held_link_1)
+		return;
+	if (sl_core_link_is_pml_recovery_running(held_link_1)) {
+		sl_ctrl_log_warn_trace(ctrl_link, LOG_NAME, "fec monitor skipped due to pml recovery running");
+		goto start_mon;
+	}
+
+	spin_lock(&ctrl_link->fec_mon_timer_lock);
+	stop = ctrl_link->fec_mon_timer_stop;
+	spin_unlock(&ctrl_link->fec_mon_timer_lock);
+	if (stop) {
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "monitor stopped");
+		return;
+	}
+
+	rtn = sl_ctrl_link_fec_data_get(ctrl_link->ctrl_lgrp->ctrl_ldev->num,
+					ctrl_link->ctrl_lgrp->num, ctrl_link->num, &cw_cntrs, &lane_cntrs,
+					&tail_cntrs);
+	if (rtn) {
+		sl_ctrl_log_err_trace(ctrl_link, LOG_NAME,
+				      "core_link_fec_tail_cntrs_get failed [%d]", rtn);
+		goto start_mon;
+	}
+
+	sl_ctrl_link_fec_data_store(ctrl_link, &cw_cntrs, &lane_cntrs, &tail_cntrs);
+
+	sl_ctrl_link_fec_data_calc(ctrl_link);
+
+	rtn = sl_ctrl_link_fec_data_check(ctrl_link);
+	if (rtn) {
+		sl_ctrl_log_err_trace(ctrl_link, LOG_NAME, "check failed [%d]", rtn);
+		return;
+	}
+
+	spin_lock(&ctrl_link->fec_data.lock);
+	period = ctrl_link->fec_data.info.monitor.period_ms;
+	spin_unlock(&ctrl_link->fec_data.lock);
+	if (!period) {
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "monitor period zero");
+		return;
+	}
+
+	spin_lock(&ctrl_link->fec_mon_timer_lock);
+	stop = ctrl_link->fec_mon_timer_stop;
+	spin_unlock(&ctrl_link->fec_mon_timer_lock);
+	if (stop) {
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "monitor stopped");
+		return;
+	}
+
+start_mon:
+	mod_timer(&ctrl_link->fec_mon_timer, jiffies + msecs_to_jiffies(period));
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "monitor started");
+}
+
+void sl_ctrl_link_fec_mon_timer(struct timer_list *timer)
+{
+	struct sl_ctrl_link *ctrl_link;
+
+	ctrl_link = timer_container_of(ctrl_link, timer, fec_mon_timer);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "monitor timer");
+
+	queue_work(ctrl_link->ctrl_lgrp->ctrl_ldev->workq, &ctrl_link->fec_mon_timer_work);
+}
+
+void sl_ctrl_link_fec_mon_stop(struct sl_ctrl_link *ctrl_link)
+{
+	bool stop;
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "monitor stop");
+
+	spin_lock(&ctrl_link->fec_mon_timer_lock);
+	stop = ctrl_link->fec_mon_timer_stop;
+	ctrl_link->fec_mon_timer_stop = true;
+	ctrl_link->fec_mon_state = SL_CTRL_LINK_FEC_MON_OFF;
+	spin_unlock(&ctrl_link->fec_mon_timer_lock);
+
+	if (stop) {
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "monitor already stopped");
+		return;
+	}
+
+	timer_delete_sync(&ctrl_link->fec_mon_timer);
+}
+
+#define SL_CTRL_LINK_FEC_LIMIT_25   25781250000ULL
+#define SL_CTRL_LINK_FEC_LIMIT_50   53125000000ULL
+#define SL_CTRL_LINK_FEC_LIMIT_100 106250000000ULL
+u32 sl_ctrl_link_fec_limit_calc(struct sl_ctrl_link *ctrl_link, u32 mant, int exp)
+{
+	u64                 limit;
+	int                 x;
+	struct sl_link_caps link_caps;
+
+	sl_core_link_caps_get(ctrl_link->ctrl_lgrp->ctrl_ldev->num,
+			      ctrl_link->ctrl_lgrp->num, ctrl_link->num, &link_caps);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"fec limit calc (tech_map = 0x%X, mant = %u, exp = %d)",
+		link_caps.tech_map, mant, exp);
+
+	if (link_caps.tech_map & SL_LGRP_CONFIG_TECH_CK_400G)
+		limit = SL_CTRL_LINK_FEC_LIMIT_100 << 2;
+	else if (link_caps.tech_map & SL_LGRP_CONFIG_TECH_CK_200G)
+		limit = SL_CTRL_LINK_FEC_LIMIT_100 << 1;
+	else if (link_caps.tech_map & SL_LGRP_CONFIG_TECH_BS_200G)
+		limit = SL_CTRL_LINK_FEC_LIMIT_50 << 2;
+	else if (link_caps.tech_map & SL_LGRP_CONFIG_TECH_CK_100G)
+		limit = SL_CTRL_LINK_FEC_LIMIT_100;
+	else if (link_caps.tech_map & SL_LGRP_CONFIG_TECH_BJ_100G)
+		limit = SL_CTRL_LINK_FEC_LIMIT_25 << 2;
+	else if (link_caps.tech_map & SL_LGRP_CONFIG_TECH_CD_100G)
+		limit = SL_CTRL_LINK_FEC_LIMIT_50 << 1;
+	else if (link_caps.tech_map & SL_LGRP_CONFIG_TECH_CD_50G)
+		limit = SL_CTRL_LINK_FEC_LIMIT_50;
+	else
+		limit = SL_CTRL_LINK_FEC_LIMIT_100;
+
+	limit *= mant;
+	for (x = exp; x < 0; ++x)
+		limit /= 10;
+
+	if (limit > INT_MAX)
+		return INT_MAX;
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"fec limit calc (limit = %llu)", limit);
+
+	return limit;
+}
diff --git a/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_link_priv.c b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_link_priv.c
new file mode 100644
index 000000000000..252673b57a0b
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_link_priv.c
@@ -0,0 +1,865 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2021-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/spinlock.h>
+
+#include <linux/hpe/sl/sl_link.h>
+
+#include "base/sl_ctrl_log.h"
+#include "sl_ctrl_ldev.h"
+#include "sl_ctrl_lgrp.h"
+#include "sl_ctrl_lgrp_notif.h"
+#include "sl_ctrl_link.h"
+#include "sl_ctrl_link_priv.h"
+#include "sl_ctrl_link_counters.h"
+#include "sl_core_link.h"
+#include "sl_core_link_an.h"
+#include "sl_core_str.h"
+
+#define LOG_NAME SL_CTRL_LINK_LOG_NAME
+
+#define SL_LINK_DOWN_CAUSE_FATAL_MASK (                \
+		SL_LINK_DOWN_CAUSE_AUTONEG_NOMATCH   | \
+		SL_LINK_DOWN_CAUSE_CONFIG            | \
+		SL_LINK_DOWN_CAUSE_DOWNSHIFT         | \
+		SL_LINK_DOWN_CAUSE_INTR_ENABLE       | \
+		SL_LINK_DOWN_CAUSE_UNSUPPORTED_CABLE | \
+		SL_LINK_DOWN_CAUSE_SS200_CABLE       | \
+		SL_LINK_DOWN_CAUSE_UCW               | \
+		SL_LINK_DOWN_CAUSE_MEDIA_HOT         | \
+		SL_LINK_DOWN_CAUSE_MEDIA_WARM        | \
+		SL_LINK_DOWN_CAUSE_NO_MEDIA          | \
+		SL_LINK_DOWN_CAUSE_UPSHIFT)
+
+void sl_ctrl_link_is_canceled_set(struct sl_ctrl_link *ctrl_link, bool canceled)
+{
+	spin_lock(&ctrl_link->data_lock);
+	ctrl_link->is_canceled = canceled;
+	spin_unlock(&ctrl_link->data_lock);
+}
+
+bool sl_ctrl_link_is_canceled(struct sl_ctrl_link *ctrl_link)
+{
+	bool is_canceled;
+
+	spin_lock(&ctrl_link->data_lock);
+	is_canceled = ctrl_link->is_canceled;
+	spin_unlock(&ctrl_link->data_lock);
+
+	return is_canceled;
+}
+
+static void sl_ctrl_link_last_up_fail_cause_map_clr(struct sl_ctrl_link *ctrl_link)
+{
+	spin_lock(&ctrl_link->data_lock);
+	ctrl_link->last_up_fail_cause_map = 0;
+	ctrl_link->last_up_fail_time      = 0;
+	spin_unlock(&ctrl_link->data_lock);
+}
+
+static void sl_ctrl_link_last_up_fail_cause_map_set(struct sl_ctrl_link *ctrl_link, u64 last_up_fail_cause_map)
+{
+	spin_lock(&ctrl_link->data_lock);
+	ctrl_link->last_up_fail_cause_map |= last_up_fail_cause_map;
+	ctrl_link->last_up_fail_time       = ktime_get_real_seconds();
+	spin_unlock(&ctrl_link->data_lock);
+}
+
+static bool sl_ctrl_link_is_last_up_fail_cause_set(struct sl_ctrl_link *ctrl_link, u64 last_up_fail_cause)
+{
+	bool is_last_up_fail_cause_set;
+
+	spin_lock(&ctrl_link->data_lock);
+	is_last_up_fail_cause_set = ctrl_link->last_up_fail_cause_map & last_up_fail_cause;
+	spin_unlock(&ctrl_link->data_lock);
+
+	return is_last_up_fail_cause_set;
+}
+
+static int sl_ctrl_link_up_notif_send(struct sl_ctrl_lgrp *ctrl_lgrp, struct sl_ctrl_link *ctrl_link,
+				      u64 info_map, u32 speed, u32 fec_mode, u32 fec_type)
+{
+	union sl_lgrp_notif_info info;
+
+	info.link_up.mode     = speed;
+	info.link_up.fec_mode = fec_mode;
+	info.link_up.fec_type = fec_type;
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "up notif send (speed = %u %s, fec mode = %u %s, fec type = %u)",
+			speed, sl_lgrp_config_tech_str(speed), fec_mode, sl_lgrp_fec_mode_str(fec_mode), fec_type);
+
+	return sl_ctrl_lgrp_notif_enqueue(ctrl_lgrp, ctrl_link->num, SL_LGRP_NOTIF_LINK_UP,
+		&info, info_map);
+}
+
+static int sl_ctrl_link_up_fail_notif_send(struct sl_ctrl_lgrp *ctrl_lgrp, struct sl_ctrl_link *ctrl_link,
+					   u64 cause_map, u64 info_map)
+{
+	union sl_lgrp_notif_info info;
+
+	info.cause_map = cause_map;
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "up fail notif send (cause_map = 0x%llX)", cause_map);
+
+	return sl_ctrl_lgrp_notif_enqueue(ctrl_lgrp, ctrl_link->num, SL_LGRP_NOTIF_LINK_UP_FAIL,
+		&info, info_map);
+}
+
+static int sl_ctrl_async_link_down_notif_send(struct sl_ctrl_link *ctrl_link, u64 cause_map, u64 info_map)
+{
+	union sl_lgrp_notif_info info;
+	char                     cause_str[SL_LINK_DOWN_CAUSE_STR_SIZE];
+
+	info.cause_map = cause_map;
+
+	sl_link_down_cause_map_with_info_str(cause_map, cause_str, sizeof(cause_str));
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"async_link_down_notif_send (core_cause_map = 0x%llX %s)", cause_map, cause_str);
+
+	return sl_ctrl_lgrp_notif_enqueue(ctrl_link->ctrl_lgrp, ctrl_link->num,
+		SL_LGRP_NOTIF_LINK_ASYNC_DOWN, &info, info_map);
+}
+
+static int sl_ctrl_link_down_notif_send(struct sl_ctrl_link *ctrl_link, u64 cause_map, u64 info_map)
+{
+	union sl_lgrp_notif_info info;
+	char                     cause_str[SL_LINK_DOWN_CAUSE_STR_SIZE];
+
+	info.cause_map = cause_map;
+
+	sl_link_down_cause_map_with_info_str(cause_map, cause_str, sizeof(cause_str));
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"link_down_notif_send (core_cause_map = 0x%llX %s)", cause_map, cause_str);
+
+	return sl_ctrl_lgrp_notif_enqueue(ctrl_link->ctrl_lgrp, ctrl_link->num,
+		SL_LGRP_NOTIF_LINK_DOWN, &info, info_map);
+}
+
+static int sl_ctrl_link_down_req_notif_send(struct sl_ctrl_link *ctrl_link, u64 cause_map, u64 info_map)
+{
+	union sl_lgrp_notif_info info;
+	char                     cause_str[SL_LINK_DOWN_CAUSE_STR_SIZE];
+
+	info.cause_map = cause_map;
+
+	sl_link_down_cause_map_with_info_str(cause_map, cause_str, sizeof(cause_str));
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"link_down_req_notif_send (core_cause_map = 0x%llX %s)", cause_map, cause_str);
+
+	return sl_ctrl_lgrp_notif_enqueue(ctrl_link->ctrl_lgrp, ctrl_link->num,
+					  SL_LGRP_NOTIF_LINK_DOWN_REQ, &info, info_map);
+}
+
+void sl_ctrl_link_up_clock_start(struct sl_ctrl_link *ctrl_link)
+{
+	spin_lock(&ctrl_link->up_clock.lock);
+	ctrl_link->up_clock.start         = ktime_get();
+	ctrl_link->up_clock.elapsed       = ktime_set(0, 0);
+	ctrl_link->up_clock.attempt_count = 0;
+	spin_unlock(&ctrl_link->up_clock.lock);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"clock start (time = %lld)", ctrl_link->up_clock.start);
+}
+
+static void sl_ctrl_link_up_clock_stop(struct sl_ctrl_link *ctrl_link)
+{
+	spin_lock(&ctrl_link->up_clock.lock);
+	ctrl_link->up_clock.elapsed = ktime_sub(ktime_get(), ctrl_link->up_clock.start);
+	ctrl_link->up_clock.start   = ktime_set(0, 0);
+	ctrl_link->up_clock.up      = ktime_get();
+	spin_unlock(&ctrl_link->up_clock.lock);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"clock stop (time = %lld)", ctrl_link->up_clock.elapsed);
+}
+
+void sl_ctrl_link_up_clock_reset(struct sl_ctrl_link *ctrl_link)
+{
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "clock reset");
+
+	spin_lock(&ctrl_link->up_clock.lock);
+	ctrl_link->up_clock.elapsed         = ktime_set(0, 0);
+	ctrl_link->up_clock.start           = ktime_set(0, 0);
+	ctrl_link->up_clock.attempt_count   = 0;
+	ctrl_link->up_clock.attempt_elapsed = ktime_set(0, 0);
+	ctrl_link->up_clock.attempt_start   = ktime_set(0, 0);
+	ctrl_link->up_clock.up              = ktime_set(0, 0);
+	spin_unlock(&ctrl_link->up_clock.lock);
+}
+
+void sl_ctrl_link_up_clock_attempt_start(struct sl_ctrl_link *ctrl_link)
+{
+	spin_lock(&ctrl_link->up_clock.lock);
+	ctrl_link->up_clock.attempt_start   = ktime_get();
+	ctrl_link->up_clock.attempt_elapsed = ktime_set(0, 0);
+	ctrl_link->up_clock.attempt_count++;
+	spin_unlock(&ctrl_link->up_clock.lock);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"clock attempt start (time = %lld)", ctrl_link->up_clock.attempt_start);
+}
+
+static void sl_ctrl_link_up_clock_attempt_stop(struct sl_ctrl_link *ctrl_link)
+{
+	spin_lock(&ctrl_link->up_clock.lock);
+	ctrl_link->up_clock.attempt_elapsed = ktime_sub(ktime_get(), ctrl_link->up_clock.attempt_start);
+	ctrl_link->up_clock.attempt_start   = ktime_set(0, 0);
+	spin_unlock(&ctrl_link->up_clock.lock);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"clock attempt stop (time = %lld)", ctrl_link->up_clock.attempt_elapsed);
+}
+
+static void sl_ctrl_link_state_stopping_set(struct sl_ctrl_link *ctrl_link)
+{
+	u32           link_state;
+
+	spin_lock(&ctrl_link->data_lock);
+	link_state = ctrl_link->state;
+	switch (link_state) {
+	case SL_LINK_STATE_STOPPING:
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "stopping set - already stopping");
+		spin_unlock(&ctrl_link->data_lock);
+		return;
+	case SL_LINK_STATE_STARTING:
+	case SL_LINK_STATE_UP:
+	case SL_LINK_STATE_UP_DOWN_REQ:
+		ctrl_link->state = SL_LINK_STATE_STOPPING;
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "stopping set - stopping");
+		spin_unlock(&ctrl_link->data_lock);
+		return;
+	default:
+		sl_ctrl_log_err(ctrl_link, LOG_NAME, "stopping set - invalid state (link_state = %u %s)",
+				link_state, sl_link_state_str(link_state));
+		spin_unlock(&ctrl_link->data_lock);
+		return;
+	}
+}
+
+int sl_ctrl_link_up_callback(void *tag, struct sl_core_link_up_info *up_info)
+{
+	struct sl_ctrl_link         *ctrl_link;
+	char                         core_imap_str[SL_LINK_INFO_STRLEN];
+	int                          max_up_tries;
+	u32                          up_count;
+	int                          rtn;
+	s64                          attempt_time;
+	s64                          total_time;
+	s64                          up_time;
+	union sl_lgrp_notif_info     info;
+	struct sl_core_link_up_info  core_link_up_info;
+	u64			     up_fail_cause_map;
+
+	ctrl_link = tag;
+	core_link_up_info = *up_info;
+
+	sl_core_info_map_str(core_link_up_info.info_map, core_imap_str, sizeof(core_imap_str));
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"up callback (core_state = %u %s, core_cause_map = 0x%llX, info_map = %s (0x%llx))",
+		core_link_up_info.state, sl_core_link_state_str(core_link_up_info.state),
+		core_link_up_info.cause_map, core_imap_str, core_link_up_info.info_map);
+
+	sl_ctrl_link_last_up_fail_cause_map_clr(ctrl_link);
+	sl_ctrl_link_last_up_fail_cause_map_set(ctrl_link, core_link_up_info.cause_map);
+
+	sl_ctrl_link_up_clock_attempt_stop(ctrl_link);
+
+	switch (core_link_up_info.state) {
+	case SL_CORE_LINK_STATE_UP:
+		SL_CTRL_LINK_COUNTER_INC(ctrl_link, LINK_UP);
+		sl_ctrl_link_up_clock_stop(ctrl_link);
+
+		rtn = sl_ctrl_link_up_clocks_get(ctrl_link->ctrl_lgrp->ctrl_ldev->num, ctrl_link->ctrl_lgrp->num,
+						 ctrl_link->num, &attempt_time, &total_time, &up_time);
+		if (rtn)
+			sl_ctrl_log_warn_trace(ctrl_link, LOG_NAME, "link_up_clocks_get failed [%d]", rtn);
+
+		rtn = sl_ctrl_link_up_count_get(ctrl_link->ctrl_lgrp->ctrl_ldev->num, ctrl_link->ctrl_lgrp->num,
+						ctrl_link->num, &up_count);
+		if (rtn)
+			sl_ctrl_log_warn_trace(ctrl_link, LOG_NAME, "link_up_count_get failed [%d]", rtn);
+
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+				"up callback (count = %d, attempt_time = %lldms, total_time = %lldms)",
+			up_count, attempt_time, total_time);
+
+		sl_ctrl_link_fec_mon_start(ctrl_link);
+
+		sl_ctrl_link_state_set(ctrl_link, SL_LINK_STATE_UP);
+
+		rtn = sl_ctrl_link_up_notif_send(ctrl_link->ctrl_lgrp, ctrl_link, core_link_up_info.info_map,
+						 core_link_up_info.speed, core_link_up_info.fec_mode, core_link_up_info.fec_type);
+		if (rtn)
+			sl_ctrl_log_warn_trace(ctrl_link, LOG_NAME,
+					       "up callback ctrl_link_up_notif_send failed [%d]", rtn);
+		return 0;
+
+	case SL_CORE_LINK_STATE_DOWN:
+		SL_CTRL_LINK_COUNTER_INC(ctrl_link, LINK_UP_FAIL);
+
+		spin_lock(&ctrl_link->config_lock);
+		max_up_tries = ctrl_link->config.link_up_tries_max;
+		spin_unlock(&ctrl_link->config_lock);
+
+		/* canceled */
+		if (sl_ctrl_link_is_canceled(ctrl_link)) {
+			sl_ctrl_link_up_clock_reset(ctrl_link);
+
+			sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "up retry canceled");
+
+			sl_ctrl_link_state_stopping_set(ctrl_link);
+
+			flush_work(&ctrl_link->ctrl_lgrp->notif_work);
+			sl_ctrl_link_state_set(ctrl_link, SL_LINK_STATE_DOWN);
+			complete_all(&ctrl_link->down_complete);
+
+			rtn = sl_ctrl_link_last_up_fail_cause_map_get(ctrl_link, &up_fail_cause_map);
+			if (rtn)
+				sl_ctrl_log_warn_trace(ctrl_link, LOG_NAME, "last_up_fail_cause_map_get failed [%d]", rtn);
+
+			rtn = sl_ctrl_link_up_fail_notif_send(ctrl_link->ctrl_lgrp, ctrl_link,
+							      up_fail_cause_map, core_link_up_info.info_map);
+			if (rtn)
+				sl_ctrl_log_warn_trace(ctrl_link, LOG_NAME,
+						       "up callback work ctrl_link_up_fail_notif_send failed [%d]", rtn);
+
+			return 0;
+		}
+
+		/* check up tries */
+		rtn = sl_ctrl_link_up_count_get(ctrl_link->ctrl_lgrp->ctrl_ldev->num,
+						ctrl_link->ctrl_lgrp->num, ctrl_link->num, &up_count);
+		if (rtn)
+			sl_ctrl_log_warn_trace(ctrl_link, LOG_NAME, "link_up_count_get failed [%d]", rtn);
+
+		if ((up_count >= max_up_tries) && (max_up_tries != SL_LINK_INFINITE_UP_TRIES)) {
+			sl_ctrl_link_up_clock_reset(ctrl_link);
+
+			sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "up callback work out of up tries");
+
+			sl_ctrl_link_state_stopping_set(ctrl_link);
+
+			sl_ctrl_link_last_up_fail_cause_map_set(ctrl_link, SL_LINK_DOWN_CAUSE_UP_TRIES_MAP);
+
+			flush_work(&ctrl_link->ctrl_lgrp->notif_work);
+			sl_ctrl_link_state_set(ctrl_link, SL_LINK_STATE_DOWN);
+
+			complete_all(&ctrl_link->down_complete);
+
+			rtn = sl_ctrl_link_last_up_fail_cause_map_get(ctrl_link, &up_fail_cause_map);
+			if (rtn)
+				sl_ctrl_log_warn_trace(ctrl_link, LOG_NAME, "last_up_fail_cause_map_get failed [%d]", rtn);
+			rtn = sl_ctrl_link_up_fail_notif_send(ctrl_link->ctrl_lgrp, ctrl_link,
+							      up_fail_cause_map, core_link_up_info.info_map);
+			if (rtn)
+				sl_ctrl_log_warn_trace(ctrl_link, LOG_NAME,
+						       "up callback work ctrl_link_up_fail_notif_send failed [%d]", rtn);
+			return 0;
+		}
+
+		/* check fatal down causes */
+		if (sl_ctrl_link_is_last_up_fail_cause_set(ctrl_link, SL_LINK_DOWN_CAUSE_FATAL_MASK)) {
+			sl_ctrl_link_up_clock_reset(ctrl_link);
+
+			sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "up callback work fatal down cause");
+
+			sl_ctrl_link_state_stopping_set(ctrl_link);
+
+			flush_work(&ctrl_link->ctrl_lgrp->notif_work);
+
+			sl_ctrl_link_state_set(ctrl_link, SL_LINK_STATE_DOWN);
+			complete_all(&ctrl_link->down_complete);
+
+			rtn = sl_ctrl_link_last_up_fail_cause_map_get(ctrl_link, &up_fail_cause_map);
+			if (rtn)
+				sl_ctrl_log_warn_trace(ctrl_link, LOG_NAME, "last_up_fail_cause_map_get failed [%d]", rtn);
+			rtn = sl_ctrl_link_up_fail_notif_send(ctrl_link->ctrl_lgrp, ctrl_link,
+							      up_fail_cause_map, core_link_up_info.info_map);
+			if (rtn)
+				sl_ctrl_log_warn_trace(ctrl_link, LOG_NAME,
+						       "up callback work ctrl_link_up_fail_notif_send failed [%d]", rtn);
+
+			return 0;
+		}
+
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "link up retry (ctrl_link = 0x%p)", ctrl_link);
+
+		SL_CTRL_LINK_COUNTER_INC(ctrl_link, LINK_UP_RETRY);
+
+		sl_ctrl_link_up_clock_attempt_start(ctrl_link);
+
+		rtn = sl_core_link_up(ctrl_link->ctrl_lgrp->ctrl_ldev->num, ctrl_link->ctrl_lgrp->num,
+				      ctrl_link->num, sl_ctrl_link_up_callback, ctrl_link);
+		if (rtn) {
+			sl_ctrl_link_up_clock_reset(ctrl_link);
+
+			sl_ctrl_link_state_stopping_set(ctrl_link);
+
+			sl_ctrl_log_err_trace(ctrl_link, LOG_NAME,
+					      "up callback work core_link_up failed [%d]", rtn);
+
+			flush_work(&ctrl_link->ctrl_lgrp->notif_work);
+			sl_ctrl_link_state_set(ctrl_link, SL_LINK_STATE_DOWN);
+
+			complete_all(&ctrl_link->down_complete);
+
+			info.error = rtn;
+			rtn = sl_ctrl_lgrp_notif_enqueue(ctrl_link->ctrl_lgrp, ctrl_link->num,
+							 SL_LGRP_NOTIF_LINK_ERROR, &info, core_link_up_info.info_map);
+			if (rtn)
+				sl_ctrl_log_warn_trace(ctrl_link, LOG_NAME,
+						       "up callback work ctrl_lgrp_notif_enqueue failed [%d]", rtn);
+
+			return info.error;
+		}
+		return 0;
+
+	default:
+		sl_ctrl_link_up_clock_reset(ctrl_link);
+		sl_ctrl_link_state_stopping_set(ctrl_link);
+
+		sl_ctrl_log_err(ctrl_link, LOG_NAME,
+				"up callback work invalid (core_state = %u, core_imap = %s)",
+			core_link_up_info.state, core_imap_str);
+
+		flush_work(&ctrl_link->ctrl_lgrp->notif_work);
+		sl_ctrl_link_state_set(ctrl_link, SL_LINK_STATE_DOWN);
+
+		complete_all(&ctrl_link->down_complete);
+
+		info.error = -EBADRQC;
+		rtn = sl_ctrl_lgrp_notif_enqueue(ctrl_link->ctrl_lgrp, ctrl_link->num,
+						 SL_LGRP_NOTIF_LINK_ERROR, &info, core_link_up_info.info_map);
+		if (rtn)
+			sl_ctrl_log_warn_trace(ctrl_link, LOG_NAME,
+					       "up callback work ctrl_lgrp_notif_enqueue failed [%d]", rtn);
+
+		return info.error;
+	}
+}
+
+int sl_ctrl_link_fault_start_callback(u8 ldev_num, u8 lgrp_num, u8 link_num)
+{
+	struct sl_ctrl_link *ctrl_link __free(sl_ctrl_link_put) = NULL;
+
+	ctrl_link = sl_ctrl_link_get(ldev_num, lgrp_num, link_num);
+	if (!ctrl_link)
+		return -ENODEV;
+	if (!ctrl_link) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"NULL link (ldev_num = %u, lgrp_num = %u, link_num = %u)",
+			ldev_num, lgrp_num, link_num);
+		return -EBADRQC;
+	}
+
+	if (!sl_ctrl_link_kref_get_unless_zero(ctrl_link)) {
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+				"fault start callback kref unavailable (ctrl_link = 0x%p)", ctrl_link);
+		return -EBADRQC;
+	}
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "fault start callback");
+
+	sl_ctrl_link_state_set(ctrl_link, SL_LINK_STATE_STOPPING);
+
+	sl_ctrl_link_fec_mon_stop(ctrl_link);
+	cancel_work_sync(&ctrl_link->fec_mon_timer_work);
+
+	if (sl_ctrl_link_put(ctrl_link))
+		sl_ctrl_log_dbg(NULL, LOG_NAME,
+				"fault start callback - link removed (link = 0x%p)", ctrl_link);
+
+	return 0;
+}
+
+int sl_ctrl_link_fault_callback(void *tag, u32 core_state, u64 core_cause_map, u64 core_info_map)
+{
+	struct sl_ctrl_link      *ctrl_link;
+	char                      core_imap_str[SL_LINK_INFO_STRLEN];
+	int                       rtn;
+	union sl_lgrp_notif_info  info;
+
+	ctrl_link = tag;
+
+	SL_CTRL_LINK_COUNTER_INC(ctrl_link, LINK_FAULT_ASYNC);
+
+	sl_core_info_map_str(core_info_map, core_imap_str, sizeof(core_imap_str));
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"fault callback (core_state = %u %s, core_cause_map = 0x%llX, core_info_map = %s (0x%llx))",
+			core_state, sl_core_link_state_str(core_state), core_cause_map, core_imap_str, core_info_map);
+
+	sl_ctrl_link_up_clock_reset(ctrl_link);
+
+	switch (core_state) {
+	case SL_CORE_LINK_STATE_DOWN:
+		SL_CTRL_LINK_COUNTER_INC(ctrl_link, LINK_DOWN);
+
+		sl_ctrl_link_fec_mon_stop(ctrl_link);
+		cancel_work_sync(&ctrl_link->fec_mon_timer_work);
+
+		flush_work(&ctrl_link->ctrl_lgrp->notif_work);
+		sl_ctrl_link_state_set(ctrl_link, SL_LINK_STATE_DOWN);
+		complete_all(&ctrl_link->down_complete);
+
+		rtn = sl_ctrl_async_link_down_notif_send(ctrl_link, core_cause_map, core_info_map);
+		if (rtn)
+			sl_ctrl_log_warn_trace(ctrl_link, LOG_NAME,
+					       "fault callback async_link_down_notif_send failed [%d]", rtn);
+
+		return 0;
+
+	default:
+		sl_ctrl_log_err(ctrl_link, LOG_NAME,
+				"fault callback invalid (core_state = %u)", core_state);
+
+		flush_work(&ctrl_link->ctrl_lgrp->notif_work);
+		sl_ctrl_link_state_set(ctrl_link, SL_LINK_STATE_DOWN);
+
+		complete_all(&ctrl_link->down_complete);
+
+		info.error = -EBADRQC;
+		rtn = sl_ctrl_lgrp_notif_enqueue(ctrl_link->ctrl_lgrp, ctrl_link->num,
+						 SL_LGRP_NOTIF_LINK_ERROR, &info, core_info_map);
+		if (rtn)
+			sl_ctrl_log_warn_trace(ctrl_link, LOG_NAME,
+					       "fault callback ctrl_lgrp_notif_enqueue failed [%d]", rtn);
+
+		return 0;
+	}
+}
+
+int sl_ctrl_link_an_lp_caps_get_callback(void *tag, struct sl_link_caps *caps, u32 result)
+{
+	int                       rtn;
+	struct sl_ctrl_link      *ctrl_link;
+	union sl_lgrp_notif_info  info;
+
+	ctrl_link          =  tag;
+	info.lp_link_caps = *caps;
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "an lp caps get callback");
+
+	switch (result) {
+	case SL_CORE_LINK_LP_CAPS_DATA:
+		rtn = sl_ctrl_lgrp_notif_enqueue(ctrl_link->ctrl_lgrp, ctrl_link->num,
+						 SL_LGRP_NOTIF_AN_DATA, &info, 0);
+		if (rtn)
+			sl_ctrl_log_warn_trace(ctrl_link, LOG_NAME,
+					       "lp caps data ctrl_lgrp_notif_enqueue failed [%d]", rtn);
+		break;
+	case SL_CORE_LINK_LP_CAPS_TIMEOUT:
+		rtn = sl_ctrl_lgrp_notif_enqueue(ctrl_link->ctrl_lgrp, ctrl_link->num,
+						 SL_LGRP_NOTIF_AN_TIMEOUT, NULL, 0);
+		if (rtn)
+			sl_ctrl_log_warn_trace(ctrl_link, LOG_NAME,
+					       "lp caps timeout ctrl_lgrp_notif_enqueue failed [%d]", rtn);
+		break;
+	case SL_CORE_LINK_LP_CAPS_ERROR:
+	default:
+		rtn = sl_ctrl_lgrp_notif_enqueue(ctrl_link->ctrl_lgrp, ctrl_link->num,
+						 SL_LGRP_NOTIF_AN_ERROR, NULL, 0);
+		if (rtn)
+			sl_ctrl_log_warn_trace(ctrl_link, LOG_NAME,
+					       "lp caps error ctrl_lgrp_notif_enqueue failed [%d]", rtn);
+		break;
+	}
+
+	return 0;
+}
+
+int sl_ctrl_link_down_callback(void *tag, u32 core_state, u64 core_cause_map, u64 core_info_map)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link;
+	char                 cause_str[100];
+
+	ctrl_link = tag;
+
+	sl_link_down_cause_map_with_info_str(core_cause_map, cause_str, sizeof(cause_str));
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"down callback (core_state = %u %s, core_cause = 0x%llX %s, core_info_map = %llu)",
+		core_state, sl_core_link_state_str(core_state), core_cause_map, cause_str, core_info_map);
+
+	switch (core_state) {
+	case SL_CORE_LINK_STATE_DOWN:
+		SL_CTRL_LINK_COUNTER_INC(ctrl_link, LINK_DOWN);
+
+		if (core_cause_map & SL_LINK_DOWN_CAUSE_CANCELED)
+			SL_CTRL_LINK_COUNTER_INC(ctrl_link, LINK_UP_CANCELED);
+
+		sl_ctrl_link_fec_mon_stop(ctrl_link);
+		cancel_work_sync(&ctrl_link->fec_mon_timer_work);
+
+		flush_work(&ctrl_link->ctrl_lgrp->notif_work);
+		sl_ctrl_link_state_set(ctrl_link, SL_LINK_STATE_DOWN);
+		complete_all(&ctrl_link->down_complete);
+
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+				"down callback (down_complete = 0x%p)", &ctrl_link->down_complete);
+
+		rtn = sl_ctrl_link_down_notif_send(ctrl_link, core_cause_map, core_info_map);
+		if (rtn)
+			sl_ctrl_log_warn_trace(ctrl_link, LOG_NAME,
+					       "down callback ctrl_link_down_notif_send failed [%d]", rtn);
+		return 0;
+	default:
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "down callback invalid (core_state = %u %s)",
+				core_state, sl_core_link_state_str(core_state));
+		return -EBADRQC;
+	}
+}
+
+static int sl_ctrl_link_async_down_callback(void *tag, u32 core_state, u64 core_cause_map, u64 core_info_map)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link;
+	char                 cause_str[100];
+
+	ctrl_link = tag;
+
+	sl_link_down_cause_map_with_info_str(core_cause_map, cause_str, sizeof(cause_str));
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"async down callback (core_state = %u %s, core_cause = 0x%llX %s, core_info_map = %llu)",
+		core_state, sl_core_link_state_str(core_state), core_cause_map, cause_str, core_info_map);
+
+	switch (core_state) {
+	case SL_CORE_LINK_STATE_DOWN:
+		SL_CTRL_LINK_COUNTER_INC(ctrl_link, LINK_DOWN);
+
+		sl_ctrl_link_fec_mon_stop(ctrl_link);
+		cancel_work_sync(&ctrl_link->fec_mon_timer_work);
+
+		flush_work(&ctrl_link->ctrl_lgrp->notif_work);
+		sl_ctrl_link_state_set(ctrl_link, SL_LINK_STATE_DOWN);
+		complete_all(&ctrl_link->down_complete);
+
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+				"async down callback (down_complete = 0x%p)", &ctrl_link->down_complete);
+
+		rtn = sl_ctrl_async_link_down_notif_send(ctrl_link, core_cause_map, core_info_map);
+		if (rtn)
+			sl_ctrl_log_warn_trace(ctrl_link, LOG_NAME,
+					       "async down callback async_link_down_notif_send failed [%d]", rtn);
+
+		sl_ctrl_link_put(ctrl_link);
+		return 0;
+	default:
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "async down callback invalid (core_state = %u %s)",
+				core_state, sl_core_link_state_str(core_state));
+
+		sl_ctrl_link_put(ctrl_link);
+		return -EBADRQC;
+	}
+}
+
+int sl_ctrl_link_async_down(struct sl_ctrl_link *ctrl_link, u64 down_cause_map, bool force_down)
+{
+	int  rtn;
+	u32  link_state;
+	u32  policy_options;
+	bool accepted;
+	char cause_str[SL_LINK_DOWN_CAUSE_STR_SIZE];
+
+	if (!sl_ctrl_link_kref_get_unless_zero(ctrl_link)) {
+		sl_ctrl_log_err(ctrl_link, LOG_NAME,
+				"async_down kref_get_unless_zero failed (ctrl_link = 0x%p)", ctrl_link);
+		return -EBADRQC;
+	}
+
+	sl_link_down_cause_map_with_info_str(down_cause_map, cause_str, sizeof(cause_str));
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"async_down (down_cause_map = 0x%llX %s)", down_cause_map, cause_str);
+
+	sl_ctrl_link_up_clock_reset(ctrl_link);
+
+	policy_options = sl_ctrl_link_policy_options_get(ctrl_link);
+
+	spin_lock(&ctrl_link->data_lock);
+	link_state = ctrl_link->state;
+	switch (link_state) {
+	case SL_LINK_STATE_UP_DOWN_REQ:
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "async_down already requested");
+		spin_unlock(&ctrl_link->data_lock);
+		sl_ctrl_link_put(ctrl_link);
+		return 0;
+	case SL_LINK_STATE_UP:
+		if (!force_down && (policy_options & SL_LINK_POLICY_OPT_LINK_DOWN_REQ)) {
+			ctrl_link->state = SL_LINK_STATE_UP_DOWN_REQ;
+			sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "async_down request link down");
+			spin_unlock(&ctrl_link->data_lock);
+			rtn = sl_ctrl_link_down_req_notif_send(ctrl_link, down_cause_map, 0);
+			if (rtn)
+				sl_ctrl_log_warn_trace(ctrl_link, LOG_NAME,
+						       "async_down ctrl_link_down_req_notif_send failed [%d]",
+						       rtn);
+			sl_ctrl_link_put(ctrl_link);
+			return 0;
+		}
+		ctrl_link->state = SL_LINK_STATE_STOPPING;
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "async_down stopping");
+		spin_unlock(&ctrl_link->data_lock);
+		kref_get(&ctrl_link->ref_cnt);
+		rtn = sl_core_link_down_request(ctrl_link->ctrl_lgrp->ctrl_ldev->num,
+						ctrl_link->ctrl_lgrp->num, ctrl_link->num,
+						sl_ctrl_link_async_down_callback, ctrl_link,
+						down_cause_map, &accepted);
+		if (!accepted)
+			sl_ctrl_link_put(ctrl_link);
+		if (rtn) {
+			sl_ctrl_log_err(ctrl_link, LOG_NAME, "async_down core_link_down failed [%d]", rtn);
+			spin_lock(&ctrl_link->data_lock);
+			if (ctrl_link->state == SL_LINK_STATE_STOPPING)
+				ctrl_link->state = SL_LINK_STATE_UP;
+			spin_unlock(&ctrl_link->data_lock);
+			sl_ctrl_link_put(ctrl_link);
+			return rtn;
+		}
+		sl_ctrl_link_put(ctrl_link);
+		return 0;
+	case SL_LINK_STATE_DOWN:
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "async_down already down");
+		spin_unlock(&ctrl_link->data_lock);
+		sl_ctrl_link_put(ctrl_link);
+		return 0;
+	case SL_LINK_STATE_STOPPING:
+		sl_ctrl_log_dbg(ctrl_link, LOG_NAME, "async_down already stopping");
+		spin_unlock(&ctrl_link->data_lock);
+		sl_ctrl_link_put(ctrl_link);
+		return 0;
+	default:
+		sl_ctrl_log_err(ctrl_link, LOG_NAME, "async_down invalid state (link_state = %u %s)",
+				link_state, sl_link_state_str(link_state));
+		spin_unlock(&ctrl_link->data_lock);
+		sl_ctrl_link_put(ctrl_link);
+		return -EBADRQC;
+	}
+}
+
+void sl_ctrl_link_config_get(struct sl_ctrl_link *ctrl_link, struct sl_link_config *link_config)
+{
+	spin_lock(&ctrl_link->config_lock);
+	*link_config = ctrl_link->config;
+	spin_unlock(&ctrl_link->config_lock);
+}
+
+void sl_ctrl_link_policy_get(struct sl_ctrl_link *ctrl_link, struct sl_link_policy *link_policy)
+{
+	spin_lock(&ctrl_link->config_lock);
+	*link_policy = ctrl_link->policy;
+	spin_unlock(&ctrl_link->config_lock);
+}
+
+s32 sl_ctrl_link_policy_fec_mon_ucw_down_limit_get(struct sl_ctrl_link *ctrl_link)
+{
+	s32 fec_mon_ucw_down_limit;
+
+	spin_lock(&ctrl_link->config_lock);
+	fec_mon_ucw_down_limit = ctrl_link->policy.fec_mon_ucw_down_limit;
+	spin_unlock(&ctrl_link->config_lock);
+
+	return fec_mon_ucw_down_limit;
+}
+
+s32 sl_ctrl_link_policy_fec_mon_ucw_warn_limit_get(struct sl_ctrl_link *ctrl_link)
+{
+	s32 fec_mon_ucw_warn_limit;
+
+	spin_lock(&ctrl_link->config_lock);
+	fec_mon_ucw_warn_limit = ctrl_link->policy.fec_mon_ucw_warn_limit;
+	spin_unlock(&ctrl_link->config_lock);
+
+	return fec_mon_ucw_warn_limit;
+}
+
+s32 sl_ctrl_link_policy_fec_mon_ccw_down_limit_get(struct sl_ctrl_link *ctrl_link)
+{
+	s32 fec_mon_ccw_down_limit;
+
+	spin_lock(&ctrl_link->config_lock);
+	fec_mon_ccw_down_limit = ctrl_link->policy.fec_mon_ccw_down_limit;
+	spin_unlock(&ctrl_link->config_lock);
+
+	return fec_mon_ccw_down_limit;
+}
+
+s32 sl_ctrl_link_policy_fec_mon_ccw_warn_limit_get(struct sl_ctrl_link *ctrl_link)
+{
+	s32 fec_mon_ccw_warn_limit;
+
+	spin_lock(&ctrl_link->config_lock);
+	fec_mon_ccw_warn_limit = ctrl_link->policy.fec_mon_ccw_warn_limit;
+	spin_unlock(&ctrl_link->config_lock);
+
+	return fec_mon_ccw_warn_limit;
+}
+
+s32 sl_ctrl_link_policy_fec_mon_period_ms_get(struct sl_ctrl_link *ctrl_link)
+{
+	s32 fec_mon_period_ms;
+
+	spin_lock(&ctrl_link->config_lock);
+	fec_mon_period_ms = ctrl_link->policy.fec_mon_period_ms;
+	spin_unlock(&ctrl_link->config_lock);
+
+	return fec_mon_period_ms;
+}
+
+u32 sl_ctrl_link_policy_options_get(struct sl_ctrl_link *ctrl_link)
+{
+	u32 options;
+
+	spin_lock(&ctrl_link->config_lock);
+	options = ctrl_link->policy.options;
+	spin_unlock(&ctrl_link->config_lock);
+
+	return options;
+}
+
+void sl_ctrl_link_state_set(struct sl_ctrl_link *ctrl_link, u32 link_state)
+{
+	spin_lock(&ctrl_link->data_lock);
+	ctrl_link->state = link_state;
+	spin_unlock(&ctrl_link->data_lock);
+}
+
+u32 sl_ctrl_link_state_get(struct sl_ctrl_link *ctrl_link)
+{
+	u32 state;
+
+	spin_lock(&ctrl_link->data_lock);
+	state = ctrl_link->state;
+	spin_unlock(&ctrl_link->data_lock);
+
+	return state;
+}
+
+int sl_ctrl_link_last_up_fail_cause_map_get(struct sl_ctrl_link *ctrl_link, u64 *last_up_fail_cause_map)
+{
+	spin_lock(&ctrl_link->data_lock);
+	*last_up_fail_cause_map = ctrl_link->last_up_fail_cause_map;
+	spin_unlock(&ctrl_link->data_lock);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"last_up_fail_cause_map_get (last_up_fail_cause_map = 0x%llX)", *last_up_fail_cause_map);
+
+	return 0;
+}
+
+int sl_ctrl_link_last_up_fail_cause_info_get(struct sl_ctrl_link *ctrl_link, u64 *last_up_fail_cause_map,
+					     time64_t *last_up_fail_time)
+{
+	spin_lock(&ctrl_link->data_lock);
+	*last_up_fail_cause_map = ctrl_link->last_up_fail_cause_map;
+	*last_up_fail_time = ctrl_link->last_up_fail_time;
+	spin_unlock(&ctrl_link->data_lock);
+
+	sl_ctrl_log_dbg(ctrl_link, LOG_NAME,
+			"last up fail time show (cause_map = 0x%llX, time = %lld %ptTt %ptTd)",
+			*last_up_fail_cause_map, *last_up_fail_time, last_up_fail_time, last_up_fail_time);
+
+	return 0;
+}
diff --git a/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_llr.c b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_llr.c
new file mode 100644
index 000000000000..016ea353da4f
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_llr.c
@@ -0,0 +1,630 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kobject.h>
+#include <linux/types.h>
+#include <linux/spinlock.h>
+#include <linux/slab.h>
+
+#include "sl_asic.h"
+#include "sl_sysfs.h"
+#include "base/sl_ctrl_log.h"
+#include "sl_ctrl_ldev.h"
+#include "sl_ctrl_lgrp.h"
+#include "sl_ctrl_lgrp_notif.h"
+#include "sl_ctrl_llr.h"
+#include "data/sl_core_data_llr.h"
+#include "sl_core_str.h"
+#include "sl_ctrl_llr_counters.h"
+
+#define LOG_NAME SL_CTRL_LLR_LOG_NAME
+
+#define SL_CTRL_LLR_DEL_WAIT_TIMEOUT_MS 2000
+
+static struct sl_ctrl_llr *ctrl_llrs[SL_ASIC_MAX_LDEVS][SL_ASIC_MAX_LGRPS][SL_ASIC_MAX_LINKS];
+static DEFINE_SPINLOCK(ctrl_llrs_lock);
+
+static void sl_ctrl_llr_setup_callback(void *tag,
+				       enum sl_core_llr_state core_llr_state,
+				       u64 core_imap,
+				       struct sl_llr_data core_llr_data)
+{
+	int rtn;
+	struct sl_ctrl_llr *ctrl_llr;
+	union sl_lgrp_notif_info info;
+
+	ctrl_llr = tag;
+
+	ctrl_llr->setup.state = core_llr_state;
+	ctrl_llr->setup.imap  = core_imap;
+	ctrl_llr->setup.data  = core_llr_data;
+
+	sl_ctrl_log_dbg(ctrl_llr, LOG_NAME, "setup callback (state = %u %s)", core_llr_state,
+			sl_core_llr_state_str(core_llr_state));
+
+	switch (core_llr_state) {
+	case SL_CORE_LLR_STATE_SETUP:
+		SL_CTRL_LLR_COUNTER_INC(ctrl_llr, LLR_SETUP);
+		info.llr_data = ctrl_llr->setup.data;
+		rtn = sl_ctrl_lgrp_notif_enqueue(ctrl_llr->ctrl_lgrp, ctrl_llr->num,
+						 SL_LGRP_NOTIF_LLR_SETUP, &info, ctrl_llr->setup.imap);
+		if (rtn)
+			sl_ctrl_log_warn_trace(ctrl_llr, LOG_NAME,
+					       "setup SETUP ctrl_lgrp_notif_enqueue failed [%d]", rtn);
+		return;
+	case SL_CORE_LLR_STATE_SETUP_TIMEOUT:
+		SL_CTRL_LLR_COUNTER_INC(ctrl_llr, LLR_SETUP_TIMEOUT);
+		rtn = sl_ctrl_lgrp_notif_enqueue(ctrl_llr->ctrl_lgrp, ctrl_llr->num,
+						 SL_LGRP_NOTIF_LLR_SETUP_TIMEOUT, NULL, ctrl_llr->setup.imap);
+		if (rtn)
+			sl_ctrl_log_warn_trace(ctrl_llr, LOG_NAME,
+					       "setup TIMEOUT ctrl_lgrp_notif_enqueue failed [%d]", rtn);
+		return;
+	case SL_CORE_LLR_STATE_CONFIGURED:
+		SL_CTRL_LLR_COUNTER_INC(ctrl_llr, LLR_CONFIGURED);
+		memset(&ctrl_llr->setup.data, 0, sizeof(struct sl_llr_data));
+		rtn = sl_ctrl_lgrp_notif_enqueue(ctrl_llr->ctrl_lgrp, ctrl_llr->num,
+						 SL_LGRP_NOTIF_LLR_CANCELED, NULL, ctrl_llr->setup.imap);
+		if (rtn)
+			sl_ctrl_log_warn_trace(ctrl_llr, LOG_NAME,
+					       "setup CONFIGURED ctrl_lgrp_notif_enqueue failed [%d]", rtn);
+		return;
+	default:
+		memset(&ctrl_llr->setup.data, 0, sizeof(struct sl_llr_data));
+		sl_ctrl_log_err(ctrl_llr, LOG_NAME,
+				"setup ERROR invalid (state = %u %s)",
+				core_llr_state, sl_core_llr_state_str(core_llr_state));
+		info.error = -ENOMSG;
+		rtn = sl_ctrl_lgrp_notif_enqueue(ctrl_llr->ctrl_lgrp, ctrl_llr->num,
+						 SL_LGRP_NOTIF_LLR_ERROR, &info, ctrl_llr->setup.imap);
+		if (rtn)
+			sl_ctrl_log_warn_trace(ctrl_llr, LOG_NAME,
+					       "setup ERROR ctrl_lgrp_notif_enqueue failed [%d]", rtn);
+		return;
+	}
+}
+
+static void sl_ctrl_llr_start_callback(void *tag,
+				       enum sl_core_llr_state core_llr_state,
+				       u64 core_imap)
+{
+	int rtn;
+	struct sl_ctrl_llr *ctrl_llr;
+	union sl_lgrp_notif_info info;
+
+	ctrl_llr = tag;
+
+	ctrl_llr->start.state = core_llr_state;
+	ctrl_llr->start.imap  = core_imap;
+
+	sl_ctrl_log_dbg(ctrl_llr, LOG_NAME, "start callback (state = %u %s)",
+			core_llr_state, sl_core_llr_state_str(core_llr_state));
+
+	switch (core_llr_state) {
+	case SL_CORE_LLR_STATE_RUNNING:
+		SL_CTRL_LLR_COUNTER_INC(ctrl_llr, LLR_RUNNING);
+		rtn = sl_ctrl_lgrp_notif_enqueue(ctrl_llr->ctrl_lgrp, ctrl_llr->num,
+						 SL_LGRP_NOTIF_LLR_RUNNING, NULL, ctrl_llr->start.imap);
+		if (rtn)
+			sl_ctrl_log_warn_trace(ctrl_llr, LOG_NAME,
+					       "start RUNNING ctrl_lgrp_notif_enqueue failed [%d[", rtn);
+		return;
+	case SL_CORE_LLR_STATE_START_TIMEOUT:
+		SL_CTRL_LLR_COUNTER_INC(ctrl_llr, LLR_START_TIMEOUT);
+		if (ctrl_llr->policy.options & SL_LLR_POLICY_OPT_CONTINUOUS_START_TRIES) {
+			sl_ctrl_log_dbg(ctrl_llr, LOG_NAME, "start TIMEOUT retry");
+			rtn = sl_core_llr_start(ctrl_llr->ctrl_lgrp->ctrl_ldev->num, ctrl_llr->ctrl_lgrp->num,
+						ctrl_llr->num, sl_ctrl_llr_start_callback, ctrl_llr, 0);
+			if (rtn)
+				sl_ctrl_log_warn_trace(ctrl_llr, LOG_NAME,
+						       "start TIMEOUT core_llr_start retry failed [%d]", rtn);
+		}
+		rtn = sl_ctrl_lgrp_notif_enqueue(ctrl_llr->ctrl_lgrp, ctrl_llr->num,
+						 SL_LGRP_NOTIF_LLR_START_TIMEOUT, NULL, ctrl_llr->start.imap);
+		if (rtn)
+			sl_ctrl_log_warn_trace(ctrl_llr, LOG_NAME,
+					       "start TIMEOUT ctrl_lgrp_notif_enqueue failed [%d[", rtn);
+		return;
+	case SL_CORE_LLR_STATE_SETUP:
+		SL_CTRL_LLR_COUNTER_INC(ctrl_llr, LLR_SETUP);
+		rtn = sl_ctrl_lgrp_notif_enqueue(ctrl_llr->ctrl_lgrp, ctrl_llr->num,
+						 SL_LGRP_NOTIF_LLR_CANCELED, NULL, ctrl_llr->start.imap);
+		if (rtn)
+			sl_ctrl_log_warn_trace(ctrl_llr, LOG_NAME,
+					       "start CONFIGURED ctrl_lgrp_notif_enqueue failed [%d[", rtn);
+		return;
+	default:
+		memset(&ctrl_llr->setup.data, 0, sizeof(struct sl_llr_data));
+		sl_ctrl_log_err(ctrl_llr, LOG_NAME, "start ERROR invalid (state = %u %s)",
+				core_llr_state, sl_core_llr_state_str(core_llr_state));
+		info.error = -ENOMSG;
+		rtn = sl_ctrl_lgrp_notif_enqueue(ctrl_llr->ctrl_lgrp, ctrl_llr->num, SL_LGRP_NOTIF_LLR_ERROR,
+						 &info, ctrl_llr->setup.imap);
+		if (rtn)
+			sl_ctrl_log_warn_trace(ctrl_llr, LOG_NAME, "start ERROR ctrl_lgrp_notif_enqueue failed [%d[",
+					       rtn);
+		return;
+	}
+}
+
+int sl_ctrl_llr_new(u8 ldev_num, u8 lgrp_num, u8 llr_num, struct kobject *sysfs_parent)
+{
+	int                 rtn;
+	struct sl_ctrl_llr *ctrl_llr;
+
+	ctrl_llr = sl_ctrl_llr_get(ldev_num, lgrp_num, llr_num);
+	if (ctrl_llr) {
+		sl_ctrl_log_err(NULL, LOG_NAME, "exists (ctrl_llr = 0x%p)", ctrl_llr);
+		return -EBADRQC;
+	}
+
+	ctrl_llr = kzalloc(sizeof(*ctrl_llr), GFP_KERNEL);
+	if (!ctrl_llr)
+		return -ENOMEM;
+
+	ctrl_llr->magic     = SL_CTRL_LLR_MAGIC;
+	ctrl_llr->ver       = SL_CTRL_LLR_VER;
+	ctrl_llr->num       = llr_num;
+	ctrl_llr->ctrl_lgrp = sl_ctrl_lgrp_get(ldev_num, lgrp_num);
+	if (!ctrl_llr->ctrl_lgrp) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"new NULL lgrp (ldev_num = %u, lgrp_num = %u)", ldev_num, lgrp_num);
+		kfree(ctrl_llr);
+		return -EBADRQC;
+	}
+
+	spin_lock_init(&ctrl_llr->data_lock);
+	kref_init(&ctrl_llr->ref_cnt);
+	init_completion(&ctrl_llr->del_complete);
+
+	rtn = sl_ctrl_llr_counters_init(ctrl_llr);
+	if (rtn) {
+		sl_ctrl_log_err(ctrl_llr, LOG_NAME, "ctrl_llr_counters_init failed [%d]", rtn);
+		goto out;
+	}
+
+	rtn = sl_ctrl_llr_cause_counters_init(ctrl_llr);
+	if (rtn) {
+		sl_ctrl_log_err(ctrl_llr, LOG_NAME, "ctrl_llr_cause_counters_init failed [%d]", rtn);
+		goto out_counters;
+	}
+
+	rtn = sl_core_llr_new(ldev_num, lgrp_num, llr_num);
+	if (rtn) {
+		sl_ctrl_log_err(ctrl_llr, LOG_NAME, "core_llr_new failed [%d]", rtn);
+		goto out_cause_counters;
+	}
+
+	if (sysfs_parent) {
+		ctrl_llr->parent_kobj = sysfs_parent;
+
+		rtn = sl_sysfs_llr_create(ctrl_llr);
+		if (rtn) {
+			sl_ctrl_log_err(ctrl_llr, LOG_NAME, "sysfs_llr_create failed [%d]", rtn);
+			goto out_llr_new;
+		}
+	}
+	sl_ctrl_log_dbg(ctrl_llr, LOG_NAME, "new (ctrl_llr = 0x%p)", ctrl_llr);
+
+	spin_lock(&ctrl_llrs_lock);
+	ctrl_llrs[ldev_num][lgrp_num][llr_num] = ctrl_llr;
+	spin_unlock(&ctrl_llrs_lock);
+
+	return 0;
+out_llr_new:
+		sl_core_llr_del(ldev_num, lgrp_num, llr_num);
+out_cause_counters:
+	sl_ctrl_llr_cause_counters_del(ctrl_llr);
+out_counters:
+	sl_ctrl_llr_counters_del(ctrl_llr);
+out:
+	kfree(ctrl_llr);
+	return rtn;
+}
+
+static void sl_ctrl_llr_release(struct kref *kref)
+{
+	int                 rtn;
+	struct sl_ctrl_llr *ctrl_llr;
+	u8                  ldev_num;
+	u8                  lgrp_num;
+	u8                  llr_num;
+
+	ctrl_llr = container_of(kref, struct sl_ctrl_llr, ref_cnt);
+	ldev_num = ctrl_llr->ctrl_lgrp->ctrl_ldev->num;
+	lgrp_num = ctrl_llr->ctrl_lgrp->num;
+	llr_num = ctrl_llr->num;
+
+	sl_ctrl_log_dbg(ctrl_llr, LOG_NAME, "release (ctrl_llr = 0x%p)", ctrl_llr);
+
+	rtn = sl_core_llr_stop(ldev_num, lgrp_num, llr_num);
+	if (rtn)
+		sl_ctrl_log_warn_trace(ctrl_llr, LOG_NAME, "release core_llr_stop failed [%d]", rtn);
+
+	/* Must delete sysfs first to guarantee nobody is reading */
+	sl_sysfs_llr_delete(ctrl_llr);
+
+	sl_core_llr_del(ldev_num, lgrp_num, llr_num);
+
+	/* Free the counters and unpublish together so cause_counter_inc() sees neither half-done */
+	spin_lock(&ctrl_llrs_lock);
+	sl_ctrl_llr_counters_del(ctrl_llr);
+	sl_ctrl_llr_cause_counters_del(ctrl_llr);
+	ctrl_llrs[ldev_num][lgrp_num][llr_num] = NULL;
+	spin_unlock(&ctrl_llrs_lock);
+
+	complete_all(&ctrl_llr->del_complete);
+
+	kfree(ctrl_llr);
+}
+
+static int sl_ctrl_llr_put(struct sl_ctrl_llr *ctrl_llr)
+{
+	return kref_put(&ctrl_llr->ref_cnt, sl_ctrl_llr_release);
+}
+
+int sl_ctrl_llr_del(u8 ldev_num, u8 lgrp_num, u8 llr_num)
+{
+	struct sl_ctrl_llr *ctrl_llr;
+	unsigned long       timeleft;
+
+	ctrl_llr = sl_ctrl_llr_get(ldev_num, lgrp_num, llr_num);
+	if (!ctrl_llr) {
+		sl_ctrl_log_err_trace(NULL, LOG_NAME,
+				      "del not found (ldev_num = %u, lgrp_num = %u, llr_num = %u)",
+				      ldev_num, lgrp_num, llr_num);
+		return -EBADRQC;
+	}
+
+	/* Release occurs on the last caller. Block until complete. */
+	if (!sl_ctrl_llr_put(ctrl_llr)) {
+		timeleft = wait_for_completion_timeout(&ctrl_llr->del_complete,
+						       msecs_to_jiffies(SL_CTRL_LLR_DEL_WAIT_TIMEOUT_MS));
+
+		if (timeleft == 0) {
+			sl_ctrl_log_err(NULL, LOG_NAME,
+					"del completion_timeout (ctrl_llr = 0x%p)", ctrl_llr);
+			return -ETIMEDOUT;
+		}
+	}
+
+	return 0;
+}
+
+static bool sl_ctrl_llr_kref_get_unless_zero(struct sl_ctrl_llr *ctrl_llr)
+{
+	return (kref_get_unless_zero(&ctrl_llr->ref_cnt) != 0);
+}
+
+struct sl_ctrl_llr *sl_ctrl_llr_get(u8 ldev_num, u8 lgrp_num, u8 llr_num)
+{
+	struct sl_ctrl_llr *ctrl_llr;
+
+	spin_lock(&ctrl_llrs_lock);
+	ctrl_llr = ctrl_llrs[ldev_num][lgrp_num][llr_num];
+	spin_unlock(&ctrl_llrs_lock);
+
+	sl_ctrl_log_dbg(NULL, LOG_NAME,
+			"get (ldev_num = %u, lgrp_num = %u, llr_num = %u, ctrl_llr = 0x%p)",
+			ldev_num, lgrp_num, llr_num, ctrl_llr);
+
+	return ctrl_llr;
+}
+
+/*
+ * The lookup and the counter update are done under ctrl_llrs_lock, which
+ * sl_ctrl_llr_release() also holds while it frees the counters.
+ */
+void sl_ctrl_llr_cause_counter_inc(struct sl_core_llr *core_llr, unsigned long cause_map)
+{
+	struct sl_ctrl_llr *ctrl_llr;
+	u8                  ldev_num = core_llr->core_lgrp->core_ldev->num;
+	u8                  lgrp_num = core_llr->core_lgrp->num;
+
+	spin_lock(&ctrl_llrs_lock);
+	ctrl_llr = ctrl_llrs[ldev_num][lgrp_num][core_llr->num];
+	if (ctrl_llr)
+		sl_ctrl_llr_cause_counters_inc(ctrl_llr, cause_map);
+	spin_unlock(&ctrl_llrs_lock);
+
+	if (!ctrl_llr)
+		sl_ctrl_log_dbg(NULL, LOG_NAME, "llr cause counter inc - llr not found");
+}
+
+int sl_ctrl_llr_config_set(u8 ldev_num, u8 lgrp_num, u8 llr_num, struct sl_llr_config *llr_config)
+{
+	int                rtn;
+	struct sl_ctrl_llr *ctrl_llr;
+
+	ctrl_llr = sl_ctrl_llr_get(ldev_num, lgrp_num, llr_num);
+	if (!ctrl_llr) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"config set NULL llr (ldev_num = %u, lgrp_num = %u, llr_num = %u)",
+				ldev_num, lgrp_num, llr_num);
+		return -EBADRQC;
+	}
+
+	if (!sl_ctrl_llr_kref_get_unless_zero(ctrl_llr)) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"config set kref_get_unless_zero failed (ctrl_llr = 0x%p)",
+				ctrl_llr);
+		return -EBADRQC;
+	}
+
+	sl_ctrl_log_dbg(ctrl_llr, LOG_NAME, "config set (setup timeout = %d, start timeout = %d)",
+			llr_config->setup_timeout_ms, llr_config->start_timeout_ms);
+
+	rtn = sl_core_llr_config_set(ldev_num, lgrp_num, llr_num, llr_config);
+	if (rtn) {
+		sl_ctrl_log_err(ctrl_llr, LOG_NAME, "core_llr_config_set failed [%d]", rtn);
+		goto out;
+	}
+
+	spin_lock(&ctrl_llr->data_lock);
+	ctrl_llr->config = *llr_config;
+	spin_unlock(&ctrl_llr->data_lock);
+
+out:
+	if (sl_ctrl_llr_put(ctrl_llr))
+		sl_ctrl_log_dbg(NULL, LOG_NAME,
+				"config set - llr removed (ctrl_llr = 0x%p)", ctrl_llr);
+
+	return rtn;
+}
+
+int sl_ctrl_llr_policy_set(u8 ldev_num, u8 lgrp_num, u8 llr_num, struct sl_llr_policy *llr_policy)
+{
+	int                rtn;
+	struct sl_ctrl_llr *ctrl_llr;
+
+	ctrl_llr = sl_ctrl_llr_get(ldev_num, lgrp_num, llr_num);
+	if (!ctrl_llr) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"policy set NULL llr (ldev_num = %u, lgrp_num = %u, llr_num = %u)",
+				ldev_num, lgrp_num, llr_num);
+		return -EBADRQC;
+	}
+
+	if (!sl_ctrl_llr_kref_get_unless_zero(ctrl_llr)) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"policy set kref_get_unless_zero failed (ctrl_llr = 0x%p)", ctrl_llr);
+		return -EBADRQC;
+	}
+
+	sl_ctrl_log_dbg(ctrl_llr, LOG_NAME, "policy set");
+
+	rtn = sl_core_llr_policy_set(ldev_num, lgrp_num, llr_num, llr_policy);
+	if (rtn) {
+		sl_ctrl_log_err(ctrl_llr, LOG_NAME, "core_llr_policy_set failed [%d]", rtn);
+		goto out;
+	}
+
+	spin_lock(&ctrl_llr->data_lock);
+	ctrl_llr->policy = *llr_policy;
+	spin_unlock(&ctrl_llr->data_lock);
+
+out:
+	if (sl_ctrl_llr_put(ctrl_llr))
+		sl_ctrl_log_dbg(NULL, LOG_NAME,
+				"policy set - llr removed (ctrl_llr = 0x%p)", ctrl_llr);
+
+	return rtn;
+}
+
+int sl_ctrl_llr_setup(u8 ldev_num, u8 lgrp_num, u8 llr_num)
+{
+	int                rtn;
+	struct sl_ctrl_llr *ctrl_llr;
+
+	ctrl_llr = sl_ctrl_llr_get(ldev_num, lgrp_num, llr_num);
+	if (!ctrl_llr) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"setup NULL llr (ldev_num = %u, lgrp_num = %u, llr_num = %u)",
+				ldev_num, lgrp_num, llr_num);
+		return -EBADRQC;
+	}
+
+	if (!sl_ctrl_llr_kref_get_unless_zero(ctrl_llr)) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"setup kref_get_unless_zero failed (ctrl_llr = 0x%p)", ctrl_llr);
+		return -EBADRQC;
+	}
+
+	sl_ctrl_log_dbg(ctrl_llr, LOG_NAME, "setup");
+
+	SL_CTRL_LLR_COUNTER_INC(ctrl_llr, LLR_SETUP_CMD);
+
+	rtn = sl_core_llr_setup(ldev_num, lgrp_num, llr_num,
+				sl_ctrl_llr_setup_callback, ctrl_llr, 0);
+	if (rtn) {
+		sl_ctrl_log_err_trace(ctrl_llr, LOG_NAME, "core_llr_setup failed [%d]", rtn);
+		SL_CTRL_LLR_COUNTER_INC(ctrl_llr, LLR_SETUP_FAIL);
+	}
+
+	if (sl_ctrl_llr_put(ctrl_llr))
+		sl_ctrl_log_dbg(NULL, LOG_NAME, "setup - llr removed (ctrl_llr = 0x%p)", ctrl_llr);
+
+	return rtn;
+}
+
+int sl_ctrl_llr_start(u8 ldev_num, u8 lgrp_num, u8 llr_num)
+{
+	int                rtn;
+	struct sl_ctrl_llr *ctrl_llr;
+
+	ctrl_llr = sl_ctrl_llr_get(ldev_num, lgrp_num, llr_num);
+	if (!ctrl_llr) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"start NULL llr (ldev_num = %u, lgrp_num = %u, llr_num = %u)",
+				ldev_num, lgrp_num, llr_num);
+		return -EBADRQC;
+	}
+
+	if (!sl_ctrl_llr_kref_get_unless_zero(ctrl_llr)) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"start kref_get_unless_zero failed (ctrl_llr = 0x%p)", ctrl_llr);
+		return -EBADRQC;
+	}
+
+	sl_ctrl_log_dbg(ctrl_llr, LOG_NAME, "start");
+
+	SL_CTRL_LLR_COUNTER_INC(ctrl_llr, LLR_START_CMD);
+
+	rtn = sl_core_llr_start(ldev_num, lgrp_num, llr_num,
+				sl_ctrl_llr_start_callback, ctrl_llr, 0);
+	if (rtn) {
+		sl_ctrl_log_err_trace(ctrl_llr, LOG_NAME, "core_llr_start failed [%d]", rtn);
+		SL_CTRL_LLR_COUNTER_INC(ctrl_llr, LLR_START_FAIL);
+	}
+
+	if (sl_ctrl_llr_put(ctrl_llr))
+		sl_ctrl_log_dbg(NULL, LOG_NAME, "start - llr removed (ctrl_llr = 0x%p)", ctrl_llr);
+
+	return rtn;
+}
+
+int sl_ctrl_llr_stop(u8 ldev_num, u8 lgrp_num, u8 llr_num)
+{
+	int                rtn;
+	struct sl_ctrl_llr *ctrl_llr;
+
+	ctrl_llr = sl_ctrl_llr_get(ldev_num, lgrp_num, llr_num);
+	if (!ctrl_llr) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"stop NULL llr (ldev_num = %u, lgrp_num = %u, llr_num = %u)",
+				ldev_num, lgrp_num, llr_num);
+		return -EBADRQC;
+	}
+
+	if (!sl_ctrl_llr_kref_get_unless_zero(ctrl_llr)) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"stop kref_get_unless_zero failed (ctrl_llr = 0x%p)", ctrl_llr);
+		return -EBADRQC;
+	}
+
+	sl_ctrl_log_dbg(ctrl_llr, LOG_NAME, "stop");
+
+	SL_CTRL_LLR_COUNTER_INC(ctrl_llr, LLR_STOP_CMD);
+
+	rtn = sl_core_llr_stop(ldev_num, lgrp_num, llr_num);
+	if (rtn) {
+		sl_ctrl_log_err_trace(ctrl_llr, LOG_NAME, "core_llr_stop failed [%d]", rtn);
+		SL_CTRL_LLR_COUNTER_INC(ctrl_llr, LLR_STOP_FAIL);
+	}
+
+	if (sl_ctrl_llr_put(ctrl_llr))
+		sl_ctrl_log_dbg(NULL, LOG_NAME, "stop - llr removed (ctrl_llr = 0x%p)", ctrl_llr);
+
+	return rtn;
+}
+
+enum sl_llr_state sl_ctrl_llr_state_from_core_llr_state(enum sl_core_llr_state core_llr_state)
+{
+	switch (core_llr_state) {
+	case SL_CORE_LLR_STATE_NEW:
+		return SL_LLR_STATE_OFF;
+	case SL_CORE_LLR_STATE_CONFIGURED:
+	case SL_CORE_LLR_STATE_SETUP_TIMEOUT:
+	case SL_CORE_LLR_STATE_SETUP_STOPPING:
+		return SL_LLR_STATE_CONFIGURED;
+	case SL_CORE_LLR_STATE_SETTING_UP:
+		return SL_LLR_STATE_SETUP_BUSY;
+	case SL_CORE_LLR_STATE_SETUP:
+	case SL_CORE_LLR_STATE_START_TIMEOUT:
+		return SL_LLR_STATE_SETUP;
+	case SL_CORE_LLR_STATE_STARTING:
+		return SL_LLR_STATE_START_BUSY;
+	case SL_CORE_LLR_STATE_RUNNING:
+		return SL_LLR_STATE_RUNNING;
+	case SL_CORE_LLR_STATE_STOPPING:
+		return SL_LLR_STATE_STOP_BUSY;
+	case SL_CORE_LLR_STATE_SETUP_CANCELING:
+	case SL_CORE_LLR_STATE_START_CANCELING:
+		return SL_LLR_STATE_CANCELING;
+	case SL_CORE_LLR_STATE_INVALID:
+	default:
+		return SL_LLR_STATE_INVALID;
+	}
+}
+
+int sl_ctrl_llr_state_get(u8 ldev_num, u8 lgrp_num, u8 llr_num, enum sl_llr_state *state)
+{
+	int rtn;
+	struct sl_ctrl_llr *ctrl_llr;
+	enum sl_core_llr_state core_llr_state;
+
+	ctrl_llr = sl_ctrl_llr_get(ldev_num, lgrp_num, llr_num);
+	if (!ctrl_llr) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"state get NULL llr (ldev_num = %u, lgrp_num = %u, llr_num = %u)",
+				ldev_num, lgrp_num, llr_num);
+		return -EBADRQC;
+	}
+
+	if (!sl_ctrl_llr_kref_get_unless_zero(ctrl_llr)) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"state get kref_get_unless_zero failed (ctrl_llr = 0x%p)",
+				ctrl_llr);
+		return -EBADRQC;
+	}
+
+	rtn = sl_core_llr_state_get(ldev_num, lgrp_num, llr_num, &core_llr_state);
+	if (rtn) {
+		sl_ctrl_log_err_trace(ctrl_llr, LOG_NAME, "core_llr_state_get failed [%d]", rtn);
+		*state = SL_LLR_STATE_OFF;
+		rtn = 0;
+		goto out;
+	}
+
+	*state = sl_ctrl_llr_state_from_core_llr_state(core_llr_state);
+	if (*state == SL_LLR_STATE_INVALID)
+		sl_ctrl_log_err(ctrl_llr, LOG_NAME,
+				"invalid (core_llr_state = %u %s)",
+				core_llr_state, sl_core_llr_state_str(core_llr_state));
+
+	sl_ctrl_log_dbg(ctrl_llr, LOG_NAME, "state (core = %u %s, ctrl = %u %s)",
+			core_llr_state, sl_core_llr_state_str(core_llr_state),
+			*state, sl_llr_state_str(*state));
+
+out:
+	if (sl_ctrl_llr_put(ctrl_llr))
+		sl_ctrl_log_dbg(NULL, LOG_NAME,
+				"state get - llr removed (ctrl_llr = 0x%p)", ctrl_llr);
+
+	return rtn;
+}
+
+int sl_ctrl_llr_info_map_get(u8 ldev_num, u8 lgrp_num, u8 llr_num, u64 *info_map)
+{
+	int                 rtn;
+	struct sl_ctrl_llr *ctrl_llr;
+
+	ctrl_llr = sl_ctrl_llr_get(ldev_num, lgrp_num, llr_num);
+	if (!ctrl_llr) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"info map get NULL llr (ldev_num = %u, lgrp_num = %u, llr_num = %u)",
+				ldev_num, lgrp_num, llr_num);
+		return -EBADRQC;
+	}
+
+	if (!sl_ctrl_llr_kref_get_unless_zero(ctrl_llr)) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"info map get kref_get_unless_zero failed (ctrl_llr = 0x%p)", ctrl_llr);
+		return -EBADRQC;
+	}
+
+	rtn = sl_core_data_llr_info_map_get(sl_core_llr_get(ldev_num, lgrp_num, llr_num), info_map);
+	if (rtn) {
+		sl_ctrl_log_err_trace(ctrl_llr, LOG_NAME, "core_data_llr_info_map_get failed [%d]", rtn);
+		goto out;
+	}
+
+	sl_ctrl_log_dbg(ctrl_llr, LOG_NAME, "info map get (info_map = 0x%llX)", *info_map);
+
+out:
+	if (sl_ctrl_llr_put(ctrl_llr))
+		sl_ctrl_log_dbg(NULL, LOG_NAME,
+				"info map get - llr removed (ctrl_llr = 0x%p)", ctrl_llr);
+
+	return rtn;
+}
diff --git a/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_llr_counters.c b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_llr_counters.c
new file mode 100644
index 000000000000..81af580d3837
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_llr_counters.c
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/slab.h>
+#include <linux/atomic.h>
+#include <linux/types.h>
+
+#include "sl_ctrl_llr.h"
+#include "sl_ctrl_llr_counters.h"
+#include "base/sl_ctrl_log.h"
+
+#define LOG_NAME SL_CTRL_LLR_LOG_NAME
+
+#define SL_CTRL_LLR_COUNTER_INIT(_llr, _counter) \
+	(_llr)->counters[_counter].name = #_counter
+
+#define SL_CTRL_LLR_CAUSE_COUNTER_INIT(_llr, _counter) \
+	(_llr)->cause_counters[_counter].name = #_counter
+
+#define SL_CTRL_LLR_CAUSE_COUNTER_INC(_llr, _counter) \
+	atomic_inc(&(_llr)->cause_counters[_counter].count)
+
+int sl_ctrl_llr_counters_init(struct sl_ctrl_llr *ctrl_llr)
+{
+	sl_ctrl_log_dbg(ctrl_llr, LOG_NAME, "llr counters init");
+
+	ctrl_llr->counters = kzalloc(sizeof(*ctrl_llr->counters) * SL_CTRL_LLR_COUNTERS_COUNT, GFP_KERNEL);
+	if (!ctrl_llr->counters)
+		return -ENOMEM;
+
+	SL_CTRL_LLR_COUNTER_INIT(ctrl_llr, LLR_SETUP_CMD);
+	SL_CTRL_LLR_COUNTER_INIT(ctrl_llr, LLR_SETUP);
+	SL_CTRL_LLR_COUNTER_INIT(ctrl_llr, LLR_SETUP_TIMEOUT);
+	SL_CTRL_LLR_COUNTER_INIT(ctrl_llr, LLR_SETUP_FAIL);
+
+	SL_CTRL_LLR_COUNTER_INIT(ctrl_llr, LLR_CONFIGURED);
+
+	SL_CTRL_LLR_COUNTER_INIT(ctrl_llr, LLR_START_CMD);
+	SL_CTRL_LLR_COUNTER_INIT(ctrl_llr, LLR_RUNNING);
+	SL_CTRL_LLR_COUNTER_INIT(ctrl_llr, LLR_START_TIMEOUT);
+	SL_CTRL_LLR_COUNTER_INIT(ctrl_llr, LLR_START_FAIL);
+
+	SL_CTRL_LLR_COUNTER_INIT(ctrl_llr, LLR_STOP_CMD);
+	SL_CTRL_LLR_COUNTER_INIT(ctrl_llr, LLR_STOP_FAIL);
+
+	return 0;
+}
+
+int sl_ctrl_llr_cause_counters_init(struct sl_ctrl_llr *ctrl_llr)
+{
+	sl_ctrl_log_dbg(ctrl_llr, LOG_NAME, "llr cause counters init");
+
+	ctrl_llr->cause_counters = kzalloc(sizeof(*ctrl_llr->cause_counters) *
+					   SL_CTRL_LLR_CAUSE_COUNTERS_COUNT, GFP_KERNEL);
+	if (!ctrl_llr->cause_counters)
+		return -ENOMEM;
+
+	SL_CTRL_LLR_CAUSE_COUNTER_INIT(ctrl_llr, LLR_CAUSE_SETUP_CONFIG);
+	SL_CTRL_LLR_CAUSE_COUNTER_INIT(ctrl_llr, LLR_CAUSE_SETUP_INTR_ENABLE);
+	SL_CTRL_LLR_CAUSE_COUNTER_INIT(ctrl_llr, LLR_CAUSE_SETUP_TIMEOUT);
+	SL_CTRL_LLR_CAUSE_COUNTER_INIT(ctrl_llr, LLR_CAUSE_START_INTR_ENABLE);
+	SL_CTRL_LLR_CAUSE_COUNTER_INIT(ctrl_llr, LLR_CAUSE_START_TIMEOUT);
+	SL_CTRL_LLR_CAUSE_COUNTER_INIT(ctrl_llr, LLR_CAUSE_COMMAND);
+	SL_CTRL_LLR_CAUSE_COUNTER_INIT(ctrl_llr, LLR_CAUSE_CANCELED);
+
+	return 0;
+}
+
+int sl_ctrl_llr_counter_get(struct sl_ctrl_llr *ctrl_llr, u32 counter, int *count)
+{
+	*count = atomic_read(&ctrl_llr->counters[counter].count);
+
+	sl_ctrl_log_dbg(ctrl_llr, LOG_NAME, "get (counter = %u %s, count = %d)", counter,
+			ctrl_llr->counters[counter].name, *count);
+
+	return 0;
+}
+
+int sl_ctrl_llr_cause_counter_get(struct sl_ctrl_llr *ctrl_llr, u32 counter, int *count)
+{
+	*count = atomic_read(&ctrl_llr->cause_counters[counter].count);
+
+	sl_ctrl_log_dbg(ctrl_llr, LOG_NAME, "get (cause counter = %u %s, count = %d)", counter,
+			ctrl_llr->cause_counters[counter].name, *count);
+
+	return 0;
+}
+
+void sl_ctrl_llr_counters_del(struct sl_ctrl_llr *ctrl_llr)
+{
+	kfree(ctrl_llr->counters);
+}
+
+void sl_ctrl_llr_cause_counters_del(struct sl_ctrl_llr *ctrl_llr)
+{
+	kfree(ctrl_llr->cause_counters);
+}
+
+void sl_ctrl_llr_cause_counters_inc(struct sl_ctrl_llr *ctrl_llr, unsigned long cause_map)
+{
+	unsigned long which;
+
+	sl_ctrl_log_dbg(ctrl_llr, LOG_NAME, "llr cause counter inc");
+
+	BUILD_BUG_ON(SL_CTRL_LLR_CAUSE_COUNTERS_COUNT > 32);
+
+	for_each_set_bit(which, &cause_map, sizeof(cause_map) * BITS_PER_BYTE) {
+		switch (BIT(which)) {
+		case SL_LLR_FAIL_CAUSE_SETUP_CONFIG:
+			SL_CTRL_LLR_CAUSE_COUNTER_INC(ctrl_llr, LLR_CAUSE_SETUP_CONFIG);
+			break;
+		case SL_LLR_FAIL_CAUSE_SETUP_INTR_ENABLE:
+			SL_CTRL_LLR_CAUSE_COUNTER_INC(ctrl_llr, LLR_CAUSE_SETUP_INTR_ENABLE);
+			break;
+		case SL_LLR_FAIL_CAUSE_SETUP_TIMEOUT:
+			SL_CTRL_LLR_CAUSE_COUNTER_INC(ctrl_llr, LLR_CAUSE_SETUP_TIMEOUT);
+			break;
+		case SL_LLR_FAIL_CAUSE_START_INTR_ENABLE:
+			SL_CTRL_LLR_CAUSE_COUNTER_INC(ctrl_llr, LLR_CAUSE_START_INTR_ENABLE);
+			break;
+		case SL_LLR_FAIL_CAUSE_START_TIMEOUT:
+			SL_CTRL_LLR_CAUSE_COUNTER_INC(ctrl_llr, LLR_CAUSE_START_TIMEOUT);
+			break;
+		case SL_LLR_FAIL_CAUSE_COMMAND:
+			SL_CTRL_LLR_CAUSE_COUNTER_INC(ctrl_llr, LLR_CAUSE_COMMAND);
+			break;
+		case SL_LLR_FAIL_CAUSE_CANCELED:
+			SL_CTRL_LLR_CAUSE_COUNTER_INC(ctrl_llr, LLR_CAUSE_CANCELED);
+			break;
+		default:
+			sl_ctrl_log_warn_trace(ctrl_llr, LOG_NAME,
+					       "cause_counter_inc unknown cause (bit = %lu)", which);
+			break;
+		}
+	}
+}
diff --git a/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_mac.c b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_mac.c
new file mode 100644
index 000000000000..a4202757d238
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_mac.c
@@ -0,0 +1,536 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kobject.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+#include <linux/slab.h>
+
+#include <linux/hpe/sl/sl_mac.h>
+
+#include "sl_asic.h"
+#include "sl_sysfs.h"
+#include "base/sl_ctrl_log.h"
+#include "sl_ctrl_ldev.h"
+#include "sl_ctrl_lgrp.h"
+#include "sl_ctrl_mac.h"
+#include "sl_core_mac.h"
+#include "sl_ctrl_mac_counters.h"
+
+#define SL_CTRL_MAC_DEL_WAIT_TIMEOUT_MS 2000
+
+#define LOG_NAME SL_CTRL_MAC_LOG_NAME
+
+static struct sl_ctrl_mac *ctrl_macs[SL_ASIC_MAX_LDEVS][SL_ASIC_MAX_LGRPS][SL_ASIC_MAX_LINKS];
+static DEFINE_SPINLOCK(ctrl_macs_lock);
+
+int sl_ctrl_mac_new(u8 ldev_num, u8 lgrp_num, u8 mac_num, struct kobject *sysfs_parent)
+{
+	int                 rtn;
+	struct sl_ctrl_mac *ctrl_mac;
+
+	ctrl_mac = sl_ctrl_mac_get(ldev_num, lgrp_num, mac_num);
+	if (ctrl_mac) {
+		sl_ctrl_log_err(NULL, LOG_NAME, "exists (mac = 0x%p)", ctrl_mac);
+		return -EBADRQC;
+	}
+
+	ctrl_mac = kzalloc(sizeof(*ctrl_mac), GFP_KERNEL);
+	if (!ctrl_mac)
+		return -ENOMEM;
+
+	ctrl_mac->magic     = SL_CTRL_MAC_MAGIC;
+	ctrl_mac->ver       = SL_CTRL_MAC_VER;
+	ctrl_mac->num       = mac_num;
+	ctrl_mac->ctrl_lgrp = sl_ctrl_lgrp_get(ldev_num, lgrp_num);
+	if (!ctrl_mac->ctrl_lgrp) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"new NULL lgrp (ldev_num = %u, lgrp_num = %u)", ldev_num, lgrp_num);
+		kfree(ctrl_mac);
+		return -EBADRQC;
+	}
+
+	kref_init(&ctrl_mac->ref_cnt);
+	kref_init(&ctrl_mac->mem_ref);
+	init_completion(&ctrl_mac->del_complete);
+
+	spin_lock_init(&ctrl_mac->data_lock);
+
+	rtn = sl_ctrl_mac_counters_init(ctrl_mac);
+	if (rtn) {
+		sl_ctrl_log_err_trace(ctrl_mac, LOG_NAME, "ctrl_mac_counters_init failed [%d]", rtn);
+		goto out;
+	}
+
+	rtn = sl_core_mac_new(ldev_num, lgrp_num, mac_num);
+	if (rtn) {
+		sl_ctrl_log_err_trace(ctrl_mac, LOG_NAME, "core_mac_new failed [%d]", rtn);
+		goto out_counters;
+	}
+
+	if (sysfs_parent) {
+		ctrl_mac->parent_kobj = sysfs_parent;
+
+		rtn = sl_sysfs_mac_create(ctrl_mac);
+		if (rtn) {
+			sl_ctrl_log_err_trace(ctrl_mac, LOG_NAME, "sysfs_mac_create failed [%d]", rtn);
+			goto out_mac_new;
+		}
+	}
+
+	sl_ctrl_log_dbg(ctrl_mac, LOG_NAME, "new (mac = 0x%p)", ctrl_mac);
+
+	spin_lock(&ctrl_macs_lock);
+	ctrl_macs[ldev_num][lgrp_num][mac_num] = ctrl_mac;
+	spin_unlock(&ctrl_macs_lock);
+
+	return 0;
+
+out_mac_new:
+	sl_core_mac_del(ldev_num, lgrp_num, mac_num);
+out_counters:
+	sl_ctrl_mac_counters_del(ctrl_mac);
+out:
+	kfree(ctrl_mac);
+	return rtn;
+}
+
+static void sl_ctrl_mac_free(struct kref *kref)
+{
+	kfree(container_of(kref, struct sl_ctrl_mac, mem_ref));
+}
+
+static void sl_ctrl_mac_release(struct kref *kref)
+{
+	struct sl_ctrl_mac *ctrl_mac;
+	u8                  ldev_num;
+	u8                  lgrp_num;
+	u8                  mac_num;
+
+	ctrl_mac = container_of(kref, struct sl_ctrl_mac, ref_cnt);
+	ldev_num = ctrl_mac->ctrl_lgrp->ctrl_ldev->num;
+	lgrp_num = ctrl_mac->ctrl_lgrp->num;
+	mac_num  = ctrl_mac->num;
+
+	sl_ctrl_log_dbg(ctrl_mac, LOG_NAME, "release (ctrl_mac = 0x%p)", ctrl_mac);
+
+	/* Must delete sysfs first to guarantee nobody is reading */
+	sl_sysfs_mac_delete(ctrl_mac);
+
+	sl_core_mac_del(ldev_num, lgrp_num, mac_num);
+
+	sl_ctrl_mac_counters_del(ctrl_mac);
+
+	spin_lock(&ctrl_macs_lock);
+	ctrl_macs[ldev_num][lgrp_num][mac_num] = NULL;
+	spin_unlock(&ctrl_macs_lock);
+
+	/*
+	 * Wake a waiting sl_ctrl_mac_del(). The memory is not freed here:
+	 * the waiter still uses del_complete and ctrl_mac after it wakes,
+	 * and holds mem_ref until it is done. The last holder frees it.
+	 */
+	complete_all(&ctrl_mac->del_complete);
+	kref_put(&ctrl_mac->mem_ref, sl_ctrl_mac_free);
+}
+
+static int sl_ctrl_mac_put(struct sl_ctrl_mac *ctrl_mac)
+{
+	return kref_put(&ctrl_mac->ref_cnt, sl_ctrl_mac_release);
+}
+
+int sl_ctrl_mac_del(u8 ldev_num, u8 lgrp_num, u8 mac_num)
+{
+	struct sl_ctrl_mac *ctrl_mac;
+	unsigned long       timeleft;
+	int                 rtn = 0;
+
+	sl_ctrl_log_dbg(NULL, LOG_NAME, "del (ldev_num = %u, lgrp_num = %u, mac_num = %u)",
+			ldev_num, lgrp_num, mac_num);
+
+	ctrl_mac = sl_ctrl_mac_get(ldev_num, lgrp_num, mac_num);
+	if (!ctrl_mac) {
+		sl_ctrl_log_err_trace(NULL, LOG_NAME,
+				      "mac not found (ldev_num = %u, lgrp_num = %u, mac_num = %u)",
+				      ldev_num, lgrp_num, mac_num);
+		return -EBADRQC;
+	}
+
+	/*
+	 * Keep the memory, and with it del_complete, valid until we are done
+	 * waiting: the release may run on another thread and must not free it
+	 * under us.
+	 */
+	kref_get(&ctrl_mac->mem_ref);
+
+	/* Release occurs on the last caller. Block until complete. */
+	if (!sl_ctrl_mac_put(ctrl_mac)) {
+		timeleft = wait_for_completion_timeout(&ctrl_mac->del_complete,
+						       msecs_to_jiffies(SL_CTRL_MAC_DEL_WAIT_TIMEOUT_MS));
+
+		sl_ctrl_log_dbg(NULL, LOG_NAME,
+				"del completion_timeout (timeleft = %lums)", timeleft);
+
+		if (timeleft == 0) {
+			sl_ctrl_log_err(NULL, LOG_NAME,
+					"del completion_timeout (ctrl_mac = 0x%p)", ctrl_mac);
+			rtn = -ETIMEDOUT;
+		}
+	}
+
+	kref_put(&ctrl_mac->mem_ref, sl_ctrl_mac_free);
+
+	return rtn;
+}
+
+static bool sl_ctrl_mac_kref_get_unless_zero(struct sl_ctrl_mac *ctrl_mac)
+{
+	return (kref_get_unless_zero(&ctrl_mac->ref_cnt) != 0);
+}
+
+struct sl_ctrl_mac *sl_ctrl_mac_get(u8 ldev_num, u8 lgrp_num, u8 mac_num)
+{
+	struct sl_ctrl_mac *ctrl_mac;
+
+	spin_lock(&ctrl_macs_lock);
+	ctrl_mac = ctrl_macs[ldev_num][lgrp_num][mac_num];
+	spin_unlock(&ctrl_macs_lock);
+
+	sl_ctrl_log_dbg(NULL, LOG_NAME,
+			"get (ldev_num = %u, lgrp_num = %u, mac_num = %u, mac = 0x%p)",
+			ldev_num, lgrp_num, mac_num, ctrl_mac);
+
+	return ctrl_mac;
+}
+
+int sl_ctrl_mac_tx_start(u8 ldev_num, u8 lgrp_num, u8 mac_num)
+{
+	int                rtn;
+	struct sl_ctrl_mac *ctrl_mac;
+
+	ctrl_mac = sl_ctrl_mac_get(ldev_num, lgrp_num, mac_num);
+	if (!ctrl_mac) {
+		sl_ctrl_log_err(NULL, LOG_NAME, "tx start - NULL mac");
+		return -EBADRQC;
+	}
+
+	if (!sl_ctrl_mac_kref_get_unless_zero(ctrl_mac)) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"tx start - kref unavailable (ctrl_mac = 0x%p)", ctrl_mac);
+		return -EBADRQC;
+	}
+
+	sl_ctrl_log_dbg(ctrl_mac, LOG_NAME, "tx start");
+
+	SL_CTRL_MAC_COUNTER_INC(ctrl_mac, MAC_TX_START_CMD);
+
+	rtn = sl_core_mac_tx_start(ldev_num, lgrp_num, mac_num);
+	if (rtn) {
+		sl_ctrl_log_err_trace(ctrl_mac, LOG_NAME, "tx start - core_mac_tx_start failed [%d]", rtn);
+		SL_CTRL_MAC_COUNTER_INC(ctrl_mac, MAC_TX_START_FAIL);
+		goto out;
+	}
+
+	SL_CTRL_MAC_COUNTER_INC(ctrl_mac, MAC_TX_STARTED);
+
+	rtn = 0;
+
+out:
+	if (sl_ctrl_mac_put(ctrl_mac))
+		sl_ctrl_log_dbg(NULL, LOG_NAME,
+				"tx start - mac removed (ctrl_mac = 0x%p)", ctrl_mac);
+
+	return rtn;
+}
+
+int sl_ctrl_mac_tx_stop(u8 ldev_num, u8 lgrp_num, u8 mac_num)
+{
+	int                rtn;
+	struct sl_ctrl_mac *ctrl_mac;
+
+	ctrl_mac = sl_ctrl_mac_get(ldev_num, lgrp_num, mac_num);
+	if (!ctrl_mac) {
+		sl_ctrl_log_dbg(NULL, LOG_NAME, "tx stop - NULL mac");
+		return 0;
+	}
+
+	if (!sl_ctrl_mac_kref_get_unless_zero(ctrl_mac)) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"tx stop - kref unavailable (ctrl_mac = 0x%p)", ctrl_mac);
+		return -EBADRQC;
+	}
+
+	sl_ctrl_log_dbg(ctrl_mac, LOG_NAME, "tx stop");
+
+	SL_CTRL_MAC_COUNTER_INC(ctrl_mac, MAC_TX_STOP_CMD);
+
+	rtn = sl_core_mac_tx_stop(ldev_num, lgrp_num, mac_num);
+	if (rtn) {
+		sl_ctrl_log_err_trace(ctrl_mac, LOG_NAME, "tx stop - core_mac_tx_stop failed [%d]", rtn);
+		SL_CTRL_MAC_COUNTER_INC(ctrl_mac, MAC_TX_STOP_FAIL);
+		goto out;
+	}
+
+	SL_CTRL_MAC_COUNTER_INC(ctrl_mac, MAC_TX_STOPPED);
+
+	rtn = 0;
+
+out:
+	if (sl_ctrl_mac_put(ctrl_mac))
+		sl_ctrl_log_dbg(NULL, LOG_NAME,
+				"tx stop - mac removed (ctrl_mac = 0x%p)", ctrl_mac);
+
+	return rtn;
+}
+
+int sl_ctrl_mac_tx_state_get(u8 ldev_num, u8 lgrp_num, u8 mac_num, u32 *state)
+{
+	int                rtn;
+	struct sl_ctrl_mac *ctrl_mac;
+	u32                core_mac_state;
+
+	ctrl_mac = sl_ctrl_mac_get(ldev_num, lgrp_num, mac_num);
+	if (!ctrl_mac) {
+		sl_ctrl_log_dbg(NULL, LOG_NAME, "tx state get - NULL mac");
+		*state = SL_MAC_STATE_OFF;
+		return 0;
+	}
+
+	if (!sl_ctrl_mac_kref_get_unless_zero(ctrl_mac)) {
+		sl_ctrl_log_dbg(NULL, LOG_NAME,
+				"tx state get - kref unavailable (ctrl_mac = 0x%p)", ctrl_mac);
+		*state = SL_MAC_STATE_OFF;
+		return 0;
+	}
+
+	rtn = sl_core_mac_tx_state_get(ldev_num, lgrp_num, mac_num, &core_mac_state);
+	if (rtn) {
+		sl_ctrl_log_dbg(ctrl_mac, LOG_NAME, "tx state get - core_mac_tx_state_get failed [%d]", rtn);
+		*state = SL_MAC_STATE_OFF;
+		goto out;
+	}
+
+	switch (core_mac_state) {
+	case SL_CORE_MAC_STATE_ON:
+		*state = SL_MAC_STATE_ON;
+		break;
+	default:
+		*state = SL_MAC_STATE_OFF;
+		break;
+	}
+
+	sl_ctrl_log_dbg(ctrl_mac, LOG_NAME, "tx state get (state = %u %s, core_state = %u)",
+			*state, sl_mac_state_str(*state), core_mac_state);
+
+out:
+	if (sl_ctrl_mac_put(ctrl_mac))
+		sl_ctrl_log_dbg(NULL, LOG_NAME,
+				"tx state get - mac removed (ctrl_mac = 0x%p)", ctrl_mac);
+
+	return 0;
+}
+
+int sl_ctrl_mac_rx_start(u8 ldev_num, u8 lgrp_num, u8 mac_num)
+{
+	int                rtn;
+	struct sl_ctrl_mac *ctrl_mac;
+
+	ctrl_mac = sl_ctrl_mac_get(ldev_num, lgrp_num, mac_num);
+	if (!ctrl_mac) {
+		sl_ctrl_log_err(NULL, LOG_NAME, "rx start - NULL mac");
+		return -EBADRQC;
+	}
+
+	if (!sl_ctrl_mac_kref_get_unless_zero(ctrl_mac)) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"rx start - kref unavailable (ctrl_mac = 0x%p)", ctrl_mac);
+		return -EBADRQC;
+	}
+
+	sl_ctrl_log_dbg(ctrl_mac, LOG_NAME, "rx start");
+
+	SL_CTRL_MAC_COUNTER_INC(ctrl_mac, MAC_RX_START_CMD);
+
+	rtn = sl_core_mac_rx_start(ldev_num, lgrp_num, mac_num);
+	if (rtn) {
+		sl_ctrl_log_err_trace(ctrl_mac, LOG_NAME, "rx start - core_mac_rx_start failed [%d]", rtn);
+		SL_CTRL_MAC_COUNTER_INC(ctrl_mac, MAC_RX_START_FAIL);
+		goto out;
+	}
+
+	SL_CTRL_MAC_COUNTER_INC(ctrl_mac, MAC_RX_STARTED);
+
+	rtn = 0;
+
+out:
+
+	if (sl_ctrl_mac_put(ctrl_mac))
+		sl_ctrl_log_dbg(NULL, LOG_NAME,
+				"rx start - mac removed (ctrl_mac = 0x%p)", ctrl_mac);
+
+	return rtn;
+}
+
+int sl_ctrl_mac_rx_stop(u8 ldev_num, u8 lgrp_num, u8 mac_num)
+{
+	int                rtn;
+	struct sl_ctrl_mac *ctrl_mac;
+
+	ctrl_mac = sl_ctrl_mac_get(ldev_num, lgrp_num, mac_num);
+	if (!ctrl_mac) {
+		sl_ctrl_log_dbg(NULL, LOG_NAME, "rx stop - NULL mac");
+		return 0;
+	}
+
+	if (!sl_ctrl_mac_kref_get_unless_zero(ctrl_mac)) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"rx stop - kref unavailable (ctrl_mac = 0x%p)", ctrl_mac);
+		return -EBADRQC;
+	}
+
+	sl_ctrl_log_dbg(ctrl_mac, LOG_NAME, "rx stop");
+
+	SL_CTRL_MAC_COUNTER_INC(ctrl_mac, MAC_RX_STOP_CMD);
+
+	rtn = sl_core_mac_rx_stop(ldev_num, lgrp_num, mac_num);
+	if (rtn) {
+		sl_ctrl_log_err_trace(ctrl_mac, LOG_NAME, "rx stop - core_mac_rx_stop failed [%d]", rtn);
+		SL_CTRL_MAC_COUNTER_INC(ctrl_mac, MAC_RX_STOP_FAIL);
+		goto out;
+	}
+
+	SL_CTRL_MAC_COUNTER_INC(ctrl_mac, MAC_RX_STOPPED);
+
+	rtn = 0;
+
+out:
+
+	sl_ctrl_mac_put(ctrl_mac);
+
+	return rtn;
+}
+
+int sl_ctrl_mac_rx_state_get(u8 ldev_num, u8 lgrp_num, u8 mac_num, u32 *state)
+{
+	int                rtn;
+	struct sl_ctrl_mac *ctrl_mac;
+	u32                core_mac_state;
+
+	ctrl_mac = sl_ctrl_mac_get(ldev_num, lgrp_num, mac_num);
+	if (!ctrl_mac) {
+		sl_ctrl_log_dbg(NULL, LOG_NAME, "rx state get - NULL mac");
+		*state = SL_MAC_STATE_OFF;
+		return 0;
+	}
+
+	if (!sl_ctrl_mac_kref_get_unless_zero(ctrl_mac)) {
+		sl_ctrl_log_dbg(NULL, LOG_NAME,
+				"rx state get - kref unavailable (ctrl_mac = 0x%p)", ctrl_mac);
+		*state = SL_MAC_STATE_OFF;
+		return 0;
+	}
+
+	rtn = sl_core_mac_rx_state_get(ldev_num, lgrp_num, mac_num, &core_mac_state);
+	if (rtn) {
+		sl_ctrl_log_dbg(ctrl_mac, LOG_NAME, "rx state get - core_mac_rx_state_get failed [%d]", rtn);
+		*state = SL_MAC_STATE_OFF;
+		goto out;
+	}
+
+	switch (core_mac_state) {
+	case SL_CORE_MAC_STATE_ON:
+		*state = SL_MAC_STATE_ON;
+		break;
+	default:
+		*state = SL_MAC_STATE_OFF;
+		break;
+	}
+
+	sl_ctrl_log_dbg(ctrl_mac, LOG_NAME, "rx state get (state = %u %s, core_state = %u)",
+			*state, sl_mac_state_str(*state), core_mac_state);
+
+out:
+
+	if (sl_ctrl_mac_put(ctrl_mac))
+		sl_ctrl_log_dbg(NULL, LOG_NAME,
+				"rx state get - mac removed (ctrl_mac = 0x%p)", ctrl_mac);
+
+	return 0;
+}
+
+int sl_ctrl_mac_reset(u8 ldev_num, u8 lgrp_num, u8 mac_num)
+{
+	int                tx_rtn;
+	int                rx_rtn;
+	int                rtn = 0;
+	struct sl_ctrl_mac *ctrl_mac;
+
+	ctrl_mac = sl_ctrl_mac_get(ldev_num, lgrp_num, mac_num);
+	if (!ctrl_mac) {
+		sl_ctrl_log_dbg(NULL, LOG_NAME, "reset - NULL mac");
+		return 0;
+	}
+
+	if (!sl_ctrl_mac_kref_get_unless_zero(ctrl_mac)) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"reset - kref unavailable (ctrl_mac = 0x%p)", ctrl_mac);
+		return -EBADRQC;
+	}
+
+	sl_ctrl_log_dbg(ctrl_mac, LOG_NAME, "reset");
+
+	SL_CTRL_MAC_COUNTER_INC(ctrl_mac, MAC_RESET_CMD);
+
+	tx_rtn = sl_core_mac_tx_stop(ldev_num, lgrp_num, mac_num);
+	if (tx_rtn) {
+		/* Log error, but allow the function to continue to mac rx stop */
+		sl_ctrl_log_err_trace(ctrl_mac, LOG_NAME, "reset - core_mac_tx_stop failed [%d]", tx_rtn);
+	}
+
+	rx_rtn = sl_core_mac_rx_stop(ldev_num, lgrp_num, mac_num);
+	if (rx_rtn) {
+		/* Log error, but allow the function to continue execution */
+		sl_ctrl_log_err_trace(ctrl_mac, LOG_NAME, "core_mac_rx_stop failed [%d]", rx_rtn);
+	}
+
+	if (tx_rtn && rx_rtn) {
+		SL_CTRL_MAC_COUNTER_INC(ctrl_mac, MAC_RESET_FAIL);
+		rtn = -EIO;
+	} else {
+		SL_CTRL_MAC_COUNTER_INC(ctrl_mac, MAC_RESET);
+	}
+
+	sl_ctrl_mac_put(ctrl_mac);
+
+	return rtn;
+}
+
+int sl_ctrl_mac_info_map_get(u8 ldev_num, u8 lgrp_num, u8 mac_num, u64 *info_map)
+{
+	struct sl_ctrl_mac *ctrl_mac;
+
+	ctrl_mac = sl_ctrl_mac_get(ldev_num, lgrp_num, mac_num);
+	if (!ctrl_mac) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"info map get NULL mac (ldev_num = %u, lgrp_num = %u, mac_num = %u)",
+				ldev_num, lgrp_num, mac_num);
+		return -EBADRQC;
+	}
+
+	if (!sl_ctrl_mac_kref_get_unless_zero(ctrl_mac)) {
+		sl_ctrl_log_err(NULL, LOG_NAME,
+				"info map get kref_get_unless_zero failed (ctrl_mac = 0x%p)",
+				ctrl_mac);
+		return -EBADRQC;
+	}
+
+	*info_map = sl_core_mac_info_map_get(ldev_num, lgrp_num, mac_num);
+
+	sl_ctrl_log_dbg(ctrl_mac, LOG_NAME, "info map get (info_map = 0x%llX)", *info_map);
+
+	if (sl_ctrl_mac_put(ctrl_mac))
+		sl_ctrl_log_dbg(NULL, LOG_NAME,
+				"info map get - mac removed (ctrl_mac = 0x%p)", ctrl_mac);
+
+	return 0;
+}
diff --git a/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_mac_counters.c b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_mac_counters.c
new file mode 100644
index 000000000000..a30e64f80122
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_mac_counters.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2025-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/slab.h>
+#include <linux/atomic.h>
+#include <linux/types.h>
+
+#include "sl_ctrl_mac.h"
+#include "sl_ctrl_mac_counters.h"
+
+#define SL_CTRL_MAC_COUNTER_INIT(_mac, _counter) \
+	(_mac)->counters[_counter].name = #_counter
+
+int sl_ctrl_mac_counters_init(struct sl_ctrl_mac *ctrl_mac)
+{
+	if (ctrl_mac->counters)
+		return -EALREADY;
+
+	ctrl_mac->counters = kzalloc(sizeof(*ctrl_mac->counters) * SL_CTRL_MAC_COUNTERS_COUNT, GFP_KERNEL);
+	if (!ctrl_mac->counters)
+		return -ENOMEM;
+
+	SL_CTRL_MAC_COUNTER_INIT(ctrl_mac, MAC_TX_START_CMD);
+	SL_CTRL_MAC_COUNTER_INIT(ctrl_mac, MAC_TX_STARTED);
+	SL_CTRL_MAC_COUNTER_INIT(ctrl_mac, MAC_TX_START_FAIL);
+
+	SL_CTRL_MAC_COUNTER_INIT(ctrl_mac, MAC_TX_STOP_CMD);
+	SL_CTRL_MAC_COUNTER_INIT(ctrl_mac, MAC_TX_STOPPED);
+	SL_CTRL_MAC_COUNTER_INIT(ctrl_mac, MAC_TX_STOP_FAIL);
+
+	SL_CTRL_MAC_COUNTER_INIT(ctrl_mac, MAC_RX_START_CMD);
+	SL_CTRL_MAC_COUNTER_INIT(ctrl_mac, MAC_RX_STARTED);
+	SL_CTRL_MAC_COUNTER_INIT(ctrl_mac, MAC_RX_START_FAIL);
+
+	SL_CTRL_MAC_COUNTER_INIT(ctrl_mac, MAC_RX_STOP_CMD);
+	SL_CTRL_MAC_COUNTER_INIT(ctrl_mac, MAC_RX_STOPPED);
+	SL_CTRL_MAC_COUNTER_INIT(ctrl_mac, MAC_RX_STOP_FAIL);
+
+	SL_CTRL_MAC_COUNTER_INIT(ctrl_mac, MAC_RESET_CMD);
+	SL_CTRL_MAC_COUNTER_INIT(ctrl_mac, MAC_RESET);
+	SL_CTRL_MAC_COUNTER_INIT(ctrl_mac, MAC_RESET_FAIL);
+
+	return 0;
+}
+
+int sl_ctrl_mac_counter_get(struct sl_ctrl_mac *ctrl_mac, u32 counter, int *count)
+{
+	*count = atomic_read(&ctrl_mac->counters[counter].count);
+
+	return 0;
+}
+
+void sl_ctrl_mac_counters_del(struct sl_ctrl_mac *ctrl_mac)
+{
+	kfree(ctrl_mac->counters);
+}
diff --git a/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_media_counters.c b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_media_counters.c
new file mode 100644
index 000000000000..0f12a479d017
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/ctrl/sl_ctrl_media_counters.c
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2025,2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/slab.h>
+#include <linux/atomic.h>
+#include <linux/types.h>
+
+#include "sl_media_jack.h"
+#include "sl_ctrl_media_counters.h"
+#include "base/sl_ctrl_log.h"
+
+#define LOG_NAME SL_CTRL_MEDIA_LOG_NAME
+
+#define SL_CTRL_MEDIA_CAUSE_COUNTER_INIT(_media, _counter) \
+	(_media)->cause_counters[_counter].name = #_counter
+
+int sl_ctrl_media_cause_counters_init(struct sl_media_jack *media_jack)
+{
+	sl_ctrl_log_dbg(media_jack, LOG_NAME, "media cause counters init");
+
+	media_jack->cause_counters = kzalloc(sizeof(*media_jack->cause_counters) *
+					     SL_CTRL_MEDIA_CAUSE_COUNTERS_COUNT, GFP_KERNEL);
+	if (!media_jack->cause_counters)
+		return -ENOMEM;
+
+	SL_CTRL_MEDIA_CAUSE_COUNTER_INIT(media_jack, MEDIA_CAUSE_EEPROM_FORMAT_UNSUPPORTED);
+	SL_CTRL_MEDIA_CAUSE_COUNTER_INIT(media_jack, MEDIA_CAUSE_EEPROM_VENDOR_UNSUPPORTED);
+	SL_CTRL_MEDIA_CAUSE_COUNTER_INIT(media_jack, MEDIA_CAUSE_EEPROM_JACK_IO);
+	SL_CTRL_MEDIA_CAUSE_COUNTER_INIT(media_jack, MEDIA_CAUSE_ONLINE_STATUS_GET);
+	SL_CTRL_MEDIA_CAUSE_COUNTER_INIT(media_jack, MEDIA_CAUSE_ONLINE_TIMEDOUT);
+	SL_CTRL_MEDIA_CAUSE_COUNTER_INIT(media_jack, MEDIA_CAUSE_ONLINE_JACK_IO);
+	SL_CTRL_MEDIA_CAUSE_COUNTER_INIT(media_jack, MEDIA_CAUSE_ONLINE_JACK_GET);
+	SL_CTRL_MEDIA_CAUSE_COUNTER_INIT(media_jack, MEDIA_CAUSE_SERDES_SETTINGS_GET);
+	SL_CTRL_MEDIA_CAUSE_COUNTER_INIT(media_jack, MEDIA_CAUSE_SCAN_STATUS_GET);
+	SL_CTRL_MEDIA_CAUSE_COUNTER_INIT(media_jack, MEDIA_CAUSE_SCAN_HDL_GET);
+	SL_CTRL_MEDIA_CAUSE_COUNTER_INIT(media_jack, MEDIA_CAUSE_SCAN_JACK_GET);
+	SL_CTRL_MEDIA_CAUSE_COUNTER_INIT(media_jack, MEDIA_CAUSE_MEDIA_ATTR_SET);
+	SL_CTRL_MEDIA_CAUSE_COUNTER_INIT(media_jack, MEDIA_CAUSE_INTR_EVENT_JACK_IO);
+	SL_CTRL_MEDIA_CAUSE_COUNTER_INIT(media_jack, MEDIA_CAUSE_POWER_SET);
+	SL_CTRL_MEDIA_CAUSE_COUNTER_INIT(media_jack, MEDIA_CAUSE_SHIFT_DOWN_JACK_IO);
+	SL_CTRL_MEDIA_CAUSE_COUNTER_INIT(media_jack, MEDIA_CAUSE_SHIFT_DOWN_JACK_IO_LOW_POWER_SET);
+	SL_CTRL_MEDIA_CAUSE_COUNTER_INIT(media_jack, MEDIA_CAUSE_SHIFT_DOWN_JACK_IO_HIGH_POWER_SET);
+	SL_CTRL_MEDIA_CAUSE_COUNTER_INIT(media_jack, MEDIA_CAUSE_SHIFT_UP_JACK_IO);
+	SL_CTRL_MEDIA_CAUSE_COUNTER_INIT(media_jack, MEDIA_CAUSE_SHIFT_UP_JACK_IO_LOW_POWER_SET);
+	SL_CTRL_MEDIA_CAUSE_COUNTER_INIT(media_jack, MEDIA_CAUSE_SHIFT_UP_JACK_IO_HIGH_POWER_SET);
+	SL_CTRL_MEDIA_CAUSE_COUNTER_INIT(media_jack, MEDIA_CAUSE_SHIFT_STATE_JACK_IO);
+	SL_CTRL_MEDIA_CAUSE_COUNTER_INIT(media_jack, MEDIA_CAUSE_OFFLINE);
+	SL_CTRL_MEDIA_CAUSE_COUNTER_INIT(media_jack, MEDIA_CAUSE_HOT);
+	SL_CTRL_MEDIA_CAUSE_COUNTER_INIT(media_jack, MEDIA_CAUSE_WARM);
+
+	return 0;
+}
+
+int sl_ctrl_media_cause_counter_get(struct sl_media_jack *media_jack, u32 counter, int *count)
+{
+	*count = atomic_read(&media_jack->cause_counters[counter].count);
+
+	sl_ctrl_log_dbg(media_jack, LOG_NAME, "get (cause counter = %u %s, count = %d)", counter,
+			media_jack->cause_counters[counter].name, *count);
+
+	return 0;
+}
+
+void sl_ctrl_media_cause_counters_del(struct sl_media_jack *media_jack)
+{
+	kfree(media_jack->cause_counters);
+}
+
+void sl_ctrl_media_cause_counter_inc(struct sl_media_jack *media_jack, unsigned long cause_map)
+{
+	unsigned long which;
+
+	sl_ctrl_log_dbg(media_jack, LOG_NAME, "media cause counter inc");
+
+	BUILD_BUG_ON(SL_CTRL_MEDIA_CAUSE_COUNTERS_COUNT > 32);
+
+	for_each_set_bit(which, &cause_map, sizeof(cause_map) * BITS_PER_BYTE) {
+		switch (BIT(which)) {
+		case SL_MEDIA_FAULT_CAUSE_EEPROM_FORMAT_UNSUPPORTED:
+			SL_CTRL_MEDIA_CAUSE_COUNTER_INC(media_jack, MEDIA_CAUSE_EEPROM_FORMAT_UNSUPPORTED);
+			break;
+		case SL_MEDIA_FAULT_CAUSE_EEPROM_VENDOR_UNSUPPORTED:
+			SL_CTRL_MEDIA_CAUSE_COUNTER_INC(media_jack, MEDIA_CAUSE_EEPROM_VENDOR_UNSUPPORTED);
+			break;
+		case SL_MEDIA_FAULT_CAUSE_EEPROM_JACK_IO:
+			SL_CTRL_MEDIA_CAUSE_COUNTER_INC(media_jack, MEDIA_CAUSE_EEPROM_JACK_IO);
+			break;
+		case SL_MEDIA_FAULT_CAUSE_ONLINE_STATUS_GET:
+			SL_CTRL_MEDIA_CAUSE_COUNTER_INC(media_jack, MEDIA_CAUSE_ONLINE_STATUS_GET);
+			break;
+		case SL_MEDIA_FAULT_CAUSE_ONLINE_TIMEDOUT:
+			SL_CTRL_MEDIA_CAUSE_COUNTER_INC(media_jack, MEDIA_CAUSE_ONLINE_TIMEDOUT);
+			break;
+		case SL_MEDIA_FAULT_CAUSE_ONLINE_JACK_IO:
+			SL_CTRL_MEDIA_CAUSE_COUNTER_INC(media_jack, MEDIA_CAUSE_ONLINE_JACK_IO);
+			break;
+		case SL_MEDIA_FAULT_CAUSE_ONLINE_JACK_GET:
+			SL_CTRL_MEDIA_CAUSE_COUNTER_INC(media_jack, MEDIA_CAUSE_ONLINE_JACK_GET);
+			break;
+		case SL_MEDIA_FAULT_CAUSE_SERDES_SETTINGS_GET:
+			SL_CTRL_MEDIA_CAUSE_COUNTER_INC(media_jack, MEDIA_CAUSE_SERDES_SETTINGS_GET);
+			break;
+		case SL_MEDIA_FAULT_CAUSE_SCAN_STATUS_GET:
+			SL_CTRL_MEDIA_CAUSE_COUNTER_INC(media_jack, MEDIA_CAUSE_SCAN_STATUS_GET);
+			break;
+		case SL_MEDIA_FAULT_CAUSE_SCAN_HDL_GET:
+			SL_CTRL_MEDIA_CAUSE_COUNTER_INC(media_jack, MEDIA_CAUSE_SCAN_HDL_GET);
+			break;
+		case SL_MEDIA_FAULT_CAUSE_SCAN_JACK_GET:
+			SL_CTRL_MEDIA_CAUSE_COUNTER_INC(media_jack, MEDIA_CAUSE_SCAN_JACK_GET);
+			break;
+		case SL_MEDIA_FAULT_CAUSE_MEDIA_ATTR_SET:
+			SL_CTRL_MEDIA_CAUSE_COUNTER_INC(media_jack, MEDIA_CAUSE_MEDIA_ATTR_SET);
+			break;
+		case SL_MEDIA_FAULT_CAUSE_INTR_EVENT_JACK_IO:
+			SL_CTRL_MEDIA_CAUSE_COUNTER_INC(media_jack, MEDIA_CAUSE_INTR_EVENT_JACK_IO);
+			break;
+		case SL_MEDIA_FAULT_CAUSE_POWER_SET:
+			SL_CTRL_MEDIA_CAUSE_COUNTER_INC(media_jack, MEDIA_CAUSE_POWER_SET);
+			break;
+		case SL_MEDIA_FAULT_CAUSE_SHIFT_DOWN_JACK_IO:
+			SL_CTRL_MEDIA_CAUSE_COUNTER_INC(media_jack, MEDIA_CAUSE_SHIFT_DOWN_JACK_IO);
+			break;
+		case SL_MEDIA_FAULT_CAUSE_SHIFT_DOWN_JACK_IO_LOW_POWER_SET:
+			SL_CTRL_MEDIA_CAUSE_COUNTER_INC(media_jack, MEDIA_CAUSE_SHIFT_DOWN_JACK_IO_LOW_POWER_SET);
+			break;
+		case SL_MEDIA_FAULT_CAUSE_SHIFT_DOWN_JACK_IO_HIGH_POWER_SET:
+			SL_CTRL_MEDIA_CAUSE_COUNTER_INC(media_jack, MEDIA_CAUSE_SHIFT_DOWN_JACK_IO_HIGH_POWER_SET);
+			break;
+		case SL_MEDIA_FAULT_CAUSE_SHIFT_UP_JACK_IO:
+			SL_CTRL_MEDIA_CAUSE_COUNTER_INC(media_jack, MEDIA_CAUSE_SHIFT_UP_JACK_IO);
+			break;
+		case SL_MEDIA_FAULT_CAUSE_SHIFT_UP_JACK_IO_LOW_POWER_SET:
+			SL_CTRL_MEDIA_CAUSE_COUNTER_INC(media_jack, MEDIA_CAUSE_SHIFT_UP_JACK_IO_LOW_POWER_SET);
+			break;
+		case SL_MEDIA_FAULT_CAUSE_SHIFT_UP_JACK_IO_HIGH_POWER_SET:
+			SL_CTRL_MEDIA_CAUSE_COUNTER_INC(media_jack, MEDIA_CAUSE_SHIFT_UP_JACK_IO_HIGH_POWER_SET);
+			break;
+		case SL_MEDIA_FAULT_CAUSE_SHIFT_STATE_JACK_IO:
+			SL_CTRL_MEDIA_CAUSE_COUNTER_INC(media_jack, MEDIA_CAUSE_SHIFT_STATE_JACK_IO);
+			break;
+		case SL_MEDIA_FAULT_CAUSE_OFFLINE:
+			SL_CTRL_MEDIA_CAUSE_COUNTER_INC(media_jack, MEDIA_CAUSE_OFFLINE);
+			break;
+		case SL_MEDIA_FAULT_CAUSE_HOT:
+			SL_CTRL_MEDIA_CAUSE_COUNTER_INC(media_jack, MEDIA_CAUSE_HOT);
+			break;
+		case SL_MEDIA_FAULT_CAUSE_WARM:
+			SL_CTRL_MEDIA_CAUSE_COUNTER_INC(media_jack, MEDIA_CAUSE_WARM);
+			break;
+		default:
+			sl_ctrl_log_warn_trace(media_jack, LOG_NAME,
+					       "cause_counter_inc unknown fault cause (bit = %lu)", which);
+			break;
+		}
+	}
+}

-- 
2.56.0


^ permalink raw reply	[flat|nested] 25+ messages in thread
* [PATCH 13/23] net: hpe: sl: add media and cable handling
  2026-10-30 20:58 [PATCH 00/23] Subject: [PATCH net-next 00/23] net/hpe: add HPE Slingshot NIC drivers Doug Ledford
                   ` (11 preceding siblings ...)
  2026-10-30 20:59 ` [PATCH 12/23] net: hpe: sl: add the control layer Doug Ledford
@ 2026-10-30 20:59 ` Doug Ledford
  2026-10-30 20:59 ` [PATCH 14/23] net: hpe: sl: add the sysfs interface Doug Ledford
                   ` (10 subsequent siblings)
  23 siblings, 0 replies; 25+ messages in thread
From: Doug Ledford @ 2026-10-30 20:59 UTC (permalink / raw)
  To: Slingshot Open Source Team, Nathan Chancellor, Nicolas Schier,
	Richard Cochran, Andrew Lunn, David S. Miller, Eric Dumazet,
	Jakub Kicinski, Paolo Abeni, Sumit Semwal, Christian König,
	Guenter Roeck
  Cc: linux-kernel, netdev, linux-kbuild, Doug Ledford, Mamila Santosh

Add cable and media handling: EEPROM parsing, the cable database,
per-jack data, and the emulated jack used when no real media is
present.

checkpatch --strict (100 columns) still reports the following in this
patch. They need coordination with the internal repositories this code
is maintained in and will be fixed in V2:
- WARNING: LONG_LINE (164), LONG_LINE_STRING (21), LONG_LINE_COMMENT
  (2), BRACES (1)
- CHECK: UNNECESSARY_PARENTHESES (27), ALLOC_SIZEOF_STRUCT (3), BRACES
  (2), COMPARISON_TO_NULL (1)

Co-developed-by: Mamila Santosh <santosh-kumar.mamila@hpe.com>
Signed-off-by: Mamila Santosh <santosh-kumar.mamila@hpe.com>
Signed-off-by: Doug Ledford <doug.ledford@hpe.com>
---
 .../ethernet/hpe/sl/media/base/sl_media_eeprom.c   |  611 +++++++++++
 .../hpe/sl/media/data/nic/sl_media_data_jack.c     |  496 +++++++++
 .../hpe/sl/media/data/nic/sl_media_data_jack_emu.c |   38 +
 .../hpe/sl/media/data/nic/sl_media_data_ldev.c     |   30 +
 .../hpe/sl/media/data/sl_media_data_cable_db_ops.c |  111 ++
 .../hpe/sl/media/data/sl_media_data_jack.c         |  344 +++++++
 .../hpe/sl/media/data/sl_media_data_ldev.c         |  115 +++
 .../hpe/sl/media/data/sl_media_data_lgrp.c         |  127 +++
 .../hpe/sl/media/data/sl_media_data_lgrp_trace.c   |   31 +
 .../net/ethernet/hpe/sl/media/nic/sl_media_io.c    |   63 ++
 .../net/ethernet/hpe/sl/media/nic/sl_media_jack.c  |  315 ++++++
 .../net/ethernet/hpe/sl/media/nic/sl_media_ldev.c  |   13 +
 drivers/net/ethernet/hpe/sl/media/sl_media_jack.c  | 1067 ++++++++++++++++++++
 drivers/net/ethernet/hpe/sl/media/sl_media_ldev.c  |   22 +
 drivers/net/ethernet/hpe/sl/media/sl_media_lgrp.c  |  498 +++++++++
 15 files changed, 3881 insertions(+)

diff --git a/drivers/net/ethernet/hpe/sl/media/base/sl_media_eeprom.c b/drivers/net/ethernet/hpe/sl/media/base/sl_media_eeprom.c
new file mode 100644
index 000000000000..80113ec4860d
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/media/base/sl_media_eeprom.c
@@ -0,0 +1,611 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2023-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/slab.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+
+#include <linux/hpe/sl/sl_media.h>
+
+#include "sl_media_eeprom.h"
+#include "sl_media_lgrp.h"
+#include "sl_media_jack.h"
+#include "base/sl_media_log.h"
+#include "data/sl_media_data_cable_db.h"
+
+#define LOG_NAME SL_MEDIA_EEPROM_LOG_NAME
+
+static void sl_media_eeprom_appsel_info_store(struct sl_media_jack *media_jack, u8 host_interface,
+					      unsigned long *speeds_map, u8 appsel_num, u8 lane_count)
+{
+	switch (host_interface) {
+	case SL_MEDIA_SS1_HOST_INTERFACE_50GAUI_1_C2M:
+	case SL_MEDIA_SS1_HOST_INTERFACE_50GBASE_CR:
+		*speeds_map |= SL_MEDIA_SPEEDS_SUPPORT_CD_50G;
+		break;
+	case SL_MEDIA_SS1_HOST_INTERFACE_100GAUI_2_C2M:
+	case SL_MEDIA_SS1_HOST_INTERFACE_100GBASE_CR2:
+		*speeds_map |= SL_MEDIA_SPEEDS_SUPPORT_CD_100G;
+		break;
+	case SL_MEDIA_SS2_HOST_INTERFACE_100GBASE_CR1:
+		*speeds_map |= SL_MEDIA_SPEEDS_SUPPORT_BJ_100G;
+		fallthrough;
+	case SL_MEDIA_SS2_HOST_INTERFACE_100GAUI_1_L_C2M:
+		*speeds_map |= SL_MEDIA_SPEEDS_SUPPORT_CK_100G;
+		break;
+	case SL_MEDIA_SS1_HOST_INTERFACE_200GBASE_CR4:
+		*speeds_map |= SL_MEDIA_SPEEDS_SUPPORT_BS_200G;
+		*speeds_map |= SL_MEDIA_SPEEDS_SUPPORT_BJ_100G;
+		break;
+	case SL_MEDIA_SS1_HOST_INTERFACE_200GAUI_4_C2M:
+		*speeds_map |= SL_MEDIA_SPEEDS_SUPPORT_BS_200G;
+		media_jack->appsel_num_200_gaui = appsel_num;
+		media_jack->lane_count_200_gaui = lane_count;
+		media_jack->host_interface_200_gaui = host_interface;
+		break;
+	case SL_MEDIA_SS2_HOST_INTERFACE_200GBASE_CR2:
+		*speeds_map |= SL_MEDIA_SPEEDS_SUPPORT_BJ_100G;
+		fallthrough;
+	case SL_MEDIA_SS2_HOST_INTERFACE_200GAUI_2_S_C2M:
+		*speeds_map |= SL_MEDIA_SPEEDS_SUPPORT_CK_200G;
+		break;
+	case SL_MEDIA_SS2_HOST_INTERFACE_400GBASE_CR4:
+		*speeds_map |= SL_MEDIA_SPEEDS_SUPPORT_BJ_100G;
+		*speeds_map |= SL_MEDIA_SPEEDS_SUPPORT_CK_400G;
+		break;
+	case SL_MEDIA_SS2_HOST_INTERFACE_400GAUI_4_S_C2M:
+		*speeds_map |= SL_MEDIA_SPEEDS_SUPPORT_CK_400G;
+		if (media_jack->appsel_num_400_gaui) /* we prefer 4_l_c2m over 4_s_c2m for default ck400G speed */
+			break;
+		media_jack->appsel_num_400_gaui = appsel_num;
+		media_jack->lane_count_400_gaui = lane_count;
+		media_jack->host_interface_400_gaui = host_interface;
+		break;
+	case SL_MEDIA_SS1_HOST_INTERFACE_400GAUI_4_L_C2M:
+		*speeds_map |= SL_MEDIA_SPEEDS_SUPPORT_CK_400G;
+		media_jack->appsel_num_400_gaui = appsel_num;
+		media_jack->lane_count_400_gaui = lane_count;
+		media_jack->host_interface_400_gaui = host_interface;
+		fallthrough;
+	case SL_MEDIA_SS1_HOST_INTERFACE_400GBASE_CR8:
+		*speeds_map |= SL_MEDIA_SPEEDS_SUPPORT_BS_200G;
+		fallthrough;
+	case SL_MEDIA_SS1_HOST_INTERFACE_CAUI_4_C2M:
+		*speeds_map |= SL_MEDIA_SPEEDS_SUPPORT_BJ_100G;
+		break;
+	case SL_MEDIA_SS2_HOST_INTERFACE_800GBASE_CR8:
+		*speeds_map |= SL_MEDIA_SPEEDS_SUPPORT_BJ_100G;
+		*speeds_map |= SL_MEDIA_SPEEDS_SUPPORT_CK_400G;
+		*speeds_map |= SL_MEDIA_SPEEDS_SUPPORT_CK_800G;
+		break;
+	case SL_MEDIA_SS2_HOST_INTERFACE_800GAUI_8_S_C2M:
+		*speeds_map |= SL_MEDIA_SPEEDS_SUPPORT_CK_400G;
+		*speeds_map |= SL_MEDIA_SPEEDS_SUPPORT_CK_800G;
+		if (!media_jack->host_interface_400_gaui) {
+			media_jack->appsel_num_400_gaui = appsel_num;
+			media_jack->host_interface_400_gaui = host_interface;
+		}
+		break;
+	default:
+		sl_media_log_dbg(media_jack, LOG_NAME,
+				 "invalid host interface (0x%x)", host_interface);
+	}
+}
+
+#define APPSEL_PAGE0_START_OFFSET 86
+#define APPSEL_PAGE1_START_OFFSET 223
+#define APPSEL_STRIDE             4
+#define APPSEL_END                0xFF
+#define APPSEL_LAST_PAGE0         114
+#define APPSEL_LAST_PAGE1         247
+#define APPSEL_LANE_COUNT_OFFSET  2
+static int sl_media_eeprom_appsel_info_get(struct sl_media_jack *media_jack, unsigned long *speeds_map)
+{
+	u8  host_interface;
+	u8  appsel_curr;
+	u8  appsel_num;
+
+	appsel_curr = APPSEL_PAGE0_START_OFFSET;
+	appsel_num = 1;
+	while (appsel_curr <= APPSEL_LAST_PAGE0) {
+		host_interface = media_jack->eeprom_page0[appsel_curr];
+		if (host_interface == APPSEL_END)
+			return 0;
+		sl_media_eeprom_appsel_info_store(media_jack, host_interface, speeds_map, appsel_num,
+						  media_jack->eeprom_page0[appsel_curr + APPSEL_LANE_COUNT_OFFSET]);
+		appsel_curr += APPSEL_STRIDE;
+		appsel_num++;
+	}
+
+	appsel_curr = APPSEL_PAGE1_START_OFFSET;
+	while (appsel_curr <= APPSEL_LAST_PAGE1) {
+		host_interface = media_jack->eeprom_page1[appsel_curr];
+		if (host_interface == APPSEL_END)
+			return 0;
+		sl_media_eeprom_appsel_info_store(media_jack, host_interface, speeds_map, appsel_num,
+						  media_jack->eeprom_page1[appsel_curr + APPSEL_LANE_COUNT_OFFSET]);
+		appsel_curr += APPSEL_STRIDE;
+		appsel_num++;
+	}
+
+	return 0;
+}
+
+static int sl_media_eeprom_furcation_get(struct sl_media_jack *media_jack, u32 *furcation)
+{
+	*furcation = SL_MEDIA_FURCATION_X1;
+	return 0;
+}
+
+#define CMIS_CONNECTOR_TYPE_OFFSET    203
+#define CMIS_CONNECTOR_POC_SR8        0x28
+#define CMIS_CONNECTOR_POC_SR4        0x0C
+#define SFF8436_CONNECTOR_TYPE_OFFSET 130
+#define SFF_CONNECTOR_AOC             0x23
+static bool sl_media_eeprom_is_type_poc(struct sl_media_jack *media_jack, u8 format)
+{
+	if (format == SL_MEDIA_MGMT_IF_CMIS) {
+		switch (media_jack->eeprom_page0[CMIS_CONNECTOR_TYPE_OFFSET]) {
+		case CMIS_CONNECTOR_POC_SR8:
+		case CMIS_CONNECTOR_POC_SR4:
+			return true;
+		default:
+			return false;
+		}
+	}
+
+	/* SFF */
+	switch (media_jack->eeprom_page0[SFF8436_CONNECTOR_TYPE_OFFSET]) {
+	case SFF_CONNECTOR_AOC:
+		return false;
+	default:
+		return true;
+	}
+}
+
+#define CMIS_TYPE_OFFSET    212
+#define CMIS_MEDIA_AOC      0x00
+#define CMIS_MEDIA_PEC      0x0A
+#define CMIS_MEDIA_AEC      0x0C
+#define CMIS_MEDIA_ACC      0x0F
+#define SFF8436_TYPE_OFFSET 147
+#define SFF_MEDIA_AOC       0x00
+#define SFF_MEDIA_PEC       0xA0
+#define SFF_MEDIA_AEC       0xC0
+static int sl_media_eeprom_type_get(struct sl_media_jack *media_jack, u8 format, u32 vendor, u32 *type)
+{
+	u8 media;
+
+	if (format == SL_MEDIA_MGMT_IF_CMIS) {
+		media = media_jack->eeprom_page0[CMIS_TYPE_OFFSET];
+		switch (media) {
+		case CMIS_MEDIA_AOC:
+			if (sl_media_eeprom_is_type_poc(media_jack, format))
+				*type = SL_MEDIA_TYPE_POC;
+			else
+				*type = SL_MEDIA_TYPE_AOC;
+			break;
+		case CMIS_MEDIA_PEC:
+			*type = SL_MEDIA_TYPE_PEC;
+			break;
+		case CMIS_MEDIA_AEC:
+			*type = SL_MEDIA_TYPE_AEC;
+			break;
+		case CMIS_MEDIA_ACC:
+			/* compensate for Molex type programming issue */
+			if (vendor == SL_MEDIA_VENDOR_MOLEX)
+				*type = SL_MEDIA_TYPE_AEC;
+			else
+				*type = SL_MEDIA_TYPE_ACC;
+			break;
+		default:
+			*type = SL_MEDIA_TYPE_UNSUPPORTED;
+		}
+	} else {
+		media = media_jack->eeprom_page0[SFF8436_TYPE_OFFSET];
+		switch (media) {
+		case SFF_MEDIA_AOC:
+			if (sl_media_eeprom_is_type_poc(media_jack, format))
+				*type = SL_MEDIA_TYPE_POC;
+			else
+				*type = SL_MEDIA_TYPE_AOC;
+			break;
+		case SFF_MEDIA_PEC:
+			*type = SL_MEDIA_TYPE_PEC;
+			break;
+		case SFF_MEDIA_AEC:
+			*type = SL_MEDIA_TYPE_AEC;
+			break;
+		default:
+			*type = SL_MEDIA_TYPE_UNSUPPORTED;
+		}
+	}
+
+	sl_media_log_dbg(media_jack, LOG_NAME,
+			 "type get (media = 0x%X, type = 0x%X %s)",
+			 media, *type, sl_media_type_str(*type));
+
+	return 0;
+}
+
+#define CMIS_VENDOR_OFFSET      129
+#define SFF8436_VENDOR_OFFSET   148
+#define VENDOR_NAME_MAX_LEN     32
+struct vendor {
+	char name[VENDOR_NAME_MAX_LEN];
+	u32  type;
+};
+
+static const struct vendor vendor_list[] = {
+	{ .name = "TE Connectivity",
+	  .type = SL_MEDIA_VENDOR_TE },
+	{ .name = "Hisense",
+	  .type = SL_MEDIA_VENDOR_HISENSE },
+	{ .name = "FINISAR CORP",
+	  .type = SL_MEDIA_VENDOR_FINISAR },
+	{ .name = "Bizlink",
+	  .type = SL_MEDIA_VENDOR_BIZLINK },
+	{ .name = "Cloud Light",
+	  .type = SL_MEDIA_VENDOR_CLOUD_LIGHT },
+	{ .name = "Molex",
+	  .type = SL_MEDIA_VENDOR_MOLEX },
+	{ .name = "MULTILANE",
+	  .type = SL_MEDIA_VENDOR_MULTILANE },
+	{ .name = "Amphenol",
+	  .type = SL_MEDIA_VENDOR_AMPHENOL },
+};
+
+static int sl_media_eeprom_vendor_get(struct sl_media_jack *media_jack, u8 format, u32 *vendor)
+{
+	const char *vendor_ptr;
+	int         x;
+
+	if (format == SL_MEDIA_MGMT_IF_CMIS)
+		vendor_ptr = &(media_jack->eeprom_page0[CMIS_VENDOR_OFFSET]);
+	else
+		vendor_ptr = &(media_jack->eeprom_page0[SFF8436_VENDOR_OFFSET]);
+
+	for (x = 0; x < ARRAY_SIZE(vendor_list); ++x) {
+		if (strnstr(vendor_ptr, vendor_list[x].name, VENDOR_NAME_MAX_LEN) == NULL)
+			continue;
+		*vendor = vendor_list[x].type;
+		sl_media_log_dbg(media_jack, LOG_NAME,
+				 "vendor get (vendor = %u %s)", *vendor, sl_media_vendor_str(*vendor));
+		return 0;
+	}
+
+	*vendor = 0;
+
+	sl_media_jack_fault_cause_set(media_jack, SL_MEDIA_FAULT_CAUSE_EEPROM_VENDOR_UNSUPPORTED);
+	sl_media_log_err_trace(media_jack, LOG_NAME, "eeprom vendor get unsupported");
+
+	return 0;
+}
+
+static bool is_valid_char(char c)
+{
+	return c >= 33 && c <= 126;
+}
+
+#define CMIS_VENDOR_PN_OFFSET 148
+#define SFF_VENDOR_PN_OFFSET  168
+static int sl_media_eeprom_vendor_pn_str_get(struct sl_media_jack *media_jack, u8 format, char *vendor_pn_str)
+{
+	int x;
+	int pos;
+	u8  vendor_pn_offset;
+
+	if (format == SL_MEDIA_MGMT_IF_CMIS)
+		vendor_pn_offset = CMIS_VENDOR_PN_OFFSET;
+	else
+		vendor_pn_offset = SFF_VENDOR_PN_OFFSET;
+
+	pos = 0;
+	memset(vendor_pn_str, 0, SL_MEDIA_VENDOR_PN_SIZE);
+	for (x = 0; x < SL_MEDIA_VENDOR_PN_SIZE - 1; ++x) {
+		if (is_valid_char(media_jack->eeprom_page0[vendor_pn_offset + x])) {
+			vendor_pn_str[pos] = media_jack->eeprom_page0[vendor_pn_offset + x];
+			pos++;
+		}
+	}
+
+	sl_media_log_dbg(media_jack, LOG_NAME,
+			 "vendor part num get (par_num = %s)", vendor_pn_str);
+
+	return 0;
+}
+
+#define HPE_PN_OFFSET 229
+static int sl_media_eeprom_hpe_pn_get(struct sl_media_jack *media_jack, u32 *hpe_pn, char *hpe_pn_str)
+{
+	const char *pn_ptr;
+	int         i;
+	int         counter;
+
+	counter = 0;
+	for (i = 0; i < SL_MEDIA_HPE_PN_SIZE - 1; ++i) {
+		if (is_valid_char(media_jack->eeprom_page0[HPE_PN_OFFSET + i])) {
+			hpe_pn_str[counter] = media_jack->eeprom_page0[HPE_PN_OFFSET + i];
+			counter++;
+		}
+	}
+	hpe_pn_str[counter] = '\0';
+
+	pn_ptr = &(media_jack->eeprom_page0[HPE_PN_OFFSET]);
+	for (i = 0; i < SL_MEDIA_HPE_PN_SIZE - 1; ++i) {
+		if (pn_ptr[i] < 48 || pn_ptr[i] > 57) /* if the PN character is not numeric, ignore it */
+			continue;
+		*hpe_pn = *hpe_pn * 10 + (pn_ptr[i] - '0');
+	}
+
+	sl_media_log_dbg(media_jack, LOG_NAME,
+			 "hpe part num get (hpe_pn = %s)", hpe_pn_str);
+
+	return 0;
+}
+
+#define CMIS_SERIAL_NUM_OFFSET 166
+#define SFF_SERIAL_NUM_OFFSET  196
+static int sl_media_eeprom_serial_num_get(struct sl_media_jack *media_jack, u8 format, char *serial_num_str)
+{
+	int i;
+	int counter;
+	u8  serial_num_offset;
+
+	if (format == SL_MEDIA_MGMT_IF_CMIS)
+		serial_num_offset = CMIS_SERIAL_NUM_OFFSET;
+	else
+		serial_num_offset = SFF_SERIAL_NUM_OFFSET;
+
+	counter = 0;
+	memset(serial_num_str, '\0', SL_MEDIA_SERIAL_NUM_SIZE);
+	for (i = 0; i < (SL_MEDIA_SERIAL_NUM_SIZE - 1); ++i) {
+		if (media_jack->eeprom_page0[serial_num_offset + i] == '-')
+			break;
+
+		if (is_valid_char(media_jack->eeprom_page0[serial_num_offset + i])) {
+			serial_num_str[counter] = media_jack->eeprom_page0[serial_num_offset + i];
+			counter++;
+		}
+	}
+
+	sl_media_log_dbg(media_jack, LOG_NAME,
+			 "serial num get (serial_num = %s)", serial_num_str);
+
+	return 0;
+}
+
+#define CMIS_DATE_CODE_OFFSET 182
+#define SFF_DATE_CODE_OFFSET  212
+static int sl_media_eeprom_date_code_get(struct sl_media_jack *media_jack, u8 format, char *date_code_str)
+{
+	u8 date_code_offset;
+
+	if (format == SL_MEDIA_MGMT_IF_CMIS)
+		date_code_offset = CMIS_DATE_CODE_OFFSET;
+	else
+		date_code_offset = SFF_DATE_CODE_OFFSET;
+
+	date_code_str[0] = media_jack->eeprom_page0[date_code_offset];
+	date_code_str[1] = media_jack->eeprom_page0[date_code_offset + 1];
+	date_code_str[2] = '-';
+	date_code_str[3] = media_jack->eeprom_page0[date_code_offset + 2];
+	date_code_str[4] = media_jack->eeprom_page0[date_code_offset + 3];
+	date_code_str[5] = '-';
+	date_code_str[6] = media_jack->eeprom_page0[date_code_offset + 4];
+	date_code_str[7] = media_jack->eeprom_page0[date_code_offset + 5];
+	date_code_str[8] = '\0';
+
+	sl_media_log_dbg(media_jack, LOG_NAME,
+			 "date code get (date = %s)", date_code_str);
+
+	return 0;
+}
+
+#define FIRMWARE_VERSION_OFFSET 39
+static int sl_media_eeprom_fw_ver_get(struct sl_media_jack *media_jack, u8 *fw_ver)
+{
+	fw_ver[0] = media_jack->eeprom_page0[FIRMWARE_VERSION_OFFSET];
+	fw_ver[1] = media_jack->eeprom_page0[FIRMWARE_VERSION_OFFSET + 1];
+
+	return 0;
+}
+
+#define CABLE_END_OFFSET 240
+static int sl_media_eeprom_cable_end_get(struct sl_media_jack *media_jack)
+{
+	media_jack->cable_end = media_jack->eeprom_page0[CABLE_END_OFFSET];
+
+	return 0;
+}
+
+#define CMIS_LENGTH_OFFSET    202
+#define SFF8436_LENGTH_OFFSET 146
+static int sl_media_eeprom_length_get(struct sl_media_jack *media_jack, u8 format, u32 *length)
+{
+	if (format == SL_MEDIA_MGMT_IF_CMIS) {
+		*length = (media_jack->eeprom_page0[CMIS_LENGTH_OFFSET] & 0x3F);
+		switch (media_jack->eeprom_page0[CMIS_LENGTH_OFFSET] & 0xC0) {
+		case 0:
+			*length *= 10;
+			break;
+		case 0x40:
+			*length *= 100;
+			break;
+		case 0x80:
+			*length *= 1000;
+			break;
+		case 0xC0:
+			*length *= 10000;
+			break;
+		default:
+			*length = 0;
+			break;
+		}
+	} else {
+		*length = media_jack->eeprom_page0[SFF8436_LENGTH_OFFSET] * 100;
+	}
+
+	sl_media_log_dbg(media_jack, LOG_NAME,
+			 "length get (length = %ucm)", *length);
+
+	return 0;
+}
+
+#define SUPPORTED_FLAGS_ADVERTISEMENT_OFFSET 157
+static void sl_media_eeprom_supported_flags_advertised_get(struct sl_media_jack *media_jack,
+							   u8 *supported_flags_advertised)
+{
+	spin_lock(&media_jack->data_lock);
+	memcpy(supported_flags_advertised, &media_jack->eeprom_page1[SUPPORTED_FLAGS_ADVERTISEMENT_OFFSET],
+	       SL_MEDIA_SUPPORTED_FLAGS_ADVERTISED_SIZE);
+	spin_unlock(&media_jack->data_lock);
+}
+
+bool sl_media_eeprom_is_fw_version_supported(struct sl_media_jack *media_jack, struct sl_media_attr *media_attr)
+{
+	sl_media_log_dbg(media_jack, LOG_NAME,
+			 "is fw version supported (type = 0x%X %s, shape = %u %s, end = %u %s, idx = %d)",
+			 media_attr->type, sl_media_type_str(media_attr->type),
+			 media_attr->shape, sl_media_shape_str(media_attr->shape),
+			 media_jack->cable_end, sl_media_cable_end_str(media_jack->cable_end),
+			 media_jack->cable_db_idx);
+	sl_media_log_dbg(media_jack, LOG_NAME,
+			 "is fw version supported (fw_ver = %02X.%02X, db_fw_ver = %02X.%02X, db_split_fw_ver = %02X.%02X)",
+			 media_attr->fw_ver[0], media_attr->fw_ver[1],
+			 cable_db[media_jack->cable_db_idx].fw_ver.major,
+			 cable_db[media_jack->cable_db_idx].fw_ver.minor,
+			 cable_db[media_jack->cable_db_idx].fw_ver.split_major,
+			 cable_db[media_jack->cable_db_idx].fw_ver.split_minor);
+
+	if (media_attr->shape == SL_MEDIA_SHAPE_SPLITTER && media_jack->cable_end != SL_MEDIA_CABLE_END_DD)
+		return ((media_attr->fw_ver[0] > cable_db[media_jack->cable_db_idx].fw_ver.split_major) ||
+			((media_attr->fw_ver[0] == cable_db[media_jack->cable_db_idx].fw_ver.split_major) &&
+			(media_attr->fw_ver[1] >= cable_db[media_jack->cable_db_idx].fw_ver.split_minor)));
+
+	return ((media_attr->fw_ver[0] > cable_db[media_jack->cable_db_idx].fw_ver.major) ||
+		((media_attr->fw_ver[0] == cable_db[media_jack->cable_db_idx].fw_ver.major) &&
+		(media_attr->fw_ver[1] >= cable_db[media_jack->cable_db_idx].fw_ver.minor)));
+}
+
+int sl_media_eeprom_target_fw_ver_str_get(struct sl_media_jack *media_jack, char *target_fw_str, size_t target_fw_size)
+{
+	sl_media_log_dbg(media_jack, LOG_NAME,
+			 "target fw ver get (idx = %u, type = 0x%X %s, shape = %u %s, end = %u %s, supported = %s)",
+			 media_jack->cable_db_idx,
+			 media_jack->cable_info[0].media_attr.type,
+			 sl_media_type_str(media_jack->cable_info[0].media_attr.type),
+			 media_jack->cable_info[0].media_attr.shape,
+			 sl_media_shape_str(media_jack->cable_info[0].media_attr.shape),
+			 media_jack->cable_end,
+			 sl_media_cable_end_str(media_jack->cable_end),
+			 media_jack->is_cable_unsupported ? "no" : "yes");
+
+	if (!SL_MEDIA_LGRP_MEDIA_TYPE_IS_ACTIVE(media_jack->cable_info[0].media_attr.type)) {
+		snprintf(target_fw_str, target_fw_size, "invalid-type\n");
+		return 0;
+	}
+
+	if (media_jack->is_cable_unsupported) {
+		snprintf(target_fw_str, target_fw_size, "unsupported\n");
+		return 0;
+	}
+
+	if (media_jack->is_supported_ss200_cable) {
+		snprintf(target_fw_str, target_fw_size, "ss200-cable\n");
+		return 0;
+	}
+
+	if (media_jack->cable_info[0].media_attr.shape == SL_MEDIA_SHAPE_SPLITTER &&
+	    media_jack->cable_end != SL_MEDIA_CABLE_END_DD) {
+		snprintf(target_fw_str, target_fw_size, "%02X.%02X\n",
+			 cable_db[media_jack->cable_db_idx].fw_ver.split_major,
+			 cable_db[media_jack->cable_db_idx].fw_ver.split_minor);
+		return 0;
+	}
+
+	snprintf(target_fw_str, target_fw_size, "%02X.%02X\n",
+		 cable_db[media_jack->cable_db_idx].fw_ver.major,
+		 cable_db[media_jack->cable_db_idx].fw_ver.minor);
+
+	return 0;
+}
+
+void sl_media_eeprom_parse(struct sl_media_jack *media_jack, struct sl_media_attr *media_attr)
+{
+	sl_media_log_dbg(media_jack, LOG_NAME, "parse");
+
+	/* vendor get MUST be first */
+	sl_media_eeprom_vendor_get(media_jack, media_attr->format, &(media_attr->vendor));
+	sl_media_eeprom_vendor_pn_str_get(media_jack, media_attr->format, media_attr->vendor_pn_str);
+	sl_media_eeprom_type_get(media_jack, media_attr->format, media_attr->vendor, &(media_attr->type));
+	sl_media_eeprom_hpe_pn_get(media_jack, &(media_attr->hpe_pn), media_attr->hpe_pn_str);
+	sl_media_eeprom_serial_num_get(media_jack, media_attr->format, media_attr->serial_num_str);
+	sl_media_eeprom_date_code_get(media_jack, media_attr->format, media_attr->date_code_str);
+	sl_media_eeprom_fw_ver_get(media_jack, media_attr->fw_ver);
+	sl_media_eeprom_cable_end_get(media_jack);
+	sl_media_eeprom_length_get(media_jack, media_attr->format, &(media_attr->length_cm));
+	sl_media_eeprom_appsel_info_get(media_jack, &(media_attr->speeds_map));
+	sl_media_eeprom_furcation_get(media_jack, &(media_attr->furcation));
+	sl_media_eeprom_supported_flags_advertised_get(media_jack, media_attr->supported_flags_advertised);
+
+	sl_media_log_dbg(media_jack, LOG_NAME,
+			 "parse (format = %u, vendor = %u %s, vendor_pn_str = %s, fw = %02X.%02X)",
+			 media_attr->format, media_attr->vendor, sl_media_vendor_str(media_attr->vendor),
+			 media_attr->vendor_pn_str, media_attr->fw_ver[0], media_attr->fw_ver[1]);
+	sl_media_log_dbg(media_jack, LOG_NAME,
+			 "parse (type = 0x%X %s, length = %ucm, speeds_map = 0x%lX)",
+			 media_attr->type, sl_media_type_str(media_attr->type), media_attr->length_cm,
+			 media_attr->speeds_map);
+	sl_media_log_dbg(media_jack, LOG_NAME,
+			 "parse (hpe_pn = %u, serial_num = %s, errors = 0x%X, info = 0x%X)",
+			 media_attr->hpe_pn, media_attr->serial_num_str, media_attr->errors, media_attr->info);
+}
+
+#define IDENTIFIER_OFFSET 0
+#define REV_CMPL_OFFSET   1
+int sl_media_eeprom_format_get(struct sl_media_jack *media_jack, u8 *format)
+{
+	u8   identifier;
+	u8   revision;
+	bool is_sff8636;
+	bool is_cmis;
+
+	sl_media_log_dbg(media_jack, LOG_NAME, "format get");
+
+	identifier = media_jack->eeprom_page0[IDENTIFIER_OFFSET];
+	revision   = media_jack->eeprom_page0[REV_CMPL_OFFSET];
+
+	is_sff8636 = (identifier == 0x0D || identifier == 0x11) && (revision < 0x27);
+	is_cmis    = ((identifier == 0x18) || (identifier == 0x19) || (identifier >= 0x1E && identifier <= 0x25)) &&
+			((revision & 0xF0) >= 0x30 && (revision & 0xF0) <= 0x50);
+
+	if (is_sff8636) {
+		*format = SL_MEDIA_MGMT_IF_SFF8636;
+		sl_media_log_dbg(media_jack, LOG_NAME, "format SFF8636 (id = 0x%X, rev = 0x%X)", identifier, revision);
+		return 0;
+	}
+
+	if (is_cmis) {
+		*format = SL_MEDIA_MGMT_IF_CMIS;
+		sl_media_log_dbg(media_jack, LOG_NAME, "format CMIS (id = 0x%X, rev = 0x%X)", identifier, revision);
+		return 0;
+	}
+
+	media_jack->is_cable_format_unsupported = true;
+	sl_media_jack_fault_cause_set(media_jack, SL_MEDIA_FAULT_CAUSE_EEPROM_FORMAT_UNSUPPORTED);
+	sl_media_log_err_trace(media_jack, LOG_NAME, "unsupported format (id = 0x%X, rev = 0x%X)",
+			       identifier, revision);
+
+	return -EMEDIUMTYPE;
+}
+
+#define MEDIA_INTERFACE_CODE_OFFSET 87
+int sl_media_eeprom_media_interface_get(struct sl_media_jack *media_jack, u8 *media_interface)
+{
+	spin_lock(&media_jack->data_lock);
+	*media_interface = media_jack->eeprom_page0[MEDIA_INTERFACE_CODE_OFFSET];
+	spin_unlock(&media_jack->data_lock);
+
+	return 0;
+}
diff --git a/drivers/net/ethernet/hpe/sl/media/data/nic/sl_media_data_jack.c b/drivers/net/ethernet/hpe/sl/media/data/nic/sl_media_data_jack.c
new file mode 100644
index 000000000000..9d46b3f13de2
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/media/data/nic/sl_media_data_jack.c
@@ -0,0 +1,496 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2024-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/delay.h>
+
+#include "base/sl_media_log.h"
+
+#include "sl_media_io.h"
+#include "sl_media_jack.h"
+#include "data/sl_media_data_jack.h"
+#include "sl_core_link.h"
+
+#define LOG_NAME SL_MEDIA_DATA_JACK_LOG_NAME
+
+enum sl_media_led_states {
+	LED_OFF          = 0,
+	LED_ON_GRN       = 1,
+	LED_SLOW_GRN     = 2,
+	LED_FAST_GRN     = 3,
+	LED_ON_YEL       = 4,
+	LED_SLOW_YEL     = 5,
+	LED_FAST_YEL     = 6,
+	LED_SLOW_GRN_YEL = 7,
+	LED_FAST_GRN_YEL = 8,
+};
+
+int sl_media_data_jack_scan(u8 ldev_num)
+{
+	struct sl_media_jack *media_jack;
+
+	sl_media_log_dbg(NULL, LOG_NAME, "jack scan");
+
+	media_jack = sl_media_data_jack_get(ldev_num, 0);
+	media_jack->cable_info[0].ldev_num = ldev_num;
+	media_jack->cable_info[0].lgrp_num = 0; /* hardcoding 0 since only one lgrp*/
+
+	return 0;
+}
+
+int sl_media_data_jack_fake_media_attr_set(struct sl_media_jack *media_jack,
+					   struct sl_media_lgrp_cable_info *cable_info, struct sl_media_attr *fake_media_attr)
+{
+	return 0;
+}
+
+void sl_media_data_jack_fake_media_attr_clr(struct sl_media_jack *media_jack,
+					    struct sl_media_lgrp_cable_info *cable_info)
+{
+
+}
+
+#define DATA_PATH_STATE_DEACTIVATED       0x1
+#define DATA_PATH_EXPLICIT_CONTROL_ENABLE 0x00
+#define DATA_PATH_ID                      0x08
+#define DATA_PATH_LOWER_LANE_CONFIG       (DATA_PATH_EXPLICIT_CONTROL_ENABLE)
+#define DATA_PATH_LANES_DEACTIVATED       (DATA_PATH_STATE_DEACTIVATED << 4 | DATA_PATH_STATE_DEACTIVATED)
+int sl_media_data_jack_cable_downshift(struct sl_media_jack *media_jack)
+{
+	int rtn;
+	int i;
+
+	sl_media_log_dbg(media_jack, LOG_NAME, "data jack cable downshift");
+
+	/*
+	 * Deinit all lanes (DataPathDeinit @ page 0x10 byte 128)
+	 */
+	rtn = sl_media_io_write8(media_jack, 0x10, 128, 0xFF);
+	if (rtn) {
+		sl_media_jack_fault_cause_set(media_jack, SL_MEDIA_FAULT_CAUSE_SHIFT_DOWN_JACK_IO);
+		sl_media_log_err_trace(media_jack, LOG_NAME, "data path deinit = 0xFF - write failed [%d]", rtn);
+		return rtn;
+	}
+	msleep(500);
+
+	/*
+	 * enable low power mode
+	 */
+	rtn = sl_media_data_jack_cable_low_power_set(media_jack);
+	if (rtn) {
+		sl_media_jack_fault_cause_set(media_jack, SL_MEDIA_FAULT_CAUSE_SHIFT_DOWN_JACK_IO_LOW_POWER_SET);
+		sl_media_log_err_trace(media_jack, LOG_NAME, "low power mode - write failed [%d]", rtn);
+		return rtn;
+	}
+	msleep(500);
+
+	/*
+	 * Staged Control Set 0, Data Path Configuration bytes @ page 0x10 bytes 145-148
+	 * Config lanes 1 to 4
+	 */
+	for (i = 0; i < 4; ++i) {
+		rtn = sl_media_io_write8(media_jack, 0x10, 145 + i,
+					 (media_jack->appsel_num_200_gaui << 4) |
+							   DATA_PATH_LOWER_LANE_CONFIG);
+		if (rtn) {
+			sl_media_jack_fault_cause_set(media_jack, SL_MEDIA_FAULT_CAUSE_SHIFT_DOWN_JACK_IO);
+			sl_media_log_err_trace(media_jack, LOG_NAME,
+					       "SCS0 configuration - config lanes 1-4 - write failed [%d]", rtn);
+			return rtn;
+		}
+	}
+	msleep(100);
+
+	/*
+	 * ApplyDPInitLane8-1
+	 */
+	rtn = sl_media_io_write8(media_jack, 0x10, 143, 0xFF);
+	if (rtn) {
+		sl_media_jack_fault_cause_set(media_jack, SL_MEDIA_FAULT_CAUSE_SHIFT_DOWN_JACK_IO);
+		sl_media_log_err_trace(media_jack, LOG_NAME, "apply dpinit = 0xFF - write failed [%d]", rtn);
+		return rtn;
+	}
+	msleep(500);
+
+	/*
+	 * enable high power mode
+	 */
+	rtn = sl_media_data_jack_cable_high_power_set(media_jack);
+	if (rtn) {
+		sl_media_jack_fault_cause_set(media_jack, SL_MEDIA_FAULT_CAUSE_SHIFT_DOWN_JACK_IO_HIGH_POWER_SET);
+		sl_media_log_err_trace(media_jack, LOG_NAME, "high power mode - write failed [%d]", rtn);
+		return rtn;
+	}
+	msleep(8000);
+
+	/*
+	 * (Re)Init all lanes (DataPathDeinit @ page 0x10 byte 128)
+	 */
+	rtn = sl_media_io_write8(media_jack, 0x10, 128, 0x00);
+	if (rtn) {
+		sl_media_jack_fault_cause_set(media_jack, SL_MEDIA_FAULT_CAUSE_SHIFT_DOWN_JACK_IO);
+		sl_media_log_err_trace(media_jack, LOG_NAME, "data path deinit = 0x00 - write failed [%d]", rtn);
+		return rtn;
+	}
+
+	/*
+	 * waiting for firmware reload
+	 */
+	msleep(3000);
+
+	return 0;
+}
+
+int sl_media_data_jack_cable_hw_shift_state_get(struct sl_media_jack *media_jack)
+{
+	int rtn;
+	int i;
+	u8  downshift_lower_lane_config;
+	u8  upshift_lower_lane_config;
+	u8  read_data[4];
+
+	sl_media_log_dbg(media_jack, LOG_NAME, "data jack cable hw shift state get");
+
+	downshift_lower_lane_config = (media_jack->appsel_num_200_gaui << 4) | DATA_PATH_LOWER_LANE_CONFIG;
+	upshift_lower_lane_config = (media_jack->appsel_num_400_gaui << 4) | DATA_PATH_LOWER_LANE_CONFIG;
+
+	for (i = 0; i < 4; ++i) {
+		rtn = sl_media_io_read8(media_jack, 0x10, 145 + i, &read_data[i]);
+		if (rtn) {
+			sl_media_log_err_trace(media_jack, LOG_NAME,
+					       "SCS0 configuration - config lanes 1-4 - read failed [%d]", rtn);
+			return SL_MEDIA_JACK_CABLE_HW_SHIFT_IO_ERROR;
+		}
+	}
+
+	if ((read_data[0] == downshift_lower_lane_config) &&
+	    (read_data[1] == downshift_lower_lane_config) &&
+	    (read_data[2] == downshift_lower_lane_config) &&
+	    (read_data[3] == downshift_lower_lane_config)) {
+		sl_media_log_dbg(media_jack, LOG_NAME, "cable is downshifted");
+		return SL_MEDIA_JACK_CABLE_HW_SHIFT_STATE_DOWNSHIFTED;
+	} else if ((read_data[0] == upshift_lower_lane_config) &&
+		   (read_data[1] == upshift_lower_lane_config) &&
+		   (read_data[2] == upshift_lower_lane_config) &&
+		   (read_data[3] == upshift_lower_lane_config)) {
+		sl_media_log_dbg(media_jack, LOG_NAME, "cable is upshifted");
+		return SL_MEDIA_JACK_CABLE_HW_SHIFT_STATE_UPSHIFTED;
+	}
+
+	sl_media_log_dbg(media_jack, LOG_NAME, "cable is in unknown shift state");
+	return SL_MEDIA_JACK_CABLE_HW_SHIFT_STATE_UNKNOWN;
+}
+
+int sl_media_data_jack_cable_upshift(struct sl_media_jack *media_jack)
+{
+	int rtn;
+	int i;
+
+	sl_media_log_dbg(media_jack, LOG_NAME, "data jack cable upshift");
+
+	/*
+	 * Deinit all lanes (DataPathDeinit @ page 0x10 byte 128)
+	 */
+	rtn = sl_media_io_write8(media_jack, 0x10, 128, 0xFF);
+	if (rtn) {
+		sl_media_jack_fault_cause_set(media_jack, SL_MEDIA_FAULT_CAUSE_SHIFT_UP_JACK_IO);
+		sl_media_log_err_trace(media_jack, LOG_NAME, "data path deinit = 0xFF - write failed [%d]", rtn);
+		return rtn;
+	}
+	msleep(500);
+
+	/*
+	 * enable low power mode
+	 */
+	rtn = sl_media_data_jack_cable_low_power_set(media_jack);
+	if (rtn) {
+		sl_media_jack_fault_cause_set(media_jack, SL_MEDIA_FAULT_CAUSE_SHIFT_UP_JACK_IO_LOW_POWER_SET);
+		sl_media_log_err_trace(media_jack, LOG_NAME, "low power mode - write failed [%d]", rtn);
+		return rtn;
+	}
+	msleep(500);
+
+	/*
+	 * Staged Control Set 0, Data Path Configuration bytes @ page 0x10 bytes 145-148
+	 * Config lanes 1 to 4
+	 */
+	for (i = 0; i < 4; ++i) {
+		rtn = sl_media_io_write8(media_jack, 0x10, 145 + i,
+					 (media_jack->appsel_num_400_gaui << 4) | DATA_PATH_LOWER_LANE_CONFIG);
+		if (rtn) {
+			sl_media_jack_fault_cause_set(media_jack, SL_MEDIA_FAULT_CAUSE_SHIFT_UP_JACK_IO);
+			sl_media_log_err_trace(media_jack, LOG_NAME,
+					       "SCS0 configuration - config lanes 1-4 - write failed [%d]", rtn);
+			return rtn;
+		}
+	}
+	msleep(100);
+
+	/*
+	 * ApplyDPInitLane8-1
+	 */
+	rtn = sl_media_io_write8(media_jack, 0x10, 143, 0xFF);
+	if (rtn) {
+		sl_media_jack_fault_cause_set(media_jack, SL_MEDIA_FAULT_CAUSE_SHIFT_UP_JACK_IO);
+		sl_media_log_err_trace(media_jack, LOG_NAME, "apply dpinit = 0xFF - write failed [%d]", rtn);
+		return rtn;
+	}
+	msleep(500);
+
+	/*
+	 * enable high power mode
+	 */
+	rtn = sl_media_data_jack_cable_high_power_set(media_jack);
+	if (rtn) {
+		sl_media_jack_fault_cause_set(media_jack, SL_MEDIA_FAULT_CAUSE_SHIFT_UP_JACK_IO_HIGH_POWER_SET);
+		sl_media_log_err_trace(media_jack, LOG_NAME, "high power mode - write failed [%d]", rtn);
+		return rtn;
+	}
+	msleep(8000);
+
+	/*
+	 * (Re)Init all lanes (DataPathDeinit @ page 0x10 byte 128)
+	 */
+	rtn = sl_media_io_write8(media_jack, 0x10, 128, 0x00);
+	if (rtn) {
+		sl_media_jack_fault_cause_set(media_jack, SL_MEDIA_FAULT_CAUSE_SHIFT_UP_JACK_IO);
+		sl_media_log_err_trace(media_jack, LOG_NAME, "data path deinit = 0x00 - write failed [%d]", rtn);
+		return rtn;
+	}
+
+	/*
+	 * waiting for firmware reload
+	 */
+	msleep(3000);
+
+	return 0;
+}
+
+int sl_media_data_jack_cable_soft_reset(struct sl_media_jack *media_jack)
+{
+	int rtn;
+
+	sl_media_log_dbg(media_jack, LOG_NAME, "data jack cable soft reset");
+
+	rtn = sl_media_io_write8(media_jack, 0x00, 0x1a, 0x08);
+	if (rtn)
+		return rtn;
+
+	msleep(300);
+
+	rtn = sl_media_io_write8(media_jack, 0x00, 0x1a, 0x00);
+	if (rtn)
+		return rtn;
+
+	/*
+	 * waiting for firmware reload
+	 */
+	msleep(3000);
+
+	return 0;
+}
+
+#define SL_MEDIA_POWER_UP_PAGE      0x00
+#define SL_MEDIA_CMIS_POWER_UP_ADDR 0x1a
+#define SL_MEDIA_CMIS_POWER_UP_DATA 0x00
+#define SL_MEDIA_SFF_POWER_UP_ADDR  0x5D
+#define SL_MEDIA_SFF_POWER_UP_DATA  0x0D
+int sl_media_data_jack_cable_high_power_set(struct sl_media_jack *media_jack)
+{
+	int rtn;
+	u8  addr;
+	u8  data;
+
+	if (sl_media_data_jack_media_is_format_cmis(media_jack)) {
+		addr = SL_MEDIA_CMIS_POWER_UP_ADDR;
+		data = SL_MEDIA_CMIS_POWER_UP_DATA;
+	} else {
+		addr = SL_MEDIA_SFF_POWER_UP_ADDR;
+		data = SL_MEDIA_SFF_POWER_UP_DATA;
+	}
+
+	sl_media_log_dbg(media_jack, LOG_NAME,
+			 "high power set (addr = 0x%X, data = 0x%X)", addr, data);
+
+	rtn = sl_media_io_write8(media_jack, SL_MEDIA_POWER_UP_PAGE, addr, data);
+	if (rtn) {
+		sl_media_log_err_trace(media_jack, LOG_NAME, "write8 failed [%d]", rtn);
+		return -EIO;
+	}
+
+	spin_lock(&media_jack->data_lock);
+	media_jack->is_high_powered = true;
+	spin_unlock(&media_jack->data_lock);
+
+	return 0;
+}
+
+#define SL_MEDIA_POWER_DOWN_PAGE      0x00
+#define SL_MEDIA_CMIS_POWER_DOWN_ADDR 0x1a
+#define SL_MEDIA_CMIS_POWER_DOWN_DATA 0x10
+#define SL_MEDIA_SFF_POWER_DOWN_ADDR  0x5D
+#define SL_MEDIA_SFF_POWER_DOWN_DATA  0x00
+int sl_media_data_jack_cable_low_power_set(struct sl_media_jack *media_jack)
+{
+	int rtn;
+	u8  addr;
+	u8  data;
+
+	if (sl_media_data_jack_media_is_format_cmis(media_jack)) {
+		addr = SL_MEDIA_CMIS_POWER_DOWN_ADDR;
+		data = SL_MEDIA_CMIS_POWER_DOWN_DATA;
+	} else {
+		addr = SL_MEDIA_SFF_POWER_DOWN_ADDR;
+		data = SL_MEDIA_SFF_POWER_DOWN_DATA;
+	}
+
+	sl_media_log_dbg(media_jack, LOG_NAME,
+			 "low power set (addr = 0x%X, data = 0x%X)", addr, data);
+
+	rtn = sl_media_io_write8(media_jack, SL_MEDIA_POWER_DOWN_PAGE, addr, data);
+	if (rtn) {
+		sl_media_log_err_trace(media_jack, LOG_NAME, "write8 failed [%d]", rtn);
+		return -EIO;
+	}
+
+	spin_lock(&media_jack->data_lock);
+	media_jack->is_high_powered = false;
+	spin_unlock(&media_jack->data_lock);
+
+	return 0;
+}
+
+int sl_media_data_jack_cable_temp_get(struct sl_media_jack *media_jack, u8 *temp)
+{
+	int rtn;
+	u8  data;
+
+	sl_media_log_dbg(media_jack, LOG_NAME, "data jack cable temp get");
+
+	if (!sl_media_lgrp_media_type_is_active(media_jack->cable_info[0].ldev_num,
+						media_jack->cable_info[0].lgrp_num)) {
+		sl_media_log_dbg(media_jack, LOG_NAME, "not active cable");
+		return -EBADRQC;
+	}
+
+	rtn = sl_media_io_read8(media_jack, 0, 14, &data);
+	if (rtn) {
+		sl_media_log_err_trace(media_jack, LOG_NAME, "temp get read failed [%d]", rtn);
+		return -EIO;
+	}
+
+	*temp = data;
+	return 0;
+}
+
+int sl_media_data_jack_cable_temp_warn_limit_get(struct sl_media_jack *media_jack, u8 *temp_warn_limit_c)
+{
+	int rtn;
+	u8  data;
+
+	sl_media_log_dbg(media_jack, LOG_NAME, "cable temp warn limit get");
+
+	if (!sl_media_lgrp_media_type_is_active(media_jack->cable_info[0].ldev_num,
+						media_jack->cable_info[0].lgrp_num)) {
+		sl_media_log_dbg(media_jack, LOG_NAME, "not active cable");
+		return -EBADRQC;
+	}
+
+	rtn = sl_media_io_read8(media_jack, 2, 132, &data);
+	if (rtn) {
+		sl_media_log_err_trace(media_jack, LOG_NAME, "cable temp warn limit read failed [%d]", rtn);
+		return -EIO;
+	}
+
+	*temp_warn_limit_c = data;
+	return 0;
+}
+
+int sl_media_data_jack_cable_temp_down_limit_get(struct sl_media_jack *media_jack, u8 *temp_down_limit_c)
+{
+	int rtn;
+	u8  data;
+
+	sl_media_log_dbg(media_jack, LOG_NAME, "cable temp down limit get");
+
+	if (!sl_media_lgrp_media_type_is_active(media_jack->cable_info[0].ldev_num,
+						media_jack->cable_info[0].lgrp_num)) {
+		sl_media_log_dbg(media_jack, LOG_NAME, "not active cable");
+		return -EBADRQC;
+	}
+
+	rtn = sl_media_io_read8(media_jack, 2, 128, &data);
+	if (rtn) {
+		sl_media_log_err_trace(media_jack, LOG_NAME, "cable temp down limit read failed [%d]", rtn);
+		return -EIO;
+	}
+
+	*temp_down_limit_c = data;
+	return 0;
+}
+
+void sl_media_data_jack_led_set(struct sl_media_jack *media_jack)
+{
+	int                  rtn;
+	struct sl_core_link *core_link;
+	u32                  link_state;
+	u8                   state;
+
+	sl_media_log_dbg(media_jack, LOG_NAME, "led set");
+
+	core_link = sl_core_link_get_pinned(media_jack->cable_info[0].ldev_num,
+					    media_jack->cable_info[0].lgrp_num, 0);
+	if (!core_link)
+		return;
+
+	/* hardcoding 0 since only one link*/
+	rtn = sl_core_link_state_get(media_jack->cable_info[0].ldev_num,
+				     media_jack->cable_info[0].lgrp_num, 0, &link_state);
+	sl_core_link_put_pinned(core_link);
+	if (rtn) {
+		sl_media_log_err_trace(media_jack, LOG_NAME, "core link state get failed [%d]", rtn);
+		return;
+	}
+
+	rtn = sl_media_jack_state_get(media_jack, &state);
+	if (rtn)
+		sl_media_log_err_trace(media_jack, LOG_NAME, "media_jack_state_get failed [%d]", rtn);
+
+	switch (state) {
+	case SL_MEDIA_JACK_CABLE_REMOVED:
+		sl_media_io_led_set(media_jack, LED_OFF);
+		return;
+	case SL_MEDIA_JACK_CABLE_ERROR:
+		sl_media_io_led_set(media_jack, LED_FAST_YEL);
+		return;
+	}
+
+	switch (link_state) {
+	case SL_CORE_LINK_STATE_UNCONFIGURED:
+	case SL_CORE_LINK_STATE_CANCELING:
+	case SL_CORE_LINK_STATE_DOWN:
+	case SL_CORE_LINK_STATE_GOING_DOWN:
+	case SL_CORE_LINK_STATE_TIMEOUT:
+		sl_media_io_led_set(media_jack, LED_OFF);
+		break;
+	case SL_CORE_LINK_STATE_GOING_UP:
+	case SL_CORE_LINK_STATE_AN:
+		sl_media_io_led_set(media_jack, LED_FAST_GRN);
+		break;
+	case SL_CORE_LINK_STATE_UP:
+		sl_media_io_led_set(media_jack, LED_ON_GRN);
+		break;
+	}
+}
+
+static inline u8 sl_media_data_jack_num_update(u8 physical_jack_num)
+{
+	return physical_jack_num - 1;
+}
+
+void sl_media_data_jack_cable_temp_monitor_start(struct sl_media_ldev *media_ldev)
+{
+}
+
+void sl_media_data_jack_cable_temp_monitor_stop(struct sl_media_ldev *media_ldev)
+{
+}
diff --git a/drivers/net/ethernet/hpe/sl/media/data/nic/sl_media_data_jack_emu.c b/drivers/net/ethernet/hpe/sl/media/data/nic/sl_media_data_jack_emu.c
new file mode 100644
index 000000000000..0aed275e8c5c
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/media/data/nic/sl_media_data_jack_emu.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2024,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+
+#include "sl_asic.h"
+
+#include "base/sl_media_log.h"
+
+#include "sl_media_lgrp.h"
+#include "sl_media_jack.h"
+#include "data/sl_media_data_jack.h"
+
+#define LOG_NAME SL_MEDIA_DATA_JACK_LOG_NAME
+
+int sl_media_data_jack_lgrp_connect(struct sl_media_lgrp *media_lgrp)
+{
+	struct sl_media_jack *media_jack;
+	u8                    i;
+
+	sl_media_log_dbg(media_lgrp, LOG_NAME, "jack lgrp connect");
+
+	media_jack = sl_media_data_jack_get(media_lgrp->media_ldev->num,
+					    media_lgrp->num >> (SL_MEDIA_LGRPS_DIVIDE_PER_PORT));
+	for (i = 0; i < SL_MEDIA_LGRPS_PER_PORT; ++i) {
+		if (media_jack->cable_info[i].lgrp_num == media_lgrp->num) {
+			media_lgrp->media_jack = media_jack;
+			media_lgrp->cable_info = &media_jack->cable_info[i];
+			return 0;
+		}
+	}
+
+	return -EFAULT;
+}
+
+void sl_media_data_jack_unregister_event_notifier(void)
+{
+}
diff --git a/drivers/net/ethernet/hpe/sl/media/data/nic/sl_media_data_ldev.c b/drivers/net/ethernet/hpe/sl/media/data/nic/sl_media_data_ldev.c
new file mode 100644
index 000000000000..a2cd33257fc5
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/media/data/nic/sl_media_data_ldev.c
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/errno.h>
+
+#include "base/sl_media_log.h"
+#include "sl_media_ldev.h"
+#include "data/sl_media_data_ldev.h"
+
+#define LOG_NAME  SL_LOG_LDEV_LOG_NAME
+
+int sl_media_data_ldev_uc_ops_set(u8 ldev_num, struct sl_uc_ops *uc_ops,
+				  struct sl_uc_accessor *uc_accessor)
+{
+	struct sl_media_ldev *media_ldev;
+
+	media_ldev = sl_media_ldev_get(ldev_num);
+	if (!media_ldev) {
+		sl_media_log_err(NULL, LOG_NAME, "ldev not found (ldev_num = %u)", ldev_num);
+		return -EINVAL;
+	}
+
+	sl_media_log_dbg(media_ldev, LOG_NAME, "media_data_ldev_uc_ops_set");
+
+	media_ldev->uc_ops = uc_ops;
+	media_ldev->uc_accessor = uc_accessor;
+
+	return 0;
+}
diff --git a/drivers/net/ethernet/hpe/sl/media/data/sl_media_data_cable_db_ops.c b/drivers/net/ethernet/hpe/sl/media/data/sl_media_data_cable_db_ops.c
new file mode 100644
index 000000000000..8099343084d8
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/media/data/sl_media_data_cable_db_ops.c
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2024,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/slab.h>
+#include <linux/kernel.h>
+
+#include <linux/hpe/sl/sl_media.h>
+
+#include "sl_media_jack.h"
+#include "data/sl_media_data_cable_db.h"
+#include "data/sl_media_data_cable_db_ops.h"
+#include "base/sl_media_log.h"
+
+#define LOG_NAME SL_MEDIA_CABLE_LOG_NAME
+
+#define SL_MEDIA_TYPE_SERDES 1
+
+int sl_media_data_cable_db_ops_cable_validate(struct sl_media_attr *media_attr, struct sl_media_jack *media_jack)
+{
+	int indexer;
+
+	sl_media_log_dbg(NULL, LOG_NAME, "cable validate");
+
+	/*
+	 * Check for loopback module
+	 */
+	if (media_attr->vendor == SL_MEDIA_VENDOR_MULTILANE) {
+		media_attr->hpe_pn       = 1;
+		media_attr->type         = SL_MEDIA_TYPE_PEC;
+		media_attr->length_cm    = 100;
+		media_attr->furcation    = SL_MEDIA_FURCATION_X1;
+		media_attr->max_speed    = SL_MEDIA_SPEEDS_SUPPORT_CK_400G;
+		media_attr->speeds_map   = SL_MEDIA_SPEEDS_SUPPORT_CK_400G |
+					   SL_MEDIA_SPEEDS_SUPPORT_BS_200G |
+					   SL_MEDIA_SPEEDS_SUPPORT_BJ_100G |
+					   SL_MEDIA_SPEEDS_SUPPORT_CD_50G;
+		media_jack->cable_db_idx = -1;
+		return 0;
+	}
+
+	/*
+	 * Linear search through the cable_db array
+	 */
+	for (indexer = 0; indexer < ARRAY_SIZE(cable_db); ++indexer) {
+		if (cable_db[indexer].hpe_pn == media_attr->hpe_pn &&
+		    cable_db[indexer].vendor == media_attr->vendor &&
+		    cable_db[indexer].type   == media_attr->type) {
+			media_attr->shape                    = cable_db[indexer].shape;
+			media_attr->max_speed                = cable_db[indexer].max_speed;
+			media_jack->is_supported_ss200_cable = cable_db[indexer].is_supported_ss200_cable;
+			media_jack->cable_db_idx             = indexer;
+			return 0;
+		}
+	}
+
+	return -ENOENT;
+}
+
+int sl_media_data_cable_db_ops_serdes_settings_get(struct sl_media_jack *media_jack, u32 media_type, u32 flags)
+{
+	sl_media_log_dbg(media_jack, LOG_NAME,
+			 "serdes settings get (media_type = 0x%X %s, flags = 0x%X)",
+		media_type, sl_media_type_str(media_type), flags);
+
+	if (flags & SL_MEDIA_TYPE_UNSUPPORTED) {
+		sl_media_log_warn_trace(media_jack, LOG_NAME, "serdes setting get unsuppported cable");
+		if (media_type == SL_MEDIA_TYPE_AEC ||
+		    media_type == SL_MEDIA_TYPE_ACC ||
+		    media_type == SL_MEDIA_TYPE_POC ||
+		    media_type == SL_MEDIA_TYPE_AOC) {
+			media_jack->serdes_settings.pre1   = -12;
+			media_jack->serdes_settings.pre2   = 0;
+			media_jack->serdes_settings.pre3   = 0;
+			media_jack->serdes_settings.cursor = 98;
+			media_jack->serdes_settings.post1  = -4;
+			media_jack->serdes_settings.post2  = 0;
+		} else {
+			media_jack->serdes_settings.pre1   = 0;
+			media_jack->serdes_settings.pre2   = 0;
+			media_jack->serdes_settings.pre3   = 0;
+			media_jack->serdes_settings.cursor = 100;
+			media_jack->serdes_settings.post1  = 0;
+			media_jack->serdes_settings.post2  = 0;
+		}
+	} else if (flags & SL_MEDIA_TYPE_BACKPLANE) {
+		media_jack->serdes_settings.pre1   = 0;
+		media_jack->serdes_settings.pre2   = 0;
+		media_jack->serdes_settings.pre3   = 0;
+		media_jack->serdes_settings.cursor = 100;
+		media_jack->serdes_settings.post1  = 0;
+		media_jack->serdes_settings.post2  = 0;
+	} else if (flags & SL_MEDIA_TYPE_LOOPBACK) {
+		media_jack->serdes_settings.pre1   = 0;
+		media_jack->serdes_settings.pre2   = 0;
+		media_jack->serdes_settings.pre3   = 0;
+		media_jack->serdes_settings.cursor = 100;
+		media_jack->serdes_settings.post1  = 0;
+		media_jack->serdes_settings.post2  = 0;
+	} else {
+		if (media_jack->cable_db_idx < 0 || media_jack->cable_db_idx >= ARRAY_SIZE(cable_db)) {
+			sl_media_log_err_trace(media_jack, LOG_NAME,
+					       "serdes settings get invalid (idx = %d)",
+					       media_jack->cable_db_idx);
+			return -ENOENT;
+		}
+		media_jack->serdes_settings = cable_db[media_jack->cable_db_idx].serdes_settings;
+	}
+	media_jack->serdes_settings.media = SL_MEDIA_TYPE_SERDES;
+
+	return 0;
+}
diff --git a/drivers/net/ethernet/hpe/sl/media/data/sl_media_data_jack.c b/drivers/net/ethernet/hpe/sl/media/data/sl_media_data_jack.c
new file mode 100644
index 000000000000..17631509afa2
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/media/data/sl_media_data_jack.c
@@ -0,0 +1,344 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2022,2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/slab.h>
+#include <linux/kernel.h>
+#include <linux/atomic.h>
+
+#include <linux/hpe/sl/sl_media.h>
+
+#include "base/sl_media_log.h"
+#include "sl_media_ldev.h"
+#include "sl_media_lgrp.h"
+#include "sl_media_jack.h"
+#include "data/sl_media_data_jack.h"
+#include "sl_asic.h"
+#include "sl_ctrl_lgrp_notif.h"
+#include "data/sl_media_data_lgrp.h"
+#include "sl_ctrl_lgrp.h"
+#include "sl_core_link.h"
+#include "sl_ctrl_media_counters.h"
+
+static struct sl_media_jack *media_jacks[SL_ASIC_MAX_LDEVS][SL_MEDIA_MAX_JACK_NUM];
+static DEFINE_SPINLOCK(media_jacks_lock);
+
+#define LOG_NAME SL_MEDIA_DATA_JACK_LOG_NAME
+
+void sl_media_data_jack_del(u8 ldev_num, u8 jack_num)
+{
+	struct sl_media_jack *media_jack;
+
+	media_jack = sl_media_data_jack_get(ldev_num, jack_num);
+	if (!media_jack) {
+		sl_media_log_dbg(NULL, LOG_NAME, "not found (jack_num = %u)", jack_num);
+		return;
+	}
+
+	sl_ctrl_media_cause_counters_del(media_jack);
+
+	spin_lock(&media_jacks_lock);
+	media_jacks[ldev_num][jack_num] = NULL;
+	spin_unlock(&media_jacks_lock);
+
+	sl_media_log_dbg(media_jack, LOG_NAME, "del (jack = 0x%p)", media_jack);
+
+	kfree(media_jack);
+}
+
+int sl_media_data_jack_new(struct sl_media_ldev *media_ldev, u8 jack_num)
+{
+	struct sl_media_jack *media_jack;
+	int                   rtn;
+
+	media_jack = sl_media_data_jack_get(media_ldev->num, jack_num);
+	if (media_jack) {
+		sl_media_log_err(NULL, LOG_NAME, "jack already exists");
+		return -EEXIST;
+	}
+
+	media_jack = kzalloc(sizeof(struct sl_media_jack), GFP_KERNEL);
+	if (!media_jack)
+		return -ENOMEM;
+
+	media_jack->magic             = SL_MEDIA_JACK_MAGIC;
+	media_jack->num               = jack_num;
+	media_jack->physical_num      = 1;
+	media_jack->cable_db_idx      = -1;
+	media_jack->fault_cause       = SL_MEDIA_FAULT_CAUSE_NONE;
+
+	spin_lock_init(&media_jack->log_lock);
+
+	rtn = sl_ctrl_media_cause_counters_init(media_jack);
+	if (rtn) {
+		sl_media_log_err(media_jack, LOG_NAME, "ctrl_media_cause_counters_init failed [%d]", rtn);
+		goto out;
+	}
+
+	spin_lock_init(&(media_jack->data_lock));
+
+	media_jack->media_ldev = media_ldev;
+
+	media_jack->state                  = SL_MEDIA_JACK_CABLE_REMOVED;
+	media_jack->lane_data.cache.cached = false;
+	media_jack->lane_data.read_state   = SL_MEDIA_JACK_LANE_DATA_READ_STATE_IDLE;
+	media_jack->lane_data.read_generation = 0;
+	init_waitqueue_head(&media_jack->lane_data.read_wait);
+
+	media_jack->temperature_value_c      = -1;
+	media_jack->temperature_down_limit_c = -1;
+	media_jack->temperature_warn_limit_c = -1;
+
+	sl_media_log_dbg(media_jack, LOG_NAME, "new (jack = 0x%p)", media_jack);
+
+	spin_lock(&media_jacks_lock);
+	media_jacks[media_ldev->num][jack_num] = media_jack;
+	spin_unlock(&media_jacks_lock);
+
+	return 0;
+
+out:
+	kfree(media_jack);
+	return -ENOMEM;
+}
+
+struct sl_media_jack *sl_media_data_jack_get(u8 ldev_num, u8 jack_num)
+{
+	struct sl_media_jack *media_jack;
+
+	spin_lock(&media_jacks_lock);
+	media_jack = media_jacks[ldev_num][jack_num];
+	spin_unlock(&media_jacks_lock);
+
+	sl_media_log_dbg(NULL, LOG_NAME,
+			 "get (ldev_num = %u, jack_num = %u, jack = 0x%p)",
+			 ldev_num, jack_num, media_jack);
+
+	return media_jack;
+}
+
+void sl_media_data_cable_serdes_settings_clr(struct sl_media_jack *media_jack)
+{
+	sl_media_log_dbg(media_jack, LOG_NAME, "serdes settings clr");
+
+	memset(&(media_jack->serdes_settings), 0, sizeof(struct sl_media_serdes_settings));
+}
+
+void sl_media_data_jack_eeprom_clr(struct sl_media_jack *media_jack)
+{
+	sl_media_log_dbg(media_jack, LOG_NAME, "eeprom clr");
+
+	memset(media_jack->eeprom_page0, 0, SL_MEDIA_EEPROM_PAGE_SIZE);
+	memset(media_jack->eeprom_page1, 0, SL_MEDIA_EEPROM_PAGE_SIZE);
+}
+
+/*
+ * This state describes the cable that is currently in the jack, so it must be
+ * cleared whenever the cable changes or the next cable inherits it. Client
+ * notification registrations, fake-cable debug state and counters belong to
+ * the jack and are kept. A stash that is still live behind a fake cable is
+ * kept too.
+ */
+void sl_media_data_jack_cable_state_clr(struct sl_media_jack *media_jack)
+{
+	unsigned int i;
+
+	sl_media_log_dbg(media_jack, LOG_NAME, "cable state clr");
+
+	spin_lock(&media_jack->data_lock);
+	media_jack->is_cable_unsupported        = false;
+	media_jack->is_cable_format_unsupported = false;
+	media_jack->is_supported_ss200_cable    = false;
+	media_jack->cable_db_idx                = -1;
+
+	media_jack->is_high_powered                = false;
+	media_jack->cable_high_power_wait_time_end = 0;
+
+	media_jack->cable_shift_state       = 0;
+	media_jack->appsel_num_200_gaui     = 0;
+	media_jack->lane_count_200_gaui     = 0;
+	media_jack->host_interface_200_gaui = 0;
+	media_jack->appsel_num_400_gaui     = 0;
+	media_jack->lane_count_400_gaui     = 0;
+	media_jack->host_interface_400_gaui = 0;
+
+	memset(&media_jack->lane_data.cache, 0, sizeof(media_jack->lane_data.cache));
+
+	media_jack->temperature_prev_state   = SL_MEDIA_JACK_TEMP_STATE_COLD;
+	media_jack->temperature_state        = SL_MEDIA_JACK_TEMP_STATE_COLD;
+	media_jack->temperature_value_c      = -1;
+	media_jack->temperature_warn_limit_c = -1;
+	media_jack->temperature_down_limit_c = -1;
+
+	for (i = 0; i < ARRAY_SIZE(media_jack->cable_info); ++i) {
+		struct sl_media_lgrp_cable_info *cable_info = &media_jack->cable_info[i];
+
+		if (cable_info->real_cable_status != CABLE_MEDIA_ATTR_STASHED)
+			memset(&cable_info->stashed_media_attr, 0,
+			       sizeof(cable_info->stashed_media_attr));
+		cable_info->hot_notif_sent  = false;
+		cable_info->warm_notif_sent = false;
+		cable_info->cold_notif_sent = false;
+	}
+	spin_unlock(&media_jack->data_lock);
+}
+
+int sl_media_data_jack_media_attr_set(struct sl_media_jack *media_jack,
+				      struct sl_media_lgrp_cable_info *cable_info, struct sl_media_attr *media_attr)
+{
+	sl_media_log_dbg(media_jack, LOG_NAME,
+			 "media attr set (format = %d, vendor = %d %s, type = 0x%X %s, length_cm = %d, speeds_map = 0x%lX)",
+			 media_attr->format, media_attr->vendor, sl_media_vendor_str(media_attr->vendor),
+			 media_attr->type, sl_media_type_str(media_attr->type),
+			 media_attr->length_cm, media_attr->speeds_map);
+
+	spin_lock(&media_jack->data_lock);
+
+	if (cable_info->real_cable_status == CABLE_MEDIA_ATTR_ADDED) {
+		sl_media_log_err_trace(media_jack, LOG_NAME, "media attr already set");
+		spin_unlock(&media_jack->data_lock);
+		return -EEXIST;
+	}
+
+	if (cable_info->fake_cable_status == CABLE_MEDIA_ATTR_ADDED) {
+		cable_info->stashed_media_attr = *media_attr;
+		cable_info->real_cable_status  = CABLE_MEDIA_ATTR_STASHED;
+	} else {
+		cable_info->media_attr        = *media_attr;
+		cable_info->real_cable_status = CABLE_MEDIA_ATTR_ADDED;
+	}
+
+	spin_unlock(&media_jack->data_lock);
+
+	return 0;
+}
+
+void sl_media_data_jack_media_attr_clr(struct sl_media_jack *media_jack,
+				       struct sl_media_lgrp_cable_info *cable_info)
+{
+	struct sl_media_lgrp *media_lgrp;
+
+	sl_media_log_dbg(media_jack, LOG_NAME, "media attr clr");
+
+	media_lgrp = sl_media_data_lgrp_get(cable_info->ldev_num, cable_info->lgrp_num);
+	spin_lock(&media_jack->data_lock);
+	if (cable_info->real_cable_status == CABLE_MEDIA_ATTR_REMOVED) {
+		spin_unlock(&media_jack->data_lock);
+		sl_media_log_dbg(media_jack, LOG_NAME, "no media attr to clear");
+		return;
+	}
+
+	if (cable_info->real_cable_status == CABLE_MEDIA_ATTR_ADDED)
+		memset(&(cable_info->media_attr), 0, sizeof(struct sl_media_attr));
+
+	cable_info->real_cable_status = CABLE_MEDIA_ATTR_REMOVED;
+	spin_unlock(&media_jack->data_lock);
+
+	if (media_lgrp) {
+		/* Only send notification if both real and fake cables are removed */
+		if (cable_info->fake_cable_status == CABLE_MEDIA_ATTR_REMOVED)
+			sl_media_data_jack_cable_if_not_present_send(media_lgrp);
+	}
+}
+
+bool sl_media_data_jack_media_is_format_cmis(struct sl_media_jack *media_jack)
+{
+	bool is_cmis;
+
+	spin_lock(&media_jack->data_lock);
+	is_cmis = (media_jack->cable_info[0].media_attr.format == SL_MEDIA_MGMT_IF_CMIS);
+	spin_unlock(&media_jack->data_lock);
+
+	return is_cmis;
+}
+
+void sl_media_data_jack_cable_if_present_send(struct sl_media_lgrp *media_lgrp)
+{
+	int                      rtn;
+	union sl_lgrp_notif_info info;
+
+	sl_media_log_dbg(media_lgrp, LOG_NAME, "present send");
+
+	spin_lock(&media_lgrp->media_jack->data_lock);
+	if ((media_lgrp->cable_info->real_cable_status == CABLE_MEDIA_ATTR_ADDED) ||
+	    (media_lgrp->cable_info->fake_cable_status == CABLE_MEDIA_ATTR_ADDED)) {
+		info.media_attr = media_lgrp->cable_info->media_attr;
+		rtn = sl_ctrl_lgrp_notif_enqueue(sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num),
+						 SL_LGRP_NOTIF_NO_LINK, SL_LGRP_NOTIF_MEDIA_PRESENT, &info, 0);
+		if (rtn)
+			sl_media_log_warn_trace(media_lgrp, LOG_NAME,
+						"present_send ctrl_lgrp_notif_enqueue failed [%d]", rtn);
+	}
+	spin_unlock(&media_lgrp->media_jack->data_lock);
+}
+
+void sl_media_data_jack_cable_if_not_present_send(struct sl_media_lgrp *media_lgrp)
+{
+	int rtn;
+
+	sl_media_log_dbg(media_lgrp, LOG_NAME, "not present send");
+
+	spin_lock(&media_lgrp->media_jack->data_lock);
+	if (media_lgrp->cable_info->real_cable_status == CABLE_MEDIA_ATTR_REMOVED) {
+		rtn = sl_ctrl_lgrp_notif_enqueue(sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num),
+						 SL_LGRP_NOTIF_NO_LINK, SL_LGRP_NOTIF_MEDIA_NOT_PRESENT, NULL, 0);
+		if (rtn)
+			sl_media_log_warn_trace(media_lgrp, LOG_NAME,
+						"not_present_send ctrl_lgrp_notif_enqueue failed [%d]", rtn);
+	}
+	spin_unlock(&media_lgrp->media_jack->data_lock);
+}
+
+void sl_media_data_jack_cable_temp_state_init(struct sl_media_jack *media_jack)
+{
+	spin_lock(&media_jack->data_lock);
+	media_jack->temperature_prev_state = SL_MEDIA_JACK_TEMP_STATE_COLD;
+	media_jack->temperature_state = SL_MEDIA_JACK_TEMP_STATE_COLD;
+	spin_unlock(&media_jack->data_lock);
+
+	sl_media_log_dbg(media_jack, LOG_NAME, "temperature state init (prev_state = %u, state = %u)",
+			 media_jack->temperature_prev_state, media_jack->temperature_state);
+}
+
+void sl_media_data_jack_cable_temp_state_set(struct sl_media_jack *media_jack, u8 temperature_state)
+{
+	spin_lock(&media_jack->data_lock);
+	media_jack->temperature_prev_state = media_jack->temperature_state;
+	media_jack->temperature_state = temperature_state;
+	spin_unlock(&media_jack->data_lock);
+
+	sl_media_log_dbg(media_jack, LOG_NAME, "temperature state set (state = %u)", media_jack->temperature_state);
+}
+
+int sl_media_data_jack_cable_temp_state_get(struct sl_media_jack *media_jack, u8 *temperature_state)
+{
+	spin_lock(&media_jack->data_lock);
+	*temperature_state = media_jack->temperature_state;
+	spin_unlock(&media_jack->data_lock);
+
+	sl_media_log_dbg(media_jack, LOG_NAME, "temperature state get (state = %u %s)",
+			 *temperature_state, sl_media_temp_state_str(*temperature_state));
+
+	return 0;
+}
+
+int  sl_media_data_jack_cable_temp_prev_state_get(struct sl_media_jack *media_jack, u8 *temperature_prev_state)
+{
+	spin_lock(&media_jack->data_lock);
+	*temperature_prev_state = media_jack->temperature_prev_state;
+	spin_unlock(&media_jack->data_lock);
+
+	sl_media_log_dbg(media_jack, LOG_NAME, "temperature prev state get (state = %u %s)",
+			 *temperature_prev_state, sl_media_temp_state_str(*temperature_prev_state));
+
+	return 0;
+}
+
+void sl_media_data_jack_headshell_busy_set(struct sl_media_jack *media_jack, int value)
+{
+	atomic_set(&media_jack->is_headshell_busy, value);
+}
+
+bool sl_media_data_jack_is_headshell_busy(struct sl_media_jack *media_jack)
+{
+	return (atomic_read(&media_jack->is_headshell_busy) == SL_MEDIA_JACK_HEADSHELL_BUSY);
+}
diff --git a/drivers/net/ethernet/hpe/sl/media/data/sl_media_data_ldev.c b/drivers/net/ethernet/hpe/sl/media/data/sl_media_data_ldev.c
new file mode 100644
index 000000000000..fddedcd46776
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/media/data/sl_media_data_ldev.c
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/spinlock.h>
+#include <linux/slab.h>
+
+#include <linux/hpe/sl/sl_media.h>
+
+#include "sl_asic.h"
+#include "base/sl_media_log.h"
+#include "sl_media_ldev.h"
+#include "data/sl_media_data_ldev.h"
+#include "data/sl_media_data_lgrp.h"
+#include "data/sl_media_data_jack.h"
+
+static struct sl_media_ldev *media_ldevs[SL_ASIC_MAX_LDEVS];
+static DEFINE_SPINLOCK(media_ldevs_lock);
+
+#define LOG_NAME SL_MEDIA_DATA_LDEV_LOG_NAME
+
+int sl_media_data_ldev_new(u8 ldev_num, struct workqueue_struct *workqueue)
+{
+	struct sl_media_ldev *media_ldev;
+	int                   rtn;
+	u8                    jack_num;
+
+	media_ldev = sl_media_data_ldev_get(ldev_num);
+	if (media_ldev) {
+		sl_media_log_err(NULL, LOG_NAME, "exists (ldev = 0x%p)", media_ldev);
+		return -EBADRQC;
+	}
+
+	media_ldev = kzalloc(sizeof(struct sl_media_ldev), GFP_KERNEL);
+	if (!media_ldev)
+		return -ENOMEM;
+
+	media_ldev->magic     = SL_MEDIA_LDEV_MAGIC;
+	media_ldev->num       = ldev_num;
+	media_ldev->workqueue = workqueue;
+
+	for (jack_num = 0; jack_num < SL_MEDIA_MAX_JACK_NUM; ++jack_num) {
+		rtn = sl_media_data_jack_new(media_ldev, jack_num);
+		if (rtn) {
+			sl_media_log_err(media_ldev, LOG_NAME, "jack new failed [%d]", rtn);
+			goto out_jacks;
+		}
+	}
+
+	rtn = sl_media_data_jack_scan(ldev_num);
+	if (rtn) {
+		sl_media_log_err(media_ldev, LOG_NAME, "jack scan failed [%d]", rtn);
+		goto out_jacks;
+	}
+
+	sl_media_log_dbg(media_ldev, LOG_NAME, "new (ldev = 0x%p)", media_ldev);
+
+	spin_lock(&media_ldevs_lock);
+	media_ldevs[ldev_num] = media_ldev;
+	spin_unlock(&media_ldevs_lock);
+
+	sl_media_data_jack_cable_temp_monitor_start(media_ldev);
+
+	return 0;
+
+out_jacks:
+	while (jack_num)
+		sl_media_data_jack_del(ldev_num, --jack_num);
+	kfree(media_ldev);
+	return -EFAULT;
+}
+
+void sl_media_data_ldev_del(u8 ldev_num)
+{
+	struct sl_media_ldev *media_ldev;
+	u8                    lgrp_num;
+	u8                    jack_num;
+
+	media_ldev = sl_media_data_ldev_get(ldev_num);
+	if (!media_ldev) {
+		sl_media_log_dbg(NULL, LOG_NAME, "not found (ldev_num = %u)", ldev_num);
+		return;
+	}
+
+	sl_media_data_jack_cable_temp_monitor_stop(media_ldev);
+
+	spin_lock(&media_ldevs_lock);
+	media_ldevs[ldev_num] = NULL;
+	spin_unlock(&media_ldevs_lock);
+
+	sl_media_log_dbg(media_ldev, LOG_NAME, "del (ldev = 0x%p)", media_ldev);
+
+	for (lgrp_num = 0; lgrp_num < SL_ASIC_MAX_LGRPS; ++lgrp_num)
+		sl_media_data_lgrp_del(ldev_num, lgrp_num);
+
+	for (jack_num = 0; jack_num < SL_MEDIA_MAX_JACK_NUM; ++jack_num)
+		sl_media_data_jack_del(ldev_num, jack_num);
+
+	sl_media_data_jack_unregister_event_notifier();
+
+	kfree(media_ldev);
+}
+
+struct sl_media_ldev *sl_media_data_ldev_get(u8 ldev_num)
+{
+	struct sl_media_ldev *media_ldev;
+
+	spin_lock(&media_ldevs_lock);
+	media_ldev = media_ldevs[ldev_num];
+	spin_unlock(&media_ldevs_lock);
+
+	sl_media_log_dbg(NULL, LOG_NAME, "get (ldev_num = %u, ldev = 0x%p)",
+			 ldev_num, media_ldev);
+
+	return media_ldev;
+}
diff --git a/drivers/net/ethernet/hpe/sl/media/data/sl_media_data_lgrp.c b/drivers/net/ethernet/hpe/sl/media/data/sl_media_data_lgrp.c
new file mode 100644
index 000000000000..27c30bdf3378
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/media/data/sl_media_data_lgrp.c
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/spinlock.h>
+#include <linux/slab.h>
+
+#include <linux/hpe/sl/sl_media.h>
+
+#include "sl_media_lgrp.h"
+#include "data/sl_media_data_lgrp.h"
+#include "data/sl_media_data_ldev.h"
+#include "data/sl_media_data_jack.h"
+#include "sl_asic.h"
+#include "base/sl_media_log.h"
+
+static struct sl_media_lgrp *media_lgrps[SL_ASIC_MAX_LDEVS][SL_ASIC_MAX_LGRPS];
+static DEFINE_SPINLOCK(media_lgrps_lock);
+
+#define LOG_NAME SL_MEDIA_DATA_LGRP_LOG_NAME
+
+int sl_media_data_lgrp_new(u8 ldev_num, u8 lgrp_num)
+{
+	struct sl_media_lgrp *media_lgrp;
+	int                   rtn;
+
+	media_lgrp = sl_media_data_lgrp_get(ldev_num, lgrp_num);
+	if (media_lgrp) {
+		sl_media_log_err(NULL, LOG_NAME, "exists (lgrp = 0x%p)", media_lgrp);
+		return -EBADRQC;
+	}
+
+	media_lgrp = kzalloc(sizeof(struct sl_media_lgrp), GFP_KERNEL);
+	if (!media_lgrp)
+		return -ENOMEM;
+
+	media_lgrp->magic       = SL_MEDIA_LGRP_MAGIC;
+	media_lgrp->num         = lgrp_num;
+	media_lgrp->media_ldev  = sl_media_data_ldev_get(ldev_num);
+
+	media_lgrp->speeds_kobj_init = false;
+	spin_lock_init(&media_lgrp->log_lock);
+	spin_lock_init(&media_lgrp->data_lock);
+	snprintf(media_lgrp->connect_id, sizeof(media_lgrp->connect_id), "lgrp%02u", lgrp_num);
+
+	rtn = sl_media_data_jack_lgrp_connect(media_lgrp);
+	if (rtn) {
+		sl_media_log_err(media_lgrp, LOG_NAME, "jack lgrp connect failed [%d]", rtn);
+		kfree(media_lgrp);
+		return -EFAULT;
+	}
+
+	sl_media_log_dbg(media_lgrp, LOG_NAME, "new (lgrp = 0x%p)", media_lgrp);
+
+	spin_lock(&media_lgrps_lock);
+	media_lgrps[ldev_num][lgrp_num] = media_lgrp;
+	spin_unlock(&media_lgrps_lock);
+
+	return 0;
+}
+
+void sl_media_data_lgrp_del(u8 ldev_num, u8 lgrp_num)
+{
+	struct sl_media_lgrp *media_lgrp;
+
+	media_lgrp = sl_media_data_lgrp_get(ldev_num, lgrp_num);
+	if (!media_lgrp) {
+		sl_media_log_dbg(NULL, LOG_NAME, "not found (lgrp_num = %u)", lgrp_num);
+		return;
+	}
+
+	spin_lock(&media_lgrps_lock);
+	media_lgrps[ldev_num][lgrp_num] = NULL;
+	spin_unlock(&media_lgrps_lock);
+
+	sl_media_log_dbg(media_lgrp, LOG_NAME, "del (lgrp = 0x%p)", media_lgrp);
+
+	kfree(media_lgrp);
+}
+
+struct sl_media_lgrp *sl_media_data_lgrp_get(u8 ldev_num, u8 lgrp_num)
+{
+	struct sl_media_lgrp *media_lgrp;
+
+	spin_lock(&media_lgrps_lock);
+	media_lgrp = media_lgrps[ldev_num][lgrp_num];
+	spin_unlock(&media_lgrps_lock);
+
+	sl_media_log_dbg(NULL, LOG_NAME,
+			 "get (ldev_num = %u, lgrp_num = %u, lgrp = 0x%p)",
+			 ldev_num, lgrp_num, media_lgrp);
+
+	return media_lgrp;
+}
+
+void sl_media_data_lgrp_connect_id_set(struct sl_media_lgrp *media_lgrp, const char *connect_id)
+{
+	unsigned long irq_flags;
+
+	spin_lock_irqsave(&(media_lgrp->log_lock), irq_flags);
+	strscpy_pad(media_lgrp->connect_id, connect_id,
+		    sizeof(media_lgrp->connect_id));
+	spin_unlock_irqrestore(&(media_lgrp->log_lock), irq_flags);
+
+	sl_media_log_dbg(media_lgrp, SL_MEDIA_DATA_LGRP_LOG_NAME, "connect_id = %s", connect_id);
+}
+
+int sl_media_data_lgrp_err_trace_enable_set(struct sl_media_lgrp *media_lgrp, bool err_trace_enable)
+{
+	spin_lock(&media_lgrp->data_lock);
+	media_lgrp->err_trace_enable = err_trace_enable;
+	spin_unlock(&media_lgrp->data_lock);
+
+	sl_media_log_dbg(media_lgrp, LOG_NAME, "set (err_trace_enable = %s)", err_trace_enable ? "true" : "false");
+
+	return 0;
+}
+
+int sl_media_data_lgrp_warn_trace_enable_set(struct sl_media_lgrp *media_lgrp, bool warn_trace_enable)
+{
+	spin_lock(&media_lgrp->data_lock);
+	media_lgrp->warn_trace_enable = warn_trace_enable;
+	spin_unlock(&media_lgrp->data_lock);
+
+	sl_media_log_dbg(media_lgrp, LOG_NAME, "set (warn_trace_enable = %s)", warn_trace_enable ? "true" : "false");
+
+	return 0;
+}
diff --git a/drivers/net/ethernet/hpe/sl/media/data/sl_media_data_lgrp_trace.c b/drivers/net/ethernet/hpe/sl/media/data/sl_media_data_lgrp_trace.c
new file mode 100644
index 000000000000..aec8a52d1cc0
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/media/data/sl_media_data_lgrp_trace.c
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/spinlock.h>
+
+#include "data/sl_media_data_lgrp_trace.h"
+
+#define LOG_NAME SL_MEDIA_DATA_LGRP_LOG_NAME
+
+int sl_media_data_lgrp_is_err_trace_enabled(struct sl_media_lgrp *media_lgrp, bool *err_trace_enable)
+{
+	spin_lock(&media_lgrp->data_lock);
+	*err_trace_enable = media_lgrp->err_trace_enable;
+	spin_unlock(&media_lgrp->data_lock);
+
+	sl_media_log_dbg(media_lgrp, LOG_NAME, "get (err_trace_enable = %s)", *err_trace_enable ? "true" : "false");
+
+	return 0;
+}
+
+int sl_media_data_lgrp_is_warn_trace_enabled(struct sl_media_lgrp *media_lgrp, bool *warn_trace_enable)
+{
+	spin_lock(&media_lgrp->data_lock);
+	*warn_trace_enable = media_lgrp->warn_trace_enable;
+	spin_unlock(&media_lgrp->data_lock);
+
+	sl_media_log_dbg(media_lgrp, LOG_NAME, "get (warn_trace_enable = %s)", *warn_trace_enable ? "true" : "false");
+
+	return 0;
+}
diff --git a/drivers/net/ethernet/hpe/sl/media/nic/sl_media_io.c b/drivers/net/ethernet/hpe/sl/media/nic/sl_media_io.c
new file mode 100644
index 000000000000..e031d82b104b
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/media/nic/sl_media_io.c
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2024,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/hpe/sl/sl_ldev.h>
+
+#include "sl_media_ldev.h"
+#include "sl_media_io.h"
+#include "sl_media_jack.h"
+#include "base/sl_media_log.h"
+
+#define LOG_NAME SL_MEDIA_IO_LOG_NAME
+
+int sl_media_io_write8(struct sl_media_jack *media_jack, u8 page, u8 offset, u8 data)
+{
+	struct sl_media_ldev *media_ldev;
+
+	media_ldev = media_jack->media_ldev;
+
+	sl_media_log_dbg(media_jack, LOG_NAME, "media_io_write8 0x%x <- 0x%x", offset, data);
+
+	return media_ldev->uc_ops->uc_write8(media_ldev->uc_accessor->uc, page, offset, data);
+}
+
+int sl_media_io_read(struct sl_media_jack *media_jack, u8 page, u8 offset, u8 *data, size_t len)
+{
+	int                   rtn_len;
+	struct sl_media_ldev *media_ldev;
+
+	media_ldev = media_jack->media_ldev;
+
+	rtn_len = media_ldev->uc_ops->uc_read(media_ldev->uc_accessor->uc, (u32)offset, (u32)page, data, len);
+	if (rtn_len < 0) {
+		sl_media_log_err_trace(media_jack, LOG_NAME, "media_io_read failed [%d]", rtn_len);
+		return rtn_len;
+	}
+
+	if (rtn_len != len) {
+		sl_media_log_err_trace(media_jack, LOG_NAME,
+				       "media_io_read length mismatch (expected = %zu, returned = %d)", len, rtn_len);
+		return -EIO;
+	}
+
+	sl_media_log_dbg(media_jack, LOG_NAME,
+			 "media_io_read (page = 0x%X, offset = 0x%X, rtn_len = %d)", page, offset, rtn_len);
+
+	return 0;
+}
+
+int sl_media_io_read8(struct sl_media_jack *media_jack, u8 page, u8 offset, u8 *data)
+{
+	return sl_media_io_read(media_jack, page, offset, data, 1);
+}
+
+void sl_media_io_led_set(struct sl_media_jack *media_jack, u8 led_pattern)
+{
+	struct sl_media_ldev *media_ldev;
+
+	sl_media_log_dbg(media_jack, LOG_NAME, "media_io_led_set (pattern = %u)", led_pattern);
+
+	media_ldev = media_jack->media_ldev;
+
+	media_ldev->uc_ops->uc_led_set(media_ldev->uc_accessor->uc, led_pattern);
+}
diff --git a/drivers/net/ethernet/hpe/sl/media/nic/sl_media_jack.c b/drivers/net/ethernet/hpe/sl/media/nic/sl_media_jack.c
new file mode 100644
index 000000000000..33f1a2a20ab7
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/media/nic/sl_media_jack.c
@@ -0,0 +1,315 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2024,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/string.h>
+
+#include <linux/hpe/sl/sl_media.h>
+
+#include "sl_asic.h"
+#include "sl_sysfs.h"
+#include "sl_media_jack.h"
+#include "sl_media_lgrp.h"
+#include "data/sl_media_data_jack.h"
+#include "data/sl_media_data_lgrp.h"
+#include "data/sl_media_data_cable_db_ops.h"
+#include "base/sl_media_log.h"
+#include "base/sl_media_eeprom.h"
+
+#define LOG_NAME SL_MEDIA_JACK_LOG_NAME
+
+#define FLAT_MEM_OFFSET 2
+#define FLAT_MEM_BIT    7
+static int sl_media_data_jack_eeprom_page1_get(struct sl_media_jack *media_jack, u8 *eeprom_page1)
+{
+	sl_media_log_dbg(media_jack, LOG_NAME, "eeprom page1 get");
+
+	if ((media_jack->eeprom_page0[FLAT_MEM_OFFSET] & BIT(FLAT_MEM_BIT)) != 0) {
+		sl_media_log_dbg(media_jack, LOG_NAME, "no page1 in eeprom");
+		return 0;
+	}
+
+	memcpy(media_jack->eeprom_page1, eeprom_page1, SL_MEDIA_EEPROM_PAGE_SIZE);
+
+	return 0;
+}
+
+static int sl_media_jack_cable_attr_set(struct sl_media_jack *media_jack, u8 ldev_num, u8 lgrp_num,
+					struct sl_media_attr *media_attr)
+{
+	int rtn;
+
+	sl_media_log_dbg(media_jack, LOG_NAME, "cable attr set");
+
+	/*
+	 * only first element is valid in cable_info since single lgrp on nic
+	 */
+	media_jack->cable_info[0].ldev_num = ldev_num;
+	media_jack->cable_info[0].lgrp_num = lgrp_num;
+
+	rtn = sl_media_data_jack_media_attr_set(media_jack, &media_jack->cable_info[0], media_attr);
+	if (rtn) {
+		sl_media_log_err_trace(media_jack, LOG_NAME, "media attr set failed [%d]", rtn);
+		sl_media_jack_fault_cause_set(media_jack, SL_MEDIA_FAULT_CAUSE_MEDIA_ATTR_SET);
+		return rtn;
+	}
+
+	return 0;
+}
+
+static void sl_media_jack_cable_attr_errors_update(struct sl_media_jack *media_jack, u32 errors)
+{
+	sl_media_log_dbg(media_jack, LOG_NAME, "cable attr errors update");
+
+	/*
+	 * only first element is valid in cable_info since single lgrp on nic
+	 */
+	media_jack->cable_info[0].media_attr.errors |= errors;
+}
+
+static void sl_media_data_jack_cable_attr_send(struct sl_media_jack *media_jack)
+{
+	struct sl_media_lgrp *media_lgrp;
+
+	sl_media_log_dbg(media_jack, LOG_NAME, "cable attr send");
+
+	/*
+	 * only first element is valid in cable_info since single lgrp on nic
+	 */
+	media_lgrp = sl_media_data_lgrp_get(media_jack->cable_info[0].ldev_num,
+					    media_jack->cable_info[0].lgrp_num);
+	if (media_lgrp)
+		sl_media_data_jack_cable_if_present_send(media_lgrp);
+}
+
+int sl_media_jack_cable_insert(u8 ldev_num, u8 lgrp_num, u8 jack_num,
+			       u8 *eeprom_page0, u8 *eeprom_page1, u32 flags)
+{
+	int                   rtn;
+	struct sl_media_attr  media_attr;
+	struct sl_media_jack *media_jack;
+
+	media_jack = sl_media_data_jack_get(ldev_num, jack_num);
+	if (!media_jack) {
+		sl_media_log_err(NULL, LOG_NAME, "media_data_jack_get failed");
+		return -EFAULT;
+	}
+
+	sl_media_log_dbg(media_jack, LOG_NAME, "cable insert");
+
+	/* Start clean so nothing from the previous cable is inherited */
+	sl_media_data_jack_cable_state_clr(media_jack);
+
+	sl_media_jack_fault_cause_set(media_jack, SL_MEDIA_FAULT_CAUSE_NONE);
+
+	memset(&media_attr, 0, sizeof(struct sl_media_attr));
+
+	media_attr.magic    = SL_MEDIA_ATTR_MAGIC;
+	media_attr.ver      = SL_MEDIA_ATTR_VER;
+	media_attr.size     = sizeof(struct sl_media_attr);
+	media_attr.errors   = 0;
+	media_attr.info     = 0;
+
+	if (flags & SL_MEDIA_TYPE_BACKPLANE) {
+		media_attr.vendor        = SL_MEDIA_VENDOR_HPE;
+		media_attr.type          = SL_MEDIA_TYPE_BKP;
+		media_attr.info          = SL_MEDIA_INFO_AUTONEG;
+		media_attr.length_cm     = 25;
+		media_attr.hpe_pn        = 60821555;
+		media_attr.furcation     = SL_MEDIA_FURCATION_X1;
+		media_attr.speeds_map    = SL_MEDIA_SPEEDS_SUPPORT_CK_400G |
+					   SL_MEDIA_SPEEDS_SUPPORT_CK_200G |
+					   SL_MEDIA_SPEEDS_SUPPORT_BS_200G |
+					   SL_MEDIA_SPEEDS_SUPPORT_CK_100G |
+					   SL_MEDIA_SPEEDS_SUPPORT_CD_100G |
+					   SL_MEDIA_SPEEDS_SUPPORT_BJ_100G |
+					   SL_MEDIA_SPEEDS_SUPPORT_CD_50G;
+		media_attr.max_speed     = SL_MEDIA_SPEEDS_SUPPORT_CK_400G;
+		media_attr.jack_type     = SL_MEDIA_JACK_TYPE_BACKPLANE;
+		strscpy_pad(media_attr.serial_num_str, "AK20212120", sizeof(media_attr.serial_num_str));
+		strscpy_pad(media_attr.hpe_pn_str, "PK60821-555", sizeof(media_attr.hpe_pn_str));
+		strscpy_pad(media_attr.date_code_str, "08-19-21", sizeof(media_attr.date_code_str));
+		memset(media_attr.fw_ver, 0, sizeof(media_attr.fw_ver));
+	} else {
+		memcpy(media_jack->eeprom_page0, eeprom_page0, SL_MEDIA_EEPROM_PAGE_SIZE);
+
+		sl_media_data_jack_eeprom_page1_get(media_jack, eeprom_page1);
+
+		rtn = sl_media_eeprom_format_get(media_jack, &(media_attr.format));
+		if (rtn) {
+			sl_media_log_warn_trace(media_jack, LOG_NAME, "eeprom format unsupported");
+			memset(&media_attr, 0, sizeof(struct sl_media_attr));
+			media_attr.errors |= SL_MEDIA_ERROR_CABLE_FORMAT_UNSUPPORTED;
+			media_attr.errors |= SL_MEDIA_ERROR_TRYABLE;
+			rtn = sl_media_jack_cable_attr_set(media_jack, ldev_num, lgrp_num, &media_attr);
+			if (rtn)
+				sl_media_log_err_trace(media_jack, LOG_NAME, "cable attr set failed [%d]", rtn);
+			sl_media_data_jack_cable_attr_send(media_jack);
+			return 0;
+		}
+
+		sl_media_eeprom_parse(media_jack, &media_attr);
+
+		if (media_attr.type == SL_MEDIA_TYPE_PEC)
+			media_attr.info |= SL_MEDIA_INFO_AUTONEG;
+
+		rtn = sl_media_data_cable_db_ops_cable_validate(&media_attr, media_jack);
+		if (rtn) {
+			sl_media_log_warn_trace(media_jack, LOG_NAME,
+						"cable validate failed [%d] (vendor = %d %s, type = 0x%X %s, length_cm = %d, speeds = 0x%lX)",
+						rtn, media_attr.vendor, sl_media_vendor_str(media_attr.vendor),
+						media_attr.type, sl_media_type_str(media_attr.type),
+						media_attr.length_cm, media_attr.speeds_map);
+
+			media_jack->is_cable_unsupported = true;
+			media_attr.errors |= SL_MEDIA_ERROR_CABLE_UNSUPPORTED;
+			media_attr.errors |= SL_MEDIA_ERROR_TRYABLE;
+		}
+
+		if (SL_MEDIA_LGRP_MEDIA_TYPE_IS_ACTIVE(media_attr.type) &&
+		    !media_jack->is_cable_unsupported && !media_jack->is_supported_ss200_cable) {
+			if (!sl_media_eeprom_is_fw_version_supported(media_jack, &media_attr)) {
+				sl_media_log_warn_trace(media_jack, LOG_NAME, "eeprom fw version unsupported");
+				media_attr.errors |= SL_MEDIA_ERROR_CABLE_FW_UNSUPPORTED;
+				media_attr.errors |= SL_MEDIA_ERROR_TRYABLE;
+			}
+			/*
+			 * disallow BJ100 speed on active cables
+			 */
+			media_attr.speeds_map &= ~SL_MEDIA_SPEEDS_SUPPORT_BJ_100G;
+		}
+
+		if (media_jack->is_supported_ss200_cable) {
+			media_attr.speeds_map  = 0;
+			media_attr.speeds_map |= SL_MEDIA_SPEEDS_SUPPORT_BS_200G;
+			media_attr.speeds_map |= SL_MEDIA_SPEEDS_SUPPORT_CD_100G;
+			media_attr.speeds_map |= SL_MEDIA_SPEEDS_SUPPORT_CD_50G;
+			media_attr.info       |= SL_MEDIA_INFO_SUPPORTED_SS200_CABLE;
+		}
+
+		media_attr.jack_type = SL_MEDIA_JACK_TYPE_QSFP;
+		media_attr.jack_type_info.qsfp.density = SL_MEDIA_QSFP_DENSITY_SINGLE;
+	}
+
+	rtn = sl_media_jack_cable_attr_set(media_jack, ldev_num, lgrp_num, &media_attr);
+	if (rtn) {
+		sl_media_log_err_trace(media_jack, LOG_NAME, "cable attr set failed [%d]", rtn);
+		return 0;
+	}
+
+	if (media_jack->is_cable_unsupported)
+		flags |= SL_MEDIA_TYPE_UNSUPPORTED;
+	if (media_attr.vendor == SL_MEDIA_VENDOR_MULTILANE)
+		flags |= SL_MEDIA_TYPE_LOOPBACK;
+	rtn = sl_media_data_cable_db_ops_serdes_settings_get(media_jack, media_attr.type, flags);
+	if (rtn) {
+		sl_media_log_err_trace(media_jack, LOG_NAME, "serdes settings get failed [%d]", rtn);
+		sl_media_jack_fault_cause_set(media_jack, SL_MEDIA_FAULT_CAUSE_SERDES_SETTINGS_GET);
+		sl_media_data_jack_cable_attr_send(media_jack);
+		return 0;
+	}
+
+	if (SL_MEDIA_LGRP_MEDIA_TYPE_IS_ACTIVE(media_attr.type)) {
+		rtn = sl_media_data_jack_cable_soft_reset(media_jack);
+		if (rtn) {
+			sl_media_log_err_trace(media_jack, LOG_NAME, "cable soft reset failed [%d]", rtn);
+			sl_media_jack_state_set(media_jack, SL_MEDIA_JACK_CABLE_ERROR);
+			sl_media_jack_cable_attr_errors_update(media_jack, SL_MEDIA_ERROR_CABLE_HEADSHELL_FAULT);
+			sl_media_data_jack_cable_attr_send(media_jack);
+			return rtn;
+		}
+
+		/* must be last in the sequence because it needs time to load firmware */
+		rtn = sl_media_jack_cable_high_power_set(ldev_num, jack_num);
+		if (rtn) {
+			sl_media_log_err_trace(media_jack, LOG_NAME, "cable high power set failed [%d]", rtn);
+			sl_media_jack_state_set(media_jack, SL_MEDIA_JACK_CABLE_ERROR);
+			sl_media_jack_cable_attr_errors_update(media_jack, SL_MEDIA_ERROR_CABLE_HEADSHELL_FAULT);
+			sl_media_data_jack_cable_attr_send(media_jack);
+			return 0;
+		}
+	}
+
+	rtn = sl_sysfs_media_speeds_create(ldev_num, lgrp_num);
+	if (rtn) {
+		sl_media_log_err_trace(media_jack, LOG_NAME, "media speeds create failed [%d]", rtn);
+		sl_media_data_jack_cable_attr_send(media_jack);
+		return rtn;
+	}
+
+	if (SL_MEDIA_LGRP_MEDIA_TYPE_IS_ACTIVE(media_attr.type)) {
+		if (sl_media_data_jack_cable_hw_shift_state_get(media_jack) ==
+		    SL_MEDIA_JACK_CABLE_HW_SHIFT_STATE_DOWNSHIFTED)
+			sl_media_jack_cable_shift_state_set(media_jack, SL_MEDIA_JACK_CABLE_SHIFT_STATE_DOWNSHIFTED);
+		else if (sl_media_data_jack_cable_hw_shift_state_get(media_jack) ==
+			 SL_MEDIA_JACK_CABLE_HW_SHIFT_STATE_UPSHIFTED)
+			sl_media_jack_cable_shift_state_set(media_jack, SL_MEDIA_JACK_CABLE_SHIFT_STATE_UPSHIFTED);
+		else
+			sl_media_jack_cable_shift_state_set(media_jack, SL_MEDIA_JACK_CABLE_SHIFT_STATE_NOTSHIFTED);
+	}
+
+	sl_media_jack_state_set(media_jack, SL_MEDIA_JACK_CABLE_ONLINE);
+
+	sl_media_data_jack_cable_attr_send(media_jack);
+
+	return 0;
+}
+
+int sl_media_jack_cable_remove(u8 ldev_num, u8 lgrp_num, u8 jack_num)
+{
+	struct sl_media_jack *media_jack;
+
+	media_jack = sl_media_data_jack_get(ldev_num, jack_num);
+	if (!media_jack) {
+		sl_media_log_err(NULL, LOG_NAME, "media_data_jack_get failed");
+		return -EFAULT;
+	}
+
+	sl_media_log_dbg(media_jack, LOG_NAME, "cable remove");
+
+	sl_sysfs_media_speeds_delete(ldev_num, lgrp_num);
+
+	/*
+	 * only first element is valid in cable_info since single lgrp on nic
+	 */
+	sl_media_data_jack_media_attr_clr(media_jack, &media_jack->cable_info[0]);
+	sl_media_data_cable_serdes_settings_clr(media_jack);
+	sl_media_data_jack_eeprom_clr(media_jack);
+	sl_media_data_jack_cable_state_clr(media_jack);
+
+	sl_media_jack_state_set(media_jack, SL_MEDIA_JACK_CABLE_REMOVED);
+	sl_media_jack_fault_cause_set(media_jack, SL_MEDIA_FAULT_CAUSE_NONE);
+
+	return 0;
+}
+
+int sl_media_jack_cable_temp_hw_check(struct sl_media_jack *media_jack)
+{
+	return SL_MEDIA_JACK_TEMP_STATE_COLD;
+}
+
+void sl_media_jack_cable_hot_notif_send(struct sl_media_jack *media_jack)
+{
+}
+
+void sl_media_jack_cable_warm_notif_send(struct sl_media_jack *media_jack)
+{
+}
+
+void sl_media_jack_cable_cold_notif_send(struct sl_media_jack *media_jack)
+{
+}
+
+void sl_media_jack_cable_hot_notif_sent_set(struct sl_media_jack *media_jack,
+					    struct sl_media_lgrp_cable_info *cable_info, bool value)
+{
+}
+
+void sl_media_jack_cable_warm_notif_sent_set(struct sl_media_jack *media_jack,
+					     struct sl_media_lgrp_cable_info *cable_info, bool value)
+{
+}
+
+void sl_media_jack_cable_cold_notif_sent_set(struct sl_media_jack *media_jack,
+					     struct sl_media_lgrp_cable_info *cable_info, bool value)
+{
+}
diff --git a/drivers/net/ethernet/hpe/sl/media/nic/sl_media_ldev.c b/drivers/net/ethernet/hpe/sl/media/nic/sl_media_ldev.c
new file mode 100644
index 000000000000..6902223eb76a
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/media/nic/sl_media_ldev.c
@@ -0,0 +1,13 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+
+#include "sl_media_ldev.h"
+#include "data/sl_media_data_ldev.h"
+
+int sl_media_ldev_uc_ops_set(u8 ldev_num, struct sl_uc_ops *uc_ops,
+			     struct sl_uc_accessor *uc_accessor)
+{
+	return sl_media_data_ldev_uc_ops_set(ldev_num, uc_ops, uc_accessor);
+}
diff --git a/drivers/net/ethernet/hpe/sl/media/sl_media_jack.c b/drivers/net/ethernet/hpe/sl/media/sl_media_jack.c
new file mode 100644
index 000000000000..14be1d19c097
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/media/sl_media_jack.c
@@ -0,0 +1,1067 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2024-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/delay.h>
+
+#include "sl_asic.h"
+#include "sl_core_link.h"
+#include "sl_media_jack.h"
+#include "sl_media_lgrp.h"
+#include "sl_media_io.h"
+#include "data/sl_media_data_jack.h"
+#include "base/sl_media_log.h"
+
+#define LOG_NAME SL_MEDIA_JACK_LOG_NAME
+
+#define SL_MEDIA_JACK_SIGNAL_CACHE_LIFETIME_MS 1200
+#define SL_MEDIA_JACK_SIGNAL_READ_TIMEOUT_MS   (2 * SL_MEDIA_JACK_SIGNAL_CACHE_LIFETIME_MS)
+#define SL_MEDIA_JACK_MAX_NUM_LANE_DATA_READS  4
+#define SL_MEDIA_JACK_LANE_DATA_POLL_TIME_MS   (SL_MEDIA_JACK_SIGNAL_CACHE_LIFETIME_MS / \
+						SL_MEDIA_JACK_MAX_NUM_LANE_DATA_READS)
+
+#define SWAP_BYTE_NIBBLE(_x) ({                    \
+	typeof(_x) __x = (_x);                     \
+	((__x & 0x0F) << 4) | ((__x & 0xF0) >> 4); \
+})
+
+#define MEDIA_LANE_DP_STATE_GET(_lane_data, _lane_num) ({ \
+	typeof(_lane_data) __lane_data = (_lane_data);    \
+	typeof(_lane_num)  __lane_num  = (_lane_num);     \
+	(__lane_data)->dp_states[__lane_num / 2] >>       \
+		(4 * (__lane_num & 1)) & 0x0F;            \
+})
+
+#define SL_MEDIA_JACK_SIGNAL_INFO_ALLOWED(_dp_state) ({         \
+	typeof(_dp_state) __dp_state = (_dp_state);             \
+	((__dp_state) == SL_MEDIA_JACK_DP_STATE_ACTIVATED)   || \
+	((__dp_state) == SL_MEDIA_JACK_DP_STATE_TX_TURN_ON)  || \
+	((__dp_state) == SL_MEDIA_JACK_DP_STATE_TX_TURN_OFF) || \
+	((__dp_state) == SL_MEDIA_JACK_DP_STATE_INITIALIZED);   \
+})
+
+enum sl_media_cable_shift {
+	SL_MEDIA_JACK_CABLE_DOWNSHIFT,
+	SL_MEDIA_JACK_CABLE_UPSHIFT,
+};
+
+int sl_media_jack_new(struct sl_media_ldev *media_ldev, u8 jack_num)
+{
+	return sl_media_data_jack_new(media_ldev, jack_num);
+}
+
+void sl_media_jack_del(u8 ldev_num, u8 jack_num)
+{
+	sl_media_data_jack_del(ldev_num, jack_num);
+}
+
+struct sl_media_jack *sl_media_jack_get(u8 ldev_num, u8 jack_num)
+{
+	return sl_media_data_jack_get(ldev_num, jack_num);
+}
+
+void sl_media_jack_state_set(struct sl_media_jack *media_jack, u8 jack_state)
+{
+	spin_lock(&media_jack->data_lock);
+	media_jack->state = jack_state;
+	spin_unlock(&media_jack->data_lock);
+
+	sl_media_data_jack_led_set(media_jack);
+}
+
+int sl_media_jack_state_get(struct sl_media_jack *media_jack, u8 *state)
+{
+	spin_lock(&media_jack->data_lock);
+	*state = media_jack->state;
+	spin_unlock(&media_jack->data_lock);
+
+	return 0;
+}
+
+int sl_media_jack_cable_end_get(struct sl_media_jack *media_jack, u8 *cable_end)
+{
+	spin_lock(&media_jack->data_lock);
+	*cable_end = media_jack->cable_end;
+	spin_unlock(&media_jack->data_lock);
+
+	return 0;
+}
+
+bool sl_media_jack_is_high_powered(struct sl_media_jack *media_jack)
+{
+	bool is_high_powered;
+
+	spin_lock(&media_jack->data_lock);
+	is_high_powered = media_jack->is_high_powered;
+	spin_unlock(&media_jack->data_lock);
+
+	return is_high_powered;
+}
+
+void sl_media_jack_cable_shift_state_set(struct sl_media_jack *media_jack, u8 state)
+{
+	spin_lock(&media_jack->data_lock);
+	media_jack->cable_shift_state = state;
+	spin_unlock(&media_jack->data_lock);
+
+	sl_media_log_dbg(media_jack, LOG_NAME, "cable shift state set = %u", media_jack->cable_shift_state);
+}
+
+int sl_media_jack_cable_shift_state_get(struct sl_media_jack *media_jack, u8 *cable_shift_state)
+{
+	spin_lock(&media_jack->data_lock);
+	*cable_shift_state = media_jack->cable_shift_state;
+	spin_unlock(&media_jack->data_lock);
+
+	sl_media_log_dbg(media_jack, LOG_NAME, "cable shift state get = %u", *cable_shift_state);
+
+	return 0;
+}
+
+bool sl_media_jack_is_cable_online(struct sl_media_jack *media_jack)
+{
+	u8 state;
+
+	spin_lock(&media_jack->data_lock);
+	state = media_jack->state;
+	spin_unlock(&media_jack->data_lock);
+
+	return (state == SL_MEDIA_JACK_CABLE_ONLINE);
+}
+
+bool sl_media_jack_is_cable_format_unsupported(struct sl_media_jack *media_jack)
+{
+	bool is_format_unsupported;
+
+	spin_lock(&media_jack->data_lock);
+	is_format_unsupported = media_jack->is_cable_format_unsupported;
+	spin_unlock(&media_jack->data_lock);
+
+	return is_format_unsupported;
+}
+
+int sl_media_jack_active_cable_200g_host_interface_get(struct sl_media_jack *media_jack, u8 *host_interface_200_gaui)
+{
+	spin_lock(&media_jack->data_lock);
+	*host_interface_200_gaui = media_jack->host_interface_200_gaui;
+	spin_unlock(&media_jack->data_lock);
+
+	return 0;
+}
+
+int sl_media_jack_active_cable_200g_appsel_num_get(struct sl_media_jack *media_jack, u8 *appsel_num_200_gaui)
+{
+	spin_lock(&media_jack->data_lock);
+	*appsel_num_200_gaui = media_jack->appsel_num_200_gaui;
+	spin_unlock(&media_jack->data_lock);
+
+	return 0;
+}
+
+int sl_media_jack_active_cable_200g_lane_count_get(struct sl_media_jack *media_jack, u8 *lane_count_200_gaui)
+{
+	spin_lock(&media_jack->data_lock);
+	*lane_count_200_gaui = media_jack->lane_count_200_gaui;
+	spin_unlock(&media_jack->data_lock);
+
+	return 0;
+}
+
+int sl_media_jack_active_cable_400g_host_interface_get(struct sl_media_jack *media_jack, u8 *host_interface_400_gaui)
+{
+	spin_lock(&media_jack->data_lock);
+	*host_interface_400_gaui = media_jack->host_interface_400_gaui;
+	spin_unlock(&media_jack->data_lock);
+
+	return 0;
+}
+
+int sl_media_jack_active_cable_400g_appsel_num_get(struct sl_media_jack *media_jack, u8 *appsel_num_400_gaui)
+{
+	spin_lock(&media_jack->data_lock);
+	*appsel_num_400_gaui = media_jack->appsel_num_400_gaui;
+	spin_unlock(&media_jack->data_lock);
+
+	return 0;
+}
+
+int sl_media_jack_active_cable_400g_lane_count_get(struct sl_media_jack *media_jack, u8 *lane_count_400_gaui)
+{
+	spin_lock(&media_jack->data_lock);
+	*lane_count_400_gaui = media_jack->lane_count_400_gaui;
+	spin_unlock(&media_jack->data_lock);
+
+	return 0;
+}
+
+#define SL_MEDIA_HIGH_POWER_WAIT_TIME 10000
+int sl_media_jack_cable_high_power_set(u8 ldev_num, u8 jack_num)
+{
+	int                   rtn;
+	struct sl_media_jack *media_jack;
+
+	media_jack = sl_media_jack_get(ldev_num, jack_num);
+
+	sl_media_log_dbg(media_jack, LOG_NAME, "high power set");
+
+	rtn = sl_media_data_jack_cable_high_power_set(media_jack);
+	if (rtn) {
+		sl_media_jack_fault_cause_set(media_jack, SL_MEDIA_FAULT_CAUSE_POWER_SET);
+		sl_media_log_err_trace(media_jack, LOG_NAME, "high power set failed [%d]", rtn);
+		return -EIO;
+	}
+
+	media_jack->cable_high_power_wait_time_end = jiffies +
+		msecs_to_jiffies(SL_MEDIA_HIGH_POWER_WAIT_TIME);
+
+	return 0;
+}
+
+static int sl_media_jack_cable_shift_checks(struct sl_media_lgrp *media_lgrp, u8 shift_state)
+{
+	u8 i;
+
+	sl_media_log_dbg(media_lgrp->media_jack, LOG_NAME, "cable shift checks");
+
+	spin_lock(&media_lgrp->media_jack->data_lock);
+	if (media_lgrp->media_jack->state != SL_MEDIA_JACK_CABLE_ONLINE) {
+		media_lgrp->media_jack->cable_shift_state = SL_MEDIA_JACK_CABLE_SHIFT_STATE_FAILED_NO_CABLE;
+		spin_unlock(&media_lgrp->media_jack->data_lock);
+		sl_media_log_dbg(media_lgrp->media_jack, LOG_NAME, "shift check failed - no online cable");
+		return -EFAULT;
+	}
+
+	for (i = 0; i < SL_MEDIA_MAX_LGRPS_PER_JACK; ++i) {
+		if (media_lgrp->media_jack->cable_info[i].real_cable_status == CABLE_MEDIA_ATTR_STASHED) {
+			media_lgrp->media_jack->cable_shift_state = SL_MEDIA_JACK_CABLE_SHIFT_STATE_FAILED_FAKE_CABLE;
+			spin_unlock(&media_lgrp->media_jack->data_lock);
+			sl_media_log_dbg(media_lgrp->media_jack, LOG_NAME,
+					 "shift check failed - fake cable (lgrp_num = %u)",
+					 media_lgrp->media_jack->cable_info[i].lgrp_num);
+			return -EFAULT;
+		}
+	}
+	if (!(media_lgrp->media_jack->cable_info[0].media_attr.speeds_map &
+			(SL_MEDIA_SPEEDS_SUPPORT_CK_400G | SL_MEDIA_SPEEDS_SUPPORT_BS_200G))) {
+		media_lgrp->media_jack->cable_shift_state = SL_MEDIA_JACK_CABLE_SHIFT_STATE_FAILED_NO_SUPPORT;
+		spin_unlock(&media_lgrp->media_jack->data_lock);
+		sl_media_log_dbg(media_lgrp->media_jack, LOG_NAME,
+				 "shift check failed - no shift support in cable");
+		return -EINVAL;
+	}
+	if (shift_state == SL_MEDIA_JACK_CABLE_DOWNSHIFT) {
+		if ((media_lgrp->media_jack->host_interface_200_gaui != SL_MEDIA_SS1_HOST_INTERFACE_200GAUI_4_C2M) ||
+		    (media_lgrp->media_jack->lane_count_200_gaui != 0x44) ||
+			(media_lgrp->media_jack->host_interface_400_gaui == 0)) {
+			media_lgrp->media_jack->cable_shift_state = SL_MEDIA_JACK_CABLE_SHIFT_STATE_FAILED_CHECK;
+			spin_unlock(&media_lgrp->media_jack->data_lock);
+			sl_media_log_dbg(media_lgrp->media_jack, LOG_NAME,
+					 "downshift check failed - invalid host interface and/or lane count");
+			return -EINVAL;
+		}
+	} else {
+		if (((media_lgrp->media_jack->host_interface_400_gaui != SL_MEDIA_SS2_HOST_INTERFACE_400GAUI_4_S_C2M) &&
+		     (media_lgrp->media_jack->host_interface_400_gaui != SL_MEDIA_SS1_HOST_INTERFACE_400GAUI_4_L_C2M)) ||
+			(media_lgrp->media_jack->lane_count_400_gaui != 0x44)) {
+			media_lgrp->media_jack->cable_shift_state = SL_MEDIA_JACK_CABLE_SHIFT_STATE_FAILED_CHECK;
+			spin_unlock(&media_lgrp->media_jack->data_lock);
+			sl_media_log_dbg(media_lgrp->media_jack, LOG_NAME,
+					 "upshift check failed - invalid host interface and/or lane count");
+			return -EINVAL;
+		}
+	}
+
+	spin_unlock(&media_lgrp->media_jack->data_lock);
+
+	return 0;
+}
+
+int sl_media_jack_cable_downshift(u8 ldev_num, u8 lgrp_num, u8 link_num)
+{
+	int                   rtn;
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+	struct sl_media_attr  media_attr;
+
+	media_lgrp = sl_media_lgrp_get(ldev_num, lgrp_num);
+	core_link = sl_core_link_get(ldev_num, lgrp_num, link_num);
+	if (!core_link)
+		return -ENODEV;
+
+	sl_media_log_dbg(media_lgrp->media_jack, LOG_NAME, "cable downshift");
+
+	if (media_lgrp->media_jack->is_cable_unsupported) {
+		sl_media_log_dbg(media_lgrp->media_jack, LOG_NAME, "cable unsupported - shift not required");
+		return 0;
+	}
+
+	if (media_lgrp->media_jack->is_supported_ss200_cable) {
+		sl_media_log_dbg(media_lgrp->media_jack, LOG_NAME, "ss200 cable - shift not required");
+		return 0;
+	}
+
+	if (!sl_media_lgrp_media_type_is_active(media_lgrp->media_ldev->num, media_lgrp->num)) {
+		sl_media_log_dbg(media_lgrp->media_jack, LOG_NAME, "non-active cable - shift not required");
+		return 0;
+	}
+
+	if (sl_media_data_jack_cable_hw_shift_state_get(media_lgrp->media_jack) == SL_MEDIA_JACK_CABLE_HW_SHIFT_STATE_DOWNSHIFTED) {
+		sl_media_jack_cable_shift_state_set(media_lgrp->media_jack, SL_MEDIA_JACK_CABLE_SHIFT_STATE_DOWNSHIFTED);
+		sl_media_log_dbg(media_lgrp->media_jack, LOG_NAME, "already downshifted");
+		return 0;
+	}
+
+	rtn = sl_media_jack_cable_shift_checks(media_lgrp, SL_MEDIA_JACK_CABLE_DOWNSHIFT);
+	if (rtn) {
+		sl_media_log_err_trace(media_lgrp->media_jack, LOG_NAME, "cable shift checks failed [%d]", rtn);
+		return 0;
+	}
+
+	if (!sl_core_link_policy_is_ignore_media_errors_set(core_link)) {
+		sl_media_lgrp_media_attr_get(ldev_num, lgrp_num, &media_attr);
+		if (media_attr.errors & SL_MEDIA_ERROR_CABLE_FW_UNSUPPORTED) {
+			sl_media_log_err_trace(media_lgrp->media_jack, LOG_NAME,
+					       "can't downshift - cable firmware unsupported");
+			return 0;
+		}
+	}
+
+	rtn = sl_media_data_jack_cable_downshift(media_lgrp->media_jack);
+	if (rtn) {
+		sl_media_jack_cable_shift_state_set(media_lgrp->media_jack,
+						    SL_MEDIA_JACK_CABLE_SHIFT_STATE_FAILED_DOWNSHIFT);
+		sl_media_log_err_trace(media_lgrp->media_jack, LOG_NAME, "data jack cable downshift failed [%d]", rtn);
+		return rtn;
+	}
+
+	sl_media_jack_cable_shift_state_set(media_lgrp->media_jack, SL_MEDIA_JACK_CABLE_SHIFT_STATE_DOWNSHIFTED);
+
+	return 0;
+}
+
+int sl_media_jack_cable_upshift(u8 ldev_num, u8 lgrp_num, u8 link_num)
+{
+	int                   rtn;
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+	struct sl_media_attr  media_attr;
+
+	media_lgrp = sl_media_lgrp_get(ldev_num, lgrp_num);
+	core_link = sl_core_link_get(ldev_num, lgrp_num, link_num);
+	if (!core_link)
+		return -ENODEV;
+
+	sl_media_log_dbg(media_lgrp->media_jack, LOG_NAME, "cable upshift");
+
+	if (media_lgrp->media_jack->is_cable_unsupported) {
+		sl_media_log_dbg(media_lgrp->media_jack, LOG_NAME, "cable unsupported - shift not required");
+		return 0;
+	}
+
+	if (media_lgrp->media_jack->is_supported_ss200_cable) {
+		sl_media_log_dbg(media_lgrp->media_jack, LOG_NAME, "ss200 cable - shift not required");
+		return 0;
+	}
+
+	if (!sl_media_lgrp_media_type_is_active(media_lgrp->media_ldev->num, media_lgrp->num)) {
+		sl_media_log_dbg(media_lgrp->media_jack, LOG_NAME, "non-active cable - shift not required");
+		return 0;
+	}
+
+	if (sl_media_data_jack_cable_hw_shift_state_get(media_lgrp->media_jack) == SL_MEDIA_JACK_CABLE_HW_SHIFT_STATE_UPSHIFTED) {
+		sl_media_jack_cable_shift_state_set(media_lgrp->media_jack, SL_MEDIA_JACK_CABLE_SHIFT_STATE_UPSHIFTED);
+		sl_media_log_dbg(media_lgrp->media_jack, LOG_NAME, "already upshifted");
+		return 0;
+	}
+
+	rtn = sl_media_jack_cable_shift_checks(media_lgrp, SL_MEDIA_JACK_CABLE_UPSHIFT);
+	if (rtn) {
+		sl_media_log_err_trace(media_lgrp->media_jack, LOG_NAME, "cable shift checks failed [%d]", rtn);
+		return 0;
+	}
+
+	if (!sl_core_link_policy_is_ignore_media_errors_set(core_link)) {
+		sl_media_lgrp_media_attr_get(ldev_num, lgrp_num, &media_attr);
+		if (media_attr.errors & SL_MEDIA_ERROR_CABLE_FW_UNSUPPORTED) {
+			sl_media_log_err_trace(media_lgrp->media_jack, LOG_NAME,
+					       "can't upshift - cable firmware unsupported");
+			return 0;
+		}
+	}
+
+	rtn = sl_media_data_jack_cable_upshift(media_lgrp->media_jack);
+	if (rtn) {
+		sl_media_jack_cable_shift_state_set(media_lgrp->media_jack,
+						    SL_MEDIA_JACK_CABLE_SHIFT_STATE_FAILED_UPSHIFT);
+		sl_media_log_err_trace(media_lgrp->media_jack, LOG_NAME, "data jack cable upshift failed [%d]", rtn);
+		return rtn;
+	}
+
+	sl_media_jack_cable_shift_state_set(media_lgrp->media_jack, SL_MEDIA_JACK_CABLE_SHIFT_STATE_UPSHIFTED);
+
+	return 0;
+}
+
+void sl_media_jack_fault_cause_set(struct sl_media_jack *media_jack, u32 fault_cause)
+{
+	spin_lock(&media_jack->data_lock);
+	media_jack->fault_cause = fault_cause;
+	media_jack->fault_time  = ktime_get_real_seconds();
+	spin_unlock(&media_jack->data_lock);
+
+	if (fault_cause == SL_MEDIA_FAULT_CAUSE_NONE)
+		return;
+
+	if (fault_cause == SL_MEDIA_FAULT_CAUSE_HOT)
+		sl_media_data_jack_led_set(media_jack);
+
+	sl_ctrl_media_cause_counter_inc(media_jack, fault_cause);
+
+	sl_media_log_dbg(media_jack, LOG_NAME, "fault cause set (cause = %u %s)", fault_cause,
+			 sl_media_fault_cause_str(fault_cause));
+}
+
+int sl_media_jack_fault_cause_get(struct sl_media_jack *media_jack, u32 *fault_cause,
+				  time64_t *fault_time)
+{
+	spin_lock(&media_jack->data_lock);
+	*fault_cause = media_jack->fault_cause;
+	*fault_time  = media_jack->fault_time;
+	spin_unlock(&media_jack->data_lock);
+
+	sl_media_log_dbg(media_jack, LOG_NAME, "cable fault cause get (cause = %u %s)", *fault_cause,
+			 sl_media_fault_cause_str(*fault_cause));
+
+	return 0;
+}
+
+const char *sl_media_fault_cause_str(u32 fault_cause)
+{
+	switch (fault_cause) {
+	case SL_MEDIA_FAULT_CAUSE_EEPROM_FORMAT_UNSUPPORTED:
+		return "eeprom-format-unsupported";
+	case SL_MEDIA_FAULT_CAUSE_EEPROM_VENDOR_UNSUPPORTED:
+		return "eeprom-vendor-unsupported";
+	case SL_MEDIA_FAULT_CAUSE_EEPROM_JACK_IO:
+		return "eeprom-jack-io";
+	case SL_MEDIA_FAULT_CAUSE_ONLINE_STATUS_GET:
+		return "online-status-get";
+	case SL_MEDIA_FAULT_CAUSE_ONLINE_TIMEDOUT:
+		return "online-timedout";
+	case SL_MEDIA_FAULT_CAUSE_ONLINE_JACK_IO:
+		return "online-jack-io";
+	case SL_MEDIA_FAULT_CAUSE_ONLINE_JACK_GET:
+		return "online-jack-get";
+	case SL_MEDIA_FAULT_CAUSE_SERDES_SETTINGS_GET:
+		return "serdes-settings-get";
+	case SL_MEDIA_FAULT_CAUSE_SCAN_STATUS_GET:
+		return "scan-status-get";
+	case SL_MEDIA_FAULT_CAUSE_SCAN_HDL_GET:
+		return "scan-hdl-get";
+	case SL_MEDIA_FAULT_CAUSE_SCAN_JACK_GET:
+		return "scan-jack-get";
+	case SL_MEDIA_FAULT_CAUSE_MEDIA_ATTR_SET:
+		return "media-attr-set";
+	case SL_MEDIA_FAULT_CAUSE_INTR_EVENT_JACK_IO:
+		return "intr-event-jack-io";
+	case SL_MEDIA_FAULT_CAUSE_POWER_SET:
+		return "power-set";
+	case SL_MEDIA_FAULT_CAUSE_SHIFT_DOWN_JACK_IO:
+		return "shift-down-jack-io";
+	case SL_MEDIA_FAULT_CAUSE_SHIFT_DOWN_JACK_IO_LOW_POWER_SET:
+		return "shift-down-jack-io-low-power-set";
+	case SL_MEDIA_FAULT_CAUSE_SHIFT_DOWN_JACK_IO_HIGH_POWER_SET:
+		return "shift-down-jack-io-high-power-set";
+	case SL_MEDIA_FAULT_CAUSE_SHIFT_UP_JACK_IO:
+		return "shift-up-jack-io";
+	case SL_MEDIA_FAULT_CAUSE_SHIFT_UP_JACK_IO_LOW_POWER_SET:
+		return "shift-up-jack-io-low-power-set";
+	case SL_MEDIA_FAULT_CAUSE_SHIFT_UP_JACK_IO_HIGH_POWER_SET:
+		return "shift-up-jack-io-high-power-set";
+	case SL_MEDIA_FAULT_CAUSE_SHIFT_STATE_JACK_IO:
+		return "shift-state-jack-io";
+	case SL_MEDIA_FAULT_CAUSE_OFFLINE:
+		return "offline";
+	case SL_MEDIA_FAULT_CAUSE_HOT:
+		return "hot";
+	case SL_MEDIA_FAULT_CAUSE_WARM:
+		return "warm";
+	default:
+		return "unknown";
+	}
+}
+
+const char *sl_media_temp_state_str(u8 temperature_state)
+{
+	switch (temperature_state) {
+	case SL_MEDIA_JACK_TEMP_STATE_COLD:
+		return "cold";
+	case SL_MEDIA_JACK_TEMP_STATE_WARM:
+		return "warm";
+	case SL_MEDIA_JACK_TEMP_STATE_HOT:
+		return "hot";
+	default:
+		return "unknown";
+	}
+}
+
+int sl_media_jack_cable_temp_state_get(struct sl_media_jack *media_jack, u8 *temperature_state)
+{
+	return sl_media_data_jack_cable_temp_state_get(media_jack, temperature_state);
+}
+
+int sl_media_jack_cable_temp_prev_state_get(struct sl_media_jack *media_jack, u8 *temperature_prev_state)
+{
+	return sl_media_data_jack_cable_temp_prev_state_get(media_jack, temperature_prev_state);
+}
+
+int sl_media_jack_cable_temp_get(u8 ldev_num, u8 lgrp_num, u8 *temp)
+{
+	struct sl_media_lgrp *group = sl_media_lgrp_get(ldev_num, lgrp_num);
+
+	if (!group || !group->media_jack)
+		return -EBADRQC;
+	return sl_media_data_jack_cable_temp_get(group->media_jack, temp);
+}
+
+int sl_media_jack_cable_temp_warn_limit_get(u8 ldev_num, u8 lgrp_num, u8 *temp_warn_limit_c)
+{
+	struct sl_media_lgrp *group = sl_media_lgrp_get(ldev_num, lgrp_num);
+
+	if (!group || !group->media_jack)
+		return -EBADRQC;
+	return sl_media_data_jack_cable_temp_warn_limit_get(group->media_jack,
+							 temp_warn_limit_c);
+}
+
+int sl_media_jack_cable_temp_down_limit_get(u8 ldev_num, u8 lgrp_num, u8 *temp_down_limit_c)
+{
+	struct sl_media_lgrp *group = sl_media_lgrp_get(ldev_num, lgrp_num);
+
+	if (!group || !group->media_jack)
+		return -EBADRQC;
+	return sl_media_data_jack_cable_temp_down_limit_get(group->media_jack,
+							 temp_down_limit_c);
+}
+
+int sl_media_jack_cable_low_power_set(struct sl_media_jack *media_jack)
+{
+	return sl_media_data_jack_cable_low_power_set(media_jack);
+}
+
+void sl_media_jack_led_set(u8 ldev_num, u8 lgrp_num)
+{
+	struct sl_media_lgrp *media_lgrp;
+
+	media_lgrp = sl_media_lgrp_get(ldev_num, lgrp_num);
+
+	sl_media_log_dbg(media_lgrp->media_jack, LOG_NAME, "led set");
+
+	sl_media_data_jack_led_set(media_lgrp->media_jack);
+}
+
+static const char *sl_media_jack_lane_dp_state_str(u8 dp_state)
+{
+	switch (dp_state) {
+	case SL_MEDIA_JACK_DP_STATE_DEACTIVATED:
+		return "dp-deactivated";
+	case SL_MEDIA_JACK_DP_STATE_INIT:
+		return "dp-init";
+	case SL_MEDIA_JACK_DP_STATE_DEINIT:
+		return "dp-deinit";
+	case SL_MEDIA_JACK_DP_STATE_ACTIVATED:
+		return "dp-activated";
+	case SL_MEDIA_JACK_DP_STATE_TX_TURN_ON:
+		return "dp-tx-turn-on";
+	case SL_MEDIA_JACK_DP_STATE_TX_TURN_OFF:
+		return "dp-tx-turn-off";
+	case SL_MEDIA_JACK_DP_STATE_INITIALIZED:
+		return "dp-initialized";
+	default:
+		return "unknown";
+	}
+}
+
+/* Swap the lanes in the lane data structure. See sl_core_lgrp_media_lane_data_swap
+ * for more details.
+ */
+static void sl_media_jack_lane_data_swap(struct sl_media_jack_lane_data *lane_data)
+{
+	u8 dp_states;
+
+	lane_data->signal.rx.los_map = SWAP_BYTE_NIBBLE(lane_data->signal.rx.los_map);
+	lane_data->signal.tx.los_map = SWAP_BYTE_NIBBLE(lane_data->signal.tx.los_map);
+	lane_data->signal.rx.lol_map = SWAP_BYTE_NIBBLE(lane_data->signal.rx.lol_map);
+	lane_data->signal.tx.lol_map = SWAP_BYTE_NIBBLE(lane_data->signal.tx.lol_map);
+	lane_data->dp_states_changed = SWAP_BYTE_NIBBLE(lane_data->dp_states_changed);
+
+	/* Swap lanes 0 & 1 for 4 & 5 and visa versa */
+	dp_states = lane_data->dp_states[2];
+	lane_data->dp_states[2] = lane_data->dp_states[0];
+	lane_data->dp_states[0] = dp_states;
+
+	/* Swap lanes 2 & 3 for 6 & 7 and visa versa */
+	dp_states = lane_data->dp_states[3];
+	lane_data->dp_states[3] = lane_data->dp_states[1];
+	lane_data->dp_states[1] = dp_states;
+}
+
+#define SL_MEDIA_JACK_DP_STATE_OFFSET    128
+#define SL_MEDIA_JACK_TX_LOS_OFFSET      136
+#define SL_MEDIA_JACK_RX_LOS_OFFSET      147
+#define SL_MEDIA_JACK_MAX_COHERENT_BYTES 8
+static int sl_media_jack_lane_data_read(u8 ldev_num, u8 lgrp_num, struct sl_media_jack_lane_data *lane_data)
+{
+	int                             rtn;
+	u8                              read_bytes[SL_MEDIA_JACK_MAX_COHERENT_BYTES];
+	bool                            swap;
+	struct sl_media_jack_lane_data  tmp_lane_data;
+	struct sl_media_jack           *media_jack;
+
+	media_jack = sl_media_lgrp_get(ldev_num, lgrp_num)->media_jack;
+
+	sl_media_log_dbg(media_jack, LOG_NAME, "media_io_read_lane_data (ldev_num = %u, lgrp_num = %u)",
+			 ldev_num, lgrp_num);
+
+	rtn = sl_media_io_read(media_jack, 0x11, SL_MEDIA_JACK_TX_LOS_OFFSET, (u8 *)&tmp_lane_data.signal.tx, 2);
+	if (rtn) {
+		sl_media_log_err(media_jack, LOG_NAME, "media_io_read_data failed [%d]", rtn);
+		return -EIO;
+	}
+
+	rtn = sl_media_io_read(media_jack, 0x11, SL_MEDIA_JACK_RX_LOS_OFFSET, (u8 *)&tmp_lane_data.signal.rx, 2);
+	if (rtn) {
+		sl_media_log_err(media_jack, LOG_NAME, "media_io_read_data failed [%d]", rtn);
+		return -EIO;
+	}
+
+	rtn = sl_media_io_read(media_jack, 0x11, SL_MEDIA_JACK_DP_STATE_OFFSET, read_bytes,
+			       SL_MEDIA_JACK_MAX_COHERENT_BYTES);
+	if (rtn) {
+		sl_media_log_err(media_jack, LOG_NAME, "media_io_read_data failed [%d]", rtn);
+		return -EIO;
+	}
+
+	memcpy(tmp_lane_data.dp_states, read_bytes, 4);
+	tmp_lane_data.dp_states_changed = read_bytes[6];
+
+	sl_media_log_dbg(media_jack, LOG_NAME,
+			 "lane data read (dp_states_changed = 0x%X)", tmp_lane_data.dp_states_changed);
+
+	swap = sl_core_lgrp_media_lane_data_swap(ldev_num, lgrp_num);
+	if (swap)
+		sl_media_jack_lane_data_swap(&tmp_lane_data);
+
+	sl_media_log_dbg(media_jack, LOG_NAME, "lane data swap = %s", swap ? "yes" : "no");
+
+	sl_media_log_dbg(media_jack, LOG_NAME,
+			 "lane data read map (rx_lol = 0x%X, tx_lol = 0x%X, rx_los = 0x%X, tx_los = 0x%X)",
+			 tmp_lane_data.signal.rx.lol_map, tmp_lane_data.signal.tx.lol_map,
+			 tmp_lane_data.signal.rx.los_map, tmp_lane_data.signal.tx.los_map);
+
+	sl_media_log_dbg(media_jack, LOG_NAME,
+			 "lanes dp_state (0 = %s, 1 = %s, 2 = %s, 3 = %s, 4 = %s, 5 = %s, 6 = %s, 7 = %s)",
+			 sl_media_jack_lane_dp_state_str(MEDIA_LANE_DP_STATE_GET(&tmp_lane_data, 0)),
+			 sl_media_jack_lane_dp_state_str(MEDIA_LANE_DP_STATE_GET(&tmp_lane_data, 1)),
+			 sl_media_jack_lane_dp_state_str(MEDIA_LANE_DP_STATE_GET(&tmp_lane_data, 2)),
+			 sl_media_jack_lane_dp_state_str(MEDIA_LANE_DP_STATE_GET(&tmp_lane_data, 3)),
+			 sl_media_jack_lane_dp_state_str(MEDIA_LANE_DP_STATE_GET(&tmp_lane_data, 4)),
+			 sl_media_jack_lane_dp_state_str(MEDIA_LANE_DP_STATE_GET(&tmp_lane_data, 5)),
+			 sl_media_jack_lane_dp_state_str(MEDIA_LANE_DP_STATE_GET(&tmp_lane_data, 6)),
+			 sl_media_jack_lane_dp_state_str(MEDIA_LANE_DP_STATE_GET(&tmp_lane_data, 7)));
+
+	spin_lock(&media_jack->data_lock);
+	memcpy(lane_data, &tmp_lane_data, sizeof(*lane_data));
+	spin_unlock(&media_jack->data_lock);
+
+	return 0;
+}
+
+static bool sl_media_jack_is_lane_data_valid(struct sl_media_jack *media_jack, unsigned long serdes_lane_map,
+					     struct sl_media_jack_lane_data *lane_data)
+{
+	u8 serdes_lane_num;
+	u8 lane_dp_state;
+
+	sl_media_log_dbg(media_jack, LOG_NAME, "lane data valid (serdes_lane_map = 0x%lx)", serdes_lane_map);
+
+	if (lane_data->dp_states_changed & serdes_lane_map) {
+		sl_media_log_dbg(media_jack, LOG_NAME,
+				 "lane data valid DP state changed (dp_states_changed = 0x%X, serdes_lane_map = 0x%lx)",
+				 lane_data->dp_states_changed, serdes_lane_map);
+		return false;
+	}
+
+	for_each_set_bit(serdes_lane_num, &serdes_lane_map, SL_ASIC_MAX_LANES) {
+		lane_dp_state = MEDIA_LANE_DP_STATE_GET(lane_data, serdes_lane_num);
+
+		if (!SL_MEDIA_JACK_SIGNAL_INFO_ALLOWED(lane_dp_state)) {
+			sl_media_log_dbg(media_jack, LOG_NAME,
+					 "lane data valid DP state not allowed (lane_num = %u, dp_state = %u %s)",
+					 serdes_lane_num, lane_dp_state,
+					 sl_media_jack_lane_dp_state_str(lane_dp_state));
+			return false;
+		}
+	}
+
+	return true;
+}
+
+static void sl_media_jack_lane_data_cache_set(struct sl_media_jack *media_jack,
+					      struct sl_media_jack_lane_data *lane_data)
+{
+	spin_lock(&media_jack->data_lock);
+	media_jack->lane_data.cache.data   = *lane_data;
+	media_jack->lane_data.cache.cached = true;
+	media_jack->lane_data.cache.timestamp_s = ktime_get_real_seconds();
+	spin_unlock(&media_jack->data_lock);
+}
+
+static bool sl_media_jack_lane_data_cache_get(struct sl_media_jack *media_jack,
+					      struct sl_media_jack_lane_data *lane_data)
+{
+	bool     cached;
+
+	spin_lock(&media_jack->data_lock);
+	cached     = media_jack->lane_data.cache.cached;
+	*lane_data = media_jack->lane_data.cache.data;
+	spin_unlock(&media_jack->data_lock);
+
+	sl_media_log_dbg(media_jack, LOG_NAME,
+			 "lane data cache get map (rx_los = 0x%X, tx_los = 0x%X, rx_lol = 0x%X, tx_lol = 0x%X)",
+			 lane_data->signal.rx.los_map, lane_data->signal.tx.los_map,
+			 lane_data->signal.rx.lol_map, lane_data->signal.tx.lol_map);
+
+	return cached;
+}
+
+static bool sl_media_jack_signal_equal(struct sl_media_jack_signal *a, struct sl_media_jack_signal *b)
+{
+	return (a->rx.los_map == b->rx.los_map) &&
+	       (a->tx.los_map == b->tx.los_map) &&
+	       (a->rx.lol_map == b->rx.lol_map) &&
+	       (a->tx.lol_map == b->tx.lol_map);
+}
+
+static void sl_media_jack_signal_or(struct sl_media_jack_signal *a, struct sl_media_jack_signal *b)
+{
+	a->rx.los_map |= b->rx.los_map;
+	a->tx.los_map |= b->tx.los_map;
+	a->rx.lol_map |= b->rx.lol_map;
+	a->tx.lol_map |= b->tx.lol_map;
+}
+
+static int sl_media_jack_lane_data_get(u8 ldev_num, u8 lgrp_num, u8 serdes_lane_map,
+				       struct sl_media_jack_lane_data *lane_data)
+{
+	int                             rtn;
+	u8                              read_count;
+	bool                            is_stable;
+	struct sl_media_jack_lane_data  current_lane_data;
+	struct sl_media_jack_signal     prev_signal;
+	struct sl_media_jack           *media_jack;
+
+	media_jack = sl_media_lgrp_get(ldev_num, lgrp_num)->media_jack;
+
+	sl_media_log_dbg(media_jack, LOG_NAME, "lane data get (ldev_num = %u, lgrp_num = %u, serdes_lane_map = 0x%X)",
+			 ldev_num, lgrp_num, serdes_lane_map);
+
+	rtn = sl_media_jack_lane_data_read(ldev_num, lgrp_num, lane_data);
+	if (rtn) {
+		sl_media_log_err_trace(media_jack, LOG_NAME, "lane data read failed [%d]", rtn);
+		return rtn;
+	}
+
+	msleep(SL_MEDIA_JACK_LANE_DATA_POLL_TIME_MS);
+
+	read_count = 0;
+	is_stable  = false;
+
+	rtn = sl_media_jack_lane_data_read(ldev_num, lgrp_num, lane_data);
+	if (rtn) {
+		sl_media_log_err_trace(media_jack, LOG_NAME, "lane data read failed [%d]", rtn);
+		return rtn;
+	}
+
+	if (!sl_media_jack_is_lane_data_valid(media_jack, serdes_lane_map, lane_data)) {
+		sl_media_log_err_trace(media_jack, LOG_NAME, "lane data not valid");
+		return -EIO;
+	}
+
+	/* Short circuit, no new bits can be set */
+	if (lane_data->signal.rx.los_map == 0xFF &&
+	    lane_data->signal.tx.los_map == 0xFF &&
+	    lane_data->signal.rx.lol_map == 0xFF &&
+	    lane_data->signal.tx.lol_map == 0xFF) {
+		read_count++;
+		is_stable = true;
+		goto out;
+	}
+
+	prev_signal = lane_data->signal;
+
+	msleep(SL_MEDIA_JACK_LANE_DATA_POLL_TIME_MS);
+
+	for (read_count = 1; read_count < SL_MEDIA_JACK_MAX_NUM_LANE_DATA_READS; ++read_count) {
+		rtn = sl_media_jack_lane_data_read(ldev_num, lgrp_num, &current_lane_data);
+		if (rtn) {
+			sl_media_log_err_trace(media_jack, LOG_NAME, "lane data read failed [%d]", rtn);
+			return rtn;
+		}
+
+		if (!sl_media_jack_is_lane_data_valid(media_jack, serdes_lane_map, &current_lane_data)) {
+			sl_media_log_err_trace(media_jack, LOG_NAME, "lane data not valid");
+			return -EIO;
+		}
+
+		prev_signal = lane_data->signal;
+		sl_media_jack_signal_or(&lane_data->signal, &current_lane_data.signal);
+
+		is_stable = sl_media_jack_signal_equal(&lane_data->signal, &prev_signal);
+		if (is_stable) {
+			++read_count;
+			break;
+		}
+
+		msleep(SL_MEDIA_JACK_LANE_DATA_POLL_TIME_MS);
+	}
+
+out:
+	sl_media_log_dbg(media_jack, LOG_NAME,
+			 "lane data get (read_count = %u)", read_count);
+
+	if (!is_stable) {
+		sl_media_log_err_trace(media_jack, LOG_NAME, "lane data unstable");
+		return -EIO;
+	}
+
+	sl_media_jack_lane_data_cache_set(media_jack, lane_data);
+
+	sl_media_log_dbg(media_jack, LOG_NAME,
+			 "lane data get map (rx_los = 0x%X, tx_los = 0x%X, rx_lol = 0x%X, tx_lol = 0x%X)",
+			 lane_data->signal.rx.los_map, lane_data->signal.tx.los_map,
+			 lane_data->signal.rx.lol_map, lane_data->signal.tx.lol_map);
+
+	return 0;
+}
+
+int sl_media_jack_signal_get(u8 ldev_num, u8 lgrp_num, u8 serdes_lane_map, struct sl_media_jack_signal *media_signal)
+{
+	int                             rtn;
+	struct sl_media_jack_lane_data  lane_data;
+	struct sl_media_jack           *media_jack;
+	bool                            cached;
+	unsigned long                   time_left;
+	u32                             generation;
+
+	media_jack = sl_media_lgrp_get(ldev_num, lgrp_num)->media_jack;
+
+	sl_media_log_dbg(media_jack, LOG_NAME, "signal get (ldev_num = %u, lgrp_num = %u, serdes_lane_map = 0x%X)",
+			 ldev_num, lgrp_num, serdes_lane_map);
+
+	if (!sl_media_lgrp_media_type_is_active(ldev_num, lgrp_num)) {
+		sl_media_log_warn_trace(media_jack, LOG_NAME, "cable not active");
+		return -EBADRQC;
+	}
+
+	if (!sl_media_lgrp_is_signal_status_supported(ldev_num, lgrp_num)) {
+		sl_media_log_dbg(media_jack, LOG_NAME, "signal status unsupported");
+		return -EBADRQC;
+	}
+
+	spin_lock(&media_jack->data_lock);
+	switch (media_jack->lane_data.read_state) {
+	case SL_MEDIA_JACK_LANE_DATA_READ_STATE_IDLE:
+		media_jack->lane_data.read_state = SL_MEDIA_JACK_LANE_DATA_READ_STATE_BUSY;
+		sl_media_log_dbg(media_jack, LOG_NAME, "reading lane data - state set to BUSY");
+		spin_unlock(&media_jack->data_lock);
+
+		rtn = sl_media_jack_lane_data_get(ldev_num, lgrp_num, serdes_lane_map, &lane_data);
+
+		spin_lock(&media_jack->data_lock);
+		media_jack->lane_data.read_state    = SL_MEDIA_JACK_LANE_DATA_READ_STATE_IDLE;
+		media_jack->lane_data.last_read_rtn = rtn;
+		WRITE_ONCE(media_jack->lane_data.read_generation,
+			   media_jack->lane_data.read_generation + 1);
+		spin_unlock(&media_jack->data_lock);
+
+		wake_up_all(&media_jack->lane_data.read_wait);
+
+		if (rtn) {
+			sl_media_log_err_trace(media_jack, LOG_NAME, "lane data read failed [%d]", rtn);
+			return rtn;
+		}
+
+		goto out;
+
+	case SL_MEDIA_JACK_LANE_DATA_READ_STATE_BUSY:
+		generation = media_jack->lane_data.read_generation;
+		sl_media_log_dbg(media_jack, LOG_NAME, "waiting for lane data read to complete");
+		spin_unlock(&media_jack->data_lock);
+
+		time_left = msecs_to_jiffies(SL_MEDIA_JACK_SIGNAL_READ_TIMEOUT_MS);
+		time_left = wait_event_timeout(media_jack->lane_data.read_wait,
+					       READ_ONCE(media_jack->lane_data.read_generation) !=
+					       generation, time_left);
+
+		if (time_left == 0) {
+			sl_media_log_err_trace(media_jack, LOG_NAME, "lane data read timed out");
+			return -ETIMEDOUT;
+		}
+
+		spin_lock(&media_jack->data_lock);
+		rtn = media_jack->lane_data.last_read_rtn;
+		if (rtn) {
+			sl_media_log_err_trace(media_jack, LOG_NAME, "lane data read failed [%d]", rtn);
+			spin_unlock(&media_jack->data_lock);
+			return rtn;
+		}
+
+		cached    = media_jack->lane_data.cache.cached;
+		lane_data = media_jack->lane_data.cache.data;
+		spin_unlock(&media_jack->data_lock);
+
+		if (!cached) {
+			sl_media_log_err_trace(media_jack, LOG_NAME, "lane data not cached");
+			return -EIO;
+		}
+
+		goto out;
+
+	default:
+		sl_media_log_err(media_jack, LOG_NAME, "invalid lane data read state (%u)",
+				 media_jack->lane_data.read_state);
+		spin_unlock(&media_jack->data_lock);
+		return -EIO;
+	}
+
+out:
+	*media_signal = lane_data.signal;
+
+	sl_media_log_dbg(media_jack, LOG_NAME,
+			 "signal get (rx_los = 0x%X, rx_lol = 0x%X, tx_los = 0x%X, tx_lol = 0x%X)",
+			 media_signal->rx.los_map, media_signal->rx.lol_map,
+			 media_signal->tx.los_map, media_signal->tx.lol_map);
+
+	return 0;
+}
+
+int sl_media_jack_signal_cache_get(u8 ldev_num, u8 lgrp_num, u8 serdes_lane_map,
+				   struct sl_media_jack_signal *media_signal)
+{
+	struct sl_media_jack_lane_data  lane_data;
+	struct sl_media_jack           *media_jack;
+
+	media_jack = sl_media_lgrp_get(ldev_num, lgrp_num)->media_jack;
+
+	sl_media_log_dbg(media_jack, LOG_NAME, "signal cache get (ldev_num =%u, lgrp_num = %u, serdes_lane_map = 0x%X)",
+			 ldev_num, lgrp_num, serdes_lane_map);
+
+	if (!sl_media_jack_lane_data_cache_get(media_jack, &lane_data)) {
+		sl_media_log_err_trace(media_jack, LOG_NAME, "lane data not cached");
+		return -ENOENT;
+	}
+
+	*media_signal = lane_data.signal;
+
+	return 0;
+}
+
+int sl_media_jack_signal_cache_time_s_get(u8 ldev_num, u8 lgrp_num, time64_t *cache_time)
+{
+	bool                  cached;
+	struct sl_media_jack *media_jack;
+
+	media_jack = sl_media_lgrp_get(ldev_num, lgrp_num)->media_jack;
+
+	sl_media_log_dbg(media_jack, LOG_NAME, "signal cache time get (ldev_num =%u, lgrp_num = %u)",
+			 ldev_num, lgrp_num);
+
+	spin_lock(&media_jack->data_lock);
+	cached = media_jack->lane_data.cache.cached;
+	*cache_time = media_jack->lane_data.cache.timestamp_s;
+	spin_unlock(&media_jack->data_lock);
+
+	sl_media_log_dbg(media_jack, LOG_NAME,
+			 "signal cache time get (cache_time = %lld, cached = %s)",
+			 *cache_time, cached ? "yes" : "no");
+
+	return cached ? 0 : -ENOENT;
+}
+
+int sl_media_jack_attr_error_map_str(unsigned long error_map, char *error_str, unsigned int error_str_size)
+{
+	int rtn;
+	int str_pos;
+	int which;
+
+	if (!error_str)
+		return -EINVAL;
+
+	if (error_str_size < SL_MEDIA_JACK_ATTR_ERR_STR_SIZE)
+		return -EINVAL;
+
+	if (!error_map) {
+		str_pos = snprintf(error_str, error_str_size, "none ");
+		goto out;
+	}
+
+	str_pos = 0;
+
+	for_each_set_bit(which, &error_map, sizeof(error_map) * BITS_PER_BYTE) {
+		switch (BIT(which)) {
+		case SL_MEDIA_ERROR_CABLE_UNSUPPORTED:
+			rtn = snprintf(error_str + str_pos, error_str_size - str_pos, "cable-unsupported ");
+			break;
+		case SL_MEDIA_ERROR_CABLE_FORMAT_UNSUPPORTED:
+			rtn = snprintf(error_str + str_pos, error_str_size - str_pos, "cable-format-unsupported ");
+			break;
+		case SL_MEDIA_ERROR_CABLE_FW_UNSUPPORTED:
+			rtn = snprintf(error_str + str_pos, error_str_size - str_pos, "cable-fw-unsupported ");
+			break;
+		case SL_MEDIA_ERROR_CABLE_HEADSHELL_FAULT:
+			rtn = snprintf(error_str + str_pos, error_str_size - str_pos, "cable-headshell-fault ");
+			break;
+		case SL_MEDIA_ERROR_TEMP_DOWN_LIMIT_DEFAULT:
+			rtn = snprintf(error_str + str_pos, error_str_size - str_pos, "temp-down-limit-default ");
+			break;
+		case SL_MEDIA_ERROR_TEMP_WARN_LIMIT_DEFAULT:
+			rtn = snprintf(error_str + str_pos, error_str_size - str_pos, "temp-warn-limit-default ");
+			break;
+		case SL_MEDIA_ERROR_TRYABLE:
+			rtn = snprintf(error_str + str_pos, error_str_size - str_pos, "tryable ");
+			break;
+		default:
+			rtn = snprintf(error_str + str_pos, error_str_size - str_pos, "unknown ");
+			break;
+		}
+
+		if (rtn < 0) {
+			str_pos = snprintf(error_str, error_str_size, "error ");
+			goto out;
+		}
+		if (str_pos + rtn >= error_str_size) {
+			error_str[str_pos - 2] = '.';
+			error_str[str_pos - 3] = '.';
+			error_str[str_pos - 4] = '.';
+			break;
+		}
+		str_pos += rtn;
+	}
+
+out:
+	error_str[str_pos - 1] = '\0';
+
+	return 0;
+}
+
+int sl_media_jack_attr_error_map_get(struct sl_media_jack *media_jack, u32 *error_map)
+{
+	spin_lock(&media_jack->data_lock);
+	*error_map = media_jack->cable_info->media_attr.errors;
+	spin_unlock(&media_jack->data_lock);
+
+	sl_media_log_dbg(media_jack, LOG_NAME, "attr error map get (error_map = %u)", *error_map);
+
+	return 0;
+}
diff --git a/drivers/net/ethernet/hpe/sl/media/sl_media_ldev.c b/drivers/net/ethernet/hpe/sl/media/sl_media_ldev.c
new file mode 100644
index 000000000000..a78d70494b5c
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/media/sl_media_ldev.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2024 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+
+#include "sl_media_ldev.h"
+#include "data/sl_media_data_ldev.h"
+
+int sl_media_ldev_new(u8 ldev_num, struct workqueue_struct *workqueue)
+{
+	return sl_media_data_ldev_new(ldev_num, workqueue);
+}
+
+void sl_media_ldev_del(u8 ldev_num)
+{
+	sl_media_data_ldev_del(ldev_num);
+}
+
+struct sl_media_ldev *sl_media_ldev_get(u8 ldev_num)
+{
+	return sl_media_data_ldev_get(ldev_num);
+}
diff --git a/drivers/net/ethernet/hpe/sl/media/sl_media_lgrp.c b/drivers/net/ethernet/hpe/sl/media/sl_media_lgrp.c
new file mode 100644
index 000000000000..b15805a82270
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/media/sl_media_lgrp.c
@@ -0,0 +1,498 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2023-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/slab.h>
+#include <linux/types.h>
+
+#include "base/sl_media_log.h"
+
+#include "sl_media_lgrp.h"
+#include "sl_media_jack.h"
+#include "data/sl_media_data_lgrp.h"
+#include "data/sl_media_data_jack.h"
+
+#define LOG_NAME SL_MEDIA_LGRP_LOG_NAME
+
+int sl_media_lgrp_new(u8 ldev_num, u8 lgrp_num)
+{
+	return sl_media_data_lgrp_new(ldev_num, lgrp_num);
+}
+
+void sl_media_lgrp_del(u8 ldev_num, u8 lgrp_num)
+{
+	sl_media_data_lgrp_del(ldev_num, lgrp_num);
+}
+
+struct sl_media_lgrp *sl_media_lgrp_get(u8 ldev_num, u8 lgrp_num)
+{
+	return sl_media_data_lgrp_get(ldev_num, lgrp_num);
+}
+
+void sl_media_lgrp_media_attr_get(u8 ldev_num, u8 lgrp_num, struct sl_media_attr *media_attr)
+{
+	struct sl_media_lgrp *media_lgrp;
+
+	memset(media_attr, 0, sizeof(struct sl_media_attr));
+
+	media_lgrp = sl_media_data_lgrp_get(ldev_num, lgrp_num);
+	if (!media_lgrp) {
+		sl_media_log_err(NULL, SL_MEDIA_LGRP_LOG_NAME, "media_data_lgrp_get failed");
+		return;
+	}
+
+	sl_media_log_dbg(media_lgrp, SL_MEDIA_LGRP_LOG_NAME, "media_attr_get");
+
+	spin_lock(&media_lgrp->media_jack->data_lock);
+	switch (media_lgrp->cable_info->real_cable_status) {
+	case CABLE_MEDIA_ATTR_ADDED:
+		*media_attr = media_lgrp->cable_info->media_attr;
+		break;
+	case CABLE_MEDIA_ATTR_STASHED:
+		*media_attr = media_lgrp->cable_info->stashed_media_attr;
+		break;
+	}
+	spin_unlock(&media_lgrp->media_jack->data_lock);
+}
+
+bool sl_media_lgrp_media_has_error(struct sl_media_lgrp *media_lgrp)
+{
+	struct sl_media_attr media_attr;
+
+	sl_media_lgrp_media_attr_get(media_lgrp->media_ldev->num, media_lgrp->num, &media_attr);
+
+	sl_media_log_dbg(media_lgrp, SL_MEDIA_LGRP_LOG_NAME,
+			 "media has error (media_attr.errors = 0x%X)", media_attr.errors);
+
+	return ((media_attr.errors & (SL_MEDIA_ERROR_CABLE_FORMAT_UNSUPPORTED |
+				      SL_MEDIA_ERROR_CABLE_FW_UNSUPPORTED)) != 0);
+}
+
+void sl_media_lgrp_media_serdes_settings_get(u8 ldev_num, u8 lgrp_num,
+					     struct sl_media_serdes_settings *media_serdes_settings)
+{
+	struct sl_media_lgrp *media_lgrp;
+
+	media_lgrp = sl_media_data_lgrp_get(ldev_num, lgrp_num);
+	sl_media_log_dbg(media_lgrp, SL_MEDIA_LGRP_LOG_NAME, "media serdes settings get");
+
+	*media_serdes_settings = media_lgrp->media_jack->serdes_settings;
+}
+
+bool sl_media_lgrp_media_type_is_active(u8 ldev_num, u8 lgrp_num)
+{
+	struct sl_media_attr media_attr;
+
+	sl_media_lgrp_media_attr_get(ldev_num, lgrp_num, &media_attr);
+
+	return SL_MEDIA_LGRP_MEDIA_TYPE_IS_ACTIVE(media_attr.type);
+}
+
+void sl_media_lgrp_connect_id_set(u8 ldev_num, u8 lgrp_num, const char *connect_id)
+{
+	sl_media_data_lgrp_connect_id_set(sl_media_data_lgrp_get(ldev_num, lgrp_num), connect_id);
+}
+
+void sl_media_lgrp_real_cable_if_present_send(u8 ldev_num, u8 lgrp_num)
+{
+	struct sl_media_lgrp *media_lgrp;
+
+	media_lgrp = sl_media_data_lgrp_get(ldev_num, lgrp_num);
+
+	sl_media_log_dbg(media_lgrp, SL_MEDIA_LGRP_LOG_NAME, "real cable if present send");
+
+	sl_media_data_jack_cable_if_present_send(media_lgrp);
+}
+
+void sl_media_lgrp_real_cable_if_not_present_send(u8 ldev_num, u8 lgrp_num)
+{
+	struct sl_media_lgrp *media_lgrp;
+
+	media_lgrp = sl_media_data_lgrp_get(ldev_num, lgrp_num);
+
+	sl_media_log_dbg(media_lgrp, SL_MEDIA_LGRP_LOG_NAME, "real cable if not present send");
+
+	sl_media_data_jack_cable_if_not_present_send(media_lgrp);
+}
+
+void sl_media_lgrp_cable_hot_send(u8 ldev_num, u8 lgrp_num)
+{
+	struct sl_media_lgrp *media_lgrp;
+
+	media_lgrp = sl_media_lgrp_get(ldev_num, lgrp_num);
+
+	sl_media_log_dbg(media_lgrp, SL_MEDIA_LGRP_LOG_NAME, "cable hot send");
+
+	if (sl_media_lgrp_media_type_is_active(ldev_num, lgrp_num)) {
+		sl_media_lgrp_hot_client_ready_set(ldev_num, lgrp_num, true);
+		if (sl_media_jack_cable_temp_hw_check(media_lgrp->media_jack) == SL_MEDIA_JACK_TEMP_STATE_HOT) {
+			sl_media_jack_fault_cause_set(media_lgrp->media_jack, SL_MEDIA_FAULT_CAUSE_HOT);
+			sl_media_jack_cable_hot_notif_send(media_lgrp->media_jack);
+		}
+	}
+}
+
+void sl_media_lgrp_cable_warm_send(u8 ldev_num, u8 lgrp_num)
+{
+	struct sl_media_lgrp *media_lgrp;
+
+	media_lgrp = sl_media_lgrp_get(ldev_num, lgrp_num);
+
+	sl_media_log_dbg(media_lgrp, SL_MEDIA_LGRP_LOG_NAME, "cable warm send");
+
+	if (sl_media_lgrp_media_type_is_active(ldev_num, lgrp_num)) {
+		sl_media_lgrp_warm_client_ready_set(ldev_num, lgrp_num, true);
+		if (sl_media_jack_cable_temp_hw_check(media_lgrp->media_jack) == SL_MEDIA_JACK_TEMP_STATE_WARM) {
+			sl_media_jack_cable_warm_notif_send(media_lgrp->media_jack);
+		}
+	}
+}
+
+void sl_media_lgrp_cable_cold_send(u8 ldev_num, u8 lgrp_num)
+{
+	struct sl_media_lgrp *media_lgrp;
+
+	media_lgrp = sl_media_lgrp_get(ldev_num, lgrp_num);
+
+	sl_media_log_dbg(media_lgrp, SL_MEDIA_LGRP_LOG_NAME, "cable cold send");
+
+	if (sl_media_lgrp_media_type_is_active(ldev_num, lgrp_num)) {
+		sl_media_lgrp_cold_client_ready_set(ldev_num, lgrp_num, true);
+		if (sl_media_jack_cable_temp_hw_check(media_lgrp->media_jack) == SL_MEDIA_JACK_TEMP_STATE_COLD)
+			sl_media_jack_cable_cold_notif_send(media_lgrp->media_jack);
+	}
+}
+
+void sl_media_lgrp_cable_temp_flags_clr(u8 ldev_num, u8 lgrp_num)
+{
+	u8                   i;
+	struct sl_media_lgrp *media_lgrp;
+
+	media_lgrp = sl_media_lgrp_get(ldev_num, lgrp_num);
+
+	sl_media_log_dbg(media_lgrp, SL_MEDIA_LGRP_LOG_NAME, "cable temp flags clr");
+
+	for (i = 0; i < media_lgrp->media_jack->port_count; ++i) {
+		if (sl_media_lgrp_media_type_is_active(ldev_num, lgrp_num)) {
+			sl_media_lgrp_hot_client_ready_set(ldev_num, lgrp_num, false);
+			sl_media_jack_cable_hot_notif_sent_set(media_lgrp->media_jack,
+							       &media_lgrp->media_jack->cable_info[i], false);
+			sl_media_lgrp_warm_client_ready_set(ldev_num, lgrp_num, false);
+			sl_media_jack_cable_warm_notif_sent_set(media_lgrp->media_jack,
+								&media_lgrp->media_jack->cable_info[i], false);
+			sl_media_lgrp_cold_client_ready_set(ldev_num, lgrp_num, false);
+			sl_media_jack_cable_cold_notif_sent_set(media_lgrp->media_jack,
+								&media_lgrp->media_jack->cable_info[i], false);
+		}
+	}
+}
+
+void sl_media_lgrp_hot_client_ready_set(u8 ldev_num, u8 lgrp_num, bool value)
+{
+	struct sl_media_lgrp *media_lgrp;
+
+	media_lgrp = sl_media_data_lgrp_get(ldev_num, lgrp_num);
+
+	sl_media_log_dbg(media_lgrp, SL_MEDIA_LGRP_LOG_NAME, "hot client ready set (value = %s)",
+			 value ? "true" : "false");
+
+	spin_lock(&media_lgrp->media_jack->data_lock);
+	media_lgrp->cable_info->hot_client_ready = value;
+	spin_unlock(&media_lgrp->media_jack->data_lock);
+}
+
+void sl_media_lgrp_warm_client_ready_set(u8 ldev_num, u8 lgrp_num, bool value)
+{
+	struct sl_media_lgrp *media_lgrp;
+
+	media_lgrp = sl_media_data_lgrp_get(ldev_num, lgrp_num);
+
+	sl_media_log_dbg(media_lgrp, SL_MEDIA_LGRP_LOG_NAME, "warm client ready set (value = %s)",
+			 value ? "true" : "false");
+
+	spin_lock(&media_lgrp->media_jack->data_lock);
+	media_lgrp->cable_info->warm_client_ready = value;
+	spin_unlock(&media_lgrp->media_jack->data_lock);
+}
+
+void sl_media_lgrp_cold_client_ready_set(u8 ldev_num, u8 lgrp_num, bool value)
+{
+	struct sl_media_lgrp *media_lgrp;
+
+	media_lgrp = sl_media_data_lgrp_get(ldev_num, lgrp_num);
+
+	sl_media_log_dbg(media_lgrp, SL_MEDIA_LGRP_LOG_NAME, "cold client ready set (value = %s)",
+			 value ? "true" : "false");
+
+	spin_lock(&media_lgrp->media_jack->data_lock);
+	media_lgrp->cable_info->cold_client_ready = value;
+	spin_unlock(&media_lgrp->media_jack->data_lock);
+}
+
+int sl_media_lgrp_vendor_get(struct sl_media_lgrp *media_lgrp, u32 *vendor)
+{
+	spin_lock(&media_lgrp->media_jack->data_lock);
+	switch (media_lgrp->cable_info->real_cable_status) {
+	case CABLE_MEDIA_ATTR_ADDED:
+		*vendor = media_lgrp->cable_info->media_attr.vendor;
+		break;
+	case CABLE_MEDIA_ATTR_STASHED:
+		*vendor = media_lgrp->cable_info->stashed_media_attr.vendor;
+		break;
+	default:
+		*vendor = SL_MEDIA_VENDOR_UNKNOWN;
+	}
+	spin_unlock(&media_lgrp->media_jack->data_lock);
+
+	return 0;
+}
+
+int sl_media_lgrp_vendor_pn_str_get(struct sl_media_lgrp *media_lgrp, char *vendor_pn_str)
+{
+	spin_lock(&media_lgrp->media_jack->data_lock);
+	switch (media_lgrp->cable_info->real_cable_status) {
+	case CABLE_MEDIA_ATTR_ADDED:
+		strscpy_pad(vendor_pn_str,
+			    media_lgrp->cable_info->media_attr.vendor_pn_str, SL_MEDIA_VENDOR_PN_SIZE);
+		break;
+	case CABLE_MEDIA_ATTR_STASHED:
+		strscpy_pad(vendor_pn_str,
+			    media_lgrp->cable_info->stashed_media_attr.vendor_pn_str, SL_MEDIA_VENDOR_PN_SIZE);
+		break;
+	default:
+		memset(vendor_pn_str, '0', SL_MEDIA_VENDOR_PN_SIZE - 2);
+		vendor_pn_str[SL_MEDIA_VENDOR_PN_SIZE - 1] = '\0';
+	}
+	spin_unlock(&media_lgrp->media_jack->data_lock);
+
+	return 0;
+}
+
+int sl_media_lgrp_type_get(struct sl_media_lgrp *media_lgrp, u32 *type)
+{
+	spin_lock(&media_lgrp->media_jack->data_lock);
+	switch (media_lgrp->cable_info->real_cable_status) {
+	case CABLE_MEDIA_ATTR_ADDED:
+		*type = media_lgrp->cable_info->media_attr.type;
+		break;
+	case CABLE_MEDIA_ATTR_STASHED:
+		*type = media_lgrp->cable_info->stashed_media_attr.type;
+		break;
+	default:
+		*type = SL_MEDIA_TYPE_UNKNOWN;
+	}
+	spin_unlock(&media_lgrp->media_jack->data_lock);
+
+	return 0;
+}
+
+int sl_media_lgrp_shape_get(struct sl_media_lgrp *media_lgrp, u32 *shape)
+{
+	spin_lock(&media_lgrp->media_jack->data_lock);
+	switch (media_lgrp->cable_info->real_cable_status) {
+	case CABLE_MEDIA_ATTR_ADDED:
+		*shape = media_lgrp->cable_info->media_attr.shape;
+		break;
+	case CABLE_MEDIA_ATTR_STASHED:
+		*shape = media_lgrp->cable_info->stashed_media_attr.shape;
+		break;
+	default:
+		*shape = SL_MEDIA_SHAPE_UNKNOWN;
+	}
+	spin_unlock(&media_lgrp->media_jack->data_lock);
+
+	return 0;
+}
+
+int sl_media_lgrp_length_get(struct sl_media_lgrp *media_lgrp, u32 *length_cm)
+{
+	spin_lock(&media_lgrp->media_jack->data_lock);
+	switch (media_lgrp->cable_info->real_cable_status) {
+	case CABLE_MEDIA_ATTR_ADDED:
+		*length_cm = media_lgrp->cable_info->media_attr.length_cm;
+		break;
+	case CABLE_MEDIA_ATTR_STASHED:
+		*length_cm = media_lgrp->cable_info->stashed_media_attr.length_cm;
+		break;
+	default:
+		*length_cm = 0;
+	}
+	spin_unlock(&media_lgrp->media_jack->data_lock);
+
+	return 0;
+}
+
+int sl_media_lgrp_max_speed_get(struct sl_media_lgrp *media_lgrp, u32 *max_speed)
+{
+	spin_lock(&media_lgrp->media_jack->data_lock);
+	switch (media_lgrp->cable_info->real_cable_status) {
+	case CABLE_MEDIA_ATTR_ADDED:
+		*max_speed = media_lgrp->cable_info->media_attr.max_speed;
+		break;
+	case CABLE_MEDIA_ATTR_STASHED:
+		*max_speed = media_lgrp->cable_info->stashed_media_attr.max_speed;
+		break;
+	default:
+		*max_speed = 0;
+	}
+	spin_unlock(&media_lgrp->media_jack->data_lock);
+
+	return 0;
+}
+
+int sl_media_lgrp_serial_num_str_get(struct sl_media_lgrp *media_lgrp, char *serial_num_str)
+{
+	spin_lock(&media_lgrp->media_jack->data_lock);
+	switch (media_lgrp->cable_info->real_cable_status) {
+	case CABLE_MEDIA_ATTR_ADDED:
+		strscpy_pad(serial_num_str,
+			    media_lgrp->cable_info->media_attr.serial_num_str, SL_MEDIA_SERIAL_NUM_SIZE);
+		break;
+	case CABLE_MEDIA_ATTR_STASHED:
+		strscpy_pad(serial_num_str,
+			    media_lgrp->cable_info->stashed_media_attr.serial_num_str, SL_MEDIA_SERIAL_NUM_SIZE);
+		break;
+	default:
+		memset(serial_num_str, '0', (SL_MEDIA_SERIAL_NUM_SIZE - 1));
+		serial_num_str[SL_MEDIA_SERIAL_NUM_SIZE - 1] = '\0';
+	}
+	spin_unlock(&media_lgrp->media_jack->data_lock);
+
+	return 0;
+}
+
+int sl_media_lgrp_hpe_pn_str_get(struct sl_media_lgrp *media_lgrp, char *hpe_pn_str)
+{
+	spin_lock(&media_lgrp->media_jack->data_lock);
+	switch (media_lgrp->cable_info->real_cable_status) {
+	case CABLE_MEDIA_ATTR_ADDED:
+		strscpy_pad(hpe_pn_str,
+			    media_lgrp->cable_info->media_attr.hpe_pn_str, SL_MEDIA_HPE_PN_SIZE);
+		break;
+	case CABLE_MEDIA_ATTR_STASHED:
+		strscpy_pad(hpe_pn_str,
+			    media_lgrp->cable_info->stashed_media_attr.hpe_pn_str, SL_MEDIA_HPE_PN_SIZE);
+		break;
+	default:
+		memset(hpe_pn_str, '0', SL_MEDIA_HPE_PN_SIZE - 2);
+		hpe_pn_str[SL_MEDIA_HPE_PN_SIZE - 1] = '\0';
+	}
+	spin_unlock(&media_lgrp->media_jack->data_lock);
+
+	return 0;
+}
+
+int sl_media_lgrp_jack_type_get(struct sl_media_lgrp *media_lgrp, u32 *jack_type)
+{
+	spin_lock(&media_lgrp->media_jack->data_lock);
+	switch (media_lgrp->cable_info->real_cable_status) {
+	case CABLE_MEDIA_ATTR_ADDED:
+		*jack_type = media_lgrp->cable_info->media_attr.jack_type;
+		break;
+	case CABLE_MEDIA_ATTR_STASHED:
+		*jack_type = media_lgrp->cable_info->stashed_media_attr.jack_type;
+		break;
+	default:
+		*jack_type = SL_MEDIA_JACK_TYPE_UNKNOWN;
+	}
+	spin_unlock(&media_lgrp->media_jack->data_lock);
+
+	return 0;
+}
+
+int sl_media_lgrp_jack_type_qsfp_density_get(struct sl_media_lgrp *media_lgrp, u32 *density)
+{
+	spin_lock(&media_lgrp->media_jack->data_lock);
+	switch (media_lgrp->cable_info->real_cable_status) {
+	case CABLE_MEDIA_ATTR_ADDED:
+		*density = media_lgrp->cable_info->media_attr.jack_type_info.qsfp.density;
+		break;
+	case CABLE_MEDIA_ATTR_STASHED:
+		*density = media_lgrp->cable_info->stashed_media_attr.jack_type_info.qsfp.density;
+		break;
+	default:
+		*density = SL_MEDIA_QSFP_DENSITY_UNKNOWN;
+	}
+	spin_unlock(&media_lgrp->media_jack->data_lock);
+
+	return 0;
+}
+
+int sl_media_lgrp_furcation_get(struct sl_media_lgrp *media_lgrp, u32 *furcation)
+{
+	spin_lock(&media_lgrp->media_jack->data_lock);
+	switch (media_lgrp->cable_info->real_cable_status) {
+	case CABLE_MEDIA_ATTR_ADDED:
+		*furcation = media_lgrp->cable_info->media_attr.furcation;
+		break;
+	case CABLE_MEDIA_ATTR_STASHED:
+		*furcation = media_lgrp->cable_info->stashed_media_attr.furcation;
+		break;
+	default:
+		*furcation = SL_MEDIA_FURCATION_UNKNOWN;
+	}
+	spin_unlock(&media_lgrp->media_jack->data_lock);
+
+	return 0;
+}
+
+bool sl_media_lgrp_is_cable_unsupported(struct sl_media_lgrp *media_lgrp)
+{
+	bool unsupported;
+
+	spin_lock(&media_lgrp->media_jack->data_lock);
+	unsupported = media_lgrp->media_jack->is_cable_unsupported;
+	spin_unlock(&media_lgrp->media_jack->data_lock);
+
+	return unsupported;
+}
+
+int sl_media_lgrp_date_code_str_get(struct sl_media_lgrp *media_lgrp, char *date_code_str)
+{
+	spin_lock(&media_lgrp->media_jack->data_lock);
+	switch (media_lgrp->cable_info->real_cable_status) {
+	case CABLE_MEDIA_ATTR_ADDED:
+		strscpy_pad(date_code_str,
+			    media_lgrp->cable_info->media_attr.date_code_str, SL_MEDIA_DATE_CODE_SIZE);
+		break;
+	case CABLE_MEDIA_ATTR_STASHED:
+		strscpy_pad(date_code_str,
+			    media_lgrp->cable_info->stashed_media_attr.date_code_str, SL_MEDIA_DATE_CODE_SIZE);
+		break;
+	default:
+		memset(date_code_str, '0', SL_MEDIA_DATE_CODE_SIZE - 2);
+		date_code_str[SL_MEDIA_DATE_CODE_SIZE - 1] = '\0';
+	}
+	spin_unlock(&media_lgrp->media_jack->data_lock);
+
+	return 0;
+}
+
+int sl_media_lgrp_fw_ver_str_get(struct sl_media_lgrp *media_lgrp, u8 *fw_ver)
+{
+	spin_lock(&media_lgrp->media_jack->data_lock);
+	switch (media_lgrp->cable_info->real_cable_status) {
+	case CABLE_MEDIA_ATTR_ADDED:
+		memcpy(fw_ver, media_lgrp->cable_info->media_attr.fw_ver, SL_MEDIA_FIRMWARE_VERSION_SIZE);
+		break;
+	case CABLE_MEDIA_ATTR_STASHED:
+		memcpy(fw_ver, media_lgrp->cable_info->stashed_media_attr.fw_ver, SL_MEDIA_FIRMWARE_VERSION_SIZE);
+		break;
+	default:
+		memset(fw_ver, 0, SL_MEDIA_FIRMWARE_VERSION_SIZE);
+	}
+	spin_unlock(&media_lgrp->media_jack->data_lock);
+
+	return 0;
+}
+
+bool sl_media_lgrp_is_signal_status_supported(u8 ldev_num, u8 lgrp_num)
+{
+	struct sl_media_attr media_attr;
+
+	sl_media_lgrp_media_attr_get(ldev_num, lgrp_num, &media_attr);
+
+	return (media_attr.supported_flags_advertised[0] & SL_MEDIA_ADVERTISED_FLAGS_TX_LOS) ||
+	       (media_attr.supported_flags_advertised[0] & SL_MEDIA_ADVERTISED_FLAGS_TX_LOL) ||
+	       (media_attr.supported_flags_advertised[1] & SL_MEDIA_ADVERTISED_FLAGS_RX_LOS) ||
+	       (media_attr.supported_flags_advertised[1] & SL_MEDIA_ADVERTISED_FLAGS_RX_LOL);
+}

-- 
2.56.0


^ permalink raw reply	[flat|nested] 25+ messages in thread
* [PATCH 14/23] net: hpe: sl: add the sysfs interface
  2026-10-30 20:58 [PATCH 00/23] Subject: [PATCH net-next 00/23] net/hpe: add HPE Slingshot NIC drivers Doug Ledford
                   ` (12 preceding siblings ...)
  2026-10-30 20:59 ` [PATCH 13/23] net: hpe: sl: add media and cable handling Doug Ledford
@ 2026-10-30 20:59 ` Doug Ledford
  2026-10-30 20:59 ` [PATCH 15/23] net: hpe: sl: add the NIC binding and logging helpers Doug Ledford
                   ` (9 subsequent siblings)
  23 siblings, 0 replies; 25+ messages in thread
From: Doug Ledford @ 2026-10-30 20:59 UTC (permalink / raw)
  To: Slingshot Open Source Team, Nathan Chancellor, Nicolas Schier,
	Richard Cochran, Andrew Lunn, David S. Miller, Eric Dumazet,
	Jakub Kicinski, Paolo Abeni, Sumit Semwal, Christian König,
	Guenter Roeck
  Cc: linux-kernel, netdev, linux-kbuild, Doug Ledford, Sandeep Bhoot

Add the sysfs interface for logical devices, link groups, links, LLR,
MAC, media, SerDes, SBus and PMI.  The many small files follow the
one-attribute-per-file sysfs rule.

Known open issue (Sashiko L14, V2): the SL sysfs tree (about 378
attributes) has no Documentation/ABI entries yet. The attribute
documentation, including which attributes are stable interfaces and
which belong in debugfs, is being prepared with the hardware engineers
and will be part of V2.

checkpatch --strict (100 columns) still reports the following in this
patch. They need coordination with the internal repositories this code
is maintained in and will be fixed in V2:
- WARNING: LONG_LINE (586), CONST_STRUCT (60), LONG_LINE_STRING (20)
- CHECK: UNNECESSARY_PARENTHESES (63), BRACES (1)

Co-developed-by: Sandeep Bhoot <sandeep.bhoot@hpe.com>
Signed-off-by: Sandeep Bhoot <sandeep.bhoot@hpe.com>
Signed-off-by: Doug Ledford <doug.ledford@hpe.com>
---
 drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_ldev.c  |  410 ++++++
 drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_lgrp.c  |   98 ++
 .../ethernet/hpe/sl/sysfs/sl_sysfs_lgrp_config.c   |  438 ++++++
 .../ethernet/hpe/sl/sysfs/sl_sysfs_lgrp_policy.c   |   53 +
 drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link.c  |  830 +++++++++++
 .../net/ethernet/hpe/sl/sysfs/sl_sysfs_link_caps.c |  303 ++++
 .../ethernet/hpe/sl/sysfs/sl_sysfs_link_config.c   |  388 +++++
 .../ethernet/hpe/sl/sysfs/sl_sysfs_link_counters.c | 1498 ++++++++++++++++++++
 .../ethernet/hpe/sl/sysfs/sl_sysfs_link_degrade.c  |  336 +++++
 .../net/ethernet/hpe/sl/sysfs/sl_sysfs_link_fec.c  |  148 ++
 .../hpe/sl/sysfs/sl_sysfs_link_fec_current.c       |  336 +++++
 .../ethernet/hpe/sl/sysfs/sl_sysfs_link_fec_down.c |  316 +++++
 .../hpe/sl/sysfs/sl_sysfs_link_fec_mon_check.c     |  195 +++
 .../ethernet/hpe/sl/sysfs/sl_sysfs_link_fec_up.c   |  299 ++++
 .../hpe/sl/sysfs/sl_sysfs_link_fec_up_check.c      |  137 ++
 .../ethernet/hpe/sl/sysfs/sl_sysfs_link_pml_rec.c  |  193 +++
 .../ethernet/hpe/sl/sysfs/sl_sysfs_link_policy.c   |  261 ++++
 drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_llr.c   |  221 +++
 .../ethernet/hpe/sl/sysfs/sl_sysfs_llr_config.c    |  140 ++
 .../ethernet/hpe/sl/sysfs/sl_sysfs_llr_counters.c  |  397 ++++++
 .../ethernet/hpe/sl/sysfs/sl_sysfs_llr_loop_time.c |  221 +++
 .../ethernet/hpe/sl/sysfs/sl_sysfs_llr_policy.c    |   74 +
 drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_mac.c   |  192 +++
 .../ethernet/hpe/sl/sysfs/sl_sysfs_mac_counters.c  |  339 +++++
 drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_media.c | 1274 +++++++++++++++++
 .../hpe/sl/sysfs/sl_sysfs_media_counters.c         |  599 ++++++++
 drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_pmi.c   |   80 ++
 .../net/ethernet/hpe/sl/sysfs/sl_sysfs_pmi_rd.c    |  197 +++
 .../net/ethernet/hpe/sl/sysfs/sl_sysfs_pmi_wr.c    |  220 +++
 drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_sbus.c  |   89 ++
 .../net/ethernet/hpe/sl/sysfs/sl_sysfs_sbus_pmi.c  |   80 ++
 .../ethernet/hpe/sl/sysfs/sl_sysfs_sbus_pmi_rd.c   |  244 ++++
 .../ethernet/hpe/sl/sysfs/sl_sysfs_sbus_pmi_wr.c   |  244 ++++
 .../net/ethernet/hpe/sl/sysfs/sl_sysfs_sbus_rd.c   |  197 +++
 .../net/ethernet/hpe/sl/sysfs/sl_sysfs_sbus_rst.c  |  105 ++
 .../net/ethernet/hpe/sl/sysfs/sl_sysfs_sbus_wr.c   |  197 +++
 .../net/ethernet/hpe/sl/sysfs/sl_sysfs_serdes.c    |  302 ++++
 .../ethernet/hpe/sl/sysfs/sl_sysfs_serdes_eye.c    |  197 +++
 .../ethernet/hpe/sl/sysfs/sl_sysfs_serdes_lol.c    |  141 ++
 .../ethernet/hpe/sl/sysfs/sl_sysfs_serdes_los.c    |  142 ++
 .../hpe/sl/sysfs/sl_sysfs_serdes_settings.c        |  506 +++++++
 .../ethernet/hpe/sl/sysfs/sl_sysfs_serdes_state.c  |  121 ++
 .../hpe/sl/sysfs/sl_sysfs_serdes_swizzle.c         |  126 ++
 43 files changed, 12884 insertions(+)

diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_ldev.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_ldev.c
new file mode 100644
index 000000000000..9aac5aa41404
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_ldev.c
@@ -0,0 +1,410 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2024-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kobject.h>
+#include <linux/sysfs.h>
+
+#include <linux/hpe/sl/sl_media.h>
+
+#include "sl.h"
+#include "sl_log.h"
+#include "sl_sysfs.h"
+#include "sl_ctrl_ldev.h"
+#include "sl_module.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+#ifdef CONFIG_SYSFS
+static const char *sl_cable_type_str(u32 type)
+{
+	switch (type) {
+	case SL_CABLE_TYPE_PEC:
+		return "PEC";
+	case SL_CABLE_TYPE_AOC:
+		return "AOC";
+	case SL_CABLE_TYPE_POC:
+		return "POC";
+	case SL_CABLE_TYPE_AEC:
+		return "AEC";
+	default:
+		return "unknown";
+	}
+}
+
+static ssize_t mod_ver_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_ldev *ctrl_ldev;
+
+	ctrl_ldev = container_of(kobj, struct sl_ctrl_ldev, sl_info_kobj);
+
+	sl_log_dbg(ctrl_ldev, LOG_BLOCK, LOG_NAME,
+		   "mod ver show (ldev = 0x%p, ver = v%s)", ctrl_ldev, sl_version_str_get());
+
+	return sysfs_emit(buf, "v%s\n", sl_version_str_get());
+}
+
+static ssize_t mod_hash_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_ldev *ctrl_ldev;
+
+	ctrl_ldev = container_of(kobj, struct sl_ctrl_ldev, sl_info_kobj);
+
+	sl_log_dbg(ctrl_ldev, LOG_BLOCK, LOG_NAME,
+		   "mod hash show (ldev = 0x%p, hash = %s)", ctrl_ldev, sl_git_hash_str_get());
+
+	return sysfs_emit(buf, "%s\n", sl_git_hash_str_get());
+}
+
+static struct kobj_attribute mod_ver  = __ATTR_RO(mod_ver);
+static struct kobj_attribute mod_hash = __ATTR_RO(mod_hash);
+
+static struct attribute *ldev_attrs[] = {
+	&mod_ver.attr,
+	&mod_hash.attr,
+	NULL
+};
+ATTRIBUTE_GROUPS(ldev);
+
+static struct kobj_type sl_info = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = ldev_groups,
+};
+
+static struct attribute *supported_cables_attrs[] = {
+	NULL,
+};
+ATTRIBUTE_GROUPS(supported_cables);
+
+static struct kobj_type supported_cables_info = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = supported_cables_groups,
+};
+
+static struct attribute *cable_types_attrs[] = {
+	NULL,
+};
+ATTRIBUTE_GROUPS(cable_types);
+
+static struct kobj_type cable_types_info = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = cable_types_groups,
+};
+
+static struct attribute *cable_vendors_attrs[] = {
+	NULL,
+};
+ATTRIBUTE_GROUPS(cable_vendors);
+
+static struct kobj_type cable_vendors_info = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = cable_vendors_groups,
+};
+
+static ssize_t length_cm_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_ldev_cable_hpe_pn_kobj *hpe_pn_kobj;
+
+	hpe_pn_kobj = container_of(kobj, struct sl_ctrl_ldev_cable_hpe_pn_kobj, kobj);
+
+	sl_log_dbg(hpe_pn_kobj->ctrl_ldev, LOG_BLOCK, LOG_NAME,
+		   "length_cm show (ctrl_ldev = 0x%p, length_cm = %u)",
+		   hpe_pn_kobj->ctrl_ldev, cable_db[hpe_pn_kobj->cable_idx].length_cm);
+
+	return sysfs_emit(buf, "%u\n", cable_db[hpe_pn_kobj->cable_idx].length_cm);
+}
+
+static ssize_t max_speed_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_ldev_cable_hpe_pn_kobj *hpe_pn_kobj;
+
+	hpe_pn_kobj = container_of(kobj, struct sl_ctrl_ldev_cable_hpe_pn_kobj, kobj);
+
+	sl_log_dbg(hpe_pn_kobj->ctrl_ldev, LOG_BLOCK, LOG_NAME,
+		   "max_speed show (ctrl_ldev = 0x%p, max_speed = %s)",
+		   hpe_pn_kobj->ctrl_ldev, sl_media_speed_str(cable_db[hpe_pn_kobj->cable_idx].max_speed));
+
+	return sysfs_emit(buf, "%s\n", sl_media_speed_str(cable_db[hpe_pn_kobj->cable_idx].max_speed));
+}
+
+static struct kobj_attribute cable_hpe_pn_length_cm = __ATTR_RO(length_cm);
+static struct kobj_attribute cable_hpe_pn_max_speed = __ATTR_RO(max_speed);
+
+static struct attribute *cable_hpe_pn_attrs[] = {
+	&cable_hpe_pn_length_cm.attr,
+	&cable_hpe_pn_max_speed.attr,
+	NULL,
+};
+ATTRIBUTE_GROUPS(cable_hpe_pn);
+
+static struct kobj_type cable_hpe_pns_info = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = cable_hpe_pn_groups,
+};
+
+static void sl_sysfs_cable_types_delete(struct sl_ctrl_ldev *ctrl_ldev, int type_idx)
+{
+	int k;
+
+	sl_log_dbg(ctrl_ldev, LOG_BLOCK, LOG_NAME, "types delete");
+
+	for (k = 0; k < type_idx; ++k) {
+		sl_log_dbg(ctrl_ldev, LOG_BLOCK, LOG_NAME, "types delete (type = %d)", k);
+		kobject_put(&ctrl_ldev->cable_types_kobj[k]);
+	}
+}
+
+static int sl_sysfs_cable_types_create(struct sl_ctrl_ldev *ctrl_ldev)
+{
+	int type_idx;
+	int rtn;
+
+	sl_log_dbg(ctrl_ldev, LOG_BLOCK, LOG_NAME, "types create");
+
+	for (type_idx = 0; type_idx < SL_CABLE_TYPES_NUM; ++type_idx) {
+		sl_log_dbg(ctrl_ldev, LOG_BLOCK, LOG_NAME, "types create (type = %d)", type_idx);
+		rtn = kobject_init_and_add(&ctrl_ldev->cable_types_kobj[type_idx],
+					   &cable_types_info, &ctrl_ldev->supported_cables_kobj,
+					   sl_cable_type_str(type_idx));
+		if (rtn) {
+			sl_log_err(ctrl_ldev, LOG_BLOCK, LOG_NAME,
+				   "types create failed (type = %d) [%d]", type_idx, rtn);
+			kobject_put(&ctrl_ldev->cable_types_kobj[type_idx]);
+			sl_sysfs_cable_types_delete(ctrl_ldev, type_idx);
+			return -ENOMEM;
+		}
+	}
+
+	return 0;
+}
+
+static void sl_sysfs_cable_vendors_delete(struct sl_ctrl_ldev *ctrl_ldev, int type_idx, int vendor_idx)
+{
+	int k;
+	int l;
+
+	sl_log_dbg(ctrl_ldev, LOG_BLOCK, LOG_NAME, "vendors delete");
+
+	for (k = 0; k < type_idx; ++k) {
+		for (l = 0; l < vendor_idx; ++l) {
+			sl_log_dbg(ctrl_ldev, LOG_BLOCK, LOG_NAME,
+				   "vendors delete (type = %d, vendor = %d)", k, l);
+			kobject_put(&ctrl_ldev->cable_vendors_kobj[k][l]);
+		}
+	}
+}
+
+static int sl_sysfs_cable_vendors_create(struct sl_ctrl_ldev *ctrl_ldev)
+{
+	int type_idx;
+	int vendor_idx;
+	int rtn;
+	int x;
+
+	BUILD_BUG_ON((SL_MEDIA_VENDOR_AMPHENOL > 10) || (SL_CABLE_VENDORS_NUM > 10));
+
+	sl_log_dbg(ctrl_ldev, LOG_BLOCK, LOG_NAME, "vendors create");
+
+	for (type_idx = 0; type_idx < SL_CABLE_TYPES_NUM; ++type_idx) {
+		for (vendor_idx = 0; vendor_idx < SL_CABLE_VENDORS_NUM; ++vendor_idx) {
+			sl_log_dbg(ctrl_ldev, LOG_BLOCK, LOG_NAME,
+				   "vendors create (type = %d, vendor = %d)", type_idx, vendor_idx);
+			rtn = kobject_init_and_add(&ctrl_ldev->cable_vendors_kobj[type_idx][vendor_idx],
+						   &cable_vendors_info, &ctrl_ldev->cable_types_kobj[type_idx],
+						   sl_media_vendor_str(vendor_idx + SL_MEDIA_VENDOR_TE));
+			if (rtn) {
+				sl_log_err(ctrl_ldev, LOG_BLOCK, LOG_NAME,
+					   "vendors create failed (type = %d, vendor = %d) [%d]",
+					   type_idx, vendor_idx, rtn);
+				kobject_put(&ctrl_ldev->cable_vendors_kobj[type_idx][vendor_idx]);
+				for (x = 0; x < vendor_idx; ++x) {
+					sl_log_dbg(ctrl_ldev, LOG_BLOCK, LOG_NAME,
+						   "vendors create delete (type = %d, vendor = %d)", type_idx, x);
+					kobject_put(&ctrl_ldev->cable_vendors_kobj[type_idx][x]);
+				}
+				sl_sysfs_cable_vendors_delete(ctrl_ldev, type_idx, SL_CABLE_VENDORS_NUM);
+				sl_sysfs_cable_types_delete(ctrl_ldev, SL_CABLE_TYPES_NUM);
+				return -ENOMEM;
+			}
+		}
+	}
+
+	return 0;
+}
+
+static void sl_sysfs_cable_db_delete(struct sl_ctrl_ldev *ctrl_ldev, int db_idx)
+{
+	int k;
+
+	sl_log_dbg(ctrl_ldev, LOG_BLOCK, LOG_NAME, "db delete");
+
+	for (k = 0; k < db_idx; ++k) {
+		sl_log_dbg(ctrl_ldev, LOG_BLOCK, LOG_NAME, "db delete (idx = %d)", k);
+		kobject_put(&ctrl_ldev->cable_hpe_pns_kobj[k].kobj);
+	}
+}
+
+static int sl_sysfs_cable_db_create(struct sl_ctrl_ldev *ctrl_ldev)
+{
+	char hpe_pn[SL_MEDIA_HPE_PN_SIZE + SL_MEDIA_VENDOR_PN_SIZE];
+	int  i;
+	int  type_kobj_num;
+	int  rtn;
+
+	sl_log_dbg(ctrl_ldev, LOG_BLOCK, LOG_NAME, "db create");
+
+	for (i = 0; i < ARRAY_SIZE(cable_db); ++i) {
+		sl_log_dbg(ctrl_ldev, LOG_BLOCK, LOG_NAME, "db create (idx = %d)", i);
+		switch (cable_db[i].type) {
+		case SL_MEDIA_TYPE_PEC:
+			type_kobj_num = SL_CABLE_TYPE_PEC;
+			break;
+		case SL_MEDIA_TYPE_AOC:
+			type_kobj_num = SL_CABLE_TYPE_AOC;
+			break;
+		case SL_MEDIA_TYPE_POC:
+			type_kobj_num = SL_CABLE_TYPE_POC;
+			break;
+		case SL_MEDIA_TYPE_AEC:
+			type_kobj_num = SL_CABLE_TYPE_AEC;
+			break;
+		default:
+			sl_log_err(ctrl_ldev, LOG_BLOCK, LOG_NAME,
+				   "unknown (type = %u)", cable_db[i].type);
+			continue;
+		}
+		ctrl_ldev->cable_hpe_pns_kobj[i].ctrl_ldev = ctrl_ldev;
+		ctrl_ldev->cable_hpe_pns_kobj[i].cable_idx = i;
+		snprintf(hpe_pn, sizeof(hpe_pn), "%u_%s", cable_db[i].hpe_pn, cable_db[i].vendor_pn_str);
+		rtn = kobject_init_and_add(&ctrl_ldev->cable_hpe_pns_kobj[i].kobj, &cable_hpe_pns_info,
+					   &ctrl_ldev->cable_vendors_kobj[type_kobj_num][cable_db[i].vendor - SL_MEDIA_VENDOR_TE],
+					   hpe_pn);
+		if (rtn) {
+			sl_log_err(ctrl_ldev, LOG_BLOCK, LOG_NAME,
+				   "hpe_pn create failed (idx = %d, type = 0x%X %s, vendor = %u %s, len = %ucm, hpe_pn = %u) [%d]",
+				   i, cable_db[i].type, sl_media_type_str(cable_db[i].type),
+				   cable_db[i].vendor, sl_media_vendor_str(cable_db[i].vendor),
+				   cable_db[i].length_cm, cable_db[i].hpe_pn, rtn);
+			kobject_put(&ctrl_ldev->cable_hpe_pns_kobj[i].kobj);
+			sl_sysfs_cable_db_delete(ctrl_ldev, i);
+			sl_sysfs_cable_vendors_delete(ctrl_ldev, SL_CABLE_TYPES_NUM, SL_CABLE_VENDORS_NUM);
+			sl_sysfs_cable_types_delete(ctrl_ldev, SL_CABLE_TYPES_NUM);
+			return -ENOMEM;
+		}
+	}
+
+	return 0;
+}
+
+static int sl_sysfs_cable_info_create(struct sl_ctrl_ldev *ctrl_ldev)
+{
+	int rtn;
+
+	sl_log_dbg(ctrl_ldev, LOG_BLOCK, LOG_NAME, "cable info create (ldev = 0x%p)", ctrl_ldev);
+
+	rtn = kobject_init_and_add(&ctrl_ldev->supported_cables_kobj, &supported_cables_info,
+				   ctrl_ldev->parent_kobj, "supported_cables");
+	if (rtn) {
+		sl_log_err(ctrl_ldev, LOG_BLOCK, LOG_NAME, "supported cables create failed [%d]", rtn);
+		kobject_put(&ctrl_ldev->supported_cables_kobj);
+		return -ENOMEM;
+	}
+
+	rtn = sl_sysfs_cable_types_create(ctrl_ldev);
+	if (rtn) {
+		sl_log_err(ctrl_ldev, LOG_BLOCK, LOG_NAME, "cable types create failed [%d]", rtn);
+		kobject_put(&ctrl_ldev->supported_cables_kobj);
+		return rtn;
+	}
+
+	rtn = sl_sysfs_cable_vendors_create(ctrl_ldev);
+	if (rtn) {
+		sl_log_err(ctrl_ldev, LOG_BLOCK, LOG_NAME, "cable vendors create failed [%d]", rtn);
+		kobject_put(&ctrl_ldev->supported_cables_kobj);
+		return rtn;
+	}
+
+	rtn = sl_sysfs_cable_db_create(ctrl_ldev);
+	if (rtn) {
+		sl_log_err(ctrl_ldev, LOG_BLOCK, LOG_NAME, "cable db create failed [%d]", rtn);
+		kobject_put(&ctrl_ldev->supported_cables_kobj);
+		return rtn;
+	}
+
+	return 0;
+}
+#endif /* CONFIG_SYSFS */
+
+int sl_sysfs_ldev_create(u8 ldev_num, struct kobject *parent)
+{
+#ifdef CONFIG_SYSFS
+	int                 rtn;
+	struct sl_ctrl_ldev *ctrl_ldev;
+
+	ctrl_ldev = sl_ctrl_ldev_get(ldev_num);
+	if (!ctrl_ldev) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "sysfs create ldev not found (ldev_num = %u)", ldev_num);
+		return -EBADRQC;
+	}
+
+	if (!sl_ctrl_ldev_kref_get_unless_zero(ctrl_ldev)) {
+		sl_log_err(ctrl_ldev, LOG_BLOCK, LOG_NAME,
+			   "kref_get_unless_zero failed (ldev = 0x%p)", ctrl_ldev);
+		return -EBADRQC;
+	}
+
+	sl_log_dbg(ctrl_ldev, LOG_BLOCK, LOG_NAME, "ldev create (ldev = 0x%p)", ctrl_ldev);
+
+	if (ctrl_ldev->is_sysfs_ok) {
+		rtn = 0;
+		goto out;
+	}
+
+	ctrl_ldev->parent_kobj = parent;
+	ctrl_ldev->is_sysfs_ok = false;
+
+	rtn = kobject_init_and_add(&(ctrl_ldev->sl_info_kobj), &sl_info, ctrl_ldev->parent_kobj, "sl_info");
+	if (rtn) {
+		sl_log_err(ctrl_ldev, LOG_BLOCK, LOG_NAME, "sl_info create failed [%d]", rtn);
+		kobject_put(&ctrl_ldev->sl_info_kobj);
+		rtn = -ENOMEM;
+		goto out;
+	}
+
+	rtn = sl_sysfs_cable_info_create(ctrl_ldev);
+	if (rtn) {
+		sl_log_err(ctrl_ldev, LOG_BLOCK, LOG_NAME, "cable info create failed [%d]", rtn);
+		kobject_put(&ctrl_ldev->sl_info_kobj);
+		goto out;
+	}
+
+	ctrl_ldev->is_sysfs_ok = true;
+	rtn = 0;
+
+out:
+	sl_ctrl_ldev_put(ctrl_ldev);
+
+	return rtn;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_ldev_delete(struct sl_ctrl_ldev *ctrl_ldev)
+{
+#ifdef CONFIG_SYSFS
+	sl_log_dbg(ctrl_ldev, LOG_BLOCK, LOG_NAME, "ldev delete (ldev = 0x%p)", ctrl_ldev);
+
+	if (!ctrl_ldev->parent_kobj)
+		return;
+	if (!ctrl_ldev->is_sysfs_ok)
+		return;
+
+	sl_sysfs_cable_db_delete(ctrl_ldev, ARRAY_SIZE(cable_db));
+	sl_sysfs_cable_vendors_delete(ctrl_ldev, SL_CABLE_TYPES_NUM, SL_CABLE_VENDORS_NUM);
+	sl_sysfs_cable_types_delete(ctrl_ldev, SL_CABLE_TYPES_NUM);
+
+	kobject_put(&ctrl_ldev->supported_cables_kobj);
+	kobject_put(&ctrl_ldev->sl_info_kobj);
+#endif /* CONFIG_SYSFS */
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_lgrp.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_lgrp.c
new file mode 100644
index 000000000000..f0533c8fd888
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_lgrp.c
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2023,2024,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kobject.h>
+
+#include "sl_log.h"
+#include "sl_sysfs.h"
+#include "sl_ctrl_lgrp.h"
+#include "sl_core_link.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+int sl_sysfs_lgrp_create(struct sl_ctrl_lgrp *ctrl_lgrp)
+{
+	int rtn;
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "lgrp create (lgrp = 0x%p)", ctrl_lgrp);
+
+	if (!ctrl_lgrp->parent_kobj) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "lgrp create missing parent");
+		return -EBADRQC;
+	}
+
+	rtn = sl_sysfs_lgrp_config_create(ctrl_lgrp);
+	if (rtn) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "config create failed [%d]", rtn);
+		return -ENOMEM;
+	}
+
+	rtn = sl_sysfs_lgrp_policy_create(ctrl_lgrp);
+	if (rtn) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "policy create failed [%d]", rtn);
+		goto out_config;
+	}
+
+	rtn = sl_sysfs_serdes_create(ctrl_lgrp);
+	if (rtn) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "serdes create failed [%d]", rtn);
+		goto out_policy;
+	}
+
+	rtn = sl_sysfs_media_create(ctrl_lgrp);
+	if (rtn) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "media create failed [%d]", rtn);
+		goto out_serdes;
+	}
+
+	rtn = sl_sysfs_pmi_create(ctrl_lgrp);
+	if (rtn) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "pmi create failed [%d]", rtn);
+		goto out_media;
+	}
+
+	rtn = sl_sysfs_sbus_create(ctrl_lgrp);
+	if (rtn) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "sbus create failed [%d]", rtn);
+		goto out_pmi;
+	}
+
+	rtn = sl_sysfs_sbus_pmi_create(ctrl_lgrp);
+	if (rtn) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "sbus_pmi create failed [%d]", rtn);
+		goto out_sbus;
+	}
+
+	return 0;
+
+out_sbus:
+	sl_sysfs_sbus_delete(ctrl_lgrp);
+out_pmi:
+	sl_sysfs_pmi_delete(ctrl_lgrp);
+out_media:
+	sl_sysfs_media_delete(ctrl_lgrp);
+out_serdes:
+	sl_sysfs_serdes_delete(ctrl_lgrp);
+out_policy:
+	sl_sysfs_lgrp_policy_delete(ctrl_lgrp);
+out_config:
+	sl_sysfs_lgrp_config_delete(ctrl_lgrp);
+	return -ENOMEM;
+}
+
+void sl_sysfs_lgrp_delete(struct sl_ctrl_lgrp *ctrl_lgrp)
+{
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "lgrp delete (lgrp = 0x%p)", ctrl_lgrp);
+
+	if (!ctrl_lgrp->parent_kobj)
+		return;
+
+	sl_sysfs_sbus_pmi_delete(ctrl_lgrp);
+	sl_sysfs_sbus_delete(ctrl_lgrp);
+	sl_sysfs_pmi_delete(ctrl_lgrp);
+	sl_sysfs_media_delete(ctrl_lgrp);
+	sl_sysfs_serdes_delete(ctrl_lgrp);
+	sl_sysfs_lgrp_policy_delete(ctrl_lgrp);
+	sl_sysfs_lgrp_config_delete(ctrl_lgrp);
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_lgrp_config.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_lgrp_config.c
new file mode 100644
index 000000000000..b2181e5114ee
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_lgrp_config.c
@@ -0,0 +1,438 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2024-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kobject.h>
+#include <linux/sysfs.h>
+#include <linux/hpe/sl/sl_lgrp.h>
+
+#include "sl_log.h"
+#include "sl_sysfs.h"
+#include "data/sl_ctrl_data_lgrp.h"
+#include "data/sl_ctrl_data_lgrp_trace.h"
+
+#define is_flag_set(_flags, _flag) ({              \
+		typeof(_flags) __flags = (_flags); \
+		typeof(_flag)  __flag  = (_flag);  \
+						   \
+		((__flags & __flag) == __flag);    \
+})
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+#ifdef CONFIG_SYSFS
+static ssize_t mfs_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	u32                  mfs;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, config_kobj);
+
+	rtn = sl_ctrl_data_lgrp_mfs_get(ctrl_lgrp, &mfs);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "mfs show (mfs = %u)", mfs);
+
+	return sysfs_emit(buf, "%u\n", mfs);
+}
+
+static ssize_t furcation_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	u32                  furcation;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, config_kobj);
+
+	rtn = sl_ctrl_data_lgrp_furcation_get(ctrl_lgrp, &furcation);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "furcation show (furcation = %u %s)",
+		   furcation, sl_lgrp_furcation_str(furcation));
+
+	return sysfs_emit(buf, "%s\n", sl_lgrp_furcation_str(furcation));
+}
+
+static ssize_t fec_mode_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	u32                  fec_mode;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, config_kobj);
+
+	rtn = sl_ctrl_data_lgrp_fec_mode_get(ctrl_lgrp, &fec_mode);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "fec mode show (mode = %u %s)",
+		   fec_mode, sl_lgrp_fec_mode_str(fec_mode));
+
+	return sysfs_emit(buf, "%s\n", sl_lgrp_fec_mode_str(fec_mode));
+}
+
+static ssize_t tech_map_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	int                  idx;
+	char                 output[50];
+	u32                  tech_map;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, config_kobj);
+
+	rtn = sl_ctrl_data_lgrp_tech_map_get(ctrl_lgrp, &tech_map);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "tech map show (map = 0x%X)", tech_map);
+
+	if (tech_map == 0)
+		return sysfs_emit(buf, "none\n");
+
+	idx = 0;
+	if (is_flag_set(tech_map, SL_LGRP_CONFIG_TECH_CK_400G))
+		idx += snprintf(output + idx, sizeof(output) - idx, "%s ",
+			sl_lgrp_config_tech_str(SL_LGRP_CONFIG_TECH_CK_400G));
+	if (is_flag_set(tech_map, SL_LGRP_CONFIG_TECH_CK_200G))
+		idx += snprintf(output + idx, sizeof(output) - idx, "%s ",
+			sl_lgrp_config_tech_str(SL_LGRP_CONFIG_TECH_CK_200G));
+	if (is_flag_set(tech_map, SL_LGRP_CONFIG_TECH_CK_100G))
+		idx += snprintf(output + idx, sizeof(output) - idx, "%s ",
+			sl_lgrp_config_tech_str(SL_LGRP_CONFIG_TECH_CK_100G));
+	if (is_flag_set(tech_map, SL_LGRP_CONFIG_TECH_BS_200G))
+		idx += snprintf(output + idx, sizeof(output) - idx, "%s ",
+			sl_lgrp_config_tech_str(SL_LGRP_CONFIG_TECH_BS_200G));
+	if (is_flag_set(tech_map, SL_LGRP_CONFIG_TECH_CD_100G))
+		idx += snprintf(output + idx, sizeof(output) - idx, "%s ",
+			sl_lgrp_config_tech_str(SL_LGRP_CONFIG_TECH_CD_100G));
+	if (is_flag_set(tech_map, SL_LGRP_CONFIG_TECH_CD_50G))
+		idx += snprintf(output + idx, sizeof(output) - idx, "%s ",
+			sl_lgrp_config_tech_str(SL_LGRP_CONFIG_TECH_CD_50G));
+	if (is_flag_set(tech_map, SL_LGRP_CONFIG_TECH_BJ_100G))
+		idx += snprintf(output + idx, sizeof(output) - idx, "%s ",
+			sl_lgrp_config_tech_str(SL_LGRP_CONFIG_TECH_BJ_100G));
+	if (!idx)
+		return sysfs_emit(buf, "none\n");
+	output[idx - 1] = '\0';
+
+	return sysfs_emit(buf, "%s\n", output);
+}
+
+static ssize_t fec_map_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	int                  idx;
+	char                 output[20];
+	u32                  fec_map;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, config_kobj);
+
+	rtn = sl_ctrl_data_lgrp_fec_map_get(ctrl_lgrp, &fec_map);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "fec map show (map = 0x%X)", fec_map);
+
+	if (fec_map == 0)
+		return sysfs_emit(buf, "none\n");
+
+	idx = 0;
+	if (is_flag_set(fec_map, SL_LGRP_CONFIG_FEC_RS_LL))
+		idx += snprintf(output + idx, sizeof(output) - idx, "%s ",
+			sl_lgrp_config_fec_str(SL_LGRP_CONFIG_FEC_RS_LL));
+	if (is_flag_set(fec_map, SL_LGRP_CONFIG_FEC_RS))
+		idx += snprintf(output + idx, sizeof(output) - idx, "%s ",
+			sl_lgrp_config_fec_str(SL_LGRP_CONFIG_FEC_RS));
+	if (!idx)
+		return sysfs_emit(buf, "none\n");
+	output[idx - 1] = '\0';
+
+	return sysfs_emit(buf, "%s\n", output);
+}
+
+static ssize_t link_type_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	u32                  options;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, config_kobj);
+
+	rtn = sl_ctrl_data_lgrp_options_get(ctrl_lgrp, &options);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	if (options & SL_LGRP_CONFIG_OPT_FABRIC)
+		return sysfs_emit(buf, "fabric\n");
+
+	return sysfs_emit(buf, "edge\n");
+}
+
+static ssize_t loopback_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	u32                  options;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, config_kobj);
+
+	rtn = sl_ctrl_data_lgrp_options_get(ctrl_lgrp, &options);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "loopback show (options = 0x%X)", options);
+
+	if (options & SL_LGRP_CONFIG_OPT_SERDES_LOOPBACK_ENABLE)
+		return sysfs_emit(buf, "enabled-serdes\n");
+
+	return sysfs_emit(buf, "disabled\n");
+}
+
+static struct kobj_attribute lgrp_mfs       = __ATTR_RO(mfs);
+static struct kobj_attribute lgrp_furcation = __ATTR_RO(furcation);
+static struct kobj_attribute lgrp_fec_mode  = __ATTR_RO(fec_mode);
+static struct kobj_attribute lgrp_tech_map  = __ATTR_RO(tech_map);
+static struct kobj_attribute lgrp_fec_map   = __ATTR_RO(fec_map);
+static struct kobj_attribute lgrp_link_type = __ATTR_RO(link_type);
+static struct kobj_attribute lgrp_loopback  = __ATTR_RO(loopback);
+
+static ssize_t err_trace_enable_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	bool                 is_err_trace_enabled;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, config_kobj);
+
+	rtn = sl_ctrl_data_lgrp_is_err_trace_enabled(ctrl_lgrp, &is_err_trace_enabled);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "err trace enable show (is_err_trace_enabled = %u)", is_err_trace_enabled);
+
+	return sysfs_emit(buf, "%u\n", is_err_trace_enabled);
+}
+
+static ssize_t err_trace_enable_store(struct kobject *kobj, struct kobj_attribute *kattr, const char *buf, size_t count)
+{
+	int                  rtn;
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	u8                   val;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, config_kobj);
+
+	rtn = kstrtou8(buf, 0, &val);
+	if (rtn) {
+		sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+			   "err trace enable store failed [%d]", rtn);
+		return rtn;
+	}
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "err trace enable store (val = %u)", val);
+
+	rtn = sl_ctrl_data_lgrp_err_trace_enable_set(ctrl_lgrp, val);
+	if (rtn) {
+		sl_log_err_trace(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+				 "err trace enable store failed [%d]", rtn);
+		return rtn;
+	}
+
+	return count;
+}
+
+static struct kobj_attribute lgrp_err_trace_enable = __ATTR_RW(err_trace_enable);
+
+static ssize_t warn_trace_enable_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	bool                 is_warn_trace_enabled;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, config_kobj);
+
+	rtn = sl_ctrl_data_lgrp_is_warn_trace_enabled(ctrl_lgrp, &is_warn_trace_enabled);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "warn trace enable show (is_warn_trace_enabled = %u)",
+		   is_warn_trace_enabled);
+
+	return sysfs_emit(buf, "%u\n", is_warn_trace_enabled);
+}
+
+static ssize_t warn_trace_enable_store(struct kobject *kobj, struct kobj_attribute *kattr,
+				       const char *buf, size_t count)
+{
+	int                  rtn;
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	u8                   val;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, config_kobj);
+
+	rtn = kstrtou8(buf, 0, &val);
+	if (rtn) {
+		sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+			   "warn trace enable store failed [%d]", rtn);
+		return rtn;
+	}
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "warn trace enable store (val = %u)", val);
+
+	rtn = sl_ctrl_data_lgrp_warn_trace_set(ctrl_lgrp, val);
+	if (rtn) {
+		sl_log_err_trace(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+				 "warn trace enable store failed [%d]", rtn);
+		return rtn;
+	}
+
+	return count;
+}
+
+static struct kobj_attribute lgrp_warn_trace_enable = __ATTR_RW(warn_trace_enable);
+
+static ssize_t serdes_lane_io_trace_enable_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	bool                 serdes_lane_io_trace;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, config_kobj);
+
+	serdes_lane_io_trace = sl_ctrl_data_lgrp_is_serdes_lane_io_trace_enabled(ctrl_lgrp);
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "core init io trace enable show (serdes_lane_io_trace = %s)",
+		   serdes_lane_io_trace ? "enabled" : "disabled");
+
+	return sysfs_emit(buf, "%u\n", serdes_lane_io_trace ? 1 : 0);
+}
+
+static ssize_t serdes_lane_io_trace_enable_store(struct kobject *kobj, struct kobj_attribute *kattr,
+						 const char *buf, size_t count)
+{
+	int                  rtn;
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	u8                   val;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, config_kobj);
+
+	rtn = kstrtou8(buf, 0, &val);
+	if (rtn) {
+		sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+			   "core init io trace enable store failed [%d]", rtn);
+		return rtn;
+	}
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "core init io trace enable store (val = %u)", val);
+
+	rtn = sl_ctrl_data_lgrp_serdes_lane_io_trace_set(ctrl_lgrp, (val == 1) ? true : false);
+	if (rtn) {
+		sl_log_err_trace(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+				 "core init io trace enable store failed [%d]", rtn);
+		return rtn;
+	}
+
+	return count;
+}
+
+static struct kobj_attribute lgrp_serdes_lane_io_trace_enable = __ATTR_RW(serdes_lane_io_trace_enable);
+
+static ssize_t fabric_link_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	u32                  options;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, config_kobj);
+
+	rtn = sl_ctrl_data_lgrp_options_get(ctrl_lgrp, &options);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "fabric link show (fabric link = %s)",
+		   (options & SL_LGRP_CONFIG_OPT_FABRIC) ? "enabled" : "disabled");
+
+	return sysfs_emit(buf, "%s\n",
+			 (options & SL_LGRP_CONFIG_OPT_FABRIC) ? "enabled" : "disabled");
+}
+
+static struct kobj_attribute lgrp_fabric_link = __ATTR_RO(fabric_link);
+
+static ssize_t r1_partner_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	u32                  options;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, config_kobj);
+
+	rtn = sl_ctrl_data_lgrp_options_get(ctrl_lgrp, &options);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "r1 partner show (r1 partner = %s)",
+		   (options & SL_LGRP_CONFIG_OPT_R1) ? "enabled" : "disabled");
+
+	return sysfs_emit(buf, "%s\n", (options & SL_LGRP_CONFIG_OPT_R1) ? "enabled" : "disabled");
+}
+
+static struct kobj_attribute lgrp_r1_partner  = __ATTR_RO(r1_partner);
+
+static struct attribute *lgrp_config_attrs[] = {
+	&lgrp_mfs.attr,
+	&lgrp_furcation.attr,
+	&lgrp_fec_mode.attr,
+	&lgrp_tech_map.attr,
+	&lgrp_fec_map.attr,
+	&lgrp_link_type.attr,
+	&lgrp_loopback.attr,
+	&lgrp_err_trace_enable.attr,
+	&lgrp_warn_trace_enable.attr,
+	&lgrp_serdes_lane_io_trace_enable.attr,
+	&lgrp_fabric_link.attr,
+	&lgrp_r1_partner.attr,
+	NULL
+};
+ATTRIBUTE_GROUPS(lgrp_config);
+
+static struct kobj_type config_info = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = lgrp_config_groups,
+};
+#endif /* CONFIG_SYSFS */
+
+int sl_sysfs_lgrp_config_create(struct sl_ctrl_lgrp *ctrl_lgrp)
+{
+#ifdef CONFIG_SYSFS
+	int rtn;
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "lgrp config create (lgrp = 0x%p)", ctrl_lgrp);
+
+	rtn = kobject_init_and_add(&(ctrl_lgrp->config_kobj), &config_info, ctrl_lgrp->parent_kobj, "config");
+	if (rtn) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "lgrp config create failed [%d]", rtn);
+		kobject_put(&(ctrl_lgrp->config_kobj));
+		return -ENOMEM;
+	}
+
+	return 0;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_lgrp_config_delete(struct sl_ctrl_lgrp *ctrl_lgrp)
+{
+#ifdef CONFIG_SYSFS
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "lgrp config delete (lgrp = 0x%p)", ctrl_lgrp);
+
+	kobject_put(&(ctrl_lgrp->config_kobj));
+#endif /* CONFIG_SYSFS */
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_lgrp_policy.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_lgrp_policy.c
new file mode 100644
index 000000000000..ccb9bf627ee4
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_lgrp_policy.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2024-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kobject.h>
+
+#include "sl_log.h"
+#include "sl_sysfs.h"
+#include "sl_ctrl_lgrp.h"
+#include "sl_core_link.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+#ifdef CONFIG_SYSFS
+static struct attribute *lgrp_policy_attrs[] = {
+	NULL
+};
+ATTRIBUTE_GROUPS(lgrp_policy);
+
+static struct kobj_type policy_info = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = lgrp_policy_groups,
+};
+#endif /* CONFIG_SYSFS */
+
+int sl_sysfs_lgrp_policy_create(struct sl_ctrl_lgrp *ctrl_lgrp)
+{
+#ifdef CONFIG_SYSFS
+	int rtn;
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "lgrp policy create (lgrp = 0x%p)", ctrl_lgrp);
+
+	rtn = kobject_init_and_add(&(ctrl_lgrp->policy_kobj), &policy_info, ctrl_lgrp->parent_kobj, "policies");
+	if (rtn) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "lgrp policy create failed [%d]", rtn);
+		kobject_put(&(ctrl_lgrp->policy_kobj));
+		return -ENOMEM;
+	}
+
+	return 0;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_lgrp_policy_delete(struct sl_ctrl_lgrp *ctrl_lgrp)
+{
+#ifdef CONFIG_SYSFS
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "lgrp policy delete (lgrp = 0x%p)", ctrl_lgrp);
+
+	kobject_put(&(ctrl_lgrp->policy_kobj));
+#endif /* CONFIG_SYSFS */
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link.c
new file mode 100644
index 000000000000..df0f51c5f77e
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link.c
@@ -0,0 +1,830 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2023-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kobject.h>
+#include <linux/sysfs.h>
+
+#include "sl_log.h"
+#include "sl_sysfs.h"
+#include "data/sl_ctrl_data_link.h"
+#include "sl_ctrl_link.h"
+#include "sl_ctrl_lgrp.h"
+#include "sl_ctrl_ldev.h"
+#include "sl_core_link.h"
+#include "sl_core_str.h"
+#include "hw/sl_core_hw_an.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+#ifdef CONFIG_SYSFS
+static ssize_t state_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link;
+	u32                  state;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, kobj);
+
+	rtn = sl_ctrl_data_link_state_get(ctrl_link, &state);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "state show (link = 0x%p, state = %u %s)", ctrl_link, state, sl_link_state_str(state));
+
+	return sysfs_emit(buf, "%s\n", sl_link_state_str(state));
+}
+
+static ssize_t speed_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  state;
+	u32                  speed;
+	int		     rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, kobj);
+
+	rtn = sl_ctrl_link_state_get_cmd(ctrl_link->ctrl_lgrp->ctrl_ldev->num,
+					 ctrl_link->ctrl_lgrp->num, ctrl_link->num, &state);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	rtn = sl_core_link_speed_get(ctrl_link->ctrl_lgrp->ctrl_ldev->num,
+				     ctrl_link->ctrl_lgrp->num, ctrl_link->num, &speed);
+	if (rtn == -ENOLINK)
+		return sysfs_emit(buf, "no-link\n");
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "speed show (state = %u %s, speed = 0x%X %s)",
+		   state, sl_link_state_str(state), speed, sl_lgrp_config_tech_str(speed));
+
+	if ((state != SL_LINK_STATE_UP) && (state != SL_LINK_STATE_UP_DOWN_REQ))
+		return sysfs_emit(buf, "no-link\n");
+
+	return sysfs_emit(buf, "%s\n", sl_lgrp_config_tech_str(speed));
+}
+
+static ssize_t ccw_warn_limit_crossed_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	bool                 is_limit_crossed;
+	time64_t             limit_crossed_time;
+	int		     rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, kobj);
+
+	rtn = sl_core_link_ccw_warn_limit_crossed_get(ctrl_link->ctrl_lgrp->ctrl_ldev->num, ctrl_link->ctrl_lgrp->num,
+						      ctrl_link->num, &is_limit_crossed, &limit_crossed_time);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "ccw warn limit crossed show (is_limit_crossed = %d %s)", is_limit_crossed,
+		is_limit_crossed ? "yes" : "no");
+
+	return sysfs_emit(buf, "%s\n", is_limit_crossed ? "yes" : "no");
+}
+
+static ssize_t ccw_warn_limit_last_crossed_time_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	bool                 is_limit_crossed;
+	time64_t             limit_crossed_time;
+	int		     rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, kobj);
+
+	rtn = sl_core_link_ccw_warn_limit_crossed_get(ctrl_link->ctrl_lgrp->ctrl_ldev->num, ctrl_link->ctrl_lgrp->num,
+						      ctrl_link->num, &is_limit_crossed, &limit_crossed_time);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "ccw warn limit last crossed time show (is_limit_crossed = 0x%X, time = %lld %ptTt %ptTd)",
+		is_limit_crossed, limit_crossed_time, &limit_crossed_time, &limit_crossed_time);
+
+	if (!is_limit_crossed)
+		return sysfs_emit(buf, "not-crossed\n");
+
+	return sysfs_emit(buf, "%ptTt %ptTd\n", &limit_crossed_time, &limit_crossed_time);
+}
+
+static ssize_t ucw_warn_limit_crossed_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	bool                 is_limit_crossed;
+	time64_t             limit_crossed_time;
+	int		     rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, kobj);
+
+	rtn = sl_core_link_ucw_warn_limit_crossed_get(ctrl_link->ctrl_lgrp->ctrl_ldev->num, ctrl_link->ctrl_lgrp->num,
+						      ctrl_link->num, &is_limit_crossed, &limit_crossed_time);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "ucw warn limit crossed show (is_limit_crossed = %d %s)", is_limit_crossed,
+		is_limit_crossed ? "yes" : "no");
+
+	return sysfs_emit(buf, "%s\n", is_limit_crossed ? "yes" : "no");
+}
+
+static ssize_t ucw_warn_limit_last_crossed_time_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	bool                 is_limit_crossed;
+	time64_t             limit_crossed_time;
+	int		     rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, kobj);
+
+	rtn = sl_core_link_ucw_warn_limit_crossed_get(ctrl_link->ctrl_lgrp->ctrl_ldev->num, ctrl_link->ctrl_lgrp->num,
+						      ctrl_link->num, &is_limit_crossed, &limit_crossed_time);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "ucw warn limit last crossed time show (is_limit_crossed = 0x%X, time = %lld %ptTt %ptTd)",
+		is_limit_crossed, limit_crossed_time, &limit_crossed_time, &limit_crossed_time);
+
+	if (!is_limit_crossed)
+		return sysfs_emit(buf, "not-crossed\n");
+
+	return sysfs_emit(buf, "%ptTt %ptTd\n", &limit_crossed_time, &limit_crossed_time);
+}
+
+static ssize_t up_count_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  up_count;
+	int		     rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, kobj);
+
+	rtn = sl_ctrl_link_up_count_get(ctrl_link->ctrl_lgrp->ctrl_ldev->num, ctrl_link->ctrl_lgrp->num,
+					ctrl_link->num, &up_count);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "up count show (up_count = %u)", up_count);
+
+	return sysfs_emit(buf, "%u\n", up_count);
+}
+
+static ssize_t time_to_link_up_ms_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	u32                  state;
+	struct sl_ctrl_link *ctrl_link;
+	s64                  attempt_time_ms;
+	s64                  total_time_ms;
+	s64                  up_time_ms;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, kobj);
+
+	rtn = sl_ctrl_data_link_state_get(ctrl_link, &state);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	if ((state != SL_LINK_STATE_UP) && (state != SL_LINK_STATE_UP_DOWN_REQ))
+		return sysfs_emit(buf, "no-link\n");
+
+	rtn = sl_ctrl_link_up_clocks_get(ctrl_link->ctrl_lgrp->ctrl_ldev->num, ctrl_link->ctrl_lgrp->num,
+					 ctrl_link->num, &attempt_time_ms, &total_time_ms, &up_time_ms);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "time to link up show (attempt_time = %lldms, total_time = %lldms)",
+		   attempt_time_ms, total_time_ms);
+
+	return sysfs_emit(buf, "%lld\n", attempt_time_ms);
+}
+
+static ssize_t total_time_to_link_up_ms_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	u32                  state;
+	struct sl_ctrl_link *ctrl_link;
+	s64                  attempt_time_ms;
+	s64                  total_time_ms;
+	s64                  up_time_ms;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, kobj);
+
+	rtn = sl_ctrl_data_link_state_get(ctrl_link, &state);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	if ((state != SL_LINK_STATE_UP) && (state != SL_LINK_STATE_UP_DOWN_REQ))
+		return sysfs_emit(buf, "no-link\n");
+
+	rtn = sl_ctrl_link_up_clocks_get(ctrl_link->ctrl_lgrp->ctrl_ldev->num, ctrl_link->ctrl_lgrp->num,
+					 ctrl_link->num, &attempt_time_ms, &total_time_ms, &up_time_ms);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "total time to link up show (attempt_time = %lldms, total_time = %lldms)",
+		   attempt_time_ms, total_time_ms);
+
+	return sysfs_emit(buf, "%lld\n", total_time_ms);
+}
+
+static ssize_t up_time_ms_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	u32                  state;
+	struct sl_ctrl_link *ctrl_link;
+	s64                  attempt_time_ms;
+	s64                  total_time_ms;
+	s64                  up_time_ms;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, kobj);
+
+	rtn = sl_ctrl_data_link_state_get(ctrl_link, &state);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	if ((state != SL_LINK_STATE_UP) && (state != SL_LINK_STATE_UP_DOWN_REQ))
+		return sysfs_emit(buf, "no-link\n");
+
+	rtn = sl_ctrl_link_up_clocks_get(ctrl_link->ctrl_lgrp->ctrl_ldev->num, ctrl_link->ctrl_lgrp->num,
+					 ctrl_link->num, &attempt_time_ms, &total_time_ms, &up_time_ms);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "up time show (up_time = %lldms)", up_time_ms);
+
+	return sysfs_emit(buf, "%lld\n", up_time_ms);
+}
+
+static ssize_t lp_caps_state_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	u32                  lp_caps_state;
+	struct sl_ctrl_link *ctrl_link;
+	int		     rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, kobj);
+
+	rtn = sl_ctrl_link_an_lp_caps_state_get(ctrl_link->ctrl_lgrp->ctrl_ldev->num, ctrl_link->ctrl_lgrp->num,
+						ctrl_link->num, &lp_caps_state);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "an lp caps state show (lp_caps_state = %u %s)",
+		   lp_caps_state, sl_link_an_lp_caps_state_str(lp_caps_state));
+
+	return sysfs_emit(buf, "%s\n", sl_link_an_lp_caps_state_str(lp_caps_state));
+}
+
+static ssize_t last_autoneg_fail_cause_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  fail_cause;
+	time64_t             fail_time;
+	int		     rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, kobj);
+
+	rtn = sl_ctrl_link_an_fail_cause_get(ctrl_link->ctrl_lgrp->ctrl_ldev->num, ctrl_link->ctrl_lgrp->num,
+					     ctrl_link->num, &fail_cause, &fail_time);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "last autoneg fail casue show (cause = %u %s)",
+		   fail_cause, sl_core_link_an_fail_cause_str(fail_cause));
+
+	if (fail_cause == SL_CORE_HW_AN_FAIL_CAUSE_NONE)
+		return sysfs_emit(buf, "no-fail\n");
+
+	return sysfs_emit(buf, "%s\n", sl_core_link_an_fail_cause_str(fail_cause));
+}
+
+static ssize_t last_autoneg_fail_time_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  fail_cause;
+	time64_t             fail_time;
+	int		     rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, kobj);
+
+	rtn = sl_ctrl_link_an_fail_cause_get(ctrl_link->ctrl_lgrp->ctrl_ldev->num, ctrl_link->ctrl_lgrp->num,
+					     ctrl_link->num, &fail_cause, &fail_time);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "last autoneg fail time show (cause = %u %s, time = %lld %ptTt %ptTd)",
+		   fail_cause, sl_core_link_an_fail_cause_str(fail_cause), fail_time, &fail_time, &fail_time);
+
+	if (fail_cause == SL_CORE_HW_AN_FAIL_CAUSE_NONE)
+		return sysfs_emit(buf, "no-fail\n");
+
+	return sysfs_emit(buf, "%ptTt %ptTd\n", &fail_time, &fail_time);
+}
+
+static ssize_t info_map_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link;
+	u64                  info_map;
+	char                 info_map_str[900];
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, kobj);
+
+	rtn = sl_ctrl_link_info_map_get(ctrl_link->ctrl_lgrp->ctrl_ldev->num,
+					ctrl_link->ctrl_lgrp->num, ctrl_link->num, &info_map);
+	if (rtn) {
+		sl_log_err(ctrl_link, LOG_BLOCK, LOG_NAME,
+			   "info map show sl_ctrl_link_info_map_get failed [%d]", rtn);
+		return sysfs_emit(buf, "no-link\n");
+	}
+
+	sl_core_info_map_str(info_map, info_map_str, sizeof(info_map_str));
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "info map show (info_map = 0x%llX %s)", info_map, info_map_str);
+
+	return sysfs_emit(buf, "%s\n", info_map_str);
+}
+
+static struct kobj_attribute link_state                            = __ATTR_RO(state);
+static struct kobj_attribute link_speed                            = __ATTR_RO(speed);
+static struct kobj_attribute link_ccw_warn_limit_crossed           = __ATTR_RO(ccw_warn_limit_crossed);
+static struct kobj_attribute link_ccw_warn_limit_last_crossed_time = __ATTR_RO(ccw_warn_limit_last_crossed_time);
+static struct kobj_attribute link_ucw_warn_limit_crossed           = __ATTR_RO(ucw_warn_limit_crossed);
+static struct kobj_attribute link_ucw_warn_limit_last_crossed_time = __ATTR_RO(ucw_warn_limit_last_crossed_time);
+static struct kobj_attribute link_up_count                         = __ATTR_RO(up_count);
+static struct kobj_attribute link_up_time_ms                       = __ATTR_RO(up_time_ms);
+static struct kobj_attribute link_time_to_link_up_ms               = __ATTR_RO(time_to_link_up_ms);
+static struct kobj_attribute link_total_time_to_link_up_ms         = __ATTR_RO(total_time_to_link_up_ms);
+static struct kobj_attribute link_lp_caps_state                    = __ATTR_RO(lp_caps_state);
+static struct kobj_attribute link_last_autoneg_fail_cause          = __ATTR_RO(last_autoneg_fail_cause);
+static struct kobj_attribute link_last_autoneg_fail_time           = __ATTR_RO(last_autoneg_fail_time);
+static struct kobj_attribute link_info_map                         = __ATTR_RO(info_map);
+
+static struct attribute *link_attrs[] = {
+	&link_state.attr,
+	&link_speed.attr,
+	&link_ccw_warn_limit_crossed.attr,
+	&link_ccw_warn_limit_last_crossed_time.attr,
+	&link_ucw_warn_limit_crossed.attr,
+	&link_ucw_warn_limit_last_crossed_time.attr,
+	&link_up_count.attr,
+	&link_up_time_ms.attr,
+	&link_time_to_link_up_ms.attr,
+	&link_total_time_to_link_up_ms.attr,
+	&link_lp_caps_state.attr,
+	&link_last_autoneg_fail_cause.attr,
+	&link_last_autoneg_fail_time.attr,
+	&link_info_map.attr,
+	NULL
+};
+ATTRIBUTE_GROUPS(link);
+
+static struct kobj_type link_info = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = link_groups,
+};
+
+static ssize_t last_down_cause_map_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf, u8 num)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u64                  down_cause_map;
+	time64_t             down_time;
+	char                 cause_str[SL_LINK_DOWN_CAUSE_STR_SIZE];
+	int		     rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, last_down_kobj);
+
+	rtn = sl_core_link_last_down_cause_map_info_get(ctrl_link->ctrl_lgrp->ctrl_ldev->num, ctrl_link->ctrl_lgrp->num,
+							ctrl_link->num, num, &down_cause_map, &down_time);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_link_down_cause_map_with_info_str(down_cause_map, cause_str, sizeof(cause_str));
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "last down cause show (num = %u, cause_map = 0x%llX %s)",
+		   num, down_cause_map, cause_str);
+
+	return sysfs_emit(buf, "%s\n", cause_str);
+}
+
+#define link_last_down_cause_map(_num)                                                                               \
+	static inline ssize_t cause_map_##_num##_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf) \
+	{                                                                                                            \
+		return last_down_cause_map_show(kobj, kattr, buf, (_num));                                           \
+	}                                                                                                            \
+	static struct kobj_attribute link_last_down_cause_map_##_num = __ATTR_RO(cause_map_##_num)
+
+link_last_down_cause_map(0);
+link_last_down_cause_map(1);
+link_last_down_cause_map(2);
+link_last_down_cause_map(3);
+link_last_down_cause_map(4);
+link_last_down_cause_map(5);
+link_last_down_cause_map(6);
+link_last_down_cause_map(7);
+link_last_down_cause_map(8);
+link_last_down_cause_map(9);
+
+static ssize_t last_down_time_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf, u8 num)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u64                  down_cause_map;
+	time64_t             down_time;
+	int		     rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, last_down_kobj);
+
+	rtn = sl_core_link_last_down_cause_map_info_get(ctrl_link->ctrl_lgrp->ctrl_ldev->num, ctrl_link->ctrl_lgrp->num,
+							ctrl_link->num, num, &down_cause_map, &down_time);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "last down time show (num = %u, cause_map = 0x%llX, time = %lld %ptTt %ptTd)",
+		   num, down_cause_map, down_time, &down_time, &down_time);
+
+	if (down_cause_map == SL_LINK_DOWN_CAUSE_NONE)
+		return sysfs_emit(buf, "none\n");
+
+	return sysfs_emit(buf, "%ptTt %ptTd\n", &down_time, &down_time);
+}
+
+#define link_last_down_time(_num)                                                                               \
+	static inline ssize_t time_##_num##_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf) \
+	{                                                                                                       \
+		return last_down_time_show(kobj, kattr, buf, (_num));                                           \
+	}                                                                                                       \
+	static struct kobj_attribute link_last_down_time_##_num = __ATTR_RO(time_##_num)
+
+link_last_down_time(0);
+link_last_down_time(1);
+link_last_down_time(2);
+link_last_down_time(3);
+link_last_down_time(4);
+link_last_down_time(5);
+link_last_down_time(6);
+link_last_down_time(7);
+link_last_down_time(8);
+link_last_down_time(9);
+
+static struct attribute *last_down_attrs[] = {
+	&link_last_down_cause_map_0.attr,
+	&link_last_down_time_0.attr,
+	&link_last_down_cause_map_1.attr,
+	&link_last_down_time_1.attr,
+	&link_last_down_cause_map_2.attr,
+	&link_last_down_time_2.attr,
+	&link_last_down_cause_map_3.attr,
+	&link_last_down_time_3.attr,
+	&link_last_down_cause_map_4.attr,
+	&link_last_down_time_4.attr,
+	&link_last_down_cause_map_5.attr,
+	&link_last_down_time_5.attr,
+	&link_last_down_cause_map_6.attr,
+	&link_last_down_time_6.attr,
+	&link_last_down_cause_map_7.attr,
+	&link_last_down_time_7.attr,
+	&link_last_down_cause_map_8.attr,
+	&link_last_down_time_8.attr,
+	&link_last_down_cause_map_9.attr,
+	&link_last_down_time_9.attr,
+	NULL,
+};
+ATTRIBUTE_GROUPS(last_down);
+
+static struct kobj_type last_down = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = last_down_groups,
+};
+
+static ssize_t last_up_fail_cause_map_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf, u8 num)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u64                  up_fail_cause_map;
+	time64_t             up_fail_time;
+	char                 cause_str[SL_LINK_UP_FAIL_CAUSE_STR_SIZE];
+	int		     rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, last_up_fail_kobj);
+	rtn = sl_core_link_last_up_fail_cause_map_info_get(ctrl_link->ctrl_lgrp->ctrl_ldev->num, ctrl_link->ctrl_lgrp->num,
+							   ctrl_link->num, num, &up_fail_cause_map, &up_fail_time);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_link_down_cause_map_with_info_str(up_fail_cause_map, cause_str, sizeof(cause_str));
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "last up_fail cause show (num = %u, cause_map = 0x%llX %s)",
+		   num, up_fail_cause_map, cause_str);
+
+	return sysfs_emit(buf, "%s\n", cause_str);
+}
+
+#define link_last_up_fail_cause_map(_num)                                                                                    \
+	static inline ssize_t up_fail_cause_map_##_num##_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf) \
+	{                                                                                                                    \
+		return last_up_fail_cause_map_show(kobj, kattr, buf, (_num));                                                \
+	}                                                                                                                    \
+	static struct kobj_attribute link_last_up_fail_cause_map_##_num = __ATTR_RO(up_fail_cause_map_##_num)
+
+link_last_up_fail_cause_map(0);
+link_last_up_fail_cause_map(1);
+link_last_up_fail_cause_map(2);
+link_last_up_fail_cause_map(3);
+link_last_up_fail_cause_map(4);
+link_last_up_fail_cause_map(5);
+link_last_up_fail_cause_map(6);
+link_last_up_fail_cause_map(7);
+link_last_up_fail_cause_map(8);
+link_last_up_fail_cause_map(9);
+
+static ssize_t last_up_fail_time_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf, u8 num)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u64                  up_fail_cause_map;
+	time64_t             up_fail_time;
+	int		     rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, last_up_fail_kobj);
+	rtn = sl_core_link_last_up_fail_cause_map_info_get(ctrl_link->ctrl_lgrp->ctrl_ldev->num, ctrl_link->ctrl_lgrp->num,
+							   ctrl_link->num, num, &up_fail_cause_map, &up_fail_time);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "last up_fail time show (num = %u, cause_map = 0x%llX, time = %lld %ptTt %ptTd)",
+		   num, up_fail_cause_map, up_fail_time, &up_fail_time, &up_fail_time);
+
+	if (up_fail_cause_map == SL_LINK_DOWN_CAUSE_NONE)
+		return sysfs_emit(buf, "none\n");
+
+	return sysfs_emit(buf, "%ptTt %ptTd\n", &up_fail_time, &up_fail_time);
+}
+
+#define link_last_up_fail_time(_num)                                                                                    \
+	static inline ssize_t up_fail_time_##_num##_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf) \
+	{                                                                                                               \
+		return last_up_fail_time_show(kobj, kattr, buf, (_num));                                                \
+	}                                                                                                               \
+	static struct kobj_attribute link_last_up_fail_time_##_num = __ATTR_RO(up_fail_time_##_num)
+
+link_last_up_fail_time(0);
+link_last_up_fail_time(1);
+link_last_up_fail_time(2);
+link_last_up_fail_time(3);
+link_last_up_fail_time(4);
+link_last_up_fail_time(5);
+link_last_up_fail_time(6);
+link_last_up_fail_time(7);
+link_last_up_fail_time(8);
+link_last_up_fail_time(9);
+
+static struct attribute *last_up_fail_attrs[] = {
+	&link_last_up_fail_cause_map_0.attr,
+	&link_last_up_fail_time_0.attr,
+	&link_last_up_fail_cause_map_1.attr,
+	&link_last_up_fail_time_1.attr,
+	&link_last_up_fail_cause_map_2.attr,
+	&link_last_up_fail_time_2.attr,
+	&link_last_up_fail_cause_map_3.attr,
+	&link_last_up_fail_time_3.attr,
+	&link_last_up_fail_cause_map_4.attr,
+	&link_last_up_fail_time_4.attr,
+	&link_last_up_fail_cause_map_5.attr,
+	&link_last_up_fail_time_5.attr,
+	&link_last_up_fail_cause_map_6.attr,
+	&link_last_up_fail_time_6.attr,
+	&link_last_up_fail_cause_map_7.attr,
+	&link_last_up_fail_time_7.attr,
+	&link_last_up_fail_cause_map_8.attr,
+	&link_last_up_fail_time_8.attr,
+	&link_last_up_fail_cause_map_9.attr,
+	&link_last_up_fail_time_9.attr,
+	NULL,
+};
+ATTRIBUTE_GROUPS(last_up_fail);
+
+static struct kobj_type last_up_fail = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = last_up_fail_groups,
+};
+
+static int sl_sysfs_link_last_up_fail_create(struct sl_ctrl_link *ctrl_link)
+{
+	int rtn;
+
+	rtn = kobject_init_and_add(&ctrl_link->last_up_fail_kobj,
+				   &last_up_fail, &ctrl_link->kobj, "last_up_fail");
+	if (rtn) {
+		sl_log_err(ctrl_link, LOG_BLOCK, LOG_NAME,
+			   "last up_fail create kobject_init_and_add failed [%d]", rtn);
+		kobject_put(&ctrl_link->last_up_fail_kobj);
+		return rtn;
+	}
+
+	return 0;
+}
+
+static void sl_sysfs_link_last_up_fail_delete(struct sl_ctrl_link *ctrl_link)
+{
+	kobject_put(&ctrl_link->last_up_fail_kobj);
+}
+
+static int sl_sysfs_link_last_down_create(struct sl_ctrl_link *ctrl_link)
+{
+	int rtn;
+
+	rtn = kobject_init_and_add(&ctrl_link->last_down_kobj,
+				   &last_down, &ctrl_link->kobj, "last_down");
+	if (rtn) {
+		sl_log_err(ctrl_link, LOG_BLOCK, LOG_NAME,
+			   "last down create kobject_init_and_add failed [%d]", rtn);
+		kobject_put(&ctrl_link->last_down_kobj);
+		return rtn;
+	}
+
+	return 0;
+}
+
+static void sl_sysfs_link_last_down_delete(struct sl_ctrl_link *ctrl_link)
+{
+	kobject_put(&ctrl_link->last_down_kobj);
+}
+#endif /* CONFIG_SYSFS */
+
+int sl_sysfs_link_create(struct sl_ctrl_link *ctrl_link)
+{
+#ifdef CONFIG_SYSFS
+	int                  rtn;
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link create (num = %u)", ctrl_link->num);
+
+	if (!ctrl_link->parent_kobj) {
+		sl_log_err(ctrl_link, LOG_BLOCK, LOG_NAME, "link create missing parent");
+		return -EBADRQC;
+	}
+
+	core_link = sl_core_link_get(ctrl_link->ctrl_lgrp->ctrl_ldev->num,
+				     ctrl_link->ctrl_lgrp->num, ctrl_link->num);
+	if (!core_link)
+		return -ENODEV;
+
+	rtn = kobject_init_and_add(&ctrl_link->kobj, &link_info, ctrl_link->parent_kobj, "link");
+	if (rtn) {
+		sl_log_err(ctrl_link, LOG_BLOCK, LOG_NAME,
+			   "link create kobject_init_and_add failed [%d]", rtn);
+		kobject_put(&ctrl_link->kobj);
+		return rtn;
+	}
+
+	rtn = sl_sysfs_link_policy_create(ctrl_link);
+	if (rtn) {
+		sl_log_err(ctrl_link, LOG_BLOCK, LOG_NAME,
+			   "sl_sysfs_link_policy_create failed [%d]", rtn);
+		kobject_put(&ctrl_link->kobj);
+		return rtn;
+	}
+
+	rtn = sl_sysfs_link_config_create(ctrl_link);
+	if (rtn) {
+		sl_log_err(ctrl_link, LOG_BLOCK, LOG_NAME,
+			   "sl_sysfs_link_config_create failed [%d]", rtn);
+		sl_sysfs_link_policy_delete(ctrl_link);
+		kobject_put(&ctrl_link->kobj);
+		return rtn;
+	}
+
+	rtn = sl_sysfs_link_degrade_create(core_link, &ctrl_link->kobj);
+	if (rtn) {
+		sl_log_err(ctrl_link, LOG_BLOCK, LOG_NAME,
+			   "sl_sysfs_link_degrade_create failed [%d]", rtn);
+		sl_sysfs_link_policy_delete(ctrl_link);
+		sl_sysfs_link_config_delete(ctrl_link);
+		kobject_put(&ctrl_link->kobj);
+		return rtn;
+	}
+
+	rtn = sl_sysfs_link_pml_rec_create(core_link, &ctrl_link->kobj);
+	if (rtn) {
+		sl_log_err(ctrl_link, LOG_BLOCK, LOG_NAME, "sl_sysfs_link_pml_rec_create failed [%d]", rtn);
+		sl_sysfs_link_policy_delete(ctrl_link);
+		sl_sysfs_link_config_delete(ctrl_link);
+		sl_sysfs_link_degrade_delete(core_link);
+		kobject_put(&ctrl_link->kobj);
+		return rtn;
+	}
+
+	rtn = sl_sysfs_link_fec_create(ctrl_link);
+	if (rtn) {
+		sl_log_err(ctrl_link, LOG_BLOCK, LOG_NAME,
+			   "sl_sysfs_link_fec_create failed [%d]", rtn);
+		sl_sysfs_link_policy_delete(ctrl_link);
+		sl_sysfs_link_config_delete(ctrl_link);
+		sl_sysfs_link_degrade_delete(core_link);
+		sl_sysfs_link_pml_rec_delete(core_link);
+		kobject_put(&ctrl_link->kobj);
+		return rtn;
+	}
+
+	rtn = sl_sysfs_link_caps_create(ctrl_link);
+	if (rtn) {
+		sl_log_err(ctrl_link, LOG_BLOCK, LOG_NAME,
+			   "sl_sysfs_link_caps_create failed [%d]", rtn);
+		sl_sysfs_link_policy_delete(ctrl_link);
+		sl_sysfs_link_config_delete(ctrl_link);
+		sl_sysfs_link_degrade_delete(core_link);
+		sl_sysfs_link_pml_rec_delete(core_link);
+		sl_sysfs_link_fec_delete(ctrl_link);
+		kobject_put(&ctrl_link->kobj);
+		return rtn;
+	}
+
+	rtn = sl_sysfs_link_counters_create(ctrl_link);
+	if (rtn) {
+		sl_log_err(ctrl_link, LOG_BLOCK, LOG_NAME,
+			   "sl_sysfs_link_counters_create failed [%d]", rtn);
+		sl_sysfs_link_policy_delete(ctrl_link);
+		sl_sysfs_link_config_delete(ctrl_link);
+		sl_sysfs_link_degrade_delete(core_link);
+		sl_sysfs_link_pml_rec_delete(core_link);
+		sl_sysfs_link_fec_delete(ctrl_link);
+		sl_sysfs_link_caps_delete(ctrl_link);
+		kobject_put(&ctrl_link->kobj);
+		return rtn;
+	}
+
+	rtn = sl_sysfs_link_last_down_create(ctrl_link);
+	if (rtn) {
+		sl_log_err(ctrl_link, LOG_BLOCK, LOG_NAME,
+			   "sl_sysfs_link_last_down_create failed [%d]", rtn);
+		sl_sysfs_link_policy_delete(ctrl_link);
+		sl_sysfs_link_config_delete(ctrl_link);
+		sl_sysfs_link_degrade_delete(core_link);
+		sl_sysfs_link_pml_rec_delete(core_link);
+		sl_sysfs_link_fec_delete(ctrl_link);
+		sl_sysfs_link_caps_delete(ctrl_link);
+		sl_sysfs_link_counters_delete(ctrl_link);
+		kobject_put(&ctrl_link->kobj);
+		return rtn;
+	}
+
+	rtn = sl_sysfs_link_last_up_fail_create(ctrl_link);
+	if (rtn) {
+		sl_log_err(ctrl_link, LOG_BLOCK, LOG_NAME,
+			   "sl_sysfs_link_last_up_fail_create failed [%d]", rtn);
+		sl_sysfs_link_policy_delete(ctrl_link);
+		sl_sysfs_link_config_delete(ctrl_link);
+		sl_sysfs_link_degrade_delete(core_link);
+		sl_sysfs_link_pml_rec_delete(core_link);
+		sl_sysfs_link_fec_delete(ctrl_link);
+		sl_sysfs_link_caps_delete(ctrl_link);
+		sl_sysfs_link_counters_delete(ctrl_link);
+		sl_sysfs_link_last_down_delete(ctrl_link);
+		kobject_put(&ctrl_link->kobj);
+		return rtn;
+	}
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "link create (link_kobj = 0x%p)", &ctrl_link->kobj);
+
+	return 0;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_link_delete(struct sl_ctrl_link *ctrl_link)
+{
+#ifdef CONFIG_SYSFS
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link delete (num = %u)", ctrl_link->num);
+
+	if (!ctrl_link->parent_kobj)
+		return;
+
+	core_link = sl_core_link_get(ctrl_link->ctrl_lgrp->ctrl_ldev->num,
+				     ctrl_link->ctrl_lgrp->num, ctrl_link->num);
+	if (!core_link)
+		return;
+
+	sl_sysfs_link_policy_delete(ctrl_link);
+	sl_sysfs_link_config_delete(ctrl_link);
+	sl_sysfs_link_degrade_delete(core_link);
+	sl_sysfs_link_pml_rec_delete(core_link);
+	sl_sysfs_link_fec_delete(ctrl_link);
+	sl_sysfs_link_caps_delete(ctrl_link);
+	sl_sysfs_link_counters_delete(ctrl_link);
+	sl_sysfs_link_last_down_delete(ctrl_link);
+	sl_sysfs_link_last_up_fail_delete(ctrl_link);
+	kobject_put(&ctrl_link->kobj);
+#endif /* CONFIG_SYSFS */
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_caps.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_caps.c
new file mode 100644
index 000000000000..f52b34b31bd3
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_caps.c
@@ -0,0 +1,303 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2024-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kobject.h>
+#include <linux/sysfs.h>
+
+#include "sl_log.h"
+#include "sl_sysfs.h"
+#include "sl_ctrl_link.h"
+#include "sl_core_link.h"
+#include "sl_ctrl_lgrp.h"
+#include "sl_ctrl_ldev.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+#ifdef CONFIG_SYSFS
+static ssize_t tech_map_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+	struct sl_core_lgrp *core_lgrp;
+	int                  idx;
+	char                 output[80];
+	u32                  tech_map;
+	u32                  link_state;
+	int		     rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, caps_kobj);
+
+	core_link = sl_core_link_get(ctrl_link->ctrl_lgrp->ctrl_ldev->num,
+				     ctrl_link->ctrl_lgrp->num, ctrl_link->num);
+	if (!core_link)
+		return sysfs_emit(buf, "no-link\n");
+
+	core_lgrp = core_link->core_lgrp;
+
+	tech_map = core_lgrp->link_caps[core_link->num].tech_map;
+
+	sl_log_dbg(core_link, LOG_BLOCK, LOG_NAME,
+		   "tech map show (link = 0x%p, map = 0x%X)", core_link, tech_map);
+
+	rtn = sl_core_link_state_get(ctrl_link->ctrl_lgrp->ctrl_ldev->num,
+				     ctrl_link->ctrl_lgrp->num, ctrl_link->num, &link_state);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	if ((tech_map == 0) ||
+	    ((link_state != SL_CORE_LINK_STATE_UP) &&
+		 (link_state != SL_CORE_LINK_STATE_GOING_UP) &&
+		 (link_state != SL_CORE_LINK_STATE_AN)) ||
+		!is_flag_set(core_link->config.flags, SL_LINK_CONFIG_OPT_AUTONEG_ENABLE))
+		return sysfs_emit(buf, "none\n");
+
+	idx = 0;
+	if (is_flag_set(tech_map, SL_LGRP_CONFIG_TECH_CK_400G))
+		idx += snprintf(output + idx, sizeof(output) - idx, "%s ",
+			sl_lgrp_config_tech_str(SL_LGRP_CONFIG_TECH_CK_400G));
+	if (is_flag_set(tech_map, SL_LGRP_CONFIG_TECH_CK_200G))
+		idx += snprintf(output + idx, sizeof(output) - idx, "%s ",
+			sl_lgrp_config_tech_str(SL_LGRP_CONFIG_TECH_CK_200G));
+	if (is_flag_set(tech_map, SL_LGRP_CONFIG_TECH_CK_100G))
+		idx += snprintf(output + idx, sizeof(output) - idx, "%s ",
+			sl_lgrp_config_tech_str(SL_LGRP_CONFIG_TECH_CK_100G));
+	if (is_flag_set(tech_map, SL_LGRP_CONFIG_TECH_BS_200G))
+		idx += snprintf(output + idx, sizeof(output) - idx, "%s ",
+			sl_lgrp_config_tech_str(SL_LGRP_CONFIG_TECH_BS_200G));
+	if (is_flag_set(tech_map, SL_LGRP_CONFIG_TECH_CD_100G))
+		idx += snprintf(output + idx, sizeof(output) - idx, "%s ",
+			sl_lgrp_config_tech_str(SL_LGRP_CONFIG_TECH_CD_100G));
+	if (is_flag_set(tech_map, SL_LGRP_CONFIG_TECH_CD_50G))
+		idx += snprintf(output + idx, sizeof(output) - idx, "%s ",
+			sl_lgrp_config_tech_str(SL_LGRP_CONFIG_TECH_CD_50G));
+	if (is_flag_set(tech_map, SL_LGRP_CONFIG_TECH_BJ_100G))
+		idx += snprintf(output + idx, sizeof(output) - idx, "%s ",
+			sl_lgrp_config_tech_str(SL_LGRP_CONFIG_TECH_BJ_100G));
+	if (!idx)
+		return sysfs_emit(buf, "none\n");
+	output[idx - 1] = '\0';
+
+	return sysfs_emit(buf, "%s\n", output);
+}
+
+static ssize_t pause_map_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+	struct sl_core_lgrp *core_lgrp;
+	int                  idx;
+	char                 output[20];
+	u32                  pause_map;
+	u32                  link_state;
+	int		     rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, caps_kobj);
+
+	core_link = sl_core_link_get(ctrl_link->ctrl_lgrp->ctrl_ldev->num,
+				     ctrl_link->ctrl_lgrp->num, ctrl_link->num);
+	if (!core_link)
+		return sysfs_emit(buf, "no-link\n");
+
+	core_lgrp = core_link->core_lgrp;
+
+	pause_map = core_lgrp->link_caps[core_link->num].pause_map;
+
+	sl_log_dbg(core_link, LOG_BLOCK, LOG_NAME,
+		   "pause map show (link = 0x%p, map = 0x%X)", core_link, pause_map);
+
+	rtn = sl_core_link_state_get(ctrl_link->ctrl_lgrp->ctrl_ldev->num,
+				     ctrl_link->ctrl_lgrp->num, ctrl_link->num, &link_state);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	if ((pause_map == 0) ||
+	    ((link_state != SL_CORE_LINK_STATE_UP) &&
+		 (link_state != SL_CORE_LINK_STATE_GOING_UP) &&
+		 (link_state != SL_CORE_LINK_STATE_AN)) ||
+		!is_flag_set(core_link->config.flags, SL_LINK_CONFIG_OPT_AUTONEG_ENABLE))
+		return sysfs_emit(buf, "none\n");
+
+	idx = 0;
+	if (is_flag_set(pause_map, SL_LINK_CONFIG_PAUSE_ASYM))
+		idx += snprintf(output + idx, sizeof(output) - idx, "%s ",
+			sl_link_config_pause_str(SL_LINK_CONFIG_PAUSE_ASYM));
+	if (is_flag_set(pause_map, SL_LINK_CONFIG_PAUSE_SYM))
+		idx += snprintf(output + idx, sizeof(output) - idx, "%s ",
+			sl_link_config_pause_str(SL_LINK_CONFIG_PAUSE_SYM));
+	if (!idx)
+		return sysfs_emit(buf, "none\n");
+	output[idx - 1] = '\0';
+
+	return sysfs_emit(buf, "%s\n", output);
+}
+
+static ssize_t fec_map_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+	struct sl_core_lgrp *core_lgrp;
+	int                  idx;
+	char                 output[20];
+	u32                  fec_map;
+	u32                  link_state;
+	int		     rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, caps_kobj);
+
+	core_link = sl_core_link_get(ctrl_link->ctrl_lgrp->ctrl_ldev->num,
+				     ctrl_link->ctrl_lgrp->num, ctrl_link->num);
+	if (!core_link)
+		return sysfs_emit(buf, "no-link\n");
+
+	core_lgrp = core_link->core_lgrp;
+
+	fec_map = core_lgrp->link_caps[core_link->num].fec_map;
+
+	sl_log_dbg(core_link, LOG_BLOCK, LOG_NAME,
+		   "fec map show (link = 0x%p, map = 0x%X)", core_link, fec_map);
+
+	rtn = sl_core_link_state_get(ctrl_link->ctrl_lgrp->ctrl_ldev->num,
+				     ctrl_link->ctrl_lgrp->num, ctrl_link->num, &link_state);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	if ((fec_map == 0) ||
+	    ((link_state != SL_CORE_LINK_STATE_UP) &&
+		 (link_state != SL_CORE_LINK_STATE_GOING_UP) &&
+		 (link_state != SL_CORE_LINK_STATE_AN)) ||
+		!is_flag_set(core_link->config.flags, SL_LINK_CONFIG_OPT_AUTONEG_ENABLE))
+		return sysfs_emit(buf, "none\n");
+
+	idx = 0;
+	if (is_flag_set(fec_map, SL_LGRP_CONFIG_FEC_RS_LL))
+		idx += snprintf(output + idx, sizeof(output) - idx, "%s ",
+			sl_lgrp_config_fec_str(SL_LGRP_CONFIG_FEC_RS_LL));
+	if (is_flag_set(fec_map, SL_LGRP_CONFIG_FEC_RS))
+		idx += snprintf(output + idx, sizeof(output) - idx, "%s ",
+			sl_lgrp_config_fec_str(SL_LGRP_CONFIG_FEC_RS));
+	if (!idx)
+		return sysfs_emit(buf, "none\n");
+	output[idx - 1] = '\0';
+
+	return sysfs_emit(buf, "%s\n", output);
+}
+
+static ssize_t hpe_map_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+	struct sl_core_lgrp *core_lgrp;
+	int                  idx;
+	char                 output[80];
+	u32                  hpe_map;
+	u32                  link_state;
+	int		     rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, caps_kobj);
+
+	core_link = sl_core_link_get(ctrl_link->ctrl_lgrp->ctrl_ldev->num,
+				     ctrl_link->ctrl_lgrp->num, ctrl_link->num);
+	if (!core_link)
+		return sysfs_emit(buf, "no-link\n");
+
+	core_lgrp = core_link->core_lgrp;
+
+	hpe_map = core_lgrp->link_caps[core_link->num].hpe_map;
+
+	sl_log_dbg(core_link, LOG_BLOCK, LOG_NAME,
+		   "hpe map show (link = 0x%p, map = 0x%X)", core_link, hpe_map);
+
+	rtn = sl_core_link_state_get(ctrl_link->ctrl_lgrp->ctrl_ldev->num,
+				     ctrl_link->ctrl_lgrp->num, ctrl_link->num, &link_state);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	if ((hpe_map == 0) ||
+	    ((link_state != SL_CORE_LINK_STATE_UP) &&
+		 (link_state != SL_CORE_LINK_STATE_GOING_UP) &&
+		 (link_state != SL_CORE_LINK_STATE_AN)) ||
+		!is_flag_set(core_link->config.flags, SL_LINK_CONFIG_OPT_AUTONEG_ENABLE))
+		return sysfs_emit(buf, "none\n");
+
+	idx = 0;
+	if (is_flag_set(hpe_map, SL_LINK_CONFIG_HPE_LINKTRAIN))
+		idx += snprintf(output + idx, sizeof(output) - idx, "%s ",
+			sl_link_config_hpe_str(SL_LINK_CONFIG_HPE_LINKTRAIN));
+	if (is_flag_set(hpe_map, SL_LINK_CONFIG_HPE_PRECODING))
+		idx += snprintf(output + idx, sizeof(output) - idx, "%s ",
+			sl_link_config_hpe_str(SL_LINK_CONFIG_HPE_PRECODING));
+	if (is_flag_set(hpe_map, SL_LINK_CONFIG_HPE_PCAL))
+		idx += snprintf(output + idx, sizeof(output) - idx, "%s ",
+			sl_link_config_hpe_str(SL_LINK_CONFIG_HPE_PCAL));
+	if (is_flag_set(hpe_map, SL_LINK_CONFIG_HPE_R3))
+		idx += snprintf(output + idx, sizeof(output) - idx, "%s ",
+			sl_link_config_hpe_str(SL_LINK_CONFIG_HPE_R3));
+	if (is_flag_set(hpe_map, SL_LINK_CONFIG_HPE_R2))
+		idx += snprintf(output + idx, sizeof(output) - idx, "%s ",
+			sl_link_config_hpe_str(SL_LINK_CONFIG_HPE_R2));
+	if (is_flag_set(hpe_map, SL_LINK_CONFIG_HPE_C3))
+		idx += snprintf(output + idx, sizeof(output) - idx, "%s ",
+			sl_link_config_hpe_str(SL_LINK_CONFIG_HPE_R3));
+	if (is_flag_set(hpe_map, SL_LINK_CONFIG_HPE_C2))
+		idx += snprintf(output + idx, sizeof(output) - idx, "%s ",
+			sl_link_config_hpe_str(SL_LINK_CONFIG_HPE_R2));
+	if (is_flag_set(hpe_map, SL_LINK_CONFIG_HPE_LLR))
+		idx += snprintf(output + idx, sizeof(output) - idx, "%s ",
+			sl_link_config_hpe_str(SL_LINK_CONFIG_HPE_LLR));
+	if (!idx)
+		return sysfs_emit(buf, "none\n");
+	output[idx - 1] = '\0';
+
+	return sysfs_emit(buf, "%s\n", output);
+}
+
+static struct kobj_attribute tech_map  = __ATTR_RO(tech_map);
+static struct kobj_attribute fec_map   = __ATTR_RO(fec_map);
+static struct kobj_attribute pause_map = __ATTR_RO(pause_map);
+static struct kobj_attribute hpe_map   = __ATTR_RO(hpe_map);
+
+static struct attribute *link_caps_attrs[] = {
+	&tech_map.attr,
+	&fec_map.attr,
+	&pause_map.attr,
+	&hpe_map.attr,
+	NULL
+};
+ATTRIBUTE_GROUPS(link_caps);
+
+static struct kobj_type link_caps = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = link_caps_groups,
+};
+#endif /* CONFIG_SYSFS */
+
+int sl_sysfs_link_caps_create(struct sl_ctrl_link *ctrl_link)
+{
+#ifdef CONFIG_SYSFS
+	int rtn;
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link caps create (num = %u)", ctrl_link->num);
+
+	rtn = kobject_init_and_add(&ctrl_link->caps_kobj, &link_caps, &ctrl_link->kobj, "caps");
+	if (rtn) {
+		sl_log_err(ctrl_link, LOG_BLOCK, LOG_NAME,
+			   "link caps create kobject_init_and_add failed [%d]", rtn);
+		kobject_put(&ctrl_link->caps_kobj);
+		return rtn;
+	}
+
+	return 0;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_link_caps_delete(struct sl_ctrl_link *ctrl_link)
+{
+#ifdef CONFIG_SYSFS
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link caps delete (num = %u)", ctrl_link->num);
+
+	kobject_put(&ctrl_link->caps_kobj);
+#endif /* CONFIG_SYSFS */
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_config.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_config.c
new file mode 100644
index 000000000000..a61072c56ca3
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_config.c
@@ -0,0 +1,388 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2024-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kobject.h>
+#include <linux/sysfs.h>
+
+#include "sl_log.h"
+#include "sl_sysfs.h"
+#include "data/sl_ctrl_data_link.h"
+#include "sl_ctrl_link.h"
+#include "sl_core_link.h"
+#include "data/sl_ctrl_data_link.h"
+#include "sl_test_common.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+#ifdef CONFIG_SYSFS
+static ssize_t link_up_timeout_ms_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link;
+	u32                  link_up_timeout_ms;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, config_kobj);
+
+	rtn = sl_ctrl_data_link_up_timeout_ms_get(ctrl_link, &link_up_timeout_ms);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "link up timeout show (link_up_timeout = %ums)", link_up_timeout_ms);
+
+	return sysfs_emit(buf, "%u\n", link_up_timeout_ms);
+}
+
+static ssize_t link_up_tries_max_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link;
+	u32                  link_up_tries_max;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, config_kobj);
+
+	rtn = sl_ctrl_data_link_up_tries_max_get(ctrl_link, &link_up_tries_max);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "link up tries max show (link_up_tries_max = %d)", link_up_tries_max);
+
+	if (link_up_tries_max == SL_LINK_INFINITE_UP_TRIES)
+		return sysfs_emit(buf, "infinite\n");
+	else
+		return sysfs_emit(buf, "%d\n", link_up_tries_max);
+}
+
+static ssize_t fec_up_settle_wait_ms_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link;
+	u32                  fec_up_settle_wait_ms;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, config_kobj);
+
+	rtn = sl_ctrl_data_link_fec_up_settle_wait_ms_get(ctrl_link, &fec_up_settle_wait_ms);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "fec_up_settle_wait show (fec_up_settle_wait = %dms)", fec_up_settle_wait_ms);
+
+	return sysfs_emit(buf, "%d\n", fec_up_settle_wait_ms);
+}
+
+static ssize_t fec_up_check_wait_ms_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link;
+	u32                  fec_up_check_wait_ms;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, config_kobj);
+
+	rtn = sl_ctrl_data_link_fec_up_check_wait_ms_get(ctrl_link, &fec_up_check_wait_ms);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "fec_up_check_wait show (fec_up_check_wait = %dms)", fec_up_check_wait_ms);
+
+	return sysfs_emit(buf, "%d\n", fec_up_check_wait_ms);
+}
+
+static ssize_t fec_up_ucw_limit_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link;
+	s32		     fec_up_ucw_limit;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, config_kobj);
+
+	rtn = sl_ctrl_data_link_fec_up_ucw_limit_get(ctrl_link, &fec_up_ucw_limit);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "fec_up_ucw_limit show (fec_up_ucw_limit = %d)", fec_up_ucw_limit);
+
+	return sysfs_emit(buf, "%d\n", fec_up_ucw_limit);
+}
+
+static ssize_t fec_up_ccw_limit_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link;
+	s32		     fec_up_ccw_limit;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, config_kobj);
+
+	rtn = sl_ctrl_data_link_fec_up_ccw_limit_get(ctrl_link, &fec_up_ccw_limit);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "fec_up_ccw_limit show (fec_up_ccw_limit = %d)", fec_up_ccw_limit);
+
+	return sysfs_emit(buf, "%d\n", fec_up_ccw_limit);
+}
+
+static ssize_t lock_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link;
+	u32                  options;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, config_kobj);
+
+	rtn = sl_ctrl_data_link_config_options_get(ctrl_link, &options);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "lock show (options = 0x%X)", options);
+
+	return sysfs_emit(buf, "%s\n", is_flag_set(options,
+			 SL_LINK_CONFIG_OPT_LOCK) ? "enabled" : "disabled");
+}
+
+static ssize_t pause_map_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link;
+	int                  idx;
+	char                 output[20];
+	u32                  pause_map;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, config_kobj);
+
+	rtn = sl_ctrl_data_link_pause_map_get(ctrl_link, &pause_map);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "pause map show (link = 0x%p, map = 0x%X)", ctrl_link, pause_map);
+
+	if (pause_map == 0)
+		return sysfs_emit(buf, "none\n");
+
+	idx = 0;
+	if (is_flag_set(pause_map, SL_LINK_CONFIG_PAUSE_ASYM))
+		idx += snprintf(output + idx, sizeof(output) - idx, "%s ",
+			sl_link_config_pause_str(SL_LINK_CONFIG_PAUSE_ASYM));
+	if (is_flag_set(pause_map, SL_LINK_CONFIG_PAUSE_SYM))
+		idx += snprintf(output + idx, sizeof(output) - idx, "%s ",
+			sl_link_config_pause_str(SL_LINK_CONFIG_PAUSE_SYM));
+	if (!idx)
+		return sysfs_emit(buf, "none\n");
+	output[idx - 1] = '\0';
+
+	return sysfs_emit(buf, "%s\n", output);
+}
+
+static ssize_t hpe_map_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link;
+	int                  idx;
+	char                 output[80];
+	u32                  hpe_map;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, config_kobj);
+
+	rtn = sl_ctrl_data_link_hpe_map_get(ctrl_link, &hpe_map);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "hpe map show (link = 0x%p, map = 0x%X)", ctrl_link, hpe_map);
+
+	if (hpe_map == 0)
+		return sysfs_emit(buf, "none\n");
+
+	idx = 0;
+	if (is_flag_set(hpe_map, SL_LINK_CONFIG_HPE_LINKTRAIN))
+		idx += snprintf(output + idx, sizeof(output) - idx, "%s ",
+			sl_link_config_hpe_str(SL_LINK_CONFIG_HPE_LINKTRAIN));
+	if (is_flag_set(hpe_map, SL_LINK_CONFIG_HPE_PRECODING))
+		idx += snprintf(output + idx, sizeof(output) - idx, "%s ",
+			sl_link_config_hpe_str(SL_LINK_CONFIG_HPE_PRECODING));
+	if (is_flag_set(hpe_map, SL_LINK_CONFIG_HPE_PCAL))
+		idx += snprintf(output + idx, sizeof(output) - idx, "%s ",
+			sl_link_config_hpe_str(SL_LINK_CONFIG_HPE_PCAL));
+	if (is_flag_set(hpe_map, SL_LINK_CONFIG_HPE_R3))
+		idx += snprintf(output + idx, sizeof(output) - idx, "%s ",
+			sl_link_config_hpe_str(SL_LINK_CONFIG_HPE_R3));
+	if (is_flag_set(hpe_map, SL_LINK_CONFIG_HPE_R2))
+		idx += snprintf(output + idx, sizeof(output) - idx, "%s ",
+			sl_link_config_hpe_str(SL_LINK_CONFIG_HPE_R2));
+	if (is_flag_set(hpe_map, SL_LINK_CONFIG_HPE_C3))
+		idx += snprintf(output + idx, sizeof(output) - idx, "%s ",
+			sl_link_config_hpe_str(SL_LINK_CONFIG_HPE_R3));
+	if (is_flag_set(hpe_map, SL_LINK_CONFIG_HPE_C2))
+		idx += snprintf(output + idx, sizeof(output) - idx, "%s ",
+			sl_link_config_hpe_str(SL_LINK_CONFIG_HPE_R2));
+	if (is_flag_set(hpe_map, SL_LINK_CONFIG_HPE_LLR))
+		idx += snprintf(output + idx, sizeof(output) - idx, "%s ",
+			sl_link_config_hpe_str(SL_LINK_CONFIG_HPE_LLR));
+	if (!idx)
+		return sysfs_emit(buf, "none\n");
+	output[idx - 1] = '\0';
+
+	return sysfs_emit(buf, "%s\n", output);
+}
+
+static ssize_t autoneg_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link;
+	u32                  options;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, config_kobj);
+
+	rtn = sl_ctrl_data_link_config_options_get(ctrl_link, &options);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "autoneg show (options = 0x%X)", options);
+
+	if (is_flag_set(options, SL_LINK_CONFIG_OPT_AUTONEG_ENABLE))
+		return sysfs_emit(buf, "enabled\n");
+
+	if (is_flag_set(options, SL_LINK_CONFIG_OPT_AUTONEG_CONTINUOUS_ENABLE))
+		return sysfs_emit(buf, "enabled-continuous\n");
+
+	return sysfs_emit(buf, "disabled\n");
+}
+
+static ssize_t loopback_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link;
+	u32                  options;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, config_kobj);
+
+	rtn = sl_ctrl_data_link_config_options_get(ctrl_link, &options);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "loopback show (options = 0x%X)", options);
+
+	if (is_flag_set(options, SL_LINK_CONFIG_OPT_HEADSHELL_LOOPBACK_ENABLE))
+		return sysfs_emit(buf, "enabled-headshell\n");
+
+	if (is_flag_set(options, SL_LINK_CONFIG_OPT_REMOTE_LOOPBACK_ENABLE))
+		return sysfs_emit(buf, "enabled-remote\n");
+
+	return sysfs_emit(buf, "disabled\n");
+}
+
+static ssize_t auto_lane_degrade_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link;
+	u32                  options;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, config_kobj);
+
+	rtn = sl_ctrl_data_link_config_options_get(ctrl_link, &options);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "auto lane degrade show (options = 0x%X)", options);
+
+	if (is_flag_set(options, SL_LINK_CONFIG_OPT_ALD_ENABLE))
+		return sysfs_emit(buf, "enabled\n");
+
+	return sysfs_emit(buf, "disabled\n");
+}
+
+static ssize_t pml_recovery_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link;
+	u32                  options;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, config_kobj);
+
+	rtn = sl_ctrl_data_link_config_options_get(ctrl_link, &options);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "pml recovery show (options = 0x%X)", options);
+
+	if (is_flag_set(options, SL_LINK_CONFIG_OPT_PML_REC_ENABLE))
+		return sysfs_emit(buf, "enabled\n");
+
+	return sysfs_emit(buf, "disabled\n");
+}
+
+static struct kobj_attribute link_up_timeout_ms    = __ATTR_RO(link_up_timeout_ms);
+static struct kobj_attribute link_up_tries_max_ms  = __ATTR_RO(link_up_tries_max);
+static struct kobj_attribute fec_up_settle_wait_ms = __ATTR_RO(fec_up_settle_wait_ms);
+static struct kobj_attribute fec_up_check_wait_ms  = __ATTR_RO(fec_up_check_wait_ms);
+static struct kobj_attribute fec_up_ucw_limit      = __ATTR_RO(fec_up_ucw_limit);
+static struct kobj_attribute fec_up_ccw_limit      = __ATTR_RO(fec_up_ccw_limit);
+static struct kobj_attribute lock                  = __ATTR_RO(lock);
+static struct kobj_attribute pause_map             = __ATTR_RO(pause_map);
+static struct kobj_attribute hpe_map               = __ATTR_RO(hpe_map);
+static struct kobj_attribute autoneg               = __ATTR_RO(autoneg);
+static struct kobj_attribute loopback              = __ATTR_RO(loopback);
+static struct kobj_attribute auto_lane_degrade     = __ATTR_RO(auto_lane_degrade);
+static struct kobj_attribute pml_recovery          = __ATTR_RO(pml_recovery);
+
+static struct attribute *link_config_attrs[] = {
+	&link_up_timeout_ms.attr,
+	&link_up_tries_max_ms.attr,
+	&fec_up_settle_wait_ms.attr,
+	&fec_up_check_wait_ms.attr,
+	&fec_up_ucw_limit.attr,
+	&fec_up_ccw_limit.attr,
+	&lock.attr,
+	&pause_map.attr,
+	&hpe_map.attr,
+	&autoneg.attr,
+	&loopback.attr,
+	&auto_lane_degrade.attr,
+	&pml_recovery.attr,
+	NULL
+};
+ATTRIBUTE_GROUPS(link_config);
+
+static struct kobj_type link_config = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = link_config_groups,
+};
+#endif /* CONFIG_SYSFS */
+
+int sl_sysfs_link_config_create(struct sl_ctrl_link *ctrl_link)
+{
+#ifdef CONFIG_SYSFS
+	int rtn;
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link config create (num = %u)", ctrl_link->num);
+
+	rtn = kobject_init_and_add(&ctrl_link->config_kobj, &link_config, &ctrl_link->kobj, "config");
+	if (rtn) {
+		sl_log_err(ctrl_link, LOG_BLOCK, LOG_NAME,
+			   "link config create kobject_init_and_add failed [%d]", rtn);
+		kobject_put(&ctrl_link->config_kobj);
+		return rtn;
+	}
+
+	return 0;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_link_config_delete(struct sl_ctrl_link *ctrl_link)
+{
+#ifdef CONFIG_SYSFS
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link config delete (num = %u)", ctrl_link->num);
+
+	kobject_put(&ctrl_link->config_kobj);
+#endif /* CONFIG_SYSFS */
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_counters.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_counters.c
new file mode 100644
index 000000000000..fdfb84636d0e
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_counters.c
@@ -0,0 +1,1498 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2025,2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kobject.h>
+#include <linux/sysfs.h>
+
+#include "sl_log.h"
+#include "sl_sysfs.h"
+#include "sl_ctrl_link.h"
+#include "sl_core_link.h"
+#include "sl_ctrl_link_counters.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+#ifdef CONFIG_SYSFS
+static ssize_t link_up_cmd_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_counters_get(ctrl_link, LINK_UP_CMD, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link up cmd show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t link_up_retry_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_counters_get(ctrl_link, LINK_UP_RETRY, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link up retry show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t link_up_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_counters_get(ctrl_link, LINK_UP, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link up show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t link_up_fail_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_counters_get(ctrl_link, LINK_UP_FAIL, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link up fail show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t link_down_cmd_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_counters_get(ctrl_link, LINK_DOWN_CMD, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link down cmd show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t link_down_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_counters_get(ctrl_link, LINK_DOWN, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link down show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t link_up_canceled_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_counters_get(ctrl_link, LINK_UP_CANCELED, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link up canceled show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t link_up_cancel_cmd_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_counters_get(ctrl_link, LINK_UP_CANCEL_CMD, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link up cancel cmd show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t link_reset_cmd_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_counters_get(ctrl_link, LINK_RESET_CMD, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link reset cmd show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t link_fault_async_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_counters_get(ctrl_link, LINK_FAULT_ASYNC, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link fault async show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t link_ccw_warn_crossed_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_counters_get(ctrl_link, LINK_CCW_WARN_CROSSED, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link ccw warn crossed show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t link_ucw_warn_crossed_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_counters_get(ctrl_link, LINK_UCW_WARN_CROSSED, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link ucw warn crossed show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t link_down_ccw_limit_crossed_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_counters_get(ctrl_link, LINK_DOWN_CCW_LIMIT_CROSSED, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link down ccw limit crossed show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t link_down_ucw_limit_crossed_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_counters_get(ctrl_link, LINK_DOWN_UCW_LIMIT_CROSSED, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link down ucw limit crossed show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t link_down_ccw_cause_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_counters_get(ctrl_link, LINK_DOWN_CCW_CAUSE, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link down ccw cause show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t link_down_ucw_cause_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_counters_get(ctrl_link, LINK_DOWN_UCW_CAUSE, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link down ucw cause show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t link_up_fail_ccw_limit_crossed_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_counters_get(ctrl_link, LINK_UP_FAIL_CCW_LIMIT_CROSSED, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link up fail ccw limit crossed show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t link_up_fail_ucw_limit_crossed_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_counters_get(ctrl_link, LINK_UP_FAIL_UCW_LIMIT_CROSSED, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link up fail ucw limit crossed show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t link_autoneg_np_retry_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_an_retry_count_get(ctrl_link, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link autoneg np retry show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t link_autoneg_attempt_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_counters_get(ctrl_link, LINK_HW_AN_ATTEMPT, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link autoneg attempt show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_ucw_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_cause_counters_get(ctrl_link, LINK_CAUSE_UCW, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link cause ucw show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_lf_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_cause_counters_get(ctrl_link, LINK_CAUSE_LF, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link cause lf show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_rf_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_cause_counters_get(ctrl_link, LINK_CAUSE_RF, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link cause rf show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_down_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_cause_counters_get(ctrl_link, LINK_CAUSE_DOWN, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link cause down show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_up_tries_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_cause_counters_get(ctrl_link, LINK_CAUSE_UP_TRIES, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link cause up tries show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_autoneg_nomatch_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_cause_counters_get(ctrl_link, LINK_CAUSE_AUTONEG_NOMATCH, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link cause autoneg nomatch show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_autoneg_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_cause_counters_get(ctrl_link, LINK_CAUSE_AUTONEG, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link cause autoneg show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_config_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_cause_counters_get(ctrl_link, LINK_CAUSE_CONFIG, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link cause config show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_intr_enable_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_cause_counters_get(ctrl_link, LINK_CAUSE_INTR_ENABLE, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link cause intr enable show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_timeout_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_cause_counters_get(ctrl_link, LINK_CAUSE_TIMEOUT, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link cause timeout show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_canceled_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_cause_counters_get(ctrl_link, LINK_CAUSE_CANCELED, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link cause canceled show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_unsupported_cable_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_cause_counters_get(ctrl_link, LINK_CAUSE_UNSUPPORTED_CABLE, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link cause unsupported cable show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_command_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_cause_counters_get(ctrl_link, LINK_CAUSE_COMMAND, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link cause command show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_downshift_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_cause_counters_get(ctrl_link, LINK_CAUSE_DOWNSHIFT, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link cause downshift show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_llr_replay_max_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_cause_counters_get(ctrl_link, LINK_CAUSE_LLR_REPLAY_MAX, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link cause llr replay max show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_upshift_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_cause_counters_get(ctrl_link, LINK_CAUSE_UPSHIFT, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link cause upshift show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_autoneg_config_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_cause_counters_get(ctrl_link, LINK_CAUSE_AUTONEG_CONFIG, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link cause autoneg config show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_pcs_fault_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_cause_counters_get(ctrl_link, LINK_CAUSE_PCS_FAULT, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link cause pcs fault show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_serdes_pll_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_cause_counters_get(ctrl_link, LINK_CAUSE_SERDES_PLL, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link cause serdes pll show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_serdes_config_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_cause_counters_get(ctrl_link, LINK_CAUSE_SERDES_CONFIG, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link cause serdes config show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_serdes_signal_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_cause_counters_get(ctrl_link, LINK_CAUSE_SERDES_SIGNAL, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link cause serdes signal show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_serdes_quality_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_cause_counters_get(ctrl_link, LINK_CAUSE_SERDES_QUALITY, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link cause serdes quality show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_no_media_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_cause_counters_get(ctrl_link, LINK_CAUSE_NO_MEDIA, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link cause no media show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_ccw_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_cause_counters_get(ctrl_link, LINK_CAUSE_CCW, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link cause ccw show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_hot_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_cause_counters_get(ctrl_link, LINK_CAUSE_MEDIA_HOT, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link cause hot show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_warm_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_cause_counters_get(ctrl_link, LINK_CAUSE_MEDIA_WARM, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link cause warm show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_intr_register_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_cause_counters_get(ctrl_link, LINK_CAUSE_INTR_REGISTER, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link cause intr register show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_media_error_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_cause_counters_get(ctrl_link, LINK_CAUSE_MEDIA_ERROR, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link cause media error show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_up_canceled_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_cause_counters_get(ctrl_link, LINK_CAUSE_UP_CANCELED, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link cause up canceled show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_unsupported_speed_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_cause_counters_get(ctrl_link, LINK_CAUSE_UNSUPPORTED_SPEED, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link cause unsupported speed show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_ss200_cable_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_cause_counters_get(ctrl_link, LINK_CAUSE_SS200_CABLE, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link cause ss200 cable show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_tx_lol_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_cause_counters_get(ctrl_link, LINK_CAUSE_TX_LOL, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link cause tx lol show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_rx_lol_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_cause_counters_get(ctrl_link, LINK_CAUSE_RX_LOL, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link cause rx lol show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_tx_los_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_cause_counters_get(ctrl_link, LINK_CAUSE_TX_LOS, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link cause tx los show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_rx_los_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_cause_counters_get(ctrl_link, LINK_CAUSE_RX_LOS, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link cause rx los show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t an_cause_lp_caps_serdes_link_up_fail_show(struct kobject *kobj,
+							 struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_an_cause_counters_get(ctrl_link, LINK_AN_CAUSE_LP_CAPS_SERDES_LINK_UP_FAIL, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link an cause lp caps serdes link up fail show (counter = %u)",
+		   counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t an_cause_lp_caps_not_complete_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_an_cause_counters_get(ctrl_link, LINK_AN_CAUSE_LP_CAPS_NOT_COMPLETE, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link an cause lp caps not complete show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t an_cause_not_complete_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_an_cause_counters_get(ctrl_link, LINK_AN_CAUSE_NOT_COMPLETE, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link an cause not complete show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t an_cause_test_caps_nomatch_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_an_cause_counters_get(ctrl_link, LINK_AN_CAUSE_TEST_CAPS_NOMATCH, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link an cause test caps nomatch show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t an_cause_serdes_link_up_fail_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_an_cause_counters_get(ctrl_link, LINK_AN_CAUSE_SERDES_LINK_UP_FAIL, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link an cause serdes link up fail show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t an_cause_bp_store_state_bad_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_an_cause_counters_get(ctrl_link, LINK_AN_CAUSE_BP_STORE_STATE_BAD, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link an cause bp store state bad show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t an_cause_bp_store_lp_ability_not_set_show(struct kobject *kobj, struct kobj_attribute *kattr,
+							 char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_an_cause_counters_get(ctrl_link, LINK_AN_CAUSE_BP_STORE_LP_ABILITY_NOT_SET, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link an cause bp store lp ability not set show (counter = %u)",
+		   counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t an_cause_bp_store_state_error_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_an_cause_counters_get(ctrl_link, LINK_AN_CAUSE_BP_STORE_STATE_ERROR, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link an cause bp store state error show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t an_cause_bp_store_bp_not_set_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_an_cause_counters_get(ctrl_link, LINK_AN_CAUSE_BP_STORE_BP_NOT_SET, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link an cause bp store bp not set show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t an_cause_bp_send_intr_enable_fail_show(struct kobject *kobj, struct kobj_attribute *kattr,
+						      char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_an_cause_counters_get(ctrl_link, LINK_AN_CAUSE_BP_SEND_INTR_ENABLE_FAIL, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link an cause bp send intr enable fail show (counter = %u)",
+		   counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t an_cause_np_store_state_bad_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_an_cause_counters_get(ctrl_link, LINK_AN_CAUSE_NP_STORE_STATE_BAD, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link an cause np store state bad show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t an_cause_np_store_bp_set_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_an_cause_counters_get(ctrl_link, LINK_AN_CAUSE_NP_STORE_BP_SET, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link an cause np store state bp set show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t an_cause_np_check_state_bad_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_an_cause_counters_get(ctrl_link, LINK_AN_CAUSE_NP_CHECK_STATE_BAD, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link an cause np check state bad show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t an_cause_intr_state_invalid_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_an_cause_counters_get(ctrl_link, LINK_AN_CAUSE_INTR_STATE_INVALID, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link an cause intr state invalid show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t an_cause_intr_an_retry_np_send_fail_show(struct kobject *kobj, struct kobj_attribute *kattr,
+							char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_an_cause_counters_get(ctrl_link, LINK_AN_CAUSE_INTR_AN_RETRY_NP_SEND_FAIL, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link an cause intr an retry np send fail show (counter = %u)",
+		   counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t an_cause_intr_out_of_pages_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_an_cause_counters_get(ctrl_link, LINK_AN_CAUSE_INTR_OUT_OF_PAGES, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link an cause intr out og pages show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t an_cause_intr_np_send_fail_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_an_cause_counters_get(ctrl_link, LINK_AN_CAUSE_INTR_NP_SEND_FAIL, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link an cause intr np send fail show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t an_cause_pages_decode_fail_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_an_cause_counters_get(ctrl_link, LINK_AN_CAUSE_PAGES_DECODE_FAIL, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link an cause pages decode fail show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t an_cause_pages_decode_no_bp_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_an_cause_counters_get(ctrl_link, LINK_AN_CAUSE_PAGES_DECODE_NO_BP, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link an cause pages decode no bp show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t an_cause_pages_decode_oui_invalid_show(struct kobject *kobj, struct kobj_attribute *kattr,
+						      char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	u32                  counter;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, counters_kobj);
+
+	rtn = sl_ctrl_link_an_cause_counters_get(ctrl_link, LINK_AN_CAUSE_PAGES_DECODE_OUI_INVALID, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link an cause pages decode oui invalid show (counter = %u)",
+		   counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static struct kobj_attribute link_up_cmd                    = __ATTR_RO(link_up_cmd);
+static struct kobj_attribute link_up_retry                  = __ATTR_RO(link_up_retry);
+static struct kobj_attribute link_up                        = __ATTR_RO(link_up);
+static struct kobj_attribute link_up_fail                   = __ATTR_RO(link_up_fail);
+static struct kobj_attribute link_down_cmd                  = __ATTR_RO(link_down_cmd);
+static struct kobj_attribute link_down                      = __ATTR_RO(link_down);
+static struct kobj_attribute link_up_cancel_cmd             = __ATTR_RO(link_up_cancel_cmd);
+static struct kobj_attribute link_up_canceled               = __ATTR_RO(link_up_canceled);
+static struct kobj_attribute link_reset_cmd                 = __ATTR_RO(link_reset_cmd);
+static struct kobj_attribute link_fault_async               = __ATTR_RO(link_fault_async);
+static struct kobj_attribute link_ccw_warn_crossed          = __ATTR_RO(link_ccw_warn_crossed);
+static struct kobj_attribute link_ucw_warn_crossed          = __ATTR_RO(link_ucw_warn_crossed);
+static struct kobj_attribute link_down_ccw_limit_crossed    = __ATTR_RO(link_down_ccw_limit_crossed);
+static struct kobj_attribute link_down_ucw_limit_crossed    = __ATTR_RO(link_down_ucw_limit_crossed);
+static struct kobj_attribute link_down_ccw_cause            = __ATTR_RO(link_down_ccw_cause);
+static struct kobj_attribute link_down_ucw_cause            = __ATTR_RO(link_down_ucw_cause);
+static struct kobj_attribute link_up_fail_ccw_limit_crossed = __ATTR_RO(link_up_fail_ccw_limit_crossed);
+static struct kobj_attribute link_up_fail_ucw_limit_crossed = __ATTR_RO(link_up_fail_ucw_limit_crossed);
+static struct kobj_attribute link_autoneg_np_retry          = __ATTR_RO(link_autoneg_np_retry);
+static struct kobj_attribute link_autoneg_attempt           = __ATTR_RO(link_autoneg_attempt);
+
+static struct kobj_attribute link_cause_ucw               = __ATTR_RO(cause_ucw);
+static struct kobj_attribute link_cause_lf                = __ATTR_RO(cause_lf);
+static struct kobj_attribute link_cause_rf                = __ATTR_RO(cause_rf);
+static struct kobj_attribute link_cause_down              = __ATTR_RO(cause_down);
+static struct kobj_attribute link_cause_up_tries          = __ATTR_RO(cause_up_tries);
+static struct kobj_attribute link_cause_autoneg_nomatch   = __ATTR_RO(cause_autoneg_nomatch);
+static struct kobj_attribute link_cause_autoneg           = __ATTR_RO(cause_autoneg);
+static struct kobj_attribute link_cause_config            = __ATTR_RO(cause_config);
+static struct kobj_attribute link_cause_intr_enable       = __ATTR_RO(cause_intr_enable);
+static struct kobj_attribute link_cause_timeout           = __ATTR_RO(cause_timeout);
+static struct kobj_attribute link_cause_canceled          = __ATTR_RO(cause_canceled);
+static struct kobj_attribute link_cause_unsupported_cable = __ATTR_RO(cause_unsupported_cable);
+static struct kobj_attribute link_cause_command           = __ATTR_RO(cause_command);
+static struct kobj_attribute link_cause_downshift         = __ATTR_RO(cause_downshift);
+static struct kobj_attribute link_cause_llr_replay_max    = __ATTR_RO(cause_llr_replay_max);
+static struct kobj_attribute link_cause_upshift           = __ATTR_RO(cause_upshift);
+static struct kobj_attribute link_cause_autoneg_config    = __ATTR_RO(cause_autoneg_config);
+static struct kobj_attribute link_cause_pcs_fault         = __ATTR_RO(cause_pcs_fault);
+static struct kobj_attribute link_cause_serdes_pll        = __ATTR_RO(cause_serdes_pll);
+static struct kobj_attribute link_cause_serdes_config     = __ATTR_RO(cause_serdes_config);
+static struct kobj_attribute link_cause_serdes_signal     = __ATTR_RO(cause_serdes_signal);
+static struct kobj_attribute link_cause_serdes_quality    = __ATTR_RO(cause_serdes_quality);
+static struct kobj_attribute link_cause_no_media          = __ATTR_RO(cause_no_media);
+static struct kobj_attribute link_cause_ccw               = __ATTR_RO(cause_ccw);
+static struct kobj_attribute link_cause_hot               = __ATTR_RO(cause_hot);
+static struct kobj_attribute link_cause_warm              = __ATTR_RO(cause_warm);
+static struct kobj_attribute link_cause_intr_register     = __ATTR_RO(cause_intr_register);
+static struct kobj_attribute link_cause_media_error       = __ATTR_RO(cause_media_error);
+static struct kobj_attribute link_cause_up_canceled       = __ATTR_RO(cause_up_canceled);
+static struct kobj_attribute link_cause_unsupported_speed = __ATTR_RO(cause_unsupported_speed);
+static struct kobj_attribute link_cause_ss200_cable       = __ATTR_RO(cause_ss200_cable);
+static struct kobj_attribute link_cause_tx_lol            = __ATTR_RO(cause_tx_lol);
+static struct kobj_attribute link_cause_rx_lol            = __ATTR_RO(cause_rx_lol);
+static struct kobj_attribute link_cause_tx_los            = __ATTR_RO(cause_tx_los);
+static struct kobj_attribute link_cause_rx_los            = __ATTR_RO(cause_rx_los);
+
+static struct kobj_attribute link_an_cause_lp_caps_serdes_link_up_fail =
+			     __ATTR_RO(an_cause_lp_caps_serdes_link_up_fail);
+static struct kobj_attribute link_an_cause_lp_caps_not_complete        = __ATTR_RO(an_cause_lp_caps_not_complete);
+static struct kobj_attribute link_an_cause_not_complete                = __ATTR_RO(an_cause_not_complete);
+static struct kobj_attribute link_an_cause_test_caps_nomatch           = __ATTR_RO(an_cause_test_caps_nomatch);
+static struct kobj_attribute link_an_cause_serdes_link_up_fail         = __ATTR_RO(an_cause_serdes_link_up_fail);
+static struct kobj_attribute link_an_cause_bp_store_state_bad          = __ATTR_RO(an_cause_bp_store_state_bad);
+static struct kobj_attribute link_an_cause_bp_store_lp_ability_not_set =
+			     __ATTR_RO(an_cause_bp_store_lp_ability_not_set);
+static struct kobj_attribute link_an_cause_bp_store_state_error        = __ATTR_RO(an_cause_bp_store_state_error);
+static struct kobj_attribute link_an_cause_bp_store_bp_not_set         = __ATTR_RO(an_cause_bp_store_bp_not_set);
+static struct kobj_attribute link_an_cause_bp_send_intr_enable_fail    =
+			     __ATTR_RO(an_cause_bp_send_intr_enable_fail);
+static struct kobj_attribute link_an_cause_np_store_state_bad          = __ATTR_RO(an_cause_np_store_state_bad);
+static struct kobj_attribute link_an_cause_np_store_bp_set             = __ATTR_RO(an_cause_np_store_bp_set);
+static struct kobj_attribute link_an_cause_np_check_state_bad          = __ATTR_RO(an_cause_np_check_state_bad);
+static struct kobj_attribute link_an_cause_intr_state_invalid          = __ATTR_RO(an_cause_intr_state_invalid);
+static struct kobj_attribute link_an_cause_intr_an_retry_np_send_fail  =
+			     __ATTR_RO(an_cause_intr_an_retry_np_send_fail);
+static struct kobj_attribute link_an_cause_intr_out_of_pages           = __ATTR_RO(an_cause_intr_out_of_pages);
+static struct kobj_attribute link_an_cause_intr_np_send_fail           = __ATTR_RO(an_cause_intr_np_send_fail);
+static struct kobj_attribute link_an_cause_pages_decode_fail           = __ATTR_RO(an_cause_pages_decode_fail);
+static struct kobj_attribute link_an_cause_pages_decode_no_bp          = __ATTR_RO(an_cause_pages_decode_no_bp);
+static struct kobj_attribute link_an_cause_pages_decode_oui_invalid    =
+			     __ATTR_RO(an_cause_pages_decode_oui_invalid);
+
+static struct attribute *link_counters_attrs[] = {
+	&link_up_cmd.attr,
+	&link_up_retry.attr,
+	&link_up.attr,
+	&link_up_fail.attr,
+	&link_down_cmd.attr,
+	&link_down.attr,
+	&link_up_cancel_cmd.attr,
+	&link_up_canceled.attr,
+	&link_reset_cmd.attr,
+	&link_fault_async.attr,
+	&link_ccw_warn_crossed.attr,
+	&link_ucw_warn_crossed.attr,
+	&link_down_ccw_limit_crossed.attr,
+	&link_down_ucw_limit_crossed.attr,
+	&link_down_ccw_cause.attr,
+	&link_down_ucw_cause.attr,
+	&link_up_fail_ccw_limit_crossed.attr,
+	&link_up_fail_ucw_limit_crossed.attr,
+	&link_autoneg_np_retry.attr,
+	&link_autoneg_attempt.attr,
+	&link_cause_ucw.attr,
+	&link_cause_lf.attr,
+	&link_cause_rf.attr,
+	&link_cause_down.attr,
+	&link_cause_up_tries.attr,
+	&link_cause_autoneg_nomatch.attr,
+	&link_cause_autoneg.attr,
+	&link_cause_config.attr,
+	&link_cause_intr_enable.attr,
+	&link_cause_timeout.attr,
+	&link_cause_canceled.attr,
+	&link_cause_unsupported_cable.attr,
+	&link_cause_command.attr,
+	&link_cause_downshift.attr,
+	&link_cause_llr_replay_max.attr,
+	&link_cause_upshift.attr,
+	&link_cause_autoneg_config.attr,
+	&link_cause_pcs_fault.attr,
+	&link_cause_serdes_pll.attr,
+	&link_cause_serdes_config.attr,
+	&link_cause_serdes_signal.attr,
+	&link_cause_serdes_quality.attr,
+	&link_cause_no_media.attr,
+	&link_cause_ccw.attr,
+	&link_cause_hot.attr,
+	&link_cause_warm.attr,
+	&link_cause_intr_register.attr,
+	&link_cause_media_error.attr,
+	&link_cause_up_canceled.attr,
+	&link_cause_unsupported_speed.attr,
+	&link_cause_ss200_cable.attr,
+	&link_cause_tx_lol.attr,
+	&link_cause_rx_lol.attr,
+	&link_cause_tx_los.attr,
+	&link_cause_rx_los.attr,
+	&link_an_cause_lp_caps_serdes_link_up_fail.attr,
+	&link_an_cause_lp_caps_not_complete.attr,
+	&link_an_cause_not_complete.attr,
+	&link_an_cause_test_caps_nomatch.attr,
+	&link_an_cause_serdes_link_up_fail.attr,
+	&link_an_cause_bp_store_state_bad.attr,
+	&link_an_cause_bp_store_lp_ability_not_set.attr,
+	&link_an_cause_bp_store_state_error.attr,
+	&link_an_cause_bp_store_bp_not_set.attr,
+	&link_an_cause_bp_send_intr_enable_fail.attr,
+	&link_an_cause_np_store_state_bad.attr,
+	&link_an_cause_np_store_bp_set.attr,
+	&link_an_cause_np_check_state_bad.attr,
+	&link_an_cause_intr_state_invalid.attr,
+	&link_an_cause_intr_an_retry_np_send_fail.attr,
+	&link_an_cause_intr_out_of_pages.attr,
+	&link_an_cause_intr_np_send_fail.attr,
+	&link_an_cause_pages_decode_fail.attr,
+	&link_an_cause_pages_decode_no_bp.attr,
+	&link_an_cause_pages_decode_oui_invalid.attr,
+	NULL
+};
+ATTRIBUTE_GROUPS(link_counters);
+
+static struct kobj_type link_counters = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = link_counters_groups,
+};
+#endif /* CONFIG_SYSFS */
+
+int sl_sysfs_link_counters_create(struct sl_ctrl_link *ctrl_link)
+{
+#ifdef CONFIG_SYSFS
+	int rtn;
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link counters create");
+
+	rtn = kobject_init_and_add(&ctrl_link->counters_kobj, &link_counters, &ctrl_link->kobj, "counters");
+	if (rtn) {
+		sl_log_err(ctrl_link, LOG_BLOCK, LOG_NAME,
+			   "link counters create kobject_init_and_add failed [%d]", rtn);
+		kobject_put(&ctrl_link->counters_kobj);
+		return rtn;
+	}
+
+	return 0;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_link_counters_delete(struct sl_ctrl_link *ctrl_link)
+{
+#ifdef CONFIG_SYSFS
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link counters delete");
+	kobject_put(&ctrl_link->counters_kobj);
+#endif /* CONFIG_SYSFS */
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_degrade.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_degrade.c
new file mode 100644
index 000000000000..3ba254a54560
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_degrade.c
@@ -0,0 +1,336 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2025-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kobject.h>
+#include <linux/sysfs.h>
+#include <linux/types.h>
+
+#include "sl_log.h"
+#include "data/sl_core_data_link.h"
+
+#include "sl_sysfs.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+#ifdef CONFIG_SYSFS
+static ssize_t state_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_core_link *core_link;
+	u32                  link_state;
+	int                  degrade_state;
+
+	core_link = container_of(kobj, struct sl_core_link, degrade_kobj);
+
+	rtn = sl_core_data_link_state_get(core_link, &link_state);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	if (link_state != SL_CORE_LINK_STATE_UP)
+		return sysfs_emit(buf, "no-link\n");
+
+	rtn = sl_core_data_link_degrade_state_get(core_link, &degrade_state);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_link, LOG_BLOCK, LOG_NAME, "degrade state show (state = %u %s)",
+		   degrade_state, sl_link_degrade_state_str(degrade_state));
+
+	return sysfs_emit(buf, "%s\n", sl_link_degrade_state_str(degrade_state));
+}
+
+static ssize_t is_rx_degraded_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_core_link *core_link;
+	bool                 is_rx_degraded;
+	u32                  link_state;
+
+	core_link = container_of(kobj, struct sl_core_link, degrade_kobj);
+
+	rtn = sl_core_data_link_state_get(core_link, &link_state);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	if (link_state != SL_CORE_LINK_STATE_UP)
+		return sysfs_emit(buf, "no-link\n");
+
+	rtn = sl_core_data_link_is_rx_degrade_get(core_link, &is_rx_degraded);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_link, LOG_BLOCK, LOG_NAME, "is rx degraded show (is_rx_degraded = %s)",
+		   is_rx_degraded ? "yes" : "no");
+
+	return sysfs_emit(buf, "%s\n", is_rx_degraded ? "yes" : "no");
+}
+
+static ssize_t rx_degrade_map_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_core_link *core_link;
+	u32                  link_state;
+	u8                   rx_degrade_map;
+	bool                 is_rx_degraded;
+
+	core_link = container_of(kobj, struct sl_core_link, degrade_kobj);
+
+	rtn = sl_core_data_link_state_get(core_link, &link_state);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	if (link_state != SL_CORE_LINK_STATE_UP)
+		return sysfs_emit(buf, "--\n");
+
+	rtn = sl_core_data_link_is_rx_degrade_get(core_link, &is_rx_degraded);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	if (!is_rx_degraded)
+		return sysfs_emit(buf, "--\n");
+
+	rtn = sl_core_data_link_degrade_rx_degrade_map_get(core_link, &rx_degrade_map);
+	if (rtn == -EBADRQC)
+		return sysfs_emit(buf, "--\n");
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_link, LOG_BLOCK, LOG_NAME,
+		   "rx degrade lane map show (rx_degrade_map = 0x%X)", rx_degrade_map);
+
+	return sysfs_emit(buf, "0x%X\n", rx_degrade_map);
+}
+
+static ssize_t rx_link_speed_gbps_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_core_link *core_link;
+	u32                  link_state;
+	u16                  link_speed;
+	bool                 is_rx_degraded;
+
+	core_link = container_of(kobj, struct sl_core_link, degrade_kobj);
+
+	rtn = sl_core_data_link_state_get(core_link, &link_state);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	if (link_state != SL_CORE_LINK_STATE_UP)
+		return sysfs_emit(buf, "--\n");
+
+	rtn = sl_core_data_link_is_rx_degrade_get(core_link, &is_rx_degraded);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	if (!is_rx_degraded)
+		return sysfs_emit(buf, "--\n");
+
+	rtn = sl_core_data_link_degrade_rx_link_speed_get(core_link, &link_speed);
+	if (rtn == -EBADRQC)
+		return sysfs_emit(buf, "--\n");
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_link, LOG_BLOCK, LOG_NAME,
+		   "rx degrade link speed gbps show (link_speed = %u)", link_speed);
+
+	return sysfs_emit(buf, "%u\n", link_speed);
+}
+
+static ssize_t is_tx_degraded_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_core_link *core_link;
+	bool                 is_tx_degraded;
+	u32                  link_state;
+
+	core_link = container_of(kobj, struct sl_core_link, degrade_kobj);
+
+	rtn = sl_core_data_link_state_get(core_link, &link_state);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	if (link_state != SL_CORE_LINK_STATE_UP)
+		return sysfs_emit(buf, "no-link\n");
+
+	rtn = sl_core_data_link_is_tx_degrade_get(core_link, &is_tx_degraded);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_link, LOG_BLOCK, LOG_NAME, "is tx degraded show (degrade = %s)",
+		   is_tx_degraded ? "yes" : "no");
+
+	return sysfs_emit(buf, "%s\n", is_tx_degraded ? "yes" : "no");
+}
+
+static ssize_t tx_degrade_map_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_core_link *core_link;
+	u32                  link_state;
+	u8                   tx_degrade_map;
+	bool                 is_tx_degraded;
+
+	core_link = container_of(kobj, struct sl_core_link, degrade_kobj);
+
+	rtn = sl_core_data_link_state_get(core_link, &link_state);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	if (link_state != SL_CORE_LINK_STATE_UP)
+		return sysfs_emit(buf, "--\n");
+
+	rtn = sl_core_data_link_is_tx_degrade_get(core_link, &is_tx_degraded);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	if (!is_tx_degraded)
+		return sysfs_emit(buf, "--\n");
+
+	rtn = sl_core_data_link_degrade_tx_degrade_map_get(core_link, &tx_degrade_map);
+	if (rtn == -EBADRQC)
+		return sysfs_emit(buf, "--\n");
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_link, LOG_BLOCK, LOG_NAME,
+		   "tx degrade lane map show (tx_degrade_map = 0x%X)", tx_degrade_map);
+
+	return sysfs_emit(buf, "0x%X\n", tx_degrade_map);
+}
+
+static ssize_t tx_link_speed_gbps_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_core_link *core_link;
+	u32                  link_state;
+	u16                  link_speed;
+	bool                 is_tx_degraded;
+
+	core_link = container_of(kobj, struct sl_core_link, degrade_kobj);
+
+	rtn = sl_core_data_link_state_get(core_link, &link_state);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	if (link_state != SL_CORE_LINK_STATE_UP)
+		return sysfs_emit(buf, "--\n");
+
+	rtn = sl_core_data_link_is_tx_degrade_get(core_link, &is_tx_degraded);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	if (!is_tx_degraded)
+		return sysfs_emit(buf, "--\n");
+
+	rtn = sl_core_data_link_degrade_tx_link_speed_get(core_link, &link_speed);
+	if (rtn == -EBADRQC)
+		return sysfs_emit(buf, "--\n");
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_link, LOG_BLOCK, LOG_NAME,
+		   "tx degrade link speed gbps show (link_speed = %u)", link_speed);
+
+	return sysfs_emit(buf, "%u\n", link_speed);
+}
+
+static ssize_t is_recoverable_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_core_link *core_link;
+	u32                  link_state;
+	bool                 is_tx_degraded;
+	bool                 is_rx_degraded;
+	bool                 is_recoverable;
+
+	core_link = container_of(kobj, struct sl_core_link, degrade_kobj);
+
+	rtn = sl_core_data_link_state_get(core_link, &link_state);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	if (link_state != SL_CORE_LINK_STATE_UP)
+		return sysfs_emit(buf, "no-link\n");
+
+	rtn = sl_core_data_link_is_tx_degrade_get(core_link, &is_tx_degraded);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	rtn = sl_core_data_link_is_rx_degrade_get(core_link, &is_rx_degraded);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	if (!is_rx_degraded && !is_tx_degraded)
+		return sysfs_emit(buf, "--\n");
+
+	rtn = sl_core_data_link_degrade_is_recoverable_get(core_link, &is_recoverable);
+	if (rtn == -EBADRQC)
+		return sysfs_emit(buf, "inactive\n");
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_link, LOG_BLOCK, LOG_NAME,
+		   "is recoverable show (is_recoverable = %s)", is_recoverable ? "yes" : "no");
+
+	return sysfs_emit(buf, "%s\n", is_recoverable ? "yes" : "no");
+}
+
+static struct kobj_attribute link_degrade_state              = __ATTR_RO(state);
+static struct kobj_attribute link_is_rx_degraded             = __ATTR_RO(is_rx_degraded);
+static struct kobj_attribute link_rx_degrade_lane_map        = __ATTR_RO(rx_degrade_map);
+static struct kobj_attribute link_rx_degrade_link_speed_gbps = __ATTR_RO(rx_link_speed_gbps);
+static struct kobj_attribute link_is_tx_degraded             = __ATTR_RO(is_tx_degraded);
+static struct kobj_attribute link_tx_degrade_lane_map        = __ATTR_RO(tx_degrade_map);
+static struct kobj_attribute link_tx_degrade_link_speed_gbps = __ATTR_RO(tx_link_speed_gbps);
+static struct kobj_attribute link_is_recoverable             = __ATTR_RO(is_recoverable);
+
+static struct attribute *link_degrade_attrs[] = {
+	&link_degrade_state.attr,
+	&link_is_rx_degraded.attr,
+	&link_rx_degrade_lane_map.attr,
+	&link_rx_degrade_link_speed_gbps.attr,
+	&link_is_tx_degraded.attr,
+	&link_tx_degrade_lane_map.attr,
+	&link_tx_degrade_link_speed_gbps.attr,
+	&link_is_recoverable.attr,
+	NULL
+};
+ATTRIBUTE_GROUPS(link_degrade);
+
+static struct kobj_type link_degrade = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = link_degrade_groups,
+};
+#endif /* CONFIG_SYSFS */
+
+int sl_sysfs_link_degrade_create(struct sl_core_link *core_link, struct kobject *parent_kobj)
+{
+#ifdef CONFIG_SYSFS
+	int rtn;
+
+	sl_log_dbg(core_link, LOG_BLOCK, LOG_NAME, "link degrade create (num = %u)", core_link->num);
+
+	rtn = kobject_init_and_add(&core_link->degrade_kobj, &link_degrade, parent_kobj, "auto_lane_degrade");
+	if (rtn) {
+		sl_log_err(core_link, LOG_BLOCK, LOG_NAME,
+			   "link degrade create kobject_init_and_add failed [%d]", rtn);
+		kobject_put(&core_link->degrade_kobj);
+		return rtn;
+	}
+
+	return 0;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_link_degrade_delete(struct sl_core_link *core_link)
+{
+#ifdef CONFIG_SYSFS
+	sl_log_dbg(core_link, LOG_BLOCK, LOG_NAME, "link degrade delete (num = %u)", core_link->num);
+
+	kobject_put(&core_link->degrade_kobj);
+#endif /* CONFIG_SYSFS */
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_fec.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_fec.c
new file mode 100644
index 000000000000..37edb89f8595
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_fec.c
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2024-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kobject.h>
+#include <linux/sysfs.h>
+
+#include "sl_log.h"
+#include "sl_sysfs.h"
+#include "sl_core_link.h"
+#include "sl_ctrl_ldev.h"
+#include "sl_ctrl_lgrp.h"
+#include "sl_ctrl_link.h"
+#include "sl_ctrl_link_fec.h"
+#include "sl_sysfs_link_fec_current.h"
+#include "sl_sysfs_link_fec_mon_check.h"
+#include "sl_sysfs_link_fec_up_check.h"
+#include "sl_sysfs_link_fec_up.h"
+#include "sl_sysfs_link_fec_down.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+#ifdef CONFIG_SYSFS
+static ssize_t monitor_state_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link;
+	u32                  state;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, fec.kobj);
+
+	rtn = sl_ctrl_link_fec_mon_state_get(ctrl_link, &state);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "monitor state show (link = 0x%p, state = %u, %s)", ctrl_link, state,
+		   sl_ctrl_link_fec_mon_state_str(state));
+
+	return sysfs_emit(buf, "%s\n", sl_ctrl_link_fec_mon_state_str(state));
+}
+
+static struct kobj_attribute fec_monitor_state = __ATTR_RO(monitor_state);
+
+static struct attribute *link_fec_attrs[] = {
+	&fec_monitor_state.attr,
+	NULL
+};
+ATTRIBUTE_GROUPS(link_fec);
+
+static struct kobj_type link_fec = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = link_fec_groups,
+};
+#endif /* CONFIG_SYSFS */
+
+int sl_sysfs_link_fec_create(struct sl_ctrl_link *ctrl_link)
+{
+#ifdef CONFIG_SYSFS
+	int                  rtn;
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link fec create (num = %u)", ctrl_link->num);
+
+	core_link = sl_core_link_get(ctrl_link->ctrl_lgrp->ctrl_ldev->num, ctrl_link->ctrl_lgrp->num, ctrl_link->num);
+	if (!core_link)
+		return -ENODEV;
+
+	rtn = kobject_init_and_add(&ctrl_link->fec.kobj, &link_fec, &ctrl_link->kobj, "fec");
+	if (rtn) {
+		sl_log_err(ctrl_link, LOG_BLOCK, LOG_NAME,
+			   "link fec create kobject_init_and_add failed [%d]", rtn);
+		kobject_put(&ctrl_link->fec.kobj);
+		return rtn;
+	}
+
+	rtn = sl_sysfs_link_fec_current_create(core_link, &ctrl_link->fec.kobj);
+	if (rtn) {
+		sl_log_err(ctrl_link, LOG_BLOCK, LOG_NAME,
+			   "link fec current create kobject_init_and_add failed [%d]", rtn);
+		kobject_put(&ctrl_link->fec.kobj);
+		return rtn;
+	}
+
+	rtn = sl_sysfs_link_fec_mon_check_create(ctrl_link);
+	if (rtn) {
+		sl_log_err(core_link, LOG_BLOCK, LOG_NAME, "fec mon check create failed [%d]", rtn);
+		sl_sysfs_link_fec_current_delete(core_link);
+		kobject_put(&ctrl_link->fec.kobj);
+		return rtn;
+	}
+
+	rtn = sl_sysfs_link_fec_up_check_create(core_link, &ctrl_link->fec.kobj);
+	if (rtn) {
+		sl_log_err(core_link, LOG_BLOCK, LOG_NAME, "fec up check create failed [%d]", rtn);
+		sl_sysfs_link_fec_current_delete(core_link);
+		sl_sysfs_link_fec_mon_check_delete(ctrl_link);
+		kobject_put(&ctrl_link->fec.kobj);
+		return rtn;
+	}
+
+	rtn = sl_sysfs_link_fec_up_create(ctrl_link);
+	if (rtn) {
+		sl_log_err(ctrl_link, LOG_BLOCK, LOG_NAME,
+			   "link fec up create kobject_init_and_add failed [%d]", rtn);
+		sl_sysfs_link_fec_current_delete(core_link);
+		sl_sysfs_link_fec_mon_check_delete(ctrl_link);
+		sl_sysfs_link_fec_up_check_delete(core_link);
+		kobject_put(&ctrl_link->fec.kobj);
+		return rtn;
+	}
+
+	rtn = sl_sysfs_link_fec_down_create(ctrl_link);
+	if (rtn) {
+		sl_log_err(ctrl_link, LOG_BLOCK, LOG_NAME,
+			   "link fec down create kobject_init_and_add failed [%d]", rtn);
+		sl_sysfs_link_fec_current_delete(core_link);
+		sl_sysfs_link_fec_mon_check_delete(ctrl_link);
+		sl_sysfs_link_fec_up_check_delete(core_link);
+		sl_sysfs_link_fec_up_delete(ctrl_link);
+		kobject_put(&ctrl_link->fec.kobj);
+		return rtn;
+	}
+
+	return 0;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_link_fec_delete(struct sl_ctrl_link *ctrl_link)
+{
+#ifdef CONFIG_SYSFS
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link fec delete (num = %u)", ctrl_link->num);
+
+	core_link = sl_core_link_get(ctrl_link->ctrl_lgrp->ctrl_ldev->num, ctrl_link->ctrl_lgrp->num, ctrl_link->num);
+	if (!core_link)
+		return;
+
+	sl_sysfs_link_fec_current_delete(core_link);
+	sl_sysfs_link_fec_mon_check_delete(ctrl_link);
+	sl_sysfs_link_fec_up_check_delete(core_link);
+	sl_sysfs_link_fec_up_delete(ctrl_link);
+	sl_sysfs_link_fec_down_delete(ctrl_link);
+	kobject_put(&ctrl_link->fec.kobj);
+#endif /* CONFIG_SYSFS */
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_fec_current.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_fec_current.c
new file mode 100644
index 000000000000..30514651d6fe
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_fec_current.c
@@ -0,0 +1,336 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2024-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kobject.h>
+#include <linux/sysfs.h>
+
+#include "sl_log.h"
+#include "sl_core_link.h"
+
+#include "sl_sysfs_link_fec_current.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+#ifdef CONFIG_SYSFS
+static ssize_t ccw_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	u64                  ccw;
+	struct sl_core_link *core_link;
+
+	core_link = container_of(kobj, struct sl_core_link, fec.current_kobj);
+
+	rtn = sl_core_link_fec_ccw_get(core_link, &ccw);
+	if (rtn == -ENOLINK) {
+		sl_log_err_trace(core_link, LOG_BLOCK, LOG_NAME,
+				 "ccw show sl_core_link_fec_ccw_get failed [%d]", rtn);
+		return sysfs_emit(buf, "no-link\n");
+	}
+	if (rtn) {
+		sl_log_err_trace(core_link, LOG_BLOCK, LOG_NAME,
+				 "ccw show sl_core_link_fec_ccw_get failed [%d]", rtn);
+		return sysfs_emit(buf, "io-error\n");
+	}
+
+	sl_log_dbg(core_link, LOG_BLOCK, LOG_NAME, "ccw show (ccw = %llu)", ccw);
+
+	return sysfs_emit(buf, "%llu\n", ccw);
+}
+
+static ssize_t ucw_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	u64                  ucw;
+	struct sl_core_link *core_link;
+
+	core_link = container_of(kobj, struct sl_core_link, fec.current_kobj);
+
+	rtn = sl_core_link_fec_ucw_get(core_link, &ucw);
+	if (rtn == -ENOLINK) {
+		sl_log_err_trace(core_link, LOG_BLOCK, LOG_NAME,
+				 "ucw show sl_core_link_fec_ucw_get failed [%d]", rtn);
+		return sysfs_emit(buf, "no-link\n");
+	}
+	if (rtn) {
+		sl_log_err_trace(core_link, LOG_BLOCK, LOG_NAME,
+				 "ucw show sl_core_link_fec_ucw_get failed [%d]", rtn);
+		return sysfs_emit(buf, "io-error\n");
+	}
+
+	sl_log_dbg(core_link, LOG_BLOCK, LOG_NAME, "ucw show (ucw = %llu)", ucw);
+
+	return sysfs_emit(buf, "%llu\n", ucw);
+}
+
+static ssize_t gcw_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int		     rtn;
+	u64                  gcw;
+	struct sl_core_link *core_link;
+
+	core_link = container_of(kobj, struct sl_core_link, fec.current_kobj);
+
+	rtn = sl_core_link_fec_gcw_get(core_link, &gcw);
+	if (rtn == -ENOLINK) {
+		sl_log_err_trace(core_link, LOG_BLOCK, LOG_NAME,
+				 "gcw show sl_core_link_fec_gcw_get failed [%d]", rtn);
+		return sysfs_emit(buf, "no-link\n");
+	}
+	if (rtn) {
+		sl_log_err_trace(core_link, LOG_BLOCK, LOG_NAME,
+				 "gcw show sl_core_link_fec_gcw_get failed [%d]", rtn);
+		return sysfs_emit(buf, "io-error\n");
+	}
+
+	sl_log_dbg(core_link, LOG_BLOCK, LOG_NAME,
+		   "gcw show (link = 0x%p, gcw = %llu)", core_link, gcw);
+
+	return sysfs_emit(buf, "%llu\n", gcw);
+}
+
+static struct kobj_attribute link_fec_ccw = __ATTR_RO(ccw);
+static struct kobj_attribute link_fec_ucw = __ATTR_RO(ucw);
+static struct kobj_attribute link_fec_gcw = __ATTR_RO(gcw);
+
+static struct attribute *link_fec_current_attrs[] = {
+	&link_fec_ccw.attr,
+	&link_fec_ucw.attr,
+	&link_fec_gcw.attr,
+	NULL
+};
+ATTRIBUTE_GROUPS(link_fec_current);
+
+static struct kobj_type link_fec_current = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = link_fec_current_groups,
+};
+
+static struct attribute *link_fec_current_lane_attrs[] = {
+	NULL
+};
+ATTRIBUTE_GROUPS(link_fec_current_lane);
+
+static struct kobj_type link_fec_current_lane = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = link_fec_current_lane_groups,
+};
+
+static ssize_t link_fec_current_fecl_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf, u8 num)
+{
+	int                            rtn;
+	struct sl_core_link_fecl_kobj *fecl_kobj;
+	struct sl_core_link           *core_link;
+	u8                             fecl_num;
+	u64                            fecl;
+
+	fecl_kobj = container_of(kobj, struct sl_core_link_fecl_kobj, kobj);
+
+	core_link = fecl_kobj->core_link;
+
+	fecl_num = ((4 * fecl_kobj->lane_num) + num);
+
+	rtn = sl_core_link_fec_lane_cntr_get(core_link, fecl_num, &fecl);
+	if (rtn == -ENOLINK) {
+		sl_log_err_trace(core_link, LOG_BLOCK, LOG_NAME,
+				 "current fecl show sl_core_link_fec_lane_cntr_get failed [%d]", rtn);
+		return sysfs_emit(buf, "no-link\n");
+	}
+	if (rtn) {
+		sl_log_err_trace(core_link, LOG_BLOCK, LOG_NAME,
+				 "current fecl show sl_core_link_fec_lane_cntr_get failed [%d]", rtn);
+		return sysfs_emit(buf, "io-error\n");
+	}
+
+	sl_log_dbg(core_link, LOG_BLOCK, LOG_NAME, "current fecl show (num = %u, lane_num = %u, fecl %u = %llu)",
+		   num, fecl_kobj->lane_num, fecl_num, fecl);
+
+	return sysfs_emit(buf, "%llu\n", fecl);
+}
+
+#define link_fec_current_fecl(_num)                                                                            \
+	static inline ssize_t fecl##_num##_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf) \
+	{                                                                                                      \
+		return link_fec_current_fecl_show(kobj, kattr, buf, (_num));                                   \
+	}                                                                                                      \
+	static struct kobj_attribute link_fecl##_num = __ATTR_RO(fecl##_num)
+
+static ssize_t link_fec_current_bin_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf, u8 num)
+{
+	int                  rtn;
+	struct sl_core_link *core_link;
+	u64                  ccw_bin;
+
+	core_link = container_of(kobj, struct sl_core_link, fec.current_tail_kobj);
+
+	rtn = sl_core_link_fec_tail_cntr_get(core_link, num, &ccw_bin);
+	if (rtn == -ENOLINK) {
+		sl_log_err_trace(core_link, LOG_BLOCK, LOG_NAME,
+				 "current bin show sl_core_link_fec_tail_cntr_get failed [%d]", rtn);
+		return sysfs_emit(buf, "no-link\n");
+	}
+	if (rtn) {
+		sl_log_err_trace(core_link, LOG_BLOCK, LOG_NAME,
+				 "current bin show sl_core_link_fec_tail_cntr_get failed [%d]", rtn);
+		return sysfs_emit(buf, "io-error\n");
+	}
+
+	sl_log_dbg(core_link, LOG_BLOCK, LOG_NAME, "current bin show (bin %u = %llu)", num, ccw_bin);
+
+	return sysfs_emit(buf, "%llu\n", ccw_bin);
+}
+
+#define link_fec_current_tail0(_num)                                                                    \
+	static ssize_t bin0##_num##_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf) \
+	{                                                                                               \
+		return link_fec_current_bin_show(kobj, kattr, buf, _num);                               \
+	}                                                                                               \
+	static struct kobj_attribute fec_bin0##_num = __ATTR_RO(bin0##_num)
+
+#define link_fec_current_tail(_num)                                                                           \
+	static inline ssize_t bin##_num##_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf) \
+	{                                                                                                     \
+		return link_fec_current_bin_show(kobj, kattr, buf, (_num));                                   \
+	}                                                                                                     \
+	static struct kobj_attribute fec_bin##_num = __ATTR_RO(bin##_num)
+
+link_fec_current_fecl(0);
+link_fec_current_fecl(1);
+link_fec_current_fecl(2);
+link_fec_current_fecl(3);
+
+static struct attribute *link_fec_current_fecl_attrs[] = {
+	&link_fecl0.attr,
+	&link_fecl1.attr,
+	&link_fecl2.attr,
+	&link_fecl3.attr,
+	NULL
+};
+ATTRIBUTE_GROUPS(link_fec_current_fecl);
+
+static struct kobj_type link_fec_current_fecl = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = link_fec_current_fecl_groups,
+};
+
+link_fec_current_tail0(0);
+link_fec_current_tail0(1);
+link_fec_current_tail0(2);
+link_fec_current_tail0(3);
+link_fec_current_tail0(4);
+link_fec_current_tail0(5);
+link_fec_current_tail0(6);
+link_fec_current_tail0(7);
+link_fec_current_tail0(8);
+link_fec_current_tail0(9);
+link_fec_current_tail(10);
+link_fec_current_tail(11);
+link_fec_current_tail(12);
+link_fec_current_tail(13);
+link_fec_current_tail(14);
+
+static struct attribute *link_fec_current_tail_attrs[] = {
+	&fec_bin00.attr,
+	&fec_bin01.attr,
+	&fec_bin02.attr,
+	&fec_bin03.attr,
+	&fec_bin04.attr,
+	&fec_bin05.attr,
+	&fec_bin06.attr,
+	&fec_bin07.attr,
+	&fec_bin08.attr,
+	&fec_bin09.attr,
+	&fec_bin10.attr,
+	&fec_bin11.attr,
+	&fec_bin12.attr,
+	&fec_bin13.attr,
+	&fec_bin14.attr,
+	NULL
+};
+ATTRIBUTE_GROUPS(link_fec_current_tail);
+
+static struct kobj_type link_fec_current_tail = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = link_fec_current_tail_groups,
+};
+#endif /* CONFIG_SYSFS */
+
+int sl_sysfs_link_fec_current_create(struct sl_core_link *core_link, struct kobject *parent_kobj)
+{
+#ifdef CONFIG_SYSFS
+	int rtn;
+	int x;
+	int out;
+
+	sl_log_dbg(core_link, LOG_BLOCK, LOG_NAME,
+		   "link fec current create (num = %u)", core_link->num);
+
+	rtn = kobject_init_and_add(&core_link->fec.current_kobj, &link_fec_current, parent_kobj, "current");
+	if (rtn) {
+		sl_log_err(core_link, LOG_BLOCK, LOG_NAME,
+			   "link fec current create kobject_init_and_add failed [%d]", rtn);
+		goto out_current;
+	}
+
+	rtn = kobject_init_and_add(&core_link->fec.current_lane_kobj,
+				   &link_fec_current_lane, &core_link->fec.current_kobj, "lane");
+	if (rtn) {
+		sl_log_err(core_link, LOG_BLOCK, LOG_NAME,
+			   "link fec current lane create kobject_init_and_add failed [%d]", rtn);
+		goto out_current_lane;
+	}
+	for (x = 0; x < SL_MAX_LANES; ++x) {
+		rtn = kobject_init_and_add(&core_link->fec.current_fecl_kobjs[x].kobj,
+					   &link_fec_current_fecl, &core_link->fec.current_lane_kobj, "%d", x);
+		if (rtn) {
+			sl_log_err(core_link, LOG_BLOCK, LOG_NAME,
+				   "link fec current fecl create kobject_init_and_add failed [%d]", rtn);
+			goto out_current_fecl;
+		}
+		core_link->fec.current_fecl_kobjs[x].core_link = core_link;
+		core_link->fec.current_fecl_kobjs[x].lane_num = x;
+	}
+
+	rtn = kobject_init_and_add(&core_link->fec.current_tail_kobj,
+				   &link_fec_current_tail, &core_link->fec.current_kobj, "tail");
+	if (rtn) {
+		sl_log_err(core_link, LOG_BLOCK, LOG_NAME,
+			   "link fec current tail create kobject_init_and_add failed [%d]", rtn);
+		goto out_current_tail;
+	}
+
+	return 0;
+
+out_current_tail:
+	kobject_put(&core_link->fec.current_tail_kobj);
+out_current_fecl:
+	if (x < SL_MAX_LANES)
+		kobject_put(&core_link->fec.current_fecl_kobjs[x].kobj);
+	for (out = 0; out < x; ++out)
+		kobject_put(&core_link->fec.current_fecl_kobjs[out].kobj);
+out_current_lane:
+	kobject_put(&core_link->fec.current_lane_kobj);
+out_current:
+	kobject_put(&core_link->fec.current_kobj);
+
+	return rtn;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_link_fec_current_delete(struct sl_core_link *core_link)
+{
+#ifdef CONFIG_SYSFS
+	int x;
+
+	sl_log_dbg(core_link, LOG_BLOCK, LOG_NAME,
+		   "link fec current delete (link_num = %u)", core_link->num);
+
+	kobject_put(&core_link->fec.current_tail_kobj);
+	for (x = 0; x < SL_MAX_LANES; ++x)
+		kobject_put(&core_link->fec.current_fecl_kobjs[x].kobj);
+	kobject_put(&core_link->fec.current_lane_kobj);
+	kobject_put(&core_link->fec.current_kobj);
+#endif /* CONFIG_SYSFS */
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_fec_down.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_fec_down.c
new file mode 100644
index 000000000000..6962b2c678da
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_fec_down.c
@@ -0,0 +1,316 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2024-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kobject.h>
+#include <linux/sysfs.h>
+
+#include "sl_log.h"
+#include "data/sl_ctrl_data_link.h"
+
+#include "sl_sysfs_link_fec_down.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+#ifdef CONFIG_SYSFS
+static ssize_t ccw_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link;
+	u64                  ccw;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, fec.down_kobj);
+
+	rtn = sl_ctrl_data_link_fec_down_cache_ccw_cntr_get(ctrl_link, &ccw);
+	if (rtn) {
+		sl_log_err(ctrl_link, LOG_BLOCK, LOG_NAME,
+			   "ccw show sl_ctrl_data_link_fec_down_cache_ccw_cntr_get failed [%d]", rtn);
+		return sysfs_emit(buf, "error\n");
+	}
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "ccw show (link = 0x%p, ccw = %llu)", ctrl_link, ccw);
+
+	return sysfs_emit(buf, "%llu\n", ccw);
+}
+
+static ssize_t ucw_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link;
+	u64                  ucw;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, fec.down_kobj);
+
+	rtn = sl_ctrl_data_link_fec_down_cache_ucw_cntr_get(ctrl_link, &ucw);
+	if (rtn) {
+		sl_log_err(ctrl_link, LOG_BLOCK, LOG_NAME,
+			   "ucw show sl_ctrl_data_link_fec_down_cache_ucw_cntr_get failed [%d]", rtn);
+		return sysfs_emit(buf, "error\n");
+	}
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "ucw show (link = 0x%p, ucw = %llu)", ctrl_link, ucw);
+
+	return sysfs_emit(buf, "%llu\n", ucw);
+}
+
+static ssize_t gcw_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link;
+	u64                  gcw;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, fec.down_kobj);
+
+	rtn = sl_ctrl_data_link_fec_down_cache_gcw_cntr_get(ctrl_link, &gcw);
+	if (rtn) {
+		sl_log_err(ctrl_link, LOG_BLOCK, LOG_NAME,
+			   "gcw show sl_ctrl_data_link_fec_down_cache_gcw_cntr_get failed [%d]", rtn);
+		return sysfs_emit(buf, "error\n");
+	}
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "gcw show (link = 0x%p, gcw = %llu)", ctrl_link, gcw);
+
+	return sysfs_emit(buf, "%llu\n", gcw);
+}
+
+static struct kobj_attribute link_fec_ccw = __ATTR_RO(ccw);
+static struct kobj_attribute link_fec_ucw = __ATTR_RO(ucw);
+static struct kobj_attribute link_fec_gcw = __ATTR_RO(gcw);
+
+static struct attribute *link_fec_down_attrs[] = {
+	&link_fec_ccw.attr,
+	&link_fec_ucw.attr,
+	&link_fec_gcw.attr,
+	NULL
+};
+ATTRIBUTE_GROUPS(link_fec_down);
+
+static struct kobj_type link_fec_down = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = link_fec_down_groups,
+};
+
+static struct attribute *link_fec_down_lane_attrs[] = {
+	NULL
+};
+ATTRIBUTE_GROUPS(link_fec_down_lane);
+
+static struct kobj_type link_fec_down_lane = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = link_fec_down_lane_groups,
+};
+
+static ssize_t link_fec_down_fecl_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf, u8 num)
+{
+	int                            rtn;
+	struct sl_ctrl_link           *ctrl_link;
+	struct sl_ctrl_link_fecl_kobj *fecl_kobj;
+	u8                             fecl_num;
+	u64                            lane_cntr;
+
+	fecl_kobj = container_of(kobj, struct sl_ctrl_link_fecl_kobj, kobj);
+	ctrl_link = fecl_kobj->ctrl_link;
+
+	fecl_num = ((4 * fecl_kobj->lane_num) + num);
+
+	rtn = sl_ctrl_data_link_fec_down_cache_lane_cntr_get(ctrl_link, fecl_num, &lane_cntr);
+	if (rtn) {
+		sl_log_err(ctrl_link, LOG_BLOCK, LOG_NAME,
+			   "current fecl show sl_ctrl_data_link_fec_down_cache_lane_cntr_get failed [%d]", rtn);
+		return sysfs_emit(buf, "error\n");
+	}
+
+	sl_log_dbg(fecl_kobj->ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "current fecl show (link = 0x%p, num = %u, lane_num = %u, fecl %u = %llu)",
+		ctrl_link, num, fecl_kobj->lane_num, fecl_num, lane_cntr);
+
+	return sysfs_emit(buf, "%llu\n", lane_cntr);
+}
+
+#define link_fec_down_fecl(_num)                                                                               \
+	static inline ssize_t fecl##_num##_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf) \
+	{                                                                                                      \
+		return link_fec_down_fecl_show(kobj, kattr, buf, (_num));                                      \
+	}                                                                                                      \
+	static struct kobj_attribute link_fecl##_num = __ATTR_RO(fecl##_num)
+
+static ssize_t link_fec_down_bin_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf, u8 num)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link;
+	u64                  tail_cntr;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, fec.down_tail_kobj);
+
+	rtn = sl_ctrl_data_link_fec_down_cache_tail_cntr_get(ctrl_link, num, &tail_cntr);
+	if (rtn) {
+		sl_log_err(ctrl_link, LOG_BLOCK, LOG_NAME,
+			   "down bin show sl_ctrl_data_link_fec_down_cache_tail_cntr_get failed [%d]", rtn);
+		return sysfs_emit(buf, "error\n");
+	}
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "down bin show (link = 0x%p, bin %u = %llu)",
+		ctrl_link, num, tail_cntr);
+
+	return sysfs_emit(buf, "%llu\n", tail_cntr);
+}
+
+#define link_fec_down_tail0(_num)                                                                       \
+	static ssize_t bin0##_num##_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf) \
+	{                                                                                               \
+		return link_fec_down_bin_show(kobj, kattr, buf, _num);                                  \
+	}                                                                                               \
+	static struct kobj_attribute fec_bin0##_num = __ATTR_RO(bin0##_num)
+
+#define link_fec_down_tail(_num)                                                                              \
+	static inline ssize_t bin##_num##_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf) \
+	{                                                                                                     \
+		return link_fec_down_bin_show(kobj, kattr, buf, (_num));                                      \
+	}                                                                                                     \
+	static struct kobj_attribute fec_bin##_num = __ATTR_RO(bin##_num)
+
+link_fec_down_fecl(0);
+link_fec_down_fecl(1);
+link_fec_down_fecl(2);
+link_fec_down_fecl(3);
+
+static struct attribute *link_fec_down_fecl_attrs[] = {
+	&link_fecl0.attr,
+	&link_fecl1.attr,
+	&link_fecl2.attr,
+	&link_fecl3.attr,
+	NULL
+};
+ATTRIBUTE_GROUPS(link_fec_down_fecl);
+
+static struct kobj_type link_fec_down_fecl = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = link_fec_down_fecl_groups,
+};
+
+link_fec_down_tail0(0);
+link_fec_down_tail0(1);
+link_fec_down_tail0(2);
+link_fec_down_tail0(3);
+link_fec_down_tail0(4);
+link_fec_down_tail0(5);
+link_fec_down_tail0(6);
+link_fec_down_tail0(7);
+link_fec_down_tail0(8);
+link_fec_down_tail0(9);
+link_fec_down_tail(10);
+link_fec_down_tail(11);
+link_fec_down_tail(12);
+link_fec_down_tail(13);
+link_fec_down_tail(14);
+
+static struct attribute *link_fec_down_tail_attrs[] = {
+	&fec_bin00.attr,
+	&fec_bin01.attr,
+	&fec_bin02.attr,
+	&fec_bin03.attr,
+	&fec_bin04.attr,
+	&fec_bin05.attr,
+	&fec_bin06.attr,
+	&fec_bin07.attr,
+	&fec_bin08.attr,
+	&fec_bin09.attr,
+	&fec_bin10.attr,
+	&fec_bin11.attr,
+	&fec_bin12.attr,
+	&fec_bin13.attr,
+	&fec_bin14.attr,
+	NULL
+};
+ATTRIBUTE_GROUPS(link_fec_down_tail);
+
+static struct kobj_type link_fec_down_tail = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = link_fec_down_tail_groups,
+};
+#endif /* CONFIG_SYSFS */
+
+int sl_sysfs_link_fec_down_create(struct sl_ctrl_link *ctrl_link)
+{
+#ifdef CONFIG_SYSFS
+	int rtn;
+	int x;
+	int out;
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "link fec down create (num = %u)", ctrl_link->num);
+
+	rtn = kobject_init_and_add(&ctrl_link->fec.down_kobj, &link_fec_down,
+				   &ctrl_link->fec.kobj, "down");
+	if (rtn) {
+		sl_log_err(ctrl_link, LOG_BLOCK, LOG_NAME,
+			   "link fec down create kobject_init_and_add failed [%d]", rtn);
+		goto out_down;
+	}
+
+	rtn = kobject_init_and_add(&ctrl_link->fec.down_lane_kobj,
+				   &link_fec_down_lane, &ctrl_link->fec.down_kobj, "lane");
+	if (rtn) {
+		sl_log_err(ctrl_link, LOG_BLOCK, LOG_NAME,
+			   "link fec down lane create kobject_init_and_add failed [%d]", rtn);
+		goto out_down_lane;
+	}
+	for (x = 0; x < SL_MAX_LANES; ++x) {
+		rtn = kobject_init_and_add(&ctrl_link->fec.down_fecl_kobjs[x].kobj,
+					   &link_fec_down_fecl, &ctrl_link->fec.down_lane_kobj, "%d", x);
+		if (rtn) {
+			sl_log_err(ctrl_link, LOG_BLOCK, LOG_NAME,
+				   "link fec down fecl create kobject_init_and_add failed [%d]", rtn);
+			goto out_down_fecl;
+		}
+		ctrl_link->fec.down_fecl_kobjs[x].ctrl_link = ctrl_link;
+		ctrl_link->fec.down_fecl_kobjs[x].lane_num = x;
+	}
+
+	rtn = kobject_init_and_add(&ctrl_link->fec.down_tail_kobj,
+				   &link_fec_down_tail, &ctrl_link->fec.down_kobj, "tail");
+	if (rtn) {
+		sl_log_err(ctrl_link, LOG_BLOCK, LOG_NAME,
+			   "link fec down tail create kobject_init_and_add failed [%d]", rtn);
+		goto out_down_tail;
+	}
+
+	return 0;
+
+out_down_tail:
+	kobject_put(&ctrl_link->fec.down_tail_kobj);
+out_down_fecl:
+	if (x < SL_MAX_LANES)
+		kobject_put(&ctrl_link->fec.down_fecl_kobjs[x].kobj);
+	for (out = 0; out < x; ++out)
+		kobject_put(&ctrl_link->fec.down_fecl_kobjs[out].kobj);
+out_down_lane:
+	kobject_put(&ctrl_link->fec.down_lane_kobj);
+out_down:
+	kobject_put(&ctrl_link->fec.down_kobj);
+
+	return rtn;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_link_fec_down_delete(struct sl_ctrl_link *ctrl_link)
+{
+#ifdef CONFIG_SYSFS
+	int x;
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "link fec down delete (link_num = %u)", ctrl_link->num);
+
+	kobject_put(&ctrl_link->fec.down_tail_kobj);
+	for (x = 0; x < SL_MAX_LANES; ++x)
+		kobject_put(&ctrl_link->fec.down_fecl_kobjs[x].kobj);
+	kobject_put(&ctrl_link->fec.down_lane_kobj);
+	kobject_put(&ctrl_link->fec.down_kobj);
+#endif /* CONFIG_SYSFS */
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_fec_mon_check.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_fec_mon_check.c
new file mode 100644
index 000000000000..f989399518fc
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_fec_mon_check.c
@@ -0,0 +1,195 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2024-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kobject.h>
+#include <linux/sysfs.h>
+
+#include "sl_log.h"
+#include "data/sl_ctrl_data_link.h"
+
+#include "sl_sysfs_link_fec_mon_check.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+#ifdef CONFIG_SYSFS
+static ssize_t ucw_down_limit_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link;
+	s32                  ucw_down_limit;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, fec.mon_check_kobj);
+
+	rtn = sl_ctrl_data_link_fec_mon_ucw_down_limit_get(ctrl_link, &ucw_down_limit);
+	if (rtn == -EBADRQC) {
+		sl_log_warn_trace(ctrl_link, LOG_BLOCK, LOG_NAME,
+				  "ucw down limit show monitoring not enabled");
+		return sysfs_emit(buf, "not-monitoring\n");
+	}
+	if (rtn) {
+		sl_log_err_trace(ctrl_link, LOG_BLOCK, LOG_NAME, "fec_mon_ucw_down_limit_get failed [%d]", rtn);
+		return sysfs_emit(buf, "error\n");
+	}
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "ucw down limit show (ucw_down_limit = %d)", ucw_down_limit);
+
+	if (ucw_down_limit == -1)
+		return sysfs_emit(buf, "calculated\n");
+
+	return sysfs_emit(buf, "%d\n", ucw_down_limit);
+}
+
+static ssize_t ucw_warn_limit_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link;
+	s32                  ucw_warn_limit;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, fec.mon_check_kobj);
+
+	rtn = sl_ctrl_data_link_fec_mon_ucw_warn_limit_get(ctrl_link, &ucw_warn_limit);
+	if (rtn == -EBADRQC) {
+		sl_log_warn_trace(ctrl_link, LOG_BLOCK, LOG_NAME,
+				  "ucw warn limit show monitoring not enabled");
+		return sysfs_emit(buf, "not-monitoring\n");
+	}
+	if (rtn) {
+		sl_log_err_trace(ctrl_link, LOG_BLOCK, LOG_NAME, "fec_mon_ucw_warn_limit_get failed [%d]", rtn);
+		return sysfs_emit(buf, "error\n");
+	}
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "ucw warn limit show (ucw_warn_limit = %d)", ucw_warn_limit);
+
+	if (ucw_warn_limit == -1)
+		return sysfs_emit(buf, "calculated\n");
+
+	return sysfs_emit(buf, "%d\n", ucw_warn_limit);
+}
+
+static ssize_t ccw_down_limit_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_link *ctrl_link;
+	s32                  ccw_down_limit;
+	int                  rtn;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, fec.mon_check_kobj);
+
+	rtn = sl_ctrl_data_link_fec_mon_ccw_down_limit_get(ctrl_link, &ccw_down_limit);
+	if (rtn == -EBADRQC) {
+		sl_log_warn_trace(ctrl_link, LOG_BLOCK, LOG_NAME,
+				  "ccw down limit show monitoring not enabled");
+		return sysfs_emit(buf, "not-monitoring\n");
+	}
+	if (rtn) {
+		sl_log_err_trace(ctrl_link, LOG_BLOCK, LOG_NAME, "fec_mon_ccw_down_limit_get failed [%d]", rtn);
+		return sysfs_emit(buf, "error\n");
+	}
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "fec_mon_ccw_down_limit show (ccw_down_limit = %d)", ccw_down_limit);
+
+	if (ccw_down_limit == -1)
+		return sysfs_emit(buf, "calculated\n");
+
+	return sysfs_emit(buf, "%d\n", ccw_down_limit);
+}
+
+static ssize_t ccw_warn_limit_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link;
+	s32                  ccw_warn_limit;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, fec.mon_check_kobj);
+
+	rtn = sl_ctrl_data_link_fec_mon_ccw_warn_limit_get(ctrl_link, &ccw_warn_limit);
+	if (rtn == -EBADRQC) {
+		sl_log_warn_trace(ctrl_link, LOG_BLOCK, LOG_NAME,
+				  "ccw warn limit show monitoring not enabled");
+		return sysfs_emit(buf, "not-monitoring\n");
+	}
+	if (rtn) {
+		sl_log_err_trace(ctrl_link, LOG_BLOCK, LOG_NAME, "fec_mon_ccw_warn_limit_get failed [%d]", rtn);
+		return sysfs_emit(buf, "error\n");
+	}
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "fec_mon_ccw_warn_limit show (ccw_warn_limit = %d)", ccw_warn_limit);
+
+	if (ccw_warn_limit == -1)
+		return sysfs_emit(buf, "calculated\n");
+
+	return sysfs_emit(buf, "%d\n", ccw_warn_limit);
+}
+
+static ssize_t period_ms_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link;
+	s32                  period_ms;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, fec.mon_check_kobj);
+
+	rtn = sl_ctrl_data_link_fec_mon_period_ms_get(ctrl_link, &period_ms);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "fec_mon_period_ms_show show (period_ms = %u)", period_ms);
+
+	return sysfs_emit(buf, "%u\n", period_ms);
+}
+
+static struct kobj_attribute ucw_down_limit = __ATTR_RO(ucw_down_limit);
+static struct kobj_attribute ucw_warn_limit = __ATTR_RO(ucw_warn_limit);
+static struct kobj_attribute ccw_down_limit = __ATTR_RO(ccw_down_limit);
+static struct kobj_attribute ccw_warn_limit = __ATTR_RO(ccw_warn_limit);
+static struct kobj_attribute period_ms      = __ATTR_RO(period_ms);
+
+static struct attribute *link_fec_mon_check_attrs[] = {
+	&ucw_down_limit.attr,
+	&ucw_warn_limit.attr,
+	&ccw_down_limit.attr,
+	&ccw_warn_limit.attr,
+	&period_ms.attr,
+	NULL
+};
+ATTRIBUTE_GROUPS(link_fec_mon_check);
+
+static struct kobj_type link_fec_mon_check = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = link_fec_mon_check_groups,
+};
+#endif /* CONFIG_SYSFS */
+
+int sl_sysfs_link_fec_mon_check_create(struct sl_ctrl_link *ctrl_link)
+{
+#ifdef CONFIG_SYSFS
+	int rtn;
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link fec mon check create (num = %u)", ctrl_link->num);
+
+	rtn = kobject_init_and_add(&ctrl_link->fec.mon_check_kobj, &link_fec_mon_check,
+				   &ctrl_link->fec.kobj, "monitor_check");
+	if (rtn) {
+		sl_log_err(ctrl_link, LOG_BLOCK, LOG_NAME,
+			   "link monitor check create kobject_init_and_add failed [%d]", rtn);
+		kobject_put(&ctrl_link->fec.mon_check_kobj);
+		return rtn;
+	}
+
+	return 0;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_link_fec_mon_check_delete(struct sl_ctrl_link *ctrl_link)
+{
+#ifdef CONFIG_SYSFS
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link fec mon check delete (num = %u)", ctrl_link->num);
+
+	kobject_put(&ctrl_link->fec.mon_check_kobj);
+#endif /* CONFIG_SYSFS */
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_fec_up.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_fec_up.c
new file mode 100644
index 000000000000..ecf92c043e01
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_fec_up.c
@@ -0,0 +1,299 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2024-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kobject.h>
+#include <linux/sysfs.h>
+
+#include "sl_log.h"
+#include "data/sl_ctrl_data_link.h"
+
+#include "sl_sysfs_link_fec_up.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+#ifdef CONFIG_SYSFS
+static ssize_t ccw_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link;
+	u64                  ccw;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, fec.up_kobj);
+
+	rtn = sl_ctrl_data_link_fec_up_cache_ccw_cntr_get(ctrl_link, &ccw);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "ccw show (ccw = %llu)", ccw);
+
+	return sysfs_emit(buf, "%llu\n", ccw);
+}
+
+static ssize_t ucw_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link;
+	u64                  ucw;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, fec.up_kobj);
+
+	rtn = sl_ctrl_data_link_fec_up_cache_ucw_cntr_get(ctrl_link, &ucw);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "ucw show (ucw = %llu)", ucw);
+
+	return sysfs_emit(buf, "%llu\n", ucw);
+}
+
+static ssize_t gcw_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link;
+	u64                  gcw;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, fec.up_kobj);
+
+	rtn = sl_ctrl_data_link_fec_up_cache_gcw_cntr_get(ctrl_link, &gcw);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "gcw show (link = 0x%p, gcw = %llu)", ctrl_link, gcw);
+
+	return sysfs_emit(buf, "%llu\n", gcw);
+}
+
+static struct kobj_attribute link_fec_ccw = __ATTR_RO(ccw);
+static struct kobj_attribute link_fec_ucw = __ATTR_RO(ucw);
+static struct kobj_attribute link_fec_gcw = __ATTR_RO(gcw);
+
+static struct attribute *link_fec_up_attrs[] = {
+	&link_fec_ccw.attr,
+	&link_fec_ucw.attr,
+	&link_fec_gcw.attr,
+	NULL
+};
+ATTRIBUTE_GROUPS(link_fec_up);
+
+static struct kobj_type link_fec_up = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = link_fec_up_groups,
+};
+
+static struct attribute *link_fec_up_lane_attrs[] = {
+	NULL
+};
+ATTRIBUTE_GROUPS(link_fec_up_lane);
+
+static struct kobj_type link_fec_up_lane = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = link_fec_up_lane_groups,
+};
+
+static ssize_t link_fec_up_fecl_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf, u8 num)
+{
+	int                            rtn;
+	struct sl_ctrl_link           *ctrl_link;
+	struct sl_ctrl_link_fecl_kobj *fecl_kobj;
+	u8                             fecl_num;
+	u64                            fecl;
+
+	fecl_kobj = container_of(kobj, struct sl_ctrl_link_fecl_kobj, kobj);
+	ctrl_link = fecl_kobj->ctrl_link;
+
+	fecl_num = ((4 * fecl_kobj->lane_num) + num);
+
+	rtn = sl_ctrl_data_link_fec_up_cache_lane_cntr_get(ctrl_link, fecl_num, &fecl);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(fecl_kobj->ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "current fecl show (link = 0x%p, num = %u, lane_num = %u, fecl %u = %llu)",
+		fecl_kobj->ctrl_link, num, fecl_kobj->lane_num, fecl_num, fecl);
+
+	return sysfs_emit(buf, "%llu\n", fecl);
+}
+
+#define link_fec_up_fecl(_num)                                                                                 \
+	static inline ssize_t fecl##_num##_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf) \
+	{                                                                                                      \
+		return link_fec_up_fecl_show(kobj, kattr, buf, (_num));                                        \
+	}                                                                                                      \
+	static struct kobj_attribute link_fecl##_num = __ATTR_RO(fecl##_num)
+
+static ssize_t link_fec_up_bin_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf, u8 num)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link;
+	u64                 tail_cntr;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, fec.up_tail_kobj);
+
+	rtn = sl_ctrl_data_link_fec_up_cache_tail_cntr_get(ctrl_link, num, &tail_cntr);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "up bin show (link = 0x%p, bin %u = %llu)",
+		ctrl_link, num, tail_cntr);
+
+	return sysfs_emit(buf, "%llu\n", tail_cntr);
+}
+
+#define link_fec_up_tail0(_num)                                                                         \
+	static ssize_t bin0##_num##_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf) \
+	{                                                                                               \
+		return link_fec_up_bin_show(kobj, kattr, buf, _num);                                    \
+	}                                                                                               \
+	static struct kobj_attribute fec_bin0##_num = __ATTR_RO(bin0##_num)
+
+#define link_fec_up_tail(_num)                                                                                \
+	static inline ssize_t bin##_num##_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf) \
+	{                                                                                                     \
+		return link_fec_up_bin_show(kobj, kattr, buf, (_num));                                        \
+	}                                                                                                     \
+	static struct kobj_attribute fec_bin##_num = __ATTR_RO(bin##_num)
+
+link_fec_up_fecl(0);
+link_fec_up_fecl(1);
+link_fec_up_fecl(2);
+link_fec_up_fecl(3);
+
+static struct attribute *link_fec_up_fecl_attrs[] = {
+	&link_fecl0.attr,
+	&link_fecl1.attr,
+	&link_fecl2.attr,
+	&link_fecl3.attr,
+	NULL
+};
+ATTRIBUTE_GROUPS(link_fec_up_fecl);
+
+static struct kobj_type link_fec_up_fecl = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = link_fec_up_fecl_groups,
+};
+
+link_fec_up_tail0(0);
+link_fec_up_tail0(1);
+link_fec_up_tail0(2);
+link_fec_up_tail0(3);
+link_fec_up_tail0(4);
+link_fec_up_tail0(5);
+link_fec_up_tail0(6);
+link_fec_up_tail0(7);
+link_fec_up_tail0(8);
+link_fec_up_tail0(9);
+link_fec_up_tail(10);
+link_fec_up_tail(11);
+link_fec_up_tail(12);
+link_fec_up_tail(13);
+link_fec_up_tail(14);
+
+static struct attribute *link_fec_up_tail_attrs[] = {
+	&fec_bin00.attr,
+	&fec_bin01.attr,
+	&fec_bin02.attr,
+	&fec_bin03.attr,
+	&fec_bin04.attr,
+	&fec_bin05.attr,
+	&fec_bin06.attr,
+	&fec_bin07.attr,
+	&fec_bin08.attr,
+	&fec_bin09.attr,
+	&fec_bin10.attr,
+	&fec_bin11.attr,
+	&fec_bin12.attr,
+	&fec_bin13.attr,
+	&fec_bin14.attr,
+	NULL
+};
+ATTRIBUTE_GROUPS(link_fec_up_tail);
+
+static struct kobj_type link_fec_up_tail = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = link_fec_up_tail_groups,
+};
+#endif /* CONFIG_SYSFS */
+
+int sl_sysfs_link_fec_up_create(struct sl_ctrl_link *ctrl_link)
+{
+#ifdef CONFIG_SYSFS
+	int rtn;
+	int x;
+	int out;
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "link fec up create (num = %u)", ctrl_link->num);
+
+	rtn = kobject_init_and_add(&ctrl_link->fec.up_kobj, &link_fec_up,
+				   &ctrl_link->fec.kobj, "up");
+	if (rtn) {
+		sl_log_err(ctrl_link, LOG_BLOCK, LOG_NAME,
+			   "link fec up create kobject_init_and_add failed [%d]", rtn);
+		goto out_up;
+	}
+
+	rtn = kobject_init_and_add(&ctrl_link->fec.up_lane_kobj,
+				   &link_fec_up_lane, &ctrl_link->fec.up_kobj, "lane");
+	if (rtn) {
+		sl_log_err(ctrl_link, LOG_BLOCK, LOG_NAME,
+			   "link fec up lane create kobject_init_and_add failed [%d]", rtn);
+		goto out_up_lane;
+	}
+	for (x = 0; x < SL_MAX_LANES; ++x) {
+		rtn = kobject_init_and_add(&ctrl_link->fec.up_fecl_kobjs[x].kobj,
+					   &link_fec_up_fecl, &ctrl_link->fec.up_lane_kobj, "%d", x);
+		if (rtn) {
+			sl_log_err(ctrl_link, LOG_BLOCK, LOG_NAME,
+				   "link fec up fecl create kobject_init_and_add failed [%d]", rtn);
+			goto out_up_fecl;
+		}
+		ctrl_link->fec.up_fecl_kobjs[x].ctrl_link = ctrl_link;
+		ctrl_link->fec.up_fecl_kobjs[x].lane_num = x;
+	}
+
+	rtn = kobject_init_and_add(&ctrl_link->fec.up_tail_kobj,
+				   &link_fec_up_tail, &ctrl_link->fec.up_kobj, "tail");
+	if (rtn) {
+		sl_log_err(ctrl_link, LOG_BLOCK, LOG_NAME,
+			   "link fec up tail create kobject_init_and_add failed [%d]", rtn);
+		goto out_up_tail;
+	}
+
+	return 0;
+
+out_up_tail:
+	kobject_put(&ctrl_link->fec.up_tail_kobj);
+out_up_fecl:
+	if (x < SL_MAX_LANES)
+		kobject_put(&ctrl_link->fec.up_fecl_kobjs[x].kobj);
+	for (out = 0; out < x; ++out)
+		kobject_put(&ctrl_link->fec.up_fecl_kobjs[out].kobj);
+out_up_lane:
+	kobject_put(&ctrl_link->fec.up_lane_kobj);
+out_up:
+	kobject_put(&ctrl_link->fec.up_kobj);
+
+	return rtn;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_link_fec_up_delete(struct sl_ctrl_link *ctrl_link)
+{
+#ifdef CONFIG_SYSFS
+	int x;
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "link fec up delete (link_num = %u)", ctrl_link->num);
+
+	kobject_put(&ctrl_link->fec.up_tail_kobj);
+	for (x = 0; x < SL_MAX_LANES; ++x)
+		kobject_put(&ctrl_link->fec.up_fecl_kobjs[x].kobj);
+	kobject_put(&ctrl_link->fec.up_lane_kobj);
+	kobject_put(&ctrl_link->fec.up_kobj);
+#endif /* CONFIG_SYSFS */
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_fec_up_check.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_fec_up_check.c
new file mode 100644
index 000000000000..763dde6ca217
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_fec_up_check.c
@@ -0,0 +1,137 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2025-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kobject.h>
+#include <linux/sysfs.h>
+
+#include "sl_log.h"
+#include "sl_core_link.h"
+#include "data/sl_core_data_link.h"
+
+#include "sl_sysfs_link_fec_up_check.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+#ifdef CONFIG_SYSFS
+static ssize_t ucw_limit_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_core_link *core_link;
+	s32                  ucw_limit;
+
+	core_link = container_of(kobj, struct sl_core_link, fec.up_check_kobj);
+
+	rtn = sl_core_data_link_fec_up_ucw_limit_get(core_link, &ucw_limit);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_link, LOG_BLOCK, LOG_NAME,
+		   "fec_up_ucw_limit show (ucw_limit = %d)", ucw_limit);
+
+	return sysfs_emit(buf, "%d\n", ucw_limit);
+}
+
+static ssize_t ccw_limit_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_core_link *core_link;
+	s32                  ccw_limit;
+
+	core_link = container_of(kobj, struct sl_core_link, fec.up_check_kobj);
+
+	rtn = sl_core_data_link_fec_up_ccw_limit_get(core_link, &ccw_limit);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_link, LOG_BLOCK, LOG_NAME,
+		   "fec_up_ccw_limit show (ccw_limit = %d)", ccw_limit);
+
+	return sysfs_emit(buf, "%d\n", ccw_limit);
+}
+
+static ssize_t settle_wait_ms_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_core_link *core_link;
+	u32                  settle_wait_ms;
+
+	core_link = container_of(kobj, struct sl_core_link, fec.up_check_kobj);
+
+	rtn = sl_core_data_link_fec_up_settle_wait_ms_get(core_link, &settle_wait_ms);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_link, LOG_BLOCK, LOG_NAME,
+		   "settle_wait_ms show (settle_wait_ms = %u)", settle_wait_ms);
+
+	return sysfs_emit(buf, "%u\n", settle_wait_ms);
+}
+
+static ssize_t check_wait_ms_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_core_link *core_link;
+	u32                  check_wait_ms;
+
+	core_link = container_of(kobj, struct sl_core_link, fec.up_check_kobj);
+
+	rtn = sl_core_data_link_fec_up_check_wait_ms_get(core_link, &check_wait_ms);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_link, LOG_BLOCK, LOG_NAME,
+		   "check_wait_ms show (check_wait_ms = %u)", check_wait_ms);
+
+	return sysfs_emit(buf, "%u\n", check_wait_ms);
+}
+
+static struct kobj_attribute ucw_limit      = __ATTR_RO(ucw_limit);
+static struct kobj_attribute ccw_limit      = __ATTR_RO(ccw_limit);
+static struct kobj_attribute settle_wait_ms = __ATTR_RO(settle_wait_ms);
+static struct kobj_attribute check_wait_ms  = __ATTR_RO(check_wait_ms);
+
+static struct attribute *link_fec_up_check_attrs[] = {
+	&ucw_limit.attr,
+	&ccw_limit.attr,
+	&settle_wait_ms.attr,
+	&check_wait_ms.attr,
+	NULL
+};
+ATTRIBUTE_GROUPS(link_fec_up_check);
+
+static struct kobj_type link_fec_up_check = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = link_fec_up_check_groups,
+};
+#endif /* CONFIG_SYSFS */
+
+int sl_sysfs_link_fec_up_check_create(struct sl_core_link *core_link, struct kobject *parent_kobj)
+{
+#ifdef CONFIG_SYSFS
+	int rtn;
+
+	sl_log_dbg(core_link, LOG_BLOCK, LOG_NAME, "link fec up check create (num = %u)", core_link->num);
+
+	rtn = kobject_init_and_add(&core_link->fec.up_check_kobj, &link_fec_up_check, parent_kobj, "up_check");
+	if (rtn) {
+		sl_log_err(core_link, LOG_BLOCK, LOG_NAME,
+			   "link up_check create kobject_init_and_add failed [%d]", rtn);
+		kobject_put(&core_link->fec.up_check_kobj);
+		return rtn;
+	}
+
+	return 0;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_link_fec_up_check_delete(struct sl_core_link *core_link)
+{
+#ifdef CONFIG_SYSFS
+	sl_log_dbg(core_link, LOG_BLOCK, LOG_NAME, "link fec up check delete (num = %u)", core_link->num);
+
+	kobject_put(&core_link->fec.up_check_kobj);
+#endif /* CONFIG_SYSFS */
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_pml_rec.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_pml_rec.c
new file mode 100644
index 000000000000..dc076274157d
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_pml_rec.c
@@ -0,0 +1,193 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kobject.h>
+#include <linux/sysfs.h>
+#include <linux/types.h>
+
+#include "sl_log.h"
+#include "data/sl_core_data_link.h"
+
+#include "sl_sysfs.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+#ifdef CONFIG_SYSFS
+static ssize_t pml_rec_attempts_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_core_link *core_link;
+	int                  attempts;
+	int		     rtn;
+
+	core_link = container_of(kobj, struct sl_core_link, pml_rec_kobj);
+
+	rtn = sl_core_data_link_pml_rec_attempts_get(core_link, &attempts);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_link, LOG_BLOCK, LOG_NAME, "pml rec attempts show (attempts = %d)", attempts);
+
+	return sysfs_emit(buf, "%d\n", attempts);
+}
+
+static ssize_t pml_rec_successes_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_core_link *core_link;
+	int                  successes;
+	int		     rtn;
+
+	core_link = container_of(kobj, struct sl_core_link, pml_rec_kobj);
+
+	rtn = sl_core_data_link_pml_rec_successes_get(core_link, &successes);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_link, LOG_BLOCK, LOG_NAME, "pml rec successes show (successes = %d)", successes);
+
+	return sysfs_emit(buf, "%d\n", successes);
+}
+
+static ssize_t pml_rec_link_fault_cause_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_core_link *core_link;
+	int                  link_fault_cause;
+	int		     rtn;
+
+	core_link = container_of(kobj, struct sl_core_link, pml_rec_kobj);
+
+	rtn = sl_core_data_link_pml_rec_link_fault_cause_get(core_link, &link_fault_cause);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_link, LOG_BLOCK, LOG_NAME, "pml rec link_fault_cause show (link_fault_cause = %d)", link_fault_cause);
+
+	return sysfs_emit(buf, "%d\n", link_fault_cause);
+}
+
+static ssize_t pml_rec_link_down_cause_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_core_link *core_link;
+	int                  link_down_cause;
+	int		     rtn;
+
+	core_link = container_of(kobj, struct sl_core_link, pml_rec_kobj);
+
+	rtn = sl_core_data_link_pml_rec_link_down_cause_get(core_link, &link_down_cause);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_link, LOG_BLOCK, LOG_NAME, "pml rec link_down_cause show (link_down_cause = %d)", link_down_cause);
+
+	return sysfs_emit(buf, "%d\n", link_down_cause);
+}
+
+static ssize_t pml_rec_link_fault_failed_cause_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_core_link *core_link;
+	int                  link_fault_failed_cause;
+	int		     rtn;
+
+	core_link = container_of(kobj, struct sl_core_link, pml_rec_kobj);
+
+	rtn = sl_core_data_link_pml_rec_link_fault_failed_cause_get(core_link, &link_fault_failed_cause);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_link, LOG_BLOCK, LOG_NAME, "pml rec link_fault_failed_cause show (link_fault_failed_cause = %d)",
+		   link_fault_failed_cause);
+
+	return sysfs_emit(buf, "%d\n", link_fault_failed_cause);
+}
+
+static ssize_t pml_rec_link_down_failed_cause_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_core_link *core_link;
+	int                  link_down_failed_cause;
+	int		     rtn;
+
+	core_link = container_of(kobj, struct sl_core_link, pml_rec_kobj);
+
+	rtn = sl_core_data_link_pml_rec_link_down_failed_cause_get(core_link, &link_down_failed_cause);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_link, LOG_BLOCK, LOG_NAME, "pml rec link_down_cause show (link_down_failed_cause = %d)",
+		   link_down_failed_cause);
+
+	return sysfs_emit(buf, "%d\n", link_down_failed_cause);
+}
+
+static ssize_t pml_rec_rate_limit_exceeded_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_core_link *core_link;
+	int                  rate_limit_exceeded;
+	int		     rtn;
+
+	core_link = container_of(kobj, struct sl_core_link, pml_rec_kobj);
+
+	rtn = sl_core_data_link_pml_rec_rate_limit_exceeded_get(core_link, &rate_limit_exceeded);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_link, LOG_BLOCK, LOG_NAME, "pml rec rate_limit_exceeded show (rate_limit_exceeded = %d)",
+		   rate_limit_exceeded);
+
+	return sysfs_emit(buf, "%d\n", rate_limit_exceeded);
+}
+
+static struct kobj_attribute link_pml_rec_attempts                = __ATTR_RO(pml_rec_attempts);
+static struct kobj_attribute link_pml_rec_successes               = __ATTR_RO(pml_rec_successes);
+static struct kobj_attribute link_pml_rec_link_fault_cause        = __ATTR_RO(pml_rec_link_fault_cause);
+static struct kobj_attribute link_pml_rec_link_down_cause         = __ATTR_RO(pml_rec_link_down_cause);
+static struct kobj_attribute link_pml_rec_link_fault_failed_cause = __ATTR_RO(pml_rec_link_fault_failed_cause);
+static struct kobj_attribute link_pml_rec_link_down_failed_cause  = __ATTR_RO(pml_rec_link_down_failed_cause);
+static struct kobj_attribute link_pml_rec_rate_limit_exceeded     = __ATTR_RO(pml_rec_rate_limit_exceeded);
+
+static struct attribute *link_pml_rec_attrs[] = {
+	&link_pml_rec_attempts.attr,
+	&link_pml_rec_successes.attr,
+	&link_pml_rec_link_fault_cause.attr,
+	&link_pml_rec_link_down_cause.attr,
+	&link_pml_rec_link_fault_failed_cause.attr,
+	&link_pml_rec_link_down_failed_cause.attr,
+	&link_pml_rec_rate_limit_exceeded.attr,
+	NULL
+};
+ATTRIBUTE_GROUPS(link_pml_rec);
+
+static struct kobj_type link_pml_rec = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = link_pml_rec_groups,
+};
+#endif /* CONFIG_SYSFS */
+
+int sl_sysfs_link_pml_rec_create(struct sl_core_link *core_link, struct kobject *parent_kobj)
+{
+#ifdef CONFIG_SYSFS
+	int rtn;
+
+	sl_log_dbg(core_link, LOG_BLOCK, LOG_NAME, "link pml rec create (num = %u)", core_link->num);
+
+	rtn = kobject_init_and_add(&core_link->pml_rec_kobj, &link_pml_rec, parent_kobj, "pml_recovery");
+	if (rtn) {
+		sl_log_err(core_link, LOG_BLOCK, LOG_NAME,
+			   "link pml rec create kobject_init_and_add failed [%d]", rtn);
+		kobject_put(&core_link->pml_rec_kobj);
+		return rtn;
+	}
+
+	return 0;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_link_pml_rec_delete(struct sl_core_link *core_link)
+{
+#ifdef CONFIG_SYSFS
+	sl_log_dbg(core_link, LOG_BLOCK, LOG_NAME, "link pml rec delete (num = %u)", core_link->num);
+
+	kobject_put(&core_link->pml_rec_kobj);
+#endif /* CONFIG_SYSFS */
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_policy.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_policy.c
new file mode 100644
index 000000000000..110486b5d274
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_link_policy.c
@@ -0,0 +1,261 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2024-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kobject.h>
+#include <linux/sysfs.h>
+
+#include "sl_log.h"
+#include "sl_sysfs.h"
+#include "data/sl_ctrl_data_link.h"
+#include "sl_ctrl_link.h"
+#include "sl_test_common.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+#ifdef CONFIG_SYSFS
+static ssize_t fec_mon_period_ms_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link;
+	s32                  fec_mon_period_ms;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, policy_kobj);
+
+	rtn = sl_ctrl_data_link_policy_fec_mon_period_ms_get(ctrl_link, &fec_mon_period_ms);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "fec_mon_period_ms show (fec_mon_period_ms = %d)", fec_mon_period_ms);
+
+	return sysfs_emit(buf, "%d\n", fec_mon_period_ms);
+}
+
+static ssize_t fec_mon_ucw_down_limit_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link;
+	s32                  fec_mon_ucw_down_limit;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, policy_kobj);
+
+	rtn = sl_ctrl_data_link_policy_fec_mon_ucw_down_limit_get(ctrl_link, &fec_mon_ucw_down_limit);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "fec_mon_ucw_down_limit show (fec_mon_ucw_down_limit = %d)", fec_mon_ucw_down_limit);
+
+	return sysfs_emit(buf, "%d\n", fec_mon_ucw_down_limit);
+}
+
+static ssize_t fec_mon_ucw_warn_limit_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link;
+	s32                  fec_mon_ucw_warn_limit;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, policy_kobj);
+
+	rtn = sl_ctrl_data_link_policy_fec_mon_ucw_warn_limit_get(ctrl_link, &fec_mon_ucw_warn_limit);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "fec_mon_ucw_warn_limit show (fec_mon_ucw_warn_limit = %d)", fec_mon_ucw_warn_limit);
+
+	return sysfs_emit(buf, "%d\n", fec_mon_ucw_warn_limit);
+}
+
+static ssize_t fec_mon_ccw_down_limit_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link;
+	s32                  fec_mon_ccw_down_limit;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, policy_kobj);
+
+	rtn = sl_ctrl_data_link_policy_fec_mon_ccw_down_limit_get(ctrl_link, &fec_mon_ccw_down_limit);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "fec_mon_ccw_down_limit show (fec_mon_ccw_down_limit = %d)", fec_mon_ccw_down_limit);
+
+	return sysfs_emit(buf, "%d\n", fec_mon_ccw_down_limit);
+}
+
+static ssize_t fec_mon_ccw_warn_limit_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link;
+	s32                  fec_mon_ccw_warn_limit;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, policy_kobj);
+
+	rtn = sl_ctrl_data_link_policy_fec_mon_ccw_warn_limit_get(ctrl_link, &fec_mon_ccw_warn_limit);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "fec_mon_ccw_warn_limit show (fec_mon_ccw_warn_limit = %d)", fec_mon_ccw_warn_limit);
+
+	return sysfs_emit(buf, "%d\n", fec_mon_ccw_warn_limit);
+}
+
+static ssize_t lock_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link;
+	u32                  options;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, policy_kobj);
+
+	rtn = sl_ctrl_data_link_policy_options_get(ctrl_link, &options);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "link_policy_option_locked show (options = 0x%X)", options);
+
+	return sysfs_emit(buf, "%s\n", (options & SL_LINK_POLICY_OPT_LOCK) ? "enabled" : "disabled");
+}
+
+static ssize_t keep_serdes_up_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link;
+	u32                  options;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, policy_kobj);
+
+	rtn = sl_ctrl_data_link_policy_options_get(ctrl_link, &options);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "link_policy_option_keep_serdes_up show (options = 0x%X)", options);
+
+	return sysfs_emit(buf, "%s\n",
+			 (options & SL_LINK_POLICY_OPT_KEEP_SERDES_UP) ? "enabled" : "disabled");
+}
+
+static ssize_t use_unsupported_cable_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link;
+	u32                  options;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, policy_kobj);
+
+	rtn = sl_ctrl_data_link_policy_options_get(ctrl_link, &options);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "link_policy_option_use_unsupported_cable show (options = 0x%X)", options);
+
+	return sysfs_emit(buf, "%s\n",
+			 (options & SL_LINK_POLICY_OPT_USE_UNSUPPORTED_CABLE) ? "enabled" : "disabled");
+}
+
+static ssize_t use_supported_ss200_cable_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link;
+	u32                  options;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, policy_kobj);
+
+	rtn = sl_ctrl_data_link_policy_options_get(ctrl_link, &options);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "link_policy_option_use_supported_ss200_cable show (options = 0x%X)", options);
+
+	return sysfs_emit(buf, "%s\n",
+			 (options & SL_LINK_POLICY_OPT_USE_SUPPORTED_SS200_CABLE) ? "enabled" : "disabled");
+}
+
+static ssize_t ignore_media_error_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_ctrl_link *ctrl_link;
+	u32                  options;
+
+	ctrl_link = container_of(kobj, struct sl_ctrl_link, policy_kobj);
+
+	rtn = sl_ctrl_data_link_policy_options_get(ctrl_link, &options);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME,
+		   "link_policy_option_ignore_media_error show (options = %u)", options);
+
+	return sysfs_emit(buf, "%s\n",
+			 (options & SL_LINK_POLICY_OPT_IGNORE_MEDIA_ERROR) ? "enabled" : "disabled");
+}
+
+static struct kobj_attribute fec_mon_period_ms         = __ATTR_RO(fec_mon_period_ms);
+static struct kobj_attribute fec_mon_ucw_down_limit    = __ATTR_RO(fec_mon_ucw_down_limit);
+static struct kobj_attribute fec_mon_ucw_warn_limit    = __ATTR_RO(fec_mon_ucw_warn_limit);
+static struct kobj_attribute fec_mon_ccw_down_limit    = __ATTR_RO(fec_mon_ccw_down_limit);
+static struct kobj_attribute fec_mon_ccw_warn_limit    = __ATTR_RO(fec_mon_ccw_warn_limit);
+static struct kobj_attribute lock                      = __ATTR_RO(lock);
+static struct kobj_attribute keep_serdes_up            = __ATTR_RO(keep_serdes_up);
+static struct kobj_attribute use_unsupported_cable     = __ATTR_RO(use_unsupported_cable);
+static struct kobj_attribute use_supported_ss200_cable = __ATTR_RO(use_supported_ss200_cable);
+static struct kobj_attribute ignore_media_error        = __ATTR_RO(ignore_media_error);
+
+static struct attribute *link_policy_attrs[] = {
+	&fec_mon_period_ms.attr,
+	&fec_mon_ucw_down_limit.attr,
+	&fec_mon_ucw_warn_limit.attr,
+	&fec_mon_ccw_down_limit.attr,
+	&fec_mon_ccw_warn_limit.attr,
+	&lock.attr,
+	&keep_serdes_up.attr,
+	&use_unsupported_cable.attr,
+	&use_supported_ss200_cable.attr,
+	&ignore_media_error.attr,
+	NULL
+};
+ATTRIBUTE_GROUPS(link_policy);
+
+static struct kobj_type link_policy = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = link_policy_groups,
+};
+#endif /* CONFIG_SYSFS */
+
+int sl_sysfs_link_policy_create(struct sl_ctrl_link *ctrl_link)
+{
+#ifdef CONFIG_SYSFS
+	int rtn;
+
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link policy create (num = %u)", ctrl_link->num);
+
+	rtn = kobject_init_and_add(&ctrl_link->policy_kobj, &link_policy, &ctrl_link->kobj, "policies");
+	if (rtn) {
+		sl_log_err(ctrl_link, LOG_BLOCK, LOG_NAME,
+			   "link policy create kobject_init_and_add failed [%d]", rtn);
+		kobject_put(&ctrl_link->policy_kobj);
+		return rtn;
+	}
+
+	return 0;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_link_policy_delete(struct sl_ctrl_link *ctrl_link)
+{
+#ifdef CONFIG_SYSFS
+	sl_log_dbg(ctrl_link, LOG_BLOCK, LOG_NAME, "link config delete (num = %u)", ctrl_link->num);
+
+	kobject_put(&ctrl_link->policy_kobj);
+#endif /* CONFIG_SYSFS */
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_llr.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_llr.c
new file mode 100644
index 000000000000..fd142ad85ea1
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_llr.c
@@ -0,0 +1,221 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2023-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kobject.h>
+#include <linux/sysfs.h>
+
+#include <linux/hpe/sl/sl_llr.h>
+
+#include "sl_log.h"
+#include "sl_sysfs.h"
+#include "sl_core_str.h"
+#include "sl_ctrl_llr.h"
+#include "sl_ctrl_lgrp.h"
+#include "sl_ctrl_ldev.h"
+
+#include "data/sl_core_data_llr.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+#ifdef CONFIG_SYSFS
+static ssize_t last_fail_cause_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                 rtn;
+	struct sl_core_llr *core_llr;
+	u32                 llr_fail_cause;
+	time64_t            llr_fail_time;
+
+	core_llr = container_of(kobj, struct sl_core_llr, kobj);
+
+	rtn = sl_core_data_llr_last_fail_cause_get(core_llr, &llr_fail_cause, &llr_fail_time);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_llr, LOG_BLOCK, LOG_NAME,
+		   "last fail cause show (cause = %u %s)", llr_fail_cause, sl_core_llr_fail_cause_str(llr_fail_cause));
+
+	if (llr_fail_cause == SL_LLR_FAIL_CAUSE_NONE)
+		return sysfs_emit(buf, "no-fail\n");
+
+	return sysfs_emit(buf, "%s\n", sl_core_llr_fail_cause_str(llr_fail_cause));
+}
+
+static ssize_t last_fail_time_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                 rtn;
+	struct sl_core_llr *core_llr;
+	u32                 llr_fail_cause;
+	time64_t            llr_fail_time;
+
+	core_llr = container_of(kobj, struct sl_core_llr, kobj);
+
+	rtn = sl_core_data_llr_last_fail_cause_get(core_llr, &llr_fail_cause, &llr_fail_time);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_llr, LOG_BLOCK, LOG_NAME,
+		   "last fail time show (cause = %u %s, time = %lld %ptTt %ptTd)",
+		   llr_fail_cause, sl_core_llr_fail_cause_str(llr_fail_cause),
+		   llr_fail_time, &llr_fail_time, &llr_fail_time);
+
+	if (llr_fail_cause == SL_LLR_FAIL_CAUSE_NONE)
+		return sysfs_emit(buf, "no-fail\n");
+
+	return sysfs_emit(buf, "%ptTt %ptTd\n", &llr_fail_time, &llr_fail_time);
+}
+
+static ssize_t state_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int rtn;
+	struct sl_core_llr *core_llr;
+	enum sl_core_llr_state core_llr_state;
+	u32 llr_state;
+
+	core_llr = container_of(kobj, struct sl_core_llr, kobj);
+
+	rtn = sl_core_data_llr_state_get(core_llr, &core_llr_state);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	llr_state = sl_ctrl_llr_state_from_core_llr_state(core_llr_state);
+
+	sl_log_dbg(core_llr, LOG_BLOCK, LOG_NAME,
+		   "state show (core_llr_state = %u %s, llr_state = %u %s)",
+		   core_llr_state, sl_core_llr_state_str(core_llr_state),
+		   llr_state, sl_llr_state_str(llr_state));
+
+	return sysfs_emit(buf, "%s\n", sl_llr_state_str(llr_state));
+}
+
+static ssize_t info_map_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                 rtn;
+	struct sl_core_llr *core_llr;
+	u64                 info_map;
+	char                info_map_str[900];
+
+	core_llr = container_of(kobj, struct sl_core_llr, kobj);
+
+	rtn = sl_core_data_llr_info_map_get(core_llr, &info_map);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_core_info_map_str(info_map, info_map_str, sizeof(info_map_str));
+
+	sl_log_dbg(core_llr, LOG_BLOCK, LOG_NAME,
+		   "info map show (info_map = 0x%llX %s)", info_map, info_map_str);
+
+	return sysfs_emit(buf, "%s\n", info_map_str);
+}
+
+static struct kobj_attribute llr_state           = __ATTR_RO(state);
+static struct kobj_attribute llr_last_fail_cause = __ATTR_RO(last_fail_cause);
+static struct kobj_attribute llr_last_fail_time  = __ATTR_RO(last_fail_time);
+static struct kobj_attribute llr_info_map        = __ATTR_RO(info_map);
+
+static struct attribute *llr_attrs[] = {
+	&llr_state.attr,
+	&llr_last_fail_cause.attr,
+	&llr_last_fail_time.attr,
+	&llr_info_map.attr,
+	NULL
+};
+ATTRIBUTE_GROUPS(llr);
+
+static struct kobj_type llr_info = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = llr_groups,
+};
+#endif /* CONFIG_SYSFS */
+
+int sl_sysfs_llr_create(struct sl_ctrl_llr *ctrl_llr)
+{
+#ifdef CONFIG_SYSFS
+	int                 rtn;
+	struct sl_core_llr *core_llr;
+
+	core_llr = sl_core_llr_get(ctrl_llr->ctrl_lgrp->ctrl_ldev->num,
+				   ctrl_llr->ctrl_lgrp->num, ctrl_llr->num);
+
+	sl_log_dbg(ctrl_llr, LOG_BLOCK, LOG_NAME, "llr create (num = %u)", ctrl_llr->num);
+
+	if (!ctrl_llr->parent_kobj) {
+		sl_log_err(ctrl_llr, LOG_BLOCK, LOG_NAME, "llr create missing parent");
+		return -EBADRQC;
+	}
+
+	rtn = kobject_init_and_add(&core_llr->kobj, &llr_info, ctrl_llr->parent_kobj, "llr");
+	if (rtn) {
+		sl_log_err(ctrl_llr, LOG_BLOCK, LOG_NAME,
+			   "llr create kobject_init_and_add failed [%d]", rtn);
+		kobject_put(&core_llr->kobj);
+		return rtn;
+	}
+
+	rtn = sl_sysfs_llr_config_create(ctrl_llr, &core_llr->kobj);
+	if (rtn) {
+		sl_log_err(ctrl_llr, LOG_BLOCK, LOG_NAME,
+			   "llr config create failed [%d]", rtn);
+		kobject_put(&core_llr->kobj);
+		return rtn;
+	}
+
+	rtn = sl_sysfs_llr_policy_create(core_llr, &core_llr->kobj);
+	if (rtn) {
+		sl_log_err(ctrl_llr, LOG_BLOCK, LOG_NAME,
+			   "llr policy create failed [%d]", rtn);
+		kobject_put(&core_llr->kobj);
+		sl_sysfs_llr_config_delete(ctrl_llr);
+		return rtn;
+	}
+
+	rtn = sl_sysfs_llr_loop_time_create(core_llr, &core_llr->kobj);
+	if (rtn) {
+		sl_log_err(ctrl_llr, LOG_BLOCK, LOG_NAME,
+			   "llr loop time create failed [%d]", rtn);
+		kobject_put(&core_llr->kobj);
+		sl_sysfs_llr_config_delete(ctrl_llr);
+		sl_sysfs_llr_policy_delete(core_llr);
+		return rtn;
+	}
+
+	rtn = sl_sysfs_llr_counters_create(ctrl_llr, &core_llr->kobj);
+	if (rtn) {
+		sl_log_err(ctrl_llr, LOG_BLOCK, LOG_NAME, "sl_sysfs_llr_counters_create failed [%d]", rtn);
+		kobject_put(&core_llr->kobj);
+		sl_sysfs_llr_config_delete(ctrl_llr);
+		sl_sysfs_llr_policy_delete(core_llr);
+		sl_sysfs_llr_loop_time_delete(core_llr);
+		return rtn;
+	}
+
+	sl_log_dbg(ctrl_llr, LOG_BLOCK, LOG_NAME,
+		   "llr create (llr_kobj = 0x%p)", &core_llr->kobj);
+
+	return 0;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_llr_delete(struct sl_ctrl_llr *ctrl_llr)
+{
+#ifdef CONFIG_SYSFS
+	struct sl_core_llr *core_llr;
+
+	sl_log_dbg(ctrl_llr, LOG_BLOCK, LOG_NAME, "delete (num = %u)", ctrl_llr->num);
+
+	if (!ctrl_llr->parent_kobj)
+		return;
+
+	core_llr = sl_core_llr_get(ctrl_llr->ctrl_lgrp->ctrl_ldev->num,
+				   ctrl_llr->ctrl_lgrp->num, ctrl_llr->num);
+
+	sl_sysfs_llr_counters_delete(ctrl_llr);
+	sl_sysfs_llr_loop_time_delete(core_llr);
+	sl_sysfs_llr_policy_delete(core_llr);
+	sl_sysfs_llr_config_delete(ctrl_llr);
+	kobject_put(&core_llr->kobj);
+#endif /* CONFIG_SYSFS */
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_llr_config.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_llr_config.c
new file mode 100644
index 000000000000..0fde52d669ca
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_llr_config.c
@@ -0,0 +1,140 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2024-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kobject.h>
+#include <linux/sysfs.h>
+#include <linux/hpe/sl/sl_lgrp.h>
+
+#include "sl_log.h"
+#include "sl_sysfs.h"
+#include "data/sl_ctrl_data_llr.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+#ifdef CONFIG_SYSFS
+static ssize_t mode_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                 rtn;
+	struct sl_ctrl_llr *ctrl_llr;
+	u32                 mode;
+
+	ctrl_llr = container_of(kobj, struct sl_ctrl_llr, config_kobj);
+
+	rtn = sl_ctrl_data_llr_config_mode_get(ctrl_llr, &mode);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_llr, LOG_BLOCK, LOG_NAME,
+		   "mode (mode = %u %s)",
+		   mode, sl_lgrp_llr_mode_str(mode));
+
+	return sysfs_emit(buf, "%s\n", sl_lgrp_llr_mode_str(mode));
+}
+
+static ssize_t setup_timeout_ms_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                 rtn;
+	struct sl_ctrl_llr *ctrl_llr;
+	u32                 setup_timeout_ms;
+
+	ctrl_llr = container_of(kobj, struct sl_ctrl_llr, config_kobj);
+
+	rtn = sl_ctrl_data_llr_config_setup_timeout_ms_get(ctrl_llr, &setup_timeout_ms);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_llr, LOG_BLOCK, LOG_NAME,
+		   "setup timeout show (setup_timeout = %ums)",
+		   setup_timeout_ms);
+
+	return sysfs_emit(buf, "%u\n", setup_timeout_ms);
+}
+
+static ssize_t start_timeout_ms_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                 rtn;
+	struct sl_ctrl_llr *ctrl_llr;
+	u32                 start_timeout_ms;
+
+	ctrl_llr = container_of(kobj, struct sl_ctrl_llr, config_kobj);
+
+	rtn = sl_ctrl_data_llr_config_start_timeout_ms_get(ctrl_llr, &start_timeout_ms);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_llr, LOG_BLOCK, LOG_NAME,
+		   "start timeout show (start_timeout = %ums)",
+		   start_timeout_ms);
+
+	return sysfs_emit(buf, "%u\n", start_timeout_ms);
+}
+
+static ssize_t link_down_behavior_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                 rtn;
+	struct sl_ctrl_llr *ctrl_llr;
+	u32                 link_dn_behavior;
+
+	ctrl_llr = container_of(kobj, struct sl_ctrl_llr, config_kobj);
+
+	rtn = sl_ctrl_data_llr_config_link_dn_behavior_get(ctrl_llr, &link_dn_behavior);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_llr, LOG_BLOCK, LOG_NAME,
+		   "down behavior show (dn_behavior = %u %s)",
+		   link_dn_behavior, sl_llr_link_dn_behavior_str(link_dn_behavior));
+
+	return sysfs_emit(buf, "%s\n", sl_llr_link_dn_behavior_str(link_dn_behavior));
+}
+
+static struct kobj_attribute mode             = __ATTR_RO(mode);
+static struct kobj_attribute setup_timeout_ms = __ATTR_RO(setup_timeout_ms);
+static struct kobj_attribute start_timeout_ms = __ATTR_RO(start_timeout_ms);
+static struct kobj_attribute dn_behavior      = __ATTR_RO(link_down_behavior);
+
+static struct attribute *llr_config_attrs[] = {
+	&mode.attr,
+	&setup_timeout_ms.attr,
+	&start_timeout_ms.attr,
+	&dn_behavior.attr,
+	NULL
+};
+ATTRIBUTE_GROUPS(llr_config);
+
+static struct kobj_type llr_config = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = llr_config_groups,
+};
+#endif /* CONFIG_SYSFS */
+
+int sl_sysfs_llr_config_create(struct sl_ctrl_llr *ctrl_llr, struct kobject *parent_kobj)
+{
+#ifdef CONFIG_SYSFS
+	int rtn;
+
+	sl_log_dbg(ctrl_llr, LOG_BLOCK, LOG_NAME, "llr config create (num = %u)", ctrl_llr->num);
+
+	rtn = kobject_init_and_add(&ctrl_llr->config_kobj, &llr_config, parent_kobj, "config");
+	if (rtn) {
+		sl_log_err(ctrl_llr, LOG_BLOCK, LOG_NAME,
+			   "llr config create kobject_init_and_add failed [%d]", rtn);
+		kobject_put(&ctrl_llr->config_kobj);
+		return rtn;
+	}
+
+	return 0;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_llr_config_delete(struct sl_ctrl_llr *ctrl_llr)
+{
+#ifdef CONFIG_SYSFS
+	sl_log_dbg(ctrl_llr, LOG_BLOCK, LOG_NAME, "llr config delete (num = %u)", ctrl_llr->num);
+
+	kobject_put(&ctrl_llr->config_kobj);
+#endif /* CONFIG_SYSFS */
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_llr_counters.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_llr_counters.c
new file mode 100644
index 000000000000..516f130c76ff
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_llr_counters.c
@@ -0,0 +1,397 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2025-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kobject.h>
+#include <linux/sysfs.h>
+
+#include "sl_sysfs.h"
+#include "sl_log.h"
+#include "sl_ctrl_llr.h"
+#include "sl_ctrl_llr_counters.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+#ifdef CONFIG_SYSFS
+static ssize_t llr_setup_cmd_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_llr *ctrl_llr;
+	u32                 counter;
+	u32                 rtn;
+
+	ctrl_llr = container_of(kobj, struct sl_ctrl_llr, counters_kobj);
+
+	rtn = sl_ctrl_llr_counter_get(ctrl_llr, LLR_SETUP_CMD, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_llr, LOG_BLOCK, LOG_NAME, "llr setup cmd show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t llr_setup_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_llr *ctrl_llr;
+	u32                 counter;
+	u32                 rtn;
+
+	ctrl_llr = container_of(kobj, struct sl_ctrl_llr, counters_kobj);
+
+	rtn = sl_ctrl_llr_counter_get(ctrl_llr, LLR_SETUP, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_llr, LOG_BLOCK, LOG_NAME, "llr setup show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t llr_setup_timeout_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_llr *ctrl_llr;
+	u32                 counter;
+	u32                 rtn;
+
+	ctrl_llr = container_of(kobj, struct sl_ctrl_llr, counters_kobj);
+
+	rtn = sl_ctrl_llr_counter_get(ctrl_llr, LLR_SETUP_TIMEOUT, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_llr, LOG_BLOCK, LOG_NAME, "llr setup timeout show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t llr_setup_fail_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_llr *ctrl_llr;
+	u32                 counter;
+	u32                 rtn;
+
+	ctrl_llr = container_of(kobj, struct sl_ctrl_llr, counters_kobj);
+
+	rtn = sl_ctrl_llr_counter_get(ctrl_llr, LLR_SETUP_FAIL, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_llr, LOG_BLOCK, LOG_NAME, "llr setup fail show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t llr_configured_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_llr *ctrl_llr;
+	u32                 counter;
+	u32                 rtn;
+
+	ctrl_llr = container_of(kobj, struct sl_ctrl_llr, counters_kobj);
+
+	rtn = sl_ctrl_llr_counter_get(ctrl_llr, LLR_CONFIGURED, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_llr, LOG_BLOCK, LOG_NAME, "llr configured show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t llr_start_cmd_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_llr *ctrl_llr;
+	u32                 counter;
+	u32                 rtn;
+
+	ctrl_llr = container_of(kobj, struct sl_ctrl_llr, counters_kobj);
+
+	rtn = sl_ctrl_llr_counter_get(ctrl_llr, LLR_START_CMD, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_llr, LOG_BLOCK, LOG_NAME, "llr start cmd show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t llr_running_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_llr *ctrl_llr;
+	u32                 counter;
+	u32                 rtn;
+
+	ctrl_llr = container_of(kobj, struct sl_ctrl_llr, counters_kobj);
+
+	rtn = sl_ctrl_llr_counter_get(ctrl_llr, LLR_RUNNING, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_llr, LOG_BLOCK, LOG_NAME, "llr running show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t llr_start_timeout_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_llr *ctrl_llr;
+	u32                 counter;
+	u32                 rtn;
+
+	ctrl_llr = container_of(kobj, struct sl_ctrl_llr, counters_kobj);
+
+	rtn = sl_ctrl_llr_counter_get(ctrl_llr, LLR_START_TIMEOUT, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_llr, LOG_BLOCK, LOG_NAME, "llr start timeout show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t llr_start_fail_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_llr *ctrl_llr;
+	u32                 counter;
+	u32                 rtn;
+
+	ctrl_llr = container_of(kobj, struct sl_ctrl_llr, counters_kobj);
+
+	rtn = sl_ctrl_llr_counter_get(ctrl_llr, LLR_START_FAIL, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_llr, LOG_BLOCK, LOG_NAME, "llr start fail show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t llr_stop_cmd_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_llr *ctrl_llr;
+	u32                 counter;
+	u32                 rtn;
+
+	ctrl_llr = container_of(kobj, struct sl_ctrl_llr, counters_kobj);
+
+	rtn = sl_ctrl_llr_counter_get(ctrl_llr, LLR_STOP_CMD, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_llr, LOG_BLOCK, LOG_NAME, "llr stop cmd show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t llr_stop_fail_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_llr *ctrl_llr;
+	u32                 counter;
+	u32                 rtn;
+
+	ctrl_llr = container_of(kobj, struct sl_ctrl_llr, counters_kobj);
+
+	rtn = sl_ctrl_llr_counter_get(ctrl_llr, LLR_STOP_FAIL, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_llr, LOG_BLOCK, LOG_NAME, "llr stop fail show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_setup_config_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_llr *ctrl_llr;
+	u32                 counter;
+	u32                 rtn;
+
+	ctrl_llr = container_of(kobj, struct sl_ctrl_llr, counters_kobj);
+
+	rtn = sl_ctrl_llr_cause_counter_get(ctrl_llr, LLR_CAUSE_SETUP_CONFIG, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_llr, LOG_BLOCK, LOG_NAME, "llr cause setup config show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_setup_intr_enable_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_llr *ctrl_llr;
+	u32                 counter;
+	u32                 rtn;
+
+	ctrl_llr = container_of(kobj, struct sl_ctrl_llr, counters_kobj);
+
+	rtn = sl_ctrl_llr_cause_counter_get(ctrl_llr, LLR_CAUSE_SETUP_INTR_ENABLE, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_llr, LOG_BLOCK, LOG_NAME, "llr cause setup intr enable show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_setup_timeout_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_llr *ctrl_llr;
+	u32                 counter;
+	u32                 rtn;
+
+	ctrl_llr = container_of(kobj, struct sl_ctrl_llr, counters_kobj);
+
+	rtn = sl_ctrl_llr_cause_counter_get(ctrl_llr, LLR_CAUSE_SETUP_TIMEOUT, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_llr, LOG_BLOCK, LOG_NAME, "llr cause setup timeout show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_start_intr_enable_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_llr *ctrl_llr;
+	u32                 counter;
+	u32                 rtn;
+
+	ctrl_llr = container_of(kobj, struct sl_ctrl_llr, counters_kobj);
+
+	rtn = sl_ctrl_llr_cause_counter_get(ctrl_llr, LLR_CAUSE_START_INTR_ENABLE, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_llr, LOG_BLOCK, LOG_NAME, "llr cause start intr enable show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_start_timeout_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_llr *ctrl_llr;
+	u32                 counter;
+	u32                 rtn;
+
+	ctrl_llr = container_of(kobj, struct sl_ctrl_llr, counters_kobj);
+
+	rtn = sl_ctrl_llr_cause_counter_get(ctrl_llr, LLR_CAUSE_START_TIMEOUT, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_llr, LOG_BLOCK, LOG_NAME, "llr cause start timeout show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_command_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_llr *ctrl_llr;
+	u32                 counter;
+	u32                 rtn;
+
+	ctrl_llr = container_of(kobj, struct sl_ctrl_llr, counters_kobj);
+
+	rtn = sl_ctrl_llr_cause_counter_get(ctrl_llr, LLR_CAUSE_COMMAND, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_llr, LOG_BLOCK, LOG_NAME, "llr cause command show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_canceled_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_llr *ctrl_llr;
+	u32                 counter;
+	u32                 rtn;
+
+	ctrl_llr = container_of(kobj, struct sl_ctrl_llr, counters_kobj);
+
+	rtn = sl_ctrl_llr_cause_counter_get(ctrl_llr, LLR_CAUSE_CANCELED, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_llr, LOG_BLOCK, LOG_NAME, "llr cause canceled show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static struct kobj_attribute llr_setup_cmd     = __ATTR_RO(llr_setup_cmd);
+static struct kobj_attribute llr_setup         = __ATTR_RO(llr_setup);
+static struct kobj_attribute llr_setup_timeout = __ATTR_RO(llr_setup_timeout);
+static struct kobj_attribute llr_setup_fail    = __ATTR_RO(llr_setup_fail);
+static struct kobj_attribute llr_configured    = __ATTR_RO(llr_configured);
+static struct kobj_attribute llr_start_cmd     = __ATTR_RO(llr_start_cmd);
+static struct kobj_attribute llr_running       = __ATTR_RO(llr_running);
+static struct kobj_attribute llr_start_timeout = __ATTR_RO(llr_start_timeout);
+static struct kobj_attribute llr_start_fail    = __ATTR_RO(llr_start_fail);
+static struct kobj_attribute llr_stop_cmd      = __ATTR_RO(llr_stop_cmd);
+static struct kobj_attribute llr_stop_fail     = __ATTR_RO(llr_stop_fail);
+
+static struct kobj_attribute llr_cause_setup_config      = __ATTR_RO(cause_setup_config);
+static struct kobj_attribute llr_cause_setup_intr_enable = __ATTR_RO(cause_setup_intr_enable);
+static struct kobj_attribute llr_cause_setup_timeout     = __ATTR_RO(cause_setup_timeout);
+static struct kobj_attribute llr_cause_start_intr_enable = __ATTR_RO(cause_start_intr_enable);
+static struct kobj_attribute llr_cause_start_timeout     = __ATTR_RO(cause_start_timeout);
+static struct kobj_attribute llr_cause_command           = __ATTR_RO(cause_command);
+static struct kobj_attribute llr_cause_canceled          = __ATTR_RO(cause_canceled);
+
+static struct attribute *llr_counters_attrs[] = {
+	&llr_setup_cmd.attr,
+	&llr_setup.attr,
+	&llr_setup_timeout.attr,
+	&llr_setup_fail.attr,
+	&llr_configured.attr,
+	&llr_start_cmd.attr,
+	&llr_running.attr,
+	&llr_start_timeout.attr,
+	&llr_start_fail.attr,
+	&llr_stop_cmd.attr,
+	&llr_stop_fail.attr,
+	&llr_cause_setup_config.attr,
+	&llr_cause_setup_intr_enable.attr,
+	&llr_cause_setup_timeout.attr,
+	&llr_cause_start_intr_enable.attr,
+	&llr_cause_start_timeout.attr,
+	&llr_cause_command.attr,
+	&llr_cause_canceled.attr,
+	NULL
+};
+ATTRIBUTE_GROUPS(llr_counters);
+
+static struct kobj_type llr_counters = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = llr_counters_groups,
+};
+#endif /* CONFIG_SYSFS */
+
+int sl_sysfs_llr_counters_create(struct sl_ctrl_llr *ctrl_llr, struct kobject *parent_kobj)
+{
+#ifdef CONFIG_SYSFS
+	int rtn;
+
+	sl_log_dbg(ctrl_llr, LOG_BLOCK, LOG_NAME, "llr counters create");
+
+	rtn = kobject_init_and_add(&ctrl_llr->counters_kobj, &llr_counters, parent_kobj, "counters");
+	if (rtn) {
+		sl_log_err(ctrl_llr, LOG_BLOCK, LOG_NAME, "llr counters create kobject_init_and_add failed [%d]", rtn);
+		kobject_put(&ctrl_llr->counters_kobj);
+		return rtn;
+	}
+
+	return 0;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_llr_counters_delete(struct sl_ctrl_llr *ctrl_llr)
+{
+#ifdef CONFIG_SYSFS
+	sl_log_dbg(ctrl_llr, LOG_BLOCK, LOG_NAME, "llr counters delete");
+	kobject_put(&ctrl_llr->counters_kobj);
+#endif /* CONFIG_SYSFS */
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_llr_loop_time.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_llr_loop_time.c
new file mode 100644
index 000000000000..977bb176b454
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_llr_loop_time.c
@@ -0,0 +1,221 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2024-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kobject.h>
+#include <linux/sysfs.h>
+
+#include "sl_log.h"
+#include "data/sl_core_data_llr.h"
+
+#include "sl_sysfs.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+#ifdef CONFIG_SYSFS
+static ssize_t llr_loop_time_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf, u8 num)
+{
+	int                 rtn;
+	struct sl_core_llr *core_llr;
+	u64                 loop_time[SL_CORE_LLR_MAX_LOOP_TIME_COUNT];
+
+	core_llr = container_of(kobj, struct sl_core_llr, loop_time_kobj);
+
+	rtn = sl_core_data_llr_loop_time_get(core_llr, loop_time);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_llr, LOG_BLOCK, LOG_NAME,
+		   "loop time show (loop_time[%u] = %lluns)", num, loop_time[num]);
+
+	return sysfs_emit(buf, "%llu\n", loop_time[num]);
+}
+
+#define llr_loop_time(_num)                                                                                        \
+	static inline ssize_t time_##_num##_ns_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf) \
+	{                                                                                                          \
+		return llr_loop_time_show(kobj, kattr, buf, (_num));                                               \
+	}                                                                                                          \
+	static struct kobj_attribute llr_loop_time_##_num = __ATTR_RO(time_##_num##_ns)
+
+llr_loop_time(0);
+llr_loop_time(1);
+llr_loop_time(2);
+llr_loop_time(3);
+llr_loop_time(4);
+llr_loop_time(5);
+llr_loop_time(6);
+llr_loop_time(7);
+llr_loop_time(8);
+llr_loop_time(9);
+
+#define sl_sysfs_llr_loop_time_file(_num)                                                       \
+	do {                                                                                    \
+		rtn = sysfs_create_file(&core_llr->loop_time_kobj, &llr_loop_time_##_num.attr); \
+		if (rtn) {                                                                      \
+			sl_log_err(core_llr, LOG_BLOCK, LOG_NAME,                               \
+				"llr loop time create file failed [%d]", rtn);                  \
+			goto out;                                                               \
+		}                                                                               \
+	} while (0)
+
+static ssize_t calc_ns_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                 rtn;
+	struct sl_core_llr *core_llr;
+	u64                 calculated_ns;
+
+	core_llr = container_of(kobj, struct sl_core_llr, loop_time_kobj);
+
+	rtn = sl_core_data_llr_loop_calculated_ns_get(core_llr, &calculated_ns);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_llr, LOG_BLOCK, LOG_NAME,
+		   "calc show (calculated_ns = %lluns)", calculated_ns);
+
+	return sysfs_emit(buf, "%llu\n", calculated_ns);
+}
+
+static ssize_t min_ns_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                 rtn;
+	struct sl_core_llr *core_llr;
+	u64                 min_ns;
+
+	core_llr = container_of(kobj, struct sl_core_llr, loop_time_kobj);
+
+	rtn = sl_core_data_llr_loop_min_ns_get(core_llr, &min_ns);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_llr, LOG_BLOCK, LOG_NAME,
+		   "min show (min_ns = %lluns)", min_ns);
+
+	return sysfs_emit(buf, "%llu\n", min_ns);
+}
+
+static ssize_t max_ns_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                 rtn;
+	struct sl_core_llr *core_llr;
+	u64                 max_ns;
+
+	core_llr = container_of(kobj, struct sl_core_llr, loop_time_kobj);
+
+	rtn = sl_core_data_llr_loop_max_ns_get(core_llr, &max_ns);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_llr, LOG_BLOCK, LOG_NAME,
+		   "max show (max_ns = %lluns)", max_ns);
+
+	return sysfs_emit(buf, "%llu\n", max_ns);
+}
+
+static ssize_t average_ns_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                 rtn;
+	struct sl_core_llr *core_llr;
+	u64                 average_ns;
+
+	core_llr = container_of(kobj, struct sl_core_llr, loop_time_kobj);
+
+	rtn = sl_core_data_llr_loop_average_ns_get(core_llr, &average_ns);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_llr, LOG_BLOCK, LOG_NAME,
+		   "average show (average_ns = %lluns)", average_ns);
+
+	return sysfs_emit(buf, "%llu\n", average_ns);
+}
+
+static struct kobj_attribute llr_loop_calc    = __ATTR_RO(calc_ns);
+static struct kobj_attribute llr_loop_min     = __ATTR_RO(min_ns);
+static struct kobj_attribute llr_loop_max     = __ATTR_RO(max_ns);
+static struct kobj_attribute llr_loop_average = __ATTR_RO(average_ns);
+
+static struct attribute *llr_loop_time_attrs[] = {
+	NULL
+};
+ATTRIBUTE_GROUPS(llr_loop_time);
+
+static struct kobj_type llr_loop_time = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = llr_loop_time_groups,
+};
+#endif /* CONFIG_SYSFS */
+
+int sl_sysfs_llr_loop_time_create(struct sl_core_llr *core_llr, struct kobject *parent_kobj)
+{
+#ifdef CONFIG_SYSFS
+	int rtn;
+
+	sl_log_dbg(core_llr, LOG_BLOCK, LOG_NAME, "llr loop time create (num = %u)", core_llr->num);
+
+	rtn = kobject_init_and_add(&core_llr->loop_time_kobj, &llr_loop_time, parent_kobj, "loop");
+	if (rtn) {
+		sl_log_err(core_llr, LOG_BLOCK, LOG_NAME,
+			   "llr loop time create kobject_init_and_add failed [%d]", rtn);
+		goto out;
+	}
+
+	BUILD_BUG_ON(SL_CORE_LLR_MAX_LOOP_TIME_COUNT < 10);
+
+	sl_sysfs_llr_loop_time_file(0);
+	sl_sysfs_llr_loop_time_file(1);
+	sl_sysfs_llr_loop_time_file(2);
+	sl_sysfs_llr_loop_time_file(3);
+	sl_sysfs_llr_loop_time_file(4);
+	sl_sysfs_llr_loop_time_file(5);
+	sl_sysfs_llr_loop_time_file(6);
+	sl_sysfs_llr_loop_time_file(7);
+	sl_sysfs_llr_loop_time_file(8);
+	sl_sysfs_llr_loop_time_file(9);
+
+	rtn = sysfs_create_file(&core_llr->loop_time_kobj, &llr_loop_calc.attr);
+	if (rtn) {
+		sl_log_err(core_llr, LOG_BLOCK, LOG_NAME,
+			   "llr loop time create file failed [%d]", rtn);
+		goto out;
+	}
+
+	rtn = sysfs_create_file(&core_llr->loop_time_kobj, &llr_loop_min.attr);
+	if (rtn) {
+		sl_log_err(core_llr, LOG_BLOCK, LOG_NAME,
+			   "llr loop time create file failed [%d]", rtn);
+		goto out;
+	}
+
+	rtn = sysfs_create_file(&core_llr->loop_time_kobj, &llr_loop_max.attr);
+	if (rtn) {
+		sl_log_err(core_llr, LOG_BLOCK, LOG_NAME,
+			   "llr loop time create file failed [%d]", rtn);
+		goto out;
+	}
+
+	rtn = sysfs_create_file(&core_llr->loop_time_kobj, &llr_loop_average.attr);
+	if (rtn) {
+		sl_log_err(core_llr, LOG_BLOCK, LOG_NAME,
+			   "llr loop time create file failed [%d]", rtn);
+		goto out;
+	}
+
+	return 0;
+out:
+	kobject_put(&core_llr->loop_time_kobj);
+	return rtn;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_llr_loop_time_delete(struct sl_core_llr *core_llr)
+{
+#ifdef CONFIG_SYSFS
+	sl_log_dbg(core_llr, LOG_BLOCK, LOG_NAME, "llr loop time delete (num = %u)", core_llr->num);
+
+	kobject_put(&core_llr->loop_time_kobj);
+#endif /* CONFIG_SYSFS */
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_llr_policy.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_llr_policy.c
new file mode 100644
index 000000000000..8b35765570c6
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_llr_policy.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2024-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kobject.h>
+#include <linux/sysfs.h>
+
+#include "sl_log.h"
+#include "data/sl_core_data_llr.h"
+
+#include "sl_sysfs.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+#ifdef CONFIG_SYSFS
+static ssize_t continuous_tries_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                 rtn;
+	struct sl_core_llr *core_llr;
+	u32                 options;
+
+	core_llr = container_of(kobj, struct sl_core_llr, policy_kobj);
+
+	rtn = sl_core_data_llr_policy_options_get(core_llr, &options);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	return sysfs_emit(buf, "%s\n",
+		(options & SL_LLR_POLICY_OPT_CONTINUOUS_START_TRIES) ? "enabled" : "disabled");
+}
+
+static struct kobj_attribute continuous_tries = __ATTR_RO(continuous_tries);
+
+static struct attribute *llr_policy_attrs[] = {
+	&continuous_tries.attr,
+	NULL
+};
+ATTRIBUTE_GROUPS(llr_policy);
+
+static struct kobj_type llr_policy = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = llr_policy_groups,
+};
+#endif /* CONFIG_SYSFS */
+
+int sl_sysfs_llr_policy_create(struct sl_core_llr *core_llr, struct kobject *parent_kobj)
+{
+#ifdef CONFIG_SYSFS
+	int rtn;
+
+	sl_log_dbg(core_llr, LOG_BLOCK, LOG_NAME, "llr policy create (num = %u)", core_llr->num);
+
+	rtn = kobject_init_and_add(&core_llr->policy_kobj, &llr_policy, parent_kobj, "policies");
+	if (rtn) {
+		sl_log_err(core_llr, LOG_BLOCK, LOG_NAME,
+			   "llr policy create kobject_init_and_add failed [%d]", rtn);
+		kobject_put(&core_llr->policy_kobj);
+		return rtn;
+	}
+
+	return 0;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_llr_policy_delete(struct sl_core_llr *core_llr)
+{
+#ifdef CONFIG_SYSFS
+	sl_log_dbg(core_llr, LOG_BLOCK, LOG_NAME, "llr policy delete (num = %u)", core_llr->num);
+
+	kobject_put(&core_llr->policy_kobj);
+#endif /* CONFIG_SYSFS */
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_mac.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_mac.c
new file mode 100644
index 000000000000..5587398a98f9
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_mac.c
@@ -0,0 +1,192 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2023-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kobject.h>
+#include <linux/sysfs.h>
+
+#include <linux/hpe/sl/sl_mac.h>
+
+#include "sl_log.h"
+#include "sl_sysfs.h"
+#include "sl_ctrl_mac.h"
+#include "sl_ctrl_lgrp.h"
+#include "sl_ctrl_ldev.h"
+#include "sl_core_str.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+#ifdef CONFIG_SYSFS
+static ssize_t rx_state_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_mac *ctrl_mac;
+	u32                 state;
+	int		    rtn;
+
+	ctrl_mac = container_of(kobj, struct sl_ctrl_mac, kobj);
+
+	rtn = sl_ctrl_mac_rx_state_get(ctrl_mac->ctrl_lgrp->ctrl_ldev->num,
+				       ctrl_mac->ctrl_lgrp->num, ctrl_mac->num, &state);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_mac, LOG_BLOCK, LOG_NAME,
+		   "rx state show (mac = 0x%p, state = %u)", ctrl_mac, state);
+
+	return sysfs_emit(buf, "%s\n", sl_mac_state_str(state));
+}
+
+static ssize_t rx_last_start_result_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_mac *ctrl_mac;
+	int                 last_start_result;
+	int                 rtn;
+
+	ctrl_mac = container_of(kobj, struct sl_ctrl_mac, kobj);
+
+	rtn = sl_core_mac_rx_last_start_result_get(ctrl_mac->ctrl_lgrp->ctrl_ldev->num,
+						   ctrl_mac->ctrl_lgrp->num, ctrl_mac->num, &last_start_result);
+
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_mac, LOG_BLOCK, LOG_NAME,
+		   "rx last start result show (mac = 0x%p, last_start_result = %d)", ctrl_mac, last_start_result);
+
+	return sysfs_emit(buf, "%d\n", last_start_result);
+}
+
+static ssize_t tx_state_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_mac *ctrl_mac;
+	u32                 state;
+	int		    rtn;
+
+	ctrl_mac = container_of(kobj, struct sl_ctrl_mac, kobj);
+
+	rtn = sl_ctrl_mac_tx_state_get(ctrl_mac->ctrl_lgrp->ctrl_ldev->num,
+				       ctrl_mac->ctrl_lgrp->num, ctrl_mac->num, &state);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_mac, LOG_BLOCK, LOG_NAME,
+		   "tx state show (mac = 0x%p, state = %u)", ctrl_mac, state);
+
+	return sysfs_emit(buf, "%s\n", sl_mac_state_str(state));
+}
+
+static ssize_t tx_last_start_result_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_mac *ctrl_mac;
+	int                 last_start_result;
+	int                 rtn;
+
+	ctrl_mac = container_of(kobj, struct sl_ctrl_mac, kobj);
+
+	rtn = sl_core_mac_tx_last_start_result_get(ctrl_mac->ctrl_lgrp->ctrl_ldev->num,
+						   ctrl_mac->ctrl_lgrp->num, ctrl_mac->num, &last_start_result);
+
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_mac, LOG_BLOCK, LOG_NAME,
+		   "tx last start result show (mac = 0x%p, last_start_result = %d)", ctrl_mac, last_start_result);
+
+	return sysfs_emit(buf, "%d\n", last_start_result);
+}
+
+static ssize_t info_map_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                 rtn;
+	struct sl_ctrl_mac *ctrl_mac;
+	u64                 info_map;
+	char                info_map_str[900];
+
+	ctrl_mac = container_of(kobj, struct sl_ctrl_mac, kobj);
+
+	rtn = sl_ctrl_mac_info_map_get(ctrl_mac->ctrl_lgrp->ctrl_ldev->num,
+				       ctrl_mac->ctrl_lgrp->num, ctrl_mac->num, &info_map);
+	if (rtn) {
+		sl_log_err(ctrl_mac, LOG_BLOCK, LOG_NAME,
+			   "info map show sl_ctrl_mac_info_map_get failed [%d]", rtn);
+		return sysfs_emit(buf, "no-mac\n");
+	}
+
+	sl_core_info_map_str(info_map, info_map_str, sizeof(info_map_str));
+
+	sl_log_dbg(ctrl_mac, LOG_BLOCK, LOG_NAME,
+		   "info map show (info_map = 0x%llX %s)", info_map, info_map_str);
+
+	return sysfs_emit(buf, "%s\n", info_map_str);
+}
+
+static struct kobj_attribute rx_state             = __ATTR_RO(rx_state);
+static struct kobj_attribute rx_last_start_result = __ATTR_RO(rx_last_start_result);
+static struct kobj_attribute tx_state             = __ATTR_RO(tx_state);
+static struct kobj_attribute tx_last_start_result = __ATTR_RO(tx_last_start_result);
+static struct kobj_attribute info_map             = __ATTR_RO(info_map);
+
+static struct attribute *mac_attrs[] = {
+	&rx_state.attr,
+	&rx_last_start_result.attr,
+	&tx_state.attr,
+	&tx_last_start_result.attr,
+	&info_map.attr,
+	NULL
+};
+ATTRIBUTE_GROUPS(mac);
+
+static struct kobj_type mac_info = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = mac_groups,
+};
+#endif /* CONFIG_SYSFS */
+
+int sl_sysfs_mac_create(struct sl_ctrl_mac *ctrl_mac)
+{
+#ifdef CONFIG_SYSFS
+	int rtn;
+
+	sl_log_dbg(ctrl_mac, LOG_BLOCK, LOG_NAME, "mac create (num = %u)", ctrl_mac->num);
+
+	if (!ctrl_mac->parent_kobj) {
+		sl_log_err(ctrl_mac, LOG_BLOCK, LOG_NAME, "mac create missing parent");
+		return -EBADRQC;
+	}
+
+	rtn = kobject_init_and_add(&ctrl_mac->kobj, &mac_info, ctrl_mac->parent_kobj, "mac");
+	if (rtn) {
+		sl_log_err(ctrl_mac, LOG_BLOCK, LOG_NAME,
+			   "mac create kobject_init_and_add failed [%d]", rtn);
+		kobject_put(&ctrl_mac->kobj);
+		return rtn;
+	}
+
+	rtn = sl_sysfs_mac_counters_create(ctrl_mac);
+	if (rtn) {
+		sl_log_err(ctrl_mac, LOG_BLOCK, LOG_NAME, "sl_sysfs_mac_counters_create failed [%d]", rtn);
+		kobject_put(&ctrl_mac->kobj);
+		return rtn;
+	}
+
+	sl_log_dbg(ctrl_mac, LOG_BLOCK, LOG_NAME,
+		   "mac create (mac_kobj = 0x%p)", &ctrl_mac->kobj);
+
+	return 0;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_mac_delete(struct sl_ctrl_mac *ctrl_mac)
+{
+#ifdef CONFIG_SYSFS
+	sl_log_dbg(ctrl_mac, LOG_BLOCK, LOG_NAME, "delete (num = %u)", ctrl_mac->num);
+
+	if (!ctrl_mac->parent_kobj)
+		return;
+
+	sl_sysfs_mac_counters_delete(ctrl_mac);
+	kobject_put(&ctrl_mac->kobj);
+#endif /* CONFIG_SYSFS */
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_mac_counters.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_mac_counters.c
new file mode 100644
index 000000000000..97ab44983d8e
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_mac_counters.c
@@ -0,0 +1,339 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2025-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kobject.h>
+#include <linux/sysfs.h>
+
+#include "sl_sysfs.h"
+#include "sl_log.h"
+#include "sl_ctrl_mac.h"
+#include "sl_ctrl_mac_counters.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+#ifdef CONFIG_SYSFS
+static ssize_t mac_tx_start_cmd_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_mac *ctrl_mac;
+	u32                 count;
+	int		    rtn;
+
+	ctrl_mac = container_of(kobj, struct sl_ctrl_mac, counters_kobj);
+
+	rtn = sl_ctrl_mac_counter_get(ctrl_mac, MAC_TX_START_CMD, &count);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_mac, LOG_BLOCK, LOG_NAME, "mac tx start cmd show (count = %u)", count);
+
+	return sysfs_emit(buf, "%u\n", count);
+}
+
+static ssize_t mac_tx_started_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_mac *ctrl_mac;
+	u32                 count;
+	int		    rtn;
+
+	ctrl_mac = container_of(kobj, struct sl_ctrl_mac, counters_kobj);
+
+	rtn = sl_ctrl_mac_counter_get(ctrl_mac, MAC_TX_STARTED, &count);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_mac, LOG_BLOCK, LOG_NAME, "mac tx started show (count = %u)", count);
+
+	return sysfs_emit(buf, "%u\n", count);
+}
+
+static ssize_t mac_tx_start_fail_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_mac *ctrl_mac;
+	u32                 count;
+	int		    rtn;
+
+	ctrl_mac = container_of(kobj, struct sl_ctrl_mac, counters_kobj);
+
+	rtn = sl_ctrl_mac_counter_get(ctrl_mac, MAC_TX_START_FAIL, &count);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_mac, LOG_BLOCK, LOG_NAME, "mac tx start fail show (count = %u)", count);
+
+	return sysfs_emit(buf, "%u\n", count);
+}
+
+static ssize_t mac_tx_stop_cmd_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_mac *ctrl_mac;
+	u32                 count;
+	int		    rtn;
+
+	ctrl_mac = container_of(kobj, struct sl_ctrl_mac, counters_kobj);
+
+	rtn = sl_ctrl_mac_counter_get(ctrl_mac, MAC_TX_STOP_CMD, &count);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_mac, LOG_BLOCK, LOG_NAME, "mac tx stop cmd show (count = %u)", count);
+
+	return sysfs_emit(buf, "%u\n", count);
+}
+
+static ssize_t mac_tx_stopped_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_mac *ctrl_mac;
+	u32                 count;
+	int		    rtn;
+
+	ctrl_mac = container_of(kobj, struct sl_ctrl_mac, counters_kobj);
+
+	rtn = sl_ctrl_mac_counter_get(ctrl_mac, MAC_TX_STOPPED, &count);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_mac, LOG_BLOCK, LOG_NAME, "mac tx stopped show (count = %u)", count);
+
+	return sysfs_emit(buf, "%u\n", count);
+}
+
+static ssize_t mac_tx_stop_fail_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_mac *ctrl_mac;
+	u32                 count;
+	int		    rtn;
+
+	ctrl_mac = container_of(kobj, struct sl_ctrl_mac, counters_kobj);
+
+	rtn = sl_ctrl_mac_counter_get(ctrl_mac, MAC_TX_STOP_FAIL, &count);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_mac, LOG_BLOCK, LOG_NAME, "mac tx stop fail show (count = %u)", count);
+
+	return sysfs_emit(buf, "%u\n", count);
+}
+
+static ssize_t mac_rx_start_cmd_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_mac *ctrl_mac;
+	u32                 count;
+	int		    rtn;
+
+	ctrl_mac = container_of(kobj, struct sl_ctrl_mac, counters_kobj);
+
+	rtn = sl_ctrl_mac_counter_get(ctrl_mac, MAC_RX_START_CMD, &count);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_mac, LOG_BLOCK, LOG_NAME, "mac rx start cmd show (count = %u)", count);
+
+	return sysfs_emit(buf, "%u\n", count);
+}
+
+static ssize_t mac_rx_started_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_mac *ctrl_mac;
+	u32                 count;
+	int		    rtn;
+
+	ctrl_mac = container_of(kobj, struct sl_ctrl_mac, counters_kobj);
+
+	rtn = sl_ctrl_mac_counter_get(ctrl_mac, MAC_RX_STARTED, &count);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_mac, LOG_BLOCK, LOG_NAME, "mac rx started show (count = %u)", count);
+
+	return sysfs_emit(buf, "%u\n", count);
+}
+
+static ssize_t mac_rx_start_fail_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_mac *ctrl_mac;
+	u32                 count;
+	int		    rtn;
+
+	ctrl_mac = container_of(kobj, struct sl_ctrl_mac, counters_kobj);
+
+	rtn = sl_ctrl_mac_counter_get(ctrl_mac, MAC_RX_START_FAIL, &count);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_mac, LOG_BLOCK, LOG_NAME, "mac rx start fail show (count = %u)", count);
+
+	return sysfs_emit(buf, "%u\n", count);
+}
+
+static ssize_t mac_rx_stop_cmd_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_mac *ctrl_mac;
+	u32                 count;
+	int		    rtn;
+
+	ctrl_mac = container_of(kobj, struct sl_ctrl_mac, counters_kobj);
+
+	rtn = sl_ctrl_mac_counter_get(ctrl_mac, MAC_RX_STOP_CMD, &count);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_mac, LOG_BLOCK, LOG_NAME, "mac rx stop cmd show (count = %u)", count);
+
+	return sysfs_emit(buf, "%u\n", count);
+}
+
+static ssize_t mac_rx_stopped_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_mac *ctrl_mac;
+	u32                 count;
+	int		    rtn;
+
+	ctrl_mac = container_of(kobj, struct sl_ctrl_mac, counters_kobj);
+
+	rtn = sl_ctrl_mac_counter_get(ctrl_mac, MAC_RX_STOPPED, &count);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_mac, LOG_BLOCK, LOG_NAME, "mac rx stopped show (count = %u)", count);
+
+	return sysfs_emit(buf, "%u\n", count);
+}
+
+static ssize_t mac_rx_stop_fail_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_mac *ctrl_mac;
+	u32                 count;
+	int		    rtn;
+
+	ctrl_mac = container_of(kobj, struct sl_ctrl_mac, counters_kobj);
+
+	rtn = sl_ctrl_mac_counter_get(ctrl_mac, MAC_RX_STOP_FAIL, &count);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_mac, LOG_BLOCK, LOG_NAME, "mac rx stop fail show (count = %u)", count);
+
+	return sysfs_emit(buf, "%u\n", count);
+}
+
+static ssize_t mac_reset_cmd_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_mac *ctrl_mac;
+	u32                 count;
+	int		    rtn;
+
+	ctrl_mac = container_of(kobj, struct sl_ctrl_mac, counters_kobj);
+
+	rtn = sl_ctrl_mac_counter_get(ctrl_mac, MAC_RESET_CMD, &count);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_mac, LOG_BLOCK, LOG_NAME, "mac reset cmd show (count = %u)", count);
+
+	return sysfs_emit(buf, "%u\n", count);
+}
+
+static ssize_t mac_reset_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_mac *ctrl_mac;
+	u32                 count;
+	int		    rtn;
+
+	ctrl_mac = container_of(kobj, struct sl_ctrl_mac, counters_kobj);
+
+	rtn = sl_ctrl_mac_counter_get(ctrl_mac, MAC_RESET, &count);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_mac, LOG_BLOCK, LOG_NAME, "mac reset show (count = %u)", count);
+
+	return sysfs_emit(buf, "%u\n", count);
+}
+
+static ssize_t mac_reset_fail_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_mac *ctrl_mac;
+	u32                 count;
+	int		    rtn;
+
+	ctrl_mac = container_of(kobj, struct sl_ctrl_mac, counters_kobj);
+
+	rtn = sl_ctrl_mac_counter_get(ctrl_mac, MAC_RESET_FAIL, &count);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_mac, LOG_BLOCK, LOG_NAME, "mac reset fail show (count = %u)", count);
+
+	return sysfs_emit(buf, "%u\n", count);
+}
+
+static struct kobj_attribute mac_tx_start_cmd  = __ATTR_RO(mac_tx_start_cmd);
+static struct kobj_attribute mac_tx_started    = __ATTR_RO(mac_tx_started);
+static struct kobj_attribute mac_tx_start_fail = __ATTR_RO(mac_tx_start_fail);
+static struct kobj_attribute mac_tx_stop_cmd   = __ATTR_RO(mac_tx_stop_cmd);
+static struct kobj_attribute mac_tx_stopped    = __ATTR_RO(mac_tx_stopped);
+static struct kobj_attribute mac_tx_stop_fail  = __ATTR_RO(mac_tx_stop_fail);
+static struct kobj_attribute mac_rx_start_cmd  = __ATTR_RO(mac_rx_start_cmd);
+static struct kobj_attribute mac_rx_started    = __ATTR_RO(mac_rx_started);
+static struct kobj_attribute mac_rx_start_fail = __ATTR_RO(mac_rx_start_fail);
+static struct kobj_attribute mac_rx_stop_cmd   = __ATTR_RO(mac_rx_stop_cmd);
+static struct kobj_attribute mac_rx_stopped    = __ATTR_RO(mac_rx_stopped);
+static struct kobj_attribute mac_rx_stop_fail  = __ATTR_RO(mac_rx_stop_fail);
+static struct kobj_attribute mac_reset_cmd     = __ATTR_RO(mac_reset_cmd);
+static struct kobj_attribute mac_reset         = __ATTR_RO(mac_reset);
+static struct kobj_attribute mac_reset_fail    = __ATTR_RO(mac_reset_fail);
+
+static struct attribute *mac_counters_attrs[] = {
+	&mac_tx_start_cmd.attr,
+	&mac_tx_started.attr,
+	&mac_tx_start_fail.attr,
+	&mac_tx_stop_cmd.attr,
+	&mac_tx_stopped.attr,
+	&mac_tx_stop_fail.attr,
+	&mac_rx_start_cmd.attr,
+	&mac_rx_started.attr,
+	&mac_rx_start_fail.attr,
+	&mac_rx_stop_cmd.attr,
+	&mac_rx_stopped.attr,
+	&mac_rx_stop_fail.attr,
+	&mac_reset_cmd.attr,
+	&mac_reset.attr,
+	&mac_reset_fail.attr,
+	NULL
+};
+ATTRIBUTE_GROUPS(mac_counters);
+
+static struct kobj_type mac_counters = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = mac_counters_groups,
+};
+#endif /* CONFIG_SYSFS */
+
+int sl_sysfs_mac_counters_create(struct sl_ctrl_mac *ctrl_mac)
+{
+#ifdef CONFIG_SYSFS
+	int rtn;
+
+	sl_log_dbg(ctrl_mac, LOG_BLOCK, LOG_NAME, "mac counters create");
+
+	rtn = kobject_init_and_add(&ctrl_mac->counters_kobj, &mac_counters, &ctrl_mac->kobj, "counters");
+	if (rtn) {
+		sl_log_err(ctrl_mac, LOG_BLOCK, LOG_NAME, "mac counters create kobject_init_and_add failed [%d]", rtn);
+		kobject_put(&ctrl_mac->counters_kobj);
+		return rtn;
+	}
+
+	return 0;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_mac_counters_delete(struct sl_ctrl_mac *ctrl_mac)
+{
+#ifdef CONFIG_SYSFS
+	sl_log_dbg(ctrl_mac, LOG_BLOCK, LOG_NAME, "mac counters delete");
+	kobject_put(&ctrl_mac->counters_kobj);
+#endif /* CONFIG_SYSFS */
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_media.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_media.c
new file mode 100644
index 000000000000..8973fcc2f378
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_media.c
@@ -0,0 +1,1274 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2024-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kobject.h>
+#include <linux/sysfs.h>
+
+#include <linux/hpe/sl/sl_media.h>
+
+#include "sl_log.h"
+#include "sl_sysfs.h"
+#include "sl_core_str.h"
+#include "sl_core_lgrp.h"
+#include "sl_ctrl_lgrp.h"
+#include "sl_ctrl_ldev.h"
+#include "sl_media_lgrp.h"
+#include "sl_media_jack.h"
+#include "data/sl_media_data_jack.h"
+#include "base/sl_media_eeprom.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+#ifdef CONFIG_SYSFS
+static ssize_t state_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u8                    state;
+	int		      rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, kobj);
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+
+	rtn = sl_media_jack_state_get(media_lgrp->media_jack, &state);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "state show (media_lgrp = 0x%p, state = %u %s)",
+		   media_lgrp, state, sl_media_state_str(state));
+
+	return sysfs_emit(buf, "%s\n", sl_media_state_str(state));
+}
+
+static ssize_t jack_power_state_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	bool                  is_high_powered;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, kobj);
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+
+	if (!sl_media_jack_is_cable_online(media_lgrp->media_jack)) {
+		if (sl_media_jack_is_cable_format_unsupported(media_lgrp->media_jack))
+			return sysfs_emit(buf, "unsupported-format\n");
+		return sysfs_emit(buf, "no-cable\n");
+	}
+
+	is_high_powered = sl_media_jack_is_high_powered(media_lgrp->media_jack);
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "power state show (media_lgrp = 0x%p, state = %s)",
+		   media_lgrp, is_high_powered ? "high" : "low");
+
+	return sysfs_emit(buf, "%s\n", is_high_powered ? "high" : "low");
+}
+
+static ssize_t temperature_celsius_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                   rtn;
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u8                    temp;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, kobj);
+	ctrl_lgrp   = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+
+	if (!sl_media_jack_is_cable_online(media_lgrp->media_jack)) {
+		if (sl_media_jack_is_cable_format_unsupported(media_lgrp->media_jack))
+			return sysfs_emit(buf, "unsupported-format\n");
+		return sysfs_emit(buf, "no-cable\n");
+	}
+
+	rtn = sl_media_jack_cable_temp_get(media_lgrp->media_ldev->num, media_lgrp->num, &temp);
+	if (rtn == -EBADRQC)
+		return sysfs_emit(buf, "not-active\n");
+	if (rtn == -EIO)
+		return sysfs_emit(buf, "io-error\n");
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "temperature_celsius show (media_lgrp = 0x%p, temp = %uc)", media_lgrp, temp);
+
+	return sysfs_emit(buf, "%u\n", temp);
+}
+
+static ssize_t temperature_warn_limit_celsius_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                   rtn;
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u8                    temp_warn_limit_c;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, kobj);
+	ctrl_lgrp  = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+
+	if (!sl_media_jack_is_cable_online(media_lgrp->media_jack)) {
+		if (sl_media_jack_is_cable_format_unsupported(media_lgrp->media_jack))
+			return sysfs_emit(buf, "unsupported-format\n");
+		return sysfs_emit(buf, "no-cable\n");
+	}
+
+	rtn = sl_media_jack_cable_temp_warn_limit_get(media_lgrp->media_ldev->num,
+						      media_lgrp->num, &temp_warn_limit_c);
+
+	if (rtn == -EBADRQC)
+		return sysfs_emit(buf, "not-active\n");
+	if (rtn == -EIO)
+		return sysfs_emit(buf, "io-error\n");
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "temperature_warn_limit_celsius show (media_lgrp = 0x%p, temp = %uc)",
+		   media_lgrp, temp_warn_limit_c);
+
+	return sysfs_emit(buf, "%u\n", temp_warn_limit_c);
+}
+
+static ssize_t temperature_down_limit_celsius_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                   rtn;
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u8                    temp_down_limit_c;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, kobj);
+	ctrl_lgrp  = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+
+	if (!sl_media_jack_is_cable_online(media_lgrp->media_jack)) {
+		if (sl_media_jack_is_cable_format_unsupported(media_lgrp->media_jack))
+			return sysfs_emit(buf, "unsupported-format\n");
+		return sysfs_emit(buf, "no-cable\n");
+	}
+
+	rtn = sl_media_jack_cable_temp_down_limit_get(media_lgrp->media_ldev->num,
+						      media_lgrp->num, &temp_down_limit_c);
+
+	if (rtn == -EBADRQC)
+		return sysfs_emit(buf, "not-active\n");
+	if (rtn == -EIO)
+		return sysfs_emit(buf, "io-error\n");
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "temperature_down_limit_celsius show (media_lgrp = 0x%p, temp = %uc)",
+		   media_lgrp, temp_down_limit_c);
+
+	return sysfs_emit(buf, "%u\n", temp_down_limit_c);
+}
+
+static ssize_t temperature_state_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u8                    temperature_state;
+	int		      rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, kobj);
+	ctrl_lgrp   = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+
+	if (!sl_media_jack_is_cable_online(media_lgrp->media_jack)) {
+		if (sl_media_jack_is_cable_format_unsupported(media_lgrp->media_jack))
+			return sysfs_emit(buf, "unsupported-format\n");
+		return sysfs_emit(buf, "no-cable\n");
+	}
+
+	if (!sl_media_lgrp_media_type_is_active(media_lgrp->media_ldev->num, media_lgrp->num))
+		return sysfs_emit(buf, "not-active\n");
+
+	rtn  = sl_media_jack_cable_temp_state_get(media_lgrp->media_jack, &temperature_state);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "temperature state show (media_lgrp = 0x%p, temperature_state = %u %s)",
+		   media_lgrp, temperature_state, sl_media_temp_state_str(temperature_state));
+
+	return sysfs_emit(buf, "%s\n", sl_media_temp_state_str(temperature_state));
+}
+
+static ssize_t vendor_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u32                   vendor;
+	int		      rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, kobj);
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+
+	if (!sl_media_jack_is_cable_online(media_lgrp->media_jack)) {
+		if (sl_media_jack_is_cable_format_unsupported(media_lgrp->media_jack))
+			return sysfs_emit(buf, "unsupported-format\n");
+		return sysfs_emit(buf, "no-cable\n");
+	}
+
+	rtn = sl_media_lgrp_vendor_get(media_lgrp, &vendor);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "vendor show (media_lgrp = 0x%p, vendor = %u %s)",
+		   media_lgrp, vendor, sl_media_vendor_str(vendor));
+
+	return sysfs_emit(buf, "%s\n", sl_media_vendor_str(vendor));
+}
+
+static ssize_t vendor_part_num_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	char                  vendor_pn_str[SL_MEDIA_VENDOR_PN_SIZE];
+	int		      rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, kobj);
+	ctrl_lgrp  = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+
+	if (!sl_media_jack_is_cable_online(media_lgrp->media_jack)) {
+		if (sl_media_jack_is_cable_format_unsupported(media_lgrp->media_jack))
+			return sysfs_emit(buf, "unsupported-format\n");
+		return sysfs_emit(buf, "no-cable\n");
+	}
+
+	rtn = sl_media_lgrp_vendor_pn_str_get(media_lgrp, vendor_pn_str);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "vendor part num show (media_lgrp = 0x%p, vendor_pn_str = %s)",
+		   media_lgrp, vendor_pn_str);
+
+	return sysfs_emit(buf, "%s\n", vendor_pn_str);
+}
+
+static ssize_t type_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u32                   type;
+	int		      rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, kobj);
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+
+	if (!sl_media_jack_is_cable_online(media_lgrp->media_jack)) {
+		if (sl_media_jack_is_cable_format_unsupported(media_lgrp->media_jack))
+			return sysfs_emit(buf, "unsupported-format\n");
+		return sysfs_emit(buf, "no-cable\n");
+	}
+
+	rtn = sl_media_lgrp_type_get(media_lgrp, &type);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "type show (media_lgrp = 0x%p, type = %u %s)",
+		   media_lgrp, type, sl_media_type_str(type));
+
+	return sysfs_emit(buf, "%s\n", sl_media_type_str(type));
+}
+
+static ssize_t shape_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u32                   shape;
+	int		      rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, kobj);
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+
+	if (!sl_media_jack_is_cable_online(media_lgrp->media_jack)) {
+		if (sl_media_jack_is_cable_format_unsupported(media_lgrp->media_jack))
+			return sysfs_emit(buf, "unsupported-format\n");
+		return sysfs_emit(buf, "no-cable\n");
+	}
+
+	rtn = sl_media_lgrp_shape_get(media_lgrp, &shape);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "shape show (media_lgrp = 0x%p, shape = %u %s)", media_lgrp, shape, sl_media_shape_str(shape));
+
+	return sysfs_emit(buf, "%s\n", sl_media_shape_str(shape));
+}
+
+static ssize_t cable_end_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u8                    cable_end;
+	int		      rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, kobj);
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+
+	if (!sl_media_jack_is_cable_online(media_lgrp->media_jack)) {
+		if (sl_media_jack_is_cable_format_unsupported(media_lgrp->media_jack))
+			return sysfs_emit(buf, "unsupported-format\n");
+		return sysfs_emit(buf, "no-cable\n");
+	}
+
+	rtn = sl_media_jack_cable_end_get(media_lgrp->media_jack, &cable_end);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "cable_end show (media_lgrp = 0x%p, cable_end = %u %s)",
+		media_lgrp, cable_end, sl_media_cable_end_str(cable_end));
+
+	return sysfs_emit(buf, "%s\n", sl_media_cable_end_str(cable_end));
+}
+
+static ssize_t length_cm_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u32                   length_cm;
+	int		      rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, kobj);
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+
+	if (!sl_media_jack_is_cable_online(media_lgrp->media_jack)) {
+		if (sl_media_jack_is_cable_format_unsupported(media_lgrp->media_jack))
+			return sysfs_emit(buf, "unsupported-format\n");
+		return sysfs_emit(buf, "no-cable\n");
+	}
+
+	rtn = sl_media_lgrp_length_get(media_lgrp, &length_cm);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "length_cm show (media_lgrp = 0x%p, length_cm = %u)",
+		   media_lgrp, length_cm);
+
+	return sysfs_emit(buf, "%u\n", length_cm);
+}
+
+static ssize_t max_speed_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u32                   max_speed;
+	int		      rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, kobj);
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+
+	if (!sl_media_jack_is_cable_online(media_lgrp->media_jack)) {
+		if (sl_media_jack_is_cable_format_unsupported(media_lgrp->media_jack))
+			return sysfs_emit(buf, "unsupported-format\n");
+		return sysfs_emit(buf, "no-cable\n");
+	}
+
+	rtn = sl_media_lgrp_max_speed_get(media_lgrp, &max_speed);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "max speed show (media_lgrp = 0x%p, max_speed = %u %s)",
+		   media_lgrp, max_speed, sl_media_speed_str(max_speed));
+
+	return sysfs_emit(buf, "%s\n", sl_media_speed_str(max_speed));
+}
+
+static ssize_t serial_num_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	char                  serial_num_str[SL_MEDIA_SERIAL_NUM_SIZE];
+	int		      rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, kobj);
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+
+	if (!sl_media_jack_is_cable_online(media_lgrp->media_jack)) {
+		if (sl_media_jack_is_cable_format_unsupported(media_lgrp->media_jack))
+			return sysfs_emit(buf, "unsupported-format\n");
+		return sysfs_emit(buf, "no-cable\n");
+	}
+
+	rtn = sl_media_lgrp_serial_num_str_get(media_lgrp, serial_num_str);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "serial num show (media_lgrp = 0x%p, serial_num = %s)",
+		   media_lgrp, serial_num_str);
+
+	return sysfs_emit(buf, "%s\n", serial_num_str);
+}
+
+static ssize_t hpe_part_num_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	char                  hpe_pn_str[SL_MEDIA_HPE_PN_SIZE];
+	int		      rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, kobj);
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+
+	if (!sl_media_jack_is_cable_online(media_lgrp->media_jack)) {
+		if (sl_media_jack_is_cable_format_unsupported(media_lgrp->media_jack))
+			return sysfs_emit(buf, "unsupported-format\n");
+		return sysfs_emit(buf, "no-cable\n");
+	}
+
+	rtn = sl_media_lgrp_hpe_pn_str_get(media_lgrp, hpe_pn_str);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "hpe part num show (media_lgrp = 0x%p, hpe_pn = %s)",
+		   media_lgrp, hpe_pn_str);
+
+	return sysfs_emit(buf, "%s\n", hpe_pn_str);
+}
+
+static ssize_t jack_num_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, kobj);
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "jack_num show (media_lgrp = 0x%p, jack_num = %u)",
+		media_lgrp, media_lgrp->media_jack->physical_num);
+
+	return sysfs_emit(buf, "%u\n", media_lgrp->media_jack->physical_num);
+}
+
+static ssize_t jack_type_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u32                   density;
+	u32                   jack_type;
+	int		      rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, kobj);
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+
+	if (!sl_media_jack_is_cable_online(media_lgrp->media_jack)) {
+		if (sl_media_jack_is_cable_format_unsupported(media_lgrp->media_jack))
+			return sysfs_emit(buf, "unsupported-format\n");
+		return sysfs_emit(buf, "no-cable\n");
+	}
+
+	rtn = sl_media_lgrp_jack_type_get(media_lgrp, &jack_type);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	rtn = sl_media_lgrp_jack_type_qsfp_density_get(media_lgrp, &density);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "jack type show (media_lgrp = 0x%p, jack_type = %u %s)",
+		   media_lgrp, jack_type, sl_media_jack_type_str(jack_type, density));
+
+	return sysfs_emit(buf, "%s\n", sl_media_jack_type_str(jack_type, density));
+}
+
+static ssize_t furcation_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u32                   furcation;
+	int		      rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, kobj);
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+
+	if (!sl_media_jack_is_cable_online(media_lgrp->media_jack)) {
+		if (sl_media_jack_is_cable_format_unsupported(media_lgrp->media_jack))
+			return sysfs_emit(buf, "unsupported-format\n");
+		return sysfs_emit(buf, "no-cable\n");
+	}
+
+	rtn = sl_media_lgrp_furcation_get(media_lgrp, &furcation);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "furcation show (media_lgrp = 0x%p, furcation = %u %s)",
+		   media_lgrp, furcation, sl_media_furcation_str(furcation));
+
+	return sysfs_emit(buf, "%s\n", sl_media_furcation_str(furcation));
+}
+
+static ssize_t is_supported_cable_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	bool                  unsupported;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, kobj);
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+
+	if (!sl_media_jack_is_cable_online(media_lgrp->media_jack)) {
+		if (sl_media_jack_is_cable_format_unsupported(media_lgrp->media_jack))
+			return sysfs_emit(buf, "unsupported-format\n");
+		return sysfs_emit(buf, "no-cable\n");
+	}
+
+	unsupported = sl_media_lgrp_is_cable_unsupported(media_lgrp);
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "is_supported_cable show (media_lgrp = 0x%p, is_supported_cable = %s)",
+		   media_lgrp, unsupported ? "no" : "yes");
+
+	return sysfs_emit(buf, "%s\n", unsupported ? "no" : "yes");
+}
+
+static ssize_t date_code_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	char                  date_code_str[SL_MEDIA_DATE_CODE_SIZE];
+	int		      rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, kobj);
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+
+	if (!sl_media_jack_is_cable_online(media_lgrp->media_jack)) {
+		if (sl_media_jack_is_cable_format_unsupported(media_lgrp->media_jack))
+			return sysfs_emit(buf, "unsupported-format\n");
+		return sysfs_emit(buf, "no-cable\n");
+	}
+
+	rtn = sl_media_lgrp_date_code_str_get(media_lgrp, date_code_str);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "date code show (media_lgrp = 0x%p, date_code = %s)",
+		   media_lgrp, date_code_str);
+
+	return sysfs_emit(buf, "%s\n", date_code_str);
+}
+
+static ssize_t firmware_version_hex_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u8                    fw_ver[SL_MEDIA_FIRMWARE_VERSION_SIZE];
+	int		      rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, kobj);
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+
+	if (!sl_media_jack_is_cable_online(media_lgrp->media_jack)) {
+		if (sl_media_jack_is_cable_format_unsupported(media_lgrp->media_jack))
+			return sysfs_emit(buf, "unsupported-format\n");
+		return sysfs_emit(buf, "no-cable\n");
+	}
+
+	rtn = sl_media_lgrp_fw_ver_str_get(media_lgrp, fw_ver);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "firmware version hex show (media_lgrp = 0x%p, firmware_version_hex = %02X.%02X)",
+		media_lgrp, fw_ver[0], fw_ver[1]);
+
+	return sysfs_emit(buf, "%02X.%02X\n", fw_ver[0], fw_ver[1]);
+}
+
+static ssize_t target_firmware_version_hex_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u8                    target_fw_ver_str[25];
+	int		      rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, kobj);
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+
+	if (!sl_media_jack_is_cable_online(media_lgrp->media_jack)) {
+		if (sl_media_jack_is_cable_format_unsupported(media_lgrp->media_jack))
+			return sysfs_emit(buf, "unsupported-format\n");
+		return sysfs_emit(buf, "no-cable\n");
+	}
+
+	rtn = sl_media_eeprom_target_fw_ver_str_get(media_lgrp->media_jack, target_fw_ver_str, sizeof(target_fw_ver_str));
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "target firmware version hex show (media_lgrp = 0x%p, target_firmware_version_hex = %s)",
+		media_lgrp, target_fw_ver_str);
+
+	return sysfs_emit(buf, "%s\n", target_fw_ver_str);
+}
+
+static ssize_t cable_speed_state_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u8                    cable_speed_state;
+	int		      rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, kobj);
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+
+	if (!sl_media_jack_is_cable_online(media_lgrp->media_jack)) {
+		if (sl_media_jack_is_cable_format_unsupported(media_lgrp->media_jack))
+			return sysfs_emit(buf, "unsupported-format\n");
+		return sysfs_emit(buf, "no-cable\n");
+	}
+
+	rtn = sl_media_jack_cable_shift_state_get(media_lgrp->media_jack, &cable_speed_state);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "cable_speed state show (media_lgrp = 0x%p, cable_speed_state = %u %s)",
+		   media_lgrp, cable_speed_state, sl_media_cable_speed_state_str(cable_speed_state));
+
+	return sysfs_emit(buf, "%s\n", sl_media_cable_speed_state_str(cable_speed_state));
+}
+
+static ssize_t active_cable_200g_host_interface_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u8                    host_interface;
+	int		      rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, kobj);
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+
+	if (!sl_media_jack_is_cable_online(media_lgrp->media_jack)) {
+		if (sl_media_jack_is_cable_format_unsupported(media_lgrp->media_jack))
+			return sysfs_emit(buf, "unsupported-format\n");
+		return sysfs_emit(buf, "no-cable\n");
+	}
+
+	rtn = sl_media_jack_active_cable_200g_host_interface_get(media_lgrp->media_jack, &host_interface);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "active cable 200g host interface show (media_lgrp = 0x%p, host_interface = 0x%X)",
+		   media_lgrp, host_interface);
+
+	return sysfs_emit(buf, "0x%02x\n", host_interface);
+}
+
+static ssize_t active_cable_200g_lane_count_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u8                    lane_count;
+	int		      rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, kobj);
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+
+	if (!sl_media_jack_is_cable_online(media_lgrp->media_jack)) {
+		if (sl_media_jack_is_cable_format_unsupported(media_lgrp->media_jack))
+			return sysfs_emit(buf, "unsupported-format\n");
+		return sysfs_emit(buf, "no-cable\n");
+	}
+
+	rtn = sl_media_jack_active_cable_200g_lane_count_get(media_lgrp->media_jack, &lane_count);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "active cable 200g lane coiunt show (media_lgrp = 0x%p, lane_count = 0x%X)",
+		   media_lgrp, lane_count);
+
+	return sysfs_emit(buf, "0x%02x\n", lane_count);
+}
+
+static ssize_t active_cable_200g_appsel_num_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u8                    appsel_num;
+	int rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, kobj);
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+
+	if (!sl_media_jack_is_cable_online(media_lgrp->media_jack)) {
+		if (sl_media_jack_is_cable_format_unsupported(media_lgrp->media_jack))
+			return sysfs_emit(buf, "unsupported-format\n");
+		return sysfs_emit(buf, "no-cable\n");
+	}
+
+	rtn = sl_media_jack_active_cable_200g_appsel_num_get(media_lgrp->media_jack, &appsel_num);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "active cable 200g appsel no show (media_lgrp = 0x%p, appsel_num = 0x%X)", media_lgrp, appsel_num);
+
+	return sysfs_emit(buf, "0x%02x\n", appsel_num);
+}
+
+static ssize_t active_cable_400g_host_interface_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u8                    host_interface;
+	int		      rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, kobj);
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+
+	if (!sl_media_jack_is_cable_online(media_lgrp->media_jack)) {
+		if (sl_media_jack_is_cable_format_unsupported(media_lgrp->media_jack))
+			return sysfs_emit(buf, "unsupported-format\n");
+		return sysfs_emit(buf, "no-cable\n");
+	}
+
+	rtn = sl_media_jack_active_cable_400g_host_interface_get(media_lgrp->media_jack, &host_interface);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "active cable 400g host interface show (media_lgrp = 0x%p, host_interface = 0x%X)",
+		   media_lgrp, host_interface);
+
+	return sysfs_emit(buf, "0x%02x\n", host_interface);
+}
+
+static ssize_t active_cable_400g_lane_count_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u8                    lane_count;
+	int		      rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, kobj);
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+
+	if (!sl_media_jack_is_cable_online(media_lgrp->media_jack)) {
+		if (sl_media_jack_is_cable_format_unsupported(media_lgrp->media_jack))
+			return sysfs_emit(buf, "unsupported-format\n");
+		return sysfs_emit(buf, "no-cable\n");
+	}
+
+	rtn = sl_media_jack_active_cable_400g_lane_count_get(media_lgrp->media_jack, &lane_count);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "active cable 400g lane count show (media_lgrp = 0x%p, lane_count = 0x%X)",
+		   media_lgrp, lane_count);
+
+	return sysfs_emit(buf, "0x%02x\n", lane_count);
+}
+
+static ssize_t active_cable_400g_appsel_num_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u8                    appsel_num;
+	int		      rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, kobj);
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+
+	if (!sl_media_jack_is_cable_online(media_lgrp->media_jack)) {
+		if (sl_media_jack_is_cable_format_unsupported(media_lgrp->media_jack))
+			return sysfs_emit(buf, "unsupported-format\n");
+		return sysfs_emit(buf, "no-cable\n");
+	}
+
+	rtn = sl_media_jack_active_cable_400g_appsel_num_get(media_lgrp->media_jack, &appsel_num);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "active cable 400g appsel no show (media_lgrp = 0x%p, appsel_num = 0x%X)", media_lgrp, appsel_num);
+
+	return sysfs_emit(buf, "0x%02x\n", appsel_num);
+}
+
+static ssize_t last_fault_cause_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u32                   fault_cause;
+	time64_t              fault_time;
+	int		      rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, kobj);
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+
+	rtn = sl_media_jack_fault_cause_get(media_lgrp->media_jack, &fault_cause, &fault_time);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "last_fault cause show (cause = %u %s)", fault_cause,
+		   sl_media_fault_cause_str(fault_cause));
+
+	if (fault_cause == SL_MEDIA_FAULT_CAUSE_NONE)
+		return sysfs_emit(buf, "no-fault\n");
+
+	return sysfs_emit(buf, "%s\n", sl_media_fault_cause_str(fault_cause));
+}
+
+static ssize_t last_fault_time_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u32                   fault_cause;
+	time64_t              fault_time;
+	int		      rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, kobj);
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+
+	rtn = sl_media_jack_fault_cause_get(media_lgrp->media_jack, &fault_cause, &fault_time);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "last fault time show (cause = %u %s, time = %lld %ptTt %ptTd)",
+		fault_cause, sl_media_fault_cause_str(fault_cause),
+		fault_time, &fault_time, &fault_time);
+
+	if (fault_cause == SL_MEDIA_FAULT_CAUSE_NONE)
+		return sysfs_emit(buf, "no-fault\n");
+
+	return sysfs_emit(buf, "%ptTt %ptTd\n", &fault_time, &fault_time);
+}
+
+static ssize_t is_supported_ss200_cable_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, kobj);
+
+	sl_log_dbg(media_lgrp, LOG_BLOCK, LOG_NAME,
+		   "is supported ss200 cable show (is_supported_ss200_cable = %s)",
+		media_lgrp->media_jack->is_supported_ss200_cable ? "yes" : "no");
+
+	if (media_lgrp->media_jack->is_supported_ss200_cable)
+		return sysfs_emit(buf, "yes\n");
+
+	return sysfs_emit(buf, "no\n");
+}
+
+static ssize_t jack_part_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	u8                    ldev_num;
+	u8                    lgrp_num;
+	u32                   jack_part;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, kobj);
+	ldev_num = media_lgrp->media_ldev->num;
+	lgrp_num = media_lgrp->num;
+
+	jack_part = sl_core_lgrp_jack_part_get(ldev_num, lgrp_num);
+
+	sl_log_dbg(media_lgrp, LOG_BLOCK, LOG_NAME,
+		   "jack part show (jack_part = %u %s)", jack_part, sl_core_lgrp_dt_jack_part_str(jack_part));
+
+	return sysfs_emit(buf, "%s\n", sl_core_lgrp_dt_jack_part_str(jack_part));
+}
+
+static ssize_t signal_cache_time_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                  rtn;
+	struct sl_media_lgrp *media_lgrp;
+	u8                   ldev_num;
+	u8                   lgrp_num;
+	time64_t             signal_cache_time_s;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, kobj);
+	ldev_num = media_lgrp->media_ldev->num;
+	lgrp_num = media_lgrp->num;
+
+	rtn = sl_media_jack_signal_cache_time_s_get(ldev_num, lgrp_num, &signal_cache_time_s);
+	if (rtn) {
+		sl_log_err_trace(media_lgrp, LOG_BLOCK, LOG_NAME, "signal cache time show failed [%d]", rtn);
+		return sysfs_emit(buf, "no-cache\n");
+	}
+
+	sl_log_dbg(media_lgrp, LOG_BLOCK, LOG_NAME,
+		   "signal cache time show (signal_cache_time_s = %llu)", signal_cache_time_s);
+
+	return sysfs_emit(buf, "%ptTt %ptTd\n", &signal_cache_time_s, &signal_cache_time_s);
+}
+
+static ssize_t error_info_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                   rtn;
+	u32                   error_map;
+	struct sl_media_lgrp *media_lgrp;
+	char                  error_str[SL_MEDIA_JACK_ATTR_ERR_STR_SIZE];
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, kobj);
+
+	rtn = sl_media_jack_attr_error_map_get(media_lgrp->media_jack, &error_map);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	rtn = sl_media_jack_attr_error_map_str(error_map, error_str, sizeof(error_str));
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(media_lgrp, LOG_BLOCK, LOG_NAME,
+		   "error info show (error_map = 0x%x %s)", error_map, error_str);
+
+	return sysfs_emit(buf, "%s\n", error_str);
+}
+
+static struct kobj_attribute media_state                            = __ATTR_RO(state);
+static struct kobj_attribute media_jack_power_state                 = __ATTR_RO(jack_power_state);
+static struct kobj_attribute media_temperature_celsius              = __ATTR_RO(temperature_celsius);
+static struct kobj_attribute media_temperature_warn_limit_celsius   = __ATTR_RO(temperature_warn_limit_celsius);
+static struct kobj_attribute media_temperature_down_limit_celsius   = __ATTR_RO(temperature_down_limit_celsius);
+static struct kobj_attribute media_temperature_state                = __ATTR_RO(temperature_state);
+static struct kobj_attribute media_vendor                           = __ATTR_RO(vendor);
+static struct kobj_attribute media_vendor_part_num                  = __ATTR_RO(vendor_part_num);
+static struct kobj_attribute media_type                             = __ATTR_RO(type);
+static struct kobj_attribute media_shape                            = __ATTR_RO(shape);
+static struct kobj_attribute media_cable_end                        = __ATTR_RO(cable_end);
+static struct kobj_attribute media_length_cm                        = __ATTR_RO(length_cm);
+static struct kobj_attribute media_max_speed                        = __ATTR_RO(max_speed);
+static struct kobj_attribute media_serial_num                       = __ATTR_RO(serial_num);
+static struct kobj_attribute media_hpe_part_num                     = __ATTR_RO(hpe_part_num);
+static struct kobj_attribute media_jack_num                         = __ATTR_RO(jack_num);
+static struct kobj_attribute media_jack_type                        = __ATTR_RO(jack_type);
+static struct kobj_attribute media_furcation                        = __ATTR_RO(furcation);
+static struct kobj_attribute media_is_supported_cable               = __ATTR_RO(is_supported_cable);
+static struct kobj_attribute media_date_code                        = __ATTR_RO(date_code);
+static struct kobj_attribute media_firmware_version_hex             = __ATTR_RO(firmware_version_hex);
+static struct kobj_attribute media_target_firmware_version_hex      = __ATTR_RO(target_firmware_version_hex);
+static struct kobj_attribute media_cable_speed_state                = __ATTR_RO(cable_speed_state);
+static struct kobj_attribute media_active_cable_200g_host_interface = __ATTR_RO(active_cable_200g_host_interface);
+static struct kobj_attribute media_active_cable_200g_lane_count     = __ATTR_RO(active_cable_200g_lane_count);
+static struct kobj_attribute media_active_cable_200g_appsel_num     = __ATTR_RO(active_cable_200g_appsel_num);
+static struct kobj_attribute media_active_cable_400g_host_interface = __ATTR_RO(active_cable_400g_host_interface);
+static struct kobj_attribute media_active_cable_400g_lane_count     = __ATTR_RO(active_cable_400g_lane_count);
+static struct kobj_attribute media_active_cable_400g_appsel_num     = __ATTR_RO(active_cable_400g_appsel_num);
+static struct kobj_attribute media_last_fault_cause                 = __ATTR_RO(last_fault_cause);
+static struct kobj_attribute media_last_fault_time                  = __ATTR_RO(last_fault_time);
+static struct kobj_attribute media_is_supported_ss200_cable         = __ATTR_RO(is_supported_ss200_cable);
+static struct kobj_attribute media_jack_part                        = __ATTR_RO(jack_part);
+static struct kobj_attribute media_signal_cache_time                = __ATTR_RO(signal_cache_time);
+static struct kobj_attribute media_error_info                       = __ATTR_RO(error_info);
+
+static struct attribute *media_attrs[] = {
+	&media_state.attr,
+	&media_jack_power_state.attr,
+	&media_temperature_celsius.attr,
+	&media_temperature_warn_limit_celsius.attr,
+	&media_temperature_down_limit_celsius.attr,
+	&media_temperature_state.attr,
+	&media_vendor.attr,
+	&media_vendor_part_num.attr,
+	&media_type.attr,
+	&media_shape.attr,
+	&media_cable_end.attr,
+	&media_length_cm.attr,
+	&media_max_speed.attr,
+	&media_serial_num.attr,
+	&media_hpe_part_num.attr,
+	&media_jack_num.attr,
+	&media_jack_type.attr,
+	&media_furcation.attr,
+	&media_is_supported_cable.attr,
+	&media_date_code.attr,
+	&media_firmware_version_hex.attr,
+	&media_target_firmware_version_hex.attr,
+	&media_cable_speed_state.attr,
+	&media_active_cable_200g_host_interface.attr,
+	&media_active_cable_200g_lane_count.attr,
+	&media_active_cable_200g_appsel_num.attr,
+	&media_active_cable_400g_host_interface.attr,
+	&media_active_cable_400g_lane_count.attr,
+	&media_active_cable_400g_appsel_num.attr,
+	&media_last_fault_cause.attr,
+	&media_last_fault_time.attr,
+	&media_is_supported_ss200_cable.attr,
+	&media_jack_part.attr,
+	&media_signal_cache_time.attr,
+	&media_error_info.attr,
+	NULL
+};
+ATTRIBUTE_GROUPS(media);
+
+static struct kobj_type media_info = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = media_groups,
+};
+
+static ssize_t host_interface_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp_speed_kobject *speed_kobj;
+	struct sl_ctrl_lgrp                *ctrl_lgrp;
+	u32                                 speed;
+	u32                                 type;
+	int				    rtn;
+
+	speed_kobj = container_of(kobj, struct sl_media_lgrp_speed_kobject, kobj);
+
+	ctrl_lgrp = sl_ctrl_lgrp_get(speed_kobj->media_lgrp->media_ldev->num, speed_kobj->media_lgrp->num);
+
+	if (!sl_media_jack_is_cable_online(speed_kobj->media_lgrp->media_jack)) {
+		if (sl_media_jack_is_cable_format_unsupported(speed_kobj->media_lgrp->media_jack))
+			return sysfs_emit(buf, "unsupported-format\n");
+		return sysfs_emit(buf, "no-cable\n");
+	}
+
+	rtn = sl_media_lgrp_type_get(speed_kobj->media_lgrp, &type);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	speed = speed_kobj->speed;
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "host interface show (media_lgrp = 0x%p, host_interface = %s)",
+		speed_kobj->media_lgrp, sl_media_host_interface_str(speed, type));
+
+	return sysfs_emit(buf, "%s\n", sl_media_host_interface_str(speed, type));
+}
+
+static ssize_t projected_ber_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp_speed_kobject *speed_kobj;
+	struct sl_ctrl_lgrp                *ctrl_lgrp;
+	u8                                  media_interface;
+	u32                                 type;
+	int				    rtn;
+
+	speed_kobj = container_of(kobj, struct sl_media_lgrp_speed_kobject, kobj);
+
+	ctrl_lgrp = sl_ctrl_lgrp_get(speed_kobj->media_lgrp->media_ldev->num, speed_kobj->media_lgrp->num);
+
+	if (!sl_media_jack_is_cable_online(speed_kobj->media_lgrp->media_jack)) {
+		if (sl_media_jack_is_cable_format_unsupported(speed_kobj->media_lgrp->media_jack))
+			return sysfs_emit(buf, "unsupported-format\n");
+		return sysfs_emit(buf, "no-cable\n");
+	}
+
+	rtn = sl_media_lgrp_type_get(speed_kobj->media_lgrp, &type);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	if (type == SL_MEDIA_TYPE_PEC || type == SL_MEDIA_TYPE_BKP) {
+		sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+			   "projected_ber show (media_lgrp = 0x%p, projected_ber = 0)", speed_kobj->media_lgrp);
+		return sysfs_emit(buf, "0\n");
+	}
+
+	rtn = sl_media_eeprom_media_interface_get(speed_kobj->media_lgrp->media_jack, &media_interface);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "projected_ber show (media_lgrp = 0x%p, projected_ber = %s)",
+		   speed_kobj->media_lgrp, sl_media_ber_str(media_interface));
+
+	return sysfs_emit(buf, "%s\n", sl_media_ber_str(media_interface));
+}
+
+static struct kobj_attribute media_speed_host_interface = __ATTR_RO(host_interface);
+static struct kobj_attribute media_speed_projected_ber  = __ATTR_RO(projected_ber);
+
+static struct attribute *media_speed_attrs[] = {
+	&media_speed_host_interface.attr,
+	&media_speed_projected_ber.attr,
+	NULL
+};
+ATTRIBUTE_GROUPS(media_speed);
+
+static struct kobj_type media_speed_info = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = media_speed_groups,
+};
+
+static void parent_speed_release(struct kobject *kobj)
+{
+}
+
+static struct kobj_type parent_speed_info = {
+	.release = parent_speed_release,
+};
+#endif /* CONFIG_SYSFS */
+
+int sl_sysfs_media_create(struct sl_ctrl_lgrp *ctrl_lgrp)
+{
+#ifdef CONFIG_SYSFS
+	int                   rtn;
+	u8                    state;
+	struct sl_media_lgrp *media_lgrp;
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "media create");
+
+	if (!ctrl_lgrp->parent_kobj) {
+		sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "media create missing parent");
+		return 0;
+	}
+
+	media_lgrp = sl_media_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!media_lgrp) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "media_lgrp_get failed");
+		return -EFAULT;
+	}
+
+	rtn = kobject_init_and_add(&media_lgrp->kobj, &media_info, ctrl_lgrp->parent_kobj, "media");
+	if (rtn) {
+		kobject_put(&media_lgrp->kobj);
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "kobject_init_and_add failed [%d]", rtn);
+		return rtn;
+	}
+
+	rtn = kobject_init_and_add(&media_lgrp->parent_speed_kobj, &parent_speed_info, &media_lgrp->kobj, "speeds");
+	if (rtn) {
+		kobject_put(&media_lgrp->parent_speed_kobj);
+		kobject_put(&media_lgrp->kobj);
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "kobject_init_and_add failed [%d]", rtn);
+		return rtn;
+	}
+
+	rtn = sl_sysfs_media_counters_create(ctrl_lgrp);
+	if (rtn) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "media counters create failed [%d]", rtn);
+		goto out_parents;
+	}
+
+	/*
+	 * This if condition will be false for nic here
+	 */
+	rtn = sl_media_jack_state_get(media_lgrp->media_jack, &state);
+	if (rtn) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "media_jack_state_get failed [%d]", rtn);
+		goto out_counters;
+	}
+
+	if (state == SL_MEDIA_JACK_CABLE_ONLINE) {
+		/*
+		 * kobj cleanup in the callee function
+		 */
+		rtn = sl_sysfs_media_speeds_create(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+		if (rtn) {
+			sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "media speeds create failed [%d]", rtn);
+			goto out_counters;
+		}
+	}
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "create (media_kobj = 0x%p)", &media_lgrp->kobj);
+
+	return 0;
+out_counters:
+	sl_sysfs_media_counters_delete(ctrl_lgrp);
+out_parents:
+	kobject_put(&media_lgrp->parent_speed_kobj);
+	kobject_put(&media_lgrp->kobj);
+	return rtn;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+int sl_sysfs_media_speeds_create(u8 ldev_num, u8 lgrp_num)
+{
+#ifdef CONFIG_SYSFS
+	int                   rtn;
+	int                   i;
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+
+	media_lgrp = sl_media_lgrp_get(ldev_num, lgrp_num);
+	ctrl_lgrp = sl_ctrl_lgrp_get(ldev_num, lgrp_num);
+
+	if (media_lgrp->speeds_kobj_init)
+		return 0;
+
+	media_lgrp->supported_speeds_num = 0;
+	if (media_lgrp->cable_info->real_cable_status == CABLE_MEDIA_ATTR_ADDED) {
+		for_each_set_bit(i, &media_lgrp->cable_info->media_attr.speeds_map,
+				 sizeof(media_lgrp->cable_info->media_attr.speeds_map) * BITS_PER_BYTE) {
+			media_lgrp->speeds_kobj[media_lgrp->supported_speeds_num].media_lgrp = media_lgrp;
+			media_lgrp->speeds_kobj[media_lgrp->supported_speeds_num].speed = BIT(i);
+			rtn = kobject_init_and_add(&media_lgrp->speeds_kobj[media_lgrp->supported_speeds_num].kobj,
+						   &media_speed_info, &media_lgrp->parent_speed_kobj, sl_media_speed_str(BIT(i)));
+			if (rtn) {
+				for (i = 0; i <= media_lgrp->supported_speeds_num; ++i)
+					kobject_put(&media_lgrp->speeds_kobj[i].kobj);
+				media_lgrp->supported_speeds_num = 0;
+				sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "kobject_init_and_add failed [%d]", rtn);
+				return rtn;
+			}
+			media_lgrp->supported_speeds_num++;
+		}
+	} else if (media_lgrp->cable_info->fake_cable_status == CABLE_MEDIA_ATTR_ADDED) {
+		for_each_set_bit(i, &media_lgrp->cable_info->stashed_media_attr.speeds_map,
+				 sizeof(media_lgrp->cable_info->stashed_media_attr.speeds_map) * BITS_PER_BYTE) {
+			media_lgrp->speeds_kobj[media_lgrp->supported_speeds_num].media_lgrp = media_lgrp;
+			media_lgrp->speeds_kobj[media_lgrp->supported_speeds_num].speed = BIT(i);
+			rtn = kobject_init_and_add(&media_lgrp->speeds_kobj[media_lgrp->supported_speeds_num].kobj,
+						   &media_speed_info, &media_lgrp->parent_speed_kobj, sl_media_speed_str(BIT(i)));
+			if (rtn) {
+				for (i = 0; i <= media_lgrp->supported_speeds_num; ++i)
+					kobject_put(&media_lgrp->speeds_kobj[i].kobj);
+				media_lgrp->supported_speeds_num = 0;
+				sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "kobject_init_and_add failed [%d]", rtn);
+				return rtn;
+			}
+			media_lgrp->supported_speeds_num++;
+		}
+	}
+
+	media_lgrp->speeds_kobj_init = true;
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "media speed nodes created");
+
+	return 0;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_media_speeds_delete(u8 ldev_num, u8 lgrp_num)
+{
+#ifdef CONFIG_SYSFS
+	struct sl_media_lgrp *media_lgrp;
+	u8 i;
+
+	media_lgrp = sl_media_lgrp_get(ldev_num, lgrp_num);
+	if (!media_lgrp)
+		return;
+
+	if (media_lgrp->speeds_kobj_init) {
+		for (i = 0; i < media_lgrp->supported_speeds_num; ++i)
+			kobject_put(&media_lgrp->speeds_kobj[i].kobj);
+	}
+	media_lgrp->speeds_kobj_init = false;
+	media_lgrp->supported_speeds_num = 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_media_delete(struct sl_ctrl_lgrp *ctrl_lgrp)
+{
+#ifdef CONFIG_SYSFS
+	struct sl_media_lgrp *media_lgrp;
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "media delete");
+
+	if (!ctrl_lgrp->parent_kobj)
+		return;
+
+	sl_sysfs_media_counters_delete(ctrl_lgrp);
+
+	media_lgrp = sl_media_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!media_lgrp) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "media_lgrp_get failed");
+		return;
+	}
+
+	sl_sysfs_media_speeds_delete(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	kobject_put(&media_lgrp->parent_speed_kobj);
+	kobject_put(&media_lgrp->kobj);
+#endif /* CONFIG_SYSFS */
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_media_counters.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_media_counters.c
new file mode 100644
index 000000000000..682c106d4d3a
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_media_counters.c
@@ -0,0 +1,599 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2025,2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kobject.h>
+#include <linux/sysfs.h>
+
+#include "sl_sysfs.h"
+#include "sl_log.h"
+#include "sl_media_lgrp.h"
+#include "sl_ctrl_ldev.h"
+#include "sl_ctrl_lgrp.h"
+#include "sl_ctrl_media_counters.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+#ifdef CONFIG_SYSFS
+static ssize_t cause_eeprom_format_unsupported_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u32                   counter;
+	u32                   rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, counters_kobj);
+
+	rtn = sl_ctrl_media_cause_counter_get(media_lgrp->media_jack, MEDIA_CAUSE_EEPROM_FORMAT_UNSUPPORTED, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "media cause eeprom format unsupported show (counter = %u)",
+		   counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_eeprom_vendor_unsupported_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u32                   counter;
+	u32                   rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, counters_kobj);
+
+	rtn = sl_ctrl_media_cause_counter_get(media_lgrp->media_jack, MEDIA_CAUSE_EEPROM_VENDOR_UNSUPPORTED, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "media cause eeprom vendor unsupported show (counter = %u)",
+		   counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_eeprom_jack_io_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u32                   counter;
+	u32                   rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, counters_kobj);
+
+	rtn = sl_ctrl_media_cause_counter_get(media_lgrp->media_jack, MEDIA_CAUSE_EEPROM_JACK_IO, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "media cause eeprom jack io show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_online_status_get_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u32                   counter;
+	u32                   rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, counters_kobj);
+
+	rtn = sl_ctrl_media_cause_counter_get(media_lgrp->media_jack, MEDIA_CAUSE_ONLINE_STATUS_GET, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "media cause online status get show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_online_timedout_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u32                   counter;
+	u32                   rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, counters_kobj);
+
+	rtn = sl_ctrl_media_cause_counter_get(media_lgrp->media_jack, MEDIA_CAUSE_ONLINE_TIMEDOUT, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "media cause online timedout show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_online_jack_io_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u32                   counter;
+	u32                   rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, counters_kobj);
+
+	rtn = sl_ctrl_media_cause_counter_get(media_lgrp->media_jack, MEDIA_CAUSE_ONLINE_JACK_IO, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "media cause online jack io show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_online_jack_get_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u32                   counter;
+	u32                   rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, counters_kobj);
+
+	rtn = sl_ctrl_media_cause_counter_get(media_lgrp->media_jack, MEDIA_CAUSE_ONLINE_JACK_GET, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "media cause online jack get show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_serdes_settings_get_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u32                   counter;
+	u32                   rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, counters_kobj);
+
+	rtn = sl_ctrl_media_cause_counter_get(media_lgrp->media_jack, MEDIA_CAUSE_SERDES_SETTINGS_GET, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "media cause serdes settings get show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_scan_status_get_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u32                   counter;
+	u32                   rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, counters_kobj);
+
+	rtn = sl_ctrl_media_cause_counter_get(media_lgrp->media_jack, MEDIA_CAUSE_SCAN_STATUS_GET, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "media cause scan status get show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_scan_hdl_get_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u32                   counter;
+	u32                   rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, counters_kobj);
+
+	rtn = sl_ctrl_media_cause_counter_get(media_lgrp->media_jack, MEDIA_CAUSE_SCAN_HDL_GET, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "media cause scan hdl get show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_scan_jack_get_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u32                   counter;
+	u32                   rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, counters_kobj);
+
+	rtn = sl_ctrl_media_cause_counter_get(media_lgrp->media_jack, MEDIA_CAUSE_SCAN_JACK_GET, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "media cause scan jack get show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_media_attr_set_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u32                   counter;
+	u32                   rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, counters_kobj);
+
+	rtn = sl_ctrl_media_cause_counter_get(media_lgrp->media_jack, MEDIA_CAUSE_MEDIA_ATTR_SET, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "media cause media attr set show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_intr_event_jack_io_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u32                   counter;
+	u32                   rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, counters_kobj);
+
+	rtn = sl_ctrl_media_cause_counter_get(media_lgrp->media_jack, MEDIA_CAUSE_INTR_EVENT_JACK_IO, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "media cause intr event jack io show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_power_set_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u32                   counter;
+	u32                   rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, counters_kobj);
+
+	rtn = sl_ctrl_media_cause_counter_get(media_lgrp->media_jack, MEDIA_CAUSE_POWER_SET, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "media cause power set show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_shift_down_jack_io_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u32                   counter;
+	u32                   rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, counters_kobj);
+
+	rtn = sl_ctrl_media_cause_counter_get(media_lgrp->media_jack, MEDIA_CAUSE_SHIFT_DOWN_JACK_IO, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "media cause shift down jack io show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_shift_down_jack_io_low_power_set_show(struct kobject *kobj,
+							   struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u32                   counter;
+	u32                   rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, counters_kobj);
+
+	rtn = sl_ctrl_media_cause_counter_get(media_lgrp->media_jack, MEDIA_CAUSE_SHIFT_DOWN_JACK_IO_LOW_POWER_SET,
+					      &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "media cause shift down jack io low power set show (counter = %u)",
+		   counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_shift_down_jack_io_high_power_set_show(struct kobject *kobj,
+							    struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u32                   counter;
+	u32                   rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, counters_kobj);
+
+	rtn = sl_ctrl_media_cause_counter_get(media_lgrp->media_jack,
+					      MEDIA_CAUSE_SHIFT_DOWN_JACK_IO_HIGH_POWER_SET, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "media cause shift down jack io high power set show (counter = %u)",
+		   counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_shift_up_jack_io_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u32                   counter;
+	u32                   rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, counters_kobj);
+
+	rtn = sl_ctrl_media_cause_counter_get(media_lgrp->media_jack, MEDIA_CAUSE_SHIFT_UP_JACK_IO, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "media cause shift up jack io show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_shift_up_jack_io_low_power_set_show(struct kobject *kobj, struct kobj_attribute *kattr,
+							 char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u32                   counter;
+	u32                   rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, counters_kobj);
+
+	rtn = sl_ctrl_media_cause_counter_get(media_lgrp->media_jack, MEDIA_CAUSE_SHIFT_UP_JACK_IO_LOW_POWER_SET,
+					      &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "media cause shift up jack io low power set show (counter = %u)",
+		   counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_shift_up_jack_io_high_power_set_show(struct kobject *kobj, struct kobj_attribute *kattr,
+							  char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u32                   counter;
+	u32                   rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, counters_kobj);
+
+	rtn = sl_ctrl_media_cause_counter_get(media_lgrp->media_jack, MEDIA_CAUSE_SHIFT_UP_JACK_IO_HIGH_POWER_SET,
+					      &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "media cause shift up jack io high power set show (counter = %u)",
+		   counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_shift_state_jack_io_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u32                   counter;
+	u32                   rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, counters_kobj);
+
+	rtn = sl_ctrl_media_cause_counter_get(media_lgrp->media_jack, MEDIA_CAUSE_SHIFT_STATE_JACK_IO, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "media cause shift state jack io show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_offline_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u32                   counter;
+	u32                   rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, counters_kobj);
+
+	rtn = sl_ctrl_media_cause_counter_get(media_lgrp->media_jack, MEDIA_CAUSE_OFFLINE, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "media cause offline show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_hot_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u32                   counter;
+	u32                   rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, counters_kobj);
+
+	rtn = sl_ctrl_media_cause_counter_get(media_lgrp->media_jack, MEDIA_CAUSE_HOT, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "media cause hot show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static ssize_t cause_warm_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_media_lgrp *media_lgrp;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	u32                   counter;
+	u32                   rtn;
+
+	media_lgrp = container_of(kobj, struct sl_media_lgrp, counters_kobj);
+
+	rtn = sl_ctrl_media_cause_counter_get(media_lgrp->media_jack, MEDIA_CAUSE_WARM, &counter);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	ctrl_lgrp = sl_ctrl_lgrp_get(media_lgrp->media_ldev->num, media_lgrp->num);
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "media cause warm show (counter = %u)", counter);
+
+	return sysfs_emit(buf, "%u\n", counter);
+}
+
+static struct kobj_attribute media_cause_eeprom_format_unsupported         =
+			     __ATTR_RO(cause_eeprom_format_unsupported);
+static struct kobj_attribute media_cause_eeprom_vendor_unsupported         =
+			     __ATTR_RO(cause_eeprom_vendor_unsupported);
+static struct kobj_attribute media_cause_eeprom_jack_io                    = __ATTR_RO(cause_eeprom_jack_io);
+static struct kobj_attribute media_cause_online_status_get                 = __ATTR_RO(cause_online_status_get);
+static struct kobj_attribute media_cause_online_timedout                   = __ATTR_RO(cause_online_timedout);
+static struct kobj_attribute media_cause_online_jack_io                    = __ATTR_RO(cause_online_jack_io);
+static struct kobj_attribute media_cause_online_jack_get                   = __ATTR_RO(cause_online_jack_get);
+static struct kobj_attribute media_cause_serdes_settings_get               = __ATTR_RO(cause_serdes_settings_get);
+static struct kobj_attribute media_cause_scan_status_get                   = __ATTR_RO(cause_scan_status_get);
+static struct kobj_attribute media_cause_scan_hdl_get                      = __ATTR_RO(cause_scan_hdl_get);
+static struct kobj_attribute media_cause_scan_jack_get                     = __ATTR_RO(cause_scan_jack_get);
+static struct kobj_attribute media_cause_media_attr_set                    = __ATTR_RO(cause_media_attr_set);
+static struct kobj_attribute media_cause_intr_event_jack_io                = __ATTR_RO(cause_intr_event_jack_io);
+static struct kobj_attribute media_cause_power_set                         = __ATTR_RO(cause_power_set);
+static struct kobj_attribute media_cause_shift_down_jack_io                = __ATTR_RO(cause_shift_down_jack_io);
+static struct kobj_attribute media_cause_shift_down_jack_io_low_power_set  =
+			     __ATTR_RO(cause_shift_down_jack_io_low_power_set);
+static struct kobj_attribute media_cause_shift_down_jack_io_high_power_set =
+			     __ATTR_RO(cause_shift_down_jack_io_high_power_set);
+static struct kobj_attribute media_cause_shift_up_jack_io                  = __ATTR_RO(cause_shift_up_jack_io);
+static struct kobj_attribute media_cause_shift_up_jack_io_low_power_set    =
+			     __ATTR_RO(cause_shift_up_jack_io_low_power_set);
+static struct kobj_attribute media_cause_shift_up_jack_io_high_power_set   =
+			     __ATTR_RO(cause_shift_up_jack_io_high_power_set);
+static struct kobj_attribute media_cause_shift_state_jack_io               =
+			     __ATTR_RO(cause_shift_state_jack_io);
+static struct kobj_attribute media_cause_offline                           = __ATTR_RO(cause_offline);
+static struct kobj_attribute media_cause_hot                               = __ATTR_RO(cause_hot);
+static struct kobj_attribute media_cause_warm                              = __ATTR_RO(cause_warm);
+
+static struct attribute *media_counters_attrs[] = {
+	&media_cause_eeprom_format_unsupported.attr,
+	&media_cause_eeprom_vendor_unsupported.attr,
+	&media_cause_eeprom_jack_io.attr,
+	&media_cause_online_status_get.attr,
+	&media_cause_online_timedout.attr,
+	&media_cause_online_jack_io.attr,
+	&media_cause_online_jack_get.attr,
+	&media_cause_serdes_settings_get.attr,
+	&media_cause_scan_status_get.attr,
+	&media_cause_scan_hdl_get.attr,
+	&media_cause_scan_jack_get.attr,
+	&media_cause_media_attr_set.attr,
+	&media_cause_intr_event_jack_io.attr,
+	&media_cause_power_set.attr,
+	&media_cause_shift_down_jack_io.attr,
+	&media_cause_shift_down_jack_io_low_power_set.attr,
+	&media_cause_shift_down_jack_io_high_power_set.attr,
+	&media_cause_shift_up_jack_io.attr,
+	&media_cause_shift_up_jack_io_low_power_set.attr,
+	&media_cause_shift_up_jack_io_high_power_set.attr,
+	&media_cause_shift_state_jack_io.attr,
+	&media_cause_offline.attr,
+	&media_cause_hot.attr,
+	&media_cause_warm.attr,
+	NULL
+};
+ATTRIBUTE_GROUPS(media_counters);
+
+static struct kobj_type media_counters = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = media_counters_groups,
+};
+#endif /* CONFIG_SYSFS */
+
+int sl_sysfs_media_counters_create(struct sl_ctrl_lgrp *ctrl_lgrp)
+{
+#ifdef CONFIG_SYSFS
+	struct sl_media_lgrp *media_lgrp;
+	int                   rtn;
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "media counters create");
+
+	media_lgrp = sl_media_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!media_lgrp) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "media_lgrp_get failed");
+		return -EFAULT;
+	}
+
+	rtn = kobject_init_and_add(&media_lgrp->counters_kobj, &media_counters, &media_lgrp->kobj,
+				   "counters");
+	if (rtn) {
+		kobject_put(&media_lgrp->counters_kobj);
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+			   "media counters create kobject_init_and_add failed [%d]", rtn);
+		return rtn;
+	}
+
+	return 0;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_media_counters_delete(struct sl_ctrl_lgrp *ctrl_lgrp)
+{
+#ifdef CONFIG_SYSFS
+	struct sl_media_lgrp *media_lgrp;
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "media counters delete");
+
+	media_lgrp = sl_media_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!media_lgrp) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "media_lgrp_get failed");
+		return;
+	}
+
+	kobject_put(&media_lgrp->counters_kobj);
+#endif /* CONFIG_SYSFS */
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_pmi.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_pmi.c
new file mode 100644
index 000000000000..605a7748e242
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_pmi.c
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2026 Hewlett Packard Enterprise Development LP */
+
+#include "sl_log.h"
+#include "sl_sysfs.h"
+#include "sl_ctrl_lgrp.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+#ifdef CONFIG_SYSFS
+static struct attribute *pmi_attrs[] = {
+	NULL,
+};
+ATTRIBUTE_GROUPS(pmi);
+
+static struct kobj_type pmi_info = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = pmi_groups,
+};
+#endif /* CONFIG_SYSFS */
+
+int sl_sysfs_pmi_create(struct sl_ctrl_lgrp *ctrl_lgrp)
+{
+#ifdef CONFIG_SYSFS
+	int rtn;
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "pmi (lgrp = 0x%p)", ctrl_lgrp);
+
+	if (!ctrl_lgrp->parent_kobj) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "pmi create missing parent");
+		return -EBADRQC;
+	}
+
+	rtn = kobject_init_and_add(&ctrl_lgrp->pmi_kobj, &pmi_info, ctrl_lgrp->parent_kobj, "pmi");
+	if (rtn) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "pmi create kobject_init_and_add failed [%d]", rtn);
+		goto out_pmi;
+	}
+
+	rtn = sl_sysfs_pmi_rd_create(ctrl_lgrp, &ctrl_lgrp->pmi_kobj);
+	if (rtn) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "pmi rd create failed [%d]", rtn);
+		goto out_pmi;
+	}
+
+	rtn = sl_sysfs_pmi_wr_create(ctrl_lgrp, &ctrl_lgrp->pmi_kobj);
+	if (rtn) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "pmi wr create failed [%d]", rtn);
+		goto out_rd;
+	}
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "pmi create (pmi_kobj = 0x%p)", &ctrl_lgrp->pmi_kobj);
+	return 0;
+
+out_rd:
+	sl_sysfs_pmi_rd_delete(ctrl_lgrp);
+out_pmi:
+	kobject_put(&ctrl_lgrp->pmi_kobj);
+
+	return -ENOMEM;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_pmi_delete(struct sl_ctrl_lgrp *ctrl_lgrp)
+{
+#ifdef CONFIG_SYSFS
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "pmi delete (lgrp = 0x%p)", ctrl_lgrp);
+
+	if (!ctrl_lgrp->parent_kobj)
+		return;
+
+	sl_sysfs_pmi_wr_delete(ctrl_lgrp);
+	sl_sysfs_pmi_rd_delete(ctrl_lgrp);
+
+	kobject_put(&ctrl_lgrp->pmi_kobj);
+#endif /* CONFIG_SYSFS */
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_pmi_rd.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_pmi_rd.c
new file mode 100644
index 000000000000..8e997c4ce3f5
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_pmi_rd.c
@@ -0,0 +1,197 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/sysfs.h>
+#include <linux/kobject.h>
+
+#include "sl_log.h"
+#include "sl_sysfs.h"
+#include "sl_ctrl_lgrp.h"
+#include "sl_ctrl_ldev.h"
+#include "sl_core_lgrp.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+#ifdef CONFIG_SYSFS
+static ssize_t addr_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	u16                  addr;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, pmi_rd_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_pmi_rd_addr_get(core_lgrp, &addr);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "pmi rd addr show (addr = 0x%04X)", addr);
+
+	return sysfs_emit(buf, "0x%04X\n", addr);
+}
+
+static ssize_t data_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	u16                  data;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, pmi_rd_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_pmi_rd_data_get(core_lgrp, &data);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "pmi rd data show (data = 0x%04X)", data);
+
+	return sysfs_emit(buf, "0x%04X\n", data);
+}
+
+static ssize_t dev_id_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	u8                   dev_id;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, pmi_rd_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_pmi_rd_dev_id_get(core_lgrp, &dev_id);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "pmi rd dev id show (dev_id = 0x%02X)", dev_id);
+
+	return sysfs_emit(buf, "0x%02X\n", dev_id);
+}
+
+static ssize_t lane_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	u8                   lane;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, pmi_rd_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_pmi_rd_lane_get(core_lgrp, &lane);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "pmi rd lane show (lane = 0x%02X)", lane);
+
+	return sysfs_emit(buf, "0x%02X\n", lane);
+}
+
+static ssize_t pll_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	u8                   pll;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, pmi_rd_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_pmi_rd_pll_get(core_lgrp, &pll);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "pmi rd pll show (pll = 0x%02X)", pll);
+
+	return sysfs_emit(buf, "0x%02X\n", pll);
+}
+
+static ssize_t result_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	int                  result;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, pmi_rd_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_pmi_rd_result_get(core_lgrp, &result);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "pmi rd result show (result = %d)", result);
+
+	return sysfs_emit(buf, "%d\n", result);
+}
+
+static struct kobj_attribute addr   = __ATTR_RO(addr);
+static struct kobj_attribute data   = __ATTR_RO(data);
+static struct kobj_attribute dev_id = __ATTR_RO(dev_id);
+static struct kobj_attribute lane   = __ATTR_RO(lane);
+static struct kobj_attribute pll    = __ATTR_RO(pll);
+static struct kobj_attribute result = __ATTR_RO(result);
+
+static struct attribute *pmi_rd_attrs[] = {
+	&addr.attr,
+	&data.attr,
+	&dev_id.attr,
+	&lane.attr,
+	&pll.attr,
+	&result.attr,
+	NULL,
+};
+ATTRIBUTE_GROUPS(pmi_rd);
+
+static struct kobj_type pmi_rd_info = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = pmi_rd_groups,
+};
+#endif
+
+int sl_sysfs_pmi_rd_create(struct sl_ctrl_lgrp *ctrl_lgrp, struct kobject *parent_kobj)
+{
+#ifdef CONFIG_SYSFS
+	int rtn;
+
+	rtn = kobject_init_and_add(&ctrl_lgrp->pmi_rd_kobj, &pmi_rd_info, parent_kobj, "rd");
+	if (rtn) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "pmi rd create kobject_init_and_add failed [%d]", rtn);
+		goto out_pmi_rd;
+	}
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "pmi rd create (pmi_rd_kobj = 0x%p)", &ctrl_lgrp->pmi_rd_kobj);
+	return 0;
+
+out_pmi_rd:
+	kobject_put(&ctrl_lgrp->pmi_rd_kobj);
+
+	return -ENOMEM;
+#else
+	return 0;
+#endif
+}
+
+void sl_sysfs_pmi_rd_delete(struct sl_ctrl_lgrp *ctrl_lgrp)
+{
+#ifdef CONFIG_SYSFS
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "pmi rd delete (lgrp = 0x%p)", ctrl_lgrp);
+
+	kobject_put(&ctrl_lgrp->pmi_rd_kobj);
+#endif
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_pmi_wr.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_pmi_wr.c
new file mode 100644
index 000000000000..ccc672378bf5
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_pmi_wr.c
@@ -0,0 +1,220 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/sysfs.h>
+#include <linux/kobject.h>
+
+#include "sl_log.h"
+#include "sl_sysfs.h"
+#include "sl_ctrl_lgrp.h"
+#include "sl_ctrl_ldev.h"
+#include "sl_core_lgrp.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+#ifdef CONFIG_SYSFS
+static ssize_t addr_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	u16                  addr;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, pmi_wr_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_pmi_wr_addr_get(core_lgrp, &addr);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "pmi wr addr show (addr = 0x%04X)", addr);
+
+	return sysfs_emit(buf, "0x%04X\n", addr);
+}
+
+static ssize_t data_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	u16                  data;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, pmi_wr_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_pmi_wr_data_get(core_lgrp, &data);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "pmi wr data show (data = 0x%04X)", data);
+
+	return sysfs_emit(buf, "0x%04X\n", data);
+}
+
+static ssize_t mask_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	u16                  mask;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, pmi_wr_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_pmi_wr_mask_get(core_lgrp, &mask);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "pmi wr mask show (mask = 0x%04X)", mask);
+
+	return sysfs_emit(buf, "0x%04X\n", mask);
+}
+
+static ssize_t dev_id_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	u8                   dev_id;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, pmi_wr_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_pmi_wr_dev_id_get(core_lgrp, &dev_id);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "pmi wr dev id show (dev_id = 0x%02X)", dev_id);
+
+	return sysfs_emit(buf, "0x%02X\n", dev_id);
+}
+
+static ssize_t lane_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	u8                   lane;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, pmi_wr_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_pmi_wr_lane_get(core_lgrp, &lane);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "pmi wr lane show (lane = 0x%02X)", lane);
+
+	return sysfs_emit(buf, "0x%02X\n", lane);
+}
+
+static ssize_t pll_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	u8                   pll;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, pmi_wr_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_pmi_wr_pll_get(core_lgrp, &pll);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "pmi wr pll show (pll = 0x%02X)", pll);
+
+	return sysfs_emit(buf, "0x%02X\n", pll);
+}
+
+static ssize_t result_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	int                  result;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, pmi_wr_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_pmi_wr_result_get(core_lgrp, &result);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "pmi wr result show (result = %d)", result);
+
+	return sysfs_emit(buf, "%d\n", result);
+}
+
+static struct kobj_attribute addr   = __ATTR_RO(addr);
+static struct kobj_attribute data   = __ATTR_RO(data);
+static struct kobj_attribute mask   = __ATTR_RO(mask);
+static struct kobj_attribute dev_id = __ATTR_RO(dev_id);
+static struct kobj_attribute lane   = __ATTR_RO(lane);
+static struct kobj_attribute pll    = __ATTR_RO(pll);
+static struct kobj_attribute result = __ATTR_RO(result);
+
+static struct attribute *pmi_wr_attrs[] = {
+	&addr.attr,
+	&data.attr,
+	&mask.attr,
+	&dev_id.attr,
+	&lane.attr,
+	&pll.attr,
+	&result.attr,
+	NULL,
+};
+ATTRIBUTE_GROUPS(pmi_wr);
+
+static struct kobj_type pmi_wr_info = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = pmi_wr_groups,
+};
+#endif /* CONFIG_SYSFS */
+
+int sl_sysfs_pmi_wr_create(struct sl_ctrl_lgrp *ctrl_lgrp, struct kobject *parent_kobj)
+{
+#ifdef CONFIG_SYSFS
+	int rtn;
+
+	rtn = kobject_init_and_add(&ctrl_lgrp->pmi_wr_kobj, &pmi_wr_info, parent_kobj, "wr");
+	if (rtn) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "pmi wr create kobject_init_and_add failed [%d]", rtn);
+		goto out_pmi_wr;
+	}
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "pmi wr create (pmi_wr_kobj = 0x%p)", &ctrl_lgrp->pmi_wr_kobj);
+	return 0;
+
+out_pmi_wr:
+	kobject_put(&ctrl_lgrp->pmi_wr_kobj);
+
+	return -ENOMEM;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_pmi_wr_delete(struct sl_ctrl_lgrp *ctrl_lgrp)
+{
+#ifdef CONFIG_SYSFS
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "pmi wr delete (lgrp = 0x%p)", ctrl_lgrp);
+
+	kobject_put(&ctrl_lgrp->pmi_wr_kobj);
+#endif /* CONFIG_SYSFS */
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_sbus.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_sbus.c
new file mode 100644
index 000000000000..a71c396e59f3
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_sbus.c
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2026 Hewlett Packard Enterprise Development LP */
+
+#include "sl_log.h"
+#include "sl_sysfs.h"
+#include "sl_ctrl_lgrp.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+#ifdef CONFIG_SYSFS
+static struct attribute *sbus_attrs[] = {
+	NULL,
+};
+ATTRIBUTE_GROUPS(sbus);
+
+static struct kobj_type sbus_info = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = sbus_groups,
+};
+#endif /* CONFIG_SYSFS */
+
+int sl_sysfs_sbus_create(struct sl_ctrl_lgrp *ctrl_lgrp)
+{
+#ifdef CONFIG_SYSFS
+	int rtn;
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "sbus (lgrp = 0x%p)", ctrl_lgrp);
+
+	if (!ctrl_lgrp->parent_kobj) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "sbus create missing parent");
+		return -EBADRQC;
+	}
+
+	rtn = kobject_init_and_add(&ctrl_lgrp->sbus_kobj, &sbus_info, ctrl_lgrp->parent_kobj, "sbus");
+	if (rtn) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "sbus create kobject_init_and_add failed [%d]", rtn);
+		goto out_sbus;
+	}
+
+	rtn = sl_sysfs_sbus_rd_create(ctrl_lgrp, &ctrl_lgrp->sbus_kobj);
+	if (rtn) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "sbus rd create failed [%d]", rtn);
+		goto out_sbus;
+	}
+
+	rtn = sl_sysfs_sbus_wr_create(ctrl_lgrp, &ctrl_lgrp->sbus_kobj);
+	if (rtn) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "sbus wr create failed [%d]", rtn);
+		goto out_rd;
+	}
+
+	rtn = sl_sysfs_sbus_rst_create(ctrl_lgrp, &ctrl_lgrp->sbus_kobj);
+	if (rtn) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "sbus rst create failed [%d]", rtn);
+		goto out_wr;
+	}
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "sbus create (sbus_kobj = 0x%p)", &ctrl_lgrp->sbus_kobj);
+	return 0;
+
+out_wr:
+	sl_sysfs_sbus_wr_delete(ctrl_lgrp);
+out_rd:
+	sl_sysfs_sbus_rd_delete(ctrl_lgrp);
+out_sbus:
+	kobject_put(&ctrl_lgrp->sbus_kobj);
+
+	return -ENOMEM;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_sbus_delete(struct sl_ctrl_lgrp *ctrl_lgrp)
+{
+#ifdef CONFIG_SYSFS
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "sbus delete (lgrp = 0x%p)", ctrl_lgrp);
+
+	if (!ctrl_lgrp->parent_kobj)
+		return;
+
+	sl_sysfs_sbus_rst_delete(ctrl_lgrp);
+	sl_sysfs_sbus_wr_delete(ctrl_lgrp);
+	sl_sysfs_sbus_rd_delete(ctrl_lgrp);
+
+	kobject_put(&ctrl_lgrp->sbus_kobj);
+#endif /* CONFIG_SYSFS */
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_sbus_pmi.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_sbus_pmi.c
new file mode 100644
index 000000000000..5048b0f69f76
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_sbus_pmi.c
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2026 Hewlett Packard Enterprise Development LP */
+
+#include "sl_log.h"
+#include "sl_sysfs.h"
+#include "sl_ctrl_lgrp.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+#ifdef CONFIG_SYSFS
+static struct attribute *sbus_pmi_attrs[] = {
+	NULL,
+};
+ATTRIBUTE_GROUPS(sbus_pmi);
+
+static struct kobj_type sbus_pmi_info = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = sbus_pmi_groups,
+};
+#endif /* CONFIG_SYSFS */
+
+int sl_sysfs_sbus_pmi_create(struct sl_ctrl_lgrp *ctrl_lgrp)
+{
+#ifdef CONFIG_SYSFS
+	int rtn;
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "sbus_pmi create (lgrp = 0x%p)", ctrl_lgrp);
+
+	if (!ctrl_lgrp->parent_kobj) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "sbus_pmi create missing parent");
+		return -EBADRQC;
+	}
+
+	rtn = kobject_init_and_add(&ctrl_lgrp->sbus_pmi_kobj, &sbus_pmi_info, ctrl_lgrp->parent_kobj, "sbus_pmi");
+	if (rtn) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "sbus_pmi create kobject_init_and_add failed [%d]", rtn);
+		goto out_sbus_pmi;
+	}
+
+	rtn = sl_sysfs_sbus_pmi_rd_create(ctrl_lgrp, &ctrl_lgrp->sbus_pmi_kobj);
+	if (rtn) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "sbus_pmi rd create failed [%d]", rtn);
+		goto out_sbus_pmi;
+	}
+
+	rtn = sl_sysfs_sbus_pmi_wr_create(ctrl_lgrp, &ctrl_lgrp->sbus_pmi_kobj);
+	if (rtn) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "sbus_pmi wr create failed [%d]", rtn);
+		goto out_rd;
+	}
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "sbus_pmi create (sbus_pmi_kobj = 0x%p)", &ctrl_lgrp->sbus_pmi_kobj);
+	return 0;
+
+out_rd:
+	sl_sysfs_sbus_pmi_rd_delete(ctrl_lgrp);
+out_sbus_pmi:
+	kobject_put(&ctrl_lgrp->sbus_pmi_kobj);
+
+	return -ENOMEM;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_sbus_pmi_delete(struct sl_ctrl_lgrp *ctrl_lgrp)
+{
+#ifdef CONFIG_SYSFS
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "sbus_pmi delete (lgrp = 0x%p)", ctrl_lgrp);
+
+	if (!ctrl_lgrp->parent_kobj)
+		return;
+
+	sl_sysfs_sbus_pmi_wr_delete(ctrl_lgrp);
+	sl_sysfs_sbus_pmi_rd_delete(ctrl_lgrp);
+
+	kobject_put(&ctrl_lgrp->sbus_pmi_kobj);
+#endif /* CONFIG_SYSFS */
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_sbus_pmi_rd.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_sbus_pmi_rd.c
new file mode 100644
index 000000000000..c8042fe67eb6
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_sbus_pmi_rd.c
@@ -0,0 +1,244 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/sysfs.h>
+#include <linux/kobject.h>
+
+#include "sl_log.h"
+#include "sl_sysfs.h"
+#include "sl_ctrl_lgrp.h"
+#include "sl_ctrl_ldev.h"
+#include "sl_core_lgrp.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+#ifdef CONFIG_SYSFS
+static ssize_t dev_addr_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	u8                   dev_addr;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, sbus_pmi_rd_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_sbus_pmi_rd_dev_addr_get(core_lgrp, &dev_addr);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "sbus_pmi rd dev_addr show (dev_addr = 0x%02X)", dev_addr);
+
+	return sysfs_emit(buf, "0x%02X\n", dev_addr);
+}
+
+static ssize_t addr_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	u16                  addr;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, sbus_pmi_rd_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_sbus_pmi_rd_addr_get(core_lgrp, &addr);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "sbus_pmi rd addr show (addr = 0x%04X)", addr);
+
+	return sysfs_emit(buf, "0x%04X\n", addr);
+}
+
+static ssize_t data_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	u16                  data;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, sbus_pmi_rd_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_sbus_pmi_rd_data_get(core_lgrp, &data);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "sbus_pmi rd data show (data = 0x%04X)", data);
+
+	return sysfs_emit(buf, "0x%04X\n", data);
+}
+
+static ssize_t mask_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	u16                  mask;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, sbus_pmi_rd_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_sbus_pmi_rd_mask_get(core_lgrp, &mask);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "sbus_pmi rd mask show (mask = 0x%04X)", mask);
+
+	return sysfs_emit(buf, "0x%04X\n", mask);
+}
+
+static ssize_t dev_id_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	u8                   dev_id;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, sbus_pmi_rd_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_sbus_pmi_rd_dev_id_get(core_lgrp, &dev_id);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "sbus_pmi rd dev id show (dev_id = 0x%02X)", dev_id);
+
+	return sysfs_emit(buf, "0x%02X\n", dev_id);
+}
+
+static ssize_t lane_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	u8                   lane;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, sbus_pmi_rd_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_sbus_pmi_rd_lane_get(core_lgrp, &lane);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "sbus_pmi rd lane show (lane = 0x%02X)", lane);
+
+	return sysfs_emit(buf, "0x%02X\n", lane);
+}
+
+static ssize_t pll_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	u8                   pll;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, sbus_pmi_rd_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_sbus_pmi_rd_pll_get(core_lgrp, &pll);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "sbus_pmi rd pll show (pll = 0x%02X)", pll);
+
+	return sysfs_emit(buf, "0x%02X\n", pll);
+}
+
+static ssize_t result_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	int                  result;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, sbus_pmi_rd_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_sbus_pmi_rd_result_get(core_lgrp, &result);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "sbus_pmi rd result show (result = %d)", result);
+
+	return sysfs_emit(buf, "%d\n", result);
+}
+
+static struct kobj_attribute dev_addr = __ATTR_RO(dev_addr);
+static struct kobj_attribute addr     = __ATTR_RO(addr);
+static struct kobj_attribute data     = __ATTR_RO(data);
+static struct kobj_attribute mask     = __ATTR_RO(mask);
+static struct kobj_attribute dev_id   = __ATTR_RO(dev_id);
+static struct kobj_attribute lane     = __ATTR_RO(lane);
+static struct kobj_attribute pll      = __ATTR_RO(pll);
+static struct kobj_attribute result   = __ATTR_RO(result);
+
+static struct attribute *sbus_pmi_rd_attrs[] = {
+	&dev_addr.attr,
+	&addr.attr,
+	&data.attr,
+	&mask.attr,
+	&dev_id.attr,
+	&lane.attr,
+	&pll.attr,
+	&result.attr,
+	NULL,
+};
+ATTRIBUTE_GROUPS(sbus_pmi_rd);
+
+static struct kobj_type sbus_pmi_rd_info = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = sbus_pmi_rd_groups,
+};
+#endif /* CONFIG_SYSFS */
+
+int sl_sysfs_sbus_pmi_rd_create(struct sl_ctrl_lgrp *ctrl_lgrp, struct kobject *parent_kobj)
+{
+#ifdef CONFIG_SYSFS
+	int rtn;
+
+	rtn = kobject_init_and_add(&ctrl_lgrp->sbus_pmi_rd_kobj, &sbus_pmi_rd_info, parent_kobj, "rd");
+	if (rtn) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "sbus_pmi rd create kobject_init_and_add failed [%d]", rtn);
+		goto out_sbus_pmi_rd;
+	}
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "sbus_pmi rd create (sbus_pmi_rd_kobj = 0x%p)",
+		   &ctrl_lgrp->sbus_pmi_rd_kobj);
+	return 0;
+
+out_sbus_pmi_rd:
+	kobject_put(&ctrl_lgrp->sbus_pmi_rd_kobj);
+
+	return -ENOMEM;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_sbus_pmi_rd_delete(struct sl_ctrl_lgrp *ctrl_lgrp)
+{
+#ifdef CONFIG_SYSFS
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "sbus_pmi rd delete (lgrp = 0x%p)", ctrl_lgrp);
+
+	kobject_put(&ctrl_lgrp->sbus_pmi_rd_kobj);
+#endif /* CONFIG_SYSFS */
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_sbus_pmi_wr.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_sbus_pmi_wr.c
new file mode 100644
index 000000000000..a9de4a9e42ea
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_sbus_pmi_wr.c
@@ -0,0 +1,244 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/sysfs.h>
+#include <linux/kobject.h>
+
+#include "sl_log.h"
+#include "sl_sysfs.h"
+#include "sl_ctrl_lgrp.h"
+#include "sl_ctrl_ldev.h"
+#include "sl_core_lgrp.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+#ifdef CONFIG_SYSFS
+static ssize_t dev_addr_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	u8                   dev_addr;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, sbus_pmi_wr_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_sbus_pmi_wr_dev_addr_get(core_lgrp, &dev_addr);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "sbus_pmi wr dev_addr show (dev_addr = 0x%02X)", dev_addr);
+
+	return sysfs_emit(buf, "0x%02X\n", dev_addr);
+}
+
+static ssize_t addr_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	u16                  addr;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, sbus_pmi_wr_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_sbus_pmi_wr_addr_get(core_lgrp, &addr);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "sbus_pmi wr addr show (addr = 0x%04X)", addr);
+
+	return sysfs_emit(buf, "0x%04X\n", addr);
+}
+
+static ssize_t data_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	u16                  data;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, sbus_pmi_wr_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_sbus_pmi_wr_data_get(core_lgrp, &data);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "sbus_pmi wr data show (data = 0x%04X)", data);
+
+	return sysfs_emit(buf, "0x%04X\n", data);
+}
+
+static ssize_t mask_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	u16                  mask;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, sbus_pmi_wr_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_sbus_pmi_wr_mask_get(core_lgrp, &mask);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "sbus_pmi wr mask show (mask = 0x%04X)", mask);
+
+	return sysfs_emit(buf, "0x%04X\n", mask);
+}
+
+static ssize_t dev_id_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	u8                   dev_id;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, sbus_pmi_wr_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_sbus_pmi_wr_dev_id_get(core_lgrp, &dev_id);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "sbus_pmi wr dev id show (dev_id = 0x%02X)", dev_id);
+
+	return sysfs_emit(buf, "0x%02X\n", dev_id);
+}
+
+static ssize_t lane_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	u8                   lane;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, sbus_pmi_wr_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_sbus_pmi_wr_lane_get(core_lgrp, &lane);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "sbus_pmi wr lane show (lane = 0x%02X)", lane);
+
+	return sysfs_emit(buf, "0x%02X\n", lane);
+}
+
+static ssize_t pll_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	u8                   pll;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, sbus_pmi_wr_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_sbus_pmi_wr_pll_get(core_lgrp, &pll);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "sbus_pmi wr pll show (pll = 0x%02X)", pll);
+
+	return sysfs_emit(buf, "0x%02X\n", pll);
+}
+
+static ssize_t result_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	int                  result;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, sbus_pmi_wr_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_sbus_pmi_wr_result_get(core_lgrp, &result);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "sbus_pmi wr result show (result = %d)", result);
+
+	return sysfs_emit(buf, "%d\n", result);
+}
+
+static struct kobj_attribute dev_addr = __ATTR_RO(dev_addr);
+static struct kobj_attribute addr     = __ATTR_RO(addr);
+static struct kobj_attribute data     = __ATTR_RO(data);
+static struct kobj_attribute mask     = __ATTR_RO(mask);
+static struct kobj_attribute dev_id   = __ATTR_RO(dev_id);
+static struct kobj_attribute lane     = __ATTR_RO(lane);
+static struct kobj_attribute pll      = __ATTR_RO(pll);
+static struct kobj_attribute result   = __ATTR_RO(result);
+
+static struct attribute *sbus_pmi_wr_attrs[] = {
+	&dev_addr.attr,
+	&addr.attr,
+	&data.attr,
+	&mask.attr,
+	&dev_id.attr,
+	&lane.attr,
+	&pll.attr,
+	&result.attr,
+	NULL,
+};
+ATTRIBUTE_GROUPS(sbus_pmi_wr);
+
+static struct kobj_type sbus_pmi_wr_info = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = sbus_pmi_wr_groups,
+};
+#endif /* CONFIG_SYSFS */
+
+int sl_sysfs_sbus_pmi_wr_create(struct sl_ctrl_lgrp *ctrl_lgrp, struct kobject *parent_kobj)
+{
+#ifdef CONFIG_SYSFS
+	int rtn;
+
+	rtn = kobject_init_and_add(&ctrl_lgrp->sbus_pmi_wr_kobj, &sbus_pmi_wr_info, parent_kobj, "wr");
+	if (rtn) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "sbus_pmi wr create kobject_init_and_add failed [%d]", rtn);
+		goto out_sbus_pmi_wr;
+	}
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "sbus_pmi wr create (sbus_pmi_wr_kobj = 0x%p)",
+		   &ctrl_lgrp->sbus_pmi_wr_kobj);
+	return 0;
+
+out_sbus_pmi_wr:
+	kobject_put(&ctrl_lgrp->sbus_pmi_wr_kobj);
+
+	return -ENOMEM;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_sbus_pmi_wr_delete(struct sl_ctrl_lgrp *ctrl_lgrp)
+{
+#ifdef CONFIG_SYSFS
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "sbus_pmi wr delete (lgrp = 0x%p)", ctrl_lgrp);
+
+	kobject_put(&ctrl_lgrp->sbus_pmi_wr_kobj);
+#endif /* CONFIG_SYSFS */
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_sbus_rd.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_sbus_rd.c
new file mode 100644
index 000000000000..8f4e74f9dd2d
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_sbus_rd.c
@@ -0,0 +1,197 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/sysfs.h>
+#include <linux/kobject.h>
+
+#include "sl_log.h"
+#include "sl_sysfs.h"
+#include "sl_ctrl_lgrp.h"
+#include "sl_ctrl_ldev.h"
+#include "sl_core_lgrp.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+#ifdef CONFIG_SYSFS
+static ssize_t dev_addr_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	u8                   dev_addr;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, sbus_rd_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_sbus_rd_dev_addr_get(core_lgrp, &dev_addr);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "sbus rd dev addr show (dev_addr = 0x%02X)", dev_addr);
+
+	return sysfs_emit(buf, "0x%02X\n", dev_addr);
+}
+
+static ssize_t data_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	u32                  data;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, sbus_rd_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_sbus_rd_data_get(core_lgrp, &data);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "sbus rd data show (data = 0x%08X)", data);
+
+	return sysfs_emit(buf, "0x%08X\n", data);
+}
+
+static ssize_t mask_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	u32                  mask;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, sbus_rd_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_sbus_rd_mask_get(core_lgrp, &mask);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "sbus rd mask show (mask = 0x%08X)", mask);
+
+	return sysfs_emit(buf, "0x%08X\n", mask);
+}
+
+static ssize_t reg_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	u8                   reg;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, sbus_rd_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_sbus_rd_reg_get(core_lgrp, &reg);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "sbus rd reg show (reg = 0x%02X)", reg);
+
+	return sysfs_emit(buf, "0x%02X\n", reg);
+}
+
+static ssize_t lsb_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	u8                   lsb;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, sbus_rd_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_sbus_rd_lsb_get(core_lgrp, &lsb);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "sbus rd lsb show (lsb = %u)", lsb);
+
+	return sysfs_emit(buf, "%u\n", lsb);
+}
+
+static ssize_t result_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	int                  result;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, sbus_rd_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_sbus_rd_result_get(core_lgrp, &result);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "sbus rd result show (result = %d)", result);
+
+	return sysfs_emit(buf, "%d\n", result);
+}
+
+static struct kobj_attribute dev_addr = __ATTR_RO(dev_addr);
+static struct kobj_attribute data     = __ATTR_RO(data);
+static struct kobj_attribute mask     = __ATTR_RO(mask);
+static struct kobj_attribute reg      = __ATTR_RO(reg);
+static struct kobj_attribute lsb      = __ATTR_RO(lsb);
+static struct kobj_attribute result   = __ATTR_RO(result);
+
+static struct attribute *sbus_rd_attrs[] = {
+	&dev_addr.attr,
+	&data.attr,
+	&mask.attr,
+	&reg.attr,
+	&lsb.attr,
+	&result.attr,
+	NULL,
+};
+ATTRIBUTE_GROUPS(sbus_rd);
+
+static struct kobj_type sbus_rd_info = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = sbus_rd_groups,
+};
+#endif /* CONFIG_SYSFS */
+
+int sl_sysfs_sbus_rd_create(struct sl_ctrl_lgrp *ctrl_lgrp, struct kobject *parent_kobj)
+{
+#ifdef CONFIG_SYSFS
+	int rtn;
+
+	rtn = kobject_init_and_add(&ctrl_lgrp->sbus_rd_kobj, &sbus_rd_info, parent_kobj, "rd");
+	if (rtn) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "sbus rd create kobject_init_and_add failed [%d]", rtn);
+		goto out_sbus_rd;
+	}
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "sbus rd create (sbus_rd_kobj = 0x%p)", &ctrl_lgrp->sbus_rd_kobj);
+	return 0;
+
+out_sbus_rd:
+	kobject_put(&ctrl_lgrp->sbus_rd_kobj);
+
+	return -ENOMEM;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_sbus_rd_delete(struct sl_ctrl_lgrp *ctrl_lgrp)
+{
+#ifdef CONFIG_SYSFS
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "sbus rd delete (lgrp = 0x%p)", ctrl_lgrp);
+
+	kobject_put(&ctrl_lgrp->sbus_rd_kobj);
+#endif /* CONFIG_SYSFS */
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_sbus_rst.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_sbus_rst.c
new file mode 100644
index 000000000000..872a80636630
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_sbus_rst.c
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/sysfs.h>
+#include <linux/kobject.h>
+
+#include "sl_log.h"
+#include "sl_sysfs.h"
+#include "sl_ctrl_lgrp.h"
+#include "sl_ctrl_ldev.h"
+#include "sl_core_lgrp.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+#ifdef CONFIG_SYSFS
+static ssize_t dev_addr_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	u8                   dev_addr;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, sbus_rst_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_sbus_rst_dev_addr_get(core_lgrp, &dev_addr);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "sbus rst dev addr show (dev_addr = 0x%02X)", dev_addr);
+
+	return sysfs_emit(buf, "0x%02X\n", dev_addr);
+}
+
+static ssize_t result_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	int                  result;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, sbus_rst_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_sbus_rst_result_get(core_lgrp, &result);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "sbus rst result show (result = %d)", result);
+
+	return sysfs_emit(buf, "%d\n", result);
+}
+
+static struct kobj_attribute dev_addr = __ATTR_RO(dev_addr);
+static struct kobj_attribute result   = __ATTR_RO(result);
+
+static struct attribute *sbus_rst_attrs[] = {
+	&dev_addr.attr,
+	&result.attr,
+	NULL,
+};
+ATTRIBUTE_GROUPS(sbus_rst);
+
+static struct kobj_type sbus_rst_info = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = sbus_rst_groups,
+};
+#endif /* CONFIG_SYSFS */
+
+int sl_sysfs_sbus_rst_create(struct sl_ctrl_lgrp *ctrl_lgrp, struct kobject *parent_kobj)
+{
+#ifdef CONFIG_SYSFS
+	int rtn;
+
+	rtn = kobject_init_and_add(&ctrl_lgrp->sbus_rst_kobj, &sbus_rst_info, parent_kobj, "rst");
+	if (rtn) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "sbus rst create kobject_init_and_add failed [%d]", rtn);
+		goto out_sbus_rst;
+	}
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "sbus rst create (sbus_rst_kobj = 0x%p)", &ctrl_lgrp->sbus_rst_kobj);
+	return 0;
+
+out_sbus_rst:
+	kobject_put(&ctrl_lgrp->sbus_rst_kobj);
+
+	return -ENOMEM;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_sbus_rst_delete(struct sl_ctrl_lgrp *ctrl_lgrp)
+{
+#ifdef CONFIG_SYSFS
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "sbus rst delete (lgrp = 0x%p)", ctrl_lgrp);
+
+	kobject_put(&ctrl_lgrp->sbus_rst_kobj);
+#endif /* CONFIG_SYSFS */
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_sbus_wr.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_sbus_wr.c
new file mode 100644
index 000000000000..036977d964d6
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_sbus_wr.c
@@ -0,0 +1,197 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/sysfs.h>
+#include <linux/kobject.h>
+
+#include "sl_log.h"
+#include "sl_sysfs.h"
+#include "sl_ctrl_lgrp.h"
+#include "sl_ctrl_ldev.h"
+#include "sl_core_lgrp.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+#ifdef CONFIG_SYSFS
+static ssize_t dev_addr_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	u8                   dev_addr;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, sbus_wr_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_sbus_wr_dev_addr_get(core_lgrp, &dev_addr);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "sbus wr dev addr show (dev_addr = 0x%02X)", dev_addr);
+
+	return sysfs_emit(buf, "0x%02X\n", dev_addr);
+}
+
+static ssize_t data_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	u32                  data;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, sbus_wr_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_sbus_wr_data_get(core_lgrp, &data);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "sbus wr data show (data = 0x%08X)", data);
+
+	return sysfs_emit(buf, "0x%08X\n", data);
+}
+
+static ssize_t mask_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	u32                  mask;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, sbus_wr_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_sbus_wr_mask_get(core_lgrp, &mask);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "sbus wr mask show (mask = 0x%08X)", mask);
+
+	return sysfs_emit(buf, "0x%08X\n", mask);
+}
+
+static ssize_t reg_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	u8                   reg;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, sbus_wr_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_sbus_wr_reg_get(core_lgrp, &reg);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "sbus wr reg show (reg = 0x%02X)", reg);
+
+	return sysfs_emit(buf, "0x%02X\n", reg);
+}
+
+static ssize_t lsb_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	u8                   lsb;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, sbus_wr_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_sbus_wr_lsb_get(core_lgrp, &lsb);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "sbus wr lsb show (lsb = %u)", lsb);
+
+	return sysfs_emit(buf, "%u\n", lsb);
+}
+
+static ssize_t result_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	int                  result;
+	int                  rtn;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, sbus_wr_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_sbus_wr_result_get(core_lgrp, &result);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "sbus wr result show (result = %d)", result);
+
+	return sysfs_emit(buf, "%d\n", result);
+}
+
+static struct kobj_attribute dev_addr = __ATTR_RO(dev_addr);
+static struct kobj_attribute data     = __ATTR_RO(data);
+static struct kobj_attribute mask     = __ATTR_RO(mask);
+static struct kobj_attribute reg      = __ATTR_RO(reg);
+static struct kobj_attribute lsb      = __ATTR_RO(lsb);
+static struct kobj_attribute result   = __ATTR_RO(result);
+
+static struct attribute *sbus_wr_attrs[] = {
+	&dev_addr.attr,
+	&data.attr,
+	&mask.attr,
+	&reg.attr,
+	&lsb.attr,
+	&result.attr,
+	NULL,
+};
+ATTRIBUTE_GROUPS(sbus_wr);
+
+static struct kobj_type sbus_wr_info = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = sbus_wr_groups,
+};
+#endif /* CONFIG_SYSFS */
+
+int sl_sysfs_sbus_wr_create(struct sl_ctrl_lgrp *ctrl_lgrp, struct kobject *parent_kobj)
+{
+#ifdef CONFIG_SYSFS
+	int rtn;
+
+	rtn = kobject_init_and_add(&ctrl_lgrp->sbus_wr_kobj, &sbus_wr_info, parent_kobj, "wr");
+	if (rtn) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "sbus wr create kobject_init_and_add failed [%d]", rtn);
+		goto out_sbus_wr;
+	}
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "sbus wr create (sbus_wr_kobj = 0x%p)", &ctrl_lgrp->sbus_wr_kobj);
+	return 0;
+
+out_sbus_wr:
+	kobject_put(&ctrl_lgrp->sbus_wr_kobj);
+
+	return -ENOMEM;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_sbus_wr_delete(struct sl_ctrl_lgrp *ctrl_lgrp)
+{
+#ifdef CONFIG_SYSFS
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "sbus wr delete (lgrp = 0x%p)", ctrl_lgrp);
+
+	kobject_put(&ctrl_lgrp->sbus_wr_kobj);
+#endif /* CONFIG_SYSFS */
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_serdes.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_serdes.c
new file mode 100644
index 000000000000..08d2858fea54
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_serdes.c
@@ -0,0 +1,302 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2024-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kobject.h>
+#include <linux/sysfs.h>
+
+#include "sl_log.h"
+#include "sl_sysfs.h"
+#include "sl_ctrl_lgrp.h"
+#include "sl_ctrl_ldev.h"
+#include "sl_core_lgrp.h"
+#include "sl_core_str.h"
+#include "sl_sysfs_serdes_settings.h"
+#include "sl_sysfs_serdes_eye.h"
+#include "sl_sysfs_serdes_state.h"
+#include "sl_sysfs_serdes_swizzle.h"
+#include "sl_sysfs_serdes_lol.h"
+#include "sl_sysfs_serdes_los.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+u8 lane_num_to_link_num(struct sl_ctrl_lgrp *ctrl_lgrp, u8 lane_num)
+{
+	switch (ctrl_lgrp->config.furcation) {
+	case SL_MEDIA_FURCATION_X1:
+	default:
+		return 0;
+	case SL_MEDIA_FURCATION_X2:
+		if (lane_num & BIT(1))
+			return 1;
+		else
+			return 0;
+	case SL_MEDIA_FURCATION_X4:
+		return lane_num;
+	}
+}
+
+#ifdef CONFIG_SYSFS
+static ssize_t hw_rev_1_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, serdes_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME,
+		   "hw ver show (hw_rev_1 = 0x%X)",
+		core_lgrp->core_ldev->serdes.hw_info[LGRP_TO_SERDES(core_lgrp->num)].rev_id_1);
+
+	return sysfs_emit(buf, "0x%X\n",
+		core_lgrp->core_ldev->serdes.hw_info[LGRP_TO_SERDES(core_lgrp->num)].rev_id_1);
+}
+
+static ssize_t hw_rev_2_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, serdes_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME,
+		   "hw ver show (hw_rev_2 = 0x%X)",
+		core_lgrp->core_ldev->serdes.hw_info[LGRP_TO_SERDES(core_lgrp->num)].rev_id_2);
+
+	return sysfs_emit(buf, "0x%X\n",
+		core_lgrp->core_ldev->serdes.hw_info[LGRP_TO_SERDES(core_lgrp->num)].rev_id_2);
+}
+
+static ssize_t hw_version_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, serdes_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME,
+		   "hw ver show (hw_version = 0x%X)",
+		core_lgrp->core_ldev->serdes.hw_info[LGRP_TO_SERDES(core_lgrp->num)].version);
+
+	return sysfs_emit(buf, "0x%X\n",
+		core_lgrp->core_ldev->serdes.hw_info[LGRP_TO_SERDES(core_lgrp->num)].version);
+}
+
+static ssize_t fw_signature_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, serdes_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME,
+		   "fw signature show (fw_signature = 0x%X)",
+		core_lgrp->core_ldev->serdes.fw_info[LGRP_TO_SERDES(core_lgrp->num)].signature);
+
+	return sysfs_emit(buf, "0x%X\n",
+		core_lgrp->core_ldev->serdes.fw_info[LGRP_TO_SERDES(core_lgrp->num)].signature);
+}
+
+static ssize_t fw_version_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+
+	ctrl_lgrp = container_of(kobj, struct sl_ctrl_lgrp, serdes_kobj);
+	core_lgrp = sl_core_lgrp_get(ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME,
+		   "fw version show (fw_version = 0x%X)",
+		core_lgrp->core_ldev->serdes.fw_info[LGRP_TO_SERDES(core_lgrp->num)].version);
+
+	return sysfs_emit(buf, "0x%X\n",
+		core_lgrp->core_ldev->serdes.fw_info[LGRP_TO_SERDES(core_lgrp->num)].version);
+}
+
+static struct kobj_attribute hw_rev_id_1   = __ATTR_RO(hw_rev_1);
+static struct kobj_attribute hw_rev_id_2   = __ATTR_RO(hw_rev_2);
+static struct kobj_attribute hw_version    = __ATTR_RO(hw_version);
+static struct kobj_attribute fw_signature  = __ATTR_RO(fw_signature);
+static struct kobj_attribute fw_version    = __ATTR_RO(fw_version);
+
+static struct attribute *serdes_attrs[] = {
+	&hw_rev_id_1.attr,
+	&hw_rev_id_2.attr,
+	&hw_version.attr,
+	&fw_signature.attr,
+	&fw_version.attr,
+	NULL
+};
+ATTRIBUTE_GROUPS(serdes);
+
+static struct kobj_type serdes_info = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = serdes_groups,
+};
+
+static struct attribute *serdes_lane_attrs[] = {
+	NULL,
+};
+ATTRIBUTE_GROUPS(serdes_lane);
+
+static struct kobj_type serdes_lane_info = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = serdes_lane_groups,
+};
+#endif /* CONFIG_SYSFS */
+
+int sl_sysfs_serdes_create(struct sl_ctrl_lgrp *ctrl_lgrp)
+{
+#ifdef CONFIG_SYSFS
+	int rtn;
+	int asic_lane_num;
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "serdes create (lgrp = 0x%p)", ctrl_lgrp);
+
+	if (!ctrl_lgrp->parent_kobj) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "serdes create missing parent");
+		return -EBADRQC;
+	}
+
+	rtn = kobject_init_and_add(&(ctrl_lgrp->serdes_kobj),
+				   &serdes_info, ctrl_lgrp->parent_kobj, "serdes");
+	if (rtn) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+			   "serdes create kobject_init_and_add failed [%d]", rtn);
+		goto out_serdes;
+	}
+
+	rtn = kobject_init_and_add(&(ctrl_lgrp->serdes_lane_kobj),
+				   &serdes_lane_info, &(ctrl_lgrp->serdes_kobj), "lane");
+	if (rtn) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+			   "serdes create kobject_init_and_add failed [%d]", rtn);
+		goto out_lane;
+	}
+
+	for (asic_lane_num = 0; asic_lane_num < SL_ASIC_MAX_LANES; ++asic_lane_num) {
+
+		rtn = kobject_init_and_add(&(ctrl_lgrp->serdes_lane_kobjs[asic_lane_num]),
+					   &serdes_lane_info, &(ctrl_lgrp->serdes_lane_kobj), "%u", asic_lane_num);
+		if (rtn) {
+			sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+				   "serdes create lane kobject_init_and_add failed [%d]", rtn);
+			goto out_lanes;
+		}
+
+		rtn = sl_sysfs_serdes_lane_state_create(ctrl_lgrp, asic_lane_num);
+		if (rtn) {
+			sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+				   "serdes_lane_state_create failed [%d]", rtn);
+			goto out_lanes;
+		}
+
+		rtn = sl_sysfs_serdes_lane_swizzle_create(ctrl_lgrp, asic_lane_num);
+		if (rtn) {
+			sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+				   "serdes_lane_swizzle_create failed [%d]", rtn);
+			goto out_state;
+		}
+
+		rtn = sl_sysfs_serdes_lane_settings_create(ctrl_lgrp, asic_lane_num);
+		if (rtn) {
+			sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+				   "serdes_lane_settings_create failed [%d]", rtn);
+			goto out_swizzle;
+		}
+
+		rtn = sl_sysfs_serdes_lane_eye_create(ctrl_lgrp, asic_lane_num);
+		if (rtn) {
+			sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+				   "serdes_lane_eye_create failed [%d]", rtn);
+			goto out_settings;
+		}
+
+		rtn = sl_sysfs_serdes_lane_lol_create(ctrl_lgrp, asic_lane_num);
+		if (rtn) {
+			sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+				   "serdes_lane_lol_create failed [%d]", rtn);
+			goto out_eye;
+		}
+
+		rtn = sl_sysfs_serdes_lane_los_create(ctrl_lgrp, asic_lane_num);
+		if (rtn) {
+			sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+				   "serdes_lane_los_create failed [%d]", rtn);
+			goto out_lol;
+		}
+	}
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "serdes create (serdes_kobj = 0x%p)", &(ctrl_lgrp->serdes_kobj));
+	return 0;
+
+out_lol:
+	sl_sysfs_serdes_lane_lol_delete(ctrl_lgrp, asic_lane_num);
+out_eye:
+	sl_sysfs_serdes_lane_eye_delete(ctrl_lgrp, asic_lane_num);
+out_settings:
+	sl_sysfs_serdes_lane_settings_delete(ctrl_lgrp, asic_lane_num);
+out_swizzle:
+	sl_sysfs_serdes_lane_swizzle_delete(ctrl_lgrp, asic_lane_num);
+out_state:
+	sl_sysfs_serdes_lane_state_delete(ctrl_lgrp, asic_lane_num);
+out_lanes:
+	kobject_put(&(ctrl_lgrp->serdes_lane_kobjs[asic_lane_num]));
+	for (asic_lane_num = asic_lane_num - 1; asic_lane_num >= 0; --asic_lane_num) {
+		sl_sysfs_serdes_lane_los_delete(ctrl_lgrp, asic_lane_num);
+		sl_sysfs_serdes_lane_lol_delete(ctrl_lgrp, asic_lane_num);
+		sl_sysfs_serdes_lane_eye_delete(ctrl_lgrp, asic_lane_num);
+		sl_sysfs_serdes_lane_settings_delete(ctrl_lgrp, asic_lane_num);
+		sl_sysfs_serdes_lane_swizzle_delete(ctrl_lgrp, asic_lane_num);
+		sl_sysfs_serdes_lane_state_delete(ctrl_lgrp, asic_lane_num);
+		kobject_put(&(ctrl_lgrp->serdes_lane_kobjs[asic_lane_num]));
+	}
+out_lane:
+	kobject_put(&(ctrl_lgrp->serdes_lane_kobj));
+out_serdes:
+	kobject_put(&(ctrl_lgrp->serdes_kobj));
+
+	return -ENOMEM;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_serdes_delete(struct sl_ctrl_lgrp *ctrl_lgrp)
+{
+#ifdef CONFIG_SYSFS
+	u8 asic_lane_num;
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME, "serdes delete (lgrp = 0x%p)", ctrl_lgrp);
+
+	if (!ctrl_lgrp->parent_kobj)
+		return;
+
+	for (asic_lane_num = 0; asic_lane_num < SL_ASIC_MAX_LANES; ++asic_lane_num) {
+		sl_sysfs_serdes_lane_los_delete(ctrl_lgrp, asic_lane_num);
+		sl_sysfs_serdes_lane_lol_delete(ctrl_lgrp, asic_lane_num);
+		sl_sysfs_serdes_lane_eye_delete(ctrl_lgrp, asic_lane_num);
+		sl_sysfs_serdes_lane_settings_delete(ctrl_lgrp, asic_lane_num);
+		sl_sysfs_serdes_lane_swizzle_delete(ctrl_lgrp, asic_lane_num);
+		sl_sysfs_serdes_lane_state_delete(ctrl_lgrp, asic_lane_num);
+		kobject_put(&(ctrl_lgrp->serdes_lane_kobjs[asic_lane_num]));
+	}
+	kobject_put(&(ctrl_lgrp->serdes_lane_kobj));
+	kobject_put(&ctrl_lgrp->serdes_kobj);
+#endif /* CONFIG_SYSFS */
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_serdes_eye.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_serdes_eye.c
new file mode 100644
index 000000000000..9dac679a96d9
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_serdes_eye.c
@@ -0,0 +1,197 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2024-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kobject.h>
+#include <linux/sysfs.h>
+
+#include "sl_log.h"
+#include "sl_sysfs.h"
+#include "sl_ctrl_lgrp.h"
+#include "sl_ctrl_ldev.h"
+#include "sl_core_lgrp.h"
+#include "sl_core_link.h"
+#include "sl_sysfs_serdes_eye.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+#ifdef CONFIG_SYSFS
+static ssize_t value_upper_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                              rtn;
+	struct sl_lgrp_serdes_lane_kobj *lane_kobj;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+	u8                               eye_upper;
+
+	lane_kobj = container_of(kobj, struct sl_lgrp_serdes_lane_kobj, kobj);
+	if (!lane_kobj->ctrl_lgrp)
+		return sysfs_emit(buf, "no-lane\n");
+
+	core_link = sl_core_link_get(lane_kobj->ctrl_lgrp->ctrl_ldev->num, lane_kobj->ctrl_lgrp->num,
+				     lane_num_to_link_num(lane_kobj->ctrl_lgrp, lane_kobj->asic_lane_num));
+	if (!core_link)
+		return sysfs_emit(buf, "no-link\n");
+
+	core_lgrp = sl_core_lgrp_get(lane_kobj->ctrl_lgrp->ctrl_ldev->num, lane_kobj->ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_eye_upper_get(core_lgrp, lane_kobj->asic_lane_num, &eye_upper);
+	if (rtn == -EIO)
+		return sysfs_emit(buf, "no-serdes\n");
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME,
+		   "eye value upper show (asic_lane_num = %u, eye = %u)",
+		lane_kobj->asic_lane_num, eye_upper);
+
+	return sysfs_emit(buf, "%u\n", eye_upper);
+}
+
+static ssize_t value_lower_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                              rtn;
+	struct sl_lgrp_serdes_lane_kobj *lane_kobj;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+	u8                               eye_lower;
+
+	lane_kobj = container_of(kobj, struct sl_lgrp_serdes_lane_kobj, kobj);
+	if (!lane_kobj->ctrl_lgrp)
+		return sysfs_emit(buf, "no-lane\n");
+
+	core_link = sl_core_link_get(lane_kobj->ctrl_lgrp->ctrl_ldev->num, lane_kobj->ctrl_lgrp->num,
+				     lane_num_to_link_num(lane_kobj->ctrl_lgrp, lane_kobj->asic_lane_num));
+	if (!core_link)
+		return sysfs_emit(buf, "no-link\n");
+
+	core_lgrp = sl_core_lgrp_get(lane_kobj->ctrl_lgrp->ctrl_ldev->num, lane_kobj->ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_eye_lower_get(core_lgrp, lane_kobj->asic_lane_num, &eye_lower);
+	if (rtn == -EIO)
+		return sysfs_emit(buf, "no-serdes\n");
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME,
+		   "eye value lower show (asic_lane_num = %u, eye = %u)",
+		lane_kobj->asic_lane_num, eye_lower);
+
+	return sysfs_emit(buf, "%u\n", eye_lower);
+}
+
+static ssize_t limit_high_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_lgrp_serdes_lane_kobj *lane_kobj;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+
+	lane_kobj = container_of(kobj, struct sl_lgrp_serdes_lane_kobj, kobj);
+	if (!lane_kobj->ctrl_lgrp)
+		return sysfs_emit(buf, "no-lane\n");
+
+	core_link = sl_core_link_get(lane_kobj->ctrl_lgrp->ctrl_ldev->num, lane_kobj->ctrl_lgrp->num,
+				     lane_num_to_link_num(lane_kobj->ctrl_lgrp, lane_kobj->asic_lane_num));
+	if (!core_link)
+		return sysfs_emit(buf, "no-link\n");
+
+	core_lgrp = sl_core_lgrp_get(lane_kobj->ctrl_lgrp->ctrl_ldev->num, lane_kobj->ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME,
+		   "eye limit high show (asic_lane_num = %u, limit = %u)",
+		lane_kobj->asic_lane_num, core_lgrp->serdes.eye_limits[lane_kobj->asic_lane_num].high);
+
+	return sysfs_emit(buf, "%u\n",
+		core_lgrp->serdes.eye_limits[lane_kobj->asic_lane_num].high);
+}
+
+static ssize_t limit_low_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_lgrp_serdes_lane_kobj *lane_kobj;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+
+	lane_kobj = container_of(kobj, struct sl_lgrp_serdes_lane_kobj, kobj);
+	if (!lane_kobj->ctrl_lgrp)
+		return sysfs_emit(buf, "no-lane\n");
+
+	core_link = sl_core_link_get(lane_kobj->ctrl_lgrp->ctrl_ldev->num, lane_kobj->ctrl_lgrp->num,
+				     lane_num_to_link_num(lane_kobj->ctrl_lgrp, lane_kobj->asic_lane_num));
+	if (!core_link)
+		return sysfs_emit(buf, "no-link\n");
+
+	core_lgrp = sl_core_lgrp_get(lane_kobj->ctrl_lgrp->ctrl_ldev->num, lane_kobj->ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME,
+		   "eye limit low show (asic_lane_num = %u, limit = %u)",
+		lane_kobj->asic_lane_num, core_lgrp->serdes.eye_limits[lane_kobj->asic_lane_num].low);
+
+	return sysfs_emit(buf, "%u\n",
+		core_lgrp->serdes.eye_limits[lane_kobj->asic_lane_num].low);
+}
+
+static struct kobj_attribute eye_value_upper = __ATTR_RO(value_upper);
+static struct kobj_attribute eye_value_lower = __ATTR_RO(value_lower);
+static struct kobj_attribute eye_limit_high  = __ATTR_RO(limit_high);
+static struct kobj_attribute eye_limit_low   = __ATTR_RO(limit_low);
+
+static struct attribute *serdes_lane_eye_attrs[] = {
+	&eye_value_upper.attr,
+	&eye_value_lower.attr,
+	&eye_limit_high.attr,
+	&eye_limit_low.attr,
+	NULL,
+};
+ATTRIBUTE_GROUPS(serdes_lane_eye);
+
+static struct kobj_type serdes_lane_eye_info = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = serdes_lane_eye_groups,
+};
+#endif /* CONFIG_SYSFS */
+
+int sl_sysfs_serdes_lane_eye_create(struct sl_ctrl_lgrp *ctrl_lgrp, u8 asic_lane_num)
+{
+#ifdef CONFIG_SYSFS
+	int rtn;
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "serdes lane eye create (lgrp = 0x%p)", ctrl_lgrp);
+
+	rtn = kobject_init_and_add(&(ctrl_lgrp->serdes_lane_eye_kobjs[asic_lane_num].kobj),
+				   &serdes_lane_eye_info, &(ctrl_lgrp->serdes_lane_kobjs[asic_lane_num]), "eye");
+	if (rtn) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+			   "serdes lane eye create kobject_init_and_add failed [%d]", rtn);
+		kobject_put(&(ctrl_lgrp->serdes_lane_eye_kobjs[asic_lane_num].kobj));
+		return -ENOMEM;
+	}
+	ctrl_lgrp->serdes_lane_eye_kobjs[asic_lane_num].ctrl_lgrp      = ctrl_lgrp;
+	ctrl_lgrp->serdes_lane_eye_kobjs[asic_lane_num].asic_lane_num = asic_lane_num;
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "serdes lane eye create (serdes_kobj = 0x%p)", &(ctrl_lgrp->serdes_kobj));
+	return 0;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_serdes_lane_eye_delete(struct sl_ctrl_lgrp *ctrl_lgrp, u8 asic_lane_num)
+{
+#ifdef CONFIG_SYSFS
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "serdes lane eye delete (lgrp = 0x%p)", ctrl_lgrp);
+
+	kobject_put(&(ctrl_lgrp->serdes_lane_eye_kobjs[asic_lane_num].kobj));
+	ctrl_lgrp->serdes_lane_eye_kobjs[asic_lane_num].ctrl_lgrp = NULL;
+#endif /* CONFIG_SYSFS */
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_serdes_lol.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_serdes_lol.c
new file mode 100644
index 000000000000..d7162e985822
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_serdes_lol.c
@@ -0,0 +1,141 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2025-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kobject.h>
+#include <linux/sysfs.h>
+
+#include "sl_log.h"
+#include "sl_ctrl_lgrp.h"
+#include "sl_ctrl_ldev.h"
+#include "sl_core_lgrp.h"
+#include "sl_sysfs_serdes_lol.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+#ifdef CONFIG_SYSFS
+static ssize_t tx_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                              rtn;
+	struct sl_lgrp_serdes_lane_kobj *lane_kobj;
+	bool                             is_tx_lol;
+	struct sl_ctrl_lgrp             *ctrl_lgrp;
+	u8                               ldev_num;
+	u8                               lgrp_num;
+
+	lane_kobj = container_of(kobj, struct sl_lgrp_serdes_lane_kobj, kobj);
+	ctrl_lgrp = lane_kobj->ctrl_lgrp;
+	ldev_num = lane_kobj->ctrl_lgrp->ctrl_ldev->num;
+	lgrp_num = lane_kobj->ctrl_lgrp->num;
+
+	rtn = sl_core_lgrp_tx_lane_is_lol(ldev_num, lgrp_num, lane_kobj->asic_lane_num, &is_tx_lol);
+	if (rtn == -ENOENT) {
+		sl_core_log_dbg(ctrl_lgrp, LOG_NAME,
+				"lol tx show (asic_lane_num = %u) - tx_lane_is_lol no cache [%d]",
+				lane_kobj->asic_lane_num, rtn);
+		return sysfs_emit(buf, "no-cache\n");
+	}
+
+	if (rtn) {
+		sl_core_log_err_trace(ctrl_lgrp, LOG_NAME,
+				      "lol tx show (asic_lane_num = %u) - tx_lane_is_lol failed [%d]",
+				      lane_kobj->asic_lane_num, rtn);
+		return sysfs_emit(buf, "error\n");
+	}
+
+	sl_core_log_dbg(ctrl_lgrp, LOG_NAME,
+			"lol tx show (asic_lane_num = %u, is_tx_lol = %s)",
+			lane_kobj->asic_lane_num, is_tx_lol ? "yes" : "no");
+
+	return sysfs_emit(buf, "%s\n", is_tx_lol ? "yes" : "no");
+}
+
+static ssize_t rx_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                              rtn;
+	struct sl_lgrp_serdes_lane_kobj *lane_kobj;
+	bool                             is_rx_lol;
+	struct sl_ctrl_lgrp             *ctrl_lgrp;
+	u8                               ldev_num;
+	u8                               lgrp_num;
+
+	lane_kobj = container_of(kobj, struct sl_lgrp_serdes_lane_kobj, kobj);
+	ctrl_lgrp = lane_kobj->ctrl_lgrp;
+	ldev_num = lane_kobj->ctrl_lgrp->ctrl_ldev->num;
+	lgrp_num = lane_kobj->ctrl_lgrp->num;
+
+	rtn = sl_core_lgrp_rx_lane_is_lol(ldev_num, lgrp_num, lane_kobj->asic_lane_num, &is_rx_lol);
+	if (rtn == -ENOENT) {
+		sl_core_log_dbg(ctrl_lgrp, LOG_NAME,
+				"lol rx show (asic_lane_num = %u) - rx_lane_is_lol no cache [%d]",
+				lane_kobj->asic_lane_num, rtn);
+		return sysfs_emit(buf, "no-cache\n");
+	}
+
+	if (rtn) {
+		sl_core_log_err_trace(ctrl_lgrp, LOG_NAME,
+				      "lol rx show (asic_lane_num = %u) - rx_lane_is_lol failed [%d]",
+				      lane_kobj->asic_lane_num, rtn);
+		return sysfs_emit(buf, "error\n");
+	}
+
+	sl_core_log_dbg(ctrl_lgrp, LOG_NAME,
+			"lol rx show (asic_lane_num = %u, is_rx_lol = %s)",
+			lane_kobj->asic_lane_num, is_rx_lol ? "yes" : "no");
+
+	return sysfs_emit(buf, "%s\n", is_rx_lol ? "yes" : "no");
+}
+
+static struct kobj_attribute lol_tx = __ATTR_RO(tx);
+static struct kobj_attribute lol_rx = __ATTR_RO(rx);
+
+static struct attribute *serdes_lane_lol_attrs[] = {
+	&lol_tx.attr,
+	&lol_rx.attr,
+	NULL,
+};
+ATTRIBUTE_GROUPS(serdes_lane_lol);
+
+static struct kobj_type serdes_lane_lol_info = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = serdes_lane_lol_groups,
+};
+#endif /* CONFIG_SYSFS */
+
+int sl_sysfs_serdes_lane_lol_create(struct sl_ctrl_lgrp *ctrl_lgrp, u8 asic_lane_num)
+{
+#ifdef CONFIG_SYSFS
+	int rtn;
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "serdes lane lol create (lgrp = 0x%p)", ctrl_lgrp);
+
+	rtn = kobject_init_and_add(&ctrl_lgrp->serdes_lane_lol_kobjs[asic_lane_num].kobj,
+				   &serdes_lane_lol_info, &ctrl_lgrp->serdes_lane_kobjs[asic_lane_num], "lol");
+	if (rtn) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+			   "serdes lane lol create kobject_init_and_add failed [%d]", rtn);
+		kobject_put(&ctrl_lgrp->serdes_lane_lol_kobjs[asic_lane_num].kobj);
+		return -ENOMEM;
+	}
+	ctrl_lgrp->serdes_lane_lol_kobjs[asic_lane_num].ctrl_lgrp     = ctrl_lgrp;
+	ctrl_lgrp->serdes_lane_lol_kobjs[asic_lane_num].asic_lane_num = asic_lane_num;
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "serdes lane lol create (serdes_kobj = 0x%p)", &ctrl_lgrp->serdes_kobj);
+	return 0;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_serdes_lane_lol_delete(struct sl_ctrl_lgrp *ctrl_lgrp, u8 asic_lane_num)
+{
+#ifdef CONFIG_SYSFS
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "serdes lane los delete (lgrp = 0x%p)", ctrl_lgrp);
+
+	kobject_put(&ctrl_lgrp->serdes_lane_lol_kobjs[asic_lane_num].kobj);
+	ctrl_lgrp->serdes_lane_lol_kobjs[asic_lane_num].ctrl_lgrp = NULL;
+#endif /* CONFIG_SYSFS */
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_serdes_los.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_serdes_los.c
new file mode 100644
index 000000000000..bdcb6b8ae4ae
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_serdes_los.c
@@ -0,0 +1,142 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2025-2026 Hewlett Packard Enterprise Development LP */
+
+#include "asm-generic/int-ll64.h"
+#include <linux/kobject.h>
+#include <linux/sysfs.h>
+
+#include "sl_log.h"
+#include "sl_ctrl_lgrp.h"
+#include "sl_ctrl_ldev.h"
+#include "sl_core_lgrp.h"
+#include "sl_sysfs_serdes_los.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+#ifdef CONFIG_SYSFS
+static ssize_t tx_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                              rtn;
+	struct sl_lgrp_serdes_lane_kobj *lane_kobj;
+	bool                             is_tx_los;
+	struct sl_ctrl_lgrp             *ctrl_lgrp;
+	u8                               ldev_num;
+	u8                               lgrp_num;
+
+	lane_kobj = container_of(kobj, struct sl_lgrp_serdes_lane_kobj, kobj);
+	ctrl_lgrp = lane_kobj->ctrl_lgrp;
+	ldev_num = lane_kobj->ctrl_lgrp->ctrl_ldev->num;
+	lgrp_num = lane_kobj->ctrl_lgrp->num;
+
+	rtn = sl_core_lgrp_tx_lane_is_los(ldev_num, lgrp_num, lane_kobj->asic_lane_num, &is_tx_los);
+	if (rtn == -ENOENT) {
+		sl_core_log_dbg(ctrl_lgrp, LOG_NAME,
+				"los tx show (asic_lane_num = %u) - tx_lane_is_los no cache [%d]",
+				lane_kobj->asic_lane_num, rtn);
+		return sysfs_emit(buf, "no-cache\n");
+	}
+
+	if (rtn) {
+		sl_core_log_err_trace(ctrl_lgrp, LOG_NAME,
+				      "los tx show (asic_lane_num = %u) - tx_lane_is_los failed [%d]",
+				      lane_kobj->asic_lane_num, rtn);
+		return sysfs_emit(buf, "error\n");
+	}
+
+	sl_core_log_dbg(ctrl_lgrp, LOG_NAME,
+			"los tx show (asic_lane_num = %u, is_tx_los = %s)",
+			lane_kobj->asic_lane_num, is_tx_los ? "yes" : "no");
+
+	return sysfs_emit(buf, "%s\n", is_tx_los ? "yes" : "no");
+}
+
+static ssize_t rx_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	int                              rtn;
+	struct sl_lgrp_serdes_lane_kobj *lane_kobj;
+	bool                             is_rx_los;
+	struct sl_ctrl_lgrp             *ctrl_lgrp;
+	u8                               ldev_num;
+	u8                               lgrp_num;
+
+	lane_kobj = container_of(kobj, struct sl_lgrp_serdes_lane_kobj, kobj);
+	ctrl_lgrp = lane_kobj->ctrl_lgrp;
+	ldev_num = lane_kobj->ctrl_lgrp->ctrl_ldev->num;
+	lgrp_num = lane_kobj->ctrl_lgrp->num;
+
+	rtn = sl_core_lgrp_rx_lane_is_los(ldev_num, lgrp_num, lane_kobj->asic_lane_num, &is_rx_los);
+	if (rtn == -ENOENT) {
+		sl_core_log_dbg(ctrl_lgrp, LOG_NAME,
+				"los rx show (asic_lane_num = %u) - rx_lane_is_los no cache [%d]",
+				lane_kobj->asic_lane_num, rtn);
+		return sysfs_emit(buf, "no-cache\n");
+	}
+
+	if (rtn) {
+		sl_core_log_err_trace(ctrl_lgrp, LOG_NAME,
+				      "los rx show (asic_lane_num = %u) - rx_lane_is_los failed [%d]",
+				      lane_kobj->asic_lane_num, rtn);
+		return sysfs_emit(buf, "error\n");
+	}
+
+	sl_core_log_dbg(ctrl_lgrp, LOG_NAME,
+			"los rx show (asic_lane_num = %u, is_rx_los = %s)",
+			lane_kobj->asic_lane_num, is_rx_los ? "yes" : "no");
+
+	return sysfs_emit(buf, "%s\n", is_rx_los ? "yes" : "no");
+}
+
+static struct kobj_attribute los_tx = __ATTR_RO(tx);
+static struct kobj_attribute los_rx = __ATTR_RO(rx);
+
+static struct attribute *serdes_lane_los_attrs[] = {
+	&los_tx.attr,
+	&los_rx.attr,
+	NULL,
+};
+ATTRIBUTE_GROUPS(serdes_lane_los);
+
+static struct kobj_type serdes_lane_los_info = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = serdes_lane_los_groups,
+};
+#endif /* CONFIG_SYSFS */
+
+int sl_sysfs_serdes_lane_los_create(struct sl_ctrl_lgrp *ctrl_lgrp, u8 asic_lane_num)
+{
+#ifdef CONFIG_SYSFS
+	int rtn;
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "serdes lane los create (lgrp = 0x%p)", ctrl_lgrp);
+
+	rtn = kobject_init_and_add(&ctrl_lgrp->serdes_lane_los_kobjs[asic_lane_num].kobj,
+				   &serdes_lane_los_info, &ctrl_lgrp->serdes_lane_kobjs[asic_lane_num], "los");
+	if (rtn) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+			   "serdes lane los create kobject_init_and_add failed [%d]", rtn);
+		kobject_put(&ctrl_lgrp->serdes_lane_los_kobjs[asic_lane_num].kobj);
+		return -ENOMEM;
+	}
+	ctrl_lgrp->serdes_lane_los_kobjs[asic_lane_num].ctrl_lgrp     = ctrl_lgrp;
+	ctrl_lgrp->serdes_lane_los_kobjs[asic_lane_num].asic_lane_num = asic_lane_num;
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "serdes lane los create (serdes_kobj = 0x%p)", &ctrl_lgrp->serdes_kobj);
+	return 0;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_serdes_lane_los_delete(struct sl_ctrl_lgrp *ctrl_lgrp, u8 asic_lane_num)
+{
+#ifdef CONFIG_SYSFS
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "serdes lane los delete (lgrp = 0x%p)", ctrl_lgrp);
+
+	kobject_put(&ctrl_lgrp->serdes_lane_los_kobjs[asic_lane_num].kobj);
+	ctrl_lgrp->serdes_lane_los_kobjs[asic_lane_num].ctrl_lgrp = NULL;
+#endif /* CONFIG_SYSFS */
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_serdes_settings.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_serdes_settings.c
new file mode 100644
index 000000000000..b33174640663
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_serdes_settings.c
@@ -0,0 +1,506 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2024-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kobject.h>
+#include <linux/sysfs.h>
+
+#include <linux/hpe/sl/sl_media.h>
+
+#include "sl_log.h"
+#include "sl_sysfs.h"
+#include "sl_ctrl_lgrp.h"
+#include "sl_ctrl_ldev.h"
+#include "sl_core_lgrp.h"
+#include "sl_core_link.h"
+#include "sl_core_str.h"
+#include "sl_sysfs_serdes_settings.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+#ifdef CONFIG_SYSFS
+static ssize_t pre1_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_lgrp_serdes_lane_kobj *lane_kobj;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+	s16                              pre1;
+	int				 rtn;
+
+	lane_kobj = container_of(kobj, struct sl_lgrp_serdes_lane_kobj, kobj);
+	if (!lane_kobj->ctrl_lgrp)
+		return sysfs_emit(buf, "no-lane\n");
+
+	core_link = sl_core_link_get(lane_kobj->ctrl_lgrp->ctrl_ldev->num, lane_kobj->ctrl_lgrp->num,
+				     lane_num_to_link_num(lane_kobj->ctrl_lgrp, lane_kobj->asic_lane_num));
+	if (!core_link)
+		return sysfs_emit(buf, "no-link\n");
+
+	core_lgrp = sl_core_lgrp_get(lane_kobj->ctrl_lgrp->ctrl_ldev->num, lane_kobj->ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_pre1_get(core_lgrp, lane_kobj->asic_lane_num, &pre1);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "settings pre1 show (pre1 = %d)", pre1);
+
+	return sysfs_emit(buf, "%d\n", pre1);
+}
+
+static ssize_t pre2_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_lgrp_serdes_lane_kobj *lane_kobj;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+	s16                              pre2;
+	int				 rtn;
+
+	lane_kobj = container_of(kobj, struct sl_lgrp_serdes_lane_kobj, kobj);
+	if (!lane_kobj->ctrl_lgrp)
+		return sysfs_emit(buf, "no-lane\n");
+
+	core_link = sl_core_link_get(lane_kobj->ctrl_lgrp->ctrl_ldev->num, lane_kobj->ctrl_lgrp->num,
+				     lane_num_to_link_num(lane_kobj->ctrl_lgrp, lane_kobj->asic_lane_num));
+	if (!core_link)
+		return sysfs_emit(buf, "no-link\n");
+
+	core_lgrp = sl_core_lgrp_get(lane_kobj->ctrl_lgrp->ctrl_ldev->num, lane_kobj->ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_pre2_get(core_lgrp, lane_kobj->asic_lane_num, &pre2);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "settings pre2 show (pre2 = %d)", pre2);
+
+	return sysfs_emit(buf, "%d\n", pre2);
+}
+
+static ssize_t pre3_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_lgrp_serdes_lane_kobj *lane_kobj;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+	s16                              pre3;
+	int				 rtn;
+
+	lane_kobj = container_of(kobj, struct sl_lgrp_serdes_lane_kobj, kobj);
+	if (!lane_kobj->ctrl_lgrp)
+		return sysfs_emit(buf, "no-lane\n");
+
+	core_link = sl_core_link_get(lane_kobj->ctrl_lgrp->ctrl_ldev->num, lane_kobj->ctrl_lgrp->num,
+				     lane_num_to_link_num(lane_kobj->ctrl_lgrp, lane_kobj->asic_lane_num));
+	if (!core_link)
+		return sysfs_emit(buf, "no-link\n");
+
+	core_lgrp = sl_core_lgrp_get(lane_kobj->ctrl_lgrp->ctrl_ldev->num, lane_kobj->ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_pre3_get(core_lgrp, lane_kobj->asic_lane_num, &pre3);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "settings pre3 show (pre3 = %d)", pre3);
+
+	return sysfs_emit(buf, "%d\n", pre3);
+}
+
+static ssize_t cursor_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_lgrp_serdes_lane_kobj *lane_kobj;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+	s16                              cursor;
+	int				 rtn;
+
+	lane_kobj = container_of(kobj, struct sl_lgrp_serdes_lane_kobj, kobj);
+	if (!lane_kobj->ctrl_lgrp)
+		return sysfs_emit(buf, "no-lane\n");
+
+	core_link = sl_core_link_get(lane_kobj->ctrl_lgrp->ctrl_ldev->num, lane_kobj->ctrl_lgrp->num,
+				     lane_num_to_link_num(lane_kobj->ctrl_lgrp, lane_kobj->asic_lane_num));
+	if (!core_link)
+		return sysfs_emit(buf, "no-link\n");
+
+	core_lgrp = sl_core_lgrp_get(lane_kobj->ctrl_lgrp->ctrl_ldev->num, lane_kobj->ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_cursor_get(core_lgrp, lane_kobj->asic_lane_num, &cursor);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "settings cursor show (cursor = %d)", cursor);
+
+	return sysfs_emit(buf, "%d\n", cursor);
+}
+
+static ssize_t post1_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_lgrp_serdes_lane_kobj *lane_kobj;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+	s16                              post1;
+	int				 rtn;
+
+	lane_kobj = container_of(kobj, struct sl_lgrp_serdes_lane_kobj, kobj);
+	if (!lane_kobj->ctrl_lgrp)
+		return sysfs_emit(buf, "no-lane\n");
+
+	core_link = sl_core_link_get(lane_kobj->ctrl_lgrp->ctrl_ldev->num, lane_kobj->ctrl_lgrp->num,
+				     lane_num_to_link_num(lane_kobj->ctrl_lgrp, lane_kobj->asic_lane_num));
+	if (!core_link)
+		return sysfs_emit(buf, "no-link\n");
+
+	core_lgrp = sl_core_lgrp_get(lane_kobj->ctrl_lgrp->ctrl_ldev->num, lane_kobj->ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_post1_get(core_lgrp, lane_kobj->asic_lane_num, &post1);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "settings post1 show (post1 = %d)", post1);
+
+	return sysfs_emit(buf, "%d\n", post1);
+}
+
+static ssize_t post2_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_lgrp_serdes_lane_kobj *lane_kobj;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+	s16                              post2;
+	int				 rtn;
+
+	lane_kobj = container_of(kobj, struct sl_lgrp_serdes_lane_kobj, kobj);
+	if (!lane_kobj->ctrl_lgrp)
+		return sysfs_emit(buf, "no-lane\n");
+
+	core_link = sl_core_link_get(lane_kobj->ctrl_lgrp->ctrl_ldev->num, lane_kobj->ctrl_lgrp->num,
+				     lane_num_to_link_num(lane_kobj->ctrl_lgrp, lane_kobj->asic_lane_num));
+	if (!core_link)
+		return sysfs_emit(buf, "no-link\n");
+
+	core_lgrp = sl_core_lgrp_get(lane_kobj->ctrl_lgrp->ctrl_ldev->num, lane_kobj->ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_post2_get(core_lgrp, lane_kobj->asic_lane_num, &post2);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "settings post2 show (post2 = %d)", post2);
+
+	return sysfs_emit(buf, "%d\n", post2);
+}
+
+static ssize_t media_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_lgrp_serdes_lane_kobj *lane_kobj;
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+
+	lane_kobj = container_of(kobj, struct sl_lgrp_serdes_lane_kobj, kobj);
+	if (!lane_kobj->ctrl_lgrp)
+		return sysfs_emit(buf, "no-lane\n");
+
+	core_link = sl_core_link_get(lane_kobj->ctrl_lgrp->ctrl_ldev->num, lane_kobj->ctrl_lgrp->num,
+				     lane_num_to_link_num(lane_kobj->ctrl_lgrp, lane_kobj->asic_lane_num));
+	if (!core_link)
+		return sysfs_emit(buf, "no-link\n");
+
+	sl_log_dbg(core_link, LOG_BLOCK, LOG_NAME,
+		   "settings media show (media = %d)", core_link->serdes.media_serdes_settings.media);
+	return sysfs_emit(buf, "%d\n", core_link->serdes.media_serdes_settings.media);
+}
+
+static struct kobj_attribute settings_pre1   = __ATTR_RO(pre1);
+static struct kobj_attribute settings_pre2   = __ATTR_RO(pre2);
+static struct kobj_attribute settings_pre3   = __ATTR_RO(pre3);
+static struct kobj_attribute settings_cursor = __ATTR_RO(cursor);
+static struct kobj_attribute settings_post1  = __ATTR_RO(post1);
+static struct kobj_attribute settings_post2  = __ATTR_RO(post2);
+static struct kobj_attribute settings_media  = __ATTR_RO(media);
+
+static ssize_t osr_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_lgrp_serdes_lane_kobj *lane_kobj;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+	u8                               osr;
+	int				 rtn;
+
+	lane_kobj = container_of(kobj, struct sl_lgrp_serdes_lane_kobj, kobj);
+	if (!lane_kobj->ctrl_lgrp)
+		return sysfs_emit(buf, "no-lane\n");
+
+	core_link = sl_core_link_get(lane_kobj->ctrl_lgrp->ctrl_ldev->num, lane_kobj->ctrl_lgrp->num,
+				     lane_num_to_link_num(lane_kobj->ctrl_lgrp, lane_kobj->asic_lane_num));
+	if (!core_link)
+		return sysfs_emit(buf, "no-link\n");
+
+	core_lgrp = sl_core_lgrp_get(lane_kobj->ctrl_lgrp->ctrl_ldev->num, lane_kobj->ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_osr_get(core_lgrp, lane_kobj->asic_lane_num, &osr);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME,
+		   "settings osr show (osr = %u %s)", osr, sl_core_serdes_lane_osr_str(osr));
+
+	return sysfs_emit(buf, "%s\n", sl_core_serdes_lane_osr_str(osr));
+}
+
+static ssize_t encoding_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_lgrp_serdes_lane_kobj *lane_kobj;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+	u8                               encoding;
+	int				 rtn;
+
+	lane_kobj = container_of(kobj, struct sl_lgrp_serdes_lane_kobj, kobj);
+	if (!lane_kobj->ctrl_lgrp)
+		return sysfs_emit(buf, "no-lane\n");
+
+	core_link = sl_core_link_get(lane_kobj->ctrl_lgrp->ctrl_ldev->num, lane_kobj->ctrl_lgrp->num,
+				     lane_num_to_link_num(lane_kobj->ctrl_lgrp, lane_kobj->asic_lane_num));
+	if (!core_link)
+		return sysfs_emit(buf, "no-link\n");
+
+	core_lgrp = sl_core_lgrp_get(lane_kobj->ctrl_lgrp->ctrl_ldev->num, lane_kobj->ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_encoding_get(core_lgrp, lane_kobj->asic_lane_num, &encoding);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME,
+		   "settings encoding show (encoding = %u %s)",
+		   encoding, sl_core_serdes_lane_encoding_str(encoding));
+
+	return sysfs_emit(buf, "%s\n", sl_core_serdes_lane_encoding_str(encoding));
+}
+
+static ssize_t clocking_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_lgrp_serdes_lane_kobj *lane_kobj;
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+	u16                              clocking;
+	int				 rtn;
+
+	lane_kobj = container_of(kobj, struct sl_lgrp_serdes_lane_kobj, kobj);
+	if (!lane_kobj->ctrl_lgrp)
+		return sysfs_emit(buf, "no-lane\n");
+
+	core_link = sl_core_link_get(lane_kobj->ctrl_lgrp->ctrl_ldev->num, lane_kobj->ctrl_lgrp->num,
+				     lane_num_to_link_num(lane_kobj->ctrl_lgrp, lane_kobj->asic_lane_num));
+	if (!core_link)
+		return sysfs_emit(buf, "no-link\n");
+
+	rtn = sl_core_link_clocking_get(core_link, &clocking);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_link, LOG_BLOCK, LOG_NAME,
+		   "settings clocking show (clocking = %u %s)",
+		   clocking, sl_core_serdes_lane_clocking_str(clocking));
+
+	return sysfs_emit(buf, "%s\n", sl_core_serdes_lane_clocking_str(clocking));
+}
+
+static ssize_t width_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_lgrp_serdes_lane_kobj *lane_kobj;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+	u8                               width;
+	int				 rtn;
+
+	lane_kobj = container_of(kobj, struct sl_lgrp_serdes_lane_kobj, kobj);
+	if (!lane_kobj->ctrl_lgrp)
+		return sysfs_emit(buf, "no-lane\n");
+
+	core_link = sl_core_link_get(lane_kobj->ctrl_lgrp->ctrl_ldev->num, lane_kobj->ctrl_lgrp->num,
+				     lane_num_to_link_num(lane_kobj->ctrl_lgrp, lane_kobj->asic_lane_num));
+	if (!core_link)
+		return sysfs_emit(buf, "no-link\n");
+
+	core_lgrp = sl_core_lgrp_get(lane_kobj->ctrl_lgrp->ctrl_ldev->num, lane_kobj->ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_width_get(core_lgrp, lane_kobj->asic_lane_num, &width);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME,
+		   "settings width show (width = %u %s)",
+		   width, sl_core_serdes_lane_width_str(width));
+
+	return sysfs_emit(buf, "%s\n", sl_core_serdes_lane_width_str(width));
+}
+
+static ssize_t dfe_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_lgrp_serdes_lane_kobj *lane_kobj;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+	u8                               dfe;
+	int				 rtn;
+
+	lane_kobj = container_of(kobj, struct sl_lgrp_serdes_lane_kobj, kobj);
+	if (!lane_kobj->ctrl_lgrp)
+		return sysfs_emit(buf, "no-lane\n");
+
+	core_link = sl_core_link_get(lane_kobj->ctrl_lgrp->ctrl_ldev->num, lane_kobj->ctrl_lgrp->num,
+				     lane_num_to_link_num(lane_kobj->ctrl_lgrp, lane_kobj->asic_lane_num));
+	if (!core_link)
+		return sysfs_emit(buf, "no-link\n");
+
+	core_lgrp = sl_core_lgrp_get(lane_kobj->ctrl_lgrp->ctrl_ldev->num, lane_kobj->ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_dfe_get(core_lgrp, lane_kobj->asic_lane_num, &dfe);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME,
+		   "settings dfe show (dfe = %s)", (dfe) ? "enabled" : "disabled");
+
+	return sysfs_emit(buf, "%s\n", (dfe) ? "enabled" : "disabled");
+}
+
+static ssize_t scramble_dis_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_lgrp_serdes_lane_kobj *lane_kobj;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+	u8                               scramble_dis;
+	int				 rtn;
+
+	lane_kobj = container_of(kobj, struct sl_lgrp_serdes_lane_kobj, kobj);
+	if (!lane_kobj->ctrl_lgrp)
+		return sysfs_emit(buf, "no-lane\n");
+
+	core_link = sl_core_link_get(lane_kobj->ctrl_lgrp->ctrl_ldev->num, lane_kobj->ctrl_lgrp->num,
+				     lane_num_to_link_num(lane_kobj->ctrl_lgrp, lane_kobj->asic_lane_num));
+	if (!core_link)
+		return sysfs_emit(buf, "no-link\n");
+
+	core_lgrp = sl_core_lgrp_get(lane_kobj->ctrl_lgrp->ctrl_ldev->num, lane_kobj->ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rtn = sl_core_lgrp_scramble_dis_get(core_lgrp, lane_kobj->asic_lane_num, &scramble_dis);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME,
+		   "settings scramble_dis show (scramble_dis = %s)", (scramble_dis) ? "set" : "not-set");
+
+	return sysfs_emit(buf, "%s\n", (scramble_dis) ? "set" : "not-set");
+}
+
+static struct kobj_attribute settings_osr          = __ATTR_RO(osr);
+static struct kobj_attribute settings_encoding     = __ATTR_RO(encoding);
+static struct kobj_attribute settings_clocking     = __ATTR_RO(clocking);
+static struct kobj_attribute settings_width        = __ATTR_RO(width);
+static struct kobj_attribute settings_dfe          = __ATTR_RO(dfe);
+static struct kobj_attribute settings_scramble_dis = __ATTR_RO(scramble_dis);
+
+static ssize_t link_training_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_lgrp_serdes_lane_kobj *lane_kobj;
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+
+	lane_kobj = container_of(kobj, struct sl_lgrp_serdes_lane_kobj, kobj);
+	if (!lane_kobj->ctrl_lgrp)
+		return sysfs_emit(buf, "no-lane\n");
+
+	core_link = sl_core_link_get(lane_kobj->ctrl_lgrp->ctrl_ldev->num, lane_kobj->ctrl_lgrp->num,
+				     lane_num_to_link_num(lane_kobj->ctrl_lgrp, lane_kobj->asic_lane_num));
+	if (!core_link)
+		return sysfs_emit(buf, "no-link\n");
+
+	if (is_flag_set(core_link->core_lgrp->link_caps[core_link->num].hpe_map, SL_LINK_CONFIG_HPE_LINKTRAIN))
+		return sysfs_emit(buf, "enabled\n");
+	else
+		return sysfs_emit(buf, "disabled\n");
+}
+
+static struct kobj_attribute settings_link_training = __ATTR_RO(link_training);
+
+static struct attribute *serdes_lane_settings_attrs[] = {
+	/* media */
+	&settings_pre1.attr,
+	&settings_pre2.attr,
+	&settings_pre3.attr,
+	&settings_cursor.attr,
+	&settings_post1.attr,
+	&settings_post2.attr,
+	&settings_media.attr,
+	/* core */
+	&settings_osr.attr,
+	&settings_encoding.attr,
+	&settings_clocking.attr,
+	&settings_width.attr,
+	&settings_dfe.attr,
+	&settings_scramble_dis.attr,
+	&settings_link_training.attr,
+	NULL
+};
+ATTRIBUTE_GROUPS(serdes_lane_settings);
+
+static struct kobj_type serdes_lane_settings_info = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = serdes_lane_settings_groups,
+};
+#endif /* CONFIG_SYSFS */
+
+int sl_sysfs_serdes_lane_settings_create(struct sl_ctrl_lgrp *ctrl_lgrp, u8 asic_lane_num)
+{
+#ifdef CONFIG_SYSFS
+	int rtn;
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "serdes lane settings create (lgrp = 0x%p)", ctrl_lgrp);
+
+	rtn = kobject_init_and_add(&(ctrl_lgrp->serdes_lane_settings_kobjs[asic_lane_num].kobj),
+				   &serdes_lane_settings_info, &(ctrl_lgrp->serdes_lane_kobjs[asic_lane_num]), "settings");
+	if (rtn) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+			   "serdes lane settings create kobject_init_and_add failed [%d]", rtn);
+		kobject_put(&(ctrl_lgrp->serdes_lane_settings_kobjs[asic_lane_num].kobj));
+		return -ENOMEM;
+	}
+	ctrl_lgrp->serdes_lane_settings_kobjs[asic_lane_num].ctrl_lgrp      = ctrl_lgrp;
+	ctrl_lgrp->serdes_lane_settings_kobjs[asic_lane_num].asic_lane_num = asic_lane_num;
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "serdes lane settings create (serdes_kobj = 0x%p)", &(ctrl_lgrp->serdes_kobj));
+
+	return 0;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_serdes_lane_settings_delete(struct sl_ctrl_lgrp *ctrl_lgrp, u8 asic_lane_num)
+{
+#ifdef CONFIG_SYSFS
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "serdes lane settings delete (lgrp = 0x%p)", ctrl_lgrp);
+
+	kobject_put(&(ctrl_lgrp->serdes_lane_settings_kobjs[asic_lane_num].kobj));
+	ctrl_lgrp->serdes_lane_settings_kobjs[asic_lane_num].ctrl_lgrp = NULL;
+#endif /* CONFIG_SYSFS */
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_serdes_state.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_serdes_state.c
new file mode 100644
index 000000000000..7fc14970a588
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_serdes_state.c
@@ -0,0 +1,121 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2024-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kobject.h>
+#include <linux/sysfs.h>
+
+#include "sl_log.h"
+#include "sl_ctrl_lgrp.h"
+#include "sl_ctrl_ldev.h"
+#include "sl_core_lgrp.h"
+#include "sl_core_str.h"
+#include "sl_sysfs_serdes_state.h"
+#include "hw/sl_core_hw_serdes_lane.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+#ifdef CONFIG_SYSFS
+static ssize_t tx_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_lgrp_serdes_lane_kobj *lane_kobj;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	u32                              state;
+	int				 rtn;
+
+	lane_kobj = container_of(kobj, struct sl_lgrp_serdes_lane_kobj, kobj);
+	if (!lane_kobj->ctrl_lgrp)
+		return sysfs_emit(buf, "no-lane\n");
+
+	core_lgrp = sl_core_lgrp_get(lane_kobj->ctrl_lgrp->ctrl_ldev->num, lane_kobj->ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+	rtn	  = sl_core_hw_serdes_tx_lane_state_get(core_lgrp, lane_kobj->asic_lane_num, &state);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME,
+		   "state tx show (asic_lane_num = %u, state = %u %s)",
+		lane_kobj->asic_lane_num, state, sl_core_serdes_lane_state_str(state));
+
+	return sysfs_emit(buf, "%s\n", sl_core_serdes_lane_state_str(state));
+}
+
+static ssize_t rx_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_lgrp_serdes_lane_kobj *lane_kobj;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	u32                              state;
+	int				 rtn;
+
+	lane_kobj = container_of(kobj, struct sl_lgrp_serdes_lane_kobj, kobj);
+	if (!lane_kobj->ctrl_lgrp)
+		return sysfs_emit(buf, "no-lane\n");
+
+	core_lgrp = sl_core_lgrp_get(lane_kobj->ctrl_lgrp->ctrl_ldev->num, lane_kobj->ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+	rtn	  = sl_core_hw_serdes_rx_lane_state_get(core_lgrp, lane_kobj->asic_lane_num, &state);
+	if (rtn)
+		return sysfs_emit(buf, "error\n");
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME,
+		   "state rx show (asic_lane_num = %u, state = %u %s)",
+		lane_kobj->asic_lane_num, state, sl_core_serdes_lane_state_str(state));
+
+	return sysfs_emit(buf, "%s\n", sl_core_serdes_lane_state_str(state));
+}
+
+static struct kobj_attribute state_tx = __ATTR_RO(tx);
+static struct kobj_attribute state_rx = __ATTR_RO(rx);
+
+static struct attribute *serdes_lane_state_attrs[] = {
+	&state_tx.attr,
+	&state_rx.attr,
+	NULL,
+};
+ATTRIBUTE_GROUPS(serdes_lane_state);
+
+static struct kobj_type serdes_lane_state_info = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = serdes_lane_state_groups,
+};
+#endif /* CONFIG_SYSFS */
+
+int sl_sysfs_serdes_lane_state_create(struct sl_ctrl_lgrp *ctrl_lgrp, u8 asic_lane_num)
+{
+#ifdef CONFIG_SYSFS
+	int rtn;
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "serdes lane state create (lgrp = 0x%p)", ctrl_lgrp);
+
+	rtn = kobject_init_and_add(&(ctrl_lgrp->serdes_lane_state_kobjs[asic_lane_num].kobj),
+				   &serdes_lane_state_info, &(ctrl_lgrp->serdes_lane_kobjs[asic_lane_num]), "state");
+	if (rtn) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+			   "serdes lane state create kobject_init_and_add failed [%d]", rtn);
+		kobject_put(&(ctrl_lgrp->serdes_lane_state_kobjs[asic_lane_num].kobj));
+		return -ENOMEM;
+	}
+	ctrl_lgrp->serdes_lane_state_kobjs[asic_lane_num].ctrl_lgrp      = ctrl_lgrp;
+	ctrl_lgrp->serdes_lane_state_kobjs[asic_lane_num].asic_lane_num = asic_lane_num;
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "serdes lane state create (serdes_kobj = 0x%p)", &(ctrl_lgrp->serdes_kobj));
+	return 0;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_serdes_lane_state_delete(struct sl_ctrl_lgrp *ctrl_lgrp, u8 asic_lane_num)
+{
+#ifdef CONFIG_SYSFS
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "serdes lane state delete (lgrp = 0x%p)", ctrl_lgrp);
+
+	kobject_put(&(ctrl_lgrp->serdes_lane_state_kobjs[asic_lane_num].kobj));
+	ctrl_lgrp->serdes_lane_state_kobjs[asic_lane_num].ctrl_lgrp = NULL;
+#endif /* CONFIG_SYSFS */
+}
diff --git a/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_serdes_swizzle.c b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_serdes_swizzle.c
new file mode 100644
index 000000000000..5f2d17fc15e9
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/sysfs/sl_sysfs_serdes_swizzle.c
@@ -0,0 +1,126 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2025-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/sysfs.h>
+#include <linux/kobject.h>
+
+#include "sl_log.h"
+#include "sl_sysfs.h"
+#include "sl_ctrl_lgrp.h"
+#include "sl_ctrl_ldev.h"
+#include "sl_core_lgrp.h"
+#include "sl_core_str.h"
+#include "sl_sysfs_serdes_swizzle.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_SYSFS_LOG_NAME
+
+#ifdef CONFIG_SYSFS
+static ssize_t tx_source_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_lgrp_serdes_lane_kobj *lane_kobj;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+	u8                               tx_source;
+
+	lane_kobj = container_of(kobj, struct sl_lgrp_serdes_lane_kobj, kobj);
+	if (!lane_kobj->ctrl_lgrp)
+		return sysfs_emit(buf, "no-lane\n");
+
+	core_link = sl_core_link_get(lane_kobj->ctrl_lgrp->ctrl_ldev->num, lane_kobj->ctrl_lgrp->num,
+				     lane_num_to_link_num(lane_kobj->ctrl_lgrp, lane_kobj->asic_lane_num));
+	if (!core_link)
+		return sysfs_emit(buf, "no-link\n");
+
+	core_lgrp = sl_core_lgrp_get(lane_kobj->ctrl_lgrp->ctrl_ldev->num, lane_kobj->ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	tx_source = core_lgrp->serdes.dt.lane_info[lane_kobj->asic_lane_num].tx_source;
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "tx_source show (tx_source = %u)", tx_source);
+
+	return sysfs_emit(buf, "%u\n", tx_source);
+}
+
+static ssize_t rx_source_show(struct kobject *kobj, struct kobj_attribute *kattr, char *buf)
+{
+	struct sl_lgrp_serdes_lane_kobj *lane_kobj;
+	struct sl_core_lgrp *core_lgrp __free(sl_core_lgrp_put) = NULL;
+	struct sl_core_link *core_link __free(sl_core_link_put) = NULL;
+	u8                               rx_source;
+
+	lane_kobj = container_of(kobj, struct sl_lgrp_serdes_lane_kobj, kobj);
+	if (!lane_kobj->ctrl_lgrp)
+		return sysfs_emit(buf, "no-lane\n");
+
+	core_link = sl_core_link_get(lane_kobj->ctrl_lgrp->ctrl_ldev->num, lane_kobj->ctrl_lgrp->num,
+				     lane_num_to_link_num(lane_kobj->ctrl_lgrp, lane_kobj->asic_lane_num));
+	if (!core_link)
+		return sysfs_emit(buf, "no-link\n");
+
+	core_lgrp = sl_core_lgrp_get(lane_kobj->ctrl_lgrp->ctrl_ldev->num, lane_kobj->ctrl_lgrp->num);
+	if (!core_lgrp)
+		return -ENODEV;
+
+	rx_source = core_lgrp->serdes.dt.lane_info[lane_kobj->asic_lane_num].rx_source;
+
+	sl_log_dbg(core_lgrp, LOG_BLOCK, LOG_NAME, "rx_source show (rx_source = %u)", rx_source);
+
+	return sysfs_emit(buf, "%u\n", rx_source);
+}
+
+static struct kobj_attribute tx_source = __ATTR_RO(tx_source);
+static struct kobj_attribute rx_source = __ATTR_RO(rx_source);
+
+static struct attribute *serdes_lane_swizzle_attrs[] = {
+	&tx_source.attr,
+	&rx_source.attr,
+	NULL,
+};
+ATTRIBUTE_GROUPS(serdes_lane_swizzle);
+
+static struct kobj_type serdes_lane_swizzle_info = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = serdes_lane_swizzle_groups,
+};
+#endif /* CONFIG_SYSFS */
+
+int sl_sysfs_serdes_lane_swizzle_create(struct sl_ctrl_lgrp *ctrl_lgrp, u8 asic_lane_num)
+{
+#ifdef CONFIG_SYSFS
+	int rtn;
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "serdes lane swizzle create (lgrp = 0x%p)", ctrl_lgrp);
+
+	rtn = kobject_init_and_add(&(ctrl_lgrp->serdes_lane_swizzle_kobjs[asic_lane_num].kobj),
+				   &serdes_lane_swizzle_info, &(ctrl_lgrp->serdes_lane_kobjs[asic_lane_num]), "swizzle");
+	if (rtn) {
+		sl_log_err(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+			   "serdes lane swizzle create kobject_init_and_add failed [%d]", rtn);
+		kobject_put(&(ctrl_lgrp->serdes_lane_swizzle_kobjs[asic_lane_num].kobj));
+		return -ENOMEM;
+	}
+	ctrl_lgrp->serdes_lane_swizzle_kobjs[asic_lane_num].ctrl_lgrp      = ctrl_lgrp;
+	ctrl_lgrp->serdes_lane_swizzle_kobjs[asic_lane_num].asic_lane_num = asic_lane_num;
+
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "serdes lane swizzle create (serdes_kobj = 0x%p)", &(ctrl_lgrp->serdes_kobj));
+	return 0;
+#else /* CONFIG_SYSFS */
+	return 0;
+#endif /* CONFIG_SYSFS */
+}
+
+void sl_sysfs_serdes_lane_swizzle_delete(struct sl_ctrl_lgrp *ctrl_lgrp, u8 asic_lane_num)
+{
+#ifdef CONFIG_SYSFS
+	sl_log_dbg(ctrl_lgrp, LOG_BLOCK, LOG_NAME,
+		   "serdes lane swizzle delete (lgrp = 0x%p)", ctrl_lgrp);
+
+	kobject_put(&(ctrl_lgrp->serdes_lane_swizzle_kobjs[asic_lane_num].kobj));
+	ctrl_lgrp->serdes_lane_swizzle_kobjs[asic_lane_num].ctrl_lgrp = NULL;
+#endif /* CONFIG_SYSFS */
+}

-- 
2.56.0


^ permalink raw reply	[flat|nested] 25+ messages in thread
* [PATCH 15/23] net: hpe: sl: add the NIC binding and logging helpers
  2026-10-30 20:58 [PATCH 00/23] Subject: [PATCH net-next 00/23] net/hpe: add HPE Slingshot NIC drivers Doug Ledford
                   ` (13 preceding siblings ...)
  2026-10-30 20:59 ` [PATCH 14/23] net: hpe: sl: add the sysfs interface Doug Ledford
@ 2026-10-30 20:59 ` Doug Ledford
  2026-10-30 20:59 ` [PATCH 16/23] net: hpe: ss1: add the Cassini core device layer Doug Ledford
                   ` (8 subsequent siblings)
  23 siblings, 0 replies; 25+ messages in thread
From: Doug Ledford @ 2026-10-30 20:59 UTC (permalink / raw)
  To: Slingshot Open Source Team, Nathan Chancellor, Nicolas Schier,
	Richard Cochran, Andrew Lunn, David S. Miller, Eric Dumazet,
	Jakub Kicinski, Paolo Abeni, Sumit Semwal, Christian König,
	Guenter Roeck
  Cc: linux-kernel, netdev, linux-kbuild, Doug Ledford, Sandeep Bhoot

Add the glue that binds SL to a NIC: ASIC and CSR definitions, the NIC
logical device and media hooks, and the logging helpers.

sl_asic_csrs.h is generated from the hardware register description and
is kept in that form; its integer types were converted to the kernel
types in the same pass as the other UAPI/header cleanups.

checkpatch --strict (100 columns) still reports the following in this
patch. They need coordination with the internal repositories this code
is maintained in and will be fixed in V2:
- WARNING: LONG_LINE (18)
- CHECK: UNNECESSARY_PARENTHESES (16), COMPARISON_TO_NULL (3)

Co-developed-by: Sandeep Bhoot <sandeep.bhoot@hpe.com>
Signed-off-by: Sandeep Bhoot <sandeep.bhoot@hpe.com>
Signed-off-by: Doug Ledford <doug.ledford@hpe.com>
---
 drivers/net/ethernet/hpe/sl/log/sl_log.c   | 566 +++++++++++++++++++++++++++++
 drivers/net/ethernet/hpe/sl/nic/sl_ldev.c  | 147 ++++++++
 drivers/net/ethernet/hpe/sl/nic/sl_media.c |  53 +++
 3 files changed, 766 insertions(+)

diff --git a/drivers/net/ethernet/hpe/sl/log/sl_log.c b/drivers/net/ethernet/hpe/sl/log/sl_log.c
new file mode 100644
index 000000000000..64382f9b46bb
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/log/sl_log.c
@@ -0,0 +1,566 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2022-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/module.h>
+#include <linux/sched.h>
+
+#include "sl_asic.h"
+
+#include "sl_log.h"
+
+#include "sl_ldev.h"
+#include "sl_lgrp.h"
+#include "sl_link.h"
+#include "sl_llr.h"
+#include "sl_mac.h"
+
+#include "sl_ctrl_ldev.h"
+#include "sl_ctrl_lgrp.h"
+#include "sl_ctrl_link.h"
+#include "sl_ctrl_llr.h"
+#include "sl_ctrl_mac.h"
+
+#include "sl_core_ldev.h"
+#include "sl_core_lgrp.h"
+#include "sl_core_link.h"
+#include "sl_core_mac.h"
+#include "sl_core_llr.h"
+
+#include "sl_media_ldev.h"
+#include "sl_media_lgrp.h"
+#include "sl_media_jack.h"
+
+#include "data/sl_ctrl_data_lgrp_trace.h"
+
+#include "hw/sl_core_hw_intr.h"
+#include "data/sl_core_data_link.h"
+#include "data/sl_core_data_lgrp.h"
+#include "data/sl_core_data_lgrp_trace.h"
+#include "data/sl_core_data_ldev.h"
+
+#include "data/sl_media_data_lgrp_trace.h"
+
+#define SL_LOG_MSG_LEN              150
+#define SL_LOG_NULL_ID_FMT          "%c[-:--:-] ???         "
+#define SL_LOG_DFLT_ID_FMT          "%c[-:--:-] 0x%08X  "
+#define SL_LOG_LDEV_ID_FMT          "%c[%1u:--:-] ldev%1u       "
+#define SL_LOG_LGRP_ID_FMT          "%c[%1u:%02u:-] %-12s"
+#define SL_LOG_LINK_ID_FMT          "%c[%1u:%02u:%1u] %-12s"
+#define SL_LOG_JACK_ID_FMT          "%c[-:--:-] jack%03u     "
+#define SL_LOG_CONTEXT              (in_interrupt() ? '^' : ' ')
+
+static int remaining_chars(int idx)
+{
+	return max(SL_LOG_MSG_LEN - idx, 0);
+}
+
+static void sl_log_msg_create(const char *level, void *ptr, char *msg,
+			      const char *block, const char *name, const char *text)
+{
+	struct sl_ldev            *ldev;
+	struct sl_lgrp            *lgrp;
+	struct sl_link            *link;
+	struct sl_llr             *llr;
+	struct sl_mac             *mac;
+	struct sl_ctrl_ldev       *ctrl_ldev;
+	struct sl_ctrl_lgrp       *ctrl_lgrp;
+	struct sl_ctrl_link       *ctrl_link;
+	struct sl_ctrl_llr        *ctrl_llr;
+	struct sl_ctrl_mac        *ctrl_mac;
+	struct sl_core_ldev       *core_ldev;
+	struct sl_core_lgrp       *core_lgrp;
+	struct sl_core_link       *core_link;
+	struct sl_core_mac        *core_mac;
+	struct sl_core_llr        *core_llr;
+	struct sl_media_ldev      *media_ldev;
+	struct sl_media_lgrp      *media_lgrp;
+	struct sl_media_jack      *media_jack;
+	int                        idx;
+	unsigned long              irq_flags;
+
+	idx = snprintf(msg, SL_LOG_MSG_LEN, "%s%s", level, module_name(THIS_MODULE));
+	if (ptr != NULL) {
+		switch (*((u32 *)ptr)) {
+		case SL_LDEV_MAGIC:
+			ldev = ptr;
+			idx += snprintf(msg + idx, remaining_chars(idx), SL_LOG_LDEV_ID_FMT,
+				SL_LOG_CONTEXT,
+				ldev->num, ldev->num);
+			break;
+		case SL_LGRP_MAGIC:
+			lgrp = ptr;
+			idx += snprintf(msg + idx, remaining_chars(idx), SL_LOG_LGRP_ID_FMT,
+				SL_LOG_CONTEXT,
+				lgrp->ldev_num, lgrp->num, "lgrp");
+			break;
+		case SL_LINK_MAGIC:
+			link = ptr;
+			idx += snprintf(msg + idx, remaining_chars(idx), SL_LOG_LINK_ID_FMT,
+				SL_LOG_CONTEXT,
+				link->ldev_num, link->lgrp_num, link->num, "link");
+			break;
+		case SL_LLR_MAGIC:
+			llr = ptr;
+			idx += snprintf(msg + idx, remaining_chars(idx), SL_LOG_LINK_ID_FMT,
+				SL_LOG_CONTEXT,
+				llr->ldev_num, llr->lgrp_num, llr->num, "llr");
+			break;
+		case SL_MAC_MAGIC:
+			mac = ptr;
+			idx += snprintf(msg + idx, remaining_chars(idx), SL_LOG_LINK_ID_FMT,
+				SL_LOG_CONTEXT,
+				mac->ldev_num, mac->lgrp_num, mac->num, "mac");
+			break;
+		case SL_CTRL_LDEV_MAGIC:
+			ctrl_ldev = ptr;
+			idx += snprintf(msg + idx, remaining_chars(idx), SL_LOG_LDEV_ID_FMT,
+				SL_LOG_CONTEXT,
+				ctrl_ldev->num, ctrl_ldev->num);
+			break;
+		case SL_CTRL_LGRP_MAGIC:
+			ctrl_lgrp = ptr;
+			spin_lock_irqsave(&(ctrl_lgrp->log_lock), irq_flags);
+			idx += snprintf(msg + idx, remaining_chars(idx), SL_LOG_LGRP_ID_FMT,
+				SL_LOG_CONTEXT,
+				ctrl_lgrp->ctrl_ldev->num, ctrl_lgrp->num,
+				ctrl_lgrp->log_connect_id);
+			spin_unlock_irqrestore(&(ctrl_lgrp->log_lock), irq_flags);
+			break;
+		case SL_CTRL_LINK_MAGIC:
+			ctrl_link = ptr;
+			spin_lock_irqsave(&(ctrl_link->ctrl_lgrp->log_lock), irq_flags);
+			idx += snprintf(msg + idx, remaining_chars(idx), SL_LOG_LINK_ID_FMT,
+				SL_LOG_CONTEXT,
+				ctrl_link->ctrl_lgrp->ctrl_ldev->num, ctrl_link->ctrl_lgrp->num, ctrl_link->num,
+				ctrl_link->ctrl_lgrp->log_connect_id);
+			spin_unlock_irqrestore(&(ctrl_link->ctrl_lgrp->log_lock), irq_flags);
+			break;
+		case SL_CTRL_LLR_MAGIC:
+			ctrl_llr = ptr;
+			spin_lock_irqsave(&(ctrl_llr->ctrl_lgrp->log_lock), irq_flags);
+			idx += snprintf(msg + idx, remaining_chars(idx), SL_LOG_LINK_ID_FMT,
+				SL_LOG_CONTEXT,
+				ctrl_llr->ctrl_lgrp->ctrl_ldev->num, ctrl_llr->ctrl_lgrp->num, ctrl_llr->num,
+				ctrl_llr->ctrl_lgrp->log_connect_id);
+			spin_unlock_irqrestore(&(ctrl_llr->ctrl_lgrp->log_lock), irq_flags);
+			break;
+		case SL_CTRL_MAC_MAGIC:
+			ctrl_mac = ptr;
+			spin_lock_irqsave(&(ctrl_mac->ctrl_lgrp->log_lock), irq_flags);
+			idx += snprintf(msg + idx, remaining_chars(idx), SL_LOG_LINK_ID_FMT,
+				SL_LOG_CONTEXT,
+				ctrl_mac->ctrl_lgrp->ctrl_ldev->num, ctrl_mac->ctrl_lgrp->num, ctrl_mac->num,
+				ctrl_mac->ctrl_lgrp->log_connect_id);
+			spin_unlock_irqrestore(&(ctrl_mac->ctrl_lgrp->log_lock), irq_flags);
+			break;
+		case SL_CORE_LDEV_MAGIC:
+			core_ldev = ptr;
+			idx += snprintf(msg + idx, remaining_chars(idx), SL_LOG_LDEV_ID_FMT,
+				SL_LOG_CONTEXT,
+				core_ldev->num, core_ldev->num);
+			break;
+		case SL_CORE_LGRP_MAGIC:
+			core_lgrp = ptr;
+			spin_lock_irqsave(&(core_lgrp->log_lock), irq_flags);
+			idx += snprintf(msg + idx, remaining_chars(idx), SL_LOG_LGRP_ID_FMT,
+				SL_LOG_CONTEXT,
+				core_lgrp->core_ldev->num, core_lgrp->num,
+				core_lgrp->log_connect_id);
+			spin_unlock_irqrestore(&(core_lgrp->log_lock), irq_flags);
+			break;
+		case SL_CORE_LINK_MAGIC:
+			core_link = ptr;
+			spin_lock_irqsave(&(core_link->core_lgrp->log_lock), irq_flags);
+			idx += snprintf(msg + idx, remaining_chars(idx), SL_LOG_LINK_ID_FMT,
+				SL_LOG_CONTEXT,
+				core_link->core_lgrp->core_ldev->num, core_link->core_lgrp->num, core_link->num,
+				core_link->core_lgrp->log_connect_id);
+			spin_unlock_irqrestore(&(core_link->core_lgrp->log_lock), irq_flags);
+			break;
+		case SL_CORE_MAC_MAGIC:
+			core_mac = ptr;
+			spin_lock_irqsave(&(core_mac->core_lgrp->log_lock), irq_flags);
+			idx += snprintf(msg + idx, remaining_chars(idx), SL_LOG_LINK_ID_FMT,
+				SL_LOG_CONTEXT,
+				core_mac->core_lgrp->core_ldev->num, core_mac->core_lgrp->num, core_mac->num,
+				core_mac->core_lgrp->log_connect_id);
+			spin_unlock_irqrestore(&(core_mac->core_lgrp->log_lock), irq_flags);
+			break;
+		case SL_CORE_LLR_MAGIC:
+			core_llr = ptr;
+			spin_lock_irqsave(&(core_llr->core_lgrp->log_lock), irq_flags);
+			idx += snprintf(msg + idx, remaining_chars(idx), SL_LOG_LINK_ID_FMT,
+				SL_LOG_CONTEXT,
+				core_llr->core_lgrp->core_ldev->num, core_llr->core_lgrp->num, core_llr->num,
+				core_llr->core_lgrp->log_connect_id);
+			spin_unlock_irqrestore(&(core_llr->core_lgrp->log_lock), irq_flags);
+			break;
+		case SL_MEDIA_LDEV_MAGIC:
+			media_ldev = ptr;
+			idx += snprintf(msg + idx, remaining_chars(idx), SL_LOG_LDEV_ID_FMT,
+				SL_LOG_CONTEXT,
+				media_ldev->num, media_ldev->num);
+			break;
+		case SL_MEDIA_LGRP_MAGIC:
+			media_lgrp = ptr;
+			spin_lock_irqsave(&media_lgrp->log_lock, irq_flags);
+			idx += snprintf(msg + idx, remaining_chars(idx), SL_LOG_LGRP_ID_FMT,
+				SL_LOG_CONTEXT,
+				media_lgrp->media_ldev->num, media_lgrp->num,
+				media_lgrp->connect_id);
+			spin_unlock_irqrestore(&media_lgrp->log_lock, irq_flags);
+			break;
+		case SL_MEDIA_JACK_MAGIC:
+			media_jack = ptr;
+			spin_lock_irqsave(&media_jack->log_lock, irq_flags);
+			idx += snprintf(msg + idx, remaining_chars(idx), SL_LOG_JACK_ID_FMT,
+				SL_LOG_CONTEXT,
+				media_jack->physical_num);
+			spin_unlock_irqrestore(&media_jack->log_lock, irq_flags);
+			break;
+		default:
+			idx += snprintf(msg + idx, remaining_chars(idx), SL_LOG_DFLT_ID_FMT,
+				SL_LOG_CONTEXT,
+				*((u32 *)ptr));
+			break;
+		}
+	} else {
+		idx += snprintf(msg + idx, remaining_chars(idx), SL_LOG_NULL_ID_FMT,
+			SL_LOG_CONTEXT);
+	}
+
+	snprintf(msg + idx, remaining_chars(idx), " %5s-%-10s: %s\n", block, name, text);
+}
+
+void sl_log(void *ptr, const char *level, const char *block,
+	    const char *name, const char *text, ...)
+{
+	char    msg[SL_LOG_MSG_LEN + 1];
+	va_list args;
+
+	if (!level) {
+		pr_err("NULL level\n");
+		return;
+	}
+	if (!block) {
+		pr_err("NULL block\n");
+		return;
+	}
+	if (!name) {
+		pr_err("NULL name\n");
+		return;
+	}
+	if (!text) {
+		pr_err("NULL text\n");
+		return;
+	}
+
+	sl_log_msg_create(level, ptr, msg, block, name, text);
+
+	va_start(args, text);
+	vprintk(msg, args);
+	va_end(args);
+}
+
+void sl_log_err_trace(void *ptr, const char *block,
+		      const char *name, const char *text, ...)
+{
+	int                  rtn;
+	char                 msg[SL_LOG_MSG_LEN + 1];
+	va_list              args;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	struct sl_ctrl_link  *ctrl_link;
+	struct sl_ctrl_llr   *ctrl_llr;
+	struct sl_ctrl_mac   *ctrl_mac;
+	struct sl_core_lgrp  *core_lgrp;
+	struct sl_core_link  *core_link;
+	struct sl_core_mac   *core_mac;
+	struct sl_core_llr   *core_llr;
+	struct sl_media_lgrp *media_lgrp;
+	bool                  err_trace_enable;
+
+	if (!block) {
+		pr_err("NULL block\n");
+		return;
+	}
+	if (!name) {
+		pr_err("NULL name\n");
+		return;
+	}
+	if (!text) {
+		pr_err("NULL text\n");
+		return;
+	}
+
+	if (ptr == NULL)
+		return;
+
+	switch (*((u32 *)ptr)) {
+	case SL_CTRL_LGRP_MAGIC:
+		ctrl_lgrp = ptr;
+		rtn = sl_ctrl_data_lgrp_is_err_trace_enabled(ctrl_lgrp, &err_trace_enable);
+		if (rtn)
+			return;
+		if (!err_trace_enable)
+			return;
+		break;
+	case SL_CTRL_LINK_MAGIC:
+		ctrl_link = ptr;
+		rtn = sl_ctrl_data_lgrp_is_err_trace_enabled(ctrl_link->ctrl_lgrp, &err_trace_enable);
+		if (rtn)
+			return;
+		if (!err_trace_enable)
+			return;
+		break;
+	case SL_CTRL_LLR_MAGIC:
+		ctrl_llr = ptr;
+		rtn = sl_ctrl_data_lgrp_is_err_trace_enabled(ctrl_llr->ctrl_lgrp, &err_trace_enable);
+		if (rtn)
+			return;
+		if (!err_trace_enable)
+			return;
+		break;
+	case SL_CTRL_MAC_MAGIC:
+		ctrl_mac = ptr;
+		rtn = sl_ctrl_data_lgrp_is_err_trace_enabled(ctrl_mac->ctrl_lgrp, &err_trace_enable);
+		if (rtn)
+			return;
+		if (!err_trace_enable)
+			return;
+		break;
+	case SL_CORE_LGRP_MAGIC:
+		core_lgrp = ptr;
+		rtn = sl_core_data_lgrp_is_err_trace_enabled(core_lgrp, &err_trace_enable);
+		if (rtn)
+			return;
+		if (!err_trace_enable)
+			return;
+		break;
+	case SL_CORE_LINK_MAGIC:
+		core_link = ptr;
+		rtn = sl_core_data_lgrp_is_err_trace_enabled(core_link->core_lgrp, &err_trace_enable);
+		if (rtn)
+			return;
+		if (!err_trace_enable)
+			return;
+		break;
+	case SL_CORE_MAC_MAGIC:
+		core_mac = ptr;
+		rtn = sl_core_data_lgrp_is_err_trace_enabled(core_mac->core_lgrp, &err_trace_enable);
+		if (rtn)
+			return;
+		if (!err_trace_enable)
+			return;
+		break;
+	case SL_CORE_LLR_MAGIC:
+		core_llr = ptr;
+		rtn = sl_core_data_lgrp_is_err_trace_enabled(core_llr->core_lgrp, &err_trace_enable);
+		if (rtn)
+			return;
+		if (!err_trace_enable)
+			return;
+		break;
+	case SL_MEDIA_LGRP_MAGIC:
+		media_lgrp = ptr;
+		rtn = sl_media_data_lgrp_is_err_trace_enabled(media_lgrp, &err_trace_enable);
+		if (rtn)
+			return;
+		if (!err_trace_enable)
+			return;
+		break;
+	default:
+		return;
+	}
+
+	sl_log_msg_create(KERN_ERR, ptr, msg, block, name, text);
+
+	va_start(args, text);
+	vprintk(msg, args);
+	va_end(args);
+}
+
+void sl_log_warn_trace(void *ptr, const char *block,
+		       const char *name, const char *text, ...)
+{
+	int                   rtn;
+	char                  msg[SL_LOG_MSG_LEN + 1];
+	va_list               args;
+	struct sl_ctrl_lgrp  *ctrl_lgrp;
+	struct sl_ctrl_link  *ctrl_link;
+	struct sl_ctrl_llr   *ctrl_llr;
+	struct sl_ctrl_mac   *ctrl_mac;
+	struct sl_core_lgrp  *core_lgrp;
+	struct sl_core_link  *core_link;
+	struct sl_core_mac   *core_mac;
+	struct sl_core_llr   *core_llr;
+	struct sl_media_lgrp *media_lgrp;
+	bool                  warn_trace_enable;
+
+	if (!block) {
+		pr_err("NULL block\n");
+		return;
+	}
+	if (!name) {
+		pr_err("NULL name\n");
+		return;
+	}
+	if (!text) {
+		pr_err("NULL text\n");
+		return;
+	}
+
+	if (ptr == NULL)
+		return;
+
+	switch (*((u32 *)ptr)) {
+	case SL_CTRL_LGRP_MAGIC:
+		ctrl_lgrp = ptr;
+		rtn = sl_ctrl_data_lgrp_is_warn_trace_enabled(ctrl_lgrp, &warn_trace_enable);
+		if (rtn)
+			return;
+		if (!warn_trace_enable)
+			return;
+		break;
+	case SL_CTRL_LINK_MAGIC:
+		ctrl_link = ptr;
+		rtn = sl_ctrl_data_lgrp_is_warn_trace_enabled(ctrl_link->ctrl_lgrp, &warn_trace_enable);
+		if (rtn)
+			return;
+		if (!warn_trace_enable)
+			return;
+		break;
+	case SL_CTRL_LLR_MAGIC:
+		ctrl_llr = ptr;
+		rtn = sl_ctrl_data_lgrp_is_warn_trace_enabled(ctrl_llr->ctrl_lgrp, &warn_trace_enable);
+		if (rtn)
+			return;
+		if (!warn_trace_enable)
+			return;
+		break;
+	case SL_CTRL_MAC_MAGIC:
+		ctrl_mac = ptr;
+		rtn = sl_ctrl_data_lgrp_is_warn_trace_enabled(ctrl_mac->ctrl_lgrp, &warn_trace_enable);
+		if (rtn)
+			return;
+		if (!warn_trace_enable)
+			return;
+		break;
+	case SL_CORE_LGRP_MAGIC:
+		core_lgrp = ptr;
+		rtn = sl_core_data_lgrp_is_warn_trace_enabled(core_lgrp, &warn_trace_enable);
+		if (rtn)
+			return;
+		if (!warn_trace_enable)
+			return;
+		break;
+	case SL_CORE_LINK_MAGIC:
+		core_link = ptr;
+		rtn = sl_core_data_lgrp_is_warn_trace_enabled(core_link->core_lgrp, &warn_trace_enable);
+		if (rtn)
+			return;
+		if (!warn_trace_enable)
+			return;
+		break;
+	case SL_CORE_MAC_MAGIC:
+		core_mac = ptr;
+		rtn = sl_core_data_lgrp_is_warn_trace_enabled(core_mac->core_lgrp, &warn_trace_enable);
+		if (rtn)
+			return;
+		if (!warn_trace_enable)
+			return;
+		break;
+	case SL_CORE_LLR_MAGIC:
+		core_llr = ptr;
+		rtn = sl_core_data_lgrp_is_warn_trace_enabled(core_llr->core_lgrp, &warn_trace_enable);
+		if (rtn)
+			return;
+		if (!warn_trace_enable)
+			return;
+		break;
+	case SL_MEDIA_LGRP_MAGIC:
+		media_lgrp = ptr;
+		rtn = sl_media_data_lgrp_is_warn_trace_enabled(media_lgrp, &warn_trace_enable);
+		if (rtn)
+			return;
+		if (!warn_trace_enable)
+			return;
+		break;
+	default:
+		return;
+	}
+
+	sl_log_msg_create(KERN_WARNING, ptr, msg, block, name, text);
+
+	va_start(args, text);
+	vprintk(msg, args);
+	va_end(args);
+}
+
+void sl_log_io_trace(void *ptr, const char *block, const char *name, const char *text, ...)
+{
+	char                 msg[SL_LOG_MSG_LEN + 1];
+	va_list              args;
+	struct sl_core_lgrp *core_lgrp;
+
+	if (!block) {
+		pr_err("NULL block\n");
+		return;
+	}
+	if (!name) {
+		pr_err("NULL name\n");
+		return;
+	}
+	if (!text) {
+		pr_err("NULL text\n");
+		return;
+	}
+
+	if (!ptr)
+		return;
+
+	switch (*((u32 *)ptr)) {
+	case SL_CORE_LGRP_MAGIC:
+		core_lgrp = ptr;
+		if (!sl_core_data_lgrp_is_io_trace_enabled(core_lgrp))
+			return;
+		break;
+	default:
+		return;
+	}
+
+	sl_log_msg_create(KERN_INFO, ptr, msg, block, name, text);
+
+	va_start(args, text);
+	vprintk(msg, args);
+	va_end(args);
+}
+
+void __sl_log_dynamic_dbg(struct _ddebug *desc, void *ptr, const char *block,
+			  const char *name, const char *text, ...)
+{
+	char    msg[SL_LOG_MSG_LEN + 1];
+	va_list args;
+
+	if (!desc) {
+		pr_err("NULL desc\n");
+		return;
+	}
+	if (!block) {
+		pr_err("NULL desc\n");
+		return;
+	}
+	if (!name) {
+		pr_err("NULL name\n");
+		return;
+	}
+	if (!text) {
+		pr_err("NULL text\n");
+		return;
+	}
+
+	sl_log_msg_create(KERN_DEBUG, ptr, msg, block, name, text);
+
+	va_start(args, text);
+	vprintk(msg, args);
+	va_end(args);
+}
diff --git a/drivers/net/ethernet/hpe/sl/nic/sl_ldev.c b/drivers/net/ethernet/hpe/sl/nic/sl_ldev.c
new file mode 100644
index 000000000000..e93cd667dab8
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/nic/sl_ldev.c
@@ -0,0 +1,147 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/module.h>
+
+#include <linux/hpe/sl/sl_ldev.h>
+
+#include "sl_log.h"
+#include "sl_ldev.h"
+#include "sl_media_ldev.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_LDEV_LOG_NAME
+
+int sl_ldev_attr_check(struct sl_ldev_attr *ldev_attr)
+{
+	if (!ldev_attr) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL ldev_attr");
+		return -EINVAL;
+	}
+	if (IS_ERR(ldev_attr)) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "ldev_attr pointer error");
+		return -EINVAL;
+	}
+	if (ldev_attr->magic != SL_LDEV_ATTR_MAGIC) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "bad ldev_attr magic");
+		return -EINVAL;
+	}
+	if (ldev_attr->ver != SL_LDEV_ATTR_VER) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "bad ldev_attr version");
+		return -EINVAL;
+	}
+	if (!ldev_attr->ops) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL ldev_attr ops");
+		return -EINVAL;
+	}
+	if (!ldev_attr->accessors) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL ldev_attr accessors");
+		return -EINVAL;
+	}
+	if (!ldev_attr->ops->read64) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL ops read64");
+		return -EINVAL;
+	}
+	if (!ldev_attr->ops->write64) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL ops write64");
+		return -EINVAL;
+	}
+	if (!ldev_attr->ops->sbus_op) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL ops sbus_op");
+		return -EINVAL;
+	}
+	if (!ldev_attr->ops->pmi_op) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL ops pmi_op");
+		return -EINVAL;
+	}
+	if (!ldev_attr->ops->pml_intr_register) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL ops pml_intr_register");
+		return -EINVAL;
+	}
+	if (!ldev_attr->ops->pml_intr_unregister) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL ops pml_intr_unregister");
+		return -EINVAL;
+	}
+	if (!ldev_attr->ops->pml_intr_enable) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL ops pml_intr_enable");
+		return -EINVAL;
+	}
+	if (!ldev_attr->ops->pml_intr_disable) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL ops pml_intr_disable");
+		return -EINVAL;
+	}
+	if (!ldev_attr->ops->dt_info_get) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL ops dt_info_get");
+		return -EINVAL;
+	}
+	if (!ldev_attr->ops->mb_info_get) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL ops mb_info_get");
+		return -EINVAL;
+	}
+	if (!ldev_attr->ops->dmac_alloc) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL ops dmac_alloc");
+		return -EINVAL;
+	}
+	if (!ldev_attr->ops->dmac_free) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL ops dmac_free");
+		return -EINVAL;
+	}
+	if (!ldev_attr->ops->dmac_xfer) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL ops dmac_xfer");
+		return -EINVAL;
+	}
+
+	if (!ldev_attr->accessors->pci) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL accessor PCI");
+		return -EINVAL;
+	}
+	if (!ldev_attr->accessors->sbus) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL accessor SBUS");
+		return -EINVAL;
+	}
+	if (!ldev_attr->accessors->pmi) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL accessor PMI");
+		return -EINVAL;
+	}
+	if (!ldev_attr->accessors->intr) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL accessor INTR");
+		return -EINVAL;
+	}
+	if (!ldev_attr->accessors->dt) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL accessor DT");
+		return -EINVAL;
+	}
+	if (!ldev_attr->accessors->mb) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL accessor MB");
+		return -EINVAL;
+	}
+	if (!ldev_attr->accessors->dmac) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL accessor DMAC");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int sl_ldev_uc_ops_set(struct sl_ldev *ldev, struct sl_uc_ops *uc_ops,
+		       struct sl_uc_accessor *uc_accessor)
+{
+	int rtn;
+
+	rtn = sl_ldev_check(ldev);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "check fail");
+		return rtn;
+	}
+
+	sl_log_dbg(ldev, LOG_BLOCK, LOG_NAME, "uc ops_set");
+
+	rtn = sl_media_ldev_uc_ops_set(ldev->num, uc_ops, uc_accessor);
+	if (rtn) {
+		sl_log_err(ldev, LOG_BLOCK, LOG_NAME, "media_ldev_uc_ops_set failed [%d]", rtn);
+		return rtn;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(sl_ldev_uc_ops_set);
diff --git a/drivers/net/ethernet/hpe/sl/nic/sl_media.c b/drivers/net/ethernet/hpe/sl/nic/sl_media.c
new file mode 100644
index 000000000000..dddfaef0cb28
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/nic/sl_media.c
@@ -0,0 +1,53 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2024,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/module.h>
+
+#include <linux/hpe/sl/sl_media.h>
+
+#include "base/sl_media_log.h"
+#include "sl_lgrp.h"
+#include "sl_media_lgrp.h"
+#include "sl_media_jack.h"
+
+#define LOG_BLOCK SL_LOG_BLOCK
+#define LOG_NAME  SL_LOG_MEDIA_LOG_NAME
+
+int sl_media_cable_insert(struct sl_lgrp *lgrp, u8 *eeprom_page0, u8 *eeprom_page1, u32 flags)
+{
+	int rtn;
+
+	rtn = sl_lgrp_check(lgrp);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "cable insert fail");
+		return rtn;
+	}
+	if (!eeprom_page0) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "NULL eeprom");
+		return -EINVAL;
+	}
+
+	/*
+	 * hardcoding 0 for now since there is only one jack. Might change in future
+	 */
+	return sl_media_jack_cable_insert(lgrp->ldev_num, lgrp->num, 0, eeprom_page0,
+					  eeprom_page1, flags);
+}
+EXPORT_SYMBOL(sl_media_cable_insert);
+
+int sl_media_cable_remove(struct sl_lgrp *lgrp)
+{
+	int rtn;
+
+	rtn = sl_lgrp_check(lgrp);
+	if (rtn) {
+		sl_log_err(NULL, LOG_BLOCK, LOG_NAME, "cable remove fail");
+		return rtn;
+	}
+
+	/*
+	 * hardcoding 0 for now since there is only one jack. Might change in future
+	 */
+	return sl_media_jack_cable_remove(lgrp->ldev_num, lgrp->num, 0);
+}
+EXPORT_SYMBOL(sl_media_cable_remove);

-- 
2.56.0


^ permalink raw reply	[flat|nested] 25+ messages in thread
* [PATCH 16/23] net: hpe: ss1: add the Cassini core device layer
  2026-10-30 20:58 [PATCH 00/23] Subject: [PATCH net-next 00/23] net/hpe: add HPE Slingshot NIC drivers Doug Ledford
                   ` (14 preceding siblings ...)
  2026-10-30 20:59 ` [PATCH 15/23] net: hpe: sl: add the NIC binding and logging helpers Doug Ledford
@ 2026-10-30 20:59 ` Doug Ledford
  2026-10-30 20:59 ` [PATCH 17/23] net: hpe: ss1: add the datapath and memory translation layers Doug Ledford
                   ` (7 subsequent siblings)
  23 siblings, 0 replies; 25+ messages in thread
From: Doug Ledford @ 2026-10-30 20:59 UTC (permalink / raw)
  To: Slingshot Open Source Team, Nathan Chancellor, Nicolas Schier,
	Richard Cochran, Andrew Lunn, David S. Miller, Eric Dumazet,
	Jakub Kicinski, Paolo Abeni, Sumit Semwal, Christian König,
	Guenter Roeck
  Cc: linux-kernel, netdev, linux-kbuild, Doug Ledford, Sandeep Bhoot,
	Iraimani P, Mamila Santosh

Add the PCI device core: probe and remove, device information, interrupt
setup, cable and link handling and the debugfs interface.

The private headers of the whole driver are added with this patch so
that each later patch, which adds the sources of one layer, compiles
on its own.

Known limitation, deferred to V2: this patch carries SR-IOV
virtual-function code (VF-to-PF mailbox requests, mailbox opcodes or VF
resource handling) from an older, incomplete version of the Cassini
SR-IOV support. V2 of this series will include the updated SR-IOV
implementation, so issues in the VF paths should be ignored for now.

checkpatch --strict (100 columns) still reports the following in this
patch. They need coordination with the internal repositories this code
is maintained in and will be fixed in V2:
- ERROR: COMPLEX_MACRO (5), FLEXIBLE_ARRAY (4)
- WARNING: LEADING_SPACE (47), SPDX_LICENSE_TAG (8), ENOTSUPP (6),
  PREFER_DEFINED_ATTRIBUTE_MACRO (3), BLOCK_COMMENT_STYLE (2),
  MACRO_ARG_UNUSED (2), RETURN_VOID (2), ALLOC_WITH_SIZEOF (1),
  AVOID_BUG (1), BRACES (1), DEPRECATED_API (1), LONG_LINE (1),
  LONG_LINE_COMMENT (1), STRCPY (1)
- CHECK: UNCOMMENTED_DEFINITION (32), BRACES (15), COMPARISON_TO_NULL
  (15), MACRO_ARG_PRECEDENCE (14), MACRO_ARG_REUSE (13), BIT_MACRO (5),
  AVOID_EXTERNS (4), UNNECESSARY_PARENTHESES (4), OPEN_ENDED_LINE (3),
  LINE_SPACING (1), PARENTHESIS_ALIGNMENT (1)

Co-developed-by: Sandeep Bhoot <sandeep.bhoot@hpe.com>
Signed-off-by: Sandeep Bhoot <sandeep.bhoot@hpe.com>
Co-developed-by: Iraimani P <iraimani.pavadai@hpe.com>
Signed-off-by: Iraimani P <iraimani.pavadai@hpe.com>
Co-developed-by: Mamila Santosh <santosh-kumar.mamila@hpe.com>
Signed-off-by: Mamila Santosh <santosh-kumar.mamila@hpe.com>
Signed-off-by: Doug Ledford <doug.ledford@hpe.com>
---
 drivers/net/ethernet/hpe/ss1/cass_cable.c          |  702 ++++
 drivers/net/ethernet/hpe/ss1/cass_cable.h          |  157 +
 drivers/net/ethernet/hpe/ss1/cass_core.c           | 1564 ++++++++
 drivers/net/ethernet/hpe/ss1/cass_core.h           | 1472 ++++++++
 drivers/net/ethernet/hpe/ss1/cass_dev_info.c       |   60 +
 drivers/net/ethernet/hpe/ss1/cass_irq.c            |  210 ++
 drivers/net/ethernet/hpe/ss1/cass_link.c           |  192 +
 drivers/net/ethernet/hpe/ss1/cass_link_misc.c      |  159 +
 drivers/net/ethernet/hpe/ss1/cass_p2p.h            |   69 +
 drivers/net/ethernet/hpe/ss1/cass_rgroup.h         |   30 +
 drivers/net/ethernet/hpe/ss1/cass_rx_tx_profile.h  |   15 +
 drivers/net/ethernet/hpe/ss1/cass_sbl.h            |  581 +++
 drivers/net/ethernet/hpe/ss1/cass_sl.h             |   95 +
 drivers/net/ethernet/hpe/ss1/cass_sl_io.h          |   19 +
 drivers/net/ethernet/hpe/ss1/cass_ss1_debugfs.c    |  824 +++++
 drivers/net/ethernet/hpe/ss1/cass_ss1_debugfs.h    |   86 +
 drivers/net/ethernet/hpe/ss1/cass_telem_tables.h   | 3874 ++++++++++++++++++++
 drivers/net/ethernet/hpe/ss1/cass_trace.h          |   60 +
 drivers/net/ethernet/hpe/ss1/cass_vf.h             |   59 +
 drivers/net/ethernet/hpe/ss1/cass_vf_notif.h       |   34 +
 drivers/net/ethernet/hpe/ss1/cuc_cxi.h             |  370 ++
 drivers/net/ethernet/hpe/ss1/cxi_ac_entry_list.h   |   20 +
 drivers/net/ethernet/hpe/ss1/cxi_aux_dev.h         |   14 +
 drivers/net/ethernet/hpe/ss1/cxi_config.h          |  234 ++
 drivers/net/ethernet/hpe/ss1/cxi_configuration.h   |  332 ++
 drivers/net/ethernet/hpe/ss1/cxi_core.h            |  434 +++
 drivers/net/ethernet/hpe/ss1/cxi_eth.h             |  352 ++
 drivers/net/ethernet/hpe/ss1/cxi_eth_debugfs.h     |   26 +
 drivers/net/ethernet/hpe/ss1/cxi_ethtool.h         |   26 +
 drivers/net/ethernet/hpe/ss1/cxi_ethtool_names.h   |  110 +
 drivers/net/ethernet/hpe/ss1/cxi_internal.h        |   39 +
 drivers/net/ethernet/hpe/ss1/cxi_link.h            |   65 +
 drivers/net/ethernet/hpe/ss1/cxi_qos_profiles.h    |  149 +
 drivers/net/ethernet/hpe/ss1/cxi_rgroup.h          |   68 +
 drivers/net/ethernet/hpe/ss1/cxi_rxtx_profile.h    |  135 +
 .../net/ethernet/hpe/ss1/cxi_rxtx_profile_list.h   |   53 +
 drivers/net/ethernet/hpe/ss1/cxi_vf_cmd.h          |   52 +
 drivers/net/ethernet/hpe/ss1/pldm_cxi.h            |  374 ++
 38 files changed, 13115 insertions(+)

diff --git a/drivers/net/ethernet/hpe/ss1/cass_cable.c b/drivers/net/ethernet/hpe/ss1/cass_cable.c
new file mode 100644
index 000000000000..a9008a839bd5
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_cable.c
@@ -0,0 +1,702 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2021-2022,2025 Hewlett Packard Enterprise Development LP */
+
+/* Cassini HSN cable support */
+
+#include <linux/hpe/sbl/sbl.h>
+#include "cass_core.h"
+#include "cass_cable.h"
+
+static int cass_hdsh_get_format(struct cass_dev *hw, u8 *qsfp_format);
+static void cass_hdsh_get_media(struct cass_dev *hw,
+				struct sbl_media_attr *attr, u8 qsfp_format);
+static void cass_hdsh_get_info(struct cass_dev *hw,
+			       struct sbl_media_attr *attr, u8 qsfp_format);
+static void cass_hdsh_get_length(struct cass_dev *hw,
+				 struct sbl_media_attr *attr, u8 qsfp_format);
+static void cass_hdsh_get_vendor(struct cass_dev *hw,
+				 struct sbl_media_attr *attr, u8 qsfp_format);
+static int cass_link_headshell_down_no_media(struct cass_dev *hw, int reason);
+
+/**
+ * cass_is_cable_present() - Check if we have an HSN cable installed
+ *
+ * @hw: the device
+ *
+ * Return: 1 if cable present, else 0
+ */
+int cass_is_cable_present(struct cass_dev *hw)
+{
+	if (!HW_PLATFORM_ASIC(hw))
+		return 1;
+	return (hw->qsfp_eeprom_page_len != 0);
+}
+
+/**
+ * cass_parse_heashell_data() - Read the QSFP EEPROM and parse into attr
+ *
+ * @hw: the device
+ * @attr: pointer to struct to initialize with cable information
+ * @qsfp_format: What spec this cable CSR space is organized according to.
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+int cass_parse_heashell_data(struct cass_dev *hw, struct sbl_media_attr *attr,
+			     u8 *qsfp_format)
+{
+	int rc = 0;
+
+	mutex_lock(&hw->qsfp_eeprom_lock);
+
+	if (hw->qsfp_eeprom_page_len <= 0) {
+		cxidev_err(&hw->cdev,
+			   "Failed to parse headshell data. EEPROM data unavailable!\n");
+		rc = -EIO;
+		goto out_unlock;
+	}
+
+	/* Start by determining the cable format */
+	rc = cass_hdsh_get_format(hw, qsfp_format);
+	if (rc)
+		goto out_unlock;
+
+	/* Read out media type information and parse into attr */
+	cass_hdsh_get_media(hw, attr, *qsfp_format);
+
+	/* Read out the supported speed modes into attr */
+	cass_hdsh_get_info(hw, attr, *qsfp_format);
+
+	/* Read out media length information into attr */
+	cass_hdsh_get_length(hw, attr, *qsfp_format);
+
+	/* Read out vendor information and parse into attr */
+	cass_hdsh_get_vendor(hw, attr, *qsfp_format);
+
+ out_unlock:
+	mutex_unlock(&hw->qsfp_eeprom_lock);
+	return rc;
+}
+
+/**
+ * cass_hdsh_get_format() - Read the QSFP EEPROM and parse out the media format
+ *
+ * @hw: the device
+ * @qsfp_format: pointer to spec this cable CSR space is organized according to
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+static int cass_hdsh_get_format(struct cass_dev *hw, u8 *qsfp_format)
+{
+	if (hw->qsfp_eeprom_page0[QSFP_IDENTIFIER_OFFSET] >= SFF8024_TYPE_QSFPDD) {
+		// What revision compliance do they claim
+		if (hw->qsfp_eeprom_page0[QSFP_REV_CMPL_OFFSET] < 0x27)
+			/* Very similar to CMIS 2.0, might need to distinguish
+			 *  someday?
+			 */
+			*qsfp_format = QDD_SFF8636;
+		else {
+			*qsfp_format = QDD_CMIS;
+			/* CMIS V3.0-V4.0 are mostly compatible.
+			 * Version-specific differences are handled in the code.
+			 */
+			/* allow CMIS v5.* */
+			if (hw->qsfp_eeprom_page0[QSFP_REV_CMPL_OFFSET] >= 0x60) {
+				cxidev_err(&hw->cdev,
+					   "Failed to parse headshell data. Bad CMIS rev (%d)!\n",
+					   hw->qsfp_eeprom_page0[QSFP_REV_CMPL_OFFSET]);
+				return -EMEDIUMTYPE;
+			}
+		}
+	} else
+		// Treat anything else as SFF-8636 Format
+		*qsfp_format = QDD_SFF8636;
+
+	return 0;
+}
+
+/**
+ * cass_hdsh_get_media() - Read the QSFP EEPROM and parse out the media type
+ *
+ * @hw: the device
+ * @attr: pointer to struct to initialize with cable information
+ * @qsfp_format: What spec this cable CSR space is organized according to.
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+static void cass_hdsh_get_media(struct cass_dev *hw,
+				struct sbl_media_attr *attr, u8 qsfp_format)
+{
+	u8 qsfp_media;
+
+	if (qsfp_format == QDD_CMIS)
+		qsfp_media = hw->qsfp_eeprom_page0[CMIS_MEDIA_TYPE_OFFSET];
+	else /* QDD_SFF8636 */
+		qsfp_media = hw->qsfp_eeprom_page0[SFF8436_MEDIA_TYPE_OFFSET];
+	if (qsfp_media >= MEDIA_COPPER_UNEQ)
+		attr->media = SBL_LINK_MEDIA_ELECTRICAL;
+	else
+		attr->media = SBL_LINK_MEDIA_OPTICAL;
+}
+
+/**
+ * cass_hdsh_get_info() - Read the QSFP EEPROM and parse out the media info
+ *
+ * @hw: the device
+ * @attr: pointer to struct to initialize with cable information
+ * @qsfp_format: What spec this cable CSR space is organized according to.
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+static void cass_hdsh_get_info(struct cass_dev *hw,
+			       struct sbl_media_attr *attr, u8 qsfp_format)
+{
+	if (attr->media == SBL_LINK_MEDIA_ELECTRICAL)
+		// For copper cables, we support all link modes
+		attr->info = SBL_MEDIA_INFO_SUPPORTS_BS_200G |
+			SBL_MEDIA_INFO_SUPPORTS_BJ_100G |
+			SBL_MEDIA_INFO_SUPPORTS_CD_100G |
+			SBL_MEDIA_INFO_SUPPORTS_CD_50G;
+	else {
+		if (qsfp_format == QDD_CMIS)
+			/* TODO - CMIS support is not immediately required */
+			return;
+		/* else: QDD_SFF8636 */
+		/* SFF8636 is not supported, so advertise all link mode
+		 *  are supported.
+		 */
+		attr->info = SBL_MEDIA_INFO_SUPPORTS_BS_200G |
+			SBL_MEDIA_INFO_SUPPORTS_BJ_100G |
+			SBL_MEDIA_INFO_SUPPORTS_CD_100G |
+			SBL_MEDIA_INFO_SUPPORTS_CD_50G;
+	}
+}
+
+/**
+ * cass_hdsh_get_length() - Read the QSFP EEPROM and parse out the media length
+ *
+ * @hw: the device
+ * @attr: pointer to struct to initialize with cable information
+ * @qsfp_format: What spec this cable CSR space is organized according to.
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+static void cass_hdsh_get_length(struct cass_dev *hw,
+				 struct sbl_media_attr *attr, u8 qsfp_format)
+{
+	u8 qsfp_length;
+	int mult, qsfp_length_mm;
+
+	if (qsfp_format == QDD_CMIS) {
+		qsfp_length = hw->qsfp_eeprom_page0[CMIS_CABLE_LEN_OFFSET];
+		mult = (qsfp_length & 0xC0) >> 6;
+		qsfp_length &= 0x3F;
+		switch (mult) {
+		case 0:
+			attr->len = qsfp_length * 10;
+			break;
+		case 1:
+			attr->len = qsfp_length * 100;
+			break;
+		case 2:
+			attr->len = qsfp_length * 1000;
+			break;
+		case 3:
+			attr->len = qsfp_length * 10000;
+			break;
+		default:
+			attr->len = 0;
+			break;
+		}
+	} else { /* QDD_SFF8636 */
+		qsfp_length = hw->qsfp_eeprom_page0[SFF8436_LINK_LEN_OFFSET];
+		attr->len = qsfp_length * 100;
+	}
+
+	/* TODO - sbl_link_len will be converted to len in cm, rather than
+	 *  this enum. Remove this section when that happens
+	 */
+	qsfp_length_mm = attr->len * 10;
+	switch (qsfp_length_mm) {
+	case 300:
+		attr->len = SBL_LINK_LEN_000_300; break;
+	case 400:
+		attr->len = SBL_LINK_LEN_000_400; break;
+	case 750:
+		attr->len = SBL_LINK_LEN_000_750; break;
+	case 800:
+		attr->len = SBL_LINK_LEN_000_800; break;
+	case 1000:
+		attr->len = SBL_LINK_LEN_001_000; break;
+	case 1100:
+		attr->len = SBL_LINK_LEN_001_100; break;
+	case 1150:
+		attr->len = SBL_LINK_LEN_001_150; break;
+	case 1200:
+		attr->len = SBL_LINK_LEN_001_200; break;
+	case 1400:
+		attr->len = SBL_LINK_LEN_001_400; break;
+	case 1420:
+		attr->len = SBL_LINK_LEN_001_420; break;
+	case 1500:
+		attr->len = SBL_LINK_LEN_001_500; break;
+	case 1600:
+		attr->len = SBL_LINK_LEN_001_600; break;
+	case 1640:
+		attr->len = SBL_LINK_LEN_001_640; break;
+	case 1700:
+		attr->len = SBL_LINK_LEN_001_700; break;
+	case 1900:
+		attr->len = SBL_LINK_LEN_001_900; break;
+	case 1910:
+		attr->len = SBL_LINK_LEN_001_910; break;
+	case 2000:
+		attr->len = SBL_LINK_LEN_002_000; break;
+	case 2100:
+		attr->len = SBL_LINK_LEN_002_100; break;
+	case 2130:
+		attr->len = SBL_LINK_LEN_002_130; break;
+	case 2200:
+		attr->len = SBL_LINK_LEN_002_200; break;
+	case 2300:
+		attr->len = SBL_LINK_LEN_002_300; break;
+	case 2390:
+		attr->len = SBL_LINK_LEN_002_390; break;
+	case 2400:
+		attr->len = SBL_LINK_LEN_002_400; break;
+	case 2500:
+		attr->len = SBL_LINK_LEN_002_500; break;
+	case 2600:
+		attr->len = SBL_LINK_LEN_002_600; break;
+	case 2620:
+		attr->len = SBL_LINK_LEN_002_620; break;
+	case 2700:
+		attr->len = SBL_LINK_LEN_002_700; break;
+	case 2800:
+		attr->len = SBL_LINK_LEN_002_800; break;
+	case 2900:
+		attr->len = SBL_LINK_LEN_002_900; break;
+	case 2990:
+		attr->len = SBL_LINK_LEN_002_990; break;
+	case 3000:
+		attr->len = SBL_LINK_LEN_003_000; break;
+	case 4000:
+		attr->len = SBL_LINK_LEN_004_000; break;
+	case 5000:
+		attr->len = SBL_LINK_LEN_005_000; break;
+	case 6000:
+		attr->len = SBL_LINK_LEN_006_000; break;
+	case 7000:
+		attr->len = SBL_LINK_LEN_007_000; break;
+	case 8000:
+		attr->len = SBL_LINK_LEN_008_000; break;
+	case 10000:
+		attr->len = SBL_LINK_LEN_010_000; break;
+	case 14000:
+		attr->len = SBL_LINK_LEN_014_000; break;
+	case 15000:
+		attr->len = SBL_LINK_LEN_015_000; break;
+	case 19000:
+		attr->len = SBL_LINK_LEN_019_000; break;
+	case 25000:
+		attr->len = SBL_LINK_LEN_025_000; break;
+	case 30000:
+		attr->len = SBL_LINK_LEN_030_000; break;
+	case 35000:
+		attr->len = SBL_LINK_LEN_035_000; break;
+	case 50000:
+		attr->len = SBL_LINK_LEN_050_000; break;
+	case 75000:
+		attr->len = SBL_LINK_LEN_075_000; break;
+	case 100000:
+		attr->len = SBL_LINK_LEN_100_000; break;
+	default:
+		attr->len = SBL_LINK_LEN_INVALID;
+		cxidev_warn(&hw->cdev, "No valid enum found for link length %d!",
+			    qsfp_length_mm);
+		break;
+	}
+}
+
+/**
+ * cass_hdsh_get_vendor() - Read the QSFP EEPROM and parse out the media vendor
+ *
+ * @hw: the device
+ * @attr: pointer to struct to initialize with cable information
+ * @qsfp_format: What spec this cable CSR space is organized according to.
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+static void cass_hdsh_get_vendor(struct cass_dev *hw,
+				 struct sbl_media_attr *attr, u8 qsfp_format)
+{
+	const char *qsfp_vendor;
+
+	if (qsfp_format == QDD_CMIS)
+		qsfp_vendor = &(hw->qsfp_eeprom_page0[CMIS_VENDOR_OFFSET]);
+	else /* QDD_SFF8636 */
+		qsfp_vendor = &(hw->qsfp_eeprom_page0[SFF8436_VENDOR_OFFSET]);
+
+	if (strnstr(qsfp_vendor, QDD_VENDOR_TE, QSFP_VENDOR_MAX_STR_LEN) != NULL)
+		attr->vendor = SBL_LINK_VENDOR_TE;
+	else if (strnstr(qsfp_vendor, QDD_VENDOR_LEONI, QSFP_VENDOR_MAX_STR_LEN) != NULL)
+		attr->vendor = SBL_LINK_VENDOR_LEONI;
+	else if (strnstr(qsfp_vendor, QDD_VENDOR_MOLEX, QSFP_VENDOR_MAX_STR_LEN) != NULL)
+		attr->vendor = SBL_LINK_VENDOR_MOLEX;
+	else if (strnstr(qsfp_vendor, QDD_VENDOR_HISENSE, QSFP_VENDOR_MAX_STR_LEN) != NULL)
+		attr->vendor = SBL_LINK_VENDOR_HISENSE;
+	else if (strnstr(qsfp_vendor, QDD_VENDOR_DUST_PHOTONICS, QSFP_VENDOR_MAX_STR_LEN) != NULL)
+		attr->vendor = SBL_LINK_VENDOR_DUST_PHOTONICS;
+	else if (strnstr(qsfp_vendor, QDD_VENDOR_FINISAR, QSFP_VENDOR_MAX_STR_LEN) != NULL)
+		attr->vendor = SBL_LINK_VENDOR_FINISAR;
+	else if (strnstr(qsfp_vendor, QDD_VENDOR_LUXSHARE, QSFP_VENDOR_MAX_STR_LEN) != NULL)
+		attr->vendor = SBL_LINK_VENDOR_LUXSHARE;
+	else if (strnstr(qsfp_vendor, QDD_VENDOR_FIT, QSFP_VENDOR_MAX_STR_LEN) != NULL)
+		attr->vendor = SBL_LINK_VENDOR_FIT;
+	else if (strnstr(qsfp_vendor, QDD_VENDOR_FT, QSFP_VENDOR_MAX_STR_LEN) != NULL)
+		attr->vendor = SBL_LINK_VENDOR_FT;
+	else if (strnstr(qsfp_vendor, QDD_VENDOR_MELLANOX, QSFP_VENDOR_MAX_STR_LEN) != NULL)
+		attr->vendor = SBL_LINK_VENDOR_MELLANOX;
+	else if (strnstr(qsfp_vendor, QDD_VENDOR_HITACHI, QSFP_VENDOR_MAX_STR_LEN) != NULL)
+		attr->vendor = SBL_LINK_VENDOR_HITACHI;
+	else if (strnstr(qsfp_vendor, QDD_VENDOR_HPE, QSFP_VENDOR_MAX_STR_LEN) != NULL)
+		attr->vendor = SBL_LINK_VENDOR_HPE;
+	else if (strnstr(qsfp_vendor, QDD_VENDOR_CLOUD_LIGHT, QSFP_VENDOR_MAX_STR_LEN) != NULL)
+		attr->vendor = SBL_LINK_VENDOR_CLOUD_LIGHT;
+	else if (strnstr(qsfp_vendor, QDD_VENDOR_AMPHENOL, QSFP_VENDOR_MAX_STR_LEN) != NULL)
+		attr->vendor = SBL_LINK_VENDOR_AMPHENOL;
+	else {
+		cxidev_warn(&hw->cdev, "No valid enum found for link Vendor %.*s",
+			    QSFP_VENDOR_MAX_STR_LEN, qsfp_vendor);
+		attr->vendor = SBL_LINK_VENDOR_INVALID;
+	}
+}
+
+/**
+ * cass_headshell_power_up() - Power headshell up to high power mode
+ *
+ * @hw: the device
+ * @qsfp_format: What spec this cable CSR space is organized according to.
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+int cass_headshell_power_up(struct cass_dev *hw, u8 qsfp_format)
+{
+	u8 qsfp_extid, data;
+	int rc = 0;
+
+	mutex_lock(&hw->qsfp_eeprom_lock);
+
+	// Full power up of all data paths + high power mode
+	if (qsfp_format == QDD_CMIS) {
+		/* TODO: aapl script will do the power up */
+		rc = 0;
+	} else if (qsfp_format == QDD_SFF8636) {
+		// If not, power up the QSFP
+		data = (SFF8636_PWR_CLASS_567_ENABLE | SFF8636_PWR_OVERRIDE);
+		qsfp_extid = hw->qsfp_eeprom_page0[SFF8436_EXT_IDENTIFIER_OFFSET];
+		// If the module supports Class8+ set that enable bit too
+		if (qsfp_extid & SFF8636_PWR_CLASS_8)
+			data |= SFF8636_PWR_CLASS_8_ENABLE;
+		rc = uc_cmd_qsfp_write(hw, 0, SFF8436_POWER_DATA_OFFSET,
+				       &data, sizeof(data));
+	} else
+		rc = -EINVAL;
+
+	mutex_unlock(&hw->qsfp_eeprom_lock);
+	return rc;
+}
+
+/**
+ * cass_link_headshell_insert() - Headshell insert
+ *
+ * @hw: the device
+ * @attr: pointer to struct containing cable information
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+int cass_link_headshell_insert(struct cass_dev *hw,
+			       struct sbl_media_attr *attr)
+{
+	int err;
+
+	cass_phy_set_state(CASS_PHY_NOLINK, hw);
+	cxidev_dbg(&hw->cdev, "headshell insert: phy state = %d\n", hw->phy.state);
+
+	if (hw->port->hstate == CASS_HEADSHELL_STATUS_PRESENT) {
+		cxidev_err(&hw->cdev, "headshell insert - already present\n");
+		return -EUCLEAN;
+	}
+
+	if (hw->port->config_state & CASS_MEDIA_CONFIGURED) {
+		cxidev_err(&hw->cdev,
+			   "headshell insert - media already configured\n");
+		return -EUCLEAN;
+	}
+
+	err = hw->link_ops->media_config(hw, attr);
+	if (err) {
+		cxidev_err(&hw->cdev, "headshell insert - media config failed [%d]\n",
+			   err);
+		hw->port->config_state &= ~CASS_MEDIA_CONFIGURED;
+		return err;
+	}
+
+	/*
+	 * check any existing link config is compatible with the new media type
+	 *
+	 *    if not unconfigure link so it must be reconfigured again
+	 *
+	 */
+	if (hw->port->config_state & CASS_LINK_CONFIGURED) {
+		switch (hw->port->lattr.bl.config_target) {
+		case SBL_BASE_LINK_CONFIG_PEC:
+			if (attr->media != SBL_LINK_MEDIA_ELECTRICAL) {
+				cxidev_warn(&hw->cdev,
+					    "headshell insert - link attr PEC incompatible with new media");
+				hw->port->config_state &= ~CASS_LINK_CONFIGURED;
+			}
+			break;
+		case SBL_BASE_LINK_CONFIG_AOC:
+			if (attr->media != SBL_LINK_MEDIA_OPTICAL) {
+				cxidev_warn(&hw->cdev,
+					    "headshell insert - link attr AOC incompatible with new media");
+				hw->port->config_state &= ~CASS_LINK_CONFIGURED;
+			}
+			break;
+		default:
+			cxidev_warn(&hw->cdev,
+				    "headshell insert - link attr incompatible with new media");
+			hw->port->config_state &= ~CASS_LINK_CONFIGURED;
+			break;
+		}
+	}
+
+	hw->port->hstate = CASS_HEADSHELL_STATUS_PRESENT;
+	hw->port->config_state |= CASS_MEDIA_CONFIGURED;
+
+	/*
+	 * if the link is supposed to be up try to restart it
+	 */
+	if ((cass_link_get_state(hw) == CASS_LINK_STATUS_DOWN) &&
+	    (hw->port->lmon_dirn == CASS_LMON_DIRECTION_UP)) {
+
+		if ((hw->port->lattr.options &
+		     CASS_LINK_OPT_RESTART_ON_INSERT)) {
+			cxidev_dbg(&hw->cdev, "starting link after insert\n");
+			cass_lmon_request_up(hw);
+		}
+	}
+
+	return 0;
+}
+
+/**
+ * cass_link_headshell_remove() - Headshell remove
+ *
+ *    Headshell must already be present and media configured.
+ *    Stop link if running and unconfigure media
+ *
+ * @hw: the device
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+int cass_link_headshell_remove(struct cass_dev *hw)
+{
+	int err;
+
+	cass_phy_set_state(CASS_PHY_HEADSHELL_REMOVED, hw);
+	cxidev_dbg(&hw->cdev, "headshell remove: phy state = %d\n", hw->phy.state);
+
+	switch (hw->port->hstate) {
+	case CASS_HEADSHELL_STATUS_NOT_PRESENT:
+		cxidev_err(&hw->cdev, "headshell remove - not present\n");
+		return -EUCLEAN;
+
+	case CASS_HEADSHELL_STATUS_PRESENT:
+		if (!(hw->port->config_state & CASS_MEDIA_CONFIGURED)) {
+			cxidev_err(&hw->cdev,
+				   "headshell remove - media not configured\n");
+			return -EUCLEAN;
+		}
+		break;
+
+	case CASS_HEADSHELL_STATUS_ERROR:
+		break;
+
+	default:
+		cxidev_err(&hw->cdev, "headshell remove - unrecognised state\n");
+		return -EUCLEAN;
+	}
+
+	/* stop link coming up */
+	cass_lmon_set_up_pause(hw, true);
+
+	/* setup new state */
+	hw->port->hstate = CASS_HEADSHELL_STATUS_NOT_PRESENT;
+	cass_link_set_led(hw);
+
+	/* ensure link down and no media configured */
+	err = cass_link_headshell_down_no_media(hw,
+						CASS_DOWN_ORIGIN_HEADSHELL_REMOVED);
+	if (err) {
+		cxidev_err(&hw->cdev,
+			   "headshell remove - down_no_media failed [%d]\n",
+			   err);
+		cass_lmon_set_up_pause(hw, false);
+		return err;
+	}
+
+	cass_lmon_set_up_pause(hw, false);
+	return 0;
+}
+
+/**
+ * cass_link_headshell_error() - Headshell error
+ *
+ *    Any start state
+ *    Stop link and unconfigure media
+ *
+ * @hw: the device
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+int cass_link_headshell_error(struct cass_dev *hw)
+{
+	int err;
+
+	cass_phy_set_state(CASS_PHY_HEADSHELL_REMOVED, hw);
+	cxidev_dbg(&hw->cdev, "headshell error: phy state = %d\n", hw->phy.state);
+
+	/* stop link coming up */
+	cass_lmon_set_up_pause(hw, true);
+
+	/* ensure link down and no media configured */
+	err = cass_link_headshell_down_no_media(hw,
+						CASS_DOWN_ORIGIN_HEADSHELL_ERROR);
+	if (err) {
+		cxidev_err(&hw->cdev,
+			   "headshell error - down_no_media failed [%d]\n",
+			   err);
+		cass_lmon_set_up_pause(hw, false);
+		return err;
+	}
+
+	/* setup new state */
+	hw->port->hstate = CASS_HEADSHELL_STATUS_ERROR;
+	cass_link_set_led(hw);
+
+	cass_lmon_set_up_pause(hw, false);
+	return 0;
+}
+
+/**
+ * cass_link_headshell_down_no_media() - take link down and unconfigure cable
+ *
+ * Common headshell remove/error code to stop link and unconfigure media
+ *
+ * @hw: the device
+ * @reason: the reason the link is going down
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+static int cass_link_headshell_down_no_media(struct cass_dev *hw, int reason)
+{
+	int err;
+
+	cxidev_dbg(&hw->cdev, "headshell down no media\n");
+
+	/* ensure link down  */
+	spin_lock(&hw->port->lock);
+	switch (hw->port->lstate) {
+	case CASS_LINK_STATUS_DOWN:
+	case CASS_LINK_STATUS_ERROR:
+	case CASS_LINK_STATUS_UNCONFIGURED:
+	case CASS_LINK_STATUS_UNKNOWN:
+		cxidev_dbg(&hw->cdev, "headshell down - already link down (%s)\n",
+			   cass_link_state_str(hw->port->lstate));
+		spin_unlock(&hw->port->lock);
+		break;
+	default:
+		spin_unlock(&hw->port->lock);
+		err = cass_link_async_down_wait(hw, reason);
+		if (err) {
+			cxidev_err(&hw->cdev,
+				   "headshell down - down_wait failed [%d]\n",
+				   err);
+			return err;
+		}
+		break;
+	}
+
+	/* remove any media configuration */
+	if (hw->port->config_state & CASS_MEDIA_CONFIGURED) {
+		err = hw->link_ops->media_unconfig(hw);
+		if (err) {
+			cxidev_err(&hw->cdev, "headshell down - media unconfig failed [%d]\n", err);
+			return err;
+		}
+		hw->port->config_state &= ~CASS_MEDIA_CONFIGURED;
+	}
+
+	return 0;
+}
+
+/*
+ * Direct media configuration
+ *
+ *   Called by hms to set media for backplane media
+ *
+ *   If you are playing with the backplane (i.e. changing compute blades)
+ *   then leave it to the user to restart the link
+ */
+int cass_link_media_config(struct cass_dev *hw, struct sbl_media_attr *attr)
+{
+	int err;
+
+	cxidev_dbg(&hw->cdev, "media config\n");
+
+	if (hw->port->hstate != CASS_HEADSHELL_STATUS_NOT_PRESENT) {
+		cxidev_dbg(&hw->cdev, "media config - bad state %s\n",
+			   cass_link_headshell_state_str(hw->port->hstate));
+		return -EUCLEAN;
+	}
+
+	if (hw->port->config_state & CASS_MEDIA_CONFIGURED) {
+		cxidev_dbg(&hw->cdev, "media config - media already configured\n");
+		return -EUCLEAN;
+	}
+
+	err = hw->link_ops->media_config(hw, attr);
+	if (err) {
+		cxidev_dbg(&hw->cdev, "media config - media config failed [%d]\n",
+			   err);
+		hw->port->config_state &= ~CASS_MEDIA_CONFIGURED;
+		return err;
+	}
+
+	hw->port->hstate = CASS_HEADSHELL_STATUS_NO_DEVICE;
+	hw->port->config_state |= CASS_MEDIA_CONFIGURED;
+
+	return 0;
+}
+
+/**
+ * cass_link_headshell_state_str() - Get a string for the headshell state
+ *
+ * Return a text string describing a headshell status
+ *
+ * @state: input enum of target headshell state
+ *
+ * Return: This function will always return a text string
+ */
+const char *cass_link_headshell_state_str(enum cass_headshell_status state)
+{
+	switch (state) {
+	case CASS_HEADSHELL_STATUS_UNKNOWN:     return "unknown";
+	case CASS_HEADSHELL_STATUS_PRESENT:     return "present";
+	case CASS_HEADSHELL_STATUS_NOT_PRESENT: return "not present";
+	case CASS_HEADSHELL_STATUS_NO_DEVICE:   return "no device";
+	case CASS_HEADSHELL_STATUS_ERROR:       return "error";
+	default:                                return "unrecognised";
+	}
+}
diff --git a/drivers/net/ethernet/hpe/ss1/cass_cable.h b/drivers/net/ethernet/hpe/ss1/cass_cable.h
new file mode 100644
index 000000000000..e43bdfcf236f
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_cable.h
@@ -0,0 +1,157 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2021 Hewlett Packard Enterprise Development LP */
+#ifndef _CASS_CABLE_H
+#define _CASS_CABLE_H
+
+#define QSFP_IDENTIFIER_OFFSET                   0
+#define QSFP_REV_CMPL_OFFSET                     1
+#define QSFP_VENDOR_MAX_STR_LEN                  16
+
+#define QDD_VENDOR_TE                   "TE Connectivity"
+#define QDD_VENDOR_HISENSE              "Hisense"
+#define QDD_VENDOR_FIT                  "FIT HON TENG"
+#define QDD_VENDOR_FT                   "FT HON TENG"
+#define QDD_VENDOR_MELLANOX             "Mellanox"
+#define QDD_VENDOR_MOLEX                "Molex"
+#define QDD_VENDOR_LEONI                "LEONI"
+#define QDD_VENDOR_HITACHI              "Hitachi Metals"
+#define QDD_VENDOR_LUXSHARE             "LUXSHARE-ICT"
+#define QDD_VENDOR_DUST_PHOTONICS       "DustPhotonics"
+#define QDD_VENDOR_FINISAR              "FINISAR CORP"
+#define QDD_VENDOR_HPE                  "HPE"
+#define QDD_VENDOR_CLOUD_LIGHT          "Cloud Light"
+#define QDD_VENDOR_AMPHENOL             "Amphenol"
+
+// SFF-8024 Specification for SFF Cross Reference -----------------------------
+#define SFF8436_MEDIA_TYPE_OFFSET                147
+#define SFF8436_LINK_LEN_OFFSET                  146
+#define SFF8436_VENDOR_OFFSET                    148
+#define SFF8436_EXT_IDENTIFIER_OFFSET            129
+#define SFF8436_POWER_DATA_OFFSET                93
+#define SFF8436_LOW_POWER_MASK                   0x02
+
+// SFF-8024 TABLE 4-1 IDENTIFIER VALUES
+#define SFF8024_TYPE_UNKNOWN                     0x00
+#define SFF8024_TYPE_GBIC                        0x01
+#define SFF8024_TYPE_MOTHERBOARD                 0x02
+#define SFF8024_TYPE_SFP                         0x03
+#define SFF8024_TYPE_300P_XBI                    0x04
+#define SFF8024_TYPE_XENPAK                      0x05
+#define SFF8024_TYPE_XFP                         0x06
+#define SFF8024_TYPE_XFF                         0x07
+#define SFF8024_TYPE_XFP_E                       0x08
+#define SFF8024_TYPE_XPAK                        0x09
+#define SFF8024_TYPE_X2                          0x0A
+#define SFF8024_TYPE_DWDM_SFP                    0x0B
+#define SFF8024_TYPE_QSFP_INF8438                0x0C
+#define SFF8024_TYPE_QSFP_PLUS                   0x0D
+#define SFF8024_TYPE_CXP                         0x0E
+#define SFF8024_TYPE_SMMHD4X                     0x0F
+#define SFF8024_TYPE_SMMHD8X                     0x10
+#define SFF8024_TYPE_QSFP28                      0x11
+#define SFF8024_TYPE_CXP2                        0x12
+#define SFF8024_TYPE_CDFP                        0x13
+#define SFF8024_TYPE_SMMHD4X_FANOUT              0x14
+#define SFF8024_TYPE_SMMHD8X_FANOUT              0x15
+#define SFF8024_TYPE_CDFP_3                      0x16
+#define SFF8024_TYPE_uQSFP                       0x17
+#define SFF8024_TYPE_QSFPDD                      0x18
+#define SFF8024_TYPE_OSFP8X                      0x19
+#define SFF8024_TYPE_SFPDD                       0x1A
+#define SFF8024_TYPE_DSFP                        0x1B
+#define SFF8024_TYPE_MINILINK4X                  0x1C
+#define SFF8024_TYPE_MINILINK8X                  0x1D
+#define SFF8024_TYPE_QSFP_PLUS_CMIS              0x1E
+
+// SFF-8636 Byte @ 93
+#define SFF8636_SW_RESET                         0x80
+#define SFF8636_PWR_CLASS_8_ENABLE               0x08
+#define SFF8636_PWR_CLASS_567_ENABLE             0x04
+#define SFF8636_PWR_CLASS_LOW                    0x02
+#define SFF8636_PWR_OVERRIDE                     0x01
+
+// SFF-8636 Extended Identifier Byte @ Page 00h byte 129
+#define SFF8636_PWR_CLASS_1234_MASK              0xC0
+#define SFF8636_PWR_CLASS_1                      0x00
+#define SFF8636_PWR_CLASS_2                      0x40
+#define SFF8636_PWR_CLASS_3                      0x80
+#define SFF8636_PWR_CLASS_4_AND_UP               0xC0
+#define SFF8636_PWR_CLASS_8                      0x20
+#define SFF8636_CLEI_IN_PG02                     0x10
+#define SFF8636_CDR_IN_TX                        0x08
+#define SFF8636_CDR_IN_RX                        0x04
+#define SFF8636_PWR_CLASS_567_MASK               0x03
+#define SFF8636_SEE_PWR_CLASS_1234               0x00
+#define SFF8636_PWR_CLASS_5                      0x01
+#define SFF8636_PWR_CLASS_6                      0x02
+#define SFF8636_PWR_CLASS_7                      0x03
+
+// Common Management Interface Specification (CMIS) ---------------------------
+#define CMIS_MEDIA_TYPE_OFFSET                   212
+#define CMIS_CABLE_LEN_OFFSET                    202
+#define CMIS_VENDOR_OFFSET                       129
+
+// CMIS and SFF-8636 Media/Transmitter Technology Types
+#define MEDIA_850_NM_VCSEL                       0x00
+#define MEDIA_1310_NM_VCSEL                      0x01
+#define MEDIA_1550_NM_VCSEL                      0x02
+#define MEDIA_1310_NM_FP                         0x03
+#define MEDIA_1310_NM_DFB                        0x04
+#define MEDIA_1550_NM_DFB                        0x05
+#define MEDIA_1310_NM_EML                        0x06
+#define MEDIA_1550_NM_EML                        0x07
+#define MEDIA_OTHERS                             0x08
+#define MEDIA_1490_NM_DFB                        0x09
+#define MEDIA_COPPER_UNEQ                        0x0A
+#define MEDIA_COPPER_PASSIVE_EQ                  0x0B
+#define MEDIA_COPPER_NEAR_FAR_LMT_ACT_EQ         0x0C
+#define MEDIA_COPPER_FAR_LMT_ACT_EQ              0x0D
+#define MEDIA_COPPER_NEAR_LMT_ACT_EQ             0x0E
+#define MEDIA_COPPER_LIN_ACT_EQ                  0x0F
+
+/**
+ * enum qsfp_format - cable spec types
+ *
+ * @QDD_FMT_UNKNOWN:       Format unknown
+ * @QDD_SFF8636:           Format compatible with SFF-8636
+ * @QDD_CMIS:              Format compatible with CMIS
+ *
+ * QSFP / QSFP-DD Protocol/Specification Types
+ */
+enum qsfp_format {
+	QDD_FMT_UNKNOWN = 0,
+	QDD_SFF8636,
+	QDD_CMIS,
+};
+
+/**
+ * enum cass_headshell_status - cable status
+ *
+ * @CASS_HEADSHELL_STATUS_UNKNOWN:       State unknown
+ * @CASS_HEADSHELL_STATUS_PRESENT:       A headshell is inserted
+ * @CASS_HEADSHELL_STATUS_NOT_PRESENT:   A headshell is not inserted
+ * @CASS_HEADSHELL_STATUS_ERROR:         A headshell has error
+ * @CASS_HEADSHELL_STATUS_NO_DEVICE:     No headshell hardware device
+ *
+ * The status of the media headshell
+ */
+enum cass_headshell_status {
+	CASS_HEADSHELL_STATUS_UNKNOWN          = 0,
+	CASS_HEADSHELL_STATUS_PRESENT          = 1 << 0,
+	CASS_HEADSHELL_STATUS_NOT_PRESENT      = 1 << 1,
+	CASS_HEADSHELL_STATUS_ERROR            = 1 << 2,
+	CASS_HEADSHELL_STATUS_NO_DEVICE        = 1 << 3,
+};
+
+int cass_is_cable_present(struct cass_dev *hw);
+int cass_headshell_power_up(struct cass_dev *hw, u8 qsfp_format);
+int cass_parse_heashell_data(struct cass_dev *hw, struct sbl_media_attr *attr,
+			     u8 *qsfp_format);
+int cass_link_headshell_insert(struct cass_dev *hw,
+			       struct sbl_media_attr *mattr);
+int cass_link_headshell_remove(struct cass_dev *hw);
+int cass_link_headshell_error(struct cass_dev *hw);
+int cass_link_media_config(struct cass_dev *hw, struct sbl_media_attr *attr);
+const char *cass_link_headshell_state_str(enum cass_headshell_status state);
+
+#endif	/* _CASS_CABLE_H */
diff --git a/drivers/net/ethernet/hpe/ss1/cass_core.c b/drivers/net/ethernet/hpe/ss1/cass_core.c
new file mode 100644
index 000000000000..45e992379e12
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_core.c
@@ -0,0 +1,1564 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2020-2026 Hewlett Packard Enterprise Development LP */
+
+/* Cassini device handler */
+
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include <linux/types.h>
+#include <linux/iopoll.h>
+#include <linux/seq_file.h>
+#include <linux/phy/phy.h>
+#include <linux/if_vlan.h>
+#include <linux/aer.h>
+#include <linux/hpe/cxi/driver.h>
+
+#include "cass_core.h"
+#include "cass_sbl.h"
+#include <linux/hpe/sbl/sbl.h>
+#include "cass_ss1_debugfs.h"
+#include "cxi_aux_dev.h"
+
+/* Range of available number of IRQs, depending on the number of VFs
+ * configured in Cassini.
+ */
+#define MIN_NUM_IRQS 63
+#define MAX_NUM_IRQS 2048
+
+static unsigned int sct_pid_mask = 0x7;
+module_param(sct_pid_mask, uint, 0444);
+MODULE_PARM_DESC(sct_pid_mask, "Source Connection PID Mask");
+
+static unsigned int hw_rev_override;
+module_param(hw_rev_override, uint, 0644);
+MODULE_PARM_DESC(hw_rev_override, "Hardware revision override");
+
+static bool enable_fgfc = true;
+module_param(enable_fgfc, bool, 0444);
+MODULE_PARM_DESC(enable_fgfc, "Enable/disable fine grain flow control");
+
+#define OUTSTANDING_LIMIT_MAX 2047U
+#define OUTSTANDING_LIMIT_MIN 1U
+#define OUTSTANDING_LIMIT_DEFAULT 64U
+
+static unsigned int get_pkt_limit;
+module_param(get_pkt_limit, uint, 0444);
+MODULE_PARM_DESC(get_pkt_limit,
+		 "Maximum number of outstanding GET packets (1-2047) per MCU");
+
+static unsigned int put_pkt_limit;
+module_param(put_pkt_limit, uint, 0444);
+MODULE_PARM_DESC(put_pkt_limit,
+		 "Maximum number of outstanding PUT packets (1-2047) per MCU");
+
+static unsigned int ioi_ord_limit;
+module_param(ioi_ord_limit, uint, 0444);
+MODULE_PARM_DESC(ioi_ord_limit,
+		 "Maximum number of outstanding ordered packets (1-2047) per MCU");
+
+static unsigned int ioi_unord_limit;
+module_param(ioi_unord_limit, uint, 0444);
+MODULE_PARM_DESC(ioi_unord_limit,
+		 "Maximum number of outstanding unordered packets (1-2047) per MCU");
+
+static bool ioi_enable = true;
+module_param(ioi_enable, bool, 0444);
+MODULE_PARM_DESC(ioi_enable,
+		 "Enable the In-Out-In protocol for puts.");
+
+bool disable_on_error = true;
+module_param(disable_on_error, bool, 0644);
+MODULE_PARM_DESC(disable_on_error,
+		 "Disable cxi device on certain unrecoverable errors");
+
+#ifndef PCI_EXT_CAP_ID_DVSEC
+#define PCI_EXT_CAP_ID_DVSEC 0x23
+#define PCI_DVSEC_HEADER1       0x4 /* Designated Vendor-Specific Header1 */
+#endif
+#ifndef PCI_DVSEC_HEADER1_VID
+#define PCI_DVSEC_HEADER1_VID(x)   ((x) & 0xffff)
+#define PCI_DVSEC_HEADER1_REV(x)   (((x) >> 16) & 0xf)
+#define PCI_DVSEC_HEADER1_LEN(x)   (((x) >> 20) & 0xfff)
+#endif
+
+static void cass_dev_release(struct device *dev)
+{
+	struct cass_dev *hw = container_of(dev, struct cass_dev, class_dev);
+
+	kfree(hw);
+}
+
+/**
+ * cxi_get_csrs_range() - Return the whole physical range of the CSRs
+ *
+ * The BAR0 contains amongst other things the CSRs. At least the retry
+ * handler needs an access to them. The CXI user module needs to mmap
+ * it.
+ *
+ * @cdev: the device
+ * @base: base address
+ * @len: length of the CSRs
+ */
+void cxi_get_csrs_range(struct cxi_dev *cdev, phys_addr_t *base, size_t *len)
+{
+	struct cass_dev *hw = container_of(cdev, struct
+					   cass_dev, cdev);
+
+	*base = hw->regs_base + C_MEMORG_CSR;
+	*len = C_MEMORG_CSR_SIZE;
+
+}
+EXPORT_SYMBOL(cxi_get_csrs_range);
+
+void traffic_shaping_cfg(struct cass_dev *hw)
+{
+	static const union c_oxe_cfg_arb_config arb_config = {
+		.mfs_out_sel = 1,
+		.fill_rate = 9,
+	};
+	const union c_oxe_cfg_arb_head_out_c head_out_c = {
+		.enable = 1,
+		.fill_qty = hw->tsc_fill_qty,
+		.limit = DIV_ROUND_UP(8 * ETHERNET_MAX_FRAME_SIZE, 1024),
+	};
+	const union c_oxe_cfg_arb_head_in_c head_in_c = {
+		.enable = 1,
+		.fill_qty = hw->tsc_fill_qty,
+		.limit = DIV_ROUND_UP(8 * ETHERNET_MAX_FRAME_SIZE, 1024),
+	};
+
+	/* 16 traffic shaping credits are returned at 100MHz frequency 200 Gbps
+	 * performance.
+	 */
+	cass_write(hw, C_OXE_CFG_ARB_CONFIG, &arb_config, sizeof(arb_config));
+	cass_write(hw, C_OXE_CFG_ARB_HEAD_OUT_C, &head_out_c,
+		   sizeof(head_out_c));
+	cass_write(hw, C_OXE_CFG_ARB_HEAD_IN_C, &head_in_c, sizeof(head_in_c));
+}
+
+/* Set the number of packets inflight based on link speed.
+ */
+static unsigned int calculate_packets_inflight(struct cass_dev *hw)
+{
+	unsigned int value;
+	struct cxi_link_info link_info;
+	bool is_link_up;
+
+	is_link_up = cass_sbl_is_link_up(hw);
+	if (!is_link_up) {
+		pr_err("cxi link info error: link is not up yet.\n");
+		return 0;
+	}
+	cxi_link_mode_get(&hw->cdev, &link_info);
+
+	if (link_info.speed == SPEED_400000)
+		value = CASS2_MAX_PACKETS_INFLIGHT;
+	else
+		value = CASS1_MAX_PACKETS_INFLIGHT;
+
+	return value;
+}
+
+/* Set outstanding limits based on kernel module parameters.
+ * If no input, use the calculated packets_inflight.
+ */
+void cass_set_outstanding_limit(struct cass_dev *hw)
+{
+	int i;
+	unsigned int packets_inflight;
+	union c_oxe_cfg_outstanding_limit outstanding_limit;
+
+	packets_inflight = calculate_packets_inflight(hw);
+
+	if (packets_inflight < OUTSTANDING_LIMIT_MIN ||
+	    packets_inflight > OUTSTANDING_LIMIT_MAX) {
+		packets_inflight = OUTSTANDING_LIMIT_DEFAULT;
+	}
+
+	if (get_pkt_limit == 0)
+		get_pkt_limit = packets_inflight;
+	if (get_pkt_limit < OUTSTANDING_LIMIT_MIN ||
+	    get_pkt_limit > OUTSTANDING_LIMIT_MAX) {
+		pr_err("Invalid get_pkt_limit %u. Setting to %u\n",
+		       get_pkt_limit, OUTSTANDING_LIMIT_DEFAULT);
+		get_pkt_limit = OUTSTANDING_LIMIT_DEFAULT;
+	}
+
+	if (put_pkt_limit == 0)
+		put_pkt_limit = packets_inflight;
+	if (put_pkt_limit < OUTSTANDING_LIMIT_MIN ||
+	    put_pkt_limit > OUTSTANDING_LIMIT_MAX) {
+		pr_err("Invalid put_pkt_limit %u. Setting to %u\n",
+		       put_pkt_limit, OUTSTANDING_LIMIT_DEFAULT);
+		put_pkt_limit = OUTSTANDING_LIMIT_DEFAULT;
+	}
+
+	if (ioi_ord_limit == 0)
+		ioi_ord_limit = packets_inflight;
+	if (ioi_ord_limit < OUTSTANDING_LIMIT_MIN ||
+	    ioi_ord_limit > OUTSTANDING_LIMIT_MAX) {
+		pr_err("Invalid ioi_ord_limit %u. Setting to %u\n",
+		       ioi_ord_limit, OUTSTANDING_LIMIT_DEFAULT);
+		ioi_ord_limit = OUTSTANDING_LIMIT_DEFAULT;
+	}
+
+	if (ioi_unord_limit == 0)
+		ioi_unord_limit = packets_inflight;
+	if (ioi_unord_limit < OUTSTANDING_LIMIT_MIN ||
+	    ioi_unord_limit > OUTSTANDING_LIMIT_MAX) {
+		pr_err("Invalid ioi_unord_limit %u. Setting to %u\n",
+		       ioi_unord_limit, OUTSTANDING_LIMIT_DEFAULT);
+		ioi_unord_limit = OUTSTANDING_LIMIT_DEFAULT;
+	}
+
+	for (i = 0; i < C_OXE_CFG_OUTSTANDING_LIMIT_ENTRIES; i++) {
+		cass_read(hw, C_OXE_CFG_OUTSTANDING_LIMIT(i),
+			  &outstanding_limit, sizeof(outstanding_limit));
+		outstanding_limit.get_limit = get_pkt_limit;
+		outstanding_limit.put_limit = put_pkt_limit;
+		outstanding_limit.ioi_ord_limit = ioi_ord_limit;
+		outstanding_limit.ioi_unord_limit = ioi_unord_limit;
+		cass_write(hw, C_OXE_CFG_OUTSTANDING_LIMIT(i),
+			   &outstanding_limit, sizeof(outstanding_limit));
+	}
+}
+
+/* Initialize OXE registers. */
+static void cass_oxe_init(struct cass_dev *hw)
+{
+	int i;
+	union c_oxe_cfg_common cfg_common;
+	union c_oxe_cfg_fgfc fgfc;
+	static const union c_oxe_cfg_arb_drr_out wdrr_out = {
+		.quanta_val0 = DIV_ROUND_UP(PORTALS_MAX_FRAME_SIZE, 32),
+		.quanta_val1 = DIV_ROUND_UP(ETHERNET_MAX_FRAME_SIZE, 32),
+	};
+	static const union c_oxe_cfg_arb_drr_in wdrr_in = {
+		.quanta_val0 = DIV_ROUND_UP(PORTALS_MAX_FRAME_SIZE, 32),
+	};
+	static const union c_oxe_cfg_arb_mfs_out mfs_out = {
+		.mfs0 = DIV_ROUND_UP(PORTALS_MAX_FRAME_SIZE, 32),
+		.mfs1 = DIV_ROUND_UP(ETHERNET_MAX_FRAME_SIZE, 32),
+	};
+	static const union c_oxe_cfg_arb_mfs_in mfs_in = {
+		.mfs0 = DIV_ROUND_UP(PORTALS_MAX_FRAME_SIZE, 32),
+	};
+	static const union c_oxe_cfg_mcu_priority_limit mcu_priority_limit = {
+		.occ_climit = 8,
+		.occ_blimit = 4,
+	};
+	static const union c_oxe_cfg_fgfc_cnt fgfc_cnt = {
+		.vni_mask = 0xffff,
+	};
+	union c_oxe_cfg_fab_param fab_param;
+
+	/* Note: All MCUs must use quanta and mfs value zero. */
+	cass_write(hw, C_OXE_CFG_ARB_DRR_OUT, &wdrr_out, sizeof(wdrr_out));
+	cass_write(hw, C_OXE_CFG_ARB_DRR_IN, &wdrr_in, sizeof(wdrr_in));
+	cass_write(hw, C_OXE_CFG_ARB_MFS_OUT, &mfs_out, sizeof(mfs_out));
+	cass_write(hw, C_OXE_CFG_ARB_MFS_IN, &mfs_in, sizeof(mfs_in));
+
+	traffic_shaping_cfg(hw);
+
+	/* Clear all default reserved buffer class values. */
+	cass_clear(hw, C_OXE_CFG_PCT_BC_CDT(0), C_OXE_CFG_PCT_BC_CDT_SIZE);
+	cass_clear(hw, C_OXE_CFG_BUF_BC_PARAM(0), C_OXE_CFG_BUF_BC_PARAM_SIZE);
+
+	/* Lower MCU arbitration priority limits to prevent a single MCU
+	 * starving other MCUs within a traffic class.
+	 */
+	for (i = 0; i < C_OXE_CFG_MCU_PRIORITY_LIMIT_ENTRIES; i++)
+		cass_write(hw, C_OXE_CFG_MCU_PRIORITY_LIMIT(i),
+			   &mcu_priority_limit, sizeof(mcu_priority_limit));
+
+	for (i = 0; i < C_OXE_CFG_FGFC_CNT_ENTRIES; i++)
+		cass_write(hw, C_OXE_CFG_FGFC_CNT(i), &fgfc_cnt,
+			   sizeof(fgfc_cnt));
+
+	cass_read(hw, C_OXE_CFG_FAB_PARAM, &fab_param, sizeof(fab_param));
+	fab_param.req_32b_enabled = 0;
+	fab_param.rsp_32b_enabled = 0;
+	cass_write(hw, C_OXE_CFG_FAB_PARAM, &fab_param, sizeof(fab_param));
+
+	/* Disable In-Out-In for C1 and Mix system */
+	if (system_type_identifier == CASSINI_1_ONLY ||
+	    system_type_identifier == CASSINI_MIX) {
+		ioi_enable = false;
+	}
+	cass_read(hw, C_OXE_CFG_COMMON, &cfg_common,
+		  sizeof(cfg_common));
+	cfg_common.ioi_enable = ioi_enable;
+	cass_write(hw, C_OXE_CFG_COMMON, &cfg_common,
+		   sizeof(cfg_common));
+
+	cass_read(hw, C_OXE_CFG_FGFC, &fgfc, sizeof(fgfc));
+	fgfc.enable = enable_fgfc;
+	cass_write(hw, C_OXE_CFG_FGFC, &fgfc, sizeof(fgfc));
+}
+
+#define DFA_NID_MASK 0xfffff000U
+
+/* TODO: Allow multiple request and response PCP configurations. Currently only
+ * request PCP 0 and response PCP 1 configuration is used.
+ */
+static void cass_pct_init(struct cass_dev *hw)
+{
+	union c_pct_cfg_ixe_rsp_fifo_limits rsp_fifo_limits;
+	union c_pct_cfg_tgt_clr_req_fifo_limit req_fifo_limit;
+	u32 pid_mask = sct_pid_mask;
+	union c_cq_cfg_ocu_hash_mask hash_mask;
+	union c_pct_cfg_sct_tag_dfa_mask dfa_mask;
+	union c_pct_cfg_timing timing;
+	int i;
+
+	/* Errata 2848 */
+	cass_read(hw, C_PCT_CFG_TGT_CLR_REQ_FIFO_LIMIT,
+		  &req_fifo_limit, sizeof(req_fifo_limit));
+	req_fifo_limit.mst_dealloc_fifo_limit = 7;
+	cass_write(hw, C_PCT_CFG_TGT_CLR_REQ_FIFO_LIMIT,
+		   &req_fifo_limit, sizeof(req_fifo_limit));
+
+	cass_read(hw, C_PCT_CFG_IXE_RSP_FIFO_LIMITS,
+		  &rsp_fifo_limits, sizeof(rsp_fifo_limits));
+	rsp_fifo_limits.smt_cdt_ack_limit = 7;
+	rsp_fifo_limits.spt_cdt_ack_limit = 7;
+	rsp_fifo_limits.sct_cdt_ack_limit = 7;
+	cass_write(hw, C_PCT_CFG_IXE_RSP_FIFO_LIMITS,
+		   &rsp_fifo_limits, sizeof(rsp_fifo_limits));
+
+	/* Set default PCT timeouts */
+	cass_read(hw, C_PCT_CFG_TIMING, &timing, sizeof(timing));
+	timing.spt_timeout_epoch_sel = C1_DEFAULT_SPT_TIMEOUT_EPOCH;
+	timing.sct_idle_epoch_sel = C1_DEFAULT_SCT_IDLE_EPOCH;
+	timing.sct_close_epoch_sel = C1_DEFAULT_SCT_CLOSE_EPOCH;
+	timing.tct_timeout_epoch_sel = C1_DEFAULT_TCT_TIMEOUT_EPOCH;
+	cass_write(hw, C_PCT_CFG_TIMING, &timing, sizeof(timing));
+
+	/* Set SCT PID Mask. CQ and PCT DFA masks must be consistent. */
+	cass_read(hw, C_CQ_CFG_OCU_HASH_MASK, &hash_mask, sizeof(hash_mask));
+
+	/* Mask off PID granule space as a part of SCT mask selection. */
+	pid_mask &= BIT(pid_bits) - 1;
+
+	/* Software uses the top bit of the PID granule space to differentiate
+	 * between unrestricted puts and gets. To support having unrestricted
+	 * puts and gets on different SCTs, the top bit of the PID granule
+	 * space must always be included in SCT selection. This bit is the top
+	 * bit in the endpoint define.
+	 */
+	pid_mask |= BIT(C_DFA_ENDPOINT_DEFINED_BITS - 1);
+
+	hash_mask.dfa = DFA_NID_MASK | pid_mask;
+	cass_write(hw, C_CQ_CFG_OCU_HASH_MASK, &hash_mask, sizeof(hash_mask));
+
+	for (i = 0; i < 4; i++)
+		dfa_mask.dscp[i].dfa_mask = pid_mask;
+
+	for (i = 0; i < C_PCT_CFG_SCT_TAG_DFA_MASK_ENTRIES; i++) {
+		cass_write(hw, C_PCT_CFG_SCT_TAG_DFA_MASK(i), &dfa_mask,
+			   sizeof(dfa_mask));
+
+		if (cass_version(hw, CASSINI_2))
+			cass_write(hw, C2_LPE_CFG_GET_FQ_DFA_MASK(i),
+				   &dfa_mask, sizeof(dfa_mask));
+	}
+
+	/* Clear the default target resource settings. This is configured later
+	 * as a part of traffic class configuration.
+	 */
+	if (cass_version(hw, CASSINI_1)) {
+		cass_clear(hw, C1_PCT_CFG_TRS_TC_DED_LIMIT(0),
+			   C1_PCT_CFG_TRS_TC_DED_LIMIT_SIZE);
+		cass_clear(hw, C1_PCT_CFG_TRS_TC_MAX_LIMIT(0),
+			   C1_PCT_CFG_TRS_TC_MAX_LIMIT_SIZE);
+	} else {
+		cass_clear(hw, C2_PCT_CFG_TRS_TC_DED_LIMIT(0),
+			   C2_PCT_CFG_TRS_TC_DED_LIMIT_SIZE);
+		cass_clear(hw, C2_PCT_CFG_TRS_TC_MAX_LIMIT(0),
+			   C2_PCT_CFG_TRS_TC_MAX_LIMIT_SIZE);
+	}
+	cass_clear(hw, C_PCT_CFG_MST_TC_DED_LIMIT(0),
+		   C_PCT_CFG_MST_TC_DED_LIMIT_SIZE);
+	cass_clear(hw, C_PCT_CFG_MST_TC_MAX_LIMIT(0),
+		   C_PCT_CFG_MST_TC_MAX_LIMIT_SIZE);
+	cass_clear(hw, C_PCT_CFG_TCT_TC_DED_LIMIT(0),
+		   C_PCT_CFG_TCT_TC_DED_LIMIT_SIZE);
+	cass_clear(hw, C_PCT_CFG_TCT_TC_MAX_LIMIT(0),
+		   C_PCT_CFG_TCT_TC_MAX_LIMIT_SIZE);
+};
+
+/* Wait for the hardware to be ready after a reset. */
+static int wait_hw_ready(struct cass_dev *hw)
+{
+	void __iomem *csr = cass_csr(hw, C_RMU_STS_INIT_DONE);
+	union {
+		u64 value;
+		union c_atu_sts_init_done atu_sts_init_done;
+		union c_cq_sts_init_done cq_sts_init_done;
+		union c_lpe_sts_init_done lpe_sts_init_done;
+		union c_oxe_sts_common oxe_sts_common;
+		union c_rmu_sts_init_done rmu_sts_init_done;
+		union c_ee_sts_init_done ee_sts_init_done;
+	} x;
+	int rc;
+
+	csr = cass_csr(hw, C_ATU_STS_INIT_DONE);
+	rc = readq_poll_timeout(csr, x.value,
+				(x.atu_sts_init_done.anchor_init_done == 1 &&
+				 x.atu_sts_init_done.tag_init_done == 1 &&
+				 x.atu_sts_init_done.prb_init_done == 1),
+				1, 1000000);
+	if (rc)
+		return rc;
+
+	csr = cass_csr(hw, C_CQ_STS_INIT_DONE);
+	rc = readq_poll_timeout(csr, x.value,
+				(x.cq_sts_init_done.tou_init_done == 1 &&
+				 x.cq_sts_init_done.cq_init_done == 1),
+				1, 1000000);
+	if (rc)
+		return rc;
+
+	csr = cass_csr(hw, C_LPE_STS_INIT_DONE);
+	rc = readq_poll_timeout(csr, x.value,
+				(x.lpe_sts_init_done.free_mask_init_done == 0xf &&
+				 x.lpe_sts_init_done.ptlte_init_done == 1),
+				1, 1000000);
+	if (rc)
+		return rc;
+
+	csr = cass_csr(hw, C_OXE_STS_COMMON);
+	rc = readq_poll_timeout(csr, x.value,
+				(x.oxe_sts_common.init_done == 1),
+				1, 1000000);
+	if (rc)
+		return rc;
+
+	csr = cass_csr(hw, C_RMU_STS_INIT_DONE);
+	rc = readq_poll_timeout(csr, x.value,
+				(x.rmu_sts_init_done.warm_reset == 0 &&
+				 x.rmu_sts_init_done.init_done == 1),
+				1, 1000000);
+	if (rc)
+		return rc;
+
+	csr = cass_csr(hw, C_EE_STS_INIT_DONE);
+	rc = readq_poll_timeout(csr, x.value,
+				(x.ee_sts_init_done.warm_reset == 0 &&
+				 x.ee_sts_init_done.init_done == 1),
+				1, 1000000);
+	if (rc)
+		return rc;
+
+	return 0;
+}
+
+/* Program the device NID. */
+static void program_nid(struct cass_dev *hw, u32 nid)
+{
+	struct cxi_dev *cdev = &hw->cdev;
+	struct cxi_adev *cadev;
+	union c_oxe_cfg_fab_sfa cfg_fab_sfa = {};
+	union c_lpe_cfg_get_ctrl cfg_get_ctrl;
+	union c_ixe_cfg_dfa cfg_dfa = {};
+	union c_pct_cfg_pkt_misc cfg_pkt_misc;
+
+	cdev->prop.nid = nid;
+
+	cass_read(hw, C_PCT_CFG_PKT_MISC, &cfg_pkt_misc, sizeof(cfg_pkt_misc));
+	cfg_pkt_misc.sfa_nid = cdev->prop.nid;
+	cass_write(hw, C_PCT_CFG_PKT_MISC, &cfg_pkt_misc, sizeof(cfg_pkt_misc));
+
+	cfg_fab_sfa.nid = cdev->prop.nid;
+	cass_write(hw, C_OXE_CFG_FAB_SFA, &cfg_fab_sfa, sizeof(cfg_fab_sfa));
+
+	cass_read(hw, C_LPE_CFG_GET_CTRL, &cfg_get_ctrl, sizeof(cfg_get_ctrl));
+	cfg_get_ctrl.dfa_nid = cdev->prop.nid;
+	cass_write(hw, C_LPE_CFG_GET_CTRL, &cfg_get_ctrl, sizeof(cfg_get_ctrl));
+
+	cfg_dfa.dfa_chk_en = 0xFF;
+	cfg_dfa.dfa_nid = cdev->prop.nid;
+	cass_write(hw, C_IXE_CFG_DFA, &cfg_dfa, sizeof(cfg_dfa));
+
+	cxi_send_async_event(cdev, CXI_EVENT_NID_CHANGED);
+
+	/*
+	 * The auxiliary device is freed when it is removed, which clears
+	 * cxi_adev under this lock first. Hold the lock for the whole
+	 * notification so removal waits for it and cannot free the device
+	 * under it.
+	 */
+	mutex_lock(&hw->cxi_adev_lock);
+	cadev = hw->cxi_adev;
+	if (cadev)
+		blocking_notifier_call_chain(&cadev->nid_notifier, nid, cdev);
+	mutex_unlock(&hw->cxi_adev_lock);
+}
+
+void cxi_set_nid(struct cxi_dev *cdev, u32 nid)
+{
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+
+	/* The NID cannot be set from a VF */
+	if (!cdev->is_physfn)
+		return;
+
+	program_nid(hw, nid);
+	hw->cdev.prop.nid_configured = true;
+}
+EXPORT_SYMBOL(cxi_set_nid);
+
+void cxi_set_nid_from_mac(struct cxi_dev *cdev, const u8 *addr)
+{
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	u32 nid;
+
+	/* The NID cannot be set from a VF */
+	if (!cdev->is_physfn)
+		return;
+
+	/* If the NID has already been explicitly configured, do not override it. */
+	if (hw->cdev.prop.nid_configured)
+		return;
+
+	nid = ether_addr_to_u64(addr) & 0xFFFFFULL;
+	program_nid(hw, nid);
+	cxidev_warn(&hw->cdev,
+		    "NID has not been explicitly set. NID derived from MAC: 0x%x\n", nid);
+}
+EXPORT_SYMBOL(cxi_set_nid_from_mac);
+
+/* Determine the Cassini link speed. When CCIX Extended Speed Mode
+ * (ESM) is enabled, non-standard speeds exist.
+ */
+static int get_pcie_link_speed(struct cass_dev *hw)
+{
+	struct pci_dev *pdev = hw->cdev.pdev;
+	enum pci_bus_speed speed;
+	u32 val;
+	int pos;
+	int rc;
+
+	/* Get the regular PCIe speed first */
+	speed = pcie_get_speed_cap(pdev);
+	switch (speed) {
+	case PCIE_SPEED_2_5GT:
+	case PCIE_SPEED_5_0GT:
+	case PCIE_SPEED_8_0GT:
+	case PCIE_SPEED_16_0GT:
+	case PCIE_SPEED_32_0GT:
+		hw->pcie_link_speed = speed;
+		break;
+
+	default:
+		hw->pcie_link_speed = CASS_SPEED_UNKNOWN;
+		break;
+	}
+
+	/* ESM is only present on first generation Cassini hardware. */
+	if (cass_version(hw, CASSINI_2))
+		return 0;
+
+	pos = 0;
+	while ((pos = pci_find_next_ext_capability(pdev, pos,
+						   PCI_EXT_CAP_ID_DVSEC))) {
+		pci_read_config_dword(pdev, pos + PCI_DVSEC_HEADER1, &val);
+		if (PCI_DVSEC_HEADER1_VID(val) == 0x0001 &&
+		    PCI_DVSEC_HEADER1_REV(val) == 0x1 &&
+		    PCI_DVSEC_HEADER1_LEN(val) == 0x040)
+			break;
+	}
+	if (pos == 0) {
+		/* The header is not present when using PCIe
+		 * passthrough with the vfio-pci driver.
+		 */
+		cxidev_warn(&hw->cdev, "Cannot find the PCIe DVSEC header\n");
+		return 0;
+	}
+
+	/* ESM control register */
+	rc = pci_read_config_dword(pdev, pos + 0x18, &val);
+	if (rc) {
+		cxidev_err(&hw->cdev, "Cannot get ESM status\n");
+		return -EIO;
+	}
+	hw->esm_active = !!(val & BIT(15));
+
+	if (!hw->esm_active)
+		return 0;
+
+	/* ESM PCIe link speed, from the ESM status register */
+	rc = pci_read_config_dword(pdev, pos + 0x14, &val);
+	if (rc) {
+		cxidev_err(&hw->cdev, "Cannot get PCIe link speed\n");
+		return -EIO;
+	}
+
+	switch (val & 0x7f) {
+	case 0x1:
+		hw->pcie_link_speed = PCIE_SPEED_2_5GT;
+		break;
+	case 0x2:
+		hw->pcie_link_speed = PCIE_SPEED_5_0GT;
+		break;
+	case 0x3:
+		hw->pcie_link_speed = PCIE_SPEED_8_0GT;
+		break;
+	case 0x6:
+		hw->pcie_link_speed = PCIE_SPEED_16_0GT;
+		break;
+	case 0xa:
+		hw->pcie_link_speed = CASS_SPEED_20_0GT;
+		break;
+	case 0xf:
+		hw->pcie_link_speed = CASS_SPEED_25_0GT;
+		break;
+	default:
+		hw->pcie_link_speed = CASS_SPEED_UNKNOWN;
+		break;
+	}
+
+	return 0;
+}
+
+static const unsigned int cfg_crnc_csr[] = {
+	C_ATU_CFG_CRNC,
+	C_CQ_CFG_CRNC,
+	C_EE_CFG_CRNC,
+	C_HNI_CFG_CRNC,
+	C_HNI_PML_CFG_CRNC,
+	C_IXE_CFG_CRNC,
+	C_LPE_CFG_CRNC,
+	C_MB_CFG_CRNC,
+	C_MST_CFG_CRNC,
+	C_OXE_CFG_CRNC,
+	C_PARBS_CFG_CRNC,
+	C_PCT_CFG_CRNC,
+	C_PI_CFG_CRNC,
+	C_PI_IPD_CFG_CRNC,
+	C_RMU_CFG_CRNC,
+};
+
+/* Initializes the hardware. */
+static int init_hw(struct cass_dev *hw)
+{
+	int ret;
+	int i;
+	u64 do_dump = 0;
+	union c_lpe_cfg_min_free_shft lpe_cfg_min_free_shift = {
+		.min_free_shft = min_free_shift,
+	};
+	static const union c_mb_cfg_crmc cfg_crmc = {
+		.ring_timeout = 0xff,
+		.rd_addr_invalid_decerr_disable = 1,
+	};
+	static const union c_mb_cfg_misc cfg_mask = {
+		.nic_warm_rst0 = 1,
+		.nic_warm_rst1 = 1,
+		.nic_warm_rst2 = 1,
+		.nic_warm_rst3 = 1,
+		.nic_warm_rst4 = 1,
+		.nic_warm_rst5 = 1,
+		.nic_warm_rst6 = 1,
+		.nic_warm_rst7 = 1,
+		.nic_warm_rst8 = 1,
+		.nic_warm_rst9 = 1,
+	};
+	union c_mb_cfg_misc cfg;
+
+	/* Trigger a warm reset of the hardware - Only the bits common
+	 * to Cassini 1 & 2 are used here.
+	 */
+	cass_read(hw, C_MB_CFG_MISC, &cfg, sizeof(cfg));
+	cfg.qw |= cfg_mask.qw;
+	cass_write(hw, C_MB_CFG_MISC, &cfg, sizeof(cfg));
+
+	/* This CSR must be cleared while warm reset is asserted. */
+	cass_clear(hw, C_EE_DBG_LM_CB_TO_EQ_MAP(0), C_EE_DBG_LM_CB_TO_EQ_MAP_SIZE);
+
+	/* De-assert warm reset */
+	cfg.qw &= ~cfg_mask.qw;
+	cass_write(hw, C_MB_CFG_MISC, &cfg, sizeof(cfg));
+
+	cass_flush_pci(hw);
+
+	if (wait_hw_ready(hw)) {
+		cxidev_err(&hw->cdev, "chip not ready\n");
+		return -ENOTSUPP;
+	}
+
+	cass_init(hw);
+
+	/* Fake hardware initialization */
+	if (HW_PLATFORM_NETSIM(hw))
+		cass_write(hw, NICSIM_CONFIG_DUMP, &do_dump, sizeof(do_dump));
+
+	for (i = 0; i < C_MB_CFG_CRMC_ENTRIES; i++)
+		cass_write(hw, C_MB_CFG_CRMC(i), &cfg_crmc, sizeof(cfg_crmc));
+
+	for (i = 0; i < ARRAY_SIZE(cfg_crnc_csr); i++) {
+		static const union c_atu_cfg_crnc cfg_crnc = {
+			.csr_timeout = 0xfd,
+		};
+
+		/* Use c_atu_cfg_crnc as it's the same structure for
+		 * all CSRs
+		 */
+		cass_write(hw, cfg_crnc_csr[i], &cfg_crnc, sizeof(cfg_crnc));
+	}
+
+	cass_write(hw, C_LPE_CFG_MIN_FREE_SHFT, &lpe_cfg_min_free_shift,
+		   sizeof(lpe_cfg_min_free_shift));
+
+	if (cass_version(hw, CASSINI_2)) {
+		union c2_lpe_cfg_match_sel cfg_match_sel = {
+			.vni_cfg = vni_matching,
+		};
+
+		hw->cdev.prop.vni_matching = vni_matching;
+		cass_write(hw, C2_LPE_CFG_MATCH_SEL, &cfg_match_sel,
+			   sizeof(cfg_match_sel));
+	}
+
+	ret = cass_dmac_init(hw);
+	if (ret)
+		goto __init_hw_err_0;
+
+	ret = cass_telem_init(hw);
+	if (ret)
+		goto __init_hw_err_1;
+
+	cass_pct_init(hw);
+	cass_hni_init(hw);
+	cass_tle_init(hw);
+	cass_cq_init(hw);
+	cass_oxe_init(hw);
+
+	ret = cass_ixe_init(hw);
+	if (ret)
+		goto __init_hw_err_2;
+
+	cass_pte_init(hw);
+	ret = cass_atu_init(hw);
+	if (ret)
+		goto __init_hw_err_2;
+
+	cass_ee_init(hw);
+	ret = cass_tc_init(hw);
+	if (ret)
+		goto __init_hw_err_3;
+
+	cxi_dev_init_eth_tx_profile(hw);
+
+	return 0;
+
+__init_hw_err_3:
+	cass_atu_fini(hw);
+
+__init_hw_err_2:
+	cass_hni_fini(hw);
+	cass_telem_fini(hw);
+
+__init_hw_err_1:
+	cass_dmac_fini(hw);
+
+__init_hw_err_0:
+	return ret;
+}
+
+static void fini_hw(struct cass_dev *hw)
+{
+	cxi_eth_tx_profile_cleanup(hw);
+	cass_tc_fini(hw);
+	cass_atu_fini(hw);
+	cass_ixe_fini(hw);
+	cass_hni_fini(hw);
+	cass_telem_fini(hw);
+	cass_dmac_fini(hw);
+}
+
+/* Check whether the hardware is supported, and set the version. */
+static int is_supported(struct cass_dev *hw)
+{
+	cass_read(hw, C_MB_STS_REV, &hw->rev, sizeof(hw->rev));
+
+	if (!HW_PLATFORM_ASIC(hw) && !HW_PLATFORM_Z1(hw) &&
+	    !HW_PLATFORM_NETSIM(hw)) {
+		cxidev_err(&hw->cdev, "device %x/%x/%x/%x/%x is not supported\n",
+			   hw->rev.vendor_id, hw->rev.device_id,
+			   hw->rev.platform, hw->rev.proto, hw->rev.rev);
+		return -ENOTSUPP;
+	}
+
+	if (hw->rev.vendor_id == PCI_VENDOR_ID_CRAY &&
+	    hw->rev.device_id == PCI_DEVICE_ID_CASSINI_1) {
+		if (hw->rev.rev == 1)
+			hw->cdev.prop.cassini_version = CASSINI_1_0;
+		else if (hw->rev.rev == 2)
+			hw->cdev.prop.cassini_version = CASSINI_1_1;
+		else
+			goto unsupported;
+	} else if (hw->rev.vendor_id == PCI_VENDOR_ID_HPE &&
+		   (hw->rev.device_id == PCI_DEVICE_ID_CASSINI_2_PF ||
+		    hw->rev.device_id == PCI_DEVICE_ID_CASSINI_2_VF)) {
+		if (hw->rev.rev == 1)
+			hw->cdev.prop.cassini_version = CASSINI_2_0;
+		else
+			goto unsupported;
+	}
+
+	if (hw_rev_override) {
+		if (hw_rev_override != CASSINI_1_0 &&
+		    hw_rev_override != CASSINI_1_1 &&
+		    hw_rev_override != CASSINI_2_0)
+			goto unsupported;
+
+		hw->cdev.prop.cassini_version = hw_rev_override;
+	}
+
+	if (cass_version(hw, CASSINI_2) && HW_PLATFORM_Z1(hw) &&
+	    (hw->rev.proto & 0x001) == 1) {
+		cxidev_info(&hw->cdev, "device has reduced PCT tables\n");
+		hw->reduced_pct_tables = true;
+	}
+
+	return 0;
+
+unsupported:
+	cxidev_err(&hw->cdev, "device %x/%x/%x/%x/%x is not supported\n",
+		   hw->rev.vendor_id, hw->rev.device_id,
+		   hw->rev.platform, hw->rev.proto, hw->rev.rev);
+	return -ENOTSUPP;
+}
+
+static int cass_link_fini_once(struct cass_dev *hw, bool *link_started)
+{
+	int rtn;
+
+	if (!*link_started)
+		return 0;
+
+	rtn = hw->link_ops->link_fini(hw);
+	if (!rtn)
+		*link_started = false;
+
+	return rtn;
+}
+
+static int cass_probe(struct pci_dev *pdev, const struct pci_device_id *id)
+{
+	int i;
+	int rc = 0;
+	struct cass_dev *hw;
+	bool is_physfn;
+	bool link_started = false;
+	bool class_dev_initialized = false;
+	int pos;
+
+	hw = kzalloc(sizeof(*hw), GFP_KERNEL);
+	if (!hw)
+		return -ENOMEM;
+
+	pci_set_drvdata(pdev, hw);
+	hw->cdev.pdev = pdev;
+	INIT_LIST_HEAD(&hw->lni_list);
+	spin_lock_init(&hw->lni_lock);
+	refcount_set(&hw->refcount, 1);
+
+	atomic_set(&hw->stats.lni, 0);
+
+	/* Initializes the RMU domains */
+	atomic_set(&hw->stats.domain, 0);
+	ida_init(&hw->rmu_index_table);
+	ida_init(&hw->domain_table);
+	spin_lock_init(&hw->domain_lock);
+	spin_lock_init(&hw->pid_pool_lock);
+	spin_lock_init(&hw->rmu_lock);
+
+	/* Initialize the EQs */
+	atomic_set(&hw->stats.eq, 0);
+	ida_init(&hw->eq_index_table);
+	spin_lock_init(&hw->eq_shadow_lock);
+	mutex_init(&hw->init_eq_hw_state);
+
+	/* Initialize the communication profiles. */
+	ida_init(&hw->cp_table);
+	mutex_init(&hw->cp_lock);
+
+	/* Initialize the transmit and target CQs. */
+	atomic_set(&hw->stats.txq, 0);
+	atomic_set(&hw->stats.tgq, 0);
+	ida_init(&hw->cq_table);
+	spin_lock_init(&hw->cq_shadow_lock);
+	mutex_init(&hw->cq_init_lock);
+
+	/* Initialize the PTs */
+	atomic_set(&hw->stats.pt, 0);
+	ida_init(&hw->pte_table);
+	ida_init(&hw->pt_index_table);
+	ida_init(&hw->set_list_table);
+	ida_init(&hw->multicast_table);
+	spin_lock_init(&hw->lpe_shadow_lock);
+	spin_lock_init(&hw->rmu_portal_list_lock);
+	mutex_init(&hw->mst_table_lock);
+	mutex_init(&hw->pte_transition_sm_lock);
+	atomic_set(&hw->plec_count, 0);
+
+	/* Initialize the CTs. */
+	atomic_set(&hw->stats.ct, 0);
+	mutex_init(&hw->ct_init_lock);
+	ida_init(&hw->ct_table);
+
+	ida_init(&hw->lni_table);
+	cass_rgid_init(hw);
+
+	ida_init(&hw->md_index_table);
+
+	for (i = 0; i < C_PE_COUNT; i++)
+		ida_init(&hw->le_pool_ids[i]);
+
+	ida_init(&hw->tle_pool_ids);
+	mutex_init(&hw->msg_relay_lock);
+	mutex_init(&hw->tc_lock);
+	INIT_LIST_HEAD(&hw->tc_list);
+	mutex_init(&hw->cxi_adev_lock);
+	for (i = 0; i < ARRAY_SIZE(hw->vfs); i++)
+		mutex_init(&hw->vfs[i].notif_lock);
+
+	/* Initialize RMU Ethernet resource management */
+	idr_init(&hw->rmu_eth_idr);
+	mutex_init(&hw->rmu_eth_lock);
+
+	mutex_init(&hw->err_flg_mutex);
+	INIT_LIST_HEAD(&hw->err_flg_list);
+	spin_lock_init(&hw->sfs_err_flg_lock);
+
+	spin_lock_init(&hw->mst_match_done_lock);
+	mutex_init(&hw->mst_update_lock);
+
+	spin_lock_init(&hw->sbl_state_lock);
+
+	mutex_init(&hw->qsfp_eeprom_lock);
+	cass_phy_init(hw);
+
+	INIT_DELAYED_WORK(&hw->lni_cleanups_work, lni_cleanups_work);
+	mutex_init(&hw->lni_cleanups_lock);
+	INIT_LIST_HEAD(&hw->lni_cleanups_list);
+
+	mutex_init(&hw->sbus_mutex);
+	mutex_init(&hw->get_ctrl_mutex);
+	mutex_init(&hw->amo_remap_to_pcie_fadd_mutex);
+
+	hw->tsc_fill_qty = TSC_DEFAULT_FILL_QTY;
+	hw->uc_platform = CUC_BOARD_TYPE_UNKNOWN;
+
+	/* Enable Device */
+	rc = pci_enable_device(pdev);
+	if (rc) {
+		cxidev_err(&hw->cdev, "pci_enable_device() failed.\n");
+		goto hw_free;
+	}
+
+	/* The is_physfn and is_virtfn fields of struct pci_dev are only set if
+	 * SR-IOV has been successfully enabled. This means that we cannot rely on
+	 * them to identify physical vs. virtual functions in all cases. A PF on
+	 * real hardware without SR-IOV support, a passthrough PF attached to a VM,
+	 * or a VF attached to a VM, will all have is_physfn = is_virtfn = 0.
+	 *
+	 * C2 (and most other PCI devices) have distinct device IDs for PF and VF.
+	 * However, C1 uses the same ID for both, so we identify PF vs. VF by the
+	 * size of BAR 0.
+	 */
+
+	switch (id->device) {
+	case PCI_DEVICE_ID_CASSINI_1:
+		is_physfn = pci_resource_len(pdev, MMIO_BAR) >= MMIO_BAR_LEN_PF;
+		break;
+	case PCI_DEVICE_ID_CASSINI_2_PF:
+		is_physfn = true;
+		break;
+	case PCI_DEVICE_ID_CASSINI_2_VF:
+		is_physfn = false;
+		break;
+	default:
+		cxidev_err(&hw->cdev, "Unknown device ID: %04x", id->device);
+		return -EOPNOTSUPP;
+	}
+	hw->cdev.is_physfn = is_physfn;
+
+	hw->pci_disabled = false;
+
+	rc = pci_enable_pcie_error_reporting(pdev);
+	if (rc)
+		cxidev_err(&hw->cdev, "PCIe AER not enabled: %d\n", rc);
+
+	/* Set PID space variables for NIC. */
+	hw->cdev.prop.pid_bits = pid_bits;
+	hw->cdev.prop.pid_count = (1 << pid_bits) - 1; /* -1 is wildcard */
+	hw->cdev.prop.pid_granule =
+		(1 << (DFA_EP_BITS - hw->cdev.prop.pid_bits));
+
+	hw->cdev.prop.min_free_shift = min_free_shift;
+
+	/* Set the NID to invalid */
+	hw->cdev.prop.nid = CXI_INVALID_NID;
+
+	/* Enable DMA */
+	pci_set_master(pdev);
+
+	dma_set_max_seg_size(&hw->cdev.pdev->dev, UINT_MAX);
+
+	rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(57));
+	if (rc) {
+		cxidev_err(&hw->cdev, "dma_set_mask_and_coherent failed: %d\n", rc);
+		goto dev_disable;
+	}
+
+	/* Enable PCIe AMO requests */
+	pcie_capability_set_word(pdev, PCI_EXP_DEVCTL2,
+				 PCI_EXP_DEVCTL2_ATOMIC_REQ);
+
+	/* Make sure VF 10-bit tag support bit is set for correct counting of
+	 * PI_IPD_pti_tarb_blocked_on_tag.
+	 */
+#define PCI_SRIOV_CTRL_VF_10BIT_TAG 0x20
+	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
+	if (pos) {
+		u16 word;
+
+		pci_read_config_word(pdev, pos + PCI_SRIOV_CTRL, &word);
+		word |= PCI_SRIOV_CTRL_VF_10BIT_TAG;
+		pci_write_config_word(pdev, pos + PCI_SRIOV_CTRL, word);
+	}
+
+	/* Sanity Check. Check BAR 0 is defined and mapped */
+	if (!(pci_resource_flags(pdev, MMIO_BAR) & IORESOURCE_MEM)) {
+		cxidev_err(&hw->cdev, "Incorrect Bar configuration\n");
+		goto dev_disable;
+	}
+
+	/* Take ownership of memory region */
+	rc = pci_request_regions(pdev, "cxi");
+	if (rc) {
+		cxidev_err(&hw->cdev, "pci_request_regions() failed.\n");
+		goto dev_disable;
+	}
+
+	/* Map the base registers */
+	hw->regs_base = pci_resource_start(pdev, MMIO_BAR);
+	if (is_physfn) {
+		hw->regs = ioremap(hw->regs_base + C_MEMORG_CSR,
+				   C_MEMORG_CSR_SIZE);
+		if (!hw->regs) {
+			cxidev_err(&hw->cdev, "ioremap failed\n");
+			goto free_regions;
+		}
+
+		/* Check hardware is supported */
+		rc = is_supported(hw);
+		if (rc)
+			goto unmap_regions;
+
+		/* Check for input and hardware version consistency */
+		if ((system_type_identifier == CASSINI_1_ONLY &&
+		     !cass_version(hw, CASSINI_1)) ||
+		    (system_type_identifier == CASSINI_2_ONLY &&
+		     !cass_version(hw, CASSINI_2))) {
+			cxidev_err(&hw->cdev,
+				   "NIC Version and system_type_identifier (%u) are inconsistent\n",
+				   system_type_identifier);
+			goto unmap_regions;
+		}
+
+		hw->cdev.system_type_identifier = system_type_identifier;
+
+		rc = get_pcie_link_speed(hw);
+		if (rc)
+			goto unmap_regions;
+
+#if defined(CXI_DISABLE_SRIOV)
+		rc = pci_sriov_set_totalvfs(pdev, 0);
+		if (rc)
+			goto unmap_regions;
+#endif
+	}
+
+	hw->with_vf_support = pdev->is_physfn || pci_msix_vec_count(pdev) != 2;
+
+	hw->cdev.cxi_num = atomic_inc_return(&cxi_num);
+	dev_set_name(&hw->class_dev, "cxi%u", hw->cdev.cxi_num);
+	strcpy(hw->cdev.name, dev_name(&hw->class_dev));
+
+	cxi_set_link_ops(hw);
+
+	rc = cass_irq_init(hw);
+	if (rc) {
+		cxidev_err(&hw->cdev, "cass_irq_init failed: %d\n", rc);
+		goto unmap_regions;
+	}
+
+	if (is_physfn) {
+		/* NIC address needs to be assigned before initialization. */
+		rc = init_hw(hw);
+		if (rc) {
+			cxidev_err(&hw->cdev, "init_hw failed: %d\n", rc);
+			goto free_irqs;
+		}
+
+		rc = register_error_handlers(hw);
+		if (rc)
+			goto fini_hw;
+
+		rc = cass_register_uc(hw);
+		if (rc) {
+			cxidev_err(&hw->cdev, "Cannot register the uC: %d\n", rc);
+			goto free_error_handlers;
+		}
+
+		switch (hw->uc_platform) {
+		case CUC_BOARD_TYPE_SAWTOOTH:
+		case CUC_BOARD_TYPE_BRAZOS:
+			if (!cass_version(hw, CASSINI_1)) {
+				cxidev_err(&hw->cdev, "Invalid Cassini 1 platform: %d\n",
+					   hw->uc_platform);
+				goto unregister_uc;
+			}
+			break;
+		case CUC_BOARD_TYPE_WASHINGTON:
+		case CUC_BOARD_TYPE_KENNEBEC:
+		case CUC_BOARD_TYPE_SOUHEGAN:
+			if (!cass_version(hw, CASSINI_2)) {
+				cxidev_err(&hw->cdev, "Invalid Cassini 2 platform: %d\n",
+					   hw->uc_platform);
+				goto unregister_uc;
+			}
+			break;
+		default:
+			cxidev_err(&hw->cdev, "Unknown uC platform %d\n",
+				   hw->uc_platform);
+			goto unregister_uc;
+		}
+
+		if (HW_PLATFORM_ASIC(hw) || HW_PLATFORM_NETSIM(hw)) {
+			/* These platforms have a micro-controller to fetch the
+			 * NIC ID from
+			 */
+			rc = uc_cmd_get_nic_id(hw);
+			if (rc)
+				goto unregister_uc;
+		} else {
+			hw->uc_nic = 0;
+		}
+
+		rc = uc_cmd_get_mac(hw);
+		if (rc)
+			eth_random_addr(hw->default_mac_addr);
+		uc_cmd_set_link_leds(hw, LED_FAST_GRN);
+
+		if (HW_PLATFORM_ASIC(hw)) {
+			/* Program MAC with burned-in MAC. */
+			ether_addr_copy(hw->cdev.mac_addr, hw->default_mac_addr);
+		} else {
+			u64 reg;
+			u8 mac_addr[ETH_ALEN];
+
+			/* Pull MAC from a scratch register on netsim and derive NID from it. */
+			if (HW_PLATFORM_NETSIM(hw))
+				cass_read(hw, NICSIM_NIC_ID, &reg, 8);
+			else
+				cass_read(hw, C_MB_DBG_SCRATCH(1), &reg, 8);
+
+			u64_to_ether_addr(reg, mac_addr);
+			ether_addr_copy(hw->cdev.mac_addr, mac_addr);
+			program_nid(hw, ether_addr_to_u64(hw->cdev.mac_addr) & 0xFFFFFULL);
+		}
+
+		/* SBL init must happen after uC init, since SBL needs to know
+		 * which NIC is associated with this driver instance
+		 */
+		rc = hw->link_ops->link_start(hw);
+		if (rc)
+			goto unregister_uc;
+		link_started = true;
+
+		cass_tc_get_hni_pause_cfg(hw);
+
+		if (cass_version(hw, CASSINI_1)) {
+			rc = cass_register_port(hw);
+			if (rc)
+				goto link_fini;
+		}
+
+		rc = cass_ptp_init(hw);
+		if (rc)
+			goto unregister_port;
+
+		rc = cxi_dmac_desc_set_alloc(&hw->cdev, 1, "pt_id");
+		if (rc < 0)
+			goto cass_ptp_fini;
+		hw->dmac_pt_id = rc;
+
+		hw->mst_entries = dma_alloc_coherent(&pdev->dev,
+						     C_MST_DBG_MST_TABLE_SIZE,
+						     &hw->mst_entries_dma_addr,
+						     GFP_KERNEL);
+		if (!hw->mst_entries)
+			goto cass_dmac_fini;
+
+		rc = cxi_dmac_desc_set_add(&hw->cdev, hw->dmac_pt_id,
+					   hw->mst_entries_dma_addr,
+					   C_MST_DBG_MST_TABLE(0),
+					   C_MST_DBG_MST_TABLE_SIZE);
+		if (rc)
+			goto cass_mst_fini;
+	}
+
+	/* Set after TC/QOS init */
+	hw->cdev.untagged_eth_pcp = hw->qos.untagged_eth_pcp;
+
+	hw->cdev.prop.device_rev = hw->rev.rev;
+	hw->cdev.prop.device_proto = hw->rev.proto;
+	hw->cdev.prop.device_platform = hw->rev.platform;
+
+	hw->max_eth_rxsize = VLAN_ETH_FRAME_LEN;
+
+	cass_probe_debugfs_init(hw);
+
+	/* Hack to grant exclusive access to userspace for QSFP
+	 * firmware flashing. The SL driver must not be able to query
+	 * the QSFP module while an upgrade is happening. Since the UC
+	 * accesses are serialized, we shouldn't need anything
+	 * stronger than that. More ideally, we should have this file
+	 * attached to the i2c debugfs entry, but this was only made
+	 * available in kernel 6.8.
+	 */
+	debugfs_create_bool("i2c_locked", 0644, hw->debug_dir, &hw->uc_i2c_locked);
+
+	/* RX and TX profile setup */
+	cass_dev_rx_tx_profiles_init(hw);
+
+	/* Resource Group setup */
+	cass_dev_rgroup_init(hw);
+
+	/* Service setup */
+	rc = cass_svc_init(hw);
+	if (rc)
+		goto rgroup_fini;
+
+	rc = cxi_configfs_device_init(hw);
+	if (rc) {
+		pr_err("configfs initialize failed\n");
+		goto svc_fini;
+	}
+
+	if (!is_physfn) {
+		struct cxi_get_dev_properties_cmd cmd = {
+			.op = CXI_OP_GET_DEV_PROPERTIES,
+		};
+		struct cxi_properties_info resp;
+		size_t reply_len = sizeof(resp);
+
+		rc = cass_vf_init(hw);
+		if (rc)
+			goto configfs_fini;
+
+		/* Retrieve the device properties */
+		rc = cxi_send_msg_to_pf(&hw->cdev, &cmd, sizeof(cmd),
+					&resp, &reply_len);
+		if (rc != 0) {
+			cxidev_err(&hw->cdev, "BAD: Reply has return code %d\n", rc);
+			goto vf_fini;
+		} else if (reply_len != sizeof(resp)) {
+			cxidev_err(&hw->cdev,
+				   "BAD: Reply has unexpected length %zu\n",
+				   reply_len);
+			goto vf_fini;
+		} else {
+			cxidev_dbg(&hw->cdev, "Reply is valid\n");
+
+			hw->cdev.prop = resp;
+		}
+	}
+
+	/* Export device information. */
+	rc = create_sysfs_properties(hw);
+	if (rc)
+		goto vf_fini;
+
+	/* Register the device with sysfs */
+	hw->class_dev.class = &cxi_class;
+	hw->class_dev.parent = &pdev->dev;
+	hw->class_dev.release = cass_dev_release;
+	dev_set_drvdata(&hw->class_dev, hw);
+	class_dev_initialized = true;
+	if (device_register(&hw->class_dev)) {
+		destroy_sysfs_properties(hw);
+		goto vf_fini;
+	}
+
+	cxi_add_device(&hw->cdev);
+
+	if (is_physfn) {
+		cass_phy_start(hw, true);
+		start_pcie_monitoring(hw);
+	}
+
+	/* RDMA is optional; the NIC and Ethernet work without it. */
+	rc = cxi_ib_add_adev(pdev, hw, hw->cdev.cxi_num);
+	if (rc)
+		cxidev_warn(&hw->cdev,
+			    "RDMA auxiliary device not created: %d\n", rc);
+
+	return 0;
+
+vf_fini:
+	if (!is_physfn)
+		cass_vf_fini(hw);
+
+configfs_fini:
+	cxi_configfs_cleanup(hw);
+svc_fini:
+	cass_svc_fini(hw);
+rgroup_fini:
+	cass_dev_rgroup_fini(hw);
+	cass_dev_rx_tx_profiles_fini(hw);
+	debugfs_remove_recursive(hw->debug_dir);
+cass_mst_fini:
+	if (is_physfn) {
+		rc = cass_link_fini_once(hw, &link_started);
+		if (rc) {
+			WARN(1, "Cassini link teardown failed during probe unwind: %d\n", rc);
+			return rc;
+		}
+	}
+	if (is_physfn)
+		dma_free_coherent(&pdev->dev, C_MST_DBG_MST_TABLE_SIZE,
+				  hw->mst_entries, hw->mst_entries_dma_addr);
+cass_dmac_fini:
+	if (is_physfn) {
+		rc = cass_link_fini_once(hw, &link_started);
+		if (rc) {
+			WARN(1, "Cassini link teardown failed during probe unwind: %d\n", rc);
+			return rc;
+		}
+	}
+	if (is_physfn)
+		cxi_dmac_desc_set_free(&hw->cdev, hw->dmac_pt_id);
+cass_ptp_fini:
+	if (is_physfn) {
+		rc = cass_link_fini_once(hw, &link_started);
+		if (rc) {
+			WARN(1, "Cassini link teardown failed during probe unwind: %d\n", rc);
+			return rc;
+		}
+	}
+	if (is_physfn)
+		cass_ptp_fini(hw);
+unregister_port:
+	if (is_physfn) {
+		rc = cass_link_fini_once(hw, &link_started);
+		if (rc) {
+			WARN(1, "Cassini link teardown failed during probe unwind: %d\n", rc);
+			return rc;
+		}
+	}
+	if (is_physfn)
+		if (cass_version(hw, CASSINI_1))
+			cass_unregister_port(hw);
+link_fini:
+	if (is_physfn) {
+		rc = cass_link_fini_once(hw, &link_started);
+		if (rc) {
+			WARN(1, "Cassini link teardown failed during probe unwind: %d\n", rc);
+			return rc;
+		}
+	}
+unregister_uc:
+	if (is_physfn) {
+		uc_cmd_set_link_leds(hw, LED_OFF);
+		cass_unregister_uc(hw);
+	}
+free_error_handlers:
+	if (is_physfn)
+		deregister_error_handlers(hw);
+fini_hw:
+	if (is_physfn)
+		fini_hw(hw);
+free_irqs:
+	cass_irq_fini(hw);
+unmap_regions:
+	if (is_physfn)
+		iounmap(hw->regs);
+free_regions:
+	pci_release_regions(pdev);
+dev_disable:
+	cxidev_err(&hw->cdev, "deregistering device\n");
+
+	pci_clear_master(pdev);
+	pci_disable_pcie_error_reporting(pdev);
+	pci_disable_device(pdev);
+hw_free:
+	pci_set_drvdata(pdev, NULL);
+	if (class_dev_initialized)
+		put_device(&hw->class_dev);
+	else
+		kfree(hw);
+
+	return -ENODEV;
+}
+
+static void cass_remove(struct pci_dev *pdev)
+{
+	struct cass_dev *hw = pci_get_drvdata(pdev);
+	int rtn;
+
+	if (hw->cxi_adev) {
+		cxi_ib_remove_adev(hw);
+	}
+
+	cxi_remove_device(&hw->cdev);
+	destroy_sysfs_properties(hw);
+	debugfs_lookup_and_remove("port", hw->debug_dir);
+	debugfs_lookup_and_remove("counters", hw->debug_dir);
+
+	if (hw->cdev.is_physfn) {
+		stop_pcie_monitoring(hw);
+		cass_phy_stop(hw, true);
+		rtn = hw->link_ops->link_fini(hw);
+		if (rtn) {
+			WARN(1, "Cassini link teardown failed during remove: %d; aborting device teardown\n",
+			     rtn);
+			return;
+		}
+	}
+
+	cancel_delayed_work_sync(&hw->lni_cleanups_work);
+	lni_cleanups(hw, true);
+
+	/* Destroy RMU Ethernet resource management */
+	idr_destroy(&hw->rmu_eth_idr);
+
+	cass_rgid_fini(hw);
+	cxi_configfs_cleanup(hw);
+	cass_svc_fini(hw);
+	cass_dev_rgroup_fini(hw);
+	cass_dev_rx_tx_profiles_fini(hw);
+
+	debugfs_remove_recursive(hw->debug_dir);
+
+	if (hw->cdev.is_physfn) {
+		if (hw->num_vfs)
+			cass_sriov_configure(hw->cdev.pdev, 0);
+		dma_free_coherent(&pdev->dev, C_MST_DBG_MST_TABLE_SIZE,
+				  hw->mst_entries, hw->mst_entries_dma_addr);
+		cxi_dmac_desc_set_free(&hw->cdev, hw->dmac_pt_id);
+		cass_ptp_fini(hw);
+		uc_cmd_set_link_leds(hw, LED_OFF);
+		cass_unregister_uc(hw);
+		if (cass_version(hw, CASSINI_1))
+			cass_unregister_port(hw);
+		deregister_error_handlers(hw);
+		fini_hw(hw);
+	} else {
+		cass_vf_fini(hw);
+	}
+
+	cass_irq_fini(hw);
+
+	if (hw->cdev.is_physfn)
+		iounmap(hw->regs);
+	pci_release_regions(pdev);
+	pci_clear_master(pdev);
+	pci_disable_pcie_error_reporting(pdev);
+	if (!hw->pci_disabled)
+		pci_disable_device(pdev);
+
+	cxidev_WARN_ONCE(&hw->cdev, !refcount_dec_and_test(&hw->refcount),
+			 "Resource leaks - HW refcount not zero: %d\n",
+			 refcount_read(&hw->refcount));
+	device_unregister(&hw->class_dev);
+}
+
+void cass_disable_device(struct pci_dev *pdev, const char *reason)
+{
+	struct cass_dev *hw = pci_get_drvdata(pdev);
+
+	if (reason)
+		cxidev_err(&hw->cdev, "Disabling device. Reason: %s", reason);
+	else
+		cxidev_err(&hw->cdev, "Disabling device");
+
+	pci_clear_master(pdev);
+	pci_disable_device(pdev);
+
+	hw->pci_disabled = true;
+}
+
+void uncor_cb(struct cass_dev *hw, unsigned int irq, bool is_ext,
+	      unsigned int bitn)
+{
+	char reason[200];
+
+	if (!disable_on_error)
+		return;
+
+	snprintf(reason, sizeof(reason),
+		 "Unrecoverable error: %s with bitn: %d",
+		 (*hw->err_handlers)[irq][is_ext ? 1 : 0].csr_name_lo, bitn);
+
+	cass_disable_device(hw->cdev.pdev, reason);
+}
+
+static struct pci_device_id cass_ids[] = {
+	{ PCI_DEVICE(PCI_VENDOR_ID_CRAY, PCI_DEVICE_ID_CASSINI_1) },
+	{ PCI_DEVICE(PCI_VENDOR_ID_HPE, PCI_DEVICE_ID_CASSINI_2_PF) },
+	{ PCI_DEVICE(PCI_VENDOR_ID_HPE, PCI_DEVICE_ID_CASSINI_2_VF) },
+	{ 0, },
+};
+
+static struct pci_driver cass_pci_driver = {
+	.name = KBUILD_MODNAME,
+	.id_table = cass_ids,
+	.probe = cass_probe,
+	.remove = cass_remove,
+	.sriov_configure = cass_sriov_configure,
+};
+
+MODULE_DEVICE_TABLE(pci, cass_ids);
+
+int hw_register(void)
+{
+	int rc;
+
+	rc = genl_register_family(&cxierr_genl_family);
+	if (rc)
+		return rc;
+
+	rc = pci_register_driver(&cass_pci_driver);
+
+	if (rc)
+		genl_unregister_family(&cxierr_genl_family);
+
+	return rc;
+}
+
+void hw_unregister(void)
+{
+	pci_unregister_driver(&cass_pci_driver);
+	genl_unregister_family(&cxierr_genl_family);
+}
+
+/**
+ * cxi_retry_handler_running() - Check if retry handler is running.
+ *
+ * @cdev: CXI device.
+ *
+ * Return: True if retry handler is running. Else, false.
+ */
+bool cxi_retry_handler_running(struct cxi_dev *cdev)
+{
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+
+	return hw->pct_eq_n != C_EQ_NONE;
+}
+EXPORT_SYMBOL(cxi_retry_handler_running);
diff --git a/drivers/net/ethernet/hpe/ss1/cass_core.h b/drivers/net/ethernet/hpe/ss1/cass_core.h
new file mode 100644
index 000000000000..0810664d4ab9
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_core.h
@@ -0,0 +1,1472 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2020-2026 Hewlett Packard Enterprise Development LP */
+
+#ifndef _CASS_CORE_H
+#define _CASS_CORE_H
+
+#include <linux/device.h>
+#include <linux/iova.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/pci.h>
+#include <linux/rbtree.h>
+#include <linux/workqueue.h>
+#include <net/netlink.h>
+#include <net/genetlink.h>
+#include <linux/ptp_clock_kernel.h>
+#include <linux/etherdevice.h>
+#include <linux/completion.h>
+#include <linux/hrtimer.h>
+#include <linux/hwmon.h>
+#include <linux/socket.h>
+#include <linux/i2c.h>
+
+#include "cxi_link.h"
+#include "cxi_core.h"
+#include "cuc_cxi.h"	/* from firmware_cassini/ */
+#include "cass_sbl.h"
+#include "pldm_cxi.h"
+#include "cass_sl.h"
+#include "cxi_qos_profiles.h"
+#include "cass_rx_tx_profile.h"
+#include "cass_rgroup.h"
+#include "cxi_config.h"
+#include "cass_p2p.h"
+#include "cass_vf.h"
+
+#define PCI_VENDOR_ID_CRAY         0x17db
+#define PCI_DEVICE_ID_CASSINI_1    0x0501
+#define PCI_VENDOR_ID_HPE          0x1590
+#define PCI_DEVICE_ID_CASSINI_2_PF 0x0371
+#define PCI_DEVICE_ID_CASSINI_2_VF 0x0372
+
+#define CXI_MODULE_NAME "cxi_ss1"
+
+/* The following are IPv6 next header values used for IPv6 extension headers.
+ * https://www.iana.org/assignments/ipv6-parameters/ipv6-parameters.xhtml
+ */
+#define IPV6_EH_HOPOPTS 0
+#define IPV6_EH_ROUTE 43
+#define IPV6_EH_FRAG 44
+#define IPV6_EH_ESP 50
+#define IPV6_EH_AH 51
+#define IPV6_EH_OPTS 60
+#define IPV6_EH_MOBILITY 135
+#define IPV6_EH_HIP 139
+#define IPV6_EH_SHIM6 140
+#define IPV6_EH_RSVD1 253
+#define IPV6_EH_RSVD2 254
+
+#define HW_PLATFORM(_hw) ((_hw)->rev.platform)
+#define HW_PLATFORM_ASIC(_hw) (HW_PLATFORM(_hw) == C_PLATFORM_ASIC)
+#define HW_PLATFORM_Z1(_hw) (HW_PLATFORM(_hw) == C_PLATFORM_Z1)
+#define HW_PLATFORM_NETSIM(_hw) (HW_PLATFORM(_hw) == C_PLATFORM_NETSIM)
+
+#define C_MAX_CSR_ERR_INFO 3
+#define C_MAX_CSR_CNTRS   3
+
+/* HPC MTU is fixed at 2k. The largest HPC header is 64 bytes. */
+#define C_MAX_HPC_MTU (2048 + 64)
+
+/* PCI BARs containing the CSRs and CQ/EQ areas. */
+#define MMIO_BAR 0
+
+/* Expected length of PCI BAR 0 for a Physical Function. Used to differentiate
+ * between Virtual Function (512M BAR 0) and Physical Function (2G BAR 0) under
+ * SR-IOV.
+ */
+#define MMIO_BAR_LEN_PF 2147483648
+
+/* Number of error interrupts */
+#define NUM_ERR_INTS 30
+
+#define PORTALS_MAX_FRAME_SIZE 2111U
+#define ETHERNET_MAX_FRAME_SIZE 9022U
+#define TSC_DEFAULT_FILL_QTY 16U
+
+#define PLEC_SIZE 256U
+
+enum cass_phy_state {
+	CASS_PHY_DOWN,
+	CASS_PHY_READY,
+	CASS_PHY_HALTED,
+	CASS_PHY_UP,
+	CASS_PHY_RUNNING,
+	CASS_PHY_NOLINK,
+	CASS_PHY_HEADSHELL_REMOVED,
+};
+
+#ifdef pr_fmt
+#undef pr_fmt
+#endif
+#define pr_fmt(fmt) KBUILD_MODNAME ":%s:%d " fmt, __func__, __LINE__
+
+#define atu_debug(fmt, ...) \
+do {						\
+	if (more_debug)				\
+		pr_debug(fmt, ##__VA_ARGS__);	\
+} while (0)
+
+/* Helper to get current task network namespace inode id safely. */
+#define CURRENT_NETNS_ID() ({					\
+	unsigned int __netns_id = 0;				\
+	struct task_struct *__ct = current;			\
+	rcu_read_lock();					\
+	if (__ct->nsproxy && __ct->nsproxy->net_ns)		\
+		__netns_id = __ct->nsproxy->net_ns->ns.inum;	\
+	rcu_read_unlock();					\
+	__netns_id;						\
+})
+
+#define ALLOC_IOVA_FAST(iovad, len, end) alloc_iova_fast(iovad, len, end, true)
+#define FREE_IOVA_FAST free_iova_fast
+
+#define INIT_IOVA_DOMAIN(iovad, ps, base, end) \
+		init_iova_domain(iovad, ps, base)
+
+#define ATU_HMM_PFN_TO_PFN(hpfn) page_to_pfn(hmm_pfn_to_page(hpfn))
+
+#define ATU_PFN_INVALID(hpfn) \
+	(!(hpfn & HMM_PFN_VALID) || \
+	 !(hpfn & HMM_PFN_WRITE) || \
+	  (hpfn & HMM_PFN_ERROR))
+#define ATU_PFN_WRITE(hpfn) ((hpfn & HMM_PFN_WRITE))
+#define ATU_PFN_VALID(hpfn) ((hpfn & HMM_PFN_VALID))
+
+/* AER is automatically enabled by the PCI core. */
+static inline int pci_enable_pcie_error_reporting(void *p) { return 0; }
+static inline void pci_disable_pcie_error_reporting(void *p) {}
+
+/* SR-IOV requires VFIO with KVM support enabled and kernel >= 5.19 */
+#if !defined(CONFIG_KVM_VFIO)
+#define CXI_DISABLE_SRIOV
+#endif
+
+#define ATU_FAULT_RETRY_MAX 16
+#define ATU_PTE_PTR (1 << 6)
+#define ATU_PTE_READ (1UL << 57)
+#define ATU_PTE_WRITE (1UL << 58)
+#define ATU_PTE_LEAF (1UL << 59)
+#define ATU_PTE_PRESENT (1UL << 60)
+#define ATU_HMM_RANGE_TIMEOUT 1000
+#define ATU_PTE_MASK (~(ATU_PTE_READ | ATU_PTE_WRITE | ATU_PTE_LEAF | \
+				ATU_PTE_PRESENT))
+
+#define MASK(x) (BIT(x) - 1)
+#define ATU_PTEPTR_SHIFT 6
+#define PTE_ADDR(pte) ((pte).ptr << ATU_PTEPTR_SHIFT)
+#define pfn2phys __pfn_to_phys
+#define PHYS_TO_PAGE(pa) pfn_to_page(__phys_to_pfn(pa))
+
+#define C_ADDR_SHIFT 12
+#define ATU_PTE_ENTRY_SIZE    sizeof(union a_pte)
+#define flsl(x) (fls64(x) - 1)
+#define ffsl(x) (fls64((x) & -(x)) - 1)
+#define ATUCQ_TIMEOUT (odp_sw_decouple ? decouple_timeout_us : atucq_timeout_us)
+#define ATU_IBW_TIMEOUT (5 * MSEC_PER_SEC * USEC_PER_MSEC)
+#define ATU_ODPQ_SPACE_TIMEOUT (100 * USEC_PER_MSEC)
+#define ATU_STS_ATUCQ_IDLE_TIMEOUT (10 * MSEC_PER_SEC * USEC_PER_MSEC)
+#define ATU_STS_IBW_IDLE_TIMEOUT (1000 * MSEC_PER_SEC * USEC_PER_MSEC)
+#define ATUCQ_ENTRY(index) (index & (C_ATU_CFG_CQ_TABLE_ENTRIES - 1))
+/* Based on the AC base page size */
+#define ATU_PMD_ORDER(cac) (cac->huge_shift - cac->page_shift)
+#define ATU_PMD_NR(cac) BIT(ATU_PMD_ORDER(cac))
+#define ATU_PTE_ORDER(cac) (cac->page_shift - PAGE_SHIFT)
+#define ATU_PTE_NR(cac) BIT(ATU_PTE_ORDER(cac))
+#define PFN_INC(cac, leaf) (leaf ? ATU_PMD_NR(cac) : 1)
+/* Based on the kernel base page size */
+#define K_PMD_ORDER(cac) (cac->huge_shift - PAGE_SHIFT)
+#define K_PMD_NR(cac) BIT(K_PMD_ORDER(cac))
+#define KPFN_INC(cac, leaf) (leaf ? K_PMD_NR(cac) : ATU_PTE_NR(cac))
+#define ATU_FLAGS_MASK ~(CXI_MAP_READ | CXI_MAP_WRITE | CXI_MAP_ALLOC_MD | \
+			 CXI_MAP_FAULT | CXI_MAP_PREFETCH)
+#define ATUCQ_INVALIDATE_ALL 0x200000000000000UL
+#define MAX_PG_TABLE_SIZE 15
+#define MIN_PG_TABLE_SIZE 3
+#define MIN_DEVICE_PG_TABLE_SIZE (MIN_PG_TABLE_SIZE + 2)
+#define INVALID_DMABUF_FD (-1)
+
+/* Reserve an AC for physical mapping to be shared by all processes */
+#define ATU_PHYS_AC (C_ATU_CFG_AC_TABLE_ENTRIES - 1)
+#define ATU_NTA_DEF_PI_ACXT ATU_PHYS_AC
+#define ATU_FLUSH_REQ_DELAY 0x3ff
+
+#ifndef VMA_ITERATOR
+#define for_each_vma(vmi, vma) for (; vma; vma = vma->vm_next)
+#endif /* VMA_ITERATOR */
+
+#define CASS_NUM_LE_POOLS (C_LPE_CFG_PE_LE_POOLS_ENTRIES / C_PE_COUNT)
+#define CASS_MIN_POOL_TLES 8
+#define ACS_AVAIL (ATU_PHYS_AC - 1)
+#define CTS_AVAIL (C_NUM_CTS - 1) /* CT 0 invalid */
+#define EQS_AVAIL (C_NUM_EQS - 1) /* EQ 0 invalid */
+
+#define CASS_MAX_IRQ_NAME 24
+
+/* Current devices have up to 31 sensors */
+#define CASS_MAX_SENSORS 32
+
+#define CASS2_MAX_PACKETS_INFLIGHT 128U
+#define CASS1_MAX_PACKETS_INFLIGHT 64U
+
+#define DEFAULT_LE_POOL_ID 0
+#define DEFAULT_TLE_POOL_ID 0
+
+enum cass_link_speed {
+	CASS_SPEED_UNKNOWN = PCI_SPEED_UNKNOWN,
+	CASS_SPEED_2_5GT = PCIE_SPEED_2_5GT,
+	CASS_SPEED_5_0GT = PCIE_SPEED_5_0GT,
+	CASS_SPEED_8_0GT = PCIE_SPEED_8_0GT,
+	CASS_SPEED_16_0GT = PCIE_SPEED_16_0GT,
+	CASS_SPEED_32_0GT = PCIE_SPEED_32_0GT,
+
+	CASS_SPEED_20_0GT,
+	CASS_SPEED_25_0GT,
+};
+
+/* Cassini clock frequency */
+#define C1_CLK_FREQ_HZ 1000000000ULL /* 1 GHz */
+#define C2_CLK_FREQ_HZ 1100000000ULL /* 1.1 GHz */
+
+extern const struct file_operations uc_fops;
+
+union a_pte {
+	struct c_page_table_entry pte;
+	u64 qw;
+};
+
+struct l1_entry {
+	/* The array of PTEs */
+	struct page *l1_pages;
+	dma_addr_t l1_pages_dma_addr;
+
+	/* Bitmap of used PTEs */
+	unsigned long *bitmap;
+};
+
+struct cass_nta {
+	/* nta root page table pointer virtual address */
+	union a_pte *root_ptr;
+	struct page *root_page;
+	dma_addr_t root_page_dma_addr;
+	int root_order;
+	int l1_order;
+	int numa_node;
+
+	/* Each L0 PDE has its own bitmap of allocated L1 PTE. */
+	int l0_entries;
+	int l1_entries;
+	struct l1_entry l1[];
+};
+
+struct cass_ac {
+	struct cxi_ac ac;
+	struct list_head list;
+	struct list_head md_list;
+	struct mutex md_mutex;
+	struct cxi_lni_priv *lni_priv;
+
+	struct mutex ac_mutex;
+
+	/* copy of the atu ac struct */
+	union c_atu_cfg_ac_table cfg_ac;
+	u32 flags;
+
+	int page_shift;
+	int huge_shift;
+	int ptg_mode;
+	bool hugepage_test;
+
+	struct cass_nta *nta;
+
+	u64 iova_base;
+	u64 iova_end;
+	u64 iova_len;
+
+	struct iova_domain *iovad;
+	struct dentry *debug_dir;
+	struct dentry *lni_dir;
+	refcount_t refcount;
+	refcount_t reader_refs;
+	struct completion readers_done;
+
+	u32 pasid;
+	struct iommu_sva *sva;
+};
+
+/* Value written by the ATU CQ in wait_rsp_data when completing
+ * commands.
+ */
+#define WAIT_RSP_DATA 0xf00fbeefULL
+
+struct cass_atu_cq {
+	/* Protects access to the ATU CQ and wait_rsp_data */
+	struct mutex atu_cq_mutex;
+	struct mutex atu_ib_mutex;
+	/* Inbound-wait hardware failure latch, protected by atu_ib_mutex. */
+	bool hw_failure;
+
+	struct wait_rsp_data {
+		u64 cmp ____cacheline_aligned;
+		u64 ib ____cacheline_aligned;
+	} wait_rsp_data;
+
+	dma_addr_t rsp_dma_addr;
+	dma_addr_t cmp_wait_rsp_addr;
+	dma_addr_t ib_wait_rsp_addr;
+
+	char cmpl_wait_int_name[CASS_MAX_IRQ_NAME];
+};
+
+struct sts_idle {
+	struct cass_dev *hw;
+	bool ib_wait;
+};
+
+#define MAX_VFMSG_SIZE (22432 + sizeof(struct vf_pf_msg_hdr))
+
+/* A VF to PF message header */
+struct vf_pf_msg_hdr {
+	unsigned int len;	/* whole message length */
+	int rc;			/* return code */
+	uid_t uid;
+	gid_t gid;
+	int seq;
+};
+
+/* Traffic Class descriptions. */
+struct cass_tc_cfg {
+	struct list_head tc_entry;
+
+	unsigned int tc;
+	enum cxi_traffic_class_type tc_type;
+
+	/* Restricted request DSCP. */
+	unsigned int res_req_dscp;
+
+	/* Unrestricted request DSCP. */
+	unsigned int unres_req_dscp;
+
+	/* Restricted response DSCP. */
+	unsigned int res_rsp_dscp;
+
+	/* Unrestricted response DSCP. */
+	unsigned int unres_rsp_dscp;
+
+	/* Request PCP. */
+	unsigned int req_pcp;
+
+	/* Response PCP. */
+	unsigned int rsp_pcp;
+
+	/* CQ OCU Set Index */
+	unsigned int ocuset;
+
+	/* Traffic class value specific to CQ configuration. */
+	unsigned int cq_tc;
+
+	/* Buffer Class */
+	unsigned int req_bc;
+};
+
+struct cass_rsrc_info {
+	u16 res;
+	u16 shared_total;
+	u16 shared_in_use;
+};
+
+struct cass_irq {
+	struct atomic_notifier_head nh;
+	int idx;
+	struct cpumask mask;
+	char irq_name[CASS_MAX_IRQ_NAME];
+	atomic_t refcount;
+	int vec;
+	struct mutex lock;
+};
+
+/* Maximum size of an error flag CSR. For Cassini-1, they are all 64
+ * bits. For Cassini-2, C_HNI_PML_ERR_FLG is 256 bits long.
+ */
+#define MAX_ERR_FLAG_BITLEN 256
+union err_flags {
+	DECLARE_BITMAP(mask, MAX_ERR_FLAG_BITLEN);
+	union c_pi_err_flg pi;
+	union c_pi_ext_err_flg pi_ext;
+	union c_pi_ipd_ext_err_flg pi_ipd_ext;
+	union c_atu_err_flg atu;
+	union c_atu_ext_err_flg atu_ext;
+	union c1_hni_err_flg c1_hni;
+	union c2_hni_err_flg c2_hni;
+	union c2_hni_ext_err_flg c2_hni_ext;
+	union c1_hni_pml_err_flg c1_hni_pml;
+	union ss2_port_pml_err_flg ss2_port_pml;
+	union c_rmu_err_flg rmu;
+	union c_lpe_err_flg lpe;
+	union c_pct_ext_err_flg pct_ext;
+	union c_ee_err_flg ee;
+	union c_ixe_err_flg ixe_err_flg;
+};
+
+struct cxi_reg_err_flg {
+	struct list_head list;
+	unsigned int irq;
+	bool is_ext;
+	union err_flags err_flags;
+	/* Callback. irq is the MSI-X interrupt index (0 to 29), and
+	 * is_ext indicates whether the flag is set in the ERR_FLG or
+	 * EXT_ERR_FLG CSR. bitn is the bit index in abovementioned
+	 * CSR.
+	 */
+	void (*cb)(struct cass_dev *hw, unsigned int irq,
+		   bool is_ext, unsigned int bitn);
+};
+
+/* For error CSR processing */
+struct flg_err_info;
+struct csr_info {
+	const char *csr_name;
+	const char *csr_name_lo; /* same, in lower case */
+
+	/* Various CSR offsets for that error. */
+	unsigned int flg;
+	unsigned int mask;
+	unsigned int clr;
+	unsigned int first_flg;
+	unsigned int first_flg_ts;
+	unsigned int bitlen;
+	const struct flg_err_info *flg_info;
+};
+
+extern const struct file_operations decouple_stats_fops;
+extern const struct file_operations sw_decouple_fops;
+
+/*
+ * there currently are not that many entities that need to reserve
+ * sets of dma descriptors.
+ *
+ * Currently, cassini telemetry/counters (with test/experimental code)
+ * uses five dmac descriptor sets and rosetta link monitoring (lmon)
+ * may use two dma descriptor sets.
+ *
+ */
+#define DMAC_DESC_SET_COUNT			16
+
+struct dmac_desc_set {
+	u16 count;      /* total number of descs */
+	u16 index;      /* index of first desc */
+	u16 numused;    /* number of descs written */
+	const char *name;	/* descriptive name to identify use */
+};
+
+struct cass_vf {
+	struct task_struct *task;
+	struct socket *req_sock;
+	struct socket *notif_sock;
+
+	/* Index and back-pointer to hardware struct for use by VF handler thread */
+	struct cass_dev *hw;
+	int vf_idx;
+
+	/* ID of physical-address context for use when configuring CQ, EQ, etc. */
+	unsigned int phys_ac;
+
+	unsigned int token;
+	int notif_seq;
+
+	/* Per VF mutex to maintain notification message/response sequencing */
+	struct mutex notif_lock;
+
+	/* Per-VF message buffers */
+	char request[MAX_VFMSG_SIZE];
+	char reply[MAX_VFMSG_SIZE];
+
+	struct task_struct *kvm_task;
+};
+
+enum cxi_rmu_eth_filter_mode {
+	CXI_RMU_ETH_FILTER_NONE = 0,
+	CXI_RMU_ETH_FILTER_DIRECT,
+	CXI_RMU_ETH_FILTER_RSS,
+};
+
+/**
+ * struct cxi_rmu_eth_priv - Private Ethernet resource tracking (INTERNAL)
+ *
+ * Full internal structure containing all resource management state.
+ * One allocation per function (PF or VF).
+ */
+struct cxi_rmu_eth_priv {
+	struct cxi_rmu_eth rmu_eth;     /* Public opaque handle */
+	struct cxi_dev *dev;            /* Device this allocation belongs to */
+	bool is_vf;                     /* True if this is a VF allocation */
+	unsigned int vf_num;            /* VF number (if is_vf=true) */
+	bool admin;                     /* True if it has admin privileges */
+
+	/* Resource allocation */
+	unsigned int indir_base;        /* Absolute offset in HW indirection table */
+	unsigned int indir_size;        /* Number of indir entries allocated */
+	unsigned int set_list_base;     /* Absolute offset in HW set_list (4+ for dynamic) */
+	unsigned int set_list_quota;    /* Max set_list entries for this function */
+
+	/* Default RSS configuration (used by all MACs when use_rss=true) */
+	unsigned int rss_queues;
+	struct cxi_pte *ptes[64];   /* PTE pointers for RSS queues */
+	u32 hash_types;
+	unsigned int indir_entries;     /* Active indirection table size */
+
+	/* Filter tracking [0..quota-1]: enum cxi_rmu_eth_filter_mode values */
+	u8 *mac_filter_slots;
+};
+
+struct cass_ac *cass_cac_get(struct cass_dev *hw, int acid);
+void cass_cac_put(struct cass_ac *cac);
+
+/* Private hardware data for Cassini. This is not seen by clients. */
+struct cass_dev {
+	/* Embed a cxi device. */
+	struct cxi_dev cdev;
+	struct cxi_cfg_group_item *cfg_dev_dir;
+
+	/* Register base in BAR0 */
+	void __iomem *regs;
+	unsigned long regs_base;
+
+	/* /sys/class interface */
+	struct device class_dev;
+
+	/* Device type and revision */
+	union c_mb_sts_rev rev;
+	bool reduced_pct_tables;
+
+	/* TODO: For development only. Netsim VFs are not really
+	 * supported.
+	 */
+	bool with_vf_support;
+
+	/* Number of VFs currently configured in the PF. */
+	unsigned int num_vfs;
+
+	/* Interrupt vector used for the PF/ VF communication */
+	unsigned int pf_vf_vec;
+	char pf_vf_int_name[CASS_MAX_IRQ_NAME];
+	struct completion pf_to_vf_comp;
+
+	/* Virtual function communication socket for SR-IOV. Used by PF to
+	 * listen for incoming VF connections, used by VF to initiate connection
+	 */
+	struct socket *vf_req_sock;
+	struct socket *vf_notif_sock;
+	struct task_struct *vf_listener;
+	struct task_struct *vf_notif_handler;
+	u8 vf_notif_buf[MAX_VFMSG_SIZE];
+	u8 vf_notif_rsp_buf[MAX_VFMSG_SIZE];
+	struct cass_vf vfs[C_NUM_VFS];
+	cxi_msg_relay_t msg_relay;
+	void *msg_relay_data;
+	struct mutex msg_relay_lock;
+	unsigned int vf_cmd_seq;
+	/* Mutex to maintain command message/response sequencing */
+	struct mutex vf_cmd_lock;
+
+	/* PCIe info */
+	bool esm_active;
+	u8 pcie_link_speed;
+	bool pci_disabled;
+
+	struct {
+		/* Monitoring */
+		struct delayed_work task;
+
+		/* Acceptable number of correctable errors per minute */
+		unsigned int corr_err_min;
+
+		/* PCIe Vendor Specific Information position */
+		unsigned int event_counter_control;
+		unsigned int event_counter_data;
+
+		/* Number of correctable and uncorrectable errors seen. */
+		u64 uncorr_err;
+		u64 corr_err;
+	} pcie_mon;
+
+	/* Error interrupts handling. Represent each of the 30 error
+	 * interrupts by a bit in err_irq_mask.
+	 */
+	unsigned long err_irq_mask;
+	unsigned long err_irq_raised;
+	int err_irq_vecs[NUM_ERR_INTS];
+	char err_int_names[NUM_ERR_INTS][CASS_MAX_IRQ_NAME];
+	struct workqueue_struct *err_irq_wq;
+	struct work_struct err_irq_work;
+	struct kobject *err_flgs_dir_kobj[2]; /* IRQA and IRQB */
+	const struct csr_info (*err_handlers)[NUM_ERR_INTS][2];
+
+	spinlock_t sfs_err_flg_lock; /* protects mask update */
+	struct sfs_err_flg {
+		struct kobject kobj;
+
+		/* IRQ A mask for the error flag CSR. */
+		DECLARE_BITMAP(err_irq_mask, MAX_ERR_FLAG_BITLEN);
+		unsigned int bitlen;
+
+		/* Which bits must never be automatically masked */
+		union err_flags no_auto_mask;
+
+		/* Which bits must never be printed in logs. Some error bits
+		 * can be raised during normal operation (eg. UC_INTERRUPT)
+		 * and should not appear in logs.
+		 */
+		union err_flags no_print_mask;
+	} sfs_err_flg[NUM_ERR_INTS][2];
+
+	/* Clients registered with the error interrupt handler, for
+	 * certain bits
+	 */
+	struct mutex err_flg_mutex;
+	struct list_head err_flg_list;
+
+	/* Temporary storage for CSR error processing. As there is
+	 * only one work at any given time, there is no race to access
+	 * these.
+	 */
+	struct {
+		struct err_info {
+			u64 data[5];
+			int count;
+		} err_info[C_MAX_CSR_ERR_INFO];
+		unsigned int err_info_count;
+		u64 cntrs_val[C_MAX_CSR_CNTRS];
+		unsigned int err_cntrs_count;
+		char err_info_str[100];
+		DECLARE_BITMAP(first_flg, MAX_ERR_FLAG_BITLEN);
+		union c_any_err_first_flg_ts first_flg_ts;
+	};
+
+	/* Each error is rate limited. If too many interrupts happen
+	 * for the same error bit, then the bit will be permanently
+	 * masked.
+	 */
+	struct ratelimit_state err_rl[NUM_ERR_INTS][MAX_ERR_FLAG_BITLEN];
+
+	/* Debugfs directories for that device */
+	struct dentry *debug_dir;
+	struct dentry *port_dir;
+	struct dentry *stats_dir;
+	struct dentry *lni_dir;
+	struct dentry *atu_dir;
+	struct dentry *decouple_dir;
+
+	/* Count users of this device. */
+	refcount_t refcount;
+
+	/* Keep track of NIs. TODO: keep as that may help debugging,
+	 * but should be removed eventually.
+	 */
+	struct list_head lni_list;
+	spinlock_t lni_lock;
+
+	struct {
+		atomic_t lni;
+		atomic_t domain;
+		atomic_t eq;
+		atomic_t txq;
+		atomic_t tgq;
+		atomic_t pt;
+		atomic_t ct;
+		atomic_t ac;
+		atomic_t md;
+	} stats;
+
+	struct dentry *domain_dir;
+	struct dentry *eq_dir;
+	struct dentry *cq_dir;
+	struct dentry *pt_dir;
+	struct dentry *ct_dir;
+	struct dentry *ac_dir;
+
+	/* Pending LNI cleanups */
+	struct list_head lni_cleanups_list;
+	struct delayed_work lni_cleanups_work;
+	struct mutex lni_cleanups_lock;
+
+	/* Number of IRQs available to that device. */
+	unsigned int num_irqs;
+
+	unsigned int atu_cq_vec;
+	unsigned int atu_pri_vec;
+
+	/* Completion IRQs */
+	unsigned int num_comp_irqs;
+	struct cass_irq *comp_irqs;
+
+	/* RMU table allocation bitmap. Each entry in the RMU table
+	 * contains a different VNI.
+	 */
+	struct ida rmu_index_table;
+	struct ida domain_table;
+	spinlock_t rmu_lock;
+	struct rb_root rmu_tree;
+
+	/* Physical PID leases and per-profile use counts are protected by
+	 * pid_pool_lock. domain_lock protects unique VNI+PID domain identities.
+	 */
+	spinlock_t pid_pool_lock;
+	spinlock_t domain_lock;
+	struct rb_root domain_tree;
+	DECLARE_BITMAP(leased_pids, 1 << MAX_PID_BITS);
+	u32 pid_usecount[1 << MAX_PID_BITS];
+
+	/* EQ allocation bitmap */
+	spinlock_t eq_shadow_lock;
+	struct ida eq_index_table;
+	struct mutex init_eq_hw_state;
+
+	/* Which EQ is registered with the PCT block. Protected by
+	 * init_eq_hw_state.
+	 */
+	unsigned int pct_eq_n;
+
+	/* Communication Profile Table (CPT) and containers. The table,
+	 * cpt_index_table, resides on the adapter and is used to reserve
+	 * one of the hardware resource. The RB tree, cp_cont_tree, is used to
+	 * store the allocated communication containers. Each container is
+	 * identified by a VNI and traffic class. Each container may contain
+	 * multiple communication profiles which map to an index in the CPT.
+	 * The lock, cp_lock, protects the tree.
+	 */
+	struct ida cp_table;
+	struct mutex cp_lock;
+
+	/* Configured traffic classes; entries can be added and removed at run time. */
+	struct list_head tc_list;
+	struct mutex tc_lock;	/* protects tc_list */
+
+	/* Next resource to be used for traffic class configuration. */
+	unsigned int next_oxe_bc;
+	unsigned int next_oxe_branch_bucket;
+	unsigned int next_oxe_leaf_bucket;
+	unsigned int next_cq_tc;
+	unsigned int next_cq_ocuset;
+	unsigned int next_cq_ocu;
+	unsigned int next_ixe_wrq;
+	unsigned int next_ixe_fq;
+	unsigned int next_lpe_fq;
+
+	u8 tsc_fill_qty;
+	struct qos_profile qos;
+	struct kobject tcs_kobj;
+
+	/* CQ allocation bitmaps. */
+	spinlock_t cq_shadow_lock;
+	struct mutex cq_init_lock;
+	struct ida cq_table;
+
+	/* CT allocations */
+	struct mutex ct_init_lock;
+
+	/* Multicast uniqueness table */
+	struct ida multicast_table;
+
+	/* PT allocation bitmap */
+	spinlock_t lpe_shadow_lock;
+	struct ida pte_table;
+	struct ida pt_index_table;
+	unsigned int dmac_pt_id;
+	struct mutex mst_table_lock;
+	struct mutex pte_transition_sm_lock;
+	union c_mst_dbg_mst_table *mst_entries;
+	dma_addr_t mst_entries_dma_addr;
+	atomic_t plec_count;
+
+	/* LE pool allocation bitmap */
+	struct ida le_pool_ids[C_PE_COUNT];
+	struct ida tle_pool_ids;
+
+	/* Ethernet Set List */
+	struct ida set_list_table;
+	struct cxi_tx_profile eth_tx_profile;
+
+	/* RMU Ethernet resource management */
+	struct idr rmu_eth_idr;
+
+	/* Protects all RMU Eth resources */
+	struct mutex rmu_eth_lock;
+
+	/* Protects C_RMU_CFG_PORTAL_LIST_X/Y. */
+	spinlock_t rmu_portal_list_lock;
+
+	/* RGID management */
+	struct xarray rgid_array;
+	refcount_t rgids_refcount;
+	struct ida lni_table;
+
+	/* ATU info */
+	void *oxe_dummy_addr;
+	dma_addr_t oxe_dummy_dma_addr;
+	struct cass_ac *cac_table[C_ATU_CFG_AC_TABLE_ENTRIES];
+	/* Protects AC publication and acquisition of reader pins. */
+	spinlock_t cac_table_lock;
+	struct ida atu_table;
+	struct cass_atu_cq atu_cq;
+	spinlock_t atu_shadow_lock;
+	atomic_t atu_error_inject;
+	atomic_t atu_odp_requests;
+	atomic_t atu_odp_fails;
+	atomic_t atu_prb_expired;
+	char odp_pri_int_name[CASS_MAX_IRQ_NAME];
+	int pri_rd_ptr;
+	struct work_struct pri_work;
+	struct workqueue_struct *pri_wq;
+	struct c_page_request_entry *page_request_table;
+	dma_addr_t prt_dma_addr;
+	struct cxi_reg_err_flg atu_err;
+	struct work_struct prb_work;
+	struct workqueue_struct *prb_wq;
+	struct mutex odpq_mutex;
+	struct list_head mm_lni_list;
+	struct mutex mm_mutex;
+	struct ida md_index_table;
+	bool ac_filter_disabled;
+	/* Flag to indicate that the IOMMU callback is in place to support
+	 * C1 ODP.
+	 */
+	bool ats_c1_odp_enable;
+
+	/* Number of invalidations due to memory deregistration */
+	atomic_t dcpl_md_clear_inval;
+	/* Number of invalidations due to the mmu notifier for NTA mode */
+	atomic_t dcpl_nta_mn_inval;
+	/* Number of invalidations due to the mmu notifier (via IOMMU callback)
+	 * for ATS mode
+	 */
+	atomic_t dcpl_ats_mn_inval;
+	/* Completion wait count */
+	atomic_t dcpl_comp_wait;
+	/* ODP decoupling entered - Completion wait has timed out */
+	atomic_t dcpl_entered;
+	/* ixe_epoch_x_cntr was 0 */
+	atomic_t dcpl_ixe_cntr_0;
+	/* ixe_epoch_x_cntr was not initially 0 but it decremented to 0 */
+	atomic_t dcpl_ixe_cntr_dec_0;
+	/* ee_epoch_x_cntr count of entering dec loop */
+	atomic_t dcpl_ee_cntr_dec_0;
+	/* ee_epoch_x_cntr is stuck */
+	atomic_t dcpl_ee_cntr_stuck;
+	/* oxe_epoch_x_cntr count of entering dec loop */
+	atomic_t dcpl_oxe_cntr_dec_0;
+	/* oxe_epoch_x_cntr is stuck */
+	atomic_t dcpl_oxe_cntr_stuck;
+	/* ixe_epoch_x_cntr is stuck after hw decoupling enabled */
+	atomic_t dcpl_ixe_cntr_stuck;
+	/* decouple process successful after hw decoupling enabled */
+	atomic_t dcpl_success;
+	/* ib_epoch_x_cntr decremented to 0 in step 6.2 */
+	atomic_t dcpl_ibw_cntr_dec_0_62;
+	/* ib_epoch_x_cntr count of dec loops in step 6.2 */
+	atomic_t dcpl_ibw_cntr_dec_0_62_count;
+	/* ib_epoch_x_cntr decremented to 0 in step 6.4 */
+	atomic_t dcpl_ibw_cntr_dec_0_64;
+	/* ib_epoch_x_cntr count of dec loops in step 6.4 */
+	atomic_t dcpl_ibw_cntr_dec_0_64_count;
+	/* ib_epoch_x_cntr is stuck */
+	atomic_t dcpl_step7;
+	/* IBW is active and ib_epoch_x_cntr is stuck */
+	atomic_t dcpl_ibw_active_stuck;
+	/* How long waiting to get the lock */
+	atomic_t dcpl_ibw_idle_wait;
+	/* IBW counter is inside of trylock loop */
+	atomic_t dcpl_ibw_cntr_is_0;
+	/* Decouple issued inbound wait */
+	atomic_t dcpl_ibw_issued;
+	/* Maximum time spent in decoupling */
+	ktime_t dcpl_max_time;
+	/* Histogram of time spent in decoupling */
+	#define DBINS 12
+	#define FIRST_BIN (64 * 1024)
+	int dcpl_time[DBINS];
+	/* Maximum time spent finding an MD */
+	ktime_t pri_max_md_time;
+	/* Histogram of time spent in finding MD during a fault */
+	#define MDBINS 8
+	#define FIRST_MDBIN (8 * 1024)
+	int pri_md_time[MDBINS];
+	/* Maximum time spent servicing a fault */
+	ktime_t pri_max_fault_time;
+	/* Histogram of time spent servicing a fault */
+	#define FBINS 7
+	#define FIRST_FBIN (8 * 1024)
+	int pri_fault_time[FBINS];
+
+	/* Counting event bitmap. */
+	struct ida ct_table;
+
+	/* Precision Time Protocol Clock */
+	struct ptp_clock_info ptp_info;
+	struct ptp_clock *ptp_clock;
+	spinlock_t rtc_lock;
+
+	/* MST locks. */
+	spinlock_t mst_match_done_lock;
+	struct mutex mst_update_lock;
+
+	/* Micro-controller */
+	bool uc_present;
+	int uc_platform;	/* CUC_BOARD_TYPE_xxx */
+	struct cxi_reg_err_flg uc_err;
+	struct completion uc_attention0_comp;
+	struct cuc_pkt uc_req;
+	struct cuc_pkt uc_resp;
+	struct workqueue_struct *uc_attn1_wq;
+	struct work_struct uc_attn1_work;
+	struct mutex uc_mbox_mutex;
+	struct i2c_adapter uc_i2c;
+	bool uc_i2c_locked;
+	s8 uc_nic;		/* NIC index from uC point of view */
+	u8 default_mac_addr[ETH_ALEN];
+	struct kobject uc_kobj;
+	char *fw_versions[7];	/* indexed by enum casuc_fw_target */
+	bool fru_info_valid;	/* FRU query was successful; do not query again. */
+	char *fru_info[PLDM_FRU_FIELD_VENDOR_IANA + 1];
+	struct idr pldm_sensors;
+	unsigned int pldm_sensors_count;
+	struct kobject *pldm_sensors_kobj;
+	unsigned int uc_dmac_id;
+	struct kobject port_kobj;
+	struct kobject port_num_kobj;
+	bool qsfp_beacon_active;
+	bool qsfp_over_temp;
+	bool qsfp_bad;
+
+	/* HW mon */
+	struct {
+		struct device *dev;
+		struct hwmon_chip_info chip_info;
+		const struct hwmon_channel_info *all_types[hwmon_max];
+
+		struct hwmon_channel_info info[5];
+
+		/* Enough room for 30 sensors. */
+		u32 config[CASS_MAX_SENSORS + hwmon_max];
+	} hwmon;
+
+	/* RX and TX Profiles */
+	struct cxi_rxtx_profile_list rx_profile_list;
+	struct cxi_rxtx_profile_list tx_profile_list;
+	struct mutex tx_profile_get_lock;
+	struct mutex rx_profile_get_lock;
+
+	/* Services */
+	struct mutex svc_lock;
+	struct idr svc_ids;
+	struct dentry *svc_debug;
+	struct list_head svc_list;
+	unsigned int svc_count;
+	struct cxi_resource_use resource_use[CXI_RESOURCE_MAX];
+	spinlock_t rgrp_lock;
+
+	/* Resource Groups */
+	struct cxi_rgroup_list rgroup_list;
+
+	/* HNI */
+	struct cxi_reg_err_flg hni_pause_err;
+	struct work_struct pause_timeout_work;
+	struct cxi_reg_err_flg hni_uncor_err;
+	struct cxi_reg_err_flg hni_pml_uncor_err;
+
+	/* IXE */
+	struct cxi_reg_err_flg ixe_pbuf_rd_err;
+
+	/* PML */
+	struct cxi_reg_err_flg pml_err;
+	struct {
+		spinlock_t lock;
+		enum cass_phy_state state;
+		struct delayed_work state_queue;
+		/* protected by lock; bumped by every non-worker transition */
+		unsigned int generation;
+		bool stopped;
+	} phy;
+
+	u32 max_eth_rxsize;
+
+	/* Ethernet TX timestamp shift. 0 to 3, stays at zero but
+	 * could become a kernel parameter.
+	 */
+	int tx_timestamp_shift;
+
+	/* base link support */
+	struct sbl_inst *sbl;           /* slingshot base-link instance */
+	atomic_t *sbl_counters;         /* sbl link counters */
+	bool link_config_dirty;         /* link config != running config */
+	spinlock_t sbl_state_lock;      /* link state lock */
+	struct cass_port *port;         /* port db array */
+	const struct cxi_link_ops *link_ops;
+
+	/* SBus config */
+	struct mutex sbus_mutex;      /* serialise SBus config accesses */
+
+	/* Rendezvous get control config */
+	struct mutex get_ctrl_mutex;  /* serialize writes from sysfs */
+
+	/* AMO remap sysfs mutex. */
+	struct mutex amo_remap_to_pcie_fadd_mutex;
+
+	/* sysfs support */
+	struct kobject properties_kobj;
+	struct kobject fru_kobj;
+	struct kobject link_restarts_kobj;
+
+	/* debugfs support */
+	struct attribute_group  port_group;
+	struct attribute        **port_attrs;
+	struct device_attribute *port_dev_attrs;
+	struct device_attribute port_attr;
+
+	/* Current copy of the QSFP eeprom, with its length. If length
+	 * is 0, the data is not valid.
+	 */
+	struct mutex qsfp_eeprom_lock;
+	u8 qsfp_eeprom_page0[ETH_MODULE_SFF_8436_LEN];
+	u8 qsfp_eeprom_page1[ETH_MODULE_SFF_8436_LEN];
+	u8 qsfp_format;
+	unsigned int qsfp_eeprom_page_len;
+
+	/*
+	 * telemetry for cassini
+	 */
+	struct {
+		struct telem_info	*info;
+	} telemetry;
+
+	/*
+	 * dma controller
+	 */
+	struct {
+		struct mutex			lock;
+		struct completion		irupt;
+		char				irupt_name[CASS_MAX_IRQ_NAME];
+		struct c_pi_dmac_cdesc		*cpl_desc;
+		dma_addr_t                      cpl_desc_dma_addr;
+		struct dmac_desc_set		*desc_sets;
+		unsigned long			*desc_map;
+	} dmac;
+
+	/* sl */
+	struct cass_sl_dev sl;
+
+	/*auxiliary device*/
+	void *cxi_adev;
+	/*
+	 * Protects the publication of cxi_adev and covers every use of it, so
+	 * the auxiliary device cannot be freed while a NID change is being
+	 * sent to it.
+	 */
+	struct mutex cxi_adev_lock;
+};
+
+static inline struct cass_dev *cxi_to_cass_dev(struct cxi_dev *dev)
+{
+	return container_of(dev, struct cass_dev, cdev);
+}
+
+/* Communication profile. */
+struct cass_cp {
+	struct cass_dev *hw;
+	struct cxi_tx_profile *tx_profile;
+
+	/* VNI/PCP and TC identify a unique communication profile. */
+	unsigned int vni_pcp;
+	enum cxi_traffic_class tc;
+	enum cxi_traffic_class_type tc_type;
+
+	/* Communication profile table ID. */
+	unsigned int id;
+
+	/* CP list ID. */
+	unsigned int list_id;
+
+	/* Number of users of this profile. */
+	refcount_t ref;
+};
+
+struct pldm_sensor {
+	struct cass_dev *hw;
+	unsigned int id;
+	struct kobject kobj;
+	char name[AUX_NAME_MAX];
+	struct numeric_sensor_pdr num;
+
+	/* Mapping when inserted into hwmon */
+	struct {
+		enum hwmon_sensor_types type;
+		int channel;
+		int multiplier;
+	} hwmon;
+};
+
+/* From struct getsensorreading_rsp */
+struct pldm_sensor_reading {
+	u8 operational_state;
+	u8 present_state;
+	u8 previous_state;
+	s64 present_reading;
+};
+
+/* Read one of the fields from a PLDM declaration */
+#define get_pldm_value(sensor, field) ({				\
+	const int s = sensor->num.sensor_data_size;			\
+	s64 value;							\
+									\
+	if (s == PLDM_DATA_SIZE_UINT8 || s == PLDM_DATA_SIZE_SINT8)	\
+		value = sensor->num.ssd.ssd8.field;			\
+	else if (s == PLDM_DATA_SIZE_UINT16 ||				\
+		 s == PLDM_DATA_SIZE_SINT16)				\
+		value = sensor->num.ssd.ssd16.field;			\
+	else								\
+		value = sensor->num.ssd.ssd32.field;			\
+									\
+	value;								\
+})
+
+static inline void __iomem *cass_csr(struct cass_dev *hw, u64 offset)
+{
+	BUG_ON(offset > C_MEMORG_CSR_SIZE);
+	return hw->regs + offset;
+}
+
+/**
+ * cass_clear() - Writes zeroes to a CSR
+ *
+ * @hw: the device
+ * @offset: offset of the CSR in the region
+ * @len: length to clear, in bytes. Must be a multiple of 8.
+ */
+static inline void cass_clear(struct cass_dev *hw, u64 offset, size_t len)
+{
+	void __iomem *base = cass_csr(hw, offset);
+	int i;
+
+	len /= sizeof(u64);
+
+	for (i = 0; i < len; i++, base += sizeof(u64))
+		writeq(0, base);
+}
+
+/* must come after cass_read/write/clear definitions. */
+#include <linux/hpe/cxi/libcassini.h>
+
+static inline bool cass_version(const struct cass_dev *hw,
+				enum cassini_version version)
+{
+	return cassini_version(&hw->cdev.prop, version);
+}
+
+static inline void cass_cond_lock(struct mutex *lock, bool need_lock)
+{
+	if (need_lock)
+		mutex_lock(lock);
+}
+
+static inline void cass_cond_unlock(struct mutex *lock, bool need_lock)
+{
+	if (need_lock)
+		mutex_unlock(lock);
+}
+
+static inline void cass_cp_lock(struct cass_dev *hw)
+{
+	mutex_lock(&hw->cp_lock);
+}
+
+static inline void cass_cp_unlock(struct cass_dev *hw)
+{
+	mutex_unlock(&hw->cp_lock);
+}
+
+static const char * const cxi_tc_strs[] = {
+	[CXI_TC_DEDICATED_ACCESS]       = "DEDICATED_ACCESS",
+	[CXI_TC_LOW_LATENCY]            = "LOW_LATENCY",
+	[CXI_TC_BULK_DATA]              = "BULK_DATA",
+	[CXI_TC_BEST_EFFORT]            = "BEST_EFFORT",
+	[CXI_TC_ETH]                    = "ETH",
+};
+
+static const char * const cxi_tc_type_strs[] = {
+	[CXI_TC_TYPE_DEFAULT] = "DEFAULT",
+	[CXI_TC_TYPE_HRP] = "HRP",
+	[CXI_TC_TYPE_RESTRICTED] = "RESTRICTED",
+	[CXI_TC_TYPE_COLL_LEAF] = "COLL_LEAF",
+};
+
+static inline const char *cxi_tc_to_str(enum cxi_traffic_class tc)
+{
+	if (tc >= CXI_TC_DEDICATED_ACCESS && tc < CXI_TC_MAX)
+		return cxi_tc_strs[tc];
+	return "(invalid)";
+}
+
+static inline
+const char *cxi_tc_type_to_str(enum cxi_traffic_class_type tc_type)
+{
+	if (tc_type >= CXI_TC_TYPE_DEFAULT && tc_type < CXI_TC_TYPE_MAX)
+		return cxi_tc_type_strs[tc_type];
+	return "(invalid)";
+}
+
+static const char * const cxi_rsrc_type_strs[] = {
+	[CXI_RSRC_TYPE_PTE] = "PTEs",
+	[CXI_RSRC_TYPE_TXQ] = "TXQs",
+	[CXI_RSRC_TYPE_TGQ] = "TGQs",
+	[CXI_RSRC_TYPE_EQ] = "EQs",
+	[CXI_RSRC_TYPE_CT] = "CTs",
+	[CXI_RSRC_TYPE_LE] = "LEs",
+	[CXI_RSRC_TYPE_TLE] = "TLEs",
+	[CXI_RSRC_TYPE_AC] = "ACs",
+};
+
+static inline
+const char *cxi_rsrc_type_to_str(enum cxi_rsrc_type rsrc_type)
+{
+	if (rsrc_type >= CXI_RSRC_TYPE_PTE && rsrc_type < CXI_RSRC_TYPE_MAX)
+		return cxi_rsrc_type_strs[rsrc_type];
+	return "(invalid)";
+}
+
+int cass_ixe_set_amo_remap_to_pcie_fadd(struct cass_dev *hw, int amo_remap);
+void cass_pte_init(struct cass_dev *hw);
+void cass_pte_set_get_ctrl(struct cass_dev *hw);
+int cass_atu_init(struct cass_dev *hw);
+void cass_atu_fini(struct cass_dev *hw);
+void cass_acs_disable(struct cxi_lni_priv *lni_priv);
+void cass_acs_free(struct cxi_lni_priv *lni_priv);
+int cass_ac_phys_alloc(struct cass_dev *hw, bool vf_en, int vf_num);
+void cass_ac_phys_free(struct cass_dev *hw, int acid);
+
+void cass_cq_init(struct cass_dev *hw);
+void cass_ee_init(struct cass_dev *hw);
+int cass_svc_init(struct cass_dev *hw);
+void cass_svc_fini(struct cass_dev *hw);
+int cass_tc_find(struct cass_dev *hw, enum cxi_traffic_class tc,
+		 enum cxi_traffic_class_type tc_type, u8 ethernet_pcp,
+		 struct cass_tc_cfg *tc_cfg);
+int cass_tc_init(struct cass_dev *hw);
+void cass_tc_fini(struct cass_dev *hw);
+void traffic_shaping_cfg(struct cass_dev *hw);
+void cass_tc_set_tx_pause_all(struct cass_dev *hw, bool enable);
+void cass_tc_set_rx_pause_all(struct cass_dev *hw, bool enable);
+void cass_clear_cps(struct cxi_tx_profile *tx_profile);
+
+static inline bool is_vni_valid(unsigned int vni)
+{
+	/* A VNI is 16 bits and VNI 0 is invalid */
+	return vni && !(vni & ~0xffff);
+}
+
+int register_error_handlers(struct cass_dev *hw);
+void deregister_error_handlers(struct cass_dev *hw);
+int cass_sriov_configure(struct pci_dev *pdev, int num_vfs);
+int cass_vf_init(struct cass_dev *hw);
+void cass_vf_fini(struct cass_dev *hw);
+
+#define ATU_CFG_AC_TABLE_MB_SHIFT 15
+/* Based on note in MEM_SIZE description - MEM_BASE must be aligned to
+ * 8x the largest configured page size.
+ * Derivative 1 Page Size as described in Table 364 - Page Table Sizes
+ */
+#define ATU_IOVA_BASE_SHIFT(ac) (12 + ac.base_pg_size + ac.pg_table_size + 3)
+#define ATU_IOVA_MASK(ac) (~MASK(ATU_IOVA_BASE_SHIFT(ac)))
+/* Maximum addressable memory range (56 bits) of Cassini. */
+#define ATU_MAX_ADDR_MEM_BITS 56
+#define ATU_LAC_SHIFT (ATU_MAX_ADDR_MEM_BITS - 3)
+#define ATU_VA_MASK(va) (va & MASK(ATU_MAX_ADDR_MEM_BITS))
+#define IS_DEVICE_MEM(md_priv) (md_priv->flags & CXI_MAP_DEVICE)
+
+extern struct mutex dev_list_mutex;
+extern int more_debug;
+extern struct genl_family cxierr_genl_family;
+extern struct cass_p2p_ops p2p_ops;
+extern bool odp_sw_decouple;
+extern bool ats_c1_override;
+
+/* Add the LAC to the top 3 bits of the IOVA so they are unique */
+static inline u64 cass_iova_base(struct cass_ac *cac)
+{
+	u64 iova_base;
+
+	iova_base = (u64)get_random_u32() << ATU_IOVA_BASE_SHIFT(cac->cfg_ac);
+	iova_base &= ~(0x7UL << ATU_LAC_SHIFT);
+	iova_base |= (u64)cac->ac.lac << ATU_LAC_SHIFT;
+
+	return iova_base;
+}
+
+void __iomem *cass_csr(struct cass_dev *hw, u64 offset);
+int cass_nta_cq_init(struct cass_dev *hw);
+void cass_nta_cq_fini(struct cass_dev *hw);
+int cass_nta_pri_init(struct cass_dev *hw);
+int cass_sts_idle(struct sts_idle *sidle);
+void cass_nta_pri_fini(struct cass_dev *hw);
+int cass_inbound_wait(struct cass_dev *hw, bool wait_for_response);
+u64 cass_nta_iova_alloc(struct cass_ac *cac, const struct ac_map_opts *m_opts);
+void cass_nta_iova_fini(struct cass_ac *cac);
+int cass_nta_iova_init(struct cass_ac *cac, size_t va_len);
+void cass_nta_free(struct cass_dev *hw, struct cass_nta *nta);
+void cass_l1_tables_free(struct cass_dev *hw, struct cass_nta *nta);
+void cass_clear_range(const struct cxi_md_priv *md_priv, u64 iova, u64 len);
+void cass_md_clear(struct cxi_md_priv *md_prv, bool inval, bool need_lock);
+void cass_dma_unmap_pages(struct cxi_md_priv *md_priv);
+int cass_dma_addr_mirror(dma_addr_t dma_addr, u64 iova, struct cass_ac *cac,
+			 u32 flags, bool is_huge_page, bool *invalidate);
+int cass_mirror_fault(const struct ac_map_opts *m_opts, u64 *pfns, int count,
+		      uintptr_t addr, size_t len);
+int cass_mirror_odp(const struct ac_map_opts *m_opts, struct cass_ac *cac,
+		    int npfns, u64 addr);
+int cass_mirror_device(struct cxi_md_priv *md_priv,
+		       const struct ac_map_opts *m_opts);
+int cass_mirror_range(struct cxi_md_priv *md_priv, struct ac_map_opts *m_opts);
+void cass_invalidate_range(const struct cass_ac *cac, u64 iova,
+			   size_t length);
+int cass_nta_init(struct cxi_lni_priv *lni_priv, struct ac_map_opts *m_opts,
+		  struct cass_ac *cac);
+int cass_nta_mirror_sgt(struct cxi_md_priv *md_priv, bool need_lock);
+int cass_nta_mirror_kern(struct cxi_md_priv *md_priv,
+			 const struct iov_iter *iter, bool need_lock);
+int cass_pin(const struct cass_ac *cac, struct page **pages, int npages,
+	     u64 addr, bool write);
+int cass_mirror_hp(const struct ac_map_opts *m_opts, struct cxi_md_priv *md_priv);
+int cass_pfns_mirror(struct cxi_md_priv *md_priv, const struct ac_map_opts *m_opts,
+		     u64 *pfns, int npfns, bool is_huge_page);
+int cass_vma_write_flag(struct mm_struct *mm, ulong start, ulong end,
+			u32 flags);
+int cass_pin_mirror(struct cxi_md_priv *md_priv, struct ac_map_opts *m_opts);
+void cass_notifier_cleanup(struct cxi_md_priv *md_priv);
+int cass_odp_decouple(struct cass_dev *hw);
+int cass_odp_supported(struct cass_dev *hw, u32 flags);
+int cass_mmu_notifier_insert(struct cxi_md_priv *md_priv,
+			     const struct ac_map_opts *m_opts);
+void cass_device_hugepage_size(int contig_cnt, struct ac_map_opts *m_opts);
+void cass_align_start_len(struct ac_map_opts *m_opts, uintptr_t va, size_t len,
+			  int align_shift);
+int cass_cpu_page_size(struct cass_dev *hw, struct ac_map_opts *m_opts,
+		       struct mm_struct *mm, uintptr_t va,
+		       const struct cxi_md_hints *hints, int *align_shift);
+int cass_ptp_init(struct cass_dev *hw);
+void cass_ptp_fini(struct cass_dev *hw);
+int cass_ats_init(struct cxi_lni_priv *lni_priv, struct ac_map_opts *m_opts,
+		  struct cass_ac *cac);
+int cass_ats_md_init(struct cxi_md_priv *md_priv, const struct ac_map_opts *m_opts);
+void cass_amd_iommu_inval_cb_init(struct pci_dev *pdev);
+void cass_unbind_ac(struct cass_dev *hw, const struct cass_ac *cac);
+void cass_iommu_init(struct cass_dev *hw);
+void cass_iommu_fini(struct cass_dev *hw);
+
+void cass_hni_init(struct cass_dev *hw);
+void cass_hni_fini(struct cass_dev *hw);
+int cass_cable_scan(struct cass_dev *hw);
+void update_oxe_link_up(struct cass_dev *hw);
+void update_hni_link_up(struct cass_dev *hw);
+int cass_create_tc_sysfs(struct cass_dev *hw);
+void cass_destroy_tc_sysfs(struct cass_dev *hw);
+
+int cass_ixe_init(struct cass_dev *hw);
+void cass_ixe_fini(struct cass_dev *hw);
+
+int cass_register_uc(struct cass_dev *hw);
+void cass_unregister_uc(struct cass_dev *hw);
+int cass_register_port(struct cass_dev *hw);
+void cass_unregister_port(struct cass_dev *hw);
+int uc_cmd_get_nic_id(struct cass_dev *hw);
+int uc_cmd_get_mac(struct cass_dev *hw);
+int uc_cmd_get_fru(struct cass_dev *hw);
+void uc_cmd_update_ier(struct cass_dev *hw, u32 set_bits, u32 clear_bits);
+int uc_cmd_qsfp_write(struct cass_dev *hw, u8 page, u8 addr,
+		      const u8 *data, size_t data_len);
+void uc_prepare_comm(struct cass_dev *hw);
+int uc_wait_for_response(struct cass_dev *hw);
+int cxi_get_qsfp_data(struct cxi_dev *cdev, u32 offset,
+		      u32 len, u32 page, u8 *data);
+void uc_cmd_set_link_leds(struct cass_dev *hw, enum casuc_led_states led_state);
+int update_sensor(struct pldm_sensor *sensor,
+		  struct pldm_sensor_reading *result);
+
+void finalize_pt_cleanups(struct cxi_lni_priv *lni, bool force);
+void finalize_cq_cleanups(struct cxi_lni_priv *lni, bool force);
+void finalize_eq_cleanups(struct cxi_lni_priv *lni);
+void finalize_ct_cleanups(struct cxi_lni_priv *lni);
+bool lni_cleanups(struct cass_dev *hw, bool force);
+void lni_cleanups_work(struct work_struct *work);
+void cass_rgid_init(struct cass_dev *hw);
+void cass_rgid_fini(struct cass_dev *hw);
+int cass_lac_get(struct cass_dev *hw, int id);
+void cass_lac_put(struct cass_dev *hw, int id, int lac);
+int cass_rgid_get(struct cass_dev *hw, struct cxi_rgroup *rgroup);
+void cass_rgid_put(struct cass_dev *hw, int id);
+int cass_lcid_get(struct cass_dev *hw, struct cxi_cp_priv *cp_priv, int rgid,
+		  enum cxi_trig_cp cp_type);
+void cass_lcid_put(struct cass_dev *hw, int rgid, int lcid);
+struct cxi_cp_priv *cass_cp_find(struct cass_dev *hw, int rgid, int lcid);
+struct cxi_cp_priv *cass_cp_rgid_find(struct cass_dev *hw,
+				      struct cxi_lni_priv *lni_priv,
+				      unsigned int vni_pcp, unsigned int tc,
+				      enum cxi_traffic_class_type tc_type,
+				      enum cxi_trig_cp cp_type);
+
+int get_dma_addr_if_contig(struct cass_dev *hw, void *addr, size_t len,
+			   enum dma_data_direction dir, struct page ***pages,
+			   dma_addr_t *dma_addr);
+
+int cass_telem_init(struct cass_dev *hw);
+void cass_telem_fini(struct cass_dev *hw);
+
+int create_sysfs_properties(struct cass_dev *hw);
+void destroy_sysfs_properties(struct cass_dev *hw);
+
+void cass_phy_init(struct cass_dev *hw);
+void cass_phy_start(struct cass_dev *hw, bool force_reconfig);
+void cass_phy_stop(struct cass_dev *hw, bool block);
+void cass_phy_bounce(struct cass_dev *hw);
+void cass_phy_trigger_machine(struct cass_dev *hw);
+void cass_phy_link_up(struct cass_dev *hw);
+void cass_phy_link_down(struct cass_dev *hw);
+
+extern unsigned int pe_total_les;
+void cass_cfg_le_pools(struct cass_dev *hw, int pool_id, int pe,
+		       const struct cxi_limits *les, bool release);
+void cass_cfg_tle_pool(struct cass_dev *hw, int pool_id,
+		       const struct cxi_limits *tles, bool release);
+void cass_tle_init(struct cass_dev *hw);
+
+int cass_dmac_init(struct cass_dev *hw);
+void cass_dmac_fini(struct cass_dev *hw);
+
+int cass_irq_init(struct cass_dev *hw);
+void cass_irq_fini(struct cass_dev *hw);
+struct cass_irq *cass_comp_irq_attach(struct cass_dev *hw,
+				      const struct cpumask *mask,
+				      struct notifier_block *nb);
+void cass_comp_irq_detach(struct cass_dev *hw, struct cass_irq *irq,
+			  struct notifier_block *nb);
+
+void cxi_register_hw_errors(struct cass_dev *hw,
+			    struct cxi_reg_err_flg *reg_err_flg);
+void cxi_unregister_hw_errors(struct cass_dev *hw,
+			      struct cxi_reg_err_flg *reg_err_flg);
+void cxi_enable_hw_errors(struct cass_dev *hw, unsigned int irq, bool is_ext,
+			  const unsigned long *bitmask);
+void cxi_disable_hw_errors(struct cass_dev *hw, unsigned int irq, bool is_ext,
+			   const unsigned long *bitmask);
+
+bool cass_phy_is_headshell_removed(struct cass_dev *hw);
+void cass_phy_set_state(enum cass_phy_state state, struct cass_dev *hw);
+
+void start_pcie_monitoring(struct cass_dev *hw);
+void stop_pcie_monitoring(struct cass_dev *hw);
+void cass_set_outstanding_limit(struct cass_dev *hw);
+
+void cass_disable_device(struct pci_dev *pdev, const char *reason);
+extern bool disable_on_error;
+void uncor_cb(struct cass_dev *hw, unsigned int irq, bool is_ext,
+	      unsigned int bitn);
+
+#endif	/* _CASS_CORE_H */
diff --git a/drivers/net/ethernet/hpe/ss1/cass_dev_info.c b/drivers/net/ethernet/hpe/ss1/cass_dev_info.c
new file mode 100644
index 000000000000..15f3e49fe380
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_dev_info.c
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2024 Hewlett Packard Enterprise Development LP */
+
+#include "cass_core.h"
+
+int cxi_dev_info_get(struct cxi_dev *dev,
+		     struct cxi_dev_info_use *devinfo)
+{
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+	int speed;
+	int state;
+
+	devinfo->nid = hw->cdev.prop.nid;
+	devinfo->pid_bits = hw->cdev.prop.pid_bits;
+	devinfo->pid_count = hw->cdev.prop.pid_count;
+	devinfo->pid_granule = hw->cdev.prop.pid_granule;
+	devinfo->min_free_shift = hw->cdev.prop.min_free_shift;
+	devinfo->rdzv_get_idx = hw->cdev.prop.rdzv_get_idx;
+	devinfo->device_rev = hw->cdev.prop.device_rev;
+	devinfo->device_proto = hw->cdev.prop.device_proto;
+	devinfo->device_platform = hw->cdev.prop.device_platform;
+	devinfo->vendor_id = hw->rev.vendor_id;
+	devinfo->device_id = hw->rev.device_id;
+	devinfo->pct_eq = hw->pct_eq_n;
+	devinfo->uc_nic = hw->uc_nic;
+	devinfo->link_mtu = C_MAX_HPC_MTU;
+	devinfo->num_ptes = hw->cdev.prop.rsrcs.ptes.max;
+	devinfo->num_txqs = hw->cdev.prop.rsrcs.txqs.max;
+	devinfo->num_tgqs = hw->cdev.prop.rsrcs.tgqs.max;
+	devinfo->num_eqs = hw->cdev.prop.rsrcs.eqs.max;
+	devinfo->num_cts = hw->cdev.prop.rsrcs.cts.max;
+	devinfo->num_acs = hw->cdev.prop.rsrcs.acs.max;
+	devinfo->num_tles = hw->cdev.prop.rsrcs.tles.max;
+	devinfo->num_les = hw->cdev.prop.rsrcs.les.max;
+	devinfo->cassini_version = hw->cdev.prop.cassini_version;
+	devinfo->system_type_identifier = hw->cdev.system_type_identifier;
+
+	if (hw->port)
+		cass_sbl_link_mode_to_speed(hw->port->lattr.bl.link_mode, &speed);
+	else
+		speed = 0;
+	devinfo->link_speed = speed;
+
+	state = hw->phy.state == CASS_PHY_RUNNING;
+	devinfo->link_state = state;
+
+	if (!hw->fru_info_valid)
+		uc_cmd_get_fru(hw);
+
+	if (hw->fru_info[PLDM_FRU_FIELD_DESCRIPTION])
+		strscpy(devinfo->fru_description, hw->fru_info[PLDM_FRU_FIELD_DESCRIPTION],
+			sizeof(devinfo->fru_description) - 1);
+	else
+		strscpy(devinfo->fru_description, "Not Available",
+			sizeof(devinfo->fru_description) - 1);
+	devinfo->fru_description[sizeof(devinfo->fru_description) - 1] = '\0';
+
+	return 0;
+}
+EXPORT_SYMBOL(cxi_dev_info_get);
diff --git a/drivers/net/ethernet/hpe/ss1/cass_irq.c b/drivers/net/ethernet/hpe/ss1/cass_irq.c
new file mode 100644
index 000000000000..c8ccd8912e8d
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_irq.c
@@ -0,0 +1,210 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2021 Hewlett Packard Enterprise Development LP */
+
+/* Cassini interrupt management */
+
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include <linux/types.h>
+
+#include "cass_core.h"
+
+/*
+ * cass_irq_int_handler() - Completion interrupt handler
+ */
+static irqreturn_t cass_irq_int_handler(int irq, void *nh)
+{
+	atomic_notifier_call_chain(nh, 0, NULL);
+
+	return IRQ_HANDLED;
+}
+
+/*
+ * cass_comp_irq_attach() - Attach to a completion interrupt
+ *
+ * @hw: Cassini device
+ * @mask: CPU mask used as an affinity hint to select IRQ vector
+ * @nb: Notifier block to be called on interrupt
+ *
+ * @return Interrupt is returned index on success. A negative errno is returned
+ * on error.
+ */
+struct cass_irq *cass_comp_irq_attach(struct cass_dev *hw,
+				      const struct cpumask *mask,
+				      struct notifier_block *nb)
+{
+	struct cass_irq *best_irq = NULL;
+	int cpu;
+	int rc;
+	int i;
+
+	for_each_cpu(cpu, mask) {
+		for (i = 0; i < hw->num_comp_irqs; i++) {
+			struct cass_irq *irq = &hw->comp_irqs[i];
+
+			if (!cpumask_test_cpu(cpu, &irq->mask))
+				continue;
+
+			if (atomic_read(&irq->refcount) == 0) {
+				best_irq = irq;
+				goto do_register;
+			}
+
+			if (!best_irq || atomic_read(&best_irq->refcount) >
+					 atomic_read(&irq->refcount))
+				best_irq = irq;
+		}
+	}
+
+	/* If no match, select a random IRQ vector. */
+	if (!best_irq) {
+		i = get_random_u32() % hw->num_comp_irqs;
+		best_irq = &hw->comp_irqs[i];
+	}
+
+do_register:
+	rc = atomic_notifier_chain_register(&best_irq->nh, nb);
+	if (rc < 0)
+		return ERR_PTR(rc);
+
+	mutex_lock(&best_irq->lock);
+
+	if (atomic_read(&best_irq->refcount) == 0) {
+		rc = request_irq(best_irq->vec, cass_irq_int_handler, 0,
+				 best_irq->irq_name, &best_irq->nh);
+		if (rc) {
+			mutex_unlock(&best_irq->lock);
+
+			cxidev_err(&hw->cdev, "request_irq failed at index %d: %d\n",
+				   i, rc);
+
+			atomic_notifier_chain_unregister(&best_irq->nh, nb);
+
+			return ERR_PTR(rc);
+		}
+
+		rc = irq_set_affinity_hint(best_irq->vec, &best_irq->mask);
+		if (rc)
+			cxidev_err(&hw->cdev, "irq_set_affinity_hint failed: %d\n",
+				   rc);
+	}
+
+	atomic_inc(&best_irq->refcount);
+
+	mutex_unlock(&best_irq->lock);
+
+	return best_irq;
+}
+
+/*
+ * cass_comp_irq_detach() - Detach from a completion interrupt
+ *
+ * @hw: Cassini device
+ * @irq: An interrupt returned from cass_comp_irq_attach()
+ * @nb: The notifier block to detach
+ */
+void cass_comp_irq_detach(struct cass_dev *hw, struct cass_irq *irq,
+			  struct notifier_block *nb)
+{
+	atomic_notifier_chain_unregister(&irq->nh, nb);
+
+	mutex_lock(&irq->lock);
+
+	if (atomic_dec_return(&irq->refcount) == 0) {
+		irq_set_affinity_hint(irq->vec, NULL);
+		free_irq(irq->vec, &irq->nh);
+	} else {
+		synchronize_irq(irq->vec);
+	}
+
+	mutex_unlock(&irq->lock);
+}
+
+/*
+ * cass_irq_init() - Initialize interrupts
+ */
+int cass_irq_init(struct cass_dev *hw)
+{
+	int rc;
+	int i;
+	int nvecs_res = 0;
+	int nvecs_min = 0;
+	int nvecs_max = 0;
+	struct cass_irq *irq;
+	struct pci_dev *pdev = hw->cdev.pdev;
+	int numa = dev_to_node(&pdev->dev);
+
+	if (!hw->with_vf_support)
+		return 0;
+
+	/* Initialize the MSI vectors table */
+	if (hw->cdev.is_physfn) {
+		/* Reserve the special IRQ numbers */
+		nvecs_res += C_FIRST_AVAIL_MSIX_INT;
+	} else {
+		/* Reserve IRQ number 0 for communicating with the PF. */
+		nvecs_res += 1;
+	}
+
+	/* Reserve IRQs for ATU */
+	hw->atu_cq_vec = nvecs_res++;
+	hw->atu_pri_vec = nvecs_res++;
+
+	/* Get as many IRQs as possible, but not too many as
+	 * request_irq() will eventually fail.
+	 */
+	nvecs_min = nvecs_res + 1;
+	if (HW_PLATFORM_NETSIM(hw))
+		nvecs_max = 128;
+	else
+		nvecs_max = pci_msix_vec_count(pdev);
+
+	/* Enable MSIX. */
+	rc = pci_alloc_irq_vectors(pdev, nvecs_min, nvecs_max, PCI_IRQ_MSIX);
+	if (rc < 0)
+		return rc;
+
+	hw->num_irqs = rc;
+	hw->num_comp_irqs = hw->num_irqs - nvecs_res;
+
+	/* Use remaining IRQs for completions */
+	hw->comp_irqs = kcalloc(hw->num_comp_irqs, sizeof(struct cass_irq),
+				GFP_KERNEL);
+	if (!hw->comp_irqs) {
+		rc = -ENOMEM;
+		goto free_irq_vecs;
+	}
+
+	for (i = 0; i < hw->num_comp_irqs; i++) {
+		irq = &hw->comp_irqs[i];
+		irq->idx = nvecs_res + i;
+		ATOMIC_INIT_NOTIFIER_HEAD(&irq->nh);
+		atomic_set(&irq->refcount, 0);
+		irq->vec = pci_irq_vector(pdev, irq->idx);
+		mutex_init(&irq->lock);
+
+		scnprintf(irq->irq_name, sizeof(irq->irq_name),
+			  "%s_comp%d", hw->cdev.name, i);
+		cpumask_set_cpu(cpumask_local_spread(i, numa), &irq->mask);
+	}
+
+	return 0;
+
+free_irq_vecs:
+	pci_free_irq_vectors(pdev);
+
+	return rc;
+}
+
+/*
+ * cass_irq_fini() - Finalize interrupts
+ */
+void cass_irq_fini(struct cass_dev *hw)
+{
+	if (!hw->with_vf_support)
+		return;
+
+	kfree(hw->comp_irqs);
+
+	pci_free_irq_vectors(hw->cdev.pdev);
+}
diff --git a/drivers/net/ethernet/hpe/ss1/cass_link.c b/drivers/net/ethernet/hpe/ss1/cass_link.c
new file mode 100644
index 000000000000..db2b3bc281c1
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_link.c
@@ -0,0 +1,192 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2020,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/device.h>
+#include <linux/workqueue.h>
+#include <linux/delay.h>
+#include <linux/hpe/sbl/sbl.h>
+
+#include "cass_core.h"
+
+/*
+ * The link has asynchronously gone down
+ *
+ *   i.e. the fabric LSM has gone down, the base link has gone down or
+ *        the headshell/media removed
+ *
+ */
+void cass_link_async_down(struct cass_dev *hw, u32 origin)
+{
+	cxidev_dbg(&hw->cdev,
+		   "async link down, origin %s, (current dirn %s, origin %s)\n",
+		   cass_link_down_origin_str(origin),
+		   cass_lmon_dirn_str(cass_lmon_get_dirn(hw)),
+		   cass_link_down_origin_str(cass_link_get_down_origin(hw)));
+
+	if (cass_version(hw, CASSINI_1))
+		atomic_inc(&hw->sbl_counters[link_async_down_tries]);
+
+	if (cass_lmon_get_dirn(hw) == CASS_LMON_DIRECTION_RESET) {
+		/*
+		 * Do nothing
+		 * This will take us down anyway and is only cleared
+		 * when reset had completed
+		 */
+		return;
+	}
+
+	spin_lock(&hw->port->lock);
+	if (hw->port->link_down_origin != CASS_DOWN_ORIGIN_CMD) {
+		/*
+		 * We are executing a command don't overwrite origin
+		 * as the link keep-up code requires it
+		 */
+		hw->port->link_down_origin = origin;
+	}
+	spin_unlock(&hw->port->lock);
+	if (cass_version(hw, CASSINI_1))
+		atomic_inc(&hw->sbl_counters[link_async_down]);
+	cass_lmon_request_down(hw);
+}
+
+/*
+ * blocking async link down
+ *
+ *   wait until the link is in a suitable state ("down") for the
+ *   media to be changed
+ *
+ *   we would link to use a completion here but its too complicated so
+ *   will simply poll for it to be in a "down" state.
+ */
+int cass_link_async_down_wait(struct cass_dev *hw, u32 origin)
+{
+	unsigned long timeout = jiffies +
+		msecs_to_jiffies(CASS_LINK_ASYNC_DOWN_TIMEOUT);
+
+	cxidev_dbg(&hw->cdev, "async down wait - origin %s\n",
+		   cass_link_down_origin_str(origin));
+
+	if (cass_version(hw, CASSINI_1))
+		atomic_inc(&hw->sbl_counters[link_async_down_tries]);
+
+	/* stop the link if its coming up */
+	spin_lock(&hw->port->lock);
+	switch (hw->port->lstate) {
+
+	case CASS_LINK_STATUS_STARTING:
+	case CASS_LINK_STATUS_UP:
+		hw->port->link_down_origin = origin;
+		spin_unlock(&hw->port->lock);
+		cass_lmon_request_down(hw);
+		break;
+
+	default:
+		spin_unlock(&hw->port->lock);
+	}
+
+	/* wait for it to get to a "down" state */
+	do {
+		spin_lock(&hw->port->lock);
+		switch (hw->port->lstate) {
+
+		case CASS_LINK_STATUS_DOWN:
+		case CASS_LINK_STATUS_UNCONFIGURED:
+		case CASS_LINK_STATUS_ERROR:
+		case CASS_LINK_STATUS_UNKNOWN:
+			cxidev_dbg(&hw->cdev, "async down wait done (%s)\n",
+				   cass_link_state_str(hw->port->lstate));
+			if (cass_version(hw, CASSINI_1))
+				atomic_inc(&hw->sbl_counters[link_async_down]);
+			spin_unlock(&hw->port->lock);
+			return 0;
+
+		default:
+			spin_unlock(&hw->port->lock);
+			msleep(CASS_LINK_ASYNC_DOWN_INTERVAL);
+			break;
+		}
+	} while time_is_after_jiffies(timeout);
+
+	cxidev_err(&hw->cdev, "async down wait timed out (%s)\n",
+		   cass_link_state_str(hw->port->lstate));
+	return -ETIMEDOUT;
+}
+
+/*
+ * blocking async link reset
+ *
+ *   block until the link reset completes
+ *
+ *   we would link to use a completion here but its too complicated so
+ *   will simply poll for it to be in an "unconfigured" state.
+ */
+int cass_link_async_reset_wait(struct cass_dev *hw, u32 origin)
+{
+	unsigned long timeout = jiffies +
+		msecs_to_jiffies(CASS_LINK_ASYNC_RESET_TIMEOUT);
+
+	cxidev_dbg(&hw->cdev, "async reset wait - origin %s\n",
+		   cass_link_down_origin_str(origin));
+
+	/* stop the link if its coming up */
+	spin_lock(&hw->port->lock);
+	switch (hw->port->lstate) {
+
+	case CASS_LINK_STATUS_STARTING:
+	case CASS_LINK_STATUS_UP:
+	case CASS_LINK_STATUS_STOPPING:
+	case CASS_LINK_STATUS_DOWN:
+	case CASS_LINK_STATUS_ERROR:
+	case CASS_LINK_STATUS_UNCONFIGURED:
+		hw->port->link_down_origin = origin;
+		spin_unlock(&hw->port->lock);
+		cass_lmon_request_reset(hw);
+		break;
+
+	default:
+		spin_unlock(&hw->port->lock);
+	}
+
+	/* wait for it to get to an "unconfigured" state */
+	do {
+		spin_lock(&hw->port->lock);
+		switch (hw->port->lstate) {
+
+		case CASS_LINK_STATUS_UNCONFIGURED:
+			cxidev_dbg(&hw->cdev, "async reset wait done (%s)\n",
+				   cass_link_state_str(hw->port->lstate));
+			spin_unlock(&hw->port->lock);
+			return 0;
+
+		default:
+			spin_unlock(&hw->port->lock);
+			msleep(CASS_LINK_ASYNC_RESET_INTERVAL);
+			break;
+		}
+	} while time_is_after_jiffies(timeout);
+
+	cxidev_err(&hw->cdev, "async reset wait timed out (%s)\n",
+		   cass_link_state_str(hw->port->lstate));
+	return -ETIMEDOUT;
+}
+
+/*
+ * print out link state, info etc for sysfs diags
+ *
+ */
+int cass_link_sysfs_sprint(struct cass_dev *hw, char *buf, size_t size)
+{
+	int rc;
+	int state;
+
+	spin_lock(&hw->port->lock);
+	state = hw->port->lstate;
+	spin_unlock(&hw->port->lock);
+
+	rc = scnprintf(buf, size, "%s", cass_link_state_str(state));
+
+	return rc;
+}
diff --git a/drivers/net/ethernet/hpe/ss1/cass_link_misc.c b/drivers/net/ethernet/hpe/ss1/cass_link_misc.c
new file mode 100644
index 000000000000..aa411234c101
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_link_misc.c
@@ -0,0 +1,159 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2020,2025 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/device.h>
+#include <linux/workqueue.h>
+#include <linux/delay.h>
+#include <linux/hpe/sbl/sbl.h>
+
+#include "cass_core.h"
+#include "cass_cable.h"
+
+/*
+ * thread safe access functions
+ *
+ *   TODO inline these
+ */
+int cass_link_get_state(struct cass_dev *hw)
+{
+	int state;
+
+	spin_lock(&hw->port->lock);
+	state = hw->port->lstate;
+	spin_unlock(&hw->port->lock);
+
+	return state;
+}
+
+void cass_link_set_led(struct cass_dev *hw)
+{
+	cxidev_dbg(&hw->cdev,
+		   "beacon = %s, overtemp = %s, hstate = %d, lstate = %d\n",
+		   hw->qsfp_beacon_active ? "true" : "false",
+		   hw->qsfp_over_temp ? "true" : "false",
+		   hw->port->hstate,
+		   hw->port->lstate);
+
+	if (hw->qsfp_beacon_active) {
+		uc_cmd_set_link_leds(hw, LED_SLOW_GRN);
+		return;
+	}
+
+	if (!cass_version(hw, CASSINI_1))
+		return;
+
+	if (hw->port->hstate == CASS_HEADSHELL_STATUS_NOT_PRESENT)
+		uc_cmd_set_link_leds(hw, LED_OFF);
+	else if (hw->qsfp_over_temp)
+		uc_cmd_set_link_leds(hw, LED_ON_YEL);
+	else if (hw->port->hstate == CASS_HEADSHELL_STATUS_ERROR)
+		uc_cmd_set_link_leds(hw, LED_FAST_YEL);
+	else {
+		switch (hw->port->lstate) {
+		case CASS_LINK_STATUS_UNKNOWN:
+		case CASS_LINK_STATUS_ERROR:
+			uc_cmd_set_link_leds(hw, LED_FAST_GRN_YEL);
+			break;
+		case CASS_LINK_STATUS_RESETTING:
+		case CASS_LINK_STATUS_UNCONFIGURED:
+		case CASS_LINK_STATUS_STOPPING:
+		case CASS_LINK_STATUS_DOWN:
+			uc_cmd_set_link_leds(hw, LED_OFF);
+			break;
+		case CASS_LINK_STATUS_STARTING:
+			uc_cmd_set_link_leds(hw, LED_FAST_GRN);
+			break;
+		case CASS_LINK_STATUS_UP:
+			uc_cmd_set_link_leds(hw, LED_ON_GRN);
+			break;
+		default:
+			break;
+		}
+	}
+}
+
+void cass_link_set_state(struct cass_dev *hw, int state, int err)
+{
+	spin_lock(&hw->port->lock);
+	hw->port->prev_lstate = hw->port->lstate;
+	hw->port->lstate = state;
+	hw->port->lerr = err;
+	spin_unlock(&hw->port->lock);
+
+	cass_link_set_led(hw);
+}
+
+int cass_link_get_down_origin(struct cass_dev *hw)
+{
+	int origin;
+
+	spin_lock(&hw->port->lock);
+	origin = hw->port->link_down_origin;
+	spin_unlock(&hw->port->lock);
+
+	return origin;
+}
+
+void cass_link_set_down_origin(struct cass_dev *hw, int origin)
+{
+	spin_lock(&hw->port->lock);
+	hw->port->link_down_origin = origin;
+	spin_unlock(&hw->port->lock);
+}
+
+/*
+ * enum to string functions
+ */
+const char *cass_link_state_str(enum cass_link_status state)
+{
+	switch (state) {
+	case CASS_LINK_STATUS_UNKNOWN:      return "unknown";
+	case CASS_LINK_STATUS_RESETTING:    return "resetting";
+	case CASS_LINK_STATUS_UNCONFIGURED: return "unconfigured";
+	case CASS_LINK_STATUS_STARTING:     return "starting";
+	case CASS_LINK_STATUS_UP:           return "up";
+	case CASS_LINK_STATUS_STOPPING:     return "stopping";
+	case CASS_LINK_STATUS_DOWN:         return "down";
+	case CASS_LINK_STATUS_ERROR:        return "error";
+	default:                            return "unrecognised";
+	}
+}
+
+const char *cass_lmon_dirn_str(enum cass_lmon_direction dirn)
+{
+	switch (dirn) {
+	case CASS_LMON_DIRECTION_INVALID: return "unknown";
+	case CASS_LMON_DIRECTION_NONE:    return "none";
+	case CASS_LMON_DIRECTION_UP:      return "up";
+	case CASS_LMON_DIRECTION_DOWN:    return "down";
+	case CASS_LMON_DIRECTION_RESET:   return "reset";
+	default:                          return "unrecognised";
+	}
+}
+
+const char *cass_link_down_origin_str(u32 origin)
+{
+	switch (origin) {
+	case CASS_DOWN_ORIGIN_UNKNOWN:           return "unknown";
+	case CASS_DOWN_ORIGIN_NONE:              return "none";
+	case CASS_DOWN_ORIGIN_CONFIG:            return "config";
+	case CASS_DOWN_ORIGIN_BL_LFAULT:         return "bl/lfault";
+	case CASS_DOWN_ORIGIN_BL_RFAULT:         return "bl/rfault";
+	case CASS_DOWN_ORIGIN_BL_ALIGN:          return "bl/align";
+	case CASS_DOWN_ORIGIN_BL_DOWN:           return "bl/down";
+	case CASS_DOWN_ORIGIN_BL_HISER:          return "bl/hiser";
+	case CASS_DOWN_ORIGIN_BL_LLR:            return "bl/llr";
+	case CASS_DOWN_ORIGIN_BL_UNKNOWN:        return "bl/unknown";
+	case CASS_DOWN_ORIGIN_LMON_UCW:          return "lmon/ucw";
+	case CASS_DOWN_ORIGIN_LMON_CCW:          return "lmon/ccw";
+	case CASS_DOWN_ORIGIN_LLR_TX_REPLAY:     return "lmon/llr_tx_replay";
+	case CASS_DOWN_ORIGIN_HEADSHELL_REMOVED: return "headshell-removed";
+	case CASS_DOWN_ORIGIN_HEADSHELL_ERROR:   return "headshell-error";
+	case CASS_DOWN_ORIGIN_MEDIA_REMOVED:     return "media-removed";
+	case CASS_DOWN_ORIGIN_CMD:               return "cmd";
+	default:                                 return "unrecognised";
+	}
+}
diff --git a/drivers/net/ethernet/hpe/ss1/cass_p2p.h b/drivers/net/ethernet/hpe/ss1/cass_p2p.h
new file mode 100644
index 000000000000..ab8fe48998a2
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_p2p.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2020-2024,2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _CASS_P2P_H
+#define _CASS_P2P_H
+
+struct ac_map_opts {
+	u64 va_start;
+	u64 va_end;
+	size_t va_len;
+	u32 flags;
+	u64 iova;
+	dma_addr_t *dma_addrs;
+	int page_shift;
+	int huge_shift;
+	int ptg_mode;
+	bool hugepage_test;
+	bool is_huge_page;
+	struct cxi_md_priv *md_priv;
+};
+
+struct cass_p2p_ops {
+	int (*get_pages)(struct ac_map_opts *m_opts);
+	void (*put_pages)(struct cxi_md_priv *md_priv);
+	int (*is_device_mem)(uintptr_t va, size_t len, int *page_shift);
+};
+
+#ifdef CONFIG_HPE_SS1_P2P_DMABUF
+int cass_device_get_pages(struct ac_map_opts *m_opts);
+void cass_device_put_pages(struct cxi_md_priv *md_priv);
+struct cxi_md_priv *cass_device_md(struct cxi_lni_priv *lni_priv, u64 va,
+				   size_t len, dma_addr_t *dma_addr);
+int cass_is_device_memory(struct cass_dev *hw, struct ac_map_opts *m_opts,
+			  uintptr_t va, size_t len);
+void cxi_p2p_fini(void);
+#else
+static inline int cass_device_get_pages(struct ac_map_opts *m_opts)
+{
+	return -ENOTSUPP;
+}
+
+static inline void cass_device_put_pages(struct cxi_md_priv *md_priv)
+{
+	return;
+}
+
+static inline struct cxi_md_priv *cass_device_md(struct cxi_lni_priv *lni_priv,
+						 u64 va, size_t len,
+						 dma_addr_t *dma_addr)
+{
+	return ERR_PTR(-ENOTSUPP);
+}
+
+static inline int cass_is_device_memory(struct cass_dev *hw,
+					struct ac_map_opts *m_opts,
+					uintptr_t va, size_t len)
+{
+	return -ENOTSUPP;
+}
+
+static inline void cxi_p2p_fini(void)
+{
+	return;
+}
+#endif
+int cxi_dmabuf_get_pages(struct ac_map_opts *m_opts);
+void cxi_dmabuf_put_pages(struct cxi_md_priv *md_priv);
+
+#endif /* CASS_P2P_H */
diff --git a/drivers/net/ethernet/hpe/ss1/cass_rgroup.h b/drivers/net/ethernet/hpe/ss1/cass_rgroup.h
new file mode 100644
index 000000000000..2a8ded868b21
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_rgroup.h
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2024 Hewlett Packard Enterprise Development LP */
+
+#ifndef _CASS_RGROUP_H_
+#define _CASS_RGROUP_H_
+
+#include <linux/xarray.h>
+
+#include "cxi_rgroup.h"
+
+void cass_dev_rgroup_init(struct cass_dev *hw);
+
+void cass_dev_rgroup_fini(struct cass_dev *hw);
+
+int cass_rgroup_add_resource(struct cxi_rgroup *rgroup,
+			     struct cxi_resource_entry *resource);
+
+int cass_rgroup_remove_resource(struct cxi_rgroup *rgroup,
+				struct cxi_resource_entry *resource);
+
+void cass_free_resource(struct cxi_rgroup *rgroup,
+			struct cxi_resource_entry *entry);
+
+int cass_alloc_resource(struct cxi_rgroup *rgroup,
+			struct cxi_resource_entry *entry);
+
+void cass_get_tle_in_use(struct cxi_rgroup *rgroup,
+			 struct cxi_resource_entry *entry);
+
+#endif /* _CASS_RGROUP_H_ */
diff --git a/drivers/net/ethernet/hpe/ss1/cass_rx_tx_profile.h b/drivers/net/ethernet/hpe/ss1/cass_rx_tx_profile.h
new file mode 100644
index 000000000000..26082e1cac82
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_rx_tx_profile.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2024 Hewlett Packard Enterprise Development LP */
+
+#ifndef _CASS_RX_TX_PROFILE_H_
+#define _CASS_RX_TX_PROFILE_H_
+
+struct cass_dev;
+
+void cass_dev_rx_tx_profiles_init(struct cass_dev *hw);
+void cass_dev_rx_tx_profiles_fini(struct cass_dev *hw);
+
+void cass_rx_profile_init(struct cass_dev *hw, struct cxi_rx_profile *rx_profile);
+void cass_tx_profile_init(struct cass_dev *hw, struct cxi_tx_profile *tx_profile);
+
+#endif /* _CASS_RX_TX_PROFILE_H_ */
diff --git a/drivers/net/ethernet/hpe/ss1/cass_sbl.h b/drivers/net/ethernet/hpe/ss1/cass_sbl.h
new file mode 100644
index 000000000000..e6e730087a86
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_sbl.h
@@ -0,0 +1,581 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2020-2024 Hewlett Packard Enterprise Development LP */
+
+#ifndef _CXI_SBL_H
+#define _CXI_SBL_H
+
+#include <linux/phy/phy.h>
+#include "uapi/ethernet/sbl-abi.h"
+
+#define PCA_SHASTA_BRAZOS_PASS_1_PN        "102325100"
+#define PCA_SHASTA_BRAZOS_PASS_2_PN        "102325101"
+#define PCA_SHASTA_BRAZOS_PASS_3_PN        "102325102"
+#define PCA_SHASTA_BRAZOS_PASS_4_PN        "P41345-"
+
+#define PCA_SHASTA_SAWTOOTH_PASS_1_PN      "102251000"
+#define PCA_SHASTA_SAWTOOTH_PASS_2_PN      "102251001"
+#define PCA_SHASTA_SAWTOOTH_PASS_3_PN      "P43012-"
+
+#define CASS_LINK_ASYNC_DOWN_TIMEOUT              5000
+#define CASS_LINK_ASYNC_DOWN_INTERVAL              500
+#define CASS_LINK_ASYNC_RESET_TIMEOUT             5000
+#define CASS_LINK_ASYNC_RESET_INTERVAL             500
+#define CASS_PORT_DEFAULT_OPT_FLAGS                  0
+
+#define CASS_PCS_NUM_FECL_CNTRS                           8
+
+/**
+ * @brief default link options flags
+ */
+#define CASS_LINK_ATTR_DEFAULT_OPT_FLAGS                  0
+#define CASS_SBL_PORT_CONFIG1_PRE                         4
+#define CASS_SBL_PORT_CONFIG2_ATTEN                       12
+#define CASS_SBL_PORT_CONFIG2_GS1                         0
+#define CASS_SBL_PORT_CONFIG2_NUM_INTR                    4
+#define CASS_SBL_PORT_CONFIG2_INTR0                       0x2c
+#define CASS_SBL_PORT_CONFIG2_DATA0                       0x0909
+#define CASS_SBL_PORT_CONFIG2_INTR1                       0x6c
+#define CASS_SBL_PORT_CONFIG2_DATA1                       0x3
+#define CASS_SBL_PORT_CONFIG2_INTR2                       0x2c
+#define CASS_SBL_PORT_CONFIG2_DATA2                       0x090a
+#define CASS_SBL_PORT_CONFIG2_INTR3                       0x6c
+#define CASS_SBL_PORT_CONFIG2_DATA3                       0xa
+#define CASS_SBL_PORT_CONFIG3_ATTEN                       6
+#define CASS_SBL_PORT_CONFIG3_PRE                         4
+#define CASS_SBL_PORT_CONFIG3_POST                        0
+#define CASS_SBL_PORT_CONFIG3_GS1                         0
+
+#define CASS_SBL_SC_MASKED_OUT                            0
+#define CASS_SBL_SC_MASKED_IN                             0xffffffffffffffff
+#define CASS_SBL_SC_NA                                    0x0
+#define CASS_SBL_SC_LP_SWITCH                             0x1
+#define CASS_SBL_SC_MT_ELEC                               0x1
+#define CASS_SBL_SC_MT_OPT_ANY                            0x6
+#define CASS_SBL_SC_LBM_ANY                               0xff
+#define CASS_SBL_SC_LM_100                                0x2
+#define CASS_SBL_SC_LM_200                                0x1
+
+/* NOTE: don't forget to add sysfs entries if changing this */
+#define CASS_SBL_LINK_RESTART_TIME_SIZE 10
+
+/* Link up FEC check */
+#define CASS_SBL_UP_MIN_FEC_WINDOW             250    /* ms */
+
+/**
+ * @brief software counter names initialisers
+ *
+ *   provides a name for each counter index
+ *
+ */
+#define CASS_SBL_COUNTER_NAMES  "link_up", \
+				"link_up_tries", \
+				"link_down", \
+				"link_down_tries", \
+				"link_async_down", \
+				"link_async_down_tries", \
+				"link_reset", \
+				"link_reset_tries", \
+				"link_auto_restart", \
+				"link_down_origin_config", \
+				"link_down_origin_bl_lfault", \
+				"link_down_origin_bl_rfault", \
+				"link_down_origin_bl_align", \
+				"link_down_origin_bl_down", \
+				"link_down_origin_bl_hiser", \
+				"link_down_origin_bl_llr", \
+				"link_down_origin_bl_unknown", \
+				"link_down_origin_lmon_ucw", \
+				"link_down_origin_lmon_ccw", \
+				"link_down_origin_lmon_llr_tx_replay", \
+				"link_down_origin_headshell_removed", \
+				"link_down_origin_headshell_error", \
+				"link_down_origin_media_removed", \
+				"link_down_origin_cmd", \
+				SBL_COUNTERS_NAME
+
+#define CASS_LMON_COUNTER_NAMES "lmon_wakeup", \
+				"lmon_active", \
+				"lmon_limiter"
+
+/**
+ * enum cass_port_subtype - The sub-type of a port
+ * @CASS_PORT_SUBTYPE_INVALID: Invalid
+ * @CASS_PORT_SUBTYPE_LOCAL:   Local group fabric port
+ * @CASS_PORT_SUBTYPE_GLOBAL:  Global (inter-group) fabric port
+ * @CASS_PORT_SUBTYPE_IEEE:    Standard Ethernet NIC
+ * @CASS_PORT_SUBTYPE_CASSINI: Cassini NIC
+ *
+ * The sub-type of a port
+ */
+enum cass_port_subtype {
+	CASS_PORT_SUBTYPE_INVALID = 0,
+	CASS_PORT_SUBTYPE_LOCAL,
+	CASS_PORT_SUBTYPE_GLOBAL,
+	CASS_PORT_SUBTYPE_IEEE,
+	CASS_PORT_SUBTYPE_CASSINI,
+};
+
+/**
+ * enum cass_port_command - Commands that can be issued to a port
+ * @CASS_CMD_NULL:       Invalid
+ * @CASS_CMD_NOOP:       Do nothing (for testing)
+ * @CASS_CMD_PORT_START: Request port starts
+ * @CASS_CMD_PORT_STOP:  Request port stops
+ * @CASS_CMD_PORT_RESET: Request port reset
+ * @CASS_CMD_LINK_UP:    Request link bring-up
+ * @CASS_CMD_LINK_DOWN:  Request link bring-down
+ * @CASS_CMD_LINK_RESET: Request link resets
+ *
+ * Commands that can be issued to a port
+ */
+enum cass_port_command {
+	CASS_CMD_NULL = 0,
+	CASS_CMD_NOOP,
+	CASS_CMD_PORT_START,
+	CASS_CMD_PORT_STOP,
+	CASS_CMD_PORT_RESET,
+	CASS_CMD_LINK_UP,
+	CASS_CMD_LINK_DOWN,
+	CASS_CMD_LINK_RESET,
+};
+
+/**
+ * enum cass_port_status - The status of a port
+ * @CASS_PORT_STATUS_UNKNOWN:          State unknown
+ * @CASS_PORT_STATUS_NOT_PRESENT:      Port not present in hardware
+ * @CASS_PORT_STATUS_UNCONFIGURED:     Port is not configured
+ * @CASS_PORT_STATUS_STARTING:         Port Starting
+ * @CASS_PORT_STATUS_UP:               Port Up
+ * @CASS_PORT_STATUS_RUNNING:          Port Up and Link Up
+ * @CASS_PORT_STATUS_RUNNING_DEGRADED: Port Up and Link Up but link degraded
+ * @CASS_PORT_STATUS_STOPPING:         Port Stopping
+ * @CASS_PORT_STATUS_DOWN:             Port is down and ready to start
+ * @CASS_PORT_STATUS_RESETTING:        Port is resetting
+ * @CASS_PORT_STATUS_ERROR:            Port has an Error
+ *
+ * The status of a port
+ */
+enum cass_port_status {
+	CASS_PORT_STATUS_UNKNOWN          = 0,
+	CASS_PORT_STATUS_NOT_PRESENT      = 1 << 0,
+	CASS_PORT_STATUS_UNCONFIGURED     = 1 << 1,
+	CASS_PORT_STATUS_STARTING         = 1 << 2,
+	CASS_PORT_STATUS_UP               = 1 << 3,
+	CASS_PORT_STATUS_RUNNING          = 1 << 4,
+	CASS_PORT_STATUS_RUNNING_DEGRADED = 1 << 5,
+	CASS_PORT_STATUS_STOPPING         = 1 << 6,
+	CASS_PORT_STATUS_DOWN             = 1 << 7,
+	CASS_PORT_STATUS_RESETTING        = 1 << 8,
+	CASS_PORT_STATUS_ERROR            = 1 << 9,
+};
+
+/**
+ * enum cass_lmon_direction - link monitor direction flags
+ *
+ * @CASS_LMON_DIRECTION_INVALID: Invalid
+ * @CASS_LMON_DIRECTION_NONE:    no action requested
+ * @CASS_LMON_DIRECTION_UP:      port should try to come up
+ * @CASS_LMON_DIRECTION_DOWN:    port should try to come down
+ * @CASS_LMON_DIRECTION_RESET:   port should reset
+ */
+enum cass_lmon_direction {
+	CASS_LMON_DIRECTION_INVALID = 0,
+	CASS_LMON_DIRECTION_NONE,
+	CASS_LMON_DIRECTION_UP,
+	CASS_LMON_DIRECTION_DOWN,
+	CASS_LMON_DIRECTION_RESET,
+};
+
+/**
+ * enum cass_link_status - Status of the link
+ *
+ * @CASS_LINK_STATUS_UNKNOWN:		State unknown
+ * @CASS_LINK_STATUS_UNCONFIGURED:	Link is not configured
+ * @CASS_LINK_STATUS_STARTING:		Link bring-up in progress
+ * @CASS_LINK_STATUS_UP:		Link Up
+ * @CASS_LINK_STATUS_STOPPING:		Link bring-down in progress
+ * @CASS_LINK_STATUS_DOWN:		Link Down
+ * @CASS_LINK_STATUS_RESETTING:		Link reset in progress
+ * @CASS_LINK_STATUS_ERROR:		Link has an error
+ */
+enum cass_link_status {
+	CASS_LINK_STATUS_UNKNOWN      = 0,
+	CASS_LINK_STATUS_UNCONFIGURED = 1 << 0,
+	CASS_LINK_STATUS_STARTING     = 1 << 1,
+	CASS_LINK_STATUS_UP           = 1 << 2,
+	CASS_LINK_STATUS_STOPPING     = 1 << 3,
+	CASS_LINK_STATUS_DOWN         = 1 << 4,
+	CASS_LINK_STATUS_RESETTING    = 1 << 5,
+	CASS_LINK_STATUS_ERROR        = 1 << 6,
+};
+
+/**
+ * enum cass_link_status - Link configuration option flags
+ * @CASS_LINK_OPT_UP_AUTO_RESTART:	Keep trying to bring up a link that has
+ *					gone down
+ * @CASS_LINK_OPT_NO_SHUTDOWN:		Keep trying to bring up a link that has
+ *					gone down
+ * @CASS_LINK_OPT_RESTART_ON_INSERT:    Allow link restart if up before
+ *                                      headshell remove
+ *
+ * Link configuration option flags
+ */
+enum cass_link_options {
+	CASS_LINK_OPT_UP_AUTO_RESTART    = 1 << 1,
+	CASS_LINK_OPT_NO_SHUTDOWN        = CASS_LINK_OPT_UP_AUTO_RESTART,
+	CASS_LINK_OPT_RESTART_ON_INSERT  = 1 << 2,
+};
+
+/**
+ * enum cass_link_down_origin - The reason the link went down
+ * @CASS_DOWN_ORIGIN_UNKNOWN:		Origin is not known
+ * @CASS_DOWN_ORIGIN_NONE:		not coming down
+ * @CASS_DOWN_ORIGIN_CONFIG:		down after config
+ * @CASS_DOWN_ORIGIN_BL_LFAULT:		base link - local fault
+ * @CASS_DOWN_ORIGIN_BL_RFAULT:		base link - remote fault
+ * @CASS_DOWN_ORIGIN_BL_ALIGN:		base link - alignment lost
+ * @CASS_DOWN_ORIGIN_BL_DOWN:		base link - link down
+ * @CASS_DOWN_ORIGIN_BL_HISER:		base link - high serdes errors
+ * @CASS_DOWN_ORIGIN_BL_LLR:		base link - llr max buffer
+ * @CASS_DOWN_ORIGIN_BL_UNKNOWN:	base link - some other reason
+ * @CASS_DOWN_ORIGIN_LMON_UCW:		lmon - high uncorrected fec error rate
+ * @CASS_DOWN_ORIGIN_LMON_CCW:		lmon - high corrected fec error rate
+ * @CASS_DOWN_ORIGIN_LLR_TX_REPLAY:	lmon - high llr_tx_replay fec error rate
+ * @CASS_DOWN_ORIGIN_HEADSHELL_REMOVED: headshell removed
+ * @CASS_DOWN_ORIGIN_HEADSHELL_ERROR:   headshell fault
+ * @CASS_DOWN_ORIGIN_MEDIA_REMOVED:     media removed
+ * @CASS_DOWN_ORIGIN_CMD:               direct command
+ *
+ * The last reason why the link has gone down.
+ */
+enum cass_link_down_origin {
+	CASS_DOWN_ORIGIN_UNKNOWN,
+	CASS_DOWN_ORIGIN_NONE,
+	CASS_DOWN_ORIGIN_CONFIG,
+	CASS_DOWN_ORIGIN_BL_LFAULT,
+	CASS_DOWN_ORIGIN_BL_RFAULT,
+	CASS_DOWN_ORIGIN_BL_ALIGN,
+	CASS_DOWN_ORIGIN_BL_DOWN,
+	CASS_DOWN_ORIGIN_BL_HISER,
+	CASS_DOWN_ORIGIN_BL_LLR,
+	CASS_DOWN_ORIGIN_BL_UNKNOWN,
+	CASS_DOWN_ORIGIN_LMON_UCW,
+	CASS_DOWN_ORIGIN_LMON_CCW,
+	CASS_DOWN_ORIGIN_LLR_TX_REPLAY,
+	CASS_DOWN_ORIGIN_HEADSHELL_REMOVED,
+	CASS_DOWN_ORIGIN_HEADSHELL_ERROR,
+	CASS_DOWN_ORIGIN_MEDIA_REMOVED,
+	CASS_DOWN_ORIGIN_CMD,
+};
+
+/**
+ * enum cass_port_config_flags - Configure/unconfigured state
+ * @CASS_TYPE_CONFIGURED:	type info has been configured
+ * @CASS_PORT_CONFIGURED:	port info  has been configured
+ * @CASS_LINK_CONFIGURED:	link info has been configured
+ * @CASS_MEDIA_CONFIGURED:	media info has been configured
+ *
+ * Configured/uncofigured state for tpml
+ */
+enum cass_port_config_flags {
+	CASS_TYPE_CONFIGURED   = (1 << 0),
+	CASS_PORT_CONFIGURED   = (1 << 1),
+	CASS_LINK_CONFIGURED   = (1 << 2),
+	CASS_MEDIA_CONFIGURED  = (1 << 3),
+};
+
+/**
+ * enum cass_phy_mode - Phy mode for Cassini SerDes
+ * @PHY_MODE_NORMAL:		normal operation
+ * @PHY_MODE_TX_DISABLED:	Transmitter disabled
+ * @PHY_MODE_LOW_POWER:		SerDes in low power mode
+ * @PHY_MODE_OFF:		SerDes powered off
+ * @PHY_MODE_SPECIAL:		special operation flag
+ *
+ * Phy mode for Cassini SerDes
+ */
+enum cass_phy_mode {
+	PHY_MODE_NORMAL		= 0,
+	PHY_MODE_TX_DISABLED	= 1,
+	PHY_MODE_LOW_POWER	= 2,
+	PHY_MODE_OFF		= 4,
+	PHY_MODE_SPECIAL	= 8,
+};
+
+/**
+ * enum cass_pause_type - Pause type for Cassini
+ * @CASS_PAUSE_TYPE_INVALID:	invalid pause type
+ * @CASS_PAUSE_TYPE_NONE:		no pause specified
+ * @CASS_PAUSE_TYPE_GLOBAL:		standard pause
+ * @CASS_PAUSE_TYPE_802_3X:		standard pause
+ * @CASS_PAUSE_TYPE_PFC:		priority flow control pause
+ * @CASS_PAUSE_TYPE_802_1QBB:	priority flow control pause
+ *
+ * Pause type for Cassini
+ */
+enum cass_pause_type {
+	CASS_PAUSE_TYPE_INVALID  = 0,
+	CASS_PAUSE_TYPE_NONE,
+	CASS_PAUSE_TYPE_GLOBAL,
+	CASS_PAUSE_TYPE_802_3X   = CASS_PAUSE_TYPE_GLOBAL,
+	CASS_PAUSE_TYPE_PFC,
+	CASS_PAUSE_TYPE_802_1QBB = CASS_PAUSE_TYPE_PFC,
+};
+
+/**
+ * enum cass_sbl_counters_idx - Software counter indexes
+ *
+ * Counters cannot be reset
+ *
+ * @link_up:                            link reached up state
+ * @link_up_tries:                      link up called
+ * @link_down:                          link reached down state
+ * @link_down_tries:                    link down called
+ * @link_async_down:                    link async down triggers down
+ * @link_async_down_tries:              link async down called
+ * @link_reset:                         link reset completed
+ * @link_reset_tries:                   link reset called
+ * @link_auto_restart:                  lmon link auto-restarted
+ * @link_down_origin_config:            after config
+ * @link_down_origin_bl_lfault:         pcs local fault
+ * @link_down_origin_bl_rfault:         pcr remote fault
+ * @link_down_origin_bl_align:          pcs align
+ * @link_down_origin_bl_down:           pcs link down
+ * @link_down_origin_bl_hiser:          pcs high serdes error rate
+ * @link_down_origin_bl_llr:            llr error
+ * @link_down_origin_bl_unknown:        base link unknown
+ * @link_down_origin_lmon_ucw:          lmon high ucw rate
+ * @link_down_origin_lmon_ccw:          lmon high ccw rate
+ * @link_down_origin_lmon_llr_tx_replay:lmon high llr tx replay rate
+ * @link_down_origin_headshell_removed: headshell removed
+ * @link_down_origin_headshell_error:   headshell in error
+ * @link_down_origin_media_removed:     media removed
+ * @link_down_origin_cmd:               user command
+ * @SBL_COUNTERS:                       sbl counters defined in sbl_counters.h
+ * @CASS_SBL_NUM_COUNTERS:              the number of counters
+ */
+enum cass_sbl_counters_idx {
+	link_up,
+	link_up_tries,
+	link_down,
+	link_down_tries,
+	link_async_down,
+	link_async_down_tries,
+	link_reset,
+	link_reset_tries,
+	link_auto_restart,
+	link_down_origin_config,
+	link_down_origin_bl_lfault,
+	link_down_origin_bl_rfault,
+	link_down_origin_bl_align,
+	link_down_origin_bl_down,
+	link_down_origin_bl_hiser,
+	link_down_origin_bl_llr,
+	link_down_origin_bl_unknown,
+	link_down_origin_lmon_ucw,
+	link_down_origin_lmon_ccw,
+	link_down_origin_lmon_llr_tx_replay,
+	link_down_origin_headshell_removed,
+	link_down_origin_headshell_error,
+	link_down_origin_media_removed,
+	link_down_origin_cmd,
+	SBL_COUNTERS,
+	CASS_SBL_NUM_COUNTERS,
+};
+
+/**
+ * enum cass_counters_idx - Software counter indexes
+ *
+ * Counters cannot be reset
+ *
+ * @lmon_wakeup:                        lmon wakeup
+ * @lmon_active:                        lmon active
+ * @lmon_limiter:                       lmon limiter
+ */
+enum cass_lmon_counters_idx {
+	lmon_wakeup,
+	lmon_active,
+	lmon_limiter,
+	CASS_LMON_NUM_COUNTERS,
+};
+
+/**
+ * struct cass_link_attr - Attributes for link configuration
+ * @bl:                 base-link attributes
+ * @options:            option flags for links
+ * @el:                 ether link specific attributes;
+ * @el.mattr:           cable related configuration
+ *
+ * These attributes must be configured for a link.
+ * Different setting will be required for fabric or Ethernet links
+ * The anonymous union is not required by base link.
+ */
+struct cass_link_attr {
+	struct sbl_base_link_attr bl;
+	__u32 options;
+	struct sbl_media_attr mattr;
+};
+
+/**
+ * struct cass_port - port-specific values
+ *
+ * @subtype:                  ieee or casssini
+ * @lock:                     TODO what lock type?
+ * @lmon:                     link monitor thread
+ * @lmon_dirn:                lmon direction
+ * @lmon_wq:                  wq for waking the link monitor
+ * @lmon_active:              lmon is awake
+ * @lmon_limiter_on:          rate limiter is active
+ * @lmon_up_pause:            link up is paused
+ * @lmon_wake_jiffies:        end of wake count period
+ * @lmon_wake_cnt:            wakeups in period
+ * @lmon_counters:            sw counter block (can never be cleared)
+ * @config_state:             what has been configured
+ * @lattr:                    link related configuration
+ * @lstate:                   link state
+ * @prev_lstate:              previous link state
+ * @lerr:                     error number that caused error state
+ * @hstate:                   headshell state
+ * @link_down_origin:         reason we are going down
+ * @link_restart_count:       auto link restarts since last up command
+ * @link_restart_time_idx     auto link restarts current buffer index
+ * @link_restart_time_buf     auto link restarts timestamp buffer
+ * @pause_lock:               lock on pause state access
+ * @pause_type:               type of pause (global/pfc)
+ * @tx_pause:                 enable tx pause
+ * @rx_pause:                 enable rx pause
+ */
+struct cass_port {
+	int subtype;
+	spinlock_t lock;
+	struct task_struct *lmon;
+	int lmon_dirn;
+	wait_queue_head_t lmon_wq;
+	bool lmon_active;
+	bool lmon_limiter_on;
+	bool lmon_up_pause;
+	unsigned long lmon_wake_jiffies;
+	int lmon_wake_cnt;
+	atomic_t *lmon_counters;
+	u32 config_state;
+	struct cass_link_attr lattr;
+	u32 lstate;
+	u32 prev_lstate;
+	u32 lerr;
+	u32 hstate;
+	u32 link_down_origin;
+	u32 link_restart_count;
+	u32 link_restart_time_idx;
+	time64_t link_restart_time_buf[CASS_SBL_LINK_RESTART_TIME_SIZE];
+	spinlock_t pause_lock;
+	u32 pause_type;
+	bool tx_pause;
+	bool rx_pause;
+	time64_t start_time;
+};
+
+int cass_sbl_init(struct cass_dev *hw);
+int cass_sbl_link_start(struct cass_dev *hw);
+int cass_sbl_link_fini(struct cass_dev *hw);
+int cass_sbl_power_on(struct cass_dev *hw);
+int cass_sbl_power_off(struct cass_dev *hw);
+void cass_sbl_set_defaults(struct cass_dev *hw);
+int cass_sbl_configure(struct cass_dev *hw);
+int cass_sbl_reset(struct cass_dev *hw);
+
+/*
+ * link monitors (lmon)
+ */
+int  cass_lmon_start_all(struct cass_dev *hw);
+int  cass_lmon_stop_all(struct cass_dev *hw);
+void cass_lmon_kill_all(struct cass_dev *hw);
+int cass_lmon_get_dirn(struct cass_dev *hw);
+void cass_lmon_set_dirn(struct cass_dev *hw, int dirn);
+bool cass_lmon_get_active(struct cass_dev *hw);
+void cass_lmon_set_active(struct cass_dev *hw, bool state);
+void cass_lmon_set_up_pause(struct cass_dev *hw, bool state);
+bool cass_lmon_get_up_pause(struct cass_dev *hw);
+int  cass_lmon_request_up(struct cass_dev *hw);
+int  cass_lmon_request_down(struct cass_dev *hw);
+int  cass_lmon_request_reset(struct cass_dev *hw);
+const char *cass_lmon_dirn_str(enum cass_lmon_direction dirn);
+
+/*
+ * misc
+ */
+int  cass_link_get_down_origin(struct cass_dev *hw);
+void cass_link_set_down_origin(struct cass_dev *hw, int origin);
+const char *cass_link_state_str(enum cass_link_status state);
+const char *cass_link_down_origin_str(u32 origin);
+void cass_tc_get_hni_pause_cfg(struct cass_dev *hw);
+
+/*
+ * Port database
+ */
+int cass_port_new_port_db(struct cass_dev *hw);
+void cass_port_del_port_db(struct cass_dev *hw);
+
+/*
+ * link state access
+ */
+int  cass_link_get_state(struct cass_dev *hw);
+void cass_link_set_state(struct cass_dev *hw, int state, int err);
+
+/*
+ * set link led
+ */
+void cass_link_set_led(struct cass_dev *hw);
+
+/*
+ * sysfs
+ */
+int cass_link_sysfs_sprint(struct cass_dev *hw, char *buf, size_t size);
+int cass_pause_sysfs_sprint(struct cass_dev *hw, char *buf, size_t size);
+
+/*
+ * Text output helpers
+ */
+const char *cass_port_subtype_str(enum cass_port_subtype subtype);
+const char *cass_link_state_str(enum cass_link_status state);
+const char *cass_pause_type_str(enum cass_pause_type type);
+
+/*
+ * principal link functions
+ */
+void cass_link_async_down(struct cass_dev *hw, u32 origin);
+int  cass_link_async_down_wait(struct cass_dev *hw, u32 origin);
+int cass_link_async_reset_wait(struct cass_dev *hw, u32 origin);
+
+void cass_sbl_mode_get(struct cass_dev *hw, struct cxi_link_info *link_info);
+void cass_sbl_mode_set(struct cass_dev *hw, const struct cxi_link_info *link_info);
+void cass_sbl_pml_recovery_set(struct cass_dev *hw, bool set);
+void cass_sbl_get_debug_flags(struct cass_dev *hw, u32 *flags);
+void cass_sbl_set_debug_flags(struct cass_dev *hw, u32 clr_flags, u32 set_flags);
+void cass_sbl_link_mode_to_speed(u32 link_mode, int *speed);
+void cass_sbl_link_speed_to_mode(int speed, u32 *link_mode);
+
+int cass_sbl_media_config(struct cass_dev *hw, void *attr);
+int cass_sbl_media_unconfig(struct cass_dev *hw);
+int cass_sbl_link_config(struct cass_dev *hw);
+bool cass_sbl_is_link_up(struct cass_dev *hw);
+
+bool cass_sbl_pml_pcs_aligned(struct cass_dev *hw);
+int cass_sbl_exit(struct cass_dev *hw);
+void cass_sbl_exit_legacy(struct cass_dev *hw);
+
+/*
+ * sbl counters
+ */
+int cass_sbl_counters_init(struct cass_dev *hw);
+void cass_sbl_counters_term(struct cass_dev *hw);
+void cass_sbl_counters_down_origin_inc(struct cass_dev *hw, int down_origin);
+void cass_sbl_counters_update(struct cass_dev *hw);
+
+/*
+ * lmon counters
+ */
+void cass_lmon_counters_init(struct cass_dev *hw);
+void cass_lmon_counters_term(struct cass_dev *hw);
+
+int cass_sbl_set_eth_name(struct cass_dev *hw, const char *name);
+#endif	/* _CXI_SBL_H */
diff --git a/drivers/net/ethernet/hpe/ss1/cass_sl.h b/drivers/net/ethernet/hpe/ss1/cass_sl.h
new file mode 100644
index 000000000000..e36f7e695c9a
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_sl.h
@@ -0,0 +1,95 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2022,2023,2024 Hewlett Packard Enterprise Development LP */
+
+#ifndef _CASS_SL_H_
+#define _CASS_SL_H_
+
+#include <linux/hpe/sl/sl_media.h>
+#include <linux/hpe/sl/sl_link.h>
+#include <linux/hpe/sl/sl_llr.h>
+#include <linux/hpe/sl/sl_mac.h>
+#include <linux/hpe/sl/sl_lgrp.h>
+#include <linux/hpe/sl/sl_ldev.h>
+#include <linux/hpe/sl/sl_fec.h>
+
+struct cass_sl_dev {
+	bool                         is_initialized;
+
+	struct sl_ops                ops;
+	struct sl_uc_ops             uc_ops;
+	struct sl_accessors          accessors;
+	struct sl_uc_accessor        uc_accessor;
+
+	struct sl_hw_attr            hw_attr;
+
+	struct sl_ldev              *ldev;
+	struct sl_ldev_attr          ldev_config;
+
+	struct sl_lgrp              *lgrp;
+	struct sl_lgrp_config        lgrp_config;
+
+	u32                          static_tech_map;
+	u32                          autoneg_tech_map;
+	u32                          link_up_mode;
+	u32                          link_up_fec_type;
+
+	struct sl_link              *link;
+	struct sl_link_config        link_config;
+	struct sl_link_policy        link_policy;
+	u32                          link_state;
+	bool                         is_fw_loaded;
+
+	struct sl_mac               *mac;
+
+	struct sl_llr               *llr;
+	struct sl_llr_config         llr_config;
+	bool                         enable_llr;
+	u32                          llr_state;
+	struct sl_llr_data           llr_data;
+
+	struct sl_media_attr         media_attr;
+	bool                         has_cable;
+
+	struct list_head             intr_list;
+	/* Serializes interrupt registration and removal. */
+	struct mutex                 intr_lock;
+
+	struct mutex                 pmi_lock;
+	struct mutex                 sbus_lock;
+
+	struct completion            step_complete;
+
+	u32                          old_an_mode;
+	u32                          old_lt_mode;
+
+	bool                         is_canceled;
+
+	struct {
+		void       *cntrs;
+		size_t      cntrs_size;
+		int         dma_id;
+		dma_addr_t  dma_addr;
+	} fec;
+};
+
+bool cass_sl_is_pcs_aligned(struct cass_dev *cass_dev);
+
+void cass_sl_mode_get(struct cass_dev *cass_dev, struct cxi_link_info *link_info);
+void cass_sl_mode_set(struct cass_dev *cass_dev, const struct cxi_link_info *link_info);
+void cass_sl_flags_get(struct cass_dev *cass_dev, u32 *flags);
+void cass_sl_flags_set(struct cass_dev *cass_dev, u32 clr_flags, u32 set_flags);
+
+void cass_sl_pml_recovery_set(struct cass_dev *cass_dev, bool set);
+
+int  cass_sl_init(struct cass_dev *cass_dev);
+int  cass_sl_connect_id_set(struct cass_dev *cass_dev, const char *connect_id);
+int  cass_sl_media_config(struct cass_dev *cass_dev, void *media_attr);
+int  cass_sl_link_config(struct cass_dev *cass_dev);
+bool cass_sl_is_link_up(struct cass_dev *cass_dev);
+int  cass_sl_link_up(struct cass_dev *cass_dev);
+int  cass_sl_link_down(struct cass_dev *cass_dev);
+int cass_sl_exit(struct cass_dev *cass_dev);
+int  cass_sl_media_unconfig(struct cass_dev *cass_dev);
+int cass_sl_link_fini(struct cass_dev *cass_dev);
+
+#endif /* _CASS_SL_H_ */
diff --git a/drivers/net/ethernet/hpe/ss1/cass_sl_io.h b/drivers/net/ethernet/hpe/ss1/cass_sl_io.h
new file mode 100644
index 000000000000..d03509583407
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_sl_io.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _CASS_SL_IO_H_
+#define _CASS_SL_IO_H_
+
+int cass_sl_uc_write8(void *uc_accessor, u8 page, u8 addr, u8 data);
+int cass_sl_uc_read(void *uc_accessor, u32 offset, u32 page, u8 *data, u32 len);
+u64 cass_sl_read64(void *pci_accessor, long addr);
+void cass_sl_write64(void *pci_accessor, long addr, u64 data64);
+int cass_sl_sbus_rd(void *sbus_accessor, u32 sbus_addr, u8 reg_addr, u32 *rd_data);
+int cass_sl_sbus_wr(void *sbus_accessor, u32 sbus_addr, u8 reg_addr, u32 req_data);
+int cass_sl_sbus_cmd(void *sbus_accessor, int ring, u32 req_data, u8 reg_addr,
+		     u8 dev_addr, u8 op, u32 *rsp_data, u8 *result_code,
+	u8 *overrun, u8 *error, int timeout_ms, u32 flags);
+int cass_sl_pmi_rd(void *pmi_accessor, u8 lgrp_num, u32 addr, u16 *data);
+int cass_sl_pmi_wr(void *pmi_accessor, u8 lgrp_num, u32 addr, u16 data, u16 mask);
+
+#endif /* _CASS_SL_IO_H_ */
diff --git a/drivers/net/ethernet/hpe/ss1/cass_ss1_debugfs.c b/drivers/net/ethernet/hpe/ss1/cass_ss1_debugfs.c
new file mode 100644
index 000000000000..edeee3937705
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_ss1_debugfs.c
@@ -0,0 +1,824 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2018, 2025-2026 Hewlett Packard Enterprise Development LP */
+
+/* cxi-ss1 debug fs*/
+#include <linux/etherdevice.h>
+#include <linux/seq_file.h>
+#include <linux/hpe/sbl/sbl.h>
+#include "cass_core.h"
+#include "cass_ss1_debugfs.h"
+
+#define DEBUGFS_BUFSIZE        800
+
+/* Dump UC logging to debugfs */
+static int uc_log(struct seq_file *s, void *unused)
+{
+	struct cass_dev *hw = s->private;
+	int rc;
+
+	if (!hw->uc_present)
+		return 0;
+
+	mutex_lock(&hw->uc_mbox_mutex);
+
+	while (!seq_has_overflowed(s)) {
+		uc_prepare_comm(hw);
+
+		hw->uc_req.cmd = CUC_CMD_GET_LOG;
+		hw->uc_req.count = 1;
+
+		rc = uc_wait_for_response(hw);
+		if (rc || hw->uc_resp.count <= 1)
+			break;
+
+		hw->uc_resp.data[CUC_DATA_BYTES - 1] = 0;
+		seq_printf(s, "%s\n", hw->uc_resp.data);
+	}
+
+	mutex_unlock(&hw->uc_mbox_mutex);
+
+	return 0;
+}
+
+static int uc_log_debug_dev_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, uc_log, inode->i_private);
+}
+
+const struct file_operations uc_fops = {
+	.owner = THIS_MODULE,
+	.open = uc_log_debug_dev_open,
+	.read = seq_read,
+	.llseek  = seq_lseek,
+	.release = single_release,
+};
+
+/*
+ * print out pause state for debugfs diags
+ *
+ */
+static void cass_pause_debugfs_print(struct cass_dev *hw, struct seq_file *s)
+{
+	u32 pause_type;
+	bool tx_pause;
+	bool rx_pause;
+
+	spin_lock(&hw->port->pause_lock);
+	pause_type = hw->port->pause_type;
+	tx_pause = hw->port->tx_pause;
+	rx_pause = hw->port->rx_pause;
+	spin_unlock(&hw->port->pause_lock);
+
+	seq_printf(s, "pause: %s", cass_pause_type_str(pause_type));
+	switch (pause_type) {
+	case CASS_PAUSE_TYPE_GLOBAL:
+	case CASS_PAUSE_TYPE_PFC:
+		seq_printf(s, ", tx %s, rx %s",
+			   tx_pause ? "on" : "off", rx_pause ? "on" : "off");
+		break;
+	default:
+		break;
+	}
+	seq_puts(s, "\n");
+}
+
+static const int rsrc_dump_order[] = {
+	CXI_RESOURCE_AC,
+	CXI_RESOURCE_CT,
+	CXI_RESOURCE_EQ,
+	CXI_RESOURCE_PTLTE,
+	CXI_RESOURCE_TGQ,
+	CXI_RESOURCE_TXQ,
+	CXI_RESOURCE_PE0_LE,
+	CXI_RESOURCE_PE1_LE,
+	CXI_RESOURCE_PE2_LE,
+	CXI_RESOURCE_PE3_LE,
+	CXI_RESOURCE_TLE
+};
+
+static int dump_rgroups(struct cass_dev *hw, struct seq_file *s)
+{
+	int i;
+	int rc;
+	unsigned long index;
+	struct cxi_rgroup *rgroup;
+	struct cxi_resource_entry *entry;
+
+	seq_puts(s, "Rgroups:");
+	for_each_rgroup(index, rgroup) {
+		seq_printf(s, "\nID: %u\n", rgroup->id);
+		seq_printf(s, "  Name:%s\n", cxi_rgroup_name(rgroup));
+		seq_printf(s, "  State:%s\n",
+			   cxi_rgroup_is_enabled(rgroup) ? "Enabled" : "Disabled");
+		seq_printf(s, "  LNIs/RGID:%d\n",
+			   cxi_rgroup_lnis_per_rgid(rgroup));
+		seq_printf(s, "  System service:%d\n",
+			   cxi_rgroup_system_service(rgroup));
+		seq_printf(s, "  Counter pool ID:%d\n",
+			   cxi_rgroup_cntr_pool_id(rgroup));
+		seq_printf(s, "  LE pool IDs: %d %d %d %d  TLE pool ID: %d\n",
+			   rgroup->pools.le_pool_id[0],
+			   rgroup->pools.le_pool_id[1],
+			   rgroup->pools.le_pool_id[2],
+			   rgroup->pools.le_pool_id[3],
+			   rgroup->pools.tle_pool_id);
+
+		cxi_rgroup_print_ac_entry_info(rgroup, s);
+
+		seq_puts(s, "           ACs     CTs     EQs    PTEs    TGQs    TXQs    LE0s    LE1s    LE2s    LE3s    TLEs\n");
+		seq_puts(s, "  max   ");
+		for (i = 0; i < ARRAY_SIZE(rsrc_dump_order); i++) {
+			rc = cxi_rgroup_get_resource_entry(rgroup,
+							   rsrc_dump_order[i],
+							   &entry);
+			seq_printf(s, "%6lu  ", rc ? 0 : entry->limits.max);
+		}
+		seq_puts(s, "\n");
+
+		seq_puts(s, "  res   ");
+		for (i = 0; i < ARRAY_SIZE(rsrc_dump_order); i++) {
+			rc = cxi_rgroup_get_resource_entry(rgroup,
+							   rsrc_dump_order[i],
+							   &entry);
+			seq_printf(s, "%6lu  ", rc ? 0 : entry->limits.reserved);
+		}
+		seq_puts(s, "\n");
+
+		seq_puts(s, "Alloc   ");
+		for (i = 0; i < ARRAY_SIZE(rsrc_dump_order); i++) {
+			rc = cxi_rgroup_get_resource_entry(rgroup,
+							   rsrc_dump_order[i],
+							   &entry);
+			seq_printf(s, "%6lu  ", rc ? 0 : entry->limits.in_use);
+		}
+		seq_puts(s, "\n");
+	}
+
+	cxi_rx_profile_print(s);
+	cxi_tx_profile_print(s);
+
+	return 0;
+}
+
+static int dump_services(struct seq_file *s, void *unused)
+{
+	int i;
+	ulong value;
+	struct cass_dev *hw = s->private;
+	struct cxi_resource_use *rsrc_use = hw->resource_use;
+
+	spin_lock(&hw->rgrp_lock);
+
+	seq_puts(s, "Resources\n");
+	seq_puts(s, "           ACs     CTs     EQs    PTEs    TGQs    TXQs    LE0s    LE1s    LE2s    LE3s    TLEs\n");
+
+	seq_puts(s, "  Max ");
+	for (i = 0; i < ARRAY_SIZE(rsrc_dump_order); i++)
+		seq_printf(s, "  %6lu", rsrc_use[rsrc_dump_order[i]].max);
+	seq_puts(s, "\n");
+
+	seq_puts(s, "  Res ");
+	for (i = 0; i < ARRAY_SIZE(rsrc_dump_order); i++)
+		seq_printf(s, "  %6lu", rsrc_use[rsrc_dump_order[i]].reserved);
+	seq_puts(s, "\n");
+
+	seq_puts(s, "Alloc ");
+	for (i = 0; i < ARRAY_SIZE(rsrc_dump_order); i++)
+		seq_printf(s, "  %6lu", rsrc_use[rsrc_dump_order[i]].in_use);
+	seq_puts(s, "\n");
+
+	seq_puts(s, "Avail ");
+	for (i = 0; i < ARRAY_SIZE(rsrc_dump_order); i++) {
+		value = rsrc_use[rsrc_dump_order[i]].shared -
+			rsrc_use[rsrc_dump_order[i]].shared_use;
+		seq_printf(s, "  %6lu", value);
+	}
+	seq_puts(s, "\n\n");
+
+	dump_rgroups(hw, s);
+
+	spin_unlock(&hw->rgrp_lock);
+
+	return 0;
+}
+
+static int dump_service_debug_dev_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, dump_services, inode->i_private);
+}
+
+static const struct file_operations svc_debug_fops = {
+	.owner = THIS_MODULE,
+	.open = dump_service_debug_dev_open,
+	.read = seq_read,
+	.llseek  = seq_lseek,
+	.release = single_release,
+};
+
+void svc_service_debugfs_create(struct cass_dev *hw)
+{
+	hw->svc_debug = debugfs_create_file("services", 0444, hw->debug_dir,
+					    hw, &svc_debug_fops);
+}
+
+static int cass_port_uptime_str(time64_t time, char *buf, int len)
+{
+	int days;
+	int hours;
+	int mins;
+	int secs;
+	int bytes;
+
+	/* divide time by seconds per day to get days */
+	days  = time / (24 * 60 * 60);
+	time %= 24 * 60 * 60;
+
+	/* divide remainder by seconds per hour to get hours */
+	hours = time / (60 * 60);
+	time %= 60 * 60;
+
+	/* divide remainder by seconds per minute to get minutes */
+	mins  = time / 60;
+	time %= 60;
+
+	/* remainder in seconds */
+	secs  = time;
+
+	if (days)
+		bytes = snprintf(buf, len, "%dd %dh %dm %ds", days, hours, mins, secs);
+	else if (hours)
+		bytes = snprintf(buf, len, "%dh %dm %ds", hours, mins, secs);
+	else if (mins)
+		bytes = snprintf(buf, len, "%dm %ds", mins, secs);
+	else
+		bytes = snprintf(buf, len, "%ds", secs);
+
+	if (bytes > len)
+		return -ENOSPC;
+	else
+		return 0;
+}
+
+/*
+ * return the time (s) that we have been running for
+ * if we are not running return 0;
+ */
+static time64_t cass_port_uptime_get(struct cass_dev *hw)
+{
+	if (hw->port->lstate == CASS_LINK_STATUS_UP)
+		return  ktime_get_seconds() - hw->port->start_time;
+
+	return 0;
+}
+
+static void cass_uptime_debugfs_print(struct cass_dev *hw, struct seq_file *s)
+{
+	time64_t uptime;
+	char uptime_str[64];
+	int err;
+
+	uptime = cass_port_uptime_get(hw);
+	if (!uptime)
+		return;
+
+	err = cass_port_uptime_str(uptime, uptime_str, sizeof(uptime_str));
+	if (err) {
+		cxidev_err(&hw->cdev, "get uptime str failed [%d]\n", err);
+		return;
+	}
+
+	seq_printf(s, "uptime: %lld (%s)\n", uptime, uptime_str);
+}
+
+static void cass_lmon_debugfs_print(struct cass_dev *hw, struct seq_file *s)
+{
+	struct task_struct *lmon;
+	int limiter;
+	int dirn;
+	bool active;
+	u32 restart_count;
+
+	spin_lock(&hw->port->lock);
+	lmon  = hw->port->lmon;
+	limiter  = hw->port->lmon_limiter_on;
+	dirn  = hw->port->lmon_dirn;
+	active = hw->port->lmon_active;
+	restart_count = hw->port->link_restart_count;
+	spin_unlock(&hw->port->lock);
+
+	if (!lmon)
+		return;
+
+	seq_printf(s, "lmon: dirn %s%s%s", cass_lmon_dirn_str(dirn),
+		   active ? ", active" : "", limiter ? ", (limited)" : "");
+	if (cass_lmon_get_up_pause(hw))
+		seq_puts(s, ", up-paused");
+	if (hw->port->lattr.options & CASS_LINK_OPT_UP_AUTO_RESTART) {
+		seq_puts(s, ", up-auto-restart");
+		if (restart_count && (dirn == CASS_LMON_DIRECTION_UP))
+			seq_printf(s, " (%d)", restart_count);
+	}
+	seq_puts(s, "\n");
+}
+
+static void cass_link_debugfs_print(struct cass_dev *hw, struct seq_file *s)
+{
+	int state;
+	int down_origin;
+	int lerr;
+
+	spin_lock(&hw->port->lock);
+	state = hw->port->lstate;
+	lerr = hw->port->lerr;
+	down_origin = hw->port->link_down_origin;
+	spin_unlock(&hw->port->lock);
+
+	seq_printf(s, "link state: %s", cass_link_state_str(state));
+
+	if (state == CASS_LINK_STATUS_ERROR)
+		seq_printf(s, " [%d]\n", lerr);
+	else if (state == CASS_LINK_STATUS_DOWN)
+		seq_printf(s, " (%s)\n",
+			   cass_link_down_origin_str(down_origin));
+	else
+		seq_puts(s, "\n");
+}
+
+static int cass_port_show(struct seq_file *s, void *unused)
+{
+	struct cass_dev *hw = s->private;
+	char buf[DEBUGFS_BUFSIZE];
+	int nic_num = hw->uc_nic;
+
+	if (!cass_version(hw, CASSINI_1)) {
+		seq_puts(s, "NOT IMPLEMENTED!!\n");
+		return 0;
+	}
+
+	seq_printf(s, "** %d **\n", nic_num);
+
+	/* config */
+	spin_lock(&hw->port->lock);
+	seq_printf(s, "configured: %c%c%c%c\n",
+		   (hw->port->config_state & CASS_TYPE_CONFIGURED)   ? 't' : '-',
+		 (hw->port->config_state & CASS_PORT_CONFIGURED)   ? 'p' : '-',
+		 (hw->port->config_state & CASS_MEDIA_CONFIGURED)  ? 'm' : '-',
+		 (hw->port->config_state & CASS_LINK_CONFIGURED)   ? 'l' : '-');
+
+	/* port */
+	seq_printf(s, "type: ether (%s)\n",
+		   cass_port_subtype_str(hw->port->subtype));
+	spin_unlock(&hw->port->lock);
+
+	/* uptime */
+	cass_uptime_debugfs_print(hw, s);
+
+	/* media */
+	memset(buf, 0, DEBUGFS_BUFSIZE);
+	sbl_media_sysfs_sprint(hw->sbl, 0, buf, DEBUGFS_BUFSIZE);
+	seq_puts(s, buf);
+
+	/* pause */
+	cass_pause_debugfs_print(hw, s);
+
+	/* serdes */
+	memset(buf, 0, DEBUGFS_BUFSIZE);
+	sbl_serdes_sysfs_sprint(hw->sbl, 0, buf, DEBUGFS_BUFSIZE);
+	seq_puts(s, buf);
+
+	/* pcs */
+	memset(buf, 0, DEBUGFS_BUFSIZE);
+	sbl_pml_pcs_sysfs_sprint(hw->sbl, 0, buf, DEBUGFS_BUFSIZE);
+	seq_puts(s, buf);
+
+	/* lane degrade status */
+	memset(buf, 0, DEBUGFS_BUFSIZE);
+	sbl_pml_pcs_lane_degrade_sysfs_sprint(hw->sbl, 0, buf, DEBUGFS_BUFSIZE);
+	seq_puts(s, buf);
+
+	/* base link */
+	memset(buf, 0, DEBUGFS_BUFSIZE);
+	sbl_base_link_sysfs_sprint(hw->sbl, 0, buf, DEBUGFS_BUFSIZE);
+	seq_puts(s, buf);
+
+	/* base link */
+	memset(buf, 0, DEBUGFS_BUFSIZE);
+	sbl_fec_sysfs_sprint(hw->sbl, 0, buf, DEBUGFS_BUFSIZE);
+	seq_puts(s, buf);
+
+	/* link */
+	cass_link_debugfs_print(hw, s);
+	cass_lmon_debugfs_print(hw, s);
+
+	return 0;
+}
+
+static int cass_port_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, cass_port_show, inode->i_private);
+}
+
+static const struct file_operations cass_port_fops = {
+	.owner = THIS_MODULE,
+	.open = cass_port_open,
+	.read = seq_read,
+	.llseek  = seq_lseek,
+	.release = single_release,
+};
+
+void cass_port_debugfs_init(struct cass_dev *hw)
+{
+	debugfs_create_file("port", 0444, hw->debug_dir, hw, &cass_port_fops);
+}
+
+static int cass_sbl_counters_show(struct seq_file *s, void *unused)
+{
+	struct cass_dev *hw = s->private;
+	static char *sbl_counter_names[CASS_SBL_NUM_COUNTERS] = { CASS_SBL_COUNTER_NAMES };
+	static char *lmon_counter_names[CASS_LMON_NUM_COUNTERS] = { CASS_LMON_COUNTER_NAMES };
+	int i;
+
+	cass_sbl_counters_update(hw);
+
+	for (i = 0; i < CASS_SBL_NUM_COUNTERS; ++i)
+		seq_printf(s, "%s %d\n", sbl_counter_names[i], atomic_read(&hw->sbl_counters[i]));
+
+	for (i = 0; i < CASS_LMON_NUM_COUNTERS; ++i)
+		seq_printf(s, "%s %d\n", lmon_counter_names[i],
+			   atomic_read(&hw->port->lmon_counters[i]));
+
+	return 0;
+}
+
+static int cass_sbl_counters_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, cass_sbl_counters_show, inode->i_private);
+}
+
+static const struct file_operations cass_sbl_counters_fops = {
+	.owner = THIS_MODULE,
+	.open = cass_sbl_counters_open,
+	.read = seq_read,
+	.llseek  = seq_lseek,
+	.release = single_release,
+};
+
+void cass_sbl_counters_debugfs_init(struct cass_dev *hw)
+{
+	debugfs_create_file("counters", 0444, hw->debug_dir, hw, &cass_sbl_counters_fops);
+}
+
+void domain_debugfs_create(int vni, int pid, struct cass_dev *hw,
+			   struct cxi_domain_priv *domain_priv)
+{
+	char name[30];
+
+	sprintf(name, "%u_%u", vni, pid);
+	domain_priv->debug_dir = debugfs_create_dir(name, hw->domain_dir);
+	debugfs_create_u32("vni", 0444, domain_priv->debug_dir,
+			   &domain_priv->domain.vni);
+}
+
+void pt_debugfs_create(int id, struct cxi_pte_priv *pt, struct cass_dev *hw,
+		       struct cxi_lni_priv *lni_priv)
+{
+	char name[30];
+	char path[30];
+
+	sprintf(name, "%u", id);
+	pt->debug_dir = debugfs_create_dir(name, hw->pt_dir);
+	sprintf(path, "../../../pt/%u", id);
+	pt->lni_dir = debugfs_create_symlink(name, lni_priv->pt_dir,
+					     path);
+}
+
+void lni_debugfs_create(int id, struct cass_dev *hw, struct cxi_lni_priv *lni_priv)
+{
+	char name[30];
+
+	sprintf(name, "%d", id);
+	lni_priv->debug_dir = debugfs_create_dir(name, hw->lni_dir);
+	debugfs_create_u32("id", 0444, lni_priv->debug_dir, &lni_priv->lni.id);
+	debugfs_create_u32("rgid", 0444, lni_priv->debug_dir, &lni_priv->lni.rgid);
+	debugfs_create_u32("pid", 0444, lni_priv->debug_dir, &lni_priv->pid);
+
+	lni_priv->cq_dir = debugfs_create_dir("cq", lni_priv->debug_dir);
+	lni_priv->pt_dir = debugfs_create_dir("pt", lni_priv->debug_dir);
+	lni_priv->eq_dir = debugfs_create_dir("eq", lni_priv->debug_dir);
+	lni_priv->ct_dir = debugfs_create_dir("ct", lni_priv->debug_dir);
+	lni_priv->ac_dir = debugfs_create_dir("ac", lni_priv->debug_dir);
+}
+
+static int eq_debugfs_info(struct seq_file *s, void *unused)
+{
+	struct cxi_eq_priv *eq = s->private;
+
+	seq_printf(s, "EQ id: %u\n", eq->eq.eqn);
+	seq_puts(s, "event MSI vector: ");
+	if (eq->event_msi_irq) {
+		const struct cass_irq *irq = eq->event_msi_irq;
+
+		seq_printf(s, "%s\n", irq->irq_name);
+	} else {
+		seq_puts(s, "none\n");
+	}
+
+	seq_puts(s, "status MSI vector: ");
+	if (eq->status_msi_irq) {
+		const struct cass_irq *irq = eq->status_msi_irq;
+
+		seq_printf(s, "%s\n", irq->irq_name);
+	} else {
+		seq_puts(s, "none\n");
+	}
+
+	seq_printf(s, "slots: %lu\n", eq->queue_size);
+	seq_printf(s, "flags: %llx\n", eq->attr.flags);
+
+	return 0;
+}
+
+static int debug_eq_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, eq_debugfs_info, inode->i_private);
+}
+
+static const struct file_operations eq_fops = {
+	.owner = THIS_MODULE,
+	.open = debug_eq_open,
+	.read = seq_read,
+	.llseek  = seq_lseek,
+	.release = single_release,
+};
+
+void eq_debugfs_create(int id, struct cxi_eq_priv *eq, struct cass_dev *hw,
+		       struct cxi_lni_priv *lni_priv)
+{
+	char name[30];
+	char path[30];
+
+	sprintf(name, "%u", id);
+	eq->debug_file = debugfs_create_file(name, 0444, hw->eq_dir,
+					     eq, &eq_fops);
+	sprintf(path, "../../../eq/%u", id);
+	eq->lni_dir = debugfs_create_symlink(name, lni_priv->eq_dir,
+					     path);
+}
+
+static int cass_dmac_desc_sets_show(struct seq_file *s, void *unused)
+{
+	struct cass_dev *hw = s->private;
+	int i;
+	int j;
+	u16 count;
+	u16 index;
+	u16 numused;
+	const char *name;
+	union c_pi_cfg_dmac_desc desc;
+	s64 dst;
+	s32 src;
+	s32 len;
+	s16 rem;
+
+	mutex_lock(&hw->dmac.lock);
+	for (i = 0 ; i < DMAC_DESC_SET_COUNT ; ++i) {
+		count	= hw->dmac.desc_sets[i].count;
+		index	= hw->dmac.desc_sets[i].index;
+		numused = hw->dmac.desc_sets[i].numused;
+		name    = hw->dmac.desc_sets[i].name;
+		seq_printf(s, "desc_set[%02d]: count=%u index=%u numused=%u name='%s'\n",
+			   i, count, index, numused,
+			   name == NULL ? "" : name);
+		if (count != 0)
+			for (j = 0; j < count; ++j) {
+				cass_read(hw, C_PI_CFG_DMAC_DESC(index + j), &desc,
+					  sizeof(desc));
+				dst =  desc.qw[0];
+				src =  desc.qw[1] & 0xffffffff;
+				len = (desc.qw[1] >> 32) & 0x000fffff;
+				rem = (desc.qw[1] >> (32 + 20)) & 0x0fff;
+				seq_printf(s, "\tdesc[%04u]=0x%03x,0x%05x,0x%08x,0x%016llx %s\n",
+					   index + j, rem, len, src, dst,
+					   (((dst & 0x7f) == 0) ? "(dst 128-byte aligned)" : ""));
+			}
+	}
+	mutex_unlock(&hw->dmac.lock);
+	return 0;
+}
+
+static int cass_dmac_desc_sets_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, cass_dmac_desc_sets_show,
+			   inode->i_private);
+}
+
+static const struct file_operations cass_dmac_desc_sets_fops = {
+	.owner = THIS_MODULE,
+	.open = cass_dmac_desc_sets_open,
+	.read = seq_read,
+	.llseek	 = seq_lseek,
+	.release = single_release,
+};
+
+void cass_dmac_debugfs_init(struct cass_dev *hw)
+{
+	debugfs_create_file("dmac-desc-sets", 0444, hw->debug_dir,
+			    hw, &cass_dmac_desc_sets_fops);
+}
+
+static int cass_rmu_eth_filters_show(struct seq_file *s, void *unused)
+{
+	struct cass_dev *hw = s->private;
+	struct cxi_rmu_eth *rmu_eth;
+	int id;
+	int active_filters = 0;
+
+	mutex_lock(&hw->rmu_eth_lock);
+	idr_for_each_entry(&hw->rmu_eth_idr, rmu_eth, id) {
+		struct cxi_rmu_eth_priv *priv =
+			container_of(rmu_eth, struct cxi_rmu_eth_priv, rmu_eth);
+		unsigned int i;
+
+		for (i = 0; i < priv->set_list_quota; i++) {
+			union c_rmu_cfg_ptlte_set_list set_list;
+			union c_rmu_cfg_ptlte_set_list set_list_mask;
+			unsigned int hw_idx;
+			u8 mac[ETH_ALEN];
+			char func[8];
+			const char *type;
+			const char *rss;
+
+			if (!priv->mac_filter_slots[i])
+				continue;
+
+			hw_idx = priv->set_list_base + i;
+			if (priv->is_vf)
+				scnprintf(func, sizeof(func), "vf%u", priv->vf_num + 1);
+			else
+				scnprintf(func, sizeof(func), "pf");
+			rss = priv->mac_filter_slots[i] == CXI_RMU_ETH_FILTER_RSS ?
+				"on" : "off";
+
+			spin_lock(&hw->rmu_lock);
+			cass_read(hw, C_RMU_CFG_PTLTE_SET_LIST_X(hw_idx), &set_list,
+				  sizeof(set_list));
+			cass_shadow_read(hw, C_RMU_BASE,
+					 C_RMU_CFG_PTLTE_SET_LIST_Y_OFFSET(hw_idx),
+					 &set_list_mask, sizeof(set_list_mask));
+			spin_unlock(&hw->rmu_lock);
+
+			u64_to_ether_addr(set_list.dmac, mac);
+
+			if (!set_list.dmac && !set_list_mask.dmac)
+				type = "promisc";
+			else if (set_list.dmac == 0x010000000000ULL)
+				type = "allmcst";
+			else
+				type = "macaddr";
+
+			seq_printf(s,
+				   "func=%-4s client=%-3d slot=%-3u hw_idx=%-4u rss=%-3s type=%-7s mac=%pM ",
+				   func, id, i, hw_idx, rss, type, mac);
+			seq_printf(s,
+				   "match=%016llx:%016llx:%016llx:%016llx ",
+				   (unsigned long long)set_list.qw[0],
+				   (unsigned long long)set_list.qw[1],
+				   (unsigned long long)set_list.qw[2],
+				   (unsigned long long)set_list.qw[3]);
+			seq_printf(s,
+				   "mask=%016llx:%016llx:%016llx:%016llx",
+				   (unsigned long long)set_list_mask.qw[0],
+				   (unsigned long long)set_list_mask.qw[1],
+				   (unsigned long long)set_list_mask.qw[2],
+				   (unsigned long long)set_list_mask.qw[3]);
+			seq_puts(s, "\n");
+
+			active_filters++;
+		}
+	}
+
+	if (!active_filters)
+		seq_puts(s, "none\n");
+
+	mutex_unlock(&hw->rmu_eth_lock);
+
+	return 0;
+}
+
+static int cass_rmu_eth_filters_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, cass_rmu_eth_filters_show, inode->i_private);
+}
+
+static const struct file_operations cass_rmu_eth_filters_fops = {
+	.owner = THIS_MODULE,
+	.open = cass_rmu_eth_filters_open,
+	.read = seq_read,
+	.llseek  = seq_lseek,
+	.release = single_release,
+};
+
+static int tc_cfg_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, tc_cfg_show, inode->i_private);
+}
+
+static const struct file_operations tc_cfg_fops = {
+	.owner = THIS_MODULE,
+	.open = tc_cfg_open,
+	.read = seq_read,
+	.llseek  = seq_lseek,
+	.release = single_release,
+};
+
+void cass_probe_debugfs_init(struct cass_dev *hw)
+{
+	/* Various debugfs entries */
+	hw->debug_dir = debugfs_create_dir(hw->cdev.name, cxi_debug_dir);
+	hw->lni_dir = debugfs_create_dir("lni", hw->debug_dir);
+	hw->stats_dir = debugfs_create_dir("stats", hw->debug_dir);
+	hw->atu_dir = debugfs_create_dir("atu", hw->debug_dir);
+	debugfs_create_atomic_t("lni", 0444, hw->stats_dir, &hw->stats.lni);
+	debugfs_create_atomic_t("domain", 0444, hw->stats_dir,
+				&hw->stats.domain);
+	debugfs_create_atomic_t("eq", 0444, hw->stats_dir, &hw->stats.eq);
+	debugfs_create_atomic_t("txq", 0444, hw->stats_dir, &hw->stats.txq);
+	debugfs_create_atomic_t("tgq", 0444, hw->stats_dir, &hw->stats.tgq);
+	debugfs_create_atomic_t("pt", 0444, hw->stats_dir, &hw->stats.pt);
+	debugfs_create_atomic_t("ct", 0444, hw->stats_dir, &hw->stats.ct);
+	debugfs_create_atomic_t("ac", 0444, hw->stats_dir, &hw->stats.ac);
+	debugfs_create_atomic_t("md", 0444, hw->stats_dir, &hw->stats.md);
+
+	hw->domain_dir = debugfs_create_dir("domain", hw->debug_dir);
+	hw->eq_dir = debugfs_create_dir("eq", hw->debug_dir);
+	hw->cq_dir = debugfs_create_dir("cq", hw->debug_dir);
+	hw->pt_dir = debugfs_create_dir("pt", hw->debug_dir);
+	hw->ct_dir = debugfs_create_dir("ct", hw->debug_dir);
+	hw->ac_dir = debugfs_create_dir("ac", hw->debug_dir);
+
+	debugfs_create_file("tc_cfg", 0444, hw->debug_dir, hw, &tc_cfg_fops);
+	debugfs_create_atomic_t("error_inject", 0644, hw->atu_dir,
+				&hw->atu_error_inject);
+	debugfs_create_atomic_t("odp_requests", 0644, hw->atu_dir,
+				&hw->atu_odp_requests);
+	debugfs_create_atomic_t("atu_odp_fails", 0644, hw->atu_dir,
+				&hw->atu_odp_fails);
+	debugfs_create_atomic_t("atu_prb_expired", 0644, hw->atu_dir,
+				&hw->atu_prb_expired);
+
+	/* ODP Decouple stats */
+	debugfs_create_file("decouple_stats", 0644, hw->atu_dir, hw,
+			    &decouple_stats_fops);
+	debugfs_create_file("odp_sw_decouple", 0644, hw->atu_dir, hw,
+			    &sw_decouple_fops);
+
+	debugfs_create_file("uc_log", 0444, hw->debug_dir, hw, &uc_fops);
+	debugfs_create_file("rmu_eth_filters", 0444, hw->debug_dir, hw,
+			    &cass_rmu_eth_filters_fops);
+
+	/* setup SBL debugfs interface */
+	cass_port_debugfs_init(hw);
+
+	if (cass_version(hw, CASSINI_1))
+		cass_sbl_counters_debugfs_init(hw); /* Port counters */
+
+	cass_dmac_debugfs_init(hw);
+}
+
+void cq_debugfs_create(int id, struct cxi_cq_priv *cq, struct cass_dev *hw,
+		       struct cxi_lni_priv *lni_priv)
+{
+	char name[30];
+	char path[30];
+
+	sprintf(name, "%u", id);
+	cq->debug_dir = debugfs_create_dir(name, hw->cq_dir);
+	sprintf(path, "../../../cq/%u", id);
+	cq->lni_dir = debugfs_create_symlink(name, lni_priv->cq_dir, path);
+	debugfs_create_u32("id", 0444, cq->debug_dir, &cq->cass_cq.idx);
+}
+
+void ct_debugfs_setup(int id, struct cxi_ct_priv *ct_priv, struct cass_dev *hw,
+		      struct cxi_lni_priv *lni_priv)
+{
+	char name[30];
+	char path[30];
+
+	sprintf(name, "%u", id);
+	ct_priv->debug_dir = debugfs_create_dir(name, hw->ct_dir);
+	sprintf(path, "../../../ct/%u", id);
+	ct_priv->lni_dir = debugfs_create_symlink(name, lni_priv->ct_dir,
+						  path);
+}
+
+void ac_debugfs_create(int id, struct cass_ac *cac, struct cass_dev *hw,
+		       struct cxi_lni_priv *lni_priv)
+{
+	char name[30];
+	char path[30];
+
+	sprintf(name, "%u", id);
+	cac->debug_dir = debugfs_create_dir(name, hw->ac_dir);
+	sprintf(path, "../../../ac/%u", id);
+	cac->lni_dir = debugfs_create_symlink(name, lni_priv->ac_dir, path);
+}
diff --git a/drivers/net/ethernet/hpe/ss1/cass_ss1_debugfs.h b/drivers/net/ethernet/hpe/ss1/cass_ss1_debugfs.h
new file mode 100644
index 000000000000..26f9bc58ba5e
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_ss1_debugfs.h
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2018 Hewlett Packard Enterprise Development LP */
+
+#ifndef __CASS_DEBUGFS_H__
+#define __CASS_DEBUGFS_H__
+#include <linux/dcache.h>
+#include <linux/debugfs.h>
+#include <linux/netdevice.h>
+
+#ifdef CONFIG_DEBUG_FS
+
+void cass_port_debugfs_init(struct cass_dev *hw);
+void cass_sbl_counters_debugfs_init(struct cass_dev *hw);
+void domain_debugfs_create(int vni, int pid, struct cass_dev *hw,
+			   struct cxi_domain_priv *domain_priv);
+void pt_debugfs_create(int id, struct cxi_pte_priv *pt, struct cass_dev *hw,
+		       struct cxi_lni_priv *lni_priv);
+void lni_debugfs_create(int id, struct cass_dev *hw, struct cxi_lni_priv *lni_priv);
+void eq_debugfs_create(int id, struct cxi_eq_priv *eq, struct cass_dev *hw,
+		       struct cxi_lni_priv *lni_priv);
+void cass_dmac_debugfs_init(struct cass_dev *hw);
+void cass_probe_debugfs_init(struct cass_dev *hw);
+void cq_debugfs_create(int id, struct cxi_cq_priv *cq, struct cass_dev *hw,
+		       struct cxi_lni_priv *lni_priv);
+void ct_debugfs_setup(int id, struct cxi_ct_priv *ct_priv, struct cass_dev *hw,
+		      struct cxi_lni_priv *lni_priv);
+void ac_debugfs_create(int id, struct cass_ac *cac, struct cass_dev *hw,
+		       struct cxi_lni_priv *lni_priv);
+void svc_service_debugfs_create(struct cass_dev *hw);
+#else
+static inline void cass_port_debugfs_init(struct cass_dev *hw)
+{
+}
+
+static inline void cass_sbl_counters_debugfs_init(struct cass_dev *hw)
+{
+}
+
+static inline void domain_debugfs_create(int vni, int pid, struct cass_dev *hw,
+					 struct cxi_domain_priv *domain_priv)
+{
+}
+
+static inline void pt_debugfs_create(int id, struct cxi_pte_priv *pt, struct cass_dev *hw,
+				     struct cxi_lni_priv *lni_priv)
+{
+}
+
+static inline void lni_debugfs_create(int id, struct cass_dev *hw,
+				      struct cxi_lni_priv *lni_priv)
+{
+}
+
+static inline void eq_debugfs_create(int id, struct cxi_eq_priv *eq, struct cass_dev *hw,
+				     struct cxi_lni_priv *lni_priv)
+{
+}
+
+static inline void cass_dmac_debugfs_init(struct cass_dev *hw)
+{
+}
+
+static inline void cass_probe_debugfs_init(struct cass_dev *hw)
+{
+}
+
+static inline void cq_debugfs_create(int id, struct cxi_cq_priv *cq,
+				     struct cass_dev *hw, struct cxi_lni_priv *lni_priv)
+{
+}
+
+static inline void ct_debugfs_setup(int id, struct cxi_ct_priv *ct_priv, struct cass_dev *hw,
+				    struct cxi_lni_priv *lni_priv)
+{
+}
+
+static inline void ac_debugfs_create(int id, struct cass_ac *cac, struct cass_dev *hw,
+				     struct cxi_lni_priv *lni_priv)
+{
+}
+
+static inline void svc_service_debugfs_create(struct cass_dev *hw)
+{
+}
+#endif
+#endif
diff --git a/drivers/net/ethernet/hpe/ss1/cass_telem_tables.h b/drivers/net/ethernet/hpe/ss1/cass_telem_tables.h
new file mode 100644
index 000000000000..b9e925172ec3
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_telem_tables.h
@@ -0,0 +1,3874 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2024 Hewlett Packard Enterprise Development LP */
+
+/*
+ * Location of each Cassini telemetry item, indexed by item ID. The item
+ * IDs and these locations come from the Cassini hardware description;
+ * user space names the items, the kernel only knows their numbers.
+ */
+
+#ifndef _CASS_TELEM_TABLES_H
+#define _CASS_TELEM_TABLES_H
+
+/* offset, lsb, numbits, type */
+#define TI(o, l, n, t) { .offset = (o), .lsb = (l), .numbits = (n), \
+			 .type = CASSINI_TELEMETRY_ITEM_TYPE_##t }
+#define TU { .type = CASSINI_TELEMETRY_ITEM_TYPE_UNDEFINED }
+
+#define C1_TELEM_TOTAL	1923
+#define C1_TELEM_VALID	1890
+static const struct telem_item c1_items[C1_TELEM_TOTAL] = {
+	TU,
+	TI(0x100205d0, 0, 56, COUNTER),
+	TI(0x100205d8, 0, 56, COUNTER),
+	TI(0x100205e0, 0, 56, COUNTER),
+	TI(0x100205e8, 0, 56, COUNTER),
+	TI(0x100205c8, 0, 56, COUNTER),
+	TI(0x10020590, 0, 56, COUNTER),
+	TI(0x10020508, 0, 56, COUNTER),
+	TI(0x10020510, 0, 56, COUNTER),
+	TI(0x10020518, 0, 56, COUNTER),
+	TI(0x10020520, 0, 56, COUNTER),
+	TI(0x100205b8, 0, 56, COUNTER),
+	TI(0x100204a8, 0, 56, COUNTER),
+	TI(0x100204b0, 0, 56, COUNTER),
+	TI(0x100204b8, 0, 56, COUNTER),
+	TI(0x100204c0, 0, 56, COUNTER),
+	TI(0x100205a8, 0, 56, COUNTER),
+	TI(0x10020588, 0, 56, COUNTER),
+	TI(0x10020430, 0, 56, COUNTER),
+	TI(0x10020438, 0, 56, COUNTER),
+	TI(0x10020440, 0, 56, COUNTER),
+	TI(0x10020448, 0, 56, COUNTER),
+	TI(0x10020450, 0, 56, COUNTER),
+	TI(0x10020458, 0, 56, COUNTER),
+	TI(0x10020460, 0, 56, COUNTER),
+	TI(0x10020468, 0, 56, COUNTER),
+	TI(0x10020470, 0, 56, COUNTER),
+	TI(0x10020478, 0, 56, COUNTER),
+	TI(0x10020480, 0, 56, COUNTER),
+	TI(0x10020488, 0, 56, COUNTER),
+	TI(0x10020410, 0, 56, COUNTER),
+	TI(0x10020418, 0, 56, COUNTER),
+	TI(0x10020420, 0, 56, COUNTER),
+	TI(0x10020428, 0, 56, COUNTER),
+	TI(0x100204a0, 0, 56, COUNTER),
+	TI(0x10020498, 0, 56, COUNTER),
+	TI(0x10020490, 0, 56, COUNTER),
+	TI(0x100204f8, 0, 56, COUNTER),
+	TI(0x100204f0, 0, 56, COUNTER),
+	TI(0x100204e8, 0, 56, COUNTER),
+	TI(0x10020568, 0, 56, COUNTER),
+	TI(0x10020570, 0, 56, COUNTER),
+	TI(0x10020578, 0, 56, COUNTER),
+	TI(0x10020580, 0, 56, COUNTER),
+	TI(0x10020500, 0, 56, COUNTER),
+	TI(0x100205a0, 0, 56, COUNTER),
+	TI(0x10020598, 0, 56, COUNTER),
+	TI(0x100205f0, 0, 56, COUNTER),
+	TI(0x100205f8, 0, 56, COUNTER),
+	TI(0x10020400, 0, 56, COUNTER),
+	TI(0x10020408, 0, 56, COUNTER),
+	TI(0x10020528, 0, 56, COUNTER),
+	TI(0x10020530, 0, 56, COUNTER),
+	TI(0x10020538, 0, 56, COUNTER),
+	TI(0x10020540, 0, 56, COUNTER),
+	TI(0x100204c8, 0, 56, COUNTER),
+	TI(0x100204d0, 0, 56, COUNTER),
+	TI(0x100204d8, 0, 56, COUNTER),
+	TI(0x100204e0, 0, 56, COUNTER),
+	TI(0x10020548, 0, 56, COUNTER),
+	TI(0x10020550, 0, 56, COUNTER),
+	TI(0x10020558, 0, 56, COUNTER),
+	TI(0x10020560, 0, 56, COUNTER),
+	TI(0x100205c0, 0, 56, COUNTER),
+	TI(0x100205b0, 0, 56, COUNTER),
+	TI(0x540, 4, 16, COUNTER),
+	TI(0x100280, 0, 56, COUNTER),
+	TI(0x100288, 0, 56, COUNTER),
+	TI(0x100290, 0, 56, COUNTER),
+	TI(0x100298, 0, 56, COUNTER),
+	TI(0x1002a0, 0, 56, COUNTER),
+	TI(0x1002a8, 0, 56, COUNTER),
+	TI(0x1002b0, 0, 56, COUNTER),
+	TI(0x1002b8, 0, 56, COUNTER),
+	TI(0x1002c0, 0, 56, COUNTER),
+	TI(0x1002c8, 0, 56, COUNTER),
+	TI(0x1002d0, 0, 56, COUNTER),
+	TI(0x1002d8, 0, 56, COUNTER),
+	TI(0x1002e0, 0, 56, COUNTER),
+	TI(0x1002e8, 0, 56, COUNTER),
+	TI(0x1002f0, 0, 56, COUNTER),
+	TI(0x1002f8, 0, 56, COUNTER),
+	TI(0x100130, 0, 56, COUNTER),
+	TI(0x100140, 0, 56, COUNTER),
+	TI(0x100138, 0, 56, COUNTER),
+	TI(0x100148, 0, 56, COUNTER),
+	TI(0x100158, 0, 56, COUNTER),
+	TI(0x100150, 0, 56, COUNTER),
+	TI(0x100300, 0, 56, COUNTER),
+	TI(0x100308, 0, 56, COUNTER),
+	TI(0x100310, 0, 56, COUNTER),
+	TI(0x100318, 0, 56, COUNTER),
+	TI(0x100200, 0, 56, COUNTER),
+	TI(0x100208, 0, 56, COUNTER),
+	TI(0x100210, 0, 56, COUNTER),
+	TI(0x100218, 0, 56, COUNTER),
+	TI(0x100220, 0, 56, COUNTER),
+	TI(0x100228, 0, 56, COUNTER),
+	TI(0x100230, 0, 56, COUNTER),
+	TI(0x100238, 0, 56, COUNTER),
+	TI(0x100240, 0, 56, COUNTER),
+	TI(0x100248, 0, 56, COUNTER),
+	TI(0x100250, 0, 56, COUNTER),
+	TI(0x100258, 0, 56, COUNTER),
+	TI(0x100260, 0, 56, COUNTER),
+	TI(0x100268, 0, 56, COUNTER),
+	TI(0x100270, 0, 56, COUNTER),
+	TI(0x100278, 0, 56, COUNTER),
+	TI(0x100018, 0, 56, COUNTER),
+	TI(0x100010, 0, 56, COUNTER),
+	TI(0x100020, 0, 56, COUNTER),
+	TI(0x100028, 0, 56, COUNTER),
+	TI(0x1001a0, 0, 56, COUNTER),
+	TI(0x1001a8, 0, 56, COUNTER),
+	TI(0x1001b0, 0, 56, COUNTER),
+	TI(0x1001b8, 0, 56, COUNTER),
+	TI(0x100180, 0, 56, COUNTER),
+	TI(0x100188, 0, 56, COUNTER),
+	TI(0x100190, 0, 56, COUNTER),
+	TI(0x100198, 0, 56, COUNTER),
+	TI(0x100160, 0, 56, COUNTER),
+	TI(0x100168, 0, 56, COUNTER),
+	TI(0x100170, 0, 56, COUNTER),
+	TI(0x100178, 0, 56, COUNTER),
+	TI(0x1001c0, 0, 56, COUNTER),
+	TI(0x1001c8, 0, 56, COUNTER),
+	TI(0x1001d0, 0, 56, COUNTER),
+	TI(0x1001d8, 0, 56, COUNTER),
+	TI(0x1003e0, 0, 56, COUNTER),
+	TI(0x1003e8, 0, 56, COUNTER),
+	TI(0x1003f0, 0, 56, COUNTER),
+	TI(0x1003f8, 0, 56, COUNTER),
+	TI(0x1003a0, 0, 56, COUNTER),
+	TI(0x1003a8, 0, 56, COUNTER),
+	TI(0x1003b0, 0, 56, COUNTER),
+	TI(0x1003b8, 0, 56, COUNTER),
+	TI(0x1003c0, 0, 56, COUNTER),
+	TI(0x1003c8, 0, 56, COUNTER),
+	TI(0x1003d0, 0, 56, COUNTER),
+	TI(0x1003d8, 0, 56, COUNTER),
+	TI(0x100380, 0, 56, COUNTER),
+	TI(0x100388, 0, 56, COUNTER),
+	TI(0x100390, 0, 56, COUNTER),
+	TI(0x100398, 0, 56, COUNTER),
+	TI(0x100080, 0, 56, COUNTER),
+	TI(0x100088, 0, 56, COUNTER),
+	TI(0x100090, 0, 56, COUNTER),
+	TI(0x100098, 0, 56, COUNTER),
+	TI(0x100120, 0, 56, COUNTER),
+	TI(0x100128, 0, 56, COUNTER),
+	TI(0x1001e0, 0, 56, COUNTER),
+	TI(0x1001e8, 0, 56, COUNTER),
+	TI(0x1001f0, 0, 56, COUNTER),
+	TI(0x1001f8, 0, 56, COUNTER),
+	TI(0x1000a0, 0, 56, COUNTER),
+	TI(0x1000a8, 0, 56, COUNTER),
+	TI(0x1000b0, 0, 56, COUNTER),
+	TI(0x1000b8, 0, 56, COUNTER),
+	TI(0x100100, 0, 56, COUNTER),
+	TI(0x100110, 0, 56, COUNTER),
+	TI(0x100108, 0, 56, COUNTER),
+	TI(0x100118, 0, 56, COUNTER),
+	TI(0x100060, 0, 56, COUNTER),
+	TI(0x100068, 0, 56, COUNTER),
+	TI(0x100070, 0, 56, COUNTER),
+	TI(0x100078, 0, 56, COUNTER),
+	TI(0x100038, 0, 56, COUNTER),
+	TI(0x100030, 0, 56, COUNTER),
+	TI(0x8b0, 24, 5, UGAUGE),
+	TI(0x8b8, 52, 9, UGAUGE),
+	TI(0x8b8, 40, 9, UGAUGE),
+	TI(0x8b0, 0, 10, UGAUGE),
+	TI(0x8b0, 16, 4, UGAUGE),
+	TI(0x8b8, 0, 5, UGAUGE),
+	TI(0x8b0, 56, 5, UGAUGE),
+	TI(0x8b0, 48, 5, UGAUGE),
+	TI(0x8b8, 24, 3, UGAUGE),
+	TI(0x8b8, 36, 3, UGAUGE),
+	TI(0x8b8, 16, 3, UGAUGE),
+	TI(0x8b0, 40, 7, UGAUGE),
+	TI(0x8b8, 8, 5, UGAUGE),
+	TI(0x8b8, 32, 4, UGAUGE),
+	TI(0x4a000, 0, 56, COUNTER),
+	TI(0x4a008, 0, 56, COUNTER),
+	TI(0x4a010, 0, 56, COUNTER),
+	TI(0x4a018, 0, 56, COUNTER),
+	TI(0x4b000, 0, 41, UGAUGE),
+	TI(0x4b008, 0, 41, UGAUGE),
+	TI(0x4b010, 0, 41, UGAUGE),
+	TI(0x4b018, 0, 41, UGAUGE),
+	TI(0x4b020, 0, 41, UGAUGE),
+	TI(0x4b028, 0, 41, UGAUGE),
+	TI(0x4b030, 0, 41, UGAUGE),
+	TI(0x4b038, 0, 41, UGAUGE),
+	TI(0x4b040, 0, 41, UGAUGE),
+	TI(0x4b048, 0, 41, UGAUGE),
+	TI(0x4b050, 0, 41, UGAUGE),
+	TI(0x4b058, 0, 41, UGAUGE),
+	TI(0x4b060, 0, 41, UGAUGE),
+	TI(0x4b068, 0, 41, UGAUGE),
+	TI(0x4b070, 0, 41, UGAUGE),
+	TI(0x4b078, 0, 41, UGAUGE),
+	TI(0x4b080, 0, 41, UGAUGE),
+	TI(0x4b088, 0, 41, UGAUGE),
+	TI(0x4b090, 0, 41, UGAUGE),
+	TI(0x4b098, 0, 41, UGAUGE),
+	TI(0x4b0a0, 0, 41, UGAUGE),
+	TI(0x4b0a8, 0, 41, UGAUGE),
+	TI(0x4b0b0, 0, 41, UGAUGE),
+	TI(0x4b0b8, 0, 41, UGAUGE),
+	TI(0x4b0c0, 0, 41, UGAUGE),
+	TI(0x4b0c8, 0, 41, UGAUGE),
+	TI(0x4b0d0, 0, 41, UGAUGE),
+	TI(0x4b0d8, 0, 41, UGAUGE),
+	TI(0x4b0e0, 0, 41, UGAUGE),
+	TI(0x4b0e8, 0, 41, UGAUGE),
+	TI(0x4b0f0, 0, 41, UGAUGE),
+	TI(0x4b0f8, 0, 41, UGAUGE),
+	TI(0x4b100, 0, 41, UGAUGE),
+	TI(0x4b108, 0, 41, UGAUGE),
+	TI(0x4b110, 0, 41, UGAUGE),
+	TI(0x4b118, 0, 41, UGAUGE),
+	TI(0x4b120, 0, 41, UGAUGE),
+	TI(0x4b128, 0, 41, UGAUGE),
+	TI(0x4b130, 0, 41, UGAUGE),
+	TI(0x4b138, 0, 41, UGAUGE),
+	TI(0x4b140, 0, 41, UGAUGE),
+	TI(0x4b148, 0, 41, UGAUGE),
+	TI(0x4b150, 0, 41, UGAUGE),
+	TI(0x4b158, 0, 41, UGAUGE),
+	TI(0x4b160, 0, 41, UGAUGE),
+	TI(0x4b168, 0, 41, UGAUGE),
+	TI(0x4b170, 0, 41, UGAUGE),
+	TI(0x4b178, 0, 41, UGAUGE),
+	TI(0x4a020, 0, 56, COUNTER),
+	TI(0x4a028, 0, 56, COUNTER),
+	TI(0x4a030, 0, 56, COUNTER),
+	TI(0x4a038, 0, 56, COUNTER),
+	TI(0x4a040, 0, 56, COUNTER),
+	TI(0x4a048, 0, 56, COUNTER),
+	TI(0x4a050, 0, 56, COUNTER),
+	TI(0x4a058, 0, 56, COUNTER),
+	TI(0x4a080, 0, 56, COUNTER),
+	TI(0x4a088, 0, 56, COUNTER),
+	TI(0x4a090, 0, 56, COUNTER),
+	TI(0x4a098, 0, 56, COUNTER),
+	TI(0x850, 0, 12, UGAUGE),
+	TI(0x858, 0, 12, UGAUGE),
+	TI(0x860, 0, 12, UGAUGE),
+	TI(0x868, 0, 12, UGAUGE),
+	TI(0x4a060, 0, 56, COUNTER),
+	TI(0x4a068, 0, 56, COUNTER),
+	TI(0x4a070, 0, 56, COUNTER),
+	TI(0x4a078, 0, 56, COUNTER),
+	TI(0x100008, 0, 56, COUNTER),
+	TI(0x100000, 0, 56, COUNTER),
+	TI(0x1000e0, 0, 56, COUNTER),
+	TI(0x1000e8, 0, 56, COUNTER),
+	TI(0x1000f0, 0, 56, COUNTER),
+	TI(0x1000f8, 0, 56, COUNTER),
+	TI(0x1000c0, 0, 56, COUNTER),
+	TI(0x1000c8, 0, 56, COUNTER),
+	TI(0x1000d0, 0, 56, COUNTER),
+	TI(0x1000d8, 0, 56, COUNTER),
+	TI(0x100040, 0, 56, COUNTER),
+	TI(0x100b40, 0, 56, COUNTER),
+	TI(0x100b48, 0, 56, COUNTER),
+	TI(0x100b50, 0, 56, COUNTER),
+	TI(0x100b58, 0, 56, COUNTER),
+	TI(0x100d20, 0, 56, COUNTER),
+	TI(0x100aa0, 0, 56, COUNTER),
+	TI(0x100aa8, 0, 56, COUNTER),
+	TI(0x100ab0, 0, 56, COUNTER),
+	TI(0x100ab8, 0, 56, COUNTER),
+	TI(0x100c90, 0, 56, COUNTER),
+	TI(0x100c98, 0, 56, COUNTER),
+	TI(0x100c58, 0, 56, COUNTER),
+	TI(0x100c60, 0, 56, COUNTER),
+	TI(0x100c68, 0, 56, COUNTER),
+	TI(0x100b20, 0, 56, COUNTER),
+	TI(0x100b28, 0, 56, COUNTER),
+	TI(0x100b30, 0, 56, COUNTER),
+	TI(0x100b38, 0, 56, COUNTER),
+	TI(0x100b00, 0, 56, COUNTER),
+	TI(0x100b08, 0, 56, COUNTER),
+	TI(0x100b10, 0, 56, COUNTER),
+	TI(0x100b18, 0, 56, COUNTER),
+	TI(0x100e50, 0, 56, COUNTER),
+	TI(0x100e60, 0, 56, COUNTER),
+	TI(0x100e58, 0, 56, COUNTER),
+	TI(0x100e68, 0, 56, COUNTER),
+	TI(0x100e90, 0, 56, COUNTER),
+	TI(0x100a80, 0, 56, COUNTER),
+	TI(0x100a88, 0, 56, COUNTER),
+	TI(0x100a90, 0, 56, COUNTER),
+	TI(0x100a98, 0, 56, COUNTER),
+	TI(0x100b60, 0, 56, COUNTER),
+	TI(0x100b68, 0, 56, COUNTER),
+	TI(0x100b70, 0, 56, COUNTER),
+	TI(0x100b78, 0, 56, COUNTER),
+	TI(0x100d10, 0, 56, COUNTER),
+	TI(0x100cb0, 0, 56, COUNTER),
+	TI(0x100cb8, 0, 56, COUNTER),
+	TI(0x100d00, 0, 56, COUNTER),
+	TI(0x100d08, 0, 56, COUNTER),
+	TI(0x100cd0, 0, 56, COUNTER),
+	TI(0x100cd8, 0, 56, COUNTER),
+	TI(0x100d18, 0, 56, COUNTER),
+	TI(0x100cc0, 0, 56, COUNTER),
+	TI(0x100cc8, 0, 56, COUNTER),
+	TI(0x100ca8, 0, 56, COUNTER),
+	TI(0x100ce0, 0, 56, COUNTER),
+	TI(0x100ce8, 0, 56, COUNTER),
+	TI(0x100cf0, 0, 56, COUNTER),
+	TI(0x100cf8, 0, 56, COUNTER),
+	TI(0x100d88, 0, 56, COUNTER),
+	TI(0x100d50, 0, 56, COUNTER),
+	TI(0x100d70, 0, 56, COUNTER),
+	TI(0x100dc8, 0, 56, COUNTER),
+	TI(0x100e30, 0, 56, COUNTER),
+	TI(0x100e20, 0, 56, COUNTER),
+	TI(0x100dc0, 0, 56, COUNTER),
+	TI(0x100dd8, 0, 56, COUNTER),
+	TI(0x100d58, 0, 56, COUNTER),
+	TI(0x100d78, 0, 56, COUNTER),
+	TI(0x100d48, 0, 56, COUNTER),
+	TI(0x100d68, 0, 56, COUNTER),
+	TI(0x100d98, 0, 56, COUNTER),
+	TI(0x100de8, 0, 56, COUNTER),
+	TI(0x100e38, 0, 56, COUNTER),
+	TI(0x100de0, 0, 56, COUNTER),
+	TI(0x100d40, 0, 56, COUNTER),
+	TI(0x100d60, 0, 56, COUNTER),
+	TI(0x100db8, 0, 56, COUNTER),
+	TI(0x100d90, 0, 56, COUNTER),
+	TI(0x100da0, 0, 56, COUNTER),
+	TI(0x100d80, 0, 56, COUNTER),
+	TI(0x100da8, 0, 56, COUNTER),
+	TI(0x100e28, 0, 56, COUNTER),
+	TI(0x100dd0, 0, 56, COUNTER),
+	TI(0x100db0, 0, 56, COUNTER),
+	TI(0x100a40, 0, 56, COUNTER),
+	TI(0x100a48, 0, 56, COUNTER),
+	TI(0x100a50, 0, 56, COUNTER),
+	TI(0x100a58, 0, 56, COUNTER),
+	TI(0x100a60, 0, 56, COUNTER),
+	TI(0x100a68, 0, 56, COUNTER),
+	TI(0x100a70, 0, 56, COUNTER),
+	TI(0x100a78, 0, 56, COUNTER),
+	TI(0x100a20, 0, 56, COUNTER),
+	TI(0x100a28, 0, 56, COUNTER),
+	TI(0x100a30, 0, 56, COUNTER),
+	TI(0x100a38, 0, 56, COUNTER),
+	TI(0x100a00, 0, 56, COUNTER),
+	TI(0x100a08, 0, 56, COUNTER),
+	TI(0x100a10, 0, 56, COUNTER),
+	TI(0x100a18, 0, 56, COUNTER),
+	TI(0x100ae0, 0, 56, COUNTER),
+	TI(0x100ae8, 0, 56, COUNTER),
+	TI(0x100af0, 0, 56, COUNTER),
+	TI(0x100af8, 0, 56, COUNTER),
+	TI(0x100c80, 0, 56, COUNTER),
+	TI(0x100c88, 0, 56, COUNTER),
+	TI(0x100c40, 0, 56, COUNTER),
+	TI(0x100c48, 0, 56, COUNTER),
+	TI(0x100c50, 0, 56, COUNTER),
+	TI(0x100bc8, 0, 56, COUNTER),
+	TI(0x100bd8, 0, 56, COUNTER),
+	TI(0x100bc0, 0, 56, COUNTER),
+	TI(0x100bb0, 0, 56, COUNTER),
+	TI(0x100bb8, 0, 56, COUNTER),
+	TI(0x100bd0, 0, 56, COUNTER),
+	TI(0x100b98, 0, 56, COUNTER),
+	TI(0x100ba8, 0, 56, COUNTER),
+	TI(0x100b90, 0, 56, COUNTER),
+	TI(0x100b80, 0, 56, COUNTER),
+	TI(0x100b88, 0, 56, COUNTER),
+	TI(0x100ba0, 0, 56, COUNTER),
+	TI(0x100ca0, 0, 56, COUNTER),
+	TI(0x100e40, 0, 56, COUNTER),
+	TI(0x100e48, 0, 56, COUNTER),
+	TI(0x100bf8, 0, 56, COUNTER),
+	TI(0x100c08, 0, 56, COUNTER),
+	TI(0x100bf0, 0, 56, COUNTER),
+	TI(0x100be0, 0, 56, COUNTER),
+	TI(0x100be8, 0, 56, COUNTER),
+	TI(0x100c00, 0, 56, COUNTER),
+	TI(0x100ac0, 0, 56, COUNTER),
+	TI(0x100ac8, 0, 56, COUNTER),
+	TI(0x100ad0, 0, 56, COUNTER),
+	TI(0x100ad8, 0, 56, COUNTER),
+	TI(0x100c28, 0, 56, COUNTER),
+	TI(0x100c38, 0, 56, COUNTER),
+	TI(0x100c20, 0, 56, COUNTER),
+	TI(0x100c10, 0, 56, COUNTER),
+	TI(0x100c18, 0, 56, COUNTER),
+	TI(0x100c30, 0, 56, COUNTER),
+	TI(0x100e78, 0, 56, COUNTER),
+	TI(0x100e80, 0, 56, COUNTER),
+	TI(0x8800808, 0, 9, UGAUGE),
+	TI(0x8800808, 16, 9, UGAUGE),
+	TI(0x100e88, 0, 56, COUNTER),
+	TI(0x100d30, 0, 56, COUNTER),
+	TI(0x100d38, 0, 56, COUNTER),
+	TI(0x100d28, 0, 56, COUNTER),
+	TI(0x100c70, 0, 56, COUNTER),
+	TI(0x100c78, 0, 56, COUNTER),
+	TI(0x100e70, 0, 56, COUNTER),
+	TI(0x10004b8, 4, 16, COUNTER),
+	TI(0x1002000, 0, 56, COUNTER),
+	TI(0x10020c0, 0, 56, COUNTER),
+	TI(0x10020c8, 0, 56, COUNTER),
+	TI(0x10020d0, 0, 56, COUNTER),
+	TI(0x10020d8, 0, 56, COUNTER),
+	TI(0x10020e0, 0, 56, COUNTER),
+	TI(0x10020e8, 0, 56, COUNTER),
+	TI(0x10020f0, 0, 56, COUNTER),
+	TI(0x10020f8, 0, 56, COUNTER),
+	TI(0x10022b8, 0, 56, COUNTER),
+	TI(0x10022b0, 0, 56, COUNTER),
+	TI(0x10022a8, 0, 56, COUNTER),
+	TI(0x1002290, 0, 56, COUNTER),
+	TI(0x1002298, 0, 56, COUNTER),
+	TI(0x1002288, 0, 56, COUNTER),
+	TI(0x10022a0, 0, 56, COUNTER),
+	TI(0x1002280, 0, 56, COUNTER),
+	TI(0x1002270, 0, 56, COUNTER),
+	TI(0x1002278, 0, 56, COUNTER),
+	TI(0x1002620, 0, 56, COUNTER),
+	TU,
+	TI(0x1002630, 0, 56, COUNTER),
+	TI(0x1002608, 0, 56, COUNTER),
+	TI(0x1002660, 0, 56, COUNTER),
+	TI(0x1002648, 0, 56, COUNTER),
+	TI(0x1002688, 0, 56, COUNTER),
+	TI(0x1002678, 0, 56, COUNTER),
+	TI(0x1002668, 0, 56, COUNTER),
+	TI(0x1002670, 0, 56, COUNTER),
+	TI(0x1002610, 0, 56, COUNTER),
+	TI(0x1002618, 0, 56, COUNTER),
+	TI(0x10025f8, 0, 56, COUNTER),
+	TI(0x1002600, 0, 56, COUNTER),
+	TI(0x1002628, 0, 56, COUNTER),
+	TI(0x1002650, 0, 56, COUNTER),
+	TI(0x1002638, 0, 56, COUNTER),
+	TI(0x1002658, 0, 56, COUNTER),
+	TI(0x1002640, 0, 56, COUNTER),
+	TI(0x1002690, 0, 56, COUNTER),
+	TI(0x1002680, 0, 56, COUNTER),
+	TI(0x10025a0, 0, 56, COUNTER),
+	TU,
+	TU,
+	TU,
+	TI(0x10025b0, 0, 56, COUNTER),
+	TI(0x1002590, 0, 56, COUNTER),
+	TI(0x1002598, 0, 56, COUNTER),
+	TU,
+	TU,
+	TI(0x1002580, 0, 56, COUNTER),
+	TI(0x1002588, 0, 56, COUNTER),
+	TI(0x10025a8, 0, 56, COUNTER),
+	TI(0x10025e8, 0, 56, COUNTER),
+	TI(0x10025c0, 0, 56, COUNTER),
+	TI(0x10025c8, 0, 56, COUNTER),
+	TI(0x10025b8, 0, 56, COUNTER),
+	TI(0x10025d8, 0, 56, COUNTER),
+	TI(0x10025e0, 0, 56, COUNTER),
+	TI(0x10025d0, 0, 56, COUNTER),
+	TI(0x10025f0, 0, 56, COUNTER),
+	TI(0x1002570, 0, 56, COUNTER),
+	TI(0x1002568, 0, 56, COUNTER),
+	TI(0x1002578, 0, 56, COUNTER),
+	TU,
+	TI(0x10024c0, 0, 56, COUNTER),
+	TI(0x10024c8, 0, 56, COUNTER),
+	TI(0x10024d0, 0, 56, COUNTER),
+	TI(0x10024d8, 0, 56, COUNTER),
+	TI(0x10024e0, 0, 56, COUNTER),
+	TI(0x10024e8, 0, 56, COUNTER),
+	TI(0x10024f0, 0, 56, COUNTER),
+	TI(0x10024f8, 0, 56, COUNTER),
+	TI(0x1002480, 0, 56, COUNTER),
+	TI(0x1002488, 0, 56, COUNTER),
+	TI(0x1002490, 0, 56, COUNTER),
+	TI(0x1002498, 0, 56, COUNTER),
+	TI(0x10024a0, 0, 56, COUNTER),
+	TI(0x10024a8, 0, 56, COUNTER),
+	TI(0x10024b0, 0, 56, COUNTER),
+	TI(0x10024b8, 0, 56, COUNTER),
+	TI(0x10022c0, 0, 56, COUNTER),
+	TI(0x10022c8, 0, 56, COUNTER),
+	TI(0x10022d0, 0, 56, COUNTER),
+	TI(0x10022d8, 0, 56, COUNTER),
+	TI(0x10022e0, 0, 56, COUNTER),
+	TI(0x10022e8, 0, 56, COUNTER),
+	TI(0x10022f0, 0, 56, COUNTER),
+	TI(0x10022f8, 0, 56, COUNTER),
+	TI(0x10023d0, 0, 56, COUNTER),
+	TI(0x10023c8, 0, 56, COUNTER),
+	TI(0x1002300, 0, 56, COUNTER),
+	TI(0x1002308, 0, 56, COUNTER),
+	TI(0x1002310, 0, 56, COUNTER),
+	TI(0x1002318, 0, 56, COUNTER),
+	TI(0x1002320, 0, 56, COUNTER),
+	TI(0x1002328, 0, 56, COUNTER),
+	TI(0x1002330, 0, 56, COUNTER),
+	TI(0x1002338, 0, 56, COUNTER),
+	TI(0x1002510, 0, 56, COUNTER),
+	TU,
+	TU,
+	TU,
+	TU,
+	TU,
+	TU,
+	TU,
+	TU,
+	TU,
+	TU,
+	TU,
+	TU,
+	TU,
+	TU,
+	TU,
+	TI(0x1002528, 0, 56, COUNTER),
+	TI(0x1002530, 0, 56, COUNTER),
+	TI(0x1002538, 0, 56, COUNTER),
+	TI(0x1002540, 0, 56, COUNTER),
+	TI(0x1002548, 0, 56, COUNTER),
+	TI(0x1002550, 0, 56, COUNTER),
+	TI(0x1002558, 0, 56, COUNTER),
+	TI(0x1002560, 0, 56, COUNTER),
+	TU,
+	TU,
+	TU,
+	TU,
+	TU,
+	TU,
+	TU,
+	TU,
+	TI(0x1002520, 0, 56, COUNTER),
+	TI(0x1002500, 0, 56, COUNTER),
+	TI(0x1002508, 0, 56, COUNTER),
+	TI(0x1002518, 0, 56, COUNTER),
+	TI(0x1002080, 0, 56, COUNTER),
+	TI(0x1002088, 0, 56, COUNTER),
+	TI(0x1002090, 0, 56, COUNTER),
+	TI(0x1002098, 0, 56, COUNTER),
+	TI(0x10020a0, 0, 56, COUNTER),
+	TI(0x10020a8, 0, 56, COUNTER),
+	TI(0x10020b0, 0, 56, COUNTER),
+	TI(0x10020b8, 0, 56, COUNTER),
+	TI(0x1002440, 0, 56, COUNTER),
+	TI(0x1002448, 0, 56, COUNTER),
+	TI(0x1002450, 0, 56, COUNTER),
+	TI(0x1002458, 0, 56, COUNTER),
+	TI(0x1002460, 0, 56, COUNTER),
+	TI(0x1002468, 0, 56, COUNTER),
+	TI(0x1002470, 0, 56, COUNTER),
+	TI(0x1002478, 0, 56, COUNTER),
+	TI(0x1002400, 0, 56, COUNTER),
+	TI(0x1002408, 0, 56, COUNTER),
+	TI(0x1002410, 0, 56, COUNTER),
+	TI(0x1002418, 0, 56, COUNTER),
+	TI(0x1002420, 0, 56, COUNTER),
+	TI(0x1002428, 0, 56, COUNTER),
+	TI(0x1002430, 0, 56, COUNTER),
+	TI(0x1002438, 0, 56, COUNTER),
+	TI(0x10021a8, 0, 56, COUNTER),
+	TI(0x10021b0, 0, 56, COUNTER),
+	TI(0x1002200, 0, 56, COUNTER),
+	TI(0x1002208, 0, 56, COUNTER),
+	TI(0x1002210, 0, 56, COUNTER),
+	TI(0x1002218, 0, 56, COUNTER),
+	TI(0x1002220, 0, 56, COUNTER),
+	TI(0x1002228, 0, 56, COUNTER),
+	TI(0x1002230, 0, 56, COUNTER),
+	TI(0x1002238, 0, 56, COUNTER),
+	TI(0x1002240, 0, 56, COUNTER),
+	TI(0x1002248, 0, 56, COUNTER),
+	TI(0x1002250, 0, 56, COUNTER),
+	TI(0x1002258, 0, 56, COUNTER),
+	TI(0x1002260, 0, 56, COUNTER),
+	TI(0x1002268, 0, 56, COUNTER),
+	TI(0x10021d0, 0, 56, COUNTER),
+	TI(0x10021b8, 0, 56, COUNTER),
+	TI(0x10021d8, 0, 56, COUNTER),
+	TI(0x1002198, 0, 56, COUNTER),
+	TI(0x10021e8, 0, 56, COUNTER),
+	TI(0x10021c8, 0, 56, COUNTER),
+	TI(0x10021c0, 0, 56, COUNTER),
+	TI(0x10021a0, 0, 56, COUNTER),
+	TI(0x10021e0, 0, 56, COUNTER),
+	TI(0x10021f0, 0, 56, COUNTER),
+	TI(0x10021f8, 0, 56, COUNTER),
+	TI(0x1002340, 0, 56, COUNTER),
+	TI(0x1002348, 0, 56, COUNTER),
+	TI(0x1002350, 0, 56, COUNTER),
+	TI(0x1002358, 0, 56, COUNTER),
+	TI(0x1002360, 0, 56, COUNTER),
+	TI(0x1002368, 0, 56, COUNTER),
+	TI(0x1002370, 0, 56, COUNTER),
+	TI(0x1002378, 0, 56, COUNTER),
+	TI(0x10023c0, 0, 56, COUNTER),
+	TI(0x1002020, 0, 56, COUNTER),
+	TI(0x1002040, 0, 56, COUNTER),
+	TI(0x1002048, 0, 56, COUNTER),
+	TI(0x1002050, 0, 56, COUNTER),
+	TI(0x1002058, 0, 56, COUNTER),
+	TI(0x1002060, 0, 56, COUNTER),
+	TI(0x1002068, 0, 56, COUNTER),
+	TI(0x1002070, 0, 56, COUNTER),
+	TI(0x1002078, 0, 56, COUNTER),
+	TI(0x1001048, 0, 56, COUNTER),
+	TI(0x1001060, 0, 56, COUNTER),
+	TI(0x1001050, 0, 56, COUNTER),
+	TI(0x1001058, 0, 56, COUNTER),
+	TI(0x1001068, 0, 56, COUNTER),
+	TI(0x1001040, 0, 56, COUNTER),
+	TI(0x1001018, 0, 56, COUNTER),
+	TI(0x1001030, 0, 56, COUNTER),
+	TI(0x1001020, 0, 56, COUNTER),
+	TI(0x1001028, 0, 56, COUNTER),
+	TI(0x1001038, 0, 56, COUNTER),
+	TI(0x1001010, 0, 56, COUNTER),
+	TI(0x1002138, 0, 56, COUNTER),
+	TI(0x1002140, 0, 56, COUNTER),
+	TI(0x1002148, 0, 56, COUNTER),
+	TI(0x1002150, 0, 56, COUNTER),
+	TI(0x1002158, 0, 56, COUNTER),
+	TI(0x1002160, 0, 56, COUNTER),
+	TI(0x1002168, 0, 56, COUNTER),
+	TI(0x1002170, 0, 56, COUNTER),
+	TI(0x1002178, 0, 56, COUNTER),
+	TI(0x1002180, 0, 56, COUNTER),
+	TI(0x1002188, 0, 56, COUNTER),
+	TI(0x1002190, 0, 56, COUNTER),
+	TI(0x1002120, 0, 56, COUNTER),
+	TI(0x1002100, 0, 56, COUNTER),
+	TI(0x1002128, 0, 56, COUNTER),
+	TI(0x1002108, 0, 56, COUNTER),
+	TI(0x1002130, 0, 56, COUNTER),
+	TI(0x10023e8, 0, 56, COUNTER),
+	TI(0x10023f8, 0, 56, COUNTER),
+	TI(0x1002380, 0, 56, COUNTER),
+	TI(0x1002388, 0, 56, COUNTER),
+	TI(0x1002390, 0, 56, COUNTER),
+	TI(0x1002398, 0, 56, COUNTER),
+	TI(0x10023a0, 0, 56, COUNTER),
+	TI(0x10023a8, 0, 56, COUNTER),
+	TI(0x10023b0, 0, 56, COUNTER),
+	TI(0x10023b8, 0, 56, COUNTER),
+	TI(0x1002110, 0, 56, COUNTER),
+	TI(0x1002118, 0, 56, COUNTER),
+	TI(0x1002010, 0, 56, COUNTER),
+	TI(0x10023e0, 0, 56, COUNTER),
+	TI(0x10023f0, 0, 56, COUNTER),
+	TI(0x1002008, 0, 56, COUNTER),
+	TI(0x9870900, 0, 56, COUNTER),
+	TI(0x98708f0, 0, 56, COUNTER),
+	TI(0x9870958, 0, 56, COUNTER),
+	TI(0x98708c8, 0, 56, COUNTER),
+	TI(0x98708d0, 0, 56, COUNTER),
+	TI(0x98708d8, 0, 56, COUNTER),
+	TI(0x98708a0, 0, 56, COUNTER),
+	TI(0x98708a8, 0, 56, COUNTER),
+	TI(0x98708b0, 0, 56, COUNTER),
+	TI(0x98708e0, 0, 56, COUNTER),
+	TI(0x9870850, 0, 56, COUNTER),
+	TI(0x9870858, 0, 56, COUNTER),
+	TI(0x9870870, 0, 56, COUNTER),
+	TI(0x9870878, 0, 56, COUNTER),
+	TI(0x9870840, 0, 56, COUNTER),
+	TI(0x9870848, 0, 56, COUNTER),
+	TI(0x9870880, 0, 56, COUNTER),
+	TI(0x9870888, 0, 56, COUNTER),
+	TI(0x9870860, 0, 56, COUNTER),
+	TI(0x9870868, 0, 56, COUNTER),
+	TI(0x98708b8, 0, 56, COUNTER),
+	TI(0x98708c0, 0, 56, COUNTER),
+	TI(0x98708e8, 0, 56, COUNTER),
+	TI(0x9870898, 0, 56, COUNTER),
+	TI(0x9870890, 0, 56, COUNTER),
+	TI(0x9870920, 0, 56, COUNTER),
+	TI(0x9870928, 0, 56, COUNTER),
+	TI(0x9870908, 0, 56, COUNTER),
+	TI(0x9870918, 0, 56, COUNTER),
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+	TI(0x9870910, 0, 56, COUNTER),
+	TI(0x98708f8, 0, 56, COUNTER),
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+	TI(0x9870a00, 0, 56, COUNTER),
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+	TI(0x98709c0, 0, 56, COUNTER),
+	TI(0x98709c8, 0, 56, COUNTER),
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+	TI(0x9870cd0, 0, 56, COUNTER),
+	TI(0x9870d40, 0, 56, COUNTER),
+	TI(0x9870cc0, 0, 56, COUNTER),
+	TI(0x9870cc8, 0, 56, COUNTER),
+	TI(0x9870cd8, 0, 56, COUNTER),
+	TI(0x9870cf8, 0, 56, COUNTER),
+	TI(0x9870ce0, 0, 56, COUNTER),
+	TI(0x9870ce8, 0, 56, COUNTER),
+	TI(0x9870cf0, 0, 56, COUNTER),
+	TI(0xa010018, 0, 12, UGAUGE),
+	TI(0x1002a90, 0, 56, COUNTER),
+	TI(0x10026b0, 0, 56, COUNTER),
+	TI(0x10026a8, 0, 56, COUNTER),
+	TI(0x10026b8, 0, 56, COUNTER),
+	TI(0x10026c8, 0, 56, COUNTER),
+	TI(0x10026d8, 0, 56, COUNTER),
+	TI(0x10026d0, 0, 56, COUNTER),
+	TI(0x10026c0, 0, 56, COUNTER),
+	TI(0x1002970, 0, 56, COUNTER),
+	TI(0x1002978, 0, 56, COUNTER),
+	TI(0x1002980, 0, 56, COUNTER),
+	TI(0x1002988, 0, 56, COUNTER),
+	TI(0x1002a98, 0, 56, COUNTER),
+	TI(0x1002aa0, 0, 56, COUNTER),
+	TI(0x1002aa8, 0, 56, COUNTER),
+	TI(0x1002ab0, 0, 56, COUNTER),
+	TI(0x1002ab8, 0, 56, COUNTER),
+	TI(0x1002ac0, 0, 56, COUNTER),
+	TI(0x1002ac8, 0, 56, COUNTER),
+	TI(0x1002ad0, 0, 56, COUNTER),
+	TI(0x1002ad8, 0, 56, COUNTER),
+	TI(0x1002ae0, 0, 56, COUNTER),
+	TI(0x1002ae8, 0, 56, COUNTER),
+	TI(0x1002af0, 0, 56, COUNTER),
+	TI(0x1002af8, 0, 56, COUNTER),
+	TI(0x1002b00, 0, 56, COUNTER),
+	TI(0x1002b08, 0, 56, COUNTER),
+	TI(0x1002b10, 0, 56, COUNTER),
+	TI(0x1002b18, 0, 56, COUNTER),
+	TI(0x1002b20, 0, 56, COUNTER),
+	TI(0x1002b28, 0, 56, COUNTER),
+	TI(0x1002b30, 0, 56, COUNTER),
+	TI(0x1002b38, 0, 56, COUNTER),
+	TI(0x1002b40, 0, 56, COUNTER),
+	TI(0x1002b48, 0, 56, COUNTER),
+	TI(0x1002b50, 0, 56, COUNTER),
+	TI(0x1002b58, 0, 56, COUNTER),
+	TI(0x1002b60, 0, 56, COUNTER),
+	TI(0x1002b68, 0, 56, COUNTER),
+	TI(0x1002b70, 0, 56, COUNTER),
+	TI(0x1002b78, 0, 56, COUNTER),
+	TI(0x1002b80, 0, 56, COUNTER),
+	TI(0x1002b88, 0, 56, COUNTER),
+	TI(0x1002b90, 0, 56, COUNTER),
+	TI(0x1002b98, 0, 56, COUNTER),
+	TI(0x1002ba0, 0, 56, COUNTER),
+	TI(0x1002ba8, 0, 56, COUNTER),
+	TI(0x1002bb0, 0, 56, COUNTER),
+	TI(0x1002bb8, 0, 56, COUNTER),
+	TI(0x1002bc0, 0, 56, COUNTER),
+	TI(0x1002bc8, 0, 56, COUNTER),
+	TI(0x1002bd0, 0, 56, COUNTER),
+	TI(0x1002bd8, 0, 56, COUNTER),
+	TI(0x1002be0, 0, 56, COUNTER),
+	TI(0x1002be8, 0, 56, COUNTER),
+	TI(0x1002bf0, 0, 56, COUNTER),
+	TI(0x1002bf8, 0, 56, COUNTER),
+	TI(0x1002c00, 0, 56, COUNTER),
+	TI(0x1002c08, 0, 56, COUNTER),
+	TI(0x1002c10, 0, 56, COUNTER),
+	TI(0x1002c18, 0, 56, COUNTER),
+	TI(0x1002c20, 0, 56, COUNTER),
+	TI(0x1002c28, 0, 56, COUNTER),
+	TI(0x1002c30, 0, 56, COUNTER),
+	TI(0x1002c38, 0, 56, COUNTER),
+	TI(0x1002c40, 0, 56, COUNTER),
+	TI(0x1002c48, 0, 56, COUNTER),
+	TI(0x1002c50, 0, 56, COUNTER),
+	TI(0x1002c58, 0, 56, COUNTER),
+	TI(0x1002c60, 0, 56, COUNTER),
+	TI(0x1002c68, 0, 56, COUNTER),
+	TI(0x1002c70, 0, 56, COUNTER),
+	TI(0x1002c78, 0, 56, COUNTER),
+	TI(0x1002c80, 0, 56, COUNTER),
+	TI(0x1002c88, 0, 56, COUNTER),
+	TI(0x1002c90, 0, 56, COUNTER),
+	TI(0x1002c98, 0, 56, COUNTER),
+	TI(0x1002ca0, 0, 56, COUNTER),
+	TI(0x1002ca8, 0, 56, COUNTER),
+	TI(0x1002cb0, 0, 56, COUNTER),
+	TI(0x1002cb8, 0, 56, COUNTER),
+	TI(0x1002cc0, 0, 56, COUNTER),
+	TI(0x1002cc8, 0, 56, COUNTER),
+	TI(0x1002cd0, 0, 56, COUNTER),
+	TI(0x1002cd8, 0, 56, COUNTER),
+	TI(0x1002ce0, 0, 56, COUNTER),
+	TI(0x1002ce8, 0, 56, COUNTER),
+	TI(0x1002cf0, 0, 56, COUNTER),
+	TI(0x1002cf8, 0, 56, COUNTER),
+	TI(0x1002d00, 0, 56, COUNTER),
+	TI(0x1002d08, 0, 56, COUNTER),
+	TI(0x1002d10, 0, 56, COUNTER),
+	TI(0x1002d18, 0, 56, COUNTER),
+	TI(0x1002d20, 0, 56, COUNTER),
+	TI(0x1002d28, 0, 56, COUNTER),
+	TI(0x1002d30, 0, 56, COUNTER),
+	TI(0x1002d38, 0, 56, COUNTER),
+	TI(0x1002d40, 0, 56, COUNTER),
+	TI(0x1002d48, 0, 56, COUNTER),
+	TI(0x1002d50, 0, 56, COUNTER),
+	TI(0x1002d58, 0, 56, COUNTER),
+	TI(0x1002d60, 0, 56, COUNTER),
+	TI(0x1002d68, 0, 56, COUNTER),
+	TI(0x1002d70, 0, 56, COUNTER),
+	TI(0x1002d78, 0, 56, COUNTER),
+	TI(0x1002d80, 0, 56, COUNTER),
+	TI(0x1002d88, 0, 56, COUNTER),
+	TI(0x1002d90, 0, 56, COUNTER),
+	TI(0x1002698, 0, 56, COUNTER),
+	TI(0x10026a0, 0, 56, COUNTER),
+	TI(0x1002a88, 0, 56, COUNTER),
+	TI(0x1002df8, 0, 56, COUNTER),
+	TI(0x1002e00, 0, 56, COUNTER),
+	TI(0x1002e08, 0, 56, COUNTER),
+	TI(0x1002e10, 0, 56, COUNTER),
+	TI(0x1002dd0, 0, 56, COUNTER),
+	TI(0x1002de0, 0, 56, COUNTER),
+	TI(0x1002dd8, 0, 56, COUNTER),
+	TI(0x1002de8, 0, 56, COUNTER),
+	TI(0x1002dc0, 0, 56, COUNTER),
+	TI(0x1002dc8, 0, 56, COUNTER),
+	TI(0x1002db8, 0, 56, COUNTER),
+	TI(0x1002da0, 0, 56, COUNTER),
+	TI(0x1002db0, 0, 56, COUNTER),
+	TI(0x1002da8, 0, 56, COUNTER),
+	TI(0x1002d98, 0, 56, COUNTER),
+	TI(0x1002df0, 0, 56, COUNTER),
+	TI(0x1002e78, 0, 56, COUNTER),
+	TI(0x1002e80, 0, 56, COUNTER),
+	TI(0x1002e88, 0, 56, COUNTER),
+	TI(0x1002e90, 0, 56, COUNTER),
+	TI(0x1002e50, 0, 56, COUNTER),
+	TI(0x1002e60, 0, 56, COUNTER),
+	TI(0x1002e58, 0, 56, COUNTER),
+	TI(0x1002e68, 0, 56, COUNTER),
+	TI(0x1002e40, 0, 56, COUNTER),
+	TI(0x1002e48, 0, 56, COUNTER),
+	TI(0x1002e38, 0, 56, COUNTER),
+	TI(0x1002e20, 0, 56, COUNTER),
+	TI(0x1002e30, 0, 56, COUNTER),
+	TI(0x1002e28, 0, 56, COUNTER),
+	TI(0x1002e18, 0, 56, COUNTER),
+	TI(0x1002e70, 0, 56, COUNTER),
+	TI(0x10029e0, 0, 56, COUNTER),
+	TI(0x10029e8, 0, 56, COUNTER),
+	TI(0x10029f0, 0, 56, COUNTER),
+	TI(0x10029f8, 0, 56, COUNTER),
+	TI(0x1002a00, 0, 56, COUNTER),
+	TI(0x1002a08, 0, 56, COUNTER),
+	TI(0x1002a10, 0, 56, COUNTER),
+	TI(0x1002a18, 0, 56, COUNTER),
+	TI(0x1002a20, 0, 56, COUNTER),
+	TI(0x1002a28, 0, 56, COUNTER),
+	TI(0x1002a80, 0, 56, COUNTER),
+	TI(0x1002990, 0, 56, COUNTER),
+	TI(0x1002998, 0, 56, COUNTER),
+	TI(0x10029a0, 0, 56, COUNTER),
+	TI(0x10029a8, 0, 56, COUNTER),
+	TI(0x10029b0, 0, 56, COUNTER),
+	TI(0x10029b8, 0, 56, COUNTER),
+	TI(0x10029c0, 0, 56, COUNTER),
+	TI(0x10029c8, 0, 56, COUNTER),
+	TI(0x10029d0, 0, 56, COUNTER),
+	TI(0x10029d8, 0, 56, COUNTER),
+	TI(0x1002a30, 0, 56, COUNTER),
+	TI(0x1002a38, 0, 56, COUNTER),
+	TI(0x1002a40, 0, 56, COUNTER),
+	TI(0x1002a48, 0, 56, COUNTER),
+	TI(0x1002a50, 0, 56, COUNTER),
+	TI(0x1002a58, 0, 56, COUNTER),
+	TI(0x1002a60, 0, 56, COUNTER),
+	TI(0x1002a68, 0, 56, COUNTER),
+	TI(0x1002a70, 0, 56, COUNTER),
+	TI(0x1002a78, 0, 56, COUNTER),
+	TU,
+	TU,
+	TI(0x10028c8, 0, 56, COUNTER),
+	TI(0x10028d0, 0, 56, COUNTER),
+	TI(0x10028d8, 0, 56, COUNTER),
+	TI(0x10028e0, 0, 56, COUNTER),
+	TI(0x10028e8, 0, 56, COUNTER),
+	TI(0x10028f0, 0, 56, COUNTER),
+	TI(0x10028f8, 0, 56, COUNTER),
+	TI(0x1002900, 0, 56, COUNTER),
+	TI(0x1002928, 0, 56, COUNTER),
+	TI(0x1002930, 0, 56, COUNTER),
+	TI(0x1002938, 0, 56, COUNTER),
+	TI(0x1002940, 0, 56, COUNTER),
+	TI(0x1002908, 0, 56, COUNTER),
+	TI(0x1002910, 0, 56, COUNTER),
+	TI(0x1002918, 0, 56, COUNTER),
+	TI(0x1002920, 0, 56, COUNTER),
+	TI(0x1002948, 0, 56, COUNTER),
+	TI(0x10028b8, 0, 56, COUNTER),
+	TI(0x1002868, 0, 56, COUNTER),
+	TI(0x1002870, 0, 56, COUNTER),
+	TI(0x1002878, 0, 56, COUNTER),
+	TI(0x1002880, 0, 56, COUNTER),
+	TI(0x1002888, 0, 56, COUNTER),
+	TI(0x1002890, 0, 56, COUNTER),
+	TI(0x1002898, 0, 56, COUNTER),
+	TI(0x10028a0, 0, 56, COUNTER),
+	TI(0x10028a8, 0, 56, COUNTER),
+	TI(0x10028b0, 0, 56, COUNTER),
+	TI(0x1002950, 0, 56, COUNTER),
+	TI(0x10028c0, 0, 56, COUNTER),
+	TI(0x1002738, 0, 56, COUNTER),
+	TI(0x1002740, 0, 56, COUNTER),
+	TI(0x1002748, 0, 56, COUNTER),
+	TI(0x1002750, 0, 56, COUNTER),
+	TI(0x1002758, 0, 56, COUNTER),
+	TI(0x1002760, 0, 56, COUNTER),
+	TI(0x1002768, 0, 56, COUNTER),
+	TI(0x1002770, 0, 56, COUNTER),
+	TI(0x1002778, 0, 56, COUNTER),
+	TI(0x1002780, 0, 56, COUNTER),
+	TI(0x1002840, 0, 56, COUNTER),
+	TI(0x10026e8, 0, 56, COUNTER),
+	TI(0x10026f0, 0, 56, COUNTER),
+	TI(0x10026f8, 0, 56, COUNTER),
+	TI(0x1002700, 0, 56, COUNTER),
+	TI(0x1002708, 0, 56, COUNTER),
+	TI(0x1002710, 0, 56, COUNTER),
+	TI(0x1002718, 0, 56, COUNTER),
+	TI(0x1002720, 0, 56, COUNTER),
+	TI(0x1002728, 0, 56, COUNTER),
+	TI(0x1002730, 0, 56, COUNTER),
+	TI(0x1002838, 0, 56, COUNTER),
+	TI(0x10027d8, 0, 56, COUNTER),
+	TI(0x10027e0, 0, 56, COUNTER),
+	TI(0x10027e8, 0, 56, COUNTER),
+	TI(0x10027f0, 0, 56, COUNTER),
+	TI(0x10027f8, 0, 56, COUNTER),
+	TI(0x1002800, 0, 56, COUNTER),
+	TI(0x1002808, 0, 56, COUNTER),
+	TI(0x1002810, 0, 56, COUNTER),
+	TI(0x1002818, 0, 56, COUNTER),
+	TI(0x1002820, 0, 56, COUNTER),
+	TI(0x1002788, 0, 56, COUNTER),
+	TI(0x1002790, 0, 56, COUNTER),
+	TI(0x1002798, 0, 56, COUNTER),
+	TI(0x10027a0, 0, 56, COUNTER),
+	TI(0x10027a8, 0, 56, COUNTER),
+	TI(0x10027b0, 0, 56, COUNTER),
+	TI(0x10027b8, 0, 56, COUNTER),
+	TI(0x10027c0, 0, 56, COUNTER),
+	TI(0x10027c8, 0, 56, COUNTER),
+	TI(0x10027d0, 0, 56, COUNTER),
+	TI(0x1002830, 0, 56, COUNTER),
+	TI(0x1002828, 0, 56, COUNTER),
+	TI(0x1002848, 0, 56, COUNTER),
+	TI(0x1002850, 0, 56, COUNTER),
+	TI(0x1002858, 0, 56, COUNTER),
+	TI(0x1002860, 0, 56, COUNTER),
+	TI(0xa803400, 32, 11, UGAUGE),
+	TI(0xa803408, 32, 11, UGAUGE),
+	TI(0xa803410, 32, 11, UGAUGE),
+	TI(0xa803418, 32, 11, UGAUGE),
+	TI(0xa803420, 32, 11, UGAUGE),
+	TI(0xa803428, 32, 11, UGAUGE),
+	TI(0xa803430, 32, 11, UGAUGE),
+	TI(0xa803438, 32, 11, UGAUGE),
+	TI(0xa803440, 32, 11, UGAUGE),
+	TI(0xa803448, 32, 11, UGAUGE),
+	TI(0xa803400, 0, 11, UGAUGE),
+	TI(0xa803408, 0, 11, UGAUGE),
+	TI(0xa803410, 0, 11, UGAUGE),
+	TI(0xa803418, 0, 11, UGAUGE),
+	TI(0xa803420, 0, 11, UGAUGE),
+	TI(0xa803428, 0, 11, UGAUGE),
+	TI(0xa803430, 0, 11, UGAUGE),
+	TI(0xa803438, 0, 11, UGAUGE),
+	TI(0xa803440, 0, 11, UGAUGE),
+	TI(0xa803448, 0, 11, UGAUGE),
+	TI(0xa803400, 16, 11, UGAUGE),
+	TI(0xa803408, 16, 11, UGAUGE),
+	TI(0xa803410, 16, 11, UGAUGE),
+	TI(0xa803418, 16, 11, UGAUGE),
+	TI(0xa803420, 16, 11, UGAUGE),
+	TI(0xa803428, 16, 11, UGAUGE),
+	TI(0xa803430, 16, 11, UGAUGE),
+	TI(0xa803438, 16, 11, UGAUGE),
+	TI(0xa803440, 16, 11, UGAUGE),
+	TI(0xa803448, 16, 11, UGAUGE),
+	TI(0xa803000, 32, 11, UGAUGE),
+	TI(0xa803008, 32, 11, UGAUGE),
+	TI(0xa803010, 32, 11, UGAUGE),
+	TI(0xa803018, 32, 11, UGAUGE),
+	TI(0xa803020, 32, 11, UGAUGE),
+	TI(0xa803028, 32, 11, UGAUGE),
+	TI(0xa803030, 32, 11, UGAUGE),
+	TI(0xa803038, 32, 11, UGAUGE),
+	TI(0xa803040, 32, 11, UGAUGE),
+	TI(0xa803048, 32, 11, UGAUGE),
+	TI(0xa803050, 32, 11, UGAUGE),
+	TI(0xa803058, 32, 11, UGAUGE),
+	TI(0xa803060, 32, 11, UGAUGE),
+	TI(0xa803068, 32, 11, UGAUGE),
+	TI(0xa803070, 32, 11, UGAUGE),
+	TI(0xa803078, 32, 11, UGAUGE),
+	TI(0xa803080, 32, 11, UGAUGE),
+	TI(0xa803088, 32, 11, UGAUGE),
+	TI(0xa803090, 32, 11, UGAUGE),
+	TI(0xa803098, 32, 11, UGAUGE),
+	TI(0xa8030a0, 32, 11, UGAUGE),
+	TI(0xa8030a8, 32, 11, UGAUGE),
+	TI(0xa8030b0, 32, 11, UGAUGE),
+	TI(0xa8030b8, 32, 11, UGAUGE),
+	TI(0xa8030c0, 32, 11, UGAUGE),
+	TI(0xa8030c8, 32, 11, UGAUGE),
+	TI(0xa8030d0, 32, 11, UGAUGE),
+	TI(0xa8030d8, 32, 11, UGAUGE),
+	TI(0xa8030e0, 32, 11, UGAUGE),
+	TI(0xa8030e8, 32, 11, UGAUGE),
+	TI(0xa8030f0, 32, 11, UGAUGE),
+	TI(0xa8030f8, 32, 11, UGAUGE),
+	TI(0xa803100, 32, 11, UGAUGE),
+	TI(0xa803108, 32, 11, UGAUGE),
+	TI(0xa803110, 32, 11, UGAUGE),
+	TI(0xa803118, 32, 11, UGAUGE),
+	TI(0xa803120, 32, 11, UGAUGE),
+	TI(0xa803128, 32, 11, UGAUGE),
+	TI(0xa803130, 32, 11, UGAUGE),
+	TI(0xa803138, 32, 11, UGAUGE),
+	TI(0xa803140, 32, 11, UGAUGE),
+	TI(0xa803148, 32, 11, UGAUGE),
+	TI(0xa803150, 32, 11, UGAUGE),
+	TI(0xa803158, 32, 11, UGAUGE),
+	TI(0xa803160, 32, 11, UGAUGE),
+	TI(0xa803168, 32, 11, UGAUGE),
+	TI(0xa803170, 32, 11, UGAUGE),
+	TI(0xa803178, 32, 11, UGAUGE),
+	TI(0xa803180, 32, 11, UGAUGE),
+	TI(0xa803188, 32, 11, UGAUGE),
+	TI(0xa803190, 32, 11, UGAUGE),
+	TI(0xa803198, 32, 11, UGAUGE),
+	TI(0xa8031a0, 32, 11, UGAUGE),
+	TI(0xa8031a8, 32, 11, UGAUGE),
+	TI(0xa8031b0, 32, 11, UGAUGE),
+	TI(0xa8031b8, 32, 11, UGAUGE),
+	TI(0xa8031c0, 32, 11, UGAUGE),
+	TI(0xa8031c8, 32, 11, UGAUGE),
+	TI(0xa8031d0, 32, 11, UGAUGE),
+	TI(0xa8031d8, 32, 11, UGAUGE),
+	TI(0xa8031e0, 32, 11, UGAUGE),
+	TI(0xa8031e8, 32, 11, UGAUGE),
+	TI(0xa8031f0, 32, 11, UGAUGE),
+	TI(0xa8031f8, 32, 11, UGAUGE),
+	TI(0xa803200, 32, 11, UGAUGE),
+	TI(0xa803208, 32, 11, UGAUGE),
+	TI(0xa803210, 32, 11, UGAUGE),
+	TI(0xa803218, 32, 11, UGAUGE),
+	TI(0xa803220, 32, 11, UGAUGE),
+	TI(0xa803228, 32, 11, UGAUGE),
+	TI(0xa803230, 32, 11, UGAUGE),
+	TI(0xa803238, 32, 11, UGAUGE),
+	TI(0xa803240, 32, 11, UGAUGE),
+	TI(0xa803248, 32, 11, UGAUGE),
+	TI(0xa803250, 32, 11, UGAUGE),
+	TI(0xa803258, 32, 11, UGAUGE),
+	TI(0xa803260, 32, 11, UGAUGE),
+	TI(0xa803268, 32, 11, UGAUGE),
+	TI(0xa803270, 32, 11, UGAUGE),
+	TI(0xa803278, 32, 11, UGAUGE),
+	TI(0xa803280, 32, 11, UGAUGE),
+	TI(0xa803288, 32, 11, UGAUGE),
+	TI(0xa803290, 32, 11, UGAUGE),
+	TI(0xa803298, 32, 11, UGAUGE),
+	TI(0xa8032a0, 32, 11, UGAUGE),
+	TI(0xa8032a8, 32, 11, UGAUGE),
+	TI(0xa8032b0, 32, 11, UGAUGE),
+	TI(0xa8032b8, 32, 11, UGAUGE),
+	TI(0xa8032c0, 32, 11, UGAUGE),
+	TI(0xa8032c8, 32, 11, UGAUGE),
+	TI(0xa8032d0, 32, 11, UGAUGE),
+	TI(0xa8032d8, 32, 11, UGAUGE),
+	TI(0xa8032e0, 32, 11, UGAUGE),
+	TI(0xa8032e8, 32, 11, UGAUGE),
+	TI(0xa8032f0, 32, 11, UGAUGE),
+	TI(0xa8032f8, 32, 11, UGAUGE),
+	TI(0xa803000, 0, 11, UGAUGE),
+	TI(0xa803008, 0, 11, UGAUGE),
+	TI(0xa803010, 0, 11, UGAUGE),
+	TI(0xa803018, 0, 11, UGAUGE),
+	TI(0xa803020, 0, 11, UGAUGE),
+	TI(0xa803028, 0, 11, UGAUGE),
+	TI(0xa803030, 0, 11, UGAUGE),
+	TI(0xa803038, 0, 11, UGAUGE),
+	TI(0xa803040, 0, 11, UGAUGE),
+	TI(0xa803048, 0, 11, UGAUGE),
+	TI(0xa803050, 0, 11, UGAUGE),
+	TI(0xa803058, 0, 11, UGAUGE),
+	TI(0xa803060, 0, 11, UGAUGE),
+	TI(0xa803068, 0, 11, UGAUGE),
+	TI(0xa803070, 0, 11, UGAUGE),
+	TI(0xa803078, 0, 11, UGAUGE),
+	TI(0xa803080, 0, 11, UGAUGE),
+	TI(0xa803088, 0, 11, UGAUGE),
+	TI(0xa803090, 0, 11, UGAUGE),
+	TI(0xa803098, 0, 11, UGAUGE),
+	TI(0xa8030a0, 0, 11, UGAUGE),
+	TI(0xa8030a8, 0, 11, UGAUGE),
+	TI(0xa8030b0, 0, 11, UGAUGE),
+	TI(0xa8030b8, 0, 11, UGAUGE),
+	TI(0xa8030c0, 0, 11, UGAUGE),
+	TI(0xa8030c8, 0, 11, UGAUGE),
+	TI(0xa8030d0, 0, 11, UGAUGE),
+	TI(0xa8030d8, 0, 11, UGAUGE),
+	TI(0xa8030e0, 0, 11, UGAUGE),
+	TI(0xa8030e8, 0, 11, UGAUGE),
+	TI(0xa8030f0, 0, 11, UGAUGE),
+	TI(0xa8030f8, 0, 11, UGAUGE),
+	TI(0xa803100, 0, 11, UGAUGE),
+	TI(0xa803108, 0, 11, UGAUGE),
+	TI(0xa803110, 0, 11, UGAUGE),
+	TI(0xa803118, 0, 11, UGAUGE),
+	TI(0xa803120, 0, 11, UGAUGE),
+	TI(0xa803128, 0, 11, UGAUGE),
+	TI(0xa803130, 0, 11, UGAUGE),
+	TI(0xa803138, 0, 11, UGAUGE),
+	TI(0xa803140, 0, 11, UGAUGE),
+	TI(0xa803148, 0, 11, UGAUGE),
+	TI(0xa803150, 0, 11, UGAUGE),
+	TI(0xa803158, 0, 11, UGAUGE),
+	TI(0xa803160, 0, 11, UGAUGE),
+	TI(0xa803168, 0, 11, UGAUGE),
+	TI(0xa803170, 0, 11, UGAUGE),
+	TI(0xa803178, 0, 11, UGAUGE),
+	TI(0xa803180, 0, 11, UGAUGE),
+	TI(0xa803188, 0, 11, UGAUGE),
+	TI(0xa803190, 0, 11, UGAUGE),
+	TI(0xa803198, 0, 11, UGAUGE),
+	TI(0xa8031a0, 0, 11, UGAUGE),
+	TI(0xa8031a8, 0, 11, UGAUGE),
+	TI(0xa8031b0, 0, 11, UGAUGE),
+	TI(0xa8031b8, 0, 11, UGAUGE),
+	TI(0xa8031c0, 0, 11, UGAUGE),
+	TI(0xa8031c8, 0, 11, UGAUGE),
+	TI(0xa8031d0, 0, 11, UGAUGE),
+	TI(0xa8031d8, 0, 11, UGAUGE),
+	TI(0xa8031e0, 0, 11, UGAUGE),
+	TI(0xa8031e8, 0, 11, UGAUGE),
+	TI(0xa8031f0, 0, 11, UGAUGE),
+	TI(0xa8031f8, 0, 11, UGAUGE),
+	TI(0xa803200, 0, 11, UGAUGE),
+	TI(0xa803208, 0, 11, UGAUGE),
+	TI(0xa803210, 0, 11, UGAUGE),
+	TI(0xa803218, 0, 11, UGAUGE),
+	TI(0xa803220, 0, 11, UGAUGE),
+	TI(0xa803228, 0, 11, UGAUGE),
+	TI(0xa803230, 0, 11, UGAUGE),
+	TI(0xa803238, 0, 11, UGAUGE),
+	TI(0xa803240, 0, 11, UGAUGE),
+	TI(0xa803248, 0, 11, UGAUGE),
+	TI(0xa803250, 0, 11, UGAUGE),
+	TI(0xa803258, 0, 11, UGAUGE),
+	TI(0xa803260, 0, 11, UGAUGE),
+	TI(0xa803268, 0, 11, UGAUGE),
+	TI(0xa803270, 0, 11, UGAUGE),
+	TI(0xa803278, 0, 11, UGAUGE),
+	TI(0xa803280, 0, 11, UGAUGE),
+	TI(0xa803288, 0, 11, UGAUGE),
+	TI(0xa803290, 0, 11, UGAUGE),
+	TI(0xa803298, 0, 11, UGAUGE),
+	TI(0xa8032a0, 0, 11, UGAUGE),
+	TI(0xa8032a8, 0, 11, UGAUGE),
+	TI(0xa8032b0, 0, 11, UGAUGE),
+	TI(0xa8032b8, 0, 11, UGAUGE),
+	TI(0xa8032c0, 0, 11, UGAUGE),
+	TI(0xa8032c8, 0, 11, UGAUGE),
+	TI(0xa8032d0, 0, 11, UGAUGE),
+	TI(0xa8032d8, 0, 11, UGAUGE),
+	TI(0xa8032e0, 0, 11, UGAUGE),
+	TI(0xa8032e8, 0, 11, UGAUGE),
+	TI(0xa8032f0, 0, 11, UGAUGE),
+	TI(0xa8032f8, 0, 11, UGAUGE),
+	TI(0x9870c98, 0, 56, COUNTER),
+	TI(0x9870c90, 0, 56, COUNTER),
+	TI(0x9870c68, 0, 56, COUNTER),
+	TI(0x9870c60, 0, 56, COUNTER),
+	TI(0x9870c70, 0, 56, COUNTER),
+	TI(0x9870c80, 0, 56, COUNTER),
+	TI(0x9870c78, 0, 56, COUNTER),
+	TI(0x9870c88, 0, 56, COUNTER),
+	TI(0x9870c48, 0, 56, COUNTER),
+	TI(0x9870c58, 0, 56, COUNTER),
+	TI(0x9870c40, 0, 56, COUNTER),
+	TI(0x9870c50, 0, 56, COUNTER),
+	TI(0x9001008, 8, 6, UGAUGE),
+	TI(0x9001008, 0, 6, UGAUGE),
+	TI(0x9870b48, 0, 56, COUNTER),
+	TI(0x9870be8, 0, 56, COUNTER),
+	TI(0x9870ba8, 0, 56, COUNTER),
+	TI(0x9870b38, 0, 56, COUNTER),
+	TI(0x9870be0, 0, 56, COUNTER),
+	TI(0x9870ba0, 0, 56, COUNTER),
+	TI(0x9870b30, 0, 56, COUNTER),
+	TI(0x9870b40, 0, 56, COUNTER),
+	TI(0x9870ad8, 0, 56, COUNTER),
+	TI(0x9870bb8, 0, 56, COUNTER),
+	TI(0x9870b78, 0, 56, COUNTER),
+	TI(0x9870ac8, 0, 56, COUNTER),
+	TI(0x9870bb0, 0, 56, COUNTER),
+	TI(0x9870b70, 0, 56, COUNTER),
+	TI(0x9870ac0, 0, 56, COUNTER),
+	TI(0x9870ad0, 0, 56, COUNTER),
+	TI(0x9870af0, 0, 56, COUNTER),
+	TI(0x9870bc0, 0, 56, COUNTER),
+	TI(0x9870b80, 0, 56, COUNTER),
+	TI(0x9870ae0, 0, 56, COUNTER),
+	TI(0x9870ae8, 0, 56, COUNTER),
+	TI(0x9870b10, 0, 56, COUNTER),
+	TI(0x9870bd0, 0, 56, COUNTER),
+	TI(0x9870b90, 0, 56, COUNTER),
+	TI(0x9870b00, 0, 56, COUNTER),
+	TI(0x9870bc8, 0, 56, COUNTER),
+	TI(0x9870b88, 0, 56, COUNTER),
+	TI(0x9870af8, 0, 56, COUNTER),
+	TI(0x9870b08, 0, 56, COUNTER),
+	TI(0x9870b28, 0, 56, COUNTER),
+	TI(0x9870bd8, 0, 56, COUNTER),
+	TI(0x9870b98, 0, 56, COUNTER),
+	TI(0x9870b18, 0, 56, COUNTER),
+	TI(0x9870b20, 0, 56, COUNTER),
+	TI(0x9870b68, 0, 56, COUNTER),
+	TI(0x9870b58, 0, 56, COUNTER),
+	TI(0x9870b60, 0, 56, COUNTER),
+	TI(0x9870b50, 0, 56, COUNTER),
+	TI(0x100698, 0, 56, COUNTER),
+	TI(0x1006b0, 0, 56, COUNTER),
+	TI(0x1006a0, 0, 56, COUNTER),
+	TI(0x100688, 0, 56, COUNTER),
+	TI(0x100728, 0, 56, COUNTER),
+	TI(0x100690, 0, 56, COUNTER),
+	TI(0x100720, 0, 56, COUNTER),
+	TI(0x1007d8, 0, 56, COUNTER),
+	TI(0x100680, 0, 56, COUNTER),
+	TI(0x100660, 0, 56, COUNTER),
+	TI(0x100668, 0, 56, COUNTER),
+	TI(0x1006e8, 0, 56, COUNTER),
+	TI(0x1006e0, 0, 56, COUNTER),
+	TI(0x100628, 0, 56, COUNTER),
+	TI(0x100900, 0, 56, COUNTER),
+	TI(0x100908, 0, 56, COUNTER),
+	TI(0x100910, 0, 56, COUNTER),
+	TI(0x100918, 0, 56, COUNTER),
+	TI(0x100920, 0, 56, COUNTER),
+	TI(0x100928, 0, 56, COUNTER),
+	TI(0x100930, 0, 56, COUNTER),
+	TI(0x100938, 0, 56, COUNTER),
+	TI(0x100940, 0, 56, COUNTER),
+	TI(0x100948, 0, 56, COUNTER),
+	TI(0x100950, 0, 56, COUNTER),
+	TI(0x100958, 0, 56, COUNTER),
+	TI(0x100960, 0, 56, COUNTER),
+	TI(0x100968, 0, 56, COUNTER),
+	TI(0x100970, 0, 56, COUNTER),
+	TI(0x100978, 0, 56, COUNTER),
+	TI(0x100648, 0, 56, COUNTER),
+	TI(0x100650, 0, 56, COUNTER),
+	TI(0x100658, 0, 56, COUNTER),
+	TI(0x100600, 0, 56, COUNTER),
+	TI(0x100608, 0, 56, COUNTER),
+	TI(0x100670, 0, 56, COUNTER),
+	TI(0x1006d0, 0, 56, COUNTER),
+	TI(0x1006c0, 0, 56, COUNTER),
+	TI(0x1006b8, 0, 56, COUNTER),
+	TI(0x1006c8, 0, 56, COUNTER),
+	TI(0x100630, 0, 56, COUNTER),
+	TI(0x100798, 0, 56, COUNTER),
+	TI(0x1007a0, 0, 56, COUNTER),
+	TI(0x100788, 0, 56, COUNTER),
+	TI(0x100790, 0, 56, COUNTER),
+	TI(0x100778, 0, 56, COUNTER),
+	TI(0x100780, 0, 56, COUNTER),
+	TI(0x1007a8, 0, 56, COUNTER),
+	TI(0x1007b8, 0, 56, COUNTER),
+	TI(0x1007b0, 0, 56, COUNTER),
+	TI(0x1007c0, 0, 56, COUNTER),
+	TI(0xb00130, 32, 12, UGAUGE),
+	TI(0xb00130, 0, 12, UGAUGE),
+	TI(0xb00100, 32, 13, UGAUGE),
+	TI(0xb00100, 0, 13, UGAUGE),
+	TI(0xb00118, 32, 9, UGAUGE),
+	TI(0xb00118, 0, 9, UGAUGE),
+	TI(0xb00110, 32, 12, UGAUGE),
+	TI(0xb00110, 0, 12, UGAUGE),
+	TI(0xb00128, 32, 12, UGAUGE),
+	TI(0xb00128, 0, 12, UGAUGE),
+	TI(0xb00108, 32, 14, UGAUGE),
+	TI(0xb00108, 0, 14, UGAUGE),
+	TI(0xb00120, 32, 12, UGAUGE),
+	TI(0xb00120, 0, 12, UGAUGE),
+	TI(0x100638, 0, 56, COUNTER),
+	TI(0x100740, 0, 56, COUNTER),
+	TI(0x100738, 0, 56, COUNTER),
+	TI(0x100748, 0, 56, COUNTER),
+	TI(0x100620, 0, 56, COUNTER),
+	TI(0x100610, 0, 56, COUNTER),
+	TI(0x100800, 0, 56, COUNTER),
+	TI(0x100808, 0, 56, COUNTER),
+	TI(0x100810, 0, 56, COUNTER),
+	TI(0x100818, 0, 56, COUNTER),
+	TI(0x100820, 0, 56, COUNTER),
+	TI(0x100828, 0, 56, COUNTER),
+	TI(0x100830, 0, 56, COUNTER),
+	TI(0x100838, 0, 56, COUNTER),
+	TI(0x100840, 0, 56, COUNTER),
+	TI(0x100848, 0, 56, COUNTER),
+	TI(0x100850, 0, 56, COUNTER),
+	TI(0x100858, 0, 56, COUNTER),
+	TI(0x100860, 0, 56, COUNTER),
+	TI(0x100868, 0, 56, COUNTER),
+	TI(0x100870, 0, 56, COUNTER),
+	TI(0x100878, 0, 56, COUNTER),
+	TI(0x100880, 0, 56, COUNTER),
+	TI(0x100888, 0, 56, COUNTER),
+	TI(0x100890, 0, 56, COUNTER),
+	TI(0x100898, 0, 56, COUNTER),
+	TI(0x1008a0, 0, 56, COUNTER),
+	TI(0x1008a8, 0, 56, COUNTER),
+	TI(0x1008b0, 0, 56, COUNTER),
+	TI(0x1008b8, 0, 56, COUNTER),
+	TI(0x1008c0, 0, 56, COUNTER),
+	TI(0x1008c8, 0, 56, COUNTER),
+	TI(0x1008d0, 0, 56, COUNTER),
+	TI(0x1008d8, 0, 56, COUNTER),
+	TI(0x1008e0, 0, 56, COUNTER),
+	TI(0x1008e8, 0, 56, COUNTER),
+	TI(0x1008f0, 0, 56, COUNTER),
+	TI(0x1008f8, 0, 56, COUNTER),
+	TI(0x1006a8, 0, 56, COUNTER),
+	TI(0x1007e0, 0, 56, COUNTER),
+	TI(0x100618, 0, 56, COUNTER),
+	TI(0x1006d8, 0, 56, COUNTER),
+	TI(0x100640, 0, 56, COUNTER),
+	TI(0x100718, 0, 56, COUNTER),
+	TI(0x100708, 0, 56, COUNTER),
+	TI(0x100710, 0, 56, COUNTER),
+	TI(0x100768, 0, 56, COUNTER),
+	TI(0x100770, 0, 56, COUNTER),
+	TI(0x100758, 0, 56, COUNTER),
+	TI(0x100760, 0, 56, COUNTER),
+	TI(0x100750, 0, 56, COUNTER),
+	TI(0x1007c8, 0, 56, COUNTER),
+	TI(0x1006f8, 0, 56, COUNTER),
+	TI(0x1006f0, 0, 56, COUNTER),
+	TI(0x100700, 0, 56, COUNTER),
+	TI(0x1007d0, 0, 56, COUNTER),
+	TI(0x100678, 0, 56, COUNTER),
+	TI(0x1007e8, 0, 56, COUNTER),
+	TI(0x100730, 0, 56, COUNTER),
+	TI(0x100203b8, 0, 56, COUNTER),
+	TI(0x100203c0, 0, 56, COUNTER),
+	TI(0x100203d0, 0, 56, COUNTER),
+	TI(0x100203c8, 0, 56, COUNTER),
+	TI(0x100203e0, 0, 56, COUNTER),
+	TI(0x100203f0, 0, 56, COUNTER),
+	TI(0x100203f8, 0, 56, COUNTER),
+	TI(0x100203e8, 0, 56, COUNTER),
+	TI(0x100203d8, 0, 56, COUNTER),
+	TI(0x11005000, 4, 16, COUNTER),
+	TI(0x110061d8, 0, 56, COUNTER),
+	TI(0x110061d0, 0, 56, COUNTER),
+	TI(0x110061c0, 0, 56, COUNTER),
+	TI(0x110061c8, 0, 56, COUNTER),
+	TI(0x110061e0, 0, 56, COUNTER),
+	TI(0x110061e8, 0, 56, COUNTER),
+	TI(0x11006178, 0, 56, COUNTER),
+	TI(0x11006170, 0, 56, COUNTER),
+	TI(0x11006160, 0, 56, COUNTER),
+	TI(0x11006168, 0, 56, COUNTER),
+	TI(0x11006158, 0, 56, COUNTER),
+	TI(0x11006150, 0, 56, COUNTER),
+	TI(0x11006140, 0, 56, COUNTER),
+	TI(0x11006148, 0, 56, COUNTER),
+	TI(0x11006180, 0, 56, COUNTER),
+	TI(0x11006188, 0, 56, COUNTER),
+	TI(0x110061b0, 0, 56, COUNTER),
+	TI(0x110061b8, 0, 56, COUNTER),
+	TI(0x11006190, 0, 56, COUNTER),
+	TI(0x11006198, 0, 56, COUNTER),
+	TI(0x11006068, 0, 56, COUNTER),
+	TI(0x11006060, 0, 56, COUNTER),
+	TI(0x11006050, 0, 56, COUNTER),
+	TI(0x11006058, 0, 56, COUNTER),
+	TI(0x11006030, 0, 56, COUNTER),
+	TI(0x11006038, 0, 56, COUNTER),
+	TI(0x11006048, 0, 56, COUNTER),
+	TI(0x11006040, 0, 56, COUNTER),
+	TI(0x11006010, 0, 56, COUNTER),
+	TI(0x11006018, 0, 56, COUNTER),
+	TI(0x11006020, 0, 56, COUNTER),
+	TI(0x11006008, 0, 56, COUNTER),
+	TI(0x11006000, 0, 56, COUNTER),
+	TI(0x11006028, 0, 56, COUNTER),
+	TI(0x11006118, 0, 56, COUNTER),
+	TI(0x11006110, 0, 56, COUNTER),
+	TI(0x11006108, 0, 56, COUNTER),
+	TI(0x11006120, 0, 56, COUNTER),
+	TI(0x11006090, 0, 56, COUNTER),
+	TI(0x11006088, 0, 56, COUNTER),
+	TI(0x110060f0, 0, 56, COUNTER),
+	TI(0x110060e8, 0, 56, COUNTER),
+	TI(0x11006098, 0, 56, COUNTER),
+	TI(0x11006100, 0, 56, COUNTER),
+	TI(0x110060f8, 0, 56, COUNTER),
+	TI(0x110061a0, 0, 56, COUNTER),
+	TI(0x110061a8, 0, 56, COUNTER),
+	TI(0x11006080, 0, 56, COUNTER),
+	TI(0x110060d8, 0, 56, COUNTER),
+	TI(0x110060d0, 0, 56, COUNTER),
+	TI(0x110060c8, 0, 56, COUNTER),
+	TI(0x110060c0, 0, 56, COUNTER),
+	TI(0x110060e0, 0, 56, COUNTER),
+	TI(0x11006128, 0, 56, COUNTER),
+	TI(0x11006130, 0, 56, COUNTER),
+	TI(0x11006138, 0, 56, COUNTER),
+	TI(0x110060b0, 0, 56, COUNTER),
+	TI(0x110060b8, 0, 56, COUNTER),
+	TI(0x110060a0, 0, 56, COUNTER),
+	TI(0x110060a8, 0, 56, COUNTER),
+	TI(0x11006078, 0, 56, COUNTER),
+	TI(0x11006070, 0, 56, COUNTER),
+	TI(0x10020268, 0, 56, COUNTER),
+	TI(0x10020280, 0, 56, COUNTER),
+	TI(0x10020290, 0, 56, COUNTER),
+	TI(0x10020288, 0, 56, COUNTER),
+	TI(0x10020260, 0, 56, COUNTER),
+	TI(0x10020270, 0, 56, COUNTER),
+	TI(0x10020278, 0, 56, COUNTER),
+	TI(0x10020238, 0, 56, COUNTER),
+	TI(0x10020240, 0, 56, COUNTER),
+	TI(0x10020210, 0, 56, COUNTER),
+	TI(0x10020208, 0, 56, COUNTER),
+	TI(0x10020228, 0, 56, COUNTER),
+	TI(0x10020220, 0, 56, COUNTER),
+	TI(0x10020230, 0, 56, COUNTER),
+	TI(0x10020218, 0, 56, COUNTER),
+	TI(0x10020200, 0, 56, COUNTER),
+	TI(0x10020250, 0, 56, COUNTER),
+	TI(0x10020248, 0, 56, COUNTER),
+	TI(0x10020258, 0, 56, COUNTER),
+	TI(0x100202e0, 0, 56, COUNTER),
+	TI(0x100202e8, 0, 56, COUNTER),
+	TI(0x100202d8, 0, 56, COUNTER),
+	TI(0x100202d0, 0, 56, COUNTER),
+	TI(0x100202c0, 0, 56, COUNTER),
+	TI(0x100202c8, 0, 56, COUNTER),
+	TI(0x100202a8, 0, 56, COUNTER),
+	TI(0x100202b0, 0, 56, COUNTER),
+	TI(0x100202a0, 0, 56, COUNTER),
+	TI(0x100202b8, 0, 56, COUNTER),
+	TI(0x10020298, 0, 56, COUNTER),
+	TI(0x100202f0, 0, 56, COUNTER),
+	TI(0x100202f8, 0, 56, COUNTER),
+	TI(0x10020380, 0, 56, COUNTER),
+	TI(0x10020388, 0, 56, COUNTER),
+	TI(0x10020350, 0, 56, COUNTER),
+	TI(0x10020370, 0, 56, COUNTER),
+	TI(0x10020378, 0, 56, COUNTER),
+	TI(0x10020358, 0, 56, COUNTER),
+	TI(0x10020328, 0, 56, COUNTER),
+	TI(0x10020360, 0, 56, COUNTER),
+	TI(0x10020368, 0, 56, COUNTER),
+	TI(0x10020340, 0, 56, COUNTER),
+	TI(0x10020330, 0, 56, COUNTER),
+	TI(0x10020320, 0, 56, COUNTER),
+	TI(0x10020318, 0, 56, COUNTER),
+	TI(0x10020348, 0, 56, COUNTER),
+	TI(0x10020308, 0, 56, COUNTER),
+	TI(0x10020300, 0, 56, COUNTER),
+	TI(0x10020310, 0, 56, COUNTER),
+	TI(0x10020338, 0, 56, COUNTER),
+	TI(0x9870a78, 0, 56, COUNTER),
+	TI(0x9870a80, 0, 56, COUNTER),
+	TI(0x9870a48, 0, 56, COUNTER),
+	TI(0x9870a50, 0, 56, COUNTER),
+	TI(0x9870a58, 0, 56, COUNTER),
+	TI(0x9870a60, 0, 56, COUNTER),
+	TI(0x9870a68, 0, 56, COUNTER),
+	TI(0x9870a70, 0, 56, COUNTER),
+	TI(0x9870a40, 0, 56, COUNTER),
+	TI(0x100450, 0, 56, COUNTER),
+	TI(0x100420, 0, 56, COUNTER),
+	TI(0x100428, 0, 56, COUNTER),
+	TI(0x1004e0, 0, 56, COUNTER),
+	TI(0x1004e8, 0, 56, COUNTER),
+	TI(0x1004f0, 0, 56, COUNTER),
+	TI(0x1004f8, 0, 56, COUNTER),
+	TI(0x100500, 0, 56, COUNTER),
+	TI(0x100508, 0, 56, COUNTER),
+	TI(0x100510, 0, 56, COUNTER),
+	TI(0x100518, 0, 56, COUNTER),
+	TI(0x100520, 0, 56, COUNTER),
+	TI(0x100528, 0, 56, COUNTER),
+	TI(0x100530, 0, 56, COUNTER),
+	TI(0x100538, 0, 56, COUNTER),
+	TI(0x100540, 0, 56, COUNTER),
+	TI(0x100548, 0, 56, COUNTER),
+	TI(0x100550, 0, 56, COUNTER),
+	TI(0x100558, 0, 56, COUNTER),
+	TI(0x100408, 0, 56, COUNTER),
+	TI(0x100448, 0, 56, COUNTER),
+	TI(0x100498, 0, 56, COUNTER),
+	TI(0x100490, 0, 56, COUNTER),
+	TI(0x1004c0, 0, 56, COUNTER),
+	TI(0x1004c8, 0, 56, COUNTER),
+	TI(0x1004d0, 0, 56, COUNTER),
+	TI(0x1004d8, 0, 56, COUNTER),
+	TI(0x1004a0, 0, 56, COUNTER),
+	TI(0x1004a8, 0, 56, COUNTER),
+	TI(0x1004b0, 0, 56, COUNTER),
+	TI(0x1004b8, 0, 56, COUNTER),
+	TI(0x100400, 0, 56, COUNTER),
+	TI(0x100430, 0, 56, COUNTER),
+	TI(0x100440, 0, 56, COUNTER),
+	TI(0x100438, 0, 56, COUNTER),
+};
+
+#define C2_TELEM_TOTAL	1923
+#define C2_TELEM_VALID	1922
+static const struct telem_item c2_items[C2_TELEM_TOTAL] = {
+	TU,
+	TI(0x100205d0, 0, 56, COUNTER),
+	TI(0x100205d8, 0, 56, COUNTER),
+	TI(0x100205e0, 0, 56, COUNTER),
+	TI(0x100205e8, 0, 56, COUNTER),
+	TI(0x100205c8, 0, 56, COUNTER),
+	TI(0x10020590, 0, 56, COUNTER),
+	TI(0x10020508, 0, 56, COUNTER),
+	TI(0x10020510, 0, 56, COUNTER),
+	TI(0x10020518, 0, 56, COUNTER),
+	TI(0x10020520, 0, 56, COUNTER),
+	TI(0x100205b8, 0, 56, COUNTER),
+	TI(0x100204a8, 0, 56, COUNTER),
+	TI(0x100204b0, 0, 56, COUNTER),
+	TI(0x100204b8, 0, 56, COUNTER),
+	TI(0x100204c0, 0, 56, COUNTER),
+	TI(0x100205a8, 0, 56, COUNTER),
+	TI(0x10020588, 0, 56, COUNTER),
+	TI(0x10020430, 0, 56, COUNTER),
+	TI(0x10020438, 0, 56, COUNTER),
+	TI(0x10020440, 0, 56, COUNTER),
+	TI(0x10020448, 0, 56, COUNTER),
+	TI(0x10020450, 0, 56, COUNTER),
+	TI(0x10020458, 0, 56, COUNTER),
+	TI(0x10020460, 0, 56, COUNTER),
+	TI(0x10020468, 0, 56, COUNTER),
+	TI(0x10020470, 0, 56, COUNTER),
+	TI(0x10020478, 0, 56, COUNTER),
+	TI(0x10020480, 0, 56, COUNTER),
+	TI(0x10020488, 0, 56, COUNTER),
+	TI(0x10020410, 0, 56, COUNTER),
+	TI(0x10020418, 0, 56, COUNTER),
+	TI(0x10020420, 0, 56, COUNTER),
+	TI(0x10020428, 0, 56, COUNTER),
+	TI(0x100204a0, 0, 56, COUNTER),
+	TI(0x10020498, 0, 56, COUNTER),
+	TI(0x10020490, 0, 56, COUNTER),
+	TI(0x100204f8, 0, 56, COUNTER),
+	TI(0x100204f0, 0, 56, COUNTER),
+	TI(0x100204e8, 0, 56, COUNTER),
+	TI(0x10020568, 0, 56, COUNTER),
+	TI(0x10020570, 0, 56, COUNTER),
+	TI(0x10020578, 0, 56, COUNTER),
+	TI(0x10020580, 0, 56, COUNTER),
+	TI(0x10020500, 0, 56, COUNTER),
+	TI(0x100205a0, 0, 56, COUNTER),
+	TI(0x10020598, 0, 56, COUNTER),
+	TI(0x100205f0, 0, 56, COUNTER),
+	TI(0x100205f8, 0, 56, COUNTER),
+	TI(0x10020400, 0, 56, COUNTER),
+	TI(0x10020408, 0, 56, COUNTER),
+	TI(0x10020528, 0, 56, COUNTER),
+	TI(0x10020530, 0, 56, COUNTER),
+	TI(0x10020538, 0, 56, COUNTER),
+	TI(0x10020540, 0, 56, COUNTER),
+	TI(0x100204c8, 0, 56, COUNTER),
+	TI(0x100204d0, 0, 56, COUNTER),
+	TI(0x100204d8, 0, 56, COUNTER),
+	TI(0x100204e0, 0, 56, COUNTER),
+	TI(0x10020548, 0, 56, COUNTER),
+	TI(0x10020550, 0, 56, COUNTER),
+	TI(0x10020558, 0, 56, COUNTER),
+	TI(0x10020560, 0, 56, COUNTER),
+	TI(0x100205c0, 0, 56, COUNTER),
+	TI(0x100205b0, 0, 56, COUNTER),
+	TI(0x540, 4, 16, COUNTER),
+	TI(0x100280, 0, 56, COUNTER),
+	TI(0x100288, 0, 56, COUNTER),
+	TI(0x100290, 0, 56, COUNTER),
+	TI(0x100298, 0, 56, COUNTER),
+	TI(0x1002a0, 0, 56, COUNTER),
+	TI(0x1002a8, 0, 56, COUNTER),
+	TI(0x1002b0, 0, 56, COUNTER),
+	TI(0x1002b8, 0, 56, COUNTER),
+	TI(0x1002c0, 0, 56, COUNTER),
+	TI(0x1002c8, 0, 56, COUNTER),
+	TI(0x1002d0, 0, 56, COUNTER),
+	TI(0x1002d8, 0, 56, COUNTER),
+	TI(0x1002e0, 0, 56, COUNTER),
+	TI(0x1002e8, 0, 56, COUNTER),
+	TI(0x1002f0, 0, 56, COUNTER),
+	TI(0x1002f8, 0, 56, COUNTER),
+	TI(0x100130, 0, 56, COUNTER),
+	TI(0x100140, 0, 56, COUNTER),
+	TI(0x100138, 0, 56, COUNTER),
+	TI(0x100148, 0, 56, COUNTER),
+	TI(0x100158, 0, 56, COUNTER),
+	TI(0x100150, 0, 56, COUNTER),
+	TI(0x100300, 0, 56, COUNTER),
+	TI(0x100308, 0, 56, COUNTER),
+	TI(0x100310, 0, 56, COUNTER),
+	TI(0x100318, 0, 56, COUNTER),
+	TI(0x100200, 0, 56, COUNTER),
+	TI(0x100208, 0, 56, COUNTER),
+	TI(0x100210, 0, 56, COUNTER),
+	TI(0x100218, 0, 56, COUNTER),
+	TI(0x100220, 0, 56, COUNTER),
+	TI(0x100228, 0, 56, COUNTER),
+	TI(0x100230, 0, 56, COUNTER),
+	TI(0x100238, 0, 56, COUNTER),
+	TI(0x100240, 0, 56, COUNTER),
+	TI(0x100248, 0, 56, COUNTER),
+	TI(0x100250, 0, 56, COUNTER),
+	TI(0x100258, 0, 56, COUNTER),
+	TI(0x100260, 0, 56, COUNTER),
+	TI(0x100268, 0, 56, COUNTER),
+	TI(0x100270, 0, 56, COUNTER),
+	TI(0x100278, 0, 56, COUNTER),
+	TI(0x100018, 0, 56, COUNTER),
+	TI(0x100010, 0, 56, COUNTER),
+	TI(0x100020, 0, 56, COUNTER),
+	TI(0x100028, 0, 56, COUNTER),
+	TI(0x1001a0, 0, 56, COUNTER),
+	TI(0x1001a8, 0, 56, COUNTER),
+	TI(0x1001b0, 0, 56, COUNTER),
+	TI(0x1001b8, 0, 56, COUNTER),
+	TI(0x100180, 0, 56, COUNTER),
+	TI(0x100188, 0, 56, COUNTER),
+	TI(0x100190, 0, 56, COUNTER),
+	TI(0x100198, 0, 56, COUNTER),
+	TI(0x100160, 0, 56, COUNTER),
+	TI(0x100168, 0, 56, COUNTER),
+	TI(0x100170, 0, 56, COUNTER),
+	TI(0x100178, 0, 56, COUNTER),
+	TI(0x1001c0, 0, 56, COUNTER),
+	TI(0x1001c8, 0, 56, COUNTER),
+	TI(0x1001d0, 0, 56, COUNTER),
+	TI(0x1001d8, 0, 56, COUNTER),
+	TI(0x1003e0, 0, 56, COUNTER),
+	TI(0x1003e8, 0, 56, COUNTER),
+	TI(0x1003f0, 0, 56, COUNTER),
+	TI(0x1003f8, 0, 56, COUNTER),
+	TI(0x1003a0, 0, 56, COUNTER),
+	TI(0x1003a8, 0, 56, COUNTER),
+	TI(0x1003b0, 0, 56, COUNTER),
+	TI(0x1003b8, 0, 56, COUNTER),
+	TI(0x1003c0, 0, 56, COUNTER),
+	TI(0x1003c8, 0, 56, COUNTER),
+	TI(0x1003d0, 0, 56, COUNTER),
+	TI(0x1003d8, 0, 56, COUNTER),
+	TI(0x100380, 0, 56, COUNTER),
+	TI(0x100388, 0, 56, COUNTER),
+	TI(0x100390, 0, 56, COUNTER),
+	TI(0x100398, 0, 56, COUNTER),
+	TI(0x100080, 0, 56, COUNTER),
+	TI(0x100088, 0, 56, COUNTER),
+	TI(0x100090, 0, 56, COUNTER),
+	TI(0x100098, 0, 56, COUNTER),
+	TI(0x100120, 0, 56, COUNTER),
+	TI(0x100128, 0, 56, COUNTER),
+	TI(0x1001e0, 0, 56, COUNTER),
+	TI(0x1001e8, 0, 56, COUNTER),
+	TI(0x1001f0, 0, 56, COUNTER),
+	TI(0x1001f8, 0, 56, COUNTER),
+	TI(0x1000a0, 0, 56, COUNTER),
+	TI(0x1000a8, 0, 56, COUNTER),
+	TI(0x1000b0, 0, 56, COUNTER),
+	TI(0x1000b8, 0, 56, COUNTER),
+	TI(0x100100, 0, 56, COUNTER),
+	TI(0x100110, 0, 56, COUNTER),
+	TI(0x100108, 0, 56, COUNTER),
+	TI(0x100118, 0, 56, COUNTER),
+	TI(0x100060, 0, 56, COUNTER),
+	TI(0x100068, 0, 56, COUNTER),
+	TI(0x100070, 0, 56, COUNTER),
+	TI(0x100078, 0, 56, COUNTER),
+	TI(0x100038, 0, 56, COUNTER),
+	TI(0x100030, 0, 56, COUNTER),
+	TI(0x8b0, 24, 5, UGAUGE),
+	TI(0x8b8, 52, 9, UGAUGE),
+	TI(0x8b8, 40, 9, UGAUGE),
+	TI(0x8b0, 0, 10, UGAUGE),
+	TI(0x8b0, 16, 4, UGAUGE),
+	TI(0x8b8, 0, 5, UGAUGE),
+	TI(0x8b0, 56, 5, UGAUGE),
+	TI(0x8b0, 48, 5, UGAUGE),
+	TI(0x8b8, 24, 3, UGAUGE),
+	TI(0x8b8, 36, 3, UGAUGE),
+	TI(0x8b8, 16, 3, UGAUGE),
+	TI(0x8b0, 40, 7, UGAUGE),
+	TI(0x8b8, 8, 5, UGAUGE),
+	TI(0x8b8, 32, 4, UGAUGE),
+	TI(0x4a000, 0, 56, COUNTER),
+	TI(0x4a008, 0, 56, COUNTER),
+	TI(0x4a010, 0, 56, COUNTER),
+	TI(0x4a018, 0, 56, COUNTER),
+	TI(0x4b000, 0, 41, UGAUGE),
+	TI(0x4b008, 0, 41, UGAUGE),
+	TI(0x4b010, 0, 41, UGAUGE),
+	TI(0x4b018, 0, 41, UGAUGE),
+	TI(0x4b020, 0, 41, UGAUGE),
+	TI(0x4b028, 0, 41, UGAUGE),
+	TI(0x4b030, 0, 41, UGAUGE),
+	TI(0x4b038, 0, 41, UGAUGE),
+	TI(0x4b040, 0, 41, UGAUGE),
+	TI(0x4b048, 0, 41, UGAUGE),
+	TI(0x4b050, 0, 41, UGAUGE),
+	TI(0x4b058, 0, 41, UGAUGE),
+	TI(0x4b060, 0, 41, UGAUGE),
+	TI(0x4b068, 0, 41, UGAUGE),
+	TI(0x4b070, 0, 41, UGAUGE),
+	TI(0x4b078, 0, 41, UGAUGE),
+	TI(0x4b080, 0, 41, UGAUGE),
+	TI(0x4b088, 0, 41, UGAUGE),
+	TI(0x4b090, 0, 41, UGAUGE),
+	TI(0x4b098, 0, 41, UGAUGE),
+	TI(0x4b0a0, 0, 41, UGAUGE),
+	TI(0x4b0a8, 0, 41, UGAUGE),
+	TI(0x4b0b0, 0, 41, UGAUGE),
+	TI(0x4b0b8, 0, 41, UGAUGE),
+	TI(0x4b0c0, 0, 41, UGAUGE),
+	TI(0x4b0c8, 0, 41, UGAUGE),
+	TI(0x4b0d0, 0, 41, UGAUGE),
+	TI(0x4b0d8, 0, 41, UGAUGE),
+	TI(0x4b0e0, 0, 41, UGAUGE),
+	TI(0x4b0e8, 0, 41, UGAUGE),
+	TI(0x4b0f0, 0, 41, UGAUGE),
+	TI(0x4b0f8, 0, 41, UGAUGE),
+	TI(0x4b100, 0, 41, UGAUGE),
+	TI(0x4b108, 0, 41, UGAUGE),
+	TI(0x4b110, 0, 41, UGAUGE),
+	TI(0x4b118, 0, 41, UGAUGE),
+	TI(0x4b120, 0, 41, UGAUGE),
+	TI(0x4b128, 0, 41, UGAUGE),
+	TI(0x4b130, 0, 41, UGAUGE),
+	TI(0x4b138, 0, 41, UGAUGE),
+	TI(0x4b140, 0, 41, UGAUGE),
+	TI(0x4b148, 0, 41, UGAUGE),
+	TI(0x4b150, 0, 41, UGAUGE),
+	TI(0x4b158, 0, 41, UGAUGE),
+	TI(0x4b160, 0, 41, UGAUGE),
+	TI(0x4b168, 0, 41, UGAUGE),
+	TI(0x4b170, 0, 41, UGAUGE),
+	TI(0x4b178, 0, 41, UGAUGE),
+	TI(0x4a020, 0, 56, COUNTER),
+	TI(0x4a028, 0, 56, COUNTER),
+	TI(0x4a030, 0, 56, COUNTER),
+	TI(0x4a038, 0, 56, COUNTER),
+	TI(0x4a040, 0, 56, COUNTER),
+	TI(0x4a048, 0, 56, COUNTER),
+	TI(0x4a050, 0, 56, COUNTER),
+	TI(0x4a058, 0, 56, COUNTER),
+	TI(0x4a080, 0, 56, COUNTER),
+	TI(0x4a088, 0, 56, COUNTER),
+	TI(0x4a090, 0, 56, COUNTER),
+	TI(0x4a098, 0, 56, COUNTER),
+	TI(0x850, 0, 12, UGAUGE),
+	TI(0x858, 0, 12, UGAUGE),
+	TI(0x860, 0, 12, UGAUGE),
+	TI(0x868, 0, 12, UGAUGE),
+	TI(0x4a060, 0, 56, COUNTER),
+	TI(0x4a068, 0, 56, COUNTER),
+	TI(0x4a070, 0, 56, COUNTER),
+	TI(0x4a078, 0, 56, COUNTER),
+	TI(0x100008, 0, 56, COUNTER),
+	TI(0x100000, 0, 56, COUNTER),
+	TI(0x1000e0, 0, 56, COUNTER),
+	TI(0x1000e8, 0, 56, COUNTER),
+	TI(0x1000f0, 0, 56, COUNTER),
+	TI(0x1000f8, 0, 56, COUNTER),
+	TI(0x1000c0, 0, 56, COUNTER),
+	TI(0x1000c8, 0, 56, COUNTER),
+	TI(0x1000d0, 0, 56, COUNTER),
+	TI(0x1000d8, 0, 56, COUNTER),
+	TI(0x100040, 0, 56, COUNTER),
+	TI(0x100b40, 0, 56, COUNTER),
+	TI(0x100b48, 0, 56, COUNTER),
+	TI(0x100b50, 0, 56, COUNTER),
+	TI(0x100b58, 0, 56, COUNTER),
+	TI(0x100d20, 0, 56, COUNTER),
+	TI(0x100aa0, 0, 56, COUNTER),
+	TI(0x100aa8, 0, 56, COUNTER),
+	TI(0x100ab0, 0, 56, COUNTER),
+	TI(0x100ab8, 0, 56, COUNTER),
+	TI(0x100c90, 0, 56, COUNTER),
+	TI(0x100c98, 0, 56, COUNTER),
+	TI(0x100c58, 0, 56, COUNTER),
+	TI(0x100c60, 0, 56, COUNTER),
+	TI(0x100c68, 0, 56, COUNTER),
+	TI(0x100b20, 0, 56, COUNTER),
+	TI(0x100b28, 0, 56, COUNTER),
+	TI(0x100b30, 0, 56, COUNTER),
+	TI(0x100b38, 0, 56, COUNTER),
+	TI(0x100b00, 0, 56, COUNTER),
+	TI(0x100b08, 0, 56, COUNTER),
+	TI(0x100b10, 0, 56, COUNTER),
+	TI(0x100b18, 0, 56, COUNTER),
+	TI(0x100e50, 0, 56, COUNTER),
+	TI(0x100e60, 0, 56, COUNTER),
+	TI(0x100e58, 0, 56, COUNTER),
+	TI(0x100e68, 0, 56, COUNTER),
+	TI(0x100e90, 0, 56, COUNTER),
+	TI(0x100a80, 0, 56, COUNTER),
+	TI(0x100a88, 0, 56, COUNTER),
+	TI(0x100a90, 0, 56, COUNTER),
+	TI(0x100a98, 0, 56, COUNTER),
+	TI(0x100b60, 0, 56, COUNTER),
+	TI(0x100b68, 0, 56, COUNTER),
+	TI(0x100b70, 0, 56, COUNTER),
+	TI(0x100b78, 0, 56, COUNTER),
+	TI(0x100d10, 0, 56, COUNTER),
+	TI(0x100cb0, 0, 56, COUNTER),
+	TI(0x100cb8, 0, 56, COUNTER),
+	TI(0x100d00, 0, 56, COUNTER),
+	TI(0x100d08, 0, 56, COUNTER),
+	TI(0x100cd0, 0, 56, COUNTER),
+	TI(0x100cd8, 0, 56, COUNTER),
+	TI(0x100d18, 0, 56, COUNTER),
+	TI(0x100cc0, 0, 56, COUNTER),
+	TI(0x100cc8, 0, 56, COUNTER),
+	TI(0x100ca8, 0, 56, COUNTER),
+	TI(0x100ce0, 0, 56, COUNTER),
+	TI(0x100ce8, 0, 56, COUNTER),
+	TI(0x100cf0, 0, 56, COUNTER),
+	TI(0x100cf8, 0, 56, COUNTER),
+	TI(0x100d88, 0, 56, COUNTER),
+	TI(0x100d50, 0, 56, COUNTER),
+	TI(0x100d70, 0, 56, COUNTER),
+	TI(0x100dc8, 0, 56, COUNTER),
+	TI(0x100e30, 0, 56, COUNTER),
+	TI(0x100e20, 0, 56, COUNTER),
+	TI(0x100dc0, 0, 56, COUNTER),
+	TI(0x100dd8, 0, 56, COUNTER),
+	TI(0x100d58, 0, 56, COUNTER),
+	TI(0x100d78, 0, 56, COUNTER),
+	TI(0x100d48, 0, 56, COUNTER),
+	TI(0x100d68, 0, 56, COUNTER),
+	TI(0x100d98, 0, 56, COUNTER),
+	TI(0x100de8, 0, 56, COUNTER),
+	TI(0x100e38, 0, 56, COUNTER),
+	TI(0x100de0, 0, 56, COUNTER),
+	TI(0x100d40, 0, 56, COUNTER),
+	TI(0x100d60, 0, 56, COUNTER),
+	TI(0x100db8, 0, 56, COUNTER),
+	TI(0x100d90, 0, 56, COUNTER),
+	TI(0x100da0, 0, 56, COUNTER),
+	TI(0x100d80, 0, 56, COUNTER),
+	TI(0x100da8, 0, 56, COUNTER),
+	TI(0x100e28, 0, 56, COUNTER),
+	TI(0x100dd0, 0, 56, COUNTER),
+	TI(0x100db0, 0, 56, COUNTER),
+	TI(0x100a40, 0, 56, COUNTER),
+	TI(0x100a48, 0, 56, COUNTER),
+	TI(0x100a50, 0, 56, COUNTER),
+	TI(0x100a58, 0, 56, COUNTER),
+	TI(0x100a60, 0, 56, COUNTER),
+	TI(0x100a68, 0, 56, COUNTER),
+	TI(0x100a70, 0, 56, COUNTER),
+	TI(0x100a78, 0, 56, COUNTER),
+	TI(0x100a20, 0, 56, COUNTER),
+	TI(0x100a28, 0, 56, COUNTER),
+	TI(0x100a30, 0, 56, COUNTER),
+	TI(0x100a38, 0, 56, COUNTER),
+	TI(0x100a00, 0, 56, COUNTER),
+	TI(0x100a08, 0, 56, COUNTER),
+	TI(0x100a10, 0, 56, COUNTER),
+	TI(0x100a18, 0, 56, COUNTER),
+	TI(0x100ae0, 0, 56, COUNTER),
+	TI(0x100ae8, 0, 56, COUNTER),
+	TI(0x100af0, 0, 56, COUNTER),
+	TI(0x100af8, 0, 56, COUNTER),
+	TI(0x100c80, 0, 56, COUNTER),
+	TI(0x100c88, 0, 56, COUNTER),
+	TI(0x100c40, 0, 56, COUNTER),
+	TI(0x100c48, 0, 56, COUNTER),
+	TI(0x100c50, 0, 56, COUNTER),
+	TI(0x100bc8, 0, 56, COUNTER),
+	TI(0x100bd8, 0, 56, COUNTER),
+	TI(0x100bc0, 0, 56, COUNTER),
+	TI(0x100bb0, 0, 56, COUNTER),
+	TI(0x100bb8, 0, 56, COUNTER),
+	TI(0x100bd0, 0, 56, COUNTER),
+	TI(0x100b98, 0, 56, COUNTER),
+	TI(0x100ba8, 0, 56, COUNTER),
+	TI(0x100b90, 0, 56, COUNTER),
+	TI(0x100b80, 0, 56, COUNTER),
+	TI(0x100b88, 0, 56, COUNTER),
+	TI(0x100ba0, 0, 56, COUNTER),
+	TI(0x100ca0, 0, 56, COUNTER),
+	TI(0x100e40, 0, 56, COUNTER),
+	TI(0x100e48, 0, 56, COUNTER),
+	TI(0x100bf8, 0, 56, COUNTER),
+	TI(0x100c08, 0, 56, COUNTER),
+	TI(0x100bf0, 0, 56, COUNTER),
+	TI(0x100be0, 0, 56, COUNTER),
+	TI(0x100be8, 0, 56, COUNTER),
+	TI(0x100c00, 0, 56, COUNTER),
+	TI(0x100ac0, 0, 56, COUNTER),
+	TI(0x100ac8, 0, 56, COUNTER),
+	TI(0x100ad0, 0, 56, COUNTER),
+	TI(0x100ad8, 0, 56, COUNTER),
+	TI(0x100c28, 0, 56, COUNTER),
+	TI(0x100c38, 0, 56, COUNTER),
+	TI(0x100c20, 0, 56, COUNTER),
+	TI(0x100c10, 0, 56, COUNTER),
+	TI(0x100c18, 0, 56, COUNTER),
+	TI(0x100c30, 0, 56, COUNTER),
+	TI(0x100e78, 0, 56, COUNTER),
+	TI(0x100e80, 0, 56, COUNTER),
+	TI(0x8800808, 0, 9, UGAUGE),
+	TI(0x8800808, 16, 9, UGAUGE),
+	TI(0x100e88, 0, 56, COUNTER),
+	TI(0x100d30, 0, 56, COUNTER),
+	TI(0x100d38, 0, 56, COUNTER),
+	TI(0x100d28, 0, 56, COUNTER),
+	TI(0x100c70, 0, 56, COUNTER),
+	TI(0x100c78, 0, 56, COUNTER),
+	TI(0x100e70, 0, 56, COUNTER),
+	TI(0x10004b8, 4, 16, COUNTER),
+	TI(0x1002000, 0, 56, COUNTER),
+	TI(0x10020c0, 0, 56, COUNTER),
+	TI(0x10020c8, 0, 56, COUNTER),
+	TI(0x10020d0, 0, 56, COUNTER),
+	TI(0x10020d8, 0, 56, COUNTER),
+	TI(0x10020e0, 0, 56, COUNTER),
+	TI(0x10020e8, 0, 56, COUNTER),
+	TI(0x10020f0, 0, 56, COUNTER),
+	TI(0x10020f8, 0, 56, COUNTER),
+	TI(0x10022b8, 0, 56, COUNTER),
+	TI(0x10022b0, 0, 56, COUNTER),
+	TI(0x10022a8, 0, 56, COUNTER),
+	TI(0x1002290, 0, 56, COUNTER),
+	TI(0x1002298, 0, 56, COUNTER),
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+	TI(0x1002b18, 0, 56, COUNTER),
+	TI(0x1002b70, 0, 56, COUNTER),
+	TI(0x1002a80, 0, 56, COUNTER),
+	TI(0x1002a88, 0, 56, COUNTER),
+	TI(0x1002a90, 0, 56, COUNTER),
+	TI(0x1002a98, 0, 56, COUNTER),
+	TI(0x1002aa0, 0, 56, COUNTER),
+	TI(0x1002aa8, 0, 56, COUNTER),
+	TI(0x1002ab0, 0, 56, COUNTER),
+	TI(0x1002ab8, 0, 56, COUNTER),
+	TI(0x1002ac0, 0, 56, COUNTER),
+	TI(0x1002ac8, 0, 56, COUNTER),
+	TI(0x1002b20, 0, 56, COUNTER),
+	TI(0x1002b28, 0, 56, COUNTER),
+	TI(0x1002b30, 0, 56, COUNTER),
+	TI(0x1002b38, 0, 56, COUNTER),
+	TI(0x1002b40, 0, 56, COUNTER),
+	TI(0x1002b48, 0, 56, COUNTER),
+	TI(0x1002b50, 0, 56, COUNTER),
+	TI(0x1002b58, 0, 56, COUNTER),
+	TI(0x1002b60, 0, 56, COUNTER),
+	TI(0x1002b68, 0, 56, COUNTER),
+	TI(0x1002a50, 0, 56, COUNTER),
+	TI(0x1002a48, 0, 56, COUNTER),
+	TI(0x10029b8, 0, 56, COUNTER),
+	TI(0x10029c0, 0, 56, COUNTER),
+	TI(0x10029c8, 0, 56, COUNTER),
+	TI(0x10029d0, 0, 56, COUNTER),
+	TI(0x10029d8, 0, 56, COUNTER),
+	TI(0x10029e0, 0, 56, COUNTER),
+	TI(0x10029e8, 0, 56, COUNTER),
+	TI(0x10029f0, 0, 56, COUNTER),
+	TI(0x1002a18, 0, 56, COUNTER),
+	TI(0x1002a20, 0, 56, COUNTER),
+	TI(0x1002a28, 0, 56, COUNTER),
+	TI(0x1002a30, 0, 56, COUNTER),
+	TI(0x10029f8, 0, 56, COUNTER),
+	TI(0x1002a00, 0, 56, COUNTER),
+	TI(0x1002a08, 0, 56, COUNTER),
+	TI(0x1002a10, 0, 56, COUNTER),
+	TI(0x1002a38, 0, 56, COUNTER),
+	TI(0x10029a8, 0, 56, COUNTER),
+	TI(0x1002958, 0, 56, COUNTER),
+	TI(0x1002960, 0, 56, COUNTER),
+	TI(0x1002968, 0, 56, COUNTER),
+	TI(0x1002970, 0, 56, COUNTER),
+	TI(0x1002978, 0, 56, COUNTER),
+	TI(0x1002980, 0, 56, COUNTER),
+	TI(0x1002988, 0, 56, COUNTER),
+	TI(0x1002990, 0, 56, COUNTER),
+	TI(0x1002998, 0, 56, COUNTER),
+	TI(0x10029a0, 0, 56, COUNTER),
+	TI(0x1002a40, 0, 56, COUNTER),
+	TI(0x10029b0, 0, 56, COUNTER),
+	TI(0x1002828, 0, 56, COUNTER),
+	TI(0x1002830, 0, 56, COUNTER),
+	TI(0x1002838, 0, 56, COUNTER),
+	TI(0x1002840, 0, 56, COUNTER),
+	TI(0x1002848, 0, 56, COUNTER),
+	TI(0x1002850, 0, 56, COUNTER),
+	TI(0x1002858, 0, 56, COUNTER),
+	TI(0x1002860, 0, 56, COUNTER),
+	TI(0x1002868, 0, 56, COUNTER),
+	TI(0x1002870, 0, 56, COUNTER),
+	TI(0x1002930, 0, 56, COUNTER),
+	TI(0x10027d8, 0, 56, COUNTER),
+	TI(0x10027e0, 0, 56, COUNTER),
+	TI(0x10027e8, 0, 56, COUNTER),
+	TI(0x10027f0, 0, 56, COUNTER),
+	TI(0x10027f8, 0, 56, COUNTER),
+	TI(0x1002800, 0, 56, COUNTER),
+	TI(0x1002808, 0, 56, COUNTER),
+	TI(0x1002810, 0, 56, COUNTER),
+	TI(0x1002818, 0, 56, COUNTER),
+	TI(0x1002820, 0, 56, COUNTER),
+	TI(0x1002928, 0, 56, COUNTER),
+	TI(0x10028c8, 0, 56, COUNTER),
+	TI(0x10028d0, 0, 56, COUNTER),
+	TI(0x10028d8, 0, 56, COUNTER),
+	TI(0x10028e0, 0, 56, COUNTER),
+	TI(0x10028e8, 0, 56, COUNTER),
+	TI(0x10028f0, 0, 56, COUNTER),
+	TI(0x10028f8, 0, 56, COUNTER),
+	TI(0x1002900, 0, 56, COUNTER),
+	TI(0x1002908, 0, 56, COUNTER),
+	TI(0x1002910, 0, 56, COUNTER),
+	TI(0x1002878, 0, 56, COUNTER),
+	TI(0x1002880, 0, 56, COUNTER),
+	TI(0x1002888, 0, 56, COUNTER),
+	TI(0x1002890, 0, 56, COUNTER),
+	TI(0x1002898, 0, 56, COUNTER),
+	TI(0x10028a0, 0, 56, COUNTER),
+	TI(0x10028a8, 0, 56, COUNTER),
+	TI(0x10028b0, 0, 56, COUNTER),
+	TI(0x10028b8, 0, 56, COUNTER),
+	TI(0x10028c0, 0, 56, COUNTER),
+	TI(0x1002920, 0, 56, COUNTER),
+	TI(0x1002918, 0, 56, COUNTER),
+	TI(0x1002938, 0, 56, COUNTER),
+	TI(0x1002940, 0, 56, COUNTER),
+	TI(0x1002948, 0, 56, COUNTER),
+	TI(0x1002950, 0, 56, COUNTER),
+	TI(0xa803400, 32, 11, UGAUGE),
+	TI(0xa803408, 32, 11, UGAUGE),
+	TI(0xa803410, 32, 11, UGAUGE),
+	TI(0xa803418, 32, 11, UGAUGE),
+	TI(0xa803420, 32, 11, UGAUGE),
+	TI(0xa803428, 32, 11, UGAUGE),
+	TI(0xa803430, 32, 11, UGAUGE),
+	TI(0xa803438, 32, 11, UGAUGE),
+	TI(0xa803440, 32, 11, UGAUGE),
+	TI(0xa803448, 32, 11, UGAUGE),
+	TI(0xa803400, 0, 11, UGAUGE),
+	TI(0xa803408, 0, 11, UGAUGE),
+	TI(0xa803410, 0, 11, UGAUGE),
+	TI(0xa803418, 0, 11, UGAUGE),
+	TI(0xa803420, 0, 11, UGAUGE),
+	TI(0xa803428, 0, 11, UGAUGE),
+	TI(0xa803430, 0, 11, UGAUGE),
+	TI(0xa803438, 0, 11, UGAUGE),
+	TI(0xa803440, 0, 11, UGAUGE),
+	TI(0xa803448, 0, 11, UGAUGE),
+	TI(0xa803400, 16, 11, UGAUGE),
+	TI(0xa803408, 16, 11, UGAUGE),
+	TI(0xa803410, 16, 11, UGAUGE),
+	TI(0xa803418, 16, 11, UGAUGE),
+	TI(0xa803420, 16, 11, UGAUGE),
+	TI(0xa803428, 16, 11, UGAUGE),
+	TI(0xa803430, 16, 11, UGAUGE),
+	TI(0xa803438, 16, 11, UGAUGE),
+	TI(0xa803440, 16, 11, UGAUGE),
+	TI(0xa803448, 16, 11, UGAUGE),
+	TI(0xa803000, 32, 11, UGAUGE),
+	TI(0xa803008, 32, 11, UGAUGE),
+	TI(0xa803010, 32, 11, UGAUGE),
+	TI(0xa803018, 32, 11, UGAUGE),
+	TI(0xa803020, 32, 11, UGAUGE),
+	TI(0xa803028, 32, 11, UGAUGE),
+	TI(0xa803030, 32, 11, UGAUGE),
+	TI(0xa803038, 32, 11, UGAUGE),
+	TI(0xa803040, 32, 11, UGAUGE),
+	TI(0xa803048, 32, 11, UGAUGE),
+	TI(0xa803050, 32, 11, UGAUGE),
+	TI(0xa803058, 32, 11, UGAUGE),
+	TI(0xa803060, 32, 11, UGAUGE),
+	TI(0xa803068, 32, 11, UGAUGE),
+	TI(0xa803070, 32, 11, UGAUGE),
+	TI(0xa803078, 32, 11, UGAUGE),
+	TI(0xa803080, 32, 11, UGAUGE),
+	TI(0xa803088, 32, 11, UGAUGE),
+	TI(0xa803090, 32, 11, UGAUGE),
+	TI(0xa803098, 32, 11, UGAUGE),
+	TI(0xa8030a0, 32, 11, UGAUGE),
+	TI(0xa8030a8, 32, 11, UGAUGE),
+	TI(0xa8030b0, 32, 11, UGAUGE),
+	TI(0xa8030b8, 32, 11, UGAUGE),
+	TI(0xa8030c0, 32, 11, UGAUGE),
+	TI(0xa8030c8, 32, 11, UGAUGE),
+	TI(0xa8030d0, 32, 11, UGAUGE),
+	TI(0xa8030d8, 32, 11, UGAUGE),
+	TI(0xa8030e0, 32, 11, UGAUGE),
+	TI(0xa8030e8, 32, 11, UGAUGE),
+	TI(0xa8030f0, 32, 11, UGAUGE),
+	TI(0xa8030f8, 32, 11, UGAUGE),
+	TI(0xa803100, 32, 11, UGAUGE),
+	TI(0xa803108, 32, 11, UGAUGE),
+	TI(0xa803110, 32, 11, UGAUGE),
+	TI(0xa803118, 32, 11, UGAUGE),
+	TI(0xa803120, 32, 11, UGAUGE),
+	TI(0xa803128, 32, 11, UGAUGE),
+	TI(0xa803130, 32, 11, UGAUGE),
+	TI(0xa803138, 32, 11, UGAUGE),
+	TI(0xa803140, 32, 11, UGAUGE),
+	TI(0xa803148, 32, 11, UGAUGE),
+	TI(0xa803150, 32, 11, UGAUGE),
+	TI(0xa803158, 32, 11, UGAUGE),
+	TI(0xa803160, 32, 11, UGAUGE),
+	TI(0xa803168, 32, 11, UGAUGE),
+	TI(0xa803170, 32, 11, UGAUGE),
+	TI(0xa803178, 32, 11, UGAUGE),
+	TI(0xa803180, 32, 11, UGAUGE),
+	TI(0xa803188, 32, 11, UGAUGE),
+	TI(0xa803190, 32, 11, UGAUGE),
+	TI(0xa803198, 32, 11, UGAUGE),
+	TI(0xa8031a0, 32, 11, UGAUGE),
+	TI(0xa8031a8, 32, 11, UGAUGE),
+	TI(0xa8031b0, 32, 11, UGAUGE),
+	TI(0xa8031b8, 32, 11, UGAUGE),
+	TI(0xa8031c0, 32, 11, UGAUGE),
+	TI(0xa8031c8, 32, 11, UGAUGE),
+	TI(0xa8031d0, 32, 11, UGAUGE),
+	TI(0xa8031d8, 32, 11, UGAUGE),
+	TI(0xa8031e0, 32, 11, UGAUGE),
+	TI(0xa8031e8, 32, 11, UGAUGE),
+	TI(0xa8031f0, 32, 11, UGAUGE),
+	TI(0xa8031f8, 32, 11, UGAUGE),
+	TI(0xa803200, 32, 11, UGAUGE),
+	TI(0xa803208, 32, 11, UGAUGE),
+	TI(0xa803210, 32, 11, UGAUGE),
+	TI(0xa803218, 32, 11, UGAUGE),
+	TI(0xa803220, 32, 11, UGAUGE),
+	TI(0xa803228, 32, 11, UGAUGE),
+	TI(0xa803230, 32, 11, UGAUGE),
+	TI(0xa803238, 32, 11, UGAUGE),
+	TI(0xa803240, 32, 11, UGAUGE),
+	TI(0xa803248, 32, 11, UGAUGE),
+	TI(0xa803250, 32, 11, UGAUGE),
+	TI(0xa803258, 32, 11, UGAUGE),
+	TI(0xa803260, 32, 11, UGAUGE),
+	TI(0xa803268, 32, 11, UGAUGE),
+	TI(0xa803270, 32, 11, UGAUGE),
+	TI(0xa803278, 32, 11, UGAUGE),
+	TI(0xa803280, 32, 11, UGAUGE),
+	TI(0xa803288, 32, 11, UGAUGE),
+	TI(0xa803290, 32, 11, UGAUGE),
+	TI(0xa803298, 32, 11, UGAUGE),
+	TI(0xa8032a0, 32, 11, UGAUGE),
+	TI(0xa8032a8, 32, 11, UGAUGE),
+	TI(0xa8032b0, 32, 11, UGAUGE),
+	TI(0xa8032b8, 32, 11, UGAUGE),
+	TI(0xa8032c0, 32, 11, UGAUGE),
+	TI(0xa8032c8, 32, 11, UGAUGE),
+	TI(0xa8032d0, 32, 11, UGAUGE),
+	TI(0xa8032d8, 32, 11, UGAUGE),
+	TI(0xa8032e0, 32, 11, UGAUGE),
+	TI(0xa8032e8, 32, 11, UGAUGE),
+	TI(0xa8032f0, 32, 11, UGAUGE),
+	TI(0xa8032f8, 32, 11, UGAUGE),
+	TI(0xa803000, 0, 11, UGAUGE),
+	TI(0xa803008, 0, 11, UGAUGE),
+	TI(0xa803010, 0, 11, UGAUGE),
+	TI(0xa803018, 0, 11, UGAUGE),
+	TI(0xa803020, 0, 11, UGAUGE),
+	TI(0xa803028, 0, 11, UGAUGE),
+	TI(0xa803030, 0, 11, UGAUGE),
+	TI(0xa803038, 0, 11, UGAUGE),
+	TI(0xa803040, 0, 11, UGAUGE),
+	TI(0xa803048, 0, 11, UGAUGE),
+	TI(0xa803050, 0, 11, UGAUGE),
+	TI(0xa803058, 0, 11, UGAUGE),
+	TI(0xa803060, 0, 11, UGAUGE),
+	TI(0xa803068, 0, 11, UGAUGE),
+	TI(0xa803070, 0, 11, UGAUGE),
+	TI(0xa803078, 0, 11, UGAUGE),
+	TI(0xa803080, 0, 11, UGAUGE),
+	TI(0xa803088, 0, 11, UGAUGE),
+	TI(0xa803090, 0, 11, UGAUGE),
+	TI(0xa803098, 0, 11, UGAUGE),
+	TI(0xa8030a0, 0, 11, UGAUGE),
+	TI(0xa8030a8, 0, 11, UGAUGE),
+	TI(0xa8030b0, 0, 11, UGAUGE),
+	TI(0xa8030b8, 0, 11, UGAUGE),
+	TI(0xa8030c0, 0, 11, UGAUGE),
+	TI(0xa8030c8, 0, 11, UGAUGE),
+	TI(0xa8030d0, 0, 11, UGAUGE),
+	TI(0xa8030d8, 0, 11, UGAUGE),
+	TI(0xa8030e0, 0, 11, UGAUGE),
+	TI(0xa8030e8, 0, 11, UGAUGE),
+	TI(0xa8030f0, 0, 11, UGAUGE),
+	TI(0xa8030f8, 0, 11, UGAUGE),
+	TI(0xa803100, 0, 11, UGAUGE),
+	TI(0xa803108, 0, 11, UGAUGE),
+	TI(0xa803110, 0, 11, UGAUGE),
+	TI(0xa803118, 0, 11, UGAUGE),
+	TI(0xa803120, 0, 11, UGAUGE),
+	TI(0xa803128, 0, 11, UGAUGE),
+	TI(0xa803130, 0, 11, UGAUGE),
+	TI(0xa803138, 0, 11, UGAUGE),
+	TI(0xa803140, 0, 11, UGAUGE),
+	TI(0xa803148, 0, 11, UGAUGE),
+	TI(0xa803150, 0, 11, UGAUGE),
+	TI(0xa803158, 0, 11, UGAUGE),
+	TI(0xa803160, 0, 11, UGAUGE),
+	TI(0xa803168, 0, 11, UGAUGE),
+	TI(0xa803170, 0, 11, UGAUGE),
+	TI(0xa803178, 0, 11, UGAUGE),
+	TI(0xa803180, 0, 11, UGAUGE),
+	TI(0xa803188, 0, 11, UGAUGE),
+	TI(0xa803190, 0, 11, UGAUGE),
+	TI(0xa803198, 0, 11, UGAUGE),
+	TI(0xa8031a0, 0, 11, UGAUGE),
+	TI(0xa8031a8, 0, 11, UGAUGE),
+	TI(0xa8031b0, 0, 11, UGAUGE),
+	TI(0xa8031b8, 0, 11, UGAUGE),
+	TI(0xa8031c0, 0, 11, UGAUGE),
+	TI(0xa8031c8, 0, 11, UGAUGE),
+	TI(0xa8031d0, 0, 11, UGAUGE),
+	TI(0xa8031d8, 0, 11, UGAUGE),
+	TI(0xa8031e0, 0, 11, UGAUGE),
+	TI(0xa8031e8, 0, 11, UGAUGE),
+	TI(0xa8031f0, 0, 11, UGAUGE),
+	TI(0xa8031f8, 0, 11, UGAUGE),
+	TI(0xa803200, 0, 11, UGAUGE),
+	TI(0xa803208, 0, 11, UGAUGE),
+	TI(0xa803210, 0, 11, UGAUGE),
+	TI(0xa803218, 0, 11, UGAUGE),
+	TI(0xa803220, 0, 11, UGAUGE),
+	TI(0xa803228, 0, 11, UGAUGE),
+	TI(0xa803230, 0, 11, UGAUGE),
+	TI(0xa803238, 0, 11, UGAUGE),
+	TI(0xa803240, 0, 11, UGAUGE),
+	TI(0xa803248, 0, 11, UGAUGE),
+	TI(0xa803250, 0, 11, UGAUGE),
+	TI(0xa803258, 0, 11, UGAUGE),
+	TI(0xa803260, 0, 11, UGAUGE),
+	TI(0xa803268, 0, 11, UGAUGE),
+	TI(0xa803270, 0, 11, UGAUGE),
+	TI(0xa803278, 0, 11, UGAUGE),
+	TI(0xa803280, 0, 11, UGAUGE),
+	TI(0xa803288, 0, 11, UGAUGE),
+	TI(0xa803290, 0, 11, UGAUGE),
+	TI(0xa803298, 0, 11, UGAUGE),
+	TI(0xa8032a0, 0, 11, UGAUGE),
+	TI(0xa8032a8, 0, 11, UGAUGE),
+	TI(0xa8032b0, 0, 11, UGAUGE),
+	TI(0xa8032b8, 0, 11, UGAUGE),
+	TI(0xa8032c0, 0, 11, UGAUGE),
+	TI(0xa8032c8, 0, 11, UGAUGE),
+	TI(0xa8032d0, 0, 11, UGAUGE),
+	TI(0xa8032d8, 0, 11, UGAUGE),
+	TI(0xa8032e0, 0, 11, UGAUGE),
+	TI(0xa8032e8, 0, 11, UGAUGE),
+	TI(0xa8032f0, 0, 11, UGAUGE),
+	TI(0xa8032f8, 0, 11, UGAUGE),
+	TI(0x9870c98, 0, 56, COUNTER),
+	TI(0x9870c90, 0, 56, COUNTER),
+	TI(0x9870c68, 0, 56, COUNTER),
+	TI(0x9870c60, 0, 56, COUNTER),
+	TI(0x9870c70, 0, 56, COUNTER),
+	TI(0x9870c80, 0, 56, COUNTER),
+	TI(0x9870c78, 0, 56, COUNTER),
+	TI(0x9870c88, 0, 56, COUNTER),
+	TI(0x9870c48, 0, 56, COUNTER),
+	TI(0x9870c58, 0, 56, COUNTER),
+	TI(0x9870c40, 0, 56, COUNTER),
+	TI(0x9870c50, 0, 56, COUNTER),
+	TI(0x9001008, 8, 6, UGAUGE),
+	TI(0x9001008, 0, 6, UGAUGE),
+	TI(0x9870b48, 0, 56, COUNTER),
+	TI(0x9870be8, 0, 56, COUNTER),
+	TI(0x9870ba8, 0, 56, COUNTER),
+	TI(0x9870b38, 0, 56, COUNTER),
+	TI(0x9870be0, 0, 56, COUNTER),
+	TI(0x9870ba0, 0, 56, COUNTER),
+	TI(0x9870b30, 0, 56, COUNTER),
+	TI(0x9870b40, 0, 56, COUNTER),
+	TI(0x9870ad8, 0, 56, COUNTER),
+	TI(0x9870bb8, 0, 56, COUNTER),
+	TI(0x9870b78, 0, 56, COUNTER),
+	TI(0x9870ac8, 0, 56, COUNTER),
+	TI(0x9870bb0, 0, 56, COUNTER),
+	TI(0x9870b70, 0, 56, COUNTER),
+	TI(0x9870ac0, 0, 56, COUNTER),
+	TI(0x9870ad0, 0, 56, COUNTER),
+	TI(0x9870af0, 0, 56, COUNTER),
+	TI(0x9870bc0, 0, 56, COUNTER),
+	TI(0x9870b80, 0, 56, COUNTER),
+	TI(0x9870ae0, 0, 56, COUNTER),
+	TI(0x9870ae8, 0, 56, COUNTER),
+	TI(0x9870b10, 0, 56, COUNTER),
+	TI(0x9870bd0, 0, 56, COUNTER),
+	TI(0x9870b90, 0, 56, COUNTER),
+	TI(0x9870b00, 0, 56, COUNTER),
+	TI(0x9870bc8, 0, 56, COUNTER),
+	TI(0x9870b88, 0, 56, COUNTER),
+	TI(0x9870af8, 0, 56, COUNTER),
+	TI(0x9870b08, 0, 56, COUNTER),
+	TI(0x9870b28, 0, 56, COUNTER),
+	TI(0x9870bd8, 0, 56, COUNTER),
+	TI(0x9870b98, 0, 56, COUNTER),
+	TI(0x9870b18, 0, 56, COUNTER),
+	TI(0x9870b20, 0, 56, COUNTER),
+	TI(0x9870b68, 0, 56, COUNTER),
+	TI(0x9870b58, 0, 56, COUNTER),
+	TI(0x9870b60, 0, 56, COUNTER),
+	TI(0x9870b50, 0, 56, COUNTER),
+	TI(0x100698, 0, 56, COUNTER),
+	TI(0x1006b0, 0, 56, COUNTER),
+	TI(0x1006a0, 0, 56, COUNTER),
+	TI(0x100688, 0, 56, COUNTER),
+	TI(0x100728, 0, 56, COUNTER),
+	TI(0x100690, 0, 56, COUNTER),
+	TI(0x100720, 0, 56, COUNTER),
+	TI(0x1007d8, 0, 56, COUNTER),
+	TI(0x100680, 0, 56, COUNTER),
+	TI(0x100660, 0, 56, COUNTER),
+	TI(0x100668, 0, 56, COUNTER),
+	TI(0x1006e8, 0, 56, COUNTER),
+	TI(0x1006e0, 0, 56, COUNTER),
+	TI(0x100628, 0, 56, COUNTER),
+	TI(0x100900, 0, 56, COUNTER),
+	TI(0x100908, 0, 56, COUNTER),
+	TI(0x100910, 0, 56, COUNTER),
+	TI(0x100918, 0, 56, COUNTER),
+	TI(0x100920, 0, 56, COUNTER),
+	TI(0x100928, 0, 56, COUNTER),
+	TI(0x100930, 0, 56, COUNTER),
+	TI(0x100938, 0, 56, COUNTER),
+	TI(0x100940, 0, 56, COUNTER),
+	TI(0x100948, 0, 56, COUNTER),
+	TI(0x100950, 0, 56, COUNTER),
+	TI(0x100958, 0, 56, COUNTER),
+	TI(0x100960, 0, 56, COUNTER),
+	TI(0x100968, 0, 56, COUNTER),
+	TI(0x100970, 0, 56, COUNTER),
+	TI(0x100978, 0, 56, COUNTER),
+	TI(0x100648, 0, 56, COUNTER),
+	TI(0x100650, 0, 56, COUNTER),
+	TI(0x100658, 0, 56, COUNTER),
+	TI(0x100600, 0, 56, COUNTER),
+	TI(0x100608, 0, 56, COUNTER),
+	TI(0x100670, 0, 56, COUNTER),
+	TI(0x1006d0, 0, 56, COUNTER),
+	TI(0x1006c0, 0, 56, COUNTER),
+	TI(0x1006b8, 0, 56, COUNTER),
+	TI(0x1006c8, 0, 56, COUNTER),
+	TI(0x100630, 0, 56, COUNTER),
+	TI(0x100798, 0, 56, COUNTER),
+	TI(0x1007a0, 0, 56, COUNTER),
+	TI(0x100788, 0, 56, COUNTER),
+	TI(0x100790, 0, 56, COUNTER),
+	TI(0x100778, 0, 56, COUNTER),
+	TI(0x100780, 0, 56, COUNTER),
+	TI(0x1007a8, 0, 56, COUNTER),
+	TI(0x1007b8, 0, 56, COUNTER),
+	TI(0x1007b0, 0, 56, COUNTER),
+	TI(0x1007c0, 0, 56, COUNTER),
+	TI(0xb00130, 32, 12, UGAUGE),
+	TI(0xb00130, 0, 12, UGAUGE),
+	TI(0xb00100, 32, 13, UGAUGE),
+	TI(0xb00100, 0, 13, UGAUGE),
+	TI(0xb00118, 32, 9, UGAUGE),
+	TI(0xb00118, 0, 9, UGAUGE),
+	TI(0xb00110, 32, 12, UGAUGE),
+	TI(0xb00110, 0, 12, UGAUGE),
+	TI(0xb00128, 32, 12, UGAUGE),
+	TI(0xb00128, 0, 12, UGAUGE),
+	TI(0xb00108, 32, 14, UGAUGE),
+	TI(0xb00108, 0, 14, UGAUGE),
+	TI(0xb00120, 32, 14, UGAUGE),
+	TI(0xb00120, 0, 14, UGAUGE),
+	TI(0x100638, 0, 56, COUNTER),
+	TI(0x100740, 0, 56, COUNTER),
+	TI(0x100738, 0, 56, COUNTER),
+	TI(0x100748, 0, 56, COUNTER),
+	TI(0x100620, 0, 56, COUNTER),
+	TI(0x100610, 0, 56, COUNTER),
+	TI(0x100800, 0, 56, COUNTER),
+	TI(0x100808, 0, 56, COUNTER),
+	TI(0x100810, 0, 56, COUNTER),
+	TI(0x100818, 0, 56, COUNTER),
+	TI(0x100820, 0, 56, COUNTER),
+	TI(0x100828, 0, 56, COUNTER),
+	TI(0x100830, 0, 56, COUNTER),
+	TI(0x100838, 0, 56, COUNTER),
+	TI(0x100840, 0, 56, COUNTER),
+	TI(0x100848, 0, 56, COUNTER),
+	TI(0x100850, 0, 56, COUNTER),
+	TI(0x100858, 0, 56, COUNTER),
+	TI(0x100860, 0, 56, COUNTER),
+	TI(0x100868, 0, 56, COUNTER),
+	TI(0x100870, 0, 56, COUNTER),
+	TI(0x100878, 0, 56, COUNTER),
+	TI(0x100880, 0, 56, COUNTER),
+	TI(0x100888, 0, 56, COUNTER),
+	TI(0x100890, 0, 56, COUNTER),
+	TI(0x100898, 0, 56, COUNTER),
+	TI(0x1008a0, 0, 56, COUNTER),
+	TI(0x1008a8, 0, 56, COUNTER),
+	TI(0x1008b0, 0, 56, COUNTER),
+	TI(0x1008b8, 0, 56, COUNTER),
+	TI(0x1008c0, 0, 56, COUNTER),
+	TI(0x1008c8, 0, 56, COUNTER),
+	TI(0x1008d0, 0, 56, COUNTER),
+	TI(0x1008d8, 0, 56, COUNTER),
+	TI(0x1008e0, 0, 56, COUNTER),
+	TI(0x1008e8, 0, 56, COUNTER),
+	TI(0x1008f0, 0, 56, COUNTER),
+	TI(0x1008f8, 0, 56, COUNTER),
+	TI(0x1006a8, 0, 56, COUNTER),
+	TI(0x1007e0, 0, 56, COUNTER),
+	TI(0x100618, 0, 56, COUNTER),
+	TI(0x1006d8, 0, 56, COUNTER),
+	TI(0x100640, 0, 56, COUNTER),
+	TI(0x100718, 0, 56, COUNTER),
+	TI(0x100708, 0, 56, COUNTER),
+	TI(0x100710, 0, 56, COUNTER),
+	TI(0x100768, 0, 56, COUNTER),
+	TI(0x100770, 0, 56, COUNTER),
+	TI(0x100758, 0, 56, COUNTER),
+	TI(0x100760, 0, 56, COUNTER),
+	TI(0x100750, 0, 56, COUNTER),
+	TI(0x1007c8, 0, 56, COUNTER),
+	TI(0x1006f8, 0, 56, COUNTER),
+	TI(0x1006f0, 0, 56, COUNTER),
+	TI(0x100700, 0, 56, COUNTER),
+	TI(0x1007d0, 0, 56, COUNTER),
+	TI(0x100678, 0, 56, COUNTER),
+	TI(0x1007e8, 0, 56, COUNTER),
+	TI(0x100730, 0, 56, COUNTER),
+	TI(0x100203b8, 0, 56, COUNTER),
+	TI(0x100203c0, 0, 56, COUNTER),
+	TI(0x100203d0, 0, 56, COUNTER),
+	TI(0x100203c8, 0, 56, COUNTER),
+	TI(0x100203e0, 0, 56, COUNTER),
+	TI(0x100203f0, 0, 56, COUNTER),
+	TI(0x100203f8, 0, 56, COUNTER),
+	TI(0x100203e8, 0, 56, COUNTER),
+	TI(0x100203d8, 0, 56, COUNTER),
+	TI(0x11005000, 4, 16, COUNTER),
+	TI(0x110061d8, 0, 56, COUNTER),
+	TI(0x110061d0, 0, 56, COUNTER),
+	TI(0x110061c0, 0, 56, COUNTER),
+	TI(0x110061c8, 0, 56, COUNTER),
+	TI(0x110061e0, 0, 56, COUNTER),
+	TI(0x110061e8, 0, 56, COUNTER),
+	TI(0x11006178, 0, 56, COUNTER),
+	TI(0x11006170, 0, 56, COUNTER),
+	TI(0x11006160, 0, 56, COUNTER),
+	TI(0x11006168, 0, 56, COUNTER),
+	TI(0x11006158, 0, 56, COUNTER),
+	TI(0x11006150, 0, 56, COUNTER),
+	TI(0x11006140, 0, 56, COUNTER),
+	TI(0x11006148, 0, 56, COUNTER),
+	TI(0x11006180, 0, 56, COUNTER),
+	TI(0x11006188, 0, 56, COUNTER),
+	TI(0x110061b0, 0, 56, COUNTER),
+	TI(0x110061b8, 0, 56, COUNTER),
+	TI(0x11006190, 0, 56, COUNTER),
+	TI(0x11006198, 0, 56, COUNTER),
+	TI(0x11006068, 0, 56, COUNTER),
+	TI(0x11006060, 0, 56, COUNTER),
+	TI(0x11006050, 0, 56, COUNTER),
+	TI(0x11006058, 0, 56, COUNTER),
+	TI(0x11006030, 0, 56, COUNTER),
+	TI(0x11006038, 0, 56, COUNTER),
+	TI(0x11006048, 0, 56, COUNTER),
+	TI(0x11006040, 0, 56, COUNTER),
+	TI(0x11006010, 0, 56, COUNTER),
+	TI(0x11006018, 0, 56, COUNTER),
+	TI(0x11006020, 0, 56, COUNTER),
+	TI(0x11006008, 0, 56, COUNTER),
+	TI(0x11006000, 0, 56, COUNTER),
+	TI(0x11006028, 0, 56, COUNTER),
+	TI(0x11006118, 0, 56, COUNTER),
+	TI(0x11006110, 0, 56, COUNTER),
+	TI(0x11006108, 0, 56, COUNTER),
+	TI(0x11006120, 0, 56, COUNTER),
+	TI(0x11006090, 0, 56, COUNTER),
+	TI(0x11006088, 0, 56, COUNTER),
+	TI(0x110060f0, 0, 56, COUNTER),
+	TI(0x110060e8, 0, 56, COUNTER),
+	TI(0x11006098, 0, 56, COUNTER),
+	TI(0x11006100, 0, 56, COUNTER),
+	TI(0x110060f8, 0, 56, COUNTER),
+	TI(0x110061a0, 0, 56, COUNTER),
+	TI(0x110061a8, 0, 56, COUNTER),
+	TI(0x11006080, 0, 56, COUNTER),
+	TI(0x110060d8, 0, 56, COUNTER),
+	TI(0x110060d0, 0, 56, COUNTER),
+	TI(0x110060c8, 0, 56, COUNTER),
+	TI(0x110060c0, 0, 56, COUNTER),
+	TI(0x110060e0, 0, 56, COUNTER),
+	TI(0x11006128, 0, 56, COUNTER),
+	TI(0x11006130, 0, 56, COUNTER),
+	TI(0x11006138, 0, 56, COUNTER),
+	TI(0x110060b0, 0, 56, COUNTER),
+	TI(0x110060b8, 0, 56, COUNTER),
+	TI(0x110060a0, 0, 56, COUNTER),
+	TI(0x110060a8, 0, 56, COUNTER),
+	TI(0x11006078, 0, 56, COUNTER),
+	TI(0x11006070, 0, 56, COUNTER),
+	TI(0x10020268, 0, 56, COUNTER),
+	TI(0x10020280, 0, 56, COUNTER),
+	TI(0x10020290, 0, 56, COUNTER),
+	TI(0x10020288, 0, 56, COUNTER),
+	TI(0x10020260, 0, 56, COUNTER),
+	TI(0x10020270, 0, 56, COUNTER),
+	TI(0x10020278, 0, 56, COUNTER),
+	TI(0x10020238, 0, 56, COUNTER),
+	TI(0x10020240, 0, 56, COUNTER),
+	TI(0x10020210, 0, 56, COUNTER),
+	TI(0x10020208, 0, 56, COUNTER),
+	TI(0x10020228, 0, 56, COUNTER),
+	TI(0x10020220, 0, 56, COUNTER),
+	TI(0x10020230, 0, 56, COUNTER),
+	TI(0x10020218, 0, 56, COUNTER),
+	TI(0x10020200, 0, 56, COUNTER),
+	TI(0x10020250, 0, 56, COUNTER),
+	TI(0x10020248, 0, 56, COUNTER),
+	TI(0x10020258, 0, 56, COUNTER),
+	TI(0x100202e0, 0, 56, COUNTER),
+	TI(0x100202e8, 0, 56, COUNTER),
+	TI(0x100202d8, 0, 56, COUNTER),
+	TI(0x100202d0, 0, 56, COUNTER),
+	TI(0x100202c0, 0, 56, COUNTER),
+	TI(0x100202c8, 0, 56, COUNTER),
+	TI(0x100202a8, 0, 56, COUNTER),
+	TI(0x100202b0, 0, 56, COUNTER),
+	TI(0x100202a0, 0, 56, COUNTER),
+	TI(0x100202b8, 0, 56, COUNTER),
+	TI(0x10020298, 0, 56, COUNTER),
+	TI(0x100202f0, 0, 56, COUNTER),
+	TI(0x100202f8, 0, 56, COUNTER),
+	TI(0x10020380, 0, 56, COUNTER),
+	TI(0x10020388, 0, 56, COUNTER),
+	TI(0x10020350, 0, 56, COUNTER),
+	TI(0x10020370, 0, 56, COUNTER),
+	TI(0x10020378, 0, 56, COUNTER),
+	TI(0x10020358, 0, 56, COUNTER),
+	TI(0x10020328, 0, 56, COUNTER),
+	TI(0x10020360, 0, 56, COUNTER),
+	TI(0x10020368, 0, 56, COUNTER),
+	TI(0x10020340, 0, 56, COUNTER),
+	TI(0x10020330, 0, 56, COUNTER),
+	TI(0x10020320, 0, 56, COUNTER),
+	TI(0x10020318, 0, 56, COUNTER),
+	TI(0x10020348, 0, 56, COUNTER),
+	TI(0x10020308, 0, 56, COUNTER),
+	TI(0x10020300, 0, 56, COUNTER),
+	TI(0x10020310, 0, 56, COUNTER),
+	TI(0x10020338, 0, 56, COUNTER),
+	TI(0x9870a78, 0, 56, COUNTER),
+	TI(0x9870a80, 0, 56, COUNTER),
+	TI(0x9870a48, 0, 56, COUNTER),
+	TI(0x9870a50, 0, 56, COUNTER),
+	TI(0x9870a58, 0, 56, COUNTER),
+	TI(0x9870a60, 0, 56, COUNTER),
+	TI(0x9870a68, 0, 56, COUNTER),
+	TI(0x9870a70, 0, 56, COUNTER),
+	TI(0x9870a40, 0, 56, COUNTER),
+	TI(0x100450, 0, 56, COUNTER),
+	TI(0x100420, 0, 56, COUNTER),
+	TI(0x100428, 0, 56, COUNTER),
+	TI(0x1004e0, 0, 56, COUNTER),
+	TI(0x1004e8, 0, 56, COUNTER),
+	TI(0x1004f0, 0, 56, COUNTER),
+	TI(0x1004f8, 0, 56, COUNTER),
+	TI(0x100500, 0, 56, COUNTER),
+	TI(0x100508, 0, 56, COUNTER),
+	TI(0x100510, 0, 56, COUNTER),
+	TI(0x100518, 0, 56, COUNTER),
+	TI(0x100520, 0, 56, COUNTER),
+	TI(0x100528, 0, 56, COUNTER),
+	TI(0x100530, 0, 56, COUNTER),
+	TI(0x100538, 0, 56, COUNTER),
+	TI(0x100540, 0, 56, COUNTER),
+	TI(0x100548, 0, 56, COUNTER),
+	TI(0x100550, 0, 56, COUNTER),
+	TI(0x100558, 0, 56, COUNTER),
+	TI(0x100408, 0, 56, COUNTER),
+	TI(0x100448, 0, 56, COUNTER),
+	TI(0x100498, 0, 56, COUNTER),
+	TI(0x100490, 0, 56, COUNTER),
+	TI(0x1004c0, 0, 56, COUNTER),
+	TI(0x1004c8, 0, 56, COUNTER),
+	TI(0x1004d0, 0, 56, COUNTER),
+	TI(0x1004d8, 0, 56, COUNTER),
+	TI(0x1004a0, 0, 56, COUNTER),
+	TI(0x1004a8, 0, 56, COUNTER),
+	TI(0x1004b0, 0, 56, COUNTER),
+	TI(0x1004b8, 0, 56, COUNTER),
+	TI(0x100400, 0, 56, COUNTER),
+	TI(0x100430, 0, 56, COUNTER),
+	TI(0x100440, 0, 56, COUNTER),
+	TI(0x100438, 0, 56, COUNTER),
+};
+
+#endif
diff --git a/drivers/net/ethernet/hpe/ss1/cass_trace.h b/drivers/net/ethernet/hpe/ss1/cass_trace.h
new file mode 100644
index 000000000000..34aa601cb57a
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_trace.h
@@ -0,0 +1,60 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2019 Hewlett Packard Enterprise Development LP */
+
+/* Cassini Kernel Trace Event Definition */
+
+#undef TRACE_SYSTEM
+#define TRACE_SYSTEM cass
+
+#if !defined(_CASS_TRACE_H) || defined(TRACE_HEADER_MULTI_READ)
+#define _CASS_TRACE_H
+
+#include <linux/tracepoint.h>
+
+TRACE_EVENT(
+	cass_err,
+	TP_PROTO(unsigned int csr_flag, unsigned int bit,
+		 unsigned long seconds, unsigned long nanoseconds,
+		 const struct flg_err_info *flg_info,
+		 struct err_info *err_info,
+		 u64 *cntrs_val),
+	TP_ARGS(csr_flag, bit, seconds, nanoseconds, flg_info,
+		err_info, cntrs_val),
+	TP_STRUCT__entry(
+		__field(unsigned int, csr_flag)
+		__field(unsigned int, bit)
+		__field(unsigned long, seconds)
+		__field(unsigned long, nanoseconds)
+		__field(enum c_error_class, ec)
+		__dynamic_array(u64, err_info_data_0, err_info[0].count)
+		__dynamic_array(u64, err_info_data_1, err_info[1].count)
+		__dynamic_array(u64, err_info_data_2, err_info[2].count)
+		__array(u64, cntrs_val, C_MAX_CSR_CNTRS)
+	),
+	TP_fast_assign(
+		__entry->csr_flag = csr_flag;
+		__entry->bit = bit;
+		__entry->seconds = seconds;
+		__entry->nanoseconds = nanoseconds;
+		__entry->ec = flg_info->ec;
+		memcpy(__get_dynamic_array(err_info_data_0), err_info[0].data,
+		       err_info[0].count * sizeof(u64));
+		memcpy(__get_dynamic_array(err_info_data_1), err_info[1].data,
+		       err_info[1].count * sizeof(u64));
+		memcpy(__get_dynamic_array(err_info_data_2), err_info[2].data,
+		       err_info[2].count * sizeof(u64));
+		memcpy(__entry->cntrs_val, cntrs_val,
+		       C_MAX_CSR_CNTRS * sizeof(u64));
+	),
+	TP_printk("csr_flag: %u, bit: %u, ec: %u",
+		  __entry->csr_flag, __entry->bit, __entry->ec)
+);
+
+#endif /* _CASS_TRACE_H */
+
+#undef TRACE_INCLUDE_PATH
+#define TRACE_INCLUDE_PATH .
+#undef TRACE_INCLUDE_FILE
+#define TRACE_INCLUDE_FILE cass_trace
+
+#include <trace/define_trace.h>
diff --git a/drivers/net/ethernet/hpe/ss1/cass_vf.h b/drivers/net/ethernet/hpe/ss1/cass_vf.h
new file mode 100644
index 000000000000..f204767c33fb
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_vf.h
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2025-2026 Hewlett Packard Enterprise Development LP */
+
+#ifndef _CASS_VF_H
+#define _CASS_VF_H
+
+/* VF private structures */
+struct cxi_lni_priv_vf {
+	/* Matching fields in cxi_lni_priv */
+	struct cxi_dev *dev;
+	struct cxi_lni lni;
+	/* VF only fields */
+	int phys_lac; /* Physical LAC associated with this LNI */
+};
+
+struct cxi_domain_priv_vf {
+	/* Matching fields in cxi_domain_priv */
+	struct cxi_domain domain;
+	struct cxi_lni_priv *lni_priv;
+};
+
+struct cxi_cp_priv_vf {
+	/* Matching fields in cxi_cp_priv */
+	struct cxi_dev *dev;
+	struct cxi_cp cp;
+	/* VF only fields */
+	unsigned int cp_hndl;
+};
+
+struct cxi_cq_priv_vf {
+	/* Matching fields in cxi_cq_priv */
+	struct cxi_lni_priv *lni_priv;
+	struct cxi_cq cass_cq;
+	size_t cmds_len;
+	size_t cmds_order;
+	struct page **pages;
+	struct page *cmds_pages;
+	void *cmds;
+	dma_addr_t cmds_dma_addr;
+	void __iomem *cq_mmio;
+	u32 flags;
+	struct cxi_md_priv *md_priv;
+};
+
+struct cxi_md_priv_vf {
+	/* Matching fields in cxi_md_priv */
+	struct cxi_lni_priv *lni_priv;
+	struct device *device;
+	struct cxi_md md;
+	struct sg_table *sgt;        /* Scatter-gather table for DMA mapping */
+	struct page **pages;         /* Array of pinned pages */
+	u32 flags;                   /* Mapping flags */
+	/* VF only fields */
+	int npages;                  /* Number of pinned pages */
+};
+
+int cass_vf_get_token(struct cxi_dev *cdev, int vf_idx, unsigned int *token);
+
+#endif /* CASS_VF_H */
diff --git a/drivers/net/ethernet/hpe/ss1/cass_vf_notif.h b/drivers/net/ethernet/hpe/ss1/cass_vf_notif.h
new file mode 100644
index 000000000000..eb45ffa0fa91
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_vf_notif.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+#ifndef	_CASS_VF_NOTIF_H
+#define	_CASS_VF_NOTIF_H
+
+enum cass_vf_notif_ops {
+	CASS_VF_NOTIF_OP_INVALID = 0,
+	CASS_VF_NOTIF_OP_PING,
+	CASS_VF_NOTIF_OP_MAX,
+};
+
+struct cass_vf_notif_common {
+	enum cass_vf_notif_ops op;
+};
+
+struct cass_vf_notif_ping {
+	enum cass_vf_notif_ops op;
+};
+
+struct cass_vf_notif_info {
+	unsigned int req_size;
+	const char *name;
+	int (*handler)(struct cass_dev *hw, const void *cmd_in,
+		       void *resp, size_t *resp_len);
+};
+
+int dispatch_vf_notif(struct cass_dev *hw, const void *req, size_t req_len,
+		      void *rsp, size_t *rsp_len);
+
+#endif	/* _CASS_VF_NOTIF_H_ */
diff --git a/drivers/net/ethernet/hpe/ss1/cuc_cxi.h b/drivers/net/ethernet/hpe/ss1/cuc_cxi.h
new file mode 100644
index 000000000000..f295064407e9
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cuc_cxi.h
@@ -0,0 +1,370 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright 2021-2024 Hewlett Packard Enterprise Development LP */
+
+/* This file defines a set of commands and  request and response packet formats for
+ * communicating with the Cassini uC over USB, SMBus, or the HSN.
+ */
+
+#ifndef CUC_CXI_H
+#define CUC_CXI_H
+
+#define CUC_DATA_BYTES  253
+
+// I2C reads and writes to QSFP use a bus number of 0xFF because
+// // the actual bus number may not be known by the requester
+#define QSFP_I2C_BUS_REDIRECT      0xFF
+
+/**
+ * struct cuc_pkt - Cassini uC Packet Format
+ *
+ * This common packet format can be used to communicate with the uC across different
+ * physical interfaces (USB, SMBus, HSN). The SMBus interface is the lowest
+ * common denominator so this is pretty much modeled after the block read/write
+ * functions. We'll leave integrity checks to the physical interfaces.
+ */
+struct cuc_pkt {
+	u8 cmd;                   /* The command to be sent */
+	u8 count;                 /* The number of bytes to follow (including 'type') */
+	u8 type;                  /* Packet type */
+	u8 data[CUC_DATA_BYTES];  /* Data to be sent */
+} __packed;
+
+enum {
+	CUC_CMD_PING = 0,                       /* Perform a simple ping to the uC firmware */
+	CUC_CMD_BOARD_INFO = 1,                 /* Get board identification info */
+	CUC_CMD_I2C_READ = 2,                   /* Read an i2c device on the Cassini uC */
+	CUC_CMD_I2C_WRITE = 3,                  /* Write an i2c device on the Cassini uC */
+	CUC_CMD_GET_LOG = 12,                   /* Get a log message from the uC */
+	CUC_CMD_GET_FRU = 25,                   /* Get the FRU information for the device */
+	CUC_CMD_SET_FAN_PWM = 26,               /* Set fan to fixed speed w/ given PWM duty cycle */
+	CUC_CMD_GET_FAN_RPM = 27,               /* Get the latest fan RPM value */
+	CUC_CMD_GET_MAC = 29,                   /* Get MAC addresses */
+	CUC_CMD_QSFP_READ = 31,                 /* Do a QSFP/AOC I2C Read */
+	CUC_CMD_QSFP_WRITE = 32,                /* Do a QSFP/AOC I2C Write */
+	CUC_CMD_QSFP_RESET = 33,                /* Do a QSFP/AOC module reset */
+	CUC_CMD_GET_INTR = 34,                  /* Get Interrupt Status and Enable bits for a NIC */
+	CUC_CMD_CLEAR_ISR = 35,                 /* Clear Interrupt Status bits for a NIC */
+	CUC_CMD_UPDATE_IER = 36,                /* Set/Clear Interrupt Enable bits for a NIC */
+	CUC_CMD_PLDM = 39,                      /* Generic entry point for PLDM transaction */
+	CUC_CMD_FIRMWARE_UPDATE_START = 46,     /* Update firmware */
+	CUC_CMD_FIRMWARE_VERSION = 51,          /* Get the version of a firmware component */
+	CUC_CMD_FIRMWARE_UPDATE_DOWNLOAD = 52,  /* Download the firmware */
+	CUC_CMD_FIRMWARE_UPDATE_STATUS = 53,    /* Get status of firmware update */
+	CUC_CMD_RESET = 54,                     /* Reset the uC */
+	CUC_CMD_SET_LED = 58,                   /* Control the blink pattern (state) of an LED */
+	CUC_CMD_GET_NIC_ID = 60,                /* Get the NIC ID associated with this interface */
+	CUC_CMD_GET_TIMINGS = 61,               /* Get the power-on and initialization timings in usec */
+};
+
+enum {
+	CUC_TYPE_REQ,          /* Request packet */
+	CUC_TYPE_RSP_SUCCESS,  /* Success response packet */
+	CUC_TYPE_RSP_ERROR,    /* Error response packet */
+	CUC_TYPE_RSP_PLDM,     /* PLDM response packet */
+};
+
+struct cuc_error_rsp_data {
+	u8 error;  /* The POSIX errno that best describes the error */
+};
+
+enum {
+	CUC_BOARD_TYPE_UNKNOWN = -1,
+	CUC_BOARD_TYPE_SAWTOOTH = 0,
+	CUC_BOARD_TYPE_BRAZOS = 1,
+	CUC_BOARD_TYPE_WASHINGTON = 2,
+	CUC_BOARD_TYPE_KENNEBEC = 3,
+	CUC_BOARD_TYPE_PANGANI = 4,
+	CUC_BOARD_TYPE_SOUHEGAN = 5,
+};
+
+#define is_cas1_board_type(bt) ((bt == CUC_BOARD_TYPE_SAWTOOTH) || \
+								 (bt == CUC_BOARD_TYPE_BRAZOS))
+#define is_cas2_board_type(bt) ((bt == CUC_BOARD_TYPE_WASHINGTON) || \
+								 (bt == CUC_BOARD_TYPE_KENNEBEC) || \
+								 (bt == CUC_BOARD_TYPE_PANGANI) || \
+								 (bt == CUC_BOARD_TYPE_SOUHEGAN))
+struct cuc_board_info_rsp {
+	u8 board_type;
+	u8 board_rev;
+} __packed;
+
+struct cuc_i2c_read_req {
+	u8 bus;        /* The i2c bus number */
+	u8 addr;       /* The 7-bit i2c slave address */
+	u8 type;       /* Transaction type (current/random8/random16 read) */
+	u8 count;      /* Number of bytes to read/write */
+	u16 offset;    /* Offset in slave device to read from (if random) */
+} __attribute__((packed));
+
+struct cuc_i2c_write_req {
+	u8 bus;        /* The i2c bus number */
+	u8 addr;       /* The 7-bit i2c slave address */
+	u8 count;      /* Number of bytes to write */
+	u8 buf[0];
+} __attribute__((packed));
+
+struct cuc_set_fan_pwm_req_data {
+	/* PWM duty cycle value to set
+	 * 0- 100: Set to manual speed control
+	 * 255: Set to auto speed control
+	 */
+	u8 percent;
+} __packed;
+
+struct cuc_get_fan_rpm_rsp_data {
+	u32 rpm;     /* Measured fan speed in RPM */
+	u8 percent;  /* Current value of PWM duty cycle percent */
+	u8 is_auto;  /* Non-zero indicates auto speed control is active */
+} __packed;
+
+/* This is a special value that can be passed in the "nic" field of the
+ * cuc_mac_req_data structure to indicate to the uC that we want to get the
+ * MAC of the NIC that made the request
+ */
+#define CUC_MAC_THIS_NIC  0xFF
+
+struct cuc_mac_req_data {
+	u8 nic;  /* The NIC whose MAC addresses we want */
+} __packed;
+
+struct cuc_mac_rsp_data {
+	u8 nic;         /* The NIC */
+	u8 nic_mac[6];  /* The NIC MAC address */
+	u8 uc_mac[6];   /* The uC MAC address */
+} __packed;
+
+struct cuc_qsfp_read_req_data {
+	u8 nic;    /* Which NIC QSFP device to read */
+	u8 page;   /* Page select for reading */
+	u8 addr;   /* Start address for reading */
+	u8 count;  /* Number of bytes to read */
+} __packed;
+
+struct cuc_qsfp_read_rsp_data {
+	u8 data[0];
+} __packed;
+
+struct cuc_qsfp_write_req_data {
+	u8 nic;      /* Which NIC QSFP device to write */
+	u8 page;     /* Page select for writing */
+	u8 addr;     /* Start address for writing */
+	u8 count;    /* Number of bytes to write */
+	u8 data[];   /* Data to be written */
+} __packed;
+
+struct cuc_qsfp_reset_req_data {
+	u8 nic;  /* Which NIC QSFP device to reset */
+} __packed;
+
+/* These are Interrupt Masks for interrupt sources that cause UC_ATTENTION[1] to be set in
+ * C_PI_ERR_FLG. Some of these interrupt sources are related to the ASIC power-off condition, in
+ * which case it won't be possible to generate the UC_ATTENTION[1] interrupt, but the interrupt
+ * status and mask values are still valid and maintained via the CasuC/CUC interface.
+ */
+/* Bits 0 through 7 are reserved for uC and board-related interrupts */
+#define ATT1_UC_RESET                   BIT(0)
+#define ATT1_SENSOR_ALERT               BIT(1)
+#define ATT1_FAN_FAIL                   BIT(2)
+/* Bits 8 through 15 are reserved for asic-related interrupts */
+#define ATT1_ASIC_PWR_UP_DONE           BIT(8)
+#define ATT1_ASIC_PWR_FAIL              BIT(9)
+#define ATT1_ASIC_EPO_TEMPERATURE       BIT(10)
+/* Bits 16 through 23 are reserved for qsfp-related interrupts */
+#define ATT1_QSFP_POWER_FAIL            BIT(16)
+#define ATT1_QSFP_INSERT                BIT(17)
+#define ATT1_QSFP_REMOVE                BIT(18)
+#define ATT1_QSFP_INT                   BIT(19)
+#define ATT1_QSFP_EPO_TEMPERATURE       BIT(20)
+#define ATT1_QSFP_BAD_CABLE             BIT(21)
+/* Bits 24 through 31 are reserved for other future use */
+#define ATT1_ALL_INTERRUPTS             (0xFFFFFFFF)
+
+/* Most ATT1 interrupts are clearable by the host. Others are hardware-based and self-clearing */
+#define HOST_CLEARED_ATT1_INTERRUPTS  (ATT1_ALL_INTERRUPTS & ~(ATT1_QSFP_INT))
+
+struct cuc_get_intr_req_data {
+	u8 nic;  /* The NIC whose interrupts are being requested */
+} __packed;
+
+struct cuc_get_intr_rsp_data {
+	u32 isr;  /* Interrupt status register */
+	u32 ier;  /* Interrupt enable register */
+} __packed;
+
+struct cuc_clear_isr_req_data {
+	u8 nic;              /* The NIC whose interrupts are being cleared */
+	u32 isr_clear_bits;  /* Interrupt status bits to clear */
+} __packed;
+
+struct cuc_update_ier_req_data {
+	u8 nic;              /* The NIC whose interrupt enables are being updated */
+	u32 ier_set_bits;    /* Interrupt bits to enable */
+	u32 ier_clear_bits;  /* Interrupt bits to disable */
+} __packed;
+
+/* Two copies of the firmware are stored for each NIC, an active copy and a recovery copy */
+enum {
+	FW_SLOT_0,
+	FW_SLOT_ACTIVE = FW_SLOT_0,
+	FW_SLOT_1,
+	FW_SLOT_RECOVERY = FW_SLOT_1,
+	FW_SLOT_MAX
+};
+
+struct cuc_firmware_update_start_req {
+	u8 nic;    /* The NIC whose firmware is to be updated */
+	u32 size;  /* The size of the new firmware */
+	u8 slot;   /* The firmware slot to update */
+} __packed;
+
+/* The firmware (aka QSPI_BLOB) is composed of multiple, separately versioned components
+ * Not all of these targets are included in each blob. Blob contents are HW-specific. */
+enum casuc_fw_target {
+	FW_UC_APPLICATION,
+	FW_UC_BOOTLOADER,
+	FW_QSPI_BLOB,
+	FW_OPROM,
+	FW_CSR1,
+	FW_CSR2,
+	FW_SRDS,
+	FW_ISL68124_SAW,
+	FW_ISL68124_BRZ,
+	FW_IR38060_QSFP_BRZ,
+	FW_IR38060 = FW_IR38060_QSFP_BRZ,
+	/* Start of CAS2-specific entries */
+	FW_TDA38740_WAS,
+	FW_IR38060_WAS,
+	FW_IR38063_WAS,
+	FW_TDA38740_KEN,
+	FW_IR38060_KEN,
+	FW_IR38063_KEN,
+	FW_RESERVED, /* deprecated - FW_IR38060_QSFP_KEN */
+	FW_MFPGA_WAS,
+	FW_TDA38740_SOU,
+	FW_IR38063_0_SOU,
+	FW_IR38063_1_SOU,
+	FW_IR38063_2_SOU,
+	FW_MFPGA_SOU,
+	FW_NUM_ENTRIES
+};
+
+#define CAS1_BLOB_FW_TARGETS	FW_UC_APPLICATION, \
+								FW_UC_BOOTLOADER, \
+								FW_QSPI_BLOB, \
+								FW_OPROM, \
+								FW_CSR1, \
+								FW_CSR2, \
+								FW_SRDS, \
+								FW_ISL68124_SAW, \
+								FW_ISL68124_BRZ, \
+								FW_IR38060_QSFP_BRZ
+
+#define CAS2_BLOB_FW_TARGETS	FW_UC_APPLICATION, \
+								FW_UC_BOOTLOADER, \
+								FW_QSPI_BLOB, \
+								FW_OPROM, \
+								FW_CSR1, \
+								FW_CSR2, \
+								FW_SRDS, \
+								FW_TDA38740_WAS, \
+								FW_IR38060_WAS, \
+								FW_IR38063_WAS, \
+								FW_TDA38740_KEN, \
+								FW_IR38060_KEN, \
+								FW_IR38063_KEN, \
+								FW_MFPGA_WAS, \
+								FW_TDA38740_SOU, \
+								FW_IR38063_0_SOU, \
+								FW_IR38063_1_SOU, \
+								FW_IR38063_2_SOU, \
+								FW_MFPGA_SOU
+
+struct cuc_get_firmware_version_req {
+	u8 fw_target;   /* The component whose version is being requested */
+	u8 nic;         /* The NIC whose firmware version is being requested */
+	u8 from_flash;  /* 0 = Get the running version, 1 = Get the stored version */
+	u8 slot;        /* The slot to get the version from, when getting stored version */
+} __packed;
+
+struct cuc_firmware_update_download_req {
+	u8 data[0];
+} __packed;
+
+enum {
+	FWU_STATUS_STARTED,             /* The firmware update has been started */
+	FWU_STATUS_DOWNLOADING,         /* The firmware is being downloaded */
+	FWU_STATUS_VERIFYING_SIGNATURE, /* The firmware signature is being validated */
+	FWU_STATUS_VALIDATING_IMAGE,    /* The firmware is being validated */
+	FWU_STATUS_FLASHING,            /* The firmware is being flashed */
+	FWU_STATUS_VERIFYING_FLASH,     /* The firmware flash is being verified */
+	FWU_STATUS_IDLE = 0x80,
+	FWU_STATUS_SUCCESS,             /* The firmware update succeeded */
+	FWU_STATUS_FAILED,              /* The firmware update failed */
+	FWU_STATUS_FAILED_DOWNLOAD,     /* The firmware download failed */
+	FWU_STATUS_FAILED_BAD_SIGN,     /* The firmware signature was incorrect */
+	FWU_STATUS_FAILED_VALIDATION,   /* Failure validating image before flashing */
+	FWU_STATUS_FAILED_FLASH,        /* Failure during flash */
+	FWU_STATUS_FAILED_VERIFICATION, /* Failure verifying image in flash */
+	FWU_STATUS_FAILED_INVALID_SLOT, /* The firmware slot is not valid */
+};
+
+struct cuc_firmware_update_status_rsp {
+	u8 status;  /* Status of the firmware update state-machine */
+} __packed;
+
+enum casuc_leds {
+	LED_LINK_STATUS = 0,
+	LED_OCP_LINK_STATUS = 1,
+	LED_OCP_ACTIVITY_STATUS = 2,
+};
+
+/* GRN represents the nominal color and YEL represents the alternate color. Slow blinking
+ * frequency is 1Hz, fast is 2Hz.
+ */
+enum casuc_led_states {
+	LED_OFF = 0,
+	LED_ON_GRN = 1,
+	LED_SLOW_GRN = 2,
+	LED_FAST_GRN = 3,
+	LED_ON_YEL = 4,
+	LED_SLOW_YEL = 5,
+	LED_FAST_YEL = 6,
+	LED_SLOW_GRN_YEL = 7,
+	LED_FAST_GRN_YEL = 8,
+};
+
+struct cuc_set_led_req {
+	u8 nic;    /* The NIC whose LED state is to be set */
+	u8 led;    /* The LED whose state is to be set */
+	u8 state;  /* The state to set */
+} __packed;
+
+struct cuc_get_nic_id_rsp {
+	u8 nic;  /* The requested NIC ID */
+} __packed;
+
+enum cuc_timing_entries {
+    TIMING_UC_APPLICATION_STARTED,
+    TIMING_UC_PIN_INIT_COMPLETE,
+    TIMING_UC_FW_INIT_COMPLETE,
+    TIMING_EN_CLKS_UC_ASSERTED,
+    TIMING_12V_PG,
+    TIMING_PG_CASSINI_ASSERTED,
+    TIMING_RST_PON_NIC_N_DEASSERTED,
+    TIMING_VID_STABLE_ASSERTED,
+    TIMING_PERST_NIC_0_N_DEASSERTED,
+    TIMING_PERST_NIC_1_N_DEASSERTED,
+    TIMING_JTAG_TRST_N_DEASSERTED,
+    TIMING_UC_CASSINI_RDY_NIC_0,
+    TIMING_UC_CASSINI_RDY_NIC_1,
+    TIMING_PCIE_LINK_UP_NIC_0,
+    TIMING_PCIE_LINK_UP_NIC_1,
+    TIMING_UPTIME,
+    TIMING_NUM_ENTRIES
+};
+
+struct cuc_get_timings_rsp {
+    u64 entries_us[TIMING_NUM_ENTRIES];
+} __attribute__((packed));
+
+#endif /* CUC_CXI_H */
diff --git a/drivers/net/ethernet/hpe/ss1/cxi_ac_entry_list.h b/drivers/net/ethernet/hpe/ss1/cxi_ac_entry_list.h
new file mode 100644
index 000000000000..954ee81e92eb
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cxi_ac_entry_list.h
@@ -0,0 +1,20 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2020 Hewlett Packard Enterprise Development LP */
+
+#ifndef _CXI_AC_ENTRY_LIST_H_
+#define _CXI_AC_ENTRY_LIST_H_
+
+/* Access Control Entries */
+
+#define AC_ENTRY_GFP_OPTS            (GFP_KERNEL)
+
+#define AC_ENTRY_ID_MIN              (1)
+#define AC_ENTRY_ID_MAX              (INT_MAX)
+#define AC_ENTRY_ID_LIMITS           (XA_LIMIT(AC_ENTRY_ID_MIN, \
+					       AC_ENTRY_ID_MAX))
+#define AC_ENTRY_ID_XARRAY_FLAGS     (XA_FLAGS_ALLOC1)
+#define AC_ENTRY_UID_XARRAY_FLAGS    (0)
+#define AC_ENTRY_GID_XARRAY_FLAGS    (0)
+#define AC_ENTRY_NETNS_XARRAY_FLAGS  (0)
+
+#endif /* _CXI_AC_ENTRY_LIST_H_ */
diff --git a/drivers/net/ethernet/hpe/ss1/cxi_aux_dev.h b/drivers/net/ethernet/hpe/ss1/cxi_aux_dev.h
new file mode 100644
index 000000000000..1eaf47550f5b
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cxi_aux_dev.h
@@ -0,0 +1,14 @@
+
+/* SPDX-License-Identifier: GPL-2.0*/
+/* Copyright 2020-2024,2025 Hewlett Packard Enterprise Development LP */
+#ifndef __CXI_AUX_DEV_H__
+#define __CXI_AUX_DEV_H__
+#include <linux/device.h>
+#include <linux/pci.h>
+
+int cxi_ib_add_adev(struct pci_dev *pdev, struct cass_dev *hw, int cxi_num);
+void cxi_ib_remove_adev(struct cass_dev *hw);
+void cxi_release_aux_dev(struct device *dev);
+u8 *cxi_get_mac_addr(struct cxi_dev *dev);
+
+#endif
diff --git a/drivers/net/ethernet/hpe/ss1/cxi_config.h b/drivers/net/ethernet/hpe/ss1/cxi_config.h
new file mode 100644
index 000000000000..dd3bf6ea8df5
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cxi_config.h
@@ -0,0 +1,234 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _CXI_CONFIGFS_MGMT_H
+#define _CXI_CONFIGFS_MGMT_H
+
+#include <linux/hpe/cxi/cxi.h>
+#include <linux/configfs.h>
+#include <linux/slab.h>
+#include <linux/workqueue.h>
+#include <linux/ctype.h>
+
+#include "cass_core.h"
+
+#define PE_LE_MAX (C_LPE_STS_LIST_ENTRIES_ENTRIES / C_PE_COUNT)
+#define CONFIGFS_DIR_LEN 64
+#define CONFIGFS_RES_TYPE_LEN 16
+
+struct cxi_cfg_group_item {
+	struct config_group group;
+	struct cxi_cfg_rgroup_dir *rgp_dir;
+	struct cxi_cfg_rx_prof_dir *rx_prof_dir;
+	struct cxi_cfg_tx_prof_dir *tx_prof_dir;
+	char name[CONFIGFS_DIR_LEN];
+};
+
+struct cxi_cfg_rgroup_dir {
+	struct cxi_dev *cdev;
+	struct cxi_rgroup *rgroup;
+	struct config_group group;
+	char name[CONFIGFS_DIR_LEN];
+};
+
+struct cxi_cfg_rgroup {
+	struct cxi_dev *cdev;
+	struct cxi_rgroup *rgroup;
+	struct cxi_cfg_rgroup_attr *rgp_attr;
+	struct cxi_cfg_rgroup_res *rgp_res;
+	struct cxi_cfg_rgroup_state *rgp_state;
+	struct cxi_cfg_rgroup_ac_entry *ac_entry;
+	struct config_group group;
+	char name[CONFIGFS_DIR_LEN];
+};
+
+struct cxi_cfg_rgroup_ac_entry {
+	struct config_group group;
+	struct cxi_rgroup *rgroup;
+	enum cxi_ac_type ac_type;
+	union cxi_ac_data ac_data;
+	char name[CONFIGFS_DIR_LEN];
+};
+
+struct cxi_cfg_rgroup_ac_entry_sub {
+	struct config_group group;
+	struct config_item item;
+	struct cxi_rgroup *rgroup;
+	enum cxi_ac_type ac_type;
+	union cxi_ac_data ac_data;
+	unsigned int id;
+	char name[CONFIGFS_DIR_LEN];
+};
+
+struct cxi_cfg_rgroup_attr {
+	struct config_group group;
+	struct config_item item;
+	struct cxi_dev *cdev;
+	struct cxi_rgroup *rgroup;
+	char name[CONFIGFS_DIR_LEN];
+	int c_p_id;
+};
+
+struct cxi_cfg_rgroup_res {
+	struct cxi_dev *cdev;
+	struct cxi_rgroup *rgroup;
+	struct config_group group;
+	struct cxi_svc_desc *desc;
+	char name[CONFIGFS_DIR_LEN];
+};
+
+struct cxi_cfg_rgroup_state {
+	struct config_group group;
+	struct config_item item;
+	struct cxi_dev *cdev;
+	struct cxi_rgroup *rgroup;
+	char name[CONFIGFS_DIR_LEN];
+};
+
+struct cxi_cfg_rgroup_res_type {
+	struct config_group group;
+	struct config_item item;
+	struct config_group *parent_group;
+	struct cxi_rgroup *rgroup;
+	struct cxi_dev *cdev;
+	unsigned int id;
+	char name[CONFIGFS_DIR_LEN];
+	char res_type[CONFIGFS_RES_TYPE_LEN];
+	int reserved;
+	int max;
+	int in_use;
+};
+
+struct cxi_cfg_tx_prof_dir {
+	struct config_group group;
+	struct cxi_dev *cdev;
+	char name[CONFIGFS_DIR_LEN];
+};
+
+struct cxi_cfg_tx_prof_state {
+	struct config_group group;
+	struct cxi_dev *cdev;
+	struct cxi_tx_profile *tx_profile;
+	char name[CONFIGFS_DIR_LEN];
+};
+
+struct cxi_cfg_tx_prof_ac_entry {
+	struct config_group group;
+	struct cxi_dev *cdev;
+	struct cxi_tx_profile *tx_profile;
+	bool enable;
+	enum cxi_ac_type ac_type;
+	union cxi_ac_data ac_data;
+	unsigned int id;
+	char name[CONFIGFS_DIR_LEN];
+};
+
+struct cxi_cfg_tx_prof_ac_entry_sub {
+	struct config_group group;
+	struct cxi_dev *cdev;
+	struct cxi_tx_profile *tx_profile;
+	bool enable;
+	enum cxi_ac_type ac_type;
+	union cxi_ac_data ac_data;
+	unsigned int id;
+	char name[CONFIGFS_DIR_LEN];
+};
+
+struct cxi_cfg_tx_prof_attr {
+	struct config_group group;
+	struct cxi_dev *cdev;
+	struct cxi_tx_profile *tx_profile;
+	u16 match;
+	u16 ignore;
+	char tx_attr_name[CXI_VNI_NAME_LEN];
+	char name[CONFIGFS_DIR_LEN];
+};
+
+struct cxi_cfg_tx_prof_tc {
+	struct config_group group;
+	struct cxi_dev *cdev;
+	struct cxi_tx_profile *tx_profile;
+	bool dedicated;
+	bool low_latency;
+	bool bulk_data;
+	bool best_effort;
+	bool eth;
+	char name[CONFIGFS_DIR_LEN];
+};
+
+struct cxi_cfg_tx_prof {
+	struct config_group group;
+	struct cxi_dev *cdev;
+	unsigned int id;
+	struct cxi_tx_profile *tx_profile;
+	struct cxi_cfg_tx_prof_ac_entry *tx_prof_ac_entry;
+	struct cxi_cfg_tx_prof_attr *tx_prof_attr;
+	struct cxi_cfg_tx_prof_state *tx_prof_state;
+	struct cxi_cfg_tx_prof_tc *tx_prof_tc;
+	char name[CONFIGFS_DIR_LEN];
+};
+
+struct cxi_cfg_rx_prof_dir {
+	struct config_group group;
+	struct cxi_dev *cdev;
+	char name[CONFIGFS_DIR_LEN];
+};
+
+struct cxi_cfg_rx_prof {
+	struct config_group group;
+	struct cxi_dev *cdev;
+	unsigned int id;
+	struct cxi_rx_profile *rx_profile;
+	struct cxi_cfg_rx_prof_ac_entry *rx_prof_ac_entry;
+	struct cxi_cfg_rx_prof_attr *rx_prof_attr;
+	struct cxi_cfg_rx_prof_state *rx_prof_state;
+	char name[CONFIGFS_DIR_LEN];
+};
+
+struct cxi_cfg_rx_prof_state {
+	struct config_group group;
+	struct cxi_dev *cdev;
+	struct cxi_rx_profile *rx_profile;
+	char name[CONFIGFS_DIR_LEN];
+};
+
+struct cxi_cfg_rx_prof_ac_entry {
+	struct config_group group;
+	struct cxi_dev *cdev;
+	struct cxi_rx_profile *rx_profile;
+	bool enable;
+	enum cxi_ac_type ac_type;
+	union cxi_ac_data ac_data;
+	unsigned int id;
+	char name[CONFIGFS_DIR_LEN];
+};
+
+struct cxi_cfg_rx_prof_ac_entry_sub {
+	struct config_group group;
+	struct cxi_dev *cdev;
+	struct cxi_rx_profile *rx_profile;
+	bool enable;
+	enum cxi_ac_type ac_type;
+	union cxi_ac_data ac_data;
+	unsigned int id;
+	char name[CONFIGFS_DIR_LEN];
+};
+
+struct cxi_cfg_rx_prof_attr {
+	struct config_group group;
+	struct cxi_dev *cdev;
+	struct cxi_rx_profile *rx_profile;
+	u16 match;
+	u16 ignore;
+	char rx_attr_name[CXI_VNI_NAME_LEN];
+	char name[CONFIGFS_DIR_LEN];
+};
+
+int cxi_configfs_subsys_init(void);
+void cxi_configfs_cleanup(struct cass_dev *hw);
+int cxi_configfs_device_init(struct cass_dev *hw);
+void cxi_configfs_fini(void);
+void cxi_configfs_exit(void);
+
+#endif /* _CXI_CONFIGFS_MGMT_H */
diff --git a/drivers/net/ethernet/hpe/ss1/cxi_configuration.h b/drivers/net/ethernet/hpe/ss1/cxi_configuration.h
new file mode 100644
index 000000000000..4458bb6078a8
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cxi_configuration.h
@@ -0,0 +1,332 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#ifndef _CXI_CONFIGURATION_H_
+#define _CXI_CONFIGURATION_H_
+
+/* Parameter for use with the 'by_user' retrieve functions */
+#define CXI_AC_ANY (CXI_AC_UID | CXI_AC_GID | CXI_AC_OPEN | CXI_AC_NETNS)
+
+#define AC_TYPE(type) \
+	ac_type == CXI_AC_UID ? "uid" : \
+	ac_type == CXI_AC_GID ? "gid" : \
+	ac_type == CXI_AC_NETNS ? "netns" : \
+	ac_type == CXI_AC_OPEN ? "open" : ""
+
+void cxi_ac_entry_list_init(struct cxi_ac_entry_list *list);
+
+void cxi_ac_entry_list_purge(struct cxi_ac_entry_list *list);
+
+void cxi_ac_entry_list_destroy(struct cxi_ac_entry_list *list);
+
+bool cxi_ac_entry_list_empty(struct cxi_ac_entry_list *list);
+
+int cxi_ac_entry_list_insert(struct cxi_ac_entry_list *list,
+			     enum cxi_ac_type ac_type,
+			     const union cxi_ac_data *ac_data,
+			     unsigned int *id);
+
+int cxi_ac_entry_list_delete(struct cxi_ac_entry_list *list,
+			     unsigned int id);
+
+int cxi_ac_entry_list_retrieve_by_id(struct cxi_ac_entry_list *list,
+				     unsigned int id,
+				     enum cxi_ac_type *ac_type,
+				     union cxi_ac_data *data);
+
+int cxi_ac_entry_list_retrieve_by_data(struct cxi_ac_entry_list *list,
+				       enum cxi_ac_type ac_type,
+				       const union cxi_ac_data *ac_data,
+				       unsigned int *id);
+
+int cxi_ac_entry_list_retrieve_by_user(struct cxi_ac_entry_list *list,
+				       uid_t uid,
+				       gid_t gid,
+				       unsigned int netns,
+				       cxi_ac_typeset_t desired_types,
+				       unsigned int *id);
+
+int cxi_ac_entry_list_retrieve_netns(struct cxi_ac_entry_list *list,
+				     union cxi_ac_data *ac_data);
+
+int cxi_ac_entry_list_get_ids(struct cxi_ac_entry_list *list,
+			      size_t max_ids,
+			      unsigned int *ids,
+			      size_t *num_ids);
+
+/* Common list for RX and TX Profiles */
+struct cxi_rxtx_profile_list {
+	struct xarray    xarray;
+	struct xa_limit  *limits;
+	gfp_t            flags;
+	gfp_t            gfp_opts;
+};
+
+int tx_profile_find_inc_refcount(struct cxi_dev *dev,
+				 unsigned int tx_profile_id,
+				 struct cxi_tx_profile **tx_profile);
+void cxi_rx_profile_remove_ac_entries(struct cxi_rx_profile *rx_profile);
+
+int cxi_rx_profile_release(struct cxi_dev *dev,
+			   unsigned int rx_profile_id);
+int cxi_rx_profile_revoke(struct cxi_dev *dev,
+			  unsigned int rx_profile_id);
+
+struct cxi_rx_profile *cxi_dev_find_rx_profile(struct cxi_dev *dev,
+					       u16 vni);
+struct cxi_rx_profile *cxi_dev_get_rx_profile(struct cxi_dev *dev,
+					      unsigned int vni);
+void cxi_rx_profile_update_pid_table(struct cxi_rx_profile *rx_profile, int pid,
+				     int count, bool set);
+void cxi_rx_profile_andnot_pid_table(struct cxi_reserved_pids *pids,
+				     int len);
+int cxi_rx_profile_alloc_pid(struct cxi_lni_priv *lni_priv,
+			     struct cxi_rx_profile *rx_profile,
+			     int pid, int vni, int count, bool reserve);
+
+int cxi_rx_profile_remove_ac_entry(struct cxi_rx_profile *rx_profile,
+				   unsigned int ac_entry_id);
+int cxi_rx_profile_get_ac_entry_ids(struct cxi_rx_profile *rx_profile,
+				    size_t max_ids,
+				    unsigned int *ac_entry_ids,
+				    size_t *num_ids);
+
+int cxi_rx_profile_get_ac_entry_data(struct cxi_rx_profile *rx_profile,
+				     unsigned int ac_entry_id,
+				     enum cxi_ac_type *ac_type,
+				     union cxi_ac_data *ac_data);
+int cxi_rx_profile_get_ac_entry_id_by_data(struct cxi_rx_profile *rx_profile,
+					   enum cxi_ac_type ac_type,
+					   const union cxi_ac_data *ac_data,
+					   unsigned int *ac_entry_id);
+int cxi_rx_profile_get_ac_entry_id_by_user(struct cxi_rx_profile *rx_profile,
+					   uid_t uid,
+					   gid_t gid,
+					   unsigned int netns,
+					   cxi_ac_typeset_t desired_types,
+					   unsigned int *ac_entry_id);
+void cxi_rx_profile_print(struct seq_file *s);
+
+void cxi_dev_init_eth_tx_profile(struct cass_dev *hw);
+void cxi_eth_tx_profile_cleanup(struct cass_dev *hw);
+struct cxi_tx_profile *cxi_dev_get_eth_tx_profile(struct cxi_dev *dev);
+
+struct cxi_tx_profile *cxi_dev_find_tx_profile(struct cxi_dev *dev,
+					       u16 vni);
+bool cxi_tx_profile_valid_tc(struct cxi_tx_profile *tx_profile,
+			     unsigned int tc);
+
+int cxi_tx_profile_release(struct cxi_dev *dev,
+			   unsigned int tx_profile_id);
+int cxi_tx_profile_revoke(struct cxi_dev *dev,
+			  unsigned int tx_profile_id);
+
+int cxi_tx_profile_get_info(struct cxi_dev *dev,
+			    struct cxi_tx_profile *tx_profile,
+			    struct cxi_tx_attr *tx_attr,
+			    struct cxi_rxtx_profile_state *state);
+
+int cxi_tx_profile_remove_ac_entry(struct cxi_tx_profile *tx_profile,
+				   unsigned int ac_entry_id);
+int cxi_tx_profile_get_ac_entry_ids(struct cxi_tx_profile *tx_profile,
+				    size_t max_ids,
+				    unsigned int *ac_entry_ids,
+				    size_t *num_ids);
+
+int cxi_tx_profile_get_ac_entry_data(struct cxi_tx_profile *tx_profile,
+				     unsigned int ac_entry_id,
+				     enum cxi_ac_type *ac_type,
+				     union cxi_ac_data *ac_data);
+int cxi_tx_profile_get_ac_entry_id_by_data(struct cxi_tx_profile *tx_profile,
+					   enum cxi_ac_type ac_type,
+					   const union cxi_ac_data *ac_data,
+					   unsigned int *ac_entry_id);
+int cxi_tx_profile_get_ac_entry_id_by_user(struct cxi_tx_profile *tx_profile,
+					   uid_t uid,
+					   gid_t gid,
+					   unsigned int netns,
+					   cxi_ac_typeset_t desired_types,
+					   unsigned int *ac_entry_id);
+void cxi_tx_profile_print(struct seq_file *s);
+
+enum cxi_profile_type {
+	CXI_PROF_RX = 1,
+	CXI_PROF_TX
+};
+
+bool cxi_valid_vni(struct cxi_dev *dev, enum cxi_profile_type type,
+		   unsigned int vni);
+
+/* Resource Group Entries */
+
+struct cxi_rgroup;
+
+struct cxi_rgroup_list {
+	struct xarray    xarray;
+};
+
+static const char * const cxi_resource_type_strs[] = {
+	[CXI_RESOURCE_PTLTE] = "ptlte",
+	[CXI_RESOURCE_TXQ] = "txq",
+	[CXI_RESOURCE_TGQ] = "tgq",
+	[CXI_RESOURCE_EQ] = "eq",
+	[CXI_RESOURCE_CT] = "ct",
+	[CXI_RESOURCE_PE0_LE] = "pe0_le",
+	[CXI_RESOURCE_PE1_LE] = "pe1_le",
+	[CXI_RESOURCE_PE2_LE] = "pe2_le",
+	[CXI_RESOURCE_PE3_LE] = "pe3_le",
+	[CXI_RESOURCE_TLE] = "tle",
+	[CXI_RESOURCE_AC] = "ac",
+};
+
+static inline
+const char *cxi_resource_type_to_str(enum cxi_resource_type type)
+{
+	if (type >= CXI_RESOURCE_PTLTE && type < CXI_RESOURCE_MAX)
+		return cxi_resource_type_strs[type];
+
+	return "(invalid)";
+}
+
+struct cxi_resource_use {
+	size_t     reserved;
+	size_t     shared;
+	size_t     shared_use;
+	size_t     in_use;
+	size_t     max;
+};
+
+struct cxi_resource_entry {
+	struct cxi_rgroup          *rgroup;
+	enum cxi_resource_type     type;
+	struct cxi_resource_limits limits;
+};
+
+struct cxi_resource_entry_list {
+	struct cxi_rgroup   *rgroup;
+	struct xarray       xarray;
+};
+
+struct cxi_rgroup_pools {
+	int            le_pool_id[C_PE_COUNT];
+	int            tle_pool_id;
+};
+
+/* Resource Group */
+
+struct cxi_rgroup_attr;
+struct cxi_rgroup_state;
+
+bool cxi_rgroup_valid_user(struct cxi_rgroup *rgroup);
+
+void cxi_dev_lock_rgroup_list(struct cass_dev *hw);
+void cxi_dev_unlock_rgroup_list(struct cass_dev *hw);
+
+void cxi_rgroup_get_info(struct cxi_rgroup *rgroup,
+			 struct cxi_rgroup_attr *attr,
+			struct cxi_rgroup_state *state);
+
+int cxi_rgroup_delete_resource(struct cxi_rgroup *rgroup,
+			       enum cxi_resource_type resource_type);
+
+int cxi_rgroup_get_resource(struct cxi_rgroup *rgroup,
+			    enum cxi_resource_type resource_type,
+			    struct cxi_resource_limits *limits);
+
+int cxi_rgroup_get_resource_entry(struct cxi_rgroup *rgroup,
+				  enum cxi_resource_type type,
+				  struct cxi_resource_entry **entry);
+
+int cxi_rgroup_get_resource_types(struct cxi_rgroup *rgroup,
+				  size_t max_resources,
+				  enum cxi_resource_type *resource_types,
+				  size_t *num_resources);
+
+int cxi_rgroup_alloc_resource(struct cxi_rgroup *rgroup,
+			      enum cxi_resource_type type);
+void cxi_rgroup_free_resource(struct cxi_rgroup *rgroup,
+			      enum cxi_resource_type type);
+
+int cxi_rgroup_delete_ac_entry(struct cxi_rgroup *rgroup,
+			       unsigned int ac_entry_id);
+
+int cxi_rgroup_get_ac_entry_ids(struct cxi_rgroup *rgroup,
+				size_t max_ids,
+				unsigned int *ids,
+				size_t *num_ids);
+
+int cxi_rgroup_get_ac_entry_data(struct cxi_rgroup *rgroup,
+				 unsigned int ac_entry_id,
+				 enum cxi_ac_type *type,
+				 union cxi_ac_data *ac_data);
+
+int cxi_rgroup_get_ac_entry_id_by_data(struct cxi_rgroup *rgroup,
+				       enum cxi_ac_type type,
+				       const union cxi_ac_data *ac_data,
+				       unsigned int *ac_entry_id);
+
+int cxi_rgroup_get_ac_entry_by_user(struct cxi_rgroup *rgroup,
+				    uid_t uid,
+				    gid_t gid,
+				    unsigned int netns,
+				    cxi_ac_typeset_t desired_types,
+				    unsigned int *ac_entry_id);
+
+void cxi_rgroup_inc_refcount(struct cxi_rgroup *rgroup);
+
+void cxi_rgroup_print_ac_entry_info(struct cxi_rgroup *rgroup,
+				    struct seq_file *s);
+
+int cxi_dev_find_rgroup_inc_refcount(struct cxi_dev *dev,
+				     unsigned int id,
+				     struct cxi_rgroup **rgroup);
+
+unsigned int cxi_dev_get_rgroup_count(struct cxi_dev *dev);
+
+int cxi_dev_get_rgroup_ids(struct cxi_dev *dev,
+			   size_t max_ids,
+			   unsigned int *rgroup_ids,
+			   size_t *num_ids);
+
+int cxi_dev_rgroup_get_resource(struct cxi_dev *dev,
+				unsigned int rgroup_id,
+				enum cxi_resource_type resource_type,
+				struct cxi_resource_limits *limits);
+
+int cxi_dev_rgroup_get_resource_types(struct cxi_dev *dev,
+				      unsigned int rgroup_id,
+				      size_t max_types,
+				      enum cxi_resource_type *resource_types,
+				      size_t *num_types);
+
+int cxi_dev_rgroup_delete_ac_entry(struct cxi_dev *dev,
+				   unsigned int rgroup_id,
+				   unsigned int ac_entry_id);
+
+int cxi_dev_rgroup_get_ac_entry_ids(struct cxi_dev *dev,
+				    unsigned int rgroup_id,
+				    size_t max_ids,
+				    unsigned int *ac_entry_ids,
+				    size_t *num_ids);
+
+int cxi_dev_rgroup_get_ac_entry_data(struct cxi_dev *dev,
+				     unsigned int rgroup_id,
+				     unsigned int ac_entry_id,
+				     enum cxi_ac_type *ac_type,
+				     union cxi_ac_data *ac_data);
+
+int cxi_dev_rgroup_get_ac_entry_id_by_data(struct cxi_dev *dev,
+					   unsigned int rgroup_id,
+					   enum cxi_ac_type ac_type,
+					   union cxi_ac_data *ac_data,
+					   unsigned int *ac_entry_id);
+
+int cxi_dev_rgroup_get_ac_entry_id_by_user(struct cxi_dev *dev,
+					   unsigned int rgroup_id,
+					   uid_t uid,
+					   gid_t gid,
+					   unsigned int netns,
+					   cxi_ac_typeset_t desired_types,
+					   unsigned int *ac_entry_id);
+
+#endif /* _CXI_CONFIGURATION_H_ */
diff --git a/drivers/net/ethernet/hpe/ss1/cxi_core.h b/drivers/net/ethernet/hpe/ss1/cxi_core.h
new file mode 100644
index 000000000000..471cc9b3b393
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cxi_core.h
@@ -0,0 +1,434 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2022-2026 Hewlett Packard Enterprise Development LP */
+
+#ifndef _CXI_CORE_H
+#define _CXI_CORE_H
+
+#include <linux/device.h>
+#include <linux/types.h>
+#include <linux/hmm.h>
+#include <linux/hpe/cxi/cxi.h>
+#include <linux/refcount.h>
+#include <linux/mmu_notifier.h>
+
+#define DFA_EP_BITS 17
+#define MAX_PID_BITS 9
+#define MIN_PID_BITS (MAX_PID_BITS - 3)
+#define XSTR(x) STR(x)
+#define STR(x) #x
+
+#define HAVE_GET_SINGLETON
+
+#define HAVE_IOVA_INIT_RCACHES
+
+#define dev_emerg_always(dev, fmt, ...)	  dev_emerg(dev, fmt, ##__VA_ARGS__)
+#define dev_alert_always(dev, fmt, ...)	  dev_alert(dev, fmt, ##__VA_ARGS__)
+#define dev_crit_always(dev, fmt, ...)	  dev_crit(dev, fmt, ##__VA_ARGS__)
+#define dev_err_always(dev, fmt, ...)	  dev_err(dev, fmt, ##__VA_ARGS__)
+#define dev_warn_always(dev, fmt, ...)	  dev_warn(dev, fmt, ##__VA_ARGS__)
+#define dev_notice_always(dev, fmt, ...)  dev_notice(dev, fmt, ##__VA_ARGS__)
+#define dev_info_always(dev, fmt, ...)	  dev_info(dev, fmt, ##__VA_ARGS__)
+#define dev_dbg_always(dev, fmt, ...)	  dev_dbg(dev, fmt, ##__VA_ARGS__)
+
+/*
+ * This is the main or core cassini cxi logging macro.	It is not intended to
+ * be used directly anywhere except the cxidev_*() macros.  The whole purpose
+ * behind this logging is to use '"%s: " fmt' and '"%s/%s: " fmt' to take
+ * advantage of C string constant concatenation to add common information to
+ * the logged cassini cxi messages.
+ */
+#define _cxi_log(freq, severity, cdev, fmt, ...)			\
+	dev_##severity##_##freq(&(cdev)->pdev->dev,		\
+				"%s[%s] " fmt,				\
+				(cdev)->name, (cdev)->eth_name,		\
+				##__VA_ARGS__)
+
+/*
+ * the cassini log equivalent of dev_*() log
+ */
+#define cxidev_emerg(cdev, fmt, ...)\
+		_cxi_log(always, emerg, cdev, fmt, ##__VA_ARGS__)
+#define cxidev_alert(cdev, fmt, ...)\
+		_cxi_log(always, alert, cdev, fmt, ##__VA_ARGS__)
+#define cxidev_crit(cdev, fmt, ...)\
+		_cxi_log(always, crit, cdev, fmt, ##__VA_ARGS__)
+#define cxidev_err(cdev, fmt, ...)\
+		_cxi_log(always, err, cdev, fmt, ##__VA_ARGS__)
+#define cxidev_warn(cdev, fmt, ...)\
+		_cxi_log(always, warn, cdev, fmt, ##__VA_ARGS__)
+#define cxidev_notice(cdev, fmt, ...)\
+		_cxi_log(always, notice, cdev, fmt, ##__VA_ARGS__)
+#define cxidev_info(cdev, fmt, ...)\
+		_cxi_log(always, info, cdev, fmt, ##__VA_ARGS__)
+#define cxidev_dbg(cdev, fmt, ...)\
+		_cxi_log(always, dbg, cdev, fmt, ##__VA_ARGS__)
+
+#define cxidev_WARN(cdev, fmt, ...)\
+		dev_WARN(&(cdev)->cdev.pdev->dev,			\
+			 "%s[%s]: " fmt, (cdev)->cdev.name,	\
+			 (cdev)->cdev.eth_name,			\
+			 ##__VA_ARGS__)
+
+/*
+ * the cassini log equivalent of dev_*_once()
+ */
+#define cxidev_emerg_once(cdev, fmt, ...)\
+		_cxi_log(once, emerg, cdev, fmt, ##__VA_ARGS__)
+#define cxidev_alert_once(cdev, fmt, ...)\
+		_cxi_log(once, alert, cdev, fmt, ##__VA_ARGS__)
+#define cxidev_crit_once(cdev, fmt, ...)\
+		_cxi_log(once, crit, cdev, fmt, ##__VA_ARGS__)
+#define cxidev_err_once(cdev, fmt, ...)\
+		_cxi_log(once, err, cdev, fmt, ##__VA_ARGS__)
+#define cxidev_warn_once(cdev, fmt, ...)\
+		_cxi_log(once, warn, cdev, fmt, ##__VA_ARGS__)
+#define cxidev_notice_once(cdev, fmt, ...)\
+		_cxi_log(once, notice, cdev, fmt, ##__VA_ARGS__)
+#define cxidev_info_once(cdev, fmt, ...)\
+		_cxi_log(once, info, cdev, fmt, ##__VA_ARGS__)
+#define cxidev_dbg_once(cdev, fmt, ...)\
+		_cxi_log(once, dbg, cdev, fmt, ##__VA_ARGS__)
+
+#define cxidev_WARN_ONCE(cdev, condition, fmt, ...)\
+		dev_WARN_ONCE(&(cdev)->pdev->dev, (condition),	\
+			      "%s[%s]: " fmt, (cdev)->name,		\
+			      (cdev)->eth_name,			\
+			      ##__VA_ARGS__)
+
+/*
+ * the cassini log equivalent of dev_*_ratelimited()
+ */
+#define cxidev_emerg_ratelimited(cdev, fmt, ...)\
+		_cxi_log(ratelimited, emerg, cdev, fmt, ##__VA_ARGS__)
+#define cxidev_alert_ratelimited(cdev, fmt, ...)\
+		_cxi_log(ratelimited, alert, cdev, fmt, ##__VA_ARGS__)
+#define cxidev_crit_ratelimited(cdev, fmt, ...)\
+		_cxi_log(ratelimited, crit, cdev, fmt, ##__VA_ARGS__)
+#define cxidev_err_ratelimited(cdev, fmt, ...)\
+		_cxi_log(ratelimited, err, cdev, fmt, ##__VA_ARGS__)
+#define cxidev_warn_ratelimited(cdev, fmt, ...)\
+		_cxi_log(ratelimited, warn, cdev, fmt, ##__VA_ARGS__)
+#define cxidev_notice_ratelimited(cdev, fmt, ...)\
+		_cxi_log(ratelimited, notice, cdev, fmt, ##__VA_ARGS__)
+#define cxidev_info_ratelimited(cdev, fmt, ...)\
+		_cxi_log(ratelimited, info, cdev, fmt, ##__VA_ARGS__)
+#define cxidev_dbg_ratelimited(cdev, fmt, ...)\
+		_cxi_log(ratelimited, dbg, cdev, fmt, ##__VA_ARGS__)
+
+extern unsigned int pid_bits;
+extern unsigned int system_type_identifier;
+extern unsigned int min_free_shift;
+extern unsigned int vni_matching;
+extern unsigned int tg_threshold[4];
+extern int untagged_eth_pcp;
+extern bool switch_connected;
+
+extern atomic_t cxi_num;
+extern struct class cxi_class;
+extern struct dentry *cxi_debug_dir;
+
+extern int hw_register(void);
+extern void hw_unregister(void);
+extern int cxi_configfs_subsys_init(void);
+extern void cxi_configfs_exit(void);
+
+void cxi_add_device(struct cxi_dev *cdev);
+void cxi_remove_device(struct cxi_dev *cdev);
+void cxi_send_async_event(struct cxi_dev *cdev, enum cxi_async_event event);
+void cxi_apply_for_all(void (*callback)(struct cxi_dev *dev, void *p),
+		       void *p);
+
+#define CXI_DEFAULT_LNIS_PER_RGID 1
+
+/* Service */
+struct cxi_svc_priv {
+	struct list_head list;
+	struct cxi_svc_desc svc_desc;
+	struct cxi_rgroup *rgroup;
+	struct cxi_rx_profile *rx_profile[CXI_SVC_MAX_VNIS];
+	struct cxi_tx_profile *tx_profile[CXI_SVC_MAX_VNIS];
+};
+
+/* Logical Network Interface */
+struct cxi_lni_priv {
+	struct cxi_dev *dev;
+	DECLARE_BITMAP(leased_pids, 1 << MAX_PID_BITS);
+	/* User LNI object. */
+	struct cxi_lni lni;
+
+	struct list_head list;
+	/* Users of this LNI. */
+	refcount_t refcount;
+
+	/* Service associated with this LNI. */
+	struct cxi_rgroup *rgroup;
+
+	/* Keep track of associated resources. TODO: keep as that may
+	 * help debugging, but should be removed eventually.
+	 */
+	struct list_head domain_list;
+	struct list_head eq_list;
+	struct list_head cq_list;
+	struct list_head pt_list;
+	struct list_head ac_list;
+	struct list_head ct_list;
+	struct list_head reserved_pids;
+	spinlock_t res_lock;
+	struct mutex ac_list_mutex;
+
+	struct ida lac_table;
+	atomic_t lpe_pe_num;
+
+	struct dentry *debug_dir;
+	struct dentry *cq_dir;
+	struct dentry *pt_dir;
+	struct dentry *eq_dir;
+	struct dentry *ct_dir;
+	struct dentry *ac_dir;
+
+	/* Pending resources to cleanup. Use res_lock to serialize. */
+	struct list_head pt_cleanups_list;
+	struct list_head cq_cleanups_list;
+	struct list_head eq_cleanups_list;
+	struct list_head ct_cleanups_list;
+
+	u32 pid;
+
+	/* Physical AC associated with the LNI. Should be ATU_PHYS_AC for LNIs
+	 * belonging to the PF, or the VF's physical AC for VFs.
+	 */
+	unsigned int phys_ac;
+
+	/* If this LNI belongs to a VF, then vf_en will be true and the VF number
+	 * will be in vf_num.
+	 */
+	bool is_vf;
+	u8 vf_num;
+};
+
+#include "cass_p2p.h" /* Pick up cxi_p2p_fini(), needs to be after the
+		       * definition of cxi_lni_priv */
+struct cass_vni;
+
+struct cxi_reserved_pids {
+	struct list_head entry;
+	struct cxi_rx_profile *rx_profile;
+	DECLARE_BITMAP(table, 1 << MAX_PID_BITS);
+};
+
+struct ct_wb_desc {
+	struct page *page;
+	dma_addr_t wb_dma_addr;
+	struct cxi_md_priv *md_priv;
+	bool is_map_page;
+};
+
+struct cxi_ct_priv {
+	struct list_head entry;
+	struct cxi_lni_priv *lni_priv;
+	struct dentry *debug_dir;
+	struct dentry *lni_dir;
+	struct ct_wb_desc wb_desc;
+	struct cxi_ct ct;
+	bool is_user;
+
+	/* Doorbell MMIO address */
+	void __iomem *ct_mmio;
+};
+
+struct cxi_domain_priv {
+	struct cxi_domain domain;
+	struct cxi_lni_priv *lni_priv;
+	struct list_head list;
+	struct dentry *debug_dir;
+	struct rb_node node;	/* attach to domain_tree */
+	struct cxi_rx_profile *rx_profile;
+
+	/* Users of this domain */
+	refcount_t refcount;
+};
+
+struct cxi_md_priv {
+	struct cxi_lni_priv *lni_priv;
+	struct device *device;
+	struct cxi_md md;
+	struct page **pages;
+	struct sg_table *sgt;
+	u32 flags;
+
+	struct list_head md_entry; /* entry in a CAC md_list */
+	struct cass_ac *cac;
+
+	struct sg_table *dmabuf_sgt;
+
+	/* DMA buffer file descriptor. This is passed in by user-space. */
+	int dmabuf_fd;
+
+	/* Offset into the DMA buffer where PFN mapping should begin. */
+	unsigned long dmabuf_offset;
+
+	/* User request DMA buffer len. This should not be aligned. */
+	unsigned long dmabuf_length;
+
+	struct dma_buf *dmabuf;
+	struct dma_buf_attachment *dmabuf_attach;
+
+	/* Users of this MD */
+	refcount_t refcount;
+
+	/* Original length of the MD */
+	size_t olen;
+
+	/* Need to lock when initially mirroring page tables */
+	bool need_lock;
+	/* SG table is owned by an external user (e.g. kfabric) */
+	bool external_sgt_owner;
+	struct mmu_interval_notifier mn_sub;
+	/* GPU direct info */
+	void *p2p_info;
+	bool cleanup_done;
+};
+
+struct cxi_cp_priv {
+	struct cxi_dev *dev;
+	struct cxi_cp cp;
+	struct cass_cp *cass_cp;
+	refcount_t refcount;
+	unsigned int rgid;
+	unsigned int lni_id;
+};
+
+/* EQ buffer description */
+struct eq_buf_desc {
+	const struct cxi_md *md; /* Virtual buffer MD. */
+	void *events;
+	size_t events_len;
+
+	struct page **pages;
+
+	dma_addr_t dma_addr; /* DMA buffer address. */
+};
+
+struct cxi_eq_priv {
+	struct cxi_lni_priv *lni_priv;
+	struct list_head list;
+	struct dentry *debug_file;
+	struct dentry *lni_dir;
+
+	bool reused;
+
+	/* Users of this EQ */
+	refcount_t refcount;
+
+	/* EQ buffer description */
+	struct eq_buf_desc active;
+
+	/* Doorbell MMIO address */
+	void __iomem *eq_mmio;
+
+	/* Current EQ descriptor state */
+	union c_ee_cfg_eq_descriptor cfg;
+
+	/* Copy of the creation attributes */
+	struct cxi_eq_attr attr;
+
+	/* Public event queue */
+	struct cxi_eq eq;
+
+	/* Interrupt vectors, and callbacks */
+	struct cass_irq *event_msi_irq;
+	void (*event_cb)(void *context);
+	void *event_cb_data;
+	struct notifier_block event_nb;
+
+	struct cass_irq *status_msi_irq;
+	void (*status_cb)(void *context);
+	void *status_cb_data;
+	struct notifier_block status_nb;
+
+	/* Number of slots in queue. */
+	size_t queue_size;
+
+	/* Resize buffer attributes */
+	struct mutex resize_mutex;
+	bool resized;
+	struct eq_buf_desc resize;
+};
+
+struct cxi_cq_priv {
+	struct cxi_lni_priv *lni_priv;
+	struct cxi_cq cass_cq;
+
+	/* DMA mapped CQ */
+	size_t cmds_len;
+	size_t cmds_order;
+	struct page **pages;
+	struct page *cmds_pages;
+	void *cmds;
+	dma_addr_t cmds_dma_addr;
+
+	/* Doorbell MMIO address */
+	void __iomem *cq_mmio;
+
+	u32 flags;
+	struct cxi_md_priv *md_priv;
+
+	struct list_head list;
+	struct dentry *debug_dir;
+	struct dentry *lni_dir;
+
+	/* EQ for error reporting. May be NULL. */
+	struct cxi_eq_priv *eq;
+};
+
+struct cxi_pte_priv {
+	struct cxi_lni_priv *lni_priv;
+	struct list_head list;
+	struct dentry *debug_dir;
+	struct dentry *lni_dir;
+
+	struct cxi_pte pte;
+
+	struct cxi_eq_priv *eq;
+
+	/* Users of this portal table entries. */
+	refcount_t refcount;
+
+	/* Pte is flow control enabled. */
+	bool fc_enabled;
+	bool plec_enabled;
+
+	/* pt_n -> mcast_id mapping */
+	unsigned int mcast_n;
+
+	/* Keep track of used MST entries when releasing the PTe. The
+	 * PTe can only be released when all MSTs attached to it have
+	 * been recycled.
+	 */
+	DECLARE_BITMAP(mst_rc_update, C_MST_DBG_MST_TABLE_ENTRIES);
+
+	int pe_num;
+	int le_pool;
+};
+
+void cxi_free_resource(struct cxi_dev *dev, struct cxi_svc_priv *svc_priv,
+		       enum cxi_rsrc_type type);
+int cxi_alloc_resource(struct cxi_dev *dev, struct cxi_svc_priv *svc_priv,
+		       enum cxi_rsrc_type type);
+unsigned int cxi_lni_get_pe_num(struct cxi_lni_priv *lni);
+
+
+void cxi_domain_lni_cleanup(struct cxi_lni_priv *lni_priv);
+
+int nvidia_p2p_init(void);
+void nvidia_p2p_fini(void);
+
+int amd_p2p_init(void);
+void amd_p2p_fini(void);
+
+int cxi_dma_buf_init(void);
+void cxi_dma_buf_fini(void);
+
+#include "cxi_configuration.h"
+
+#endif	/* _CXI_CORE_H */
diff --git a/drivers/net/ethernet/hpe/ss1/cxi_eth.h b/drivers/net/ethernet/hpe/ss1/cxi_eth.h
new file mode 100644
index 000000000000..84590ef58ebf
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cxi_eth.h
@@ -0,0 +1,352 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Cassini ethernet driver
+ * Copyright 2018-2020,2022 Hewlett Packard Enterprise Development LP
+ */
+
+#ifndef __CXI_ETH_H__
+#define __CXI_ETH_H__
+#include <linux/hpe/cxi/cxi.h>
+#include <uapi/ethernet/cassini_user_defs.h>
+#include <linux/ethtool.h>
+#include <linux/net_tstamp.h>
+#include <linux/netlink.h>
+
+#include "cxi_ethtool.h"
+#include "cxi_core.h"
+
+#define NETIF_NAPI_ADD netif_napi_add
+#define NETIF_NAPI_ADD_TX netif_napi_add_tx
+
+#define CXI_ETH_1_MB (1024 * 1024)
+#define CXI_ETH_1_GB (CXI_ETH_1_MB * 1024)
+
+#define SMALL_PKTS_BUF_COUNT_MIN 1U
+#define SMALL_PKTS_BUF_COUNT_MAX (16 * 1024U)
+
+#define LARGE_PKTS_BUF_COUNT_MIN 1U
+#define LARGE_PKTS_BUF_COUNT_MAX 10000U
+
+#define TX_QUEUE_LEN_DEFAULT 1000
+
+#define MAX_LE_LIMIT 16384
+
+/* Align max TX queues to max RX queues. */
+#define CXI_ETH_MAX_TX_QUEUES CXI_ETH_MAX_RSS_QUEUES
+
+/* 4.12 kernels do not define these.
+ * TODO: remove eventually
+ */
+#define SPEED_400000       400000
+#define SPEED_200000       200000
+#define ETHTOOL_LINK_MODE_50000baseKR_Full_BIT   52
+#define	ETHTOOL_LINK_MODE_100000baseCR2_Full_BIT 59
+#define	ETHTOOL_LINK_MODE_200000baseCR4_Full_BIT 66
+
+/* Cassini 1 & 2 support up to 5 segments */
+#define C_MAX_ETH_FRAGS 5
+#define MAX_CB_LEN 3
+
+/* Private DMA registration data stored in the SKB cb */
+struct cb_data {
+	u8 num_frags;
+	u16 dma_len[MAX_CB_LEN]; /* alas, not enough room for C_MAX_ETH_FRAGS */
+	dma_addr_t dma_addr[C_MAX_ETH_FRAGS];
+};
+
+static inline void cxi_force_icrc_check(struct sk_buff *skb)
+{
+#ifdef SKBTX_ZEROCOPY_FRAG
+	skb_shinfo(skb)->__unused |= BIT(1);
+#else
+	skb_shinfo(skb)->flags |= BIT(6);
+#endif
+}
+
+static inline void cxi_skb_icrc_gone(struct sk_buff *skb)
+{
+#ifdef SKBTX_ZEROCOPY_FRAG
+	skb_shinfo(skb)->__unused |= BIT(0);
+#else
+	skb_shinfo(skb)->flags |= BIT(7);
+#endif
+}
+
+/* An RX buffer. It can end-up on the request or priority list. */
+struct rx_buffer {
+	struct list_head buf_list;
+
+	unsigned int id;
+
+	size_t data_size;
+
+	enum c_ptl_list ptl_list; /* PRIORITY or REQUEST */
+
+	union {
+		struct {
+			/* Valid only if list is PRIORITY */
+			struct page *page;
+			dma_addr_t mapping;
+			size_t cur_offset;
+			unsigned int posted_count;
+		};
+		struct {
+			/* Valid only if list is REQUEST */
+			struct cxi_md *md;
+			u8 *data;
+		};
+	};
+};
+
+struct tx_queue {
+	struct cxi_eth *dev;
+	struct cxi_eq_attr eq_attr;
+	struct cxi_md *eq_md;
+	struct cxi_eq *eq;
+	struct cxi_cq *eth1_cq;
+	struct cxi_cq *eth2_cq; /* Initialized conditionally */
+	struct cxi_cq *shared_cq;
+	struct cxi_cq *untagged_cq; /* Points to one of the above CQs */
+	struct napi_struct napi;
+
+	/* It is possible for start_xmit to get a lot of small packets
+	 * that fill up the TX queue, in which case
+	 * netif_tx_stop_queue() would be called. However since IDC
+	 * packets do not generate an interrupt, the send queue may
+	 * never be awaken again. Protect against that by forcing a
+	 * DMA instead of IDC every 'force_dma_interval' contiguous
+	 * IDC requests.
+	 */
+	int force_dma;
+	int force_dma_interval;
+
+	/* Associated netdev TX queue. */
+	unsigned int id;
+
+	/* NUMA node and CPU TX queue should be bound to. */
+	unsigned int node;
+	unsigned int cpu;
+
+	/* Each DMA op can use up to an EQ slot (16 or 32 bytes event,
+	 * plus padding). If too many DMA operations are in flight,
+	 * the EQ might get overrun. Pause the EQ in that case.
+	 */
+	atomic_t dma_eq_cdt;
+
+	struct {
+		u64 polling;
+		u64 stopped;	/* netif queue stopped by driver, CQ almost full */
+		u64 stopped_eq;	/* netif queue stopped by driver, EQ almost full */
+		u64 restarted;	/* netif queue restarted by driver */
+		u64 tx_busy;	/* returned NETDEV_TX_BUSY */
+		u64 idc;
+		u64 idc_bytes;
+		u64 dma;
+		u64 dma_bytes;
+		u64 dma_forced;
+	} stats;
+};
+
+#define NB_BUCKETS 23
+struct bucket {
+	u64 min_ts;
+	u64 max_ts;
+	u64 b[NB_BUCKETS];
+};
+
+struct rx_queue {
+	struct cxi_eth *dev;
+	void *eq_buf;
+	size_t eq_buf_size;
+	struct cxi_md *eq_md;
+	struct cxi_eq *eq;
+	struct cxi_pte *pt;
+	struct napi_struct napi;
+
+	struct cxi_cq *cq_tgt_prio;
+
+	/* Pool of receive buffers. Buffers start on the rx_ready
+	 * list, where they wait to be appended to a portal. When a
+	 * buffer is appended, it moves to the rx_in_use
+	 * list. Eventually the buffer is unlinked by Cassini (usually
+	 * after it becomes full) and reused again by the driver once
+	 * all its data has been consumed.
+	 *
+	 * The buffers on the request list are for "small" packets,
+	 * while the buffers on the priority list are for large
+	 * packets.
+	 */
+	struct list_head rx_unallocated;
+	struct list_head rx_ready; /* allocated but not appended */
+	struct list_head rx_in_use; /* appended or unlinked */
+
+	unsigned int rx_bufs_count;
+	struct rx_buffer *rx_bufs;
+
+	/* Segmented packet reassembly state */
+	enum { FRAG_NONE, FRAG_MORE, FRAG_DROP } frag_state;
+	u64 pkt_cnt;
+	u8 next_seg_cnt;
+
+	unsigned int last_bad_frag_drop_rc;
+
+	struct {
+		u64 append_prio;
+		u64 append_req;
+		u64 append_failed;
+		u64 unlinked_prio;
+		u64 unlinked_req;
+	} stats;
+
+	/* Associated netdev RX queue. */
+	unsigned int id;
+
+	/* NUMA node and CPU RX queue should be bound to. */
+	unsigned int node;
+	unsigned int cpu;
+
+	/* Debug code. Should be removed eventually. Measure the time
+	 * between a napi schedule call, and the call to rx_eq_cb() to
+	 * process the queue.
+	 */
+	ktime_t time_napi_schedule;
+	struct bucket eth_napi_schedule;
+
+	/* Number of times an page should be posted to the priority queue. */
+	unsigned int page_chunks;
+};
+
+/* A queue only for PTP packets. Cassini ERRATA-3258. */
+#define PTP_RX_Q max_rss_queues
+
+struct cxi_eth {
+	struct list_head dev_list;
+	struct cxi_dev *cxi_dev;
+	bool is_c2;
+
+	struct net_device *ndev;
+
+	struct dentry *debug;
+
+	bool is_active;
+
+	int svc_id;
+	u32 min_free;
+	u64 mac_addr;
+
+	/* Cassini ERRATA-3258 for PTP. Cassini 1/1.1 doesn't set the timestamp
+	 * bit. Instead we have a separate portal entry that will only
+	 * get the PTP packets with the special MAC address. If
+	 * ptp_ts_enabled is true then these packets will have a
+	 * timestamp, except for a very short window.
+	 */
+	bool ptp_ts_enabled;
+	u64 ptp_mac_addr;
+	struct sk_buff *tstamp_skb;
+
+	unsigned int phys_lac;
+
+	bool eth2_active;
+	int eth1_pcp;
+	int eth2_pcp;
+
+	struct cxi_lni *lni;
+	struct cxi_cp *eth1_cp;
+	struct cxi_cp *eth2_cp;
+	struct cxi_cp *shared_cp;
+
+	/* Shared CQ with every RX channel for their target request
+	 * list. As posted buffers are big, operations on this CQ will
+	 * be few and far between.
+	 */
+	spinlock_t cq_tgt_req_lock;
+	struct cxi_cq *cq_tgt_req;
+
+	/* Event queue used for CQ errors. */
+	struct cxi_eq *err_eq;
+	struct cxi_eq_attr err_eq_attr;
+
+	/* TX queues/rings. TXQ zero remains allocated for the duration of the
+	 * Ethernet interface remaining open. TXQs greater than zero are
+	 * allocated/deallocated base on number of configured TX queues.
+	 */
+	struct tx_queue *txqs;
+	unsigned int cur_txqs;
+
+	/* RX queues/rings. RXQ zero is the default/catch-all RX queue and
+	 * remains allocated for the duration of the Ethernet interface
+	 * remaining open. RXQs greater than zero and allocated/deallocated
+	 * based on number of configured RX queues.
+	 */
+	struct rx_queue *rxqs;
+
+	/* Number of RX buffers */
+	unsigned int num_prio_buffers;
+	unsigned int num_req_buffers;
+
+	struct ethtool_ringparam ringparam;
+	struct kernel_ethtool_ringparam kernel_ring;
+
+	struct cxi_eth_res res;
+	struct cxi_eth_info eth_info;
+
+	/* ethtool private flags (CXI_ETH_PF_...) */
+	u32 priv_flags;
+
+	/* Timestamp config copy */
+	struct hwtstamp_config tstamp_config;
+};
+
+extern unsigned int rss_indir_size;
+extern unsigned int max_rss_queues;
+extern unsigned int max_tx_queues;
+extern unsigned int small_pkts_buf_size;
+extern unsigned int idc_dma_threshold;
+extern unsigned int lpe_cdt_thresh_id;
+extern unsigned long rx_repost_retry_jiffies;
+extern unsigned int small_pkts_buf_count;
+extern unsigned int large_pkts_buf_count;
+extern unsigned int buffer_threshold;
+
+#define CXI_ETH_MAX_MTU 9000
+#define CXI_ETH_TX_TIMEOUT (5 * HZ)
+
+/* Compute an approximative number of packets that can be contained in
+ * the small buffers. Since each segment cannot be larger that the
+ * buffer_threshold, use that as a base.
+ */
+static inline u32 num_small_packets(u32 buf_count)
+{
+	return buf_count * (small_pkts_buf_size / buffer_threshold);
+}
+
+size_t get_rxq_eq_buf_size(struct cxi_eth *dev);
+void hw_cleanup(struct cxi_eth *dev);
+int hw_setup(struct cxi_eth *dev);
+
+/* Netdev methods */
+int cxi_eth_open(struct net_device *ndev);
+int cxi_eth_close(struct net_device *ndev);
+netdev_tx_t cxi_eth_start_xmit(struct sk_buff *skb, struct net_device *dev);
+int cxi_eth_mac_addr(struct net_device *dev, void *p);
+void cxi_eth_set_rx_mode(struct net_device *dev);
+int cxi_change_mtu(struct net_device *netdev, int new_mtu);
+void disable_rx_queue(struct rx_queue *rx);
+void free_rx_queue(struct rx_queue *rx);
+int alloc_rx_queue(struct cxi_eth *dev, unsigned int id);
+void enable_rx_queue(struct rx_queue *rx);
+int post_rx_buffers(struct rx_queue *rx, gfp_t gfp);
+int alloc_tx_queue(struct cxi_eth *dev, unsigned int id);
+void free_tx_queue(struct tx_queue *tx);
+void enable_tx_queue(struct tx_queue *tx);
+void disable_tx_queue(struct tx_queue *tx);
+int cxi_set_rx_channels(struct cxi_eth *dev, unsigned int num_rx_channels);
+int cxi_set_tx_channels(struct cxi_eth *dev, unsigned int num_tx_channels);
+int cxi_eth_hwtstamp_get(struct net_device *ndev,
+			 struct kernel_hwtstamp_config *config);
+int cxi_eth_hwtstamp_set(struct net_device *ndev,
+			 struct kernel_hwtstamp_config *config,
+			 struct netlink_ext_ack *extack);
+
+extern const struct ethtool_ops cxi_eth_ethtool_ops;
+#endif
diff --git a/drivers/net/ethernet/hpe/ss1/cxi_eth_debugfs.h b/drivers/net/ethernet/hpe/ss1/cxi_eth_debugfs.h
new file mode 100644
index 000000000000..03b6e38b2e96
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cxi_eth_debugfs.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2018 Hewlett Packard Enterprise Development LP */
+/* cxi-eth debug fs*/
+
+#ifndef __CXI_ETH_DEBUGFS_H__
+#define __CXI_ETH_DEBUGFS_H__
+#include <linux/debugfs.h>
+#include <linux/netdevice.h>
+
+#ifdef CONFIG_DEBUG_FS
+void device_debugfs_create(char *name, struct cxi_eth *dev,
+			   struct dentry *cxieth_debug_dir);
+struct dentry *device_eth_debugfs_init(void);
+
+#else
+static inline void device_debugfs_create(char *name, struct cxi_eth *dev,
+					 struct dentry *cxieth_debug_dir)
+{
+}
+
+static inline struct dentry *device_eth_debugfs_init(void)
+{
+	return NULL;
+}
+#endif
+#endif
diff --git a/drivers/net/ethernet/hpe/ss1/cxi_ethtool.h b/drivers/net/ethernet/hpe/ss1/cxi_ethtool.h
new file mode 100644
index 000000000000..481c5a5e3741
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cxi_ethtool.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2018-2020,2022,2024,2026 Hewlett Packard Enterprise Development LP */
+
+/* ethtool private flags for the Cassini Ethernet driver */
+#define CXI_ETH_PF_INTERNAL_LOOPBACK         BIT(0)  /* internal loopback, tx to rx */
+#define CXI_ETH_PF_EXTERNAL_LOOPBACK         BIT(1)  /* external loopback, rx to tx */
+#define CXI_ETH_PF_LLR                       BIT(2)
+#define CXI_ETH_PF_PRECODING                 BIT(3)
+#define CXI_ETH_PF_IFG_HPC                   BIT(4)
+#define CXI_ETH_PF_ROCE_OPT                  BIT(5)  /* RoCE Cassini Optimizations */
+#define CXI_ETH_PF_IGNORE_ALIGN              BIT(6)  /* ignore align interrupt */
+#define CXI_ETH_PF_PML_REC                   BIT(7)  /* control pml recovery */
+#define CXI_ETH_PF_LINKTRAIN                 BIT(8)  /* link training */
+#define CXI_ETH_PF_REMOTE_FAULT_RECOVERY     BIT(9)  /* enable pml recovery for remote faults */
+#define CXI_ETH_PF_USE_UNSUPPORTED_CABLE     BIT(10) /* allow link up with unsupported cable */
+#define CXI_ETH_PF_FEC_MONITOR               BIT(11) /* Turn FEC Monitor on/off */
+#define CXI_ETH_PF_ALD                       BIT(12) /* control auto lane degrade */
+#define CXI_ETH_PF_IGNORE_MEDIA_ERROR        BIT(13) /* ignore media error */
+#define CXI_ETH_PF_USE_SUPPORTED_SS200_CABLE BIT(14) /* allow link up with supported ss200 cable */
+#define CXI_ETH_PF_LOS_LOL_HIDE              BIT(15) /* hide LOS/LOL down and link up fail cause */
+#define CXI_ETH_PF_R1_LINK_PARTNER           BIT(16) /* R1 link partner */
+
+#define PRIV_FLAGS_COUNT 17
+
+#define LOOPBACK_MODE (CXI_ETH_PF_INTERNAL_LOOPBACK | CXI_ETH_PF_EXTERNAL_LOOPBACK)
+#define LINK_DEBUG_FLAGS (CXI_ETH_PF_IGNORE_ALIGN | CXI_ETH_PF_REMOTE_FAULT_RECOVERY)
diff --git a/drivers/net/ethernet/hpe/ss1/cxi_ethtool_names.h b/drivers/net/ethernet/hpe/ss1/cxi_ethtool_names.h
new file mode 100644
index 000000000000..fd0b90e90c6a
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cxi_ethtool_names.h
@@ -0,0 +1,110 @@
+/* SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause */
+/*
+ * Copyright 2024 Hewlett Packard Enterprise Development LP
+ */
+
+#ifndef __CXI_ETHTOOL_NAMES_H
+#define __CXI_ETHTOOL_NAMES_H
+
+/* stats returned via .get_ethtool_stats()  */
+#define CXI_GLOBAL_STATS_LEN    ARRAY_SIZE(cxi_get_ethtool_stats_set)
+/* Telemetry item IDs */
+static const unsigned int cxi_get_ethtool_stats_set[] = {
+	586,	/* hni_rx_ok_ieee */
+	567,	/* hni_rx_bad_ieee */
+	637,	/* hni_tx_ok_ieee */
+	651,	/* hni_tx_poisoned_ieee */
+	590,	/* hni_rx_ok_opt */
+	568,	/* hni_rx_bad_opt */
+	639,	/* hni_tx_ok_opt */
+	652,	/* hni_tx_poisoned_opt */
+	507,	/* hni_pcs_corrected_cw */
+	542,	/* hni_pcs_uncorrected_cw */
+	539,	/* hni_pcs_good_cw */
+	543,	/* hni_pfc_fifo_oflw_cntr_0 */
+	544,	/* hni_pfc_fifo_oflw_cntr_1 */
+	545,	/* hni_pfc_fifo_oflw_cntr_2 */
+	546,	/* hni_pfc_fifo_oflw_cntr_3 */
+	547,	/* hni_pfc_fifo_oflw_cntr_4 */
+	548,	/* hni_pfc_fifo_oflw_cntr_5 */
+	549,	/* hni_pfc_fifo_oflw_cntr_6 */
+	550,	/* hni_pfc_fifo_oflw_cntr_7 */
+	758,	/* ixe_rx_udp_pkt */
+	757,	/* ixe_rx_tcp_pkt */
+	734,	/* ixe_rx_ipv4_pkt */
+	735,	/* ixe_rx_ipv6_pkt */
+	754,	/* ixe_rx_roce_pkt */
+	744,	/* ixe_rx_ptl_gen_pkt */
+	752,	/* ixe_rx_ptl_sml_pkt */
+	753,	/* ixe_rx_ptl_unrestricted_pkt */
+	750,	/* ixe_rx_ptl_smallmsg_pkt */
+	743,	/* ixe_rx_ptl_continuation_pkt */
+	749,	/* ixe_rx_ptl_restricted_pkt */
+	742,	/* ixe_rx_ptl_connmgmt_pkt */
+	748,	/* ixe_rx_ptl_response_pkt */
+	759,	/* ixe_rx_unrecognized_pkt */
+	751,	/* ixe_rx_ptl_sml_amo_pkt */
+	746,	/* ixe_rx_ptl_msgs */
+	747,	/* ixe_rx_ptl_multi_msgs */
+	745,	/* ixe_rx_ptl_mr_msgs */
+	737,	/* ixe_rx_pkt_drop_pct */
+	738,	/* ixe_rx_pkt_drop_rmu_norsp */
+	739,	/* ixe_rx_pkt_drop_rmu_wrsp */
+	736,	/* ixe_rx_pkt_drop_ixe_parser */
+	740,	/* ixe_rx_pkt_ipv4_options */
+	741,	/* ixe_rx_pkt_ipv6_options */
+	733,	/* ixe_rx_eth_seg */
+	755,	/* ixe_rx_roce_seg */
+	756,	/* ixe_rx_roce_spseg */
+};
+
+static const char cxi_get_ethtool_stats_name[CXI_GLOBAL_STATS_LEN][ETH_GSTRING_LEN] = {
+	"rx_ok_ieee",
+	"rx_bad_ieee",
+	"tx_ok_ieee",
+	"tx_poisoned_ieee",
+	"rx_ok_opt",
+	"rx_bad_opt",
+	"tx_ok_opt",
+	"tx_poisoned_opt",
+	"corrected_cw",
+	"uncorrected_cw",
+	"good_cw",
+	"fifo_oflw_cntr_0",
+	"fifo_oflw_cntr_1",
+	"fifo_oflw_cntr_2",
+	"fifo_oflw_cntr_3",
+	"fifo_oflw_cntr_4",
+	"fifo_oflw_cntr_5",
+	"fifo_oflw_cntr_6",
+	"fifo_oflw_cntr_7",
+	"rx_udp_pkt",
+	"rx_tcp_pkt",
+	"rx_ipv4_pkt",
+	"rx_ipv6_pkt",
+	"rx_roce_pkt",
+	"rx_ptl_gen_pkt",
+	"rx_ptl_sml_pkt",
+	"rx_ptl_unrestricted_pkt",
+	"rx_ptl_smallmsg_pkt",
+	"rx_ptl_continuation_pkt",
+	"rx_ptl_restricted_pkt",
+	"rx_ptl_connmgmt_pkt",
+	"rx_ptl_response_pkt",
+	"rx_unrecognized_pkt",
+	"rx_ptl_sml_amo_pkt",
+	"rx_ptl_msgs",
+	"rx_ptl_multi_msgs",
+	"rx_ptl_mr_msgs",
+	"rx_pkt_drop_pct",
+	"rx_pkt_drop_rmu_norsp",
+	"rx_pkt_drop_rmu_wrsp",
+	"rx_pkt_drop_ixe_parser",
+	"rx_pkt_ipv4_options",
+	"rx_pkt_ipv6_options",
+	"rx_eth_seg",
+	"rx_roce_seg",
+	"rx_roce_spseg",
+};
+
+#endif
diff --git a/drivers/net/ethernet/hpe/ss1/cxi_internal.h b/drivers/net/ethernet/hpe/ss1/cxi_internal.h
new file mode 100644
index 000000000000..5768a26aa804
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cxi_internal.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2026 Hewlett Packard Enterprise Development LP */
+
+#ifndef _CXI_INTERNAL_H
+#define _CXI_INTERNAL_H
+
+#include <linux/hpe/cxi/cxi.h>
+
+struct cxi_ct *cxi_ct_alloc_internal(struct cxi_lni *lni,
+				     struct c_ct_writeback *wb, bool is_user,
+				     dma_addr_t wb_dma_addr);
+int cxi_ct_wb_update_internal(struct cxi_ct *ct, struct c_ct_writeback *wb,
+			      dma_addr_t wb_dma_addr);
+
+struct cxi_lni *cxi_lni_alloc_internal(struct cxi_dev *dev, unsigned int svc_id,
+				       bool vf_en, u8 vf_num);
+int cxi_lni_pid_alloc(struct cxi_lni *lni);
+void cxi_lni_pid_free(struct cxi_lni *lni, unsigned int pid);
+
+struct cxi_eq *cxi_eq_alloc_internal(struct cxi_lni *lni, const struct cxi_md *md,
+				     const struct cxi_eq_attr *attr,
+				     void (*event_cb)(void *cb_data),
+				     void *event_cb_data,
+				     void (*status_cb)(void *cb_data),
+				     void *status_cb_data, dma_addr_t dma_addr,
+				     int event_irq_idx, int status_irq_idx);
+int cxi_eq_resize_internal(struct cxi_eq *evtq, void *queue,
+			   size_t queue_len, struct cxi_md *queue_md,
+			   dma_addr_t dma_addr);
+
+struct cxi_cq *cxi_cq_alloc_buf_internal(struct cxi_lni *lni, struct cxi_eq *evtq,
+					 const struct cxi_cq_alloc_opts_buf *opts_b,
+					 int numa_node, dma_addr_t cmds_dma_addr,
+					 size_t cmds_len);
+
+struct cxi_rmu_eth *cxi_rmu_eth_alloc_internal(struct cxi_dev *cdev, bool vf_en,
+					       u8 vf_num);
+
+#endif /* _CXI_INTERNAL_H */
diff --git a/drivers/net/ethernet/hpe/ss1/cxi_link.h b/drivers/net/ethernet/hpe/ss1/cxi_link.h
new file mode 100644
index 000000000000..e015248fe7aa
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cxi_link.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2023,2024,2026 Hewlett Packard Enterprise Development LP */
+
+#ifndef _CXI_LINK_H
+#define _CXI_LINK_H
+
+struct cxi_dev;
+struct cass_dev;
+
+/**
+ * struct cxi_link_info - Attributes for link configuration
+ *
+ * @flags: CXI private flags (CXI_ETH_PF_xxx)
+ * @speed: ethtool speed setting (SPEED_xxx)
+ * @autoneg: ethtool autonegotiation setting (AUTONEG_ENABLE / AUTONEG_DISABLE)
+ * @port_type: ethtool; port type (PORT_FIBRE, PORT_DA, ...)
+ * @fec_type: ethtool; fec (ETHTOOL_FEC_OFF, ETHTOOL_FEC_RS, ...)
+ *
+ * These attributes must be configured for a link.
+ * Different setting will be required for fabric or Ethernet links
+ */
+struct cxi_link_info {
+	u32 flags;		/* or'ed CXI_ETH_PF_xxx */
+	int speed;		/* SPEED_xxx */
+	u32 autoneg;		/* AUTONEG_ENABLE / AUTONEG_DISABLE */
+	u32 port_type;		/* PORT_FIBRE, PORT_DA, ... */
+	u32 fec_type;           /* ETHTOOL_FEC_OFF, ETHTOOL_FEC_RS, ... */
+};
+
+void cxi_link_mode_get(struct cxi_dev *cxi_dev, struct cxi_link_info *link_info);
+void cxi_link_mode_set(struct cxi_dev *cxi_dev, const struct cxi_link_info *link_info);
+void cxi_link_flags_get(struct cxi_dev *cxi_dev, u32 *flags);
+void cxi_link_flags_set(struct cxi_dev *cxi_dev, u32 clr_flags, u32 set_flags);
+u32 cxi_link_flags_supported(struct cxi_dev *cxi_dev);
+void cxi_link_use_unsupported_cable(struct cxi_dev *cxi_dev, bool use);
+void cxi_link_use_supported_ss200_cable(struct cxi_dev *cxi_dev, bool use);
+void cxi_link_ignore_media_error(struct cxi_dev *cxi_dev, bool ignore);
+void cxi_link_auto_lane_degrade(struct cxi_dev *cxi_dev, bool enable);
+void cxi_pml_recovery_set(struct cxi_dev *cxi_dev, bool set);
+void cxi_link_los_lol_hide(struct cxi_dev *cxi_dev, bool enable);
+
+struct cxi_link_ops {
+	int (*init)(struct cass_dev *hw);
+	int (*link_start)(struct cass_dev *hw);
+	int (*link_fini)(struct cass_dev *hw);
+	void (*mode_get)(struct cass_dev *hw, struct cxi_link_info *link_info);
+	void (*mode_set)(struct cass_dev *hw, const struct cxi_link_info *link_info);
+	void (*flags_get)(struct cass_dev *hw, u32 *flags);
+	void (*flags_set)(struct cass_dev *hw, u32 clr_flags, u32 set_flags);
+	u32  flags_supported;	/* CXI_ETH_PF_xxx handled by flags_set */
+	int  (*link_up)(struct cass_dev *hw);
+	int  (*link_down)(struct cass_dev *hw);
+	bool (*is_pcs_aligned)(struct cass_dev *hw);
+	int  (*media_config)(struct cass_dev *hw, void *attr);
+	int  (*media_unconfig)(struct cass_dev *hw);
+	int  (*link_config)(struct cass_dev *hw);
+	int  (*link_reset)(struct cass_dev *hw);
+	void (*link_exit)(struct cass_dev *hw);
+	void (*pml_recovery_set)(struct cass_dev *hw, bool set);
+	bool (*is_link_up)(struct cass_dev *hw);
+	int (*eth_name_set)(struct cass_dev *hw, const char *name);
+};
+
+void cxi_set_link_ops(struct cass_dev *hw);
+#endif
diff --git a/drivers/net/ethernet/hpe/ss1/cxi_qos_profiles.h b/drivers/net/ethernet/hpe/ss1/cxi_qos_profiles.h
new file mode 100644
index 000000000000..be97faeae3c3
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cxi_qos_profiles.h
@@ -0,0 +1,149 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/*
+ * Cassini QoS Profiles
+ * Copyright 2023 Hewlett Packard Enterprise Development LP
+ */
+
+#define CXI_MAX_RDMA_TCS 4
+#define PCP_COUNT 8U
+#define CXI_ETH_TC_MAX (CXI_ETH_TC2 + 1)
+
+struct cass_tc_oxe_settings {
+	unsigned int spt_rsvd;
+	unsigned int smt_rsvd;
+	unsigned int sct_rsvd;
+	unsigned int srb_rsvd;
+	unsigned int pbuf_rsvd;
+	unsigned int assured_percent;
+	unsigned int ceiling_percent;
+	unsigned int bucket_limit;
+	unsigned int leaf_request_priority;
+	unsigned int leaf_response_priority;
+	unsigned int branch_priority;
+	unsigned int mfs_index;
+};
+
+struct cass_tc_dscp_pcp_settings {
+	/* Required request and response PCP and DSCP for all traffic classes
+	 * and traffic class types.
+	 */
+	unsigned int req_pcp;
+	unsigned int rsp_pcp;
+	unsigned int res_rsp_dscp;
+	unsigned int unres_rsp_dscp;
+
+	/* Restricted request DSCP used for CXI_TC_TYPE_DEFAULT and
+	 * CXI_TC_TYPE_RESTRICTED traffic class types.
+	 */
+	unsigned int res_req_dscp;
+
+	/* Unrestricted request DSCP used for CXI_TC_TYPE_DEFAULT and
+	 * CXI_TC_TYPE_HRP traffic class types.
+	 */
+	unsigned int unres_req_dscp;
+
+	/* Restricted request DSCP used only for CXI_TC_TYPE_HRP traffic class
+	 * type. -1 disables the CXI_TC_TYPE_HRP traffic class type for a given
+	 * traffic class.
+	 */
+	int hrp_res_req_dscp;
+
+	/* Restricted request DSCP used only for CXI_TC_TYPE_COLL_LEAF
+	 * traffic class type. -1 disables the CXI_TC_TYPE COLL_LEAF for a
+	 * given traffic class.
+	 */
+	int coll_leaf_res_req_dscp;
+
+	/* Unrestricted request DSCP used only for CXI_TC_TYPE_RESTRICTED
+	 * traffic class type. -1 disables the CXI_TC_TYPE_RESTRICTED traffic
+	 * class type for a given traffic class.
+	 */
+	int restricted_unres_req_dscp;
+};
+
+struct cass_tc_cq_settings {
+	unsigned int dynamic_fq_count;
+	unsigned int static_fq_count;
+	unsigned int fq_buf_reserved;
+	unsigned int pfq_high_thresh;
+};
+
+struct cass_tc_ixe_settings {
+	unsigned int fq_count;
+};
+
+struct cass_tc_lpe_settings {
+	unsigned int fq_count;
+};
+
+struct cass_tc_pct_settings {
+	unsigned int trs_rsvd;
+	unsigned int mst_rsvd;
+	unsigned int tct_rsvd;
+};
+
+struct cass_tc_hni_settings {
+	unsigned int pbuf_rsvd;
+	unsigned int mfs;
+};
+
+enum cxi_qos_profile {
+	CXI_QOS_HPC = 1, /* Leave 0 as Invalid to catch errors */
+	CXI_QOS_LL_BE_BD_ET,
+	CXI_QOS_LL_BE_BD_ET1_ET2,
+	CXI_QOS_NUM_PROF
+};
+
+struct cass_tc_eth_settings {
+	unsigned int pcp;
+	bool tc_pcps[8]; /* Used only by ETH_SHARED */
+};
+
+struct cxi_tc {
+	enum cxi_traffic_class tc;
+	struct kobject kobj;
+	unsigned int default_ocuset;
+	unsigned int default_cq_tc;
+	unsigned int restricted_ocuset;
+	unsigned int restricted_cq_tc;
+	unsigned int branch;
+	unsigned int leaf[2]; /* assumes always 2 leaves per TC */
+	unsigned int req_bc;
+
+	/* RDMA Only Settings */
+	struct cass_tc_dscp_pcp_settings dscp_pcp_settings;
+	struct cass_tc_ixe_settings ixe_settings;
+	struct cass_tc_lpe_settings lpe_settings;
+	struct cass_tc_pct_settings pct_settings;
+
+	/* Settings for RDMA + "Global" Ethernet */
+	struct cass_tc_oxe_settings oxe_settings;
+	struct cass_tc_cq_settings cq_settings;
+	struct cass_tc_hni_settings hni_settings;
+
+	/* Eth only settings */
+	struct cass_tc_eth_settings eth_settings;
+};
+
+struct qos_profile {
+	struct mutex mutex;
+	bool tcs_active[CXI_ETH_TC_MAX];
+	unsigned int pct_control_pcp;
+	unsigned int pct_control_res_rsp_dscp;
+	unsigned int pct_control_unres_rsp_dscp;
+	unsigned int tc_restricted_oxe_req_bc;
+	unsigned int untagged_eth_pcp;
+	struct cxi_tc tcs[CXI_ETH_TC_MAX];
+};
+
+extern struct qos_profile profiles[];
+int tc_cfg_show(struct seq_file *s, void *unused);
+
+/* Check if a TC is an ethernet TC. Excludes the general CXI_ETH class */
+static inline bool is_eth_tc(unsigned int tc)
+{
+	return (tc > CXI_TC_ETH && tc < CXI_ETH_TC_MAX);
+}
+
+void cxi_qos_calculate_limits(struct qos_profile *qos, bool is_c2);
diff --git a/drivers/net/ethernet/hpe/ss1/cxi_rgroup.h b/drivers/net/ethernet/hpe/ss1/cxi_rgroup.h
new file mode 100644
index 000000000000..ae903ad466e6
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cxi_rgroup.h
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2024 Hewlett Packard Enterprise Development LP */
+
+/* TODO: are these really part of the uapi? */
+
+#ifndef _CXI_RGROUP_H_
+#define _CXI_RGROUP_H_
+
+#include <linux/xarray.h>
+#include "cass_core.h"
+
+/* Resource Groups contigurables */
+
+#define RGROUP_GFP_OPTS              (GFP_KERNEL)
+#define RGROUP_ID_MIN                (CXI_DEFAULT_SVC_ID)
+#define RGROUP_ID_MAX                (INT_MAX)
+#define RGROUP_ID_LIMITS             (XA_LIMIT(RGROUP_ID_MIN, \
+					       RGROUP_ID_MAX))
+#define RGROUP_XARRAY_FLAGS          (XA_FLAGS_ALLOC1)
+
+/* Resource Entries */
+
+#define RESOURCE_ENTRY_GFP_OPTS      (GFP_KERNEL)
+#define RESOURCE_ENTRY_ID_MIN        (0)
+#define RESOURCE_ENTRY_ID_MAX        (INT_MAX)
+#define RESOURCE_ENTRY_ID_LIMITS     (XA_LIMIT(RESOURCE_ENTRY_ID_MIN, \
+					       RESOURCE_ENTRY_ID_MAX))
+#define RESOURCE_ENTRY_XARRAY_FLAGS  (XA_FLAGS_ALLOC)
+
+struct cxi_rgroup_attr {
+	unsigned int   id;
+	unsigned int   cntr_pool_id;
+	unsigned int   lnis_per_rgid;
+	bool           system_service;
+	char           name[50];
+};
+
+struct cxi_rgroup_state {
+	bool           enabled;
+	refcount_t     refcount;
+};
+
+struct cxi_rgroup {
+	unsigned int                   id;
+	struct cass_dev                *hw;
+	struct cxi_rgroup_attr         attr;
+	struct cxi_rgroup_state        state;
+	struct cxi_resource_entry_list resource_entry_list;
+	struct cxi_ac_entry_list       ac_entry_list;
+	struct cxi_rgroup_pools        pools;
+};
+
+void cxi_dev_rgroup_init(struct cxi_dev *dev);
+void cxi_dev_rgroup_fini(struct cxi_dev *dev);
+
+/**
+ * for_each_rgroup() - Iterate over rgroup_list
+ *
+ * @list: rgroup list
+ * @index: index of @entry
+ * @entry: rgroup retrieved from array
+ *
+ * Return: first non-zero return value of operator or 0
+ */
+#define for_each_rgroup(index, entry) \
+	xa_for_each(&hw->rgroup_list.xarray, index, entry)
+
+#endif /* _CXI_RGROUP_H_ */
diff --git a/drivers/net/ethernet/hpe/ss1/cxi_rxtx_profile.h b/drivers/net/ethernet/hpe/ss1/cxi_rxtx_profile.h
new file mode 100644
index 000000000000..250d765b4b67
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cxi_rxtx_profile.h
@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright (C) 2024 Hewlett Packard Enterprise Development LP */
+
+/** Common parts of RX and TX Profiles
+ *
+ * These functions should only be used to implement RX and TX profile
+ * functions.
+ */
+
+#ifndef _CXI_RXTX_PROFILE_H_
+#define _CXI_RXTX_PROFILE_H_
+
+#define DEF_RMU_INDEX (-1)
+
+void cxi_rxtx_profile_init(struct cxi_rxtx_profile *rxtx_profile,
+			   struct cass_dev *hw,
+			   const struct cxi_rxtx_vni_attr *vni_attr);
+
+void cxi_rxtx_profile_destroy(struct cxi_rxtx_profile *rxtx_profile);
+
+int cxi_rxtx_profile_find_inc_refcount(struct cxi_rxtx_profile_list *list,
+				       unsigned int profile_id,
+				       struct cxi_rxtx_profile **rxtx_profile);
+
+int cxi_rxtx_profile_test_insert(struct cxi_rxtx_profile_list *list,
+				 struct cxi_rxtx_profile *rxtx_profile,
+				 unsigned int *id,
+				 int (*test_func)(const struct cxi_rxtx_profile *p1,
+						  const struct cxi_rxtx_profile *p2));
+
+void cxi_rxtx_profile_release(struct cxi_rxtx_profile *rxtx_profile);
+void cxi_rxtx_profile_revoke(struct cxi_rxtx_profile *rxtx_profile);
+
+void cxi_rxtx_profile_get_info(struct cxi_rxtx_profile *rxtx_profile,
+			       struct cxi_rxtx_vni_attr *vni_attr,
+			       struct cxi_rxtx_profile_state *state);
+
+int cxi_rxtx_profile_add_ac_entry(struct cxi_rxtx_profile *rxtx_profile,
+				  enum cxi_ac_type ac_type,
+				  union cxi_ac_data *ac_data,
+				  unsigned int *ac_entry_id);
+
+int cxi_rxtx_profile_remove_ac_entry(struct cxi_rxtx_profile *rxtx_profile,
+				     unsigned int ac_entry_id);
+
+int cxi_rxtx_profile_get_ac_entry_ids(struct cxi_rxtx_profile *rxtx_profile,
+				      size_t max_ids,
+				      unsigned int *ac_entry_ids,
+				      size_t *num_ids);
+
+int cxi_rxtx_profile_get_ac_entry_data(struct cxi_rxtx_profile *rxtx_profile,
+				       unsigned int ac_entry_id,
+				       enum cxi_ac_type *ac_type,
+				       union cxi_ac_data *ac_data);
+
+int cxi_rxtx_profile_get_ac_entry_id_by_data(struct cxi_rxtx_profile *rxtx_profile,
+					     enum cxi_ac_type ac_type,
+					     const union cxi_ac_data *ac_data,
+					     unsigned int *ac_entry_id);
+
+int cxi_rxtx_profile_get_ac_entry_id_by_user(struct cxi_rxtx_profile *rxtx_profile,
+					     uid_t uid,
+					     gid_t gid,
+					     unsigned int netns,
+					     cxi_ac_typeset_t desired_types,
+					     unsigned int *ac_entry_id);
+
+void cxi_tx_profile_list_destroy(struct cass_dev *cdev);
+
+int vni_overlap_test(struct cxi_rxtx_profile *profile1,
+		     void *user_arg);
+bool unique_vni_space(struct cass_dev *hw,
+		      struct cxi_rxtx_profile_list *list,
+		      const struct cxi_rxtx_vni_attr *attr);
+
+__maybe_unused
+static struct cxi_rx_profile *co_rx_profile(struct cxi_rxtx_profile *profile)
+{
+	return container_of(profile, struct cxi_rx_profile, profile_common);
+}
+
+__maybe_unused
+static struct cxi_tx_profile *co_tx_profile(struct cxi_rxtx_profile *profile)
+{
+	return container_of(profile, struct cxi_tx_profile, profile_common);
+}
+
+/**
+ * vni_well_formed() - determine if any of the match bits
+ *                     are also in the ignore mask.
+ *
+ * @attr: pointer to the VNI attributes
+ *
+ * Return: whether we consider this set of attributes good.
+ */
+static inline bool vni_well_formed(const struct cxi_rxtx_vni_attr *attr)
+{
+	return !(attr->match & attr->ignore);
+}
+
+/**
+ * zero_vni() - Check for the zero vni which is invalid
+ *              Used for allocating an rx profile with unknown attributes
+ *              which will be updated later.
+ *
+ * @attr: pointer to the VNI attributes
+ *
+ * Return: The match value is the default (invalid) value of 0.
+ */
+static inline bool zero_vni(const struct cxi_rxtx_vni_attr *attr)
+{
+	return !attr->match;
+}
+
+/**
+ * vni_overlap() - determine if 2 vni specifications share
+ *                 any VNI space.
+ *
+ * @attr1: pointer to a VNI attribute
+ * @attr2: pointer to second VNI attribute
+ *
+ * Return: true if any VNI satisfies both specifications.
+ */
+static inline bool vni_overlap(const struct cxi_rxtx_vni_attr *attr1,
+			       const struct cxi_rxtx_vni_attr *attr2)
+{
+	u16 ignore = attr1->ignore | attr2->ignore;
+
+	if ((attr1->match & ~ignore) != (attr2->match & ~ignore))
+		return false;
+
+	return true;
+}
+
+#endif /* _CXI_RXTX_PROFILE_H_ */
diff --git a/drivers/net/ethernet/hpe/ss1/cxi_rxtx_profile_list.h b/drivers/net/ethernet/hpe/ss1/cxi_rxtx_profile_list.h
new file mode 100644
index 000000000000..45faf343b283
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cxi_rxtx_profile_list.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright 2023 Hewlett Packard Enterprise Development LP */
+
+#ifndef _CXI_RXTX_PROFILE_LIST_H_
+#define _CXI_RXTX_PROFILE_LIST_H_
+
+#include <linux/xarray.h>
+
+#define RX_PROFILE_ID_MIN        (1)
+#define RX_PROFILE_ID_MAX        (UINT_MAX)
+#define RX_PROFILE_XARRAY_FLAGS  (XA_FLAGS_ALLOC1)
+#define RX_PROFILE_GFP_OPTS      (GFP_KERNEL)
+
+#define TX_PROFILE_ID_MIN        (1)
+#define TX_PROFILE_ID_MAX        (UINT_MAX)
+#define TX_PROFILE_XARRAY_FLAGS  (XA_FLAGS_ALLOC1)
+#define TX_PROFILE_GFP_OPTS      (GFP_KERNEL)
+
+struct cxi_rxtx_profile;
+
+void cxi_rxtx_profile_list_init(struct cxi_rxtx_profile_list *list,
+				struct xa_limit *limits,
+				gfp_t flags,
+				gfp_t gfp_opts);
+
+void cxi_rxtx_profile_list_destroy(struct cxi_rxtx_profile_list *list,
+				   void (*cleanup)(struct cxi_rxtx_profile *rxtx_profile,
+						   void *user_args),
+				   void *user_args);
+
+void cxi_rxtx_profile_list_lock(struct cxi_rxtx_profile_list *list);
+void cxi_rxtx_profile_list_unlock(struct cxi_rxtx_profile_list *list);
+
+int cxi_rxtx_profile_list_iterate(struct cxi_rxtx_profile_list *list,
+				  int (*operator)(struct cxi_rxtx_profile *rxtx_profile,
+						void *user_arg),
+				void *user_arg);
+
+int cxi_rxtx_profile_list_insert(struct cxi_rxtx_profile_list *list,
+				 struct cxi_rxtx_profile *rxtx_profile,
+				 unsigned int *rxtx_profile_id);
+int cxi_rxtx_profile_list_remove(struct cxi_rxtx_profile_list *list,
+				 unsigned int rxtx_profile_id);
+int cxi_rxtx_profile_list_retrieve(struct cxi_rxtx_profile_list *list,
+				   unsigned int id,
+				   struct cxi_rxtx_profile **rxtx_profile);
+
+int cxi_rxtx_profile_list_get_ids(struct cxi_rxtx_profile_list *list,
+				  size_t max_ids,
+				  unsigned int *ids,
+				  size_t *num_ids);
+
+#endif /* _CXI_RXTX_PROFILE_LIST_H_ */
diff --git a/drivers/net/ethernet/hpe/ss1/cxi_vf_cmd.h b/drivers/net/ethernet/hpe/ss1/cxi_vf_cmd.h
new file mode 100644
index 000000000000..cc82e2b1a40a
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cxi_vf_cmd.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/* Copyright 2026 Hewlett Packard Enterprise Development LP */
+
+#ifndef _CXI_VF_CMD_H
+#define _CXI_VF_CMD_H
+
+#include <linux/hpe/cxi/cxi.h>
+
+struct cxi_lni_alloc_resp_vf {
+	struct cxi_lni_alloc_resp base;
+	unsigned int rgid;
+};
+
+struct cxi_svc_list_get_resp_vf {
+	struct cxi_svc_list_get_resp base;
+	struct cxi_svc_desc svc_list[];
+};
+
+struct cxi_svc_rsrc_list_get_resp_vf {
+	struct cxi_svc_rsrc_list_get_resp base;
+	struct cxi_rsrc_use rsrc_list[];
+};
+
+struct cxi_ct_alloc_cmd_vf {
+	struct cxi_ct_alloc_cmd base;
+	u64 wb_dma_addr;
+};
+
+struct cxi_ct_wb_update_cmd_vf {
+	struct cxi_ct_wb_update_cmd base;
+	u64 wb_dma_addr;
+};
+
+struct cxi_cq_alloc_buf_cmd_vf {
+	struct cxi_cq_alloc_buf_cmd base;
+	u64 dma_addr;
+	size_t cmds_len;
+};
+
+struct cxi_eq_alloc_cmd_vf {
+	struct cxi_eq_alloc_cmd base;
+	u64 dma_addr;
+	int event_irq_idx;
+	int status_irq_idx;
+};
+
+struct cxi_eq_resize_cmd_vf {
+	struct cxi_eq_resize_cmd base;
+	u64 dma_addr;
+};
+
+#endif /* _CXI_VF_CMD_H */
diff --git a/drivers/net/ethernet/hpe/ss1/pldm_cxi.h b/drivers/net/ethernet/hpe/ss1/pldm_cxi.h
new file mode 100644
index 000000000000..794c59ebcf98
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/pldm_cxi.h
@@ -0,0 +1,374 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright 2021 Hewlett Packard Enterprise Development LP */
+
+/* This file contains Platform Level Data Model (PLDM) definitions
+ * necessary to read numeric sensors and parse FRU record data from
+ * the Cassini uC PLDM subsystem.
+ *
+ * More information can be found in the following DMTF documents
+ * (https://www.dmtf.org):
+ * DSP0240 v1.0.0: PLDM Base Specification
+ * DSP0245 v1.3.0: PLDM IDs and Codes Specification
+ * DSP0248 v1.2.0: PLDM for Platform Monitoring and Control Specification
+ * DSP0257 v1.0.0: PLDM for FRU Data Specification
+ */
+
+#ifndef PLDM_CXI_H
+#define PLDM_CXI_H
+
+#define C_MASK(XVAL, XBIT) XVAL##_MASK = (1 << XBIT)
+#define C_ENUM(XNAME, XVAL) XNAME = XVAL
+
+#define PLDM_THRESHOLD_LIST \
+    C(PLDM_THRESHOLD_UPPER_WARNING, 0), \
+    C(PLDM_THRESHOLD_UPPER_CRITICAL, 1), \
+    C(PLDM_THRESHOLD_UPPER_FATAL, 2), \
+    C(PLDM_THRESHOLD_LOWER_WARNING, 3), \
+    C(PLDM_THRESHOLD_LOWER_CRITICAL, 4), \
+    C(PLDM_THRESHOLD_LOWER_FATAL, 5)
+
+#define C C_ENUM
+enum pldm_threshold {
+    PLDM_THRESHOLD_LIST,
+    PLDM_THRESHOLD_COUNT
+};
+
+#undef C
+
+#define C C_MASK
+enum {
+    PLDM_THRESHOLD_LIST
+};
+
+#undef C
+
+/* Generic PLDM Message Fields (DSP0240 Figure 1) */
+struct pldm_hdr {
+	u8 instance_id:5;
+	u8 rsvd:1;
+	u8 d:1;
+	u8 rq:1;
+
+	u8 pldm_type:6;
+	u8 hdr_ver:2;
+
+	u8 pldm_command_code;
+	u8 payload[0];
+} __packed;
+
+/* PLDM Type Codes (DSP0245 Table 1) */
+enum pldm_type_code {
+	PLDM_TYPE_MESSAGING_CONTROL_AND_DISCOVERY = 0,
+	PLDM_TYPE_SMBIOS,
+	PLDM_TYPE_PLATFORM_MONITORING_AND_CONTROL,
+	PLDM_TYPE_BIOS_CONTROL_AND_CONFIGURATION,
+	PLDM_TYPE_FRU_DATA,
+	PLDM_TYPE_FIRMWARE_UPDATE,
+	PLDM_TYPE_REDFISH_DEVICE,
+	PLDM_TYPE_OEM = 0x3F,
+	PLDM_TYPE_COUNT
+};
+
+/* Generic PLDM Completion Codes (DSP0240 Table 4) */
+enum pldm_completion_code {
+	PLDM_SUCCESS = 0,
+	PLDM_ERROR = 1,
+	PLDM_ERROR_INVALID_DATA = 2,
+	PLDM_ERROR_INVALID_LENGTH = 3,
+	PLDM_ERROR_NOT_READY = 4,
+	PLDM_ERROR_UNSUPPORTED_CMD = 5,
+	PLDM_ERROR_INVALID_PLDM_TYPE = 6,
+	PLDM_ERROR_COMMAND_SPECIFIC_START = 0x80,
+	PLDM_ERROR_COMMAND_SPECIFIC_END = 0xFF
+};
+
+/* PLDM Command Numbers (DSP0248 Table 107) */
+enum pldm_platform_cmd {
+	PLDM_CMD_GET_SENSOR_READING = 0x11,
+	PLDM_CMD_GET_PDR = 0x51
+};
+
+enum pldm_sensor_opstate {
+    PLDM_OPSTATE_ENABLED = 0,
+    PLDM_OPSTATE_DISABLED = 1,
+    PLDM_OPSTATE_UNAVAILABLE = 2,
+    PLDM_OPSTATE_STATUS_UNKNOWN = 3,
+    PLDM_OPSTATE_FAILED = 4,
+    PLDM_OPSTATE_INITIALIZING = 5,
+    PLDM_OPSTATE_SHUTTING_DOWN = 6,
+    PLDM_OPSTATE_IN_TEST = 7
+};
+
+/* PLDM Sensor Units (Table 62 of DSP0248) */
+enum sensor_unit {
+    PLDM_UNIT_NONE = 0,
+    PLDM_UNIT_DEGREES_C = 2,
+    PLDM_UNIT_VOLTS = 5,
+    PLDM_UNIT_AMPS = 6,
+    PLDM_UNIT_WATTS = 7,
+};
+
+enum unit_modifier {
+    PLDM_MODIFIER_NANO = -9,
+    PLDM_MODIFIER_MICRO = -6,
+    PLDM_MODIFIER_MILLI = -3,
+    PLDM_MODIFIER_CENTI = -2,
+    PLDM_MODIFIER_DECI = -1,
+    PLDM_MODIFIER_NONE = 0,
+    PLDM_MODIFIER_KILO = 3,
+};
+
+/* GetSensorReading presentReading variable types (DSP0248 Table 30) */
+union sensor_value {
+	s8 value_SINT8;
+	u8 value_UINT8;
+	s16 value_SINT16;
+	u16 value_UINT16;
+	s32 value_SINT32;
+	u32 value_UINT32;
+};
+
+/* GetSensorReading Command Request Format (DSP0248 Table 30) */
+struct get_sensor_reading_req {
+	struct pldm_hdr hdr;
+	u16 sensor_id;
+	u8 rearm_event_status;
+} __packed;
+
+/* GetSensorReading Command Response Format (DSP0248 Table 30) */
+struct get_sensor_reading_rsp {
+	struct pldm_hdr hdr;
+	u8 completion_code;
+	u8 sensor_data_size;
+	u8 sensor_operational_state;
+	u8 sensor_event_message_enable;
+	u8 present_state;
+	u8 previous_state;
+	u8 event_state;
+	union sensor_value present_reading;
+} __packed;
+
+/* GetPDR Command Request Format (DSP0248 Table 68) */
+struct get_pdr_req {
+	struct pldm_hdr hdr;
+	u32 record_handle;
+	u32 data_transfer_handle;
+	u8 transfer_operation_flag;
+	u16 request_count;
+	u16 record_change_number;
+} __packed;
+
+/* GetPDR Command Response Format (DSP0248 Table 68) */
+struct get_pdr_rsp {
+	struct pldm_hdr hdr;
+	u8 completion_code;
+	u32 next_record_handle;
+	u32 next_data_transfer_handle;
+	u8 transfer_flag;
+	u16 response_count;
+	u8 record_data[];
+} __packed;
+
+/* GetPDR transferOperationFlag values (DSP0248 Table 68) */
+enum pldm_transfer_op {
+	PLDM_XFER_OP_GET_NEXT_PART = 0,
+	PLDM_XFER_OP_GET_FIRST_PART = 1
+};
+
+/* Common PDR Header Format (DSP0248 Table 75) */
+struct pdr_hdr {
+	u32 record_handle;
+	u8 pdr_header_version;
+	u8 pdr_type;
+	u16 record_change_number;
+	u16 data_length;
+	u8 data[0];
+} __packed;
+
+/* PDR Type Values (DSP0248 Table 76) */
+enum pdr_type {
+	PLDM_PDR_TERMINUS_LOCATOR = 1,
+	PLDM_PDR_NUMERIC_SENSOR = 2,
+	PLDM_PDR_STATE_SENSOR = 4,
+	PLDM_PDR_SENSOR_AUXILIARY_NAMES = 6,
+	PLDM_PDR_STATE_EFFECTER = 11,
+	PLDM_PDR_EFFECTER_AUXILIARY_NAMES = 13,
+	PLDM_PDR_ENTITY_ASSOCIATION = 15,
+	PLDM_PDR_ENTITY_AUXILIARY_NAMES = 16,
+	PLDM_PDR_FRU_RECORD_SET = 20,
+	PLDM_PDR_OEM = 127
+};
+
+/* Numeric Sensor PDR sensorDataSize values (DSP0248 Table 78) */
+enum pldm_data_size {
+	PLDM_DATA_SIZE_UINT8,
+	PLDM_DATA_SIZE_SINT8,
+	PLDM_DATA_SIZE_UINT16,
+	PLDM_DATA_SIZE_SINT16,
+	PLDM_DATA_SIZE_UINT32,
+	PLDM_DATA_SIZE_SINT32,
+};
+
+/* The Numeric Sensor PDR has variably sized fields depending on the size of the sensor reading.
+ * To keep the structure packing as simple as possible, unions are used for everything downstream
+ * of the first variably sized field. These sensor size dependent structs are only defined for a
+ * given size (not signedness). They include all Numeric Sensor PDR fields from 'hysteresis' to
+ * 'fatal_low' (DSP0248 Table 78)
+ */
+struct numeric_sensor_ssd8 {
+	u8 hysteresis;
+	u8 supported_thresholds;
+	u8 threshold_and_hysteresis_volatility;
+	float state_transition_interval;
+	float update_interval;
+	u8 max_readable;
+	u8 min_readable;
+	u8 range_field_format;
+	u8 range_field_support;
+	u8 nominal_value;
+	u8 normal_max;
+	u8 normal_min;
+	u8 warning_high;
+	u8 warning_low;
+	u8 critical_high;
+	u8 critical_low;
+	u8 fatal_high;
+	u8 fatal_low;
+} __packed;
+
+struct numeric_sensor_ssd16 {
+	u16 hysteresis;
+	u8 supported_thresholds;
+	u8 threshold_and_hysteresis_volatility;
+	float state_transition_interval;
+	float update_interval;
+	u16 max_readable;
+	u16 min_readable;
+	u8 range_field_format;
+	u8 range_field_support;
+	u16 nominal_value;
+	u16 normal_max;
+	u16 normal_min;
+	u16 warning_high;
+	u16 warning_low;
+	u16 critical_high;
+	u16 critical_low;
+	u16 fatal_high;
+	u16 fatal_low;
+} __packed;
+
+struct numeric_sensor_ssd32 {
+	u32 hysteresis;
+	u8 supported_thresholds;
+	u8 threshold_and_hysteresis_volatility;
+	float state_transition_interval;
+	float update_interval;
+	u32 max_readable;
+	u32 min_readable;
+	u8 range_field_format;
+	u8 range_field_support;
+	u32 nominal_value;
+	u32 normal_max;
+	u32 normal_min;
+	u32 warning_high;
+	u32 warning_low;
+	u32 critical_high;
+	u32 critical_low;
+	u32 fatal_high;
+	u32 fatal_low;
+} __packed;
+
+/* Numeric Sensor PDR Format (DSP0248 Table 78) */
+struct numeric_sensor_pdr {
+	struct pdr_hdr hdr;
+	u16 pldm_terminus_handle;
+	u16 sensor_id;
+	union {
+		struct {
+			u16 entity_type_entity_id :15;
+			u16 entity_type_logical   :1;
+		};
+		u16 entity_type;
+	};
+	u16 entity_instance_number;
+	u16 container_id;
+	u8 sensor_init;
+	u8 sensor_auxiliary_names_pdr;
+	u8 base_unit;
+	s8 unit_modifier;
+	u8 rate_unit;
+	u8 base_oem_unit_handle;
+	u8 aux_unit;
+	s8 aux_unit_modifier;
+	u8 aux_rate_unit;
+	u8 rel;
+	u8 aux_oem_unit_handle;
+	u8 is_linear;
+	u8 sensor_data_size;
+	float resolution;
+	float offset;
+	u16 accuracy;
+	u8 plus_tolerance;
+	u8 minus_tolerance;
+	union {
+		struct numeric_sensor_ssd8 ssd8;
+		struct numeric_sensor_ssd16 ssd16;
+		struct numeric_sensor_ssd32 ssd32;
+	} ssd;
+} __packed;
+
+#define AUX_NAME_MAX  33
+
+/* Sensor Auxiliary Names PDR Format (DSP0248 Table 83) */
+struct aux_name_pdr {
+	struct pdr_hdr hdr;
+	u16 pldm_terminus_handle;
+	u16 sensor_id;
+	u8 sensor_count;
+	u8 name_string_count;           /* Currently hard-coded to a single name */
+	u8 name_language_tag[3];        /* Currently hard-coded to "en" only */
+	u16 sensor_name[AUX_NAME_MAX];
+} __packed;
+
+/* PLDM FRU Field TLV (DSP0257 Table 2) */
+struct pldm_fru_field {
+	u8 field_type;
+	u8 length;
+	u8 value[];
+} __packed;
+
+/* PLDM FRU Record Data Format (DSP0257 Table 2) */
+struct pldm_fru_record {
+	u16 record_set_id;
+	u8 record_type;
+	u8 num_fields;
+	u8 field_encoding;
+	u8 field_data[];
+} __packed;
+
+/* FRU Record Types (DSP0257 Table 4) */
+enum pldm_fru_record_type {
+	PLDM_FRU_RECORD_GENERAL = 1,
+	PLDM_FRU_RECORD_OEM = 254
+};
+
+/* General FRU Record Field Types (DSP0257 Table 5) */
+enum pldm_fru_field_type {
+	PLDM_FRU_FIELD_CHASSIS_TYPE = 1,
+	PLDM_FRU_FIELD_MODEL = 2,
+	PLDM_FRU_FIELD_PART_NUMBER = 3,
+	PLDM_FRU_FIELD_SERIAL_NUMBER = 4,
+	PLDM_FRU_FIELD_MANUFACTURER = 5,
+	PLDM_FRU_FIELD_MANUFACTURE_DATE = 6,
+	PLDM_FRU_FIELD_VENDOR = 7,
+	PLDM_FRU_FIELD_NAME = 8,
+	PLDM_FRU_FIELD_SKU = 9,
+	PLDM_FRU_FIELD_VERSION = 10,
+	PLDM_FRU_FIELD_ASSET_TAG = 11,
+	PLDM_FRU_FIELD_DESCRIPTION = 12,
+	PLDM_FRU_FIELD_ENGINEERING_CHANGE_LEVEL = 13,
+	PLDM_FRU_FIELD_OTHER = 14,
+	PLDM_FRU_FIELD_VENDOR_IANA = 15
+};
+
+#endif /* PLDM_CXI_H */

-- 
2.56.0


^ permalink raw reply	[flat|nested] 25+ messages in thread
* [PATCH 17/23] net: hpe: ss1: add the datapath and memory translation layers
  2026-10-30 20:58 [PATCH 00/23] Subject: [PATCH net-next 00/23] net/hpe: add HPE Slingshot NIC drivers Doug Ledford
                   ` (15 preceding siblings ...)
  2026-10-30 20:59 ` [PATCH 16/23] net: hpe: ss1: add the Cassini core device layer Doug Ledford
@ 2026-10-30 20:59 ` Doug Ledford
  2026-10-30 20:59 ` [PATCH 18/23] net: hpe: ss1: add the link layer glue Doug Ledford
                   ` (6 subsequent siblings)
  23 siblings, 0 replies; 25+ messages in thread
From: Doug Ledford @ 2026-10-30 20:59 UTC (permalink / raw)
  To: Slingshot Open Source Team, Nathan Chancellor, Nicolas Schier,
	Richard Cochran, Andrew Lunn, David S. Miller, Eric Dumazet,
	Jakub Kicinski, Paolo Abeni, Sumit Semwal, Christian König,
	Guenter Roeck
  Cc: linux-kernel, netdev, linux-kbuild, Doug Ledford, Iraimani P,
	Sandeep Bhoot, Mamila Santosh

Add the datapath: event and command queues, counting events, the ATU
and ATS (address translation) layers, the RMU, the NTA and P2P/DMA
mapping.

When pinning user memory for buffers the device keeps mapped
(event queues, counting event write-back), pages are now pinned with
FOLL_LONGTERM, and event queue pages the device wrote are dirtied
before they are unpinned so data written by the device is not lost on
reclaim.  The counting event write-back path drops its page pin when
the DMA mapping fails, so the PF and VF error paths do not leak it.

cass_p2p.c refuses device memory when no GPU backend is registered;
previously a missing backend left a NULL callback that was then
called.  When EQ interrupts are re-attached all callback and data
pointers are replaced, including with NULL, so a stale callback cannot
be reused with a NULL interrupt object.

The inbound-wait hardware failure latch lives in the per-adapter ATU
state under the adapter's own mutex, so a failure on one NIC does not
block waits on another.

Known open issues in VF paths, deferred to the V2 SR-IOV update:

- Sashiko H51: the VF CT and EQ free paths can leak their private
  allocations when the PF does not reply.
- Sashiko M48: cxi_cq_ack_counter_vf() returns a negative errno from the
  PF mailbox through an unsigned counter API.
- Sashiko M50: VF CQ free returns early on a PF RPC error while the
  queue backing may still be DMA-active.

Open hardware question (Sashiko H50, finding fixed): the DMAC wait is
bounded, and the engine is disabled and its interrupt drained before the
completion descriptor is read. Whether clearing C_PI_CFG_DMAC ENABLE
guarantees that no further host writes occur is being confirmed with the
hardware engineers. Current callers keep their DMA buffers for the
lifetime of the device.

Known limitation, deferred to V2: this patch carries SR-IOV
virtual-function code (VF-to-PF mailbox requests, mailbox opcodes or VF
resource handling) from an older, incomplete version of the Cassini
SR-IOV support. V2 of this series will include the updated SR-IOV
implementation, so issues in the VF paths should be ignored for now.

checkpatch --strict (100 columns) still reports the following in this
patch. They need coordination with the internal repositories this code
is maintained in and will be fixed in V2:
- WARNING: ALLOC_WITH_SIZEOF (19), BLOCK_COMMENT_STYLE (2),
  SUSPECT_CODE_INDENT (2), AVOID_BUG (1), AVOID_EXTERNS (1),
  DEPRECATED_API (1), LONG_LINE (1), VOLATILE (1)
- CHECK: UNNECESSARY_PARENTHESES (13), COMPARISON_TO_NULL (12), BRACES
  (4), BIT_MACRO (3), ALLOC_SIZEOF_STRUCT (2), MACRO_ARG_REUSE (2),
  ASSIGNMENT_CONTINUATIONS (1), CAMELCASE (1), MACRO_ARG_PRECEDENCE (1),
  OPEN_ENDED_LINE (1)

Co-developed-by: Iraimani P <iraimani.pavadai@hpe.com>
Signed-off-by: Iraimani P <iraimani.pavadai@hpe.com>
Co-developed-by: Sandeep Bhoot <sandeep.bhoot@hpe.com>
Signed-off-by: Sandeep Bhoot <sandeep.bhoot@hpe.com>
Co-developed-by: Mamila Santosh <santosh-kumar.mamila@hpe.com>
Signed-off-by: Mamila Santosh <santosh-kumar.mamila@hpe.com>
Signed-off-by: Doug Ledford <doug.ledford@hpe.com>
---
 drivers/net/ethernet/hpe/ss1/cass_ats.c           |  299 +++
 drivers/net/ethernet/hpe/ss1/cass_ats_inval.c     |   79 +
 drivers/net/ethernet/hpe/ss1/cass_atu.c           | 2072 +++++++++++++++++++++
 drivers/net/ethernet/hpe/ss1/cass_cq.c            | 1243 ++++++++++++
 drivers/net/ethernet/hpe/ss1/cass_ct.c            |  639 +++++++
 drivers/net/ethernet/hpe/ss1/cass_dmac.c          |  597 ++++++
 drivers/net/ethernet/hpe/ss1/cass_eq.c            | 1518 +++++++++++++++
 drivers/net/ethernet/hpe/ss1/cass_nta.c           | 1996 ++++++++++++++++++++
 drivers/net/ethernet/hpe/ss1/cass_p2p.c           |  321 ++++
 drivers/net/ethernet/hpe/ss1/cass_rmu.c           |  376 ++++
 drivers/net/ethernet/hpe/ss1/cass_rmu_eth.c       | 1017 ++++++++++
 drivers/net/ethernet/hpe/ss1/cass_rx_tx_profile.c |  104 ++
 12 files changed, 10261 insertions(+)

diff --git a/drivers/net/ethernet/hpe/ss1/cass_ats.c b/drivers/net/ethernet/hpe/ss1/cass_ats.c
new file mode 100644
index 000000000000..f1642317abb6
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_ats.c
@@ -0,0 +1,299 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2019, 2024-2026 Hewlett Packard Enterprise Development LP */
+
+/*
+ * Address Translation Unit (ATU) management
+ * ATS functionality
+ */
+
+#include <linux/pci.h>
+#include <linux/types.h>
+#include <linux/iommu.h>
+
+#include "cass_core.h"
+
+/* PCIe IP PF0_PORT_LOGIC register */
+#define SYMBOL_TIMER_FILTER_1_OFF 0x71c
+#define CX_FLT_MASK_CPL_LEN_MATCH (1 << 26)
+#define FILTER_MASK_2_OFF 0x720
+#define CX_FLT_UNMASK_ATS_SPECIFIC_RULES (1 << 10)
+
+#define ATU_NUM_PASIDS ATU_PHYS_AC
+#define MAX_PAGE_REQS 512
+
+#ifdef CONFIG_IOMMU_SVA
+
+static bool enable_ats = true;
+module_param(enable_ats, bool, 0644);
+MODULE_PARM_DESC(enable_ats, "Enable Address Translation Services (PCIe ATS)");
+
+static bool odp_mode_nic_pri;
+module_param(odp_mode_nic_pri, bool, 0644);
+MODULE_PARM_DESC(odp_mode_nic_pri,
+		 "ODP mode used for ATS. ATS_PRS:0, NIC_PRI:1");
+
+static int cass_bind_sva(struct pci_dev *pdev, struct cass_ac *cac)
+{
+	u32 pasid;
+	struct iommu_sva *sva;
+
+	sva = iommu_sva_bind_device(&pdev->dev, current->mm);
+	if (IS_ERR(sva)) {
+		pr_err("iommu_sva_bind_device failed ret:%ld\n", PTR_ERR(sva));
+		return PTR_ERR(sva);
+	}
+
+	pasid = iommu_sva_get_pasid(sva);
+	if (pasid == IOMMU_PASID_INVALID) {
+		pr_err("pasid invalid\n");
+		iommu_sva_unbind_device(sva);
+		return -ENODEV;
+	}
+
+	cac->sva = sva;
+	cac->pasid = pasid;
+
+	return 0;
+}
+
+static void cass_unbind_sva(const struct cass_ac *cac)
+{
+	iommu_sva_unbind_device(cac->sva);
+}
+
+/**
+ * cass_bind_ac() - Bind an address context to the current task.
+ *
+ * @hw:  Cassini device
+ * @cac: Cassini AC struct
+ *
+ * @return: 0 on success
+ */
+static int cass_bind_ac(struct cass_dev *hw, struct cass_ac *cac)
+{
+	struct pci_dev *pdev = hw->cdev.pdev;
+
+	if (!pdev->ats_enabled) {
+		cxidev_dbg(&hw->cdev, "ATS not enabled\n");
+		return -EOPNOTSUPP;
+	}
+
+	if (!pdev->pasid_enabled) {
+		cxidev_dbg(&hw->cdev, "PASID not enabled\n");
+		return -EOPNOTSUPP;
+	}
+
+	return cass_bind_sva(pdev, cac);
+}
+
+/**
+ * cass_unbind_ac() - Unbind an address context. Called during AC cleanup.
+ *
+ * @hw:  Cassini device
+ * @cac: Cassini AC struct
+ */
+void cass_unbind_ac(struct cass_dev *hw, const struct cass_ac *cac)
+{
+	if (!enable_ats)
+		return;
+
+	if (cac->sva)
+		cass_unbind_sva(cac);
+}
+
+void cass_iommu_fini(struct cass_dev *hw)
+{
+}
+
+/**
+ * cass_iommu_init() - Initialize the AMD/Intel IOMMU for the physical device
+ *
+ * If the IOMMU is not enabled or available, ATS mode is not supported.
+ *
+ * @hw: Cassini device
+ */
+void cass_iommu_init(struct cass_dev *hw)
+{
+	int pos;
+	u32 filter_mask;
+	u32 max_requests;
+	struct pci_dev *pdev = hw->cdev.pdev;
+
+	/*
+	 * Mask length match for completions.
+	 * The PCI interface checks if the completion length matches
+	 * the requested length. Unfortunately, this is not the case for
+	 * ATS transactions as only pages that are present are returned
+	 * so enable Mask length match for Cassini 1.
+	 */
+	if (cass_version(hw, CASSINI_1)) {
+		pci_read_config_dword(pdev, SYMBOL_TIMER_FILTER_1_OFF,
+				      &filter_mask);
+		filter_mask |= CX_FLT_MASK_CPL_LEN_MATCH;
+		pci_write_config_dword(pdev, SYMBOL_TIMER_FILTER_1_OFF,
+				       filter_mask);
+	}
+
+	/*
+	 * Enable CX_FLT_UNMASK_ATS_SPECIFIC_RULES for C2.
+	 *
+	 * Cassini 2 has a new capability which uses
+	 * CX_FLT_UNMASK_ATS_SPECIFIC_RULES. The PCI controller used by
+	 * C2 has a reference section which states the following:
+	 * Lower Address is not checked for Cpls related to ATS Requests.
+	 * An ATS-related Cpl completes the request if it has a Byte Count
+	 * that is equal to four times the Length field.
+	 */
+	if (cass_version(hw, CASSINI_2)) {
+		pci_read_config_dword(pdev, FILTER_MASK_2_OFF, &filter_mask);
+		filter_mask |= CX_FLT_UNMASK_ATS_SPECIFIC_RULES;
+		pci_write_config_dword(pdev, FILTER_MASK_2_OFF, filter_mask);
+	}
+
+	/*
+	 * The AMD IOMMU is currently hardcoding max requests to 32.
+	 * Set to MAX_PAGE_REQS.
+	 */
+	pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
+	if (!pos) {
+		dev_warn(&pdev->dev, "Error: PRI extended capability in PCI config not present\n");
+		return;
+	}
+
+	pci_read_config_dword(pdev, pos + PCI_PRI_MAX_REQ, &max_requests);
+	max_requests = min_t(u32, max_requests, (u32)MAX_PAGE_REQS);
+	pdev->pri_reqs_alloc = max_requests;
+	pci_write_config_dword(pdev, pos + PCI_PRI_ALLOC_REQ, max_requests);
+}
+
+/**
+ * cass_ats_init() - Initialize an AC using either ATS or ATS passthrough
+ *                   and bind the AC to the current task
+ *
+ * @lni_priv: Private LNI struct
+ * @m_opts: User map options
+ * @cac:    Cassini AC struct
+ *
+ * @return: 0 on success, negative value on failure
+ */
+int cass_ats_init(struct cxi_lni_priv *lni_priv,
+		  struct ac_map_opts *m_opts,
+		  struct cass_ac *cac)
+{
+	int ret;
+	bool privileged = !(m_opts->flags & CXI_MAP_USER_ADDR);
+	union c_atu_cfg_ac_table *ac = &cac->cfg_ac;
+	struct cxi_dev *cdev = lni_priv->dev;
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	bool have_pri = hw->cdev.pdev->pri_enabled;
+
+	if (!enable_ats)
+		return -EOPNOTSUPP;
+
+	ret = cass_bind_ac(hw, cac);
+	if (ret)
+		return ret;
+
+	if (m_opts->flags & CXI_MAP_ATS_PT)
+		ac->ta_mode = C_ATU_PASSTHROUGH_MODE;
+	else if (m_opts->flags & CXI_MAP_ATS_DYN)
+		ac->ta_mode = C_ATU_ATS_DYNAMIC_MODE;
+	else
+		ac->ta_mode = C_ATU_ATS_MODE;
+
+	m_opts->iova = m_opts->va_start;
+	cac->iova_base = 0;
+	cac->iova_len = m_opts->flags & CXI_MAP_USER_ADDR ?
+				TASK_SIZE : ULONG_MAX;
+	cac->iova_end = cac->iova_base + cac->iova_len - 1;
+
+	ac->cntr_pool_id = 1;
+	ac->ats_vf_en = lni_priv->is_vf;
+	ac->ats_vf_num = lni_priv->is_vf ? lni_priv->vf_num : 0;
+	ac->ats_no_write = 0;
+	ac->ats_pasid = cac->pasid;
+	ac->ats_pasid_en = 1;
+	ac->ats_pasid_er = 0;
+	ac->ats_pasid_pmr = !!privileged;
+	ac->mem_base = cac->iova_base >> ATU_CFG_AC_TABLE_MB_SHIFT;
+	ac->mem_size = cac->iova_len >> C_ADDR_SHIFT;
+	ac->odp_mode = have_pri && !odp_mode_nic_pri ?
+			C_ATU_ODP_MODE_ATS_PRS : C_ATU_ODP_MODE_NIC_PRI;
+
+	return 0;
+}
+
+/**
+ * cass_ats_md_init() - Pin ATS pages or set up notifier
+ *
+ * When using ODP with NIC_PRI mode, the mmu notifier will be initialized
+ * for this descriptor. If pinning, just pin the pages.
+ *
+ * @md_priv: Private memory descriptor
+ * @m_opts:  User options containing the IOVA range
+ *
+ * @return: Success or -ENOMEM
+ */
+int cass_ats_md_init(struct cxi_md_priv *md_priv,
+		     const struct ac_map_opts *m_opts)
+{
+	int ret;
+	int write = m_opts->flags & CXI_MAP_WRITE;
+	int npages = md_priv->md.len >> md_priv->md.page_shift;
+	struct page **pages;
+	size_t size = npages * sizeof(*pages);
+	struct cass_dev *hw = container_of(md_priv->lni_priv->dev,
+					   struct cass_dev, cdev);
+
+	if (!enable_ats)
+		return -EOPNOTSUPP;
+
+	if (!(m_opts->flags & CXI_MAP_PIN)) {
+		if (odp_mode_nic_pri || !hw->cdev.pdev->pri_enabled)
+			return cass_mmu_notifier_insert(md_priv, m_opts);
+
+		return 0;
+	}
+
+	pages = kvmalloc(size, GFP_KERNEL);
+	if (!pages)
+		return -ENOMEM;
+
+	ret = cass_pin(md_priv->cac, pages, npages, md_priv->md.va, write);
+
+	if (ret) {
+		kvfree(pages);
+		return ret;
+	}
+
+	md_priv->pages = pages;
+
+	return ret;
+}
+
+#else /* CONFIG_IOMMU_SVA */
+void cass_unbind_ac(struct cass_dev *hw, const struct cass_ac *cac)
+{
+}
+
+void cass_iommu_fini(struct cass_dev *hw)
+{
+}
+
+void cass_iommu_init(struct cass_dev *hw)
+{
+}
+
+int cass_ats_init(struct cxi_lni_priv *lni_priv,
+		  struct ac_map_opts *m_opts,
+		  struct cass_ac *cac)
+{
+	return -ENODEV;
+}
+
+int cass_ats_md_init(struct cxi_md_priv *md_priv,
+		     const struct ac_map_opts *m_opts)
+{
+	return -ENODEV;
+}
+#endif /* !CONFIG_IOMMU_SVA */
diff --git a/drivers/net/ethernet/hpe/ss1/cass_ats_inval.c b/drivers/net/ethernet/hpe/ss1/cass_ats_inval.c
new file mode 100644
index 000000000000..39a1a683d85e
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_ats_inval.c
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2022 Hewlett Packard Enterprise Development LP */
+
+#ifdef CONFIG_AMD_IOMMU
+
+#include <linux/module.h>
+#include <linux/amd-iommu.h>
+
+#include "cass_core.h"
+
+/*
+ * ATS invalidate interface for Cassini 1.1
+ */
+
+typedef void (*amd_iommu_invalidate_range)(struct pci_dev *pdev,
+					   int pasid, unsigned long start,
+					   unsigned long end);
+int amd_iommu_set_invalidate_range_cb(struct pci_dev *pdev,
+				      amd_iommu_invalidate_range cb);
+
+/**
+ * cass_ats_invalidate_range_cb() - Callback from the AMD IOMMU to invalidate
+ *				    and address range.
+ *
+ * @pdev: PCI device
+ * @pasid: The process address space ID.
+ * @start: Start of address range
+ * @end: End of address range
+ */
+static void cass_ats_invalidate_range_cb(struct pci_dev *pdev, int pasid,
+					 unsigned long start, unsigned long end)
+{
+
+	struct cass_dev *hw = pci_get_drvdata(pdev);
+	struct cass_ac *cac;
+
+	cac = cass_cac_get(hw, pasid);
+	if (!cac)
+		return;
+
+	pr_debug("pasid:%d start:%lx end:%lx\n", pasid, start, end);
+
+	cass_invalidate_range(cac, start, end - start);
+	atomic_inc(&hw->dcpl_ats_mn_inval);
+	cass_cac_put(cac);
+}
+
+/**
+ * cass_amd_iommu_inval_cb_init() - Initialize the invalidation callback.
+ *
+ * @pdev: PCI device
+ */
+void cass_amd_iommu_inval_cb_init(struct pci_dev *pdev)
+{
+	int (*set_inval_range_cb)(struct pci_dev *pdev,
+				  amd_iommu_invalidate_range cb);
+	struct cass_dev *hw = pci_get_drvdata(pdev);
+	int ret;
+
+	/* Only set up invalidation callback for Cassini 1 */
+	if (!cass_version(hw, CASSINI_1))
+		return;
+
+	set_inval_range_cb = symbol_get(amd_iommu_set_invalidate_range_cb);
+	if (set_inval_range_cb) {
+		ret = set_inval_range_cb(pdev, cass_ats_invalidate_range_cb);
+		if (ret) {
+			dev_WARN(&pdev->dev,
+				 "Error setting invalidation callback (%d)\n",
+				 ret);
+		} else {
+			hw->ats_c1_odp_enable = true;
+		}
+
+		symbol_put(amd_iommu_set_invalidate_range_cb);
+	}
+}
+
+#endif /* CONFIG_AMD_IOMMU */
diff --git a/drivers/net/ethernet/hpe/ss1/cass_atu.c b/drivers/net/ethernet/hpe/ss1/cass_atu.c
new file mode 100644
index 000000000000..6e80024dbc37
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_atu.c
@@ -0,0 +1,2072 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2018, 2024-2026 Hewlett Packard Enterprise Development LP */
+
+/* Address Translation Unit (ATU) management */
+
+#include <linux/interrupt.h>
+#include <linux/types.h>
+#include <linux/hugetlb.h>
+#include <linux/iova.h>
+#include <linux/bvec.h>
+#include <linux/iopoll.h>
+#include <linux/workqueue.h>
+#include <linux/random.h>
+
+#include "cass_core.h"
+#include "cass_ss1_debugfs.h"
+
+int more_debug;
+module_param(more_debug, int, 0644);
+MODULE_PARM_DESC(more_debug, "More debug");
+
+static int default_ptg_mode = C_ATU_PTG_MODE_DBL_C;
+module_param(default_ptg_mode, int, 0644);
+MODULE_PARM_DESC(default_ptg_mode, "Default PTG Mode");
+
+/* Invalidation interval is 2^(inval_process_interval+1) - 10 is ~2 uS */
+static int inval_process_interval = 10;
+module_param(inval_process_interval, int, 0644);
+MODULE_PARM_DESC(inval_process_interval, "ATS invalidate processing interval");
+
+/* Relaxed ordering bits test */
+static bool acxt_mem_rd_ro;
+module_param(acxt_mem_rd_ro, bool, 0644);
+MODULE_PARM_DESC(acxt_mem_rd_ro, "Memory Read Relaxed Ordering");
+static bool acxt_flush_req_ro;
+module_param(acxt_flush_req_ro, bool, 0644);
+MODULE_PARM_DESC(acxt_flush_req_ro, "Flush Request Relaxed Ordering");
+static bool acxt_translation_req_ro;
+module_param(acxt_translation_req_ro, bool, 0644);
+MODULE_PARM_DESC(acxt_translation_req_ro, "Translation Request Relaxed Ordering");
+static bool acxt_fetching_amo_ro;
+module_param(acxt_fetching_amo_ro, bool, 0644);
+MODULE_PARM_DESC(acxt_fetching_amo_ro, "Fetching AMO Relaxed Ordering");
+static bool acxt_ido;
+module_param(acxt_ido, bool, 0644);
+MODULE_PARM_DESC(acxt_ido, "ID-Based Ordering");
+
+static bool ac_salt = true;
+module_param(ac_salt, bool, 0644);
+MODULE_PARM_DESC(ac_salt, "Add salt to ACs");
+
+static bool acxt_ph_en;
+module_param(acxt_ph_en, bool, 0644);
+MODULE_PARM_DESC(acxt_ph_en, "Enable use of Processing Hints and Steering Tag");
+static u8 acxt_phints;
+module_param(acxt_phints, byte, 0644);
+MODULE_PARM_DESC(acxt_phints, "TLP Processing Hints");
+static u8 acxt_steering_tag;
+module_param(acxt_steering_tag, byte, 0644);
+MODULE_PARM_DESC(acxt_steering_tag, "Steering Tag");
+
+bool ats_c1_override;
+module_param(ats_c1_override, bool, 0644);
+MODULE_PARM_DESC(ats_c1_override, "Override ODP Enable for ATS with C1");
+
+/* Use a larger base page size when huge_shift - page_shift is greater
+ * than the maximum page table size (max-threshold) allowed. This allows
+ * us to support 256, 512 and 1024 MB Cray hugepage sizes.
+ */
+static int hugepage_threshold = 1;
+module_param(hugepage_threshold, int, 0644);
+MODULE_PARM_DESC(hugepage_threshold, "Threshold to increase base page size.");
+
+void cass_atu_fini(struct cass_dev *hw)
+{
+	cxi_unregister_hw_errors(hw, &hw->atu_err);
+	iova_cache_put();
+	dma_unmap_single(&hw->cdev.pdev->dev, hw->oxe_dummy_dma_addr,
+			 PAGE_SIZE, DMA_TO_DEVICE);
+	kfree(hw->oxe_dummy_addr);
+	ida_destroy(&hw->atu_table);
+	cass_iommu_fini(hw);
+	cass_nta_pri_fini(hw);
+	cass_nta_cq_fini(hw);
+	refcount_dec(&hw->refcount);
+}
+
+/* Atomically write an Address Context */
+static void cass_write_ac(struct cass_dev *hw, union c_atu_cfg_ac_table *ac,
+			  unsigned int index, bool user, bool is_physac,
+			  bool vf_en, int vf_num)
+{
+	union c_pi_cfg_acxt pi_cfg_acxt = {
+		.ac_en = ac->context_en,
+	};
+
+	pi_cfg_acxt.vf_en = vf_en;
+	pi_cfg_acxt.vf_num = vf_num;
+
+	if (ac->ta_mode != C_ATU_NTA_MODE) {
+		pi_cfg_acxt.pasid = ac->ats_pasid;
+		pi_cfg_acxt.pasid_en = ac->ats_pasid_en;
+		pi_cfg_acxt.pasid_er = ac->ats_pasid_er;
+		pi_cfg_acxt.pasid_pmr = ac->ats_pasid_pmr;
+	}
+
+	pi_cfg_acxt.mem_rd_ro = acxt_mem_rd_ro;
+	pi_cfg_acxt.flush_req_ro = acxt_flush_req_ro;
+	pi_cfg_acxt.translation_req_ro = acxt_translation_req_ro;
+	pi_cfg_acxt.fetching_amo_ro = acxt_fetching_amo_ro;
+	pi_cfg_acxt.ido = acxt_ido;
+
+	if (acxt_ph_en && user) {
+		pi_cfg_acxt.ph_en = acxt_ph_en;
+		pi_cfg_acxt.phints = acxt_phints;
+		pi_cfg_acxt.steering_tag = acxt_steering_tag;
+	}
+
+	if (ac_salt) {
+		u32 rand = get_random_u32();
+
+		ac->ptn_salt = rand;
+		ac->idx_salt = rand >> 2;
+	}
+
+	spin_lock(&hw->atu_shadow_lock);
+	cass_config_ac(hw, index, ac);
+	spin_unlock(&hw->atu_shadow_lock);
+
+	/* WORKAROUND: Cassini ERRATA-3277
+	 * When disabling an AC, invalidate before disabling the ACXT.
+	 */
+	if (!is_physac && cass_version(hw, CASSINI_1) && !ac->context_en) {
+		struct cass_ac *cac = container_of(ac, struct cass_ac, cfg_ac);
+
+		cass_invalidate_range(cac, 0, ATUCQ_INVALIDATE_ALL);
+	}
+
+	cass_config_pi_acxt(hw, index, &pi_cfg_acxt);
+}
+
+/* Callback registered with the interrupt error handler, executed when
+ * C_ATU_ERR_FLG.PRB_EXPIRED error interrupt is detected.
+ */
+static void cass_prb_exp_cb(struct cass_dev *hw, unsigned int irq,
+			    bool is_ext, unsigned int bitn)
+{
+	queue_work(hw->prb_wq, &hw->prb_work);
+}
+
+int cass_atu_init(struct cass_dev *hw)
+{
+	int i;
+	int ret;
+	union c_atu_cfg_nta cfg_nta = {
+		.acid = ATU_NTA_DEF_PI_ACXT,
+	};
+	union c_atu_cfg_ac_table ac = {
+		.context_en = 1,
+		.ta_mode = C_ATU_PASSTHROUGH_MODE,
+	};
+	union c_oxe_cfg_dummy_addr oxe_dummy = {
+		.ac = ATU_PHYS_AC
+	};
+	union c_atu_cfg_ats cfg_ats;
+
+	ac.mem_size = ~ac.mem_size;
+
+	hw->oxe_dummy_addr = kcalloc(1, PAGE_SIZE, GFP_KERNEL);
+	if (hw->oxe_dummy_addr == NULL)
+		return -ENOMEM;
+
+	ida_init(&hw->atu_table);
+	refcount_inc(&hw->refcount);
+	spin_lock_init(&hw->cac_table_lock);
+	spin_lock_init(&hw->atu_shadow_lock);
+	mutex_init(&hw->odpq_mutex);
+	atomic_set(&hw->stats.md, 0);
+	atomic_set(&hw->atu_error_inject, 0);
+	atomic_set(&hw->atu_odp_requests, 0);
+	atomic_set(&hw->atu_odp_fails, 0);
+	atomic_set(&hw->atu_prb_expired, 0);
+	atomic_set(&hw->dcpl_md_clear_inval, 0);
+	atomic_set(&hw->dcpl_nta_mn_inval, 0);
+	atomic_set(&hw->dcpl_ats_mn_inval, 0);
+	atomic_set(&hw->dcpl_comp_wait, 0);
+	atomic_set(&hw->dcpl_entered, 0);
+	atomic_set(&hw->dcpl_ixe_cntr_0, 0);
+	atomic_set(&hw->dcpl_ixe_cntr_dec_0, 0);
+	atomic_set(&hw->dcpl_ee_cntr_dec_0, 0);
+	atomic_set(&hw->dcpl_ee_cntr_stuck, 0);
+	atomic_set(&hw->dcpl_oxe_cntr_dec_0, 0);
+	atomic_set(&hw->dcpl_oxe_cntr_stuck, 0);
+	atomic_set(&hw->dcpl_ixe_cntr_stuck, 0);
+	atomic_set(&hw->dcpl_success, 0);
+	atomic_set(&hw->dcpl_ibw_cntr_dec_0_62, 0);
+	atomic_set(&hw->dcpl_ibw_cntr_dec_0_62_count, 0);
+	atomic_set(&hw->dcpl_ibw_cntr_dec_0_64, 0);
+	atomic_set(&hw->dcpl_ibw_cntr_dec_0_64_count, 0);
+	atomic_set(&hw->dcpl_ibw_active_stuck, 0);
+	atomic_set(&hw->dcpl_ibw_idle_wait, 0);
+	atomic_set(&hw->dcpl_ibw_cntr_is_0, 0);
+	atomic_set(&hw->dcpl_ibw_issued, 0);
+	hw->dcpl_max_time = 0;
+	for (i = 0; i < DBINS; i++)
+		hw->dcpl_time[i] = 0;
+	hw->pri_max_md_time = 0;
+	hw->pri_max_fault_time = 0;
+	for (i = 0; i < MDBINS; i++)
+		hw->pri_md_time[i] = 0;
+	for (i = 0; i < FBINS; i++)
+		hw->pri_fault_time[i] = 0;
+
+	cass_write_ac(hw, &ac, ATU_PHYS_AC, false, false,
+		      ac.ats_vf_en, ac.ats_vf_num);
+	cass_write(hw, C_ATU_CFG_NTA, &cfg_nta, sizeof(union c_atu_cfg_nta));
+
+	hw->oxe_dummy_dma_addr = dma_map_single(&hw->cdev.pdev->dev,
+						hw->oxe_dummy_addr, PAGE_SIZE,
+						DMA_TO_DEVICE);
+	if (dma_mapping_error(&hw->cdev.pdev->dev, hw->oxe_dummy_dma_addr)) {
+		ret = -ENOMEM;
+		goto free_dummy;
+	}
+	oxe_dummy.subaddr = hw->oxe_dummy_dma_addr >> C_ADDR_SHIFT;
+	cass_write(hw, C_OXE_CFG_DUMMY_ADDR, &oxe_dummy,
+		   sizeof(union c_oxe_cfg_dummy_addr));
+
+	cass_read(hw, C_ATU_CFG_ATS, &cfg_ats.qw, sizeof(cfg_ats));
+
+	/* The simulator runs much slower so we need to change the
+	 * invalidate processing interval to a lower value.
+	 * The AMD IOMMU (in Epyc processors earlier than the 7002 series)
+	 * has bug where it returns multiple translations
+	 * with the same address if the page size is larger than the
+	 * STU size. Setting truncate_gt_stu_rsp is a workaround.
+	 * Cassini ERRATA-2431
+	 */
+	if (HW_PLATFORM_Z1(hw)) {
+		cfg_ats.inval_process_interval = 5;
+		cfg_ats.truncate_gt_stu_rsp = 1;
+	}
+
+	/* The inval_process_interval default causes IOMMU timeouts. */
+	if (HW_PLATFORM_ASIC(hw))
+		cfg_ats.inval_process_interval = inval_process_interval;
+
+	if (HW_PLATFORM_Z1(hw) || HW_PLATFORM_ASIC(hw))
+		cass_write(hw, C_ATU_CFG_ATS, &cfg_ats, sizeof(cfg_ats));
+
+	if (!cass_version(hw, CASSINI_1))
+		odp_sw_decouple = false;
+
+	if (cass_version(hw, CASSINI_1)) {
+		/* Errata 3117 */
+		union c1_atu_cfg_odp_decouple odp_decouple;
+
+		cass_read(hw, C1_ATU_CFG_ODP_DECOUPLE, &odp_decouple,
+			  sizeof(odp_decouple));
+		odp_decouple.flush_req_delay = ATU_FLUSH_REQ_DELAY;
+		odp_decouple.enable = odp_sw_decouple ? 0 : 1;
+		cass_write(hw, C1_ATU_CFG_ODP_DECOUPLE, &odp_decouple,
+			   sizeof(odp_decouple));
+	}
+
+	ret = cass_nta_cq_init(hw);
+	if (ret)
+		goto cq_init_fail;
+
+	ret = cass_nta_pri_init(hw);
+	if (ret)
+		goto pri_init_fail;
+
+	iova_cache_get();
+	cass_iommu_init(hw);
+
+	/* Register callback for C_ATU_ERR_FLG.PRB_EXPIRED bit */
+	hw->atu_err.irq = C_ATU_IRQA_MSIX_INT;
+	hw->atu_err.is_ext = false;
+	hw->atu_err.err_flags.atu.prb_expired = 1;
+	hw->atu_err.cb = cass_prb_exp_cb;
+	cxi_register_hw_errors(hw, &hw->atu_err);
+
+	return 0;
+
+pri_init_fail:
+	cass_nta_cq_fini(hw);
+
+cq_init_fail:
+	refcount_dec(&hw->refcount);
+	dma_unmap_single(&hw->cdev.pdev->dev, hw->oxe_dummy_dma_addr,
+			 PAGE_SIZE, DMA_TO_DEVICE);
+free_dummy:
+	kfree(hw->oxe_dummy_addr);
+
+	return ret;
+}
+
+static void cass_md_list_free(struct cass_ac *cac)
+{
+	struct cxi_md_priv *tmp;
+	struct cxi_md_priv *le;
+
+	mutex_lock(&cac->md_mutex);
+
+	list_for_each_entry_safe(le, tmp, &cac->md_list, md_entry) {
+		list_del(&le->md_entry);
+		refcount_dec(&cac->refcount);
+		cass_md_clear(le, false, true);
+		kfree(le);
+	}
+
+	mutex_unlock(&cac->md_mutex);
+}
+
+/**
+ * cass_cac_get - Pin a published Address Context for a reader
+ *
+ * @hw:  Cassini device
+ * @acid: Address Context ID
+ */
+struct cass_ac *cass_cac_get(struct cass_dev *hw, int acid)
+{
+	struct cass_ac *cac;
+	unsigned long flags;
+
+	if (acid < 0 || acid >= ARRAY_SIZE(hw->cac_table))
+		return NULL;
+
+	spin_lock_irqsave(&hw->cac_table_lock, flags);
+	cac = hw->cac_table[acid];
+	if (cac && !refcount_inc_not_zero(&cac->reader_refs))
+		cac = NULL;
+	spin_unlock_irqrestore(&hw->cac_table_lock, flags);
+
+	return cac;
+}
+
+void cass_cac_put(struct cass_ac *cac)
+{
+	if (cac && refcount_dec_and_test(&cac->reader_refs))
+		complete(&cac->readers_done);
+}
+
+static void cass_cac_unpublish(struct cass_dev *hw, struct cass_ac *cac)
+{
+	int acid = cac->ac.acid;
+	unsigned long flags;
+
+	spin_lock_irqsave(&hw->cac_table_lock, flags);
+	hw->cac_table[acid] = NULL;
+	spin_unlock_irqrestore(&hw->cac_table_lock, flags);
+
+	cass_cac_put(cac);
+	wait_for_completion(&cac->readers_done);
+}
+
+static void cass_cac_free(struct cass_dev *hw, struct cass_ac *cac)
+{
+	int acid = cac->ac.acid;
+
+	if (!refcount_dec_and_test(&cac->refcount)) {
+		cxidev_WARN_ONCE(&hw->cdev, true,
+				 "Resource leaks - AC refcount not zero: %d\n",
+				 refcount_read(&cac->refcount));
+		return;
+	}
+
+	kfree(cac);
+	ida_free(&hw->atu_table, acid);
+}
+
+static void cass_ac_init(struct cass_ac *cac, const struct ac_map_opts *m_opts)
+{
+	union c_atu_cfg_ac_table *ac = &cac->cfg_ac;
+	struct cass_dev *hw = container_of(cac->lni_priv->dev,
+					   struct cass_dev, cdev);
+
+	ac->pg_table_size = cac->huge_shift - cac->page_shift;
+	ac->base_pg_size = cac->page_shift - C_ADDR_SHIFT;
+	ac->ptg_mode = cac->ptg_mode;
+	ac->do_not_cache = !!(cac->flags & CXI_MAP_NOCACHE);
+	ac->odp_en = !(cass_version(hw, CASSINI_1_0) ||
+		       (cac->flags & CXI_MAP_PIN));
+	ac->do_not_filter = hw->ac_filter_disabled;
+	ac->context_en = 1;
+
+	pr_debug("page_shift:%d huge_shift:%d base_pg_sz:%d pg_table_sz:%d\n",
+		 cac->page_shift, cac->huge_shift, ac->base_pg_size,
+		 ac->pg_table_size);
+}
+
+/**
+ * cass_lac_free() - Unmap an AC from the LNI's resource group.
+ *
+ * @lni_priv: the Logical Network Interface
+ * @lac: LAC to free
+ */
+static void cass_lac_free(struct cxi_lni_priv *lni_priv, int lac)
+{
+	struct cass_dev *hw = container_of(lni_priv->dev, struct cass_dev, cdev);
+
+	cass_set_acid(hw, lni_priv->lni.rgid, lac, C_AC_NONE);
+	cass_lac_put(hw, lni_priv->lni.rgid, lac);
+}
+
+/**
+ * cass_ac_phys_alloc - Allocate a physical Address Context for a VF
+ *
+ * This per-VF AC is analogous to ATU_PHYS_AC and is used in its place when
+ * configuring resources such as CQs that belong to a VF.
+ *
+ * @hw: CXI device
+ * @vf_en: true if allocating an AC for a VF
+ * @vf_num: VF number to allocate AC for (ignored if vf_en is false)
+ */
+int cass_ac_phys_alloc(struct cass_dev *hw, bool vf_en, int vf_num)
+{
+	int acid;
+	union c_atu_cfg_ac_table ac = {
+		.context_en = 1,
+		.ta_mode = C_ATU_PASSTHROUGH_MODE,
+		.mem_size = ~0,
+		.ats_vf_en = vf_en,
+		.ats_vf_num = vf_en ? vf_num : 0,
+	};
+
+	acid = ida_alloc_range(&hw->atu_table, 1, ATU_PHYS_AC - 1, GFP_KERNEL);
+	if (acid < 0)
+		return acid;
+
+	cass_write_ac(hw, &ac, acid, false, true, vf_en, vf_num);
+
+	return acid;
+}
+
+/**
+ * cass_ac_phys_free - Free a physical Address Context allocated by
+ * cass_ac_phys_alloc()
+ *
+ * @hw: CXI device
+ * @acid: ID of address context
+ */
+void cass_ac_phys_free(struct cass_dev *hw, int acid)
+{
+	union c_atu_cfg_ac_table ac = {};
+
+	cass_write_ac(hw, &ac, acid, false, true, false, 0);
+	ida_free(&hw->atu_table, acid);
+}
+
+/**
+ * cass_ac_alloc() - Allocate an Address Context
+ *
+ * Once the ACID is written to hardware, it cannot be freed until the LNI
+ * is freed.
+ *
+ * @lni_priv: the Logical Network Interface
+ * @m_opts: User map options
+ */
+static struct cass_ac *cass_ac_alloc(struct cxi_lni_priv *lni_priv,
+				     struct ac_map_opts *m_opts)
+{
+	int ret;
+	unsigned long irq_flags;
+	struct cass_ac *cac;
+	struct cxi_dev *dev = lni_priv->dev;
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+
+	/* ac->pg_table_size is limited to 4 bits and a minimum of 8 entries */
+	if ((m_opts->huge_shift - m_opts->page_shift > MAX_PG_TABLE_SIZE) ||
+	    ((m_opts->ptg_mode != C_ATU_PTG_MODE_SGL) &&
+	     ((m_opts->huge_shift - m_opts->page_shift) < MIN_PG_TABLE_SIZE))) {
+		pr_debug("Invalid huge_shift:%d/page_shift:%d combination\n",
+			 m_opts->huge_shift, m_opts->page_shift);
+		return ERR_PTR(-EINVAL);
+	}
+
+	/* Check the associated service to see if this AC can be allocated */
+	ret = cxi_rgroup_alloc_resource(lni_priv->rgroup, CXI_RESOURCE_AC);
+	if (ret)
+		return ERR_PTR(ret);
+
+	cac = kzalloc(sizeof(*cac), GFP_KERNEL);
+	if (!cac) {
+		ret = -ENOMEM;
+		goto dec_rsrc_use;
+	}
+
+	/* AC_NONE (0) is invalid, ATU_PHYS_AC is reserved for physical
+	 * mappings
+	 */
+	ret = ida_alloc_range(&hw->atu_table, 1, ATU_PHYS_AC - 1, GFP_KERNEL);
+	if (ret < 0)
+		goto cac_free;
+
+	cac->ac.acid = ret;
+
+	ret = cass_lac_get(hw, lni_priv->lni.rgid);
+	if (ret < 0)
+		goto ac_put;
+
+	cac->ac.lac = ret;
+
+	refcount_set(&cac->refcount, 1);
+	mutex_init(&cac->ac_mutex);
+	cac->lni_priv = lni_priv;
+	cac->flags = m_opts->flags;
+	cac->ptg_mode = m_opts->ptg_mode;
+	cac->page_shift = m_opts->page_shift;
+	cac->huge_shift = m_opts->huge_shift;
+	cac->hugepage_test = m_opts->hugepage_test;
+
+	cass_ac_init(cac, m_opts);
+
+	if (m_opts->flags & CXI_MAP_ATS)
+		ret = cass_ats_init(lni_priv, m_opts, cac);
+	else
+		ret = cass_nta_init(lni_priv, m_opts, cac);
+
+	if (ret)
+		goto lac_put;
+
+	INIT_LIST_HEAD(&cac->md_list);
+	mutex_init(&cac->md_mutex);
+	refcount_set(&cac->reader_refs, 1);
+	init_completion(&cac->readers_done);
+
+	spin_lock_irqsave(&hw->cac_table_lock, irq_flags);
+	hw->cac_table[cac->ac.acid] = cac;
+	spin_unlock_irqrestore(&hw->cac_table_lock, irq_flags);
+
+	cass_write_ac(hw, &cac->cfg_ac, cac->ac.acid,
+		      m_opts->flags & CXI_MAP_USER_ADDR, false,
+		      cac->lni_priv->is_vf,
+		      cac->lni_priv->is_vf ? cac->lni_priv->vf_num : 0);
+	cass_set_acid(hw, lni_priv->lni.rgid, cac->ac.lac, cac->ac.acid);
+
+	list_add_tail(&cac->list, &lni_priv->ac_list);
+	refcount_inc(&lni_priv->refcount);
+
+	atomic_inc(&hw->stats.ac);
+
+	ac_debugfs_create(cac->ac.acid, cac, hw, lni_priv);
+
+	return cac;
+
+lac_put:
+	cass_lac_put(hw, lni_priv->lni.rgid, cac->ac.lac);
+ac_put:
+	ida_free(&hw->atu_table, cac->ac.acid);
+cac_free:
+	kfree(cac);
+dec_rsrc_use:
+	cxi_rgroup_free_resource(lni_priv->rgroup, CXI_RESOURCE_AC);
+
+	pr_debug("failed rc %d\n", ret);
+	return ERR_PTR(ret);
+}
+
+static void cass_ac_free(struct cass_dev *hw, struct cass_ac *cac)
+{
+	struct cxi_lni_priv *lni_priv = cac->lni_priv;
+
+	pr_debug("freeing ac %d\n", cac->ac.acid);
+
+	cass_cac_unpublish(hw, cac);
+
+	debugfs_remove(cac->lni_dir);
+	debugfs_remove_recursive(cac->debug_dir);
+
+	atomic_dec(&hw->stats.ac);
+	cxi_rgroup_free_resource(lni_priv->rgroup, CXI_RESOURCE_AC);
+
+	cass_md_list_free(cac);
+	cass_nta_iova_fini(cac);
+
+	if (cac->nta) {
+		cass_l1_tables_free(hw, cac->nta);
+		cass_invalidate_range(cac, 0, ATUCQ_INVALIDATE_ALL);
+		cass_nta_free(hw, cac->nta);
+	}
+
+	memset(&cac->cfg_ac, 0, sizeof(cac->cfg_ac));
+	cass_write_ac(hw, &cac->cfg_ac, cac->ac.acid, false, false,
+		      lni_priv->is_vf, lni_priv->is_vf ? lni_priv->vf_num : 0);
+
+	cass_unbind_ac(hw, cac);
+
+	cass_lac_free(lni_priv, cac->ac.lac);
+	cass_cac_free(hw, cac);
+	refcount_dec(&lni_priv->refcount);
+}
+
+/**
+ * cass_acs_disable() - Disable all the ACs of an LNI
+ *
+ * The LNI is getting released. This is the first part of the cleanup.
+ *
+ * @lni_priv: the Logical Network Interface
+ */
+void cass_acs_disable(struct cxi_lni_priv *lni_priv)
+{
+	struct cxi_dev *dev = lni_priv->dev;
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+	struct cass_ac *cac;
+
+	mutex_lock(&lni_priv->ac_list_mutex);
+
+	list_for_each_entry(cac, &lni_priv->ac_list, list) {
+		cac->cfg_ac.context_en = 0;
+		cass_write_ac(hw, &cac->cfg_ac, cac->ac.acid, false, false,
+			      cac->lni_priv->is_vf,
+			      cac->lni_priv->is_vf ? cac->lni_priv->vf_num : 0);
+	}
+
+	mutex_unlock(&lni_priv->ac_list_mutex);
+
+	cass_flush_pci(hw);
+}
+
+/**
+ * cass_acs_free() - Free all ACs associated with an LNI
+ *
+ * The ac_list is used by cass_pri_fault() and cass_sync_pagetables().
+ * LNI cleanup disables all the ACs associated with the LNI and then calls
+ * inbound wait so cass_pri_fault() will not be called while cleaning up.
+ * cass_hmm_fini() will remove this process from the hmm mirrors list so
+ * cass_sync_pagetables() will not be called while cleaning up.
+ *
+ * @lni_priv: the Logical Network Interface
+ */
+void cass_acs_free(struct cxi_lni_priv *lni_priv)
+{
+	struct cass_ac *cac;
+	struct cxi_dev *dev = lni_priv->dev;
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+
+	mutex_lock(&lni_priv->ac_list_mutex);
+
+	while ((cac = list_first_entry_or_null(&lni_priv->ac_list,
+					       struct cass_ac, list))) {
+		list_del(&cac->list);
+		mutex_unlock(&lni_priv->ac_list_mutex);
+		cass_ac_free(hw, cac);
+		mutex_lock(&lni_priv->ac_list_mutex);
+	}
+
+	mutex_unlock(&lni_priv->ac_list_mutex);
+
+	if (dev->is_physfn)
+		cass_flush_pci(hw);
+}
+
+/**
+ * cass_iova_alloc() - Allocate an IO virtual address in an Address Context
+ *
+ * Find an AC with matching characteristics and allocate an IOVA.
+ *
+ * @lni_priv: the Logical Network Interface
+ * @m_opts: User map options
+ */
+static struct cass_ac *cass_iova_alloc(struct cxi_lni_priv *lni_priv,
+				       struct ac_map_opts *m_opts)
+{
+	u64 iova;
+	struct list_head *ptr;
+	u32 masked_flags = m_opts->flags & ATU_FLAGS_MASK;
+
+	list_for_each(ptr, &lni_priv->ac_list) {
+		struct cass_ac *cac = list_entry(ptr, struct cass_ac, list);
+		u32 cac_msk_flags = cac->flags & ATU_FLAGS_MASK;
+
+		if ((m_opts->page_shift == cac->page_shift) &&
+		    (m_opts->huge_shift == cac->huge_shift) &&
+				(m_opts->ptg_mode == cac->ptg_mode) &&
+				(masked_flags == cac_msk_flags) &&
+				!m_opts->hugepage_test) {
+			if (m_opts->flags & CXI_MAP_ATS) {
+				iova = m_opts->va_start;
+			} else {
+				iova = cass_nta_iova_alloc(cac, m_opts);
+				if (!iova)
+					continue;
+			}
+
+			m_opts->iova = iova;
+
+			return cac;
+		}
+	}
+
+	return ERR_PTR(-ENOSPC);
+}
+
+/* Find or allocate an AC matching the options */
+static struct cass_ac *get_matching_ac(struct cxi_lni_priv *lni_priv,
+				       struct ac_map_opts *m_opts)
+{
+	struct cass_ac *cac;
+
+	mutex_lock(&lni_priv->ac_list_mutex);
+
+	cac = cass_iova_alloc(lni_priv, m_opts);
+	if (IS_ERR(cac))
+		cac = cass_ac_alloc(lni_priv, m_opts);
+
+	mutex_unlock(&lni_priv->ac_list_mutex);
+
+	return cac;
+}
+
+static void cass_init_md(const struct ac_map_opts *m_opts,
+			 struct cxi_md_priv *md_priv)
+{
+	md_priv->md.iova = m_opts->iova;
+	md_priv->md.va = m_opts->va_start;
+	md_priv->md.len = m_opts->va_len;
+	md_priv->md.page_shift = m_opts->page_shift;
+	md_priv->md.huge_shift = m_opts->huge_shift;
+	md_priv->md.lac = md_priv->cac->ac.lac;
+	md_priv->olen = m_opts->va_len;
+	md_priv->flags = m_opts->flags & ~(CXI_MAP_FAULT | CXI_MAP_PREFETCH);
+
+	/* Since we don't mirror the page tables when CXI_MAP_ALLOC_MD
+	 * is set, the first call to cxi_update_iov needs to lock.
+	 */
+	if (m_opts->flags & CXI_MAP_ALLOC_MD)
+		md_priv->need_lock = true;
+}
+
+/* Add an MD to an LNI */
+static void cass_add_md(struct cxi_lni_priv *lni_priv,
+			const struct ac_map_opts *m_opts,
+			struct cxi_md_priv *md_priv)
+{
+	struct cass_ac *cac = md_priv->cac;
+	struct cass_dev *hw = container_of(cac->lni_priv->dev, struct cass_dev, cdev);
+
+	mutex_lock(&cac->md_mutex);
+	list_add_tail(&md_priv->md_entry, &cac->md_list);
+	refcount_inc(&cac->refcount);
+	atomic_inc(&hw->stats.md);
+	mutex_unlock(&cac->md_mutex);
+}
+
+/**
+ * cass_remove_md() - Remove an MD from its LNI, clear and invalidate
+ *                    page table entries.
+ *
+ * @md_priv: Private memory descriptor
+ */
+static void cass_remove_md(struct cxi_md_priv *md_priv)
+{
+	struct cass_ac *cac = md_priv->cac;
+	struct cass_dev *hw = container_of(cac->lni_priv->dev, struct cass_dev, cdev);
+
+	mutex_lock(&md_priv->cac->md_mutex);
+	list_del(&md_priv->md_entry);
+	refcount_dec(&cac->refcount);
+	atomic_dec(&hw->stats.md);
+	mutex_unlock(&md_priv->cac->md_mutex);
+
+	cass_md_clear(md_priv, true, true);
+}
+
+static void cass_md_iova_free(struct cxi_md_priv *md_priv)
+{
+	struct cass_ac *cac = md_priv->cac;
+
+	if (cac->iovad)
+		FREE_IOVA_FAST(cac->iovad, md_priv->md.iova, md_priv->olen);
+}
+
+static int cass_bvec(struct cass_dev *hw, const struct iov_iter *iter,
+		     size_t *len, u64 *va)
+{
+	int i;
+	int last_seg = iter->nr_segs - 1;
+	const struct bio_vec *bvec = iter->bvec;
+
+	*va = (u64)page_address(bvec->bv_page);
+
+	for (i = 0; i < iter->nr_segs; i++) {
+		if (i && (bvec->bv_offset & ~PAGE_MASK)) {
+			cxidev_err(&hw->cdev, "bvec[%d] offset not aligned %d\n", i,
+				   bvec->bv_offset);
+			return -EINVAL;
+		}
+
+		if (i < last_seg && ((bvec->bv_offset + bvec->bv_len) &
+						~PAGE_MASK)) {
+			cxidev_err(&hw->cdev, "bvec[%d] contains a hole\n", i);
+			return -EINVAL;
+		}
+		bvec++;
+	}
+
+	*len = iter->nr_segs * PAGE_SIZE;
+
+	return 0;
+}
+
+static int cass_kvec(struct cass_dev *hw, const struct iov_iter *iter,
+		     size_t *len, u64 *va)
+{
+	int i;
+	int alen;
+	int tlen = 0;
+	int last_seg = iter->nr_segs - 1;
+	const struct kvec *kvec = iter->kvec;
+
+	*va = (u64)kvec->iov_base & PAGE_MASK;
+
+	for (i = 0; i < iter->nr_segs; i++) {
+		/*
+		 * Only the first kvec may be unaligned. The first and last
+		 * kvec's lengths can be less that a page but the rest need
+		 * to be full pages. The first base + len must be aligned.
+		 */
+		if (i && ((u64)kvec->iov_base & ~PAGE_MASK)) {
+			cxidev_err(&hw->cdev, "kvec[%d] base not aligned %p\n", i,
+				   kvec->iov_base);
+			return -EINVAL;
+		}
+
+		if (i < last_seg && (((u64)kvec->iov_base + kvec->iov_len) &
+					~PAGE_MASK)) {
+			cxidev_err(&hw->cdev, "kvec[%d] contains a hole\n", i);
+			return -EINVAL;
+		}
+
+		alen = PAGE_ALIGN(kvec->iov_len);
+		tlen += alen;
+		kvec++;
+	}
+
+	*len = tlen;
+
+	return 0;
+}
+
+/* cass_sgtable_is_valid() - Check for invalid sgt
+ *
+ * Requirements for entries in sgt:
+ * one entry:
+ *     offset < PAGE_SIZE
+ * multiple entries:
+ *     first:  offset < PAGE_SIZE, (len + offset) % PAGE_SIZE
+ *     middle: offset == 0, len % PAGE_SIZE
+ *     last:   offset == 0
+ */
+static bool cass_sgtable_is_valid(struct cass_dev *hw,
+				  const struct sg_table *sgt, size_t *length)
+{
+	int i;
+	struct scatterlist *sg;
+	int last_entry = sgt->nents - 1;
+
+	*length = 0;
+
+	for_each_sgtable_dma_sg(sgt, sg, i) {
+		size_t len = sg_dma_len(sg);
+
+		if (sg->offset > PAGE_SIZE) {
+			cxidev_err(&hw->cdev,
+				   "Entry %d offset:%x > PAGE_SIZE\n",
+				   i, sg->offset);
+
+			return false;
+		}
+
+		/* first of multiple entries */
+		if ((!i && i != last_entry && ((len + sg->offset) % PAGE_SIZE)) ||
+		    /* last entry */
+		    (i && i == last_entry && sg->offset) ||
+		    /* middle entries */
+		    (i && i < last_entry && (sg->offset ||
+					     len % PAGE_SIZE))) {
+			cxidev_err(&hw->cdev, "Hole in sg_table at entry %d offset:%x len:%lx\n",
+				   i, sg->offset, len);
+
+			return false;
+		}
+
+		*length += ALIGN(len + sg->offset, PAGE_SIZE);
+	}
+
+	return true;
+}
+
+/**
+ * cass_mirror_range() - Mirror an address range
+ *
+ * @md_priv: Private memory descriptor
+ * @m_opts:  User options
+ *
+ * @return: 0 on success or -ENOMEM
+ */
+int cass_mirror_range(struct cxi_md_priv *md_priv, struct ac_map_opts *m_opts)
+{
+	if (!(m_opts->flags & CXI_MAP_USER_ADDR))
+		return cass_nta_mirror_kern(md_priv, NULL, true);
+
+	if (m_opts->flags & CXI_MAP_ATS)
+		return cass_ats_md_init(md_priv, m_opts);
+
+	if (m_opts->flags & CXI_MAP_DEVICE)
+		return cass_mirror_device(md_priv, m_opts);
+
+	if (m_opts->hugepage_test)
+		return cass_mirror_hp(m_opts, md_priv);
+
+	if (m_opts->flags & CXI_MAP_PIN)
+		return cass_pin_mirror(md_priv, m_opts);
+
+	return cass_mmu_notifier_insert(md_priv, m_opts);
+}
+
+static void cass_unpin(struct cxi_md_priv *md_priv)
+{
+	int npages = md_priv->md.len >> PAGE_SHIFT;
+
+	if (!(md_priv->flags & CXI_MAP_PIN))
+		return;
+
+	if (!md_priv->pages)
+		return;
+
+	unpin_user_pages(md_priv->pages, npages);
+	kvfree(md_priv->pages);
+	md_priv->pages = NULL;
+}
+
+/**
+ * cass_md_clear() - Clear a memory descriptor
+ *
+ * Remove page table entries for NTA mode
+ * Unpin ATS or device pinned pages
+ *
+ * @md_priv: Private memory descriptor
+ * @inval: Invalidate this iova range
+ * @need_lock: Indicates whether the ac_mutex is required
+ */
+void cass_md_clear(struct cxi_md_priv *md_priv, bool inval, bool need_lock)
+{
+	struct cass_dev *hw = container_of(md_priv->cac->lni_priv->dev,
+					   struct cass_dev, cdev);
+
+	cass_notifier_cleanup(md_priv);
+
+	if (md_priv->flags & CXI_MAP_ATS)
+		return cass_unpin(md_priv);
+
+	/* If inval is false we have been called from cass_md_list_free()
+	 * which is only called when the AC is cleaning up so we don't
+	 * need to invalidate here as we will invalidate the whole AC range.
+	 */
+	cass_cond_lock(&md_priv->cac->ac_mutex, need_lock);
+	cass_clear_range(md_priv, md_priv->md.iova,
+			 md_priv->md.len);
+	cass_cond_unlock(&md_priv->cac->ac_mutex, need_lock);
+
+	if (inval) {
+		cass_invalidate_range(md_priv->cac, md_priv->md.iova,
+				      md_priv->md.len);
+		atomic_inc(&hw->dcpl_md_clear_inval);
+	}
+
+	if (md_priv->flags & CXI_MAP_DEVICE)
+		cass_device_put_pages(md_priv);
+	else
+		cass_unpin(md_priv);
+}
+
+static int largest_hp_size(struct vm_area_struct *vma, u64 end)
+{
+	int vma_hs;
+	int hs = INT_MAX;
+	ulong vm_end_prev;
+#ifdef VMA_ITERATOR
+	VMA_ITERATOR(vmi, vma->vm_mm, vma->vm_start);
+#endif
+
+	while (true) {
+		if (!is_vm_hugetlb_page(vma))
+			return PMD_SHIFT;
+
+		vma_hs = huge_page_shift(hstate_vma(vma));
+
+		hs = vma_hs < hs ? vma_hs : hs;
+
+		if (vma->vm_end >= end)
+			return hs;
+
+		vm_end_prev = vma->vm_end;
+#ifdef VMA_ITERATOR
+		vma = vma_next(&vmi);
+#else
+		vma = vma->vm_next;
+#endif
+		/* full range is not backed by vmas */
+		if (!vma)
+			return PMD_SHIFT;
+
+		/* found a hole */
+		if (vma->vm_start > vm_end_prev)
+			return PMD_SHIFT;
+
+		/* not in range */
+		if (vma->vm_start >= end)
+			break;
+	}
+
+	return hs;
+}
+
+static int align_and_page_shift(struct ac_map_opts *m_opts)
+{
+	/* To support hugepage sizes larger than 128MB, we need
+	 * a larger base page size.
+	 */
+	if ((m_opts->huge_shift - m_opts->page_shift) >
+			(MAX_PG_TABLE_SIZE - hugepage_threshold))
+		m_opts->page_shift = m_opts->huge_shift -
+				MAX_PG_TABLE_SIZE + hugepage_threshold;
+
+	/* A hugepage is backing this address so align
+	 * to and map the full hugepage.
+	 */
+	return m_opts->huge_shift;
+}
+
+int cass_cpu_page_size(struct cass_dev *hw, struct ac_map_opts *m_opts,
+		       struct mm_struct *mm, uintptr_t va,
+		       const struct cxi_md_hints *hints, int *align_shift)
+{
+	int ret = 0;
+	struct vm_area_struct *vma;
+
+	/* ODP hint from user for the hugepage size */
+	if (hints && !hints->page_shift && hints->huge_shift &&
+	    !(m_opts->flags & (CXI_MAP_PIN | CXI_MAP_FAULT | CXI_MAP_PREFETCH))) {
+		m_opts->huge_shift = hints->huge_shift;
+		*align_shift = align_and_page_shift(m_opts);
+
+		return 0;
+	}
+
+	mmap_read_lock(mm);
+	vma = find_vma(mm, va);
+	if (!vma) {
+		cxidev_warn(&hw->cdev, "No VMA covering 0x%016lx)\n", va);
+		ret = -EFAULT;
+		goto unlock;
+	}
+
+	/* Test arbitrary page sizes supplied by the user. The contiguous
+	 * pages will be mmapped from a 1G hugepage and combined into larger
+	 * base pages and smaller hugepages.
+	 */
+	if (hints && hints->page_shift && is_vm_hugetlb_page(vma)) {
+		m_opts->huge_shift = huge_page_shift(hstate_vma(vma));
+
+		pr_debug("Testing huge shift:%d bs:%d hs:%d\n",
+			 m_opts->huge_shift, hints->page_shift,
+			 hints->huge_shift);
+
+		if (hints->huge_shift > m_opts->huge_shift) {
+			cxidev_warn(&hw->cdev, "Hints huge_shift (%d) > vma's huge_shift (%d)\n",
+				    hints->huge_shift, m_opts->huge_shift);
+			ret = -EINVAL;
+			goto unlock;
+		}
+
+		m_opts->page_shift = hints->page_shift;
+		m_opts->huge_shift = hints->huge_shift;
+		*align_shift = hints->huge_shift;
+		m_opts->hugepage_test = true;
+		goto unlock;
+	}
+
+	if (is_vm_hugetlb_page(vma)) {
+		m_opts->huge_shift = largest_hp_size(vma, m_opts->va_end);
+		m_opts->is_huge_page = true;
+		*align_shift = align_and_page_shift(m_opts);
+	} else {
+		int vms_fs = ffsl(vma->vm_start);
+		int vml_fs = ffsl(vma->vm_end - vma->vm_start);
+
+		/* Small regions may not be aligned to the default alignment
+		 * passed in so limit alignment to the VMA.
+		 */
+		if (vms_fs < *align_shift || vml_fs < *align_shift)
+			*align_shift = min_t(int, vms_fs, vml_fs);
+	}
+
+unlock:
+	mmap_read_unlock(mm);
+
+	return ret;
+}
+
+/**
+ * cass_align_start_len() - Align the va and len to align_shift page size
+ *
+ * @m_opts: User map options
+ * @va: Virtual address
+ * @len: Length of address
+ * @align_shift: Power of two to align to
+ */
+void cass_align_start_len(struct ac_map_opts *m_opts, uintptr_t va, size_t len,
+			  int align_shift)
+{
+	size_t page_size = BIT(align_shift);
+
+	m_opts->va_start = round_down(va, page_size);
+	m_opts->va_len = round_up(va + len, page_size) - m_opts->va_start;
+	m_opts->va_end = m_opts->va_start + m_opts->va_len;
+}
+
+/**
+ * cxi_phys_lac_alloc_vf() - Allocate a physical LAC for the given LNI for a VF.
+ *
+ * @lni: the Logical Network Interface
+ * @return: LAC or negative errno
+ */
+static int cxi_phys_lac_alloc_vf(struct cxi_lni *lni)
+{
+	struct cxi_lni_priv_vf *lni_priv_vf = container_of(lni, struct cxi_lni_priv_vf, lni);
+
+	return lni_priv_vf->phys_lac;
+}
+
+/**
+ * cxi_phys_lac_alloc() - Allocate a physical LAC for the given LNI.
+ *                        Exported to allow clients to perform DMA using physical addresses.
+ *
+ * @lni: the Logical Network Interface
+ * @return: LAC or negative errno
+ */
+int cxi_phys_lac_alloc(struct cxi_lni *lni)
+{
+	struct cxi_lni_priv *lni_priv = container_of(lni, struct cxi_lni_priv, lni);
+	struct cxi_dev *cdev = lni_priv->dev;
+	struct cass_dev *hw = container_of(lni_priv->dev, struct cass_dev, cdev);
+	int lac;
+
+	if (!cdev->is_physfn)
+		return cxi_phys_lac_alloc_vf(lni);
+
+	lac = cass_lac_get(hw, lni_priv->lni.rgid);
+	if (lac < 0)
+		return lac;
+
+	/* Program the phys_ac that was already selected at the lni allocation */
+	cass_set_acid(hw, lni_priv->lni.rgid, lac, lni_priv->phys_ac);
+
+	return lac;
+}
+EXPORT_SYMBOL(cxi_phys_lac_alloc);
+
+/**
+ * cxi_phys_lac_free() - Unmap a physical LAC
+ *
+ * @lni: the Logical Network Interface
+ * @lac: LAC to free
+ */
+void cxi_phys_lac_free(struct cxi_lni *lni, int lac)
+{
+	struct cxi_lni_priv *lni_priv = container_of(lni, struct cxi_lni_priv, lni);
+	struct cxi_dev *cdev = lni_priv->dev;
+
+	/* VFs do not free physical LACs. They will be freed when the LNI is freed */
+	if (!cdev->is_physfn)
+		return;
+
+	cass_lac_free(lni_priv, lac);
+}
+EXPORT_SYMBOL(cxi_phys_lac_free);
+
+/**
+ * cxi_clear_md() - Zero page table entries and invalidate a memory descriptor
+ *
+ * @md: Memory Descriptor used in network operations
+ */
+int cxi_clear_md(struct cxi_md *md)
+{
+	struct cxi_md_priv *md_priv;
+
+	if (!md)
+		return -EINVAL;
+
+	md_priv = container_of(md, struct cxi_md_priv, md);
+
+	pr_debug("va:%llx iova:%llx len:%lx\n", md->va, md->iova, md->len);
+
+	cass_md_clear(md_priv, true, false);
+	cass_dma_unmap_pages(md_priv);
+	md_priv->external_sgt_owner = false;
+	md_priv->sgt = NULL;
+
+	return 0;
+}
+EXPORT_SYMBOL(cxi_clear_md);
+
+/**
+ * cxi_update_iov() - Map a list of virtual address or pages in an IO
+ *                    virtual address space into an existing memory
+ *                    descriptor.
+ *
+ * @md: Memory descriptor
+ * @iter: List of virtual addresses to map - supports ITER_KVEC and ITER_BVEC
+ */
+int cxi_update_iov(struct cxi_md *md, const struct iov_iter *iter)
+{
+	u64 va;
+	int ret;
+	size_t len;
+	struct cxi_md_priv *md_priv;
+	struct cxi_lni_priv *lni_priv;
+	struct cxi_dev *dev;
+	struct cass_dev *hw;
+
+	if (!md)
+		return -EINVAL;
+
+	md_priv = container_of(md, struct cxi_md_priv, md);
+	lni_priv = md_priv->lni_priv;
+	dev = lni_priv->dev;
+	hw = container_of(dev, struct cass_dev, cdev);
+
+	if (iov_iter_is_bvec(iter))
+		ret = cass_bvec(hw, iter, &len, &va);
+	else
+		ret = cass_kvec(hw, iter, &len, &va);
+	if (ret)
+		return ret;
+
+	if (len > md_priv->olen)
+		return -EINVAL;
+
+	md->len = len;
+
+	ret = cass_nta_mirror_kern(md_priv, iter, md_priv->need_lock);
+
+	pr_debug("iovs:%ld len:0x%lx iova:%llx\n", iter->nr_segs, md->len,
+		 md->iova);
+
+	return ret;
+
+}
+EXPORT_SYMBOL(cxi_update_iov);
+
+/**
+ * cxi_map_iov() - Map a list of virtual address or pages in an IO
+ *                 virtual address space
+ *
+ * @lni: the Logical Network Interface
+ * @iter: List of virtual addresses to map - supports ITER_KVEC and ITER_BVEC
+ * @flags: various options affecting the map
+ */
+struct cxi_md *cxi_map_iov(struct cxi_lni *lni, const struct iov_iter *iter,
+			   u32 flags)
+{
+	u64 va;
+	int ret;
+	struct cxi_lni_priv *lni_priv = container_of(lni, struct cxi_lni_priv, lni);
+	struct cxi_dev *cdev = lni_priv->dev;
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	struct cxi_md_priv *md_priv;
+	struct cxi_md *md;
+	struct ac_map_opts m_opts = {
+		.page_shift = PAGE_SHIFT,
+		.huge_shift = PMD_SHIFT
+	};
+	struct cass_ac *cac;
+
+	/* currently unsupported flags */
+	if (flags & CXI_MAP_ATS)
+		return ERR_PTR(-EINVAL);
+
+	if (iov_iter_is_bvec(iter))
+		ret = cass_bvec(hw, iter, &m_opts.va_len, &va);
+	else
+		ret = cass_kvec(hw, iter, &m_opts.va_len, &va);
+	if (ret)
+		return ERR_PTR(ret);
+
+	m_opts.va_start = 0;
+	m_opts.flags = flags;
+	m_opts.va_end = m_opts.va_start + m_opts.va_len;
+	m_opts.ptg_mode = default_ptg_mode;
+
+	cac = get_matching_ac(lni_priv, &m_opts);
+	if (IS_ERR(cac))
+		return ERR_PTR(PTR_ERR(cac));
+
+	md_priv = kzalloc(sizeof(*md_priv), GFP_KERNEL);
+	if (md_priv == NULL)
+		return ERR_PTR(-ENOMEM);
+	refcount_set(&md_priv->refcount, 1);
+	md = &md_priv->md;
+	md_priv->device = &hw->cdev.pdev->dev;
+
+	/* Get an MD ID, above CXI_MD_NONE */
+	ret = ida_alloc_min(&hw->md_index_table, 1, GFP_KERNEL);
+	if (ret < 0) {
+		cxidev_err(cdev, "ida_alloc_min failed %d\n", ret);
+		goto md_free;
+	}
+	md->id = ret;
+
+	md_priv->cac = cac;
+	md_priv->lni_priv = lni_priv;
+
+	cass_init_md(&m_opts, md_priv);
+
+	ret = cass_nta_mirror_kern(md_priv, iter, true);
+	if (ret)
+		goto mirror_range_error;
+
+	cass_add_md(lni_priv, &m_opts, md_priv);
+
+	pr_debug("iovs:%ld len:0x%lx iova:%llx\n", iter->nr_segs, md->len,
+		 md->iova);
+
+	refcount_inc(&lni_priv->refcount);
+
+	return md;
+
+mirror_range_error:
+	cass_md_iova_free(md_priv);
+	ida_free(&hw->md_index_table, md->id);
+md_free:
+	kfree(md_priv);
+
+	return ERR_PTR(ret);
+}
+EXPORT_SYMBOL(cxi_map_iov);
+
+/**
+ * cxi_map_sgtable_vf() - Map an sg table to an IO virtual address space for a VF
+ *
+ * @lni: The Logical Network Interface
+ * @sgt: The sg_table object. It is expected to be dma mapped.
+ * @flags: Various options affecting the map
+ *
+ * @return: memory descriptor or error code
+ */
+static struct cxi_md *cxi_map_sgtable_vf(struct cxi_lni *lni,
+					 struct sg_table *sgt, u32 flags)
+{
+	struct cxi_lni_priv *lni_priv = container_of(lni, struct cxi_lni_priv, lni);
+	struct cxi_lni_priv_vf *lni_priv_vf = container_of(lni, struct cxi_lni_priv_vf, lni);
+	struct cxi_dev *dev = lni_priv_vf->dev;
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+	struct cxi_md_priv_vf *md_priv_vf;
+	struct cxi_atu_map_sgt_cmd *cmd;
+	struct cxi_atu_map_sgt_resp resp = {};
+	size_t resp_len = sizeof(resp);
+	struct scatterlist *sg;
+	int i;
+	int rc;
+	size_t sgt_len;
+
+	if (!sgt)
+		return ERR_PTR(-EINVAL);
+
+	if (!cass_sgtable_is_valid(hw, sgt, &sgt_len))
+		return ERR_PTR(-EINVAL);
+
+	sg = sgt->sgl;
+
+	md_priv_vf = kzalloc(sizeof(*md_priv_vf), GFP_KERNEL);
+	if (!md_priv_vf)
+		return ERR_PTR(-ENOMEM);
+
+	md_priv_vf->lni_priv = lni_priv;
+	md_priv_vf->device = &hw->cdev.pdev->dev;
+	md_priv_vf->md.va = 0;
+	md_priv_vf->md.len = sgt_len;
+	md_priv_vf->md.page_shift = PAGE_SHIFT;
+	md_priv_vf->md.huge_shift = PMD_SHIFT;
+	md_priv_vf->flags = flags & ~(CXI_MAP_FAULT | CXI_MAP_PREFETCH);
+	md_priv_vf->sgt = sgt;
+	md_priv_vf->pages = NULL;
+	md_priv_vf->npages = 0;
+
+	/* Send sgt to the PF to run cxi_map_sgtable there */
+	if (sgt->nents > CXI_ATU_SGT_MAX_ENTRIES) {
+		rc = -E2BIG;
+		cxidev_err(&hw->cdev, "SGT has too many entries: %u\n", sgt->nents);
+		goto free_md_priv;
+	}
+
+	pr_debug("VF map: md:%p lni:%u rgid:%u nents:%u len:0x%lx flags:0x%x\n",
+		 md_priv_vf, lni_priv_vf->lni.id, lni_priv_vf->lni.rgid, sgt->nents, sgt_len,
+		 flags);
+
+	cmd = kvzalloc(sizeof(*cmd), GFP_KERNEL);
+	if (!cmd) {
+		rc = -ENOMEM;
+		goto free_md_priv;
+	}
+
+	cmd->op = CXI_OP_ATU_MAP_SGT;
+	cmd->lni = lni_priv_vf->lni.id;
+	cmd->flags = flags;
+	cmd->nents = sgt->nents;
+
+	pr_debug("Sending SGT with %d entries to PF\n", sgt->nents);
+	for (i = 0; i < sgt->nents; i++) {
+		cmd->sge[i].dma_addr = sg_dma_address(sg);
+		cmd->sge[i].dma_len = sg_dma_len(sg);
+		cmd->sge[i].offset = sg->offset;
+
+		sg = sg_next(sg);
+	}
+
+	rc = cxi_send_msg_to_pf(dev, cmd, sizeof(*cmd), &resp, &resp_len);
+	kvfree(cmd);
+	if (rc)
+		goto free_md_priv;
+
+	/* Set the iova and the lac retrieved from the PF */
+	md_priv_vf->md.iova = resp.md.iova;
+	md_priv_vf->md.lac = resp.md.lac;
+	md_priv_vf->md.id = resp.md.id;
+	pr_debug("VF map resp: md:%d iova:%llx lac:%u resp_len:%zu\n",
+		 md_priv_vf->md.id, md_priv_vf->md.iova,
+		 md_priv_vf->md.lac, resp_len);
+
+	return &md_priv_vf->md;
+
+free_md_priv:
+	kfree(md_priv_vf);
+	return ERR_PTR(rc);
+}
+
+static int cxi_unmap_sgtable_vf(struct cxi_dev *dev,
+				struct cxi_md_priv_vf *md_priv_vf,
+				struct cass_dev *hw, int md_id)
+{
+	struct cxi_atu_unmap_cmd cmd = {
+		.op = CXI_OP_ATU_UNMAP,
+		.id = md_priv_vf->md.id,
+	};
+	size_t resp_len = 0;
+	int rc;
+
+	rc = cxi_send_msg_to_pf(dev, &cmd, sizeof(cmd), NULL, &resp_len);
+	if (rc)
+		cxidev_err(&hw->cdev, "VF ATU_UNMAP failed md:%d pf_md:%d rc:%d\n",
+			   md_id, md_priv_vf->md.id, rc);
+
+	return rc;
+}
+
+/**
+ * cxi_map_sgtable() - Map an sg table to an IO virtual address space
+ *
+ * @lni: The Logical Network Interface
+ * @sgt: The sg_table object. It is expected to be dma mapped.
+ * @flags: Various options affecting the map
+ *
+ * @return: memory descriptor or error code
+ */
+struct cxi_md *cxi_map_sgtable(struct cxi_lni *lni, struct sg_table *sgt,
+			       u32 flags)
+{
+	int ret;
+	size_t len;
+	struct cxi_md *md;
+	struct cass_ac *cac;
+	struct cxi_md_priv *md_priv;
+	struct cxi_lni_priv *lni_priv = container_of(lni, struct cxi_lni_priv, lni);
+	struct cxi_dev *cdev = lni_priv->dev;
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	struct ac_map_opts m_opts = {
+		.page_shift = PAGE_SHIFT,
+		.huge_shift = PMD_SHIFT
+	};
+
+	/* unsupported flags */
+	if (flags & CXI_MAP_ATS)
+		return ERR_PTR(-EINVAL);
+
+	if (!cass_sgtable_is_valid(hw, sgt, &len))
+		return ERR_PTR(-EINVAL);
+
+	if (!cdev->is_physfn)
+		return cxi_map_sgtable_vf(lni, sgt, flags);
+
+	m_opts.va_start = 0;
+	m_opts.flags = flags;
+	m_opts.va_len = len;
+	m_opts.va_end = m_opts.va_len;
+	m_opts.ptg_mode = default_ptg_mode;
+
+	cac = get_matching_ac(lni_priv, &m_opts);
+	if (IS_ERR(cac))
+		return ERR_PTR(PTR_ERR(cac));
+
+	md_priv = kzalloc(sizeof(*md_priv), GFP_KERNEL);
+	if (md_priv == NULL)
+		return ERR_PTR(-ENOMEM);
+	refcount_set(&md_priv->refcount, 1);
+	md = &md_priv->md;
+	md_priv->device = &hw->cdev.pdev->dev;
+
+	/* Get an MD ID, above CXI_MD_NONE */
+	ret = ida_alloc_min(&hw->md_index_table, 1, GFP_KERNEL);
+	if (ret < 0) {
+		cxidev_err(cdev, "ida_alloc_min failed %d\n", ret);
+		goto md_free;
+	}
+	md->id = ret;
+
+	md_priv->sgt = sgt;
+	md_priv->external_sgt_owner = true;
+	md_priv->cac = cac;
+	md_priv->lni_priv = lni_priv;
+
+	cass_init_md(&m_opts, md_priv);
+
+	pr_debug("va:%llx va_len:%lx iova:%0llx iova_base:%llx md:%d ac:%d flags:%x\n",
+		 m_opts.va_start, m_opts.va_len, m_opts.iova, cac->iova_base,
+		 md->id, md_priv->cac->ac.acid, flags);
+
+	ret = cass_nta_mirror_sgt(md_priv, true);
+	if (ret)
+		goto mirror_range_error;
+
+	cass_add_md(lni_priv, &m_opts, md_priv);
+
+	pr_debug("nents:%u len:0x%lx iova:%llx\n", sgt->nents, md->len,
+		 md->iova);
+
+	refcount_inc(&lni_priv->refcount);
+
+	return md;
+
+mirror_range_error:
+	cass_md_iova_free(md_priv);
+	ida_free(&hw->md_index_table, md->id);
+md_free:
+	kfree(md_priv);
+
+	return ERR_PTR(ret);
+}
+EXPORT_SYMBOL(cxi_map_sgtable);
+
+/**
+ * cxi_update_sgtable() - Update the specified address range contained in MD
+ *
+ * @md: Memory Descriptor used in network operations
+ * @sgt: The sg_table object. It is expected to be dma mapped.
+ *
+ * @return: 0 on success or negative error value
+ */
+int cxi_update_sgtable(struct cxi_md *md, struct sg_table *sgt)
+{
+	int ret;
+	size_t len;
+	struct cxi_md_priv *md_priv = container_of(md, struct cxi_md_priv, md);
+	struct cxi_dev *cdev = md_priv->lni_priv->dev;
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+
+	if (!cass_sgtable_is_valid(hw, sgt, &len))
+		return -EINVAL;
+
+	if (len > md_priv->olen) {
+		pr_debug("Address range not bounded by MD\n");
+		return -EINVAL;
+	}
+
+	md_priv->sgt = sgt;
+	md_priv->external_sgt_owner = true;
+
+	pr_debug("nents:%u len:0x%lx iova:%llx\n", sgt->nents, md->len,
+		 md->iova);
+
+	ret = cass_nta_mirror_sgt(md_priv, md_priv->need_lock);
+	if (ret)
+		return ret;
+
+	md_priv->need_lock = false;
+
+	return 0;
+}
+EXPORT_SYMBOL(cxi_update_sgtable);
+
+/**
+ * cass_virt_to_pages() - Get page structures for kernel virtual addresses
+ *
+ * @hw: Cassini device for error reporting
+ * @va: Starting virtual address (will be page-aligned)
+ * @npages: Number of pages to get
+ * @pages: Array to store page pointers
+ *
+ * @return: 0 on success, negative error code on failure
+ */
+static int cass_virt_to_pages(struct cass_dev *hw, uintptr_t va, int npages,
+			      struct page **pages)
+{
+	int i;
+	uintptr_t addr = va & PAGE_MASK;
+
+	for (i = 0; i < npages; i++, addr += PAGE_SIZE) {
+		if (is_vmalloc_addr((void *)addr))
+			pages[i] = vmalloc_to_page((void *)addr);
+		else
+			pages[i] = virt_to_page(addr);
+
+		if (!pages[i]) {
+			cxidev_err(&hw->cdev, "Failed to get page for addr 0x%lx\n", addr);
+			return -EFAULT;
+		}
+	}
+
+	return 0;
+}
+
+static struct cxi_md *cxi_map_vf(struct cxi_lni *lni, uintptr_t va, size_t len,
+				 u32 flags, const struct cxi_md_hints *hints)
+{
+	struct cxi_lni_priv_vf *lni_priv_vf = container_of(lni, struct cxi_lni_priv_vf, lni);
+	struct cxi_dev *dev = lni_priv_vf->dev;
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+	struct cxi_md *md;
+	struct cxi_md_priv_vf *md_priv_vf;
+	/* For now, we do not support hugepages. This will come later when we add the ATS
+	 * for both VF and PF: NETCASSINI-7859.
+	 * In this effort we will reuse code to align pages and to support huge pages too
+	 */
+	const int npages = (PAGE_ALIGN(va + len) - (va & PAGE_MASK)) >> PAGE_SHIFT;
+	struct page **pages;
+	struct sg_table *sgt;
+	int rc;
+
+	if (flags & CXI_MAP_USER_ADDR && !(flags & CXI_MAP_PIN)) {
+		cxidev_err(&hw->cdev, "VF does not support ODP\n");
+		return ERR_PTR(-EOPNOTSUPP);
+	}
+
+	if (flags & CXI_MAP_DEVICE) {
+		cxidev_err(&hw->cdev, "TODO: VF does not support device memory\n");
+		return ERR_PTR(-EOPNOTSUPP);
+	}
+
+	if (!va) {
+		cxidev_err(&hw->cdev, "NULL virtual address\n");
+		return ERR_PTR(-EINVAL);
+	}
+
+	pages = kvmalloc_array(npages, sizeof(struct page *), GFP_KERNEL);
+	if (!pages) {
+		rc = -ENOMEM;
+		return ERR_PTR(rc);
+	}
+
+	/* Get the pages and pin them if requested */
+	if (flags & CXI_MAP_PIN) {
+		rc = pin_user_pages_fast(va & PAGE_MASK, npages, FOLL_WRITE | FOLL_LONGTERM, pages);
+		if (rc != npages) {
+			cxidev_err(&hw->cdev, "pin_user_pages_fast failed: %d/%d\n", rc, npages);
+			if (rc > 0)
+				unpin_user_pages(pages, rc);
+			rc = rc < 0 ? rc : -EFAULT;
+			goto free_pages;
+		}
+	} else {
+		rc = cass_virt_to_pages(hw, va, npages, pages);
+		if (rc)
+			goto free_pages;
+	}
+
+	/* Now we DMA-map the pages using a scatter-gather table */
+	sgt = kzalloc(sizeof(*sgt), GFP_KERNEL);
+	if (!sgt) {
+		rc = -ENOMEM;
+		goto unpin_pages;
+	}
+
+	rc = sg_alloc_table_from_pages_segment(sgt, pages, npages,
+					       va & ~PAGE_MASK, len,
+					       UINT_MAX, GFP_KERNEL);
+	if (rc)
+		goto free_sgt;
+
+	rc = dma_map_sgtable(&hw->cdev.pdev->dev, sgt, DMA_BIDIRECTIONAL, 0);
+	if (rc) {
+		cxidev_err(&hw->cdev, "dma_map_sgtable failed\n");
+		goto free_sgt_table;
+	}
+
+	pr_debug("va:0x%lx len:0x%lx npages:%d nents:%u page_aligned_va:0x%lx page_offset:0x%lx\n",
+		 va, len, npages, sgt->nents, va & PAGE_MASK, va & ~PAGE_MASK);
+
+	md = cxi_map_sgtable_vf(lni, sgt, flags);
+	if (IS_ERR(md)) {
+		rc = PTR_ERR(md);
+		goto unmap_sgt;
+	}
+
+	md_priv_vf = container_of(md, struct cxi_md_priv_vf, md);
+	md_priv_vf->md.va = va;
+	md_priv_vf->sgt = sgt;
+	md_priv_vf->pages = pages;
+	md_priv_vf->npages = npages;
+
+	/* Adjust IOVA to include the within-page offset.
+	 * PF returns page-aligned IOVA, but application needs the actual data address.
+	 */
+	md_priv_vf->md.iova += (va & ~PAGE_MASK);
+	md_priv_vf->md.len = len;
+
+	return md;
+
+unmap_sgt:
+	dma_unmap_sgtable(&hw->cdev.pdev->dev, sgt, DMA_BIDIRECTIONAL, 0);
+free_sgt_table:
+	sg_free_table(sgt);
+free_sgt:
+	kfree(sgt);
+unpin_pages:
+	if (flags & CXI_MAP_PIN)
+		unpin_user_pages(pages, npages);
+free_pages:
+	kvfree(pages);
+	return ERR_PTR(rc);
+}
+
+/**
+ * cxi_map() - Map virtual addresses into IO  address space
+ *
+ * If CXI_MAP_ALLOC_MD is set, just allocate an IOVA and return the MD.
+ *
+ * @lni: the Logical Network Interface
+ * @va: kernel or user virtual address
+ * @len: length of address to map in bytes
+ * @flags: various options affecting the map
+ * @hints: hints used for debugging
+ *
+ * @return: memory descriptor or error code
+ */
+struct cxi_md *cxi_map(struct cxi_lni *lni, uintptr_t va, size_t len,
+		       u32 flags, const struct cxi_md_hints *hints)
+{
+	struct cxi_lni_priv *lni_priv = container_of(lni, struct cxi_lni_priv, lni);
+	struct cxi_dev *cdev = lni_priv->dev;
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	int ret;
+	struct cxi_md_priv *md_priv;
+	struct cxi_md *md;
+	struct ac_map_opts m_opts = {
+		.huge_shift = PMD_SHIFT,
+		.page_shift = PAGE_SHIFT
+	};
+	struct cass_ac *cac;
+	u64 ova = va;
+	size_t olen = len;
+
+	if (!len) {
+		pr_debug("Length is 0\n");
+		return ERR_PTR(-EINVAL);
+	}
+
+	if (flags & CXI_MAP_PIN &&
+	    (flags & CXI_MAP_FAULT || flags & CXI_MAP_PREFETCH)) {
+		pr_debug("Invalid flags combination:0x%x\n", flags);
+		return ERR_PTR(-EINVAL);
+	}
+
+	if (hints && (hints->ptg_mode_valid)) {
+		/* Invalid combination. hugepage_test builds two
+		 * level tables.
+		 */
+		if ((hints->ptg_mode == C_ATU_PTG_MODE_SGL) &&
+		    m_opts.hugepage_test) {
+			cxidev_info(cdev, "Hugepage test cannot be used with PTG Mode Single\n");
+			return ERR_PTR(-EINVAL);
+		}
+
+		if ((hints->ptg_mode < C_ATU_PTG_MODE_SGL) ||
+		    (hints->ptg_mode > C_ATU_PTG_MODE_DBL_C)) {
+			cxidev_info(cdev, "Invalid PTG_MODE supplied:%d\n",
+				    hints->ptg_mode);
+			return ERR_PTR(-EINVAL);
+		}
+		m_opts.ptg_mode = hints->ptg_mode;
+	} else {
+		m_opts.ptg_mode = default_ptg_mode;
+	}
+
+	if (!cdev->is_physfn)
+		return cxi_map_vf(lni, va, len, flags, hints);
+
+	ret = cass_odp_supported(hw, flags);
+	if (ret)
+		return ERR_PTR(ret);
+
+	md_priv = kzalloc(sizeof(*md_priv), GFP_KERNEL);
+	if (md_priv == NULL)
+		return ERR_PTR(-ENOMEM);
+
+	refcount_set(&md_priv->refcount, 1);
+	md = &md_priv->md;
+	md_priv->lni_priv = lni_priv;
+	md_priv->device = &hw->cdev.pdev->dev;
+	m_opts.flags = flags;
+	m_opts.md_priv = md_priv;
+
+	if (flags & CXI_MAP_ATS) {
+		cass_align_start_len(&m_opts, va, len, PAGE_SHIFT);
+	} else if (flags & CXI_MAP_DEVICE) {
+		if (hints) {
+			if (hints->dmabuf_valid) {
+				md_priv->dmabuf_fd = hints->dmabuf_fd;
+				md_priv->dmabuf_offset = hints->dmabuf_offset;
+				md_priv->dmabuf_length = olen;
+			} else {
+				md_priv->dmabuf_fd = INVALID_DMABUF_FD;
+			}
+		}
+
+		ret = cass_is_device_memory(hw, &m_opts, va, len);
+		if (ret)
+			goto md_free;
+
+		cass_align_start_len(&m_opts, va, len, m_opts.page_shift);
+
+		ret = cass_device_get_pages(&m_opts);
+		if (ret)
+			goto md_free;
+
+	} else if (flags & CXI_MAP_USER_ADDR) {
+		int align_shift = m_opts.page_shift;
+
+		m_opts.va_end = va + len;
+		ret = cass_cpu_page_size(hw, &m_opts, current->mm, va, hints,
+					 &align_shift);
+		if (ret)
+			goto md_free;
+
+		cass_align_start_len(&m_opts, va, len, align_shift);
+	} else {
+		/* VA is a kernel address which is expected to be aligned
+		 * to the PAGE_SIZE.
+		 */
+		if (va & ~PAGE_MASK) {
+			cxidev_err(cdev, "va not aligned 0x%lx\n", va);
+			ret = -EINVAL;
+			goto md_free;
+		}
+
+		cass_align_start_len(&m_opts, va, len, m_opts.page_shift);
+	}
+
+	if (m_opts.ptg_mode == C_ATU_PTG_MODE_SGL)
+		m_opts.huge_shift = m_opts.page_shift;
+
+	cac = get_matching_ac(lni_priv, &m_opts);
+	if (IS_ERR(cac)) {
+		cxidev_dbg(cdev, "Failure to get AC:%ld\n", PTR_ERR(cac));
+		ret = PTR_ERR(cac);
+		goto put_device_pages;
+	}
+
+	md_priv->cac = cac;
+
+	/* Get an MD ID, above CXI_MD_NONE */
+	ret = ida_alloc_min(&hw->md_index_table, 1, GFP_KERNEL);
+	if (ret < 0) {
+		cxidev_err(cdev, "ida_alloc_min failed %d\n", ret);
+		goto iova_free;
+	}
+
+	md->id = ret;
+
+	cass_init_md(&m_opts, md_priv);
+
+	pr_debug("ova:%llx olen:%lx va:%llx iova:%0llx iova_base:%llx md:%d ac:%d len:%lx flags:%x\n",
+		 ova, olen, m_opts.va_start, md->iova, cac->iova_base,
+		 md->id, md_priv->cac->ac.acid, md->len, flags);
+
+	if (!(flags & CXI_MAP_ALLOC_MD)) {
+		ret = cass_mirror_range(md_priv, &m_opts);
+		if (ret) {
+			pr_debug("Mirror address range failed:%d\n", ret);
+			goto mirror_range_error;
+		}
+	}
+
+	cass_add_md(lni_priv, &m_opts, md_priv);
+	refcount_inc(&lni_priv->refcount);
+
+	return md;
+
+mirror_range_error:
+	ida_free(&hw->md_index_table, md->id);
+iova_free:
+	cass_md_iova_free(md_priv);
+put_device_pages:
+	if (flags & CXI_MAP_DEVICE)
+		cass_device_put_pages(md_priv);
+md_free:
+	kfree(md_priv);
+
+	return ERR_PTR(ret);
+}
+EXPORT_SYMBOL(cxi_map);
+
+static int cxi_unmap_vf(struct cxi_md *md)
+{
+	struct cxi_md_priv_vf *md_priv_vf = container_of(md, struct cxi_md_priv_vf, md);
+	struct cxi_dev *dev = md_priv_vf->lni_priv->dev;
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+
+	pr_debug("VF md:%d lac:%d va:%llx iova:%llx len:%lx\n",
+		 md->id, md->lac, md->va, md->iova, md->len);
+
+	/* Notify PF to free the MD created from the VF sglist */
+	cxi_unmap_sgtable_vf(dev, md_priv_vf, hw, md->id);
+
+	/* Unmap and free scatter-gather table if we own it */
+	if (md_priv_vf->pages && md_priv_vf->sgt) {
+		dma_unmap_sgtable(md_priv_vf->device, md_priv_vf->sgt, DMA_BIDIRECTIONAL, 0);
+		sg_free_table(md_priv_vf->sgt);
+		kfree(md_priv_vf->sgt);
+	}
+
+	/* Unpin pages if they were pinned, or just free the pages array */
+	if (md_priv_vf->pages) {
+		if (md_priv_vf->flags & CXI_MAP_PIN)
+			unpin_user_pages(md_priv_vf->pages, md_priv_vf->npages);
+		kvfree(md_priv_vf->pages);
+	}
+
+	/* Free the VF MD structure */
+	kfree(md_priv_vf);
+
+	return 0;
+}
+
+/**
+ * cxi_unmap() - Unmap a virtual address
+ *
+ * @md: Memory Descriptor used in network operations
+ */
+int cxi_unmap(struct cxi_md *md)
+{
+	struct cxi_md_priv *md_priv;
+	struct cxi_lni_priv *lni_priv;
+	struct cxi_dev *dev;
+	struct cass_dev *hw;
+
+	if (!md || md->lac >= C_NUM_LACS)
+		return -EINVAL;
+
+	dev = container_of(md, struct cxi_md_priv, md)->lni_priv->dev;
+	if (!dev->is_physfn)
+		return cxi_unmap_vf(md);
+
+	md_priv = container_of(md, struct cxi_md_priv, md);
+	lni_priv = md_priv->lni_priv;
+	dev = lni_priv->dev;
+	hw = container_of(dev, struct cass_dev, cdev);
+
+	/* One reference for CAC allocation, one reference for MD. */
+	if (refcount_read(&md_priv->cac->refcount) < 2)
+		return -EINVAL;
+
+	pr_debug("md:%d ac:%d lac:%d va:%llx iova:%llx len:%lx\n",
+		 md->id, md_priv->cac->ac.acid, md->lac, md->va, md->iova,
+		 md->len);
+
+	cass_remove_md(md_priv);
+	cass_md_iova_free(md_priv);
+	ida_free(&hw->md_index_table, md->id);
+
+	cxidev_WARN_ONCE(dev, !refcount_dec_and_test(&md_priv->refcount),
+			 "Resource leaks - MD refcount not zero: %d\n",
+			 refcount_read(&md_priv->refcount));
+
+	cass_dma_unmap_pages(md_priv);
+	kfree(md_priv);
+
+	refcount_dec(&lni_priv->refcount);
+
+	return 0;
+}
+EXPORT_SYMBOL(cxi_unmap);
+
+/**
+ * cxi_update_md() - Update the specified address range contained in MD
+ *
+ * @md: Memory Descriptor used in network operations
+ * @va: User virtual address
+ * @len: Length of address to fault in bytes
+ * @flags: Currently only supports faulting pages with CXI_MAP_FAULT flag
+ *         for an ODP MD.
+ *
+ * @return: 0 on success or negative error value
+ */
+int cxi_update_md(struct cxi_md *md, uintptr_t va, size_t len, u32 flags)
+{
+	int ret;
+	struct cxi_md_priv *md_priv;
+	struct cass_dev *hw;
+	int align_shift;
+	struct ac_map_opts m_opts = {};
+
+	if (!md || md->lac >= C_NUM_LACS)
+		return -EINVAL;
+
+	if (va < md->va || len > ULONG_MAX - va ||
+	    va - md->va > md->len || len > md->len - (va - md->va)) {
+		pr_debug("Address range not bounded by MD\n");
+		return -EINVAL;
+	}
+
+	/* Just support CXI_MAP_FAULT for now */
+	if (!(flags & CXI_MAP_FAULT)) {
+		pr_debug("Only CXI_MAP_FAULT is supported\n");
+		return -EINVAL;
+	}
+
+	md_priv = container_of(md, struct cxi_md_priv, md);
+	hw = container_of(md_priv->lni_priv->dev, struct cass_dev, cdev);
+
+	if (md_priv->flags & CXI_MAP_PIN) {
+		pr_debug("Must be ODP MD\n");
+		return -EINVAL;
+	}
+
+	m_opts.va_end = va + len;
+	m_opts.md_priv = md_priv;
+	m_opts.page_shift = md->page_shift;
+	m_opts.huge_shift = md->huge_shift;
+	/* Use the permissions from the MD */
+	m_opts.flags = md_priv->flags & (CXI_MAP_READ | CXI_MAP_WRITE);
+	m_opts.flags |= flags;
+	align_shift = m_opts.page_shift;
+
+	ret = cass_cpu_page_size(hw, &m_opts, current->mm, va, NULL,
+				 &align_shift);
+	if (ret)
+		return ret;
+
+	/* We only support VMAs that match the MD's hugepage size. */
+	if (m_opts.huge_shift != md->huge_shift) {
+		pr_debug("Error: VMA huge_shift (%d) must match MD (%d)\n",
+			 m_opts.huge_shift, md->huge_shift);
+		return -EINVAL;
+	}
+
+	cass_align_start_len(&m_opts, va, len, align_shift);
+	m_opts.iova = md->iova + (m_opts.va_start - md->va);
+
+	pr_debug("md:%d ac:%d md.va:%llx va:%llx iova:%llx len:%lx flags:%x\n",
+		 md->id, md_priv->cac->ac.acid, md->va, m_opts.va_start,
+		 m_opts.iova, m_opts.va_len, m_opts.flags);
+
+	ret = cass_mirror_odp(&m_opts, md_priv->cac,
+			      m_opts.va_len >> m_opts.page_shift,
+			      m_opts.va_start);
+
+	return ret;
+}
+EXPORT_SYMBOL(cxi_update_md);
diff --git a/drivers/net/ethernet/hpe/ss1/cass_cq.c b/drivers/net/ethernet/hpe/ss1/cass_cq.c
new file mode 100644
index 000000000000..fb8523590bc5
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_cq.c
@@ -0,0 +1,1243 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2018, 2024-2026 Hewlett Packard Enterprise Development LP */
+
+/* Create and destroy Cassini command queues */
+
+#include <linux/hpe/cxi/cxi.h>
+#include <linux/dma-mapping.h>
+#include <linux/iopoll.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+#include "cass_core.h"
+#include "cxi_internal.h"
+#include "cass_ss1_debugfs.h"
+#include "cxi_vf_cmd.h"
+
+#ifdef CONFIG_ARM64
+/* Provide a workaround for avoiding writecombine on platforms where it is broken
+ * and for which the Linux kernel does not already provide a workaround, such as the
+ * Ampere Altra, used in the RL300.
+ */
+DEFINE_STATIC_KEY_FALSE(avoid_writecombine);
+#endif
+
+/* Lower bound for number of 64 byte commands. */
+#define MIN_CQ_COUNT (PAGE_SIZE / C_CQ_CMD_SIZE)
+
+void cass_cq_init(struct cass_dev *hw)
+{
+	static const union c_cq_cfg_cq_policy cq_policy = {
+		.policy[CXI_CQ_UPDATE_ALWAYS] = {
+			.shift = 0,
+		},
+		.policy[CXI_CQ_UPDATE_HIGH_FREQ_EMPTY] = {
+			.shift = 4,
+			.empty = 1,
+		},
+		.policy[CXI_CQ_UPDATE_LOW_FREQ_EMPTY] = {
+			.shift = 8,
+			.empty = 1,
+		},
+		.policy[CXI_CQ_UPDATE_LOW_FREQ] = {
+			.shift = 8,
+		},
+	};
+	union c_cq_cfg_tg_thresh tg_thresh = {
+		.tg[0].thresh = tg_threshold[0],
+		.tg[1].thresh = tg_threshold[1],
+		.tg[2].thresh = tg_threshold[2],
+		.tg[3].thresh = tg_threshold[3],
+	};
+
+	/* Initialize CQ policies. */
+	cass_write(hw, C_CQ_CFG_CQ_POLICY, &cq_policy, sizeof(cq_policy));
+
+	/* LPE append credits */
+	cass_write(hw, C_CQ_CFG_TG_THRESH, &tg_thresh, sizeof(tg_thresh));
+
+	/* Zero FQ allocation settings. */
+	cass_clear(hw, C_CQ_CFG_FQ_RESRV(0), C_CQ_CFG_FQ_RESRV_SIZE);
+
+#ifdef CONFIG_ARM64
+	if (pci_get_device(PCI_VENDOR_ID_AMPERE, 0xe100, NULL))
+		static_branch_enable(&avoid_writecombine);
+#endif
+}
+
+static phys_addr_t
+cq_mmio_phys_addr(const struct cass_dev *hw, int cq_id)
+{
+	return hw->regs_base + C_CQ_LAUNCH_TXQ_BASE +
+		C_CQ_LAUNCH_PAGE_SIZE * cq_id;
+}
+
+/* Write TX CQ configuration to hardware */
+static int setup_hw_tx_cq(struct cass_dev *hw, unsigned int cq_n,
+			  const struct cxi_cq_alloc_opts *opts,
+			  struct cxi_lni_priv *lni_priv,
+			  struct cxi_cq_priv *cq,
+			  struct cxi_eq_priv *eq,
+			  struct cxi_cp_priv *cp_priv)
+{
+	size_t cmds_count = cq->cmds_len / C_CQ_CMD_SIZE;
+	union c_cq_txq_tc_table tc = {
+		.mem_q_eth = !!(opts->flags & CXI_CQ_TX_ETHERNET),
+		.mem_q_trig = !!(opts->flags & CXI_CQ_TX_WITH_TRIG_CMDS),
+	};
+	union c_cq_txq_base_table txq_cfg = {
+		.mem_q_eq = eq ? eq->eq.eqn : C_EQ_NONE,
+		.mem_q_base = cq->cmds_dma_addr >> C_ADDR_SHIFT,
+		.mem_q_max_ptr = cmds_count - 1,
+		.mem_q_rgid = lni_priv->lni.rgid,
+		.mem_q_stat_cnt_pool = opts->stat_cnt_pool,
+		.mem_q_lcid = opts->lcid,
+		.mem_q_acid = lni_priv->phys_ac,
+		.mem_q_policy = opts->policy,
+	};
+	union c_cq_cfg_init_txq_hw_state txq_init;
+	union c_cq_cfg_cp_fl_table flow_cfg;
+	void __iomem *csr;
+	int rc;
+
+	/* Transmit CQ needs to be configured with the same PFQ and TC
+	 * values the corresponding communication profile is using.
+	 */
+	cass_read(hw, C_CQ_CFG_CP_FL_TABLE(cp_priv->cass_cp->id),
+		  &flow_cfg, sizeof(flow_cfg));
+
+	tc.mem_q_tc = flow_cfg.tc;
+	txq_cfg.mem_q_pfq = flow_cfg.pfq;
+
+	if (opts->flags & CXI_CQ_TX_WITH_TRIG_CMDS)
+		txq_cfg.mem_q_pfq = cxi_rgroup_tle_pool_id(lni_priv->rgroup);
+
+	spin_lock(&hw->cq_shadow_lock);
+	cass_tx_cq_init(hw, &cq->cass_cq, cq_n, &tc, &txq_cfg);
+	spin_unlock(&hw->cq_shadow_lock);
+
+	mutex_lock(&hw->cq_init_lock);
+	cass_read(hw, C_CQ_CFG_INIT_TXQ_HW_STATE, &txq_init,
+		  sizeof(txq_init));
+
+	cxidev_WARN_ONCE(&hw->cdev, txq_init.pending == 1,
+			 "TXQ init pending CSR should not be set");
+	if (txq_init.pending == 1) {
+		mutex_unlock(&hw->cq_init_lock);
+		return -EIO;
+	}
+
+	txq_init.cq_handle = cq_n;
+
+	cass_write(hw, C_CQ_CFG_INIT_TXQ_HW_STATE, &txq_init,
+		   sizeof(txq_init));
+
+	csr = cass_csr(hw, C_CQ_CFG_INIT_TXQ_HW_STATE);
+	rc = readq_poll_timeout(csr, txq_init.qw, txq_init.pending == 0,
+				1, 1000);
+
+	cxidev_WARN_ONCE(&hw->cdev, rc, "Timeout waiting for TXQ init");
+	if (rc) {
+		mutex_unlock(&hw->cq_init_lock);
+		return -EIO;
+	}
+	mutex_unlock(&hw->cq_init_lock);
+
+	cass_tx_cq_enable(hw, cq_n);
+
+	return 0;
+}
+
+/* Write TGT CQ configuration to hardware */
+#define MEM_Q_TC_REG_SIZE BIT(3)
+static int setup_hw_tgt_cq(struct cass_dev *hw, unsigned int cq_n,
+			   const struct cxi_cq_alloc_opts *opts,
+			   struct cxi_lni_priv *lni_priv,
+			   struct cxi_cq_priv *cq,
+			   struct cxi_eq_priv *eq)
+{
+	size_t cmds_count = cq->cmds_len / C_CQ_CMD_SIZE;
+	// TODO: Handle TGT TC
+	const union c_cq_tgq_table tgt_cfg = {
+		.mem_q_eq = eq ? eq->eq.eqn : C_EQ_NONE,
+		.mem_q_base = cq->cmds_dma_addr >> C_ADDR_SHIFT,
+		.mem_q_max_ptr = cmds_count - 1,
+		.mem_q_rgid = lni_priv->lni.rgid,
+		.mem_q_stat_cnt_pool = opts->stat_cnt_pool,
+		.mem_q_tc_reg = cq_n % MEM_Q_TC_REG_SIZE,
+		.mem_q_acid = lni_priv->phys_ac,
+		.mem_q_policy = opts->policy,
+	};
+	union c_cq_cfg_init_tgq_hw_state tgq_init;
+	union c_cq_cfg_thresh_map thresh_map = {
+		.thresh_id = opts->lpe_cdt_thresh_id,
+	};
+	void __iomem *csr;
+	int rc;
+
+	spin_lock(&hw->cq_shadow_lock);
+	cass_tgt_cq_init(hw, &cq->cass_cq, cq_n, &tgt_cfg);
+	spin_unlock(&hw->cq_shadow_lock);
+
+	mutex_lock(&hw->cq_init_lock);
+	cass_read(hw, C_CQ_CFG_INIT_TGQ_HW_STATE, &tgq_init,
+		  sizeof(tgq_init));
+
+	cxidev_WARN_ONCE(&hw->cdev, tgq_init.pending == 1,
+			 "TGQ init pending CSR should not be set");
+	if (tgq_init.pending == 1) {
+		mutex_unlock(&hw->cq_init_lock);
+		return -EIO;
+	}
+
+	cass_write(hw, C_CQ_CFG_THRESH_MAP(cq_n),
+		   &thresh_map, sizeof(thresh_map));
+
+	tgq_init.cq_handle = cq_n;
+	cass_write(hw, C_CQ_CFG_INIT_TGQ_HW_STATE, &tgq_init,
+		   sizeof(tgq_init));
+
+	/* TODO: Check delay and timeouts are correct for real NIC. */
+	csr = cass_csr(hw, C_CQ_CFG_INIT_TGQ_HW_STATE);
+	rc = readq_poll_timeout(csr, tgq_init.qw, tgq_init.pending == 0,
+				1, 1000);
+
+	cxidev_WARN_ONCE(&hw->cdev, rc, "Timeout waiting for TGQ init");
+	if (rc) {
+		mutex_unlock(&hw->cq_init_lock);
+		return -EIO;
+	}
+	mutex_unlock(&hw->cq_init_lock);
+
+	cass_tgt_cq_enable(hw, cq_n);
+
+	return 0;
+}
+
+/* Return an available CQ with an ID */
+static struct cxi_cq_priv *pf_get_cq_id(struct cxi_lni_priv *lni_priv,
+					const struct cxi_cq_alloc_opts *opts)
+{
+	struct cxi_dev *dev = lni_priv->dev;
+	struct cass_dev *hw =
+		container_of(dev, struct cass_dev, cdev);
+	struct cxi_cq_priv *cq;
+	enum cxi_resource_type rsrc_type;
+	int rc;
+
+	cq = kzalloc(sizeof(struct cxi_cq_priv), GFP_KERNEL);
+	if (cq == NULL)
+		return ERR_PTR(-ENOMEM);
+
+	/* Check the associated service to see if this CQ can be allocated */
+	if (opts->flags & CXI_CQ_IS_TX)
+		rsrc_type = CXI_RESOURCE_TXQ;
+	else
+		rsrc_type = CXI_RESOURCE_TGQ;
+
+	rc = cxi_rgroup_alloc_resource(lni_priv->rgroup, rsrc_type);
+	if (rc) {
+		/* Attempt to cleanup all CQs on this LNI to return service
+		 * credits and then reattempt to allocate resource.
+		 */
+		finalize_cq_cleanups(lni_priv, false);
+
+		rc = cxi_rgroup_alloc_resource(lni_priv->rgroup, rsrc_type);
+		if (rc)
+			goto cq_free;
+	}
+
+	if (opts->flags & CXI_CQ_IS_TX)
+		rc = ida_alloc_range(&hw->cq_table, 0, C_NUM_TRANSMIT_CQS - 1, GFP_KERNEL);
+	else
+		rc = ida_alloc_range(&hw->cq_table, C_NUM_TRANSMIT_CQS,
+				     C_NUM_TRANSMIT_CQS + C_NUM_TARGET_CQS - 1,
+				     GFP_KERNEL);
+
+	if (rc < 0) {
+		/* Out of CQs. Accelerate possible CQ cleanup. */
+		lni_cleanups(hw, false);
+
+		if (opts->flags & CXI_CQ_IS_TX)
+			rc = ida_alloc_range(&hw->cq_table, 0,
+					     C_NUM_TRANSMIT_CQS - 1, GFP_KERNEL);
+		else
+			rc = ida_alloc_range(&hw->cq_table, C_NUM_TRANSMIT_CQS,
+					     C_NUM_TRANSMIT_CQS + C_NUM_TARGET_CQS - 1,
+					     GFP_KERNEL);
+	}
+
+	if (rc < 0)
+		goto dec_rsrc_use;
+
+	cq->cass_cq.idx = rc;
+
+	return cq;
+
+dec_rsrc_use:
+	cxi_rgroup_free_resource(lni_priv->rgroup, rsrc_type);
+
+cq_free:
+	kfree(cq);
+
+	return ERR_PTR(rc);
+}
+
+static void put_cq_id(struct cxi_cq_priv *cq)
+{
+	struct cxi_lni_priv *lni_priv = cq->lni_priv;
+	struct cxi_dev *dev = lni_priv->dev;
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+
+	ida_free(&hw->cq_table, cq->cass_cq.idx);
+	if (cq->flags & CXI_CQ_IS_TX)
+		cxi_rgroup_free_resource(lni_priv->rgroup, CXI_RESOURCE_TXQ);
+	else
+		cxi_rgroup_free_resource(lni_priv->rgroup, CXI_RESOURCE_TGQ);
+	kfree(cq);
+}
+
+/**
+ * cxi_cq_free_vf() - Free the communication profile for VF
+ *
+ * @cmdq: Command queue to be freed
+ */
+static void cxi_cq_free_vf(struct cxi_cq *cmdq)
+{
+	struct cxi_cq_priv_vf *cq_priv_vf =
+		container_of(cmdq, struct cxi_cq_priv_vf, cass_cq);
+	struct cxi_dev *dev = cq_priv_vf->lni_priv->dev;
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+	const struct cxi_cq_free_cmd cmd = {
+		.op = CXI_OP_CQ_FREE,
+		.cq = cq_priv_vf->cass_cq.idx,
+	};
+	size_t resp_len = 0;
+	int rc;
+
+	rc = cxi_send_msg_to_pf(dev, &cmd, sizeof(cmd), NULL, &resp_len);
+	if (rc)
+		return;
+
+	if (cq_priv_vf->cq_mmio)
+		iounmap(cq_priv_vf->cq_mmio);
+
+	dma_unmap_page(&hw->cdev.pdev->dev, cq_priv_vf->cmds_dma_addr,
+		       cq_priv_vf->cmds_len, DMA_BIDIRECTIONAL);
+
+	if (cq_priv_vf->cmds_pages) {
+		__free_pages(cq_priv_vf->cmds_pages, cq_priv_vf->cmds_order);
+	} else {
+		if (cq_priv_vf->md_priv) {
+			cass_device_put_pages(cq_priv_vf->md_priv);
+			kfree(cq_priv_vf->md_priv);
+		}
+
+		if (cq_priv_vf->pages) {
+			unpin_user_pages(cq_priv_vf->pages, cq_priv_vf->cmds_len >> PAGE_SHIFT);
+			kfree(cq_priv_vf->pages);
+		}
+	}
+
+	kfree(cq_priv_vf);
+}
+
+/**
+ * get_dma_addr_if_contig() - Check for contiguous pages of user buffer,
+ *                            pin and return dma_addr.
+ *
+ * If pages are contiguous, pin the pages and return the dma_addr of the base.
+ * Otherwise, return negative errno.
+ *
+ * @hw: The cassini device
+ * @addr: address of page aligned buffer
+ * @len: page aligned length of buffer - must not be 0
+ * @dir: dma map direction
+ * @pages: ptr to list of pages returned
+ * @dma_addr: dma_addr of user buffer
+ *
+ * @return: 0 on success, negative error value
+ */
+int get_dma_addr_if_contig(struct cass_dev *hw, void *addr, size_t len,
+			   enum dma_data_direction dir, struct page ***pages,
+			   dma_addr_t *dma_addr)
+{
+	int i;
+	int rc;
+	int npinned;
+	dma_addr_t pa;
+	size_t npg = len >> PAGE_SHIFT;
+
+	*pages = kmalloc_array(npg, sizeof(struct page *), GFP_KERNEL);
+	if (!*pages)
+		return -ENOMEM;
+
+	npinned = pin_user_pages_fast((u64)addr, npg,
+				      FOLL_WRITE | FOLL_LONGTERM, *pages);
+	if (npinned < 0) {
+		rc = npinned;
+		goto free_pages;
+	}
+
+	if (npinned != npg) {
+		rc = -EFAULT;
+		goto put_pages;
+	}
+
+	/* Naively check that each page is in sequence. */
+	pa = page_to_phys((*pages)[0]);
+	for (i = 1; i < npg; i++) {
+		pa += PAGE_SIZE;
+		if (pa != page_to_phys((*pages)[i])) {
+			cxidev_dbg(&hw->cdev,
+				   "Buffer supplied is required to be contiguous\n");
+			rc = -EINVAL;
+			goto put_pages;
+		}
+	}
+
+	*dma_addr = dma_map_page(&hw->cdev.pdev->dev, (*pages)[0], 0, len, dir);
+	if (dma_mapping_error(&hw->cdev.pdev->dev, *dma_addr)) {
+		rc = -ENOMEM;
+		goto put_pages;
+	}
+
+	return 0;
+
+put_pages:
+	unpin_user_pages(*pages, npinned);
+
+free_pages:
+	kfree(*pages);
+
+	return rc;
+}
+
+static struct cxi_md_priv *get_device_addr(struct cxi_lni_priv *lni_priv,
+					   uintptr_t va, size_t len,
+					   int dmabuf_fd,
+					   unsigned long dmabuf_offset,
+					   dma_addr_t *dma_addr)
+{
+	int i;
+	int rc;
+	struct scatterlist *sg;
+	struct cxi_dev *cdev = lni_priv->dev;
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	struct cxi_md_priv *md_priv;
+	struct ac_map_opts m_opts = {
+		.huge_shift = PMD_SHIFT,
+		.page_shift = PAGE_SHIFT
+	};
+	u32 flags = CXI_MAP_DEVICE;
+	dma_addr_t next_addr = 0;
+
+	if (!len) {
+		pr_debug("Length is 0\n");
+		return ERR_PTR(-EINVAL);
+	}
+
+	md_priv = kzalloc(sizeof(*md_priv), GFP_KERNEL);
+	if (!md_priv)
+		return ERR_PTR(-ENOMEM);
+
+	refcount_set(&md_priv->refcount, 1);
+	md_priv->lni_priv = lni_priv;
+	md_priv->device = &hw->cdev.pdev->dev;
+	md_priv->dmabuf_fd = dmabuf_fd;
+	md_priv->dmabuf_offset = dmabuf_offset;
+	md_priv->dmabuf_length = len;
+	m_opts.flags = flags;
+	m_opts.md_priv = md_priv;
+
+	rc = cass_is_device_memory(hw, &m_opts, va, len);
+	if (rc)
+		goto md_free;
+
+	cass_align_start_len(&m_opts, va, len, m_opts.page_shift);
+
+	rc = cass_device_get_pages(&m_opts);
+	if (rc) {
+		cxidev_dbg(&hw->cdev,
+			   "cass_device_get_pages failed rc:%d\n", rc);
+		goto md_free;
+	}
+
+	/* AMD p2p pages are not guaranteed to be contiguous. */
+	for_each_sgtable_dma_sg(md_priv->sgt, sg, i) {
+		long len = sg_dma_len(sg);
+		dma_addr_t dma_addr = sg_dma_address(sg);
+
+		if (dma_addr != PAGE_ALIGN(dma_addr)) {
+			cxidev_dbg(&hw->cdev,
+				   "Buffer supplied is required to be page aligned\n");
+			rc = -EINVAL;
+			goto put_pages;
+		}
+
+		if (!next_addr) {
+			next_addr = dma_addr + len;
+			continue;
+		}
+
+		if (dma_addr != next_addr) {
+			cxidev_dbg(&hw->cdev,
+				   "Buffer supplied is required to be contiguous\n");
+			rc = -EINVAL;
+			goto put_pages;
+		}
+
+		next_addr = dma_addr + len;
+	}
+
+	md_priv->olen = m_opts.va_len;
+	md_priv->flags = m_opts.flags;
+	*dma_addr = sg_dma_address(md_priv->sgt->sgl);
+
+	return md_priv;
+
+put_pages:
+	cass_device_put_pages(md_priv);
+
+md_free:
+	kfree(md_priv);
+
+	return ERR_PTR(rc);
+}
+
+/**
+ * cxi_cq_alloc_buf_vf() - Allocate a new command queue for VF
+ *
+ * The new CQ is attached to attached to the NI.
+ *
+ * @lni: LNI to associate with the command queue.
+ * @evtq: Event Queue to associate with the command queue, for error
+ *        reporting. May be NULL.
+ * @opts_b: Options affecting the CQ.
+ * @numa_node: NUMA node ID CQ memory should be allocated from.
+ *
+ * @return: the command queue or an error pointer
+ */
+static struct cxi_cq *cxi_cq_alloc_buf_vf(struct cxi_lni *lni, struct cxi_eq *evtq,
+					  const struct cxi_cq_alloc_opts_buf *opts_b,
+					  int numa_node)
+{
+	struct cxi_lni_priv_vf *lni_priv_vf =
+		container_of(lni, struct cxi_lni_priv_vf, lni);
+	struct cxi_dev *cdev = lni_priv_vf->dev;
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	const struct cxi_cq_alloc_opts *opts = &opts_b->opts;
+	struct cxi_cq_priv_vf *cq;
+	struct cxi_cq_alloc_buf_cmd_vf cmd = {
+		.base.op = CXI_OP_CQ_ALLOC_BUF,
+		.base.lni = lni_priv_vf->lni.id,
+		.base.eq = evtq ? evtq->eqn : C_EQ_NONE,
+		.base.opts = *opts_b,
+	};
+	struct cxi_cq_alloc_resp resp;
+	size_t resp_len = sizeof(resp);
+	bool is_user = opts->flags & CXI_CQ_USER;
+	struct page *cmds_pages;
+	size_t cmds_count;
+	size_t cmds_order;
+	size_t cmds_len;
+	int rc;
+
+	/* Use provided commands count to calculate commands length. Then, use
+	 * commands length to recalculate commands count to consume entire
+	 * buffer space.
+	 */
+	cmds_count = max_t(size_t, MIN_CQ_COUNT, opts->count);
+	cmds_order = get_order(cmds_count * C_CQ_CMD_SIZE);
+	cmds_len = (1 << cmds_order) * PAGE_SIZE;
+	cmds_count = cmds_len / C_CQ_CMD_SIZE;
+
+	if (cmds_count > CXI_MAX_CQ_COUNT) {
+		cxidev_dbg(cdev, "cmds_count:%ld is > CXI_MAX_CQ_COUNT:%d\n",
+			   cmds_count, CXI_MAX_CQ_COUNT);
+		return ERR_PTR(-E2BIG);
+	}
+
+	cq = kzalloc(sizeof(*cq), GFP_KERNEL);
+	if (!cq)
+		return ERR_PTR(-ENOMEM);
+
+	if (opts_b->buf) {
+		if (!IS_ALIGNED((u64)opts_b->buf, PAGE_SIZE)) {
+			cxidev_dbg(cdev, "buffer %llx not aligned to PAGE_SIZE\n",
+				   (u64)opts_b->buf);
+			rc = -EINVAL;
+			goto free_cq;
+		}
+
+		if (opts_b->is_host_mem) {
+			rc = get_dma_addr_if_contig(hw, opts_b->buf, cmds_len,
+						    DMA_BIDIRECTIONAL,
+						    &cq->pages,
+						    &cq->cmds_dma_addr);
+			if (rc)
+				goto free_cq;
+		} else {
+			cq->md_priv = get_device_addr(container_of(lni, struct cxi_lni_priv, lni),
+						      (uintptr_t)opts_b->buf,
+						      cmds_len,
+						      opts_b->dmabuf_fd,
+						      opts_b->dmabuf_offset,
+						      &cq->cmds_dma_addr);
+			if (IS_ERR(cq->md_priv)) {
+				rc = PTR_ERR(cq->md_priv);
+				goto free_cq;
+			}
+		}
+		cq->cmds = NULL;
+	} else {
+		cmds_pages = alloc_pages_node(numa_node, GFP_KERNEL | __GFP_ZERO,
+					      cmds_order);
+		if (!cmds_pages) {
+			rc = -ENOMEM;
+			goto free_cq;
+		}
+
+		cq->cmds_order = cmds_order;
+		cq->cmds = page_address(cmds_pages);
+		cq->cmds_pages = cmds_pages;
+		cq->cmds_dma_addr = dma_map_page(&hw->cdev.pdev->dev,
+						 cmds_pages, 0, cmds_len,
+						 DMA_BIDIRECTIONAL);
+		if (dma_mapping_error(&hw->cdev.pdev->dev, cq->cmds_dma_addr)) {
+			rc = -ENOMEM;
+			goto free_pages;
+		}
+	}
+
+	cq->cmds_len = cmds_len;
+	cmd.dma_addr = cq->cmds_dma_addr;
+	cmd.cmds_len = cmds_len;
+
+	rc = cxi_send_msg_to_pf(cdev, &cmd, sizeof(cmd), &resp, &resp_len);
+	if (rc)
+		goto cq_release;
+
+	if (!is_user) {
+		phys_addr_t mmio_phys = cq_mmio_phys_addr(hw, resp.cq);
+#ifdef CONFIG_ARM64
+		if (static_branch_unlikely(&avoid_writecombine))
+			cq->cq_mmio = ioremap(mmio_phys, PAGE_SIZE);
+		else
+#endif
+		cq->cq_mmio = ioremap_wc(mmio_phys, PAGE_SIZE);
+		if (!cq->cq_mmio) {
+			cxidev_warn_once(cdev, "ioremap_wc failed\n");
+			rc = -EFAULT;
+			goto cq_release;
+		}
+	}
+
+	/* Initialize client interface structure */
+	cxi_cq_init(&cq->cass_cq,
+		    cq->cmds,
+		    cmds_count,
+		    (__force void *)cq->cq_mmio,
+		    resp.cq);
+
+	cq->lni_priv = container_of(lni, struct cxi_lni_priv, lni);
+	cq->flags = opts->flags;
+	cq->cass_cq.size = resp.count;
+	cq->cass_cq.idx = resp.cq;
+
+	return &cq->cass_cq;
+
+cq_release:
+	dma_unmap_page(&hw->cdev.pdev->dev, cq->cmds_dma_addr,
+		       cq->cmds_len, DMA_BIDIRECTIONAL);
+
+	if (cq->pages) {
+		unpin_user_pages(cq->pages, cq->cmds_len >> PAGE_SHIFT);
+		kfree(cq->pages);
+	}
+free_pages:
+	if (cq->cmds_pages)
+		__free_pages(cq->cmds_pages, cmds_order);
+free_cq:
+	kfree(cq);
+	return ERR_PTR(rc);
+}
+
+/**
+ * cxi_cq_alloc_buf_internal() - Allocate a new command queue
+ *
+ * The new CQ is attached to the LNI.
+ * The CQ buffer may be supplied by the user. It must be physically
+ * contiguous.
+ *
+ * @lni: LNI to associate with the command queue.
+ * @evtq: Event Queue to associate with the command queue, for error
+ *        reporting. May be NULL.
+ * @opts_b: Options affecting the CQ.
+ * @numa_node: NUMA node ID CQ memory should be allocated from.
+ * @cmds_dma_addr: Pre-allocated DMA address (0 to allocate new)
+ * @cmds_len: Length of pre-allocated memory (0 to allocate new)
+ *
+ * @return: the command queue or an error pointer
+ */
+struct cxi_cq *cxi_cq_alloc_buf_internal(struct cxi_lni *lni, struct cxi_eq *evtq,
+					 const struct cxi_cq_alloc_opts_buf *opts_b,
+					 int numa_node, dma_addr_t cmds_dma_addr,
+					 size_t cmds_len)
+{
+	struct cxi_lni_priv *lni_priv =
+		container_of(lni, struct cxi_lni_priv, lni);
+	struct cxi_dev *cdev = lni_priv->dev;
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	const struct cxi_cq_alloc_opts *opts = &opts_b->opts;
+	struct cxi_eq_priv *eq;
+	struct cxi_cq_priv *cq;
+	int cq_idx;
+	int cq_n;
+	int rc;
+	size_t cmds_count;
+	size_t cmds_order;
+	struct page *cmds_pages;
+	struct cxi_cp_priv *cp_priv = NULL;
+	bool is_user = opts->flags & CXI_CQ_USER;
+
+	if (opts->policy < 0 || opts->policy > CXI_CQ_UPDATE_LOW_FREQ)
+		return ERR_PTR(-EINVAL);
+
+	if (!(opts->flags & CXI_CQ_IS_TX) && opts->lpe_cdt_thresh_id > 3)
+		return ERR_PTR(-EINVAL);
+
+	/*
+	 * Use provided commands count to calculate commands length. Then, use
+	 * commands length to recalculate commands count to consume entire
+	 * buffer space.
+	 */
+	cmds_count = max_t(size_t, MIN_CQ_COUNT, opts->count);
+	cmds_order = get_order(cmds_count * C_CQ_CMD_SIZE);
+	cmds_len = (1 << cmds_order) * PAGE_SIZE;
+	cmds_count = cmds_len / C_CQ_CMD_SIZE;
+
+	if (cmds_count > CXI_MAX_CQ_COUNT) {
+		cxidev_dbg(cdev, "cmds_count:%ld is > CXI_MAX_CQ_COUNT:%d\n",
+			   cmds_count, CXI_MAX_CQ_COUNT);
+		return ERR_PTR(-E2BIG);
+	}
+
+	/* At least one communication profile is needed for a transmit
+	 * CQ.
+	 */
+	if (opts->flags & CXI_CQ_IS_TX) {
+		/* For triggered CQs, only LCID zero can be used. */
+		if ((opts->flags & CXI_CQ_TX_WITH_TRIG_CMDS) && opts->lcid != 0)
+			return ERR_PTR(-EINVAL);
+
+		cp_priv = cass_cp_find(hw, lni_priv->lni.rgid, opts->lcid);
+		if (!cp_priv)
+			return ERR_PTR(-EINVAL);
+	}
+
+	/* Only privileged client can use the C_CMD_ETHERNET_TX command. */
+	if ((opts->flags & CXI_CQ_TX_ETHERNET) && !capable(CAP_NET_RAW))
+		return ERR_PTR(-EPERM);
+
+	cq = pf_get_cq_id(lni_priv, opts);
+	if (IS_ERR(cq))
+		return ERR_PTR(PTR_ERR(cq));
+
+	cq_idx = cq->cass_cq.idx;
+
+	if (evtq)
+		eq = container_of(evtq, struct cxi_eq_priv, eq);
+	else
+		eq = NULL;
+
+	cq->lni_priv = lni_priv;
+	cq->eq = eq;
+	cq->flags = opts->flags;
+	cq->cmds_len = cmds_len;
+
+	if (!lni_priv->is_vf) {
+		/* For physical function, we use user buffer if provided or we
+		 * allocate a new one
+		 */
+		if (opts_b->buf) {
+			if (!IS_ALIGNED((u64)opts_b->buf, PAGE_SIZE)) {
+				cxidev_dbg(cdev, "buffer %llx not aligned to PAGE_SIZE\n",
+					   (u64)opts_b->buf);
+				rc = -EINVAL;
+				goto put_id;
+			}
+
+			if (opts_b->is_host_mem) {
+				rc = get_dma_addr_if_contig(hw, opts_b->buf, cmds_len,
+							    DMA_BIDIRECTIONAL,
+							&cq->pages,
+							&cq->cmds_dma_addr);
+				if (rc)
+					goto put_id;
+			} else {
+				cq->md_priv = get_device_addr(lni_priv,
+							      (uintptr_t)opts_b->buf,
+							cmds_len,
+							opts_b->dmabuf_fd,
+							opts_b->dmabuf_offset,
+							&cq->cmds_dma_addr);
+				if (IS_ERR(cq->md_priv)) {
+					rc = PTR_ERR(cq->md_priv);
+					goto put_id;
+				}
+			}
+
+			cq->cmds = NULL;
+		} else {
+			/* CQ needs contiguous memory region. */
+			cmds_pages = alloc_pages_node(numa_node, GFP_KERNEL | __GFP_ZERO,
+						      cmds_order);
+			if (!cmds_pages) {
+				rc = -ENOMEM;
+				goto put_id;
+			}
+
+			cq->cmds_order = cmds_order;
+			cq->cmds = page_address(cmds_pages);
+			cq->cmds_pages = cmds_pages;
+			cq->cmds_dma_addr = dma_map_page(&hw->cdev.pdev->dev,
+							 cmds_pages, 0, cq->cmds_len,
+							 DMA_BIDIRECTIONAL);
+			if (dma_mapping_error(&hw->cdev.pdev->dev, cq->cmds_dma_addr)) {
+				rc = -ENOMEM;
+				goto free_pages;
+			}
+		}
+	} else {
+		/* For VF we use the provided dma_addr */
+		if (!cmds_dma_addr) {
+			rc = -EINVAL;
+			goto put_id;
+		}
+
+		cq->cmds_len = cmds_len;
+		cq->cmds_dma_addr = cmds_dma_addr;
+		/* PF doesn't have access to VF's virtual address space.
+		 * VF has already initialized its own cxi_cq structure.
+		 */
+		cq->cmds = NULL;
+	}
+
+	if (!is_user && !lni_priv->is_vf) {
+		phys_addr_t mmio_phys = cq_mmio_phys_addr(hw, cq_idx);
+#ifdef CONFIG_ARM64
+		if (static_branch_unlikely(&avoid_writecombine))
+			cq->cq_mmio = ioremap(mmio_phys, PAGE_SIZE);
+		else
+#endif
+		cq->cq_mmio = ioremap_wc(mmio_phys, PAGE_SIZE);
+		if (!cq->cq_mmio) {
+			cxidev_warn_once(cdev, "ioremap_wc failed\n");
+			rc = -EFAULT;
+			goto cq_release;
+		}
+	}
+
+	/* Initialize client interface structure */
+	cxi_cq_init(&cq->cass_cq, cq->cmds, cmds_count,
+		    (__force void *)cq->cq_mmio, cq_idx);
+
+	cq_n = cxi_cq_get_cqn(&cq->cass_cq);
+	if (opts->flags & CXI_CQ_IS_TX)
+		rc = setup_hw_tx_cq(hw, cq_n, opts, lni_priv, cq, eq, cp_priv);
+	else
+		rc = setup_hw_tgt_cq(hw, cq_n, opts, lni_priv, cq, eq);
+
+	if (rc)
+		goto cq_unmap;
+
+	if (cq->flags & CXI_CQ_IS_TX)
+		atomic_inc(&hw->stats.txq);
+	else
+		atomic_inc(&hw->stats.tgq);
+
+	cq_debugfs_create(cq_idx, cq, hw, lni_priv);
+
+	spin_lock(&lni_priv->res_lock);
+	list_add_tail(&cq->list, &lni_priv->cq_list);
+	spin_unlock(&lni_priv->res_lock);
+
+	refcount_inc(&lni_priv->refcount);
+	if (eq)
+		refcount_inc(&eq->refcount);
+
+	/* Grant access to the resource from the VF */
+	if (lni_priv->is_vf)
+		cass_config_sriovt(hw, true, lni_priv->vf_num,
+				   (cq->flags & CXI_CQ_IS_TX) ? cq_n :
+								(1024 + cq_n));
+
+	return &cq->cass_cq;
+
+cq_unmap:
+	if (!is_user)
+		iounmap(cq->cq_mmio);
+cq_release:
+	dma_unmap_page(&hw->cdev.pdev->dev, cq->cmds_dma_addr,
+		       cq->cmds_len, DMA_BIDIRECTIONAL);
+
+	if (cq->md_priv) {
+		cass_device_put_pages(cq->md_priv);
+		kfree(cq->md_priv);
+	}
+
+	if (cq->pages) {
+		unpin_user_pages(cq->pages, cq->cmds_len >> PAGE_SHIFT);
+		kfree(cq->pages);
+	}
+
+free_pages:
+	if (cq->cmds_pages)
+		__free_pages(cq->cmds_pages, cmds_order);
+put_id:
+	put_cq_id(cq);
+
+	return ERR_PTR(rc);
+}
+EXPORT_SYMBOL(cxi_cq_alloc_buf_internal);
+
+/**
+ * cxi_cq_alloc_buf() - Allocate a new command queue
+ *
+ * The new CQ is attached to the LNI.
+ * The CQ buffer may be supplied by the user. It must be physically
+ * contiguous.
+ *
+ * @lni: LNI to associate with the command queue.
+ * @evtq: Event Queue to associate with the command queue, for error
+ *        reporting. May be NULL.
+ * @opts_b: Options affecting the CQ.
+ * @numa_node: NUMA node ID CQ memory should be allocated from.
+ *
+ * @return: the command queue or an error pointer
+ */
+struct cxi_cq *cxi_cq_alloc_buf(struct cxi_lni *lni, struct cxi_eq *evtq,
+				const struct cxi_cq_alloc_opts_buf *opts_b,
+				int numa_node)
+{
+	struct cxi_dev *cdev = container_of(lni, struct cxi_lni_priv, lni)->dev;
+
+	if (!cdev->is_physfn)
+		return cxi_cq_alloc_buf_vf(lni, evtq, opts_b, numa_node);
+
+	return cxi_cq_alloc_buf_internal(lni, evtq, opts_b, numa_node, 0, 0);
+}
+EXPORT_SYMBOL(cxi_cq_alloc_buf);
+
+/**
+ * cxi_cq_alloc() - Allocate a new command queue
+ *
+ * The new CQ is attached to attached to the NI.
+ *
+ * @lni: LNI to associate with the command queue.
+ * @evtq: Event Queue to associate with the command queue, for error
+ *        reporting. May be NULL.
+ * @opts: Options affecting the CQ.
+ * @numa_node: NUMA node ID CQ memory should be allocated from.
+ *
+ * @return: the command queue or an error pointer
+ */
+struct cxi_cq *cxi_cq_alloc(struct cxi_lni *lni, struct cxi_eq *evtq,
+			    const struct cxi_cq_alloc_opts *opts,
+			    int numa_node)
+{
+	struct cxi_cq_alloc_opts_buf opts_b = {};
+
+	opts_b.opts = *opts;
+	return cxi_cq_alloc_buf(lni, evtq, &opts_b, numa_node);
+}
+EXPORT_SYMBOL(cxi_cq_alloc);
+
+/* Test whether a transmit CQ is done working */
+static bool is_txq_done(struct cass_dev *hw, int id)
+{
+	union c_cq_txq_rdptr_table rd_ptr;
+	union c_cq_txq_preptr_table pre_ptr;
+	union c_cq_txq_ack_ctr ack_ctr;
+
+	cass_read(hw, C_CQ_TXQ_ACK_CTR(id), &ack_ctr, sizeof(ack_ctr));
+	if (ack_ctr.mem_q_ack_ctr != 0)
+		return false;
+
+	cass_read(hw, C_CQ_TXQ_RDPTR_TABLE(id), &rd_ptr, sizeof(rd_ptr));
+	cass_read(hw, C_CQ_TXQ_PREPTR_TABLE(id), &pre_ptr, sizeof(pre_ptr));
+
+	if (rd_ptr.mem_q_rd_ptr != pre_ptr.mem_q_pre_ptr)
+		return false;
+
+	return true;
+}
+
+/* Test whether a target CQ is done working */
+static bool is_tgq_done(struct cass_dev *hw, int id)
+{
+	union c_cq_tgq_rdptr_table rd_ptr;
+	union c_cq_tgq_preptr_table pre_ptr;
+	union c_cq_tgq_ack_ctr ack_ctr;
+
+	cass_read(hw, C_CQ_TGQ_ACK_CTR(id), &ack_ctr, sizeof(ack_ctr));
+	if (ack_ctr.mem_q_ack_ctr != 0)
+		return false;
+
+	cass_read(hw, C_CQ_TGQ_RDPTR_TABLE(id), &rd_ptr, sizeof(rd_ptr));
+	cass_read(hw, C_CQ_TGQ_PREPTR_TABLE(id), &pre_ptr, sizeof(pre_ptr));
+	if (rd_ptr.mem_q_rd_ptr != pre_ptr.mem_q_pre_ptr)
+		return false;
+
+	return true;
+}
+
+/**
+ * cxi_cq_free() - Destroy a command queue
+ *
+ * @cmdq: the command queue to release
+ */
+void cxi_cq_free(struct cxi_cq *cmdq)
+{
+	struct cxi_cq_priv *cq = container_of(cmdq, struct cxi_cq_priv, cass_cq);
+	struct cxi_lni_priv *lni_priv = cq->lni_priv;
+	struct cxi_eq_priv *eq = cq->eq;
+	struct cxi_dev *cdev = lni_priv->dev;
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	unsigned int cq_n = cxi_cq_get_cqn(cmdq);
+	unsigned int mem_q_rd_ptr;
+
+	if (!cdev->is_physfn) {
+		cxi_cq_free_vf(cmdq);
+		return;
+	}
+
+	/* Remove access to this resource from a VF */
+	if (lni_priv->is_vf)
+		cass_config_sriovt(hw, false, lni_priv->vf_num,
+				   (cq->flags & CXI_CQ_IS_TX) ? cq_n :
+								(1024 + cq_n));
+
+	/* CQ invalidation requires disabling and setting the drain bit for the
+	 * CQ. This is done in cass_tx_cq_disable() and cass_tgt_cq_disable().
+	 *
+	 * By the time the read pointer is stable, the buffer is not
+	 * accessed anymore and can be freed.
+	 */
+	if (cq->flags & CXI_CQ_IS_TX) {
+		union c_cq_txq_rdptr_table rd_ptr;
+
+		cass_tx_cq_disable(hw, cq_n);
+
+		cass_read(hw, C_CQ_TXQ_RDPTR_TABLE(cq_n),
+			  &rd_ptr, sizeof(rd_ptr));
+		mem_q_rd_ptr = rd_ptr.mem_q_rd_ptr;
+
+		while (true) {
+			cass_read(hw, C_CQ_TXQ_RDPTR_TABLE(cq_n),
+				  &rd_ptr, sizeof(rd_ptr));
+			if (mem_q_rd_ptr == rd_ptr.mem_q_rd_ptr)
+				break;
+			mem_q_rd_ptr = rd_ptr.mem_q_rd_ptr;
+			udelay(1);
+		}
+	} else {
+		union c_cq_tgq_rdptr_table rd_ptr;
+
+		cass_tgt_cq_disable(hw, cq_n);
+
+		cass_read(hw, C_CQ_TGQ_RDPTR_TABLE(cq_n),
+			  &rd_ptr, sizeof(rd_ptr));
+		mem_q_rd_ptr = rd_ptr.mem_q_rd_ptr;
+		while (true) {
+			cass_read(hw, C_CQ_TGQ_RDPTR_TABLE(cq_n),
+				  &rd_ptr, sizeof(rd_ptr));
+			if (mem_q_rd_ptr == rd_ptr.mem_q_rd_ptr)
+				break;
+			mem_q_rd_ptr = rd_ptr.mem_q_rd_ptr;
+			udelay(1);
+		}
+	}
+
+	if (!lni_priv->is_vf) {
+		if (!(cq->flags & CXI_CQ_USER))
+			iounmap(cq->cq_mmio);
+
+		dma_unmap_page(&hw->cdev.pdev->dev, cq->cmds_dma_addr,
+			       cq->cmds_len, DMA_BIDIRECTIONAL);
+
+		if (cq->cmds_pages) {
+			__free_pages(cq->cmds_pages, cq->cmds_order);
+		} else {
+			if (cq->md_priv) {
+				cass_device_put_pages(cq->md_priv);
+				kfree(cq->md_priv);
+			}
+
+			if (cq->pages) {
+				unpin_user_pages(cq->pages, cq->cmds_len >> PAGE_SHIFT);
+				kfree(cq->pages);
+			}
+		}
+	}
+
+	if (eq)
+		refcount_dec(&eq->refcount);
+
+	spin_lock(&lni_priv->res_lock);
+	list_del(&cq->list);
+	list_add_tail(&cq->list, &lni_priv->cq_cleanups_list);
+	spin_unlock(&lni_priv->res_lock);
+}
+EXPORT_SYMBOL(cxi_cq_free);
+
+/* Go through the list of CQ waiting for cleanup. If the CQ is quiet,
+ * it can be freed, otherwise it stays.
+ *
+ * If force is true, the CQ will be release unconditionally.
+ */
+void finalize_cq_cleanups(struct cxi_lni_priv *lni, bool force)
+{
+	struct cxi_dev *cdev = lni->dev;
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	struct cxi_cq_priv *cq;
+	struct cxi_cq_priv *tmp;
+	struct list_head free_list;
+
+	INIT_LIST_HEAD(&free_list);
+
+	spin_lock(&lni->res_lock);
+
+	list_for_each_entry_safe(cq, tmp, &lni->cq_cleanups_list, list) {
+		unsigned int cq_n = cxi_cq_get_cqn(&cq->cass_cq);
+
+		if (!force) {
+			/* Ensure that in-flight commands are done. */
+			if (cq->flags & CXI_CQ_IS_TX) {
+				if (!is_txq_done(hw, cq_n))
+					continue;
+			} else {
+				if (!is_tgq_done(hw, cq_n))
+					continue;
+			}
+		}
+
+		list_del(&cq->list);
+		list_add(&cq->list, &free_list);
+	}
+
+	spin_unlock(&lni->res_lock);
+
+	while ((cq = list_first_entry_or_null(&free_list,
+					      struct cxi_cq_priv, list))) {
+		list_del(&cq->list);
+
+		debugfs_remove(cq->lni_dir);
+		debugfs_remove_recursive(cq->debug_dir);
+
+		refcount_dec(&lni->refcount);
+
+		if (cq->flags & CXI_CQ_IS_TX)
+			atomic_dec(&hw->stats.txq);
+		else
+			atomic_dec(&hw->stats.tgq);
+
+		put_cq_id(cq);
+	}
+}
+
+/**
+ * cxi_cq_user_info() - Get the information to mmap a cq to userspace
+ *
+ * @cmdq: the command queue
+ * @cmds_size: on return, will hold the size of the queue in 64-bytes blocks
+ * @cmds_pages: on return, will hold the pages to mmap
+ * @wp_addr: on return, will hold the CSR to control the CQ
+ * @wp_addr_size: on return, size of the CSR
+ *
+ * @return: 0, or -EINVAL is the CQ isn't for userspace
+ */
+int cxi_cq_user_info(struct cxi_cq *cmdq, size_t *cmds_size,
+		     struct page **cmds_pages, phys_addr_t *wp_addr,
+		     size_t *wp_addr_size)
+{
+	struct cxi_cq_priv *cq = container_of(cmdq, struct cxi_cq_priv, cass_cq);
+	struct cxi_lni_priv *lni_priv = cq->lni_priv;
+	struct cxi_dev *cdev = lni_priv->dev;
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+
+	if (!(cq->flags & CXI_CQ_USER))
+		return -EINVAL;
+
+	/* userspace will need to know what pages to mmap. */
+	*cmds_size = cq->cmds_len;
+	*cmds_pages = cq->cmds_pages;
+
+	*wp_addr = cq_mmio_phys_addr(hw, cq->cass_cq.idx);
+	*wp_addr_size = PAGE_SIZE;
+
+	return 0;
+}
+EXPORT_SYMBOL(cxi_cq_user_info);
+
+/**
+ * cxi_cq_ack_counter_vf() - Get the current ack counter for a CQ in VF
+ *
+ * @cmdq: CQ to get current ack counter for.
+ *
+ * Return: Current ack counter value.
+ */
+static unsigned int cxi_cq_ack_counter_vf(struct cxi_cq *cmdq)
+{
+	struct cxi_cq_priv_vf *cq_priv_vf =
+		container_of(cmdq, struct cxi_cq_priv_vf, cass_cq);
+	struct cxi_dev *dev = cq_priv_vf->lni_priv->dev;
+	const struct cxi_cq_ack_counter_cmd cmd = {
+		.op = CXI_OP_CQ_ACK_COUNTER,
+		.cq = cq_priv_vf->cass_cq.idx,
+	};
+	struct cxi_cq_ack_counter_resp resp;
+	size_t resp_len = sizeof(resp);
+	int rc;
+
+	rc = cxi_send_msg_to_pf(dev, &cmd, sizeof(cmd), &resp, &resp_len);
+	if (rc)
+		return rc;
+
+	return resp.ack_counter;
+}
+
+/**
+ * cxi_cq_ack_counter() - Get the current ack counter for a CQ.
+ *
+ * @cq: CQ to get current ack counter for.
+ *
+ * Return: Current ack counter value.
+ */
+unsigned int cxi_cq_ack_counter(struct cxi_cq *cq)
+{
+	struct cxi_cq_priv *cq_priv =
+		container_of(cq, struct cxi_cq_priv, cass_cq);
+	struct cass_dev *hw =
+		container_of(cq_priv->lni_priv->dev, struct cass_dev, cdev);
+	unsigned int cq_n = cxi_cq_get_cqn(cq);
+	union c_cq_txq_ack_ctr txq_ack_ctr;
+	union c_cq_tgq_ack_ctr tgq_ack_ctr;
+	unsigned int ack_ctr;
+
+	if (!hw->cdev.is_physfn)
+		return cxi_cq_ack_counter_vf(cq);
+
+	if (cq_priv->flags & CXI_CQ_IS_TX) {
+		cass_read(hw, C_CQ_TXQ_ACK_CTR(cq_n), &txq_ack_ctr,
+			  sizeof(txq_ack_ctr));
+		ack_ctr = txq_ack_ctr.mem_q_ack_ctr;
+	} else {
+		cass_read(hw, C_CQ_TGQ_ACK_CTR(cq_n), &tgq_ack_ctr,
+			  sizeof(tgq_ack_ctr));
+		ack_ctr = tgq_ack_ctr.mem_q_ack_ctr;
+	}
+	return ack_ctr;
+}
+EXPORT_SYMBOL(cxi_cq_ack_counter);
diff --git a/drivers/net/ethernet/hpe/ss1/cass_ct.c b/drivers/net/ethernet/hpe/ss1/cass_ct.c
new file mode 100644
index 000000000000..f4d642884671
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_ct.c
@@ -0,0 +1,639 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Create and destroy Cassini counting events.
+ * Copyright 2018, 2024-2026 Hewlett Packard Enterprise Development LP
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/hpe/cxi/cxi.h>
+#include <linux/iopoll.h>
+
+#include "cass_core.h"
+#include "cxi_internal.h"
+#include "cass_ss1_debugfs.h"
+#include "cxi_vf_cmd.h"
+
+/* Initializes (if init is true) or cancel (if init is false) pending
+ * triggered operations on a CT.
+ */
+static int set_hw_state(struct cass_dev *hw, unsigned int ctn,
+			bool init)
+{
+	void __iomem *csr = cass_csr(hw, C_CQ_CFG_INIT_CT_HW_STATE);
+	union c_cq_cfg_init_ct_hw_state ct_hw_state;
+	int rc;
+
+	mutex_lock(&hw->ct_init_lock);
+
+	ct_hw_state.qw = 0;
+	ct_hw_state.ct_handle = ctn;
+	if (init)
+		ct_hw_state.init = 1;
+	else
+		ct_hw_state.cancel = 1;
+	cass_write(hw, C_CQ_CFG_INIT_CT_HW_STATE, &ct_hw_state.qw,
+		   sizeof(ct_hw_state));
+
+	rc = readq_poll_timeout(csr, ct_hw_state.qw,
+				ct_hw_state.pending == 0, 1, 1000000);
+	cxidev_WARN_ONCE(&hw->cdev, rc, "Timeout waiting for CT operation (%d)\n",
+			 init);
+
+	/* Need to zero cancel and init fields so that they can be reused. */
+	memset(&ct_hw_state, 0, sizeof(ct_hw_state));
+	cass_write(hw, C_CQ_CFG_INIT_CT_HW_STATE, &ct_hw_state.qw,
+		   sizeof(ct_hw_state));
+
+	mutex_unlock(&hw->ct_init_lock);
+
+	return rc;
+}
+
+/* Map the wb buffer using DMA address. Pin buffer if from user space. */
+static int ct_wb_map(struct cass_dev *hw, const struct cxi_ct_priv *ct_priv,
+		     struct ct_wb_desc *desc, struct c_ct_writeback *wb)
+{
+	static const struct c_ct_writeback wb_init = {};
+	struct device *device = &hw->cdev.pdev->dev;
+	dma_addr_t dma_addrs;
+	int rc;
+
+	desc->md_priv = NULL;
+	desc->page = NULL;
+
+	if (!ct_priv->is_user) {
+		*wb = wb_init;
+
+		if (is_vmalloc_addr(wb)) {
+			desc->wb_dma_addr = dma_map_page(device,
+							 vmalloc_to_page(wb),
+							 offset_in_page(wb),
+							 sizeof(*wb), DMA_FROM_DEVICE);
+			desc->is_map_page = 1;
+		} else {
+			desc->wb_dma_addr = dma_map_single(device, wb, sizeof(*wb),
+							   DMA_FROM_DEVICE);
+		}
+		if (dma_mapping_error(&hw->cdev.pdev->dev, desc->wb_dma_addr))
+			return -ENOMEM;
+
+		return 0;
+	}
+
+	rc = pin_user_pages_fast((unsigned long)wb, 1,
+				 FOLL_WRITE | FOLL_LONGTERM, &desc->page);
+	if (rc == 1) {
+		desc->wb_dma_addr = dma_map_single(device,
+						   page_address(desc->page) +
+						   offset_in_page(wb),
+						   sizeof(*wb), DMA_FROM_DEVICE);
+		if (dma_mapping_error(device, desc->wb_dma_addr)) {
+			unpin_user_page(desc->page);
+			desc->page = NULL;
+			return -ENOMEM;
+		}
+
+		return 0;
+	}
+
+	desc->md_priv = cass_device_md(ct_priv->lni_priv, (u64)wb, sizeof(*wb),
+				       &dma_addrs);
+	if (IS_ERR(desc->md_priv))
+		return PTR_ERR(desc->md_priv);
+
+	desc->wb_dma_addr = dma_addrs + offset_in_page(wb);
+
+	return 0;
+}
+
+static void ct_wb_unmap(struct cass_dev *hw, const struct cxi_ct_priv *ct_priv,
+			struct ct_wb_desc *desc)
+{
+	if (desc->wb_dma_addr == 0)
+		return;
+
+	/* The presence of md_priv indicates device memory which is unmapped
+	 * when the pages are released.
+	 */
+	if (desc->md_priv == NULL) {
+		if (desc->is_map_page)
+			dma_unmap_page(&hw->cdev.pdev->dev, desc->wb_dma_addr,
+				       sizeof(struct c_ct_writeback),
+				       DMA_FROM_DEVICE);
+		else
+			dma_unmap_single(&hw->cdev.pdev->dev, desc->wb_dma_addr,
+					 sizeof(struct c_ct_writeback),
+					 DMA_FROM_DEVICE);
+	}
+
+	if (!ct_priv->is_user)
+		return;
+
+	if (desc->page) {
+		unpin_user_page(desc->page);
+		desc->page = NULL;
+	} else if (desc->md_priv) {
+		p2p_ops.put_pages(desc->md_priv);
+		kfree(desc->md_priv);
+		desc->md_priv = NULL;
+	}
+}
+
+static struct cxi_ct *cxi_ct_alloc_vf(struct cxi_lni *lni,
+				      struct c_ct_writeback *wb, bool is_user)
+{
+	struct cxi_dev *dev = container_of(lni, struct cxi_lni_priv_vf, lni)->dev;
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+	struct cxi_ct_priv *ct_priv;
+	int rc;
+	int ctn;
+	struct cxi_ct_alloc_cmd_vf cmd = {
+		.base.op = CXI_OP_CT_ALLOC,
+		.base.lni = lni->id,
+	};
+	struct cxi_ct_alloc_resp resp = {};
+	size_t resp_len = sizeof(resp);
+	struct cxi_ct_free_cmd free_cmd = {
+		.op = CXI_OP_CT_FREE,
+	};
+
+	/* WB address must be 8-byte aligned. */
+	if (!IS_ALIGNED((u64)wb, 8))
+		return ERR_PTR(-EINVAL);
+
+	ct_priv = kzalloc(sizeof(*ct_priv), GFP_KERNEL);
+	if (!ct_priv)
+		return ERR_PTR(-ENOMEM);
+	ct_priv->lni_priv = container_of(lni, struct cxi_lni_priv, lni);
+	ct_priv->is_user = is_user;
+
+	/* A WB address context of zero means that WB is disabled for the CT. */
+	if (wb) {
+		rc = ct_wb_map(hw, ct_priv, &ct_priv->wb_desc, wb);
+		if (rc)
+			goto free_ct_priv;
+	} else {
+		ct_priv->wb_desc.wb_dma_addr = 0;
+	}
+
+	cmd.wb_dma_addr = ct_priv->wb_desc.wb_dma_addr;
+
+	rc = cxi_send_msg_to_pf(dev, &cmd, sizeof(cmd), &resp, &resp_len);
+	if (rc)
+		goto unmap_wb;
+
+	ctn = resp.ctn;
+	ct_priv->ct.ctn = ctn;
+
+	if (!is_user) {
+		phys_addr_t mmio_phys = hw->regs_base + C_MEMORG_CQ_TOU +
+				ctn * C_TOU_LAUNCH_PAGE_SIZE;
+		ct_priv->ct_mmio = ioremap(mmio_phys, PAGE_SIZE);
+		if (!ct_priv->ct_mmio) {
+			cxidev_warn_once(dev, "ioremap failed\n");
+			rc = -ENOMEM;
+			goto free_pf_ct;
+		}
+	}
+
+	return &ct_priv->ct;
+
+free_pf_ct:
+	free_cmd.ctn = ctn;
+	resp_len = 0;
+	cxi_send_msg_to_pf(dev, &free_cmd, sizeof(free_cmd), NULL, &resp_len);
+unmap_wb:
+	if (wb)
+		ct_wb_unmap(hw, ct_priv, &ct_priv->wb_desc);
+free_ct_priv:
+	kfree(ct_priv);
+	return ERR_PTR(rc);
+}
+
+/**
+ * cxi_ct_alloc_internal() - Allocate a counting event (internal implementation
+ * to handle VF requests)
+ *
+ * @lni: LNI counting event is allocated against
+ * @wb: User defined writeback buffer, must be DMA-able.
+ * @is_user: Non-zero value if the counting event is for userspace.
+ * @wb_dma_addr: Pre-mapped DMA address for writeback buffer (for requests from VF)
+ *
+ * Writeback buffer is optional. If @wb is NULL, the wb field in the returned
+ * cxi_ct will also be NULL. @wb must be NULL in requests coming from VFs, the
+ * writeback buffer (if any) is passed using wb_dma_addr, having already been
+ * mapped by the VF.
+ *
+ * Return: Valid pointer on success. Else, negative errno pointer.
+ */
+struct cxi_ct *cxi_ct_alloc_internal(struct cxi_lni *lni,
+				     struct c_ct_writeback *wb, bool is_user,
+				     dma_addr_t wb_dma_addr)
+{
+	struct cxi_lni_priv *lni_priv =
+		container_of(lni, struct cxi_lni_priv, lni);
+	struct cxi_dev *dev = lni_priv->dev;
+	struct cass_dev *hw =
+		container_of(dev, struct cass_dev, cdev);
+	struct cxi_ct_priv *ct_priv;
+	u16 wb_ac;
+	int rc;
+	int ctn;
+
+	/* WB address must be 8-byte aligned. */
+	if (!IS_ALIGNED((u64)wb, 8))
+		return ERR_PTR(-EINVAL);
+
+	ct_priv = kzalloc(sizeof(*ct_priv), GFP_KERNEL);
+	if (!ct_priv)
+		return ERR_PTR(-ENOMEM);
+	ct_priv->lni_priv = lni_priv;
+	ct_priv->is_user = is_user;
+
+	/* Check the associated service to see if this CT can be allocated */
+	rc = cxi_rgroup_alloc_resource(lni_priv->rgroup, CXI_RESOURCE_CT);
+	if (rc)
+		goto free_ct_priv;
+
+	/*
+	 * A WB address context of zero means that WB is disabled for
+	 * the CT.
+	 */
+	if (wb) {
+		rc = ct_wb_map(hw, ct_priv, &ct_priv->wb_desc, wb);
+		if (rc)
+			goto dec_rsrc_use;
+		wb_ac = lni_priv->phys_ac;
+	} else if (wb_dma_addr) {
+		ct_priv->wb_desc.wb_dma_addr = wb_dma_addr;
+		wb_ac = lni_priv->phys_ac;
+	} else {
+		ct_priv->wb_desc.wb_dma_addr = 0;
+		wb_ac = C_AC_NONE;
+	}
+
+	/* Allocate and configure the counting event. */
+	rc = ida_alloc_range(&hw->ct_table, 1, C_NUM_CTS - 1, GFP_KERNEL);
+	if (rc < 0)
+		goto free_md_priv;
+	ctn = rc;
+
+	if (!is_user) {
+		phys_addr_t mmio_phys = hw->regs_base + C_MEMORG_CQ_TOU +
+				ctn * C_TOU_LAUNCH_PAGE_SIZE;
+		ct_priv->ct_mmio = ioremap(mmio_phys, PAGE_SIZE);
+		if (!ct_priv->ct_mmio) {
+			cxidev_warn_once(dev, "ioremap failed\n");
+			rc = -ENOMEM;
+			goto ct_release;
+		}
+	}
+
+	/* Reset the hardware CT. */
+	rc = set_hw_state(hw, ctn, true);
+	if (rc)
+		goto ct_unmap;
+
+	if (lni_priv->is_vf)
+		cass_config_sriovt(hw, true, lni_priv->vf_num, 2048 + ctn);
+
+	/* Finally the CT can be enabled */
+	cxi_ct_init(&ct_priv->ct, wb, ctn, (__force u64 *)ct_priv->ct_mmio);
+	cass_ct_enable(hw, ctn, lni_priv->lni.rgid, ct_priv->wb_desc.wb_dma_addr, wb_ac);
+
+	/* Track the counting event. */
+	spin_lock(&lni_priv->res_lock);
+	list_add_tail(&ct_priv->entry, &lni_priv->ct_list);
+	refcount_inc(&lni_priv->refcount);
+	atomic_inc(&hw->stats.ct);
+	spin_unlock(&lni_priv->res_lock);
+
+	ct_debugfs_setup(ct_priv->ct.ctn, ct_priv, hw, lni_priv);
+
+	return &ct_priv->ct;
+
+ct_unmap:
+	if (!is_user)
+		iounmap(ct_priv->ct_mmio);
+ct_release:
+	ida_free(&hw->ct_table, ctn);
+free_md_priv:
+	if (wb)
+		ct_wb_unmap(hw, ct_priv, &ct_priv->wb_desc);
+dec_rsrc_use:
+	cxi_rgroup_free_resource(lni_priv->rgroup, CXI_RESOURCE_CT);
+free_ct_priv:
+	kfree(ct_priv);
+
+	return ERR_PTR(rc);
+}
+EXPORT_SYMBOL(cxi_ct_alloc_internal);
+
+/**
+ * cxi_ct_alloc() - Allocate a counting event
+ *
+ * @lni: LNI counting event is allocated against
+ * @wb: User defined writeback buffer, must be DMA-able.
+ * @is_user: Non-zero value if the counting event is for userspace.
+ *
+ * Writeback buffer is optional. If @wb is NULL, the wb field in the returned
+ * cxi_ct will also be NULL.
+ *
+ * Return: Valid pointer on success. Else, negative errno pointer.
+ */
+struct cxi_ct *cxi_ct_alloc(struct cxi_lni *lni,
+			    struct c_ct_writeback *wb, bool is_user)
+{
+	struct cxi_dev *dev = container_of(lni, struct cxi_lni_priv, lni)->dev;
+
+	if (dev->is_physfn)
+		return cxi_ct_alloc_internal(lni, wb, is_user, 0);
+	else
+		return cxi_ct_alloc_vf(lni, wb, is_user);
+}
+EXPORT_SYMBOL(cxi_ct_alloc);
+
+/* Wait for credits_in_use.tou_wb_credits to drain to 0. We then know that
+ * no more writebacks are in progress.
+ */
+static int drain_wb_credits(struct cass_dev *hw)
+{
+	ktime_t timeout;
+	int timeout_us = 1000;
+	union c_cq_sts_credits_in_use in_use;
+
+	timeout = ktime_add_us(ktime_get(), timeout_us);
+
+	for (;;) {
+		cass_read(hw, C_CQ_STS_CREDITS_IN_USE, &in_use,
+			  sizeof(in_use));
+
+		if (in_use.tou_wb_credits == 0)
+			return 0;
+
+		if (ktime_compare(ktime_get(), timeout) > 0)
+			return -ETIMEDOUT;
+
+		usleep_range(5, 20);
+	}
+}
+
+static int cxi_ct_wb_update_vf(struct cxi_ct *ct, struct c_ct_writeback *wb)
+{
+	struct cxi_ct_priv *ct_priv = container_of(ct, struct cxi_ct_priv, ct);
+	struct cxi_dev *dev = ct_priv->lni_priv->dev;
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+	struct cxi_ct_wb_update_cmd_vf cmd = {
+		.base.op = CXI_OP_CT_WB_UPDATE,
+		.base.ctn = ct->ctn,
+	};
+	size_t resp_len = 0;
+	struct ct_wb_desc new_desc;
+	int rc;
+
+	if (!wb)
+		return -EINVAL;
+
+	rc = ct_wb_map(hw, ct_priv, &new_desc, wb);
+	if (rc)
+		return rc;
+
+	cmd.wb_dma_addr = new_desc.wb_dma_addr;
+
+	rc = cxi_send_msg_to_pf(dev, &cmd, sizeof(cmd), NULL, &resp_len);
+	if (rc)
+		goto unmap_new_desc;
+
+	/* Previous pinned pages need to be cleaned up. */
+	ct_wb_unmap(hw, ct_priv, &ct_priv->wb_desc);
+	ct_priv->wb_desc = new_desc;
+
+	/* finally, save the new wb */
+	ct->wb = wb;
+
+	return 0;
+
+unmap_new_desc:
+	ct_wb_unmap(hw, ct_priv, &new_desc);
+	return rc;
+}
+
+/**
+ * cxi_ct_wb_update_internal() - Update a counting event with a new writeback
+ * address (internal implementation to handle VF requests)
+ *
+ * Flush by setting c_cq_cfg_credit_limits.tou_wb_credits to 0. When
+ * c_cq_sts_credits_in_use.tou_wb_credits is 0, then no writebacks are
+ * in progress. Re-enable the c_cq_cfg_credit_limits.tou_wb_credits.
+ *
+ * @ct: Counting event
+ * @wb: User defined writeback buffer, must be DMA-able.
+ * @wb_dma_addr: Pre-mapped DMA address for writeback buffer (for requests from VF)
+ *
+ * As documented in cxi_ct_alloc_internal(), @wb must be NULL in requests coming
+ * from VFs, the new writeback buffer is passed using @wb_dma_addr, having
+ * already been mapped by the VF.
+ */
+int cxi_ct_wb_update_internal(struct cxi_ct *ct, struct c_ct_writeback *wb,
+			      dma_addr_t wb_dma_addr)
+{
+	struct cxi_ct_priv *ct_priv = container_of(ct, struct cxi_ct_priv, ct);
+	struct cxi_lni_priv *lni_priv = ct_priv->lni_priv;
+	struct cass_dev *hw =
+		container_of(lni_priv->dev, struct cass_dev, cdev);
+	union c_cq_cfg_credit_limits limits = {};
+	union c_cq_cfg_ct_wb_mem_addr mem = {
+		.wb_mem_context = lni_priv->phys_ac,
+	};
+	struct ct_wb_desc new_desc = {};
+	int wb_credits = 0;
+	int rc = 0;
+
+	// TODO: write pycxi test for this fn + driver test
+
+	if (!wb && !wb_dma_addr)
+		return -EINVAL;
+
+	if (!lni_priv->is_vf) {
+		rc = ct_wb_map(hw, ct_priv, &new_desc, wb);
+		if (rc)
+			return rc;
+	} else {
+		new_desc.wb_dma_addr = wb_dma_addr;
+	}
+
+	mutex_lock(&hw->ct_init_lock);
+
+	/* If wb is valid, it may be in use. */
+	if (ct_priv->wb_desc.wb_dma_addr) {
+		/* stop wb writes */
+		cass_read(hw, C_CQ_CFG_CREDIT_LIMITS, &limits, sizeof(limits));
+		wb_credits = limits.tou_wb_credits;
+		limits.tou_wb_credits = 0;
+		cass_write(hw, C_CQ_CFG_CREDIT_LIMITS, &limits, sizeof(limits));
+
+		rc = drain_wb_credits(hw);
+		if (rc)
+			goto set_limit;
+	}
+
+	mem.wb_mem_addr = new_desc.wb_dma_addr >> 3;
+	cass_write(hw, C_CQ_CFG_CT_WB_MEM_ADDR(ct->ctn), &mem, sizeof(mem));
+	cass_flush_pci(hw);
+
+	/* Previous pinned pages need to be cleaned up. */
+	if (!lni_priv->is_vf)
+		ct_wb_unmap(hw, ct_priv, &ct_priv->wb_desc);
+
+set_limit:
+	if (ct_priv->wb_desc.wb_dma_addr) {
+		limits.tou_wb_credits = wb_credits;
+		cass_write(hw, C_CQ_CFG_CREDIT_LIMITS, &limits, sizeof(limits));
+	}
+
+	/* finally, save the new wb */
+	if (!rc) {
+		ct->wb = wb;
+		ct_priv->wb_desc = new_desc;
+	}
+	mutex_unlock(&hw->ct_init_lock);
+
+	if (rc && !lni_priv->is_vf)
+		ct_wb_unmap(hw, ct_priv, &new_desc);
+
+	return rc;
+}
+EXPORT_SYMBOL(cxi_ct_wb_update_internal);
+
+/**
+ * cxi_ct_wb_update() - Update a counting event with a new writeback address.
+ *
+ * Flush by setting c_cq_cfg_credit_limits.tou_wb_credits to 0. When
+ * c_cq_sts_credits_in_use.tou_wb_credits is 0, then no writebacks are
+ * in progress. Re-enable the c_cq_cfg_credit_limits.tou_wb_credits.
+ *
+ * @ct: Counting event
+ * @wb: User defined writeback buffer, must be DMA-able.
+ */
+int cxi_ct_wb_update(struct cxi_ct *ct, struct c_ct_writeback *wb)
+{
+	struct cxi_ct_priv *ct_priv = container_of(ct, struct cxi_ct_priv, ct);
+
+	if (!ct_priv->lni_priv->dev->is_physfn)
+		return cxi_ct_wb_update_vf(ct, wb);
+	else
+		return cxi_ct_wb_update_internal(ct, wb, 0);
+}
+EXPORT_SYMBOL(cxi_ct_wb_update);
+
+static void cxi_ct_free_vf(struct cxi_ct *ct)
+{
+	struct cxi_ct_priv *ct_priv = container_of(ct, struct cxi_ct_priv, ct);
+	struct cxi_dev *dev = ct_priv->lni_priv->dev;
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+	struct cxi_ct_free_cmd cmd = {
+		.op = CXI_OP_CT_FREE,
+		.ctn = ct->ctn,
+	};
+	size_t resp_len = 0;
+
+	/* Inform PF to free the CT */
+	cxi_send_msg_to_pf(dev, &cmd, sizeof(cmd), NULL, &resp_len);
+
+	if (!ct_priv->is_user)
+		iounmap(ct_priv->ct_mmio);
+
+	ct_wb_unmap(hw, ct_priv, &ct_priv->wb_desc);
+}
+
+/**
+ * cxi_ct_free() - Free a counting event.
+ * @ct: Counting event
+ */
+void cxi_ct_free(struct cxi_ct *ct)
+{
+	struct cxi_ct_priv *ct_priv = container_of(ct, struct cxi_ct_priv, ct);
+	struct cxi_lni_priv *lni_priv = ct_priv->lni_priv;
+	struct cass_dev *hw =
+		container_of(lni_priv->dev, struct cass_dev, cdev);
+
+	if (!hw->cdev.is_physfn) {
+		cxi_ct_free_vf(ct);
+		return;
+	}
+
+	/* Change ownership to the driver. */
+	cass_ct_disable(hw, ct_priv->ct.ctn);
+
+	if (lni_priv->is_vf)
+		cass_config_sriovt(hw, false, lni_priv->vf_num, 2048 + ct_priv->ct.ctn);
+
+	/* Cancel all pending operations. */
+	set_hw_state(hw, ct_priv->ct.ctn, false);
+
+	spin_lock(&lni_priv->res_lock);
+	list_del(&ct_priv->entry);
+	spin_unlock(&lni_priv->res_lock);
+
+	if (!ct_priv->is_user)
+		iounmap(ct_priv->ct_mmio);
+
+	if (!lni_priv->is_vf)
+		ct_wb_unmap(hw, ct_priv, &ct_priv->wb_desc);
+
+	/* Hang the CT on the LNI pending deletion list, to be
+	 * released later
+	 */
+	spin_lock(&lni_priv->res_lock);
+	list_add_tail(&ct_priv->entry, &lni_priv->ct_cleanups_list);
+	spin_unlock(&lni_priv->res_lock);
+}
+EXPORT_SYMBOL(cxi_ct_free);
+
+/* Finish releasing all the CTs on the deletion pending list */
+void finalize_ct_cleanups(struct cxi_lni_priv *lni)
+{
+	struct cxi_dev *dev = lni->dev;
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+	struct cxi_ct_priv *ct;
+
+	while ((ct = list_first_entry_or_null(&lni->ct_cleanups_list,
+					      struct cxi_ct_priv, entry))) {
+		list_del(&ct->entry);
+
+		debugfs_remove(ct->lni_dir);
+		debugfs_remove_recursive(ct->debug_dir);
+
+		refcount_dec(&lni->refcount);
+		atomic_dec(&hw->stats.ct);
+		cxi_rgroup_free_resource(lni->rgroup, CXI_RESOURCE_CT);
+		ida_free(&hw->ct_table, ct->ct.ctn);
+		kfree(ct);
+	}
+}
+
+/**
+ * cxi_ct_user_info() - Get userspace mmap info for counting event doorbell.
+ * @ct: Counting event
+ * @doorbell_addr: On success, will contain the address of the doorbell.
+ * @doorbell_size: On success, will contain the size of the doorbell.
+ *
+ * Return: On success, returns zero. On error, returns a negative error number.
+ */
+int cxi_ct_user_info(struct cxi_ct *ct, phys_addr_t *doorbell_addr,
+		     size_t *doorbell_size)
+{
+	struct cxi_ct_priv *ct_priv = container_of(ct, struct cxi_ct_priv, ct);
+	struct cass_dev *hw = container_of(ct_priv->lni_priv->dev,
+					   struct cass_dev, cdev);
+
+	if (!ct_priv->is_user)
+		return -EINVAL;
+
+	*doorbell_addr = hw->regs_base + C_MEMORG_CQ_TOU +
+		(ct->ctn * C_TOU_LAUNCH_PAGE_SIZE);
+	*doorbell_size = PAGE_SIZE;
+
+	return 0;
+}
+EXPORT_SYMBOL(cxi_ct_user_info);
diff --git a/drivers/net/ethernet/hpe/ss1/cass_dmac.c b/drivers/net/ethernet/hpe/ss1/cass_dmac.c
new file mode 100644
index 000000000000..5c1e4f335a6d
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_dmac.c
@@ -0,0 +1,597 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2020-2021, 2024-2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/iopoll.h>
+#include <linux/bitmap.h>
+
+#include "cass_core.h"
+#include "cass_ss1_debugfs.h"
+
+#define DMAC_DESC_INDEX_UNSPECIFIED		((u16)(~0))
+
+/*
+ * A transfer copies at most a few KB of NIC CSRs and normally finishes in
+ * well under a millisecond, so this is only the limit for a stuck engine.
+ */
+#define CASS_DMAC_XFER_TIMEOUT_MS		5000
+
+/*
+ * _must_ only be called when holding mutex hw->dmac.lock
+ * TODO: add kernel 'requires_lock' annotations
+ */
+static int cass_dmac_desc_set_id_verify(struct cass_dev *hw, int set_id)
+{
+	if (set_id < 0 || set_id >= DMAC_DESC_SET_COUNT ||
+	    hw->dmac.desc_sets[set_id].count == 0)
+		return -EINVAL;
+	return 0;
+}
+
+static void dmac_desc_zero_n(struct cass_dev *hw, u16 desc_index, u16 count)
+{
+	cass_clear(hw, C_PI_CFG_DMAC_DESC(desc_index),
+		   sizeof(union c_pi_cfg_dmac_desc) * count);
+	cass_flush_pci(hw);
+}
+
+static void dmac_desc_zero_all(struct cass_dev *hw)
+{
+	dmac_desc_zero_n(hw, 0, C_PI_CFG_DMAC_DESC_NUM_AVAILABLE_ENTRIES -
+			 C_PI_CFG_DMAC_DESC_NUM_RSVD_ENTRIES);
+}
+
+static void dmac_disable(struct cass_dev *hw)
+{
+	/* Disable DMAC */
+	cass_clear(hw, C_PI_CFG_DMAC, C_PI_CFG_DMAC_SIZE);
+	cass_flush_pci(hw);
+}
+
+static void dmac_enable(struct cass_dev *hw, u16 desc_index)
+{
+	union c_pi_cfg_dmac dmac = {
+		.desc_index	  = desc_index,
+		.enable		  = 1,
+		.start		  = 1,
+		.cpl_event_enable = 1,
+		.irq_on_done	  = 1,
+		.irq_on_error	  = 1
+	};
+
+	/* Enable DMAC */
+	cass_write(hw, C_PI_CFG_DMAC, &dmac, sizeof(dmac));
+	cass_flush_pci(hw);
+}
+
+/**
+ * cxi_dmac_desc_set_reset() - reset number used to zero
+ * @cdev: the device
+ * @set_id: dmac descriptor set id
+ *
+ * reset the number of used descriptors associated with the supplied
+ * dmac descriptor set id to zero
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+int cxi_dmac_desc_set_reset(struct cxi_dev *cdev, int set_id)
+{
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	int retval;
+
+	if (!cdev->is_physfn)
+		return -EPERM;
+
+	mutex_lock(&hw->dmac.lock);
+
+	retval = cass_dmac_desc_set_id_verify(hw, set_id);
+	if (retval == 0)
+		hw->dmac.desc_sets[set_id].numused = 0;
+
+	mutex_unlock(&hw->dmac.lock);
+	return retval;
+}
+EXPORT_SYMBOL(cxi_dmac_desc_set_reset);
+
+/**
+ * cxi_dmac_desc_set_add() - write the next descriptor in the set
+ * @cdev: the device
+ * @set_id: dmac descriptor set id
+ * @dst: DMA address of host buffer
+ * @src: starting nic csr offset
+ * @len: length to read, in bytes. must be a multiple of 8 (sizeof(u64))
+ *
+ * use the supplied parameters to write the appropriate values to the
+ * next descriptor in the supplied dmac descriptor set id and
+ * if this is not the first descriptor in the set written then set
+ * the continue flag of previous descriptor to true
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+int cxi_dmac_desc_set_add(struct cxi_dev *cdev, int set_id, dma_addr_t dst,
+			  u32 src, size_t len)
+{
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	int retval = 0;
+	u16 count;
+	u16 index;
+	u16 numused;
+	union c_pi_cfg_dmac_desc desc = {};
+	u32 src_end;
+	const u32 u64count = len / sizeof(u64);
+
+	if (!cdev->is_physfn)
+		return -EPERM;
+
+	/*
+	 * dst address and src offset must be 64-bit aligned
+	 *
+	 * len must be a multiple of 8 (sizeof(u64))
+	 *
+	 * u64count can not be zero and u64count - 1 must fit in 20-bits
+	 *
+	 * cxi csr offsets are within 29 bits
+	 *      the starting & ending src offsets
+	 *      must be contained in 29 bits.
+	 *
+	 * if src offset crosses 23 bit addr boundary,
+	 * then src must be 128 byte aligned
+	 */
+
+	if (!IS_ALIGNED(dst, 8)) {
+		cxidev_err(cdev,
+			   "destination address is not 64-bit aligned: 0x%016llx\n",
+			   dst);
+		return -EINVAL;
+	}
+
+	if ((len % sizeof(u64)) != 0) {
+		cxidev_err(cdev,
+			   "length is not multiple of 8 (sizeof(u64)): %ld\n",
+			   len);
+		return -EINVAL;
+	}
+	if (u64count == 0) {
+		cxidev_err(cdev, "length is zero\n");
+		return -EINVAL;
+	}
+	if (u64count > 0x00100000UL || len != u64count * sizeof(u64)) {
+		cxidev_err(cdev, "length is too large: %ld\n", len);
+		return -EINVAL;
+	}
+
+	if (!IS_ALIGNED(src, 8)) {
+		cxidev_err(cdev,
+			   "source offset is not 64-bit aligned: 0x%08x\n",
+			   src);
+		return -EINVAL;
+	}
+	if (src >= C_MEMORG_CSR_SIZE) {
+		cxidev_err(cdev,
+			   "starting source offset is out of range: 0x%08x\n",
+			   src);
+		return -EINVAL;
+	}
+	src_end = src + (u64count - 1) * sizeof(u64);
+	if (src_end >= C_MEMORG_CSR_SIZE) {
+		cxidev_err(cdev,
+			   "ending source offset is out of range: 0x%08x\n",
+			   src_end);
+		return -EINVAL;
+	}
+	if ((src & 0xff000000UL) != (src_end & 0xff000000UL) &&
+	    (src & 0x7fUL) != 0) {
+		cxidev_err(cdev,
+			   "source offset should be 128-byte aligned when transfer crosses bit-23: 0x%08x 0x%08x\n",
+			   src, src_end);
+		return -EINVAL;
+	}
+
+	mutex_lock(&hw->dmac.lock);
+
+	retval = cass_dmac_desc_set_id_verify(hw, set_id);
+	if (retval != 0)
+		goto __cxi_dmac_desc_set_add_0;
+
+	count = hw->dmac.desc_sets[set_id].count;
+	index = hw->dmac.desc_sets[set_id].index;
+	numused  = hw->dmac.desc_sets[set_id].numused;
+
+	if (numused == count) {
+		retval = -ENOSPC;
+		goto __cxi_dmac_desc_set_add_0;
+	}
+
+	desc.dst_addr = dst >> 3;
+	desc.src_addr = src >> 3;
+	desc.length   = u64count - 1;
+
+	/*
+	 * write the descriptor
+	 */
+	cass_write(hw, C_PI_CFG_DMAC_DESC(index + numused), &desc, sizeof(desc));
+
+	/*
+	 * if the added descriptor is not the first one (0th index) of the set,
+	 * then modify previous descriptor's cont flag to be 1 indicating to
+	 * chain to the next descriptor.
+	 */
+	if (numused != 0) {
+		cass_read(hw, C_PI_CFG_DMAC_DESC(index + numused - 1) +
+			  sizeof(desc.qw[0]), &desc.qw[1],
+			  sizeof(desc.qw[1]));
+		desc.cont = 1;
+		cass_write(hw, C_PI_CFG_DMAC_DESC(index + numused - 1) +
+			   sizeof(desc.qw[0]), &desc.qw[1],
+			   sizeof(desc.qw[1]));
+	}
+
+	++hw->dmac.desc_sets[set_id].numused;
+
+__cxi_dmac_desc_set_add_0:
+	mutex_unlock(&hw->dmac.lock);
+	return retval;
+}
+EXPORT_SYMBOL(cxi_dmac_desc_set_add);
+
+/*
+ * _must_ only be called when holding mutex hw->dmac.lock
+ */
+static void cass_dmac_desc_set_id_fill(struct cass_dev *hw, int set_id,
+				       u16 num_descs, u16 index,
+				       const char *name)
+{
+	cxidev_dbg(&hw->cdev, "set_id=%d num_descs=%u index=%u\n",
+		   set_id, num_descs, index);
+	hw->dmac.desc_sets[set_id].count = num_descs;
+	hw->dmac.desc_sets[set_id].index = index;
+	hw->dmac.desc_sets[set_id].numused  = 0;
+	hw->dmac.desc_sets[set_id].name = name;
+}
+
+/*
+ * _must_ only be called when holding mutex hw->dmac.lock
+ */
+static void cass_dmac_desc_set_id_clear(struct cass_dev *hw, int set_id)
+{
+	cass_dmac_desc_set_id_fill(hw, set_id, 0, DMAC_DESC_INDEX_UNSPECIFIED,
+				   NULL);
+}
+
+static int cass_dmac_desc_set_common_alloc(struct cass_dev *hw,
+					   u16 num_descs, u16 desc_idx,
+					   const char *name)
+{
+	int retval;
+	int i;
+	int set_id;
+	unsigned long index;
+	u16 idx = ((desc_idx == DMAC_DESC_INDEX_UNSPECIFIED) ? 0 : desc_idx);
+
+	if (num_descs == 0 || num_descs >= C_PI_CFG_DMAC_DESC_ENTRIES)
+		return -EINVAL;
+
+	mutex_lock(&hw->dmac.lock);
+
+	for (i = 0; i < DMAC_DESC_SET_COUNT; ++i)
+		if (hw->dmac.desc_sets[i].count == 0)
+			break;
+	if (i == DMAC_DESC_SET_COUNT) {
+		retval = -ENOSPC;
+		goto __cass_dmac_desc_set_common_alloc_0;
+	} else {
+		set_id = i;
+	}
+
+	index = bitmap_find_next_zero_area(hw->dmac.desc_map,
+					   C_PI_CFG_DMAC_DESC_ENTRIES,
+					   idx, num_descs, 0);
+
+	if (index >= C_PI_CFG_DMAC_DESC_ENTRIES) {
+		retval = -ENOSPC;
+		goto __cass_dmac_desc_set_common_alloc_0;
+	}
+
+	if (desc_idx != DMAC_DESC_INDEX_UNSPECIFIED && index != desc_idx) {
+		retval = -ENOSPC;
+		goto __cass_dmac_desc_set_common_alloc_0;
+	}
+
+	bitmap_set(hw->dmac.desc_map, index, num_descs);
+	cass_dmac_desc_set_id_fill(hw, set_id, num_descs, index, name);
+
+	retval = set_id;
+
+__cass_dmac_desc_set_common_alloc_0:
+	mutex_unlock(&hw->dmac.lock);
+	return retval;
+}
+
+/**
+ * cxi_dmac_desc_set_reserve() - reserve dmac descriptors
+ * @cdev: the device
+ * @num_descs: number of descriptors to reserve
+ * @desc_idx: starting NIC dmac descriptor
+ * @name: descriptive name to associate the dmac descriptor set
+ *        where the string must remain valid for the lifetime of the set
+ *
+ * reserve 'num_descs' contiguous from the NIC dmac descriptor pool
+ * starting with index 'desc_idx'
+ *
+ * Return: dmac descriptor set id on success, negative errno on failure
+ */
+int cxi_dmac_desc_set_reserve(struct cxi_dev *cdev, u16 num_descs,
+			      u16 desc_idx, const char *name)
+{
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	int retval;
+
+	if (!cdev->is_physfn)
+		return -EPERM;
+
+	cxidev_dbg(cdev, "hw=%p num_descs=%u desc_idx=%u\n", hw, num_descs,
+		   desc_idx);
+
+	if (desc_idx >= C_PI_CFG_DMAC_DESC_ENTRIES)
+		return -EINVAL;
+
+	retval = cass_dmac_desc_set_common_alloc(hw, num_descs, desc_idx,
+						 name);
+	return retval;
+}
+EXPORT_SYMBOL(cxi_dmac_desc_set_reserve);
+
+/**
+ * cxi_dmac_desc_set_alloc() - allocate dmac descriptors
+ * @cdev: the device
+ * @num_descs: number of descriptors to reserve
+ * @name: descriptive name to associate the dmac descriptor set
+ *        where the string must remain valid for the lifetime of the set
+ *
+ * allocate 'num_descs' contiguous from the NIC dmac descriptor free pool
+ *
+ * Return: dmac descriptor set id on success, negative errno on failure
+ */
+int cxi_dmac_desc_set_alloc(struct cxi_dev *cdev, u16 num_descs,
+			    const char *name)
+{
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	int retval;
+
+	if (!cdev->is_physfn)
+		return -EPERM;
+
+	cxidev_dbg(cdev, "hw=%p num_descs=%u\n", hw, num_descs);
+
+	retval = cass_dmac_desc_set_common_alloc(hw, num_descs,
+						 DMAC_DESC_INDEX_UNSPECIFIED,
+						 name);
+
+	return retval;
+}
+EXPORT_SYMBOL(cxi_dmac_desc_set_alloc);
+
+/**
+ * cxi_dmac_desc_set_free() - free dmac descriptors
+ * @cdev: the device
+ * @set_id: dmac descriptor set id
+ *
+ * free the descriptors associated with 'set_id' returning them
+ * back to the free pool
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+int cxi_dmac_desc_set_free(struct cxi_dev *cdev, int set_id)
+{
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	int retval = 0;
+	u16 count;
+	u16 index;
+
+	if (!cdev->is_physfn)
+		return -EPERM;
+
+	cxidev_dbg(cdev, "hw=%p set_id=%d\n", hw, set_id);
+
+	mutex_lock(&hw->dmac.lock);
+
+	retval = cass_dmac_desc_set_id_verify(hw, set_id);
+	if (retval != 0)
+		goto __cxi_dmac_desc_set_free_0;
+
+	count = hw->dmac.desc_sets[set_id].count;
+	index = hw->dmac.desc_sets[set_id].index;
+
+	dmac_desc_zero_n(hw, index, count);
+	bitmap_clear(hw->dmac.desc_map, index, count);
+
+	cass_dmac_desc_set_id_clear(hw, set_id);
+
+__cxi_dmac_desc_set_free_0:
+	mutex_unlock(&hw->dmac.lock);
+	return retval;
+}
+EXPORT_SYMBOL(cxi_dmac_desc_set_free);
+
+/**
+ * cxi_dmac_xfer() - start dma & wait/block for completion
+ * @cdev: the device
+ * @set_id: dmac descriptor set id
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+int cxi_dmac_xfer(struct cxi_dev *cdev, int set_id)
+{
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	volatile struct c_pi_dmac_cdesc *cpl_desc = hw->dmac.cpl_desc;
+	int retval;
+
+	if (!cdev->is_physfn)
+		return -EPERM;
+
+	cxidev_dbg(&hw->cdev, "hw=%p set_id=%d\n", hw, set_id);
+
+	mutex_lock(&hw->dmac.lock);
+
+	retval = cass_dmac_desc_set_id_verify(hw, set_id);
+	if (retval != 0)
+		goto __cxi_dmac_xfer_0;
+
+	if (hw->dmac.desc_sets[set_id].numused == 0) {
+		retval = -EINVAL;
+		goto __cxi_dmac_xfer_0;
+	}
+
+	/*
+	 * A transfer that timed out can still raise its interrupt later, so
+	 * drop any completion left over from one before starting this one.
+	 */
+	reinit_completion(&hw->dmac.irupt);
+
+	dmac_enable(hw, hw->dmac.desc_sets[set_id].index);
+
+	if (!wait_for_completion_timeout(&hw->dmac.irupt,
+					 msecs_to_jiffies(CASS_DMAC_XFER_TIMEOUT_MS)))
+		cxidev_err(cdev, "ERROR: DMAC completion timed out\n");
+
+	/*
+	 * Stop the engine before reading and clearing the completion
+	 * descriptor. In the error case, including the timeout, it may still
+	 * be running, and it must not write to the descriptor or the
+	 * destination buffer once this returns and the caller can free them.
+	 * The lock is held, so descriptor set and buffer teardown, which
+	 * takes it, cannot start before this.
+	 *
+	 * The next version of this becomes interrupt driven and the
+	 * further paranoia wants to disable irupts in dmac when done
+	 * to prevent 'erroneous spurious interrupts'.
+	 */
+	dmac_disable(hw);
+
+	/* Drain a handler for this transfer's interrupt before the next starts */
+	synchronize_irq(pci_irq_vector(hw->cdev.pdev, C_PI_DMAC_MSIX_INT));
+	reinit_completion(&hw->dmac.irupt);
+
+	if (cpl_desc->done == 0) {
+		cxidev_err(cdev,
+			   "ERROR: failed to get DMAC completion\n");
+		retval = -ETIME;
+	}
+	if (cpl_desc->status != C_PI_DMAC_CDESC_STATUS_AXI_RESP_OKAY) {
+		cxidev_err(cdev,
+			   "ERROR: DMAC_CDESC_STATUS=%x is 'not OK'\n",
+			   cpl_desc->status);
+		retval = -EBADE;
+	}
+
+	cxidev_dbg(&hw->cdev, "hw->dmac.cpl_desc=%016llx\n", *((u64 *)cpl_desc));
+
+	memset((void *)cpl_desc, 0, sizeof(*cpl_desc));
+
+__cxi_dmac_xfer_0:
+	mutex_unlock(&hw->dmac.lock);
+	return retval;
+}
+EXPORT_SYMBOL(cxi_dmac_xfer);
+
+static irqreturn_t cass_dmac_irupt_handler(int irq, void *p)
+{
+	struct completion *x = (struct completion *)p;
+
+	complete(x);
+	return IRQ_HANDLED;
+}
+
+/*
+ * Initialize DMAC (DMA Controller)
+ */
+int cass_dmac_init(struct cass_dev *hw)
+{
+	struct device *dma_dev = &hw->cdev.pdev->dev;
+	union c_pi_cfg_dmac_cpl_addr dmac_cpl = {};
+	int i;
+	int retval;
+	int vec;
+
+	dmac_disable(hw);
+	/*
+	 * Configure the DMAC to write a completion event to cpl_desc
+	 */
+	hw->dmac.cpl_desc = dma_alloc_coherent(dma_dev, sizeof(*hw->dmac.cpl_desc),
+					       &hw->dmac.cpl_desc_dma_addr,
+					       GFP_KERNEL);
+	if (!hw->dmac.cpl_desc)
+		return -ENOMEM;
+	memset(hw->dmac.cpl_desc, 0, sizeof(*hw->dmac.cpl_desc));
+	dmac_cpl.address = hw->dmac.cpl_desc_dma_addr >> 3;
+	cass_write(hw, C_PI_CFG_DMAC_CPL_ADDR, &dmac_cpl, sizeof(dmac_cpl));
+
+	dmac_desc_zero_all(hw);	/* the zero will cass_flush_pci() */
+
+	mutex_init(&hw->dmac.lock);
+
+	init_completion(&hw->dmac.irupt);
+
+	hw->dmac.desc_sets = kcalloc(DMAC_DESC_SET_COUNT,
+				     sizeof(*hw->dmac.desc_sets), GFP_KERNEL);
+
+	if (hw->dmac.desc_sets == NULL) {
+		retval = -ENOMEM;
+		goto __cass_dmac_init_0;
+	}
+
+	for (i = 0; i < DMAC_DESC_SET_COUNT; ++i)
+		cass_dmac_desc_set_id_clear(hw, i);
+
+	hw->dmac.desc_map = bitmap_zalloc(C_PI_CFG_DMAC_DESC_ENTRIES,
+					  GFP_KERNEL);
+	if (hw->dmac.desc_map == NULL) {
+		retval = -ENOMEM;
+		goto __cass_dmac_init_1;
+	}
+	scnprintf(hw->dmac.irupt_name, sizeof(hw->dmac.irupt_name),
+		  "%s_irupt_dmac", hw->cdev.name);
+	vec = pci_irq_vector(hw->cdev.pdev, C_PI_DMAC_MSIX_INT);
+	retval = request_irq(vec, cass_dmac_irupt_handler, 0,
+			     hw->dmac.irupt_name, &hw->dmac.irupt);
+	if (retval != 0)
+		goto __cass_dmac_init_2;
+
+	return 0;
+
+__cass_dmac_init_2:
+	bitmap_free(hw->dmac.desc_map);
+
+__cass_dmac_init_1:
+	kfree(hw->dmac.desc_sets);
+
+__cass_dmac_init_0:
+	mutex_destroy(&hw->dmac.lock);
+	dmac_cpl.address = 0;
+	cass_write(hw, C_PI_CFG_DMAC_CPL_ADDR, &dmac_cpl, sizeof(dmac_cpl));
+	dma_free_coherent(dma_dev, sizeof(*hw->dmac.cpl_desc),
+			  hw->dmac.cpl_desc, hw->dmac.cpl_desc_dma_addr);
+	hw->dmac.cpl_desc = NULL;
+
+	return retval;
+}
+
+/*
+ * Finish/finalize DMAC (DMA Controller)
+ */
+void cass_dmac_fini(struct cass_dev *hw)
+{
+	struct device *dma_dev = &hw->cdev.pdev->dev;
+	int vec;
+
+	dmac_disable(hw);
+	vec = pci_irq_vector(hw->cdev.pdev, C_PI_DMAC_MSIX_INT);
+	free_irq(vec, &hw->dmac.irupt);
+	cass_clear(hw, C_PI_CFG_DMAC_CPL_ADDR, C_PI_CFG_DMAC_CPL_ADDR_SIZE);
+	dmac_desc_zero_all(hw);
+	dma_free_coherent(dma_dev, sizeof(*hw->dmac.cpl_desc),
+			  hw->dmac.cpl_desc, hw->dmac.cpl_desc_dma_addr);
+	hw->dmac.cpl_desc = NULL;
+	bitmap_free(hw->dmac.desc_map);
+	kfree(hw->dmac.desc_sets);
+	mutex_destroy(&hw->dmac.lock);
+}
diff --git a/drivers/net/ethernet/hpe/ss1/cass_eq.c b/drivers/net/ethernet/hpe/ss1/cass_eq.c
new file mode 100644
index 000000000000..2d65df985b05
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_eq.c
@@ -0,0 +1,1518 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2018, 2024-2026 Hewlett Packard Enterprise Development LP */
+
+/* Portals-like interface for Cassini */
+
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/hpe/cxi/cxi.h>
+#include <linux/iopoll.h>
+
+#include "cass_core.h"
+#include "cxi_internal.h"
+#include "cass_ss1_debugfs.h"
+#include "cxi_vf_cmd.h"
+
+static unsigned int ee_timestamp_period_ms = 1000;
+module_param(ee_timestamp_period_ms, uint, 0644);
+MODULE_PARM_DESC(ee_timestamp_period_ms,
+		 "Period between EE timestamp events in milliseconds.");
+
+#define LT_LIMIT_MAX (BIT(9) - 1)
+#define GRAN_DEF 50
+
+static const union c_ee_cfg_latency_monitor lat_monitor_def = {
+	/* The EQ latency_tolerance configuration limit. An EQ's
+	 * latency_tolerance * EE granularity is the ECB expiration timeout.
+	 * Limit is 9 bits wide. Allow any configuration.
+	 */
+	.lt_limit = LT_LIMIT_MAX,
+
+	/* Latency step granularity. An EQ's latency_tolerance * EE granularity
+	 * is the ECB expiration timeout. Granularity is effectively the step
+	 * size of latency_tolerance in ns. 16 bits wide, ~65us max step size.
+	 *
+	 * A default of 50 allows a range of ~0-25us (50ns*511).
+	 */
+	.granularity = GRAN_DEF,
+
+	/* When a configured portion of ECBs are in use, the latency monitor
+	 * transitions to using a separate granularity/latency_tolerance
+	 * configuration which can accelerate ECB expiration.
+	 *
+	 * There are two stages, A and B. Stage transitions are defined by a
+	 * threshold and hysteresis value. When ECB usage hits the threshold,
+	 * the latency monitor enters the corresponding stage. When ECB usage
+	 * drops below the hysteresis value, the stage is exited.
+	 */
+	.thresh_a       = 128,
+	.hysteresis_a   = 100,
+	.granularity_a  = GRAN_DEF / 2, /* 2x speedup in stage A */
+	.lt_limit_a     = LT_LIMIT_MAX,
+	.lt_reduction_a = 0,
+
+	.thresh_b       = 196,
+	.hysteresis_b   = 150,
+	.granularity_b  = GRAN_DEF / 10,       /* 10x speedup in stage B */
+	.lt_limit_b     = 200 / (GRAN_DEF / 10), /* Hard limit of 200 ns */
+	.lt_reduction_b = 0,
+};
+
+#define LATENCY_TOLERANCE_DEF_NS (500)
+
+/* The max number of event entries in an event queue is calculated by:
+ * The number of 4kB pages the C_EE_CFG_EQ_DESCRIPTOR BUFFER_*_SIZE value
+ * can address which is 20-bits worth of addressing or 4GB (2^32) of space.
+ */
+#define MAX_EQ_LEN (1ull << 32)
+
+/* Convert EQ queue length, in bytes, into queue size in ECB units. */
+static size_t get_eq_queue_size(size_t queue_len)
+{
+	return queue_len / C_EE_CFG_ECB_SIZE;
+}
+
+void cass_ee_init(struct cass_dev *hw)
+{
+	union c_ee_cfg_timestamp_freq ts_freq;
+	unsigned int clk_freq_khz;
+
+	if (cass_version(hw, CASSINI_1))
+		clk_freq_khz = C1_CLK_FREQ_HZ / 1000;
+	else
+		clk_freq_khz = C2_CLK_FREQ_HZ / 1000;
+
+	ts_freq.clk_divider = ee_timestamp_period_ms * clk_freq_khz / C_NUM_EQS;
+
+	cass_write(hw, C_EE_CFG_TIMESTAMP_FREQ, &ts_freq, sizeof(ts_freq));
+
+	cass_write(hw, C_EE_CFG_LATENCY_MONITOR, &lat_monitor_def,
+		   sizeof(lat_monitor_def));
+}
+
+/* Event interrupt handler for EQs */
+static int eq_event_nb(struct notifier_block *nb, unsigned long action,
+		       void *data)
+{
+	struct cxi_eq_priv *eq = container_of(nb, struct cxi_eq_priv,
+					      event_nb);
+
+	eq->event_cb(eq->event_cb_data);
+
+	return NOTIFY_OK;
+}
+
+/* Status interrupt handler for EQs */
+static int eq_status_nb(struct notifier_block *nb, unsigned long action,
+			void *data)
+{
+	struct cxi_eq_priv *eq = container_of(nb, struct cxi_eq_priv,
+					      status_nb);
+
+	eq->status_cb(eq->status_cb_data);
+
+	return NOTIFY_OK;
+}
+
+/* Return an EQ latency_tolerance value representing the requested nanosecond
+ * delay according to the currently configured ECB latency monitor granularity.
+ * Reading the currently configured value supports the expected behavior while
+ * using OOB interfaces to configure the latency monitor.
+ */
+static unsigned int eq_compute_lt(struct cass_dev *hw, unsigned int ns)
+{
+	union c_ee_cfg_latency_monitor lat_mon;
+	unsigned int step_size;
+	unsigned int lt;
+
+	cass_read(hw, C_EE_CFG_LATENCY_MONITOR, &lat_mon, sizeof(lat_mon));
+	if (cass_version(hw, CASSINI_1))
+		step_size = lat_mon.granularity / (C1_CLK_FREQ_HZ / NSEC_PER_SEC);
+	else
+		step_size = lat_mon.granularity / (C2_CLK_FREQ_HZ / NSEC_PER_SEC);
+	lt = ns / step_size;
+
+	if (lt > LT_LIMIT_MAX)
+		lt = LT_LIMIT_MAX;
+
+	return lt;
+}
+
+/* Toggle EQ timestamp events. Use eq_shadow_lock to serialize calls. */
+static void eq_timestamp_toggle(struct cass_dev *hw, int eq_n, bool enable)
+{
+	union c_ee_cfg_periodic_tstamp_table ts_tbl;
+	int ts_tbl_idx = eq_n / 64;
+	int ts_tbl_bit = eq_n % 64;
+	u64 csr_off = C_EE_CFG_PERIODIC_TSTAMP_TABLE(ts_tbl_idx);
+
+	cass_read(hw, csr_off, &ts_tbl.qw, 8);
+	if (enable)
+		ts_tbl.n63_n0_enable_periodic_tstamp |= BIT(ts_tbl_bit);
+	else
+		ts_tbl.n63_n0_enable_periodic_tstamp &= ~BIT(ts_tbl_bit);
+	cass_write(hw, csr_off, &ts_tbl.qw, 8);
+}
+
+/* Configure an EQ descriptor's status write-back settings given a queue size.
+ * This must be done each time the EQ size is changed. eq_status_config() does
+ * not write the new settings to hardware.
+ */
+static void eq_status_config(struct cxi_eq_priv *eq, size_t queue_size)
+{
+	unsigned int base_slots;
+	unsigned int delta_slots;
+	int thld_shift;
+
+	if (eq->attr.status_thresh_count) {
+		/* Don't count EQ status slot in queue size. */
+		queue_size -= 1;
+		/* Configure status update thresholds */
+		base_slots = queue_size * (100 - eq->attr.status_thresh_base) / 100;
+		delta_slots = queue_size * eq->attr.status_thresh_delta / 100;
+
+		/* Set threshold shift to preserve the 6 MSBs of the larger of
+		 * the base and delta values.
+		 */
+		thld_shift = (base_slots > delta_slots) ?
+				fls(base_slots) : fls(delta_slots);
+		thld_shift = thld_shift > 6 ? thld_shift - 6 : 0;
+
+		eq->cfg.eq_sts_num_thld = eq->attr.status_thresh_count - 1;
+		eq->cfg.eq_sts_thld_base = base_slots >> thld_shift;
+		eq->cfg.eq_sts_thld_offst = delta_slots >> thld_shift;
+		eq->cfg.eq_sts_thld_shift = thld_shift;
+	} else {
+		/* Max shift value disables threshold updates. */
+		eq->cfg.eq_sts_thld_shift = 0x1f;
+	}
+}
+
+#define EQ_MAX_RESERVED_FC (BIT(14) - 1)
+
+static int is_valid_eq_reserved_fc(struct cxi_eq_priv *eq, int fc_value)
+{
+	int new_fc_value = (int)eq->cfg.reserved_fc + fc_value;
+	int max_fc_value = eq->queue_size - 1;
+
+	if (abs(fc_value) > EQ_MAX_RESERVED_FC ||
+	    new_fc_value > EQ_MAX_RESERVED_FC || new_fc_value < 0)
+		return -EINVAL;
+
+	if (new_fc_value > max_fc_value)
+		return -ENOSPC;
+
+	return 0;
+}
+
+/**
+ * cxi_eq_adjust_reserved_fc_vf() - Adjust EQ reserved FC value for VF.
+ * @eq: EQ
+ * @value: Amount to adjust reserved FC value by. Can be negative or positive.
+ *
+ * Return: On success, value greater than or equal to zero representing current
+ * EQ reserved FC value. Else, -EINVAL if value is invalid or -ENOSPC if a valid
+ * value is provided but could not be applied.
+ */
+static int cxi_eq_adjust_reserved_fc_vf(struct cxi_eq *eq, int value)
+{
+	struct cxi_dev *cdev = container_of(eq, struct cxi_eq_priv, eq)->lni_priv->dev;
+	struct cxi_eq_adjust_reserved_fc_resp resp;
+	size_t resp_len = sizeof(resp);
+	const struct cxi_eq_adjust_reserved_fc_cmd cmd = {
+		.op = CXI_OP_EQ_ADJUST_RESERVED_FC,
+		.eq_hndl = eq->eqn,
+		.value = value,
+		.resp = &resp,
+	};
+	int rc;
+
+	rc = cxi_send_msg_to_pf(cdev, &cmd, sizeof(cmd), &resp, &resp_len);
+	if (rc)
+		return rc;
+
+	return resp.reserved_fc;
+}
+
+/**
+ * cxi_eq_adjust_reserved_fc() - Adjust EQ reserved FC value.
+ * @eq: EQ
+ * @value: Amount to adjust reserved FC value by. Can be negative or positive.
+ *
+ * Return: On success, value greater than or equal to zero representing current
+ * EQ reserved FC value. Else, -EINVAL if value is invalid or -ENOSPC if a valid
+ * value is provided but could not be applied.
+ */
+int cxi_eq_adjust_reserved_fc(struct cxi_eq *eq, int value)
+{
+	struct cxi_eq_priv *eq_priv;
+	struct cxi_dev *cdev;
+	struct cass_dev *hw;
+	int rc;
+
+	if (!eq)
+		return -EINVAL;
+
+	eq_priv = container_of(eq, struct cxi_eq_priv, eq);
+	cdev = eq_priv->lni_priv->dev;
+
+	if (!cdev->is_physfn)
+		return cxi_eq_adjust_reserved_fc_vf(eq, value);
+
+	hw = container_of(cdev, struct cass_dev, cdev);
+
+	/* Use EQ shadow_lock to serialize EQ access. */
+	spin_lock(&hw->eq_shadow_lock);
+
+	rc = is_valid_eq_reserved_fc(eq_priv, value);
+	if (rc)
+		goto unlock_out;
+
+	eq_priv->cfg.reserved_fc += value;
+
+	cass_shadow_write(hw, C_EE_BASE, C_EE_CFG_EQ_DESCRIPTOR(eq->eqn),
+			  &eq_priv->cfg, sizeof(eq_priv->cfg));
+
+	rc = eq_priv->cfg.reserved_fc;
+
+unlock_out:
+	spin_unlock(&hw->eq_shadow_lock);
+
+	return rc;
+}
+EXPORT_SYMBOL(cxi_eq_adjust_reserved_fc);
+
+/**
+ * put_pages_contig() - Un-pin a sequence of physical pages.
+ *
+ * @hw: The cassini device
+ * @desc: EQ buffer descriptor
+ */
+static void put_pages_contig(struct cass_dev *hw, struct eq_buf_desc *desc)
+{
+	size_t npg = desc->events_len >> PAGE_SHIFT;
+
+	dma_unmap_page(&hw->cdev.pdev->dev, desc->dma_addr, desc->events_len,
+		       DMA_FROM_DEVICE);
+
+	unpin_user_pages_dirty_lock(desc->pages, npg, true);
+	kfree(desc->pages);
+}
+
+static int cxi_eq_resize_vf(struct cxi_eq *evtq, void *queue, size_t queue_len,
+			    struct cxi_md *queue_md)
+{
+	struct cxi_eq_priv *eq = container_of(evtq, struct cxi_eq_priv, eq);
+	struct cxi_dev *cdev = eq->lni_priv->dev;
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	struct cxi_eq_resize_cmd_vf cmd = {
+		.base.op = CXI_OP_EQ_RESIZE,
+		.base.eq_hndl = eq->eq.eqn,
+		.base.queue_len = queue_len,
+		.base.queue_md = queue_md ? queue_md->id : CXI_MD_NONE,
+	};
+	bool passthrough = !!(eq->attr.flags & CXI_EQ_PASSTHROUGH);
+	bool is_user = eq->attr.flags & CXI_EQ_USER;
+	int rc = 0;
+
+	if (!queue_len || queue_len > MAX_EQ_LEN || !queue)
+		return -EINVAL;
+
+	/* Queue buffer address and length must be page aligned. */
+	if (!IS_ALIGNED((uintptr_t)queue, PAGE_SIZE))
+		return -EINVAL;
+
+	if (!IS_ALIGNED(queue_len, PAGE_SIZE))
+		return -EINVAL;
+
+	mutex_lock(&eq->resize_mutex);
+
+	eq->resize.md = queue_md;
+	eq->resize.events = queue;
+	eq->resize.events_len = queue_len;
+
+	if (passthrough) {
+		if (is_user) {
+			rc = get_dma_addr_if_contig(hw, queue, queue_len,
+						    DMA_FROM_DEVICE,
+						    &eq->resize.pages,
+						    &eq->resize.dma_addr);
+		} else {
+			eq->resize.dma_addr = dma_map_single(&hw->cdev.pdev->dev,
+							     eq->resize.events,
+							     eq->resize.events_len,
+							     DMA_FROM_DEVICE);
+			if (dma_mapping_error(&hw->cdev.pdev->dev, eq->resize.dma_addr))
+				rc = -ENOMEM;
+		}
+
+		if (rc)
+			goto unlock;
+	} else {
+		eq->resize.dma_addr = queue_md->iova;
+	}
+
+	cmd.dma_addr = eq->resize.dma_addr;
+
+	rc = cxi_send_msg_to_pf(cdev, &cmd, sizeof(cmd), NULL, NULL);
+	if (rc)
+		goto unmap_dma;
+
+	eq->resized = true;
+	mutex_unlock(&eq->resize_mutex);
+
+	return 0;
+unmap_dma:
+	if (passthrough) {
+		if (is_user)
+			put_pages_contig(hw, &eq->resize);
+		else
+			dma_unmap_single(&hw->cdev.pdev->dev, eq->resize.dma_addr,
+					 eq->resize.events_len, DMA_FROM_DEVICE);
+	}
+unlock:
+	mutex_unlock(&eq->resize_mutex);
+	return rc;
+}
+
+int cxi_eq_resize_internal(struct cxi_eq *evtq, void *queue,
+			   size_t queue_len, struct cxi_md *queue_md,
+			   dma_addr_t dma_addr)
+{
+	struct cxi_eq_priv *eq = container_of(evtq, struct cxi_eq_priv, eq);
+	struct cxi_lni_priv *lni_priv = eq->lni_priv;
+	struct cxi_dev *cdev = lni_priv->dev;
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	struct cxi_md_priv *md_priv;
+	int rc = 0;
+	int passthrough = !!(eq->attr.flags & CXI_EQ_PASSTHROUGH);
+	bool is_vf = lni_priv->is_vf;
+
+	if (!cdev->is_physfn)
+		return -EOPNOTSUPP;
+
+	if (!queue_len || queue_len > MAX_EQ_LEN)
+		return -EINVAL;
+
+	if ((!is_vf && !queue) || (is_vf && !dma_addr))
+		return -EINVAL;
+
+	/* Queue buffer address and length must be page aligned. */
+	if ((!is_vf && !IS_ALIGNED((uintptr_t)queue, PAGE_SIZE)) ||
+	    (is_vf && !IS_ALIGNED(dma_addr, PAGE_SIZE)))
+		return -EINVAL;
+
+	if (!IS_ALIGNED(queue_len, PAGE_SIZE))
+		return -EINVAL;
+
+	if (!is_vf && !passthrough) {
+		if (!queue_md || !CXI_MD_CONTAINS(queue_md, queue, queue_len)) {
+			cxidev_err(cdev, "MD does not contain queue buffer\n");
+			return -EINVAL;
+		}
+
+		if (eq->active.md->lac != queue_md->lac) {
+			cxidev_err(cdev, "New buffer AC does not match EQ\n");
+			return -EINVAL;
+		}
+	}
+
+	mutex_lock(&eq->resize_mutex);
+
+	if (eq->resized) {
+		rc = -EINVAL;
+		goto unlock;
+	}
+
+	eq->resize.md = queue_md;
+	eq->resize.events = queue;
+	eq->resize.events_len = queue_len;
+
+	if (!is_vf) {
+		if (passthrough) {
+			if (eq->attr.flags & CXI_EQ_USER) {
+				rc = get_dma_addr_if_contig(hw, queue, queue_len,
+							    DMA_FROM_DEVICE,
+							    &eq->resize.pages,
+							    &eq->resize.dma_addr);
+			} else {
+				eq->resize.dma_addr = dma_map_single(&hw->cdev.pdev->dev,
+								     queue, queue_len,
+								     DMA_FROM_DEVICE);
+				if (dma_mapping_error(&hw->cdev.pdev->dev, eq->resize.dma_addr))
+					rc = -ENOMEM;
+				else
+					rc = 0;
+			}
+
+			if (rc)
+				goto unlock;
+		} else {
+			eq->resize.dma_addr = CXI_VA_TO_IOVA(queue_md, queue);
+			md_priv = container_of(eq->resize.md, struct cxi_md_priv, md);
+			refcount_inc(&md_priv->refcount);
+		}
+	} else if (!passthrough) {
+		md_priv = container_of(queue_md, struct cxi_md_priv, md);
+		refcount_inc(&md_priv->refcount);
+		eq->resize.dma_addr = dma_addr;
+	}
+
+	if (eq->cfg.use_buffer_b) {
+		eq->cfg.buffer_a_size = queue_len >> C_ADDR_SHIFT;
+		eq->cfg.buffer_a_en   = 1;
+		eq->cfg.buffer_a_addr = eq->resize.dma_addr >> C_ADDR_SHIFT;
+		eq->cfg.use_buffer_b = 0;
+	} else {
+		eq->cfg.buffer_b_size = queue_len >> C_ADDR_SHIFT;
+		eq->cfg.buffer_b_en   = 1;
+		eq->cfg.buffer_b_addr = eq->resize.dma_addr >> C_ADDR_SHIFT;
+		eq->cfg.use_buffer_b = 1;
+	}
+
+	/* Reconfigure EQ status settings using new queue length. */
+	eq_status_config(eq, queue_len / C_EE_CFG_ECB_SIZE);
+
+	/* Re-write the EQ descriptor with the new buffer description. Read
+	 * back the descriptor to ensure it has been updated before returning
+	 * to the client in order to guarantee that a subsequent client write
+	 * to EQ_SW_STATE will force the resize to be processed by the device.
+	 */
+	spin_lock(&hw->eq_shadow_lock);
+	cass_shadow_write(hw, C_EE_BASE, C_EE_CFG_EQ_DESCRIPTOR(eq->eq.eqn),
+			  &eq->cfg, sizeof(eq->cfg));
+	cass_shadow_read(hw, C_EE_BASE, C_EE_CFG_EQ_DESCRIPTOR(eq->eq.eqn),
+			 &eq->cfg,
+			 sizeof(eq->cfg));
+	spin_unlock(&hw->eq_shadow_lock);
+
+	eq->resized = true;
+
+	mutex_unlock(&eq->resize_mutex);
+
+	return 0;
+
+unlock:
+	mutex_unlock(&eq->resize_mutex);
+
+	return rc;
+}
+EXPORT_SYMBOL(cxi_eq_resize_internal);
+
+/* cxi_eq_resize() - Resize a CXI Event Queue buffer.
+ *
+ * Resizing an Event Queue is a multi-step process. The first step is to call
+ * cxi_eq_resize() to pass a new event buffer to the device. After this call,
+ * evtq will continue to reference the old EQ buffer. The device may write a
+ * small number of events to the old EQ buffer followed by a special
+ * C_EVENT_EQ_SWITCH event to indicate that hardware has transitioned to
+ * writing to the new EQ buffer. When this event is detected, software must
+ * call cxi_eq_resize_complete() in order to start reading events from the new
+ * EQ buffer.
+ *
+ * The new event queue buffer must use the same translation mechanism as was
+ * used to allocate the EQ. If translation is used, the Addressing Context (AC)
+ * used by the new MD must match the MD used to allocate the EQ.
+ *
+ * The new event queue buffer must be cleared before calling cxi_eq_resize().
+ *
+ * @evtq: The Event Queue to resize.
+ * @queue: The new event queue buffer. Must be page aligned.
+ * @queue_len: The new event queue buffer length in bytes. Must be page aligned.
+ * @queue_md: The new event queue memory descriptor.
+ *
+ * Return: On success, 0 is returned and a resized buffer has been
+ * submitted to the device.
+ */
+int cxi_eq_resize(struct cxi_eq *evtq, void *queue, size_t queue_len,
+		  struct cxi_md *queue_md)
+{
+	struct cxi_eq_priv *eq = container_of(evtq, struct cxi_eq_priv, eq);
+	struct cxi_lni_priv *lni_priv = eq->lni_priv;
+	struct cxi_dev *cdev = lni_priv->dev;
+
+	if (cdev->is_physfn)
+		return cxi_eq_resize_internal(evtq, queue, queue_len, queue_md, 0);
+	else
+		return cxi_eq_resize_vf(evtq, queue, queue_len, queue_md);
+}
+EXPORT_SYMBOL(cxi_eq_resize);
+
+static int cxi_eq_resize_complete_vf(struct cxi_eq *evtq)
+{
+	struct cxi_eq_priv *eq = container_of(evtq, struct cxi_eq_priv, eq);
+	struct cxi_dev *cdev = eq->lni_priv->dev;
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	const struct cxi_eq_resize_complete_cmd cmd = {
+		.op = CXI_OP_EQ_RESIZE_COMPLETE,
+		.eq_hndl = evtq->eqn,
+	};
+	int rc;
+
+	mutex_lock(&eq->resize_mutex);
+
+	rc = cxi_send_msg_to_pf(cdev, &cmd, sizeof(cmd), NULL, NULL);
+	if (rc)
+		goto unlock;
+
+	if (eq->attr.flags & CXI_EQ_PASSTHROUGH) {
+		if (eq->attr.flags & CXI_EQ_USER)
+			put_pages_contig(hw, &eq->active);
+		else
+			dma_unmap_single(&hw->cdev.pdev->dev, eq->active.dma_addr,
+					 eq->active.events_len, DMA_FROM_DEVICE);
+	}
+
+	eq->active = eq->resize;
+	eq->resized = false;
+	cxi_eq_init(evtq, eq->active.events, eq->active.events_len, eq->eq.eqn,
+		    (__force u64 *)(hw->regs + C_MEMORG_EE +
+				    eq->eq.eqn * C_EE_SW_STATE_PAGE_SIZE));
+	evtq->sw_state.reading_buffer_b = !evtq->sw_state.reading_buffer_b;
+
+unlock:
+	mutex_unlock(&eq->resize_mutex);
+	return rc;
+}
+
+/**
+ * cxi_eq_resize_complete() - Complete resizing a CXI Event Queue buffer.
+ *
+ * cxi_eq_resize_complete() must be called after an EQ has been resized
+ * using cxi_eq_resize() and a C_EVENT_EQ_SWITCH event was delivered. See
+ * the documentation for cxi_eq_resize().
+ *
+ * @evtq: The Event Queue to being resized.
+ *
+ * Return: On success, 0 is returned and evtq references the new, resized
+ * buffer.
+ */
+int cxi_eq_resize_complete(struct cxi_eq *evtq)
+{
+	struct cxi_eq_priv *eq = container_of(evtq, struct cxi_eq_priv, eq);
+	struct cxi_lni_priv *lni_priv = eq->lni_priv;
+	struct cxi_dev *cdev = lni_priv->dev;
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	struct cxi_md_priv *md_priv;
+	bool is_vf = lni_priv->is_vf;
+
+	if (!cdev->is_physfn)
+		return cxi_eq_resize_complete_vf(evtq);
+
+	mutex_lock(&eq->resize_mutex);
+
+	if (!eq->resized) {
+		mutex_unlock(&eq->resize_mutex);
+		return -EINVAL;
+	}
+
+	if (!is_vf) {
+		if (eq->attr.flags & CXI_EQ_PASSTHROUGH) {
+			if (eq->attr.flags & CXI_EQ_USER)
+				put_pages_contig(hw, &eq->active);
+			else
+				dma_unmap_single(&hw->cdev.pdev->dev, eq->active.dma_addr,
+						 eq->active.events_len, DMA_FROM_DEVICE);
+		} else {
+			md_priv = container_of(eq->active.md, struct cxi_md_priv, md);
+			refcount_dec(&md_priv->refcount);
+		}
+	} else if (!(eq->attr.flags & CXI_EQ_PASSTHROUGH)) {
+		md_priv = container_of(eq->active.md, struct cxi_md_priv, md);
+		refcount_dec(&md_priv->refcount);
+	}
+
+	eq->active = eq->resize;
+
+	eq->attr.queue = eq->active.events;
+	eq->attr.queue_len = eq->active.events_len;
+
+	eq->queue_size = get_eq_queue_size(eq->active.events_len);
+
+	/* Re-initialize the user evtq to reference new buffer */
+	cxi_eq_init(evtq, eq->active.events, eq->active.events_len, eq->eq.eqn,
+		    (__force u64 *)(hw->regs + C_MEMORG_EE +
+				    eq->eq.eqn * C_EE_SW_STATE_PAGE_SIZE));
+	evtq->sw_state.reading_buffer_b = !evtq->sw_state.reading_buffer_b;
+
+	eq->resized = false;
+
+	mutex_unlock(&eq->resize_mutex);
+
+	return 0;
+}
+EXPORT_SYMBOL(cxi_eq_resize_complete);
+
+/* Register the PCT EQ in all 3 places */
+static void set_pct_eq(struct cass_dev *hw, unsigned int eq_n)
+{
+	union c_pct_cfg_eq_retry_q_handle rh_q = {
+		.eq_handle = eq_n,
+	};
+
+	cass_write(hw, C_PCT_CFG_EQ_RETRY_Q_HANDLE, &rh_q, sizeof(rh_q));
+	cass_write(hw, C_PCT_CFG_EQ_TGT_Q_HANDLE, &rh_q, sizeof(rh_q));
+	cass_write(hw, C_PCT_CFG_EQ_CONN_LD_Q_HANDLE, &rh_q, sizeof(rh_q));
+}
+
+/* Return an available event queue with an ID */
+static struct cxi_eq_priv *pf_get_eq_id(struct cxi_lni_priv *lni_priv)
+{
+	struct cxi_dev *cdev = lni_priv->dev;
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	struct cxi_eq_priv *eq;
+	int rc;
+
+	/* Try to reuse an existing EQ that was put on the cleanup list */
+	spin_lock(&lni_priv->res_lock);
+
+	eq = list_first_entry_or_null(&lni_priv->eq_cleanups_list,
+				      struct cxi_eq_priv, list);
+	if (eq)
+		list_del(&eq->list);
+
+	spin_unlock(&lni_priv->res_lock);
+
+	if (eq) {
+		memset(&eq->cfg, 0, sizeof(eq->cfg));
+		eq->reused = true;
+		return eq;
+	}
+
+	/* Check the associated service to see if this EQ can be
+	 * allocated.
+	 */
+	rc = cxi_rgroup_alloc_resource(lni_priv->rgroup, CXI_RESOURCE_EQ);
+	if (rc)
+		return ERR_PTR(rc);
+
+	eq = kzalloc(sizeof(*eq), GFP_KERNEL);
+	if (eq == NULL) {
+		rc = -ENOMEM;
+		goto dec_rsrc_use;
+	}
+
+	/* Get event queue ID */
+	rc = ida_alloc_range(&hw->eq_index_table, 1, C_NUM_EQS - 1, GFP_KERNEL);
+	if (rc < 0) {
+		cxidev_err(cdev, "ida_alloc_range failed %d\n", rc);
+		goto eq_free;
+	}
+
+	eq->eq.eqn = rc;
+
+	return eq;
+
+eq_free:
+	kfree(eq);
+
+dec_rsrc_use:
+	cxi_rgroup_free_resource(lni_priv->rgroup, CXI_RESOURCE_EQ);
+
+	return ERR_PTR(rc);
+}
+
+/* Free an EQ allocated with pf_get_eq_id */
+static void pf_put_eq_id(struct cxi_eq_priv *eq)
+{
+	struct cxi_lni_priv *lni_priv = eq->lni_priv;
+	struct cxi_dev *cdev = lni_priv->dev;
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+
+	if (eq->reused) {
+		spin_lock(&lni_priv->res_lock);
+		list_add_tail(&eq->list, &lni_priv->eq_cleanups_list);
+		spin_unlock(&lni_priv->res_lock);
+	} else {
+		ida_free(&hw->eq_index_table, eq->eq.eqn);
+		cxi_rgroup_free_resource(lni_priv->rgroup, CXI_RESOURCE_EQ);
+		kfree(eq);
+	}
+}
+
+/* Prepare and write the EQ config to the adapter */
+static int pf_write_eq_config(struct cxi_eq_priv *eq, bool is_vf,
+			      int vf_event_irq_idx, int vf_status_irq_idx)
+{
+	struct cxi_dev *cdev = eq->lni_priv->dev;
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	union c_ee_cfg_init_eq_hw_state init_eq_hw_state;
+	unsigned int eq_n = eq->eq.eqn;
+	const struct cxi_eq_attr *attr = &eq->attr;
+	void __iomem *csr;
+	int rc;
+
+	if (is_vf && vf_event_irq_idx >= 0) {
+		eq->cfg.event_int_idx = vf_event_irq_idx;
+		eq->cfg.event_int_en = 1;
+	} else if (!is_vf && eq->event_cb) {
+		eq->cfg.event_int_idx = eq->event_msi_irq->idx;
+		eq->cfg.event_int_en = 1;
+	}
+
+	if (is_vf && vf_status_irq_idx >= 0) {
+		eq->cfg.eq_sts_int_idx = vf_status_irq_idx;
+		eq->cfg.eq_sts_int_en = 1;
+	} else if (!is_vf && eq->status_cb) {
+		eq->cfg.eq_sts_int_idx = eq->status_msi_irq->idx;
+		eq->cfg.eq_sts_int_en = 1;
+	}
+
+	if (eq->attr.flags & CXI_EQ_PASSTHROUGH) {
+		eq->cfg.acid = eq->lni_priv->phys_ac;
+		eq->cfg.buffer_a_addr = eq->active.dma_addr >> C_ADDR_SHIFT;
+	} else {
+		struct cxi_md_priv *md_priv =
+			container_of(eq->active.md, struct cxi_md_priv, md);
+
+		eq->cfg.acid = md_priv->cac->ac.acid;
+		eq->cfg.buffer_a_addr =
+			CXI_VA_TO_IOVA(eq->active.md, eq->active.events) >>
+			C_ADDR_SHIFT;
+	}
+
+	eq->cfg.buffer_a_size = eq->active.events_len >> C_ADDR_SHIFT;
+	eq->cfg.buffer_a_en = 1;
+	eq->cfg.eq_enable = 1;
+
+	rc = is_valid_eq_reserved_fc(eq, eq->attr.reserved_slots);
+	if (rc)
+		return rc;
+	eq->cfg.reserved_fc = eq->attr.reserved_slots;
+
+	eq_status_config(eq, eq->queue_size);
+
+	eq->cfg.eq_sts_dropped_en =
+		eq->attr.flags & CXI_EQ_DROP_STATUS_DISABLE ? 0 : 1;
+
+	if (eq->attr.flags & CXI_EQ_EC_DISABLE) {
+		/* Disable all event combining. */
+		eq->cfg.latency_tolerance = 0;
+	} else if (attr->ec_delay) {
+		/* Set custom ECB expiration delay. */
+		eq->cfg.latency_tolerance = eq_compute_lt(hw, attr->ec_delay);
+	} else {
+		/* Use default ECB expiration configuration. */
+		eq->cfg.latency_tolerance =
+			eq_compute_lt(hw, LATENCY_TOLERANCE_DEF_NS);
+	}
+
+	mutex_lock(&hw->init_eq_hw_state);
+
+	/* Wait for C_EE_CFG_INIT_EQ_HW_STATE to be ready for use */
+	csr = cass_csr(hw, C_EE_CFG_INIT_EQ_HW_STATE);
+	rc = readq_poll_timeout(csr, init_eq_hw_state.qw,
+				init_eq_hw_state.pending == 0, 1, 1000);
+	if (rc) {
+		cxidev_warn_once(cdev, "C_EE_CFG_INIT_EQ_HW_STATE was still pending.\n");
+		mutex_unlock(&hw->init_eq_hw_state);
+		return rc;
+	}
+
+	/* Ensure no other PCT EQ exist before activating it. */
+	if (attr->flags & CXI_EQ_REGISTER_PCT) {
+		if (hw->pct_eq_n != C_EQ_NONE) {
+			mutex_unlock(&hw->init_eq_hw_state);
+			return -EEXIST;
+		}
+
+		hw->pct_eq_n = eq_n;
+	}
+
+	/* Write EQ configuration to hardware */
+	spin_lock(&hw->eq_shadow_lock);
+
+	cass_eq_init(hw, eq_n, eq->lni_priv->lni.rgid, &eq->cfg,
+		     attr->flags & CXI_EQ_INIT_LONG,
+		     attr->flags & CXI_EQ_TGT_LONG);
+
+	if (attr->flags & CXI_EQ_TIMESTAMP_EVENTS)
+		eq_timestamp_toggle(hw, eq_n, true);
+
+	spin_unlock(&hw->eq_shadow_lock);
+
+	if (attr->flags & CXI_EQ_REGISTER_PCT) {
+		/* The EQ is reserved, and up and running now. The PCT
+		 * EQ can be programmed.
+		 */
+		set_pct_eq(hw, eq_n);
+	}
+
+	mutex_unlock(&hw->init_eq_hw_state);
+
+	return 0;
+}
+
+static int eq_mmio_map(struct cass_dev *hw, void __iomem **eq_mmio, int eq_idx)
+{
+	phys_addr_t mmio_phys = hw->regs_base + C_MEMORG_EE +
+		eq_idx * C_EE_SW_STATE_PAGE_SIZE;
+
+	*eq_mmio = ioremap(mmio_phys, PAGE_SIZE);
+	if (!*eq_mmio) {
+		cxidev_warn_once(&hw->cdev, "ioremap failed");
+		return -EFAULT;
+	}
+
+	return 0;
+}
+
+/**
+ * cass_eq_attach_irqs() - Attach event and status interrupt handlers to an EQ.
+ *
+ * @eq: Event queue structure
+ * @hw: Cassini device
+ * @cpus: CPU mask for IRQ affinity
+ * @event_cb: Event interrupt callback
+ * @event_cb_data: Event callback data
+ * @status_cb: Status interrupt callback
+ * @status_cb_data: Status callback data
+ *
+ * Return: 0 on success, negative error code on failure
+ */
+static int cass_eq_attach_irqs(struct cxi_eq_priv *eq, struct cass_dev *hw,
+			       struct cpumask *cpus,
+			       void (*event_cb)(void *cb_data), void *event_cb_data,
+			       void (*status_cb)(void *cb_data), void *status_cb_data)
+{
+	struct cass_irq *irq;
+	int rc = 0;
+
+	eq->event_cb = event_cb;
+	eq->event_cb_data = event_cb_data;
+	eq->status_cb = status_cb;
+	eq->status_cb_data = status_cb_data;
+	if (event_cb) {
+		eq->event_nb.notifier_call = eq_event_nb;
+
+		irq = cass_comp_irq_attach(hw, cpus, &eq->event_nb);
+		if (IS_ERR(irq)) {
+			rc = PTR_ERR(irq);
+			goto out;
+		}
+		eq->event_msi_irq = irq;
+	} else {
+		eq->event_msi_irq = NULL;
+	}
+
+	if (status_cb) {
+		eq->status_nb.notifier_call = eq_status_nb;
+
+		irq = cass_comp_irq_attach(hw, cpus, &eq->status_nb);
+		if (IS_ERR(irq)) {
+			rc = PTR_ERR(irq);
+			goto event_irq_detach;
+		}
+		eq->status_msi_irq = irq;
+	} else {
+		eq->status_msi_irq = NULL;
+	}
+
+	return 0;
+
+event_irq_detach:
+	if (eq->event_msi_irq)
+		cass_comp_irq_detach(hw, eq->event_msi_irq, &eq->event_nb);
+out:
+	return rc;
+}
+
+static struct cxi_eq *cxi_eq_alloc_vf(struct cxi_lni *lni, const struct cxi_md *md,
+				      const struct cxi_eq_attr *attr,
+				      void (*event_cb)(void *cb_data),
+				      void *event_cb_data,
+				      void (*status_cb)(void *cb_data),
+				      void *status_cb_data)
+{
+	struct cxi_dev *dev = container_of(lni, struct cxi_lni_priv, lni)->dev;
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+	struct cxi_eq_priv *eq;
+	bool passthrough = !!(attr->flags & CXI_EQ_PASSTHROUGH);
+	struct cxi_eq_alloc_cmd_vf cmd = {
+		.base.op = CXI_OP_EQ_ALLOC,
+		.base.lni = lni->id,
+		.base.attr = *attr,
+		/* We explicitly tell PF to do nothing with these fields */
+		.base.queue_md = (!passthrough && md) ? md->id : CXI_MD_NONE,
+		.base.event_wait = CXI_WAIT_NONE,
+		.base.status_wait = CXI_WAIT_NONE,
+	};
+	struct cxi_eq_alloc_resp resp;
+	size_t resp_len = sizeof(resp);
+	bool is_user = attr->flags & CXI_EQ_USER;
+	struct cpumask cpus = {};
+	struct cxi_eq_attr cmd_attr = *attr;
+	int rc;
+
+	if (!passthrough && !md) {
+		cxidev_err(dev, "EQ_ALLOC(VF): missing MD for non-passthrough\n");
+		return ERR_PTR(-EINVAL);
+	}
+
+	/* Queue buffer address and length must be page aligned. */
+	if (!IS_ALIGNED((uintptr_t)attr->queue, PAGE_SIZE))
+		return ERR_PTR(-EINVAL);
+
+	if (!IS_ALIGNED(attr->queue_len, PAGE_SIZE))
+		return ERR_PTR(-EINVAL);
+
+	if (!passthrough) {
+		cmd_attr.queue = (void *)(uintptr_t)
+			((uintptr_t)attr->queue - (uintptr_t)md->va);
+	}
+
+	eq = kzalloc(sizeof(*eq), GFP_KERNEL);
+	if (!eq)
+		return ERR_PTR(-ENOMEM);
+
+	eq->attr = *attr;
+	eq->lni_priv = container_of(lni, struct cxi_lni_priv, lni);
+	eq->active.md = md;
+	eq->active.events = eq->attr.queue;
+	eq->active.events_len = eq->attr.queue_len;
+	eq->queue_size = get_eq_queue_size(eq->active.events_len);
+	mutex_init(&eq->resize_mutex);
+	eq->resized = false;
+
+	if (eq->attr.cpu_affinity < nr_cpumask_bits)
+		cpumask_set_cpu(eq->attr.cpu_affinity, &cpus);
+
+	rc = cass_eq_attach_irqs(eq, hw, &cpus, event_cb, event_cb_data, status_cb, status_cb_data);
+	if (rc)
+		goto free_eq_alloc;
+
+	if (passthrough) {
+		if (is_user) {
+			rc = get_dma_addr_if_contig(hw, eq->active.events,
+						    eq->active.events_len,
+						    DMA_FROM_DEVICE,
+						    &eq->active.pages,
+						    &eq->active.dma_addr);
+		} else {
+			eq->active.dma_addr = dma_map_single(&hw->cdev.pdev->dev,
+							     eq->active.events,
+							     eq->active.events_len,
+							     DMA_FROM_DEVICE);
+			if (dma_mapping_error(&hw->cdev.pdev->dev, eq->active.dma_addr))
+				rc = -ENOMEM;
+		}
+
+		if (rc)
+			goto free_irqs;
+	} else {
+		eq->active.dma_addr = md->iova;
+	}
+
+	cmd.dma_addr = eq->active.dma_addr;
+	/* ... and instead give it the IRQ indices */
+	cmd.event_irq_idx = eq->event_msi_irq ? eq->event_msi_irq->idx : -1;
+	cmd.status_irq_idx = eq->status_msi_irq ? eq->status_msi_irq->idx : -1;
+	cmd.base.attr = cmd_attr;
+
+	rc = cxi_send_msg_to_pf(dev, &cmd, sizeof(cmd), &resp, &resp_len);
+	if (rc)
+		goto free_dma_map;
+
+	eq->eq.eqn = resp.eq;
+
+	if (!is_user) {
+		rc = eq_mmio_map(hw, &eq->eq_mmio, eq->eq.eqn);
+		if (rc) {
+			cxi_eq_free(&eq->eq);
+			return ERR_PTR(rc);
+		}
+	}
+
+	cxi_eq_init(&eq->eq, eq->active.events, eq->active.events_len,
+		    eq->eq.eqn, (__force u64 *)eq->eq_mmio);
+
+	return &eq->eq;
+
+free_dma_map:
+	if (passthrough) {
+		if (is_user)
+			put_pages_contig(hw, &eq->active);
+		else
+			dma_unmap_single(&hw->cdev.pdev->dev, eq->active.dma_addr,
+					 eq->active.events_len, DMA_FROM_DEVICE);
+	}
+free_irqs:
+	if (eq->event_msi_irq)
+		cass_comp_irq_detach(hw, eq->event_msi_irq, &eq->event_nb);
+	if (eq->status_msi_irq)
+		cass_comp_irq_detach(hw, eq->status_msi_irq, &eq->status_nb);
+free_eq_alloc:
+	kfree(eq);
+	return ERR_PTR(rc);
+}
+
+/**
+ * cxi_eq_alloc_internal() - Allocate a new event queue resource.
+ *
+ * @lni: LNI to associate with the event queue.
+ * @md: Memory descriptor for the queue
+ * @attr: Event queue creation attributes.
+ * @event_cb: Event interrupt callback for that EQ.
+ * @event_cb_data: Opaque owner context pointer. Can be used in the event
+ *                 interrupt callback to retrieve some internal structures.
+ * @status_cb: Status interrupt callback for that EQ.
+ * @status_cb_data: Opaque owner context pointer. Can be used in the status
+ *                  interrupt callback to retrieve some internal structures.
+ * @dma_addr: DMA address of the event queue buffer. NULL if not provided.
+ * @event_irq_idx: Event IRQ index for VF EQ allocation. Use -1 for PF EQ allocation.
+ * @status_irq_idx: Status IRQ index for VF EQ allocation. Use -1 for PF EQ allocation.
+ *
+ * Return: On success, a pointer to the allocated event queue structure. On
+ * error, an error pointer containing a negative error number.
+ */
+struct cxi_eq *cxi_eq_alloc_internal(struct cxi_lni *lni, const struct cxi_md *md,
+				     const struct cxi_eq_attr *attr,
+				     void (*event_cb)(void *cb_data),
+				     void *event_cb_data,
+				     void (*status_cb)(void *cb_data),
+				     void *status_cb_data, dma_addr_t dma_addr,
+				     int event_irq_idx, int status_irq_idx)
+{
+	struct cxi_lni_priv *lni_priv = container_of(lni, struct cxi_lni_priv, lni);
+	struct cxi_dev *cdev = lni_priv->dev;
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	struct cxi_eq_priv *eq;
+	struct cxi_md_priv *md_priv = NULL;
+	int eq_n;
+	int rc;
+	bool passthrough = !!(attr->flags & CXI_EQ_PASSTHROUGH);
+	bool is_user = attr->flags & CXI_EQ_USER;
+	struct cpumask cpus = {};
+	bool is_vf = lni_priv->is_vf;
+	u8 vf_num = lni_priv->vf_num;
+
+	if (!attr->queue_len || attr->queue_len > MAX_EQ_LEN ||
+	    (!attr->queue && !(is_vf && !passthrough)))
+		return ERR_PTR(-EINVAL);
+
+	/* If status updates are enabled, ensure all requested updates are in
+	 * the range [0-100].
+	 */
+	if (attr->status_thresh_count &&
+	    (attr->status_thresh_count > 4 ||
+	     attr->status_thresh_base > 100 ||
+	     attr->status_thresh_delta > 100 ||
+	     ((attr->status_thresh_count - 1) * attr->status_thresh_delta +
+	      (100 - attr->status_thresh_base)) > 100))
+		return ERR_PTR(-EINVAL);
+
+	/* Queue buffer address and length must be page aligned. */
+	if (!IS_ALIGNED((uintptr_t)attr->queue, PAGE_SIZE))
+		return ERR_PTR(-EINVAL);
+
+	if (!IS_ALIGNED(attr->queue_len, PAGE_SIZE))
+		return ERR_PTR(-EINVAL);
+
+	/* If using EQ translation, the MD must cover the aligned buffer. */
+	if (!passthrough &&
+	    (!md ||
+	     !CXI_MD_CONTAINS(md, attr->queue, attr->queue_len)))
+		return ERR_PTR(-EINVAL);
+
+	/* Only admin can create the EQ for PCT */
+	if ((attr->flags & CXI_EQ_REGISTER_PCT) && !capable(CAP_SYS_ADMIN))
+		return ERR_PTR(-EPERM);
+
+	if ((size_t)attr->reserved_slots >
+	    (get_eq_queue_size(attr->queue_len) - 1))
+		return ERR_PTR(-EINVAL);
+
+	eq = pf_get_eq_id(lni_priv);
+	if (IS_ERR(eq))
+		return ERR_PTR(PTR_ERR(eq));
+
+	eq_n = eq->eq.eqn;
+
+	eq->attr = *attr;
+	eq->lni_priv = lni_priv;
+	eq->active.md = md;
+	eq->active.events = eq->attr.queue;
+	eq->active.events_len = eq->attr.queue_len;
+	eq->queue_size = get_eq_queue_size(eq->active.events_len);
+	mutex_init(&eq->resize_mutex);
+	eq->resized = false;
+
+	refcount_set(&eq->refcount, 1);
+
+	if (!is_user && !is_vf) {
+		phys_addr_t mmio_phys = hw->regs_base + C_MEMORG_EE +
+				eq_n * C_EE_SW_STATE_PAGE_SIZE;
+		eq->eq_mmio = ioremap(mmio_phys, PAGE_SIZE);
+		if (!eq->eq_mmio) {
+			cxidev_warn_once(cdev, "ioremap failed\n");
+			rc = -EFAULT;
+			goto id_remove;
+		}
+	}
+
+	if (!is_vf && eq->attr.cpu_affinity < nr_cpumask_bits)
+		cpumask_set_cpu(eq->attr.cpu_affinity, &cpus);
+
+	if (!is_vf) {
+		rc = cass_eq_attach_irqs(eq, hw, &cpus, event_cb, event_cb_data,
+					 status_cb, status_cb_data);
+		if (rc)
+			goto eq_unmap;
+
+		if (passthrough) {
+			if (is_user) {
+				rc = get_dma_addr_if_contig(hw, eq->active.events,
+							    eq->active.events_len,
+							    DMA_FROM_DEVICE,
+							    &eq->active.pages,
+							    &eq->active.dma_addr);
+			} else {
+				eq->active.dma_addr = dma_map_single(&hw->cdev.pdev->dev,
+								     eq->active.events,
+								     eq->active.events_len,
+								     DMA_FROM_DEVICE);
+				if (dma_mapping_error(&hw->cdev.pdev->dev, eq->active.dma_addr))
+					rc = -ENOMEM;
+				else
+					rc = 0;
+			}
+
+			if (rc)
+				goto status_irq_detach;
+		} else {
+			md_priv = container_of(eq->active.md, struct cxi_md_priv, md);
+
+			refcount_inc(&md_priv->refcount);
+		}
+	} else {
+		if (passthrough) {
+			/* VF EQ passthrough: use dma_addr from the VF */
+			eq->active.dma_addr = dma_addr;
+		} else {
+			md_priv = container_of(eq->active.md, struct cxi_md_priv, md);
+			refcount_inc(&md_priv->refcount);
+		}
+	}
+
+	cxi_eq_init(&eq->eq, eq->active.events, eq->active.events_len,
+		    eq_n, (__force u64 *)eq->eq_mmio);
+
+	if (!is_user && !is_vf)
+		memset(eq->active.events, 0, eq->active.events_len);
+
+	rc = pf_write_eq_config(eq, is_vf, event_irq_idx, status_irq_idx);
+	if (rc)
+		goto free_md;
+
+	spin_lock(&lni_priv->res_lock);
+	list_add_tail(&eq->list, &lni_priv->eq_list);
+	spin_unlock(&lni_priv->res_lock);
+
+	if (!eq->reused) {
+		atomic_inc(&hw->stats.eq);
+
+		eq_debugfs_create(eq_n, eq, hw, lni_priv);
+
+		refcount_inc(&lni_priv->refcount);
+	}
+
+	/* Grant access to the resource from the VF */
+	if (is_vf)
+		cass_config_sriovt(hw, true, vf_num, 4096 + eq_n);
+
+	return &eq->eq;
+
+free_md:
+	if (passthrough) {
+		if (!is_vf) {
+			if (is_user)
+				put_pages_contig(hw, &eq->active);
+			else
+				dma_unmap_single(&hw->cdev.pdev->dev, eq->active.dma_addr,
+						 eq->attr.queue_len, DMA_FROM_DEVICE);
+		}
+	} else {
+		refcount_dec(&md_priv->refcount);
+	}
+
+status_irq_detach:
+	if (eq->status_msi_irq)
+		cass_comp_irq_detach(hw, eq->status_msi_irq, &eq->status_nb);
+	if (eq->event_msi_irq)
+		cass_comp_irq_detach(hw, eq->event_msi_irq, &eq->event_nb);
+eq_unmap:
+	if (!is_user)
+		iounmap(eq->eq_mmio);
+id_remove:
+	pf_put_eq_id(eq);
+
+	return ERR_PTR(rc);
+}
+EXPORT_SYMBOL(cxi_eq_alloc_internal);
+
+/**
+ * cxi_eq_alloc() - Allocate a new event queue resource.
+ *
+ * @lni: LNI to associate with the event queue.
+ * @md: Memory descriptor for the queue
+ * @attr: Event queue creation attributes.
+ * @event_cb: Event interrupt callback for that EQ.
+ * @event_cb_data: Opaque owner context pointer. Can be used in the event
+ *                 interrupt callback to retrieve some internal structures.
+ * @status_cb: Status interrupt callback for that EQ.
+ * @status_cb_data: Opaque owner context pointer. Can be used in the status
+ *                  interrupt callback to retrieve some internal structures.
+ *
+ * Return: On success, a pointer to the allocated event queue structure. On
+ * error, an error pointer containing a negative error number.
+ */
+struct cxi_eq *cxi_eq_alloc(struct cxi_lni *lni, const struct cxi_md *md,
+			    const struct cxi_eq_attr *attr,
+			    void (*event_cb)(void *cb_data),
+			    void *event_cb_data,
+			    void (*status_cb)(void *cb_data),
+			    void *status_cb_data)
+{
+	struct cxi_dev *dev = container_of(lni, struct cxi_lni_priv, lni)->dev;
+
+	if (!dev->is_physfn)
+		return cxi_eq_alloc_vf(lni, md, attr,
+				       event_cb, event_cb_data,
+				       status_cb, status_cb_data);
+
+	return cxi_eq_alloc_internal(lni, md, attr,
+				     event_cb, event_cb_data,
+				     status_cb, status_cb_data, 0, -1, -1);
+}
+EXPORT_SYMBOL(cxi_eq_alloc);
+
+/** cxi_eq_free_vf() - Free VF event queue resource.
+ *
+ * @evtq: A pointer to previously allocated event queue structure.
+ *
+ * Return: On success, returns zero.
+ */
+static int cxi_eq_free_vf(struct cxi_eq *evtq)
+{
+	struct cxi_eq_priv *eq = container_of(evtq, struct cxi_eq_priv, eq);
+	struct cxi_dev *cdev = container_of(&eq->lni_priv->lni, struct cxi_lni_priv_vf, lni)->dev;
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	bool passthrough = !!(eq->attr.flags & CXI_EQ_PASSTHROUGH);
+	bool is_user = eq->attr.flags & CXI_EQ_USER;
+	size_t resp_len = 0;
+	const struct cxi_eq_free_cmd cmd = {
+		.op = CXI_OP_EQ_FREE,
+		.eq = eq->eq.eqn,
+	};
+	int rc;
+
+	/* Send EQ free command to PF */
+	rc = cxi_send_msg_to_pf(cdev, &cmd, sizeof(cmd), NULL, &resp_len);
+	if (rc)
+		return rc;
+
+	/* Detach IRQs */
+	if (eq->status_msi_irq)
+		cass_comp_irq_detach(hw, eq->status_msi_irq, &eq->status_nb);
+	if (eq->event_msi_irq)
+		cass_comp_irq_detach(hw, eq->event_msi_irq, &eq->event_nb);
+
+	/* Unmap EQ MMIO if not for user */
+	if (!is_user)
+		iounmap(eq->eq_mmio);
+
+	/* Unmap EQ buffer if passthrough */
+	if (passthrough) {
+		if (is_user) {
+			put_pages_contig(hw, &eq->active);
+			if (eq->resized)
+				put_pages_contig(hw, &eq->resize);
+		} else {
+			dma_unmap_single(&hw->cdev.pdev->dev,
+					 eq->active.dma_addr, eq->attr.queue_len,
+					 DMA_FROM_DEVICE);
+			if (eq->resized)
+				dma_unmap_single(&hw->cdev.pdev->dev,
+						 eq->resize.dma_addr,
+						 eq->resize.events_len,
+						 DMA_FROM_DEVICE);
+		}
+	}
+
+	return 0;
+}
+
+/**
+ * cxi_eq_free() - Free event queue resource.
+ *
+ * @evtq: A pointer to previously allocated event queue structure.
+ *
+ * Return: On success, returns zero.
+ */
+int cxi_eq_free(struct cxi_eq *evtq)
+{
+	struct cxi_eq_priv *eq;
+	struct cxi_dev *cdev;
+	struct cass_dev *hw;
+	struct cxi_lni_priv *lni_priv;
+	struct cxi_md_priv *md_priv;
+	bool passthrough;
+	bool is_user;
+	bool is_vf;
+	union c_ee_cfg_sts_eq_hw_state hw_state;
+	unsigned int wr_ptr;
+
+	if (!evtq)
+		return -EINVAL;
+
+	eq = container_of(evtq, struct cxi_eq_priv, eq);
+	cdev = eq->lni_priv->dev;
+
+	if (!cdev->is_physfn)
+		return cxi_eq_free_vf(evtq);
+
+	hw = container_of(cdev, struct cass_dev, cdev);
+	lni_priv = eq->lni_priv;
+	is_user = eq->attr.flags & CXI_EQ_USER;
+	is_vf = lni_priv->is_vf;
+	passthrough = !!(eq->attr.flags & CXI_EQ_PASSTHROUGH);
+
+	/* Remove access to this resource from a VF */
+	if (is_vf)
+		cass_config_sriovt(hw, false, lni_priv->vf_num, 4096 + eq->eq.eqn);
+
+	cxidev_WARN_ONCE(cdev, !refcount_dec_and_test(&eq->refcount),
+			 "Resource leaks - EQ refcount not zero: %d\n",
+			 refcount_read(&eq->refcount));
+
+	spin_lock(&lni_priv->res_lock);
+	list_del(&eq->list);
+	spin_unlock(&lni_priv->res_lock);
+
+	if (eq->attr.flags & CXI_EQ_REGISTER_PCT) {
+		set_pct_eq(hw, C_EQ_NONE);
+
+		mutex_lock(&hw->init_eq_hw_state);
+		hw->pct_eq_n = C_EQ_NONE;
+		mutex_unlock(&hw->init_eq_hw_state);
+	}
+
+	if (eq->status_msi_irq)
+		cass_comp_irq_detach(hw, eq->status_msi_irq, &eq->status_nb);
+
+	if (eq->event_msi_irq)
+		cass_comp_irq_detach(hw, eq->event_msi_irq, &eq->event_nb);
+
+	spin_lock(&hw->eq_shadow_lock);
+
+	if (eq->attr.flags & CXI_EQ_TIMESTAMP_EVENTS)
+		eq_timestamp_toggle(hw, eq->eq.eqn, false);
+
+	cass_eq_clear(hw, &eq->eq);
+
+	spin_unlock(&hw->eq_shadow_lock);
+
+	/* Wait for the EQ write pointer to stabilize before freeing
+	 * the buffer
+	 */
+	cass_read(hw, C_EE_CFG_STS_EQ_HW_STATE(eq->eq.eqn),
+		  &hw_state, sizeof(hw_state));
+	wr_ptr = hw_state.wr_ptr;
+	while (true) {
+		cass_read(hw, C_EE_CFG_STS_EQ_HW_STATE(eq->eq.eqn),
+			  &hw_state, sizeof(hw_state));
+		if (wr_ptr == hw_state.wr_ptr)
+			break;
+		wr_ptr = hw_state.wr_ptr;
+		udelay(1);
+	}
+
+	if (passthrough) {
+		if (!is_vf) {
+			if (is_user) {
+				put_pages_contig(hw, &eq->active);
+
+				if (eq->resized)
+					put_pages_contig(hw, &eq->resize);
+			} else {
+				dma_unmap_single(&hw->cdev.pdev->dev,
+						 eq->active.dma_addr, eq->attr.queue_len,
+						 DMA_FROM_DEVICE);
+				if (eq->resized)
+					dma_unmap_single(&hw->cdev.pdev->dev,
+							 eq->resize.dma_addr,
+							 eq->resize.events_len,
+							 DMA_FROM_DEVICE);
+			}
+		}
+	} else {
+		md_priv = container_of(eq->active.md, struct cxi_md_priv, md);
+		refcount_dec(&md_priv->refcount);
+
+		if (eq->resized) {
+			md_priv = container_of(eq->resize.md,
+					       struct cxi_md_priv, md);
+			refcount_dec(&md_priv->refcount);
+		}
+	}
+
+	if (!is_user)
+		iounmap(eq->eq_mmio);
+
+	/* Hang the EQ on the LNI pending deletion list, to be
+	 * released later
+	 */
+	spin_lock(&lni_priv->res_lock);
+	list_add_tail(&eq->list, &lni_priv->eq_cleanups_list);
+	spin_unlock(&lni_priv->res_lock);
+
+	return 0;
+}
+EXPORT_SYMBOL(cxi_eq_free);
+
+/* Finish releasing all the EQs on the deletion pending list */
+void finalize_eq_cleanups(struct cxi_lni_priv *lni)
+{
+	struct cxi_dev *dev = lni->dev;
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+	struct cxi_eq_priv *eq;
+
+	while ((eq = list_first_entry_or_null(&lni->eq_cleanups_list,
+					      struct cxi_eq_priv, list))) {
+		list_del(&eq->list);
+
+		debugfs_remove(eq->lni_dir);
+		debugfs_remove(eq->debug_file);
+
+		refcount_dec(&lni->refcount);
+		atomic_dec(&hw->stats.eq);
+		cxi_rgroup_free_resource(lni->rgroup, CXI_RESOURCE_EQ);
+		ida_free(&hw->eq_index_table, eq->eq.eqn);
+		kfree(eq);
+	}
+}
+
+/**
+ * cxi_eq_user_info() - Get userspace mmap info for an event queue.
+ *
+ * @evtq: A pointer to previously allocated event queue structure.
+ * @csr_addr: On success, will contain the address of the event queue CSRs.
+ * @csr_size: On success, will contain the size of the event queue CSRs.
+ *
+ * Return: On success, returns zero. On error, returns a negative error number.
+ */
+int cxi_eq_user_info(struct cxi_eq *evtq,
+		     phys_addr_t *csr_addr, size_t *csr_size)
+{
+	struct cxi_eq_priv *eq = container_of(evtq, struct cxi_eq_priv, eq);
+	struct cxi_dev *cdev = eq->lni_priv->dev;
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+
+	/* Userspace needs the SW State descriptor CSR address */
+	*csr_addr = hw->regs_base + C_MEMORG_EE +
+		(eq->eq.eqn * C_EE_SW_STATE_PAGE_SIZE);
+	*csr_size = PAGE_SIZE;
+
+	return 0;
+}
+EXPORT_SYMBOL(cxi_eq_user_info);
diff --git a/drivers/net/ethernet/hpe/ss1/cass_nta.c b/drivers/net/ethernet/hpe/ss1/cass_nta.c
new file mode 100644
index 000000000000..416595de9500
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_nta.c
@@ -0,0 +1,1996 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2019, 2024-2026 Hewlett Packard Enterprise Development LP */
+
+/*
+ * Address Translation Unit (ATU) management
+ * Nic Translation Agent (NTA) mode
+ */
+
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#include <linux/types.h>
+#include <linux/hugetlb.h>
+#include <linux/iova.h>
+#include <linux/bvec.h>
+#include <linux/iopoll.h>
+#include <linux/workqueue.h>
+#include <linux/mmu_notifier.h>
+
+#include "cass_core.h"
+
+/* Default size of the root page table for a two level table.
+ * The root page table size is 2 ^ (PAGE_SHIFT + ac_size_dbl) (currently
+ * 16 KB) and covers 2 ^ ac_size_dbl GB.
+ */
+static int ac_size_dbl = 5;
+module_param(ac_size_dbl, int, 0644);
+MODULE_PARM_DESC(ac_size_dbl, "Default two level AC size");
+
+/* Default size of the root page table for a single level table.
+ * The root page table size is 2 ^ (PAGE_SHIFT + ac_size_sgl) (currently
+ * 8 MB) and covers 2 ^ ((PAGE_SHIFT * 2) + ac_size_sgl) bytes.
+ */
+static int ac_size_sgl = 8;
+module_param(ac_size_sgl, int, 0644);
+MODULE_PARM_DESC(ac_size_sgl, "Default one level AC size");
+
+static ulong min_iova_offset = 1UL * 1024 * 1024 * 1024;
+module_param(min_iova_offset, ulong, 0644);
+MODULE_PARM_DESC(min_iova_offset, "IOVA offset if VA range straddles AC");
+
+static int atucq_timeout_us = 100000;
+module_param(atucq_timeout_us, int, 0644);
+MODULE_PARM_DESC(atucq_timeout_us, "ATUCQ timeout in microseconds");
+
+static int decouple_timeout_us = 150;
+module_param(decouple_timeout_us, int, 0644);
+MODULE_PARM_DESC(decouple_timeout_us,
+		 "ATUCQ timeout in microseconds when decoupling is enabled");
+
+bool odp_sw_decouple = true;
+module_param(odp_sw_decouple, bool, 0644);
+MODULE_PARM_DESC(odp_sw_decouple, "Enable software ODP decoupling");
+
+static int pri_shift_set(const char *val, const struct kernel_param *kp)
+{
+	int n;
+	int ret;
+
+	ret = kstrtoint(val, 10, &n);
+	if (ret || n < 12 || n > 30)
+		return -EINVAL;
+
+	return param_set_int(val, kp);
+}
+
+static const struct kernel_param_ops pri_shift_ops = {
+	.set = pri_shift_set,
+	.get = param_get_int,
+};
+
+static int pri_shift = 16;
+module_param_cb(pri_shift, &pri_shift_ops, &pri_shift, 0644);
+MODULE_PARM_DESC(pri_shift, "ODP default number of pages to fault");
+
+static irqreturn_t cass_pri_int_cb(int irq, void *context);
+static void cass_pri_worker(struct work_struct *work);
+static void cass_prb_worker(struct work_struct *work);
+static void cass_odpq_write(struct cass_dev *hw, int index,
+			    enum c_odp_status status);
+
+static int min_root_entries(struct cass_ac *cac)
+{
+	int default_ac_size = (cac->ptg_mode == C_ATU_PTG_MODE_SGL) ?
+			ac_size_sgl : ac_size_dbl;
+
+	return BIT(PAGE_SHIFT + default_ac_size) / ATU_PTE_ENTRY_SIZE;
+}
+
+static void cass_nta_cmdproc_write(struct cass_dev *hw, unsigned int wr_index)
+{
+	union c_atu_cfg_cmdproc atu_ptrs = {
+		.wr_ptr = wr_index
+	};
+
+	cass_write(hw, C_ATU_CFG_CMDPROC, &atu_ptrs, sizeof(atu_ptrs));
+}
+
+static void cass_nta_cq_write(struct cass_dev *hw, unsigned int index,
+			      const union c_atu_cfg_cq_table *entry)
+{
+	cass_write(hw, C_ATU_CFG_CQ_TABLE(index), entry, sizeof(*entry));
+}
+
+void cass_nta_cq_fini(struct cass_dev *hw)
+{
+	free_irq(pci_irq_vector(hw->cdev.pdev, hw->atu_cq_vec), hw);
+}
+
+static irqreturn_t cass_nta_cq_cb(int irq, void *context)
+{
+	/* Not expected to ever be called */
+	BUG();
+
+	return IRQ_HANDLED;
+}
+
+/**
+ * cass_nta_cq_init() - NTA command queue initialization
+ *
+ * @hw: Cassini device
+ */
+int cass_nta_cq_init(struct cass_dev *hw)
+{
+	struct cass_atu_cq *cq = &hw->atu_cq;
+	static const union c_atu_cfg_wb_data wb_data = {
+		.data = WAIT_RSP_DATA
+	};
+	union c_atu_cfg_cmds cfg_cmds = {
+		.writeback_acid = ATU_NTA_DEF_PI_ACXT
+	};
+	int rc;
+
+	cq->rsp_dma_addr = dma_map_single(&hw->cdev.pdev->dev, &cq->wait_rsp_data,
+					  sizeof(cq->wait_rsp_data), DMA_FROM_DEVICE);
+	if (dma_mapping_error(&hw->cdev.pdev->dev, cq->rsp_dma_addr))
+		return -ENOMEM;
+
+	cq->cmp_wait_rsp_addr = (cq->rsp_dma_addr + offsetof(struct wait_rsp_data, cmp)) >> 3;
+	cq->ib_wait_rsp_addr = (cq->rsp_dma_addr + offsetof(struct wait_rsp_data, ib)) >> 3;
+
+	mutex_init(&cq->atu_cq_mutex);
+	mutex_init(&cq->atu_ib_mutex);
+	cass_write(hw, C_ATU_CFG_WB_DATA, &wb_data, sizeof(wb_data));
+
+	scnprintf(cq->cmpl_wait_int_name, sizeof(cq->cmpl_wait_int_name),
+		  "%s_atu_cq", hw->cdev.name);
+	rc = request_irq(pci_irq_vector(hw->cdev.pdev, hw->atu_cq_vec),
+			 cass_nta_cq_cb, 0, cq->cmpl_wait_int_name, hw);
+	if (rc) {
+		dev_err(&hw->cdev.pdev->dev, "Failed to request IRQ.\n");
+		dma_unmap_single(&hw->cdev.pdev->dev, cq->rsp_dma_addr,
+				 sizeof(cq->wait_rsp_data), DMA_FROM_DEVICE);
+		return rc;
+	}
+
+	disable_irq(pci_irq_vector(hw->cdev.pdev, hw->atu_cq_vec));
+
+	cfg_cmds.ib_wait_int_idx = hw->atu_cq_vec;
+	cfg_cmds.cmpl_wait_int_idx = hw->atu_cq_vec;
+	cass_write(hw, C_ATU_CFG_CMDS, &cfg_cmds, sizeof(cfg_cmds));
+
+	return 0;
+}
+
+void cass_nta_pri_fini(struct cass_dev *hw)
+{
+	if (cass_version(hw, CASSINI_1_0))
+		return;
+
+	cass_clear(hw, C_ATU_CFG_ODP, C_ATU_CFG_ODP_SIZE);
+	cass_clear(hw, C_ATU_CFG_PRI, C_ATU_CFG_PRI_SIZE);
+	cass_flush_pci(hw);
+	free_irq(pci_irq_vector(hw->cdev.pdev, hw->atu_pri_vec), hw);
+	destroy_workqueue(hw->prb_wq);
+	destroy_workqueue(hw->pri_wq);
+	dma_unmap_single(&hw->cdev.pdev->dev, hw->prt_dma_addr,
+			 sizeof(struct c_page_request_entry), DMA_FROM_DEVICE);
+	kfree(hw->page_request_table);
+	dma_unmap_single(&hw->cdev.pdev->dev, hw->atu_cq.rsp_dma_addr,
+			 sizeof(struct wait_rsp_data), DMA_FROM_DEVICE);
+}
+
+/**
+ * cass_nta_pri_init() - Initialize the NTA Page Request interface
+ *
+ * @hw: Cassini device
+ */
+int cass_nta_pri_init(struct cass_dev *hw)
+{
+	int rc;
+	union c_atu_cfg_pri cpa;
+	union c_atu_cfg_odp codp = {
+		.acid = ATU_PHYS_AC,
+		.int_enable = 1,
+		.odp_en = 1
+	};
+
+	if (cass_version(hw, CASSINI_1_0))
+		return 0;
+
+	hw->page_request_table = kcalloc(C_ATU_PRB_ENTRIES,
+					 sizeof(struct c_page_request_entry),
+					 GFP_KERNEL);
+	if (!hw->page_request_table)
+		return -ENOMEM;
+
+	hw->prt_dma_addr = dma_map_single(&hw->cdev.pdev->dev, hw->page_request_table,
+					  sizeof(struct c_page_request_entry),
+					  DMA_FROM_DEVICE);
+	if (dma_mapping_error(&hw->cdev.pdev->dev, hw->prt_dma_addr)) {
+		rc = -ENOMEM;
+		goto free_table;
+	}
+
+	hw->pri_rd_ptr = 0;
+
+	scnprintf(hw->odp_pri_int_name, sizeof(hw->odp_pri_int_name),
+		  "%s_odp_pri", hw->cdev.name);
+	rc = request_irq(pci_irq_vector(hw->cdev.pdev, hw->atu_pri_vec),
+			 cass_pri_int_cb, 0, hw->odp_pri_int_name, hw);
+	if (rc) {
+		pr_err("Failed to request IRQ.\n");
+		goto free_mapping;
+	}
+
+	/* limit to a single threaded worker */
+	hw->pri_wq = alloc_workqueue("pri_wq", WQ_UNBOUND, 1);
+	if (!hw->pri_wq) {
+		rc = -ENOMEM;
+		pr_err("Failed to allocate PRI workqueue\n");
+		goto alloc_wq_failed;
+	}
+
+	hw->prb_wq = alloc_workqueue("prb_wq", WQ_UNBOUND, 1);
+	if (!hw->prb_wq) {
+		rc = -ENOMEM;
+		pr_err("Failed to allocate PRB workqueue\n");
+		goto alloc_prb_wq_failed;
+	}
+
+	cpa.base_addr = hw->prt_dma_addr >> C_ADDR_SHIFT;
+	cass_write(hw, C_ATU_CFG_PRI, &cpa, sizeof(cpa));
+
+	codp.int_idx = hw->atu_pri_vec;
+	cass_write(hw, C_ATU_CFG_ODP, &codp, sizeof(codp));
+
+	INIT_WORK(&hw->pri_work, cass_pri_worker);
+	INIT_WORK(&hw->prb_work, cass_prb_worker);
+
+	return 0;
+
+alloc_prb_wq_failed:
+	destroy_workqueue(hw->pri_wq);
+alloc_wq_failed:
+	free_irq(pci_irq_vector(hw->cdev.pdev, hw->atu_pri_vec), hw);
+free_mapping:
+	dma_unmap_single(&hw->cdev.pdev->dev, hw->prt_dma_addr,
+			 sizeof(struct c_page_request_entry), DMA_FROM_DEVICE);
+free_table:
+	kfree(hw->page_request_table);
+
+	return rc;
+}
+
+int cass_sts_idle(struct sts_idle *sidle)
+{
+	union c_atu_sts_cmdproc sts;
+	struct cass_dev *hw = sidle->hw;
+
+	cass_read(hw, C_ATU_STS_CMDPROC, &sts, sizeof(sts));
+
+	return sidle->ib_wait ? sts.inbound_wait_idle : sts.atucq_idle;
+}
+
+static int cass_poll_sts_cmdproc_idle(struct cass_dev *hw, bool ib_wait)
+{
+	int ret;
+	int idle;
+	int timeout_us = ib_wait ? ATU_STS_IBW_IDLE_TIMEOUT :
+					ATU_STS_ATUCQ_IDLE_TIMEOUT;
+	struct sts_idle sidle = {
+		.hw = hw,
+		.ib_wait = ib_wait
+	};
+
+	ret = readx_poll_timeout(cass_sts_idle, &sidle, idle, (idle),
+				 10, timeout_us);
+	if (ret)
+		pr_crit("Timed out waiting for %s idle\n",
+			ib_wait ? "IB wait" : "ATUCQ");
+
+	return ret;
+}
+
+#define err_dump_csr64(name) do {		\
+	u64 val;				\
+	cass_read(hw, name, &val, sizeof(val));	\
+	cxidev_warn_ratelimited(&hw->cdev, #name " %016llx\n", val);	\
+	} while (0)
+
+static bool cass_cmdproc_debug(struct cass_dev *hw, bool inbound_wait)
+{
+	union c_mb_sts_rev rev;
+
+	/* check if HW is still alive */
+	cass_read(hw, C_MB_STS_REV, &rev, sizeof(rev));
+	if (rev.vendor_id != hw->rev.vendor_id) {
+		pr_err("HW is in a bad state\n");
+		return true;
+	}
+
+	cxidev_warn_ratelimited(&hw->cdev, "%s wait timeout\n",
+				inbound_wait ? "Inbound" : "Completion");
+	err_dump_csr64(C_ATU_STS_CMDPROC);
+	err_dump_csr64(C_ATU_STS_ODP_DECOUPLE);
+	err_dump_csr64(C_ATU_STS_AT_EPOCH);
+	err_dump_csr64(C_ATU_STS_IB_EPOCH);
+
+	return false;
+}
+
+static void cass_dcpl_debug(struct cass_dev *hw)
+{
+	u64 val1;
+	u64 val2;
+
+	cass_read(hw, C_ATU_STS_CMDPROC, &val1, sizeof(val1));
+	cass_read(hw, C_ATU_STS_AT_EPOCH, &val2, sizeof(val2));
+	cxidev_warn_ratelimited(&hw->cdev,
+				"Completion wait timeout after decouple. atu_sts_cmdproc:0x%llx atu_sts_at_epoch:0x%llx rsp_data:0x%llx\n",
+				val1, val2, hw->atu_cq.wait_rsp_data.cmp);
+}
+
+static void cass_completion_wait(struct cass_dev *hw, unsigned int wr_index)
+{
+	int rc;
+	int ret;
+	u64 cw_rsp_read_data;
+	bool hw_failure;
+	int decoupled = 0;
+	union c_atu_cfg_cq_table entry = {};
+	struct cass_atu_cq *cq = &hw->atu_cq;
+	int timeout = odp_sw_decouple ? decouple_timeout_us : atucq_timeout_us;
+
+	atomic_inc(&hw->dcpl_comp_wait);
+
+	entry.cmd = C_ATU_COMPLETION_WAIT;
+	entry.comp_wait_rsp_en = 1;
+	entry.comp_wait_rsp_addr = cq->cmp_wait_rsp_addr;
+
+	cq->wait_rsp_data.cmp = 0;
+
+	cass_nta_cq_write(hw, ATUCQ_ENTRY(wr_index), &entry);
+
+	/* WR_PTR should point at the entry that immediately follows
+	 * the last outstanding command.
+	 */
+	wr_index++;
+
+	/* Writes to C_ATU_CFG_CMDPROC are ignored if ATUCQ is not idle. */
+	cass_poll_sts_cmdproc_idle(hw, false);
+
+	/* start the processing of the command queue */
+	cass_nta_cmdproc_write(hw, wr_index);
+	cass_flush_pci(hw);
+
+	/* increase the timeout on the emulator */
+	if (HW_PLATFORM_Z1(hw))
+		timeout *= 10;
+
+	do {
+		ret = readq_poll_timeout_atomic(&cq->wait_rsp_data.cmp,
+						cw_rsp_read_data,
+						(cw_rsp_read_data == WAIT_RSP_DATA),
+						1, timeout);
+		if (ret) {
+			if (odp_sw_decouple) {
+				if (decoupled) {
+					cass_dcpl_debug(hw);
+					break;
+				}
+
+				rc = cass_odp_decouple(hw);
+				if (rc) {
+					cxidev_warn_ratelimited(&hw->cdev,
+								"Decoupling failed\n");
+					break;
+				}
+
+				decoupled++;
+				timeout = atucq_timeout_us;
+			} else {
+				hw_failure = cass_cmdproc_debug(hw, false);
+				if (hw_failure)
+					return;
+			}
+		}
+	} while (ret);
+}
+
+/**
+ * cass_invalidate_range() - Invalidate a range of IOVAs
+ *
+ * Invalidate a range of IOVAs by powers of two. Does not return until
+ * the commands have been executed - the completion wait is finished.
+ * inval_addr is modified with the length when invalidating sizes larger
+ * than a page. Treat the inval_size as bit 11 of the address.
+ *
+ * @cac:    Address Context struct
+ * @iova:   IO virtual address
+ * @length: Length of address range to invalidate
+ */
+void cass_invalidate_range(const struct cass_ac *cac, u64 iova,
+			   size_t length)
+{
+	u64 len;
+	u64 align;
+	u64 size_bits;
+	struct cass_dev *hw = container_of(cac->lni_priv->dev, struct cass_dev,
+					   cdev);
+	struct cass_atu_cq *cq = &hw->atu_cq;
+
+	if (cac->cfg_ac.do_not_cache) {
+		/* Completion wait needs to be performed so that the ODP
+		 * pri_worker is not referencing the AC while it is being
+		 * destroyed.
+		 */
+		if (cac->flags & CXI_MAP_USER_ADDR) {
+			mutex_lock(&cq->atu_cq_mutex);
+			cass_completion_wait(hw, 0);
+			mutex_unlock(&cq->atu_cq_mutex);
+		}
+
+		return;
+	}
+
+	pr_debug("ac:%d iova:%llx length:%lx\n", cac->ac.acid, iova, length);
+
+	mutex_lock(&cq->atu_cq_mutex);
+
+	while (length > 0) {
+		union c_atu_cfg_cq_table entry = {};
+		unsigned int wr_index = 0;
+
+		/* save room for the completion wait command */
+		while (length > 0 &&
+		       (C_ATU_CFG_CQ_TABLE_ENTRIES - wr_index) > 1) {
+			/* Walk through the iova and invalidate a len
+			 * based on its current alignment and the length
+			 * remaining.
+			 */
+			len = BIT(flsl(length));
+			align = !iova ? len : BIT(ffsl(iova));
+
+			if (len > align)
+				len = align;
+
+			/*
+			 * size_bits gives the 1's necessary to fill in the
+			 * lower bits of inval_addr and the inval_size fields
+			 */
+			size_bits = ((len - 1) & ~MASK(C_ADDR_SHIFT)) >> 1;
+			entry.qw = iova | size_bits;
+			entry.cmd = C_ATU_INVALIDATE_PAGES;
+			entry.inval_acid = cac->ac.acid;
+
+			atu_debug("ac:%d entry:%llx addr:%llx len:%llx\n",
+				  cac->ac.acid, entry.qw, iova, len);
+			cass_nta_cq_write(hw, ATUCQ_ENTRY(wr_index), &entry);
+
+			length -= len;
+			iova += len;
+			wr_index++;
+		}
+
+		cass_completion_wait(hw, wr_index);
+	}
+
+	mutex_unlock(&cq->atu_cq_mutex);
+}
+
+/**
+ * cass_inbound_wait() - flush internal Cassini buffers
+ *
+ * Called during resource cleanup.
+ *
+ * @hw: the device
+ * @wait_for_response: wait for hardware completion
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+int cass_inbound_wait(struct cass_dev *hw, bool wait_for_response)
+{
+	int ret;
+	int rc = 0;
+	int count = 0;
+	u64 rsp_read_data;
+	struct cass_atu_cq *cq = &hw->atu_cq;
+	union c_atu_cfg_inbound_wait cfg_iw = {
+		.rsp_en = wait_for_response,
+		.rsp_addr = cq->ib_wait_rsp_addr,
+	};
+
+	/* hw_failure was set previously. No need to progress */
+	if (cq->hw_failure)
+		return -EHOSTDOWN;
+
+	cq->wait_rsp_data.ib = 0;
+
+	/* Writes to C_ATU_CFG_CMDPROC are ignored if ATUCQ is not idle. */
+	ret = cass_poll_sts_cmdproc_idle(hw, true);
+	if (ret) {
+		rc = -EALREADY;
+		goto done;
+	}
+
+	/* process an inbound wait */
+	cass_write(hw, C_ATU_CFG_INBOUND_WAIT, &cfg_iw, sizeof(cfg_iw));
+	cass_flush_pci(hw);
+
+	if (wait_for_response) {
+		do {
+			ret = readq_poll_timeout_atomic(
+				&cq->wait_rsp_data.ib, rsp_read_data,
+				(rsp_read_data == WAIT_RSP_DATA), 1,
+				ATU_IBW_TIMEOUT);
+			if (ret) {
+				cq->hw_failure = cass_cmdproc_debug(hw, true);
+
+				if (cq->hw_failure) {
+					rc = -EHOSTDOWN;
+					break;
+				}
+
+				if (count++ > 4) {
+					rc = -ETIMEDOUT;
+					pr_err("Inbound wait is stuck - bailing out\n");
+					break;
+				}
+			}
+		} while (ret);
+	}
+
+done:
+	return rc;
+}
+
+static int cxi_inbound_wait_vf(struct cxi_dev *cdev)
+{
+	const struct cxi_inbound_wait_cmd cmd = {
+		.op = CXI_OP_INBOUND_WAIT,
+	};
+
+	return cxi_send_msg_to_pf(cdev, &cmd, sizeof(cmd), NULL, 0);
+}
+
+extern bool ibw_epoch_cntr_is_0(struct cass_dev *hw, bool *epoch_ret);
+/*
+ * cxi_inbound_wait - Flush internal cassini buffers
+ *
+ * @cdev: Cassini Device
+ * Return: 0 on success, negative errno on failure
+ */
+int cxi_inbound_wait(struct cxi_dev *cdev)
+{
+	int ret;
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	struct cass_atu_cq *cq = &hw->atu_cq;
+
+	if (!cdev->is_physfn)
+		return cxi_inbound_wait_vf(cdev);
+
+	mutex_lock(&cq->atu_ib_mutex);
+	ret = cass_inbound_wait(hw, true);
+	mutex_unlock(&cq->atu_ib_mutex);
+
+	return ret;
+}
+EXPORT_SYMBOL(cxi_inbound_wait);
+
+/**
+ * cass_nta_iova_alloc() - Allocate an IOVA from the domain
+ *
+ * @cac: Address Context
+ * @m_opts: Map options
+ */
+u64 cass_nta_iova_alloc(struct cass_ac *cac, const struct ac_map_opts *m_opts)
+{
+	u64 iova;
+
+	if (!cac->iovad)
+		return 0;
+
+	iova = ALLOC_IOVA_FAST(cac->iovad, m_opts->va_len, cac->iova_end);
+
+	/* Check for an iova overflow because of a 5.11+ (sles15sp4+)
+	 * iova bug. Free the current allocation and return iova not found.
+	 */
+	if (iova && iova < cac->iova_base) {
+		pr_debug("alloc_iova overflow iova:%llx iova_base:%llx\n",
+			 iova, cac->iova_base);
+		FREE_IOVA_FAST(cac->iovad, iova, m_opts->va_len);
+		iova = 0;
+	}
+
+	return iova;
+}
+
+void cass_nta_iova_fini(struct cass_ac *cac)
+{
+	if (cac->iovad) {
+		put_iova_domain(cac->iovad);
+		kfree(cac->iovad);
+	}
+}
+
+int cass_nta_iova_init(struct cass_ac *cac, size_t va_len)
+{
+#ifdef HAVE_IOVA_INIT_RCACHES
+	int ret;
+#endif
+
+	cac->iovad = kzalloc(sizeof(*cac->iovad), GFP_KERNEL);
+	if (!cac->iovad)
+		return -ENOMEM;
+
+	INIT_IOVA_DOMAIN(cac->iovad, PAGE_SIZE, cac->iova_base,
+			 cac->iova_end);
+
+/* linux 5.18 removed the initialization of the rcaches from init_iova_domain */
+#ifdef HAVE_IOVA_INIT_RCACHES
+	ret = iova_domain_init_rcaches(cac->iovad);
+	if (ret) {
+		cass_nta_iova_fini(cac);
+		return ret;
+	}
+#endif
+
+	return 0;
+}
+
+void cass_nta_free(struct cass_dev *hw, struct cass_nta *nta)
+{
+	dma_unmap_page(&hw->cdev.pdev->dev, nta->root_page_dma_addr,
+		       PAGE_SIZE << nta->root_order, DMA_TO_DEVICE);
+	__free_pages(nta->root_page, nta->root_order);
+	kfree(nta);
+}
+
+static struct cass_nta *cass_nta_alloc(struct cass_ac *cac, int l0_entries,
+				       int l1_entries)
+{
+	struct cass_dev *hw = container_of(cac->lni_priv->dev, struct cass_dev, cdev);
+	struct cass_nta *nta;
+	int ret;
+
+	nta = kzalloc(struct_size(nta, l1, l0_entries), GFP_KERNEL);
+	if (!nta)
+		return ERR_PTR(-ENOMEM);
+
+	nta->numa_node = dev_to_node(&hw->cdev.pdev->dev);
+	nta->root_order = get_order(l0_entries * ATU_PTE_ENTRY_SIZE);
+	nta->l1_order = get_order(l1_entries * ATU_PTE_ENTRY_SIZE);
+
+	nta->root_page = alloc_pages_node(nta->numa_node, GFP_KERNEL | __GFP_ZERO,
+					  nta->root_order);
+	if (!nta->root_page) {
+		ret = -ENOMEM;
+		goto alloc_pages_fail;
+	}
+
+	nta->root_page_dma_addr = dma_map_page(&hw->cdev.pdev->dev, nta->root_page, 0,
+					       PAGE_SIZE << nta->root_order,
+					       DMA_TO_DEVICE);
+	if (dma_mapping_error(&hw->cdev.pdev->dev, nta->root_page_dma_addr)) {
+		ret = -ENOMEM;
+		goto map_fail;
+	}
+
+	nta->root_ptr = page_address(nta->root_page);
+	nta->l0_entries = l0_entries;
+	nta->l1_entries = l1_entries;
+	cac->cfg_ac.nta_root_ptr = nta->root_page_dma_addr >> C_ADDR_SHIFT;
+	cac->cfg_ac.mem_base = cac->iova_base >> ATU_CFG_AC_TABLE_MB_SHIFT;
+	cac->cfg_ac.mem_size = cac->iova_len >> C_ADDR_SHIFT;
+	cac->cfg_ac.odp_mode = C_ATU_ODP_MODE_NIC_PRI;
+	cac->cfg_ac.ta_mode = C_ATU_NTA_MODE;
+
+	return nta;
+
+map_fail:
+	__free_pages(nta->root_page, nta->root_order);
+alloc_pages_fail:
+	kfree(nta);
+
+	return ERR_PTR(ret);
+}
+
+static int cass_ac_size(const struct ac_map_opts *m_opts, struct cass_ac *cac,
+			ulong npfns, int l1_entries)
+{
+	u64 l0_entries;
+
+	l0_entries = round_up(npfns / l1_entries, min_root_entries(cac));
+	cac->iova_base = ATU_VA_MASK(cass_iova_base(cac));
+	cac->iova_len = l0_entries * (u64)l1_entries * BIT(cac->page_shift);
+	cac->iova_base &= ~(cac->iova_len - 1);
+	cac->iova_end = cac->iova_base + cac->iova_len - 1;
+
+	pr_debug("ac:%d iova_base:%016llx iova_end:%016llx iova_len:%016llx\n",
+		 cac->ac.acid, cac->iova_base, cac->iova_end, cac->iova_len);
+
+	return l0_entries;
+}
+
+/**
+ * cass_nta_init() - Initialize an NTA Address Context
+ *
+ * @lni_priv: the Logical Network Interface
+ * @m_opts: Map options
+ * @cac:    Address Context
+ */
+int cass_nta_init(struct cxi_lni_priv *lni_priv, struct ac_map_opts *m_opts,
+		  struct cass_ac *cac)
+{
+	int ret;
+	ulong npfns;
+	int l0_entries;
+	int l1_entries;
+	int len_order;
+
+	l1_entries = BIT(cac->cfg_ac.pg_table_size);
+	npfns = m_opts->va_len >> m_opts->page_shift;
+	npfns = ALIGN(npfns, l1_entries);
+
+	/* Round up to the next power of 2 if not aligned. If the length
+	 * passed to init_iova_domain is not aligned to a power of 2, calling
+	 * iova_alloc_fast with a length that is larger than half of the
+	 * domain size can fail since the iova is aligned to the length.
+	 */
+	len_order = flsl(npfns);
+	if (npfns & MASK(len_order))
+		npfns = BIT(len_order + 1);
+
+	l0_entries = cass_ac_size(m_opts, cac, npfns, l1_entries);
+
+	ret = cass_nta_iova_init(cac, m_opts->va_len);
+	if (ret)
+		goto iova_init_fail;
+
+	m_opts->iova = cass_nta_iova_alloc(cac, m_opts);
+	if (!m_opts->iova) {
+		if (cac->iovad) {
+			pr_debug("cass_iova_alloc failed %lld\n", m_opts->iova);
+			ret = -ENOENT;
+			goto alloc_iova_fail;
+		}
+	}
+
+	cac->nta = cass_nta_alloc(cac, l0_entries, l1_entries);
+	if (IS_ERR(cac->nta)) {
+		ret = PTR_ERR(cac->nta);
+		goto iova_cleanup;
+	}
+
+	return 0;
+
+iova_cleanup:
+	if (cac->iovad)
+		FREE_IOVA_FAST(cac->iovad, m_opts->iova, m_opts->va_len);
+alloc_iova_fail:
+	cass_nta_iova_fini(cac);
+iova_init_fail:
+
+	return ret;
+}
+
+static void cass_l1_table_free(struct cass_dev *hw, struct cass_nta *nta,
+			       unsigned int l0_index)
+{
+	struct l1_entry *l1 = &nta->l1[l0_index];
+
+	dma_unmap_page(&hw->cdev.pdev->dev, l1->l1_pages_dma_addr,
+		       PAGE_SIZE << nta->l1_order, DMA_TO_DEVICE);
+	__free_pages(l1->l1_pages, nta->l1_order);
+	bitmap_free(l1->bitmap);
+
+	memset(l1, 0, sizeof(*l1));
+}
+
+/* Return the virtual address of a given PTE */
+static union a_pte *get_virt_pte(const struct cass_nta *nta, unsigned int l0_index,
+				 unsigned int l1_index)
+{
+	union a_pte *l1_array;
+
+	l1_array = page_address(nta->l1[l0_index].l1_pages);
+
+	return &l1_array[l1_index];
+}
+
+static void cass_pte_clear(struct cass_dev *hw, const struct cxi_md_priv *md_priv,
+			   unsigned int l0_index, unsigned int l1_index,
+			   bool unmap)
+{
+	struct cass_ac *cac = md_priv->cac;
+	struct cass_nta *nta = cac->nta;
+	union a_pte *pte = get_virt_pte(nta, l0_index, l1_index);
+	unsigned long *map;
+
+	if (pte && pte->pte.p) {
+		if (unmap)
+			dma_unmap_page(&hw->cdev.pdev->dev, PTE_ADDR(pte->pte),
+				       1 << cac->page_shift, DMA_BIDIRECTIONAL);
+		pte->qw = 0;
+	}
+
+	map = nta->l1[l0_index].bitmap;
+	if (map)
+		clear_bit(l1_index, map);
+}
+
+static void cass_clear_pde(struct cass_dev *hw, union a_pte *pde)
+{
+	pde->qw = 0;
+}
+
+void cass_l1_tables_free(struct cass_dev *hw, struct cass_nta *nta)
+{
+	int i;
+	union a_pte *pde;
+
+	for (i = 0; i < nta->l0_entries; i++) {
+		if (!nta->l1[i].bitmap)
+			continue;
+
+		pde = &nta->root_ptr[i];
+		if (!pde->qw) {
+			pr_warn("%d map entry but pde 0\n", i);
+			continue;
+		}
+
+		cass_l1_table_free(hw, nta, i);
+		cass_clear_pde(hw, pde);
+	}
+}
+
+static void cass_pg_tbl_indices(const struct cass_ac *cac, s64 iova_offset,
+				int *l0_index, int *l1_index)
+{
+	int pts = cac->cfg_ac.pg_table_size;
+	int l1_shift = cac->cfg_ac.base_pg_size + C_ADDR_SHIFT;
+	int l0_shift = l1_shift + pts;
+
+	*l0_index = iova_offset >> l0_shift;
+	*l1_index = (iova_offset >> l1_shift) & MASK(pts);
+}
+
+/**
+ * cass_clear_range() - clear a range of ptes and invalidate the ATU cache
+ *
+ * @md_priv: Private memory descriptor
+ * @iova: IO virtual address
+ * @len: IOVA range to clear
+ */
+void cass_clear_range(const struct cxi_md_priv *md_priv, u64 iova, u64 len)
+{
+	struct cass_dev *hw = container_of(md_priv->cac->lni_priv->dev,
+					   struct cass_dev, cdev);
+	int l0_index;
+	int l1_index;
+	struct cass_ac *cac = md_priv->cac;
+	int page_shift = cac->page_shift;
+	int entries = len >> page_shift;
+	s64 iova_offset = iova - cac->iova_base;
+	union a_pte *pde;
+	/* Only ODP needs to be unmapped here. Device and pinned memory will
+	 * be unmapped when the SG table is cleaned up.
+	 */
+	bool do_unmap = !md_priv->sgt;
+
+	if (!len)
+		return;
+
+	for (; entries > 0; iova_offset += BIT(page_shift), entries--) {
+		cass_pg_tbl_indices(cac, iova_offset, &l0_index, &l1_index);
+
+		pde = &cac->nta->root_ptr[l0_index];
+		if (!pde->qw)
+			continue;
+
+		if (!cac->cfg_ac.pg_table_size) {
+			/* single level table */
+			if (do_unmap)
+				dma_unmap_page(&hw->cdev.pdev->dev,
+					       PTE_ADDR(pde->pte),
+					       1 << cac->page_shift,
+					       DMA_BIDIRECTIONAL);
+			pde->qw = 0;
+		} else if (pde->pte.leaf) {
+			if (do_unmap)
+				dma_unmap_page(&hw->cdev.pdev->dev,
+					       PTE_ADDR(pde->pte),
+					       1 << cac->huge_shift,
+					       DMA_BIDIRECTIONAL);
+			cass_clear_pde(hw, pde);
+			/*
+			 * the rest of the entries for this pde don't need to
+			 * be checked
+			 */
+			entries -= ATU_PMD_NR(cac) - 1;
+			iova_offset += BIT(page_shift) * (ATU_PMD_NR(cac) - 1);
+		} else {
+			if (!cac->nta->l1[l0_index].bitmap)
+				pr_err("ac:%d iova:%llx offset:%llx map %d is NULL\n",
+				       cac->ac.acid, iova, iova_offset,
+				       l0_index);
+
+			cass_pte_clear(hw, md_priv, l0_index, l1_index,
+				       do_unmap);
+		}
+	}
+}
+
+/**
+ * cass_pte_build() - construct a page table entry based on the pfn and flags
+ *
+ * @hpfn: pfn from the CPU page table containing read and write permissions
+ * @pte: constructed page table entry
+ * @dma_addr: DMA address of the page frame number
+ * @leaf: indication of the final translation - l0 hugepage entry or l1 entry
+ * @flags: user requested read and write permissions
+ * @is_hmm_pfn: DMA address is from an hpfn - use the hpfn flags
+ * @l0_entry: indicates this is a root table entry
+ */
+static void cass_pte_build(u64 hpfn, union a_pte *pte, dma_addr_t dma_addr,
+			   bool leaf, u32 flags, bool is_hmm_pfn,
+			   bool l0_entry)
+{
+	/* Always set rd/wr permissions for a non-leaf root table entry
+	 * since the 2nd level could be either rd or wr and the NIC checks
+	 * both levels for proper permissions.
+	 */
+	bool rw = l0_entry && !leaf;
+	bool rd = rw || (flags & CXI_MAP_READ);
+	bool wr = rw || (flags & CXI_MAP_WRITE);
+	bool h_wr = rw || ATU_PFN_WRITE(hpfn);
+
+	pte->qw = dma_addr;
+	pte->pte.leaf = leaf;
+
+	if (is_hmm_pfn) {
+		if (ATU_PFN_INVALID(hpfn)) {
+			pte->qw = 0;
+			return;
+		}
+
+		pte->pte.r = rd;
+		pte->pte.w = h_wr && wr;
+		pte->pte.p = !leaf || ATU_PFN_VALID(hpfn);
+	} else {
+		/* TODO: check page attributes? */
+		pte->pte.r = rd;
+		pte->pte.w = wr;
+		pte->pte.p = 1;
+	}
+}
+
+/**
+ * cass_l1_table_empty - Free l1 map buffer if table is empty.
+ *
+ * @cac:   Address context
+ * @pde:   Page directory entry
+ * @index: L1 map to free and clean up
+ * @iova:  IO virtual address
+ */
+static int cass_l1_table_empty(const struct cass_ac *cac,
+			       union a_pte *pde, int index, u64 iova)
+{
+	struct cass_dev *hw = container_of(cac->lni_priv->dev,
+					   struct cass_dev, cdev);
+	struct cass_nta *nta = cac->nta;
+
+	if (!nta->l1[index].bitmap) {
+		pr_err("ac:%d iova:%llx map %d is NULL\n", cac->ac.acid,
+		       iova, index);
+		return -EINVAL;
+	}
+
+	if (!bitmap_empty(nta->l1[index].bitmap, nta->l1_entries)) {
+		pr_err("bitmap is not empty iova:%llx\n", iova);
+		return -EINVAL;
+	}
+
+	cass_l1_table_free(hw, nta, index);
+
+	return 0;
+}
+
+static int cass_l1_table_alloc(struct cass_dev *hw, struct cass_nta *nta,
+			       int l0_index)
+{
+	struct l1_entry *l1 = &nta->l1[l0_index];
+
+	l1->bitmap = bitmap_zalloc(nta->l1_entries, GFP_KERNEL);
+	if (!l1->bitmap)
+		return -ENOMEM;
+
+	l1->l1_pages = alloc_pages_node(nta->numa_node, GFP_KERNEL | __GFP_ZERO,
+					nta->l1_order);
+	if (!l1->l1_pages)
+		goto free_bitmap;
+
+	l1->l1_pages_dma_addr = dma_map_page(&hw->cdev.pdev->dev, l1->l1_pages,
+					     0, PAGE_SIZE << nta->l1_order,
+					     DMA_TO_DEVICE);
+	if (dma_mapping_error(&hw->cdev.pdev->dev, l1->l1_pages_dma_addr))
+		goto free_pages;
+
+	return 0;
+
+free_pages:
+	__free_pages(l1->l1_pages, nta->l1_order);
+free_bitmap:
+	bitmap_free(l1->bitmap);
+
+	memset(l1, 0, sizeof(*l1));
+
+	return -ENOMEM;
+}
+
+int cass_dma_addr_mirror(dma_addr_t dma_addr, u64 iova, struct cass_ac *cac,
+			 u32 flags, bool is_huge_page, bool *invalidate)
+{
+	int ret;
+	int l0_index;
+	int l1_index;
+	union a_pte *ppde;
+	union a_pte *ppte;
+	union a_pte pde = {};
+	union a_pte pte = {};
+	bool update_pde = false;
+	s64 iova_offset = iova - cac->iova_base;
+	bool ptg_mode_sgl = !cac->cfg_ac.pg_table_size;
+	struct cass_dev *hw = container_of(cac->lni_priv->dev, struct cass_dev,
+					   cdev);
+
+	if (iova_offset > cac->iova_len) {
+		pr_warn("iova_offset:0x%llx > iova_len:0x%llx iova:%llx iova_base:%llx\n",
+			iova_offset, cac->iova_len, iova, cac->iova_base);
+		return -EINVAL;
+	}
+
+	cass_pg_tbl_indices(cac, iova_offset, &l0_index, &l1_index);
+	ppde = &cac->nta->root_ptr[l0_index];
+
+	if (is_huge_page && ppde->qw) {
+		if (l1_index) {
+			pr_err("Huge page not aligned iova:%llx\n", iova);
+			return -EINVAL;
+		}
+
+		/* Replacing a non-leaf entry with a leaf entry. */
+		/* TODO: check if this is still necessary */
+		if (!ppde->pte.leaf) {
+			ret = cass_l1_table_empty(cac, ppde, l0_index,
+						  iova_offset);
+			if (ret)
+				return ret;
+
+			pr_debug("Replacing non-leaf pde iova:%llx entry:%lx\n",
+				 iova_offset, (ulong)PTE_ADDR(ppde->pte));
+			update_pde = true;
+			goto new_pde;
+		}
+
+		/* It is possible to get an ODP page request for the same
+		 * IOVA since we try to fill more than one entry at a time.
+		 */
+		cass_pte_build(0, &pde, dma_addr, true, flags, false, true);
+
+		if (pde.qw != ppde->qw) {
+			pr_err("Overlapping huge page ac:%d iova:%llx\n",
+			       cac->ac.acid, iova_offset);
+			return -EINVAL;
+		}
+
+		return 0;
+	}
+
+new_pde:
+	if (!ppde->qw || update_pde) {
+		if (is_huge_page || ptg_mode_sgl) {
+			cass_pte_build(0, &pde, dma_addr, true, flags, false,
+				       true);
+		} else {
+			if (update_pde) {
+				pr_err("Expected hugepage update iova:%llx l0_index:%d l1_index:%d\n",
+				       iova_offset, l0_index, l1_index);
+				return -EINVAL;
+			}
+
+			ret = cass_l1_table_alloc(hw, cac->nta, l0_index);
+			if (ret) {
+				pr_err("Error allocating l1 table\n");
+				return ret;
+			}
+
+			cass_pte_build(0, &pde,
+				       cac->nta->l1[l0_index].l1_pages_dma_addr,
+				       false, flags, false, true);
+		}
+
+		atu_debug("pde iova:%llx dma_addr:0x%llx entry:%llx\n",
+			  iova, dma_addr, pde.qw);
+		ppde->qw = pde.qw;
+
+		if (update_pde)
+			cass_invalidate_range(cac, cac->iova_base + iova_offset,
+					      BIT(cac->huge_shift));
+
+		if (is_huge_page || ptg_mode_sgl)
+			return 0;
+	} else if (ppde->pte.leaf) {
+		pr_err("Unexpected leaf iova:%llx pde %llx, l0_index:%d l1_index:%d\n",
+		       iova_offset, ppde->qw, l0_index, l1_index);
+
+		return -EINVAL;
+	}
+
+	/* fill in the l1 table entry */
+	cass_pte_build(0, &pte, dma_addr, true, flags, false, false);
+	ppte = get_virt_pte(cac->nta, l0_index, l1_index);
+
+	atu_debug("pte %p phys:%lx iova:%llx entry:0x%llx\n", ppte,
+		  (ulong)PTE_ADDR(pte.pte) + l1_index * ATU_PTE_ENTRY_SIZE,
+		  iova, pte.qw);
+
+	ppte->qw = pte.qw;
+	set_bit(l1_index, cac->nta->l1[l0_index].bitmap);
+
+	return 0;
+}
+
+/**
+ * cass_pfns_mirror() - Mirror PTEs from a list of HMM pfns
+ *
+ * @md_priv: Private memory descriptor
+ * @m_opts: map options
+ * @pfns: pfns to mirror
+ * @npfns: number of pfns to mirror
+ * @is_huge_page: The vma is covered by a hugepage. For device memory,
+ *                indicates that the pfns are contiguous.
+ *
+ * Return: 0 on success or negative error value
+ */
+int cass_pfns_mirror(struct cxi_md_priv *md_priv, const struct ac_map_opts *m_opts,
+		     u64 *pfns, int npfns, bool is_huge_page)
+{
+	int ret;
+	int i;
+	size_t size;
+	bool inval = false;
+	int invalidate = 0;
+	struct page *page;
+	dma_addr_t dma_addr;
+	u64 iova = m_opts->iova;
+	struct cass_ac *cac = md_priv->cac;
+	size_t page_size = BIT(cac->page_shift);
+
+	for (i = 0; i < npfns;) {
+		/* Skip pfns that are invalid which may happen during
+		 * prefetch.
+		 */
+		if (!ATU_PFN_VALID(pfns[i])) {
+			i += ATU_PTE_NR(cac);
+			iova += page_size;
+			continue;
+		}
+
+		page = hmm_pfn_to_page(pfns[i]);
+
+		/* Check if there are enough remaining pfns to cover an L0
+		 * entry.
+		 */
+		if ((npfns - i) < K_PMD_NR(cac))
+			is_huge_page = false;
+
+		if (is_huge_page &&
+		    ((iova & MASK(cac->huge_shift)) || !PageHuge(page)))
+			is_huge_page = false;
+
+		size = is_huge_page ? BIT(cac->huge_shift) : page_size;
+		dma_addr = dma_map_page(md_priv->device, page, 0, size,
+					DMA_BIDIRECTIONAL);
+		if (dma_mapping_error(md_priv->device, dma_addr)) {
+			ret = -EINVAL;
+			goto mirror_error;
+		}
+
+		ret = cass_dma_addr_mirror(dma_addr, iova, cac, md_priv->flags,
+					   is_huge_page, &inval);
+		if (ret)
+			goto mirror_error;
+
+		i += KPFN_INC(cac, is_huge_page);
+		invalidate += inval;
+		iova += size;
+	}
+
+mirror_error:
+	if (i < npfns) {
+		pr_err("Error populating %d PTEs at index %d\n", npfns, i);
+
+		/* Clean up previously populated ptes. */
+		cass_clear_range(md_priv, m_opts->iova, i * page_size);
+	}
+
+	/* If any PTEs are replaced they will need to be invalidated.
+	 * Invalidate the whole range.
+	 */
+	if (invalidate)
+		cass_invalidate_range(cac, m_opts->iova, npfns * page_size);
+
+	return ret;
+}
+
+static struct page *cass_virt_to_page(u64 addr)
+{
+	if (is_vmalloc_addr((void *)addr))
+		return vmalloc_to_page((void *)addr);
+	else
+		return virt_to_page(addr);
+}
+
+static bool cass_error_inject(const struct cxi_lni_priv *lni_priv)
+{
+	struct cass_dev *hw =
+		container_of(lni_priv->dev, struct cass_dev, cdev);
+
+	/* decrement if not 0 */
+	atomic_add_unless(&hw->atu_error_inject, -1, 0);
+
+	if (atomic_read(&hw->atu_error_inject) == 1)
+		return true;
+
+	return false;
+}
+
+/**
+ * cass_pin() - Call pin_user_pages() to pin an address range
+ *
+ * @cac:     Address Context metadata
+ * @pages:   Array of pages returned. Only used if there is an error.
+ * @npages:  Number of pages to pin
+ * @addr:    Virtual address
+ * @write:   Write permission
+ *
+ * Return: Success or -EFAULT or return value of gup
+ */
+int cass_pin(const struct cass_ac *cac, struct page **pages, int npages,
+	     u64 addr, bool write)
+{
+	int i;
+	int gotn;
+	unsigned int gup_flags = FOLL_LONGTERM | (write ? FOLL_WRITE : 0);
+
+	gotn = pin_user_pages_fast(addr, npages, gup_flags, pages);
+	if (gotn < 0)
+		return gotn;
+
+	if ((gotn != npages) || cass_error_inject(cac->lni_priv)) {
+		pr_debug("gup failed gotn %d of %d\n", gotn, npages);
+
+		for (i = 0; i < gotn; i++)
+			unpin_user_page(pages[i]);
+
+		return -EFAULT;
+	}
+
+	return 0;
+}
+
+/**
+ * cass_mirror_hp() - Mirror simulated hugepages from a large hugepage
+ *
+ * Support testing of arbitrary hugepage sizes.
+ * These pages do not have a notifier callback.
+ * The pinned pages are contiguous pages masquerading as a larger page size.
+ *
+ * @m_opts: map options
+ * @md_priv: Private memory descriptor
+ *
+ * Return: number of mirrored pages or error
+ */
+int cass_mirror_hp(const struct ac_map_opts *m_opts, struct cxi_md_priv *md_priv)
+{
+	int i;
+	int ret = 0;
+	int l0_index;
+	int l1_index;
+	dma_addr_t dma_addr;
+	union a_pte *ppde;
+	union a_pte pde = {};
+	struct page *page;
+	u64 iova = m_opts->iova;
+	struct cass_ac *cac = md_priv->cac;
+	uintptr_t addr = m_opts->va_start;
+	int n_mir = 1 + ((m_opts->va_len - 1) >> cac->huge_shift);
+
+	mutex_lock(&cac->ac_mutex);
+
+	for (i = 0; i < n_mir; i++) {
+		ret = cass_pin(cac, &page, 1, addr, true);
+		if (ret)
+			break;
+
+		unpin_user_page(page);
+
+		dma_addr = dma_map_page(md_priv->device, page, 0,
+					1 << cac->huge_shift,
+					DMA_BIDIRECTIONAL);
+		if (dma_mapping_error(md_priv->device, dma_addr)) {
+			ret = -ENOMEM;
+			break;
+		}
+
+		cass_pg_tbl_indices(cac, iova - cac->iova_base, &l0_index,
+				    &l1_index);
+		ppde = &cac->nta->root_ptr[l0_index];
+		cass_pte_build(0, &pde, dma_addr, true, m_opts->flags, false,
+			       true);
+
+		atu_debug("pde dma_addr:0x%llx entry:%llx\n", dma_addr, pde.qw);
+		ppde->qw = pde.qw;
+
+		iova += BIT(cac->huge_shift);
+		addr += BIT(cac->huge_shift);
+	}
+
+	if (ret) {
+		pr_debug("ret:%d\n", ret);
+		cass_clear_range(md_priv, m_opts->iova, i << cac->huge_shift);
+	}
+
+	mutex_unlock(&cac->ac_mutex);
+
+	return ret;
+}
+
+/**
+ * cass_mirror_device() - Mirror a GPU device memory address range into
+ *                        device page tables
+ *
+ * @md_priv: Private memory descriptor
+ * @m_opts:  User options containing the IOVA range
+ *
+ * Return: 0 on success, -ENOENT if not GPU memory or error
+ */
+int cass_mirror_device(struct cxi_md_priv *md_priv,
+		       const struct ac_map_opts *m_opts)
+{
+	int i;
+	int j = 0;
+	int ret;
+	bool inval;
+	struct scatterlist *sg;
+	u64 iova = md_priv->md.iova;
+	struct cass_ac *cac = md_priv->cac;
+	size_t plen = BIT(cac->page_shift);
+	size_t hlen = BIT(cac->huge_shift);
+
+	mutex_lock(&md_priv->cac->ac_mutex);
+
+	i = 0;
+	for_each_sgtable_dma_sg(md_priv->sgt, sg, j) {
+		long len = sg_dma_len(sg);
+		dma_addr_t dma_addr = sg_dma_address(sg);
+
+		atu_debug("dma_addr:%llx len:%lx\n", dma_addr, len);
+
+		while (len > 0) {
+			bool is_hp = ffsl(dma_addr) >= cac->huge_shift &&
+					ffsl(iova) >= cac->huge_shift &&
+					len >= hlen;
+			size_t inc = is_hp ? hlen : plen;
+
+			atu_debug("iova:%llx dma_addr:%llx inc:%lx\n",
+				  iova, dma_addr, inc);
+			ret = cass_dma_addr_mirror(dma_addr, iova, cac,
+						   md_priv->flags,
+						   is_hp, &inval);
+			if (ret)
+				goto mirror_error;
+
+			iova += inc;
+			dma_addr += inc;
+			len -= inc;
+			i += KPFN_INC(cac, is_hp);
+		}
+	}
+
+	mutex_unlock(&md_priv->cac->ac_mutex);
+
+	return 0;
+
+mirror_error:
+	if (i) {
+		pr_err("Error populating length 0x%lx at index %d\n",
+		       md_priv->md.len, i);
+
+		/* Clean up previously populated ptes. */
+		cass_clear_range(md_priv, md_priv->md.iova, md_priv->md.len);
+	}
+
+	mutex_unlock(&md_priv->cac->ac_mutex);
+
+	return ret;
+}
+
+/**
+ * cass_mirror_odp() - Mirror a virtual address range into device page tables
+ *
+ * @m_opts:  User options containing the IOVA range
+ * @cac:     Address Context
+ * @npfns:   Number of pages
+ * @addr:    Virtual address
+ *
+ * @return: 0 on success or negative error value
+ */
+int cass_mirror_odp(const struct ac_map_opts *m_opts, struct cass_ac *cac,
+		    int npfns, u64 addr)
+{
+	int ret;
+	u64 *pfns;
+
+	pfns = kcalloc(npfns, sizeof(*pfns), GFP_KERNEL);
+	if (!pfns)
+		return -ENOMEM;
+
+	ret = cass_mirror_fault(m_opts, pfns, npfns, addr, m_opts->va_len);
+
+	kfree(pfns);
+
+	return ret;
+}
+
+static int cass_dma_map_pages(struct cxi_md_priv *md_priv,
+			      struct page **pages, int npages, bool is_huge_page)
+{
+	int ret;
+	struct sg_table *sgt;
+
+	sgt = kzalloc(sizeof(*sgt), GFP_KERNEL);
+	if (!sgt)
+		return -ENOMEM;
+
+	ret = sg_alloc_table_from_pages_segment(sgt, pages, npages,
+						0, md_priv->md.len, UINT_MAX, GFP_KERNEL);
+	if (ret)
+		goto sg_table_error;
+
+	ret = dma_map_sgtable(md_priv->device, sgt, DMA_BIDIRECTIONAL, 0);
+	if (ret)
+		goto dma_map_error;
+
+	md_priv->sgt = sgt;
+
+	return 0;
+
+dma_map_error:
+	sg_free_table(sgt);
+sg_table_error:
+	kfree(sgt);
+
+	return ret;
+}
+
+void cass_dma_unmap_pages(struct cxi_md_priv *md_priv)
+{
+	if (!md_priv->sgt)
+		return;
+
+	if (md_priv->external_sgt_owner)
+		return;
+
+	dma_unmap_sgtable(md_priv->device, md_priv->sgt, DMA_BIDIRECTIONAL, 0);
+	sg_free_table(md_priv->sgt);
+	kfree(md_priv->sgt);
+	md_priv->sgt = NULL;
+}
+
+/**
+ * cass_pin_mirror() - Pin and mirror a virtual address range into device
+ *                     page tables
+ *
+ * @m_opts:  User options containing the IOVA range
+ * @md_priv: Private memory descriptor
+ *
+ * Return: 0 on success or error
+ */
+int cass_pin_mirror(struct cxi_md_priv *md_priv, struct ac_map_opts *m_opts)
+{
+	int i;
+	int ret;
+	int addr_inc;
+	bool inval = false;
+	int invalidate = 0;
+	bool is_huge_page;
+	u64 iova = m_opts->iova;
+	struct page **pages = NULL;
+	struct cass_ac *cac = md_priv->cac;
+	uintptr_t addr = m_opts->va_start;
+	uintptr_t end = m_opts->va_end;
+	int hlen = BIT(m_opts->huge_shift);
+	int plen = BIT(m_opts->page_shift);
+	u64 hmask = hlen - 1;
+	size_t md_len = m_opts->va_len;
+	int npages = m_opts->va_len >> PAGE_SHIFT;
+	struct scatterlist *sg;
+
+	pages = kvmalloc_array(npages, sizeof(pages), GFP_KERNEL);
+	if (!pages)
+		return -ENOMEM;
+
+	mmap_read_lock(current->mm);
+	ret = cass_vma_write_flag(current->mm, addr, end, m_opts->flags);
+	mmap_read_unlock(current->mm);
+
+	if (ret < 0)
+		goto err;
+
+	ret = cass_pin(cac, pages, npages, m_opts->va_start, ret);
+	if (ret < 0)
+		goto err;
+
+	ret = cass_dma_map_pages(md_priv, pages, npages, m_opts->is_huge_page);
+	if (ret)
+		goto map_err;
+
+	mutex_lock(&cac->ac_mutex);
+
+	for_each_sgtable_dma_sg(md_priv->sgt, sg, i) {
+		size_t len = sg_dma_len(sg);
+		dma_addr_t dma_addr = sg_dma_address(sg);
+
+		while (len > 0 && md_len > 0) {
+			is_huge_page = m_opts->is_huge_page && (len >= hlen) &&
+						!(iova & hmask);
+			addr_inc = is_huge_page ? hlen : plen;
+
+			ret = cass_dma_addr_mirror(dma_addr, iova, cac,
+						   m_opts->flags,
+						   is_huge_page, &inval);
+			if (ret) {
+				pr_err("Error populating %d PTEs at index %d iova:%llx inc:%x\n",
+				       npages, i, iova, addr_inc);
+				goto mirror_error;
+			}
+
+			dma_addr += addr_inc;
+			iova += addr_inc;
+			len -= addr_inc;
+			md_len -= addr_inc;
+			invalidate += inval;
+		}
+
+		if (md_len <= 0)
+			break;
+	}
+
+	mutex_unlock(&cac->ac_mutex);
+
+	if (invalidate)
+		cass_invalidate_range(cac, m_opts->iova, plen * i);
+
+	md_priv->pages = pages;
+
+	return 0;
+
+mirror_error:
+	cass_clear_range(md_priv, m_opts->iova, plen * i);
+	mutex_unlock(&cac->ac_mutex);
+	cass_dma_unmap_pages(md_priv);
+
+map_err:
+	unpin_user_pages(pages, npages);
+
+err:
+	kvfree(pages);
+
+	return ret;
+}
+
+static int atu_odpq_space(struct cass_dev *hw)
+{
+	union c_atu_sts_odpq sts_odpq;
+
+	cass_read(hw, C_ATU_STS_ODPQ, &sts_odpq, sizeof(sts_odpq));
+
+	return sts_odpq.odpq_space;
+}
+
+static int cass_odpq_space(struct cass_dev *hw)
+{
+	int ret;
+	int space;
+
+	ret = readx_poll_timeout(atu_odpq_space, hw, space, (space > 0), 1,
+				 ATU_ODPQ_SPACE_TIMEOUT);
+	if (ret) {
+		pr_err("Timed out waiting for ODPQ space\n");
+		return ret;
+	}
+
+	return space;
+}
+
+/**
+ * cass_odpq_write() - Write the result of a page request
+ *
+ * Also used to clear out expired page requests.
+ * The queue is 8 deep and we just write one entry at
+ * a time so it should never overflow.
+ *
+ * @hw:     the device
+ * @index:  PRB entry
+ * @status: C_ATU_ODP_FAILURE or C_ATU_ODP_SUCCESS
+ */
+static void cass_odpq_write(struct cass_dev *hw, int index,
+			    enum c_odp_status status)
+{
+	int space;
+	union c_atu_cfg_odpq odpq = {
+		.status = status,
+		.prb_index = index
+	};
+
+	mutex_lock(&hw->odpq_mutex);
+
+	space = cass_odpq_space(hw);
+	if (space <= 0)
+		pr_err("Timed out waiting for ODPQ\n");
+	else
+		cass_write(hw, C_ATU_CFG_ODPQ, &odpq, sizeof(odpq));
+
+	mutex_unlock(&hw->odpq_mutex);
+}
+
+/**
+ * cass_prb_worker() - Clean up expired PRB entries
+ *
+ * Scan the PRB table and look for expired entries and report entry as
+ * failed. Keep scanning until there are no more entries.
+ *
+ * @work: the work_struct
+ */
+static void cass_prb_worker(struct work_struct *work)
+{
+	int i;
+	bool scan_again;
+	union c_atu_sts_prb_table entry;
+	struct cass_dev *hw = container_of(work, struct cass_dev, prb_work);
+
+	do {
+		scan_again = false;
+
+		for (i = 0; i < C_ATU_STS_PRB_TABLE_ENTRIES; i++) {
+			cass_read(hw, C_ATU_STS_PRB_TABLE(i), &entry,
+				  sizeof(entry));
+
+			if (entry.valid && entry.expired) {
+				pr_warn("Entry %d expired ac:%d addr:%lx\n",
+					i, entry.acid,
+					(ulong)entry.addr << PAGE_SHIFT);
+				scan_again = true;
+				cass_odpq_write(hw, i, C_ATU_ODP_FAILURE);
+				atomic_inc(&hw->atu_prb_expired);
+			}
+		}
+	} while (scan_again);
+}
+
+static void add_md_time_to_bin(struct cass_dev *hw, ktime_t time)
+{
+	int i;
+	int bin = FIRST_MDBIN;
+
+	if (ktime_compare(hw->pri_max_md_time, time) < 0)
+		hw->pri_max_md_time = time;
+
+	for (i = 0; i < MDBINS; i++, bin <<= 1) {
+		if (time < bin) {
+			hw->pri_md_time[i]++;
+			break;
+		}
+	}
+}
+
+static void add_fault_time_to_bin(struct cass_dev *hw, ktime_t time)
+{
+	int i;
+	int bin = FIRST_FBIN;
+
+	if (ktime_compare(hw->pri_max_fault_time, time) < 0)
+		hw->pri_max_fault_time = time;
+
+	for (i = 0; i < FBINS; i++, bin <<= 1) {
+		if (time < bin) {
+			hw->pri_fault_time[i]++;
+			break;
+		}
+	}
+}
+
+/**
+ * cass_pri_fault() - Respond to a NIC PRI page request
+ *
+ * The page request interface consists of a buffer of 512
+ * page request entries containing an AC, index and iova.
+ * Fault in the page requested, clear the request in the
+ * buffer and write a response to the ODP queue.
+ * The page request interface can only request one page
+ * at a time.
+ *
+ * @hw:  the device
+ * @pre: page request entry
+ */
+static void cass_pri_fault(struct cass_dev *hw,
+			   struct c_page_request_entry *pre)
+{
+	int rc = -1;
+	u64 iova = 0;
+	u64 addr = 0;
+	int npages;
+	int align_shift;
+	int index = pre->index;
+	struct cass_ac *cac;
+	struct cxi_md_priv *e = NULL;
+	struct ac_map_opts m_opts = {};
+	union c_atu_sts_prb_table entry;
+	enum c_odp_status status = C_ATU_ODP_FAILURE;
+	ktime_t fault_time;
+	ktime_t fault_start;
+	ktime_t get_md_time;
+	ktime_t start = ktime_get_raw();
+
+	cac = cass_cac_get(hw, pre->acid);
+	if (!cac)
+		goto no_cac;
+
+	iova = (u64)pre->addr << C_ADDR_SHIFT;
+
+	if (!(cac->flags & CXI_MAP_USER_ADDR)) {
+		pr_err("Kern iova:%llx page not present\n", iova);
+		goto no_cac;
+	}
+
+	mutex_lock(&cac->md_mutex);
+	list_for_each_entry(e, &cac->md_list, md_entry) {
+		u64 md_end = e->md.iova + e->md.len;
+
+		if ((e->md.iova <= iova) && (iova < md_end)) {
+			addr = e->md.va + (iova - e->md.iova);
+			m_opts.flags = e->flags;
+			break;
+		}
+	}
+
+	fault_start = ktime_get_raw();
+	get_md_time = fault_start - start;
+	add_md_time_to_bin(hw, get_md_time);
+
+	if (!addr)
+		goto no_md;
+
+	align_shift = pri_shift;
+	m_opts.page_shift = cac->page_shift;
+	m_opts.va_end = addr + PAGE_SIZE;
+	rc = cass_cpu_page_size(hw, &m_opts, e->mn_sub.mm, addr, NULL,
+				&align_shift);
+	if (rc)
+		goto no_md;
+
+	/* There may be vmas with larger hugepage sizes than the AC
+	 * is configured with. Use the smaller of AC configured
+	 * hugepage size or vma hugepage size (if present).
+	 */
+	align_shift = min_t(int, align_shift, cac->huge_shift);
+
+	/* Align the m_opts.va_* to align_shift */
+	cass_align_start_len(&m_opts, addr, PAGE_SIZE, align_shift);
+	/* Bound the m_opts.va_* to the MD */
+	m_opts.va_start = max_t(u64, m_opts.va_start, e->md.va);
+	m_opts.va_end = min_t(u64, m_opts.va_end, e->md.va + e->md.len);
+	m_opts.va_len = m_opts.va_end - m_opts.va_start;
+	/* Adjust iova to match va_start offset from addr */
+	m_opts.iova = iova - (addr - m_opts.va_start);
+	m_opts.md_priv = e;
+	m_opts.flags |= CXI_MAP_FAULT;
+
+	atu_debug("req_iova:%llx addr:%llx md:%d md.va:%llx iova:%llx start:%llx end:%llx va_len:%lx\n",
+		  iova, addr, e->md.id, e->md.va, m_opts.iova, m_opts.va_start,
+		  m_opts.va_end, m_opts.va_len);
+
+	npages = m_opts.va_len >> cac->page_shift;
+	rc = cass_mirror_odp(&m_opts, cac, npages, m_opts.va_start);
+	if (rc >= 0)
+		status = C_ATU_ODP_SUCCESS;
+	else {
+		atomic_inc(&hw->atu_odp_fails);
+		cass_read(hw, C_ATU_STS_PRB_TABLE(index), &entry,
+			  sizeof(entry));
+		pr_warn("ODP failure rc:%d PRT:ac:%d iova:%llx mdva:%llx SPRBT:i:%d v:%d e:%d ac:%d client:%d addr:%lx w:%d r:%d\n",
+			rc, pre->acid, iova, e->md.va,
+			index, entry.valid, entry.expired, entry.acid,
+			entry.client, (ulong)entry.addr << PAGE_SHIFT,
+			entry.w, entry.r);
+	}
+
+	fault_time = ktime_get_raw() - fault_start;
+	add_fault_time_to_bin(hw, fault_time);
+
+no_md:
+	mutex_unlock(&cac->md_mutex);
+no_cac:
+	atu_debug("sts:%s rc:%d ac:%d index:%d iova:%llx md.va:%llx\n",
+		  status ? "f" : "s", rc, pre->acid, index, iova, e ? e->md.va : 0);
+
+	*(u64 *)pre = 0;
+	/* make sure entry is zeroed before reporting to hw */
+	wmb();
+	atomic_inc(&hw->atu_odp_requests);
+	cass_odpq_write(hw, index, status);
+	cass_cac_put(cac);
+}
+
+static void cass_pri_worker(struct work_struct *work)
+{
+	struct c_page_request_entry *pre;
+	struct cass_dev *hw = container_of(work, struct cass_dev, pri_work);
+	int rd_ptr = hw->pri_rd_ptr;
+
+	while (1) {
+		pre = &hw->page_request_table[rd_ptr];
+
+		if (!pre->acid)
+			break;
+
+		cass_pri_fault(hw, pre);
+		rd_ptr = (rd_ptr + 1) % C_ATU_PRB_ENTRIES;
+	}
+
+	hw->pri_rd_ptr = rd_ptr;
+}
+
+static irqreturn_t cass_pri_int_cb(int irq, void *context)
+{
+	struct cass_dev *hw = context;
+
+	queue_work(hw->pri_wq, &hw->pri_work);
+
+	return IRQ_HANDLED;
+}
+
+int cass_nta_mirror_sgt(struct cxi_md_priv *md_priv, bool need_lock)
+{
+	int i;
+	int j = 0;
+	int ret;
+	bool inval;
+	struct scatterlist *sg;
+	u64 iova = md_priv->md.iova;
+	struct cass_ac *cac = md_priv->cac;
+
+	cass_cond_lock(&cac->ac_mutex, need_lock);
+
+	for_each_sgtable_dma_sg(md_priv->sgt, sg, i) {
+		dma_addr_t dma_addr = sg_dma_address(sg) & PAGE_MASK;
+		long len = sg_dma_len(sg) + (sg_dma_address(sg) % PAGE_SIZE);
+
+		atu_debug("dma_addr:%llx len:%lx\n", dma_addr, len);
+
+		while (len > 0) {
+			ret = cass_dma_addr_mirror(dma_addr, iova, cac,
+						   md_priv->flags, false,
+						   &inval);
+			if (ret)
+				goto mirror_error;
+
+			dma_addr += PAGE_SIZE;
+			iova += PAGE_SIZE;
+			len -= PAGE_SIZE;
+			j++;
+		}
+	}
+
+	cass_cond_unlock(&cac->ac_mutex, need_lock);
+
+	return 0;
+
+mirror_error:
+	cass_clear_range(md_priv, md_priv->md.iova, j * PAGE_SIZE);
+	cass_cond_unlock(&cac->ac_mutex, need_lock);
+
+	return ret;
+}
+
+int cass_nta_mirror_kern(struct cxi_md_priv *md_priv,
+			 const struct iov_iter *iter, bool need_lock)
+{
+	int i;
+	int j;
+	int ret;
+	int alen;
+	struct page *page;
+	struct sg_table *sgt;
+	struct scatterlist *sg;
+	u64 iova = md_priv->md.iova;
+	uintptr_t addr = md_priv->md.va;
+	int npages = md_priv->md.len >> PAGE_SHIFT;
+
+	sgt = kmalloc(sizeof(struct sg_table), GFP_KERNEL);
+	if (!sgt)
+		return -ENOMEM;
+
+	ret = sg_alloc_table(sgt, npages, GFP_KERNEL);
+	if (ret)
+		goto sg_alloc_error;
+
+	pr_debug("va:%lx iova:%llx len:%lx\n", addr, iova, md_priv->md.len);
+
+	sg = sgt->sgl;
+	if (iter == NULL) {
+		for (i = 0; i < npages; i++) {
+			if (!sg) {
+				pr_info("sg is null at %d\n", i);
+				goto dma_map_error;
+			}
+			page = cass_virt_to_page(addr + (i * PAGE_SIZE));
+			sg_set_page(sg, page, PAGE_SIZE, 0);
+			sg = sg_next(sg);
+		}
+	} else if (iov_iter_is_bvec(iter)) {
+		const struct bio_vec *bvec = iter->bvec;
+
+		for (i = 0; i < npages; i++) {
+			sg_set_page(sg, bvec->bv_page, PAGE_SIZE, 0);
+			sg = sg_next(sg);
+			bvec++;
+		}
+	} else if (iov_iter_is_kvec(iter)) {
+		int ipages;
+		const struct kvec *kvec = iter->kvec;
+
+		for (i = 0; i < npages;) {
+			alen = PAGE_ALIGN(kvec->iov_len);
+			ipages = alen >> PAGE_SHIFT;
+
+			for (j = 0; j < ipages; j++) {
+				page = cass_virt_to_page((u64)kvec->iov_base +
+								j * PAGE_SIZE);
+				sg_set_page(sg, page, PAGE_SIZE, 0);
+				sg = sg_next(sg);
+				i++;
+			}
+
+			kvec++;
+		}
+	}
+
+	ret = dma_map_sgtable(md_priv->device, sgt, DMA_BIDIRECTIONAL, 0);
+	if (ret)
+		goto dma_map_error;
+
+	md_priv->sgt = sgt;
+
+	ret = cass_nta_mirror_sgt(md_priv, need_lock);
+	if (ret)
+		goto mirror_error;
+
+	md_priv->need_lock = false;
+
+	return 0;
+
+mirror_error:
+	dma_unmap_sgtable(md_priv->device, sgt, DMA_BIDIRECTIONAL, 0);
+
+dma_map_error:
+	sg_free_table(sgt);
+
+sg_alloc_error:
+	kfree(sgt);
+
+	return ret;
+}
diff --git a/drivers/net/ethernet/hpe/ss1/cass_p2p.c b/drivers/net/ethernet/hpe/ss1/cass_p2p.c
new file mode 100644
index 000000000000..02845ff7649a
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_p2p.c
@@ -0,0 +1,321 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2020-2021 Hewlett Packard Enterprise Development LP */
+
+/* GPU direct (P2P) interface */
+
+#include "cass_core.h"
+
+static bool device_hugepage_enable = true;
+module_param(device_hugepage_enable, bool, 0644);
+MODULE_PARM_DESC(device_hugepage_enable, "Enable device hugepages");
+
+#define DEVICE_HS_ARRAY_SIZE 2
+static int device_hs_array_n = DEVICE_HS_ARRAY_SIZE;
+/* Default to 2MB and 64M. */
+static int device_hs_array[DEVICE_HS_ARRAY_SIZE] = {21, 26};
+
+#define MIN_DEVICE_HP_SHIFT (MIN_DEVICE_PG_TABLE_SIZE + PAGE_SHIFT)
+#define MAX_DEVICE_HP_SHIFT (MIN_DEVICE_HP_SHIFT + MAX_PG_TABLE_SIZE)
+#define DEVICE_HS_ARRAY_BUFFER_SIZE (DEVICE_HS_ARRAY_SIZE * 3)
+
+static int device_hs_array_get(char *buffer, const struct kernel_param *kp)
+{
+	return param_array_ops.get(buffer, kp);
+}
+
+static int device_hs_array_set(const char *val, const struct kernel_param *kp)
+{
+	int i;
+	int ret;
+	int prev = 0;
+	char buf[DEVICE_HS_ARRAY_BUFFER_SIZE];
+
+	/* save the current list in case there is an invalid value */
+	ret = device_hs_array_get(buf, kp);
+	if (ret < 0)
+		return ret;
+
+	/* set to the new value */
+	ret = param_array_ops.set(val, kp);
+	if (ret)
+		return ret;
+
+	/* check for out of range and that they are ascending in value */
+	for (i = 0; i < device_hs_array_n; i++) {
+		if (device_hs_array[i] < MIN_DEVICE_HP_SHIFT ||
+		    device_hs_array[i] > MAX_DEVICE_HP_SHIFT) {
+			pr_info("Value (%d) out of range of %d-%d\n",
+				device_hs_array[i], MIN_DEVICE_HP_SHIFT,
+				MAX_DEVICE_HP_SHIFT);
+			goto invalid;
+		}
+
+		if (device_hs_array[i] < prev) {
+			pr_info("Values should be ascending\n");
+			goto invalid;
+		}
+
+		prev = device_hs_array[i];
+	}
+
+	return 0;
+invalid:
+	/* restore previous values */
+	param_array_ops.set(buf, kp);
+	return -EINVAL;
+}
+
+static const struct kernel_param_ops device_hs_array_ops = {
+	.set = device_hs_array_set,
+	.get = device_hs_array_get,
+};
+
+/* Modified version of module_param_array_named to include the ops */
+#define module_param_array_named_cb(name, array, type, _ops, nump, perm) \
+	param_check_##type(name, &(array)[0]);				\
+	static const struct kparam_array __param_arr_##name		\
+	= { .max = ARRAY_SIZE(array), .num = nump,			\
+	    .ops = &param_ops_##type,					\
+	    .elemsize = sizeof(array[0]), .elem = array };		\
+	__module_param_call(MODULE_PARAM_PREFIX, name, &_ops,		\
+			    .arr = &__param_arr_##name, perm, -1, 0);	\
+	__MODULE_PARM_TYPE(name, "array of " #type)
+
+module_param_array_named_cb(device_hs_array, device_hs_array, int,
+			    device_hs_array_ops, &device_hs_array_n, 0644);
+MODULE_PARM_DESC(device_hs_array, "Array of allowed hugeshift values");
+
+enum cxi_p2p_type {
+	CXI_P2P_AMD_GPU = 1,
+	CXI_P2P_NVIDIA_GPU,
+};
+
+static enum cxi_p2p_type cxi_supported_p2p_type;
+static DEFINE_MUTEX(p2p_init_lock);
+
+/**
+ * cxi_p2p_init - Discover a GPU direct interface and initialize it.
+ */
+static int cxi_p2p_init(void)
+{
+	int ret = 0;
+
+	if (cxi_supported_p2p_type > 0)
+		return 0;
+
+	mutex_lock(&p2p_init_lock);
+
+	if (cxi_supported_p2p_type > 0)
+		goto out_unlock;
+
+#ifdef HAVE_NVIDIA_P2P
+	ret = nvidia_p2p_init();
+	if (!ret) {
+		cxi_supported_p2p_type = CXI_P2P_NVIDIA_GPU;
+		goto out_unlock;
+	}
+#endif
+
+#ifdef HAVE_AMD_RDMA
+	ret = amd_p2p_init();
+	if (!ret)
+		cxi_supported_p2p_type = CXI_P2P_AMD_GPU;
+#endif
+
+out_unlock:
+	mutex_unlock(&p2p_init_lock);
+
+	return ret;
+}
+
+/**
+ * cxi_p2p_fini - Clean up a GPU direct interface.
+ */
+void cxi_p2p_fini(void)
+{
+	switch (cxi_supported_p2p_type) {
+	case CXI_P2P_AMD_GPU:
+#ifdef HAVE_AMD_RDMA
+		amd_p2p_fini();
+#endif
+		break;
+	case CXI_P2P_NVIDIA_GPU:
+#ifdef HAVE_NVIDIA_P2P
+		nvidia_p2p_fini();
+#endif
+		break;
+	}
+}
+
+/**
+ * cass_device_md() - Allocate a memory descriptor and get GPU device pages
+ *
+ * @lni_priv: LNI
+ * @va: device virtual address
+ * @len: length
+ * @dma_addr: dma address of va
+ * @return: memory descriptor
+ */
+struct cxi_md_priv *cass_device_md(struct cxi_lni_priv *lni_priv, u64 va,
+				   size_t len, dma_addr_t *dma_addr)
+{
+	int rc;
+	struct ac_map_opts m_opts = {};
+	struct cxi_md_priv *md_priv;
+	struct cass_dev *hw = container_of(lni_priv->dev, struct cass_dev,
+					   cdev);
+
+	rc = cass_is_device_memory(hw, &m_opts, va, len);
+	if (rc)
+		return ERR_PTR(rc);
+
+	md_priv = kzalloc(sizeof(*md_priv), GFP_KERNEL);
+	if (!md_priv)
+		return ERR_PTR(-ENOMEM);
+
+	m_opts.md_priv = md_priv;
+	cass_align_start_len(&m_opts, va, len, m_opts.page_shift);
+
+	md_priv->lni_priv = lni_priv;
+	md_priv->md.va = m_opts.va_start;
+	md_priv->md.len = m_opts.va_len;
+	md_priv->md.page_shift = m_opts.page_shift;
+
+	refcount_set(&md_priv->refcount, 1);
+
+	rc = cass_device_get_pages(&m_opts);
+	if (rc) {
+		kfree(md_priv);
+		return ERR_PTR(rc);
+	}
+
+	/* Get the first entry of the sg_table */
+	*dma_addr = sg_dma_address(md_priv->sgt->sgl);
+
+	return md_priv;
+}
+
+/**
+ * cass_device_hugepage_size - Determine an appropriate hugepage size for
+ *                             the dma address list based on the number of
+ *                             contiguous entries.
+ *
+ * @contig_cnt: Number contiguous entries
+ * @m_opts: User map options
+ */
+void cass_device_hugepage_size(int contig_cnt, struct ac_map_opts *m_opts)
+{
+	int i;
+	int va_shift;
+	int len_shift;
+	int cntg_shift;
+	int daddr_shift;
+	int align_shift;
+	dma_addr_t dma_addr = sg_dma_address(m_opts->md_priv->sgt->sgl);
+
+	if (!device_hugepage_enable)
+		return;
+
+	cntg_shift = flsl(contig_cnt) + m_opts->page_shift;
+	len_shift = ffsl(__rounddown_pow_of_two(m_opts->va_len));
+	va_shift = ffsl(m_opts->va_start);
+	daddr_shift = ffsl(dma_addr);
+	align_shift = min_t(int, va_shift, len_shift);
+	align_shift = min_t(int, daddr_shift, align_shift);
+	align_shift = min_t(int, cntg_shift, align_shift);
+
+	/* From the list of usable hugepage sizes, pick the largest one
+	 * that the registration consumes.
+	 */
+	for (i = device_hs_array_n - 1; i >= 0; i--) {
+		int page_table_size = device_hs_array[i] - m_opts->page_shift;
+
+		if (device_hs_array[i] <= align_shift &&
+		    page_table_size <= MAX_PG_TABLE_SIZE &&
+				page_table_size >= MIN_DEVICE_PG_TABLE_SIZE) {
+			m_opts->is_huge_page = true;
+			m_opts->huge_shift = device_hs_array[i];
+			break;
+		}
+	}
+
+	pr_debug("len:%lx align_shift:%d hs:%d is_hp:%d\n", m_opts->va_len,
+		 align_shift, m_opts->huge_shift, m_opts->is_huge_page);
+}
+
+/**
+ * cass_is_device_memory - Check if va is backed by device memory
+ *
+ * Also, return the page size.
+ *
+ * @hw: The cassini device
+ * @m_opts: User map options
+ * @va: Device virtual address
+ * @len: Length of address to map in bytes
+ * @return: 0 on success or < 0 on failure
+ */
+int cass_is_device_memory(struct cass_dev *hw, struct ac_map_opts *m_opts,
+			  uintptr_t va, size_t len)
+{
+	int ret;
+
+	if (m_opts->md_priv &&
+	    m_opts->md_priv->dmabuf_fd != INVALID_DMABUF_FD) {
+		m_opts->page_shift = PAGE_SHIFT;
+
+		return 0;
+	}
+
+	if (p2p_ops.is_device_mem == NULL) {
+		ret = cxi_p2p_init();
+		if (ret) {
+			cxidev_info_ratelimited(&hw->cdev, "p2p_init failed %d\n",
+						ret);
+			return ret;
+		}
+	}
+
+	if (!p2p_ops.is_device_mem)
+		return -EOPNOTSUPP;
+
+	ret = p2p_ops.is_device_mem(va, len, &m_opts->page_shift);
+	if (ret) {
+		cxidev_info_ratelimited(&hw->cdev, "Expected device memory ret:%d\n",
+					ret);
+		return ret;
+	}
+
+	return 0;
+}
+
+/**
+ * cass_device_get_pages - Get device pages
+ *
+ * @m_opts: User map options
+ * @return: 0 on success or < 0 on failure
+ */
+int cass_device_get_pages(struct ac_map_opts *m_opts)
+{
+	if (m_opts->md_priv->dmabuf_fd != INVALID_DMABUF_FD)
+		return cxi_dmabuf_get_pages(m_opts);
+
+	if (p2p_ops.get_pages)
+		return p2p_ops.get_pages(m_opts);
+
+	return -EINVAL;
+}
+
+/**
+ * cass_device_put_pages - Put device pages returned from cass_device_get_pages
+ *
+ * @md_priv: Private memory descriptor
+ */
+void cass_device_put_pages(struct cxi_md_priv *md_priv)
+{
+	if (md_priv->dmabuf_fd != INVALID_DMABUF_FD) {
+		cxi_dmabuf_put_pages(md_priv);
+		return;
+	}
+
+	p2p_ops.put_pages(md_priv);
+}
diff --git a/drivers/net/ethernet/hpe/ss1/cass_rmu.c b/drivers/net/ethernet/hpe/ss1/cass_rmu.c
new file mode 100644
index 000000000000..c510831c9e15
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_rmu.c
@@ -0,0 +1,376 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2018, 2024-2026 Hewlett Packard Enterprise Development LP */
+
+/* Create and destroy Cassini command queues */
+
+#include <linux/hpe/cxi/cxi.h>
+#include <linux/idr.h>
+#include <linux/kernel.h>
+#include <linux/rbtree.h>
+#include <linux/types.h>
+
+#include "cass_core.h"
+#include "cass_ss1_debugfs.h"
+
+/* Add a new domain into a device domain tree. */
+static int insert_domain(struct rb_root *root,
+			 struct cxi_domain_priv *domain_priv)
+{
+	struct rb_node **new = &(root->rb_node), *parent = NULL;
+
+	/* Figure out where to put new node */
+	while (*new) {
+		struct cxi_domain_priv *this =
+			container_of(*new, struct cxi_domain_priv, node);
+
+		parent = *new;
+		if (domain_priv->domain.vni < this->domain.vni)
+			new = &((*new)->rb_left);
+		else if (domain_priv->domain.vni > this->domain.vni)
+			new = &((*new)->rb_right);
+		else if (domain_priv->domain.pid < this->domain.pid)
+			new = &((*new)->rb_left);
+		else if (domain_priv->domain.pid > this->domain.pid)
+			new = &((*new)->rb_right);
+		else
+			return -EEXIST;
+	}
+
+	/* Add new node and rebalance tree. */
+	rb_link_node(&domain_priv->node, parent, new);
+	rb_insert_color(&domain_priv->node, root);
+
+	return 0;
+}
+
+/* Look up an existing domain by (vni,pid) without modifying the tree. */
+static struct cxi_domain_priv *find_domain(struct rb_root *root,
+					   unsigned int vni, unsigned int pid)
+{
+	struct rb_node *node = root->rb_node;
+
+	while (node) {
+		struct cxi_domain_priv *this =
+			container_of(node, struct cxi_domain_priv, node);
+
+		if (vni < this->domain.vni)
+			node = node->rb_left;
+		else if (vni > this->domain.vni)
+			node = node->rb_right;
+		else if (pid < this->domain.pid)
+			node = node->rb_left;
+		else if (pid > this->domain.pid)
+			node = node->rb_right;
+		else
+			return this;
+	}
+
+	return NULL;
+}
+
+/* Atomically reserve a contiguous range of VNI PIDs. On success, PIDs are
+ * reserved to the LNI. Reserved PIDs are released when the LNI is destroyed.
+ * cxi_domain_alloc() must be used to create a Domain using a reserved PID.
+ */
+int cxi_domain_reserve(struct cxi_lni *lni, unsigned int vni, unsigned int pid,
+		       unsigned int count)
+{
+	struct cxi_lni_priv *lni_priv =
+		container_of(lni, struct cxi_lni_priv, lni);
+	struct cxi_dev *cdev = lni_priv->dev;
+	struct cxi_rx_profile *rx_profile;
+	struct cxi_reserved_pids *pids;
+	int rc;
+	int i;
+
+	/* Sanity checks. */
+	if (!is_vni_valid(vni))
+		return -EINVAL;
+
+	if (!cxi_valid_vni(cdev, CXI_PROF_RX, vni))
+		return -EINVAL;
+
+	if (pid >= cdev->prop.pid_count && pid != C_PID_ANY)
+		return -EINVAL;
+
+	if (!count || count > cdev->prop.pid_count)
+		return -EINVAL;
+
+	rx_profile = cxi_dev_find_rx_profile(cdev, vni);
+	if (!rx_profile)
+		return -ENOENT;
+
+	rc = cxi_rx_profile_alloc_pid(lni_priv, rx_profile, pid, vni, count, true);
+	if (rc < 0)
+		goto put_rx_profile;
+	pid = rc;
+
+	pids = kzalloc(sizeof(*pids), GFP_KERNEL);
+	if (!pids) {
+		rc = -ENOMEM;
+		goto clear_pids;
+	}
+
+	pids->rx_profile = rx_profile;
+
+	for (i = 0; i < count; i++)
+		set_bit(pid + i, pids->table);
+
+	spin_lock(&lni_priv->res_lock);
+	list_add_tail(&pids->entry, &lni_priv->reserved_pids);
+	spin_unlock(&lni_priv->res_lock);
+
+	return pid;
+
+clear_pids:
+	cxi_rx_profile_update_pid_table(rx_profile, pid, count, false);
+put_rx_profile:
+	cxi_rx_profile_dec_refcount(cdev, rx_profile);
+
+	return rc;
+}
+EXPORT_SYMBOL(cxi_domain_reserve);
+
+/* Clean up PIDs reserved to the LNI. */
+void cxi_domain_lni_cleanup(struct cxi_lni_priv *lni_priv)
+{
+	struct cxi_reserved_pids *pids;
+
+	while ((pids = list_first_entry_or_null(&lni_priv->reserved_pids,
+						struct cxi_reserved_pids,
+						entry))) {
+		list_del(&pids->entry);
+		cxi_rx_profile_andnot_pid_table(pids,
+						lni_priv->dev->prop.pid_count);
+		cxi_rx_profile_dec_refcount(lni_priv->dev, pids->rx_profile);
+		kfree(pids);
+	}
+}
+
+/** cxi_domain_alloc_vf() - Allocate a domain for VF
+ *
+ * @lni: LNI to allocate the domain on
+ * @vni: VNI for the domain
+ * @pid: PID for the domain
+ *
+ * Return: Pointer to allocated domain on success, ERR_PTR on failure.
+ */
+static struct cxi_domain *
+cxi_domain_alloc_vf(struct cxi_lni *lni, unsigned int vni, unsigned int pid)
+{
+	struct cxi_lni_priv_vf *lni_priv_vf =
+		container_of(lni, struct cxi_lni_priv_vf, lni);
+	struct cxi_dev *dev = lni_priv_vf->dev;
+	struct cxi_domain_priv_vf *domain_priv_vf;
+	const struct cxi_domain_alloc_cmd cmd = {
+		.op = CXI_OP_DOMAIN_ALLOC,
+		.lni = lni_priv_vf->lni.id,
+		.vni = vni,
+		.pid = pid,
+	};
+	struct cxi_domain_alloc_resp resp;
+	size_t resp_len = sizeof(resp);
+	int rc;
+
+	domain_priv_vf = kzalloc(sizeof(*domain_priv_vf), GFP_KERNEL);
+	if (!domain_priv_vf)
+		return ERR_PTR(-ENOMEM);
+
+	rc = cxi_send_msg_to_pf(dev, &cmd, sizeof(cmd), &resp, &resp_len);
+	if (rc)
+		goto error_out;
+
+	domain_priv_vf->lni_priv = container_of(lni, struct cxi_lni_priv, lni);
+	domain_priv_vf->domain.id = resp.domain;
+	domain_priv_vf->domain.vni = resp.vni;
+	domain_priv_vf->domain.pid = resp.pid;
+
+	return &domain_priv_vf->domain;
+
+error_out:
+	kfree(domain_priv_vf);
+
+	return ERR_PTR(rc);
+}
+
+/* Allocate a new domain, with a unique per-device VNI+PID. The VNI is
+ * reserved in the RMU table if it doesn't already exist.
+ */
+struct cxi_domain *cxi_domain_alloc(struct cxi_lni *lni, unsigned int vni,
+				    unsigned int pid)
+{
+	struct cxi_lni_priv *lni_priv =
+		container_of(lni, struct cxi_lni_priv, lni);
+	struct cxi_dev *cdev = lni_priv->dev;
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	struct cxi_domain_priv *domain_priv;
+	struct cxi_domain_priv *existing;
+	int rc;
+	int domain_pid = pid;
+	struct cxi_rx_profile *rx_profile;
+
+	if (!cdev->is_physfn)
+		return cxi_domain_alloc_vf(lni, vni, pid);
+
+	/* Sanity checks. */
+	if (!is_vni_valid(vni))
+		return ERR_PTR(-EINVAL);
+
+	if (domain_pid >= cdev->prop.pid_count && domain_pid != C_PID_ANY)
+		return ERR_PTR(-EINVAL);
+
+	/*
+	 * Multiple QPs on one LNI (one PD/svc_id, in the RDMA per-PD-LNI
+	 * model) may legitimately want the same (vni,pid) domain identity —
+	 * e.g. several receive queues/services on one PID. Share the
+	 * existing object (refcounted) instead of colliding, but only
+	 * within the same LNI: cross-LNI reuse of one (vni,pid) would mean
+	 * two unrelated processes receiving on the same address, which
+	 * stays a hard conflict. A C_PID_ANY request always allocates
+	 * fresh, since there's nothing concrete yet to look up.
+	 */
+	if (domain_pid != C_PID_ANY) {
+		spin_lock(&hw->domain_lock);
+		existing = find_domain(&hw->domain_tree, vni, domain_pid);
+		if (existing) {
+			if (existing->lni_priv != lni_priv) {
+				spin_unlock(&hw->domain_lock);
+				return ERR_PTR(-EEXIST);
+			}
+			refcount_inc(&existing->refcount);
+			spin_unlock(&hw->domain_lock);
+			return &existing->domain;
+		}
+		spin_unlock(&hw->domain_lock);
+	}
+
+	rx_profile = cxi_dev_get_rx_profile(cdev, vni);
+	if (IS_ERR(rx_profile)) {
+		rc = PTR_ERR(rx_profile);
+		pr_debug("rx_profile not found for vni:%d rc:%d\n",
+			 vni, rc);
+		return ERR_PTR(rc);
+	}
+
+	domain_pid = cxi_rx_profile_alloc_pid(lni_priv, rx_profile, pid, vni,
+					      1, false);
+	if (domain_pid < 0) {
+		rc = domain_pid;
+		goto put_rx_profile;
+	}
+
+	domain_priv = kzalloc(sizeof(*domain_priv), GFP_KERNEL);
+	if (domain_priv == NULL) {
+		rc = -ENOMEM;
+		goto free_pid;
+	}
+
+	/* Get a domain ID */
+	rc = ida_alloc_min(&hw->domain_table, 1, GFP_KERNEL);
+	if (rc < 0) {
+		cxidev_err(cdev, "ida_alloc_min failed %d\n", rc);
+		goto free_domain;
+	}
+	domain_priv->domain.id = rc;
+
+	refcount_set(&domain_priv->refcount, 1);
+
+	domain_priv->lni_priv = lni_priv;
+	domain_priv->rx_profile = rx_profile;
+	domain_priv->domain.vni = vni;
+	domain_priv->domain.pid = domain_pid;
+
+	spin_lock(&hw->domain_lock);
+	rc = insert_domain(&hw->domain_tree, domain_priv);
+	spin_unlock(&hw->domain_lock);
+	if (rc)
+		goto free_dom_id;
+
+	domain_debugfs_create(vni, domain_pid, hw, domain_priv);
+
+	spin_lock(&lni_priv->res_lock);
+	atomic_inc(&hw->stats.domain);
+	list_add_tail(&domain_priv->list, &lni_priv->domain_list);
+	spin_unlock(&lni_priv->res_lock);
+
+	refcount_inc(&lni_priv->refcount);
+	return &domain_priv->domain;
+
+free_dom_id:
+	ida_free(&hw->domain_table, domain_priv->domain.id);
+free_domain:
+	kfree(domain_priv);
+free_pid:
+	cxi_rx_profile_update_pid_table(rx_profile, pid, 1, false);
+put_rx_profile:
+	cxi_rx_profile_dec_refcount(cdev, rx_profile);
+
+	return ERR_PTR(rc);
+}
+EXPORT_SYMBOL(cxi_domain_alloc);
+
+/** cxi_domain_free_vf() - Free an allocated domain for VF
+ *
+ * @domain: Domain to be freed
+ */
+static void cxi_domain_free_vf(struct cxi_domain *domain)
+{
+	struct cxi_domain_priv_vf *domain_priv_vf =
+		container_of(domain, struct cxi_domain_priv_vf, domain);
+	struct cxi_dev *dev = domain_priv_vf->lni_priv->dev;
+	const struct cxi_domain_free_cmd cmd = {
+		.op = CXI_OP_DOMAIN_FREE,
+		.domain = domain_priv_vf->domain.id,
+	};
+	size_t resp_len = 0;
+	int rc;
+
+	rc = cxi_send_msg_to_pf(dev, &cmd, sizeof(cmd), NULL, &resp_len);
+	if (rc)
+		cxidev_warn(dev, "VF domain free request failed: %d\n", rc);
+
+	kfree(domain_priv_vf);
+}
+
+/* Free an allocated domain. */
+void cxi_domain_free(struct cxi_domain *domain)
+{
+	struct cxi_domain_priv *domain_priv =
+			container_of(domain, struct cxi_domain_priv, domain);
+	struct cxi_lni_priv *lni_priv = domain_priv->lni_priv;
+	struct cxi_dev *cdev = lni_priv->dev;
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+
+	if (!cdev->is_physfn) {
+		cxi_domain_free_vf(domain);
+		return;
+	}
+
+	/* Other QPs on this LNI may still hold a reference (see the reuse
+	 * path in cxi_domain_alloc()) — only the last one actually tears
+	 * this domain down.
+	 */
+	if (!refcount_dec_and_test(&domain_priv->refcount))
+		return;
+
+	spin_lock(&lni_priv->res_lock);
+	list_del(&domain_priv->list);
+	atomic_dec(&hw->stats.domain);
+	spin_unlock(&lni_priv->res_lock);
+
+	debugfs_remove_recursive(domain_priv->debug_dir);
+
+	spin_lock(&hw->domain_lock);
+	rb_erase(&domain_priv->node, &hw->domain_tree);
+	spin_unlock(&hw->domain_lock);
+
+	cxi_rx_profile_update_pid_table(domain_priv->rx_profile,
+					domain->pid, 1, false);
+	cxi_rx_profile_dec_refcount(cdev, domain_priv->rx_profile);
+
+	ida_free(&hw->domain_table, domain_priv->domain.id);
+	kfree(domain_priv);
+
+	refcount_dec(&lni_priv->refcount);
+}
+EXPORT_SYMBOL(cxi_domain_free);
diff --git a/drivers/net/ethernet/hpe/ss1/cass_rmu_eth.c b/drivers/net/ethernet/hpe/ss1/cass_rmu_eth.c
new file mode 100644
index 000000000000..150ba1f762b6
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_rmu_eth.c
@@ -0,0 +1,1017 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2026 Hewlett Packard Enterprise Development LP */
+
+/* RMU Ethernet Resource Management */
+
+#include <linux/hpe/cxi/cxi.h>
+#include <linux/etherdevice.h>
+#include <linux/ethtool.h>
+#include <linux/xarray.h>
+#include <linux/idr.h>
+
+#include "cass_core.h"
+#include "cxi_internal.h"
+
+_Static_assert(CXI_ETH_MAX_INDIR_ENTRIES <=
+	       C_RMU_CFG_PORTAL_INDEX_INDIR_TABLE_ENTRIES,
+	       "CXI_ETH_MAX_INDIR_ENTRIES exceeds NIC table size");
+
+/* Maximum number of concurrent clients allowed in PF */
+static unsigned int rmu_pf_max_clients = 2;
+module_param(rmu_pf_max_clients, uint, 0444);
+MODULE_PARM_DESC(rmu_pf_max_clients, "Maximum number of concurrent RMU Ethernet clients in PF");
+
+/* Total MAC filter allocation (set_list entries)
+ * - PF gets fixed quota: rmu_pf_client_max_filters (default 20, module parameter)
+ * - VFs split remaining pool equally.
+ */
+static unsigned int rmu_pf_client_max_filters = 20;
+module_param(rmu_pf_client_max_filters, uint, 0444);
+MODULE_PARM_DESC(rmu_pf_client_max_filters,
+		 "Maximum number of MAC filters allocated to a PF client");
+
+/* Indirection table allocation
+ * - PF gets fixed quota: rmu_pf_client_max_rss_indir_size (default 64, module parameter)
+ * - VFs split remaining pool equally.
+ */
+static unsigned int rmu_pf_client_max_rss_indir_size = 64;
+static int param_set_rmu_pf_client_max_rss_indir_size(const char *val,
+						      const struct kernel_param *kp)
+{
+	unsigned int tmp;
+	int rc;
+
+	rc = kstrtouint(val, 0, &tmp);
+	if (rc)
+		return rc;
+
+	if (tmp > CXI_ETH_MAX_INDIR_ENTRIES)
+		return -EINVAL;
+
+	*(unsigned int *)kp->arg = tmp;
+
+	return 0;
+}
+
+static const struct kernel_param_ops param_ops_rmu_pf_client_max_rss_indir_size = {
+	.set = param_set_rmu_pf_client_max_rss_indir_size,
+	.get = param_get_uint,
+};
+
+module_param_cb(rmu_pf_client_max_rss_indir_size,
+		&param_ops_rmu_pf_client_max_rss_indir_size,
+		&rmu_pf_client_max_rss_indir_size, 0444);
+MODULE_PARM_DESC(rmu_pf_client_max_rss_indir_size,
+		 "Maximum size of RSS indirection table for each PF client");
+
+/**
+ * validate_mac_vf() - Validate MAC address for VF use
+ * @mac_addr: MAC address to validate
+ *
+ * VFs can only use valid unicast MAC addresses (not multicast, broadcast, or zero).
+ * This also includes the reserved MAC addresses for PTP and multicast base,
+ * which should not be used by VFs.
+ *
+ * Return: 0 if valid, -EINVAL if invalid
+ */
+static int validate_mac_vf(u64 mac_addr)
+{
+	u8 addr[ETH_ALEN];
+
+	u64_to_ether_addr(mac_addr, addr);
+
+	return is_valid_ether_addr(addr) ? 0 : -EINVAL;
+}
+
+/**
+ * cxi_rmu_eth_alloc_vf() - Allocate Ethernet packet matching resources for VF
+ * @cdev: CXI device
+ *
+ * VF version: Sends allocation request to PF via vsock. The PF will allocate
+ * the actual hardware resources and track them. The VF maintains a minimal
+ * private structure for sending future commands to the PF.
+ *
+ * Return: Pointer to cxi_rmu_eth or ERR_PTR on error
+ */
+static struct cxi_rmu_eth *cxi_rmu_eth_alloc_vf(struct cxi_dev *cdev)
+{
+	struct cxi_rmu_eth_priv *priv;
+	struct cxi_rmu_eth_alloc_resp resp;
+	const struct cxi_rmu_eth_alloc_cmd cmd = {
+		.op = CXI_OP_RMU_ETH_ALLOC,
+		.resp = &resp,
+	};
+	size_t resp_len = sizeof(resp);
+	int rc;
+
+	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return ERR_PTR(-ENOMEM);
+
+	/* Send allocation request to PF */
+	rc = cxi_send_msg_to_pf(cdev, &cmd, sizeof(cmd), &resp, &resp_len);
+	if (rc) {
+		kfree(priv);
+		return ERR_PTR(rc);
+	}
+
+	priv->dev = cdev;
+	priv->rmu_eth.id = resp.rmu_eth;
+
+	return &priv->rmu_eth;
+}
+
+/**
+ * cxi_rmu_eth_alloc_internal() - Allocate Ethernet packet matching resources
+ * @cdev: CXI device
+ * @vf_en: Whether this is a VF allocation
+ * @vf_num: VF number if vf_en is true
+ *
+ * PF supports up to CXI_RMU_ETH_PF_MAX_CLIENTS concurrent allocations.
+ * VFs support single client per function.
+ * Returns -EBUSY if no slots available.
+ *
+ * Automatically allocates FULL per-function quota based on num_vfs.
+ *
+ * Return: Pointer to cxi_rmu_eth or ERR_PTR on error
+ */
+struct cxi_rmu_eth *cxi_rmu_eth_alloc_internal(struct cxi_dev *cdev, bool vf_en, u8 vf_num)
+{
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	struct cxi_rmu_eth *rmu_eth = NULL;
+	struct cxi_rmu_eth_priv *priv;
+	unsigned int indir_quota;
+	unsigned int set_list_quota;
+	int id;
+	int i;
+
+	if (vf_en && hw->num_vfs == 0)
+		return ERR_PTR(-EINVAL);
+
+	mutex_lock(&hw->rmu_eth_lock);
+
+	/* Allocate private structure */
+	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+	if (!priv) {
+		mutex_unlock(&hw->rmu_eth_lock);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	/* Initialize structure */
+	priv->dev = cdev;
+	priv->is_vf = vf_en;
+	priv->vf_num = vf_num;
+	priv->admin = vf_en ? false : true; /* Only PF client has admin privileges */
+
+	/* Store allocation in device structure (needed before ID allocation) */
+	rmu_eth = &priv->rmu_eth;
+
+	/* Get unique ID for this allocation. PF and VFs have separate ID spaces.
+	 * PF clients: IDs 0 to (rmu_pf_max_clients - 1)
+	 * VF clients: IDs starting from rmu_pf_max_clients
+	 */
+	id = idr_alloc(&hw->rmu_eth_idr, rmu_eth,
+		       vf_en ? rmu_pf_max_clients + vf_num : 0,
+		       vf_en ? rmu_pf_max_clients + vf_num + 1 : rmu_pf_max_clients,
+		       GFP_KERNEL);
+
+	if (id < 0) {
+		kfree(priv);
+		mutex_unlock(&hw->rmu_eth_lock);
+		return ERR_PTR(id);
+	}
+
+	rmu_eth->id = id;
+
+	/* Calculate per-client quotas and base indices
+	 * - indirection table layout remains unchanged (PF first, then VFs).
+	 * - set_list places PF clients at the end to avoid PF catch-all filters
+	 *   taking early slots.
+	 */
+	if (vf_en) {
+		/* VF gets equal share of remaining indirection and set_list pools */
+		indir_quota = (C_RMU_CFG_PORTAL_INDEX_INDIR_TABLE_ENTRIES -
+			      (rmu_pf_client_max_rss_indir_size * rmu_pf_max_clients)) / hw->num_vfs;
+		set_list_quota = (C_RMU_CFG_PTLTE_SET_LIST_ENTRIES -
+				 (rmu_pf_client_max_filters * rmu_pf_max_clients)) / hw->num_vfs;
+
+		priv->indir_base = (rmu_pf_client_max_rss_indir_size * rmu_pf_max_clients) +
+				   (vf_num * indir_quota);
+		priv->set_list_base = vf_num * set_list_quota;
+	} else {
+		/* PF client keeps original indirection layout and gets tail set_list */
+		indir_quota = rmu_pf_client_max_rss_indir_size;
+		set_list_quota = rmu_pf_client_max_filters;
+
+		priv->indir_base = id * indir_quota;
+		priv->set_list_base = C_RMU_CFG_PTLTE_SET_LIST_ENTRIES -
+				     (rmu_pf_max_clients * set_list_quota) +
+				     (id * set_list_quota);
+	}
+
+	priv->indir_size = indir_quota;
+	priv->set_list_quota = set_list_quota;
+
+	/* Allocate MAC filter slot tracking array */
+	priv->mac_filter_slots = kcalloc(set_list_quota, sizeof(u8), GFP_KERNEL);
+	if (!priv->mac_filter_slots) {
+		idr_remove(&hw->rmu_eth_idr, id);
+		kfree(priv);
+		mutex_unlock(&hw->rmu_eth_lock);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	/* Invalidate all set_list entries in our quota to ensure clean state */
+	spin_lock(&hw->rmu_lock);
+	for (i = 0; i < set_list_quota; i++)
+		cass_invalidate_set_list(hw, priv->set_list_base + i);
+	spin_unlock(&hw->rmu_lock);
+
+	/* Default RSS configuration (disabled initially) */
+	priv->rss_queues = 0;
+	priv->hash_types = 0;
+	priv->indir_entries = 0;  /* Active indirection table size */
+
+	mutex_unlock(&hw->rmu_eth_lock);
+
+	return &priv->rmu_eth;
+}
+EXPORT_SYMBOL(cxi_rmu_eth_alloc_internal);
+
+struct cxi_rmu_eth *cxi_rmu_eth_alloc(struct cxi_dev *cdev)
+{
+	return cdev->is_physfn ? cxi_rmu_eth_alloc_internal(cdev, false, 0) :
+				 cxi_rmu_eth_alloc_vf(cdev);
+}
+EXPORT_SYMBOL(cxi_rmu_eth_alloc);
+
+/**
+ * cxi_rmu_eth_free_vf() - Free Ethernet resources (VF version)
+ * @rmu_eth: Resource handle
+ *
+ * VF version: Sends free request to PF via vsock.
+ */
+static void cxi_rmu_eth_free_vf(struct cxi_rmu_eth *rmu_eth)
+{
+	struct cxi_rmu_eth_priv *priv = container_of(rmu_eth,
+						     struct cxi_rmu_eth_priv,
+						     rmu_eth);
+	const struct cxi_rmu_eth_free_cmd cmd = {
+		.op = CXI_OP_RMU_ETH_FREE,
+		.resp = NULL,
+		.rmu_eth = rmu_eth->id,
+	};
+	size_t resp_len = 0;
+	int rc;
+
+	rc = cxi_send_msg_to_pf(priv->dev, &cmd, sizeof(cmd), NULL, &resp_len);
+	if (rc)
+		cxidev_err(priv->dev, "Failed to free RMU Ethernet resources on PF: %d\n", rc);
+
+	kfree(priv);
+}
+
+/**
+ * cxi_rmu_eth_free() - Free Ethernet resources
+ * @rmu_eth: Resource handle
+ *
+ * Automatically invalidates all set_list entries, clears indirection table,
+ * and releases all resources.
+ */
+void cxi_rmu_eth_free(struct cxi_rmu_eth *rmu_eth)
+{
+	struct cxi_rmu_eth_priv *priv = container_of(rmu_eth,
+						     struct cxi_rmu_eth_priv,
+						     rmu_eth);
+	struct cass_dev *hw = container_of(priv->dev, struct cass_dev, cdev);
+	int i;
+
+	if (!priv->dev->is_physfn) {
+		cxi_rmu_eth_free_vf(rmu_eth);
+		return;
+	}
+
+	mutex_lock(&hw->rmu_eth_lock);
+
+	/* Invalidate all set_list entries in our quota range */
+	spin_lock(&hw->rmu_lock);
+
+	for (i = 0; i < priv->set_list_quota; i++) {
+		unsigned int hw_idx = priv->set_list_base + i;
+
+		/* Debug log for entries that were actually programmed */
+		if (priv->mac_filter_slots[i]) {
+			cxidev_dbg(priv->dev, "Removing RMU filter at idx=%d (hw_idx=%u)\n",
+				   i, hw_idx);
+		}
+
+		cass_invalidate_set_list(hw, hw_idx);
+	}
+
+	spin_unlock(&hw->rmu_lock);
+
+	/* Free slot tracking array */
+	kfree(priv->mac_filter_slots);
+
+	/* Remove from IDR */
+	idr_remove(&hw->rmu_eth_idr, rmu_eth->id);
+
+	mutex_unlock(&hw->rmu_eth_lock);
+
+	kfree(priv);
+}
+EXPORT_SYMBOL(cxi_rmu_eth_free);
+
+/**
+ * add_rmu_set_list_filter() - Common hardware programming logic for filter installation
+ * @priv: Private resource structure
+ * @idx: Relative index within client's quota
+ * @pte: PTE pointer
+ * @use_rss: Whether traffic participates in RSS
+ * @set_list: Prepared set_list entry with match criteria
+ * @set_list_mask: Prepared mask for set_list
+ *
+ * Handles index validation, translation, and hardware programming for both
+ * MAC filters and promiscuous mode filters.
+ *
+ * Return: 0 on success, negative errno on error
+ */
+static int add_rmu_set_list_filter(struct cxi_rmu_eth_priv *priv, unsigned int idx,
+				   struct cxi_pte *pte, bool use_rss,
+				   const union c_rmu_cfg_ptlte_set_list *set_list,
+				   const union c_rmu_cfg_ptlte_set_list *set_list_mask)
+{
+	struct cass_dev *hw = container_of(priv->dev, struct cass_dev, cdev);
+	unsigned int set_list_idx;
+	unsigned int portal_idx;
+	struct c_rmu_cfg_ptlte_set_ctrl_table_entry set_ctrl = {};
+
+	/* Validate index range */
+	if (idx >= priv->set_list_quota) {
+		cxidev_err(priv->dev, "Index %d out of range [0..%u]\n",
+			   idx, priv->set_list_quota - 1);
+		return -EINVAL;
+	}
+
+	/* Extract portal index from PTE */
+	portal_idx = pte->id;
+
+	/* Translate relative index to hardware index */
+	set_list_idx = priv->set_list_base + idx;
+
+	spin_lock(&hw->rmu_lock);
+
+	/* Program set_list */
+	cass_config_set_list(hw, set_list_idx, portal_idx,
+			     set_list, set_list_mask);
+
+	/* Program set_ctrl for RSS or direct portal */
+	if (use_rss && priv->rss_queues > 1) {
+		/* Use RSS */
+		set_ctrl.portal_index_indir_base = priv->indir_base;
+		set_ctrl.hash_bits = ilog2(priv->indir_entries);
+		set_ctrl.hash_types_enabled = priv->hash_types;
+	} else {
+		/* Direct portal (RSS disabled) - point to fallback entry */
+		set_ctrl.portal_index_indir_base = 2048 + set_list_idx;
+		set_ctrl.hash_bits = 0;
+		set_ctrl.hash_types_enabled = 0;
+	}
+
+	/* Program set_ctrl */
+	cass_config_set_ctrl(hw, set_list_idx, &set_ctrl);
+
+	/* Program default portal at indir_table[2048 + set_list_idx] */
+	cass_config_indir_entry(hw, 2048 + set_list_idx, portal_idx);
+
+	spin_unlock(&hw->rmu_lock);
+
+	/* Mark slot as used */
+	priv->mac_filter_slots[idx] = use_rss ? CXI_RMU_ETH_FILTER_RSS :
+					      CXI_RMU_ETH_FILTER_DIRECT;
+
+	return 0;
+}
+
+/**
+ * cxi_rmu_eth_add_mac_filter_vf() - Add MAC address filter (VF version)
+ * @rmu_eth: Resource handle
+ * @idx: Relative index (0-based) within client's quota
+ * @mac_addr: MAC address to match (48-bit)
+ * @pte: PTE pointer
+ * @use_rss: Whether this MAC participates in RSS distribution
+ *
+ * VF version: Sends add_mac request to PF via vsock.
+ *
+ * Return: 0 on success, negative errno on error
+ */
+static int cxi_rmu_eth_add_mac_filter_vf(struct cxi_rmu_eth *rmu_eth,
+					 unsigned int idx, u64 mac_addr,
+					 struct cxi_pte *pte, bool use_rss)
+{
+	struct cxi_rmu_eth_priv *priv = container_of(rmu_eth,
+						     struct cxi_rmu_eth_priv,
+						     rmu_eth);
+	const struct cxi_rmu_eth_add_mac_filter_cmd cmd = {
+		.op = CXI_OP_RMU_ETH_ADD_MAC_FILTER,
+		.rmu_eth = rmu_eth->id,
+		.idx = idx,
+		.mac_addr = mac_addr,
+		.pte = pte->id,
+		.use_rss = use_rss,
+	};
+	size_t resp_len = 0;
+	int rc;
+
+	rc = cxi_send_msg_to_pf(priv->dev, &cmd, sizeof(cmd), NULL, &resp_len);
+	if (rc)
+		return rc;
+
+	return 0;
+}
+
+/**
+ * cxi_rmu_eth_add_all_mcast_filter_vf() - Add all-multicast filter (VF version)
+ * @rmu_eth: Resource handle
+ * @idx: Relative index (0-based) within client's quota
+ * @pte: PTE pointer
+ * @use_rss: Whether this filter participates in RSS distribution
+ *
+ * VF version: Sends add-all-multicast request to PF via vsock.
+ *
+ * Return: 0 on success, negative errno on error
+ */
+static int cxi_rmu_eth_add_all_mcast_filter_vf(struct cxi_rmu_eth *rmu_eth, unsigned int idx,
+					       struct cxi_pte *pte, bool use_rss)
+{
+	struct cxi_rmu_eth_priv *priv = container_of(rmu_eth,
+						     struct cxi_rmu_eth_priv,
+						     rmu_eth);
+	const struct cxi_rmu_eth_add_all_mcast_filter_cmd cmd = {
+		.op = CXI_OP_RMU_ETH_ADD_ALL_MCAST_FILTER,
+		.rmu_eth = rmu_eth->id,
+		.idx = idx,
+		.pte = pte->id,
+		.use_rss = use_rss,
+	};
+	size_t resp_len = 0;
+	int rc;
+
+	rc = cxi_send_msg_to_pf(priv->dev, &cmd, sizeof(cmd), NULL, &resp_len);
+	if (rc)
+		return rc;
+
+	return 0;
+}
+
+/**
+ * cxi_rmu_eth_add_mac_filter() - Add MAC address filter with portal and RSS control
+ * @rmu_eth: Resource handle
+ * @idx: Relative index (0-based) within client's quota
+ * @mac_addr: MAC address to match (48-bit)
+ * @pte: PTE pointer (provides portal index via pte->portal_index)
+ * @use_rss: Whether this MAC participates in RSS distribution
+ *
+ * Client provides relative index [0..quota-1], kernel translates to hardware index.
+ * Reserved indices (0-3) can only be used by PF.
+ *
+ * Return: 0 on success, negative errno on error
+ */
+int cxi_rmu_eth_add_mac_filter(struct cxi_rmu_eth *rmu_eth, unsigned int idx, u64 mac_addr,
+			       struct cxi_pte *pte, bool use_rss)
+{
+	struct cxi_rmu_eth_priv *priv;
+	union c_rmu_cfg_ptlte_set_list set_list = {};
+	union c_rmu_cfg_ptlte_set_list set_list_mask = {};
+	u8 mac_bytes[ETH_ALEN];
+	int rc;
+
+	if (!rmu_eth || !pte)
+		return -EINVAL;
+
+	priv = container_of(rmu_eth, struct cxi_rmu_eth_priv, rmu_eth);
+
+	if (!priv->dev->is_physfn)
+		return cxi_rmu_eth_add_mac_filter_vf(rmu_eth, idx, mac_addr, pte, use_rss);
+
+	u64_to_ether_addr(mac_addr, mac_bytes);
+	cxidev_dbg(priv->dev, "Adding MAC RMU filter %pM at idx=%d (hw_idx=%u) use_rss=%d pte id %u\n",
+		   mac_bytes, idx, priv->set_list_base + idx, use_rss, pte->id);
+
+	/* VFs must use valid unicast MACs only */
+	if (!priv->admin) {
+		rc = validate_mac_vf(mac_addr);
+		if (rc) {
+			cxidev_err(priv->dev, "VF cannot use MAC %pM\n", mac_bytes);
+			return rc;
+		}
+	}
+
+	/* Prepare set_list entry for MAC match */
+	set_list.frame_type = C_RMU_ENET_802_3;
+	set_list.dmac = mac_addr;
+
+	/* Accept only that MAC */
+	set_list_mask.qw[0] = ~set_list.qw[0];
+	set_list_mask.qw[1] = ~set_list.qw[1];
+	set_list_mask.qw[2] = ~set_list.qw[2];
+	set_list_mask.qw[3] = ~set_list.qw[3];
+
+	/* Ignore VLAN/PCP/DEI bits */
+	set_list_mask.vlan_present = 0;
+	set_list_mask.pcp = 0;
+	set_list_mask.dei = 0;
+	set_list_mask.vid = 0;
+	set_list_mask.lossless = 0;
+
+	/* Program hardware set_list filter */
+	return add_rmu_set_list_filter(priv, idx, pte, use_rss, &set_list, &set_list_mask);
+}
+EXPORT_SYMBOL(cxi_rmu_eth_add_mac_filter);
+
+/**
+ * cxi_rmu_eth_add_all_mcast_filter() - Add all-multicast filter with portal and RSS control
+ * @rmu_eth: Resource handle
+ * @idx: Relative index (0-based) within client's quota
+ * @pte: PTE pointer (provides portal index via pte->portal_index)
+ * @use_rss: Whether this filter participates in RSS distribution
+ *
+ * Programs a filter that accepts all multicast Ethernet packets by matching
+ * only frame type and destination MAC multicast bit semantics.
+ *
+ * Return: 0 on success, negative errno on error
+ */
+int cxi_rmu_eth_add_all_mcast_filter(struct cxi_rmu_eth *rmu_eth, unsigned int idx,
+				     struct cxi_pte *pte, bool use_rss)
+{
+	struct cxi_rmu_eth_priv *priv;
+	const union c_rmu_cfg_ptlte_set_list set_list = {
+		.frame_type = C_RMU_ENET_802_3,
+		.dmac = 0x010000000000ULL,
+	};
+	const union c_rmu_cfg_ptlte_set_list set_list_mask = {
+		.qw = {
+			[2] = ~set_list.qw[2],
+			[3] = ~set_list.qw[3],
+		}
+	};
+
+	if (!rmu_eth || !pte)
+		return -EINVAL;
+
+	priv = container_of(rmu_eth, struct cxi_rmu_eth_priv, rmu_eth);
+
+	if (!priv->dev->is_physfn)
+		return cxi_rmu_eth_add_all_mcast_filter_vf(rmu_eth, idx, pte, use_rss);
+
+	cxidev_dbg(priv->dev,
+		   "Adding all-multicast RMU filter at idx=%d (hw_idx=%u) use_rss=%d pte id %u\n",
+		   idx, priv->set_list_base + idx, use_rss, pte->id);
+
+	return add_rmu_set_list_filter(priv, idx, pte, use_rss, &set_list, &set_list_mask);
+}
+EXPORT_SYMBOL(cxi_rmu_eth_add_all_mcast_filter);
+
+/**
+ * cxi_rmu_eth_remove_filter_vf() - Remove filter (VF version)
+ * @rmu_eth: Resource handle
+ * @idx: Relative index of filter to remove
+ *
+ * VF version: Sends remove_filter request to PF via vsock.
+ *
+ * Return: 0 on success, negative errno on error
+ */
+static int cxi_rmu_eth_remove_filter_vf(struct cxi_rmu_eth *rmu_eth, unsigned int idx)
+{
+	struct cxi_rmu_eth_priv *priv = container_of(rmu_eth,
+						     struct cxi_rmu_eth_priv,
+						     rmu_eth);
+	const struct cxi_rmu_eth_remove_filter_cmd cmd = {
+		.op = CXI_OP_RMU_ETH_REMOVE_FILTER,
+		.rmu_eth = rmu_eth->id,
+		.idx = idx,
+	};
+	size_t resp_len = 0;
+	int rc;
+
+	rc = cxi_send_msg_to_pf(priv->dev, &cmd, sizeof(cmd), NULL, &resp_len);
+	if (rc)
+		return rc;
+
+	return 0;
+}
+
+/**
+ * cxi_rmu_eth_remove_filter() - Remove filter by index
+ * @rmu_eth: Resource handle
+ * @idx: Relative index of filter to remove
+ *
+ * Works for both MAC address filters and promiscuous mode filters.
+ * MAC filters use slot tracking and return -ENOENT if slot is empty.
+ * Promiscuous filters don't use slot tracking.
+ *
+ * Return: 0 on success, -ENOENT if MAC slot is empty, -EINVAL for invalid index
+ */
+int cxi_rmu_eth_remove_filter(struct cxi_rmu_eth *rmu_eth, unsigned int idx)
+{
+	struct cxi_rmu_eth_priv *priv = container_of(rmu_eth,
+						     struct cxi_rmu_eth_priv,
+						     rmu_eth);
+	struct cass_dev *hw = container_of(priv->dev, struct cass_dev, cdev);
+	unsigned int set_list_idx;
+
+	if (!priv->dev->is_physfn)
+		return cxi_rmu_eth_remove_filter_vf(rmu_eth, idx);
+
+	/* Validate index range */
+	if (idx >= priv->set_list_quota) {
+		cxidev_err(priv->dev, "Index %d out of range [0..%u]\n",
+			   idx, priv->set_list_quota - 1);
+		return -EINVAL;
+	}
+
+	/* Check if slot is occupied (both MAC and promiscuous filters use slot tracking) */
+	if (!priv->mac_filter_slots[idx]) {
+		cxidev_dbg(priv->dev, "Remove filter at idx=%d (hw_idx=%u) but slot is empty\n",
+			   idx, priv->set_list_base + idx);
+		return -ENOENT;
+	}
+
+	cxidev_dbg(priv->dev, "Remove filter at idx=%d (hw_idx=%u)\n",
+		   idx, priv->set_list_base + idx);
+	/* Translate to hardware index */
+	set_list_idx = priv->set_list_base + idx;
+
+	/* Invalidate hardware entry */
+	spin_lock(&hw->rmu_lock);
+	cass_invalidate_set_list(hw, set_list_idx);
+	spin_unlock(&hw->rmu_lock);
+
+	/* Clear slot (all filters use slot tracking now) */
+	priv->mac_filter_slots[idx] = CXI_RMU_ETH_FILTER_NONE;
+
+	return 0;
+}
+EXPORT_SYMBOL(cxi_rmu_eth_remove_filter);
+
+/**
+ * cxi_rmu_eth_add_promiscuous_filter() - Enable promiscuous mode filter
+ * @rmu_eth: Resource handle
+ * @idx: Relative index within client's quota for this filter
+ * @pte: PTE pointer
+ * @use_rss: Whether promiscuous traffic participates in RSS
+ *
+ * Return: 0 on success, negative errno on error
+ */
+int cxi_rmu_eth_add_promiscuous_filter(struct cxi_rmu_eth *rmu_eth, unsigned int idx,
+				       struct cxi_pte *pte, bool use_rss)
+{
+	struct cxi_rmu_eth_priv *priv;
+	const union c_rmu_cfg_ptlte_set_list set_list = {
+		.frame_type = C_RMU_ENET_802_3,
+	};
+	const union c_rmu_cfg_ptlte_set_list set_list_mask = {
+		.qw = {
+			[2] = ~set_list.qw[2],
+			[3] = ~set_list.qw[3],
+		}
+	};
+
+	if (!rmu_eth || !pte)
+		return -EINVAL;
+
+	priv = container_of(rmu_eth, struct cxi_rmu_eth_priv, rmu_eth);
+
+	/* VF cannot enable promiscuous mode */
+	if (!priv->admin)
+		return -EPERM;
+
+	cxidev_dbg(priv->dev, "Add promiscuous RMU filter at idx=%u (hw_idx=%u) use_rss=%d\n",
+		   idx, priv->set_list_base + idx, use_rss);
+
+	/* Program hardware set_list filter */
+	return add_rmu_set_list_filter(priv, idx, pte, use_rss, &set_list, &set_list_mask);
+}
+EXPORT_SYMBOL(cxi_rmu_eth_add_promiscuous_filter);
+
+/**
+ * update_rss_filters() - Update set_ctrl for all RSS-enabled filters
+ * @priv: Private resource structure
+ * @enable: If true, enable RSS; if false, disable RSS
+ *
+ * Helper function to update set_ctrl entries for all filters that use RSS.
+ * This is called when changing RSS configuration or indirection table.
+ */
+static void update_rss_filters(struct cxi_rmu_eth_priv *priv, bool enable)
+{
+	struct cass_dev *hw = container_of(priv->dev, struct cass_dev, cdev);
+	unsigned int i;
+	struct c_rmu_cfg_ptlte_set_ctrl_table_entry set_ctrl = {};
+
+	if (enable && priv->rss_queues > 1) {
+		/* RSS enabled - configure indirection table */
+		set_ctrl.portal_index_indir_base = priv->indir_base;
+		set_ctrl.hash_bits = ilog2(priv->indir_entries);
+		set_ctrl.hash_types_enabled = priv->hash_types;
+	}
+	/* else: set_ctrl stays zero (direct portal mode); portal_index_indir_base
+	 * is set per-filter below */
+
+	/* Update all filters that use RSS */
+	for (i = 0; i < priv->set_list_quota; i++) {
+		if (priv->mac_filter_slots[i] == CXI_RMU_ETH_FILTER_RSS) {
+			unsigned int hw_idx = priv->set_list_base + i;
+
+			if (!enable || priv->rss_queues <= 1) {
+				/* Use direct portal */
+				set_ctrl.portal_index_indir_base = 2048 + hw_idx;
+			}
+
+			cass_config_set_ctrl(hw, hw_idx, &set_ctrl);
+		}
+	}
+}
+
+/**
+ * cxi_rmu_eth_set_rss_queues_vf() - Configure RSS queues (VF version)
+ * @rmu_eth: Resource handle
+ * @num_queues: Number of RSS queues
+ * @ptes: Array of PTE pointers
+ * @hash_types: Hash types to enable
+ *
+ * VF version: Sends set_rss_queues request to PF via vsock.
+ *
+ * Return: 0 on success, negative errno on error
+ */
+static int cxi_rmu_eth_set_rss_queues_vf(struct cxi_rmu_eth *rmu_eth,
+					 unsigned int num_queues,
+					 struct cxi_pte **ptes,
+					 u32 hash_types)
+{
+	struct cxi_rmu_eth_priv *priv = container_of(rmu_eth,
+						     struct cxi_rmu_eth_priv,
+						     rmu_eth);
+	struct cxi_rmu_eth_set_rss_queues_cmd cmd = {
+		.op = CXI_OP_RMU_ETH_SET_RSS_QUEUES,
+		.rmu_eth = rmu_eth->id,
+		.num_queues = num_queues,
+		.hash_types = hash_types,
+	};
+	size_t resp_len = 0;
+	unsigned int i;
+
+	if (num_queues > CXI_ETH_MAX_RSS_QUEUES)
+		return -EINVAL;
+
+	/* Copy PTE numbers into command */
+	for (i = 0; i < num_queues; i++)
+		cmd.ptes[i] = ptes[i]->id;
+
+	return cxi_send_msg_to_pf(priv->dev, &cmd, sizeof(cmd), NULL, &resp_len);
+}
+
+/**
+ * cxi_rmu_eth_set_rss_queues() - Configure RSS queues and hash types
+ * @rmu_eth: Resource handle
+ * @num_queues: Number of RSS queues (0-64, where 0 disables RSS)
+ * @ptes: Array of PTE pointers for RSS queues
+ * @hash_types: Hash types to enable
+ *
+ * Return: 0 on success, negative errno on error
+ */
+int cxi_rmu_eth_set_rss_queues(struct cxi_rmu_eth *rmu_eth,
+			       unsigned int num_queues,
+			       struct cxi_pte **ptes,
+			       u32 hash_types)
+{
+	struct cxi_rmu_eth_priv *priv = container_of(rmu_eth,
+						     struct cxi_rmu_eth_priv,
+						     rmu_eth);
+	struct cass_dev *hw = container_of(priv->dev, struct cass_dev, cdev);
+	unsigned int i;
+
+	if (!priv->dev->is_physfn)
+		return cxi_rmu_eth_set_rss_queues_vf(rmu_eth, num_queues, ptes,
+						     hash_types);
+
+	/* RSS requires at least 2 queues and non-zero hash types */
+	if (num_queues == 0 || num_queues == 1 || hash_types == 0) {
+		/* Disable RSS */
+		num_queues = 0;
+		hash_types = 0;
+	} else {
+		/* Validate RSS queue count */
+		if (num_queues > CXI_ETH_MAX_RSS_QUEUES)
+			return -EINVAL;
+
+		/* Store PTE pointers for RSS queues */
+		for (i = 0; i < num_queues; i++)
+			priv->ptes[i] = ptes[i];
+	}
+
+	/* Update default RSS configuration */
+	priv->rss_queues = num_queues;
+	priv->hash_types = hash_types;
+	priv->indir_entries = (num_queues > 1) ? priv->indir_size : 0;
+
+	/* Program indirection table with default round-robin */
+	spin_lock(&hw->rmu_lock);
+
+	/* Disable RSS filters before modifying indirection table */
+	update_rss_filters(priv, false);
+
+	if (num_queues > 1) {
+		for (i = 0; i < priv->indir_entries; i++) {
+			unsigned int queue_idx = ethtool_rxfh_indir_default(i, num_queues);
+			unsigned int portal_idx = ptes[queue_idx]->id;
+
+			cass_config_indir_entry(hw, priv->indir_base + i, portal_idx);
+		}
+
+		/* Re-enable RSS filters with new configuration */
+		update_rss_filters(priv, true);
+	}
+
+	spin_unlock(&hw->rmu_lock);
+
+	return 0;
+}
+EXPORT_SYMBOL(cxi_rmu_eth_set_rss_queues);
+
+/**
+ * cxi_rmu_eth_set_indir_table_vf() - Set custom traffic distribution (VF version)
+ * @rmu_eth: Resource handle
+ * @indir_table: Custom indirection table, or NULL for default
+ * @indir_size: Size of indirection table
+ *
+ * VF version: Sends set_indir_table request to PF via vsock.
+ *
+ * Return: 0 on success, negative errno on error
+ */
+static int cxi_rmu_eth_set_indir_table_vf(struct cxi_rmu_eth *rmu_eth,
+					  const u8 *indir_table,
+					  unsigned int indir_size)
+{
+	struct cxi_rmu_eth_priv *priv = container_of(rmu_eth,
+						     struct cxi_rmu_eth_priv,
+						     rmu_eth);
+	struct cxi_rmu_eth_set_indir_table_cmd *cmd;
+	size_t resp_len = 0;
+	int ret;
+
+	cmd = kzalloc(sizeof(*cmd), GFP_KERNEL);
+	if (!cmd)
+		return -ENOMEM;
+
+	cmd->op = CXI_OP_RMU_ETH_SET_INDIR_TABLE;
+	cmd->rmu_eth = rmu_eth->id;
+	cmd->indir_size = indir_size;
+
+	/* Copy indirection table if provided, NULL means use default (all zeros) */
+	if (indir_table && indir_size <= CXI_ETH_MAX_INDIR_ENTRIES)
+		memcpy(cmd->indir_table, indir_table, indir_size);
+
+	ret = cxi_send_msg_to_pf(priv->dev, cmd, sizeof(*cmd), NULL, &resp_len);
+	kfree(cmd);
+	return ret;
+}
+
+/**
+ * cxi_rmu_eth_set_indir_table() - Set custom traffic distribution weights
+ * @rmu_eth: Resource handle
+ * @indir_table: Custom indirection table, or NULL for default
+ * @indir_size: Size of indirection table (must be power of 2)
+ *
+ * Return: 0 on success, negative errno on error
+ */
+int cxi_rmu_eth_set_indir_table(struct cxi_rmu_eth *rmu_eth,
+				const u8 *indir_table, unsigned int indir_size)
+{
+	struct cxi_rmu_eth_priv *priv = container_of(rmu_eth,
+						     struct cxi_rmu_eth_priv,
+						     rmu_eth);
+	struct cass_dev *hw = container_of(priv->dev, struct cass_dev, cdev);
+	unsigned int i;
+
+	if (!priv->dev->is_physfn)
+		return cxi_rmu_eth_set_indir_table_vf(rmu_eth, indir_table, indir_size);
+
+	if (indir_size == 0 || !is_power_of_2(indir_size)) {
+		cxidev_err(priv->dev, "Invalid indirection table size %u (must be power of 2)\n",
+			   indir_size);
+		return -EINVAL;
+	}
+
+	if (priv->rss_queues == 0) {
+		cxidev_dbg(priv->dev,
+			   "Ignoring indirection table update while RSS is disabled (indir_size=%u)\n",
+			   indir_size);
+		return 0;
+	}
+
+	cxidev_dbg(priv->dev, "Setting up RSS indirection table: indir_size=%u\n", indir_size);
+
+	if (indir_size > priv->indir_size) {
+		cxidev_err(priv->dev, "Indirection table size %u exceeds allocated size %u\n",
+			   indir_size, priv->indir_size);
+		return -EINVAL;
+	}
+
+	/* Validate all queue indices before modifying hardware */
+	if (indir_table) {
+		for (i = 0; i < indir_size; i++) {
+			if (indir_table[i] >= priv->rss_queues) {
+				cxidev_err(priv->dev, "Invalid queue index %u in indirection table (max %u)\n",
+					   indir_table[i], priv->rss_queues - 1);
+				return -EINVAL;
+			}
+		}
+	}
+
+	/* Update active indirection table size */
+	priv->indir_entries = indir_size;
+
+	spin_lock(&hw->rmu_lock);
+
+	/* Disable hashing on all active filters before modifying indirection table */
+	update_rss_filters(priv, false);
+
+	/* Program the requested entries (custom or default) */
+	for (i = 0; i < indir_size; i++) {
+		unsigned int queue_idx;
+		unsigned int portal_idx;
+
+		if (!indir_table) {
+			/* Default round-robin */
+			queue_idx = ethtool_rxfh_indir_default(i, priv->rss_queues);
+		} else {
+			/* Custom table - already validated above */
+			queue_idx = indir_table[i];
+		}
+
+		portal_idx = priv->ptes[queue_idx]->id;
+		cass_config_indir_entry(hw, priv->indir_base + i, portal_idx);
+	}
+
+	/* Fill remaining entries with default round-robin to avoid stale values although
+	 * the HW would not be using them once we update the hash_bits */
+	for (i = indir_size; i < priv->indir_size; i++) {
+		unsigned int queue_idx = ethtool_rxfh_indir_default(i, priv->rss_queues);
+		unsigned int portal_idx = priv->ptes[queue_idx]->id;
+
+		cass_config_indir_entry(hw, priv->indir_base + i, portal_idx);
+	}
+
+	/* Re-enable hashing on all active filters */
+	update_rss_filters(priv, true);
+
+	spin_unlock(&hw->rmu_lock);
+
+	return 0;
+}
+EXPORT_SYMBOL(cxi_rmu_eth_set_indir_table);
+
+static void cxi_rmu_eth_get_hash_key_vf(struct cxi_dev *cdev, u8 *key)
+{
+	const struct cxi_rmu_eth_hash_key_get_cmd cmd = {
+		.op = CXI_OP_RMU_ETH_HASH_KEY_GET,
+	};
+	struct cxi_rmu_eth_get_hash_key_resp resp = {};
+	size_t resp_len = sizeof(resp);
+	int rc;
+
+	BUILD_BUG_ON(sizeof(resp.key) != CXI_ETH_HASH_KEY_SIZE);
+
+	rc = cxi_send_msg_to_pf(cdev, &cmd, sizeof(cmd), &resp, &resp_len);
+	if (rc) {
+		/* On error, zero out the key */
+		memset(key, 0, CXI_ETH_HASH_KEY_SIZE);
+		return;
+	}
+
+	memcpy(key, resp.key, CXI_ETH_HASH_KEY_SIZE);
+}
+
+/**
+ * cxi_rmu_eth_get_hash_key() - Retrieve the RSS hash key
+ *
+ * @cdev: CXI device
+ * @key: A sufficiently large (CXI_ETH_HASH_KEY_SIZE) array to store the key.
+ */
+void cxi_rmu_eth_get_hash_key(struct cxi_dev *cdev, u8 *key)
+{
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	union c_rmu_cfg_hash_key hash_key;
+
+	if (!cdev->is_physfn) {
+		cxi_rmu_eth_get_hash_key_vf(cdev, key);
+		return;
+	}
+
+	spin_lock(&hw->rmu_lock);
+	cass_read(hw, C_RMU_CFG_HASH_KEY, &hash_key, sizeof(hash_key));
+	spin_unlock(&hw->rmu_lock);
+
+	memcpy(key, hash_key.qw, CXI_ETH_HASH_KEY_SIZE);
+}
+EXPORT_SYMBOL(cxi_rmu_eth_get_hash_key);
diff --git a/drivers/net/ethernet/hpe/ss1/cass_rx_tx_profile.c b/drivers/net/ethernet/hpe/ss1/cass_rx_tx_profile.c
new file mode 100644
index 000000000000..23bf05c02bce
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_rx_tx_profile.c
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright (C) 2024 Hewlett Packard Enterprise Development LP */
+
+/* VNI Entry manipulation routines for Cassini Device */
+
+#include "cass_core.h"
+#include "cass_rx_tx_profile.h"
+
+#include "cxi_rxtx_profile.h"
+#include "cxi_rxtx_profile_list.h"
+
+static struct xa_limit    rx_profile_limits = {
+	.min = RX_PROFILE_ID_MIN,
+	.max = RX_PROFILE_ID_MAX,
+};
+
+static struct xa_limit    tx_profile_limits = {
+	.min = TX_PROFILE_ID_MIN,
+	.max = TX_PROFILE_ID_MAX,
+};
+
+/* **************************************************************** */
+/* Cassini device initialization and shutdown                       */
+/* **************************************************************** */
+
+/**
+ * cass_dev_rx_tx_profiles_init() - Create device structures to support
+ *                                  RX and TX Profile lists.
+ *
+ * @hw: The cassini device
+ */
+void cass_dev_rx_tx_profiles_init(struct cass_dev *hw)
+{
+	cxi_rxtx_profile_list_init(&hw->rx_profile_list,
+				   &rx_profile_limits,
+				   RX_PROFILE_XARRAY_FLAGS,
+				   RX_PROFILE_GFP_OPTS);
+
+	cxi_rxtx_profile_list_init(&hw->tx_profile_list,
+				   &tx_profile_limits,
+				   TX_PROFILE_XARRAY_FLAGS,
+				   TX_PROFILE_GFP_OPTS);
+
+	mutex_init(&hw->rx_profile_get_lock);
+	mutex_init(&hw->tx_profile_get_lock);
+}
+
+struct profile_destroy_data {
+	struct cxi_dev   *cxi_dev;
+};
+
+static void rx_profile_destroy(struct cxi_rxtx_profile *rxtx_profile,
+			       void *user_arg)
+{
+	struct profile_destroy_data *data = user_arg;
+
+	refcount_dec(&rxtx_profile->state.refcount);
+	cxi_rx_profile_dec_refcount(data->cxi_dev, co_rx_profile(rxtx_profile));
+}
+
+/**
+ * cass_dev_rx_tx_profiles_fini() - Destroy all RX and TX Profile entries
+ * associated with this device, as well as locks, etc.
+ *
+ * @hw: Cassini Device
+ */
+void cass_dev_rx_tx_profiles_fini(struct cass_dev *hw)
+{
+	struct profile_destroy_data  data;
+
+	data.cxi_dev = &hw->cdev;
+
+	cxi_rxtx_profile_list_destroy(&hw->rx_profile_list,
+				      rx_profile_destroy, &data);
+	cxi_tx_profile_list_destroy(hw);
+}
+
+/**
+ * cass_rx_profile_init() - initialize the hardware specific
+ *                                 part of the RX Profile
+ * @hw: Cassini device pointer
+ * @rx_profile: pointer to Profile
+ */
+void cass_rx_profile_init(struct cass_dev *hw,
+			  struct cxi_rx_profile *rx_profile)
+{
+	spin_lock_init(&rx_profile->config.pid_lock);
+	rx_profile->config.device = &hw->cdev;
+	rx_profile->config.rmu_index = DEF_RMU_INDEX;
+}
+
+/**
+ * cass_tx_profile_init() - initialize the hardware specific
+ *                                 part of the TX Profile
+ * @hw: Cassini device pointer
+ * @tx_profile: pointer to Profile
+ */
+void cass_tx_profile_init(struct cass_dev *hw,
+			  struct cxi_tx_profile *tx_profile)
+{
+	tx_profile->config.hw = hw;
+	idr_init(&tx_profile->config.cass_cp_table);
+	spin_lock_init(&tx_profile->config.lock);
+}

-- 
2.56.0


^ permalink raw reply	[flat|nested] 25+ messages in thread
* [PATCH 18/23] net: hpe: ss1: add the link layer glue
  2026-10-30 20:58 [PATCH 00/23] Subject: [PATCH net-next 00/23] net/hpe: add HPE Slingshot NIC drivers Doug Ledford
                   ` (16 preceding siblings ...)
  2026-10-30 20:59 ` [PATCH 17/23] net: hpe: ss1: add the datapath and memory translation layers Doug Ledford
@ 2026-10-30 20:59 ` Doug Ledford
  2026-10-30 20:59 ` [PATCH 19/23] net: hpe: ss1: add SR-IOV support Doug Ledford
                   ` (5 subsequent siblings)
  23 siblings, 0 replies; 25+ messages in thread
From: Doug Ledford @ 2026-10-30 20:59 UTC (permalink / raw)
  To: Slingshot Open Source Team, Nathan Chancellor, Nicolas Schier,
	Richard Cochran, Andrew Lunn, David S. Miller, Eric Dumazet,
	Jakub Kicinski, Paolo Abeni, Sumit Semwal, Christian König,
	Guenter Roeck
  Cc: linux-kernel, netdev, linux-kbuild, Doug Ledford, Sandeep Bhoot,
	Mamila Santosh

Add the glue between the core driver and the SBL and SL link layers,
the PHY and port helpers.

checkpatch --strict (100 columns) still reports the following in this
patch. They need coordination with the internal repositories this code
is maintained in and will be fixed in V2:
- WARNING: LONG_LINE (8), CONST_STRUCT (3), ALLOC_WITH_SIZEOF (2),
  BLOCK_COMMENT_STYLE (2)
- CHECK: UNNECESSARY_PARENTHESES (65), PARENTHESIS_ALIGNMENT (9),
  ALLOC_SIZEOF_STRUCT (1), BRACES (1)

Co-developed-by: Sandeep Bhoot <sandeep.bhoot@hpe.com>
Signed-off-by: Sandeep Bhoot <sandeep.bhoot@hpe.com>
Co-developed-by: Mamila Santosh <santosh-kumar.mamila@hpe.com>
Signed-off-by: Mamila Santosh <santosh-kumar.mamila@hpe.com>
Signed-off-by: Doug Ledford <doug.ledford@hpe.com>
---
 drivers/net/ethernet/hpe/ss1/cass_phy.c       |  224 ++++
 drivers/net/ethernet/hpe/ss1/cass_port_misc.c |   68 +
 drivers/net/ethernet/hpe/ss1/cass_sbl.c       | 1706 +++++++++++++++++++++++++
 drivers/net/ethernet/hpe/ss1/cass_sl.c        | 1524 ++++++++++++++++++++++
 drivers/net/ethernet/hpe/ss1/cass_sl_io.c     |  368 ++++++
 5 files changed, 3890 insertions(+)

diff --git a/drivers/net/ethernet/hpe/ss1/cass_phy.c b/drivers/net/ethernet/hpe/ss1/cass_phy.c
new file mode 100644
index 000000000000..beb5e2edf433
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_phy.c
@@ -0,0 +1,224 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2020-2021,2025 Hewlett Packard Enterprise Development LP */
+/* Cassini pseudo PHY interface
+ * Copy the interface from drivers/net/phy/phy.c
+ */
+
+#include <linux/debugfs.h>
+#include <linux/iopoll.h>
+#include <linux/hpe/cxi/cxi.h>
+
+#include "cass_core.h"
+#include "cass_sbl.h"
+#include <linux/hpe/sbl/sbl.h>
+
+/**
+ * cass_phy_is_started() - Convenience function to check whether PHY is started
+ *
+ * @hw: Cassini device.
+ */
+static bool cass_phy_is_started(struct cass_dev *hw)
+{
+	lockdep_assert_held(&hw->phy.lock);
+	return hw->phy.state >= CASS_PHY_UP;
+}
+
+bool cass_phy_is_headshell_removed(struct cass_dev *hw)
+{
+	return hw->phy.state == CASS_PHY_HEADSHELL_REMOVED;
+}
+
+void cass_phy_set_state(enum cass_phy_state state, struct cass_dev *hw)
+{
+	spin_lock(&hw->phy.lock);
+	hw->phy.state = state;
+	hw->phy.generation++;
+	spin_unlock(&hw->phy.lock);
+}
+
+static void cass_phy_set_up_unless_removed(struct cass_dev *hw)
+{
+	lockdep_assert_held(&hw->phy.lock);
+	if (hw->phy.state != CASS_PHY_HEADSHELL_REMOVED)
+		hw->phy.state = CASS_PHY_UP;
+}
+
+static void cass_phy_queue_locked(struct cass_dev *hw, unsigned long delay)
+{
+	if (hw->phy.stopped || !cass_phy_is_started(hw))
+		return;
+
+	if (!(work_busy(&hw->phy.state_queue.work) & WORK_BUSY_PENDING))
+		mod_delayed_work(system_power_efficient_wq, &hw->phy.state_queue, delay);
+}
+
+static void cass_phy_queue_state_machine(struct cass_dev *hw,
+					 unsigned long delay)
+{
+	spin_lock(&hw->phy.lock);
+	cass_phy_queue_locked(hw, delay);
+	spin_unlock(&hw->phy.lock);
+}
+
+void cass_phy_trigger_machine(struct cass_dev *hw)
+{
+	cass_phy_queue_state_machine(hw, 0);
+}
+
+void cass_phy_link_up(struct cass_dev *hw)
+{
+	cxidev_warn(&hw->cdev, "CXI_EVENT_LINK_UP");
+	update_hni_link_up(hw);
+	update_oxe_link_up(hw);
+	cass_set_outstanding_limit(hw);
+	cxi_send_async_event(&hw->cdev, CXI_EVENT_LINK_UP);
+}
+
+void cass_phy_link_down(struct cass_dev *hw)
+{
+	cxidev_warn(&hw->cdev, "CXI_EVENT_LINK_DOWN");
+	cxi_send_async_event(&hw->cdev, CXI_EVENT_LINK_DOWN);
+}
+
+static void cass_phy_check_link_status(struct cass_dev *hw,
+				       unsigned int generation)
+{
+	bool up = cass_link_get_state(hw) == CASS_LINK_STATUS_UP;
+	enum cass_phy_state target = up ? CASS_PHY_RUNNING : CASS_PHY_NOLINK;
+	bool changed = false;
+
+	/* TODO - phy.state and lstate duplicate one another */
+	spin_lock(&hw->phy.lock);
+	/* A stop, start or cable transition since the sample supersedes it */
+	if (!hw->phy.stopped && hw->phy.generation == generation &&
+	    hw->phy.state != target) {
+		hw->phy.state = target;
+		changed = true;
+	}
+	spin_unlock(&hw->phy.lock);
+
+	if (!changed)
+		return;
+
+	if (up)
+		cass_phy_link_up(hw);
+	else
+		cass_phy_link_down(hw);
+}
+
+/* cass_phy_start_aneg - start auto-negotiation for the device */
+static void cass_phy_start_aneg(struct cass_dev *hw, unsigned int generation)
+{
+	cass_lmon_request_up(hw);
+	cass_phy_check_link_status(hw, generation);
+}
+
+static void cass_phy_state_machine(struct work_struct *work)
+{
+	struct delayed_work *dwork = to_delayed_work(work);
+	struct cass_dev *hw =
+		container_of(dwork, struct cass_dev, phy.state_queue);
+	enum cass_phy_state old_state;
+	enum cass_phy_state new_state;
+	unsigned int generation;
+	bool needs_aneg = false;
+
+	spin_lock(&hw->phy.lock);
+	if (hw->phy.stopped) {
+		spin_unlock(&hw->phy.lock);
+		return;
+	}
+	old_state = hw->phy.state;
+	generation = hw->phy.generation;
+	spin_unlock(&hw->phy.lock);
+
+	switch (old_state) {
+	case CASS_PHY_DOWN:
+	case CASS_PHY_READY:
+	case CASS_PHY_HEADSHELL_REMOVED:
+		break;
+
+	case CASS_PHY_UP:
+		needs_aneg = true;
+		break;
+
+	case CASS_PHY_NOLINK:
+	case CASS_PHY_RUNNING:
+		cass_lmon_request_up(hw);
+		cass_phy_check_link_status(hw, generation);
+		break;
+	case CASS_PHY_HALTED:
+		if (cass_link_get_state(hw) == CASS_LINK_STATUS_UP)
+			cass_phy_link_down(hw);
+		break;
+	}
+
+	if (needs_aneg)
+		cass_phy_start_aneg(hw, generation);
+
+	spin_lock(&hw->phy.lock);
+	new_state = hw->phy.state;
+	if (new_state != CASS_PHY_RUNNING)
+		cass_phy_queue_locked(hw, HZ);
+	spin_unlock(&hw->phy.lock);
+
+	if (old_state != new_state)
+		cxidev_dbg(&hw->cdev, "PHY state change %d -> %d\n",
+			   old_state, new_state);
+}
+
+void cass_phy_init(struct cass_dev *hw)
+{
+	spin_lock_init(&hw->phy.lock);
+	INIT_DELAYED_WORK(&hw->phy.state_queue, cass_phy_state_machine);
+}
+
+void cass_phy_bounce(struct cass_dev *hw)
+{
+	cass_phy_stop(hw, true);
+	cass_phy_start(hw, false);
+}
+
+void cass_phy_start(struct cass_dev *hw, bool force_reconfig)
+{
+	if (hw->link_config_dirty || force_reconfig)
+		cass_sbl_configure(hw);
+
+	/* Start the PHY directly in UP mode */
+	spin_lock(&hw->phy.lock);
+	hw->phy.stopped = false;
+	hw->phy.generation++;
+	cass_phy_set_up_unless_removed(hw);
+	cass_phy_queue_locked(hw, 0);
+	spin_unlock(&hw->phy.lock);
+}
+
+void cass_phy_stop(struct cass_dev *hw, bool block)
+{
+	int err;
+
+	spin_lock(&hw->phy.lock);
+	hw->phy.stopped = true;
+	hw->phy.generation++;
+	spin_unlock(&hw->phy.lock);
+
+	cancel_delayed_work_sync(&hw->phy.state_queue);
+
+	spin_lock(&hw->phy.lock);
+	if (cass_phy_is_started(hw))
+		cass_phy_set_up_unless_removed(hw);
+	spin_unlock(&hw->phy.lock);
+
+	if (!block)
+		err = cass_lmon_request_down(hw);
+	else
+		err = cass_link_async_down_wait(hw, CASS_DOWN_ORIGIN_CONFIG);
+
+	if (err || (cass_link_get_state(hw) == CASS_LINK_STATUS_ERROR)) {
+		cass_link_async_reset_wait(hw, CASS_DOWN_ORIGIN_CONFIG);
+		cass_sbl_configure(hw);
+		spin_lock(&hw->phy.lock);
+		cass_phy_set_up_unless_removed(hw);
+		spin_unlock(&hw->phy.lock);
+	}
+}
diff --git a/drivers/net/ethernet/hpe/ss1/cass_port_misc.c b/drivers/net/ethernet/hpe/ss1/cass_port_misc.c
new file mode 100644
index 000000000000..0d01985d1741
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_port_misc.c
@@ -0,0 +1,68 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2020 Hewlett Packard Enterprise Development LP */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/device.h>
+#include <linux/hpe/sbl/sbl.h>
+
+#include "cass_core.h"
+
+/*
+ * create and initialise the port array
+ */
+int cass_port_new_port_db(struct cass_dev *hw)
+{
+	hw->port = kzalloc(sizeof(struct cass_port), GFP_KERNEL);
+	if (!hw->port)
+		return -ENOMEM;
+
+	spin_lock_init(&hw->port->lock);
+	hw->port->lstate = CASS_LINK_STATUS_UNCONFIGURED;
+	init_waitqueue_head(&hw->port->lmon_wq);
+	spin_lock_init(&hw->port->pause_lock);
+	hw->port->pause_type = CASS_PAUSE_TYPE_NONE;
+	hw->port->tx_pause = false;
+	hw->port->rx_pause = false;
+	hw->port->lmon_counters = NULL;
+	hw->port->start_time = 0;
+	cass_lmon_counters_init(hw);
+
+	return 0;
+}
+
+void cass_port_del_port_db(struct cass_dev *hw)
+{
+	if (hw->port) {
+		cass_lmon_kill_all(hw);
+		cass_lmon_counters_term(hw);
+		kfree(hw->port);
+		hw->port = NULL;
+	}
+}
+
+/*
+ * text output helpers
+ */
+const char *cass_port_subtype_str(enum cass_port_subtype subtype)
+{
+	switch (subtype) {
+	case CASS_PORT_SUBTYPE_IEEE:    return "ieee";
+	case CASS_PORT_SUBTYPE_CASSINI: return "cassini";
+	case CASS_PORT_SUBTYPE_LOCAL:   return "local";
+	case CASS_PORT_SUBTYPE_GLOBAL:  return "global";
+	default:                        return "unknown";
+	}
+}
+
+const char *cass_pause_type_str(enum cass_pause_type type)
+{
+	switch (type) {
+	case CASS_PAUSE_TYPE_INVALID: return "invalid";
+	case CASS_PAUSE_TYPE_NONE:    return "none";
+	case CASS_PAUSE_TYPE_GLOBAL:  return "global/802.3x";
+	case CASS_PAUSE_TYPE_PFC:     return "pfc/802.1qbb";
+	default:                      return "unrecognised";
+	}
+}
diff --git a/drivers/net/ethernet/hpe/ss1/cass_sbl.c b/drivers/net/ethernet/hpe/ss1/cass_sbl.c
new file mode 100644
index 000000000000..3b39e917fd5a
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_sbl.c
@@ -0,0 +1,1706 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Cassini device handler
+ * Copyright 2020-2024 Hewlett Packard Enterprise Development LP
+ */
+
+#include <linux/iopoll.h>
+#include <linux/hpe/cxi/cxi.h>
+#include <linux/hpe/sbl/sbl_mb.h>
+#include <linux/hpe/sbl/sbl.h>
+#include <uapi/ethernet/sbl-abi.h>
+#include <uapi/ethernet/sbl_cassini.h>
+
+#include "cass_core.h"
+#include "cass_cable.h"
+#include "cxi_ethtool.h"
+#include "cass_ss1_debugfs.h"
+
+#define SYSFS_BUFSIZE        1000
+
+static unsigned int pml_rec_timeout = SBL_DFLT_PML_REC_TIMEOUT;
+module_param(pml_rec_timeout, uint, 0644);
+MODULE_PARM_DESC(pml_rec_timeout, "PML recovery timeout in ms");
+
+static unsigned int pml_rec_rl_max_dur = SBL_DFLT_PML_REC_RL_MAX_DURATION;
+module_param(pml_rec_rl_max_dur, uint, 0644);
+MODULE_PARM_DESC(pml_rec_rl_max_dur, "PML recovery max time in ms per window");
+
+static unsigned int pml_rec_rl_win_size = SBL_DFLT_PML_REC_RL_WINDOW_SIZE;
+module_param(pml_rec_rl_win_size, uint, 0644);
+MODULE_PARM_DESC(pml_rec_rl_win_size, "PML recovery rate limiter window in ms");
+
+/**
+ * cass_sbl_link_attr_cmp() - Check if input attr matches device attr
+ *
+ *  Checks each member of input cass_link_attr against value stored in
+ *  device. If any values differ, return -1, else return 0.
+ *
+ * @hw: the device
+ * @tgt_val: comparison values
+ *
+ * Return: 0 on if the structs are the same, else -1
+ */
+static int cass_sbl_link_attr_cmp(const struct cass_dev *hw,
+				  const struct cass_link_attr *tgt_val)
+{
+	const struct cass_port *port = hw->port;
+
+	if ((tgt_val->options != port->lattr.options) ||
+	    (tgt_val->bl.options != port->lattr.bl.options) ||
+	    (tgt_val->bl.magic != port->lattr.bl.magic) ||
+	    (tgt_val->bl.start_timeout != port->lattr.bl.start_timeout) ||
+	    (tgt_val->bl.config_target != port->lattr.bl.config_target) ||
+	    (tgt_val->bl.pec.an_mode != port->lattr.bl.pec.an_mode) ||
+	    (tgt_val->bl.pec.an_retry_timeout != port->lattr.bl.pec.an_retry_timeout) ||
+	    (tgt_val->bl.pec.an_max_retry != port->lattr.bl.pec.an_max_retry) ||
+	    (tgt_val->bl.lpd_timeout != port->lattr.bl.lpd_timeout) ||
+	    (tgt_val->bl.lpd_poll_interval != port->lattr.bl.lpd_poll_interval) ||
+	    (tgt_val->bl.link_mode != port->lattr.bl.link_mode) ||
+	    (tgt_val->bl.loopback_mode != port->lattr.bl.loopback_mode) ||
+	    (tgt_val->bl.link_partner != port->lattr.bl.link_partner) ||
+	    (tgt_val->bl.tuning_pattern != port->lattr.bl.tuning_pattern) ||
+	    (tgt_val->bl.precoding != port->lattr.bl.precoding) ||
+	    (tgt_val->bl.dfe_pre_delay != port->lattr.bl.dfe_pre_delay) ||
+	    (tgt_val->bl.dfe_timeout != port->lattr.bl.dfe_timeout) ||
+	    (tgt_val->bl.dfe_poll_interval != port->lattr.bl.dfe_poll_interval) ||
+	    (tgt_val->bl.pcal_eyecheck_holdoff != port->lattr.bl.pcal_eyecheck_holdoff) ||
+	    (tgt_val->bl.nrz_min_eye_height != port->lattr.bl.nrz_min_eye_height) ||
+	    (tgt_val->bl.nrz_max_eye_height != port->lattr.bl.nrz_max_eye_height) ||
+	    (tgt_val->bl.pam4_min_eye_height != port->lattr.bl.pam4_min_eye_height) ||
+	    (tgt_val->bl.pam4_max_eye_height != port->lattr.bl.pam4_max_eye_height) ||
+	    (tgt_val->bl.fec_mode != port->lattr.bl.fec_mode) ||
+	    (tgt_val->bl.enable_autodegrade != port->lattr.bl.enable_autodegrade) ||
+	    (tgt_val->bl.llr_mode != port->lattr.bl.llr_mode) ||
+	    (tgt_val->bl.ifg_config != port->lattr.bl.ifg_config) ||
+	    (tgt_val->bl.pml_recovery.timeout != port->lattr.bl.pml_recovery.timeout) ||
+	    (tgt_val->bl.pml_recovery.rl_max_duration !=
+		port->lattr.bl.pml_recovery.rl_max_duration) ||
+	    (tgt_val->bl.pml_recovery.rl_window_size !=
+		port->lattr.bl.pml_recovery.rl_window_size))
+		return -1;
+
+	return 0;
+}
+
+/* Initializes the sbl module. */
+int cass_sbl_link_start(struct cass_dev *hw)
+{
+	int ret;
+	int fini_rtn;
+
+	cxidev_dbg(&hw->cdev, "initializing SBL...\n");
+
+	ret = cass_port_new_port_db(hw);
+	if (ret) {
+		cxidev_err(&hw->cdev, "cass_port_new_port_db failed [%d]\n", ret);
+		goto out;
+	}
+
+	ret = hw->link_ops->init(hw);
+	if (ret != 0) {
+		cxidev_err(&hw->cdev, "init failed [%d]\n", ret);
+		goto out_ports;
+	}
+
+	hw->port->hstate = CASS_HEADSHELL_STATUS_NOT_PRESENT;
+
+	ret = cass_lmon_start_all(hw);
+	if (ret) {
+		cxidev_err(&hw->cdev, "cass_lmon_start_all failed [%d]\n", ret);
+		goto out_sbl;
+	}
+
+	ret = cass_cable_scan(hw);
+	if (ret) {
+		cxidev_err(&hw->cdev, "cass_cable_scan failed [%d]\n", ret);
+		goto out_lmon;
+	}
+
+	cass_sbl_set_defaults(hw);
+	ret = cass_sbl_configure(hw);
+	if (ret != 0) {
+		cxidev_err(&hw->cdev, "cass_sbl_configure failed [%d]\n", ret);
+		goto out_lmon;
+	}
+	cxidev_dbg(&hw->cdev, "SBL initialized\n");
+
+	return 0;
+
+out_lmon:
+	cass_lmon_kill_all(hw);
+out_sbl:
+	fini_rtn = hw->link_ops->link_fini(hw);
+	if (fini_rtn) {
+		WARN(1, "SBL link teardown failed during startup unwind: %d\n", fini_rtn);
+		return fini_rtn;
+	}
+out_ports:
+	cass_port_del_port_db(hw);
+out:
+	return ret;
+}
+
+int cass_sbl_link_fini(struct cass_dev *hw)
+{
+	int err;
+
+	if (hw->port_kobj.state_in_sysfs)
+		kobject_del(&hw->port_kobj);
+	cass_lmon_kill_all(hw);
+	err = cass_sbl_exit(hw);
+	if (err)
+		return err;
+	cass_port_del_port_db(hw);
+	return 0;
+}
+
+/* getters/setters follow */
+
+/**
+ * cass_sbl_mode_set() - Setter for various link configuration options
+ *
+ * Updates the cass_dev cass_link_attr with the target value.
+ * If there are any differences between the requested config and the
+ * running config, the link will be torn down and brought back up with
+ * the new config.
+ *
+ * @hw: the device
+ * @link_info: CXI ethtool private flags
+ */
+void cass_sbl_mode_set(struct cass_dev *hw, const struct cxi_link_info *link_info)
+{
+	struct cass_link_attr attrs = hw->port->lattr;
+
+	switch (link_info->flags & LOOPBACK_MODE) {
+	case 0:
+		attrs.bl.loopback_mode = SBL_LOOPBACK_MODE_OFF;
+		break;
+	case CXI_ETH_PF_INTERNAL_LOOPBACK:
+		attrs.bl.loopback_mode = SBL_LOOPBACK_MODE_LOCAL;
+		break;
+	case CXI_ETH_PF_EXTERNAL_LOOPBACK:
+		attrs.bl.loopback_mode = SBL_LOOPBACK_MODE_REMOTE;
+		break;
+	default:
+		/* Invalid configuration, no change */
+		break;
+	}
+
+	if (link_info->flags & CXI_ETH_PF_LLR)
+		attrs.bl.llr_mode = SBL_LLR_MODE_ON;
+	else
+		attrs.bl.llr_mode = SBL_LLR_MODE_OFF;
+
+	if (link_info->flags & CXI_ETH_PF_PRECODING)
+		attrs.bl.precoding = SBL_PRECODING_ON;
+	else
+		attrs.bl.precoding = SBL_PRECODING_OFF;
+
+	if (link_info->flags & CXI_ETH_PF_IFG_HPC)
+		attrs.bl.ifg_config = SBL_IFG_CONFIG_HPC;
+	else
+		attrs.bl.ifg_config = SBL_IFG_CONFIG_IEEE_200G;
+
+	if (link_info->flags & CXI_ETH_PF_PML_REC)
+		attrs.bl.options |= SBL_DISABLE_PML_RECOVERY;
+	else
+		attrs.bl.options &= ~SBL_DISABLE_PML_RECOVERY;
+
+	if (attrs.mattr.media != SBL_LINK_MEDIA_OPTICAL) {
+		if (link_info->autoneg == AUTONEG_DISABLE)
+			attrs.bl.pec.an_mode = SBL_AN_MODE_OFF;
+		else
+			attrs.bl.pec.an_mode = SBL_AN_MODE_ON;
+	}
+
+	if (!cass_sbl_link_attr_cmp(hw, &attrs))
+		hw->link_config_dirty = false;
+	else
+		hw->link_config_dirty = true;
+
+	if (hw->link_config_dirty) {
+		hw->port->lattr = attrs;
+		/* Bounce the link to apply the new config */
+		cass_phy_bounce(hw);
+	}
+}
+
+void cass_sbl_pml_recovery_set(struct cass_dev *hw, bool set)
+{
+	sbl_disable_pml_recovery(hw->sbl, 0, set);
+}
+
+/**
+ * cass_sbl_mode_get() - Getter for various link configuration options
+ *
+ * Updates the input tgt_val with the cass_dev cass_link_attr contents.
+ *
+ * @hw: the device
+ * @link_info: location to write cass_link_attr struct
+ */
+void cass_sbl_mode_get(struct cass_dev *hw, struct cxi_link_info *link_info)
+{
+	const struct cass_link_attr *attrs = &hw->port->lattr;
+	int sstate;
+	int blstate;
+	int link_mode;
+
+	memset(link_info, 0, sizeof(*link_info));
+
+	sbl_base_link_get_status(hw->sbl, 0, &blstate,
+				 NULL, &sstate, NULL, NULL, &link_mode);
+
+	switch (blstate) {
+	case SBL_BASE_LINK_STATUS_UNKNOWN:
+	case SBL_BASE_LINK_STATUS_UNCONFIGURED:
+	case SBL_BASE_LINK_STATUS_RESETTING:
+	case SBL_BASE_LINK_STATUS_ERROR:
+		link_info->speed = SPEED_UNKNOWN;
+		break;
+	default:
+		switch (sstate) {
+		case SBL_SERDES_STATUS_UNKNOWN:
+		case SBL_SERDES_STATUS_RESETTING:
+		case SBL_SERDES_STATUS_ERROR:
+			link_info->speed = SPEED_UNKNOWN;
+			break;
+		default:
+			cass_sbl_link_mode_to_speed(link_mode, &link_info->speed);
+		}
+	}
+
+	if (attrs->bl.loopback_mode == SBL_LOOPBACK_MODE_LOCAL)
+		link_info->flags |= CXI_ETH_PF_INTERNAL_LOOPBACK;
+	else if (attrs->bl.loopback_mode == SBL_LOOPBACK_MODE_REMOTE)
+		link_info->flags |= CXI_ETH_PF_EXTERNAL_LOOPBACK;
+
+	if (attrs->bl.llr_mode == SBL_LLR_MODE_ON)
+		link_info->flags |= CXI_ETH_PF_LLR;
+
+	if (attrs->bl.precoding == SBL_PRECODING_ON)
+		link_info->flags |= CXI_ETH_PF_PRECODING;
+
+	if (attrs->bl.ifg_config == SBL_IFG_CONFIG_HPC)
+		link_info->flags |= CXI_ETH_PF_IFG_HPC;
+
+	if (attrs->bl.options & SBL_DISABLE_PML_RECOVERY)
+		link_info->flags |= CXI_ETH_PF_PML_REC;
+
+	if (attrs->mattr.media != SBL_LINK_MEDIA_OPTICAL) {
+		if (attrs->bl.pec.an_mode == SBL_AN_MODE_OFF)
+			link_info->autoneg = AUTONEG_DISABLE;
+		else
+			link_info->autoneg = AUTONEG_ENABLE;
+	}
+
+	switch (attrs->mattr.media) {
+	case SBL_LINK_MEDIA_ELECTRICAL:
+		link_info->port_type = PORT_DA;
+		break;
+	case SBL_LINK_MEDIA_OPTICAL:
+		link_info->port_type = PORT_FIBRE;
+		break;
+	default:
+		link_info->port_type = PORT_OTHER;
+		break;
+	}
+}
+
+/**
+ * cass_sbl_get_debug_flags() - Getter for debug flags
+ *
+ * Updates the input flags with the current debug flags.
+ *
+ * @hw: the device
+ * @debug_flags: storage for private CXI flags (CXI_ETH_PF_xxx)
+ */
+void cass_sbl_get_debug_flags(struct cass_dev *hw, u32 *debug_flags)
+{
+	u32 flags;
+
+	sbl_debug_get_config(hw->sbl, 0, &flags);
+
+	*debug_flags = 0;
+
+	if (flags & SBL_DEBUG_IGNORE_ALIGN)
+		*debug_flags |= CXI_ETH_PF_IGNORE_ALIGN;
+
+	if (flags & SBL_DEBUG_REMOTE_FAULT_RECOVERY)
+		*debug_flags |= CXI_ETH_PF_REMOTE_FAULT_RECOVERY;
+}
+
+/**
+ * cass_sbl_set_debug_flags() - Setter for debug flags
+ *
+ * Updates the debug flags.
+ *
+ * @hw: the device
+ * @clr_flags: desired clear flags
+ * @set_flags: desired set flags
+ */
+void cass_sbl_set_debug_flags(struct cass_dev *hw, u32 clr_flags, u32 set_flags)
+{
+	u32 clr_flags_sbl = 0;
+	u32 set_flags_sbl = 0;
+
+	if (clr_flags & CXI_ETH_PF_IGNORE_ALIGN)
+		clr_flags_sbl |= SBL_DEBUG_IGNORE_ALIGN;
+
+	if (set_flags & CXI_ETH_PF_IGNORE_ALIGN)
+		set_flags_sbl |= SBL_DEBUG_IGNORE_ALIGN;
+
+	if (clr_flags & CXI_ETH_PF_REMOTE_FAULT_RECOVERY)
+		clr_flags_sbl |= SBL_DEBUG_REMOTE_FAULT_RECOVERY;
+
+	if (set_flags & CXI_ETH_PF_REMOTE_FAULT_RECOVERY)
+		set_flags_sbl |= SBL_DEBUG_REMOTE_FAULT_RECOVERY;
+
+	sbl_debug_update_config(hw->sbl, 0, clr_flags_sbl, set_flags_sbl);
+}
+
+/* Return whether the link is up or down. */
+bool cass_sbl_is_link_up(struct cass_dev *hw)
+{
+	enum cass_link_status state = cass_link_get_state(hw);
+
+	return state == CASS_LINK_STATUS_UP;
+}
+
+/* sbl_ops follow */
+/**
+ * cass_read64() - wrapper around Cassini read function
+ *
+ * Read a CSR on BAR0.
+ *
+ * @pci_accessor: the SBL device
+ * @offset: offset of the CSR in the region
+ *
+ * Return: u64 containing the read result
+ */
+static u64 cass_read64(void *pci_accessor, long offset)
+{
+	struct cass_dev *hw = (struct cass_dev *)pci_accessor;
+	size_t len = sizeof(u64);
+	u64 data_out;
+
+	cass_read(hw, (u64)offset, &data_out, len);
+
+	return data_out;
+}
+
+/**
+ * cass_write64() - wrapper around Cassini write function
+ *
+ * Modify a control status register (CSR) on BAR0.
+ *
+ * @pci_accessor: the SBL device
+ * @offset: offset of the CSR in the region
+ * @val: data to write
+ */
+static void cass_write64(void *pci_accessor, long offset, u64 val)
+{
+	struct cass_dev *hw = (struct cass_dev *)pci_accessor;
+	size_t len = sizeof(u64);
+
+	cass_write(hw, (u64)offset, &val, len);
+}
+
+/**
+ * cass_read32() - wrapper around Cassini 64-bit read function
+ *
+ * Read a CSR on BAR0.
+ *
+ * @pci_accessor: the SBL device
+ * @offset: offset of the CSR in the region
+ *
+ * Return: u32 containing the read result
+ */
+static u32 cass_read32(void *pci_accessor, long offset)
+{
+	struct cass_dev *hw = (struct cass_dev *)pci_accessor;
+	size_t len = sizeof(u64);
+	u64 data_out;
+
+	cass_read(hw, (u64)offset, &data_out, len);
+
+	/* Explicit loss of precision here - Cassini doe not have 32-bit CSRs.
+	 *  CSRs which are described as 32 bits can be read/written
+	 *  Using the 64-bit access functions.
+	 */
+	return (u32)data_out;
+}
+
+/**
+ * cass_write32() - wrapper around Cassini 64-bit write function
+ *
+ * Modify a control status register (CSR) on BAR0.
+ *
+ * @pci_accessor: the SBL device
+ * @offset: offset of the CSR in the region
+ * @val: data to write
+ */
+static void cass_write32(void *pci_accessor, long offset, u32 val)
+{
+	struct cass_dev *hw = (struct cass_dev *)pci_accessor;
+	size_t len = sizeof(u64);
+	u64 wval = 0;
+
+	/* Explicit loss of precision here - Cassini doe not have 32-bit CSRs.
+	 *  CSRs which are described as 32 bits can be read/written
+	 *  Using the 64-bit access functions.
+	 */
+	wval |= val;
+	cass_write(hw, (u64)offset, &wval, len);
+}
+
+static bool cass_sbl_is_fabric_link(void *accessor, int port_num)
+{
+	return false;
+}
+
+/**
+ * cass_sbl_get_max_frame_size() - Get MTU
+ *
+ * Return the MTU value from the cxi_dev
+ *
+ * @accessor: the SBL device
+ * @port_num: unused
+ *
+ * Return: int containing the MTU
+ */
+static int cass_sbl_get_max_frame_size(void *accessor, int port_num)
+{
+	struct cass_dev *hw = (struct cass_dev *)accessor;
+	u32 size = C_MAX_HPC_MTU;
+
+	/* SBL uses MTU to set LLR buffer size. Use the largest of the fixed
+	 * HPC frame size and configurable Ethernet (standard or optimized)
+	 * frame size(s).
+	 */
+	if (hw->max_eth_rxsize > size)
+		size = hw->max_eth_rxsize;
+
+	cxidev_dbg(&hw->cdev, "sbl get_max_frame_size returning %u\n", size);
+
+	return size;
+}
+
+/**
+ * cass_sbl_pml_hdlr() - The PML block intr handler
+ *
+ * This just calls into the sbl block handler, which determines the irq itself
+ *
+ * @hw: the device
+ * @irq: unused
+ * @is_ext: unused
+ * @bitn: unused
+ */
+static void cass_sbl_pml_hdlr(struct cass_dev *hw, unsigned int irq,
+			      bool is_ext, unsigned int bitn)
+{
+	int err;
+
+	err = sbl_pml_hdlr(hw->sbl, 0, NULL);
+	if (err)
+		cxidev_err(&hw->cdev, "(sbl): call to sbl_pml_hdl failed [%d]\n",
+			   err);
+}
+
+/**
+ * cass_sbl_pml_install_intr_handler() - Installs the PML block intr handler
+ *
+ * Wrapper around the Cassini IRQ registration function
+ *
+ * @accessor: the SBL device
+ * @port_num: unused
+ * @err_flags: bitmask of interrupts to enable
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+static int cass_sbl_pml_install_intr_handler(void *accessor, int port_num,
+					     u64 err_flags)
+{
+	struct cass_dev *hw = (struct cass_dev *)accessor;
+
+	cxidev_dbg(&hw->cdev, "(sbl): installing intr handlers\n");
+
+	hw->pml_err.irq = C_HNI_PML_IRQA_MSIX_INT;
+	hw->pml_err.is_ext = false;
+	hw->pml_err.err_flags.c1_hni_pml.qw = err_flags;
+	hw->pml_err.cb = cass_sbl_pml_hdlr;
+	cxi_register_hw_errors(hw, &hw->pml_err);
+
+	return 0;
+}
+
+/**
+ * cass_sbl_pml_enable_intr_handler() - Enable bits in PML block intr handler
+ *
+ * Wrapper around the Cassini IRQ enable function
+ *
+ * @accessor: the SBL device
+ * @port_num: unused
+ * @err_flags: bitmask of interrupts to enable
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+static int cass_sbl_pml_enable_intr_handler(void *accessor, int port_num,
+					    u64 err_flags)
+{
+	struct cass_dev *hw = (struct cass_dev *)accessor;
+	unsigned int irq = C_HNI_PML_IRQA_MSIX_INT;
+	bool is_ext = false;
+
+	cxidev_dbg(&hw->cdev, "(sbl): enabling intr handler\n");
+	cxi_enable_hw_errors(hw, irq, is_ext, (unsigned long *)&err_flags);
+
+	return 0;
+}
+
+/**
+ * cass_sbl_pml_remove_intr_handler() - Remove PML block intr handler
+ *
+ * Wrapper around the Cassini IRQ unregister function
+ *
+ * @accessor: the SBL device
+ * @port_num: unused
+ * @err_flags: unused
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+static int cass_sbl_pml_remove_intr_handler(void *accessor, int port_num,
+					    u64 err_flags)
+{
+	struct cass_dev *hw = (struct cass_dev *)accessor;
+
+	cxidev_dbg(&hw->cdev, "(sbl): removing intr handlers\n");
+	cxi_unregister_hw_errors(hw, &hw->pml_err);
+
+	return 0;
+}
+
+/**
+ * cass_sbl_pml_disable_intr_handler() - Disable bits in PML block intr handler
+ *
+ * Wrapper around the Cassini IRQ disable function
+ *
+ * @accessor: the SBL device
+ * @port_num: unused
+ * @err_flags: bitmask of interrupts to disable
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+static int cass_sbl_pml_disable_intr_handler(void *accessor, int port_num,
+					     u64 err_flags)
+{
+	struct cass_dev *hw = (struct cass_dev *)accessor;
+	unsigned int irq = C_HNI_PML_IRQA_MSIX_INT;
+	bool is_ext = false;
+
+	cxidev_dbg(&hw->cdev, "(sbl): disabling intr handler\n");
+	cxi_disable_hw_errors(hw, irq, is_ext, (unsigned long *)&err_flags);
+
+	return 0;
+}
+
+/**
+ * cass_sbl_link_down_async_handler() - link down handler
+ *
+ * Handler function called by the SBL async alert if the alert type is
+ * a link down event
+ *
+ * @hw: Cassini device
+ * @port_num: unused
+ * @down_origin: one of enum sbl_link_down_origin
+ */
+static void cass_sbl_link_down_async_handler(struct cass_dev *hw, int port_num,
+					     int down_origin)
+{
+	int down_reason;
+
+	cxidev_dbg(&hw->cdev, "(sbl): async link down\n");
+
+	switch (down_origin) {
+	case SBL_LINK_DOWN_ORIGIN_LOCAL_FAULT:
+		down_reason = CASS_DOWN_ORIGIN_BL_LFAULT;
+		break;
+	case SBL_LINK_DOWN_ORIGIN_REMOTE_FAULT:
+		down_reason = CASS_DOWN_ORIGIN_BL_RFAULT;
+		break;
+	case SBL_LINK_DOWN_ORIGIN_ALIGN:
+		down_reason = CASS_DOWN_ORIGIN_BL_ALIGN;
+		break;
+	case SBL_LINK_DOWN_ORIGIN_LINK_DOWN:
+		down_reason = CASS_DOWN_ORIGIN_BL_DOWN;
+		break;
+	case SBL_LINK_DOWN_ORIGIN_HISER:
+		down_reason = CASS_DOWN_ORIGIN_BL_HISER;
+		break;
+	case SBL_LINK_DOWN_ORIGIN_LLR_MAX:
+		down_reason = CASS_DOWN_ORIGIN_BL_LLR;
+		break;
+	case SBL_LINK_DOWN_ORIGIN_UCW:
+		down_reason = CASS_DOWN_ORIGIN_LMON_UCW;
+		break;
+	case SBL_LINK_DOWN_ORIGIN_CCW:
+		down_reason = CASS_DOWN_ORIGIN_LMON_CCW;
+		break;
+	case SBL_LINK_DOWN_ORIGIN_LLR_TX_REPLAY:
+		down_reason = CASS_DOWN_ORIGIN_LLR_TX_REPLAY;
+		break;
+	default:
+		down_reason = CASS_DOWN_ORIGIN_BL_UNKNOWN;
+		break;
+	}
+
+	cass_link_async_down(hw, down_reason);
+}
+
+/**
+ * cass_sbl_async_alert() - async alert
+ *
+ * Notification function asynchronously called by the base link when it sends
+ * an alert
+ *
+ * @accessor: the SBL device
+ * @port_num: port number
+ * @alert_type: one of enum sbl_async_alert_type
+ * @alert_data: opaque pointer to alert data
+ * @size: size of the data
+ */
+static void cass_sbl_async_alert(void *accessor, int port_num, int alert_type,
+				 void *alert_data, int size)
+{
+	struct cass_dev *hw = (struct cass_dev *)accessor;
+	int down_origin;
+
+	cxidev_dbg(&hw->cdev, "(sbl): %s alert", sbl_async_alert_str(alert_type));
+
+	switch (alert_type) {
+	case SBL_ASYNC_ALERT_LINK_DOWN:
+		cxidev_warn(&hw->cdev, "(sbl): %d: link down alert\n",
+			    port_num);
+		down_origin = (int)(uintptr_t)alert_data;
+		cass_sbl_link_down_async_handler(hw, port_num, down_origin);
+		break;
+	case SBL_ASYNC_ALERT_SERDES_FW_CORRUPTION:
+		cxidev_crit(&hw->cdev, "(sbl): %d: serdes fw corruption alert\n",
+			    port_num);
+		break;
+	case SBL_ASYNC_ALERT_TX_DEGRADE:
+		cxidev_warn(&hw->cdev, "(sbl): %d: tx degrade alert\n",
+			    port_num);
+		break;
+	case SBL_ASYNC_ALERT_RX_DEGRADE:
+		cxidev_warn(&hw->cdev, "(sbl): %d: rx degrade alert\n",
+			    port_num);
+		break;
+	case SBL_ASYNC_ALERT_TX_DEGRADE_FAILURE:
+		cxidev_warn(&hw->cdev, "(sbl): %d: tx degrade failure alert\n",
+			    port_num);
+		break;
+	case SBL_ASYNC_ALERT_RX_DEGRADE_FAILURE:
+		cxidev_warn(&hw->cdev, "(sbl): %d: rx degrade failure alert\n",
+			    port_num);
+		break;
+	default:
+		cxidev_warn(&hw->cdev, "(sbl): %d: unknown alert reported: %d\n",
+			    port_num, alert_type);
+		break;
+	}
+}
+
+/**
+ * cass_sbl_sbus_op() - Perform an sbus operation
+ *
+ * Performs target sbus operation on this NIC's Cassini Sbus ring
+ *
+ * @accessor: the SBL device
+ * @ring: unused
+ * @req_data: Data for request
+ * @data_addr: Data address within the SBus Receiver
+ * @rx_addr: Address of destination SBus Receiver
+ * @command: Command for request
+ * @rsp_data: pointer to store response data
+ * @result_code: pointer to store result code from SBus request
+ * @overrun: pointer to store request overrun condition
+ * @timeout: timeout in ms
+ * @flags: specified polling delay and interval from cass_timing_flag
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+static int cass_sbl_sbus_op(void *accessor, int ring, u32 req_data,
+			    u8 data_addr, u8 rx_addr, u8 command,
+			    u32 *rsp_data, u8 *result_code, u8 *overrun,
+			    int timeout, unsigned int flags)
+{
+	struct cass_dev *hw = (struct cass_dev *)accessor;
+	struct cxi_sbus_op_params params = {
+		.req_data = req_data,
+		.data_addr = data_addr,
+		.rx_addr = rx_addr,
+		.command = command,
+		.timeout = timeout,
+	};
+
+	if (flags & SBL_FLAG_DELAY_3US)
+		params.delay = 3;
+	else if (flags & SBL_FLAG_DELAY_4US)
+		params.delay = 4;
+	else if (flags & SBL_FLAG_DELAY_5US)
+		params.delay = 5;
+	else if (flags & SBL_FLAG_DELAY_10US)
+		params.delay = 10;
+	else if (flags & SBL_FLAG_DELAY_20US)
+		params.delay = 20;
+	else if (flags & SBL_FLAG_DELAY_50US)
+		params.delay = 50;
+	else if (flags & SBL_FLAG_DELAY_100US)
+		params.delay = 100;
+	else
+		return -EINVAL;
+
+	if (flags & SBL_FLAG_INTERVAL_1MS)
+		params.poll_interval = 1;
+	else if (flags & SBL_FLAG_INTERVAL_10MS)
+		params.poll_interval = 10;
+	else if (flags & SBL_FLAG_INTERVAL_100MS)
+		params.poll_interval = 100;
+	else if (flags & SBL_FLAG_INTERVAL_1S)
+		params.poll_interval = 1000;
+	else
+		return -EINVAL;
+
+	return cxi_sbus_op(&hw->cdev, &params, rsp_data, result_code, overrun);
+}
+
+/**
+ * cass_sbl_sbus_op_reset() - Perform an sbus op reset
+ *
+ * Note this doesn't reset the sbus - all it does is clear the MB accessor
+ * registers
+ *
+ * @accessor: the SBL device
+ * @ring: unused
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+static int cass_sbl_sbus_op_reset(void *accessor, int ring)
+{
+	struct cass_dev *hw = (struct cass_dev *)accessor;
+
+	return cxi_sbus_op_reset(&hw->cdev);
+}
+
+/* End sbl_ops */
+
+/* phy_ops follow */
+/**
+ * cass_sbl_init() - Create a base link device
+ *
+ * Implements phy_ops' .init function
+ *
+ * @hw: the device
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+int cass_sbl_init(struct cass_dev *hw)
+{
+	struct sbl_inst *sbl;
+	struct sbl_ops ops;
+	struct sbl_instance_attr sbl_attr = SBL_INSTANCE_ATTR_INITIALIZER;
+	struct sbl_init_attr sbl_iattr;
+	int err = 0;
+
+	ops.sbl_read32			 = cass_read32;
+	ops.sbl_write32			 = cass_write32;
+	ops.sbl_read64			 = cass_read64;
+	ops.sbl_write64			 = cass_write64;
+	ops.sbl_sbus_op			 = cass_sbl_sbus_op;
+	ops.sbl_sbus_op_reset		 = cass_sbl_sbus_op_reset;
+	ops.sbl_is_fabric_link		 = cass_sbl_is_fabric_link;
+	ops.sbl_get_max_frame_size	 = cass_sbl_get_max_frame_size;
+	ops.sbl_pml_install_intr_handler = cass_sbl_pml_install_intr_handler;
+	ops.sbl_pml_enable_intr_handler	 = cass_sbl_pml_enable_intr_handler;
+	ops.sbl_pml_remove_intr_handler	 = cass_sbl_pml_remove_intr_handler;
+	ops.sbl_pml_disable_intr_handler = cass_sbl_pml_disable_intr_handler;
+	ops.sbl_async_alert              = cass_sbl_async_alert;
+
+	sbl_iattr.magic = SBL_INIT_ATTR_MAGIC;
+	sbl_iattr.uc_nic = hw->uc_nic;
+
+	switch (hw->uc_platform) {
+	case CUC_BOARD_TYPE_SAWTOOTH:
+		sbl_iattr.uc_platform = SBL_UC_PLATFORM_SAWTOOTH;
+		break;
+	case CUC_BOARD_TYPE_BRAZOS:
+		sbl_iattr.uc_platform = SBL_UC_PLATFORM_BRAZOS;
+		break;
+	default:
+		sbl_iattr.uc_platform = SBL_UC_PLATFORM_UNKNOWN;
+	}
+
+	sbl = sbl_new_instance(hw, hw, &ops, &sbl_iattr);
+
+	if (IS_ERR(sbl)) {
+		cxidev_err(&hw->cdev, "new sbl instance failed [%ld]\n",
+			   PTR_ERR(sbl));
+		err = PTR_ERR(sbl);
+		goto out_bad_sbl;
+	}
+	hw->sbl = sbl;
+
+	/* initialise the base link instance */
+	strscpy(sbl_attr.inst_name, hw->cdev.name,
+		sizeof(sbl_attr.inst_name));
+	err = sbl_initialise_instance(hw->sbl, &sbl_attr);
+	if (err) {
+		cxidev_err(&hw->cdev, "sbl init failed [%d]\n", err);
+		sbl_delete_instance(hw->sbl);
+		goto out_bad_sbl;
+	}
+
+	hw->sbl_counters = NULL;
+	err = cass_sbl_counters_init(hw);
+	if (err)
+		sbl_delete_instance(hw->sbl);
+
+ out_bad_sbl:
+	if (err)
+		hw->sbl = NULL;
+
+	return err;
+}
+
+/**
+ * cass_sbl_exit() - Delete a base link device
+ *
+ * Implements phy_ops' .exit function
+ *
+ * @hw: the device
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+int cass_sbl_exit(struct cass_dev *hw)
+{
+	int err;
+
+	if (!hw->sbl)
+		return 0;
+
+	err = sbl_delete_instance(hw->sbl);
+	if (err) {
+		cxidev_err(&hw->cdev, "delete sbl instance failed [%d]\n", err);
+		return err;
+	}
+	cass_sbl_counters_term(hw);
+	hw->sbl = NULL;
+	return 0;
+}
+
+void cass_sbl_exit_legacy(struct cass_dev *hw)
+{
+	WARN_ON(cass_sbl_exit(hw));
+}
+
+/**
+ * cass_sbl_power_on() - Bring a link up
+ *
+ * Implements phy_ops' .power_on function
+ *
+ * @hw: the device
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+int cass_sbl_power_on(struct cass_dev *hw)
+{
+	bool auto_restart;
+	int blstate;
+	int err = 0;
+	bool auto_neg_timedout = false;
+
+	cxidev_dbg(&hw->cdev, "link: up starting\n");
+	atomic_inc(&hw->sbl_counters[link_up_tries]);
+
+	hw->port->config_state |= CASS_PORT_CONFIGURED;
+
+	if (cass_link_get_state(hw) == CASS_LINK_STATUS_UP)
+		goto out;
+	else
+		cass_link_set_state(hw, CASS_LINK_STATUS_STARTING, 0);
+
+	cass_link_set_down_origin(hw, CASS_DOWN_ORIGIN_NONE);
+	auto_restart = hw->port->lattr.options & CASS_LINK_OPT_UP_AUTO_RESTART;
+
+	if (hw->port->subtype != CASS_PORT_SUBTYPE_IEEE)
+		sbl_enable_opt_lane_degrade(hw->sbl, 0, true);
+	/*
+	 * bring up the base link (serdes,pcs,mac,[llr])
+	 */
+	err = sbl_base_link_start(hw->sbl, 0);
+	if (err) {
+		if (err == -ETIME)
+			auto_neg_timedout = true;
+
+		if (auto_restart || (err == -ECANCELED)) {
+			/*
+			 * link did not come up
+			 * try to cleanup base link for another restart attempt
+			 */
+			cxidev_dbg(&hw->cdev, "link: base link start failed [%d]\n",
+				   err);
+			sbl_base_link_try_start_fail_cleanup(hw->sbl, 0);
+			sbl_base_link_get_status(hw->sbl, 0, &blstate,
+						 NULL, NULL, NULL, NULL, NULL);
+			cxidev_dbg(&hw->cdev, "link: base link status = %d\n",
+				   blstate);
+			if (blstate == SBL_BASE_LINK_STATUS_DOWN)
+				goto out_non_fatal;
+			else if (blstate == SBL_BASE_LINK_STATUS_UNCONFIGURED)
+				goto out_non_fatal;
+			else
+				goto out_fatal;
+		} else {
+			cxidev_err(&hw->cdev, "link: base link start failed [%d]\n",
+				   err);
+			err = -ENOLINK;
+			goto out_fatal;
+		}
+	}
+
+	atomic_inc(&hw->sbl_counters[link_up]);
+
+	/* report success */
+out:
+	cass_link_set_state(hw, CASS_LINK_STATUS_UP, 0);
+	cass_phy_link_up(hw);
+
+	hw->port->start_time = ktime_get_seconds();
+
+	return 0;
+
+out_non_fatal:
+	if (!auto_neg_timedout) {
+		cass_link_set_state(hw, CASS_LINK_STATUS_DOWN, 0);
+		cass_phy_link_down(hw);
+	}
+
+	return err;
+
+	/*
+	 * fatal errors result in the error state and require a reset to clear
+	 */
+out_fatal:
+	cass_link_set_state(hw, CASS_LINK_STATUS_ERROR, err);
+
+	return err;
+}
+
+/**
+ * cass_sbl_power_off() - Bring a link down
+ *
+ * Implements phy_ops' .power_off function
+ *
+ * @hw: the device
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+int cass_sbl_power_off(struct cass_dev *hw)
+{
+	int err = 0;
+
+	cxidev_dbg(&hw->cdev, "link: down starting (from %s)\n",
+		   cass_link_state_str(cass_link_get_state(hw)));
+
+	atomic_inc(&hw->sbl_counters[link_down_tries]);
+
+	if (cass_link_get_state(hw) == CASS_LINK_STATUS_DOWN)
+		goto out;
+	else
+		cass_link_set_state(hw, CASS_LINK_STATUS_STOPPING, 0);
+
+	/*
+	 * ethernet links need to make sure all flows are empty
+	 */
+	sbl_pml_mac_stop(hw->sbl, 0);
+
+	/*
+	 * stop base link
+	 */
+	if (hw->port->link_down_origin == CASS_DOWN_ORIGIN_BL_HISER ||
+	    hw->port->link_down_origin == CASS_DOWN_ORIGIN_LMON_UCW ||
+	    hw->port->link_down_origin == CASS_DOWN_ORIGIN_BL_DOWN)
+		sbl_serdes_invalidate_tuning_params(hw->sbl, 0);
+
+	err = sbl_base_link_stop(hw->sbl, 0);
+	if (err) {
+		cxidev_err(&hw->cdev,
+			   "link: fabric stop, sbl_link_down failed [%d]\n",
+			   err);
+		goto out_fatal;
+	}
+
+	atomic_inc(&hw->sbl_counters[link_down]);
+
+	/* report success */
+out:
+	cass_link_set_state(hw, CASS_LINK_STATUS_DOWN, 0);
+	hw->port->config_state &= ~CASS_PORT_CONFIGURED;
+	cass_phy_link_down(hw);
+
+	return 0;
+
+out_fatal:
+	cass_link_set_state(hw, CASS_LINK_STATUS_ERROR, err);
+
+	return err;
+}
+
+/**
+ * cass_sbl_serdes_config_defaults() - Writes a Cassini-specific config to SBL
+ *
+ * Updates SBL config to include an additional SerDes config value set.
+ *
+ * @hw: the device
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+static int cass_sbl_serdes_config_defaults(struct cass_dev *hw)
+{
+	struct sbl_sc_values vals = { 0 };
+	int rc, err;
+
+	/* CONFIG 1: 200G and 100G PEC to switch */
+	u64 port_mask = 0x1;
+	u8  serdes_mask = 0xf;
+	u64 tp_state_mask0 = sbl_create_tp_hash0((u8)CASS_SBL_SC_MASKED_IN,
+						 (u8)CASS_SBL_SC_MASKED_IN,
+						 (u8)CASS_SBL_SC_MASKED_OUT,
+						 (u8)CASS_SBL_SC_MASKED_OUT,
+						 (u8)CASS_SBL_SC_MASKED_IN,
+						 (u16)CASS_SBL_SC_MASKED_OUT);
+	u64 tp_state_mask1 = sbl_create_tp_hash1(CASS_SBL_SC_MASKED_IN);
+	u64 tp_state_match0 = sbl_create_tp_hash0(CASS_SBL_SC_LP_SWITCH,
+						 CASS_SBL_SC_LBM_ANY,
+						 CASS_SBL_SC_NA,
+						 CASS_SBL_SC_NA,
+						 CASS_SBL_SC_MT_ELEC,
+						 CASS_SBL_SC_NA);
+	u64 tp_state_match1 = sbl_create_tp_hash1(CASS_SBL_SC_NA);
+
+	vals.magic    = SBL_SERDES_CONFIG_MAGIC;
+	vals.atten    = SBL_DFLT_PORT_CONFIG_ATTEN;
+	vals.pre      = CASS_SBL_PORT_CONFIG1_PRE;
+	vals.post     = SBL_DFLT_PORT_CONFIG_POST;
+	vals.pre2     = SBL_DFLT_PORT_CONFIG_PRE2;
+	vals.pre3     = SBL_DFLT_PORT_CONFIG_PRE3;
+	vals.gs1      = SBL_DFLT_PORT_CONFIG_GS1_OPTICAL;
+	vals.gs2      = SBL_DFLT_PORT_CONFIG_GS2_OPTICAL;
+	vals.num_intr = SBL_DFLT_PORT_CONFIG_NUM_INTR;
+
+	err = sbl_serdes_add_config(hw->sbl, tp_state_mask0, tp_state_mask1,
+				    tp_state_match0, tp_state_match1, port_mask,
+				   serdes_mask, &vals, false);
+	/* If we failed trying to add a duplicate config - we still got what
+	 * we wanted. Return 0.
+	 */
+	if ((err == 0) || (err == -EEXIST))
+		rc = 0;
+	else
+		rc = err;
+
+	// CONFIG 2: 100G AOC to switch
+	// All the same mask/match params, save for the following:
+	tp_state_match0 = sbl_create_tp_hash0((u8)CASS_SBL_SC_LP_SWITCH,
+					      (u8)CASS_SBL_SC_LBM_ANY,
+					      (u8)CASS_SBL_SC_NA,
+					      (u8)CASS_SBL_SC_LM_100,
+					      (u8)CASS_SBL_SC_MT_OPT_ANY,
+					      (u16)CASS_SBL_SC_NA);
+	vals.atten    = CASS_SBL_PORT_CONFIG2_ATTEN;
+	vals.pre      = SBL_DFLT_PORT_CONFIG_PRE;
+	vals.post     = SBL_DFLT_PORT_CONFIG_POST;
+	vals.pre2     = SBL_DFLT_PORT_CONFIG_PRE2;
+	vals.pre3     = SBL_DFLT_PORT_CONFIG_PRE3;
+	vals.gs1      = CASS_SBL_PORT_CONFIG2_GS1;
+	vals.gs2      = SBL_DFLT_PORT_CONFIG_GS2_OPTICAL;
+	vals.num_intr = CASS_SBL_PORT_CONFIG2_NUM_INTR;
+	vals.intr_val[0] = CASS_SBL_PORT_CONFIG2_INTR0;
+	vals.data_val[0] = CASS_SBL_PORT_CONFIG2_DATA0;
+	vals.intr_val[1] = CASS_SBL_PORT_CONFIG2_INTR1;
+	vals.data_val[1] = CASS_SBL_PORT_CONFIG2_DATA1;
+	vals.intr_val[2] = CASS_SBL_PORT_CONFIG2_INTR2;
+	vals.data_val[2] = CASS_SBL_PORT_CONFIG2_DATA2;
+	vals.intr_val[3] = CASS_SBL_PORT_CONFIG2_INTR3;
+	vals.data_val[3] = CASS_SBL_PORT_CONFIG2_DATA3;
+
+	err = sbl_serdes_add_config(hw->sbl, tp_state_mask0, tp_state_mask1,
+				    tp_state_match0, tp_state_match1, port_mask,
+				   serdes_mask, &vals, false);
+	if ((err == 0) || (err == -EEXIST))
+		rc += 0;
+	else
+		rc += err;
+
+	// CONFIG 3: 200G AOC to switch
+	// All the same mask/match params, save for the following:
+	tp_state_match0 = sbl_create_tp_hash0((u8)CASS_SBL_SC_LP_SWITCH,
+					      (u8)CASS_SBL_SC_LBM_ANY,
+					      (u8)CASS_SBL_SC_NA,
+					      (u8)CASS_SBL_SC_LM_200,
+					      (u8)CASS_SBL_SC_MT_OPT_ANY,
+					      (u16)CASS_SBL_SC_NA);
+	vals.atten    = CASS_SBL_PORT_CONFIG3_ATTEN;
+	vals.pre      = CASS_SBL_PORT_CONFIG3_PRE;
+	vals.post     = SBL_DFLT_PORT_CONFIG_POST;
+	vals.pre2     = SBL_DFLT_PORT_CONFIG_PRE2;
+	vals.pre3     = SBL_DFLT_PORT_CONFIG_PRE3;
+	vals.gs1      = CASS_SBL_PORT_CONFIG3_GS1;
+	vals.gs2      = SBL_DFLT_PORT_CONFIG_GS2_OPTICAL;
+	vals.num_intr = SBL_DFLT_PORT_CONFIG_NUM_INTR;
+
+	err = sbl_serdes_add_config(hw->sbl, tp_state_mask0, tp_state_mask1,
+				    tp_state_match0, tp_state_match1, port_mask,
+				   serdes_mask, &vals, false);
+	if ((err == 0) || (err == -EEXIST))
+		rc += 0;
+	else
+		rc += err;
+
+	if (rc)
+		cxidev_err(&hw->cdev, "Failed to update SBL config [%d]\n", rc);
+	return rc;
+}
+
+/**
+ * cass_sbl_set_defaults() - Set link defaults
+ *
+ * Sets reasonable defaults for 200G Electrical link
+ *
+ * @hw: the device
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+void cass_sbl_set_defaults(struct cass_dev *hw)
+{
+	struct sbl_media_attr mattr;
+
+	/* The media attribute can be configured during cable scan, which has
+	 * already happened. Don't blow away this information.
+	 */
+	mattr = hw->port->lattr.mattr;
+	memset(&hw->port->lattr, 0, sizeof(struct cass_link_attr));
+	hw->port->lattr.mattr = mattr;
+
+	/* base link config */
+	hw->port->lattr.bl.magic = SBL_LINK_ATTR_MAGIC;
+	hw->port->lattr.bl.options = SBL_OPT_ENABLE_PCAL | SBL_DISABLE_PML_RECOVERY;
+	hw->port->lattr.options = CASS_LINK_ATTR_DEFAULT_OPT_FLAGS
+		| CASS_LINK_OPT_UP_AUTO_RESTART;
+
+	switch (hw->port->lattr.mattr.media) {
+	case SBL_LINK_MEDIA_ELECTRICAL:
+	default:
+		hw->port->lattr.bl.options |= SBL_OPT_AUTONEG_TIMEOUT_SSHOT |
+			SBL_OPT_AUTONEG_100CR4_FIXUP;
+		hw->port->lattr.bl.start_timeout =
+			SBL_LINK_START_TIMEOUT_PEC;
+		hw->port->lattr.bl.config_target =
+			SBL_BASE_LINK_CONFIG_PEC;
+		hw->port->lattr.bl.pec.an_mode =
+			SBL_AN_MODE_ON;
+		hw->port->lattr.bl.pec.an_retry_timeout =
+			SBL_LINK_DFLT_AN_RETRY_TIMEOUT;
+		hw->port->lattr.bl.pec.an_max_retry =
+			SBL_LINK_DFLT_AN_MAX_RETRY;
+		hw->port->lattr.bl.lpd_timeout = 0;
+		hw->port->lattr.bl.lpd_poll_interval = 0;
+		hw->port->lattr.bl.dfe_pre_delay =
+			SBL_DFLT_DFE_PRE_DELAY_PEC;
+		hw->port->lattr.bl.dfe_timeout =
+			SBL_DFLT_DFE_TIMEOUT_PEC;
+		hw->port->lattr.bl.dfe_poll_interval =
+			SBL_DFLT_DFE_POLL_INTERVAL;
+		hw->port->lattr.bl.pcal_eyecheck_holdoff =
+			SBL_DFLT_PCAL_EYECHECK_HOLDOFF_PEC;
+		hw->port->lattr.bl.nrz_min_eye_height =
+			SBL_DFLT_NRZ_PEC_MIN_EYE_HEIGHT;
+		hw->port->lattr.bl.nrz_max_eye_height =
+			SBL_DFLT_NRZ_PEC_MAX_EYE_HEIGHT;
+		hw->port->lattr.bl.pam4_min_eye_height =
+			SBL_DFLT_PAM4_PEC_MIN_EYE_HEIGHT;
+		hw->port->lattr.bl.pam4_max_eye_height =
+			SBL_DFLT_PAM4_PEC_MAX_EYE_HEIGHT;
+		break;
+	case SBL_LINK_MEDIA_OPTICAL:
+		hw->port->lattr.bl.start_timeout =
+			SBL_LINK_START_TIMEOUT_AOC;
+		hw->port->lattr.bl.config_target =
+			SBL_BASE_LINK_CONFIG_AOC;
+		hw->port->lattr.bl.aoc.reserved = 0;
+		hw->port->lattr.bl.aoc.optical_lock_delay =
+			SBL_DFLT_OPTICAL_LOCK_DELAY;
+		hw->port->lattr.bl.aoc.optical_lock_interval =
+			SBL_DFLT_OPTICAL_LOCK_INTERVAL;
+		/* hw->port->lattr.bl.options |= */
+		/*	SBL_OPT_SERDES_LPD; */
+		hw->port->lattr.bl.lpd_timeout =
+			SBL_DFLT_LPD_TIMEOUT;
+		hw->port->lattr.bl.lpd_poll_interval =
+			SBL_DFLT_LPD_POLL_INTERVAL;
+		hw->port->lattr.bl.dfe_pre_delay =
+			SBL_DFLT_DFE_PRE_DELAY_AOC;
+		hw->port->lattr.bl.dfe_timeout =
+			SBL_DFLT_DFE_TIMEOUT_AOC;
+		hw->port->lattr.bl.dfe_poll_interval =
+			SBL_DFLT_DFE_POLL_INTERVAL;
+		hw->port->lattr.bl.pcal_eyecheck_holdoff =
+			SBL_DFLT_PCAL_EYECHECK_HOLDOFF_AOC;
+		hw->port->lattr.bl.nrz_min_eye_height =
+			SBL_DFLT_NRZ_AOC_MIN_EYE_HEIGHT;
+		hw->port->lattr.bl.nrz_max_eye_height =
+			SBL_DFLT_NRZ_AOC_MAX_EYE_HEIGHT;
+		hw->port->lattr.bl.pam4_min_eye_height =
+			SBL_DFLT_PAM4_AOC_MIN_EYE_HEIGHT;
+		hw->port->lattr.bl.pam4_max_eye_height =
+			SBL_DFLT_PAM4_AOC_MAX_EYE_HEIGHT;
+		break;
+	}
+
+	if ((HW_PLATFORM_Z1(hw)) &&
+	    (hw->port->lattr.mattr.media == SBL_LINK_MEDIA_ELECTRICAL)) {
+		hw->port->lattr.bl.pec.an_mode = SBL_AN_MODE_FIXED;
+	}
+
+	hw->port->lattr.bl.link_mode          = SBL_LINK_MODE_BS_200G;
+	hw->port->lattr.bl.loopback_mode      = SBL_LOOPBACK_MODE_OFF;
+	hw->port->lattr.bl.link_partner       = SBL_LINK_PARTNER_SWITCH;
+	hw->port->lattr.bl.tuning_pattern     = SBL_TUNING_PATTERN_CORE;
+	hw->port->lattr.bl.fec_mode           = SBL_RS_MODE_ON;
+	hw->port->lattr.bl.enable_autodegrade = 0;
+	if (HW_PLATFORM_ASIC(hw))
+		hw->port->lattr.bl.llr_mode   = SBL_LLR_MODE_ON;
+	else
+		hw->port->lattr.bl.llr_mode   = SBL_LLR_MODE_OFF;
+	hw->port->lattr.bl.ifg_config         = SBL_IFG_CONFIG_IEEE_200G;
+	hw->port->lattr.bl.precoding          = SBL_PRECODING_OFF;
+
+	hw->port->lattr.bl.pml_recovery.timeout         = pml_rec_timeout;
+	hw->port->lattr.bl.pml_recovery.rl_max_duration = pml_rec_rl_max_dur;
+	hw->port->lattr.bl.pml_recovery.rl_window_size  = pml_rec_rl_win_size;
+}
+
+/**
+ * cass_sbl_configure() - Send configuration to SBL
+ *
+ * @hw: the device
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+int cass_sbl_configure(struct cass_dev *hw)
+{
+	int err;
+
+	cxidev_dbg(&hw->cdev, "Configuring SBL\n");
+
+	if ((hw->port->lattr.bl.llr_mode == SBL_LLR_MODE_ON) ||
+	    (hw->port->lattr.bl.ifg_config == SBL_IFG_CONFIG_HPC))
+		hw->port->subtype = CASS_PORT_SUBTYPE_CASSINI;
+	else
+		hw->port->subtype = CASS_PORT_SUBTYPE_IEEE;
+
+	err = hw->link_ops->link_config(hw);
+	if (err) {
+		cxidev_err(&hw->cdev, "configure failed [%d]\n", err);
+		return err;
+	}
+
+	cass_link_set_state(hw, CASS_LINK_STATUS_DOWN, 0);
+	hw->link_config_dirty = false;
+	hw->port->config_state |= CASS_TYPE_CONFIGURED | CASS_LINK_CONFIGURED;
+
+	return err;
+}
+
+/**
+ * cass_sbl_reset() - Reset a link
+ *
+ * Implements phy_ops' .reset function
+ *
+ * @hw: the device
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+int cass_sbl_reset(struct cass_dev *hw)
+{
+	int bl_state;
+	int err;
+
+	cxidev_dbg(&hw->cdev, "link: reset (from %s)\n",
+		   cass_link_state_str(cass_link_get_state(hw)));
+
+	atomic_inc(&hw->sbl_counters[link_reset_tries]);
+
+	cass_link_set_state(hw, CASS_LINK_STATUS_RESETTING, 0);
+
+	/* reset the base link */
+	sbl_base_link_get_status(hw->sbl, 0, &bl_state, NULL, NULL, NULL,
+				 NULL, NULL);
+
+	if (bl_state != SBL_BASE_LINK_STATUS_UNCONFIGURED) {
+		err = sbl_base_link_reset(hw->sbl, 0);
+		if (err)
+			cxidev_err(&hw->cdev,
+				   "link: reset, base link reset failed [%d]\n",
+				   err);
+	}
+
+	spin_lock(&hw->sbl_state_lock);
+	hw->port->prev_lstate = hw->port->lstate;
+	hw->port->lstate = CASS_LINK_STATUS_UNCONFIGURED;
+	hw->port->lerr = 0;
+	hw->port->config_state &= ~CASS_LINK_CONFIGURED;
+	spin_unlock(&hw->sbl_state_lock);
+
+	atomic_inc(&hw->sbl_counters[link_reset]);
+
+	return 0;
+}
+
+/* end phy_ops */
+
+/* sysfs */
+static ssize_t link_show(struct kobject *kobj,
+			 struct kobj_attribute *kattr, char *buf)
+{
+	int rc;
+	struct cass_dev *hw =
+		container_of(kobj, struct cass_dev, port_kobj);
+
+	if (!cass_version(hw, CASSINI_1))
+		return snprintf(buf, SYSFS_BUFSIZE, "NOT IMPLEMENTED!!\n");
+
+	rc = cass_link_sysfs_sprint(hw, buf, PAGE_SIZE);
+
+	return rc;
+}
+
+static ssize_t link_layer_retry_show(struct kobject *kobj,
+				     struct kobj_attribute *kattr, char *buf)
+{
+	int rc;
+	struct cass_dev *hw =
+		container_of(kobj, struct cass_dev, port_kobj);
+
+	if (!cass_version(hw, CASSINI_1))
+		return snprintf(buf, SYSFS_BUFSIZE, "NOT IMPLEMENTED!!\n");
+
+	rc = sbl_base_link_llr_sysfs_sprint(hw->sbl, 0, buf, PAGE_SIZE);
+
+	return rc;
+}
+
+static ssize_t loopback_show(struct kobject *kobj,
+			     struct kobj_attribute *kattr, char *buf)
+{
+	int rc;
+	struct cass_dev *hw =
+		container_of(kobj, struct cass_dev, port_kobj);
+
+	if (!cass_version(hw, CASSINI_1))
+		return snprintf(buf, SYSFS_BUFSIZE, "NOT IMPLEMENTED!!\n");
+
+	rc = sbl_base_link_loopback_sysfs_sprint(hw->sbl, 0, buf, PAGE_SIZE);
+
+	return rc;
+}
+
+static ssize_t media_show(struct kobject *kobj,
+			  struct kobj_attribute *kattr, char *buf)
+{
+	int rc;
+	struct cass_dev *hw =
+		container_of(kobj, struct cass_dev, port_kobj);
+
+	if (!cass_version(hw, CASSINI_1))
+		return snprintf(buf, SYSFS_BUFSIZE, "NOT IMPLEMENTED!!\n");
+
+	rc = sbl_media_type_sysfs_sprint(hw->sbl, 0, buf, PAGE_SIZE);
+
+	return rc;
+}
+
+static ssize_t pause_show(struct kobject *kobj,
+			  struct kobj_attribute *kattr, char *buf)
+{
+	int rc;
+	struct cass_dev *hw =
+		container_of(kobj, struct cass_dev, port_kobj);
+
+	if (!cass_version(hw, CASSINI_1))
+		return snprintf(buf, SYSFS_BUFSIZE, "NOT IMPLEMENTED!!\n");
+
+	rc = cass_pause_sysfs_sprint(hw, buf, PAGE_SIZE);
+
+	return rc;
+}
+
+static ssize_t speed_show(struct kobject *kobj,
+			  struct kobj_attribute *kattr, char *buf)
+{
+	int rc;
+	struct cass_dev *hw =
+		container_of(kobj, struct cass_dev, port_kobj);
+
+	if (!cass_version(hw, CASSINI_1))
+		return snprintf(buf, SYSFS_BUFSIZE, "NOT IMPLEMENTED!!\n");
+
+	rc = sbl_pml_pcs_speed_sysfs_sprint(hw->sbl, 0, buf, PAGE_SIZE);
+
+	return rc;
+}
+
+static struct kobj_attribute dev_attr_link = __ATTR_RO(link);
+static struct kobj_attribute dev_attr_link_layer_retry =
+	__ATTR_RO(link_layer_retry);
+static struct kobj_attribute dev_attr_loopback = __ATTR_RO(loopback);
+static struct kobj_attribute dev_attr_media = __ATTR_RO(media);
+static struct kobj_attribute dev_attr_pause = __ATTR_RO(pause);
+static struct kobj_attribute dev_attr_speed = __ATTR_RO(speed);
+
+static struct attribute *port_attrs[] = {
+	&dev_attr_link.attr,
+	&dev_attr_link_layer_retry.attr,
+	&dev_attr_loopback.attr,
+	&dev_attr_media.attr,
+	&dev_attr_pause.attr,
+	&dev_attr_speed.attr,
+	NULL,
+};
+ATTRIBUTE_GROUPS(port);
+
+static struct kobj_type port_sysfs_entries = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = port_groups,
+};
+
+int cass_register_port(struct cass_dev *hw)
+{
+	int rc;
+
+	/* Create the port sysfs entries */
+	rc = kobject_init_and_add(&hw->port_kobj, &port_sysfs_entries,
+				  &hw->cdev.pdev->dev.kobj,
+				  "port");
+	if (rc)
+		kobject_put(&hw->port_kobj);
+
+	return rc;
+}
+
+void cass_unregister_port(struct cass_dev *hw)
+{
+	kobject_put(&hw->port_kobj);
+}
+
+void cass_sbl_link_mode_to_speed(u32 link_mode, int *speed)
+{
+	switch (link_mode) {
+	case SBL_LINK_MODE_BS_200G:
+		*speed = SPEED_200000;
+		return;
+	case SBL_LINK_MODE_BJ_100G:
+	case SBL_LINK_MODE_CD_100G:
+		*speed = SPEED_100000;
+		return;
+	case SBL_LINK_MODE_CD_50G:
+		*speed = SPEED_50000;
+		return;
+	default:
+		*speed = SPEED_UNKNOWN;
+		return;
+	}
+}
+
+void cass_sbl_link_speed_to_mode(int speed, u32 *link_mode)
+{
+	switch (speed) {
+	case SPEED_200000:
+	case SPEED_UNKNOWN:
+		*link_mode = SBL_LINK_MODE_BS_200G;
+		return;
+	case SPEED_100000:
+		*link_mode = SBL_LINK_MODE_BJ_100G;
+		return;
+	case SPEED_50000:
+		*link_mode = SBL_LINK_MODE_CD_50G;
+		return;
+	default:
+		*link_mode = SBL_LINK_MODE_INVALID;
+		return;
+	}
+}
+
+int cass_sbl_media_config(struct cass_dev *hw, void *attr)
+{
+	int err;
+
+	cxidev_dbg(&hw->cdev, "sbl media config\n");
+
+	err = sbl_media_config(hw->sbl, 0, attr);
+	if (err) {
+		cxidev_err(&hw->cdev, "sbl media config failed [%d]\n", err);
+		return err;
+	}
+
+	return 0;
+}
+
+int cass_sbl_media_unconfig(struct cass_dev *hw)
+{
+	int err;
+
+	cxidev_dbg(&hw->cdev, "sbl media unconfig\n");
+
+	err = sbl_media_unconfig(hw->sbl, 0);
+	if (err) {
+		cxidev_err(&hw->cdev, "sbl media unconfig failed [%d]\n", err);
+		return err;
+	}
+
+	return 0;
+}
+
+int cass_sbl_link_config(struct cass_dev *hw)
+{
+	int err;
+
+	cxidev_dbg(&hw->cdev, "sbl link config\n");
+
+	err = sbl_base_link_config(hw->sbl, 0, &hw->port->lattr.bl);
+	if (err) {
+		cxidev_err(&hw->cdev, "Failed to set SBL config defaults\n");
+		return err;
+	}
+
+	err = cass_sbl_serdes_config_defaults(hw);
+	if (err) {
+		cxidev_err(&hw->cdev, "Failed to set SerDes config defaults\n");
+		return err;
+	}
+
+	return 0;
+}
+
+bool cass_sbl_pml_pcs_aligned(struct cass_dev *hw)
+{
+	return sbl_pml_pcs_aligned(hw->sbl, 0);
+}
+
+/*
+ * Create and initialise the port's counter array
+ */
+int cass_sbl_counters_init(struct cass_dev *hw)
+{
+	int i;
+
+	hw->sbl_counters = kzalloc(sizeof(atomic_t) * CASS_SBL_NUM_COUNTERS, GFP_KERNEL);
+	if (!hw->sbl_counters)
+		return -ENOMEM;
+
+	for (i = 0; i < CASS_SBL_NUM_COUNTERS; ++i)
+		atomic_set(&hw->sbl_counters[i], 0);
+
+	return 0;
+}
+
+/*
+ * Destroy the port's counter array
+ */
+void cass_sbl_counters_term(struct cass_dev *hw)
+{
+	kfree(hw->sbl_counters);
+	hw->sbl_counters = NULL;
+}
+
+/*
+ * Update down origin counters
+ */
+void cass_sbl_counters_down_origin_inc(struct cass_dev *hw, int down_origin)
+{
+	switch (down_origin) {
+	case CASS_DOWN_ORIGIN_CONFIG:
+		atomic_inc(&hw->sbl_counters[link_down_origin_config]);
+		break;
+	case CASS_DOWN_ORIGIN_BL_LFAULT:
+		atomic_inc(&hw->sbl_counters[link_down_origin_bl_lfault]);
+		break;
+	case CASS_DOWN_ORIGIN_BL_RFAULT:
+		atomic_inc(&hw->sbl_counters[link_down_origin_bl_rfault]);
+		break;
+	case CASS_DOWN_ORIGIN_BL_ALIGN:
+		atomic_inc(&hw->sbl_counters[link_down_origin_bl_align]);
+		break;
+	case CASS_DOWN_ORIGIN_BL_DOWN:
+		atomic_inc(&hw->sbl_counters[link_down_origin_bl_down]);
+		break;
+	case CASS_DOWN_ORIGIN_BL_HISER:
+		atomic_inc(&hw->sbl_counters[link_down_origin_bl_hiser]);
+		break;
+	case CASS_DOWN_ORIGIN_BL_LLR:
+		atomic_inc(&hw->sbl_counters[link_down_origin_bl_llr]);
+		break;
+	case CASS_DOWN_ORIGIN_BL_UNKNOWN:
+		atomic_inc(&hw->sbl_counters[link_down_origin_bl_unknown]);
+		break;
+	case CASS_DOWN_ORIGIN_LMON_UCW:
+		atomic_inc(&hw->sbl_counters[link_down_origin_lmon_ucw]);
+		break;
+	case CASS_DOWN_ORIGIN_LMON_CCW:
+		atomic_inc(&hw->sbl_counters[link_down_origin_lmon_ccw]);
+		break;
+	case CASS_DOWN_ORIGIN_LLR_TX_REPLAY:
+		atomic_inc(&hw->sbl_counters[link_down_origin_lmon_llr_tx_replay]);
+		break;
+	case CASS_DOWN_ORIGIN_HEADSHELL_REMOVED:
+		atomic_inc(&hw->sbl_counters[link_down_origin_headshell_removed]);
+		break;
+	case CASS_DOWN_ORIGIN_HEADSHELL_ERROR:
+		atomic_inc(&hw->sbl_counters[link_down_origin_headshell_error]);
+		break;
+	case CASS_DOWN_ORIGIN_MEDIA_REMOVED:
+		atomic_inc(&hw->sbl_counters[link_down_origin_media_removed]);
+		break;
+	case CASS_DOWN_ORIGIN_CMD:
+		atomic_inc(&hw->sbl_counters[link_down_origin_cmd]);
+		break;
+	default:
+		cxidev_err(&hw->cdev, "down origin (%d) with no counter", down_origin);
+		break;
+	}
+}
+
+/*
+ * Update sbl counters
+ */
+void cass_sbl_counters_update(struct cass_dev *hw)
+{
+	int sbl_counters[SBL_NUM_COUNTERS];
+	int i;
+	int err;
+
+	err = sbl_link_counters_get(hw->sbl, 0, sbl_counters, 0, SBL_NUM_COUNTERS);
+	if (err)
+		return;
+
+	for (i = 0; i < SBL_NUM_COUNTERS; ++i)
+		atomic_set(&hw->sbl_counters[SBL_COUNTERS_FIRST + i], sbl_counters[i]);
+}
+
+int cass_sbl_set_eth_name(struct cass_dev *hw, const char *name)
+{
+	sbl_set_eth_name(hw->sbl, name);
+
+	return 0;
+}
diff --git a/drivers/net/ethernet/hpe/ss1/cass_sl.c b/drivers/net/ethernet/hpe/ss1/cass_sl.c
new file mode 100644
index 000000000000..72c8724a3327
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_sl.c
@@ -0,0 +1,1524 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2022,2023,2024,2025,2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/delay.h>
+
+#include "cass_core.h"
+#include "cass_sl.h"
+#include "cass_sl_io.h"
+#include "cass_cable.h"
+#include "cxi_ethtool.h"
+
+#define CASS_SL_LGRP_NUM            0
+#define CASS_SL_LINK_NUM            0
+#define CASS_SL_LLR_NUM             0
+#define CASS_SL_MAC_NUM             0
+
+#define CASS_SL_INFO_MAP_STR_SIZE   80
+
+#define CASS_SL_SERDES_RATE_25  25781250000ULL
+#define CASS_SL_SERDES_RATE_50  53125000000ULL
+#define CASS_SL_SERDES_RATE_100 106250000000ULL
+
+#define CASS_SL_LINK_DOWN_TIMEOUT_MS  5000
+
+/* Default BER goals for FEC
+ * The maximum rate LLR can incur UCWs (1e-10). Typically a burst error
+ */
+#define CASS_SL_DEFAULT_BER_MANT_UCW 1
+#define CASS_SL_DEFAULT_BER_EXP_UCW  -10
+
+#define CASS_SL_DEFAULT_BER_MANT_CCW 2
+#define CASS_SL_DEFAULT_BER_EXP_CCW  -5
+
+#define SL_DFLT_PML_REC_TIMEOUT_MS                 60
+#define SL_DFLT_PML_REC_RATE_LIMIT_MAX_TIME_MS     60
+#define SL_DFLT_PML_REC_RATE_LIMIT_WINDOW_SIZE_MS  1000
+
+static unsigned int cass_sl_pml_rec_timeout_ms = SL_DFLT_PML_REC_TIMEOUT_MS;
+module_param(cass_sl_pml_rec_timeout_ms, uint, 0644);
+MODULE_PARM_DESC(cass_sl_pml_rec_timeout_ms, "PML recovery timeout in ms");
+
+static unsigned int cass_sl_pml_rec_rate_limit_max_time_ms = SL_DFLT_PML_REC_RATE_LIMIT_MAX_TIME_MS;
+module_param(cass_sl_pml_rec_rate_limit_max_time_ms, uint, 0644);
+MODULE_PARM_DESC(cass_sl_pml_rec_rate_limit_max_time_ms, "PML recovery max time in ms per window");
+
+static unsigned int cass_sl_pml_rec_rate_limit_win_size_ms = SL_DFLT_PML_REC_RATE_LIMIT_WINDOW_SIZE_MS;
+module_param(cass_sl_pml_rec_rate_limit_win_size_ms, uint, 0644);
+MODULE_PARM_DESC(cass_sl_pml_rec_rate_limit_win_size_ms, "PML recovery rate limiter window in ms");
+
+static struct kobj_type cass_sl_port_sysfs = {
+	.sysfs_ops = &kobj_sysfs_ops,
+};
+
+static struct kobj_type cass_sl_port_num_sysfs = {
+	.sysfs_ops = &kobj_sysfs_ops,
+};
+
+bool cass_sl_is_pcs_aligned(struct cass_dev *cass_dev)
+{
+	union ss2_port_pml_sts_rx_pcs_subport sts;
+
+	cass_read(cass_dev, SS2_PORT_PML_STS_RX_PCS_SUBPORT(CASS_SL_LINK_NUM),
+		  &sts, sizeof(sts));
+
+	return !!sts.align_status;
+}
+
+static int cass_sl_speed_get(u32 tech)
+{
+	switch (tech) {
+	case SL_LGRP_CONFIG_TECH_BJ_100G:
+		return SPEED_100000;
+	case SL_LGRP_CONFIG_TECH_BS_200G:
+		return SPEED_200000;
+	case SL_LGRP_CONFIG_TECH_CK_400G:
+		return SPEED_400000;
+	default:
+		return 0;
+	}
+}
+
+static u32 cass_sl_tech_get(int speed)
+{
+	switch (speed) {
+	case SPEED_100000:
+		return SL_LGRP_CONFIG_TECH_BJ_100G;
+	case SPEED_200000:
+		return SL_LGRP_CONFIG_TECH_BS_200G;
+	case SPEED_400000:
+		return SL_LGRP_CONFIG_TECH_CK_400G;
+	default:
+		return 0;
+	}
+}
+
+void cass_sl_mode_get(struct cass_dev *cass_dev, struct cxi_link_info *link_info)
+{
+	cxidev_dbg(&cass_dev->cdev, "sl mode get\n");
+
+	memset(link_info, 0, sizeof(*link_info));
+
+	/* auto neg */
+	if (cass_dev->sl.link_config.options & SL_LINK_CONFIG_OPT_AUTONEG_ENABLE) {
+		cxidev_dbg(&cass_dev->cdev, "sl mode get autoneg enabled\n");
+		link_info->autoneg = AUTONEG_ENABLE;
+		link_info->speed   = cass_sl_speed_get(cass_dev->sl.link_up_mode);
+	} else {
+		cxidev_dbg(&cass_dev->cdev,
+			   "sl mode get autoneg disabled (tech_map = 0x%X)\n",
+			   cass_dev->sl.static_tech_map);
+		link_info->autoneg = AUTONEG_DISABLE;
+		link_info->speed   = cass_sl_speed_get(cass_dev->sl.static_tech_map);
+	}
+
+	/* llr */
+	if (cass_dev->sl.enable_llr)
+		link_info->flags |= CXI_ETH_PF_LLR;
+
+	/* loopback */
+	if (cass_dev->sl.lgrp_config.options & SL_LGRP_CONFIG_OPT_SERDES_LOOPBACK_ENABLE)
+		link_info->flags |= CXI_ETH_PF_INTERNAL_LOOPBACK;
+	else if (cass_dev->sl.link_config.options & SL_LINK_CONFIG_OPT_REMOTE_LOOPBACK_ENABLE)
+		link_info->flags |= CXI_ETH_PF_EXTERNAL_LOOPBACK;
+
+	/* link training */
+	if (cass_dev->sl.link_config.hpe_map & SL_LINK_CONFIG_HPE_LINKTRAIN)
+		link_info->flags |= CXI_ETH_PF_LINKTRAIN;
+	else
+		link_info->flags &= ~CXI_ETH_PF_LINKTRAIN;
+
+	/* FEC Monitor */
+	if (cass_dev->sl.link_policy.fec_mon_period_ms != 0)
+		link_info->flags |= CXI_ETH_PF_FEC_MONITOR;
+
+	if (cass_dev->sl.link_config.options & SL_LINK_CONFIG_OPT_LOS_LOL_UP_FAIL_HIDE)
+		link_info->flags |= CXI_ETH_PF_LOS_LOL_HIDE;
+
+	/* R1 link partner */
+	if (cass_dev->sl.lgrp_config.options & SL_LGRP_CONFIG_OPT_R1)
+		link_info->flags |= CXI_ETH_PF_R1_LINK_PARTNER;
+	else
+		link_info->flags &= ~CXI_ETH_PF_R1_LINK_PARTNER;
+
+	/* type */
+	if (cass_dev->sl.media_attr.type & SL_MEDIA_TYPE_BACKPLANE)
+		link_info->port_type = PORT_DA;
+	else if (cass_dev->sl.media_attr.type & SL_MEDIA_TYPE_OPTICAL)
+		link_info->port_type = PORT_FIBRE;
+	else if (cass_dev->sl.media_attr.type & SL_MEDIA_TYPE_ELECTRICAL)
+		link_info->port_type = PORT_TP;
+	else
+		link_info->port_type = PORT_OTHER;
+
+	/* fec type */
+	if (cass_dev->sl.link_up_fec_type == SL_LGRP_CONFIG_FEC_RS)
+		link_info->fec_type = ETHTOOL_FEC_RS;
+	else if (cass_dev->sl.link_up_fec_type == SL_LGRP_CONFIG_FEC_RS_LL)
+		link_info->fec_type = ETHTOOL_FEC_LLRS;
+	else
+		link_info->fec_type = ETHTOOL_FEC_OFF;
+
+	cxidev_dbg(&cass_dev->cdev,
+		   "sl mode get (type = %u, AN = %u, speed = %u, llr = %lu, fec = %u, LB = %lu, R1 = %u)\n",
+		   link_info->port_type, link_info->autoneg, link_info->speed,
+		   link_info->flags & CXI_ETH_PF_LLR, !!(link_info->flags & CXI_ETH_PF_FEC_MONITOR),
+		   link_info->flags & LOOPBACK_MODE, !!(link_info->flags & CXI_ETH_PF_R1_LINK_PARTNER));
+}
+
+static void cass_sl_mode_set_autoneg_enable(struct cass_dev *cass_dev)
+{
+	cass_dev->sl.link_config.options |= SL_LINK_CONFIG_OPT_AUTONEG_ENABLE;
+	cass_dev->sl.lgrp_config.tech_map = cass_dev->sl.autoneg_tech_map;
+}
+
+static void cass_sl_mode_set_autoneg_disable(struct cass_dev *cass_dev)
+{
+	cass_dev->sl.link_config.options &= ~SL_LINK_CONFIG_OPT_AUTONEG_ENABLE;
+	cass_dev->sl.lgrp_config.tech_map = cass_dev->sl.static_tech_map;
+}
+
+void cass_sl_mode_set(struct cass_dev *cass_dev, const struct cxi_link_info *link_info)
+{
+	struct sl_link_config *link_config;
+	struct sl_link_policy *link_policy;
+	struct sl_lgrp_config *lgrp_config;
+	u32                    autoneg_mode;
+	u32                    tech_mode;
+	bool                   is_mode_changed;
+
+	cxidev_dbg(&cass_dev->cdev, "sl mode set\n");
+
+	link_config = &cass_dev->sl.link_config;
+	link_policy = &cass_dev->sl.link_policy;
+	lgrp_config = &cass_dev->sl.lgrp_config;
+	is_mode_changed = false;
+
+	/* speed */
+	cxidev_dbg(&cass_dev->cdev, "sl mode set (speed = %d)\n", link_info->speed);
+	tech_mode = cass_sl_tech_get(link_info->speed);
+	if (tech_mode && cass_dev->sl.static_tech_map != tech_mode) {
+		cxidev_dbg(&cass_dev->cdev, "sl mode set tech_mode to 0x%X\n", tech_mode);
+		cass_dev->sl.static_tech_map = tech_mode;
+		if (!(cass_dev->sl.link_config.options & SL_LINK_CONFIG_OPT_AUTONEG_ENABLE))
+			cass_dev->sl.lgrp_config.tech_map = cass_dev->sl.static_tech_map;
+		is_mode_changed = true;
+	}
+
+	/* auto neg */
+	cxidev_dbg(&cass_dev->cdev, "sl mode set (autoneg = %d)\n", link_info->autoneg);
+	autoneg_mode = link_config->options & SL_LINK_CONFIG_OPT_AUTONEG_ENABLE;
+	switch (link_info->autoneg) {
+	case AUTONEG_DISABLE:
+		if (autoneg_mode == 0)
+			break;
+		cxidev_dbg(&cass_dev->cdev, "sl mode set autoneg to off\n");
+		cass_sl_mode_set_autoneg_disable(cass_dev);
+		is_mode_changed = true;
+		break;
+	case AUTONEG_ENABLE:
+		if (autoneg_mode != 0)
+			break;
+		cxidev_dbg(&cass_dev->cdev, "sl mode set autoneg to on\n");
+		cass_sl_mode_set_autoneg_enable(cass_dev);
+		is_mode_changed = true;
+		break;
+	}
+
+	/* llr */
+	cxidev_dbg(&cass_dev->cdev, "sl mode set (llr = %d)\n",
+		   !!(link_info->flags & CXI_ETH_PF_LLR));
+	switch (link_info->flags & CXI_ETH_PF_LLR) {
+	case 0:
+		if (!cass_dev->sl.enable_llr)
+			break;
+		cxidev_dbg(&cass_dev->cdev, "sl mode set LLR to off\n");
+		cass_dev->sl.enable_llr = false;
+		cass_dev->sl.link_config.hpe_map &= ~SL_LINK_CONFIG_HPE_LLR;
+		is_mode_changed = true;
+		break;
+	case CXI_ETH_PF_LLR:
+		if (cass_dev->sl.enable_llr)
+			break;
+		cxidev_dbg(&cass_dev->cdev, "sl mode set LLR to on\n");
+		cass_dev->sl.enable_llr = true;
+		cass_dev->sl.link_config.hpe_map |= SL_LINK_CONFIG_HPE_LLR;
+		is_mode_changed = true;
+		break;
+	}
+
+	/* link training */
+	cxidev_dbg(&cass_dev->cdev, "sl mode set (linktrain = 0x%lX)\n",
+		   link_info->flags & CXI_ETH_PF_LINKTRAIN);
+	switch (link_info->flags & CXI_ETH_PF_LINKTRAIN) {
+	case 0:
+		if (!(link_config->hpe_map & SL_LINK_CONFIG_HPE_LINKTRAIN))
+			break;
+		cxidev_dbg(&cass_dev->cdev, "sl mode set linktrain to off\n");
+		link_config->hpe_map &= ~SL_LINK_CONFIG_HPE_LINKTRAIN;
+		is_mode_changed = true;
+		break;
+	case CXI_ETH_PF_LINKTRAIN:
+		if (link_config->hpe_map & SL_LINK_CONFIG_HPE_LINKTRAIN)
+			break;
+		cxidev_dbg(&cass_dev->cdev, "sl mode set linktrain to on\n");
+		link_config->hpe_map |= SL_LINK_CONFIG_HPE_LINKTRAIN;
+		is_mode_changed = true;
+		break;
+	}
+
+	/* loopback */
+	cxidev_dbg(&cass_dev->cdev, "sl mode set (loopback_mode = %lu)\n",
+		   link_info->flags & LOOPBACK_MODE);
+	switch (link_info->flags & LOOPBACK_MODE) {
+	case 0:
+		if (!(lgrp_config->options & SL_LGRP_CONFIG_OPT_SERDES_LOOPBACK_ENABLE) &&
+		    !(link_config->options & SL_LINK_CONFIG_OPT_REMOTE_LOOPBACK_ENABLE))
+			break;
+		cxidev_dbg(&cass_dev->cdev, "sl mode set loopback to off\n");
+		lgrp_config->options &= ~SL_LGRP_CONFIG_OPT_SERDES_LOOPBACK_ENABLE;
+		link_config->options &= ~SL_LINK_CONFIG_OPT_REMOTE_LOOPBACK_ENABLE;
+		if (cass_dev->sl.old_an_mode == AUTONEG_ENABLE)
+			cass_sl_mode_set_autoneg_enable(cass_dev);
+		else
+			cass_sl_mode_set_autoneg_disable(cass_dev);
+		if (cass_dev->sl.old_lt_mode)
+			link_config->hpe_map |= SL_LINK_CONFIG_HPE_LINKTRAIN;
+		else
+			link_config->hpe_map &= ~SL_LINK_CONFIG_HPE_LINKTRAIN;
+		is_mode_changed = true;
+		break;
+	case CXI_ETH_PF_INTERNAL_LOOPBACK:
+		if (lgrp_config->options & SL_LGRP_CONFIG_OPT_SERDES_LOOPBACK_ENABLE)
+			break;
+		cxidev_dbg(&cass_dev->cdev, "sl mode set serdes loopback to on\n");
+		lgrp_config->options |= SL_LGRP_CONFIG_OPT_SERDES_LOOPBACK_ENABLE;
+		cass_sl_mode_set_autoneg_disable(cass_dev);
+		link_config->options &= ~SL_LINK_CONFIG_OPT_REMOTE_LOOPBACK_ENABLE;
+		cass_dev->sl.old_an_mode = link_info->autoneg;
+		cass_dev->sl.old_lt_mode = (link_config->hpe_map & SL_LINK_CONFIG_HPE_LINKTRAIN);
+		link_config->hpe_map &= ~SL_LINK_CONFIG_HPE_LINKTRAIN;
+		is_mode_changed = true;
+		break;
+	case CXI_ETH_PF_EXTERNAL_LOOPBACK:
+		if (link_config->options & SL_LINK_CONFIG_OPT_REMOTE_LOOPBACK_ENABLE)
+			break;
+		cxidev_dbg(&cass_dev->cdev, "sl mode set remote loopback to on\n");
+		link_config->options |= SL_LINK_CONFIG_OPT_REMOTE_LOOPBACK_ENABLE;
+		cass_sl_mode_set_autoneg_disable(cass_dev);
+		lgrp_config->options &= ~SL_LGRP_CONFIG_OPT_SERDES_LOOPBACK_ENABLE;
+		cass_dev->sl.old_an_mode = link_info->autoneg;
+		cass_dev->sl.old_lt_mode = (link_config->hpe_map & SL_LINK_CONFIG_HPE_LINKTRAIN);
+		link_config->hpe_map &= ~SL_LINK_CONFIG_HPE_LINKTRAIN;
+		is_mode_changed = true;
+		break;
+	}
+
+	cxidev_dbg(&cass_dev->cdev, "sl mode set (fec_monitor = %u)\n",
+		   !!(link_info->flags & CXI_ETH_PF_FEC_MONITOR));
+	switch (link_info->flags & CXI_ETH_PF_FEC_MONITOR) {
+	case 0:
+		if (link_policy->fec_mon_period_ms == 0)
+			break;
+		link_policy->fec_mon_period_ms = 0;
+		cxidev_dbg(&cass_dev->cdev, "sl mode set fec_monitor to off\n");
+		is_mode_changed = true;
+		break;
+	case CXI_ETH_PF_FEC_MONITOR:
+		if (link_policy->fec_mon_period_ms != 0)
+			break;
+		link_policy->fec_mon_period_ms = -1;
+		cxidev_dbg(&cass_dev->cdev, "sl mode set fec_monitor to on\n");
+		is_mode_changed = true;
+		break;
+	}
+
+	cxidev_dbg(&cass_dev->cdev, "sl mode set (los_lol_hide = %u)\n",
+		   !!(link_info->flags & CXI_ETH_PF_LOS_LOL_HIDE));
+	switch (link_info->flags & CXI_ETH_PF_LOS_LOL_HIDE) {
+	case 0:
+		if (!(link_config->options & SL_LINK_CONFIG_OPT_LOS_LOL_UP_FAIL_HIDE))
+			break;
+		cxidev_dbg(&cass_dev->cdev, "sl mode set los_lol_hide to off\n");
+		link_config->options &= ~SL_LINK_CONFIG_OPT_LOS_LOL_UP_FAIL_HIDE;
+		is_mode_changed = true;
+		break;
+	case CXI_ETH_PF_LOS_LOL_HIDE:
+		if (link_config->options & SL_LINK_CONFIG_OPT_LOS_LOL_UP_FAIL_HIDE)
+			break;
+		cxidev_dbg(&cass_dev->cdev, "sl mode set los_lol_hide to on\n");
+		link_config->options |= SL_LINK_CONFIG_OPT_LOS_LOL_UP_FAIL_HIDE;
+		is_mode_changed = true;
+		break;
+	}
+
+	cxidev_dbg(&cass_dev->cdev, "sl mode set (r1_link_partner = %u)\n",
+		   !!(link_info->flags & CXI_ETH_PF_R1_LINK_PARTNER));
+	switch (link_info->flags & CXI_ETH_PF_R1_LINK_PARTNER) {
+	case 0:
+		if (!(lgrp_config->options & SL_LGRP_CONFIG_OPT_R1))
+			break;
+		cxidev_dbg(&cass_dev->cdev, "sl mode set r1_link_partner to no\n");
+		lgrp_config->options &= ~SL_LGRP_CONFIG_OPT_R1;
+		is_mode_changed = true;
+		break;
+	case CXI_ETH_PF_R1_LINK_PARTNER:
+		if (lgrp_config->options & SL_LGRP_CONFIG_OPT_R1)
+			break;
+		cxidev_dbg(&cass_dev->cdev, "sl mode set r1_link_partner to yes\n");
+		lgrp_config->options |= SL_LGRP_CONFIG_OPT_R1;
+		is_mode_changed = true;
+		break;
+	}
+
+	/* if anything changed bounce the link */
+	cxidev_dbg(&cass_dev->cdev, "sl mode set (is_mode_changed = %d)\n", is_mode_changed);
+	if (is_mode_changed)
+		cass_phy_bounce(cass_dev);
+}
+
+/* SL has no ignore-align or remote-fault-recovery control; see flags_supported */
+void cass_sl_flags_get(struct cass_dev *cass_dev, u32 *flags)
+{
+	*flags = 0;
+}
+
+void cass_sl_flags_set(struct cass_dev *cass_dev, u32 clr_flags, u32 set_flags)
+{
+}
+
+void cass_sl_pml_recovery_set(struct cass_dev *cass_dev, bool set)
+{
+	cxidev_dbg(&cass_dev->cdev, "pml recovery set\n");
+
+	if (set)
+		cass_dev->sl.link_config.options |= SL_LINK_CONFIG_OPT_PML_REC_ENABLE;
+	else
+		cass_dev->sl.link_config.options &= ~SL_LINK_CONFIG_OPT_PML_REC_ENABLE;
+}
+
+struct cass_sl_intr_entry {
+	struct list_head        list;
+	sl_intr_handler_t       hdlr;
+	struct cxi_reg_err_flg  reg;
+	void                   *data;
+};
+
+static void cass_sl_intr_hdlr(struct cass_dev *cass_dev,
+			      unsigned int irq, bool is_ext, unsigned int bitn)
+{
+	struct cass_sl_intr_entry *intr;
+	DECLARE_BITMAP(ss2_port_pml_err_flgs, MAX_ERR_FLAG_BITLEN);
+
+	cxidev_dbg(&cass_dev->cdev, "sl intr handler (bit = %d)\n", bitn);
+
+	lockdep_assert_held(&cass_dev->err_flg_mutex);
+
+	list_for_each_entry(intr, &cass_dev->sl.intr_list, list) {
+		if (test_bit(bitn, intr->reg.err_flags.mask)) {
+			cxidev_dbg(&cass_dev->cdev, "call handler\n");
+			bitmap_zero(ss2_port_pml_err_flgs, MAX_ERR_FLAG_BITLEN);
+			set_bit(bitn, ss2_port_pml_err_flgs);
+			intr->hdlr((u64 *)ss2_port_pml_err_flgs, 4, intr->data);
+			break;
+		}
+	}
+}
+
+#define CASS_SL_SBUS_CMD_RESET 0x20
+static int cass_sl_sbus_op(void *sbus_accessor, u8 op, u8 ring, u8 dev_addr, u8 reg,
+			   u32 *rd_data, u32 wr_data)
+{
+	u32 rsp_data;
+	u8  result;
+	u8  overrun;
+	u8  error;
+
+	switch (op) {
+	case SL_SBUS_OP_RST:
+		return cass_sl_sbus_cmd(sbus_accessor, 0, 0, 0, dev_addr,
+					CASS_SL_SBUS_CMD_RESET, &rsp_data, &result,
+					&overrun, &error, 10, 0);
+	case SL_SBUS_OP_RD:
+		return cass_sl_sbus_rd(sbus_accessor, dev_addr, reg, rd_data);
+	case SL_SBUS_OP_WR:
+		return cass_sl_sbus_wr(sbus_accessor, dev_addr, reg, wr_data);
+	}
+
+	return -EBADRQC;
+}
+
+static int cass_sl_pmi_op(void *pmi_accessor, u8 lgrp_num, u8 op, u32 addr,
+			  u16 *rd_data, u16 wr_data, u16 wr_data_mask)
+{
+	switch (op) {
+	case SL_PMI_OP_RST:
+		// FIXME: need to implement
+		return 0;
+	case SL_PMI_OP_RD:
+		return cass_sl_pmi_rd(pmi_accessor, lgrp_num, addr, rd_data);
+	case SL_PMI_OP_WR:
+		return cass_sl_pmi_wr(pmi_accessor, lgrp_num, addr, wr_data, wr_data_mask);
+	}
+
+	return -EBADRQC;
+}
+
+static int cass_sl_intr_register(void *intr_accessor, u32 port_grp_num, char *tag,
+				 u64 *err_flgs, sl_intr_handler_t handler, void *data)
+{
+	struct cass_dev           *cass_dev = intr_accessor;
+	struct cass_sl_intr_entry *intr;
+
+	cxidev_dbg(&cass_dev->cdev, "sl intr register (0x%llX 0x%llX 0x%llX 0x%llX)\n",
+		*(err_flgs), *(err_flgs + 1), *(err_flgs + 2), *(err_flgs + 3));
+
+	intr = kzalloc(sizeof(*intr), GFP_KERNEL);
+	if (!intr)
+		return -ENOMEM;
+
+	INIT_LIST_HEAD(&intr->list);
+	intr->hdlr       = handler;
+	intr->reg.irq    = C_HNI_PML_IRQA_MSIX_INT;
+	intr->reg.is_ext = false;
+	intr->reg.cb     = cass_sl_intr_hdlr;
+	memcpy(&(intr->reg.err_flags.ss2_port_pml.qw[0]), err_flgs,
+	       sizeof(intr->reg.err_flags.ss2_port_pml.qw));
+	intr->data       = data;
+
+	mutex_lock(&cass_dev->sl.intr_lock);
+	mutex_lock(&cass_dev->err_flg_mutex);
+	list_add(&intr->list, &cass_dev->sl.intr_list);
+	mutex_unlock(&cass_dev->err_flg_mutex);
+
+	cxi_register_hw_errors(cass_dev, &(intr->reg));
+	mutex_unlock(&cass_dev->sl.intr_lock);
+
+	return 0;
+}
+
+static int cass_sl_intr_unregister(void *intr_accessor, u32 port_grp_num,
+				   u64 *err_flgs, sl_intr_handler_t handler)
+{
+	struct cass_dev           *cass_dev = intr_accessor;
+	struct cass_sl_intr_entry *intr;
+
+	cxidev_dbg(&cass_dev->cdev, "sl intr unregister (0x%llX 0x%llX 0x%llX 0x%llX)\n",
+		*(err_flgs), *(err_flgs + 1), *(err_flgs + 2), *(err_flgs + 3));
+
+	mutex_lock(&cass_dev->sl.intr_lock);
+	list_for_each_entry(intr, &cass_dev->sl.intr_list, list) {
+		if (memcmp(&(intr->reg.err_flags.ss2_port_pml.qw[0]), err_flgs,
+			   sizeof(intr->reg.err_flags.ss2_port_pml.qw)) == 0) {
+			cxidev_dbg(&cass_dev->cdev, "match\n");
+			cxi_unregister_hw_errors(cass_dev, &(intr->reg));
+			mutex_lock(&cass_dev->err_flg_mutex);
+			list_del(&(intr->list));
+			mutex_unlock(&cass_dev->err_flg_mutex);
+			kfree(intr);
+			mutex_unlock(&cass_dev->sl.intr_lock);
+			return 0;
+		}
+	}
+	mutex_unlock(&cass_dev->sl.intr_lock);
+
+	return -EBADRQC;
+}
+
+static int cass_sl_intr_enable(void *intr_accessor, u32 port_grp_num,
+			       u64 *err_flgs, sl_intr_handler_t handler)
+{
+	struct cass_dev *cass_dev = intr_accessor;
+
+	cxidev_dbg(&cass_dev->cdev, "sl intr enable (0x%llX 0x%llX 0x%llX 0x%llX)\n",
+		*(err_flgs), *(err_flgs + 1), *(err_flgs + 2), *(err_flgs + 3));
+
+	cxi_enable_hw_errors(cass_dev, C_HNI_PML_IRQA_MSIX_INT,
+			     false, (unsigned long *)err_flgs);
+
+	return 0;
+}
+
+static int cass_sl_intr_disable(void *intr_accessor, u32 port_grp_num,
+				u64 *err_flgs, sl_intr_handler_t handler)
+{
+	struct cass_dev *cass_dev = intr_accessor;
+
+	cxidev_dbg(&cass_dev->cdev, "sl intr disable (0x%llX 0x%llX 0x%llX 0x%llX)\n",
+		*(err_flgs), *(err_flgs + 1), *(err_flgs + 2), *(err_flgs + 3));
+
+	cxi_disable_hw_errors(cass_dev, C_HNI_PML_IRQA_MSIX_INT,
+			      false, (unsigned long *)err_flgs);
+
+	return 0;
+}
+
+static int cass_sl_dt_info_get(void *dt_accessor, u8 ldev_num, u8 lgrp_num,
+			       struct sl_dt_lgrp_info *info)
+{
+	struct cass_dev *cass_dev = dt_accessor;
+
+	cxidev_dbg(&cass_dev->cdev, "sl dt info get\n");
+
+	info->sbus_ring = 0;
+	info->dev_id    = 1;
+	info->dev_addr  = 0x5;
+
+	switch (cass_dev->uc_platform) {
+	case CUC_BOARD_TYPE_WASHINGTON:
+		switch (cass_dev->uc_nic) {
+		case 0:
+			/* TX: [3, 2, 1, 0] = {3, 2, 1, 0inv} */
+			info->lane_info[3].tx_source = 3;
+			info->lane_info[3].tx_invert = 0;
+			info->lane_info[2].tx_source = 2;
+			info->lane_info[2].tx_invert = 0;
+			info->lane_info[1].tx_source = 1;
+			info->lane_info[1].tx_invert = 0;
+			info->lane_info[0].tx_source = 0;
+			info->lane_info[0].tx_invert = 1;
+			/* RX: [3, 2, 1, 0] = {3, 2, 1, 0} */
+			info->lane_info[3].rx_source = 3;
+			info->lane_info[3].rx_invert = 0;
+			info->lane_info[2].rx_source = 2;
+			info->lane_info[2].rx_invert = 0;
+			info->lane_info[1].rx_source = 1;
+			info->lane_info[1].rx_invert = 0;
+			info->lane_info[0].rx_source = 0;
+			info->lane_info[0].rx_invert = 0;
+			break;
+		case 1:
+			/* TX: [3, 2, 1, 0] = {3, 2, 1inv, 0} */
+			info->lane_info[3].tx_source = 3;
+			info->lane_info[3].tx_invert = 0;
+			info->lane_info[2].tx_source = 2;
+			info->lane_info[2].tx_invert = 0;
+			info->lane_info[1].tx_source = 1;
+			info->lane_info[1].tx_invert = 1;
+			info->lane_info[0].tx_source = 0;
+			info->lane_info[0].tx_invert = 0;
+			/* RX: [3, 2, 1, 0] = {3, 2inv, 1inv, 0inv} */
+			info->lane_info[3].rx_source = 3;
+			info->lane_info[3].rx_invert = 0;
+			info->lane_info[2].rx_source = 2;
+			info->lane_info[2].rx_invert = 1;
+			info->lane_info[1].rx_source = 1;
+			info->lane_info[1].rx_invert = 1;
+			info->lane_info[0].rx_source = 0;
+			info->lane_info[0].rx_invert = 1;
+			break;
+		}
+		break;
+	case CUC_BOARD_TYPE_KENNEBEC:
+		/* TX: [3, 2, 1, 0] = {1inv, 0, 2inv, 3} */
+		/* CSR:      serdes = logical            */
+		info->lane_info[3].tx_source = 1;
+		info->lane_info[3].tx_invert = 1;
+		info->lane_info[2].tx_source = 0;
+		info->lane_info[2].tx_invert = 0;
+		info->lane_info[1].tx_source = 2;
+		info->lane_info[1].tx_invert = 1;
+		info->lane_info[0].tx_source = 3;
+		info->lane_info[0].tx_invert = 0;
+		/* RX: [3, 2, 1, 0] = {2inv, 3, 1inv, 0} */
+		/* CSR:     logical = serdes             */
+		info->lane_info[3].rx_source = 2;
+		info->lane_info[3].rx_invert = 1;
+		info->lane_info[2].rx_source = 3;
+		info->lane_info[2].rx_invert = 0;
+		info->lane_info[1].rx_source = 1;
+		info->lane_info[1].rx_invert = 1;
+		info->lane_info[0].rx_source = 0;
+		info->lane_info[0].rx_invert = 0;
+		break;
+	case CUC_BOARD_TYPE_SOUHEGAN:
+		cxidev_dbg(&cass_dev->cdev,
+			   "sl dt info get SOUHEGAN (nic = %d)\n", cass_dev->uc_nic);
+		/* Lane         3210              3210
+		   ---------------------------------------------
+		   -tx-lane-map 2310 -rx-lane-map 1023 -a :5.*
+		   -tx-lane-map 0132 -rx-lane-map 2013 -a 1:5.*  */
+		switch (cass_dev->uc_nic) {
+		case 0:
+			/* TX: [3, 2, 1, 0] = {2, 3, 1, 0} */
+			/* CSR:      serdes = logical      */
+			info->lane_info[3].tx_source = 2;
+			info->lane_info[3].tx_invert = 0;
+			info->lane_info[2].tx_source = 3;
+			info->lane_info[2].tx_invert = 0;
+			info->lane_info[1].tx_source = 1;
+			info->lane_info[1].tx_invert = 0;
+			info->lane_info[0].tx_source = 0;
+			info->lane_info[0].tx_invert = 0;
+			/* RX: [3, 2, 1, 0] = {1, 0, 2, 3} */
+			/* CSR:     logical = serdes       */
+			info->lane_info[3].rx_source = 1;
+			info->lane_info[3].rx_invert = 0;
+			info->lane_info[2].rx_source = 0;
+			info->lane_info[2].rx_invert = 0;
+			info->lane_info[1].rx_source = 2;
+			info->lane_info[1].rx_invert = 0;
+			info->lane_info[0].rx_source = 3;
+			info->lane_info[0].rx_invert = 0;
+			break;
+		case 1:
+			/* TX: [3, 2, 1, 0] = {0, 1, 3, 2} */
+			/* CSR:      serdes = logical      */
+			info->lane_info[3].tx_source = 0;
+			info->lane_info[3].tx_invert = 0;
+			info->lane_info[2].tx_source = 1;
+			info->lane_info[2].tx_invert = 0;
+			info->lane_info[1].tx_source = 3;
+			info->lane_info[1].tx_invert = 0;
+			info->lane_info[0].tx_source = 2;
+			info->lane_info[0].tx_invert = 0;
+			/* RX: [3, 2, 1, 0] = {2, 0, 1, 3} */
+			/* CSR:     logical = serdes       */
+			info->lane_info[3].rx_source = 2;
+			info->lane_info[3].rx_invert = 0;
+			info->lane_info[2].rx_source = 0;
+			info->lane_info[2].rx_invert = 0;
+			info->lane_info[1].rx_source = 1;
+			info->lane_info[1].rx_invert = 0;
+			info->lane_info[0].rx_source = 3;
+			info->lane_info[0].rx_invert = 0;
+			break;
+		}
+		break;
+	default:  /* straight */
+		info->lane_info[3].tx_source = 3;
+		info->lane_info[3].tx_invert = 0;
+		info->lane_info[2].tx_source = 2;
+		info->lane_info[2].tx_invert = 0;
+		info->lane_info[1].tx_source = 1;
+		info->lane_info[1].tx_invert = 0;
+		info->lane_info[0].tx_source = 0;
+		info->lane_info[0].tx_invert = 0;
+		break;
+	}
+
+	return 0;
+}
+
+static int cass_sl_mb_info_get(void *mb_accessor, u8 *platform, u16 *revision, u16 *proto)
+{
+	struct cass_dev *cass_dev = mb_accessor;
+
+	cxidev_dbg(&cass_dev->cdev, "sl mb info get\n");
+
+	if (platform)
+		*platform = HW_PLATFORM(cass_dev);
+	if (revision)
+		*revision = 0;
+	if (proto)
+		*proto = 0;
+
+	return 0;
+}
+
+static int cass_sl_dmac_alloc(void *dmac_accessor, u32 offset, size_t size)
+{
+	int              rtn;
+	struct cass_dev *cass_dev = dmac_accessor;
+
+	cxidev_dbg(&cass_dev->cdev, "sl dmac alloc\n");
+
+	rtn = cxi_dmac_desc_set_alloc(&cass_dev->cdev, 1, "fec_id");
+	if (rtn < 0) {
+		cxidev_err(&cass_dev->cdev,
+			   "cxi_dmac_desc_set_alloc failed [%d]\n", rtn);
+		return rtn;
+	}
+	cass_dev->sl.fec.dma_id = rtn;
+	cxidev_dbg(&cass_dev->cdev, "dma_id = %d\n", cass_dev->sl.fec.dma_id);
+
+	cass_dev->sl.fec.cntrs = dma_alloc_coherent(&cass_dev->cdev.pdev->dev, size,
+						    &cass_dev->sl.fec.dma_addr, GFP_KERNEL);
+	if (!cass_dev->sl.fec.cntrs) {
+		rtn = -ENOMEM;
+		goto out_dmac_fini;
+	}
+
+	cxidev_dbg(&cass_dev->cdev, "cntrs = %p\n", cass_dev->sl.fec.cntrs);
+	cass_dev->sl.fec.cntrs_size = size;
+
+	rtn = cxi_dmac_desc_set_add(&cass_dev->cdev, cass_dev->sl.fec.dma_id,
+				    cass_dev->sl.fec.dma_addr, offset, size);
+	if (rtn) {
+		cxidev_err(&cass_dev->cdev,
+			   "cxi_dmac_desc_set_add failed [%d]\n", rtn);
+		goto out_dma_free;
+	}
+
+	return 0;
+
+out_dma_free:
+	dma_free_coherent(&cass_dev->cdev.pdev->dev, size, cass_dev->sl.fec.cntrs, cass_dev->sl.fec.dma_addr);
+out_dmac_fini:
+	cxi_dmac_desc_set_free(&cass_dev->cdev, cass_dev->sl.fec.dma_id);
+
+	return rtn;
+}
+
+static void cass_sl_dmac_free(void *dmac_accessor)
+{
+	struct cass_dev *cass_dev = dmac_accessor;
+
+	cxidev_dbg(&cass_dev->cdev, "sl dmac free\n");
+
+	cxi_dmac_desc_set_free(&cass_dev->cdev, cass_dev->sl.fec.dma_id);
+	dma_free_coherent(&cass_dev->cdev.pdev->dev, cass_dev->sl.fec.cntrs_size, cass_dev->sl.fec.cntrs,
+			  cass_dev->sl.fec.dma_addr);
+}
+
+static int cass_sl_dmac_xfer(void *dmac_accessor, void *data)
+{
+	int              rtn;
+	struct cass_dev *cass_dev = dmac_accessor;
+
+	cxidev_dbg(&cass_dev->cdev, "sl dmac xfer\n");
+
+	rtn = cxi_dmac_xfer(&cass_dev->cdev, cass_dev->sl.fec.dma_id);
+	if (rtn) {
+		cxidev_err(&cass_dev->cdev, "Unable to get fec cntrs [%d]\n", rtn);
+		return rtn;
+	}
+
+	memcpy(data, cass_dev->sl.fec.cntrs, cass_dev->sl.fec.cntrs_size);
+
+	return 0;
+}
+
+static void cass_sl_ops_init(struct cass_dev *cass_dev)
+{
+	cass_dev->sl.ops.read64              = cass_sl_read64;
+	cass_dev->sl.ops.write64             = cass_sl_write64;
+
+	cass_dev->sl.ops.sbus_op             = cass_sl_sbus_op;
+	cass_dev->sl.ops.pmi_op              = cass_sl_pmi_op;
+
+	cass_dev->sl.ops.pml_intr_register   = cass_sl_intr_register;
+	cass_dev->sl.ops.pml_intr_unregister = cass_sl_intr_unregister;
+	cass_dev->sl.ops.pml_intr_enable     = cass_sl_intr_enable;
+	cass_dev->sl.ops.pml_intr_disable    = cass_sl_intr_disable;
+
+	cass_dev->sl.ops.dt_info_get         = cass_sl_dt_info_get;
+	cass_dev->sl.ops.mb_info_get         = cass_sl_mb_info_get;
+	cass_dev->sl.ops.dmac_alloc          = cass_sl_dmac_alloc;
+	cass_dev->sl.ops.dmac_xfer           = cass_sl_dmac_xfer;
+	cass_dev->sl.ops.dmac_free           = cass_sl_dmac_free;
+
+	cass_dev->sl.accessors.pci           = cass_dev;
+	cass_dev->sl.accessors.sbus          = cass_dev;
+	cass_dev->sl.accessors.pmi           = cass_dev;
+	cass_dev->sl.accessors.intr          = cass_dev;
+	cass_dev->sl.accessors.dt            = cass_dev;
+	cass_dev->sl.accessors.mb            = cass_dev;
+	cass_dev->sl.accessors.dmac          = cass_dev;
+
+	cass_dev->sl.enable_llr              = true;
+	cass_dev->sl.is_canceled             = false;
+}
+
+#define CASS_SL_CALLBACKS (SL_LGRP_NOTIF_MEDIA_PRESENT     | \
+			   SL_LGRP_NOTIF_MEDIA_NOT_PRESENT | \
+			   SL_LGRP_NOTIF_LANE_DEGRADE      | \
+			   SL_LGRP_NOTIF_LINK_UP           | \
+			   SL_LGRP_NOTIF_LINK_UP_FAIL      | \
+			   SL_LGRP_NOTIF_LINK_ASYNC_DOWN   | \
+			   SL_LGRP_NOTIF_LINK_DOWN         | \
+			   SL_LGRP_NOTIF_LINK_ERROR        | \
+			   SL_LGRP_NOTIF_LLR_SETUP         | \
+			   SL_LGRP_NOTIF_LLR_SETUP_TIMEOUT | \
+			   SL_LGRP_NOTIF_LLR_RUNNING       | \
+			   SL_LGRP_NOTIF_LLR_START_TIMEOUT | \
+			   SL_LGRP_NOTIF_LLR_ERROR)
+
+static void cass_sl_uc_led_set(void *uc_accessor, u8 led_state)
+{
+	struct cass_dev *hw = uc_accessor;
+
+	cxidev_dbg(&hw->cdev, "sl uc led set (state = %u)\n", led_state);
+
+	uc_cmd_set_link_leds(hw, (enum casuc_led_states)led_state);
+}
+
+static void cass_sl_uc_ops_init(struct cass_dev *cass_dev)
+{
+	cass_dev->sl.uc_ops.uc_read    = cass_sl_uc_read;
+	cass_dev->sl.uc_ops.uc_write8  = cass_sl_uc_write8;
+	cass_dev->sl.uc_ops.uc_led_set = cass_sl_uc_led_set;
+
+	cass_dev->sl.uc_accessor.uc = cass_dev;
+}
+
+static void cass_sl_callback(void *tag, struct sl_lgrp_notif_msg *msg)
+{
+	struct cass_dev *cass_dev = tag;
+
+	cxidev_dbg(&cass_dev->cdev, "callback (type = 0x%X)\n", msg->type);
+
+	switch (msg->type) {
+	case SL_LGRP_NOTIF_MEDIA_PRESENT:
+		cass_dev->sl.media_attr = msg->info.media_attr;
+		if (msg->info.media_attr.type & SL_MEDIA_TYPE_ACTIVE) {
+			cass_dev->sl.link_config.hpe_map &= ~SL_LINK_CONFIG_HPE_LINKTRAIN;
+			cass_sl_mode_set_autoneg_disable(cass_dev);
+		} else {
+			cass_dev->sl.link_config.hpe_map |= SL_LINK_CONFIG_HPE_LINKTRAIN;
+			cass_sl_mode_set_autoneg_enable(cass_dev);
+		}
+		cass_dev->sl.has_cable = true;
+		break;
+	case SL_LGRP_NOTIF_MEDIA_NOT_PRESENT:
+		memset(&cass_dev->sl.media_attr, 0, sizeof(cass_dev->sl.media_attr));
+		cass_dev->sl.has_cable = false;
+		break;
+	case SL_LGRP_NOTIF_LANE_DEGRADE:
+		cxidev_info(&cass_dev->cdev, "lane degrade occurred (rx_degrade_map = 0x%X, tx_degrade_map = 0x%X)\n",
+			    msg->info.degrade_info.rx_degrade_map,
+			    msg->info.degrade_info.tx_degrade_map);
+		break;
+	case SL_LGRP_NOTIF_LINK_UP:
+		cass_dev->sl.link_state = SL_LINK_STATE_UP;
+		cass_dev->sl.link_up_mode = msg->info.link_up.mode;
+		cass_dev->sl.link_up_fec_type = msg->info.link_up.fec_type;
+		complete(&(cass_dev->sl.step_complete));
+		break;
+	case SL_LGRP_NOTIF_LINK_UP_FAIL:
+	case SL_LGRP_NOTIF_LINK_ASYNC_DOWN:
+	case SL_LGRP_NOTIF_LINK_ERROR:
+		cass_dev->sl.link_state = SL_LINK_STATE_DOWN;
+		complete(&(cass_dev->sl.step_complete));
+		cass_link_async_down(cass_dev, CASS_DOWN_ORIGIN_BL_DOWN);
+		break;
+	case SL_LGRP_NOTIF_LLR_START_TIMEOUT:
+	case SL_LGRP_NOTIF_LLR_SETUP_TIMEOUT:
+	case SL_LGRP_NOTIF_LLR_ERROR:
+		cass_dev->sl.llr_state = SL_LLR_STATE_OFF;
+		complete(&(cass_dev->sl.step_complete));
+		cass_link_async_down(cass_dev, CASS_DOWN_ORIGIN_BL_DOWN);
+		break;
+	case SL_LGRP_NOTIF_LLR_SETUP:
+		cass_dev->sl.llr_state = SL_LLR_STATE_SETUP;
+		cass_dev->sl.llr_data = msg->info.llr_data;
+		complete(&(cass_dev->sl.step_complete));
+		break;
+	case SL_LGRP_NOTIF_LLR_RUNNING:
+		cass_dev->sl.llr_state = SL_LLR_STATE_RUNNING;
+		complete(&(cass_dev->sl.step_complete));
+		break;
+	case SL_LGRP_NOTIF_LINK_DOWN:
+		cass_dev->sl.link_state = SL_LINK_STATE_DOWN;
+		complete(&(cass_dev->sl.step_complete));
+		break;
+	default:
+		cxidev_err(&cass_dev->cdev, "callback error (type = 0x%X)\n", msg->type);
+		break;
+	}
+}
+
+#define CASS_SL_LINK_UP_TIMEOUT_MS    35000
+#define CASS_SL_LLR_SETUP_TIMEOUT_MS  4000
+#define CASS_SL_LLR_START_TIMEOUT_MS  3000
+static void cass_sl_config_init(struct cass_dev *cass_dev)
+{
+	cxidev_dbg(&cass_dev->cdev,
+		   "sl config init (platform = %d, cxi = %u, nic = %d)\n",
+		   HW_PLATFORM(cass_dev), cass_dev->cdev.cxi_num, cass_dev->uc_nic);
+
+	cass_dev->sl.hw_attr.magic   = SL_HW_ATTR_MAGIC;
+	cass_dev->sl.hw_attr.ver     = SL_HW_ATTR_VER;
+	cass_dev->sl.hw_attr.nic_num = cass_dev->uc_nic;
+	cass_dev->sl.hw_attr.cxi_num = cass_dev->cdev.cxi_num;
+
+	cass_dev->sl.ldev_config.magic     = SL_LDEV_ATTR_MAGIC;
+	cass_dev->sl.ldev_config.ver       = SL_LDEV_ATTR_VER;
+	cass_dev->sl.ldev_config.accessors = &(cass_dev->sl.accessors);
+	cass_dev->sl.ldev_config.ops       = &(cass_dev->sl.ops);
+
+	cass_dev->sl.lgrp_config.magic     = SL_LGRP_CONFIG_MAGIC;
+	cass_dev->sl.lgrp_config.ver       = SL_LGRP_CONFIG_VER;
+	cass_dev->sl.lgrp_config.mfs       = 9216;
+	cass_dev->sl.lgrp_config.furcation = SL_MEDIA_FURCATION_X1;
+	cass_dev->sl.lgrp_config.fec_mode  = SL_LGRP_FEC_MODE_OFF;
+	cass_dev->sl.lgrp_config.fec_map   = SL_LGRP_CONFIG_FEC_RS;
+	cass_dev->sl.lgrp_config.options   = 0;
+	cass_dev->sl.static_tech_map       = SL_LGRP_CONFIG_TECH_CK_400G;
+	cass_dev->sl.autoneg_tech_map      = SL_LGRP_CONFIG_TECH_CK_400G |
+					     SL_LGRP_CONFIG_TECH_BS_200G |
+					     SL_LGRP_CONFIG_TECH_BJ_100G;
+	cass_dev->sl.link_up_mode          = 0;
+	cass_dev->sl.link_up_fec_type      = 0;
+	cass_sl_mode_set_autoneg_enable(cass_dev);
+
+	cass_dev->sl.link_config.magic                             = SL_LINK_CONFIG_MAGIC;
+	cass_dev->sl.link_config.ver                               = SL_LINK_CONFIG_VER;
+	cass_dev->sl.link_config.link_up_timeout_ms                = CASS_SL_LINK_UP_TIMEOUT_MS;
+	cass_dev->sl.link_config.link_up_tries_max                 = 1;
+	cass_dev->sl.link_config.fec_up_settle_wait_ms             = -1;
+	cass_dev->sl.link_config.fec_up_check_wait_ms              = -1;
+	cass_dev->sl.link_config.fec_up_ucw_limit                  = -1;
+	cass_dev->sl.link_config.fec_up_ccw_limit                  = -1;
+	cass_dev->sl.link_config.pml_rec_timeout_ms                = cass_sl_pml_rec_timeout_ms;
+	cass_dev->sl.link_config.pml_rec_rate_limit_max_time_ms    = cass_sl_pml_rec_rate_limit_max_time_ms;
+	cass_dev->sl.link_config.pml_rec_rate_limit_window_size_ms = cass_sl_pml_rec_rate_limit_win_size_ms;
+	cass_dev->sl.link_config.pause_map                         = 0;
+	cass_dev->sl.link_config.options                           = SL_LINK_CONFIG_OPT_PML_REC_ENABLE |
+								     SL_LINK_CONFIG_OPT_ALD_ENABLE;
+	cass_dev->sl.link_config.hpe_map                           = SL_LINK_CONFIG_HPE_C2;
+	cass_dev->sl.link_config.hpe_map                          |= SL_LINK_CONFIG_HPE_LINKTRAIN;
+	if (cass_dev->sl.enable_llr)
+		cass_dev->sl.link_config.hpe_map                  |= SL_LINK_CONFIG_HPE_LLR;
+
+	cass_dev->sl.link_policy.magic                   = SL_LINK_POLICY_MAGIC;
+	cass_dev->sl.link_policy.ver                     = SL_LINK_POLICY_VER;
+	cass_dev->sl.link_policy.fec_mon_ucw_down_limit  = -1;
+	cass_dev->sl.link_policy.fec_mon_ucw_warn_limit  = 0;
+	cass_dev->sl.link_policy.fec_mon_ccw_down_limit  = 0;
+	cass_dev->sl.link_policy.fec_mon_ccw_warn_limit  = 0;
+	cass_dev->sl.link_policy.fec_mon_period_ms       = -1;
+
+	cass_dev->sl.llr_config.magic            = SL_LLR_CONFIG_MAGIC;
+	cass_dev->sl.llr_config.ver              = SL_LLR_CONFIG_VER;
+	cass_dev->sl.llr_config.setup_timeout_ms = CASS_SL_LLR_SETUP_TIMEOUT_MS;
+	cass_dev->sl.llr_config.start_timeout_ms = CASS_SL_LLR_START_TIMEOUT_MS;
+}
+
+static int cass_sl_uc_ops_set(struct cass_dev *cass_dev)
+{
+	cxidev_dbg(&cass_dev->cdev, "sl_uc_ops_set\n");
+
+	return sl_ldev_uc_ops_set(cass_dev->sl.ldev, &(cass_dev->sl.uc_ops),
+				&(cass_dev->sl.uc_accessor));
+}
+
+int cass_sl_init(struct cass_dev *cass_dev)
+{
+	int  rtn;
+	char connect_id[12];
+
+	cxidev_dbg(&cass_dev->cdev, "sl init (cxi_num = %u)\n", cass_dev->cdev.cxi_num);
+
+	if (cass_dev->sl.is_initialized) {
+		cxidev_dbg(&cass_dev->cdev, "sl already initialized\n");
+		return -EBADRQC;
+	}
+
+	memset(&(cass_dev->sl), 0, sizeof(cass_dev->sl));
+
+	cass_sl_ops_init(cass_dev);
+	cass_sl_uc_ops_init(cass_dev);
+	cass_sl_config_init(cass_dev);
+
+	INIT_LIST_HEAD(&cass_dev->sl.intr_list);
+	mutex_init(&cass_dev->sl.intr_lock);
+
+	mutex_init(&cass_dev->sl.pmi_lock);
+	mutex_init(&cass_dev->sl.sbus_lock);
+
+	init_completion(&(cass_dev->sl.step_complete));
+
+	rtn = kobject_init_and_add(&cass_dev->port_kobj, &cass_sl_port_sysfs,
+				   &cass_dev->cdev.pdev->dev.kobj, "port");
+	if (rtn != 0) {
+		cxidev_err(&cass_dev->cdev,
+			   "kobject_init_and_add port failed [%d]\n", rtn);
+		goto out_kobject_put_port;
+	}
+	rtn = kobject_init_and_add(&cass_dev->port_num_kobj, &cass_sl_port_num_sysfs,
+				   &cass_dev->port_kobj, "0");
+	if (rtn != 0) {
+		cxidev_err(&cass_dev->cdev,
+			   "kobject_init_and_add port_num failed [%d]\n", rtn);
+		goto out_kobject_put_port_num;
+	}
+
+	cass_dev->sl.ldev = sl_ldev_new(cass_dev->cdev.cxi_num,
+					NULL, &(cass_dev->sl.ldev_config));
+	if (IS_ERR(cass_dev->sl.ldev)) {
+		rtn = PTR_ERR(cass_dev->sl.ldev);
+		cxidev_err(&cass_dev->cdev, "sl_ldev_new failed [%d]\n", rtn);
+		goto out_kobject_put_port_num;
+	}
+
+	rtn = sl_ldev_sysfs_parent_set(cass_dev->sl.ldev, &(cass_dev->port_num_kobj));
+	if (rtn) {
+		cxidev_err(&cass_dev->cdev, "sl_ldev_sysfs_parent_set failed [%d]\n", rtn);
+		goto out_ldev_del;
+	}
+
+	rtn = cass_sl_uc_ops_set(cass_dev);
+	if (rtn) {
+		cxidev_err(&cass_dev->cdev, "sl_uc_ops_set failed [%d]\n", rtn);
+		goto out_ldev_del;
+	}
+
+	cass_dev->sl.lgrp = sl_lgrp_new(cass_dev->sl.ldev,
+					CASS_SL_LGRP_NUM, &cass_dev->port_num_kobj);
+	if (IS_ERR(cass_dev->sl.lgrp)) {
+		rtn = PTR_ERR(cass_dev->sl.lgrp);
+		cxidev_err(&cass_dev->cdev, "sl_lgrp_new failed [%d]\n", rtn);
+		goto out_ldev_del;
+	}
+
+	cass_dev->sl.link = sl_link_new(cass_dev->sl.lgrp,
+					CASS_SL_LINK_NUM, &cass_dev->port_num_kobj);
+	if (IS_ERR(cass_dev->sl.link)) {
+		rtn = PTR_ERR(cass_dev->sl.link);
+		cxidev_err(&cass_dev->cdev, "sl_link_new failed [%d]\n", rtn);
+		goto out_lgrp_del;
+	}
+
+	cass_dev->sl.mac = sl_mac_new(cass_dev->sl.lgrp,
+				      CASS_SL_MAC_NUM, &cass_dev->port_num_kobj);
+	if (IS_ERR(cass_dev->sl.mac)) {
+		rtn = PTR_ERR(cass_dev->sl.mac);
+		cxidev_err(&cass_dev->cdev, "sl_mac_new failed [%d]\n", rtn);
+		goto out_link_del;
+	}
+
+	cass_dev->sl.llr = sl_llr_new(cass_dev->sl.lgrp,
+				      CASS_SL_LLR_NUM, &cass_dev->port_num_kobj);
+	if (IS_ERR(cass_dev->sl.llr)) {
+		rtn = PTR_ERR(cass_dev->sl.llr);
+		cxidev_err(&cass_dev->cdev, "sl_llr_new failed [%d]\n", rtn);
+		goto out_mac_del;
+	}
+
+	snprintf(connect_id, sizeof(connect_id), "cas[%d]", cass_dev->cdev.cxi_num);
+	rtn = sl_lgrp_connect_id_set(cass_dev->sl.lgrp, connect_id);
+	if (rtn != 0) {
+		cxidev_err(&cass_dev->cdev, "sl_lgrp_connect_id_set failed [%d]\n", rtn);
+		goto out_llr_del;
+	}
+
+	rtn = sl_lgrp_hw_attr_set(cass_dev->sl.lgrp, &cass_dev->sl.hw_attr);
+	if (rtn != 0) {
+		cxidev_err(&cass_dev->cdev, "sl_lgrp_hw_attr_set failed [%d]\n", rtn);
+		goto out_llr_del;
+	}
+
+	rtn = sl_lgrp_notif_callback_reg(cass_dev->sl.lgrp, cass_sl_callback, CASS_SL_CALLBACKS, cass_dev);
+	if (rtn != 0) {
+		cxidev_err(&cass_dev->cdev, "sl_lgrp_notif_callback_reg failed [%d]\n", rtn);
+		goto out_llr_del;
+	}
+
+	cass_dev->sl.is_initialized = true;
+
+	return 0;
+
+out_llr_del:
+	sl_llr_del(cass_dev->sl.llr);
+out_mac_del:
+	sl_mac_del(cass_dev->sl.mac);
+out_link_del:
+	sl_link_del(cass_dev->sl.link);
+out_lgrp_del:
+	sl_lgrp_del(cass_dev->sl.lgrp);
+out_ldev_del:
+	sl_ldev_del(cass_dev->sl.ldev);
+out_kobject_put_port_num:
+	kobject_put(&cass_dev->port_num_kobj);
+out_kobject_put_port:
+	kobject_put(&cass_dev->port_kobj);
+
+	return rtn;
+}
+
+int cass_sl_connect_id_set(struct cass_dev *cass_dev, const char *connect_id)
+{
+	int rtn;
+
+	cxidev_dbg(&cass_dev->cdev, "sl connect id set\n");
+
+	rtn = sl_lgrp_connect_id_set(cass_dev->sl.lgrp, connect_id);
+	if (rtn != 0) {
+		cxidev_err(&cass_dev->cdev, "sl_lgrp_connect_id failed [%d]\n", rtn);
+		return rtn;
+	}
+
+	return 0;
+}
+
+int cass_sl_media_config(struct cass_dev *cass_dev, void *unused)
+{
+	u32 flags = 0;
+
+	cxidev_dbg(&cass_dev->cdev, "media config\n");
+
+	if (cass_dev->uc_platform == CUC_BOARD_TYPE_WASHINGTON)
+		flags |= SL_MEDIA_TYPE_BACKPLANE;
+
+	return sl_media_cable_insert(cass_dev->sl.lgrp, cass_dev->qsfp_eeprom_page0,
+				     cass_dev->qsfp_eeprom_page1, flags);
+}
+
+int cass_sl_media_unconfig(struct cass_dev *cass_dev)
+{
+	cxidev_dbg(&cass_dev->cdev, "media unconfig\n");
+
+	return sl_media_cable_remove(cass_dev->sl.lgrp);
+}
+
+static void cass_sl_port_group_cfg_set(struct cass_dev *cass_dev)
+{
+	union ss2_port_pml_cfg_port_group config;
+
+	cxidev_dbg(&cass_dev->cdev, "sl port group cfg set\n");
+
+	cass_read(cass_dev, SS2_PORT_PML_CFG_PORT_GROUP, &config, sizeof(config));
+
+	/* EDGE1 */
+	config.pg_cfg = 0;
+
+	if (cass_dev->sl.lgrp_config.options & SL_LGRP_CONFIG_OPT_R1)
+		config.link_function = C2_LF_C2_R1;
+	else
+		config.link_function = C2_LF_C2_R2;
+
+	cass_write(cass_dev, SS2_PORT_PML_CFG_PORT_GROUP, &config, sizeof(config));
+}
+
+int cass_sl_link_config(struct cass_dev *cass_dev)
+{
+	/* NO-OP: configuration set happens during link up */
+	return 0;
+}
+
+bool cass_sl_is_link_up(struct cass_dev *cass_dev)
+{
+	return cass_dev->sl.link_state == SL_LINK_STATE_UP;
+}
+
+int cass_sl_link_up(struct cass_dev *cass_dev)
+{
+	int          rtn;
+	unsigned int timeleft;
+
+	cxidev_dbg(&cass_dev->cdev, "sl link up\n");
+
+	if (!cass_dev->sl.has_cable)
+		return 0;
+
+	if (cass_dev->sl.is_canceled)
+		return 0;
+
+	/* initial delay between attempts */
+	msleep(1000);
+
+	cass_dev->sl.link_state       = SL_LINK_STATE_DOWN;
+	cass_dev->sl.llr_state        = SL_LLR_STATE_OFF;
+	cass_dev->sl.link_up_mode     = 0;
+	cass_dev->sl.link_up_fec_type = 0;
+
+	if (!cass_dev->sl.is_fw_loaded) {
+		rtn = sl_ldev_serdes_init(cass_dev->sl.ldev);
+		if (rtn) {
+			cxidev_err(&cass_dev->cdev,
+				   "sl_ldev_serdes_init failed [%d]\n", rtn);
+			return rtn;
+		}
+		cass_dev->sl.is_fw_loaded = true;
+	}
+
+	/* config */
+	rtn = sl_lgrp_config_set(cass_dev->sl.lgrp, &cass_dev->sl.lgrp_config);
+	if (rtn != 0) {
+		cxidev_err(&cass_dev->cdev, "sl_lgrp_config_set failed [%d]\n", rtn);
+		return rtn;
+	}
+	rtn = sl_link_config_set(cass_dev->sl.link, &cass_dev->sl.link_config);
+	if (rtn != 0) {
+		cxidev_err(&cass_dev->cdev, "sl_link_config_set failed [%d]\n", rtn);
+		return rtn;
+	}
+	rtn = sl_link_policy_set(cass_dev->sl.link, &cass_dev->sl.link_policy);
+	if (rtn != 0) {
+		cxidev_err(&cass_dev->cdev, "sl_link_policy_set failed [%d]\n", rtn);
+		return rtn;
+	}
+	cass_sl_port_group_cfg_set(cass_dev);
+
+	if (cass_dev->sl.is_canceled)
+		return 0;
+
+	/* link up */
+	reinit_completion(&(cass_dev->sl.step_complete));
+	rtn = sl_link_up(cass_dev->sl.link);
+	if (rtn != 0) {
+		cxidev_err(&cass_dev->cdev, "sl_link_up failed [%d]\n", rtn);
+		goto out_no_link;
+	}
+	timeleft = wait_for_completion_timeout(&(cass_dev->sl.step_complete),
+		msecs_to_jiffies(2 * CASS_SL_LINK_UP_TIMEOUT_MS));
+	if (timeleft == 0) {
+		cxidev_dbg(&cass_dev->cdev, "sl_link_up timeout\n");
+		goto out_link_down;
+	}
+	if (cass_dev->sl.link_state != SL_LINK_STATE_UP) {
+		cxidev_dbg(&cass_dev->cdev, "sl_link_up not up\n");
+		goto out_link_down;
+	}
+
+	if (cass_dev->sl.is_canceled)
+		goto out_link_down;
+
+	/* enable MAC */
+	rtn = sl_mac_tx_start(cass_dev->sl.mac);
+	if (rtn != 0) {
+		cxidev_err(&cass_dev->cdev, "sl_mac_tx_start failed [%d]\n", rtn);
+		goto out_link_down;
+	}
+	rtn = sl_mac_rx_start(cass_dev->sl.mac);
+	if (rtn != 0) {
+		cxidev_err(&cass_dev->cdev, "sl_mac_rx_start failed [%d]\n", rtn);
+		goto out_mac_tx_stop;
+	}
+
+	if (cass_dev->sl.is_canceled)
+		goto out_mac_rx_stop;
+
+	/* LLR */
+	if (cass_dev->sl.enable_llr) {
+
+		/* config */
+		rtn = sl_llr_config_set(cass_dev->sl.llr, &cass_dev->sl.llr_config);
+		if (rtn != 0) {
+			cxidev_err(&cass_dev->cdev, "sl_llr_config_set failed [%d]\n", rtn);
+			goto out_mac_rx_stop;
+		}
+
+		/* setup */
+		reinit_completion(&(cass_dev->sl.step_complete));
+		rtn = sl_llr_setup(cass_dev->sl.llr);
+		if (rtn) {
+			cxidev_err(&cass_dev->cdev, "sl_llr_setup failed [%d]\n", rtn);
+			goto out_llr_stop;
+		}
+		timeleft = wait_for_completion_timeout(&(cass_dev->sl.step_complete),
+			msecs_to_jiffies(2 * CASS_SL_LLR_SETUP_TIMEOUT_MS));
+		if (timeleft == 0) {
+			cxidev_dbg(&cass_dev->cdev, "sl_llr_setup timeout\n");
+			goto out_llr_stop;
+		}
+		if (cass_dev->sl.llr_state != SL_LLR_STATE_SETUP) {
+			cxidev_dbg(&cass_dev->cdev, "sl_llr_setup not setup\n");
+			goto out_llr_stop;
+		}
+
+		/* start */
+		reinit_completion(&(cass_dev->sl.step_complete));
+		rtn = sl_llr_start(cass_dev->sl.llr);
+		if (rtn) {
+			cxidev_err(&cass_dev->cdev, "sl_llr_start failed [%d]\n", rtn);
+			goto out_llr_stop;
+		}
+		timeleft = wait_for_completion_timeout(&(cass_dev->sl.step_complete),
+			msecs_to_jiffies(2 * CASS_SL_LLR_START_TIMEOUT_MS));
+		if (timeleft == 0) {
+			cxidev_dbg(&cass_dev->cdev, "sl_llr_start timeout\n");
+			goto out_llr_stop;
+		}
+		if (cass_dev->sl.llr_state != SL_LLR_STATE_RUNNING) {
+			cxidev_dbg(&cass_dev->cdev, "sl_llr_start not running\n");
+			goto out_llr_stop;
+		}
+	}
+
+	if (cass_dev->sl.is_canceled)
+		goto out_llr_stop;
+
+	cass_link_set_state(cass_dev, CASS_LINK_STATUS_UP, 0);
+
+	return 0;
+
+out_llr_stop:
+	sl_llr_stop(cass_dev->sl.llr);
+	/* need to stop twice to make sure both setup and start are stopped */
+	sl_llr_stop(cass_dev->sl.llr);
+
+out_mac_rx_stop:
+	sl_mac_rx_stop(cass_dev->sl.mac);
+
+out_mac_tx_stop:
+	sl_mac_tx_stop(cass_dev->sl.mac);
+
+out_link_down:
+	reinit_completion(&(cass_dev->sl.step_complete));
+	rtn = sl_link_down(cass_dev->sl.link);
+	switch (rtn) {
+	case -EALREADY:
+		break;
+	case -EINPROGRESS:
+		msleep(500);
+		break;
+	case 0:
+		timeleft = wait_for_completion_timeout(&(cass_dev->sl.step_complete),
+			msecs_to_jiffies(2 * CASS_SL_LINK_DOWN_TIMEOUT_MS));
+		if (timeleft == 0)
+			cxidev_dbg(&cass_dev->cdev, "sl_link_down (link_up) timeout\n");
+		break;
+	default:
+		cxidev_warn(&cass_dev->cdev, "sl_link_down (link_up) failed [%d]\n", rtn);
+		break;
+	}
+
+out_no_link:
+
+	return -ENOLINK;
+}
+
+int cass_sl_link_down(struct cass_dev *cass_dev)
+{
+	int          rtn;
+	int          err = 0;
+	unsigned int timeleft;
+
+	cxidev_dbg(&cass_dev->cdev, "sl link down\n");
+
+	/* stop llr */
+	rtn = sl_llr_stop(cass_dev->sl.llr);
+	if (rtn) {
+		cxidev_warn(&cass_dev->cdev, "sl_llr_stop failed [%d]\n", rtn);
+		err = rtn;
+	}
+	/* need to stop twice to make sure both setup and start are stopped */
+	rtn = sl_llr_stop(cass_dev->sl.llr);
+	if (rtn && !err) {
+		cxidev_warn(&cass_dev->cdev, "sl_llr_stop retry failed [%d]\n", rtn);
+		err = rtn;
+	}
+
+	/* stop MAC */
+	rtn = sl_mac_tx_stop(cass_dev->sl.mac);
+	if (rtn) {
+		cxidev_warn(&cass_dev->cdev, "sl_mac_tx_stop failed [%d]\n", rtn);
+		if (!err)
+			err = rtn;
+	}
+	rtn = sl_mac_rx_stop(cass_dev->sl.mac);
+	if (rtn) {
+		cxidev_warn(&cass_dev->cdev, "sl_mac_rx_stop failed [%d]\n", rtn);
+		if (!err)
+			err = rtn;
+	}
+
+	/* down link */
+	if (cass_dev->sl.link_state != SL_LINK_STATE_DOWN) {
+		reinit_completion(&(cass_dev->sl.step_complete));
+		rtn = sl_link_down(cass_dev->sl.link);
+		switch (rtn) {
+		case -EALREADY:
+			break;
+		case -EINPROGRESS:
+		case 0:
+			timeleft = wait_for_completion_timeout(&(cass_dev->sl.step_complete),
+				msecs_to_jiffies(2 * CASS_SL_LINK_DOWN_TIMEOUT_MS));
+			if (timeleft == 0) {
+				cxidev_err(&cass_dev->cdev,
+					   "sl_link_down (link_down) timed out\n");
+				return -ETIMEDOUT;
+			}
+			break;
+		default:
+			cxidev_warn(&cass_dev->cdev, "sl_link_down (link_down) failed [%d]\n", rtn);
+			return rtn;
+		}
+		if (cass_dev->sl.link_state != SL_LINK_STATE_DOWN)
+			return -EBUSY;
+	}
+
+	if (err)
+		return err;
+
+	cass_link_set_state(cass_dev, CASS_LINK_STATUS_DOWN, 0);
+
+	return 0;
+}
+
+int cass_sl_exit(struct cass_dev *cass_dev)
+{
+	int rtn;
+
+	cxidev_dbg(&cass_dev->cdev, "sl exit\n");
+	if (!cass_dev->sl.is_initialized)
+		return 0;
+
+	rtn = sl_lgrp_notif_callback_unreg(cass_dev->sl.lgrp, cass_sl_callback, CASS_SL_CALLBACKS);
+	if (rtn != 0) {
+		cxidev_warn(&cass_dev->cdev, "sl_lgrp_notif_callback_unreg failed [%d]\n", rtn);
+		return rtn;
+	}
+
+	rtn = sl_llr_del(cass_dev->sl.llr);
+	if (rtn != 0) {
+		cxidev_warn(&cass_dev->cdev, "sl_llr_del failed [%d]\n", rtn);
+		return rtn;
+	}
+
+	rtn = sl_mac_del(cass_dev->sl.mac);
+	if (rtn != 0) {
+		cxidev_warn(&cass_dev->cdev, "sl_mac_del failed [%d]\n", rtn);
+		return rtn;
+	}
+
+	rtn = sl_link_del(cass_dev->sl.link);
+	if (rtn != 0) {
+		cxidev_warn(&cass_dev->cdev, "sl_link_del failed [%d]\n", rtn);
+		return rtn;
+	}
+
+	rtn = sl_lgrp_del(cass_dev->sl.lgrp);
+	if (rtn != 0) {
+		cxidev_warn(&cass_dev->cdev, "sl_lgrp_del failed [%d]\n", rtn);
+		return rtn;
+	}
+
+	rtn = sl_ldev_del(cass_dev->sl.ldev);
+	if (rtn != 0) {
+		cxidev_warn(&cass_dev->cdev, "sl_ldev_del failed [%d]\n", rtn);
+		return rtn;
+	}
+
+	if (cass_dev->sl.is_initialized) {
+		kobject_put(&cass_dev->port_num_kobj);
+		kobject_put(&cass_dev->port_kobj);
+		cass_dev->sl.is_initialized = false;
+	}
+
+	return 0;
+}
+
+int cass_sl_link_fini(struct cass_dev *cass_dev)
+{
+	int rtn;
+
+	cxidev_dbg(&cass_dev->cdev, "sl fini\n");
+	if (!cass_dev->sl.is_initialized)
+		return 0;
+
+	cass_lmon_kill_all(cass_dev);
+	rtn = cass_sl_link_down(cass_dev);
+	if (rtn) {
+		cxidev_err(&cass_dev->cdev,
+			   "link quiesce failed; aborting SL teardown [%d]\n", rtn);
+		return rtn;
+	}
+
+	rtn = cass_sl_media_unconfig(cass_dev);
+	if (rtn) {
+		cxidev_warn(&cass_dev->cdev, "media unconfig failed [%d]\n", rtn);
+		return rtn;
+	}
+	cass_dev->port->config_state &= ~CASS_MEDIA_CONFIGURED;
+	rtn = cass_sl_exit(cass_dev);
+	if (rtn)
+		return rtn;
+
+	cass_port_del_port_db(cass_dev);
+	return 0;
+}
diff --git a/drivers/net/ethernet/hpe/ss1/cass_sl_io.c b/drivers/net/ethernet/hpe/ss1/cass_sl_io.c
new file mode 100644
index 000000000000..5eca53cb0969
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_sl_io.c
@@ -0,0 +1,368 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+#include "cass_core.h"
+#include "cass_sl_io.h"
+
+int cass_sl_uc_write8(void *uc_accessor, u8 page, u8 addr, u8 data)
+{
+	struct cass_dev *cass_dev = uc_accessor;
+	int              rtn;
+
+	rtn = uc_cmd_qsfp_write(cass_dev, page, addr, &data, sizeof(data));
+
+	cxidev_dbg(&cass_dev->cdev, "sl_uc_write8 0x%x <- 0x%x\n", addr, data);
+
+	return rtn;
+}
+
+int cass_sl_uc_read(void *uc_accessor, u32 offset, u32 page, u8 *data, u32 len)
+{
+	struct cass_dev *cass_dev = uc_accessor;
+
+	cxidev_dbg(&cass_dev->cdev, "sl uc read (offset = 0x%X, page = %u, len = %u)\n",
+		   offset, page, len);
+
+	return cxi_get_qsfp_data(&cass_dev->cdev, offset, len, page, data);
+}
+
+u64 cass_sl_read64(void *pci_accessor, long addr)
+{
+	struct cass_dev *cass_dev = pci_accessor;
+	u64              data64;
+
+	cass_read(cass_dev, addr, &data64, sizeof(u64));
+
+	cxidev_dbg(&cass_dev->cdev, "sl read64 0x%lX = 0x%llX\n", addr, data64);
+
+	return data64;
+}
+
+void cass_sl_write64(void *pci_accessor, long addr, u64 data64)
+{
+	struct cass_dev *cass_dev = pci_accessor;
+
+	cass_write(cass_dev, addr, &data64, sizeof(u64));
+
+	cxidev_dbg(&cass_dev->cdev, "sl write64 0x%lX <- 0x%llX\n", addr, data64);
+}
+
+#define CASS_SL_SBUS_RD_CMD           0x22
+#define CASS_SL_SBUS_RD_DELAY_US      50
+#define CASS_SL_SBUS_RD_TIMOUT_MS     500
+#define CASS_SL_SBUS_RD_POLL_INTVL_MS 10
+int cass_sl_sbus_rd(void *sbus_accessor, u32 sbus_addr, u8 reg_addr, u32 *rd_data)
+{
+	int                        rtn;
+	struct cass_dev           *cass_dev = sbus_accessor;
+	struct cxi_sbus_op_params  params;
+	u8                         result_code;
+	u8                         overrun;
+
+	params.req_data      = 0;
+	params.data_addr     = reg_addr;
+	params.rx_addr       = (sbus_addr & 0xFF);
+	params.command       = CASS_SL_SBUS_RD_CMD;
+	params.delay         = CASS_SL_SBUS_RD_DELAY_US;
+	params.timeout       = CASS_SL_SBUS_RD_TIMOUT_MS;
+	params.poll_interval = CASS_SL_SBUS_RD_POLL_INTVL_MS;
+
+	mutex_lock(&cass_dev->sl.sbus_lock);
+
+	rtn = cxi_sbus_op(&cass_dev->cdev, &params, rd_data, &result_code, &overrun);
+	if (rtn != 0) {
+		cxidev_err(&cass_dev->cdev, "sl sbus rd - cxi_sbus_op failed [%d]\n", rtn);
+		goto out;
+	}
+	if (result_code != 4) {
+		cxidev_err(&cass_dev->cdev, "sl sbus rd - cxi_sbus_op (rc = %d)\n", result_code);
+		rtn = -EBADRQC;
+		goto out;
+	}
+	if (overrun != 0) {
+		cxidev_err(&cass_dev->cdev, "sl sbus rd - cxi_sbus_op (overrun = %d)\n", overrun);
+		rtn = -EIO;
+		goto out;
+	}
+
+	cxidev_dbg(&cass_dev->cdev, "sl sbus rd (sbus_addr = 0x%08X, reg = 0x%02X, data = 0x%08X)\n",
+		   sbus_addr, reg_addr, *rd_data);
+
+	rtn = 0;
+
+out:
+	mutex_unlock(&cass_dev->sl.sbus_lock);
+
+	return rtn;
+}
+
+#define CASS_SL_SBUS_WR_CMD           0x21
+#define CASS_SL_SBUS_WR_DELAY_US      50
+#define CASS_SL_SBUS_WR_TIMOUT_MS     500
+#define CASS_SL_SBUS_WR_POLL_INTVL_MS 10
+int cass_sl_sbus_wr(void *sbus_accessor, u32 sbus_addr, u8 reg_addr, u32 req_data)
+{
+	int                        rtn;
+	struct cass_dev           *cass_dev = sbus_accessor;
+	struct cxi_sbus_op_params  params;
+	u32                        rsp_data;
+	u8                         result_code;
+	u8                         overrun;
+
+	params.req_data      = req_data;
+	params.data_addr     = reg_addr;
+	params.rx_addr       = (sbus_addr & 0xFF);
+	params.command       = CASS_SL_SBUS_WR_CMD;
+	params.delay         = CASS_SL_SBUS_WR_DELAY_US;
+	params.timeout       = CASS_SL_SBUS_WR_TIMOUT_MS;
+	params.poll_interval = CASS_SL_SBUS_WR_POLL_INTVL_MS;
+
+	mutex_lock(&cass_dev->sl.sbus_lock);
+
+	rtn = cxi_sbus_op(&cass_dev->cdev, &params, &rsp_data, &result_code, &overrun);
+	if (rtn != 0) {
+		cxidev_err(&cass_dev->cdev, "sl sbus wr - cxi_sbus_op failed [%d]\n", rtn);
+		goto out;
+	}
+	if (result_code != 1) {
+		cxidev_err(&cass_dev->cdev, "sl sbus wr - cxi_sbus_op (rc = %d)\n", result_code);
+		rtn = -EBADRQC;
+		goto out;
+	}
+	if (overrun != 0) {
+		cxidev_err(&cass_dev->cdev, "sl sbus wr - cxi_sbus_op (overrun = %d)\n", overrun);
+		rtn = -EIO;
+		goto out;
+	}
+
+	cxidev_dbg(&cass_dev->cdev, "sl sbus wr (sbus = 0x%08X, reg = 0x%02X, data = 0x%08X)\n",
+		   sbus_addr, reg_addr, req_data);
+
+	rtn = 0;
+
+out:
+	mutex_unlock(&cass_dev->sl.sbus_lock);
+
+	return rtn;
+}
+
+#define CASS_SL_SBUS_OP_DELAY_US      50
+#define CASS_SL_SBUS_OP_TIMOUT_MS     500
+#define CASS_SL_SBUS_OP_POLL_INTVL_MS 10
+int cass_sl_sbus_cmd(void *sbus_accessor, int ring, u32 req_data,
+		     u8 reg_addr, u8 dev_addr, u8 op,
+			    u32 *rsp_data, u8 *result_code, u8 *overrun,
+			    u8 *error, int timeout_ms, u32 flags)
+{
+	int                        rtn;
+	struct cass_dev           *cass_dev = sbus_accessor;
+	struct cxi_sbus_op_params  params;
+
+	params.req_data      = req_data;
+	params.data_addr     = reg_addr;
+	params.rx_addr       = dev_addr;
+	params.command       = op;
+	params.delay         = CASS_SL_SBUS_OP_DELAY_US;
+	params.timeout       = CASS_SL_SBUS_OP_TIMOUT_MS;
+	params.poll_interval = CASS_SL_SBUS_OP_POLL_INTVL_MS;
+
+	cxidev_dbg(&cass_dev->cdev, "sl sbus cmd\n");
+
+	mutex_lock(&cass_dev->sl.sbus_lock);
+
+	rtn = cxi_sbus_op(&cass_dev->cdev, &params, rsp_data, result_code, overrun);
+	if (rtn != 0) {
+		cxidev_err(&cass_dev->cdev, "sl sbus cmd - cxi_sbus_op failed [%d]\n", rtn);
+		goto out;
+	}
+
+	cxidev_dbg(&cass_dev->cdev,
+		   "sl sbus cmd (op - 0x%X, dev = 0x%02X, reg = 0x%02X, data = 0x%08X, result = %u)\n",
+		op, dev_addr, reg_addr, req_data, *result_code);
+
+	// FIXME: for now just checking reset
+	if (((op & 0xF) == 0) && (*result_code != 0)) {
+		cxidev_err(&cass_dev->cdev, "sl sbus cmd - cxi_sbus_op (result = %u)\n",
+			   *result_code);
+		rtn = -EBADRQC;
+		goto out;
+	}
+	if (*overrun != 0) {
+		cxidev_err(&cass_dev->cdev, "sl sbus cmd - cxi_sbus_op (overrun = %u)\n", *overrun);
+		rtn = -EIO;
+		goto out;
+	}
+
+	rtn = 0;
+
+out:
+	mutex_unlock(&cass_dev->sl.sbus_lock);
+
+	return rtn;
+}
+
+#define CASS_SL_PMI_RD_READY_MAX_COUNT 2
+#define CASS_SL_PMI_RD_READY_DELAY_MS  1000
+#define CASS_SL_PMI_RD_MAX_COUNT 10
+#define CASS_SL_PMI_RD_DELAY_MS  100
+int cass_sl_pmi_rd(void *pmi_accessor, u8 lgrp_num, u32 addr, u16 *data)
+{
+	int                           rtn;
+	struct cass_dev              *cass_dev = pmi_accessor;
+	int                           x;
+	union c2_hni_serdes_pmi_ctl   pmi_ctl;
+	union c2_hni_serdes_pmi_data  pmi_data;
+
+	mutex_lock(&cass_dev->sl.pmi_lock);
+
+	/* check ready */
+	for (x = 0; x < CASS_SL_PMI_RD_READY_MAX_COUNT; ++x) {
+		cass_read(cass_dev, C2_HNI_SERDES_PMI_CTL, &pmi_ctl, sizeof(pmi_ctl));
+		if (!pmi_ctl.pmi_lp_ack)
+			break;
+		msleep(CASS_SL_PMI_RD_READY_DELAY_MS);
+	}
+	if (x >= CASS_SL_PMI_RD_READY_MAX_COUNT) {
+		cxidev_err(&cass_dev->cdev,
+			   "sl pmi rd - ready timeout (ctl = 0x%016llX)\n", pmi_ctl.qw);
+		rtn = -1;
+		goto out;
+	}
+
+	/* start */
+	pmi_ctl.qw          = 0ULL;
+	pmi_ctl.pmi_lp_addr = addr;
+	pmi_ctl.pmi_lp_en   = 1;
+	cxidev_dbg(&cass_dev->cdev, "sl pmi rd - ctrl 0x%016llX -> 0x%08X\n",
+		   pmi_ctl.qw, C2_HNI_SERDES_PMI_CTL);
+	cass_write(cass_dev, C2_HNI_SERDES_PMI_CTL, &pmi_ctl, sizeof(pmi_ctl));
+
+	/* poll for done */
+	for (x = 0; x < CASS_SL_PMI_RD_MAX_COUNT; ++x) {
+		cass_read(cass_dev, C2_HNI_SERDES_PMI_CTL, &pmi_ctl, sizeof(pmi_ctl));
+		cxidev_dbg(&cass_dev->cdev, "sl pmi rd - check #%d 0x%08X = 0x%016llX\n",
+			   x, C2_HNI_SERDES_PMI_CTL, pmi_ctl.qw);
+		if (pmi_ctl.pmi_lp_error) {
+			cxidev_err(&cass_dev->cdev, "sl pml rd - error\n");
+			rtn = -1;
+			goto out;
+		}
+		if (pmi_ctl.pmi_lp_ack)
+			break;
+		msleep(CASS_SL_PMI_RD_DELAY_MS);
+	}
+	if (x >= CASS_SL_PMI_RD_MAX_COUNT) {
+		cxidev_err(&cass_dev->cdev, "sl pmi rd - timeout\n");
+		rtn = -ETIMEDOUT;
+		goto out;
+	}
+
+	/* check valid */
+	if (!pmi_ctl.pmi_lp_read_vld) {
+		cxidev_err(&cass_dev->cdev, "sl pmi rd - data not valid\n");
+		rtn = -1;
+		goto out;
+	}
+
+	/* get data */
+	cass_read(cass_dev, C2_HNI_SERDES_PMI_DATA, &pmi_data, sizeof(pmi_data));
+
+	cxidev_dbg(&cass_dev->cdev, "sl pmi rd - read 0x%08X = 0x%016llX\n",
+		   C2_HNI_SERDES_PMI_DATA, pmi_data.qw);
+
+	*data = pmi_data.pmi_lp_rddata;
+
+	cxidev_dbg(&cass_dev->cdev, "sl pmi rd (addr = 0x%08X, data = 0x%04X)\n", addr, *data);
+
+	rtn = 0;
+
+out:
+	/* finish transaction */
+	pmi_ctl.qw = 0ULL;
+	cass_write(cass_dev, C2_HNI_SERDES_PMI_CTL, &pmi_ctl, sizeof(pmi_ctl));
+
+	mutex_unlock(&cass_dev->sl.pmi_lock);
+
+	return rtn;
+}
+
+#define CASS_SL_PMI_WR_READY_MAX_COUNT 2
+#define CASS_SL_PMI_WR_READY_DELAY_MS  1000
+#define CASS_SL_PMI_WR_MAX_COUNT 10
+#define CASS_SL_PMI_WR_DELAY_MS  100
+int cass_sl_pmi_wr(void *pmi_accessor, u8 lgrp_num, u32 addr, u16 data, u16 mask)
+{
+	int                           rtn;
+	struct cass_dev              *cass_dev = pmi_accessor;
+	int                           x;
+	union c2_hni_serdes_pmi_ctl   pmi_ctl;
+	union c2_hni_serdes_pmi_data  pmi_data;
+
+	mutex_lock(&cass_dev->sl.pmi_lock);
+
+	/* check ready */
+	for (x = 0; x < CASS_SL_PMI_WR_READY_MAX_COUNT; ++x) {
+		cass_read(cass_dev, C2_HNI_SERDES_PMI_CTL, &pmi_ctl, sizeof(pmi_ctl));
+		if (!pmi_ctl.pmi_lp_ack)
+			break;
+		msleep(CASS_SL_PMI_WR_READY_DELAY_MS);
+	}
+	if (x >= CASS_SL_PMI_WR_READY_MAX_COUNT) {
+		cxidev_err(&cass_dev->cdev,
+			   "sl pmi wr - ready timeout (ctl = 0x%016llX)\n", pmi_ctl.qw);
+		rtn = -1;
+		goto out;
+	}
+
+	/* load data */
+	pmi_data.qw              = 0ULL;
+	pmi_data.pmi_lp_wrdata   = data;
+	pmi_data.pmi_lp_maskdata = ~mask;
+	cxidev_dbg(&cass_dev->cdev, "sl pmi wr - data 0x%016llX -> 0x%08X\n",
+		   pmi_data.qw, C2_HNI_SERDES_PMI_DATA);
+	cass_write(cass_dev, C2_HNI_SERDES_PMI_DATA, &pmi_data, sizeof(pmi_data));
+
+	/* start */
+	pmi_ctl.qw           = 0ULL;
+	pmi_ctl.pmi_lp_addr  = addr;
+	pmi_ctl.pmi_lp_en    = 1;
+	pmi_ctl.pmi_lp_write = 1;
+	cxidev_dbg(&cass_dev->cdev, "sl pmi wr - ctrl 0x%016llX -> 0x%08X\n",
+		   pmi_ctl.qw, C2_HNI_SERDES_PMI_CTL);
+	cass_write(cass_dev, C2_HNI_SERDES_PMI_CTL, &pmi_ctl, sizeof(pmi_ctl));
+
+	/* poll for done */
+	for (x = 0; x < CASS_SL_PMI_WR_MAX_COUNT; ++x) {
+		cass_read(cass_dev, C2_HNI_SERDES_PMI_CTL, &pmi_ctl, sizeof(pmi_ctl));
+		cxidev_dbg(&cass_dev->cdev, "sl pmi wr - check #%d 0x%08X = 0x%016llX\n",
+			   x, C2_HNI_SERDES_PMI_CTL, pmi_ctl.qw);
+		if (pmi_ctl.pmi_lp_error) {
+			cxidev_err(&cass_dev->cdev, "sl pmi wr - error\n");
+			rtn = -1;
+			goto out;
+		}
+		if (pmi_ctl.pmi_lp_ack)
+			break;
+		msleep(CASS_SL_PMI_WR_DELAY_MS);
+	}
+	if (x >= CASS_SL_PMI_WR_MAX_COUNT) {
+		cxidev_err(&cass_dev->cdev, "sl pmi wr - timeout\n");
+		rtn = -ETIMEDOUT;
+		goto out;
+	}
+
+	cxidev_dbg(&cass_dev->cdev, "sl pmi wr (addr = 0x%08X, data = 0x%04X, mask = 0x%04X)\n",
+		   addr, data, mask);
+
+	rtn = 0;
+
+out:
+	/* finish transaction */
+	pmi_ctl.qw = 0ULL;
+	cass_write(cass_dev, C2_HNI_SERDES_PMI_CTL, &pmi_ctl, sizeof(pmi_ctl));
+
+	mutex_unlock(&cass_dev->sl.pmi_lock);
+
+	return rtn;
+}
+

-- 
2.56.0


^ permalink raw reply	[flat|nested] 25+ messages in thread
* [PATCH 19/23] net: hpe: ss1: add SR-IOV support
  2026-10-30 20:58 [PATCH 00/23] Subject: [PATCH net-next 00/23] net/hpe: add HPE Slingshot NIC drivers Doug Ledford
                   ` (17 preceding siblings ...)
  2026-10-30 20:59 ` [PATCH 18/23] net: hpe: ss1: add the link layer glue Doug Ledford
@ 2026-10-30 20:59 ` Doug Ledford
  2026-10-30 20:59 ` [PATCH 20/23] net: hpe: ss1: add the CXI core interfaces Doug Ledford
                   ` (4 subsequent siblings)
  23 siblings, 0 replies; 25+ messages in thread
From: Doug Ledford @ 2026-10-30 20:59 UTC (permalink / raw)
  To: Slingshot Open Source Team, Nathan Chancellor, Nicolas Schier,
	Richard Cochran, Andrew Lunn, David S. Miller, Eric Dumazet,
	Jakub Kicinski, Paolo Abeni, Sumit Semwal, Christian König,
	Guenter Roeck
  Cc: linux-kernel, netdev, linux-kbuild, Doug Ledford

Add SR-IOV support: VF creation, the PF/VF mailbox and its
notifications.

Known open issues, deferred to the V2 SR-IOV update:

- Sashiko H58: the PF/VF mailbox path is not wired up in-tree.
- Sashiko H59: pf_vf_handshake() can abort VF initialization when it
  probes the wrong half of the endpoint pair.

Known limitation, deferred to V2: this patch carries SR-IOV
virtual-function code (VF-to-PF mailbox requests, mailbox opcodes or VF
resource handling) from an older, incomplete version of the Cassini
SR-IOV support. V2 of this series will include the updated SR-IOV
implementation, so issues in the VF paths should be ignored for now.

Signed-off-by: Doug Ledford <doug.ledford@hpe.com>
---
 drivers/net/ethernet/hpe/ss1/cass_sriov.c    | 1274 ++++++++++++++++++++++++++
 drivers/net/ethernet/hpe/ss1/cass_vf.c       |   58 ++
 drivers/net/ethernet/hpe/ss1/cass_vf_notif.c |   51 ++
 3 files changed, 1383 insertions(+)

diff --git a/drivers/net/ethernet/hpe/ss1/cass_sriov.c b/drivers/net/ethernet/hpe/ss1/cass_sriov.c
new file mode 100644
index 000000000000..5c947372ab9c
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_sriov.c
@@ -0,0 +1,1274 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2019, 2024-2026 Hewlett Packard Enterprise Development LP */
+
+/* Cassini SRIOV and VFs handler
+ *
+ * AF_VSOCK sockets are used to pass messages and responses from the VF to the
+ * PF, both when the VF is attached to a guest (using the appropriate hypervisor
+ * vsock transport), and when the VF is attached to the host (using the
+ * vsock_loopback module).
+ *
+ * The VF index of an incoming vsock connection is identified by probing the
+ * PF-to-VF interrupt of each unaccounted-for VF and waiting for a response.
+ * After this initial handshake, communication is always initiated by the VF,
+ * and an acknowledgment from the PF is always expected. Messages are prefixed
+ * with an integer result code (only used by the response from the PF) and
+ * message length.
+ */
+
+#include <linux/pci.h>
+#include <linux/types.h>
+#include <linux/kmod.h>
+#include <linux/kthread.h>
+#include <linux/kvm_host.h>
+#include <linux/net.h>
+#include <linux/vfio.h>
+#include <linux/vm_sockets.h>
+#include <net/sock.h>
+
+#include "cass_core.h"
+#include "cass_vf_notif.h"
+#include "cxi_core.h"
+
+MODULE_SOFTDEP("pre: vsock vsock_loopback");
+
+#if defined(CXI_DISABLE_SRIOV)
+#warning "SR-IOV support is disabled."
+
+int cass_sriov_configure(struct pci_dev *pdev, int num_vfs)
+{
+	return -EOPNOTSUPP;
+}
+
+int cass_vf_init(struct cass_dev *hw)
+{
+	return -EOPNOTSUPP;
+}
+
+void cass_vf_fini(struct cass_dev *hw)
+{
+}
+
+int cxi_send_msg_to_pf(struct cxi_dev *cdev, const void *req,
+		       size_t req_len, void *rsp, size_t *rsp_len)
+{
+	return -EOPNOTSUPP;
+}
+EXPORT_SYMBOL(cxi_send_msg_to_pf);
+
+int cxi_send_msg_to_vf(struct cxi_dev *cdev, int vf_num, const void *req,
+		       size_t req_len, void *rsp, size_t *rsp_len)
+{
+	return -EOPNOTSUPP;
+}
+EXPORT_SYMBOL(cxi_send_msg_to_vf);
+
+int cxi_register_msg_relay(struct cxi_dev *cdev, cxi_msg_relay_t msg_relay,
+			   void *msg_relay_data)
+{
+	return 0;
+}
+EXPORT_SYMBOL(cxi_register_msg_relay);
+
+int cxi_unregister_msg_relay(struct cxi_dev *cdev)
+{
+	return 0;
+}
+EXPORT_SYMBOL(cxi_unregister_msg_relay);
+
+int cass_vf_get_token(struct cxi_dev *hw, int vf_idx, unsigned int *token)
+{
+	return -EOPNOTSUPP;
+}
+EXPORT_SYMBOL(cass_vf_get_token);
+
+#else /* CXI_DISABLE_SRIOV */
+
+/* TODO: make port configurable? (0x17db is arbitrary, taken from C1 PCI vendor ID) */
+#define CXI_SRIOV_VSOCK_PORT 0x17db
+#define CXI_SRIOV_VSOCK_NOTIF_PORT (CXI_SRIOV_VSOCK_PORT + 1)
+
+/* Magic numbers used in VF-PF handshake */
+#define CXI_SRIOV_MAGIC1 0x17db0000
+#define CXI_SRIOV_MAGIC2 0x12345678
+
+/* PF-side timeout for vsock. Kept short so that listener-thread loop still runs. */
+#define CXI_SRIOV_PF_TIMEOUT (HZ / 4)
+
+/* VF-side timeout - longer than PF timeout, to allow time for PF to respond to requests */
+#define CXI_SRIOV_VF_TIMEOUT (HZ * 10)
+
+static int vsock_send_all(struct socket *sock, const void *buffer, size_t length)
+{
+	const u8 *data = buffer;
+	int rc;
+
+	while (length) {
+		struct msghdr msghdr = { .msg_flags = MSG_NOSIGNAL };
+		struct kvec vec = {
+			.iov_base = (void *)data,
+			.iov_len = length,
+		};
+
+		rc = kernel_sendmsg(sock, &msghdr, &vec, 1, length);
+		if (rc <= 0) {
+			kernel_sock_shutdown(sock, SHUT_RDWR);
+			return rc ? rc : -EPIPE;
+		}
+		data += rc;
+		length -= rc;
+	}
+	return 0;
+}
+
+static int write_message_to_vsock(struct socket *sock, const void *msg,
+				  size_t msg_len, int msg_rc, int seq)
+{
+	struct vf_pf_msg_hdr hdr = {
+		.len = msg_len,
+		.rc = msg_rc,
+		.uid = __kuid_val(current_euid()),
+		.gid = __kgid_val(current_egid()),
+		.seq = seq,
+	};
+	int rc;
+
+	if (msg_len > MAX_VFMSG_SIZE || (msg_len && !msg))
+		return -EINVAL;
+	rc = vsock_send_all(sock, &hdr, sizeof(hdr));
+	if (rc)
+		return rc;
+	rc = vsock_send_all(sock, msg, msg_len);
+	if (rc)
+		return rc;
+	return sizeof(hdr) + msg_len;
+}
+
+static int vsock_recv_all(struct socket *sock, void *buffer, size_t length)
+{
+	u8 *data = buffer;
+	size_t received = 0;
+	int rc;
+
+	while (received < length) {
+		struct msghdr msghdr = {};
+		struct kvec vec = {
+			.iov_base = data + received,
+			.iov_len = length - received,
+		};
+
+		rc = kernel_recvmsg(sock, &msghdr, &vec, 1, vec.iov_len, 0);
+		if (rc <= 0) {
+			if (received || !rc)
+				kernel_sock_shutdown(sock, SHUT_RDWR);
+			if (received && (rc == -EAGAIN || rc == -EINTR))
+				return -EPROTO;
+			return rc ? rc : -ECONNRESET;
+		}
+		received += rc;
+	}
+	return 0;
+}
+
+static int read_message_from_vsock(struct socket *sock, void *msg,
+				   size_t *msg_len, int *msg_rc,
+				   uid_t *uid, gid_t *gid, int *seq)
+{
+	struct vf_pf_msg_hdr hdr;
+	u8 discard[64];
+	size_t remaining;
+	int rc;
+
+	rc = vsock_recv_all(sock, &hdr, sizeof(hdr));
+	if (rc)
+		return rc;
+
+	if (hdr.len > MAX_VFMSG_SIZE) {
+		pr_err("Bad message size (%u > %zu)", hdr.len, MAX_VFMSG_SIZE);
+		rc = -EINVAL;
+		goto fail_frame;
+	}
+
+	if (msg && hdr.len && (!msg_len || *msg_len < hdr.len)) {
+		pr_err("Message buffer too small (%u > %zu)", hdr.len, msg_len ? *msg_len : 0);
+		rc = -EMSGSIZE;
+		goto fail_frame;
+	}
+
+	remaining = hdr.len;
+	while (remaining) {
+		size_t chunk = msg ? remaining :
+			min_t(size_t, remaining, sizeof(discard));
+
+		rc = vsock_recv_all(sock, msg ? msg : discard, chunk);
+		if (rc) {
+			if (rc == -EAGAIN || rc == -EINTR)
+				rc = -EPROTO;
+			goto fail_frame;
+		}
+		remaining -= chunk;
+	}
+
+	if (msg_len)
+		*msg_len = hdr.len;
+	if (msg_rc)
+		*msg_rc = hdr.rc;
+	if (uid)
+		*uid = hdr.uid;
+	if (gid)
+		*gid = hdr.gid;
+	if (seq)
+		*seq = hdr.seq;
+
+	return hdr.len ? hdr.len : sizeof(hdr);
+fail_frame:
+	kernel_sock_shutdown(sock, SHUT_RDWR);
+	return rc;
+}
+
+/* Given a PF's pci_dev struct, find the pci_dev of one of its VFs */
+static struct pci_dev *get_vf_pdev(struct pci_dev *pdev, int vf_idx)
+{
+	int devfn = pci_iov_virtfn_devfn(pdev, vf_idx);
+
+	if (devfn < 0)
+		return ERR_PTR(devfn);
+	return pci_get_slot(pdev->bus, devfn);
+}
+
+/* Identify the KVM task associated with a VF that is bound to a guest VM. */
+static struct task_struct *pf_get_kvm_task(struct cass_vf *vf)
+{
+	struct cass_dev *hw = vf->hw;
+	struct pci_dev *vf_pdev = NULL;
+	struct vfio_device *vfio_dev = NULL;
+	struct task_struct *task = NULL;
+	struct pid *pid;
+
+	vf_pdev = get_vf_pdev(hw->cdev.pdev, vf->vf_idx);
+	if (IS_ERR(vf_pdev)) {
+		cxidev_err(&hw->cdev, "vf %d: could not get device", vf->vf_idx);
+		return ERR_PTR(PTR_ERR(vf_pdev));
+	}
+
+	cxidev_dbg(&hw->cdev, "vf %d: device at %s", vf->vf_idx, pci_name(vf_pdev));
+
+	if (!vf_pdev->driver) {
+		task = ERR_PTR(-ENODEV);
+	} else if (!strncmp(vf_pdev->driver->name, "vfio-pci", strlen("vfio-pci"))) {
+		/* VF is under control of VFIO driver, look for KVM task. */
+		vfio_dev = pci_get_drvdata(vf_pdev);
+		if (vfio_dev->kvm) {
+			pid = find_get_pid(vfio_dev->kvm->userspace_pid);
+			task = get_pid_task(pid, PIDTYPE_PID);
+			put_pid(pid);
+		} else {
+			task = ERR_PTR(-ESRCH);
+		}
+	} else if (!strncmp(vf_pdev->driver->name, KBUILD_MODNAME,
+			    strlen(KBUILD_MODNAME))) {
+		/* VF is under control of our driver, KVM task is not applicable */
+		task = NULL;
+	} else {
+		task = ERR_PTR(-EPERM);
+	}
+	pci_dev_put(vf_pdev);
+	return task;
+}
+
+/* Handler thread for incoming messages from the VF driver to the PF. 1 instance
+ * per active VF.
+ */
+static int pf_vf_msghandler(void *data)
+{
+	struct cass_vf *vf = (struct cass_vf *)data;
+	struct cass_dev *hw = vf->hw;
+	struct task_struct *kvm_task;
+	int rc, msg_rc;
+	size_t request_len, reply_len;
+	uid_t uid;
+	gid_t gid;
+	int seq;
+
+	vf->req_sock->sk->sk_rcvtimeo = CXI_SRIOV_PF_TIMEOUT;
+
+	cxidev_dbg(&hw->cdev, "vf %d: started message handler", vf->vf_idx);
+
+	kvm_task = pf_get_kvm_task(vf);
+	if (IS_ERR(kvm_task)) {
+		rc = PTR_ERR(kvm_task);
+		goto err;
+	}
+	vf->kvm_task = kvm_task;
+
+	while (!kthread_should_stop()) {
+		request_len = MAX_VFMSG_SIZE;
+		rc = read_message_from_vsock(vf->req_sock, vf->request,
+					     &request_len, NULL, &uid, &gid, &seq);
+		if (rc == -EAGAIN) {
+			continue;
+		} else if (rc == -EINTR) {
+			/* Expected when thread is asked to terminate */
+			continue;
+		} else if (rc < 0) {
+			cxidev_err(&hw->cdev, "vf %d: error reading request: %d",
+				   vf->vf_idx, rc);
+			break;
+		} else if (rc == 0) {
+			cxidev_err(&hw->cdev, "vf %d: connection closed by VF",
+				   vf->vf_idx);
+			break;
+		}
+
+		cxidev_dbg(&hw->cdev, "vf %d: got %ld byte message", vf->vf_idx,
+			   request_len);
+
+		if (vf->kvm_task) {
+			/* VFs associated with a guest virtual machine must use the
+			 * credentials of the VM's process on the host, rather than the
+			 * guest's user creds that come over the vsock.
+			 */
+			const struct cred *cred;
+
+			rcu_read_lock();
+			cred = rcu_dereference(vf->kvm_task->cred);
+			uid = __kuid_val(cred->uid);
+			gid = __kgid_val(cred->gid);
+			rcu_read_unlock();
+		}
+
+		mutex_lock(&hw->msg_relay_lock);
+		if (hw->msg_relay) {
+			reply_len = MAX_VFMSG_SIZE;
+			msg_rc = hw->msg_relay(hw->msg_relay_data, vf->vf_idx,
+					       vf->request, request_len, uid, gid,
+					       vf->reply, &reply_len);
+		} else {
+			reply_len = 0;
+			msg_rc = -ENODEV;
+		}
+		mutex_unlock(&hw->msg_relay_lock);
+
+		if (reply_len > MAX_VFMSG_SIZE) {
+			reply_len = 0;
+			msg_rc = -E2BIG;
+		}
+
+		cxidev_dbg(&hw->cdev, "vf %d: responding with %ld bytes, rc=%d",
+			   vf->vf_idx, reply_len, msg_rc);
+		rc = write_message_to_vsock(vf->req_sock, vf->reply, reply_len,
+					    msg_rc, seq);
+		if (rc < 0) {
+			cxidev_err(&hw->cdev, "vf %d: error sending response: %d",
+				   vf->vf_idx, rc);
+			break;
+		}
+	}
+
+	/* Send a NULL request message to indicate that this VF disconnected */
+	mutex_lock(&hw->msg_relay_lock);
+	if (hw->msg_relay)
+		hw->msg_relay(hw->msg_relay_data, vf->vf_idx, NULL, 0, 0, 0, NULL,
+			      &reply_len);
+	mutex_unlock(&hw->msg_relay_lock);
+
+	if (rc > 0)
+		rc = 0;
+
+err:
+	cxidev_dbg(&hw->cdev, "vf %d: handler exiting, rc=%d", vf->vf_idx, rc);
+
+	if (vf->kvm_task)
+		put_task_struct(vf->kvm_task);
+	kernel_sock_shutdown(vf->req_sock, SHUT_RDWR);
+	sock_release(vf->req_sock);
+	vf->req_sock = NULL;
+	mutex_lock(&vf->notif_lock);
+	if (vf->notif_sock) {
+		kernel_sock_shutdown(vf->notif_sock, SHUT_RDWR);
+		sock_release(vf->notif_sock);
+		vf->notif_sock = NULL;
+	}
+	mutex_unlock(&vf->notif_lock);
+
+	vf->kvm_task = NULL;
+
+	cass_ac_phys_free(hw, vf->phys_ac);
+	vf->phys_ac = 0;
+
+	return rc;
+}
+
+/* Probe inactive VFs from range_min to range_max inclusive */
+static int pf_probe_vfs(struct cass_dev *hw, struct socket *sock,
+			int range_min, int range_max)
+{
+	int i, rc;
+	int magic;
+	size_t msg_len = sizeof(magic);
+	union c_pi_ipd_cfg_pf_vf_irq irqs = {
+		.irq = 0,
+	};
+
+	for (i = range_min; i <= range_max; i++)
+		if (!hw->vfs[i].req_sock) /* Only probe VFs that aren't already active */
+			irqs.irq |= 1ULL << i;
+	if (!irqs.irq)
+		return 0;
+
+	magic = CXI_SRIOV_MAGIC1;
+	rc = write_message_to_vsock(sock, &magic, sizeof(magic), 0, 0);
+	if (rc < 0) {
+		cxidev_err(&hw->cdev, "could not send magic to incoming VF: %d", rc);
+		return rc;
+	}
+
+	cass_write(hw, C_PI_IPD_CFG_PF_VF_IRQ, &irqs,
+		   sizeof(union c_pi_ipd_cfg_pf_vf_irq));
+
+	msg_len = sizeof(magic);
+	do {
+		rc = read_message_from_vsock(sock, &magic, &msg_len, NULL, NULL, NULL, NULL);
+		if (rc == -EINTR)
+			schedule();
+	} while (rc == -EINTR);
+	if (rc < 0) {
+		cxidev_err(&hw->cdev, "could not read magic from incoming VF: %d", rc);
+		return rc;
+	}
+
+	return magic;
+}
+
+/* Identify which VF an incoming connection belongs to, by probing the PF-to-VF
+ * interrupt of VFs that do not have an active connection.
+ */
+static int pf_vf_handshake(struct cass_dev *hw, struct socket *sock)
+{
+	int range_min = 0;
+	int range_max = hw->num_vfs - 1;
+	int range_mid, rc, seq, vf_idx;
+	int magic;
+
+	seq = 0; /* Handshake sequence number */
+	do {
+		magic = CXI_SRIOV_MAGIC1 + seq;
+		range_mid = range_min + (range_max - range_min) / 2;
+		if (pf_probe_vfs(hw, sock, range_min, range_mid) == magic) {
+			seq += 1;
+			range_max = range_mid;
+		} else if (pf_probe_vfs(hw, sock, range_mid + 1, range_max) == magic) {
+			seq += 1;
+			range_min = range_mid + 1;
+		} else {
+			break;
+		}
+	} while (range_max != range_min);
+
+	if (range_max != range_min) {
+		cxidev_err(&hw->cdev, "vf search failed");
+		return -ENOENT;
+	}
+	vf_idx = range_min;
+
+	magic = CXI_SRIOV_MAGIC2;
+	rc = write_message_to_vsock(sock, &magic, sizeof(magic), 0, 0);
+	if (rc < 0) {
+		cxidev_err(&hw->cdev, "could not send magic to incoming VF: %d", rc);
+		return rc;
+	}
+
+	return vf_idx;
+}
+
+/* Handle an incoming request connection from a VF */
+static void handle_vf_req_conn(struct cass_dev *hw,
+			       struct socket *incoming)
+{
+	struct sockaddr_vm peeraddr;
+	struct cass_vf *vf;
+	int rc, vf_idx;
+
+	rc = kernel_getpeername(incoming, (struct sockaddr *)&peeraddr);
+	if (rc < 0) {
+		cxidev_err(&hw->cdev, "could not get peer addr for vf: %d", rc);
+		goto close_sock;
+	}
+
+	vf_idx = pf_vf_handshake(hw, incoming);
+	if (vf_idx < 0) {
+		cxidev_err(&hw->cdev, "vf handshake from cid %d failed: %d",
+			   peeraddr.svm_cid, vf_idx);
+		goto close_sock;
+	}
+
+	cxidev_dbg(&hw->cdev, "pf got request connection from cid %d, vf %d",
+		   peeraddr.svm_cid, vf_idx);
+
+	vf = &hw->vfs[vf_idx];
+	if (vf->req_sock) {
+		cxidev_err(&hw->cdev, "vf %d already in use", vf_idx);
+		goto close_sock;
+	}
+
+	vf->vf_idx = vf_idx;
+	vf->hw = hw;
+	vf->req_sock = incoming;
+	get_random_bytes(&vf->token, sizeof(vf->token));
+
+	rc = cass_ac_phys_alloc(hw, true, vf_idx);
+	if (rc <= 0) {
+		cxidev_err(&hw->cdev, "could not allocate ac for vf %d: %d",
+			   vf_idx, rc);
+		vf->req_sock = NULL;
+		goto close_sock;
+	}
+	vf->phys_ac = rc;
+	cxidev_dbg(&hw->cdev, "allocated acid %d for vf %d", vf->phys_ac, vf_idx);
+
+	vf->task = kthread_run(pf_vf_msghandler, vf, "cxi_vf_%d", vf_idx);
+	if (IS_ERR(vf->task)) {
+		cxidev_err(&hw->cdev, "failed to start handler for vf %d", vf_idx);
+		cass_ac_phys_free(hw, vf->phys_ac);
+		vf->phys_ac = 0;
+		vf->req_sock = NULL;
+		vf->task = NULL;
+		goto close_sock;
+	}
+	return;
+
+close_sock:
+	kernel_sock_shutdown(incoming, SHUT_RDWR);
+	sock_release(incoming);
+}
+
+/* Handle an incoming notification connection from a VF */
+static void handle_vf_notif_conn(struct cass_dev *hw,
+				 struct socket *incoming)
+{
+	struct sockaddr_vm peeraddr;
+	struct cass_vf *vf;
+	int rc, vf_idx, i;
+	unsigned int token;
+	struct cass_vf_notif_ping ping = {
+		.op = CASS_VF_NOTIF_OP_PING,
+	};
+	size_t msg_len;
+
+	rc = kernel_getpeername(incoming, (struct sockaddr *)&peeraddr);
+	if (rc < 0) {
+		cxidev_err(&hw->cdev,
+			   "could not get peer addr for notification connection: %d", rc);
+		goto close_sock;
+	}
+
+	/* Read token to identify which VF this is */
+	msg_len = sizeof(token);
+	do {
+		rc = read_message_from_vsock(incoming, &token, &msg_len, NULL, NULL, NULL, NULL);
+		if (rc == -EINTR)
+			schedule();
+	} while (rc == -EINTR);
+	if (rc < 0) {
+		cxidev_err(&hw->cdev,
+			   "could not read token from notification connection: %d", rc);
+		goto close_sock;
+	}
+
+	if (msg_len != sizeof(token)) {
+		cxidev_err(&hw->cdev, "invalid token size: %zu", msg_len);
+		goto close_sock;
+	}
+
+	/* Find VF by matching token */
+	vf_idx = -1;
+	for (i = 0; i < hw->num_vfs; i++) {
+		if (hw->vfs[i].req_sock && hw->vfs[i].token == token) {
+			vf_idx = i;
+			break;
+		}
+	}
+
+	if (vf_idx < 0) {
+		cxidev_err(&hw->cdev, "notification connection with unknown token %u",
+			   token);
+		goto close_sock;
+	}
+
+	cxidev_dbg(&hw->cdev, "pf got notification connection from cid %d, vf %d",
+		   peeraddr.svm_cid, vf_idx);
+
+	vf = &hw->vfs[vf_idx];
+	mutex_lock(&vf->notif_lock);
+	if (vf->notif_sock) {
+		cxidev_err(&hw->cdev, "vf %d notification socket already in use", vf_idx);
+		mutex_unlock(&vf->notif_lock);
+		goto close_sock;
+	}
+
+	vf->notif_seq = 0;
+	vf->notif_sock = incoming;
+	mutex_unlock(&vf->notif_lock);
+	cxidev_dbg(&hw->cdev, "vf %d: notification socket connected", vf_idx);
+
+	/* Send test notification */
+	msg_len = sizeof(ping);
+	rc = cxi_send_msg_to_vf(&hw->cdev, vf_idx, &ping, msg_len,
+				NULL, NULL);
+	if (rc < 0) {
+		cxidev_err(&hw->cdev, "vf %d: could not send test notification: %d",
+			   vf_idx, rc);
+		mutex_lock(&vf->notif_lock);
+		if (vf->notif_sock != incoming) {
+			mutex_unlock(&vf->notif_lock);
+			return;
+		}
+		vf->notif_sock = NULL;
+		mutex_unlock(&vf->notif_lock);
+		goto close_sock;
+	}
+
+	return;
+
+close_sock:
+	kernel_sock_shutdown(incoming, SHUT_RDWR);
+	sock_release(incoming);
+}
+
+static int vsock_create_listen(struct socket **sock, unsigned int port,
+			       int timeout, int backlog)
+{
+	int rc;
+	struct sockaddr_vm addr = {
+		.svm_family = AF_VSOCK,
+		.svm_port = port,
+		.svm_cid = VMADDR_CID_ANY
+	};
+
+	rc = sock_create_kern(&init_net, PF_VSOCK, SOCK_STREAM, 0, sock);
+	if (rc < 0)
+		return rc;
+
+	rc = kernel_bind(*sock, (struct sockaddr_unsized *)&addr, sizeof(addr));
+	if (rc < 0)
+		goto release_sock;
+
+	(*sock)->sk->sk_rcvtimeo = timeout;
+	rc = kernel_listen(*sock, backlog);
+	if (rc < 0)
+		goto release_sock;
+
+	return 0;
+release_sock:
+	sock_release(*sock);
+	*sock = NULL;
+	return rc;
+}
+
+/* Combined listener thread for incoming connections from VFs to the PF.
+ * Handles both request and notification sockets. 1 instance only.
+ */
+static int pf_vf_listener(void *data)
+{
+	int rc, vf_idx;
+	struct cass_dev *hw = (struct cass_dev *)data;
+
+	cxidev_dbg(&hw->cdev, "started vf listener");
+
+	rc = vsock_create_listen(&hw->vf_req_sock, CXI_SRIOV_VSOCK_PORT,
+				 CXI_SRIOV_PF_TIMEOUT, hw->num_vfs);
+	if (rc < 0) {
+		cxidev_err(&hw->cdev, "could not create vf request listener socket: %d", rc);
+		return rc;
+	}
+
+	rc = vsock_create_listen(&hw->vf_notif_sock, CXI_SRIOV_VSOCK_NOTIF_PORT,
+				 CXI_SRIOV_PF_TIMEOUT, hw->num_vfs);
+	if (rc < 0) {
+		cxidev_err(&hw->cdev, "could not create vf notification listener socket: %d", rc);
+		goto shutdown_req;
+	}
+
+	while (!kthread_should_stop()) {
+		struct socket *incoming;
+
+		rc = kernel_accept(hw->vf_req_sock, &incoming, 0);
+		if (rc == 0) {
+			handle_vf_req_conn(hw, incoming);
+			continue;
+		} else if (rc != -EAGAIN && rc != -EINTR) {
+			cxidev_err(&hw->cdev, "vf request listener socket accept error: %d", rc);
+			break;
+		}
+
+		rc = kernel_accept(hw->vf_notif_sock, &incoming, 0);
+		if (rc == 0) {
+			handle_vf_notif_conn(hw, incoming);
+			continue;
+		} else if (rc != -EAGAIN && rc != -EINTR) {
+			cxidev_err(&hw->cdev, "vf notification listener socket accept error: %d",
+				   rc);
+			break;
+		}
+	}
+
+	cxidev_dbg(&hw->cdev, "vf listener exiting");
+
+	for (vf_idx = 0; vf_idx < hw->num_vfs; vf_idx++) {
+		if (hw->vfs[vf_idx].req_sock) {
+			kthread_stop(hw->vfs[vf_idx].task);
+			hw->vfs[vf_idx].task = NULL;
+		}
+		mutex_lock(&hw->vfs[vf_idx].notif_lock);
+		if (hw->vfs[vf_idx].notif_sock) {
+			kernel_sock_shutdown(hw->vfs[vf_idx].notif_sock, SHUT_RDWR);
+			sock_release(hw->vfs[vf_idx].notif_sock);
+			hw->vfs[vf_idx].notif_sock = NULL;
+		}
+		mutex_unlock(&hw->vfs[vf_idx].notif_lock);
+	}
+
+	kernel_sock_shutdown(hw->vf_notif_sock, SHUT_RDWR);
+	sock_release(hw->vf_notif_sock);
+	hw->vf_notif_sock = NULL;
+
+shutdown_req:
+	kernel_sock_shutdown(hw->vf_req_sock, SHUT_RDWR);
+	sock_release(hw->vf_req_sock);
+	hw->vf_req_sock = NULL;
+
+	return rc;
+}
+
+static void disable_sriov(struct pci_dev *pdev)
+{
+	struct cass_dev *hw = pci_get_drvdata(pdev);
+
+	pci_disable_sriov(pdev);
+
+	if (hw->vf_listener) {
+		kthread_stop(hw->vf_listener);
+		hw->vf_listener = NULL;
+	}
+
+	hw->num_vfs = 0;
+}
+
+static int enable_sriov(struct pci_dev *pdev, int num_vfs)
+{
+	int rc;
+	int sriov;
+	u16 offset;
+	u16 stride;
+	union c_pi_cfg_pri_sriov pri_sriov = {};
+	struct cass_dev *hw = pci_get_drvdata(pdev);
+
+	rc = request_module("vsock");
+	if (rc) {
+		cxidev_err(&hw->cdev, "could not load vsock module");
+		goto err_novf;
+	}
+
+	rc = request_module("vsock_loopback");
+	if (rc) {
+		cxidev_err(&hw->cdev, "could not load vsock_loopback module");
+		goto err_novf;
+	}
+
+	hw->num_vfs = num_vfs;
+
+	if (!hw->vf_listener)
+		hw->vf_listener = kthread_run(pf_vf_listener, hw, "cxi_vf_listener");
+	if (IS_ERR(hw->vf_listener)) {
+		cxidev_err(&hw->cdev, "could not start vf listener thread");
+		rc = PTR_ERR(hw->vf_listener);
+		hw->vf_listener = NULL;
+		goto err_novf;
+	}
+
+	/* The VF Offset and Stride need to match the SR-IOV configuration. */
+	sriov = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
+	if (!sriov) {
+		cxidev_err(&hw->cdev, "No extended capabilities found\n");
+		rc = -ENODEV;
+		goto err_kill_listener;
+	}
+
+	pci_read_config_word(pdev, sriov + PCI_SRIOV_VF_OFFSET, &offset);
+	pci_read_config_word(pdev, sriov + PCI_SRIOV_VF_STRIDE, &stride);
+
+	pri_sriov.vf_offset = offset;
+	pri_sriov.vf_stride = stride;
+
+	cass_write(hw, C_PI_CFG_PRI_SRIOV, &pri_sriov,
+		   sizeof(union c_pi_cfg_pri_sriov));
+
+	rc = pci_enable_sriov(pdev, num_vfs);
+	if (rc) {
+		cxidev_err(&hw->cdev, "SRIOV enable failed %d\n", rc);
+		goto err_kill_listener;
+	}
+
+	return num_vfs;
+
+err_kill_listener:
+	kthread_stop(hw->vf_listener);
+	hw->vf_listener = NULL;
+err_novf:
+	hw->num_vfs = 0;
+	return rc;
+}
+
+int cass_sriov_configure(struct pci_dev *pdev, int num_vfs)
+{
+	if (num_vfs < 0)
+		return -EINVAL;
+
+	if (num_vfs == 0) {
+		disable_sriov(pdev);
+		return 0;
+	}
+
+	return enable_sriov(pdev, num_vfs);
+}
+
+static irqreturn_t pf_to_vf_int_cb(int irq, void *context)
+{
+	struct cass_dev *hw = context;
+
+	complete(&hw->pf_to_vf_comp);
+	return IRQ_HANDLED;
+}
+
+/* VF-side handler thread for receiving notifications from PF */
+static int vf_notif_handler(void *data)
+{
+	struct cass_dev *hw = (struct cass_dev *)data;
+	int rc;
+	size_t msg_len, rsp_len;
+
+	cxidev_dbg(&hw->cdev, "started notification handler");
+
+	while (!kthread_should_stop()) {
+		msg_len = MAX_VFMSG_SIZE;
+		rc = read_message_from_vsock(hw->vf_notif_sock, hw->vf_notif_buf,
+					     &msg_len, NULL, NULL, NULL, NULL);
+		if (rc == -EAGAIN) {
+			continue;
+		} else if (rc == -EINTR) {
+			/* Expected when thread is asked to terminate */
+			continue;
+		} else if (rc < 0) {
+			cxidev_err(&hw->cdev, "error reading notification from PF: %d", rc);
+			break;
+		} else if (rc == 0) {
+			cxidev_dbg(&hw->cdev, "notification connection closed by PF");
+			break;
+		}
+
+		cxidev_dbg(&hw->cdev, "received %ld byte notification from PF", msg_len);
+
+		rsp_len = 0;
+		rc = dispatch_vf_notif(hw, hw->vf_notif_buf, msg_len,
+				       hw->vf_notif_rsp_buf, &rsp_len);
+		rc = write_message_to_vsock(hw->vf_notif_sock, hw->vf_notif_rsp_buf,
+					    rsp_len, rc, 0);
+		if (rc < 0) {
+			cxidev_err(&hw->cdev, "failed to send notification response: %d", rc);
+			break;
+		}
+	}
+
+	cxidev_dbg(&hw->cdev, "notification handler exiting");
+
+	return 0;
+}
+
+int cass_vf_init(struct cass_dev *hw)
+{
+	int rc, seq;
+	unsigned int magic;
+	size_t msg_len = sizeof(magic);
+	bool init_done = false;
+	const struct cxi_vf_get_token_cmd token_cmd = {
+		.op = CXI_OP_VF_GET_TOKEN,
+	};
+	struct cxi_vf_get_token_resp token_resp;
+	size_t resp_len = sizeof(token_resp);
+	struct sockaddr_vm addr = {
+		.svm_family = AF_VSOCK,
+		.svm_port = CXI_SRIOV_VSOCK_PORT,
+		.svm_cid = VMADDR_CID_HOST,
+	};
+
+	if (!hw->with_vf_support)
+		return 0;
+
+	init_completion(&hw->pf_to_vf_comp);
+
+	mutex_init(&hw->vf_cmd_lock);
+
+	scnprintf(hw->pf_vf_int_name, sizeof(hw->pf_vf_int_name),
+		  "%s_from_pf", hw->cdev.name);
+	hw->pf_vf_vec = pci_irq_vector(hw->cdev.pdev, 0);
+	rc = request_irq(hw->pf_vf_vec, pf_to_vf_int_cb, 0, hw->pf_vf_int_name, hw);
+	if (rc)
+		return rc;
+
+	rc = request_module("vsock");
+	if (rc) {
+		cxidev_err(&hw->cdev, "could not load vsock module");
+		goto free_irq;
+	}
+
+	rc = sock_create_kern(&init_net, PF_VSOCK, SOCK_STREAM, 0, &hw->vf_req_sock);
+	if (rc < 0) {
+		cxidev_err(&hw->cdev, "vf socket create failed: %d", rc);
+		goto free_irq;
+	}
+
+	hw->vf_req_sock->sk->sk_rcvtimeo = CXI_SRIOV_VF_TIMEOUT;
+	hw->vf_cmd_seq = 0;
+
+	rc = kernel_connect(hw->vf_req_sock, (struct sockaddr_unsized *)&addr,
+			    sizeof(addr), 0);
+	if (rc < 0) {
+		cxidev_err(&hw->cdev, "vf socket connect failed: %d", rc);
+		goto release_vf_sock;
+	}
+
+	/* Handshake with PF driver starts here. */
+	seq = 0;
+	while (!init_done) {
+		msg_len = sizeof(magic);
+		do {
+			rc = read_message_from_vsock(hw->vf_req_sock, &magic, &msg_len,
+						     NULL, NULL, NULL, NULL);
+			if (rc == -EINTR)
+				schedule();
+		} while (rc == -EINTR);
+		if (rc < 0) {
+			cxidev_err(&hw->cdev, "error receiving magic from PF: %d", rc);
+			init_done = true;
+			break;
+		} else if (rc == 0) {
+			cxidev_err(&hw->cdev, "PF closed connection during handshake");
+			rc = -ENOTCONN;
+			init_done = true;
+			break;
+		}
+		switch (magic) {
+		case CXI_SRIOV_MAGIC1:
+			rc = wait_for_completion_timeout(&hw->pf_to_vf_comp,
+							 CXI_SRIOV_VF_TIMEOUT);
+			if (rc == 0) {
+				cxidev_err(&hw->cdev, "timed out waiting for irq from pf");
+				rc = -ETIMEDOUT;
+				init_done = true;
+				break;
+			}
+			magic = CXI_SRIOV_MAGIC1 + seq;
+			msg_len = sizeof(magic);
+			rc = write_message_to_vsock(hw->vf_req_sock, &magic,
+						    msg_len, 0, 0);
+			if (rc < 0) {
+				cxidev_err(&hw->cdev, "error sending magic to PF: %d", rc);
+				init_done = true;
+				break;
+			}
+			seq += 1;
+			break;
+		case CXI_SRIOV_MAGIC2:
+			init_done = true;
+			break;
+		default:
+			cxidev_err(&hw->cdev, "got unexpected magic from PF: %x", magic);
+			rc = -EINVAL;
+			init_done = true;
+			break;
+		}
+	}
+
+	if (rc < 0)
+		goto shutdown_vf_sock;
+
+	/* Handshake successful, now retrieve token and connect notification socket */
+	rc = cxi_send_msg_to_pf(&hw->cdev, &token_cmd, sizeof(token_cmd),
+				&token_resp, &resp_len);
+	if (rc < 0) {
+		cxidev_err(&hw->cdev, "failed to get token from PF: %d", rc);
+		goto shutdown_vf_sock;
+	}
+
+	rc = sock_create_kern(&init_net, PF_VSOCK, SOCK_STREAM, 0,
+			      &hw->vf_notif_sock);
+	if (rc < 0) {
+		cxidev_err(&hw->cdev, "vf notif socket create failed: %d", rc);
+		goto shutdown_vf_sock;
+	}
+
+	hw->vf_notif_sock->sk->sk_rcvtimeo = CXI_SRIOV_VF_TIMEOUT;
+
+	addr.svm_port = CXI_SRIOV_VSOCK_NOTIF_PORT;
+	rc = kernel_connect(hw->vf_notif_sock, (struct sockaddr_unsized *)&addr,
+			    sizeof(addr), 0);
+	if (rc < 0) {
+		cxidev_err(&hw->cdev, "vf notif socket connect failed: %d", rc);
+		goto release_notif_sock;
+	}
+
+	/* Send token to identify this VF */
+	rc = write_message_to_vsock(hw->vf_notif_sock, &token_resp.token,
+				    sizeof(token_resp.token), 0, 0);
+	if (rc < 0) {
+		cxidev_err(&hw->cdev, "failed to send token to PF: %d", rc);
+		goto shutdown_notif_sock;
+	}
+
+	/* Start notification handler thread */
+	hw->vf_notif_handler = kthread_run(vf_notif_handler, hw, "cxi_vf_notif");
+	if (IS_ERR(hw->vf_notif_handler)) {
+		cxidev_err(&hw->cdev, "failed to start notification handler");
+		rc = PTR_ERR(hw->vf_notif_handler);
+		hw->vf_notif_handler = NULL;
+		goto shutdown_notif_sock;
+	}
+
+	return 0;
+
+shutdown_notif_sock:
+	kernel_sock_shutdown(hw->vf_notif_sock, SHUT_RDWR);
+release_notif_sock:
+	sock_release(hw->vf_notif_sock);
+	hw->vf_notif_sock = NULL;
+shutdown_vf_sock:
+	kernel_sock_shutdown(hw->vf_req_sock, SHUT_RDWR);
+release_vf_sock:
+	sock_release(hw->vf_req_sock);
+	hw->vf_req_sock = NULL;
+free_irq:
+	free_irq(hw->pf_vf_vec, hw);
+	return rc;
+}
+
+void cass_vf_fini(struct cass_dev *hw)
+{
+	if (!hw->with_vf_support)
+		return;
+
+	free_irq(hw->pf_vf_vec, hw);
+
+	if (hw->vf_notif_handler) {
+		kthread_stop(hw->vf_notif_handler);
+		hw->vf_notif_handler = NULL;
+	}
+
+	mutex_lock(&hw->vf_cmd_lock);
+	if (hw->vf_req_sock) {
+		kernel_sock_shutdown(hw->vf_req_sock, SHUT_RDWR);
+		sock_release(hw->vf_req_sock);
+		hw->vf_req_sock = NULL;
+	}
+	mutex_unlock(&hw->vf_cmd_lock);
+
+	if (hw->vf_notif_sock) {
+		kernel_sock_shutdown(hw->vf_notif_sock, SHUT_RDWR);
+		sock_release(hw->vf_notif_sock);
+		hw->vf_notif_sock = NULL;
+	}
+}
+
+/**
+ * cxi_vsock_send() - Send a vsock message using a provided socket
+ *
+ * @cdev: the device
+ * @sock: connected vsock socket
+ * @req: message data
+ * @req_len: length of message
+ * @rsp: buffer for response
+ * @rsp_len: length of response buffer (updated to reflect response length)
+ * @seq: sequence number to include in message header and expect in response
+ */
+
+static int cxi_vsock_send(struct cxi_dev *cdev, struct socket *sock, const void *req,
+			  size_t req_len, void *rsp, size_t *rsp_len, int seq)
+{
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	int rc;
+	int msg_rc;
+	int rsp_seq;
+
+	if (req_len > MAX_VFMSG_SIZE)
+		return -EINVAL;
+
+	if (!sock)
+		return -ENOTCONN;
+
+	rc = write_message_to_vsock(sock, req, req_len, 0, seq);
+	if (rc < 0) {
+		cxidev_err(&hw->cdev, "error sending vsock message: %d", rc);
+		return -EPROTO;
+	}
+	rc = read_message_from_vsock(sock, rsp, rsp_len, &msg_rc,
+				     NULL, NULL, &rsp_seq);
+	if (rc == -EAGAIN) {
+		kernel_sock_shutdown(sock, SHUT_RDWR);
+		cxidev_err(&hw->cdev, "vsock response timed out\n");
+		return -ETIMEDOUT;
+	} else if (rc <= 0) {
+		kernel_sock_shutdown(sock, SHUT_RDWR);
+		cxidev_err(&hw->cdev, "error reading vsock response: %d", rc);
+		return -EPROTO;
+	}
+
+	if (rsp_seq != seq) {
+		kernel_sock_shutdown(sock, SHUT_RDWR);
+		cxidev_err(&hw->cdev, "expected response seq %d but got %d",
+			   seq, rsp_seq);
+		return -EPROTO;
+	}
+
+	return msg_rc;
+}
+
+/**
+ * cxi_send_msg_to_pf() - Send a message from VF to PF
+ *
+ * @cdev: the device
+ * @req: message data
+ * @req_len: length of message
+ * @rsp: buffer for response from PF
+ * @rsp_len: length of response buffer (updated to reflect response length)
+ */
+int cxi_send_msg_to_pf(struct cxi_dev *cdev, const void *req,
+		       size_t req_len, void *rsp, size_t *rsp_len)
+{
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	int rc;
+
+	if (cdev->is_physfn)
+		return -EINVAL;
+
+	cxidev_dbg(&hw->cdev, "Sending %ld bytes to PF", req_len);
+
+	mutex_lock(&hw->vf_cmd_lock);
+	rc = cxi_vsock_send(cdev, hw->vf_req_sock, req, req_len, rsp, rsp_len,
+			    hw->vf_cmd_seq++);
+	mutex_unlock(&hw->vf_cmd_lock);
+
+	cxidev_dbg(&hw->cdev, "Got %ld byte reply from PF, rc=%d",
+		   rsp_len ? *rsp_len : 0, rc);
+
+	return rc;
+}
+EXPORT_SYMBOL(cxi_send_msg_to_pf);
+
+/**
+ * cxi_send_msg_to_vf() - Send a message from PF to a specific VF
+ *
+ * @cdev: the device
+ * @vf_num: VF index to send the message to
+ * @req: message data
+ * @req_len: length of message
+ * @rsp: buffer for response from VF
+ * @rsp_len: length of response buffer (updated to reflect response length)
+ */
+int cxi_send_msg_to_vf(struct cxi_dev *cdev, int vf_num, const void *req,
+		       size_t req_len, void *rsp, size_t *rsp_len)
+{
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	int rc;
+
+	if (!cdev->is_physfn)
+		return -EINVAL;
+
+	if (vf_num < 0 || vf_num >= hw->num_vfs)
+		return -EINVAL;
+
+	cxidev_dbg(&hw->cdev, "Sending %ld bytes to VF %d", req_len, vf_num);
+
+	mutex_lock(&hw->vfs[vf_num].notif_lock);
+	rc = cxi_vsock_send(cdev, hw->vfs[vf_num].notif_sock,
+			    req, req_len, rsp, rsp_len,
+			    hw->vfs[vf_num].notif_seq++);
+	mutex_unlock(&hw->vfs[vf_num].notif_lock);
+
+	cxidev_dbg(&hw->cdev, "Got %ld byte reply from VF %d, rc=%d",
+		   rsp_len ? *rsp_len : 0, vf_num, rc);
+
+	return rc;
+}
+EXPORT_SYMBOL(cxi_send_msg_to_vf);
+
+/**
+ * cxi_register_msg_relay() - Register a VF to PF message handler
+ *
+ * The user driver, when inserting a new PF device, is registering a
+ * callback to receive messages from VFs.
+ *
+ * @cdev: the device
+ * @msg_relay: the message handler
+ * @msg_relay_data: opaque pointer to give when caller the handler
+ */
+int cxi_register_msg_relay(struct cxi_dev *cdev, cxi_msg_relay_t msg_relay,
+			   void *msg_relay_data)
+{
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	int rc;
+
+	if (!cdev->is_physfn)
+		return -EINVAL;
+
+	mutex_lock(&hw->msg_relay_lock);
+
+	if (hw->msg_relay) {
+		rc = -EINVAL;
+	} else {
+		hw->msg_relay = msg_relay;
+		hw->msg_relay_data = msg_relay_data;
+		rc = 0;
+	}
+
+	mutex_unlock(&hw->msg_relay_lock);
+
+	return rc;
+}
+EXPORT_SYMBOL(cxi_register_msg_relay);
+
+int cxi_unregister_msg_relay(struct cxi_dev *cdev)
+{
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	int rc;
+
+	mutex_lock(&hw->msg_relay_lock);
+
+	if (!hw->msg_relay) {
+		rc = -EINVAL;
+	} else {
+		hw->msg_relay = NULL;
+		hw->msg_relay_data = NULL;
+		rc = 0;
+	}
+
+	mutex_unlock(&hw->msg_relay_lock);
+
+	return rc;
+}
+EXPORT_SYMBOL(cxi_unregister_msg_relay);
+
+int cass_vf_get_token(struct cxi_dev *cdev, int vf_idx, unsigned int *token)
+{
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+
+	if (!cdev->is_physfn)
+		return -EOPNOTSUPP;
+
+	if (vf_idx < 0 || vf_idx >= hw->num_vfs)
+		return -EINVAL;
+
+	*token = hw->vfs[vf_idx].token;
+	return 0;
+}
+EXPORT_SYMBOL(cass_vf_get_token);
+
+#endif /* CXI_DISABLE_SRIOV */
diff --git a/drivers/net/ethernet/hpe/ss1/cass_vf.c b/drivers/net/ethernet/hpe/ss1/cass_vf.c
new file mode 100644
index 000000000000..fde40d1b491a
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_vf.c
@@ -0,0 +1,58 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/hpe/cxi/cxi.h>
+#include <linux/dma-mapping.h>
+#include "cass_core.h"
+#include "cass_vf.h"
+
+/* Compile-time assertions to ensure VF structures can be safely cast to their
+ * corresponding PF structures and vice versa.
+ * These verify that the common fields are at the same offsets in both structures.
+ */
+static inline void __cxi_vf_structure_offset_checks(void)
+{
+	/* Ensure cxi_lni_priv_vf can be cast to cxi_lni_priv */
+	BUILD_BUG_ON(offsetof(struct cxi_lni_priv_vf, dev) !=
+		     offsetof(struct cxi_lni_priv, dev));
+	BUILD_BUG_ON(offsetof(struct cxi_lni_priv_vf, lni) !=
+		     offsetof(struct cxi_lni_priv, lni));
+
+	/* Ensure cxi_domain_priv_vf can be cast to cxi_domain_priv */
+	BUILD_BUG_ON(offsetof(struct cxi_domain_priv_vf, domain) !=
+		     offsetof(struct cxi_domain_priv, domain));
+	BUILD_BUG_ON(offsetof(struct cxi_domain_priv_vf, lni_priv) !=
+		     offsetof(struct cxi_domain_priv, lni_priv));
+
+	/* Ensure cxi_cp_priv_vf can be cast to cxi_cp_priv */
+	BUILD_BUG_ON(offsetof(struct cxi_cp_priv_vf, dev) !=
+		     offsetof(struct cxi_cp_priv, dev));
+	BUILD_BUG_ON(offsetof(struct cxi_cp_priv_vf, cp) !=
+		     offsetof(struct cxi_cp_priv, cp));
+
+	/* Ensure cxi_cq_priv_vf can be cast to cxi_cq_priv */
+	BUILD_BUG_ON(offsetof(struct cxi_cq_priv_vf, lni_priv) !=
+		     offsetof(struct cxi_cq_priv, lni_priv));
+	BUILD_BUG_ON(offsetof(struct cxi_cq_priv_vf, cass_cq) !=
+		     offsetof(struct cxi_cq_priv, cass_cq));
+	BUILD_BUG_ON(offsetof(struct cxi_cq_priv_vf, pages) !=
+		     offsetof(struct cxi_cq_priv, pages));
+	BUILD_BUG_ON(offsetof(struct cxi_cq_priv_vf, cq_mmio) !=
+		     offsetof(struct cxi_cq_priv, cq_mmio));
+	BUILD_BUG_ON(offsetof(struct cxi_cq_priv_vf, flags) !=
+		     offsetof(struct cxi_cq_priv, flags));
+
+	/* Ensure cxi_md_priv_vf can be cast to cxi_md_priv */
+	BUILD_BUG_ON(offsetof(struct cxi_md_priv_vf, lni_priv) !=
+		     offsetof(struct cxi_md_priv, lni_priv));
+	BUILD_BUG_ON(offsetof(struct cxi_md_priv_vf, device) !=
+		     offsetof(struct cxi_md_priv, device));
+	BUILD_BUG_ON(offsetof(struct cxi_md_priv_vf, md) !=
+		     offsetof(struct cxi_md_priv, md));
+	BUILD_BUG_ON(offsetof(struct cxi_md_priv_vf, sgt) !=
+		     offsetof(struct cxi_md_priv, sgt));
+	BUILD_BUG_ON(offsetof(struct cxi_md_priv_vf, pages) !=
+		     offsetof(struct cxi_md_priv, pages));
+	BUILD_BUG_ON(offsetof(struct cxi_md_priv_vf, flags) !=
+		     offsetof(struct cxi_md_priv, flags));
+}
diff --git a/drivers/net/ethernet/hpe/ss1/cass_vf_notif.c b/drivers/net/ethernet/hpe/ss1/cass_vf_notif.c
new file mode 100644
index 000000000000..c46e19869873
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_vf_notif.c
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+
+#include "cass_core.h"
+#include "cxi_core.h"
+#include "cass_vf_notif.h"
+
+#if !defined(CXI_DISABLE_SRIOV)
+
+static int cass_vf_notif_ping_handler(struct cass_dev *hw,
+				      const void *cmd_in, void *resp,
+				      size_t *resp_len)
+{
+	return 0;
+}
+
+static const struct cass_vf_notif_info vf_notif_info[] = {
+	[CASS_VF_NOTIF_OP_PING] = {
+		.req_size   = sizeof(struct cass_vf_notif_ping),
+		.name       = "PING",
+		.handler    = cass_vf_notif_ping_handler, },
+};
+
+int dispatch_vf_notif(struct cass_dev *hw, const void *req, size_t req_len,
+		      void *rsp, size_t *rsp_len)
+{
+	const struct cass_vf_notif_common *common_req = req;
+	enum cass_vf_notif_ops op;
+	const struct cass_vf_notif_info *info;
+
+	op = common_req->op;
+	if (op <= CASS_VF_NOTIF_OP_INVALID || op >= CASS_VF_NOTIF_OP_MAX)
+		return -EINVAL;
+
+	info = &vf_notif_info[op];
+	if (!info->handler)
+		return -EOPNOTSUPP;
+
+	if (req_len != info->req_size)
+		return -EINVAL;
+
+	cxidev_dbg(&hw->cdev, "VF notification received: %s\n", info->name);
+
+	return info->handler(hw, req, rsp, rsp_len);
+}
+
+#endif /* CXI_DISABLE_SRIOV */

-- 
2.56.0


^ permalink raw reply	[flat|nested] 25+ messages in thread
* [PATCH 20/23] net: hpe: ss1: add the CXI core interfaces
  2026-10-30 20:58 [PATCH 00/23] Subject: [PATCH net-next 00/23] net/hpe: add HPE Slingshot NIC drivers Doug Ledford
                   ` (18 preceding siblings ...)
  2026-10-30 20:59 ` [PATCH 19/23] net: hpe: ss1: add SR-IOV support Doug Ledford
@ 2026-10-30 20:59 ` Doug Ledford
  2026-10-30 20:59 ` [PATCH 21/23] net: hpe: ss1: add resource groups, QoS and services Doug Ledford
                   ` (3 subsequent siblings)
  23 siblings, 0 replies; 25+ messages in thread
From: Doug Ledford @ 2026-10-30 20:59 UTC (permalink / raw)
  To: Slingshot Open Source Team, Nathan Chancellor, Nicolas Schier,
	Richard Cochran, Andrew Lunn, David S. Miller, Eric Dumazet,
	Jakub Kicinski, Paolo Abeni, Sumit Semwal, Christian König,
	Guenter Roeck
  Cc: linux-kernel, netdev, linux-kbuild, Doug Ledford, Sandeep Bhoot,
	Mamila Santosh

Add the CXI core interface: client registration, the auxiliary device
used by the RDMA driver, link control and the configuration tables.

Known limitation, deferred to V2: this patch carries SR-IOV
virtual-function code (VF-to-PF mailbox requests, mailbox opcodes or VF
resource handling) from an older, incomplete version of the Cassini
SR-IOV support. V2 of this series will include the updated SR-IOV
implementation, so issues in the VF paths should be ignored for now.

checkpatch --strict (100 columns) still reports the following in this
patch. They need coordination with the internal repositories this code
is maintained in and will be fixed in V2:
- WARNING: ALLOC_WITH_SIZEOF (23), LONG_LINE (4), SPDX_LICENSE_TAG (4),
  BLOCK_COMMENT_STYLE (1), BRACES (1), MACRO_WITH_FLOW_CONTROL (1),
  MODULE_LICENSE (1)
- CHECK: ALLOC_SIZEOF_STRUCT (2)

Co-developed-by: Sandeep Bhoot <sandeep.bhoot@hpe.com>
Signed-off-by: Sandeep Bhoot <sandeep.bhoot@hpe.com>
Co-developed-by: Mamila Santosh <santosh-kumar.mamila@hpe.com>
Signed-off-by: Mamila Santosh <santosh-kumar.mamila@hpe.com>
Signed-off-by: Doug Ledford <doug.ledford@hpe.com>
---
 drivers/net/ethernet/hpe/ss1/cxi_aux_dev.c |  137 ++
 drivers/net/ethernet/hpe/ss1/cxi_config.c  | 2990 ++++++++++++++++++++++++++++
 drivers/net/ethernet/hpe/ss1/cxi_core.c    |  281 +++
 drivers/net/ethernet/hpe/ss1/cxi_link.c    |  227 +++
 4 files changed, 3635 insertions(+)

diff --git a/drivers/net/ethernet/hpe/ss1/cxi_aux_dev.c b/drivers/net/ethernet/hpe/ss1/cxi_aux_dev.c
new file mode 100644
index 000000000000..74f20e156d5e
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cxi_aux_dev.c
@@ -0,0 +1,137 @@
+/* SPDX-License-Identifier: GPL-2.0*/
+/* Copyright 2026 Hewlett Packard Enterprise Development LP */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/hpe/cxi/cxi.h>
+#include <linux/hpe/cxi/driver.h>
+#include <linux/hpe/cxi/cxi_prov_hw.h>
+#include "cass_core.h"
+#include "cxi_aux_dev.h"
+#include "cxi_internal.h"
+
+void cxi_release_aux_dev(struct device *dev)
+{
+	struct cxi_adev *cadev = container_of(dev, struct cxi_adev, adev.dev);
+
+	kfree(cadev);
+}
+
+/* Stop publishing the auxiliary device and wait for anyone using it. */
+static void cxi_ib_unpublish_adev(struct cass_dev *hw)
+{
+	mutex_lock(&hw->cxi_adev_lock);
+	hw->cxi_adev = NULL;
+	mutex_unlock(&hw->cxi_adev_lock);
+}
+
+void cxi_ib_remove_adev(struct cass_dev *hw)
+{
+	struct cxi_adev *cadev;
+
+	/*
+	 * Unpublish first. A NID change in progress holds the lock, so once
+	 * this returns nothing can still be using the device, and nothing new
+	 * can find it.
+	 */
+	mutex_lock(&hw->cxi_adev_lock);
+	cadev = hw->cxi_adev;
+	hw->cxi_adev = NULL;
+	mutex_unlock(&hw->cxi_adev_lock);
+
+	if (!cadev)
+		return;
+
+	auxiliary_device_delete(&cadev->adev);
+	auxiliary_device_uninit(&cadev->adev);
+}
+
+u8 *cxi_get_mac_addr(struct cxi_dev *dev)
+{
+	return dev->mac_addr;
+}
+
+int cxi_ib_add_adev(struct pci_dev *pdev, struct cass_dev *hw, int cxi_num)
+{
+	struct auxiliary_device *adev;
+	struct cxi_adev *cadev;
+	int rc;
+
+	cadev = kzalloc(sizeof(*cadev), GFP_KERNEL);
+	if (!cadev)
+		return -ENOMEM;
+
+	cadev->dev = &pdev->dev;
+	cadev->pdev = pdev;
+	cadev->cxi_dev = &hw->cdev;
+	BLOCKING_INIT_NOTIFIER_HEAD(&cadev->nid_notifier);
+	cadev->lni_alloc = cxi_lni_alloc;
+	cadev->svc_enable = cxi_svc_enable;
+	cadev->svc_set_vni_range = cxi_svc_set_vni_range;
+	cadev->svc_get_vni_range = cxi_svc_get_vni_range;
+	cadev->tc_cfg = cxi_tc_cfg;
+	cadev->pid_alloc = cxi_lni_pid_alloc;
+	cadev->pid_free = cxi_lni_pid_free;
+	cadev->lni_free  = cxi_lni_free;
+	cadev->query_device = NULL; /* optional */
+	cadev->cxi_map  = cxi_map;
+	cadev->dev_info_get = cxi_dev_info_get;
+	cadev->is_link_up   = cxi_is_link_up;
+	cadev->svc_get = cxi_svc_get;
+	cadev->svc_rsrc_get = cxi_svc_rsrc_get;
+	cadev->svc_alloc = cxi_svc_alloc;
+	cadev->svc_destroy = cxi_svc_destroy;
+	cadev->job_tc_bind = cxi_job_tc_bind;
+	cadev->tc_clear = cxi_tc_clear;
+	cadev->tc_list = cxi_tc_list;
+	cadev->domain_reserve = cxi_domain_reserve;
+	cadev->domain_alloc = cxi_domain_alloc;
+	cadev->domain_free = cxi_domain_free;
+	cadev->cp_alloc = cxi_cp_alloc;
+	cadev->cp_free = cxi_cp_free;
+	cadev->cq_alloc = cxi_cq_alloc;
+	cadev->cq_free = cxi_cq_free;
+	cadev->cxi_pte_alloc = cxi_pte_alloc;
+	cadev->cq_user_info = cxi_cq_user_info;
+	cadev->eq_alloc = cxi_eq_alloc;
+	cadev->eq_free = cxi_eq_free;
+	cadev->eq_get_event = cxi_eq_get_event;
+	cadev->eq_next_event = cxi_eq_next_event;
+	cadev->cxi_unmap = cxi_unmap;
+	cadev->cxi_pte_free = cxi_pte_free;
+	cadev->ct_alloc = cxi_ct_alloc;
+	cadev->ct_free  = cxi_ct_free;
+	cadev->clear_md = cxi_clear_md;
+	cadev->eq_user_info = cxi_eq_user_info;
+	cadev->ct_user_info = cxi_ct_user_info;
+	cadev->pte_map = cxi_pte_map;
+	cadev->pte_unmap = cxi_pte_unmap;
+	cadev->get_mac_addr = cxi_get_mac_addr;
+
+	adev = &cadev->adev;
+	adev->name = "rdma";
+	adev->id = cxi_num;
+	adev->dev.parent = &pdev->dev;
+	adev->dev.release = cxi_release_aux_dev;
+
+	mutex_lock(&hw->cxi_adev_lock);
+	hw->cxi_adev = cadev;
+	mutex_unlock(&hw->cxi_adev_lock);
+
+	rc = auxiliary_device_init(adev);
+	if (rc) {
+		cxi_ib_unpublish_adev(hw);
+		kfree(cadev);
+		return rc;
+	}
+
+	rc = auxiliary_device_add(adev);
+	if (rc) {
+		cxi_ib_unpublish_adev(hw);
+		auxiliary_device_uninit(adev);	/* release() frees cadev */
+		return rc;
+	}
+
+	return 0;
+}
+
diff --git a/drivers/net/ethernet/hpe/ss1/cxi_config.c b/drivers/net/ethernet/hpe/ss1/cxi_config.c
new file mode 100644
index 000000000000..dd604753daee
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cxi_config.c
@@ -0,0 +1,2990 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+/* Copyright 2025 Hewlett Packard Enterprise Development LP */
+
+/*
+ * Configuration and Management of rgroup/rx profile/tx profile using
+ * configfs Filesystem Interface
+ */
+
+#include "cxi_config.h"
+
+struct cxi_cfg_teardown_marker {
+	struct list_head list;
+	struct config_item *item;
+};
+
+static LIST_HEAD(cxi_cfg_teardown_markers);
+static DEFINE_SPINLOCK(cxi_cfg_teardown_lock);
+
+static void cxi_cfg_drop_item_ref(struct config_item *item)
+{
+	struct cxi_cfg_teardown_marker *marker;
+	unsigned long flags;
+	bool teardown_owns_ref = false;
+
+	spin_lock_irqsave(&cxi_cfg_teardown_lock, flags);
+	list_for_each_entry(marker, &cxi_cfg_teardown_markers, list) {
+		if (marker->item == item) {
+			teardown_owns_ref = true;
+			break;
+		}
+	}
+	spin_unlock_irqrestore(&cxi_cfg_teardown_lock, flags);
+
+	if (!teardown_owns_ref)
+		config_item_put(item);
+}
+
+static enum cxi_resource_type cxi_resource_str_to_type(const char *name)
+{
+	int i;
+
+	for (i = CXI_RESOURCE_PTLTE; i < CXI_RESOURCE_MAX; i++) {
+		if (strcmp(name, cxi_resource_type_strs[i]) == 0)
+			return i;
+	}
+
+	return CXI_RESOURCE_MAX;
+}
+
+static struct config_group *get_parent_config_group(struct config_group *child_group)
+{
+	struct config_group *parent_config_group;
+
+	if (!child_group->cg_item.ci_parent)
+		return NULL;
+
+	parent_config_group = container_of(child_group->cg_item.ci_parent,
+					   struct config_group,
+					   cg_item);
+
+	return parent_config_group;
+}
+
+static const int resource_max[CXI_RESOURCE_MAX] = {
+	[CXI_RESOURCE_PTLTE] = C_NUM_PTLTES,
+	[CXI_RESOURCE_TXQ] = C_NUM_TRANSMIT_CQS,
+	[CXI_RESOURCE_TGQ] = C_NUM_TARGET_CQS,
+	[CXI_RESOURCE_EQ] = EQS_AVAIL,
+	[CXI_RESOURCE_CT] = CTS_AVAIL,
+	[CXI_RESOURCE_PE0_LE] = PE_LE_MAX,
+	[CXI_RESOURCE_PE1_LE] = PE_LE_MAX,
+	[CXI_RESOURCE_PE2_LE] = PE_LE_MAX,
+	[CXI_RESOURCE_PE3_LE] = PE_LE_MAX,
+	[CXI_RESOURCE_TLE] = 0,
+	[CXI_RESOURCE_AC] = ACS_AVAIL,
+};
+
+static struct cxi_cfg_rgroup_ac_entry_sub *to_cxi_cfg_rgroup_ac_entry_sub(struct config_item *item)
+{
+	return container_of(to_config_group(item), struct cxi_cfg_rgroup_ac_entry_sub, group);
+}
+
+static ssize_t cxi_cfg_rgroup_ac_entry_sub_type_show(struct config_item *item,
+						     char *page)
+{
+	struct cxi_cfg_rgroup_ac_entry_sub *ac_entry_sub;
+	int rc;
+	enum cxi_ac_type ac_type;
+	union cxi_ac_data ac_data;
+
+	ac_entry_sub = to_cxi_cfg_rgroup_ac_entry_sub(item);
+
+	rc = cxi_rgroup_get_ac_entry_data(ac_entry_sub->rgroup,
+					  ac_entry_sub->id,
+					  &ac_type,
+					  &ac_data);
+	if (rc)
+		return rc;
+
+	return sprintf(page, "%d\n", ac_type);
+}
+
+static ssize_t cxi_cfg_rgroup_ac_entry_sub_type_store(struct config_item *item,
+						      const char *page,
+						      size_t count)
+{
+	struct cxi_cfg_rgroup_ac_entry_sub *ac_entry_sub;
+	int rc;
+	enum cxi_ac_type ac_type_val;
+	union cxi_ac_data ac_data_t = {};
+	unsigned int ac_entry_id;
+
+	ac_entry_sub = to_cxi_cfg_rgroup_ac_entry_sub(item);
+	if (!ac_entry_sub->rgroup) {
+		pr_debug("Unable to get rgroup reference\n");
+		return -EINVAL;
+	}
+
+	rc = kstrtouint(page, 0, (unsigned int *)&ac_type_val);
+	if (rc)
+		return rc;
+
+	if (ac_type_val == CXI_AC_UID)
+		ac_data_t.uid = ac_entry_sub->ac_data.uid;
+	else if (ac_type_val == CXI_AC_GID)
+		ac_data_t.gid = ac_entry_sub->ac_data.gid;
+	else if (ac_type_val == CXI_AC_NETNS)
+		ac_data_t.netns = ac_entry_sub->ac_data.netns;
+	else if (ac_type_val == CXI_AC_OPEN)
+		pr_debug("Setting type to CXI_AC_OPEN\n");
+	else
+		return -EINVAL;
+
+	rc = cxi_rgroup_add_ac_entry(ac_entry_sub->rgroup,
+				     ac_type_val,
+				     &ac_data_t,
+				     &ac_entry_id);
+	if (rc < 0) {
+		pr_debug("Unable to add ac entry to resource group: err val %d\n", rc);
+		return rc;
+	}
+
+	ac_entry_sub->ac_type = ac_type_val;
+	ac_entry_sub->id = ac_entry_id;
+
+	return count;
+}
+
+static ssize_t cxi_cfg_rgroup_ac_entry_sub_data_show(struct config_item *item,
+						     char *page)
+{
+	struct cxi_cfg_rgroup_ac_entry_sub *ac_entry_sub;
+	enum cxi_ac_type ac_type;
+	union cxi_ac_data ac_data;
+	int rc;
+
+	ac_entry_sub = to_cxi_cfg_rgroup_ac_entry_sub(item);
+
+	rc = cxi_rgroup_get_ac_entry_data(ac_entry_sub->rgroup,
+					  ac_entry_sub->id,
+					  &ac_type,
+					  &ac_data);
+	if (rc)
+		return rc;
+
+	if (ac_type == CXI_AC_UID)
+		return sprintf(page, "%d\n", ac_data.uid);
+	else if (ac_type == CXI_AC_GID)
+		return sprintf(page, "%d\n", ac_data.gid);
+	else if (ac_type == CXI_AC_NETNS)
+		return sprintf(page, "%d\n", ac_data.netns);
+	else if (ac_type == CXI_AC_OPEN)
+		return sprintf(page, "%d\n", CXI_AC_OPEN);
+
+	return -EINVAL;
+}
+
+static ssize_t cxi_cfg_rgroup_ac_entry_sub_data_store(struct config_item *item,
+						      const char *page,
+						      size_t count)
+{
+	struct cxi_cfg_rgroup_ac_entry_sub *ac_entry_sub;
+	int rc;
+	unsigned int ac_data_val;
+
+	ac_entry_sub = to_cxi_cfg_rgroup_ac_entry_sub(item);
+
+	rc = kstrtouint(page, 0, &ac_data_val);
+	if (rc)
+		return rc;
+
+	if (ac_entry_sub->ac_type == CXI_AC_UID) {
+		ac_entry_sub->ac_data.uid = ac_data_val;
+		return count;
+	} else if (ac_entry_sub->ac_type == CXI_AC_GID) {
+		ac_entry_sub->ac_data.gid = ac_data_val;
+		return count;
+	} else if (ac_entry_sub->ac_type == CXI_AC_NETNS) {
+		ac_entry_sub->ac_data.netns = ac_data_val;
+		return count;
+	}
+
+	return -EINVAL;
+}
+
+static void cxi_cfg_rgroup_ac_entry_sub_free(struct config_item *item)
+{
+	struct cxi_cfg_rgroup_ac_entry_sub *ac_entry_sub;
+
+	ac_entry_sub = container_of(item, struct cxi_cfg_rgroup_ac_entry_sub,
+				    group.cg_item);
+	kfree(ac_entry_sub);
+}
+
+CONFIGFS_ATTR(cxi_cfg_rgroup_ac_entry_sub_, type);
+CONFIGFS_ATTR(cxi_cfg_rgroup_ac_entry_sub_, data);
+
+static struct configfs_attribute *cxi_cfg_rgroup_ac_entry_sub_attrs[] = {
+	&cxi_cfg_rgroup_ac_entry_sub_attr_type,
+	&cxi_cfg_rgroup_ac_entry_sub_attr_data,
+	NULL,
+};
+
+static struct configfs_item_operations cxi_cfg_rgroup_ac_entry_sub_item_ops = {
+	.release     = cxi_cfg_rgroup_ac_entry_sub_free,
+};
+
+static const struct config_item_type cxi_cfg_rgroup_ac_entry_sub_type = {
+	.ct_attrs       = cxi_cfg_rgroup_ac_entry_sub_attrs,
+	.ct_item_ops    = &cxi_cfg_rgroup_ac_entry_sub_item_ops,
+	.ct_owner       = THIS_MODULE,
+};
+
+static struct cxi_cfg_rgroup_ac_entry_sub *alloc_dev_rgroup_ac_entry_sub(const char *name)
+{
+	struct cxi_cfg_rgroup_ac_entry_sub *ac_entry_dir_sub;
+
+	ac_entry_dir_sub = kzalloc(sizeof(*ac_entry_dir_sub),
+				   GFP_KERNEL);
+	if (!ac_entry_dir_sub)
+		return NULL;
+
+	strscpy(ac_entry_dir_sub->name, name, sizeof(ac_entry_dir_sub->name));
+
+	config_group_init_type_name(&ac_entry_dir_sub->group,
+				    ac_entry_dir_sub->name,
+				    &cxi_cfg_rgroup_ac_entry_sub_type);
+
+	return ac_entry_dir_sub;
+}
+
+static struct
+config_group *cxi_cfg_rgroup_ac_entry_make_group(struct config_group *group,
+						 const char *name)
+{
+	struct cxi_cfg_rgroup_ac_entry *ac_entry;
+	struct cxi_cfg_rgroup_ac_entry_sub *ac_entry_sub;
+
+	if (strlen(name) > CONFIGFS_DIR_LEN - 1)
+		return ERR_PTR(-EINVAL);
+
+	ac_entry = container_of(group, struct cxi_cfg_rgroup_ac_entry, group);
+
+	ac_entry_sub = alloc_dev_rgroup_ac_entry_sub(name);
+	if (!ac_entry_sub) {
+		pr_debug("Failed to alloc memory for configfs ac entry");
+		return ERR_PTR(-ENOMEM);
+	}
+
+	ac_entry_sub->rgroup = ac_entry->rgroup;
+	ac_entry_sub->ac_type = CXI_AC_UID;
+	ac_entry_sub->ac_data.uid = 0;
+
+	return &ac_entry_sub->group;
+}
+
+static void
+cxi_cfg_rgroup_ac_entry_drop_item(struct config_group *group,
+				  struct config_item *item)
+{
+	struct cxi_cfg_rgroup_ac_entry_sub *ac_entry_sub;
+	unsigned int ac_entry_id;
+	int rc;
+
+	ac_entry_sub = container_of(item, struct cxi_cfg_rgroup_ac_entry_sub, group.cg_item);
+
+	if (ac_entry_sub->ac_type == CXI_AC_UID) {
+		rc = cxi_rgroup_get_ac_entry_id_by_data(ac_entry_sub->rgroup,
+							CXI_AC_UID,
+							&ac_entry_sub->ac_data,
+							&ac_entry_id);
+
+		pr_debug("Getting an entry info rc = %d\n", rc);
+	} else if (ac_entry_sub->ac_type == CXI_AC_GID) {
+		rc = cxi_rgroup_get_ac_entry_id_by_data(ac_entry_sub->rgroup,
+							CXI_AC_GID,
+							&ac_entry_sub->ac_data,
+							&ac_entry_id);
+
+		pr_debug("Getting an entry info rc = %d\n", rc);
+	} else if (ac_entry_sub->ac_type == CXI_AC_NETNS) {
+		rc = cxi_rgroup_get_ac_entry_id_by_data(ac_entry_sub->rgroup,
+							CXI_AC_NETNS,
+							&ac_entry_sub->ac_data,
+							&ac_entry_id);
+		pr_debug("Getting an entry info rc = %d\n", rc);
+	} else {
+		rc = cxi_rgroup_get_ac_entry_id_by_data(ac_entry_sub->rgroup,
+							CXI_AC_OPEN,
+							NULL,
+							&ac_entry_id);
+		pr_debug("Getting an entry info rc = %d\n", rc);
+	}
+
+	if (!rc)
+		cxi_rgroup_delete_ac_entry(ac_entry_sub->rgroup,
+					   ac_entry_id);
+	cxi_cfg_drop_item_ref(item);
+}
+
+static void cxi_cfg_rgroup_ac_entry_free(struct config_item *item)
+{
+	struct cxi_cfg_rgroup_ac_entry *ac_entry;
+
+	ac_entry = container_of(item, struct cxi_cfg_rgroup_ac_entry,
+				group.cg_item);
+
+	kfree(ac_entry);
+}
+
+static struct configfs_group_operations cxi_cfg_rgroup_ac_entry_ops = {
+	.make_group     = cxi_cfg_rgroup_ac_entry_make_group,
+	.drop_item      = cxi_cfg_rgroup_ac_entry_drop_item
+};
+
+static struct configfs_item_operations cxi_cfg_rgroup_ac_entry_item_ops = {
+	.release     = cxi_cfg_rgroup_ac_entry_free,
+};
+
+static const struct config_item_type cxi_cfg_rgroup_ac_entry_type = {
+	.ct_group_ops   = &cxi_cfg_rgroup_ac_entry_ops,
+	.ct_item_ops    = &cxi_cfg_rgroup_ac_entry_item_ops,
+	.ct_owner       = THIS_MODULE,
+};
+
+static struct cxi_cfg_rgroup_res_type *to_cxi_cfg_rgroup_res_type(struct config_item *item)
+{
+	return container_of(to_config_group(item), struct cxi_cfg_rgroup_res_type, group);
+}
+
+static ssize_t cxi_cfg_rgroup_res_type_max_show(struct config_item *item,
+						char *page)
+{
+	struct cxi_cfg_rgroup_res_type *rgroup_res_type;
+	struct cxi_resource_entry *entry;
+	int rc;
+
+	rgroup_res_type = to_cxi_cfg_rgroup_res_type(item);
+	rc = cxi_rgroup_get_resource_entry(rgroup_res_type->rgroup,
+					   cxi_resource_str_to_type(rgroup_res_type->name),
+					   &entry);
+	if (rc != 0) {
+		pr_debug("Error: Resource entry not yet created for the resource type\n");
+		pr_debug("Error: Set the max file first and then the reserved file to create the resource type\n");
+		return -EINVAL;
+	}
+
+	return sprintf(page, "%ld\n", entry->limits.max);
+}
+
+static ssize_t cxi_cfg_rgroup_res_type_max_store(struct config_item *item,
+						 const char *page,
+						 size_t count)
+{
+	struct cxi_cfg_rgroup_res_type *rgroup_res_type;
+	struct cxi_resource_entry *entry;
+	int rc;
+
+	rgroup_res_type = to_cxi_cfg_rgroup_res_type(item);
+
+	rc = cxi_rgroup_get_resource_entry(rgroup_res_type->rgroup,
+					   cxi_resource_str_to_type(rgroup_res_type->name),
+					   &entry);
+	if (rc == 0) {
+		pr_debug("Error: Given resource type has already been added\n");
+		return -EINVAL;
+	}
+
+	rc = kstrtoint(page, 0, &rgroup_res_type->max);
+	if (rc)
+		return rc;
+
+	pr_debug("resource max value set to: %d\n", rgroup_res_type->max);
+
+	return count;
+}
+
+static ssize_t cxi_cfg_rgroup_res_type_reserved_show(struct config_item *item,
+						     char *page)
+{
+	int rc;
+	struct cxi_cfg_rgroup_res_type *rgroup_res_type;
+	struct cxi_resource_entry *entry;
+
+	rgroup_res_type = to_cxi_cfg_rgroup_res_type(item);
+
+	rc = cxi_rgroup_get_resource_entry(rgroup_res_type->rgroup,
+					   cxi_resource_str_to_type(rgroup_res_type->name),
+					   &entry);
+	if (rc != 0) {
+		pr_debug("Error: Resource entry not found for the resource type\n");
+		return -EINVAL;
+	}
+
+	return sprintf(page, "%ld\n", entry->limits.reserved);
+}
+
+static ssize_t cxi_cfg_rgroup_res_type_reserved_store(struct config_item *item,
+						      const char *page,
+						      size_t count)
+{
+	struct cxi_cfg_rgroup_res_type *rgroup_res_type;
+	int rc;
+	enum cxi_resource_type e_type;
+	struct cxi_resource_limits limits = {};
+
+	rgroup_res_type = to_cxi_cfg_rgroup_res_type(item);
+
+	rc = kstrtoint(page, 0, &rgroup_res_type->reserved);
+	if (rc)
+		return rc;
+
+	e_type = cxi_resource_str_to_type(rgroup_res_type->name);
+
+	limits.max = rgroup_res_type->max;
+	limits.reserved = rgroup_res_type->reserved;
+
+	rc = cxi_rgroup_add_resource(rgroup_res_type->rgroup, e_type, &limits);
+	if (rc)
+		return rc;
+
+	return count;
+}
+
+static ssize_t cxi_cfg_rgroup_res_type_in_use_show(struct config_item *item,
+						   char *page)
+{
+	struct cxi_cfg_rgroup_res_type *rgroup_res_type;
+	struct cxi_resource_entry *entry;
+	int rc;
+
+	rgroup_res_type = to_cxi_cfg_rgroup_res_type(item);
+
+	rc = cxi_rgroup_get_resource_entry(rgroup_res_type->rgroup,
+					   cxi_resource_str_to_type(rgroup_res_type->name),
+					   &entry);
+	if (rc != 0) {
+		pr_debug("Error: Given resource type has not yet been added\n");
+		return -EINVAL;
+	}
+
+	return sprintf(page, "%ld\n", entry->limits.in_use);
+}
+
+static void cxi_cfg_rgroup_res_type_free(struct config_item *item)
+{
+	kfree(container_of(item, struct cxi_cfg_rgroup_res_type, group.cg_item));
+}
+
+CONFIGFS_ATTR(cxi_cfg_rgroup_res_type_, reserved);
+CONFIGFS_ATTR(cxi_cfg_rgroup_res_type_, max);
+CONFIGFS_ATTR_RO(cxi_cfg_rgroup_res_type_, in_use);
+
+static struct configfs_attribute *cxi_cfg_rgroup_res_type_attrs[] = {
+	&cxi_cfg_rgroup_res_type_attr_reserved,
+	&cxi_cfg_rgroup_res_type_attr_max,
+	&cxi_cfg_rgroup_res_type_attr_in_use,
+	NULL
+};
+
+static struct configfs_item_operations cxi_cfg_rgroup_res_type_item_ops = {
+	.release     = cxi_cfg_rgroup_res_type_free,
+};
+
+static const struct config_item_type cxi_cfg_rgroup_res_type_type = {
+	.ct_attrs       = cxi_cfg_rgroup_res_type_attrs,
+	.ct_item_ops    = &cxi_cfg_rgroup_res_type_item_ops,
+	.ct_owner       = THIS_MODULE,
+};
+
+static struct cxi_cfg_rgroup_res_type *alloc_dev_rgroup_res_type(const char *name)
+{
+	struct cxi_cfg_rgroup_res_type *dev_dir;
+
+	dev_dir = kzalloc(sizeof(*dev_dir), GFP_KERNEL);
+	if (!dev_dir)
+		return NULL;
+
+	strscpy(dev_dir->name, name, sizeof(dev_dir->name));
+
+	config_group_init_type_name(&dev_dir->group,
+				    dev_dir->name,
+				    &cxi_cfg_rgroup_res_type_type);
+
+	return dev_dir;
+}
+
+static struct
+config_group *cxi_cfg_rgroup_res_make_group(struct config_group *group,
+					    const char *name)
+{
+	struct cxi_cfg_rgroup_res_type *res_type;
+	struct cxi_cfg_rgroup_res *res;
+	enum cxi_resource_type e_type;
+
+	e_type = cxi_resource_str_to_type(name);
+	if (e_type == CXI_RESOURCE_MAX) {
+		pr_debug("Unknown resource name %s\n", name);
+		return ERR_PTR(-EINVAL);
+	}
+
+	res_type = alloc_dev_rgroup_res_type(name);
+	if (!res_type) {
+		pr_debug("Failed to alloc memory for configfs resource types");
+		return ERR_PTR(-ENOMEM);
+	}
+
+	res = container_of(group, struct cxi_cfg_rgroup_res, group);
+	if (!res) {
+		pr_debug("No parent resource group found\n");
+		kfree(res_type);
+		return ERR_PTR(-EINVAL);
+	}
+
+	res_type->max = resource_max[e_type];
+	res_type->reserved = 0;
+	res_type->rgroup = res->rgroup;
+
+	return &res_type->group;
+}
+
+static void
+cxi_cfg_rgroup_res_drop_item(struct config_group *group,
+			     struct config_item *item)
+{
+	struct config_group *parent_group;
+	int rc;
+	struct cxi_cfg_rgroup *rgp;
+	struct cxi_cfg_rgroup_res_type *res_type;
+
+	parent_group = get_parent_config_group(group);
+
+	rgp = container_of(parent_group, struct cxi_cfg_rgroup, group);
+
+	res_type = container_of(to_config_group(item),
+				struct cxi_cfg_rgroup_res_type,
+				group);
+
+	/*
+	 * For accidental deletion of a configfs resource type directory which is
+	 * enabled. In the future a different approach will be taken to handle
+	 * accidental deletion by user
+	 */
+	if (cxi_rgroup_is_enabled(rgp->rgroup))
+		cxi_rgroup_disable(rgp->rgroup);
+
+	rc = cxi_rgroup_delete_resource(res_type->rgroup,
+					cxi_resource_str_to_type(item->ci_name));
+
+	pr_debug("Resource group resource deletion rc = %d\n", rc);
+	cxi_cfg_drop_item_ref(item);
+}
+
+static void cxi_cfg_rgroup_res_free(struct config_item *item)
+{
+	kfree(container_of(item, struct cxi_cfg_rgroup_res, group.cg_item));
+}
+
+static struct configfs_group_operations cxi_cfg_rgroup_res_ops = {
+	.make_group     = cxi_cfg_rgroup_res_make_group,
+	.drop_item      = cxi_cfg_rgroup_res_drop_item,
+};
+
+static struct configfs_item_operations cxi_cfg_rgroup_res_item_ops = {
+	.release     = cxi_cfg_rgroup_res_free,
+};
+
+static const struct config_item_type cxi_cfg_rgroup_res_type = {
+	.ct_group_ops   = &cxi_cfg_rgroup_res_ops,
+	.ct_item_ops    = &cxi_cfg_rgroup_res_item_ops,
+	.ct_owner       = THIS_MODULE,
+};
+
+static struct cxi_cfg_rgroup_attr *to_cxi_cfg_rgroup_attr(struct config_item *item)
+{
+	return container_of(to_config_group(item), struct cxi_cfg_rgroup_attr, group);
+}
+
+static ssize_t cxi_cfg_rgroup_attr_name_show(struct config_item *item,
+					     char *page)
+{
+	struct cxi_cfg_rgroup_attr *rgroup_attr;
+
+	rgroup_attr = to_cxi_cfg_rgroup_attr(item);
+
+	return sprintf(page, "%s\n", cxi_rgroup_name(rgroup_attr->rgroup));
+}
+
+static ssize_t cxi_cfg_rgroup_attr_cntr_pool_id_show(struct config_item *item,
+						     char *page)
+{
+	struct cxi_cfg_rgroup_attr *rgroup_attr;
+
+	rgroup_attr = to_cxi_cfg_rgroup_attr(item);
+
+	return sprintf(page, "%u\n",
+		       cxi_rgroup_cntr_pool_id(rgroup_attr->rgroup));
+}
+
+static ssize_t cxi_cfg_rgroup_attr_system_service_show(struct config_item *item,
+						       char *page)
+{
+	struct cxi_cfg_rgroup_attr *rgroup_attr;
+
+	rgroup_attr = to_cxi_cfg_rgroup_attr(item);
+
+	return scnprintf(page, PAGE_SIZE, "%s\n",
+			 cxi_rgroup_system_service(rgroup_attr->rgroup) ? "true" : "false");
+}
+
+static ssize_t cxi_cfg_rgroup_attr_lnis_per_rgid_show(struct config_item *item,
+						      char *page)
+{
+	struct cxi_cfg_rgroup_attr *rgroup_attr;
+
+	rgroup_attr = to_cxi_cfg_rgroup_attr(item);
+
+	return sprintf(page, "%d\n", cxi_rgroup_lnis_per_rgid(rgroup_attr->rgroup));
+}
+
+static void cxi_cfg_rgroup_attr_free(struct config_item *item)
+{
+	kfree(container_of(item, struct cxi_cfg_rgroup_attr, group.cg_item));
+}
+
+CONFIGFS_ATTR_RO(cxi_cfg_rgroup_attr_, name);
+CONFIGFS_ATTR_RO(cxi_cfg_rgroup_attr_, cntr_pool_id);
+CONFIGFS_ATTR_RO(cxi_cfg_rgroup_attr_, system_service);
+CONFIGFS_ATTR_RO(cxi_cfg_rgroup_attr_, lnis_per_rgid);
+
+static struct configfs_attribute *cxi_cfg_rgroup_attr_attrs[] = {
+	&cxi_cfg_rgroup_attr_attr_name,
+	&cxi_cfg_rgroup_attr_attr_cntr_pool_id,
+	&cxi_cfg_rgroup_attr_attr_system_service,
+	&cxi_cfg_rgroup_attr_attr_lnis_per_rgid,
+	NULL,
+};
+
+static struct configfs_item_operations cxi_cfg_rgroup_attr_item_ops = {
+	.release     = cxi_cfg_rgroup_attr_free,
+};
+
+static const struct config_item_type cxi_cfg_rgroup_attr_type = {
+	.ct_attrs       = cxi_cfg_rgroup_attr_attrs,
+	.ct_item_ops    = &cxi_cfg_rgroup_attr_item_ops,
+	.ct_owner       = THIS_MODULE,
+};
+
+static struct cxi_cfg_rgroup_state *to_cxi_cfg_rgroup_state(struct config_item *item)
+{
+	return container_of(to_config_group(item), struct cxi_cfg_rgroup_state, group);
+}
+
+static ssize_t cxi_cfg_rgroup_state_enabled_show(struct config_item *item,
+						 char *page)
+{
+	struct cxi_cfg_rgroup_state *rgroup_state;
+
+	rgroup_state = to_cxi_cfg_rgroup_state(item);
+
+	return scnprintf(page, PAGE_SIZE, "%s\n",
+			 cxi_rgroup_is_enabled(rgroup_state->rgroup) ? "true" : "false");
+}
+
+static ssize_t cxi_cfg_rgroup_state_enabled_store(struct config_item *item,
+						  const char *page,
+						  size_t count)
+{
+	struct cxi_cfg_rgroup_state *rgroup_state;
+	bool b_val;
+
+	if (kstrtobool(page, &b_val))
+		return -EINVAL;
+
+	rgroup_state = to_cxi_cfg_rgroup_state(item);
+
+	if (b_val) {
+		cxi_rgroup_enable(rgroup_state->rgroup);
+	} else {
+		cxi_rgroup_disable(rgroup_state->rgroup);
+	}
+
+	return count;
+}
+
+static ssize_t cxi_cfg_rgroup_state_refcount_show(struct config_item *item,
+						  char *page)
+{
+	struct cxi_cfg_rgroup_state *rgroup_state;
+
+	rgroup_state = to_cxi_cfg_rgroup_state(item);
+
+	return sprintf(page, "%d\n", cxi_rgroup_refcount(rgroup_state->rgroup));
+}
+
+static void cxi_cfg_rgroup_state_free(struct config_item *item)
+{
+	kfree(container_of(item, struct cxi_cfg_rgroup_state, group.cg_item));
+}
+
+CONFIGFS_ATTR(cxi_cfg_rgroup_state_, enabled);
+CONFIGFS_ATTR_RO(cxi_cfg_rgroup_state_, refcount);
+
+static struct configfs_attribute *cxi_cfg_rgroup_state_attrs[] = {
+	&cxi_cfg_rgroup_state_attr_enabled,
+	&cxi_cfg_rgroup_state_attr_refcount,
+	NULL
+};
+
+static struct configfs_item_operations cxi_cfg_rgroup_state_item_ops = {
+	.release     = cxi_cfg_rgroup_state_free,
+};
+
+static const struct config_item_type cxi_cfg_rgroup_state_type = {
+	.ct_attrs       = cxi_cfg_rgroup_state_attrs,
+	.ct_item_ops    = &cxi_cfg_rgroup_state_item_ops,
+	.ct_owner       = THIS_MODULE,
+};
+
+static struct cxi_cfg_rgroup_ac_entry *alloc_dev_rgroup_ac_entry(const char *name)
+{
+	struct cxi_cfg_rgroup_ac_entry *ac_entry_dir;
+
+	ac_entry_dir = kzalloc(sizeof(*ac_entry_dir),
+			       GFP_KERNEL);
+	if (!ac_entry_dir)
+		return NULL;
+
+	strscpy(ac_entry_dir->name, name, sizeof(ac_entry_dir->name));
+
+	config_group_init_type_name(&ac_entry_dir->group,
+				    ac_entry_dir->name,
+				    &cxi_cfg_rgroup_ac_entry_type);
+
+	return ac_entry_dir;
+}
+
+static struct cxi_cfg_rgroup_res *alloc_dev_rgroup_res(const char *name)
+{
+	struct cxi_cfg_rgroup_res *p_res;
+
+	p_res = kzalloc(sizeof(*p_res), GFP_KERNEL);
+	if (!p_res)
+		return NULL;
+
+	strscpy(p_res->name, name, sizeof(p_res->name));
+
+	config_group_init_type_name(&p_res->group,
+				    p_res->name,
+				    &cxi_cfg_rgroup_res_type);
+
+	return p_res;
+}
+
+static struct cxi_cfg_rgroup_state *alloc_dev_rgroup_state(const char *name)
+{
+	struct cxi_cfg_rgroup_state *rgp_st;
+
+	rgp_st = kzalloc(sizeof(*rgp_st), GFP_KERNEL);
+	if (!rgp_st)
+		return NULL;
+
+	strscpy(rgp_st->name, name, sizeof(rgp_st->name));
+
+	config_group_init_type_name(&rgp_st->group,
+				    rgp_st->name,
+				    &cxi_cfg_rgroup_state_type);
+
+	return rgp_st;
+}
+
+static struct cxi_cfg_rgroup_attr *alloc_dev_rgroup_attr(const char *name)
+{
+	struct cxi_cfg_rgroup_attr *p_attr;
+
+	p_attr = kzalloc(sizeof(*p_attr), GFP_KERNEL);
+	if (!p_attr)
+		return NULL;
+
+	strscpy(p_attr->name, name, sizeof(p_attr->name));
+
+	config_group_init_type_name(&p_attr->group,
+				    p_attr->name,
+				    &cxi_cfg_rgroup_attr_type);
+
+	return p_attr;
+}
+
+static struct
+config_group *cxi_cfg_rgroup_make_group(struct config_group *group,
+					const char *name)
+{
+	struct cxi_cfg_rgroup *rgp = container_of(group,
+						  struct cxi_cfg_rgroup,
+						  group);
+	struct cxi_cfg_rgroup_state *rgp_state;
+	struct cxi_cfg_rgroup_attr *rgp_attr;
+	struct cxi_cfg_rgroup_ac_entry *ac_entry;
+	struct cxi_cfg_rgroup_res *rgp_res;
+
+	if (strncmp(name, "resources", sizeof("resources") - 1) == 0) {
+		rgp_res = alloc_dev_rgroup_res("resources");
+		if (!rgp_res) {
+			pr_debug("unable to alloc rgroup resources");
+			return ERR_PTR(-EINVAL);
+		}
+		rgp_res->rgroup = rgp->rgroup;
+		rgp->rgp_res = rgp_res;
+		rgp->rgp_res->cdev = rgp->cdev;
+
+		return &rgp->rgp_res->group;
+	}
+
+	if (strncmp(name, "attr", sizeof("attr") - 1) == 0) {
+		rgp_attr = alloc_dev_rgroup_attr("attr");
+		if (!rgp_attr) {
+			pr_debug("unable to alloc rgroup attr");
+			return ERR_PTR(-EINVAL);
+		}
+
+		rgp_attr->rgroup = rgp->rgroup;
+		rgp->rgp_attr = rgp_attr;
+		rgp->rgp_attr->cdev = rgp->cdev;
+
+		return &rgp->rgp_attr->group;
+	}
+
+	if (strncmp(name, "state", sizeof("state") - 1) == 0) {
+		rgp_state = alloc_dev_rgroup_state("state");
+		if (!rgp_state) {
+			pr_debug("unable to alloc rgroup state");
+			return ERR_PTR(-EINVAL);
+		}
+		rgp_state->rgroup = rgp->rgroup;
+		rgp->rgp_state = rgp_state;
+		rgp->rgp_state->cdev = rgp->cdev;
+
+		return &rgp->rgp_state->group;
+	}
+
+	if (strncmp(name, "ac-entry", sizeof("ac-entry") - 1) == 0) {
+		ac_entry = alloc_dev_rgroup_ac_entry("ac-entry");
+		if (!ac_entry) {
+			pr_debug("unable to alloc rgroup ac-entry");
+			return ERR_PTR(-EINVAL);
+		}
+		ac_entry->rgroup = rgp->rgroup;
+		rgp->ac_entry = ac_entry;
+
+		return &rgp->ac_entry->group;
+	}
+
+	return ERR_PTR(-EINVAL);
+}
+
+static void
+cxi_cfg_rgroup_drop_item(struct config_group *group,
+			 struct config_item *item)
+{
+	cxi_cfg_drop_item_ref(item);
+}
+
+static void cxi_cfg_rgroup_free(struct config_item *item)
+{
+	kfree(container_of(item, struct cxi_cfg_rgroup, group.cg_item));
+}
+
+static struct cxi_cfg_rgroup *to_cxi_cfg_rgroup(struct config_item *item)
+{
+	return container_of(to_config_group(item), struct cxi_cfg_rgroup, group);
+}
+
+static ssize_t cxi_cfg_rgroup_id_show(struct config_item *item,
+				      char *page)
+{
+	struct cxi_cfg_rgroup *rgp = to_cxi_cfg_rgroup(item);
+
+	return scnprintf(page, PAGE_SIZE, "%d\n", rgp->rgroup->id);
+}
+
+CONFIGFS_ATTR_RO(cxi_cfg_rgroup_, id);
+
+static struct configfs_attribute *cxi_cfg_rgroup_attrs[] = {
+	&cxi_cfg_rgroup_attr_id,
+	NULL,
+};
+
+static struct configfs_group_operations cxi_cfg_rgroup_ops = {
+	.make_group    = cxi_cfg_rgroup_make_group,
+	.drop_item     = cxi_cfg_rgroup_drop_item
+};
+
+static struct configfs_item_operations cxi_cfg_rgroup_item_ops = {
+	.release     = cxi_cfg_rgroup_free,
+};
+
+static const struct config_item_type cxi_cfg_rgroup_type = {
+	.ct_group_ops   = &cxi_cfg_rgroup_ops,
+	.ct_attrs       = cxi_cfg_rgroup_attrs,
+	.ct_item_ops    = &cxi_cfg_rgroup_item_ops,
+	.ct_owner       = THIS_MODULE,
+};
+
+static struct cxi_cfg_rgroup *alloc_dev_rgroup(const char *name)
+{
+	struct cxi_cfg_rgroup *rgp;
+
+	rgp = kzalloc(sizeof(*rgp), GFP_KERNEL);
+	if (!rgp)
+		return NULL;
+
+	strscpy(rgp->name, name, sizeof(rgp->name));
+
+	config_group_init_type_name(&rgp->group,
+				    rgp->name,
+				    &cxi_cfg_rgroup_type);
+
+	return rgp;
+}
+
+static struct
+config_group *cxi_cfg_rgroup_dir_make_group(struct config_group *group,
+					    const char *name)
+{
+	struct cxi_cfg_rgroup_dir *dev_rgp;
+	struct cxi_cfg_rgroup *rgp;
+	struct cxi_rgroup *rgroup;
+	struct cxi_rgroup_attr attr = {
+		.cntr_pool_id = 0,
+		.name = {'\0'},
+		.system_service = false,
+		.lnis_per_rgid = CXI_DEFAULT_LNIS_PER_RGID
+	};
+
+	if (strlen(name) > CONFIGFS_DIR_LEN - 1)
+		return ERR_PTR(-EINVAL);
+
+	dev_rgp = container_of(group, struct cxi_cfg_rgroup_dir, group);
+	rgp = alloc_dev_rgroup(name);
+	if (!rgp) {
+		pr_debug("Failed to alloc memory for configfs rgroup dir");
+		return ERR_PTR(-ENOMEM);
+	}
+
+	rgp->cdev = dev_rgp->cdev;
+	strscpy(attr.name, name, sizeof(attr.name));
+	rgroup = cxi_dev_alloc_rgroup(dev_rgp->cdev,
+				      &attr);
+	if (IS_ERR(rgroup)) {
+		kfree(rgp);
+		return ERR_PTR(PTR_ERR(rgroup));
+	}
+	rgp->rgroup = rgroup;
+
+	return &rgp->group;
+}
+
+static void
+cxi_cfg_rgroup_dir_drop_item(struct config_group *group,
+			     struct config_item *item)
+{
+	struct cxi_cfg_rgroup *rgp;
+
+	rgp = container_of(item, struct cxi_cfg_rgroup, group.cg_item);
+
+	/*
+	 * For accidental deletion of resource group directory
+	 * by configfs user. In the future we will employ a
+	 * different approach to handle accidental deletion.
+	 */
+	cxi_rgroup_dec_refcount(rgp->rgroup);
+
+	cxi_cfg_drop_item_ref(item);
+}
+
+static void cxi_cfg_rgroup_dir_free(struct config_item *item)
+{
+	struct cxi_cfg_rgroup_dir *rgp_dir;
+
+	rgp_dir = container_of(item, struct cxi_cfg_rgroup_dir,
+			       group.cg_item);
+	kfree(rgp_dir);
+}
+
+static struct configfs_group_operations cxi_cfg_rgroup_dir_ops = {
+	.make_group     = cxi_cfg_rgroup_dir_make_group,
+	.drop_item      = cxi_cfg_rgroup_dir_drop_item,
+};
+
+static struct configfs_item_operations cxi_cfg_rgroup_dir_item_ops = {
+	.release     = cxi_cfg_rgroup_dir_free,
+};
+
+static const struct config_item_type cxi_cfg_rgroup_dir_type = {
+	.ct_group_ops   = &cxi_cfg_rgroup_dir_ops,
+	.ct_item_ops    = &cxi_cfg_rgroup_dir_item_ops,
+	.ct_owner       = THIS_MODULE,
+};
+
+static void cxi_cfg_group_free(struct config_item *item)
+{
+	struct cxi_cfg_group_item *grp_dir;
+
+	grp_dir = container_of(item, struct cxi_cfg_group_item,
+			       group.cg_item);
+	kfree(grp_dir);
+}
+
+static struct configfs_item_operations cxi_cfg_group_item_ops = {
+	.release     = cxi_cfg_group_free,
+};
+
+static const struct config_item_type cxi_cfg_group_type = {
+	.ct_item_ops    = &cxi_cfg_group_item_ops,
+	.ct_owner       = THIS_MODULE,
+};
+
+static struct configfs_subsystem cxi_cfg_group_subsys = {
+	.su_group = {
+		.cg_item = {
+			.ci_namebuf = "cxi",
+			.ci_type = &cxi_cfg_group_type,
+		},
+	},
+};
+
+static struct cxi_cfg_group_item *alloc_dev_subdir(const char *name)
+{
+	struct cxi_cfg_group_item *dev_dir;
+
+	dev_dir = kzalloc(sizeof(*dev_dir), GFP_KERNEL);
+	if (!dev_dir)
+		return NULL;
+
+	strscpy(dev_dir->name, name, sizeof(dev_dir->name));
+
+	config_group_init_type_name(&dev_dir->group,
+				    dev_dir->name,
+				    &cxi_cfg_group_type);
+
+	return dev_dir;
+}
+
+static struct cxi_cfg_rgroup_dir *alloc_dev_attr1(const char *name)
+{
+	struct cxi_cfg_rgroup_dir *dev_rgp;
+
+	dev_rgp = kzalloc(sizeof(*dev_rgp), GFP_KERNEL);
+	if (!dev_rgp)
+		return NULL;
+
+	strscpy(dev_rgp->name, name, sizeof(dev_rgp->name));
+
+	config_group_init_type_name(&dev_rgp->group,
+				    dev_rgp->name,
+				    &cxi_cfg_rgroup_dir_type);
+
+	return dev_rgp;
+}
+
+static struct cxi_cfg_tx_prof_ac_entry_sub *to_cxi_cfg_tx_prof_ac_entry_sub(struct config_item *item)
+{
+	return container_of(to_config_group(item), struct cxi_cfg_tx_prof_ac_entry_sub, group);
+}
+
+static ssize_t cxi_cfg_tx_prof_ac_entry_sub_type_show(struct config_item *item,
+						      char *page)
+{
+	struct cxi_cfg_tx_prof_ac_entry_sub *tx_prof_ac_entry_sub;
+	int rc;
+	enum cxi_ac_type ac_type;
+	union cxi_ac_data ac_data;
+
+	tx_prof_ac_entry_sub = to_cxi_cfg_tx_prof_ac_entry_sub(item);
+
+	rc = cxi_tx_profile_get_ac_entry_data(tx_prof_ac_entry_sub->tx_profile,
+					      tx_prof_ac_entry_sub->id,
+					      &ac_type,
+					      &ac_data);
+	if (rc)
+		return rc;
+
+	return sprintf(page, "%d\n", ac_type);
+}
+
+static ssize_t cxi_cfg_tx_prof_ac_entry_sub_type_store(struct config_item *item,
+						       const char *page,
+						       size_t count)
+{
+	struct cxi_cfg_tx_prof_ac_entry_sub *ac_entry_sub;
+	int rc;
+	enum cxi_ac_type ac_type_val;
+	uid_t uid;
+	gid_t gid;
+	unsigned int netns;
+	unsigned int ac_entry_id;
+
+	ac_entry_sub = to_cxi_cfg_tx_prof_ac_entry_sub(item);
+	if (!ac_entry_sub->tx_profile) {
+		pr_debug("Unable to get tx profile reference\n");
+		return -EINVAL;
+	}
+
+	rc = kstrtouint(page, 0, (unsigned int *)&ac_type_val);
+	if (rc)
+		return rc;
+
+	if (ac_type_val == CXI_AC_UID)
+		uid = ac_entry_sub->ac_data.uid;
+	else if (ac_type_val == CXI_AC_GID)
+		gid = ac_entry_sub->ac_data.gid;
+	else if (ac_type_val == CXI_AC_NETNS)
+		netns = ac_entry_sub->ac_data.netns;
+	else if (ac_type_val == CXI_AC_OPEN)
+		pr_debug("Setting type to CXI_AC_OPEN\n");
+	else
+		return -EINVAL;
+
+	rc = cxi_tx_profile_add_ac_entry(ac_entry_sub->tx_profile,
+					 ac_type_val,
+					 uid,
+					 gid,
+					 netns,
+					 &ac_entry_id);
+	if (rc < 0) {
+		pr_debug("Unable to add ac entry to tx profile: err val %d\n", rc);
+		return rc;
+	}
+
+	ac_entry_sub->id = ac_entry_id;
+	ac_entry_sub->ac_type = ac_type_val;
+
+	return count;
+}
+
+static ssize_t cxi_cfg_tx_prof_ac_entry_sub_data_show(struct config_item *item,
+						      char *page)
+{
+	struct cxi_cfg_tx_prof_ac_entry_sub *tx_prof_ac_entry_sub;
+	enum cxi_ac_type ac_type;
+	union cxi_ac_data ac_data;
+	int rc;
+
+	tx_prof_ac_entry_sub = to_cxi_cfg_tx_prof_ac_entry_sub(item);
+
+	rc = cxi_tx_profile_get_ac_entry_data(tx_prof_ac_entry_sub->tx_profile,
+					      tx_prof_ac_entry_sub->id,
+					      &ac_type,
+					      &ac_data);
+	if (rc)
+		return rc;
+
+	if (ac_type == CXI_AC_UID)
+		return sprintf(page, "%d\n", ac_data.uid);
+	else if (ac_type == CXI_AC_GID)
+		return sprintf(page, "%d\n", ac_data.gid);
+	else if (ac_type == CXI_AC_NETNS)
+		return sprintf(page, "%d\n", ac_data.netns);
+	else if (ac_type == CXI_AC_OPEN)
+		return sprintf(page, "%d\n", CXI_AC_OPEN);
+
+	return -EINVAL;
+}
+
+static ssize_t cxi_cfg_tx_prof_ac_entry_sub_data_store(struct config_item *item,
+						       const char *page,
+						       size_t count)
+{
+	struct cxi_cfg_tx_prof_ac_entry_sub *ac_entry_sub;
+	int rc;
+	unsigned int ac_data_val;
+
+	ac_entry_sub = to_cxi_cfg_tx_prof_ac_entry_sub(item);
+
+	rc = kstrtouint(page, 0, &ac_data_val);
+	if (rc)
+		return rc;
+
+	if (ac_entry_sub->ac_type == CXI_AC_UID) {
+		ac_entry_sub->ac_data.uid = ac_data_val;
+		return count;
+	} else if (ac_entry_sub->ac_type == CXI_AC_GID) {
+		ac_entry_sub->ac_data.gid = ac_data_val;
+		return count;
+	} else if (ac_entry_sub->ac_type == CXI_AC_NETNS) {
+		ac_entry_sub->ac_data.netns = ac_data_val;
+		return count;
+	}
+
+	return -EINVAL;
+}
+
+static void cxi_cfg_tx_prof_ac_entry_sub_free(struct config_item *item)
+{
+	kfree(container_of(item, struct cxi_cfg_tx_prof_ac_entry_sub, group.cg_item));
+}
+
+CONFIGFS_ATTR(cxi_cfg_tx_prof_ac_entry_sub_, type);
+CONFIGFS_ATTR(cxi_cfg_tx_prof_ac_entry_sub_, data);
+
+static struct configfs_attribute *cxi_cfg_tx_prof_ac_entry_sub_attrs[] = {
+	&cxi_cfg_tx_prof_ac_entry_sub_attr_type,
+	&cxi_cfg_tx_prof_ac_entry_sub_attr_data,
+	NULL,
+};
+
+static struct configfs_item_operations cxi_cfg_tx_prof_ac_entry_sub_item_ops = {
+	.release     = cxi_cfg_tx_prof_ac_entry_sub_free,
+};
+
+static const struct config_item_type cxi_cfg_tx_prof_ac_entry_sub_type = {
+	.ct_attrs       = cxi_cfg_tx_prof_ac_entry_sub_attrs,
+	.ct_item_ops    = &cxi_cfg_tx_prof_ac_entry_sub_item_ops,
+	.ct_owner       = THIS_MODULE,
+};
+
+static struct cxi_cfg_tx_prof_ac_entry_sub *alloc_dev_tx_prof_ac_entry_sub(const char *name)
+{
+	struct cxi_cfg_tx_prof_ac_entry_sub *tx_prof_ac_entry_sub;
+
+	tx_prof_ac_entry_sub = kzalloc(sizeof(*tx_prof_ac_entry_sub), GFP_KERNEL);
+	if (!tx_prof_ac_entry_sub)
+		return NULL;
+
+	strscpy(tx_prof_ac_entry_sub->name, name, sizeof(tx_prof_ac_entry_sub->name));
+
+	config_group_init_type_name(&tx_prof_ac_entry_sub->group,
+				    tx_prof_ac_entry_sub->name,
+				    &cxi_cfg_tx_prof_ac_entry_sub_type);
+
+	return tx_prof_ac_entry_sub;
+}
+
+static struct
+config_group *cxi_cfg_tx_prof_ac_entry_make_group(struct config_group *group,
+						  const char *name)
+{
+	struct cxi_cfg_tx_prof_ac_entry *tx_prof_ac_entry;
+	struct cxi_cfg_tx_prof_ac_entry_sub *tx_prof_ac_entry_sub;
+
+	if (strlen(name) > CONFIGFS_DIR_LEN - 1)
+		return ERR_PTR(-EINVAL);
+
+	tx_prof_ac_entry = container_of(group, struct cxi_cfg_tx_prof_ac_entry, group);
+
+	tx_prof_ac_entry_sub = alloc_dev_tx_prof_ac_entry_sub(name);
+	if (!tx_prof_ac_entry_sub) {
+		pr_debug("Memory allocation failed for ac entry group\n");
+		return ERR_PTR(-ENOMEM);
+	}
+
+	tx_prof_ac_entry_sub->ac_type = CXI_AC_UID;
+	tx_prof_ac_entry_sub->ac_data.uid = 0;
+	tx_prof_ac_entry_sub->tx_profile = tx_prof_ac_entry->tx_profile;
+
+	return &tx_prof_ac_entry_sub->group;
+}
+
+static void
+cxi_cfg_tx_prof_ac_entry_drop_item(struct config_group *group,
+				   struct config_item *item)
+{
+	struct cxi_cfg_tx_prof_ac_entry_sub *tx_prof_ac_entry_sub;
+	int rc;
+	unsigned int ac_entry_id;
+
+	tx_prof_ac_entry_sub = container_of(item, struct cxi_cfg_tx_prof_ac_entry_sub, group.cg_item);
+
+	if (tx_prof_ac_entry_sub->ac_type == CXI_AC_UID) {
+		rc = cxi_tx_profile_get_ac_entry_id_by_data(tx_prof_ac_entry_sub->tx_profile,
+							    CXI_AC_UID,
+							    &tx_prof_ac_entry_sub->ac_data,
+							    &ac_entry_id);
+
+		pr_debug("Getting an entry info type uid rc = %d\n", rc);
+	} else if (tx_prof_ac_entry_sub->ac_type == CXI_AC_GID) {
+		rc = cxi_tx_profile_get_ac_entry_id_by_data(tx_prof_ac_entry_sub->tx_profile,
+							    CXI_AC_GID,
+							    &tx_prof_ac_entry_sub->ac_data,
+							    &ac_entry_id);
+
+		pr_debug("Getting an entry info type gid rc = %d\n", rc);
+	} else if (tx_prof_ac_entry_sub->ac_type == CXI_AC_NETNS) {
+		rc = cxi_tx_profile_get_ac_entry_id_by_data(tx_prof_ac_entry_sub->tx_profile,
+							    CXI_AC_NETNS,
+							    &tx_prof_ac_entry_sub->ac_data,
+							    &ac_entry_id);
+
+		pr_debug("Getting an entry info type netns rc = %d\n", rc);
+	} else {
+		rc = cxi_tx_profile_get_ac_entry_id_by_data(tx_prof_ac_entry_sub->tx_profile,
+							    CXI_AC_OPEN,
+							    NULL,
+							    &ac_entry_id);
+		pr_debug("Getting an entry info type open rc = %d\n", rc);
+	}
+
+	if (!rc)
+		cxi_tx_profile_remove_ac_entry(tx_prof_ac_entry_sub->tx_profile,
+					       ac_entry_id);
+	cxi_cfg_drop_item_ref(item);
+}
+
+static void cxi_cfg_tx_prof_ac_entry_free(struct config_item *item)
+{
+	kfree(container_of(item, struct cxi_cfg_tx_prof_ac_entry, group.cg_item));
+}
+
+static struct configfs_group_operations cxi_cfg_tx_prof_ac_entry_ops = {
+	.make_group     = cxi_cfg_tx_prof_ac_entry_make_group,
+	.drop_item      = cxi_cfg_tx_prof_ac_entry_drop_item,
+};
+
+static struct configfs_item_operations cxi_cfg_tx_prof_ac_entry_item_ops = {
+	.release     = cxi_cfg_tx_prof_ac_entry_free,
+};
+
+static const struct config_item_type cxi_cfg_tx_prof_ac_entry_type = {
+	.ct_group_ops   = &cxi_cfg_tx_prof_ac_entry_ops,
+	.ct_item_ops    = &cxi_cfg_tx_prof_ac_entry_item_ops,
+	.ct_owner       = THIS_MODULE,
+};
+
+static struct cxi_cfg_tx_prof_state *to_cxi_cfg_tx_prof_state(struct config_item *item)
+{
+	return container_of(to_config_group(item), struct cxi_cfg_tx_prof_state, group);
+}
+
+static ssize_t cxi_cfg_tx_prof_state_enabled_show(struct config_item *item,
+						  char *page)
+{
+	struct cxi_cfg_tx_prof_state *tx_prof_state;
+	struct cxi_tx_attr tx_attr;
+	struct cxi_rxtx_profile_state state;
+	int rc;
+
+	tx_prof_state = to_cxi_cfg_tx_prof_state(item);
+
+	rc = cxi_tx_profile_get_info(tx_prof_state->cdev,
+				     tx_prof_state->tx_profile,
+				     &tx_attr,
+				     &state);
+	if (rc < 0) {
+		pr_debug("Unable to get tx-profile info rc = %d\n", rc);
+		return rc;
+	}
+
+	return scnprintf(page, PAGE_SIZE, "%s\n", state.enable ? "true" : "false");
+}
+
+static ssize_t cxi_cfg_tx_prof_state_enabled_store(struct config_item *item,
+						   const char *page,
+						   size_t count)
+{
+	struct cxi_cfg_tx_prof_state *tx_prof_state;
+	int rc;
+	bool b_val;
+
+	if (kstrtobool(page, &b_val))
+		return -EINVAL;
+
+	tx_prof_state = to_cxi_cfg_tx_prof_state(item);
+
+	if (b_val) {
+		rc = cxi_tx_profile_enable(tx_prof_state->cdev,
+					   tx_prof_state->tx_profile);
+		if (rc)
+			return rc;
+	} else {
+		cxi_tx_profile_disable(tx_prof_state->cdev,
+				       tx_prof_state->tx_profile);
+	}
+
+	return count;
+}
+
+static ssize_t cxi_cfg_tx_prof_state_refcount_show(struct config_item *item,
+						   char *page)
+{
+	struct cxi_cfg_tx_prof_state *tx_prof_state;
+	struct cxi_tx_attr tx_attr;
+	struct cxi_rxtx_profile_state state;
+	int rc;
+
+	tx_prof_state = to_cxi_cfg_tx_prof_state(item);
+
+	rc = cxi_tx_profile_get_info(tx_prof_state->cdev,
+				     tx_prof_state->tx_profile,
+				     &tx_attr,
+				     &state);
+	if (rc < 0) {
+		pr_debug("Unable to get rx-profile info rc = %d\n", rc);
+		return rc;
+	}
+
+	return sprintf(page, "%d\n", refcount_read(&state.refcount));
+}
+
+static void cxi_cfg_tx_prof_state_free(struct config_item *item)
+{
+	kfree(container_of(item, struct cxi_cfg_tx_prof_state, group.cg_item));
+}
+
+CONFIGFS_ATTR(cxi_cfg_tx_prof_state_, enabled);
+CONFIGFS_ATTR_RO(cxi_cfg_tx_prof_state_, refcount);
+
+static struct configfs_attribute *cxi_cfg_tx_prof_state_attrs[] = {
+	&cxi_cfg_tx_prof_state_attr_enabled,
+	&cxi_cfg_tx_prof_state_attr_refcount,
+	NULL
+};
+
+static struct configfs_item_operations cxi_cfg_tx_prof_state_item_ops = {
+	.release     = cxi_cfg_tx_prof_state_free,
+};
+
+static const struct config_item_type cxi_cfg_tx_prof_state_type = {
+	.ct_attrs       = cxi_cfg_tx_prof_state_attrs,
+	.ct_item_ops    = &cxi_cfg_tx_prof_state_item_ops,
+	.ct_owner       = THIS_MODULE,
+};
+
+static struct cxi_cfg_tx_prof_state *alloc_dev_tx_prof_state(const char *name)
+{
+	struct cxi_cfg_tx_prof_state *tx_prof_state;
+
+	tx_prof_state = kzalloc(sizeof(*tx_prof_state), GFP_KERNEL);
+	if (!tx_prof_state)
+		return NULL;
+
+	strscpy(tx_prof_state->name, name, sizeof(tx_prof_state->name));
+
+	config_group_init_type_name(&tx_prof_state->group,
+				    tx_prof_state->name,
+				    &cxi_cfg_tx_prof_state_type);
+	return tx_prof_state;
+}
+
+static struct cxi_cfg_tx_prof_attr *to_cxi_cfg_tx_prof_attr(struct config_item *item)
+{
+	return container_of(to_config_group(item), struct cxi_cfg_tx_prof_attr, group);
+}
+
+static ssize_t cxi_cfg_tx_prof_attr_name_show(struct config_item *item,
+					      char *page)
+{
+	struct cxi_cfg_tx_prof_attr *tx_prof_attr;
+
+	tx_prof_attr = to_cxi_cfg_tx_prof_attr(item);
+
+	return scnprintf(page, PAGE_SIZE, "%s\n",
+			 tx_prof_attr->tx_profile->profile_common.vni_attr.name);
+}
+
+static ssize_t cxi_cfg_tx_prof_attr_match_show(struct config_item *item,
+					       char *page)
+{
+	struct cxi_cfg_tx_prof_attr *tx_prof_attr;
+	struct cxi_tx_attr tx_attr;
+	struct cxi_rxtx_profile_state state;
+	int rc;
+
+	tx_prof_attr = to_cxi_cfg_tx_prof_attr(item);
+
+	rc = cxi_tx_profile_get_info(tx_prof_attr->cdev,
+				     tx_prof_attr->tx_profile,
+				     &tx_attr,
+				     &state);
+	if (rc < 0)
+		return rc;
+
+	return scnprintf(page, PAGE_SIZE, "%d\n", tx_attr.vni_attr.match);
+}
+
+static ssize_t cxi_cfg_tx_prof_attr_match_store(struct config_item *item,
+						const char *page,
+						size_t count)
+{
+	struct cxi_cfg_tx_prof_attr *tx_prof_attr;
+	int rc;
+	struct cxi_tx_attr tx_attr = {};
+
+	tx_prof_attr = to_cxi_cfg_tx_prof_attr(item);
+
+	rc = kstrtou16(page, 0, &tx_prof_attr->match);
+	if (rc)
+		return rc;
+
+	tx_attr.vni_attr.match = tx_prof_attr->match;
+	tx_attr.vni_attr.ignore = tx_prof_attr->ignore;
+
+	strscpy(tx_attr.vni_attr.name,
+		tx_prof_attr->tx_profile->profile_common.vni_attr.name,
+		sizeof(tx_attr.vni_attr.name));
+
+	rc = cxi_dev_set_tx_profile_attr(tx_prof_attr->cdev,
+					 tx_prof_attr->tx_profile,
+					 &tx_attr);
+	if (rc)
+		return rc;
+
+	return count;
+}
+
+static ssize_t cxi_cfg_tx_prof_attr_ignore_show(struct config_item *item,
+						char *page)
+{
+	struct cxi_cfg_tx_prof_attr *tx_prof_attr;
+	int rc;
+	struct cxi_tx_attr tx_attr;
+	struct cxi_rxtx_profile_state state;
+
+	tx_prof_attr = to_cxi_cfg_tx_prof_attr(item);
+
+	rc = cxi_tx_profile_get_info(tx_prof_attr->cdev,
+				     tx_prof_attr->tx_profile,
+				     &tx_attr,
+				     &state);
+	if (rc < 0) {
+		pr_debug("Unable to get rx-profile info rc = %d\n", rc);
+		return rc;
+	}
+
+	return scnprintf(page, PAGE_SIZE, "%d\n", tx_attr.vni_attr.ignore);
+}
+
+static ssize_t cxi_cfg_tx_prof_attr_ignore_store(struct config_item *item,
+						 const char *page,
+						 size_t count)
+{
+	struct cxi_cfg_tx_prof_attr *tx_prof_attr;
+	struct cxi_rxtx_profile_state state;
+	struct cxi_tx_attr tx_attr;
+	u16 ignore;
+	int rc;
+
+	tx_prof_attr = to_cxi_cfg_tx_prof_attr(item);
+	rc = kstrtou16(page, 0, &ignore);
+	if (rc)
+		return rc;
+
+	rc = cxi_tx_profile_get_info(tx_prof_attr->cdev,
+				     tx_prof_attr->tx_profile, &tx_attr, &state);
+	if (rc < 0)
+		return rc;
+	tx_attr.vni_attr.ignore = ignore;
+	rc = cxi_dev_set_tx_profile_attr(tx_prof_attr->cdev,
+					 tx_prof_attr->tx_profile, &tx_attr);
+	if (rc)
+		return rc;
+	tx_prof_attr->ignore = ignore;
+	return count;
+}
+
+static ssize_t cxi_cfg_tx_prof_attr_exclusive_cp_show(struct config_item *item,
+						      char *page)
+{
+	struct cxi_cfg_tx_prof_attr *tx_prof_attr;
+
+	tx_prof_attr = to_cxi_cfg_tx_prof_attr(item);
+
+	return scnprintf(page, PAGE_SIZE, "%s\n",
+			 cxi_tx_profile_exclusive_cp(tx_prof_attr->tx_profile) ? "true" : "false");
+}
+
+static ssize_t cxi_cfg_tx_prof_attr_exclusive_cp_store(struct config_item *item,
+						       const char *page,
+						       size_t count)
+{
+	struct cxi_cfg_tx_prof_attr *tx_prof_attr;
+	bool cp_val;
+	int rc;
+
+	if (kstrtobool(page, &cp_val))
+		return -EINVAL;
+
+	tx_prof_attr = to_cxi_cfg_tx_prof_attr(item);
+
+	rc = cxi_tx_profile_set_exclusive_cp(tx_prof_attr->tx_profile,
+					     cp_val);
+	if (rc)
+		return rc;
+
+	return count;
+}
+
+static void cxi_cfg_tx_prof_attr_free(struct config_item *item)
+{
+	kfree(container_of(item, struct cxi_cfg_tx_prof_attr, group.cg_item));
+}
+
+CONFIGFS_ATTR(cxi_cfg_tx_prof_attr_, ignore);
+CONFIGFS_ATTR(cxi_cfg_tx_prof_attr_, match);
+CONFIGFS_ATTR(cxi_cfg_tx_prof_attr_, exclusive_cp);
+CONFIGFS_ATTR_RO(cxi_cfg_tx_prof_attr_, name);
+
+static struct configfs_attribute *cxi_cfg_tx_prof_attr_attrs[] = {
+	&cxi_cfg_tx_prof_attr_attr_name,
+	&cxi_cfg_tx_prof_attr_attr_match,
+	&cxi_cfg_tx_prof_attr_attr_ignore,
+	&cxi_cfg_tx_prof_attr_attr_exclusive_cp,
+	NULL
+};
+
+static struct configfs_item_operations cxi_cfg_tx_prof_attr_item_ops = {
+	.release     = cxi_cfg_tx_prof_attr_free,
+};
+
+static const struct config_item_type cxi_cfg_tx_prof_attr_type = {
+	.ct_attrs       = cxi_cfg_tx_prof_attr_attrs,
+	.ct_item_ops    = &cxi_cfg_tx_prof_attr_item_ops,
+	.ct_owner       = THIS_MODULE,
+};
+
+static struct cxi_cfg_tx_prof_tc *to_cxi_cfg_tx_prof_tc(struct config_item *item)
+{
+	return container_of(to_config_group(item), struct cxi_cfg_tx_prof_tc, group);
+}
+
+static void set_tc_bool_type(unsigned int tc_type,
+			     struct cxi_cfg_tx_prof_tc *tx_prof_tc,
+			     bool tc_bool)
+{
+	switch (tc_type) {
+	case CXI_TC_BEST_EFFORT:
+		tx_prof_tc->best_effort = tc_bool;
+		break;
+	case CXI_TC_DEDICATED_ACCESS:
+		tx_prof_tc->dedicated = tc_bool;
+		break;
+	case CXI_TC_LOW_LATENCY:
+		tx_prof_tc->low_latency = tc_bool;
+		break;
+	case CXI_TC_BULK_DATA:
+		tx_prof_tc->bulk_data = tc_bool;
+		break;
+	case CXI_TC_ETH:
+		tx_prof_tc->eth = tc_bool;
+		break;
+	}
+
+	cxi_tx_profile_set_tc(tx_prof_tc->tx_profile, tc_type, tc_bool);
+}
+
+#define cxi_cfg_tx_prof_set_tc_common(item, tc_type, page)			\
+	do {									\
+		struct cxi_cfg_tx_prof_tc *tx_prof_tc;				\
+		bool b_val;							\
+		if (kstrtobool(page, &b_val))					\
+			return -EINVAL;						\
+		tx_prof_tc = to_cxi_cfg_tx_prof_tc((item));			\
+		set_tc_bool_type((tc_type), tx_prof_tc, b_val);			\
+	} while (0)
+
+static ssize_t cxi_cfg_tx_prof_tc_best_effort_show(struct config_item *item,
+						   char *page)
+{
+	struct cxi_cfg_tx_prof_tc *tx_prof_tc;
+
+	tx_prof_tc = to_cxi_cfg_tx_prof_tc(item);
+
+	return scnprintf(page, PAGE_SIZE, "%s\n",
+			 tx_prof_tc->best_effort ? "true" : "false");
+}
+
+static ssize_t cxi_cfg_tx_prof_tc_best_effort_store(struct config_item *item,
+						    const char *page,
+						    size_t count)
+{
+	cxi_cfg_tx_prof_set_tc_common(item, CXI_TC_BEST_EFFORT, page);
+
+	return count;
+}
+
+static ssize_t cxi_cfg_tx_prof_tc_dedicated_show(struct config_item *item,
+						 char *page)
+{
+	struct cxi_cfg_tx_prof_tc *tx_prof_tc;
+
+	tx_prof_tc = to_cxi_cfg_tx_prof_tc(item);
+
+	return scnprintf(page, PAGE_SIZE, "%s\n",
+			 tx_prof_tc->dedicated ? "true" : "false");
+}
+
+static ssize_t cxi_cfg_tx_prof_tc_dedicated_store(struct config_item *item,
+						  const char *page,
+						  size_t count)
+{
+	cxi_cfg_tx_prof_set_tc_common(item, CXI_TC_DEDICATED_ACCESS, page);
+
+	return count;
+}
+
+static ssize_t cxi_cfg_tx_prof_tc_low_latency_show(struct config_item *item,
+						   char *page)
+{
+	struct cxi_cfg_tx_prof_tc *tx_prof_tc;
+
+	tx_prof_tc = to_cxi_cfg_tx_prof_tc(item);
+
+	return scnprintf(page, PAGE_SIZE, "%s\n",
+			 tx_prof_tc->low_latency ? "true" : "false");
+}
+
+static ssize_t cxi_cfg_tx_prof_tc_low_latency_store(struct config_item *item,
+						    const char *page,
+						    size_t count)
+{
+	cxi_cfg_tx_prof_set_tc_common(item, CXI_TC_LOW_LATENCY, page);
+
+	return count;
+}
+
+static ssize_t cxi_cfg_tx_prof_tc_bulk_data_show(struct config_item *item,
+						 char *page)
+{
+	struct cxi_cfg_tx_prof_tc *tx_prof_tc;
+
+	tx_prof_tc = to_cxi_cfg_tx_prof_tc(item);
+
+	return scnprintf(page, PAGE_SIZE, "%s\n",
+			 tx_prof_tc->bulk_data ? "true" : "false");
+}
+
+static ssize_t cxi_cfg_tx_prof_tc_bulk_data_store(struct config_item *item,
+						  const char *page,
+						  size_t count)
+{
+	cxi_cfg_tx_prof_set_tc_common(item, CXI_TC_BULK_DATA, page);
+
+	return count;
+}
+
+static ssize_t cxi_cfg_tx_prof_tc_eth_show(struct config_item *item,
+					   char *page)
+{
+	struct cxi_cfg_tx_prof_tc *tx_prof_tc;
+
+	tx_prof_tc = to_cxi_cfg_tx_prof_tc(item);
+
+	return scnprintf(page, PAGE_SIZE, "%s\n",
+			 tx_prof_tc->eth ? "true" : "false");
+}
+
+static void cxi_cfg_tx_prof_tc_free(struct config_item *item)
+{
+	kfree(container_of(item, struct cxi_cfg_tx_prof_tc, group.cg_item));
+}
+
+CONFIGFS_ATTR(cxi_cfg_tx_prof_tc_,  best_effort);
+CONFIGFS_ATTR(cxi_cfg_tx_prof_tc_,  dedicated);
+CONFIGFS_ATTR(cxi_cfg_tx_prof_tc_,  low_latency);
+CONFIGFS_ATTR(cxi_cfg_tx_prof_tc_,  bulk_data);
+CONFIGFS_ATTR_RO(cxi_cfg_tx_prof_tc_,  eth);
+
+static struct configfs_attribute *cxi_cfg_tx_prof_tc_attrs[] = {
+	&cxi_cfg_tx_prof_tc_attr_best_effort,
+	&cxi_cfg_tx_prof_tc_attr_dedicated,
+	&cxi_cfg_tx_prof_tc_attr_low_latency,
+	&cxi_cfg_tx_prof_tc_attr_bulk_data,
+	&cxi_cfg_tx_prof_tc_attr_eth,
+	NULL
+};
+
+static struct configfs_item_operations cxi_cfg_tx_prof_tc_item_ops = {
+	.release     = cxi_cfg_tx_prof_tc_free,
+};
+
+static const struct config_item_type cxi_cfg_tx_prof_tc_type = {
+	.ct_attrs       = cxi_cfg_tx_prof_tc_attrs,
+	.ct_item_ops    = &cxi_cfg_tx_prof_tc_item_ops,
+	.ct_owner       = THIS_MODULE,
+};
+
+static struct cxi_cfg_tx_prof_tc *alloc_dev_tx_prof_tc(const char *name)
+{
+	struct cxi_cfg_tx_prof_tc *tx_prof_tc;
+
+	tx_prof_tc = kzalloc(sizeof(*tx_prof_tc), GFP_KERNEL);
+	if (!tx_prof_tc)
+		return NULL;
+
+	strscpy(tx_prof_tc->name, name, sizeof(tx_prof_tc->name));
+
+	config_group_init_type_name(&tx_prof_tc->group,
+				    tx_prof_tc->name,
+				    &cxi_cfg_tx_prof_tc_type);
+
+	return tx_prof_tc;
+}
+
+static struct cxi_cfg_tx_prof_attr *alloc_dev_tx_prof_attr(const char *name)
+{
+	struct cxi_cfg_tx_prof_attr *tx_prof_attr;
+
+	tx_prof_attr = kzalloc(sizeof(*tx_prof_attr), GFP_KERNEL);
+	if (!tx_prof_attr)
+		return NULL;
+
+	strscpy(tx_prof_attr->name, name, sizeof(tx_prof_attr->name));
+
+	config_group_init_type_name(&tx_prof_attr->group,
+				    tx_prof_attr->name,
+				    &cxi_cfg_tx_prof_attr_type);
+
+	return tx_prof_attr;
+}
+
+static struct cxi_cfg_tx_prof_ac_entry *alloc_dev_tx_prof_ac_entry(const char *name)
+{
+	struct cxi_cfg_tx_prof_ac_entry *tx_prof_ac_entry;
+
+	tx_prof_ac_entry = kzalloc(sizeof(*tx_prof_ac_entry),
+				   GFP_KERNEL);
+	if (!tx_prof_ac_entry)
+		return NULL;
+
+	strscpy(tx_prof_ac_entry->name,
+		name,
+		sizeof(tx_prof_ac_entry->name));
+
+	config_group_init_type_name(&tx_prof_ac_entry->group,
+				    tx_prof_ac_entry->name,
+				    &cxi_cfg_tx_prof_ac_entry_type);
+
+	return tx_prof_ac_entry;
+}
+
+static struct
+config_group *cxi_cfg_tx_prof_make_group(struct config_group *group,
+					 const char *name)
+{
+	struct cxi_cfg_tx_prof *tx_prof;
+	struct cxi_cfg_tx_prof_state *tx_prof_state;
+	struct cxi_cfg_tx_prof_attr *tx_prof_attr;
+	struct cxi_cfg_tx_prof_ac_entry *tx_prof_ac_entry;
+	struct cxi_cfg_tx_prof_tc *tx_prof_tc;
+
+	tx_prof = container_of(group,
+			       struct cxi_cfg_tx_prof,
+			       group);
+
+	if (strncmp(name, "attr", sizeof("attr") - 1) == 0) {
+		tx_prof_attr = alloc_dev_tx_prof_attr("attr");
+		if (!tx_prof_attr)
+			return ERR_PTR(-ENOMEM);
+		tx_prof->tx_prof_attr = tx_prof_attr;
+		tx_prof->tx_prof_attr->cdev = tx_prof->cdev;
+		tx_prof_attr->tx_profile = tx_prof->tx_profile;
+		tx_prof->tx_prof_attr->cdev = tx_prof->cdev;
+
+		return &tx_prof->tx_prof_attr->group;
+	}
+
+	if (strncmp(name, "state", sizeof("state") - 1) == 0) {
+		tx_prof_state = alloc_dev_tx_prof_state("state");
+		if (!tx_prof_state)
+			return ERR_PTR(-ENOMEM);
+		tx_prof->tx_prof_state = tx_prof_state;
+		tx_prof_state->tx_profile = tx_prof->tx_profile;
+		tx_prof->tx_prof_state->cdev = tx_prof->cdev;
+
+		return &tx_prof->tx_prof_state->group;
+	}
+
+	if (strncmp(name, "ac-entry", sizeof("ac-entry") - 1) == 0) {
+		tx_prof_ac_entry = alloc_dev_tx_prof_ac_entry("ac-entry");
+		if (!tx_prof_ac_entry)
+			return ERR_PTR(-ENOMEM);
+		tx_prof->tx_prof_ac_entry = tx_prof_ac_entry;
+		tx_prof_ac_entry->tx_profile = tx_prof->tx_profile;
+		tx_prof_ac_entry->cdev = tx_prof->cdev;
+
+		return &tx_prof->tx_prof_ac_entry->group;
+	}
+
+	if (strncmp(name, "tc", sizeof("tc") - 1) == 0) {
+		tx_prof_tc = alloc_dev_tx_prof_tc("tc");
+		if (!tx_prof_tc)
+			return ERR_PTR(-ENOMEM);
+		tx_prof->tx_prof_tc = tx_prof_tc;
+		tx_prof_tc->tx_profile = tx_prof->tx_profile;
+		tx_prof_tc->cdev = tx_prof->cdev;
+
+		return &tx_prof->tx_prof_tc->group;
+	}
+
+	return ERR_PTR(-EINVAL);
+}
+
+static void
+cxi_cfg_tx_prof_drop_item(struct config_group *group,
+			  struct config_item *item)
+{
+	cxi_cfg_drop_item_ref(item);
+}
+
+static void cxi_cfg_tx_prof_free(struct config_item *item)
+{
+	kfree(container_of(item, struct cxi_cfg_tx_prof, group.cg_item));
+}
+
+static struct cxi_cfg_tx_prof *to_cxi_cfg_tx_prof(struct config_item *item)
+{
+	return container_of(to_config_group(item), struct cxi_cfg_tx_prof, group);
+}
+
+static ssize_t cxi_cfg_tx_prof_id_show(struct config_item *item,
+				       char *page)
+{
+	struct cxi_cfg_tx_prof *tx_prof = to_cxi_cfg_tx_prof(item);
+
+	return scnprintf(page, PAGE_SIZE, "%d\n", tx_prof->id);
+}
+
+CONFIGFS_ATTR_RO(cxi_cfg_tx_prof_, id);
+
+static struct configfs_attribute *cxi_cfg_tx_prof_attrs[] = {
+	&cxi_cfg_tx_prof_attr_id,
+	NULL,
+};
+
+static struct configfs_group_operations cxi_cfg_tx_prof_ops = {
+	.make_group = cxi_cfg_tx_prof_make_group,
+	.drop_item  = cxi_cfg_tx_prof_drop_item,
+};
+
+static struct configfs_item_operations cxi_cfg_tx_prof_item_ops = {
+	.release     = cxi_cfg_tx_prof_free,
+};
+
+static const struct config_item_type cxi_cfg_tx_prof_type = {
+	.ct_group_ops   = &cxi_cfg_tx_prof_ops,
+	.ct_attrs       = cxi_cfg_tx_prof_attrs,
+	.ct_item_ops    = &cxi_cfg_tx_prof_item_ops,
+	.ct_owner       = THIS_MODULE,
+};
+
+static struct cxi_cfg_tx_prof *alloc_dev_tx_prof(const char *name)
+{
+	struct cxi_cfg_tx_prof *dev_tx_prof;
+
+	dev_tx_prof = kzalloc(sizeof(struct cxi_cfg_tx_prof), GFP_KERNEL);
+	if (!dev_tx_prof)
+		return NULL;
+
+	strscpy(dev_tx_prof->name, name, sizeof(dev_tx_prof->name));
+
+	config_group_init_type_name(&dev_tx_prof->group,
+				    dev_tx_prof->name,
+				    &cxi_cfg_tx_prof_type);
+
+	return dev_tx_prof;
+}
+
+static struct
+config_group *cxi_cfg_tx_prof_dir_make_group(struct config_group *group,
+					     const char *name)
+{
+	struct cxi_cfg_tx_prof_dir *tx_prof_dir;
+	struct cxi_cfg_tx_prof *tx_prof;
+	struct cxi_tx_profile *tx_prof_ptr;
+	struct cxi_tx_attr tx_attr = {};
+
+	if (strlen(name) > CONFIGFS_DIR_LEN - 1)
+		return ERR_PTR(-EINVAL);
+
+	tx_prof_dir = container_of(group, struct cxi_cfg_tx_prof_dir, group);
+	tx_prof = alloc_dev_tx_prof(name);
+	if (!tx_prof) {
+		pr_debug("Failed to alloc memory\n");
+		return ERR_PTR(-ENOMEM);
+	}
+
+	tx_prof->cdev = tx_prof_dir->cdev;
+	strscpy(tx_attr.vni_attr.name, name, sizeof(tx_attr.vni_attr.name));
+
+	tx_prof_ptr = cxi_dev_alloc_tx_profile(tx_prof->cdev,
+					       &tx_attr);
+	if (IS_ERR(tx_prof_ptr)) {
+		kfree(tx_prof);
+		pr_debug("Failed to alloc rx profile\n");
+		return ERR_PTR(PTR_ERR(tx_prof_ptr));
+	}
+
+	tx_prof->tx_profile = tx_prof_ptr;
+	tx_prof->id = tx_prof_ptr->profile_common.id;
+
+	return &tx_prof->group;
+}
+
+static void
+cxi_cfg_tx_prof_dir_drop_item(struct config_group *group,
+			      struct config_item *item)
+{
+	struct cxi_cfg_tx_prof *tx_prof;
+
+	tx_prof = container_of(item, struct cxi_cfg_tx_prof, group.cg_item);
+
+	/*
+	 * For accidental deletion of resource group directory
+	 * by configfs user. In the future we will employ a
+	 * different approach to handle accidental deletion.
+	 */
+	cxi_tx_profile_dec_refcount(tx_prof->cdev,
+				    tx_prof->tx_profile,
+				    true);
+	cxi_cfg_drop_item_ref(item);
+}
+
+static void cxi_cfg_tx_prof_dir_free(struct config_item *item)
+{
+	struct cxi_cfg_tx_prof_dir *tx_prof_dir;
+
+	tx_prof_dir = container_of(item, struct cxi_cfg_tx_prof_dir,
+				   group.cg_item);
+	kfree(tx_prof_dir);
+}
+
+static struct configfs_group_operations cxi_cfg_tx_prof_dir_ops = {
+	.make_group     = cxi_cfg_tx_prof_dir_make_group,
+	.drop_item      = cxi_cfg_tx_prof_dir_drop_item,
+};
+
+static struct configfs_item_operations cxi_cfg_tx_prof_dir_item_ops = {
+	.release     = cxi_cfg_tx_prof_dir_free,
+};
+
+static const struct config_item_type cxi_cfg_tx_prof_dir_type = {
+	.ct_group_ops   = &cxi_cfg_tx_prof_dir_ops,
+	.ct_item_ops    = &cxi_cfg_tx_prof_dir_item_ops,
+	.ct_owner       = THIS_MODULE,
+};
+
+static struct cxi_cfg_tx_prof_dir *alloc_dev_tx_prof_dir(const char *name)
+{
+	struct cxi_cfg_tx_prof_dir *dev_tx_prof_dir;
+
+	dev_tx_prof_dir = kzalloc(sizeof(*dev_tx_prof_dir), GFP_KERNEL);
+	if (!dev_tx_prof_dir)
+		return NULL;
+
+	strscpy(dev_tx_prof_dir->name, name, sizeof(dev_tx_prof_dir->name));
+
+	config_group_init_type_name(&dev_tx_prof_dir->group,
+				    dev_tx_prof_dir->name,
+				    &cxi_cfg_tx_prof_dir_type);
+
+	return dev_tx_prof_dir;
+}
+
+static struct cxi_cfg_rx_prof_ac_entry_sub *to_cxi_cfg_rx_prof_ac_entry_sub(struct config_item *item)
+{
+	return container_of(to_config_group(item), struct cxi_cfg_rx_prof_ac_entry_sub, group);
+}
+
+static ssize_t cxi_cfg_rx_prof_ac_entry_sub_type_show(struct config_item *item,
+						      char *page)
+{
+	struct cxi_cfg_rx_prof_ac_entry_sub *rx_prof_ac_entry_sub;
+	enum cxi_ac_type ac_type;
+	union cxi_ac_data ac_data;
+	int rc;
+
+	rx_prof_ac_entry_sub = to_cxi_cfg_rx_prof_ac_entry_sub(item);
+
+	rc = cxi_rx_profile_get_ac_entry_data(rx_prof_ac_entry_sub->rx_profile,
+					      rx_prof_ac_entry_sub->id,
+					      &ac_type,
+					      &ac_data);
+	if (rc)
+		return rc;
+
+	return sprintf(page, "%d\n", ac_type);
+}
+
+static ssize_t cxi_cfg_rx_prof_ac_entry_sub_type_store(struct config_item *item,
+						       const char *page,
+						       size_t count)
+{
+	struct cxi_cfg_rx_prof_ac_entry_sub *ac_entry_sub;
+	int rc;
+	enum cxi_ac_type ac_type_val;
+	uid_t uid;
+	gid_t gid;
+	unsigned int netns;
+	unsigned int ac_entry_id;
+
+	ac_entry_sub = to_cxi_cfg_rx_prof_ac_entry_sub(item);
+	if (!ac_entry_sub->rx_profile) {
+		pr_debug("Unable to get rx profile reference\n");
+		return -EINVAL;
+	}
+
+	rc = kstrtouint(page, 0, (unsigned int *)&ac_type_val);
+	if (rc)
+		return rc;
+
+	if (ac_type_val == CXI_AC_UID)
+		uid = ac_entry_sub->ac_data.uid;
+	else if (ac_type_val == CXI_AC_GID)
+		gid = ac_entry_sub->ac_data.gid;
+	else if (ac_type_val == CXI_AC_NETNS)
+		netns = ac_entry_sub->ac_data.netns;
+	else if (ac_type_val == CXI_AC_OPEN)
+		pr_debug("Setting type to CXI_AC_OPEN\n");
+	else
+		return -EINVAL;
+
+	rc = cxi_rx_profile_add_ac_entry(ac_entry_sub->rx_profile,
+					 ac_type_val,
+					 uid,
+					 gid,
+					 netns,
+					 &ac_entry_id);
+	if (rc < 0) {
+		pr_debug("Unable to add ac entry to rx profile: err val %d\n", rc);
+		return rc;
+	}
+
+	ac_entry_sub->id = ac_entry_id;
+	ac_entry_sub->ac_type = ac_type_val;
+
+	return count;
+}
+
+static ssize_t cxi_cfg_rx_prof_ac_entry_sub_data_show(struct config_item *item,
+						      char *page)
+{
+	struct cxi_cfg_rx_prof_ac_entry_sub *rx_prof_ac_entry_sub;
+	int rc;
+	enum cxi_ac_type ac_type;
+	union cxi_ac_data ac_data;
+
+	rx_prof_ac_entry_sub = to_cxi_cfg_rx_prof_ac_entry_sub(item);
+
+	rc = cxi_rx_profile_get_ac_entry_data(rx_prof_ac_entry_sub->rx_profile,
+					      rx_prof_ac_entry_sub->id,
+					      &ac_type,
+					      &ac_data);
+	if (rc)
+		return rc;
+
+	if (ac_type == CXI_AC_UID)
+		return sprintf(page, "%d\n", ac_data.uid);
+	else if (ac_type == CXI_AC_GID)
+		return sprintf(page, "%d\n", ac_data.gid);
+	else if (ac_type == CXI_AC_NETNS)
+		return sprintf(page, "%d\n", ac_data.netns);
+	else if (ac_type == CXI_AC_OPEN)
+		return sprintf(page, "%d\n", CXI_AC_OPEN);
+
+	return -EINVAL;
+}
+
+static ssize_t cxi_cfg_rx_prof_ac_entry_sub_data_store(struct config_item *item,
+						       const char *page,
+						       size_t count)
+{
+	struct cxi_cfg_rx_prof_ac_entry_sub *ac_entry_sub;
+	int rc;
+	unsigned int ac_data_val;
+
+	ac_entry_sub = to_cxi_cfg_rx_prof_ac_entry_sub(item);
+
+	rc = kstrtouint(page, 0, &ac_data_val);
+	if (rc)
+		return rc;
+
+	if (ac_entry_sub->ac_type == CXI_AC_UID) {
+		ac_entry_sub->ac_data.uid = ac_data_val;
+		return count;
+	} else if (ac_entry_sub->ac_type == CXI_AC_GID) {
+		ac_entry_sub->ac_data.gid = ac_data_val;
+		return count;
+	} else if (ac_entry_sub->ac_type == CXI_AC_NETNS) {
+		ac_entry_sub->ac_data.netns = ac_data_val;
+		return count;
+	}
+
+	return -EINVAL;
+}
+
+static void cxi_cfg_rx_prof_ac_entry_sub_free(struct config_item *item)
+{
+	kfree(container_of(item, struct cxi_cfg_rx_prof_ac_entry_sub, group.cg_item));
+}
+
+CONFIGFS_ATTR(cxi_cfg_rx_prof_ac_entry_sub_, type);
+CONFIGFS_ATTR(cxi_cfg_rx_prof_ac_entry_sub_, data);
+
+static struct configfs_attribute *cxi_cfg_rx_prof_ac_entry_sub_attrs[] = {
+	&cxi_cfg_rx_prof_ac_entry_sub_attr_type,
+	&cxi_cfg_rx_prof_ac_entry_sub_attr_data,
+	NULL,
+};
+
+static struct configfs_item_operations cxi_cfg_rx_prof_ac_entry_sub_item_ops = {
+	.release     = cxi_cfg_rx_prof_ac_entry_sub_free,
+};
+
+static const struct config_item_type cxi_cfg_rx_prof_ac_entry_sub_type = {
+	.ct_attrs       = cxi_cfg_rx_prof_ac_entry_sub_attrs,
+	.ct_item_ops    = &cxi_cfg_rx_prof_ac_entry_sub_item_ops,
+	.ct_owner       = THIS_MODULE,
+};
+
+static struct cxi_cfg_rx_prof_ac_entry_sub *alloc_dev_rx_prof_ac_entry_sub(const char *name)
+{
+	struct cxi_cfg_rx_prof_ac_entry_sub *rx_prof_ac_entry_sub;
+
+	rx_prof_ac_entry_sub = kzalloc(sizeof(*rx_prof_ac_entry_sub), GFP_KERNEL);
+	if (!rx_prof_ac_entry_sub)
+		return NULL;
+
+	strscpy(rx_prof_ac_entry_sub->name, name, sizeof(rx_prof_ac_entry_sub->name));
+
+	config_group_init_type_name(&rx_prof_ac_entry_sub->group,
+				    rx_prof_ac_entry_sub->name,
+				    &cxi_cfg_rx_prof_ac_entry_sub_type);
+
+	return rx_prof_ac_entry_sub;
+}
+
+static struct
+config_group *cxi_cfg_rx_prof_ac_entry_make_group(struct config_group *group,
+						  const char *name)
+{
+	struct cxi_cfg_rx_prof_ac_entry *rx_prof_ac_entry;
+	struct cxi_cfg_rx_prof_ac_entry_sub *rx_prof_ac_entry_sub;
+
+	if (strlen(name) > CONFIGFS_DIR_LEN - 1)
+		return ERR_PTR(-EINVAL);
+
+	rx_prof_ac_entry_sub = alloc_dev_rx_prof_ac_entry_sub(name);
+	if (!rx_prof_ac_entry_sub) {
+		pr_debug("Memory allocation failed for ac entry group\n");
+		return ERR_PTR(-ENOMEM);
+	}
+
+	rx_prof_ac_entry_sub->ac_type = CXI_AC_UID;
+	rx_prof_ac_entry_sub->ac_data.uid = 0;
+
+	rx_prof_ac_entry = container_of(group, struct cxi_cfg_rx_prof_ac_entry, group);
+	rx_prof_ac_entry_sub->rx_profile = rx_prof_ac_entry->rx_profile;
+
+	return &rx_prof_ac_entry_sub->group;
+}
+
+static void
+cxi_cfg_rx_prof_ac_entry_drop_item(struct config_group *group,
+				   struct config_item *item)
+{
+	struct cxi_cfg_rx_prof_ac_entry_sub *rx_prof_ac_entry_sub;
+
+	rx_prof_ac_entry_sub = container_of(item, struct cxi_cfg_rx_prof_ac_entry_sub, group.cg_item);
+	cxi_rx_profile_remove_ac_entry(rx_prof_ac_entry_sub->rx_profile,
+				       rx_prof_ac_entry_sub->id);
+
+	cxi_cfg_drop_item_ref(item);
+}
+
+static void cxi_cfg_rx_prof_ac_entry_free(struct config_item *item)
+{
+	kfree(container_of(item, struct cxi_cfg_rx_prof_ac_entry, group.cg_item));
+}
+
+static struct configfs_group_operations cxi_cfg_rx_prof_ac_entry_ops = {
+	.make_group     = cxi_cfg_rx_prof_ac_entry_make_group,
+	.drop_item      = cxi_cfg_rx_prof_ac_entry_drop_item,
+};
+
+static struct configfs_item_operations cxi_cfg_rx_prof_ac_entry_item_ops = {
+	.release     = cxi_cfg_rx_prof_ac_entry_free,
+};
+
+static const struct config_item_type cxi_cfg_rx_prof_ac_entry_type = {
+	.ct_group_ops   = &cxi_cfg_rx_prof_ac_entry_ops,
+	.ct_item_ops    = &cxi_cfg_rx_prof_ac_entry_item_ops,
+	.ct_owner       = THIS_MODULE,
+};
+
+static struct cxi_cfg_rx_prof_state *to_cxi_cfg_rx_prof_state(struct config_item *item)
+{
+	return container_of(to_config_group(item), struct cxi_cfg_rx_prof_state, group);
+}
+
+static ssize_t cxi_cfg_rx_prof_state_enabled_show(struct config_item *item,
+						  char *page)
+{
+	struct cxi_cfg_rx_prof_state *rx_prof_state;
+	struct cxi_rx_attr rx_attr;
+	struct cxi_rxtx_profile_state state;
+	int rc;
+
+	rx_prof_state = to_cxi_cfg_rx_prof_state(item);
+
+	rc = cxi_rx_profile_get_info(rx_prof_state->cdev,
+				     rx_prof_state->rx_profile,
+				     &rx_attr,
+				     &state);
+	if (rc < 0) {
+		pr_debug("Unable to get rx-profile info rc = %d\n", rc);
+		return rc;
+	}
+
+	return scnprintf(page, PAGE_SIZE, "%s\n", state.enable ? "true" : "false");
+}
+
+static ssize_t cxi_cfg_rx_prof_state_enabled_store(struct config_item *item,
+						   const char *page,
+						   size_t count)
+{
+	struct cxi_cfg_rx_prof_state *rx_prof_state;
+	int rc;
+	bool b_val;
+
+	if (kstrtobool(page, &b_val))
+		return -EINVAL;
+
+	rx_prof_state = to_cxi_cfg_rx_prof_state(item);
+
+	if (b_val) {
+		rc = cxi_rx_profile_enable(rx_prof_state->cdev,
+					   rx_prof_state->rx_profile);
+		if (rc)
+			return rc;
+	} else {
+		cxi_rx_profile_disable(rx_prof_state->cdev,
+				       rx_prof_state->rx_profile);
+	}
+
+	return count;
+}
+
+static ssize_t cxi_cfg_rx_prof_state_refcount_show(struct config_item *item,
+						   char *page)
+{
+	struct cxi_cfg_rx_prof_state *rx_prof_state;
+	struct cxi_rx_attr rx_attr;
+	struct cxi_rxtx_profile_state state;
+	int rc;
+
+	rx_prof_state = to_cxi_cfg_rx_prof_state(item);
+
+	rc = cxi_rx_profile_get_info(rx_prof_state->cdev,
+				     rx_prof_state->rx_profile,
+				     &rx_attr,
+				     &state);
+	if (rc < 0) {
+		pr_debug("Unable to get rx-profile info rc = %d\n", rc);
+		return rc;
+	}
+
+	return sprintf(page, "%d\n", refcount_read(&state.refcount));
+}
+
+static void cxi_cfg_rx_prof_state_free(struct config_item *item)
+{
+	kfree(container_of(item, struct cxi_cfg_rx_prof_state, group.cg_item));
+}
+
+CONFIGFS_ATTR(cxi_cfg_rx_prof_state_, enabled);
+CONFIGFS_ATTR_RO(cxi_cfg_rx_prof_state_, refcount);
+
+static struct configfs_attribute *cxi_cfg_rx_prof_state_attrs[] = {
+	&cxi_cfg_rx_prof_state_attr_enabled,
+	&cxi_cfg_rx_prof_state_attr_refcount,
+	NULL
+};
+
+static struct configfs_item_operations cxi_cfg_rx_prof_state_item_ops = {
+	.release     = cxi_cfg_rx_prof_state_free,
+};
+
+static const struct config_item_type cxi_cfg_rx_prof_state_type = {
+	.ct_attrs       = cxi_cfg_rx_prof_state_attrs,
+	.ct_item_ops    = &cxi_cfg_rx_prof_state_item_ops,
+	.ct_owner       = THIS_MODULE,
+};
+
+static struct cxi_cfg_rx_prof_state *alloc_dev_rx_prof_state(const char *name)
+{
+	struct cxi_cfg_rx_prof_state *rx_prof_state;
+
+	rx_prof_state = kzalloc(sizeof(*rx_prof_state), GFP_KERNEL);
+	if (!rx_prof_state)
+		return NULL;
+
+	strscpy(rx_prof_state->name, name, sizeof(rx_prof_state->name));
+
+	config_group_init_type_name(&rx_prof_state->group,
+				    rx_prof_state->name,
+				    &cxi_cfg_rx_prof_state_type);
+
+	return rx_prof_state;
+}
+
+static struct cxi_cfg_rx_prof_attr *to_cxi_cfg_rx_prof_attr(struct config_item *item)
+{
+	return container_of(to_config_group(item), struct cxi_cfg_rx_prof_attr, group);
+}
+
+static ssize_t cxi_cfg_rx_prof_attr_name_show(struct config_item *item,
+					      char *page)
+{
+	struct cxi_cfg_rx_prof_attr *rx_prof_attr;
+
+	rx_prof_attr = to_cxi_cfg_rx_prof_attr(item);
+
+	return scnprintf(page, PAGE_SIZE, "%s\n",
+			 rx_prof_attr->rx_profile->profile_common.vni_attr.name);
+}
+
+static ssize_t cxi_cfg_rx_prof_attr_match_show(struct config_item *item,
+					       char *page)
+{
+	struct cxi_cfg_rx_prof_attr *rx_prof_attr;
+	struct cxi_rx_attr rx_attr;
+	struct cxi_rxtx_profile_state state;
+	int rc;
+
+	rx_prof_attr = to_cxi_cfg_rx_prof_attr(item);
+
+	rc = cxi_rx_profile_get_info(rx_prof_attr->cdev,
+				     rx_prof_attr->rx_profile,
+				     &rx_attr,
+				     &state);
+	if (rc < 0)
+		return rc;
+
+	return scnprintf(page, PAGE_SIZE, "%d\n", rx_attr.vni_attr.match);
+}
+
+static ssize_t cxi_cfg_rx_prof_attr_match_store(struct config_item *item,
+						const char *page,
+						size_t count)
+{
+	struct cxi_cfg_rx_prof_attr *rx_prof_attr;
+	int rc;
+	struct cxi_rx_attr rx_attr = {};
+
+	rx_prof_attr = to_cxi_cfg_rx_prof_attr(item);
+	rc = kstrtou16(page, 0, &rx_prof_attr->match);
+	if (rc)
+		return rc;
+
+	rx_attr.vni_attr.match = rx_prof_attr->match;
+	rx_attr.vni_attr.ignore = rx_prof_attr->ignore;
+
+	strscpy(rx_attr.vni_attr.name,
+		rx_prof_attr->rx_profile->profile_common.vni_attr.name,
+		sizeof(rx_attr.vni_attr.name));
+
+	rc = cxi_dev_set_rx_profile_attr(rx_prof_attr->cdev,
+					 rx_prof_attr->rx_profile,
+					 &rx_attr);
+	if (rc)
+		return rc;
+
+	return count;
+}
+
+static ssize_t cxi_cfg_rx_prof_attr_ignore_show(struct config_item *item,
+						char *page)
+{
+	struct cxi_cfg_rx_prof_attr *rx_prof_attr;
+	int rc;
+	struct cxi_rx_attr rx_attr;
+	struct cxi_rxtx_profile_state state;
+
+	rx_prof_attr = to_cxi_cfg_rx_prof_attr(item);
+
+	rc = cxi_rx_profile_get_info(rx_prof_attr->cdev,
+				     rx_prof_attr->rx_profile,
+				     &rx_attr,
+				     &state);
+	if (rc < 0) {
+		pr_err("Unable to get rx-profile info rc = %d\n", rc);
+		return rc;
+	}
+
+	return scnprintf(page, PAGE_SIZE, "%d\n", rx_attr.vni_attr.ignore);
+}
+
+static ssize_t cxi_cfg_rx_prof_attr_ignore_store(struct config_item *item,
+						 const char *page,
+						 size_t count)
+{
+	struct cxi_cfg_rx_prof_attr *rx_prof_attr;
+	struct cxi_rxtx_profile_state state;
+	struct cxi_rx_attr rx_attr;
+	u16 ignore;
+	int rc;
+
+	rx_prof_attr = to_cxi_cfg_rx_prof_attr(item);
+	rc = kstrtou16(page, 0, &ignore);
+	if (rc)
+		return rc;
+
+	rc = cxi_rx_profile_get_info(rx_prof_attr->cdev,
+				     rx_prof_attr->rx_profile, &rx_attr, &state);
+	if (rc < 0)
+		return rc;
+	rx_attr.vni_attr.ignore = ignore;
+	rc = cxi_dev_set_rx_profile_attr(rx_prof_attr->cdev,
+					 rx_prof_attr->rx_profile, &rx_attr);
+	if (rc)
+		return rc;
+	rx_prof_attr->ignore = ignore;
+	return count;
+}
+
+static void cxi_cfg_rx_prof_attr_free(struct config_item *item)
+{
+	kfree(container_of(item, struct cxi_cfg_rx_prof_attr, group.cg_item));
+}
+
+CONFIGFS_ATTR(cxi_cfg_rx_prof_attr_, ignore);
+CONFIGFS_ATTR(cxi_cfg_rx_prof_attr_, match);
+CONFIGFS_ATTR_RO(cxi_cfg_rx_prof_attr_, name);
+
+static struct configfs_attribute *cxi_cfg_rx_prof_attr_attrs[] = {
+	&cxi_cfg_rx_prof_attr_attr_name,
+	&cxi_cfg_rx_prof_attr_attr_match,
+	&cxi_cfg_rx_prof_attr_attr_ignore,
+	NULL
+};
+
+static struct configfs_item_operations cxi_cfg_rx_prof_attr_item_ops = {
+	.release     = cxi_cfg_rx_prof_attr_free,
+};
+
+static const struct config_item_type cxi_cfg_rx_prof_attr_type = {
+	.ct_attrs       = cxi_cfg_rx_prof_attr_attrs,
+	.ct_item_ops    = &cxi_cfg_rx_prof_attr_item_ops,
+	.ct_owner       = THIS_MODULE,
+};
+
+static struct cxi_cfg_rx_prof_attr *alloc_dev_rx_prof_attr(const char *name)
+{
+	struct cxi_cfg_rx_prof_attr *rx_prof_attr;
+
+	rx_prof_attr = kzalloc(sizeof(*rx_prof_attr), GFP_KERNEL);
+	if (!rx_prof_attr)
+		return NULL;
+
+	strscpy(rx_prof_attr->name, name, sizeof(rx_prof_attr->name));
+
+	config_group_init_type_name(&rx_prof_attr->group,
+				    rx_prof_attr->name,
+				    &cxi_cfg_rx_prof_attr_type);
+
+	return rx_prof_attr;
+}
+
+static struct cxi_cfg_rx_prof_ac_entry *alloc_dev_rx_prof_ac_entry(const char *name)
+{
+	struct cxi_cfg_rx_prof_ac_entry *rx_prof_ac_entry;
+
+	rx_prof_ac_entry = kzalloc(sizeof(*rx_prof_ac_entry),
+				   GFP_KERNEL);
+	if (!rx_prof_ac_entry)
+		return NULL;
+
+	strscpy(rx_prof_ac_entry->name,
+		name,
+		sizeof(rx_prof_ac_entry->name));
+
+	config_group_init_type_name(&rx_prof_ac_entry->group,
+				    rx_prof_ac_entry->name,
+				    &cxi_cfg_rx_prof_ac_entry_type);
+
+	return rx_prof_ac_entry;
+}
+
+static struct
+config_group *cxi_cfg_rx_prof_make_group(struct config_group *group,
+					 const char *name)
+{
+	struct cxi_cfg_rx_prof *rx_prof;
+	struct cxi_cfg_rx_prof_state *rx_prof_state;
+	struct cxi_cfg_rx_prof_attr *rx_prof_attr;
+	struct cxi_cfg_rx_prof_ac_entry *rx_prof_ac_entry;
+
+	rx_prof = container_of(group, struct cxi_cfg_rx_prof, group);
+
+	if (strncmp(name, "attr", sizeof("attr") - 1) == 0) {
+		rx_prof_attr = alloc_dev_rx_prof_attr("attr");
+		if (!rx_prof_attr)
+			return ERR_PTR(-ENOMEM);
+
+		rx_prof->rx_prof_attr = rx_prof_attr;
+		rx_prof->rx_prof_attr->cdev = rx_prof->cdev;
+		rx_prof_attr->rx_profile = rx_prof->rx_profile;
+		rx_prof->rx_prof_attr->cdev = rx_prof->cdev;
+
+		return &rx_prof->rx_prof_attr->group;
+	}
+
+	if (strncmp(name, "state", sizeof("state") - 1) == 0) {
+		rx_prof_state = alloc_dev_rx_prof_state("state");
+		if (!rx_prof_state)
+			return ERR_PTR(-ENOMEM);
+
+		rx_prof->rx_prof_state = rx_prof_state;
+		rx_prof_state->rx_profile = rx_prof->rx_profile;
+		rx_prof->rx_prof_state->cdev = rx_prof->cdev;
+
+		return &rx_prof->rx_prof_state->group;
+	}
+
+	if (strncmp(name, "ac-entry", sizeof("ac-entry") - 1) == 0) {
+		rx_prof_ac_entry = alloc_dev_rx_prof_ac_entry("ac-entry");
+		if (!rx_prof_ac_entry)
+			return ERR_PTR(-ENOMEM);
+
+		rx_prof->rx_prof_ac_entry = rx_prof_ac_entry;
+		rx_prof_ac_entry->rx_profile = rx_prof->rx_profile;
+		rx_prof_ac_entry->cdev = rx_prof->cdev;
+
+		return &rx_prof->rx_prof_ac_entry->group;
+	}
+
+	return ERR_PTR(-EINVAL);
+}
+
+static void
+cxi_cfg_rx_prof_drop_item(struct config_group *group,
+			  struct config_item *item)
+{
+	cxi_cfg_drop_item_ref(item);
+}
+
+static void cxi_cfg_rx_prof_free(struct config_item *item)
+{
+	kfree(container_of(item, struct cxi_cfg_rx_prof, group.cg_item));
+}
+
+static struct cxi_cfg_rx_prof *to_cxi_cfg_rx_prof(struct config_item *item)
+{
+	return container_of(to_config_group(item), struct cxi_cfg_rx_prof, group);
+}
+
+static ssize_t cxi_cfg_rx_prof_id_show(struct config_item *item,
+				       char *page)
+{
+	struct cxi_cfg_rx_prof *rx_prof = to_cxi_cfg_rx_prof(item);
+
+	return scnprintf(page, PAGE_SIZE, "%d\n", rx_prof->id);
+}
+
+CONFIGFS_ATTR_RO(cxi_cfg_rx_prof_, id);
+
+static struct configfs_attribute *cxi_cfg_rx_prof_attrs[] = {
+	&cxi_cfg_rx_prof_attr_id,
+	NULL,
+};
+
+static struct configfs_group_operations cxi_cfg_rx_prof_ops = {
+	.make_group = cxi_cfg_rx_prof_make_group,
+	.drop_item  = cxi_cfg_rx_prof_drop_item,
+};
+
+static struct configfs_item_operations cxi_cfg_rx_prof_item_ops = {
+	.release     = cxi_cfg_rx_prof_free,
+};
+
+static const struct config_item_type cxi_cfg_rx_prof_type = {
+	.ct_group_ops   = &cxi_cfg_rx_prof_ops,
+	.ct_attrs       = cxi_cfg_rx_prof_attrs,
+	.ct_item_ops    = &cxi_cfg_rx_prof_item_ops,
+	.ct_owner       = THIS_MODULE,
+};
+
+static struct cxi_cfg_rx_prof *alloc_dev_rx_prof(const char *name)
+{
+	struct cxi_cfg_rx_prof *dev_rx_prof;
+
+	dev_rx_prof = kzalloc(sizeof(struct cxi_cfg_rx_prof), GFP_KERNEL);
+	if (!dev_rx_prof)
+		return NULL;
+
+	strscpy(dev_rx_prof->name, name, sizeof(dev_rx_prof->name));
+
+	config_group_init_type_name(&dev_rx_prof->group,
+				    dev_rx_prof->name,
+				    &cxi_cfg_rx_prof_type);
+
+	return dev_rx_prof;
+}
+
+static struct
+config_group *cxi_cfg_rx_prof_dir_make_group(struct config_group *group,
+					     const char *name)
+{
+	struct cxi_cfg_rx_prof_dir *rx_prof_dir;
+	struct cxi_cfg_rx_prof *rx_prof;
+	struct cxi_rx_profile *rx_prof_ptr;
+	struct cxi_rx_attr rx_attr = {};
+
+	if (strlen(name) > CONFIGFS_DIR_LEN - 1)
+		return ERR_PTR(-EINVAL);
+
+	rx_prof_dir = container_of(group, struct cxi_cfg_rx_prof_dir, group);
+	rx_prof = alloc_dev_rx_prof(name);
+	if (!rx_prof) {
+		pr_debug("Failed to alloc memory\n");
+		return ERR_PTR(-ENOMEM);
+	}
+
+	rx_prof->cdev = rx_prof_dir->cdev;
+
+	strscpy(rx_attr.vni_attr.name, name, sizeof(rx_attr.vni_attr.name));
+
+	rx_prof_ptr = cxi_dev_alloc_rx_profile(rx_prof->cdev,
+					       &rx_attr);
+	if (IS_ERR(rx_prof_ptr)) {
+		kfree(rx_prof);
+		pr_debug("Failed to alloc rx profile\n");
+		return ERR_PTR(PTR_ERR(rx_prof_ptr));
+	}
+
+	rx_prof->rx_profile = rx_prof_ptr;
+	rx_prof->id = rx_prof_ptr->profile_common.id;
+
+	return &rx_prof->group;
+}
+
+static void
+cxi_cfg_rx_prof_dir_drop_item(struct config_group *group,
+			      struct config_item *item)
+{
+	struct cxi_cfg_rx_prof *rx_prof;
+
+	rx_prof = container_of(item, struct cxi_cfg_rx_prof, group.cg_item);
+
+	/*
+	 * For accidental deletion of resource group directory
+	 * by configfs user. In the future we will employ a
+	 * different approach to handle accidental deletion.
+	 */
+	cxi_rx_profile_dec_refcount(rx_prof->cdev,
+				    rx_prof->rx_profile);
+
+	cxi_cfg_drop_item_ref(item);
+}
+
+static void cxi_cfg_rx_prof_dir_free(struct config_item *item)
+{
+	struct cxi_cfg_rx_prof_dir *rx_prof_dir;
+
+	rx_prof_dir = container_of(item, struct cxi_cfg_rx_prof_dir,
+				   group.cg_item);
+	kfree(rx_prof_dir);
+}
+
+static struct configfs_group_operations cxi_cfg_rx_prof_dir_ops = {
+	.make_group     = cxi_cfg_rx_prof_dir_make_group,
+	.drop_item      = cxi_cfg_rx_prof_dir_drop_item,
+};
+
+static struct configfs_item_operations cxi_cfg_rx_prof_dir_item_ops = {
+	.release     = cxi_cfg_rx_prof_dir_free,
+};
+
+static const struct config_item_type cxi_cfg_rx_prof_dir_type = {
+	.ct_group_ops   = &cxi_cfg_rx_prof_dir_ops,
+	.ct_item_ops    = &cxi_cfg_rx_prof_dir_item_ops,
+	.ct_owner       = THIS_MODULE,
+};
+
+static struct cxi_cfg_rx_prof_dir *alloc_dev_rx_prof_dir(const char *name)
+{
+	struct cxi_cfg_rx_prof_dir *dev_rx_prof_dir;
+
+	dev_rx_prof_dir = kzalloc(sizeof(*dev_rx_prof_dir), GFP_KERNEL);
+	if (!dev_rx_prof_dir)
+		return NULL;
+
+	strscpy(dev_rx_prof_dir->name, name, sizeof(dev_rx_prof_dir->name));
+
+	config_group_init_type_name(&dev_rx_prof_dir->group,
+				    dev_rx_prof_dir->name,
+				    &cxi_cfg_rx_prof_dir_type);
+
+	return dev_rx_prof_dir;
+}
+
+int cxi_configfs_device_init(struct cass_dev *hw)
+{
+	struct config_group *parent_group;
+	struct cxi_cfg_group_item *cxi_cfg_configfs;
+	struct cxi_cfg_rgroup_dir *rgp_dir;
+	struct cxi_cfg_rx_prof_dir *rx_prof_dir;
+	struct cxi_cfg_tx_prof_dir *tx_prof_dir;
+	int rc;
+
+	parent_group = &cxi_cfg_group_subsys.su_group;
+
+	cxi_cfg_configfs = alloc_dev_subdir(hw->cdev.name);
+	if (!cxi_cfg_configfs)
+		return -ENOMEM;
+
+	hw->cfg_dev_dir = cxi_cfg_configfs;
+
+	rc = configfs_register_group(parent_group,
+				     &cxi_cfg_configfs->group);
+	if (rc)
+		goto dev_grp_reg_err;
+
+	rgp_dir = alloc_dev_attr1("rgroup");
+	if (!rgp_dir) {
+		rc = -ENOMEM;
+		goto rgp_dir_alloc_err;
+	}
+
+	rc = configfs_register_group(&cxi_cfg_configfs->group,
+				     &rgp_dir->group);
+	if (rc)
+		goto rgp_dir_reg_err;
+
+	cxi_cfg_configfs->rgp_dir = rgp_dir;
+	rgp_dir->cdev = &hw->cdev;
+
+	rx_prof_dir = alloc_dev_rx_prof_dir("rx-profile");
+	if (!rx_prof_dir) {
+		rc = -ENOMEM;
+		goto rx_prof_dir_alloc_err;
+	}
+
+	rc = configfs_register_group(&cxi_cfg_configfs->group,
+				     &rx_prof_dir->group);
+	if (rc)
+		goto rx_prof_dir_reg_err;
+
+	cxi_cfg_configfs->rx_prof_dir = rx_prof_dir;
+	rx_prof_dir->cdev = &hw->cdev;
+
+	tx_prof_dir = alloc_dev_tx_prof_dir("tx-profile");
+	if (!tx_prof_dir) {
+		rc = -ENOMEM;
+		goto tx_prof_dir_alloc_err;
+	}
+
+	rc = configfs_register_group(&cxi_cfg_configfs->group,
+				     &tx_prof_dir->group);
+	if (rc)
+		goto tx_prof_dir_reg_err;
+
+	cxi_cfg_configfs->tx_prof_dir = tx_prof_dir;
+	tx_prof_dir->cdev = &hw->cdev;
+
+	return 0;
+
+tx_prof_dir_reg_err:
+	kfree(tx_prof_dir);
+tx_prof_dir_alloc_err:
+	configfs_unregister_group(&rx_prof_dir->group);
+rx_prof_dir_reg_err:
+	kfree(rx_prof_dir);
+rx_prof_dir_alloc_err:
+	configfs_unregister_group(&rgp_dir->group);
+rgp_dir_reg_err:
+	kfree(rgp_dir);
+rgp_dir_alloc_err:
+	configfs_unregister_group(&cxi_cfg_configfs->group);
+dev_grp_reg_err:
+	hw->cfg_dev_dir = NULL;
+	kfree(cxi_cfg_configfs);
+
+	return rc;
+}
+
+int cxi_configfs_subsys_init(void)
+{
+	struct configfs_subsystem *subsys;
+	int rc;
+
+	subsys = &cxi_cfg_group_subsys;
+
+	config_group_init(&subsys->su_group);
+	mutex_init(&subsys->su_mutex);
+
+	rc = configfs_register_subsystem(subsys);
+	if (rc)
+		return rc;
+
+	return 0;
+}
+
+/*
+ * cg_children is protected by the subsystem's su_mutex: configfs mkdir and
+ * rmdir add and remove children with it held. configfs_unregister_group()
+ * takes su_mutex itself, so it can't be called with it held. Look at the
+ * list under the lock, pin the child so it can't be freed under us, and
+ * drop the lock before unregistering it.
+ *
+ * Returns the first child with a reference held, or NULL if there are none.
+ */
+static struct config_group *
+get_first_child_config_group(struct config_group *parent_group,
+			     struct cxi_cfg_teardown_marker *marker)
+{
+	struct config_item *child_item;
+	struct config_group *child_group = NULL;
+	unsigned long flags;
+
+	mutex_lock(&cxi_cfg_group_subsys.su_mutex);
+	child_item = list_first_entry_or_null(&parent_group->cg_children,
+					      struct config_item, ci_entry);
+	if (child_item) {
+		config_item_get(child_item);
+		marker->item = child_item;
+		INIT_LIST_HEAD(&marker->list);
+		spin_lock_irqsave(&cxi_cfg_teardown_lock, flags);
+		list_add(&marker->list, &cxi_cfg_teardown_markers);
+		spin_unlock_irqrestore(&cxi_cfg_teardown_lock, flags);
+		child_group = container_of(child_item,
+					   struct config_group, cg_item);
+	}
+	mutex_unlock(&cxi_cfg_group_subsys.su_mutex);
+
+	return child_group;
+}
+
+static void unregister_all_sub_config_groups_recur(struct config_group *parent_group)
+{
+	struct config_group *child_group;
+	struct cxi_cfg_teardown_marker marker;
+	unsigned long flags;
+
+	/*
+	 * Unregistering a child unlinks it from cg_children, so the list
+	 * is re-read each time round instead of being walked across the
+	 * unlocked section.
+	 */
+	while ((child_group = get_first_child_config_group(parent_group, &marker))) {
+		unregister_all_sub_config_groups_recur(child_group);
+		configfs_unregister_group(child_group);
+
+		spin_lock_irqsave(&cxi_cfg_teardown_lock, flags);
+		list_del_init(&marker.list);
+		spin_unlock_irqrestore(&cxi_cfg_teardown_lock, flags);
+
+		/* The reference taken by get_first_child_config_group() */
+		config_item_put(&child_group->cg_item);
+		/* The creator's reference, as before */
+		config_item_put(&child_group->cg_item);
+	}
+}
+
+void cxi_configfs_cleanup(struct cass_dev *hw)
+{
+	struct cxi_cfg_group_item *dev_dir = hw->cfg_dev_dir;
+
+	if (!dev_dir)
+		return;
+	hw->cfg_dev_dir = NULL;
+	unregister_all_sub_config_groups_recur(&dev_dir->group);
+	configfs_unregister_group(&dev_dir->group);
+	config_item_put(&dev_dir->group.cg_item);
+}
+
+void cxi_configfs_exit(void)
+{
+	configfs_unregister_subsystem(&cxi_cfg_group_subsys);
+}
diff --git a/drivers/net/ethernet/hpe/ss1/cxi_core.c b/drivers/net/ethernet/hpe/ss1/cxi_core.c
new file mode 100644
index 000000000000..d46ab3a1df10
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cxi_core.c
@@ -0,0 +1,281 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2018,2024 Hewlett Packard Enterprise Development LP */
+
+#include <linux/module.h>
+#include <linux/debugfs.h>
+#include <linux/moduleparam.h>
+#include <linux/pci.h>
+
+#include "cxi_core.h"
+
+#define DEFAULT_PID_BITS MAX_PID_BITS
+
+/* TODO: Make this a per device configurable. */
+unsigned int pid_bits = DEFAULT_PID_BITS;
+module_param(pid_bits, uint, 0444);
+MODULE_PARM_DESC(pid_bits, "Width of the PID field within a NIC address");
+
+/* System info to determine if a system is mixed (C1 & C2)
+ * or homogeneous (only C1 or only C2).
+ */
+unsigned int system_type_identifier;
+module_param(system_type_identifier, uint, 0444);
+MODULE_PARM_DESC(system_type_identifier,
+		 "Identifies what type of Cassini NICs are present in the system\n"
+		"0 - Cassini 1 and Cassini 2 (Default)\n"
+		"1 - Cassini 1 Only\n"
+		"2 - Cassini 2 Only\n");
+
+unsigned int min_free_shift;
+module_param(min_free_shift, uint, 0444);
+MODULE_PARM_DESC(min_free_shift, "min_free shift (0 to 8)");
+
+unsigned int vni_matching;
+module_param(vni_matching, uint, 0444);
+MODULE_PARM_DESC(vni_matching, "vni matching configuration (0 to 3)");
+
+unsigned int tg_threshold[4] = { 0, 64, 128, 256 };
+module_param_array(tg_threshold, uint, NULL, 0644);
+MODULE_PARM_DESC(tg_threshold, "Array of 4 LPE append credits. Credits are 0 for immediate append, or 4 to 16383 for delayed append.");
+
+int untagged_eth_pcp = -1;
+module_param(untagged_eth_pcp, int, 0444);
+MODULE_PARM_DESC(untagged_eth_pcp, "PCP used by untagged Ethernet frames. Valid PCPs 0-7. Use -1 to use the PCP specified in chosen QOS Profile");
+
+bool switch_connected = true;
+module_param(switch_connected, bool, 0644);
+MODULE_PARM_DESC(switch_connected, "Connected to a switch or another NIC");
+
+struct class cxi_class = {
+	.name = "cxi",
+};
+
+/* For device naming purposes */
+atomic_t cxi_num = ATOMIC_INIT(-1);
+
+/* root debugfs directory for all devices */
+struct dentry *cxi_debug_dir;
+
+/* List of devices and its mutex. */
+static LIST_HEAD(dev_list);
+static DEFINE_MUTEX(dev_list_mutex);
+
+/* List of clients. Protected by dev_list_mutex. */
+static LIST_HEAD(client_list);
+
+/* Include here as p2p support is optional and we don't build the p2p file
+ * when it's disabled, but still need the ops struct itself */
+struct cass_p2p_ops p2p_ops = {
+	.get_pages = NULL,
+	.put_pages = NULL,
+	.is_device_mem = NULL,
+};
+
+int cxi_get_lpe_append_credits(unsigned int lpe_cdt_thresh_id)
+{
+	if (lpe_cdt_thresh_id >= ARRAY_SIZE(tg_threshold))
+		return -EINVAL;
+	return tg_threshold[lpe_cdt_thresh_id];
+}
+EXPORT_SYMBOL(cxi_get_lpe_append_credits);
+
+/**
+ * cxi_register_client() - Register a CXI client
+ *
+ * @client: client to be registered
+ */
+int cxi_register_client(struct cxi_client *client)
+{
+	struct cxi_dev *dev;
+
+	mutex_lock(&dev_list_mutex);
+
+	list_add_tail(&client->list, &client_list);
+
+	list_for_each_entry(dev, &dev_list, dev_list)
+		if (client->add)
+			client->add(dev);
+
+	mutex_unlock(&dev_list_mutex);
+
+	return 0;
+}
+EXPORT_SYMBOL(cxi_register_client);
+
+/**
+ * cxi_unregister_client() - Unregister a CXI client
+ *
+ * @client: client to be unregistered
+ */
+void cxi_unregister_client(struct cxi_client *client)
+{
+	struct cxi_dev *dev;
+
+	mutex_lock(&dev_list_mutex);
+
+	list_for_each_entry_reverse(dev, &dev_list, dev_list)
+		if (client->remove)
+			client->remove(dev);
+
+	list_del(&client->list);
+
+	mutex_unlock(&dev_list_mutex);
+}
+EXPORT_SYMBOL(cxi_unregister_client);
+
+/* A device driver is declaring a new CXI device */
+void cxi_add_device(struct cxi_dev *cdev)
+{
+	struct cxi_client *client;
+
+	mutex_lock(&dev_list_mutex);
+	list_add_tail(&cdev->dev_list, &dev_list);
+
+	list_for_each_entry(client, &client_list, list)
+		if (client->add)
+			client->add(cdev);
+
+	mutex_unlock(&dev_list_mutex);
+}
+
+/* A device driver signals it's going away. */
+void cxi_remove_device(struct cxi_dev *cdev)
+{
+	struct cxi_client *client;
+
+	mutex_lock(&dev_list_mutex);
+	list_del(&cdev->dev_list);
+
+	list_for_each_entry_reverse(client, &client_list, list)
+		if (client->remove)
+			client->remove(cdev);
+
+	mutex_unlock(&dev_list_mutex);
+}
+
+/* Send an asynchronous event to the clients */
+void cxi_send_async_event(struct cxi_dev *cdev, enum cxi_async_event event)
+{
+	struct cxi_client *client;
+
+	mutex_lock_nested(&dev_list_mutex, SINGLE_DEPTH_NESTING);
+
+	list_for_each_entry(client, &client_list, list)
+		if (client->async_event)
+			client->async_event(cdev, event);
+
+	mutex_unlock(&dev_list_mutex);
+}
+
+void cxi_apply_for_all(void (*callback)(struct cxi_dev *dev, void *p), void *p)
+{
+	struct cxi_dev *dev;
+
+	mutex_lock(&dev_list_mutex);
+
+	list_for_each_entry(dev, &dev_list, dev_list)
+		(*callback)(dev, p);
+
+	mutex_unlock(&dev_list_mutex);
+}
+
+static int __init cxi_init(void)
+{
+	int rc;
+	int i;
+
+	if (pid_bits > MAX_PID_BITS) {
+		pr_warn("PID count (%u) exceeded max (%u). Using default (%u).\n",
+			pid_bits, MAX_PID_BITS, DEFAULT_PID_BITS);
+		pid_bits = DEFAULT_PID_BITS;
+	}
+
+	if (pid_bits < MIN_PID_BITS) {
+		pr_warn("PID bits (%u) less than min (%u). Using default (%u).\n",
+			pid_bits, MIN_PID_BITS, DEFAULT_PID_BITS);
+		pid_bits = DEFAULT_PID_BITS;
+	}
+
+	if (untagged_eth_pcp > 7 || untagged_eth_pcp < -1) {
+		pr_err("Invalid untagged Ethernet PCP value: %u\n",
+		       untagged_eth_pcp);
+		return -EINVAL;
+	}
+
+	if (min_free_shift > 8) {
+		pr_warn("min_free_shift (%d) must be 0 to 8.\n",
+			min_free_shift);
+		return -EINVAL;
+	}
+
+	if (vni_matching > 3) {
+		pr_warn("vni_matching (%d) must be 0 to 3.\n", vni_matching);
+		return -EINVAL;
+	}
+
+	for (i = 0; i < ARRAY_SIZE(tg_threshold); i++) {
+		if ((tg_threshold[i] >= 1 && tg_threshold[i] <= 3) ||
+		    tg_threshold[i] > 16383) {
+			pr_warn("tg_threshold must be 0 or 4 to 16383\n");
+			return -EINVAL;
+		}
+	}
+
+	cxi_debug_dir = debugfs_create_dir("cxi", NULL);
+
+	rc = class_register(&cxi_class);
+	if (rc) {
+		pr_warn("Couldn't create Cray eXascale Interconnect device class\n");
+		goto err_class_reg;
+	}
+
+	rc = cxi_configfs_subsys_init();
+	if (rc) {
+		pr_err("Error while registering configfs subsystem\n");
+		goto err_configfs_reg;
+	}
+
+	rc = hw_register();
+	if (rc < 0) {
+		pr_err("Driver registration failed\n");
+		goto err_drv_reg;
+	}
+
+	if (!(system_type_identifier == CASSINI_1_ONLY ||
+	      system_type_identifier == CASSINI_2_ONLY ||
+		system_type_identifier == CASSINI_MIX)) {
+		pr_warn("Unknown system_type_identifier (%u). Using default (%u).\n",
+			system_type_identifier, CASSINI_MIX);
+		system_type_identifier = CASSINI_MIX;
+	}
+
+	return 0;
+
+err_drv_reg:
+	cxi_configfs_exit();
+err_configfs_reg:
+	class_unregister(&cxi_class);
+
+err_class_reg:
+	debugfs_remove(cxi_debug_dir);
+
+	cxi_p2p_fini();
+
+	return rc;
+}
+
+static void __exit cxi_exit(void)
+{
+	hw_unregister();
+	class_unregister(&cxi_class);
+	cxi_configfs_exit();
+	debugfs_remove(cxi_debug_dir);
+	cxi_p2p_fini();
+}
+
+module_init(cxi_init);
+module_exit(cxi_exit);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Cray Cassini Nic Driver");
+MODULE_AUTHOR("Cray Inc.");
diff --git a/drivers/net/ethernet/hpe/ss1/cxi_link.c b/drivers/net/ethernet/hpe/ss1/cxi_link.c
new file mode 100644
index 000000000000..8d53bbb2f027
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cxi_link.c
@@ -0,0 +1,227 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Cassini LINK
+ * Copyright 2022, 2024-2026 Hewlett Packard Enterprise Development LP
+ */
+
+#include <linux/kernel.h>
+#include <linux/hpe/cxi/cxi.h>
+
+#include "cass_core.h"
+#include "cass_sbl.h"
+#include "cass_sl.h"
+#include "cxi_ethtool.h"
+
+static const struct cxi_link_ops cxi_link_ops_sbl = {
+	.init = cass_sbl_init,
+	.link_start = cass_sbl_link_start,
+	.link_fini = cass_sbl_link_fini,
+	.mode_get  = cass_sbl_mode_get,
+	.mode_set  = cass_sbl_mode_set,
+	.flags_get = cass_sbl_get_debug_flags,
+	.flags_set = cass_sbl_set_debug_flags,
+	.flags_supported = LINK_DEBUG_FLAGS,
+	.link_up   = cass_sbl_power_on,
+	.link_down = cass_sbl_power_off,
+	.is_pcs_aligned = cass_sbl_pml_pcs_aligned,
+	.media_config = cass_sbl_media_config,
+	.media_unconfig = cass_sbl_media_unconfig,
+	.link_config  = cass_sbl_link_config,
+	.link_reset = cass_sbl_reset,
+	.link_exit = cass_sbl_exit_legacy,
+	.pml_recovery_set = cass_sbl_pml_recovery_set,
+	.is_link_up = cass_sbl_is_link_up,
+	.eth_name_set = cass_sbl_set_eth_name,
+};
+
+static void cass_sl_exit_legacy(struct cass_dev *hw)
+{
+	int rtn = cass_sl_exit(hw);
+
+	if (rtn)
+		WARN(1, "Cassini SL exit failed: %d\n", rtn);
+}
+
+static const struct cxi_link_ops cxi_link_ops_sl = {
+	.init               = cass_sl_init,
+	.link_start         = cass_sbl_link_start, /* TODO - temporary */
+	.link_fini          = cass_sl_link_fini,
+	.mode_get           = cass_sl_mode_get,
+	.mode_set           = cass_sl_mode_set,
+	.flags_get          = cass_sl_flags_get,
+	.flags_set          = cass_sl_flags_set,
+	.flags_supported    = 0,
+	.link_up            = cass_sl_link_up,
+	.link_down          = cass_sl_link_down,
+	.is_pcs_aligned     = cass_sl_is_pcs_aligned,
+	.media_config       = cass_sl_media_config,
+	.media_unconfig     = cass_sl_media_unconfig,
+	.link_config        = cass_sl_link_config,
+	.link_reset         = cass_sl_link_down,
+	.link_exit          = cass_sl_exit_legacy,
+	.pml_recovery_set   = cass_sl_pml_recovery_set,
+	.is_link_up	    = cass_sl_is_link_up,
+	.eth_name_set	    = cass_sl_connect_id_set,
+};
+
+void cxi_set_link_ops(struct cass_dev *hw)
+{
+	if (cass_version(hw, CASSINI_1))
+		hw->link_ops = &cxi_link_ops_sbl;
+	else
+		hw->link_ops = &cxi_link_ops_sl;
+}
+
+void cxi_link_mode_get(struct cxi_dev *cxi_dev, struct cxi_link_info *link_info)
+{
+	struct cass_dev *hw = container_of(cxi_dev, struct cass_dev, cdev);
+
+	hw->link_ops->mode_get(hw, link_info);
+}
+EXPORT_SYMBOL(cxi_link_mode_get);
+
+void cxi_link_mode_set(struct cxi_dev *cxi_dev, const struct cxi_link_info *link_info)
+{
+	struct cass_dev *hw = container_of(cxi_dev, struct cass_dev, cdev);
+
+	hw->link_ops->mode_set(hw, link_info);
+}
+EXPORT_SYMBOL(cxi_link_mode_set);
+
+void cxi_link_flags_get(struct cxi_dev *cxi_dev, u32 *flags)
+{
+	struct cass_dev *hw = container_of(cxi_dev, struct cass_dev, cdev);
+
+	hw->link_ops->flags_get(hw, flags);
+}
+EXPORT_SYMBOL(cxi_link_flags_get);
+
+void cxi_link_flags_set(struct cxi_dev *cxi_dev, u32 clr_flags, u32 set_flags)
+{
+	struct cass_dev *hw = container_of(cxi_dev, struct cass_dev, cdev);
+
+	hw->link_ops->flags_set(hw, clr_flags, set_flags);
+}
+EXPORT_SYMBOL(cxi_link_flags_set);
+
+u32 cxi_link_flags_supported(struct cxi_dev *cxi_dev)
+{
+	struct cass_dev *hw = container_of(cxi_dev, struct cass_dev, cdev);
+
+	return hw->link_ops->flags_supported;
+}
+EXPORT_SYMBOL(cxi_link_flags_supported);
+
+void cxi_link_use_unsupported_cable(struct cxi_dev *cxi_dev, bool use)
+{
+	struct cass_dev *hw = container_of(cxi_dev, struct cass_dev, cdev);
+
+	cxidev_dbg(&hw->cdev, "use unsupported cable\n");
+
+	if (use)
+		hw->sl.link_policy.options |= SL_LINK_POLICY_OPT_USE_UNSUPPORTED_CABLE;
+	else
+		hw->sl.link_policy.options &= ~SL_LINK_POLICY_OPT_USE_UNSUPPORTED_CABLE;
+}
+EXPORT_SYMBOL(cxi_link_use_unsupported_cable);
+
+void cxi_link_use_supported_ss200_cable(struct cxi_dev *cxi_dev, bool use)
+{
+	struct cass_dev *hw = container_of(cxi_dev, struct cass_dev, cdev);
+
+	cxidev_dbg(&hw->cdev, "use supported ss200 cable\n");
+
+	if (use)
+		hw->sl.link_policy.options |= SL_LINK_POLICY_OPT_USE_SUPPORTED_SS200_CABLE;
+	else
+		hw->sl.link_policy.options &= ~SL_LINK_POLICY_OPT_USE_SUPPORTED_SS200_CABLE;
+}
+EXPORT_SYMBOL(cxi_link_use_supported_ss200_cable);
+
+void cxi_link_ignore_media_error(struct cxi_dev *cxi_dev, bool ignore)
+{
+	struct cass_dev *hw = container_of(cxi_dev, struct cass_dev, cdev);
+
+	cxidev_dbg(&hw->cdev, "ignore media error\n");
+
+	if (ignore)
+		hw->sl.link_policy.options |= SL_LINK_POLICY_OPT_IGNORE_MEDIA_ERROR;
+	else
+		hw->sl.link_policy.options &= ~SL_LINK_POLICY_OPT_IGNORE_MEDIA_ERROR;
+}
+EXPORT_SYMBOL(cxi_link_ignore_media_error);
+
+void cxi_link_auto_lane_degrade(struct cxi_dev *cxi_dev, bool enable)
+{
+	struct cass_dev *hw = container_of(cxi_dev, struct cass_dev, cdev);
+
+	cxidev_dbg(&hw->cdev, "auto lane degrade\n");
+
+	if (enable)
+		hw->sl.link_config.options |= SL_LINK_CONFIG_OPT_ALD_ENABLE;
+	else
+		hw->sl.link_config.options &= ~SL_LINK_CONFIG_OPT_ALD_ENABLE;
+}
+EXPORT_SYMBOL(cxi_link_auto_lane_degrade);
+
+void cxi_pml_recovery_set(struct cxi_dev *cxi_dev, bool set)
+{
+	struct cass_dev *hw = container_of(cxi_dev, struct cass_dev, cdev);
+
+	hw->link_ops->pml_recovery_set(hw, set);
+}
+EXPORT_SYMBOL(cxi_pml_recovery_set);
+
+void cxi_link_los_lol_hide(struct cxi_dev *cxi_dev, bool enable)
+{
+	struct cass_dev *hw = container_of(cxi_dev, struct cass_dev, cdev);
+
+	cxidev_dbg(&hw->cdev, "los_lol_hide\n");
+
+	if (enable)
+		hw->sl.link_config.options |= SL_LINK_CONFIG_OPT_LOS_LOL_UP_FAIL_HIDE;
+	else
+		hw->sl.link_config.options &= ~SL_LINK_CONFIG_OPT_LOS_LOL_UP_FAIL_HIDE;
+}
+EXPORT_SYMBOL(cxi_link_los_lol_hide);
+
+/**
+ * cxi_is_link_up_vf() - Query the PF for the current link state
+ *
+ * @cdev: VF CXI device
+ *
+ * Return: true if the link is up, false otherwise or on error.
+ */
+static bool cxi_is_link_up_vf(struct cxi_dev *cdev)
+{
+	const struct cxi_eth_link_state_get_cmd cmd = {
+		.op = CXI_OP_ETH_LINK_STATE_GET,
+	};
+	struct cxi_eth_get_link_state_resp resp = {};
+	size_t resp_len = sizeof(resp);
+	int rc;
+
+	rc = cxi_send_msg_to_pf(cdev, &cmd, sizeof(cmd), &resp, &resp_len);
+	if (rc)
+		return false;
+
+	return !!resp.link_up;
+}
+
+/**
+ * cxi_is_link_up() - Returns whether the link is up or down
+ *
+ * @cdev: the device
+ *
+ * Return: true if the link is up, false otherwise.
+ */
+bool cxi_is_link_up(struct cxi_dev *cdev)
+{
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+
+	if (!cdev->is_physfn)
+		return cxi_is_link_up_vf(cdev);
+
+	return hw->link_ops->is_link_up(hw);
+}
+EXPORT_SYMBOL(cxi_is_link_up);

-- 
2.56.0


^ permalink raw reply	[flat|nested] 25+ messages in thread
* [PATCH 21/23] net: hpe: ss1: add resource groups, QoS and services
  2026-10-30 20:58 [PATCH 00/23] Subject: [PATCH net-next 00/23] net/hpe: add HPE Slingshot NIC drivers Doug Ledford
                   ` (19 preceding siblings ...)
  2026-10-30 20:59 ` [PATCH 20/23] net: hpe: ss1: add the CXI core interfaces Doug Ledford
@ 2026-10-30 20:59 ` Doug Ledford
  2026-10-30 20:59 ` [PATCH 22/23] net: hpe: ss1: add the Ethernet personality Doug Ledford
                   ` (2 subsequent siblings)
  23 siblings, 0 replies; 25+ messages in thread
From: Doug Ledford @ 2026-10-30 20:59 UTC (permalink / raw)
  To: Slingshot Open Source Team, Nathan Chancellor, Nicolas Schier,
	Richard Cochran, Andrew Lunn, David S. Miller, Eric Dumazet,
	Jakub Kicinski, Paolo Abeni, Sumit Semwal, Christian König,
	Guenter Roeck
  Cc: linux-kernel, netdev, linux-kbuild, Doug Ledford, Sandeep Bhoot,
	Mamila Santosh

Add the remaining core resources: resource groups and IDs, QoS
profiles, traffic classes, services and their access control lists,
local network interfaces (LNI), portals, communication profiles, error
handling, ODP/HMM, telemetry and the PCIe, link and ASIC monitors.

Known limitation, deferred to V2: this patch carries SR-IOV
virtual-function code (VF-to-PF mailbox requests, mailbox opcodes or VF
resource handling) from an older, incomplete version of the Cassini
SR-IOV support. V2 of this series will include the updated SR-IOV
implementation, so issues in the VF paths should be ignored for now.

checkpatch --strict (100 columns) still reports the following in this
patch. They need coordination with the internal repositories this code
is maintained in and will be fixed in V2:
- WARNING: LONG_LINE (20), ALLOC_WITH_SIZEOF (13), CONST_STRUCT (9),
  ENOTSUPP (5), DEPRECATED_API (3), SPLIT_STRING (1), STRCPY (1)
- CHECK: BRACES (16), UNNECESSARY_PARENTHESES (11), OPEN_ENDED_LINE (9),
  COMPARISON_TO_NULL (6), MACRO_ARG_REUSE (5), ALLOC_SIZEOF_STRUCT (3),
  ASSIGNMENT_CONTINUATIONS (1), BIT_MACRO (1), MACRO_ARG_PRECEDENCE (1),
  MULTIPLE_ASSIGNMENTS (1)

Co-developed-by: Sandeep Bhoot <sandeep.bhoot@hpe.com>
Signed-off-by: Sandeep Bhoot <sandeep.bhoot@hpe.com>
Co-developed-by: Mamila Santosh <santosh-kumar.mamila@hpe.com>
Signed-off-by: Mamila Santosh <santosh-kumar.mamila@hpe.com>
Signed-off-by: Doug Ledford <doug.ledford@hpe.com>
---
 drivers/net/ethernet/hpe/ss1/cass_cpt.c          |  585 +++++
 drivers/net/ethernet/hpe/ss1/cass_dma_buf.c      |  256 ++
 drivers/net/ethernet/hpe/ss1/cass_errors.c       | 1155 +++++++++
 drivers/net/ethernet/hpe/ss1/cass_eth.c          |  702 ++++++
 drivers/net/ethernet/hpe/ss1/cass_hmm.c          |  320 +++
 drivers/net/ethernet/hpe/ss1/cass_hni.c          |  370 +++
 drivers/net/ethernet/hpe/ss1/cass_ixe.c          |  348 +++
 drivers/net/ethernet/hpe/ss1/cass_lmon.c         |  573 +++++
 drivers/net/ethernet/hpe/ss1/cass_lni.c          |  404 ++++
 drivers/net/ethernet/hpe/ss1/cass_odp_decouple.c |  599 +++++
 drivers/net/ethernet/hpe/ss1/cass_pcie_mon.c     |  288 +++
 drivers/net/ethernet/hpe/ss1/cass_pt.c           | 1255 ++++++++++
 drivers/net/ethernet/hpe/ss1/cass_ptp.c          |  304 +++
 drivers/net/ethernet/hpe/ss1/cass_rgid.c         |  293 +++
 drivers/net/ethernet/hpe/ss1/cass_rgroup.c       |  281 +++
 drivers/net/ethernet/hpe/ss1/cass_sbus.c         |  172 ++
 drivers/net/ethernet/hpe/ss1/cass_svc.c          | 2011 ++++++++++++++++
 drivers/net/ethernet/hpe/ss1/cass_sysfs.c        |  849 +++++++
 drivers/net/ethernet/hpe/ss1/cass_tc.c           | 2780 ++++++++++++++++++++++
 drivers/net/ethernet/hpe/ss1/cass_telem.c        |  309 +++
 drivers/net/ethernet/hpe/ss1/cass_uc.c           | 1933 +++++++++++++++
 drivers/net/ethernet/hpe/ss1/cxi_ac_entry_list.c |  499 ++++
 drivers/net/ethernet/hpe/ss1/cxi_qos_profiles.c  |  722 ++++++
 drivers/net/ethernet/hpe/ss1/cxi_rgroup.c        | 1791 ++++++++++++++
 drivers/net/ethernet/hpe/ss1/cxi_rx_profile.c    |  833 +++++++
 drivers/net/ethernet/hpe/ss1/cxi_tx_profile.c    |  819 +++++++
 26 files changed, 20451 insertions(+)

diff --git a/drivers/net/ethernet/hpe/ss1/cass_cpt.c b/drivers/net/ethernet/hpe/ss1/cass_cpt.c
new file mode 100644
index 000000000000..b63143dd8a62
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_cpt.c
@@ -0,0 +1,585 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2018, 2024-2026 Hewlett Packard Enterprise Development LP */
+
+/* Communication Profile Table (CPT) management */
+
+#include <linux/iopoll.h>
+#include "cass_core.h"
+
+#define ENABLED_PFQ 0
+
+static int cass_cp_clear_table(int id, void *ptr, void *data)
+{
+	struct cass_cp *cp = ptr;
+	struct cass_dev *hw = data;
+	const union c_cq_cfg_cp_table cp_cfg = {};
+
+	cass_set_cp_table(hw, cp->id, &cp_cfg);
+
+	return 0;
+}
+
+/**
+ * cass_clear_cps() - Walk list of Communication profiles and clear
+ *                    the entries.
+ *
+ * @tx_profile: TX profile to clean
+ */
+void cass_clear_cps(struct cxi_tx_profile *tx_profile)
+	__must_hold(&hw->cp_lock)
+{
+	struct cass_dev *hw = tx_profile->config.hw;
+
+	idr_for_each(&tx_profile->config.cass_cp_table, &cass_cp_clear_table,
+		     hw);
+}
+
+struct vni_tc_data {
+	unsigned int vni_pcp;
+	unsigned int tc;
+	enum cxi_traffic_class_type tc_type;
+};
+
+/**
+ * cass_cp_free() - Free a communication profile.
+ *
+ * @cp: Communication profile to be freed.
+ */
+static void cass_cp_free(struct cass_cp *cp)
+{
+	struct cass_dev *hw = cp->hw;
+	const union c_cq_cfg_cp_table cp_cfg = {};
+
+	cxidev_dbg(&hw->cdev, "%s cp freed: cp=%u vni_pcp=%u label=%u\n",
+		   hw->cdev.name, cp->id, cp->vni_pcp, cp->tc);
+
+	cass_set_cp_table(hw, cp->id, &cp_cfg);
+
+	if (!cp->tx_profile->config.exclusive_cp)
+		idr_remove(&cp->tx_profile->config.cass_cp_table, cp->list_id);
+
+	ida_free(&hw->cp_table, cp->id);
+
+	kfree(cp);
+}
+
+/**
+ * cass_cp_alloc() - Allocate a new communication profile.
+ *
+ * @tx_profile: TX profile object
+ * @vni_pcp: VNI for communication profile. If using an ethernet tc,
+ * this argument is treated as PCP.
+ * @tc: Traffic class for communication profile.
+ * @tc_type: Traffic class type for communication profile.
+ *
+ * @return: Valid pointer on success. Else, negative errno value.
+ */
+static struct cass_cp *cass_cp_alloc(struct cxi_tx_profile *tx_profile,
+				     unsigned int vni_pcp,
+				     unsigned int tc,
+				     enum cxi_traffic_class_type tc_type)
+	__must_hold(&hw->cp_lock)
+{
+	struct cass_cp *cp;
+	unsigned int cp_id;
+	int rc;
+	struct cass_dev *hw = tx_profile->config.hw;
+	union c_cq_cfg_cp_table cp_cfg = {
+		.valid = 1,
+		.hrp_vld = tc_type == CXI_TC_TYPE_HRP,
+	};
+	union c_cq_cfg_cp_fl_table flow_cfg = {};
+	struct cass_tc_cfg tc_cfg;
+
+	rc = cass_tc_find(hw, tc, tc_type, vni_pcp, &tc_cfg);
+	if (rc) {
+		cxidev_dbg(&hw->cdev, "%s TC mapping does not exist, TC: %s TYPE: %s",
+			   hw->cdev.name, cxi_tc_to_str(tc),
+			   cxi_tc_type_to_str(tc_type));
+		return ERR_PTR(-EINVAL);
+	}
+
+	cp = kzalloc(sizeof(*cp), GFP_KERNEL);
+	if (!cp)
+		return ERR_PTR(-ENOMEM);
+
+	rc = ida_alloc_range(&hw->cp_table, 1, C_CQ_CFG_CP_TABLE_ENTRIES - 1,
+			     GFP_KERNEL);
+	if (rc < 0) {
+		cxidev_dbg(&hw->cdev,
+			   "%s hardware communication profiles exhausted\n",
+			   hw->cdev.name);
+		goto error_free_cp;
+	}
+
+	cp_id = rc;
+
+	if (!tx_profile->config.exclusive_cp) {
+		rc = idr_alloc(&tx_profile->config.cass_cp_table, cp, 1, 0, GFP_KERNEL);
+		if (rc < 0)
+			goto error_remove_ida;
+	}
+
+	refcount_set(&cp->ref, 1);
+
+	cp->list_id = rc;
+	cp->id = cp_id;
+	cp->vni_pcp = vni_pcp;
+	cp->tc = tc;
+	cp->tc_type = tc_type;
+	cp->hw = hw;
+	cp->tx_profile = tx_profile;
+
+	cp_cfg.vni = vni_pcp;
+	cp_cfg.dscp_unrsto = tc_cfg.unres_req_dscp;
+	cp_cfg.dscp_rstuno = tc_cfg.res_req_dscp;
+
+	if (is_eth_tc(tc)) {
+		cp_cfg.srb_disabled = 1;
+		cp_cfg.sct_disabled = 1;
+		cp_cfg.smt_disabled = 1;
+	}
+
+	cass_set_cp_table(hw, cp_id, &cp_cfg);
+
+	flow_cfg.pfq = tc_cfg.ocuset;
+	flow_cfg.tc = tc_cfg.cq_tc;
+
+	cass_set_cp_fl_table(hw, cp_id, &flow_cfg);
+
+	cxidev_dbg(&hw->cdev,
+		   "%s cp allocated: tc=%s tc_type=%s cp=%u vni_pcp=%u label=%u tc=%u pfq=%u exclusive=%u\n",
+		   hw->cdev.name, cxi_tc_to_str(tc),
+		   cxi_tc_type_to_str(tc_type), cp->id, cp->vni_pcp, cp->tc,
+		   flow_cfg.tc, flow_cfg.pfq, cp->tx_profile->config.exclusive_cp);
+
+	return cp;
+
+error_remove_ida:
+	ida_free(&hw->cp_table, cp_id);
+error_free_cp:
+	kfree(cp);
+
+	return ERR_PTR(rc);
+}
+
+/**
+ * cass_cp_put() - Put a communication profile.
+ *
+ * @cp: Communication profile where reference should be put.
+ */
+static void cass_cp_put(struct cass_cp *cp)
+	__must_hold(&hw->cp_lock)
+{
+	if (refcount_dec_and_test(&cp->ref))
+		cass_cp_free(cp);
+}
+
+static int cp_match(int id, void *ptr, void *data)
+{
+	struct cass_cp *cp = ptr;
+	struct vni_tc_data *vni_tc = data;
+
+	if (vni_tc->vni_pcp == cp->vni_pcp &&
+	    vni_tc->tc == cp->tc &&
+	    vni_tc->tc_type == cp->tc_type)
+		return cp->list_id;
+
+	return 0;
+}
+
+/**
+ * cass_cp_get() - Get a communication profile.
+ *
+ * @tx_profile: TX profile
+ * @vni_pcp: VNI for communication profile. If using an ethernet tc,
+ *           this argument is treated as PCP.
+ * @tc: Traffic class for communication profile.
+ * @tc_type: Traffic class type for communication profile.
+ *
+ * Reusing communication profiles is preferred over allocating a new one.
+ *
+ * @return: Valid pointer on success. Else, negative errno value.
+ */
+static struct cass_cp *cass_cp_get(struct cxi_tx_profile *tx_profile,
+				   unsigned int vni_pcp,
+				   unsigned int tc,
+				   enum cxi_traffic_class_type tc_type)
+	__must_hold(&hw->cp_lock)
+{
+	int id;
+	struct cass_cp *cp;
+	struct vni_tc_data data = {
+		.vni_pcp = vni_pcp,
+		.tc = tc,
+		.tc_type = tc_type
+	};
+
+	if (tx_profile->config.exclusive_cp)
+		return cass_cp_alloc(tx_profile, vni_pcp, tc, tc_type);
+
+	id = idr_for_each(&tx_profile->config.cass_cp_table, &cp_match, &data);
+	if (id) {
+		cp = idr_find(&tx_profile->config.cass_cp_table, id);
+		if (!cp) {
+			pr_err("Could not find id %d\n", id);
+			return ERR_PTR(-ENOENT);
+		}
+
+		refcount_inc(&cp->ref);
+
+		return cp;
+	}
+
+	return cass_cp_alloc(tx_profile, vni_pcp, tc, tc_type);
+}
+
+/**
+ * cxi_trig_cp_alloc_vf() - Allocate a communication profile with type of
+ *                          LCID parameter for VF
+ *
+ * @lni: LNI the communication profile should be mapped into
+ * @vni_pcp: VNI of communication profile. If using an ethernet tc
+ * this argument is treated as PCP.
+ * @tc: Traffic class of the communication profile
+ * @tc_type: Traffic class type of the communication profile
+ * @cp_type: NON_TRIG_LCID and any LCID for ANY_LCID.
+ *
+ * Note: Allocating communication profiles with the same LNI, VNI, TC, and TC
+ * type will result in a redundant communication profile being mapped into the
+ * LNI.
+ *
+ * @return: Valid pointer on success. Else, negative errno value.
+ */
+static struct cxi_cp *cxi_trig_cp_alloc_vf(struct cxi_lni *lni, unsigned int vni_pcp,
+					   unsigned int tc,
+					   enum cxi_traffic_class_type tc_type,
+					   enum cxi_trig_cp cp_type)
+{
+	struct cxi_lni_priv_vf *lni_priv_vf =
+		container_of(lni, struct cxi_lni_priv_vf, lni);
+	struct cxi_dev *dev = lni_priv_vf->dev;
+	struct cxi_cp_priv_vf *cp_priv_vf;
+	const struct cxi_trig_cp_alloc_cmd cmd = {
+		.op = CXI_OP_TRIG_CP_ALLOC,
+		.lni = lni_priv_vf->lni.id,
+		.vni = vni_pcp,
+		.tc = tc,
+		.tc_type = tc_type,
+		.cp_type = cp_type
+	};
+	struct cxi_cp_alloc_resp resp;
+	size_t resp_len = sizeof(resp);
+	int rc;
+
+	cp_priv_vf = kzalloc(sizeof(*cp_priv_vf), GFP_KERNEL);
+	if (!cp_priv_vf)
+		return ERR_PTR(-ENOMEM);
+
+	rc = cxi_send_msg_to_pf(dev, &cmd, sizeof(cmd), &resp, &resp_len);
+	if (rc)
+		goto error_out;
+
+	cp_priv_vf->dev = dev;
+	cp_priv_vf->cp_hndl = resp.cp_hndl;
+	cp_priv_vf->cp.vni_pcp = vni_pcp;
+	cp_priv_vf->cp.tc = tc;
+	cp_priv_vf->cp.tc_type = tc_type;
+	cp_priv_vf->cp.lcid = resp.lcid;
+
+	return &cp_priv_vf->cp;
+
+error_out:
+	kfree(cp_priv_vf);
+
+	return ERR_PTR(rc);
+}
+
+/**
+ * cxi_trig_cp_alloc() - Allocate a communication profile with type of
+ *                       LCID parameter
+ *
+ * @lni: LNI the communication profile should be mapped into
+ * @vni_pcp: VNI of communication profile. If using an ethernet tc
+ * this argument is treated as PCP.
+ * @tc: Traffic class of the communication profile
+ * @tc_type: Traffic class type of the communication profile
+ * @cp_type: Return CP with LCID 0 for TRIG_LCID, a non-0 LCID for
+ *           NON_TRIG_LCID and any LCID for ANY_LCID.
+ *
+ * Note: Allocating communication profiles with the same LNI, VNI, TC, and TC
+ * type will result in a redundant communication profile being mapped into the
+ * LNI.
+ *
+ * @return: Valid pointer on success. Else, negative errno value.
+ */
+struct cxi_cp *cxi_trig_cp_alloc(struct cxi_lni *lni, unsigned int vni_pcp,
+				 unsigned int tc,
+				 enum cxi_traffic_class_type tc_type,
+				 enum cxi_trig_cp cp_type)
+{
+	struct cxi_lni_priv *lni_priv = container_of(lni, struct cxi_lni_priv,
+						     lni);
+	struct cxi_dev *dev = lni_priv->dev;
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+	struct cass_cp *cass_cp;
+	struct cxi_cp_priv *cp_priv;
+	struct cxi_tx_profile *tx_profile = NULL;
+	int rc;
+	int lcid;
+
+	if (!dev->is_physfn)
+		return cxi_trig_cp_alloc_vf(lni, vni_pcp, tc, tc_type, cp_type);
+
+	if (tc < 0 || tc >= CXI_ETH_TC_MAX || tc_type < 0 ||
+	    tc_type >= CXI_TC_TYPE_MAX)
+		return ERR_PTR(-EINVAL);
+
+	/* Specific traffic class checks. */
+	if (is_eth_tc(tc)) {
+		/* Only 8 PCPs (0-7) are supported. */
+		if (vni_pcp > 7)
+			return ERR_PTR(-EINVAL);
+		else if (!capable(CAP_NET_RAW))
+			return ERR_PTR(-EPERM);
+
+		tx_profile = cxi_dev_get_eth_tx_profile(&hw->cdev);
+	} else {
+		if (!is_vni_valid(vni_pcp)) {
+			pr_debug("Invalid vni:%d\n", vni_pcp);
+			return ERR_PTR(-EINVAL);
+		}
+
+		tx_profile = cxi_dev_get_tx_profile(&hw->cdev, vni_pcp);
+		if (IS_ERR(tx_profile)) {
+			rc = PTR_ERR(tx_profile);
+			pr_debug("tx_profile not found for vni:%d rc:%d\n",
+				 vni_pcp, rc);
+			return ERR_PTR(rc);
+		}
+
+		if (!cxi_tx_profile_valid_tc(tx_profile, tc)) {
+			pr_debug("Invalid tc:%d for tx_profile ID:%d\n", tc,
+				 tx_profile->profile_common.id);
+			rc = -EINVAL;
+			goto free_tx_profile;
+		}
+	}
+
+	mutex_lock(&hw->cp_lock);
+	cp_priv = cass_cp_rgid_find(hw, lni_priv, vni_pcp, tc, tc_type,
+				    cp_type);
+	if (cp_priv) {
+		mutex_unlock(&hw->cp_lock);
+		pr_debug("Reuse cp:%u cp_type:%d rgid:%u lcid:%u refcount:%d\n",
+			 cp_priv->cass_cp->id, cp_type, cp_priv->rgid,
+			 cp_priv->cp.lcid, refcount_read(&cp_priv->refcount));
+		return &cp_priv->cp;
+	}
+
+	cp_priv = kzalloc(sizeof(*cp_priv), GFP_KERNEL);
+	if (!cp_priv) {
+		mutex_unlock(&hw->cp_lock);
+		return ERR_PTR(-ENOMEM);
+	}
+
+	cp_priv->dev = dev;
+	cp_priv->rgid = lni_priv->lni.rgid;
+	cp_priv->lni_id = lni_priv->lni.id;
+	cp_priv->cp.vni_pcp = vni_pcp;
+	cp_priv->cp.tc = tc;
+	cp_priv->cp.tc_type = tc_type;
+	refcount_set(&cp_priv->refcount, 1);
+
+	/* Allocate the communication profile. */
+	cass_cp = cass_cp_get(tx_profile, vni_pcp, tc, tc_type);
+	if (IS_ERR(cass_cp)) {
+		rc = PTR_ERR(cass_cp);
+		goto free_cp_priv;
+	}
+
+	cp_priv->cass_cp = cass_cp;
+
+	/* Map the communication profile to LCID. */
+	lcid = cass_lcid_get(hw, cp_priv, lni_priv->lni.rgid, cp_type);
+	if (lcid < 0) {
+		cxidev_dbg(dev, "%s rgid=%u lcids exhausted\n", dev->name,
+			   lni_priv->lni.rgid);
+		rc = lcid;
+		goto free_cp;
+	}
+	cp_priv->cp.lcid = lcid;
+
+	mutex_unlock(&hw->cp_lock);
+
+	cass_set_cid(hw, lni_priv->lni.rgid, lcid, cass_cp->id);
+
+	cxidev_dbg(dev, "lcid allocated: lni:%d rgid=%u lcid=%u cp=%u cp_type:%d\n",
+		   lni_priv->lni.id, lni_priv->lni.rgid, cp_priv->cp.lcid, cass_cp->id,
+		   cp_type);
+
+	cass_flush_pci(hw);
+
+	return &cp_priv->cp;
+
+free_cp:
+	cass_cp_put(cass_cp);
+free_cp_priv:
+	mutex_unlock(&hw->cp_lock);
+	kfree(cp_priv);
+free_tx_profile:
+	cxi_tx_profile_dec_refcount(dev, tx_profile, true);
+
+	return ERR_PTR(rc);
+}
+EXPORT_SYMBOL(cxi_trig_cp_alloc);
+
+/**
+ * cxi_cp_alloc() - Allocate a communication profile
+ *
+ * @lni: LNI the communication profile should be mapped into
+ * @vni_pcp: VNI of communication profile. If using an ethernet tc
+ * this argument is treated as PCP.
+ * @tc: Traffic class of the communication profile
+ * @tc_type: Traffic class type of the communication profile
+ *
+ * Note: Allocating communication profiles with the same LNI, VNI, TC, and TC
+ * type will result in a redundant communication profile being mapped into the
+ * LNI.
+ *
+ * @return: Valid pointer on success. Else, negative errno value.
+ */
+struct cxi_cp *cxi_cp_alloc(struct cxi_lni *lni, unsigned int vni_pcp,
+			    unsigned int tc,
+			    enum cxi_traffic_class_type tc_type)
+{
+	return cxi_trig_cp_alloc(lni, vni_pcp, tc, tc_type, ANY_LCID);
+}
+EXPORT_SYMBOL(cxi_cp_alloc);
+
+/**
+ * cxi_cp_free_vf() - Free the communication profile for VF
+ *
+ * @cp: Communication profile to be freed
+ */
+static void cxi_cp_free_vf(struct cxi_cp *cp)
+{
+	struct cxi_cp_priv_vf *cp_priv_vf =
+		container_of(cp, struct cxi_cp_priv_vf, cp);
+	struct cxi_dev *dev = cp_priv_vf->dev;
+	const struct cxi_cp_free_cmd cmd = {
+		.op = CXI_OP_CP_FREE,
+		.cp_hndl = cp_priv_vf->cp_hndl,
+	};
+	size_t resp_len = 0;
+	int rc;
+
+	rc = cxi_send_msg_to_pf(dev, &cmd, sizeof(cmd), NULL, &resp_len);
+	if (rc)
+		return;
+
+	kfree(cp_priv_vf);
+}
+
+/**
+ * cxi_cp_free() - Free the communication profile
+ *
+ * @cp: Communication profile to be freed
+ */
+void cxi_cp_free(struct cxi_cp *cp)
+{
+	struct cxi_cp_priv *cp_priv = container_of(cp, struct cxi_cp_priv, cp);
+	struct cass_dev *hw;
+	struct cxi_tx_profile *tx_profile;
+
+	if (!cp_priv->dev->is_physfn) {
+		cxi_cp_free_vf(cp);
+		return;
+	}
+
+	hw = cp_priv->cass_cp->hw;
+	tx_profile = cp_priv->cass_cp->tx_profile;
+
+	cxi_tx_profile_dec_refcount(&hw->cdev, tx_profile, true);
+
+	mutex_lock(&hw->cp_lock);
+
+	if (!refcount_dec_and_test(&cp_priv->refcount)) {
+		mutex_unlock(&hw->cp_lock);
+		pr_debug("Return cp:%u rgid:%u lcid:%u refcount:%d\n",
+			 cp_priv->cass_cp->id, cp_priv->rgid,
+			 cp_priv->cp.lcid, refcount_read(&cp_priv->refcount));
+		return;
+	}
+
+	cxidev_dbg(&hw->cdev, "%s lcid freed: rgid=%u lcid=%u cp=%u\n",
+		   hw->cdev.name, cp_priv->rgid, cp_priv->cp.lcid,
+		   cp_priv->cass_cp->id);
+
+	cass_set_cid(hw, cp_priv->rgid, cp_priv->cp.lcid, 0);
+
+	cass_lcid_put(hw, cp_priv->rgid, cp_priv->cp.lcid);
+	cass_cp_put(cp_priv->cass_cp);
+
+	mutex_unlock(&hw->cp_lock);
+
+	kfree(cp_priv);
+
+	cass_flush_pci(hw);
+}
+EXPORT_SYMBOL(cxi_cp_free);
+
+int cxi_cp_modify(struct cxi_cp *cp, unsigned int vni_pcp)
+{
+	struct cxi_cp_priv *cp_priv = container_of(cp, struct cxi_cp_priv, cp);
+	struct cass_cp *cass_cp = cp_priv->cass_cp;
+	struct cass_dev *hw = cp_priv->cass_cp->hw;
+	int rc = 0;
+	struct cass_tc_cfg tc_cfg;
+	union c_cq_cfg_cp_table cp_cfg = {
+	      .valid = 1,
+	      .hrp_vld = cp->tc_type == CXI_TC_TYPE_HRP,
+	};
+
+	if (!cass_cp->tx_profile->config.exclusive_cp)
+		return -EINVAL;
+
+	if (is_eth_tc(cp->tc)) {
+		pr_debug("eth tc:%s for cp:%u is invalid for cp modify\n",
+			 cxi_tc_to_str(cp->tc), cass_cp->id);
+		return -EINVAL;
+	}
+
+	if (!cxi_valid_vni(&hw->cdev, CXI_PROF_TX, vni_pcp)) {
+		pr_debug("cp modify received invalid vni: %d for cp:%u\n",
+			 vni_pcp, cass_cp->id);
+		return -EINVAL;
+	}
+
+	rc = cass_tc_find(hw, cp->tc, cp->tc_type, vni_pcp, &tc_cfg);
+	if (rc) {
+		cxidev_dbg(&hw->cdev,
+			   "%s tc mapping does not exist for cp:%u vni_pcp:%u tc:%s tc_type:%s",
+			   hw->cdev.name, cass_cp->id, vni_pcp,
+			   cxi_tc_to_str(cp->tc),
+			   cxi_tc_type_to_str(cp->tc_type));
+		return -EINVAL;
+	}
+
+	cp->vni_pcp = vni_pcp;
+	cp_cfg.vni = vni_pcp;
+	cp_cfg.dscp_unrsto = tc_cfg.unres_req_dscp;
+	cp_cfg.dscp_rstuno = tc_cfg.res_req_dscp;
+
+	cass_set_cp_table(hw, cass_cp->id, &cp_cfg);
+
+	cxidev_dbg(&hw->cdev,
+		   "%s cp modified: tc=%s tc_type=%s cp=%u vni_pcp=%u\n",
+		   hw->cdev.name, cxi_tc_to_str(cp->tc),
+		   cxi_tc_type_to_str(cp->tc_type), cass_cp->id, cp->vni_pcp);
+
+	cass_flush_pci(hw);
+
+	return rc;
+}
+EXPORT_SYMBOL(cxi_cp_modify);
diff --git a/drivers/net/ethernet/hpe/ss1/cass_dma_buf.c b/drivers/net/ethernet/hpe/ss1/cass_dma_buf.c
new file mode 100644
index 000000000000..8051df1111da
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_dma_buf.c
@@ -0,0 +1,256 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2021-2023 Hewlett Packard Enterprise Development LP */
+
+#include "cass_core.h"
+
+MODULE_IMPORT_NS("DMA_BUF");
+
+/* This macro is needed for dma-buf.h but is defined is such a way that it is
+ * not easy to include. Thus, redefine it.
+ */
+#define LINUX_DMABUF_BACKPORT(__sym) dmabufbkpt_ ##__sym
+
+/* Need to use quotes to avoid conflict with system default DMA buf headers. */
+#include "linux/dma-buf.h"
+#include "linux/dma-resv.h"
+
+#define DMABUF_DMA_ADDR_TO_MD_PFN(dma_addr) ((dma_addr) >> PAGE_SHIFT)
+#define DMABUF_MD_DEBUG(md_priv, fmt, ...) \
+	pr_debug("DMA buf MD va=%#llx iova=%#llx len=%lu fd=%d fd_offset=%#lx fd_len=%lu: " fmt "", \
+		 (md_priv)->md.va, (md_priv)->md.iova, (md_priv)->md.len, \
+		 (md_priv)->dmabuf_fd, (md_priv)->dmabuf_offset, \
+		 (md_priv)->dmabuf_length, ##__VA_ARGS__)
+#define DMABUF_MD_MDEBUG(md_priv, fmt, ...) \
+do {						\
+	if (more_debug)				\
+		DMABUF_MD_DEBUG(md_priv, fmt, ##__VA_ARGS__);	\
+} while (0)
+#define DMABUF_MD_ERROR(md_priv, fmt, ...) \
+	pr_err("DMA buf MD va=%#llx iova=%#llx len=%lu fd=%d fd_offset=%#lx fd_len=%lu: " fmt "", \
+	       (md_priv)->md.va, (md_priv)->md.iova, (md_priv)->md.len, \
+	       (md_priv)->dmabuf_fd, (md_priv)->dmabuf_offset, \
+	       (md_priv)->dmabuf_length, ##__VA_ARGS__)
+
+static void cxi_dma_buf_invalidate_mappings(struct dma_buf_attachment *attach)
+{
+	struct cxi_md_priv *md_priv = attach->importer_priv;
+	struct cass_ac *cac = md_priv->cac;
+
+	DMABUF_MD_ERROR(md_priv, "DMA buf invalidate mappings not supported\n");
+
+	/* TODO: Properly support invalidation by taking DMA resv lock and
+	 * unmapping SG table. This requires ODP.
+	 */
+	mutex_lock(&cac->ac_mutex);
+	cass_clear_range(md_priv, md_priv->md.iova, md_priv->md.len);
+	mutex_unlock(&cac->ac_mutex);
+	cass_invalidate_range(cac, md_priv->md.iova, md_priv->md.len);
+}
+
+static const struct dma_buf_attach_ops cxi_dma_buf_attach_ops = {
+	.allow_peer2peer = 1,
+	.invalidate_mappings = cxi_dma_buf_invalidate_mappings,
+};
+
+void cxi_dmabuf_put_pages(struct cxi_md_priv *md_priv)
+{
+	DMABUF_MD_DEBUG(md_priv, "DMA buf unmapped\n");
+
+	refcount_dec(&md_priv->refcount);
+
+	dma_resv_lock(md_priv->dmabuf->resv, NULL);
+	dma_buf_unmap_attachment(md_priv->dmabuf_attach, md_priv->dmabuf_sgt,
+				 DMA_BIDIRECTIONAL);
+	dma_resv_unlock(md_priv->dmabuf->resv);
+
+	dma_buf_detach(md_priv->dmabuf, md_priv->dmabuf_attach);
+	dma_buf_put(md_priv->dmabuf);
+	md_priv->dmabuf_sgt = NULL;
+
+	/* cass_dma_unmap_pages does a dma_unmap but this sgt
+	 * has not been dma mapped free the table here.
+	 */
+	sg_free_table(md_priv->sgt);
+	kfree(md_priv->sgt);
+	md_priv->sgt = NULL;
+}
+
+/* cp_md_sgtable - Copy dmabuf sgt entries bounded by dmabuf offset and
+ *                 length to a new sg table for use by the mirroring
+ *                 subsystem.
+ */
+static int cp_md_sgtable(struct cxi_md_priv *md_priv)
+{
+	int i;
+	int rc;
+	ulong end;
+	ulong start;
+	ulong cur = 0;
+	int nents = 0;
+	struct sg_table *sgt;
+	struct scatterlist *sg;
+	struct scatterlist *nsg;
+
+	sgt = kmalloc(sizeof(struct sg_table), GFP_KERNEL);
+	if (!sgt)
+		return -ENOMEM;
+
+	rc = sg_alloc_table(sgt, md_priv->dmabuf_sgt->nents, GFP_KERNEL);
+	if (rc)
+		goto sg_alloc_error;
+
+	start = ALIGN_DOWN(md_priv->dmabuf_offset, PAGE_SIZE);
+	end = PAGE_ALIGN(md_priv->dmabuf_offset + md_priv->dmabuf_length);
+
+	nsg = sgt->sgl;
+	for_each_sgtable_dma_sg(md_priv->dmabuf_sgt, sg, i) {
+		ulong len = sg_dma_len(sg);
+
+		if (start >= cur + len) {
+			cur += len;
+			continue;
+		}
+
+		sg_dma_address(nsg) = sg_dma_address(sg);
+		sg_dma_len(nsg) = len;
+		nents++;
+
+		if (cur <= start) {
+			ulong offset = start - cur;
+
+			sg_dma_address(nsg) += offset;
+			sg_dma_len(nsg) -= offset;
+		}
+
+		if (cur < end && end <= cur + len) {
+			ulong trim = cur + len - end;
+
+			sg_dma_len(nsg) -= trim;
+			break;
+		}
+
+		cur += len;
+		nsg = sg_next(nsg);
+	}
+
+	sgt->nents = nents;
+	md_priv->sgt = sgt;
+
+	return 0;
+
+sg_alloc_error:
+	kfree(sgt);
+
+	return rc;
+}
+
+int cxi_dmabuf_get_pages(struct ac_map_opts *m_opts)
+{
+	struct dma_fence *fence = NULL;
+	unsigned long end;
+	struct cxi_md_priv *md_priv = m_opts->md_priv;
+	struct cxi_dev *dev = md_priv->lni_priv->dev;
+	int rc;
+
+	if (check_add_overflow(md_priv->dmabuf_length, md_priv->dmabuf_offset,
+			       &end)) {
+		rc = -EINVAL;
+		DMABUF_MD_DEBUG(md_priv, "Invalid DMA buf len and offset\n");
+		goto err;
+	}
+
+	md_priv->dmabuf = dma_buf_get(md_priv->dmabuf_fd);
+	if (IS_ERR(md_priv->dmabuf)) {
+		rc = PTR_ERR(md_priv->dmabuf);
+		DMABUF_MD_DEBUG(md_priv, "dma_buf_get failed: rc=%d\n", rc);
+		goto err;
+	}
+
+	if (md_priv->dmabuf->size < end) {
+		rc = -EFAULT;
+		DMABUF_MD_DEBUG(md_priv,
+				"MD size to large for DMA buf size: md_size=%lu dma_buf_size=%lu\n",
+				end, md_priv->dmabuf->size);
+		goto err_release_dma_buf;
+	}
+
+	md_priv->dmabuf_attach = dma_buf_dynamic_attach(md_priv->dmabuf,
+							&dev->pdev->dev,
+							&cxi_dma_buf_attach_ops,
+							md_priv);
+	if (IS_ERR(md_priv->dmabuf_attach)) {
+		rc = PTR_ERR(md_priv->dmabuf_attach);
+		DMABUF_MD_DEBUG(md_priv,
+				"dma_buf_dynamic_attach failed: rc=%d\n", rc);
+		goto err_release_dma_buf;
+	}
+
+	dma_resv_lock(md_priv->dmabuf->resv, NULL);
+
+	md_priv->dmabuf_sgt = dma_buf_map_attachment(md_priv->dmabuf_attach,
+						     DMA_BIDIRECTIONAL);
+	if (IS_ERR(md_priv->dmabuf_sgt)) {
+		rc = PTR_ERR(md_priv->dmabuf_sgt);
+		DMABUF_MD_DEBUG(md_priv,
+				"dma_buf_map_attachment failed: rc=%d\n", rc);
+		goto err_release_unlock_attach;
+	}
+
+	DMABUF_MD_DEBUG(md_priv, "DMA buf SGT nents=%u\n",
+			md_priv->dmabuf_sgt->nents);
+
+	rc = cp_md_sgtable(md_priv);
+	if (rc)
+		goto err_unmap_attach;
+
+	/*
+	 * Although the sg list is valid now, the content of the pages
+	 * may be not up-to-date. Wait for the exporter to finish
+	 * the migration.
+	 */
+#if defined(HAVE_GET_SINGLETON)
+	rc = dma_resv_get_singleton(md_priv->dmabuf->resv, DMA_RESV_USAGE_WRITE,
+				    &fence);
+	if (rc) {
+		rc = dma_resv_wait_timeout(md_priv->dmabuf->resv, DMA_RESV_USAGE_WRITE,
+					   false, MAX_SCHEDULE_TIMEOUT);
+		if (rc) {
+			DMABUF_MD_DEBUG(md_priv,
+					"dma_resv_wait_timeout failed: rc = %d\n", rc);
+			goto err_free_sgt;
+		}
+	}
+#else
+	fence = dma_resv_excl_fence(md_priv->dmabuf->resv);
+	if (fence) {
+		rc = dma_fence_wait(fence, false);
+		if (rc) {
+			DMABUF_MD_DEBUG(md_priv,
+					"dma_fence_wait failed: rc = %d\n", rc);
+			goto err_free_sgt;
+		}
+	}
+#endif  /* defined(HAVE_GET_SINGLETON) */
+
+	dma_resv_unlock(md_priv->dmabuf->resv);
+
+	/* TODO: Is this refcount needed? */
+	refcount_inc(&md_priv->refcount);
+
+	return 0;
+
+err_free_sgt:
+	sg_free_table(md_priv->sgt);
+	kfree(md_priv->sgt);
+	md_priv->sgt = NULL;
+err_unmap_attach:
+	dma_buf_unmap_attachment(md_priv->dmabuf_attach, md_priv->dmabuf_sgt,
+				 DMA_BIDIRECTIONAL);
+err_release_unlock_attach:
+	dma_resv_unlock(md_priv->dmabuf->resv);
+	dma_buf_detach(md_priv->dmabuf, md_priv->dmabuf_attach);
+err_release_dma_buf:
+	dma_buf_put(md_priv->dmabuf);
+err:
+	return rc;
+}
diff --git a/drivers/net/ethernet/hpe/ss1/cass_errors.c b/drivers/net/ethernet/hpe/ss1/cass_errors.c
new file mode 100644
index 000000000000..3d59bbf75643
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_errors.c
@@ -0,0 +1,1155 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2019 Hewlett Packard Enterprise Development LP */
+
+/* Cassini CSR error handlers */
+
+#include <linux/interrupt.h>
+#include <linux/types.h>
+#include <linux/version.h>
+
+#define CREATE_TRACE_POINTS
+
+#include "cass_core.h"
+#include <linux/hpe/cxi/cassini_error_defs.h>
+
+#include "cass_trace.h"
+
+/* Prepare a netlink message, queue it, and trigger the tasklet to
+ * send it. The message cannot be sent from this function directly
+ * because it is called from the interrupt handler.
+ */
+static void send_nl_msg(const struct cxi_dev *cdev, const struct csr_info *info,
+			const struct flg_err_info *flg_info, unsigned int bitn)
+{
+	struct sk_buff *msg;
+	size_t msg_size;
+	void *hdr;
+	int rc;
+
+	msg_size = nla_total_size(2 * nla_attr_size(sizeof(u32)) +
+				  nla_attr_size(sizeof(u8)));
+	msg = genlmsg_new(msg_size, GFP_ATOMIC);
+	if (!msg) {
+		cxidev_err(cdev, "Can't allocate GENL skb\n");
+		return;
+	}
+
+	hdr = genlmsg_put(msg, 0, 0, &cxierr_genl_family,
+			  0, CXIERR_ERR_MSG);
+	if (!hdr) {
+		cxidev_err(cdev, "genl put error");
+		goto fail;
+	}
+
+	rc = nla_put_u32(msg, CXIERR_GENL_ATTR_CSR_FLG, info->flg);
+	if (rc) {
+		cxidev_err(cdev, "nla put str error %d\n", rc);
+		goto fail;
+	}
+
+	rc = nla_put_u8(msg, CXIERR_GENL_ATTR_BIT, bitn);
+	if (rc) {
+		cxidev_err(cdev, "nla put str error %d\n", rc);
+		goto fail;
+	}
+
+	rc = nla_put_u32(msg, CXIERR_GENL_ATTR_DEV_NUM, cdev->cxi_num);
+	if (rc) {
+		cxidev_err(cdev, "nla put str error %d\n", rc);
+		goto fail;
+	}
+
+	genlmsg_end(msg, hdr);
+
+	genlmsg_multicast(&cxierr_genl_family, msg, 0, 0, GFP_ATOMIC);
+
+	return;
+
+fail:
+	genlmsg_cancel(msg, hdr);
+	nlmsg_free(msg);
+}
+
+/* Collect the information needed to analyze an error flag.
+ *
+ * Some fields in error CSRs are arrays (PFC_FIFO_OFLW in
+ * C_HNI_ERR_FLG for instance). bit_index is their index.
+ */
+static void collect_flg_info(struct cass_dev *hw,
+			     const struct flg_err_info *flg_info,
+			     unsigned int bit_index)
+{
+	int i;
+	int idx = 0;
+
+	hw->err_info_count = 0;
+
+	for (idx = 0;
+	     idx < C_MAX_CSR_ERR_INFO && flg_info->err_info[idx].offset != 0;
+	     idx++) {
+		struct err_info *info = &hw->err_info[idx];
+		void __iomem *base =
+				cass_csr(hw, flg_info->err_info[idx].offset);
+		int count = flg_info->err_info[idx].size / 8;
+
+		/* The ERR_INFO CSRs are up to 5 64-bits values, but
+		 * that may change.
+		 */
+		if (cxidev_WARN_ONCE(&hw->cdev, count > 5,
+				     "err_info CSR %x is too big: %d\n",
+				     flg_info->err_info[idx].offset, count)) {
+			count = 5;
+		}
+
+		for (i = 0; i < count; i++, base += sizeof(u64))
+			info->data[i] = readq(base);
+
+		info->count = count;
+
+		hw->err_info_count++;
+	}
+
+	hw->err_cntrs_count = 0;
+
+	for (idx = 0;
+	     idx < C_MAX_CSR_CNTRS && flg_info->cntr[idx].offset != 0;
+	     idx++) {
+		void __iomem *base;
+
+		if (flg_info->cntr[idx].index == C_ERR_INDEX_NONE)
+			base = cass_csr(hw, flg_info->cntr[idx].offset);
+		else
+			base = cass_csr(hw, flg_info->cntr[idx].offset +
+					bit_index * sizeof(u64));
+
+		hw->cntrs_val[idx] = readq(base);
+		hw->err_cntrs_count++;
+	}
+}
+
+/*
+ * eventually move this logging macro  as an addition or a replacement
+ * for	_cxi_log() in cass_core.h.
+ */
+#define _dump_flg_info_logger(loglevel, hw, fmt, ...)			\
+	do {								\
+		switch (loglevel) {					\
+		case LOGLEVEL_EMERG:					\
+			dev_emerg(&(hw)->cdev.pdev->dev,		\
+				"%s[%s]: " fmt,				\
+				(hw)->cdev.name, (hw)->cdev.eth_name,	\
+				##__VA_ARGS__);				\
+			break;						\
+		case LOGLEVEL_ALERT:					\
+			dev_alert(&(hw)->cdev.pdev->dev,		\
+				"%s[%s]: " fmt,				\
+				(hw)->cdev.name, (hw)->cdev.eth_name,	\
+				##__VA_ARGS__);				\
+			break;						\
+		case LOGLEVEL_CRIT:					\
+			dev_crit(&(hw)->cdev.pdev->dev,			\
+				"%s[%s]: " fmt,				\
+				(hw)->cdev.name, (hw)->cdev.eth_name,	\
+				##__VA_ARGS__);				\
+			break;						\
+		case LOGLEVEL_ERR:					\
+			dev_err(&(hw)->cdev.pdev->dev,			\
+				"%s[%s]: " fmt,				\
+				(hw)->cdev.name, (hw)->cdev.eth_name,	\
+				##__VA_ARGS__);				\
+			break;						\
+		case LOGLEVEL_WARNING:					\
+			dev_warn(&(hw)->cdev.pdev->dev,			\
+				"%s[%s]: " fmt,				\
+				(hw)->cdev.name, (hw)->cdev.eth_name,	\
+				##__VA_ARGS__);				\
+			break;						\
+		case LOGLEVEL_NOTICE:					\
+			dev_notice(&(hw)->cdev.pdev->dev,		\
+				"%s[%s]: " fmt,				\
+				(hw)->cdev.name, (hw)->cdev.eth_name,	\
+				##__VA_ARGS__);				\
+			break;						\
+		case LOGLEVEL_INFO:					\
+			dev_info(&(hw)->cdev.pdev->dev,			\
+				"%s[%s]: " fmt,				\
+				(hw)->cdev.name, (hw)->cdev.eth_name,	\
+				##__VA_ARGS__);				\
+			break;						\
+		case LOGLEVEL_DEBUG:					\
+			dev_dbg(&(hw)->cdev.pdev->dev,			\
+				"%s[%s]: " fmt,				\
+				(hw)->cdev.name, (hw)->cdev.eth_name,	\
+				##__VA_ARGS__);				\
+			break;						\
+		}							\
+	} while (0)
+
+/* Emit the collected information for a given error flag to the kernel
+ * log.
+ */
+static void dump_flg_info(struct cass_dev *hw,
+			  unsigned int irq, bool is_ext,
+			  const struct csr_info *info,
+			  const struct flg_err_info *flg_info,
+			  unsigned int bitn)
+{
+	int i;
+	char *first_err;
+	int log_level = 0;
+	static const char * const error_event_names[] = {
+		"C_EC_SFTWR",
+		"C_EC_INFO",
+		"C_EC_TRS_NS",
+		"C_EC_TRS_S",
+		"C_EC_TRNSNT_NS",
+		"C_EC_TRNSNT_S",
+		"C_EC_BADCON_NS",
+		"C_EC_BADCON_S",
+		"C_EC_DEGRD_NS",
+		"C_EC_COR",
+		"C_EC_UNCOR_NS",
+		"C_EC_UNCOR_S",
+		"C_EC_CRIT",
+	};
+	const char *errname;
+
+	if (test_bit(bitn, hw->first_flg)) {
+		first_err = hw->err_info_str;
+		sprintf(hw->err_info_str, "(was first error at %lu:%09lu)",
+			(unsigned long)hw->first_flg_ts.seconds,
+			(unsigned long)hw->first_flg_ts.nanoseconds);
+	} else {
+		first_err = "";
+	}
+
+	if (test_bit(bitn,
+		     hw->sfs_err_flg[irq][is_ext ? 1 : 0].no_print_mask.mask))
+		return;
+
+	/* Find the log level for that error. Not all errors reported
+	 * by the device are bad.
+	 */
+	switch (flg_info->ec) {
+	case C_EC_SFTWR:
+	case C_EC_INFO:
+	case C_EC_TRS_NS:
+	case C_EC_TRS_S:
+	case C_EC_TRNSNT_NS:
+	case C_EC_TRNSNT_S:
+		errname = error_event_names[flg_info->ec];
+		log_level = LOGLEVEL_INFO;
+		break;
+
+	case C_EC_BADCON_NS:
+	case C_EC_BADCON_S:
+	case C_EC_COR:
+		errname = error_event_names[flg_info->ec];
+		log_level = LOGLEVEL_WARNING;
+		break;
+
+	case C_EC_DEGRD_NS:
+		errname = error_event_names[flg_info->ec];
+		log_level = LOGLEVEL_ERR;
+		break;
+
+	case C_EC_UNCOR_NS:
+	case C_EC_UNCOR_S:
+		errname = error_event_names[flg_info->ec];
+		if (strcmp("llr_eopb", flg_info->bit_name) == 0)
+			log_level = LOGLEVEL_INFO;
+		else
+			log_level = LOGLEVEL_CRIT;
+		break;
+
+	case C_EC_CRIT:
+		errname = error_event_names[flg_info->ec];
+		log_level = LOGLEVEL_CRIT;
+		break;
+
+	default:
+		errname = "unrecognized c_error_class value";
+		log_level = LOGLEVEL_CRIT;
+		break;
+	}
+
+	_dump_flg_info_logger(log_level, hw, "%s: %s error: %s (%d) %s\n",
+			      errname, info->csr_name, flg_info->bit_name,
+			      bitn, first_err);
+
+	if (hw->err_info_count) {
+		int idx;
+
+		for (idx = 0; idx < hw->err_info_count; idx++) {
+			struct err_info *info = &hw->err_info[idx];
+			char *p = hw->err_info_str;
+
+			*p = '\0';
+
+			for (i = 0; i < info->count; i++)
+				p += sprintf(p, " %016llx", info->data[i]);
+
+			_dump_flg_info_logger(log_level, hw, "%s: %s%s\n",
+					      errname,
+					      flg_info->err_info[idx].name,
+					      hw->err_info_str);
+		}
+	}
+
+	if (hw->err_cntrs_count) {
+		int idx;
+
+		for (idx = 0; idx < hw->err_cntrs_count; idx++)
+			_dump_flg_info_logger(log_level, hw, "%s: %s: %llu\n",
+					      errname,
+					      flg_info->cntr[idx].name,
+					      hw->cntrs_val[idx]);
+	}
+}
+
+static void trace_err_info(struct cass_dev *hw,
+			   const struct csr_info *info,
+			   const struct flg_err_info *flg_info,
+			   unsigned int bitn)
+{
+	unsigned long seconds;
+	unsigned long nanoseconds;
+
+	if (test_bit(bitn, hw->first_flg)) {
+		seconds = hw->first_flg_ts.seconds;
+		nanoseconds = hw->first_flg_ts.nanoseconds;
+	} else {
+		seconds = 0;
+		nanoseconds = 0;
+	}
+
+	trace_cass_err(info->flg, bitn, seconds, nanoseconds,
+		       flg_info, hw->err_info, hw->cntrs_val);
+}
+
+/* Check whether some registered handlers are interested in that bit. */
+static void
+process_registered_handlers(struct cass_dev *hw, unsigned int irq, bool is_ext,
+			    unsigned int bitn)
+{
+	struct cxi_reg_err_flg *err_flg;
+
+	if (list_empty(&hw->err_flg_list))
+		return;
+
+	mutex_lock(&hw->err_flg_mutex);
+	list_for_each_entry(err_flg, &hw->err_flg_list, list) {
+		if ((irq == err_flg->irq) &&
+		    (is_ext == err_flg->is_ext) &&
+		    test_bit(bitn, err_flg->err_flags.mask))
+			err_flg->cb(hw, irq, is_ext, bitn);
+	}
+	mutex_unlock(&hw->err_flg_mutex);
+}
+
+/* Called for each bit in an ERR_FLG (or EXT_ERR_FLG) CSR.
+ *
+ * irq is which interrupt was triggered (C_PI_IPD_IRQA_MSIX_INT to
+ *   C_OXE_IRQB_MSIX_INT.)
+ * is_ext indicates whether this is the normal CSR or its EXT part.
+ * bitn is the bit number (0 to 63) that has been set in that CSR.
+ */
+static void process_err_flg(struct cass_dev *hw, unsigned int irq, bool is_ext,
+			    const struct csr_info *info, unsigned int bitn)
+{
+	const struct flg_err_info *flg_info = info->flg_info;
+
+	/* Both for_each_set_bit and flg_info->bit go
+	 * up. Match the range.
+	 */
+	while (flg_info->bit + flg_info->num_bits <= bitn)
+		flg_info++;
+
+	if (flg_info->bit <= bitn) {
+		collect_flg_info(hw, flg_info, bitn - flg_info->bit);
+
+		/* TODO?: once the API stabilizes, it might be
+		 * possible to have these 3 handlers as clients of
+		 * process_registered_handlers().
+		 */
+
+		dump_flg_info(hw, irq, is_ext, info, flg_info, bitn);
+		send_nl_msg(&hw->cdev, info, flg_info, bitn);
+		trace_err_info(hw, info, flg_info, bitn);
+
+		process_registered_handlers(hw, irq, is_ext, bitn);
+	} else {
+		cxidev_info(&hw->cdev, "%s error: unhandled bit %u\n",
+			    info->csr_name, bitn);
+		flg_info = NULL;
+	}
+
+	if (!__ratelimit(&hw->err_rl[irq][bitn])) {
+		struct sfs_err_flg *sfs = &hw->sfs_err_flg[irq][is_ext ? 1 : 0];
+
+		if (!test_bit(bitn, sfs->no_auto_mask.mask)) {
+			union err_flags bitmask = {};
+
+			cxidev_info(&hw->cdev,
+				    "Too many interrupts for %s.%s. Masking.\n",
+				    info->csr_name,
+				    flg_info ? flg_info->bit_name : "unknown");
+
+			set_bit(bitn, bitmask.mask);
+			cxi_disable_hw_errors(hw, irq, is_ext, bitmask.mask);
+		}
+	}
+}
+
+static ssize_t mask_show(struct kobject *kobj,
+			 struct kobj_attribute *attr, char *buf)
+{
+	struct sfs_err_flg *sfs = container_of(kobj, struct sfs_err_flg, kobj);
+
+	return scnprintf(buf, PAGE_SIZE, "%*pb\n",
+			 sfs->bitlen, sfs->err_irq_mask);
+}
+
+static ssize_t no_print_mask_show(struct kobject *kobj,
+				  struct kobj_attribute *attr, char *buf)
+{
+	struct sfs_err_flg *sfs = container_of(kobj, struct sfs_err_flg, kobj);
+
+	return scnprintf(buf, PAGE_SIZE, "%*pb\n",
+			 sfs->bitlen, sfs->no_print_mask.mask);
+}
+
+static ssize_t no_print_mask_store(struct kobject *kobj,
+				   struct kobj_attribute *attr,
+				   const char *buf, size_t len)
+{
+	struct sfs_err_flg *sfs = container_of(kobj, struct sfs_err_flg, kobj);
+	DECLARE_BITMAP(new, MAX_ERR_FLAG_BITLEN);
+	int ret;
+
+	ret = bitmap_parse(buf, len, new, sfs->bitlen);
+	if (ret)
+		return ret;
+
+	bitmap_copy(sfs->no_print_mask.mask, new, sfs->bitlen);
+
+	return len;
+}
+
+static ssize_t no_auto_mask_show(struct kobject *kobj,
+				 struct kobj_attribute *attr, char *buf)
+{
+	struct sfs_err_flg *sfs = container_of(kobj, struct sfs_err_flg, kobj);
+
+	return scnprintf(buf, PAGE_SIZE, "%*pb\n",
+			 sfs->bitlen, sfs->no_auto_mask.mask);
+}
+
+static ssize_t no_auto_mask_store(struct kobject *kobj,
+				  struct kobj_attribute *attr,
+				  const char *buf, size_t len)
+{
+	struct sfs_err_flg *sfs = container_of(kobj, struct sfs_err_flg, kobj);
+	DECLARE_BITMAP(new, MAX_ERR_FLAG_BITLEN);
+	int ret;
+
+	ret = bitmap_parse(buf, len, new, sfs->bitlen);
+	if (ret)
+		return ret;
+
+	bitmap_copy(sfs->no_auto_mask.mask, new, sfs->bitlen);
+
+	return len;
+}
+
+#define CSR_ERROR_ATTR_RO(_name) \
+	static struct kobj_attribute _name##_attr = __ATTR_RO(_name)
+
+#define CSR_ERROR_ATTR_RW(_name)					\
+	static struct kobj_attribute _name##_attr = __ATTR_RW(_name)
+
+CSR_ERROR_ATTR_RO(mask);
+CSR_ERROR_ATTR_RW(no_print_mask);
+CSR_ERROR_ATTR_RW(no_auto_mask);
+
+static struct attribute *irq_attrs[] = {
+	&mask_attr.attr,
+	&no_print_mask_attr.attr,
+	&no_auto_mask_attr.attr,
+	NULL
+};
+ATTRIBUTE_GROUPS(irq);
+
+static struct kobj_type irq_kobj_type = {
+	.sysfs_ops  = &kobj_sysfs_ops,
+	.default_groups = irq_groups,
+};
+
+/* Define which error CSRs are connected to which IRQs.
+ * pf1 = prefix for the main CSR (ie. C1_IXE_ERR_FLG)
+ * pf2 = prefix for the sub-CSRs (ie. C_IXE_ERR_FIRST_FLG)
+ * The main can be different between C1/C2, but the other don't have
+ * the named fields in them, so they are identical. This is messy.
+ */
+#define CSRERR1(pf1, pf2, name, irq, namelo) {				\
+	.csr_name = #pf1 "_" #name, .flg = pf1##_##name##_ERR_FLG,	\
+	.mask = pf2##_##name##_ERR_IRQ##irq##_MSK,			\
+	.clr = pf2##_##name##_ERR_CLR, .flg_info = namelo##_err_info,	\
+	.first_flg = pf2##_##name##_ERR_FIRST_FLG,			\
+	.first_flg_ts = pf2##_##name##_ERR_FIRST_FLG_TS,		\
+	.csr_name_lo = #namelo,						\
+	.bitlen = (pf1##_##name##_ERR_FLG_SIZE * BITS_PER_BYTE)		\
+}
+
+#define CSRERR2(pf1, pf2, name, irq, namelo) {				\
+	.csr_name = #pf1 "_" #name, .flg = pf1##_##name##_ERR_FLG,	\
+	.mask = pf2##_##name##_ERR_IRQ##irq##_MSK,			\
+	.clr = pf2##_##name##_ERR_CLR, .flg_info = c2_##namelo##_err_info, \
+	.first_flg = pf2##_##name##_ERR_FIRST_FLG,			\
+	.first_flg_ts = pf2##_##name##_ERR_FIRST_FLG_TS,		\
+	.csr_name_lo = #namelo,						\
+	.bitlen = (pf1##_##name##_ERR_FLG_SIZE * BITS_PER_BYTE)		\
+}
+
+#define CSRERRSS2(pf1, pf2, name, irq, namelo) {				\
+	.csr_name = #pf1 "_" #name, .flg = pf1##_##name##_ERR_FLG,	\
+	.mask = pf2##_##name##_ERR_IRQ##irq##_MSK,			\
+	.clr = pf2##_##name##_ERR_CLR, .flg_info = ss2_##namelo##_err_info, \
+	.first_flg = pf2##_##name##_ERR_FIRST_FLG,			\
+	.first_flg_ts = pf2##_##name##_ERR_FIRST_FLG_TS,		\
+	.csr_name_lo = #namelo,						\
+	.bitlen = (pf1##_##name##_ERR_FLG_SIZE * BITS_PER_BYTE)		\
+}
+
+static const struct csr_info c1_handlers[NUM_ERR_INTS][2] = {
+	{ CSRERR1(C, C, PI_IPD, A, pi_ipd),
+	  CSRERR1(C, C, PI_IPD_EXT, A, pi_ipd_ext) },
+	{ CSRERR1(C, C, PI, A, pi), CSRERR1(C, C, PI_EXT, A, pi_ext) },
+	{ CSRERR1(C, C, MB, A, mb), CSRERR1(C, C, MB_EXT, A, mb_ext) },
+	{ CSRERR1(C, C, CQ, A, cq), CSRERR1(C, C, CQ_EXT, A, cq_ext) },
+	{ CSRERR1(C1, C, PCT, A, pct), CSRERR1(C, C, PCT_EXT, A, pct_ext) },
+	{ CSRERR1(C1, C, HNI, A, hni), },
+	{ CSRERR1(C1, C1, HNI_PML, A, hni_pml) },
+	{ CSRERR1(C, C, RMU, A, rmu) },
+	{ CSRERR1(C, C, IXE, A, ixe), CSRERR1(C, C, IXE_EXT, A, ixe_ext) },
+	{ CSRERR1(C, C, ATU, A, atu), CSRERR1(C, C, ATU_EXT, A, atu_ext) },
+	{ CSRERR1(C, C, EE, A, ee), CSRERR1(C, C, EE_EXT, A, ee_ext) },
+	{ CSRERR1(C, C, PARBS, A, parbs),
+	  CSRERR1(C, C, PARBS_EXT, A, parbs_ext) },
+	{ CSRERR1(C, C, LPE, A, lpe) },
+	{ CSRERR1(C, C, MST, A, mst) },
+	{ CSRERR1(C, C, OXE, A, oxe) },
+	{ CSRERR1(C, C, PI_IPD, B, pi_ipd),
+	  CSRERR1(C, C, PI_IPD_EXT, B, pi_ipd_ext) },
+	{ CSRERR1(C, C, PI, B, pi), CSRERR1(C, C, PI_EXT, B, pi_ext) },
+	{ CSRERR1(C, C, MB, B, mb), CSRERR1(C, C, MB_EXT, B, mb_ext) },
+	{ CSRERR1(C, C, CQ, B, cq), CSRERR1(C, C, CQ_EXT, B, cq_ext) },
+	{ CSRERR1(C1, C, PCT, B, pct), CSRERR1(C, C, PCT_EXT, B, pct_ext) },
+	{ CSRERR1(C1, C, HNI, B, hni) },
+	{ CSRERR1(C1, C1, HNI_PML, B, hni_pml) },
+	{ CSRERR1(C, C, RMU, B, rmu) },
+	{ CSRERR1(C, C, IXE, B, ixe), CSRERR1(C, C, IXE_EXT, B, ixe_ext) },
+	{ CSRERR1(C, C, ATU, B, atu), CSRERR1(C, C, ATU_EXT, B, atu_ext) },
+	{ CSRERR1(C, C, EE, B, ee), CSRERR1(C, C, EE_EXT, B, ee_ext) },
+	{ CSRERR1(C, C, PARBS, B, parbs),
+	  CSRERR1(C, C, PARBS_EXT, B, parbs_ext) },
+	{ CSRERR1(C, C, LPE, B, lpe) },
+	{ CSRERR1(C, C, MST, B, mst) },
+	{ CSRERR1(C, C, OXE, B, oxe) },
+};
+
+static const struct csr_info c2_handlers[NUM_ERR_INTS][2] = {
+	{ CSRERR2(C, C, PI_IPD, A, pi_ipd),
+	  CSRERR2(C, C, PI_IPD_EXT, A, pi_ipd_ext) },
+	{ CSRERR2(C, C, PI, A, pi), CSRERR2(C, C, PI_EXT, A, pi_ext) },
+	{ CSRERR2(C, C, MB, A, mb), CSRERR2(C, C, MB_EXT, A, mb_ext) },
+	{ CSRERR2(C, C, CQ, A, cq), CSRERR2(C, C, CQ_EXT, A, cq_ext) },
+	{ CSRERR2(C2, C, PCT, A, pct), CSRERR2(C, C, PCT_EXT, A, pct_ext) },
+	{ CSRERR2(C2, C, HNI, A, hni), CSRERR2(C2, C2, HNI_EXT, A, hni_ext) },
+	{ CSRERRSS2(SS2, SS2, PORT_PML, A, port_pml) },
+	{ CSRERR2(C, C, RMU, A, rmu) },
+	{ CSRERR2(C, C, IXE, A, ixe), CSRERR2(C, C, IXE_EXT, A, ixe_ext) },
+	{ CSRERR2(C, C, ATU, A, atu), CSRERR2(C, C, ATU_EXT, A, atu_ext) },
+	{ CSRERR2(C, C, EE, A, ee), CSRERR2(C, C, EE_EXT, A, ee_ext) },
+	{ CSRERR2(C, C, PARBS, A, parbs),
+	  CSRERR2(C, C, PARBS_EXT, A, parbs_ext) },
+	{ CSRERR2(C, C, LPE, A, lpe) },
+	{ CSRERR2(C, C, MST, A, mst) },
+	{ CSRERR2(C, C, OXE, A, oxe) },
+	{ CSRERR2(C, C, PI_IPD, B, pi_ipd),
+	  CSRERR2(C, C, PI_IPD_EXT, B, pi_ipd_ext) },
+	{ CSRERR2(C, C, PI, B, pi), CSRERR2(C, C, PI_EXT, B, pi_ext) },
+	{ CSRERR2(C, C, MB, B, mb), CSRERR2(C, C, MB_EXT, B, mb_ext) },
+	{ CSRERR2(C, C, CQ, B, cq), CSRERR2(C, C, CQ_EXT, B, cq_ext) },
+	{ CSRERR2(C2, C, PCT, B, pct), CSRERR2(C, C, PCT_EXT, B, pct_ext) },
+	{ CSRERR2(C2, C, HNI, B, hni), CSRERR2(C2, C2, HNI_EXT, B, hni_ext) },
+	{ CSRERRSS2(SS2, SS2, PORT_PML, B, port_pml) },
+	{ CSRERR2(C, C, RMU, B, rmu) },
+	{ CSRERR2(C, C, IXE, B, ixe), CSRERR2(C, C, IXE_EXT, B, ixe_ext) },
+	{ CSRERR2(C, C, ATU, B, atu), CSRERR2(C, C, ATU_EXT, B, atu_ext) },
+	{ CSRERR2(C, C, EE, B, ee), CSRERR2(C, C, EE_EXT, B, ee_ext) },
+	{ CSRERR2(C, C, PARBS, B, parbs),
+	  CSRERR2(C, C, PARBS_EXT, B, parbs_ext) },
+	{ CSRERR2(C, C, LPE, B, lpe) },
+	{ CSRERR2(C, C, MST, B, mst) },
+	{ CSRERR2(C, C, OXE, B, oxe) },
+};
+
+/* Whether the extended error flag exists */
+#define INFO(irq, idx) ((*hw->err_handlers)[irq][idx])
+#define HAS_EXT(irq) (INFO(irq, 1).csr_name)
+
+static void process_err_irq(struct cass_dev *hw, int irq)
+{
+	union err_flags err_flag[2];
+	DECLARE_BITMAP(mask, MAX_ERR_FLAG_BITLEN);
+	int i;
+	unsigned int bitn;
+
+	while (true) {
+		bool empty[2] = { true, true };
+
+		/* Read the normal CSR and the extended CSR if it
+		 * exists. Bits that are not valid must be ignored.
+		 */
+		for (i = 0; i < 2; i++) {
+			const struct csr_info *info = &INFO(irq, i);
+
+			if (i == 0 || HAS_EXT(irq)) {
+				cass_read(hw, info->flg,
+					  &err_flag[i].mask, info->bitlen / BITS_PER_BYTE);
+
+				cass_read(hw, info->mask, mask, info->bitlen / BITS_PER_BYTE);
+				bitmap_andnot(err_flag[i].mask, err_flag[i].mask, mask,
+					      info->bitlen);
+
+				if (!bitmap_empty(err_flag[i].mask, info->bitlen))
+					empty[i] = false;
+			} else {
+				bitmap_zero(err_flag[i].mask, info->bitlen);
+			}
+		}
+
+		/* A new error might have been raised since being
+		 * cleared in the previous loop. We must ensure the
+		 * error flags are 0 before leaving.
+		 */
+		if (empty[0] && empty[1])
+			return;
+
+		for (i = 0; i < 2; i++) {
+			const struct csr_info *info = &INFO(irq, i);
+
+			if (empty[i])
+				continue;
+
+			cass_read(hw, info->first_flg,
+				  hw->first_flg, info->bitlen / BITS_PER_BYTE);
+
+			cass_read(hw, info->first_flg_ts,
+				  &hw->first_flg_ts, sizeof(hw->first_flg_ts));
+
+			for_each_set_bit(bitn, err_flag[i].mask, info->bitlen)
+				process_err_flg(hw, irq, i == 1, info, bitn);
+
+			/* Clear the error bits after processing the flagged
+			 * error(s), otherwise the associated error CSRs might
+			 * be reset for the next error, but before the driver
+			 * has time to read them.
+			 */
+			cass_write(hw, info->clr, &err_flag[i],
+				   info->bitlen / BITS_PER_BYTE);
+		}
+	}
+}
+
+/* Worker to process all raised interrupts */
+static void error_irq_worker(struct work_struct *work)
+{
+	struct cass_dev *hw = container_of(work, struct cass_dev, err_irq_work);
+	int irq;
+	unsigned long irqs_raised;
+
+	irqs_raised = xchg(&hw->err_irq_raised, 0);
+
+	for_each_set_bit(irq, &irqs_raised, NUM_ERR_INTS)
+		process_err_irq(hw, irq);
+}
+
+/* Main interrupt handler for error registers */
+static irqreturn_t error_irq_cb(int vec, void *context)
+{
+	struct cass_dev *hw = context;
+	int irq;
+
+	/* Find the irq from the vector. This could be more efficient,
+	 * but these interrupts should be fairly rare.
+	 */
+	for (irq = 0; irq < NUM_ERR_INTS; irq++) {
+		if (hw->err_irq_vecs[irq] == vec)
+			break;
+	}
+
+	if (irq == NUM_ERR_INTS) {
+		cxidev_warn_once(&hw->cdev, "Error IRQ not found for vector %u\n",
+				 vec);
+		return IRQ_HANDLED;
+	}
+
+	set_bit(irq, &hw->err_irq_raised);
+	queue_work(hw->err_irq_wq, &hw->err_irq_work);
+
+	return IRQ_HANDLED;
+}
+
+static int cxierr_msg(struct sk_buff *skb, struct genl_info *info)
+{
+	return 0;
+}
+
+static const struct nla_policy cxierr_genl_policy[CXIERR_GENL_ATTR_MAX] = {
+	[CXIERR_GENL_ATTR_DEV_NUM] = { .type = NLA_U32 },
+	[CXIERR_GENL_ATTR_CSR_FLG] = { .type = NLA_U32 },
+	[CXIERR_GENL_ATTR_BIT] = { .type = NLA_U8 },
+};
+
+static const struct genl_ops cxierr_genl_ops[] = {
+	{
+		.cmd = CXIERR_ERR_MSG,
+		.doit = cxierr_msg,
+		.flags = GENL_ADMIN_PERM,
+	},
+};
+
+static const struct genl_multicast_group cxierr_mcast_grps[] = {
+	{ .name = CXIERR_GENL_MCAST_GROUP_NAME, },
+};
+
+struct genl_family cxierr_genl_family __ro_after_init = {
+	.module = THIS_MODULE,
+	.name = CXIERR_GENL_FAMILY_NAME,
+	.version = CXIERR_GENL_VERSION,
+	.maxattr = CXIERR_GENL_ATTR_MAX - 1,
+	.policy = cxierr_genl_policy,
+	.ops = cxierr_genl_ops,
+	.n_ops = ARRAY_SIZE(cxierr_genl_ops),
+	.mcgrps = cxierr_mcast_grps,
+	.n_mcgrps = ARRAY_SIZE(cxierr_mcast_grps),
+};
+
+static void free_err_irqs(struct cass_dev *hw)
+{
+	static const u64 mask;
+	int irq;
+
+	for (irq = 0; irq < NUM_ERR_INTS; irq++) {
+		int vec = hw->err_irq_vecs[irq];
+
+		if (vec < 0)
+			continue;
+
+		/* Reset their masks */
+		cass_write(hw, INFO(irq, 0).mask, &mask, sizeof(mask));
+		if (HAS_EXT(irq))
+			cass_write(hw, INFO(irq, 1).mask, &mask, sizeof(mask));
+
+		free_irq(vec, hw);
+
+		hw->err_irq_vecs[irq] = -1;
+	}
+}
+
+/**
+ * cxi_register_hw_errors() - register a callback for error bits
+ *
+ * When an error interrupt is generated, one or two CSR (ERR_FLG) have
+ * information. This allows a caller to be informed, through a
+ * callback, when some of these bits are set.
+ *
+ * @hw: the device
+ * @reg_err_flg: caller-initialized parameters (bitmask, callback, ...)
+ */
+void cxi_register_hw_errors(struct cass_dev *hw,
+			    struct cxi_reg_err_flg *reg_err_flg)
+{
+	mutex_lock(&hw->err_flg_mutex);
+	list_add_tail(&reg_err_flg->list, &hw->err_flg_list);
+	mutex_unlock(&hw->err_flg_mutex);
+}
+
+/**
+ * cxi_unregister_hw_errors() - un-register a callback for error bits
+ *
+ * @hw: the device
+ * @reg_err_flg: same structure used to register
+ */
+void cxi_unregister_hw_errors(struct cass_dev *hw,
+			      struct cxi_reg_err_flg *reg_err_flg)
+{
+	mutex_lock(&hw->err_flg_mutex);
+	list_del(&reg_err_flg->list);
+	mutex_unlock(&hw->err_flg_mutex);
+}
+
+/**
+ * cxi_enable_hw_errors() - enable interrupts for some error bits
+ *
+ * @hw: the device
+ * @irq: the IRQ/BLOCK (eg. C_HNI_PML_IRQA_MSIX_INT)
+ * @is_ext: whether or not the error flag is in the EXT_FLG CSR
+ * @bitmask: bitmask of interrupts to enable
+ */
+void cxi_enable_hw_errors(struct cass_dev *hw, unsigned int irq, bool is_ext,
+			  const unsigned long *bitmask)
+{
+	unsigned int idx = is_ext ? 1 : 0;
+	const struct csr_info *info = &INFO(irq, idx);
+	struct sfs_err_flg *sfs = &hw->sfs_err_flg[irq][idx];
+
+	spin_lock_bh(&hw->sfs_err_flg_lock);
+	bitmap_andnot(sfs->err_irq_mask, sfs->err_irq_mask,
+		      bitmask, sfs->bitlen);
+	cass_write(hw, info->mask, &sfs->err_irq_mask,
+		   sfs->bitlen / BITS_PER_BYTE);
+	spin_unlock_bh(&hw->sfs_err_flg_lock);
+}
+
+/**
+ * cxi_disable_hw_errors() - disable interrupts for some error bits
+ *
+ * @hw: the device
+ * @irq: the IRQ/BLOCK (eg. C_HNI_PML_IRQA_MSIX_INT)
+ * @is_ext: whether or not the error flag is in the EXT_FLG CSR
+ * @bitmask: bitmask of interrupts to disable
+ */
+void cxi_disable_hw_errors(struct cass_dev *hw, unsigned int irq, bool is_ext,
+			   const unsigned long *bitmask)
+{
+	unsigned int idx = is_ext ? 1 : 0;
+	const struct csr_info *info = &INFO(irq, idx);
+	struct sfs_err_flg *sfs = &hw->sfs_err_flg[irq][idx];
+
+	spin_lock_bh(&hw->sfs_err_flg_lock);
+	bitmap_or(sfs->err_irq_mask, sfs->err_irq_mask, bitmask, sfs->bitlen);
+	cass_write(hw, info->mask, &sfs->err_irq_mask,
+		   sfs->bitlen / BITS_PER_BYTE);
+	spin_unlock_bh(&hw->sfs_err_flg_lock);
+}
+
+static void alloc_kobjs_and_hw_errors(struct cass_dev *hw)
+{
+	struct sfs_err_flg *sfs;
+	DECLARE_BITMAP(bitmask, MAX_ERR_FLAG_BITLEN);
+	int irq = 0;
+	int rc;
+	int i;
+
+	bitmap_fill(bitmask, MAX_ERR_FLAG_BITLEN);
+
+	/* Only register with IrqA. Unmask all IrqA and mask all IrqB
+	 * interrupts.
+	 */
+	for (irq = 0; irq < NUM_ERR_INTS; irq++) {
+		for (i = 0; i < 2; i++) {
+			struct kobject *dkobj = hw->err_flgs_dir_kobj[0];
+			const struct csr_info *info = &INFO(irq, i);
+
+			if (info->csr_name == NULL)
+				continue;
+
+			sfs = &hw->sfs_err_flg[irq][i];
+
+			/* Clear all existing error conditions */
+			cass_write(hw, info->clr, &bitmask,
+				   sfs->bitlen / BITS_PER_BYTE);
+
+			if (irq < NUM_ERR_INTS / 2) {
+				/* IrqA */
+				rc = kobject_init_and_add(&sfs->kobj,
+							  &irq_kobj_type,
+							  dkobj,
+							  "%s",
+							  info->csr_name_lo);
+				if (rc)
+					cxidev_warn(&hw->cdev,
+						    "Can't add kobject for error CSR %s\n",
+						    info->csr_name);
+
+				cxi_enable_hw_errors(hw, irq, i, bitmask);
+			} else {
+				/* IrqB */
+				cxi_disable_hw_errors(hw, irq, i, bitmask);
+			}
+		}
+	}
+}
+
+static void free_kobjs_and_hw_errors(struct cass_dev *hw)
+{
+	struct sfs_err_flg *sfs;
+	DECLARE_BITMAP(bitmask, MAX_ERR_FLAG_BITLEN);
+	int irq = 0;
+	int i;
+
+	bitmap_fill(bitmask, MAX_ERR_FLAG_BITLEN);
+
+	for (irq = 0; irq < NUM_ERR_INTS; irq++) {
+		for (i = 0; i < 2; i++) {
+			const struct csr_info *info = &INFO(irq, i);
+
+			if (info->csr_name == NULL)
+				continue;
+
+			sfs = &hw->sfs_err_flg[irq][i];
+
+			if (irq < NUM_ERR_INTS / 2) {
+				/* IrqA */
+				kobject_put(&sfs->kobj);
+			}
+
+			cxi_disable_hw_errors(hw, irq, i, bitmask);
+		}
+	}
+}
+
+int register_error_handlers(struct cass_dev *hw)
+{
+	struct sfs_err_flg *sfs;
+	union err_flags bitmask;
+	int irq = 0;
+	int rc;
+	int i;
+	int j;
+
+	if (cass_version(hw, CASSINI_1))
+		hw->err_handlers = &c1_handlers;
+	else
+		hw->err_handlers = &c2_handlers;
+
+	for (irq = 0; irq < NUM_ERR_INTS; irq++)
+		hw->err_irq_vecs[irq] = -1;
+
+	for (i = 0; i < NUM_ERR_INTS; i++) {
+		for (j = 0; j < MAX_ERR_FLAG_BITLEN; j++) {
+			ratelimit_default_init(&hw->err_rl[i][j]);
+			ratelimit_set_flags(&hw->err_rl[i][j],
+					    RATELIMIT_MSG_ON_RELEASE);
+		}
+	}
+
+	for (irq = 0; irq < NUM_ERR_INTS; irq++) {
+		for (i = 0; i < 2; i++) {
+			const struct csr_info *info = &INFO(irq, i);
+			struct sfs_err_flg *sfs = &hw->sfs_err_flg[irq][i];
+
+			if (info->csr_name == NULL)
+				continue;
+
+			sfs->bitlen = info->bitlen;
+		}
+	}
+
+	hw->err_flgs_dir_kobj[0] =
+		kobject_create_and_add("err_flgs_irqa",
+				       &hw->cdev.pdev->dev.kobj);
+	if (hw->err_flgs_dir_kobj[0] == NULL)
+		return -ENOMEM;
+
+	alloc_kobjs_and_hw_errors(hw);
+
+	/* Hardcode some options. */
+
+	/* PI.UC_ATTENTION[] should not be printed, and never masked. */
+	sfs = &hw->sfs_err_flg[C_PI_IRQA_MSIX_INT][0];
+	sfs->no_print_mask.pi.uc_attention = 0b11;
+	sfs->no_auto_mask.pi.uc_attention = 0b11;
+
+	/* Mask some PCIe errors that are monitored by the driver's
+	 * PCIe monitor, and other errors we don't want to see.
+	 */
+	sfs = &hw->sfs_err_flg[C_PI_IPD_IRQA_MSIX_INT][1];
+	bitmap_zero(bitmask.mask, sfs->bitlen);
+	bitmask.pi_ipd_ext.ip_cfg_bad_tlp_err_sts = 1;
+	bitmask.pi_ipd_ext.ip_cfg_bad_dllp_err_sts = 1;
+	bitmask.pi_ipd_ext.ip_cfg_replay_timer_timeout_err_sts = 1;
+	bitmask.pi_ipd_ext.ip_cfg_replay_number_rollover_err_sts = 1;
+	bitmask.pi_ipd_ext.pri_rbyp_abort = 1;
+	bitmap_copy(sfs->no_print_mask.mask, bitmask.mask, sfs->bitlen);
+	cxi_disable_hw_errors(hw, C_PI_IPD_IRQA_MSIX_INT, true, bitmask.mask);
+
+	sfs = &hw->sfs_err_flg[C_PI_IRQA_MSIX_INT][1];
+	sfs->no_print_mask.pi_ext.pri_rarb_xlat_rbyp_abort_error = 1;
+
+	/* ATU.PRB_EXPIRED should not be printed, and never
+	 * masked. Ignore some other.
+	 */
+	sfs = &hw->sfs_err_flg[C_ATU_IRQA_MSIX_INT][0];
+	sfs->no_print_mask.atu.prb_expired = 1;
+	sfs->no_auto_mask.atu.prb_expired = 1;
+	sfs->no_print_mask.atu.invalid_ac = 1;
+	sfs->no_print_mask.atu.no_translation = 1;
+
+	bitmap_zero(bitmask.mask, sfs->bitlen);
+	bitmask.atu.invalid_ac = 1;
+	bitmask.atu.no_translation = 1;
+	cxi_disable_hw_errors(hw, C_ATU_IRQA_MSIX_INT, false, bitmask.mask);
+
+	/* Ignore some RMU errors. */
+	sfs = &hw->sfs_err_flg[C_RMU_IRQA_MSIX_INT][0];
+	sfs->no_print_mask.rmu.enet_frame_rejected = 1;
+	sfs->no_print_mask.rmu.ptl_no_ptlte = 1;
+
+	bitmap_copy(bitmask.mask, sfs->no_print_mask.mask, sfs->bitlen);
+	cxi_disable_hw_errors(hw, C_RMU_IRQA_MSIX_INT, false, bitmask.mask);
+
+	/* Ignore some LPE errors. */
+	sfs = &hw->sfs_err_flg[C_LPE_IRQA_MSIX_INT][0];
+	sfs->no_print_mask.lpe.entry_not_found = 1;
+	sfs->no_print_mask.lpe.pt_disabled_dis = 1;
+	sfs->no_print_mask.lpe.pt_disabled_fc = 1;
+	sfs->no_print_mask.lpe.src_error = 1;
+
+	bitmap_copy(bitmask.mask, sfs->no_print_mask.mask, sfs->bitlen);
+	cxi_disable_hw_errors(hw, C_LPE_IRQA_MSIX_INT, false, bitmask.mask);
+
+	/* Some PCT EXT errors can be ignored in C1*/
+	if (cass_version(hw, CASSINI_1)) {
+		sfs = &hw->sfs_err_flg[C_PCT_IRQA_MSIX_INT][1];
+		bitmap_zero(bitmask.mask, sfs->bitlen);
+		bitmask.pct_ext.sct_tbl_rd_misc_unused = 1;
+		bitmask.pct_ext.sct_tbl_rd_ram_unused = 1;
+		cxi_disable_hw_errors(hw, C_PCT_IRQA_MSIX_INT, true, bitmask.mask);
+	}
+
+	/* Mask some EE errors and don't print them */
+	sfs = &hw->sfs_err_flg[C_EE_IRQA_MSIX_INT][0];
+	sfs->no_print_mask.ee.eq_dsabld_event = 1;
+
+	bitmap_zero(bitmask.mask, sfs->bitlen);
+	bitmask.ee.eq_dsabld_event = 1;
+	cxi_disable_hw_errors(hw, C_EE_IRQA_MSIX_INT, false, bitmask.mask);
+
+	/* Disable some link management error flags in HNI_PML. These
+	 * bits are controlled by the link driver.
+	 */
+	if (cass_version(hw, CASSINI_2)) {
+		sfs = &hw->sfs_err_flg[C_HNI_IRQA_MSIX_INT][0];
+		bitmap_zero(bitmask.mask, sfs->bitlen);
+		bitmask.c2_hni.llr_eopb = 1;
+		bitmap_copy(sfs->no_auto_mask.mask, bitmask.mask, sfs->bitlen);
+		cxi_disable_hw_errors(hw, C_HNI_IRQA_MSIX_INT, false, bitmask.mask);
+
+		sfs = &hw->sfs_err_flg[C_HNI_IRQA_MSIX_INT][1];
+		bitmap_zero(bitmask.mask, sfs->bitlen);
+		bitmask.c2_hni_ext.pmi_ack = 1;
+		bitmap_copy(sfs->no_auto_mask.mask, bitmask.mask, sfs->bitlen);
+		cxi_disable_hw_errors(hw, C_HNI_IRQA_MSIX_INT, true, bitmask.mask);
+	}
+
+	sfs = &hw->sfs_err_flg[C_HNI_PML_IRQA_MSIX_INT][0];
+	bitmap_zero(bitmask.mask, sfs->bitlen);
+	if (cass_version(hw, CASSINI_1)) {
+		sfs->no_print_mask.c1_hni_pml.autoneg_page_received = 1;
+		sfs->no_print_mask.c1_hni_pml.autoneg_complete = 1;
+		sfs->no_print_mask.c1_hni_pml.pcs_lanes_locked = 1;
+		sfs->no_print_mask.c1_hni_pml.pcs_aligned = 1;
+		sfs->no_print_mask.c1_hni_pml.pcs_ready = 1;
+		sfs->no_print_mask.c1_hni_pml.pcs_link_down = 1;
+
+		bitmask.c1_hni_pml.autoneg_page_received = 1;
+		bitmask.c1_hni_pml.autoneg_complete = 1;
+		bitmask.c1_hni_pml.pcs_hi_ser = 1;
+		bitmask.c1_hni_pml.pcs_link_down = 1;
+		bitmask.c1_hni_pml.llr_replay_at_max = 1;
+		bitmask.c1_hni_pml.pcs_lanes_locked = 1;
+		bitmask.c1_hni_pml.pcs_aligned = 1;
+		bitmask.c1_hni_pml.pcs_ready = 1;
+	} else {
+		bitmask.ss2_port_pml.autoneg_page_received_0 = 1;
+		bitmask.ss2_port_pml.autoneg_failed_0 = 1;
+
+		bitmask.ss2_port_pml.llr_init_complete_0 = 1;
+		bitmask.ss2_port_pml.llr_init_fail_0 = 1;
+		bitmask.ss2_port_pml.llr_loop_time_0 = 1;
+		bitmask.ss2_port_pml.llr_loop_time_fail_0 = 1;
+		bitmask.ss2_port_pml.llr_replay_at_max_0 = 1;
+		bitmask.ss2_port_pml.llr_tx_dp_err = 1;
+		bitmask.ss2_port_pml.llr_rx_dp_err = 1;
+
+		bitmask.ss2_port_pml.pcs_aligned_0 = 1;
+		bitmask.ss2_port_pml.pcs_hi_ser_0 = 1;
+		bitmask.ss2_port_pml.pcs_lanes_locked_0 = 1;
+		bitmask.ss2_port_pml.pcs_link_down_0 = 1;
+		bitmask.ss2_port_pml.pcs_link_down_lf_0 = 1;
+		bitmask.ss2_port_pml.pcs_link_down_rf_0 = 1;
+		bitmask.ss2_port_pml.pcs_link_up_0 = 1;
+		bitmask.ss2_port_pml.pcs_tx_dp_err = 1;
+		bitmask.ss2_port_pml.pcs_rx_dp_err = 1;
+
+		bitmask.ss2_port_pml.mac_tx_dp_err = 1;
+		bitmask.ss2_port_pml.mac_rx_dp_err = 1;
+		bitmask.ss2_port_pml.mac_rx_fcs32_err_0 = 1;
+		bitmask.ss2_port_pml.mac_rx_framing_err_0 = 1;
+		bitmask.ss2_port_pml.mac_rx_preamble_err_0 = 1;
+	}
+
+	bitmap_copy(sfs->no_auto_mask.mask, bitmask.mask, sfs->bitlen);
+	cxi_disable_hw_errors(hw, C_HNI_PML_IRQA_MSIX_INT, false, bitmask.mask);
+
+	/* Allocate the work queue with a single worker. */
+	hw->err_irq_wq = alloc_workqueue("error_wq", WQ_UNBOUND, 1);
+	if (!hw->err_irq_wq) {
+		rc = -ENOMEM;
+		goto free_err_flg_kobjs;
+	}
+
+	INIT_WORK(&hw->err_irq_work, error_irq_worker);
+
+	/* Register all 15 IRQA interrupts. */
+	hw->err_irq_mask = 0x7fff;
+
+	/* Register and activate all the error reporting
+	 * interrupts.
+	 */
+	for_each_set_bit(irq, &hw->err_irq_mask, NUM_ERR_INTS) {
+		int vec;
+		char irq_name[CASS_MAX_IRQ_NAME];
+
+		vec = pci_irq_vector(hw->cdev.pdev, irq);
+		hw->err_irq_vecs[irq] = vec;
+
+		scnprintf(irq_name, CASS_MAX_IRQ_NAME,  "%s_err_%s",
+			  hw->cdev.name, INFO(irq, 0).csr_name_lo);
+		strcpy(hw->err_int_names[irq], irq_name);
+		rc = request_irq(vec, error_irq_cb, 0,
+				 hw->err_int_names[irq], hw);
+		if (rc) {
+			cxidev_err(&hw->cdev, "Failed to request IRQ for events.\n");
+			hw->err_irq_vecs[irq] = -1;
+			goto remove;
+		}
+	}
+
+	return 0;
+
+remove:
+	free_err_irqs(hw);
+	destroy_workqueue(hw->err_irq_wq);
+	hw->err_irq_wq = NULL;
+
+free_err_flg_kobjs:
+	free_kobjs_and_hw_errors(hw);
+
+	kobject_put(hw->err_flgs_dir_kobj[0]);
+
+	return rc;
+}
+
+void deregister_error_handlers(struct cass_dev *hw)
+{
+	free_err_irqs(hw);
+	destroy_workqueue(hw->err_irq_wq);
+	hw->err_irq_wq = NULL;
+	free_kobjs_and_hw_errors(hw);
+	kobject_put(hw->err_flgs_dir_kobj[0]);
+}
diff --git a/drivers/net/ethernet/hpe/ss1/cass_eth.c b/drivers/net/ethernet/hpe/ss1/cass_eth.c
new file mode 100644
index 000000000000..726e22da1d6a
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_eth.c
@@ -0,0 +1,702 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2019, 2022, 2024-2026 Hewlett Packard Enterprise Development LP */
+
+/* Core driver support for Ethernet devices */
+
+#include <linux/hpe/cxi/cxi.h>
+#include <linux/hpe/cxi/driver.h>
+#include <linux/etherdevice.h>
+
+#include "cass_core.h"
+
+/* TODO: documentation format is incorrect. Use kernel documentation
+ * format for functions
+ */
+/**
+ * cxi_eth_set_list() - Program the RMU address filter
+ *
+ * @cdev: CXI device
+ * @res: Ethernet resource with catch-all portal in C_PTLTE_ETHERNET state
+ * @set_list: how to program the set list
+ * @set_list_mask: valid bits for @set_list
+ * @is_ptp: whether the MAC address is for PTP timestamping
+ *
+ * @return: 0 on success or a negative errno
+ */
+static int cxi_eth_set_list(struct cxi_dev *cdev,
+			    struct cxi_eth_res *res,
+			    const union c_rmu_cfg_ptlte_set_list *set_list,
+			    const union c_rmu_cfg_ptlte_set_list *set_list_mask,
+			    bool is_ptp)
+{
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	int set_list_idx;
+
+	set_list_idx = ida_alloc_max(&hw->set_list_table,
+				     C_RMU_CFG_PTLTE_SET_LIST_ENTRIES - 1,
+				     GFP_KERNEL);
+	if (set_list_idx < 0)
+		return -EINVAL;
+
+	set_bit(set_list_idx, res->sl);
+
+	spin_lock(&hw->rmu_lock);
+
+	cass_config_set_list(hw, set_list_idx,
+			     is_ptp ? res->ptn_ptp : res->ptn_def,
+			     set_list, set_list_mask);
+
+	spin_unlock(&hw->rmu_lock);
+
+	return 0;
+}
+
+/**
+ * cxi_eth_add_mac() - Add a MAC address match for an Ethernet PTE
+ *
+ * Program the RMU filter to accept the given MAC address.
+ *
+ * @cdev: CXI device
+ * @res: Ethernet resource with catch-all portal in C_PTLTE_ETHERNET state
+ * @mac_addr: A MAC address
+ * @is_ptp: whether the MAC address is for PTP timestamping
+ *
+ * @return: 0 on success or a negative errno
+ */
+int cxi_eth_add_mac(struct cxi_dev *cdev, struct cxi_eth_res *res,
+		    u64 mac_addr, bool is_ptp)
+{
+	const union c_rmu_cfg_ptlte_set_list set_list = {
+		.frame_type = C_RMU_ENET_802_3,
+		.dmac = mac_addr,
+	};
+	/* Accept only that MAC */
+	union c_rmu_cfg_ptlte_set_list set_list_mask = {
+		.qw = {
+			[0] = ~set_list.qw[0],
+			[1] = ~set_list.qw[1],
+			[2] = ~set_list.qw[2],
+			[3] = ~set_list.qw[3],
+		}
+	};
+
+	/* Ignore any bits which could prevent an Ethernet packet from landing
+	 * against the configured MAC address.
+	 */
+	set_list_mask.vlan_present = 0;
+	set_list_mask.pcp = 0;
+	set_list_mask.dei = 0;
+	set_list_mask.vid = 0;
+	set_list_mask.lossless = 0;
+
+	return cxi_eth_set_list(cdev, res, &set_list, &set_list_mask, is_ptp);
+}
+EXPORT_SYMBOL(cxi_eth_add_mac);
+
+/**
+ * cxi_eth_set_promiscuous() - Set the Ethernet promiscuous mode
+ *
+ * Program the RMU filter to accept any MAC address. This essentially
+ * moves the Ethernet adapter into promiscuous mode.
+ *
+ * @cdev: CXI device
+ * @res: Ethernet resource with catch-all portal in C_PTLTE_ETHERNET state
+ *
+ * @return: 0 on success or a negative errno
+ */
+int cxi_eth_set_promiscuous(struct cxi_dev *cdev, struct cxi_eth_res *res)
+{
+	const union c_rmu_cfg_ptlte_set_list set_list = {
+		.frame_type = C_RMU_ENET_802_3,
+	};
+	const union c_rmu_cfg_ptlte_set_list set_list_mask = {
+		.qw = {
+			[2] = ~set_list.qw[2],
+			[3] = ~set_list.qw[3],
+		}
+	};
+
+	return cxi_eth_set_list(cdev, res, &set_list, &set_list_mask, false);
+}
+EXPORT_SYMBOL(cxi_eth_set_promiscuous);
+
+/**
+ * cxi_eth_set_all_multi() - Receive all multicast Ethernet packets
+ *
+ * Program the RMU filter to accept any multicast Ethernet traffic.
+ *
+ * @cdev: CXI device
+ * @res: Ethernet resource with catch-all portal in C_PTLTE_ETHERNET state
+ *
+ * @return: 0 on success or a negative errno
+ */
+int cxi_eth_set_all_multi(struct cxi_dev *cdev, struct cxi_eth_res *res)
+{
+	const union c_rmu_cfg_ptlte_set_list set_list = {
+		.frame_type = C_RMU_ENET_802_3,
+		.dmac = 0x010000000000ULL, /* MAC multicast bit */
+	};
+	const union c_rmu_cfg_ptlte_set_list set_list_mask = {
+		.qw = {
+			[2] = ~set_list.qw[2],
+			[3] = ~set_list.qw[3],
+		}
+	};
+
+	return cxi_eth_set_list(cdev, res, &set_list, &set_list_mask, false);
+}
+EXPORT_SYMBOL(cxi_eth_set_all_multi);
+
+/**
+ * cxi_eth_set_list_invalidate_all() - Invalidate all entries in set list
+ *
+ * @cdev: CXI device
+ * @res: Ethernet resource with catch-all portal in C_PTLTE_ETHERNET state
+ */
+void cxi_eth_set_list_invalidate_all(struct cxi_dev *cdev,
+				     struct cxi_eth_res *res)
+{
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	int set_list_idx;
+
+	for_each_set_bit(set_list_idx, res->sl,
+			 C_RMU_CFG_PTLTE_SET_LIST_ENTRIES) {
+		cass_invalidate_set_list(hw, set_list_idx);
+
+		ida_free(&hw->set_list_table, set_list_idx);
+	}
+
+	bitmap_zero(res->sl, C_RMU_CFG_PTLTE_SET_LIST_ENTRIES);
+}
+EXPORT_SYMBOL(cxi_eth_set_list_invalidate_all);
+
+/**
+ * cass_eth_set_hash_types() - Set the hashing types
+ *
+ * @cdev: CXI device
+ * @res: Ethernet resource with catch-all portal in C_PTLTE_ETHERNET state
+ * @entry: content to program, include the hash types to enable
+ */
+static void cass_eth_set_hash_types(struct cxi_dev *cdev,
+				    const struct cxi_eth_res *res,
+				    const struct c_rmu_cfg_ptlte_set_ctrl_table_entry *entry)
+{
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	unsigned int sl_idx;
+
+	/* Set the hashing type on each used Set Ctrl entries */
+	for_each_set_bit(sl_idx, res->sl, C_RMU_CFG_PTLTE_SET_LIST_ENTRIES)
+		cass_config_set_ctrl(hw, sl_idx, entry);
+}
+
+/**
+ * cxi_eth_set_indir_table() - Set the indirection tables
+ *
+ * Program the indirection table, and reset the corresponding Set Ctrl
+ * entries.
+ *
+ * @cdev: CXI device
+ * @res: Ethernet resource with catch-all portal in C_PTLTE_ETHERNET state
+ *
+ * @return: 0 on success or a negative errno
+ */
+void cxi_eth_set_indir_table(struct cxi_dev *cdev, struct cxi_eth_res *res)
+{
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	struct c_rmu_cfg_ptlte_set_ctrl_table_entry entry = {
+		.portal_index_indir_base = res->portal_index_indir_base,
+		.hash_bits = ilog2(res->rss_queues),
+		.hash_types_enabled = res->hash_types_enabled,
+	};
+	int i;
+
+	/* Disable hashing */
+	cxi_eth_clear_indir_table(cdev, res);
+
+	/* Exit now if there is no hash requested, or nothing to hash to. */
+	if (res->hash_types_enabled == 0 || res->rss_queues == 0 ||
+	    res->rss_indir_size == 0)
+		return;
+
+	/* Program the table */
+	for (i = 0; i < res->rss_indir_size; i++)
+		cass_config_indir_entry(hw, res->portal_index_indir_base + i,
+					res->ptn_rss[res->indir_table[i]]);
+
+	/* Re-enable hashing */
+	cass_eth_set_hash_types(cdev, res, &entry);
+}
+EXPORT_SYMBOL(cxi_eth_set_indir_table);
+
+/**
+ * cxi_eth_clear_indir_table() - Clear the indirection tables
+ *
+ * Reset the indirection table, which disables RSS hashing.
+ *
+ * @cdev: CXI device
+ * @res: Ethernet resource with catch-all portal in C_PTLTE_ETHERNET state
+ *
+ * @return: 0 on success or a negative errno
+ */
+void cxi_eth_clear_indir_table(struct cxi_dev *cdev, struct cxi_eth_res *res)
+{
+	static const struct c_rmu_cfg_ptlte_set_ctrl_table_entry entry = {};
+
+	cass_eth_set_hash_types(cdev, res, &entry);
+}
+EXPORT_SYMBOL(cxi_eth_clear_indir_table);
+
+/**
+ * cxi_eth_get_hash_key() - Retrieve the RSS hash key
+ *
+ * @cdev: CXI device
+ * @key: A sufficiently large (CXI_ETH_HASH_KEY_SIZE) array to store the key.
+ */
+void cxi_eth_get_hash_key(struct cxi_dev *cdev, u8 *key)
+{
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	union c_rmu_cfg_hash_key hash_key;
+
+	spin_lock(&hw->rmu_lock);
+	cass_read(hw, C_RMU_CFG_HASH_KEY, &hash_key, sizeof(hash_key));
+	spin_unlock(&hw->rmu_lock);
+
+	memcpy(key, hash_key.qw, CXI_ETH_HASH_KEY_SIZE);
+}
+EXPORT_SYMBOL(cxi_eth_get_hash_key);
+
+/**
+ * cxi_set_ethernet_threshold() - Configure the Ethernet buffer threshold
+ * @cdev: CXI device
+ * @threshold: Threshold to set
+ *
+ * See C_LPE_CFG_ETHERNET_THRESHOLD documentation
+ */
+void cxi_set_ethernet_threshold(struct cxi_dev *cdev, unsigned int threshold)
+{
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	union c_lpe_cfg_ethernet_threshold eth_thr = {
+		.threshold = threshold,
+	};
+
+	if (!cdev->is_physfn)
+		return;
+
+	cass_write(hw, C_LPE_CFG_ETHERNET_THRESHOLD, &eth_thr, sizeof(eth_thr));
+}
+EXPORT_SYMBOL(cxi_set_ethernet_threshold);
+
+/**
+ * cxi_set_roce_rcv_seg() - Control RoCE receive segmentation
+ *
+ * Whether to enable or disable the RoCE receive segmentation. When
+ * enabled, the HW will put the RoCE payload in a separate SKB
+ * fragment, and the driver will add the RoCE CRC in a third fragment.
+ *
+ * @cdev: CXI device
+ * @enable: true to enable, false to disable
+ */
+void cxi_set_roce_rcv_seg(struct cxi_dev *cdev, bool enable)
+{
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	union c_ixe_cfg_roce cfg_roce;
+
+	if (!cdev->is_physfn)
+		return;
+
+	cass_read(hw, C_IXE_CFG_ROCE, &cfg_roce, sizeof(cfg_roce));
+	cfg_roce.enable_1k = enable;
+	cfg_roce.enable_2k = enable;
+	cfg_roce.enable_4k = enable;
+	cass_write(hw, C_IXE_CFG_ROCE, &cfg_roce, sizeof(cfg_roce));
+}
+EXPORT_SYMBOL(cxi_set_roce_rcv_seg);
+
+static void cxi_eth_devinfo_vf(struct cxi_dev *cdev, struct cxi_eth_info *eth_info)
+{
+	const struct cxi_eth_dev_info_get_cmd cmd = {
+		.op = CXI_OP_ETH_DEV_INFO_GET,
+		.buf_size = sizeof(*eth_info),
+	};
+	size_t resp_len = sizeof(*eth_info);
+	int rc;
+
+	rc = cxi_send_msg_to_pf(cdev, &cmd, sizeof(cmd), eth_info, &resp_len);
+	if (rc)
+		goto err;
+
+	if (resp_len != sizeof(*eth_info)) {
+		cxidev_err(cdev, "Invalid response length: %zu (expected %zu)\n",
+			   resp_len, sizeof(*eth_info));
+		goto err;
+	}
+
+	return;
+
+err:
+	memset(eth_info, 0, sizeof(*eth_info));
+}
+
+/**
+ * cxi_eth_devinfo() - Get some current Ethernet related device information
+ *
+ * @cdev: CXI device
+ * @eth_info: structure to return the information
+ */
+void cxi_eth_devinfo(struct cxi_dev *cdev, struct cxi_eth_info *eth_info)
+{
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	union c_ixe_cfg_parser cfg_parser;
+
+	if (!cdev->is_physfn) {
+		cxi_eth_devinfo_vf(cdev, eth_info);
+		return;
+	}
+
+	cass_read(hw, C_IXE_CFG_PARSER, &cfg_parser, sizeof(cfg_parser));
+	eth_info->max_segment_size = (cfg_parser.eth_segment + 1) * 128;
+	ether_addr_copy(eth_info->default_mac_addr, hw->default_mac_addr);
+
+	mutex_lock(&hw->qsfp_eeprom_lock);
+	eth_info->qsfp_eeprom_len = hw->qsfp_eeprom_page_len;
+	memcpy(eth_info->qsfp_eeprom, hw->qsfp_eeprom_page0, hw->qsfp_eeprom_page_len);
+	mutex_unlock(&hw->qsfp_eeprom_lock);
+
+	if (hw->fw_versions[FW_QSPI_BLOB])
+		strscpy(eth_info->fw_version, hw->fw_versions[FW_QSPI_BLOB],
+			sizeof(eth_info->fw_version));
+
+	if (hw->fw_versions[FW_OPROM])
+		strscpy(eth_info->erom_version, hw->fw_versions[FW_OPROM],
+			sizeof(eth_info->erom_version));
+
+	eth_info->ptp_clock_index = ptp_clock_index(hw->ptp_clock);
+	eth_info->min_free_shift = cdev->prop.min_free_shift;
+}
+EXPORT_SYMBOL(cxi_eth_devinfo);
+
+/**
+ * cxi_set_led_beacon() - Activate or deactivate LED beacon
+ *
+ * @cdev: CXI device
+ * @state: true to activate, false to deactivate
+ */
+void cxi_set_led_beacon(struct cxi_dev *cdev, bool state)
+{
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+
+	if (!cdev->is_physfn)
+		return;
+
+	hw->qsfp_beacon_active = state;
+	cass_link_set_led(hw);
+}
+EXPORT_SYMBOL(cxi_set_led_beacon);
+
+/**
+ * cxi_set_eth_name() - Set an Ethernet device name to a CXI interface
+ *
+ * When an Ethernet interface is added, call this function to match
+ * both interfaces. This is to be used primarily for logging, as it's
+ * not always clear which CXI device an Ethernet interface belongs to.
+ *
+ * @cdev: CXI device
+ * @name: Ethernet name assigned to the device, such as "hsn0" or "eth0".
+ */
+void cxi_set_eth_name(struct cxi_dev *cdev, const char *name)
+{
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+
+	strscpy(cdev->eth_name, name, sizeof(cdev->eth_name));
+
+	/* Update name in sbl/sl (only in PF) */
+	if (cdev->is_physfn)
+		hw->link_ops->eth_name_set(hw, cdev->eth_name);
+}
+EXPORT_SYMBOL(cxi_set_eth_name);
+
+/**
+ * cxi_eth_cfg_timestamp() - timestamping of packets
+ *
+ * @cdev: CXI device
+ * @config: timestamp configuration. TX filter must be
+ *          HWTSTAMP_TX_ON/OFF, and RX filter must be
+ *          HWTSTAMP_FILTER_NONE or HWTSTAMP_FILTER_PTP_V2_L2_EVENT.
+ *
+ * TODO: locking ? from caller?
+ */
+int cxi_eth_cfg_timestamp(struct cxi_dev *cdev,
+			  struct hwtstamp_config *config)
+{
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	union c_hni_cfg_gen cfg_gen;
+
+	if (!cdev->is_physfn)
+		return -EOPNOTSUPP;
+
+	if (config->flags != 0)
+		return -EINVAL;
+
+	if (config->tx_type != HWTSTAMP_TX_OFF &&
+	    config->tx_type != HWTSTAMP_TX_ON)
+		return -EINVAL;
+
+	if (config->rx_filter != HWTSTAMP_FILTER_NONE &&
+	    config->rx_filter != HWTSTAMP_FILTER_PTP_V2_L2_EVENT)
+		return -EINVAL;
+
+	/* Turn everything on if any timestamping is requested. */
+	if (config->tx_type != HWTSTAMP_TX_OFF)
+		config->tx_type = HWTSTAMP_TX_ON;
+
+	cass_read(hw, C_HNI_CFG_GEN, &cfg_gen, sizeof(cfg_gen));
+
+	cfg_gen.tx_timestamp_en = config->tx_type == HWTSTAMP_TX_ON;
+	cfg_gen.rx_timestamp_en =
+		config->rx_filter == HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
+
+	if (cfg_gen.tx_timestamp_en) {
+		/* Only program IEEE-1588 packets. */
+		static const union c_hni_cfg_txts_l2_mask l2_mask = {
+			.dmac = ~0,
+			.ethertype = 0,
+		};
+		static const union c_hni_cfg_txts_l2_match l2_match = {
+			.dmac = 0,
+			.ethertype = PTP_L2_ETHERTYPE,
+		};
+		static const union c_hni_cfg_txts_l3_mask l3_mask = {
+			.hdr = ~0,
+		};
+		static const union c_hni_cfg_txts_l3_match l3_match = {
+			.hdr = 0,
+		};
+		union c_hni_pml_sts_tx_pcs tx_ts;
+
+		cass_write(hw, C_HNI_CFG_TXTS_L2_MASK,
+			   &l2_mask, sizeof(l2_mask));
+		cass_write(hw, C_HNI_CFG_TXTS_L2_MATCH,
+			   &l2_match, sizeof(l2_match));
+		cass_write(hw, C_HNI_CFG_TXTS_L3_MASK,
+			   &l3_mask, sizeof(l3_mask));
+		cass_write(hw, C_HNI_CFG_TXTS_L3_MATCH,
+			   &l3_match, sizeof(l3_match));
+
+		/* Set the timestamp format/shift in 2 CSRs */
+		cfg_gen.timestamp_fmt = hw->tx_timestamp_shift;
+
+		if (cass_version(hw, CASSINI_1)) {
+			union c1_hni_pml_cfg_pcs cfg_pcs;
+
+			cass_read(hw, C1_HNI_PML_CFG_PCS, &cfg_pcs, sizeof(cfg_pcs));
+			cfg_pcs.timestamp_shift = hw->tx_timestamp_shift;
+			cass_write(hw, C1_HNI_PML_CFG_PCS, &cfg_pcs, sizeof(cfg_pcs));
+
+			/* Clear the timestamp_valid bit just in case */
+			cass_read(hw, C1_HNI_PML_STS_TX_PCS, &tx_ts, sizeof(tx_ts));
+			tx_ts.timestamp_valid = 0;
+			cass_write(hw, C1_HNI_PML_STS_TX_PCS, &tx_ts, sizeof(tx_ts));
+		} else {
+			union ss2_port_pml_cfg_pcs cfg_pcs;
+
+			cass_read(hw, SS2_PORT_PML_CFG_PCS, &cfg_pcs, sizeof(cfg_pcs));
+			cfg_pcs.timestamp_shift = hw->tx_timestamp_shift;
+			cass_write(hw, SS2_PORT_PML_CFG_PCS, &cfg_pcs, sizeof(cfg_pcs));
+
+			/* Clear the timestamp_valid bit just in case */
+			cass_read(hw, SS2_PORT_PML_STS_TX_PCS(0), &tx_ts, sizeof(tx_ts));
+			tx_ts.timestamp_valid = 0;
+			cass_write(hw, SS2_PORT_PML_STS_TX_PCS(0), &tx_ts, sizeof(tx_ts));
+		}
+	}
+
+	if (cfg_gen.rx_timestamp_en) {
+		/* WORKAROUND: Cassini ERRATA-3258, only program IEEE-1588 packets. */
+		static const union c_hni_cfg_rxts_l2_mask l2_mask = {
+			.dmac = 0,
+			.ethertype = 0,
+		};
+		static const union c_hni_cfg_rxts_l2_match l2_match = {
+			.dmac = PTP_L2_MAC,
+			.ethertype = PTP_L2_ETHERTYPE,
+		};
+		static const union c_hni_cfg_rxts_l3_mask l3_mask = {
+			.hdr = ~0,
+		};
+		static const union c_hni_cfg_rxts_l3_match l3_match = {
+			.hdr = 0,
+		};
+
+		cass_write(hw, C_HNI_CFG_RXTS_L2_MASK,
+			   &l2_mask, sizeof(l2_mask));
+		cass_write(hw, C_HNI_CFG_RXTS_L2_MATCH,
+			   &l2_match, sizeof(l2_match));
+		cass_write(hw, C_HNI_CFG_RXTS_L3_MASK,
+			   &l3_mask, sizeof(l3_mask));
+		cass_write(hw, C_HNI_CFG_RXTS_L3_MATCH,
+			   &l3_match, sizeof(l3_match));
+	}
+
+	cass_write(hw, C_HNI_CFG_GEN, &cfg_gen, sizeof(cfg_gen));
+	cass_flush_pci(hw);
+
+	return 0;
+}
+EXPORT_SYMBOL(cxi_eth_cfg_timestamp);
+
+/**
+ * cxi_eth_get_tx_timestamp() - Retrieve current Ethernet TX timestamp
+ *
+ * After the driver requested timestamping of Ethernet TX packets, the
+ * Ethernet driver can retrieve the current timestamp upon the send
+ * completion.
+ *
+ * @cdev: CXI device
+ * @tstamps: storage to return the timestamp
+ **/
+int cxi_eth_get_tx_timestamp(struct cxi_dev *cdev,
+			     struct skb_shared_hwtstamps *tstamps)
+{
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	union c_hni_err_elapsed_time err_elapsed_time;
+	union c_hni_cfg_rt_offset rt_offset;
+	union c_hni_pml_sts_tx_pcs tx_ts;
+	struct timespec64 ts;
+	u64 ts_sec;
+	u64 curr_sec;
+	u64 diff_sec;
+
+	if (!cdev->is_physfn)
+		return -EOPNOTSUPP;
+
+	/* Note: union c_hni_pml_sts_tx_pcs and union
+	 * ss2_port_pml_sts_tx_pcs are identical structures.
+	 */
+	if (cass_version(hw, CASSINI_1))
+		cass_read(hw, C1_HNI_PML_STS_TX_PCS, &tx_ts, sizeof(tx_ts));
+	else
+		cass_read(hw, SS2_PORT_PML_STS_TX_PCS(0), &tx_ts, sizeof(tx_ts));
+
+	cass_read(hw, C_HNI_ERR_ELAPSED_TIME,
+		  &err_elapsed_time, sizeof(err_elapsed_time));
+	cass_read(hw, C_HNI_CFG_RT_OFFSET, &rt_offset, sizeof(rt_offset));
+
+	if (WARN_ON_ONCE(!tx_ts.timestamp_valid))
+		return -ENODATA;
+
+	switch (hw->tx_timestamp_shift) {
+	case 0:
+		ts.tv_nsec = tx_ts.timestamp & (BIT(30) - 1) * 1;
+		ts_sec = tx_ts.timestamp >> 30;
+		curr_sec = err_elapsed_time.seconds & ((BIT(2) - 1));
+		diff_sec = BIT(2);
+		break;
+	case 1:
+		ts.tv_nsec = (tx_ts.timestamp & (BIT(28) - 1)) * 4;
+		ts_sec = tx_ts.timestamp >> 28;
+		curr_sec = err_elapsed_time.seconds & ((BIT(4) - 1));
+		diff_sec = BIT(4);
+		break;
+	case 2:
+		ts.tv_nsec = (tx_ts.timestamp & (BIT(26) - 1)) * 16;
+		ts_sec = tx_ts.timestamp >> 26;
+		curr_sec = err_elapsed_time.seconds & ((BIT(6) - 1));
+		diff_sec = BIT(6);
+		break;
+	case 3:
+		ts.tv_nsec = (tx_ts.timestamp & (BIT(24) - 1)) * 64;
+		ts_sec = tx_ts.timestamp >> 24;
+		curr_sec = err_elapsed_time.seconds & ((BIT(8) - 1));
+		diff_sec = BIT(8);
+		break;
+	default:
+		/* Normally unreachable */
+		cxidev_WARN_ONCE(cdev, true, "bad tx_timestamp_shift");
+		return -EINVAL;
+	}
+
+	if (curr_sec < ts_sec)
+		diff_sec += curr_sec - ts_sec;
+	else
+		diff_sec = curr_sec - ts_sec;
+
+	ts.tv_sec = rt_offset.seconds + err_elapsed_time.seconds - diff_sec;
+
+	tstamps->hwtstamp = timespec64_to_ktime(ts);
+
+	/* Clear valid bit for next packet. */
+	tx_ts.timestamp_valid = 0;
+	if (cass_version(hw, CASSINI_1))
+		cass_write(hw, C1_HNI_PML_STS_TX_PCS, &tx_ts, sizeof(tx_ts));
+	else
+		cass_write(hw, SS2_PORT_PML_STS_TX_PCS(0), &tx_ts, sizeof(tx_ts));
+
+	return 0;
+}
+EXPORT_SYMBOL(cxi_eth_get_tx_timestamp);
+
+static void cxi_eth_get_pause_vf(struct cxi_dev *cdev, struct ethtool_pauseparam *pause)
+{
+	struct cxi_eth_pause_get_cmd cmd = {
+		.op = CXI_OP_ETH_PAUSE_GET,
+	};
+	struct cxi_eth_get_pause_resp resp = {};
+	size_t resp_len = sizeof(resp);
+	int rc;
+
+	rc = cxi_send_msg_to_pf(cdev, &cmd, sizeof(cmd), &resp, &resp_len);
+	if (rc) {
+		/* On error, set pause to disabled */
+		pause->tx_pause = false;
+		pause->rx_pause = false;
+		return;
+	}
+
+	pause->tx_pause = resp.tx_pause;
+	pause->rx_pause = resp.rx_pause;
+}
+
+/**
+ * cxi_eth_get_pause() - Enable of disable the RX and TX pause packets
+ *
+ * @cdev: CXI device
+ * @pause: ethtool parameters
+ */
+void cxi_eth_get_pause(struct cxi_dev *cdev, struct ethtool_pauseparam *pause)
+{
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	union c_hni_cfg_pause_tx_ctrl tx_ctrl_cfg;
+	union c_hni_cfg_pause_rx_ctrl rx_ctrl_cfg;
+
+	if (!cdev->is_physfn) {
+		cxi_eth_get_pause_vf(cdev, pause);
+		return;
+	}
+
+	cass_read(hw, C_HNI_CFG_PAUSE_TX_CTRL, &tx_ctrl_cfg,
+		  sizeof(tx_ctrl_cfg));
+	pause->tx_pause = tx_ctrl_cfg.enable_send_pause != 0;
+
+	cass_read(hw, C_HNI_CFG_PAUSE_RX_CTRL, &rx_ctrl_cfg,
+		  sizeof(rx_ctrl_cfg));
+	pause->rx_pause = rx_ctrl_cfg.enable_rec_pause != 0;
+}
+EXPORT_SYMBOL(cxi_eth_get_pause);
+
+/**
+ * cxi_eth_set_pause() - Enable of disable the RX and TX pause packets
+ *
+ * @cdev: CXI device
+ * @pause: ethtool parameters
+ */
+void cxi_eth_set_pause(struct cxi_dev *cdev, const struct ethtool_pauseparam *pause)
+{
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+
+	if (!cdev->is_physfn)
+		return;
+
+	cass_tc_set_tx_pause_all(hw, pause->tx_pause);
+	cass_tc_set_rx_pause_all(hw, pause->rx_pause);
+}
+EXPORT_SYMBOL(cxi_eth_set_pause);
diff --git a/drivers/net/ethernet/hpe/ss1/cass_hmm.c b/drivers/net/ethernet/hpe/ss1/cass_hmm.c
new file mode 100644
index 000000000000..47fd47ea0ae7
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_hmm.c
@@ -0,0 +1,320 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2019 Hewlett Packard Enterprise Development LP */
+
+/* Handle differences in the HMM interface for different kernel versions. */
+
+#include "cass_core.h"
+#include "linux/sched/mm.h"
+
+int cass_vma_write_flag(struct mm_struct *mm, ulong start, ulong end, u32 flags)
+{
+	int write;
+	struct vm_area_struct *vma;
+
+	vma = find_vma_intersection(mm, start, end);
+
+	/* When prefetching, indicate to caller there is no VMA */
+	if (!vma && (flags & CXI_MAP_PREFETCH))
+		return -ENOENT;
+
+	if (!vma || start < vma->vm_start) {
+		pr_warn("No VMA covering 0x%016lx)\n", start);
+		return -EINVAL;
+	}
+
+	write = vma->vm_flags & VM_WRITE;
+	if (!write && (flags & CXI_MAP_WRITE)) {
+		pr_warn("VMA does not have write permissions\n");
+		return -EINVAL;
+	}
+
+	return write;
+}
+
+void cass_notifier_cleanup(struct cxi_md_priv *md_priv)
+{
+	if (!md_priv->mn_sub.mm)
+		return;
+
+	mmu_interval_notifier_remove(&md_priv->mn_sub);
+	md_priv->mn_sub.mm = NULL;
+}
+
+/* Fault in pages from all VMAs in the address range.
+ * When prefetching, ignore failures of VMAs that may have errors.
+ * If -EBUSY is returned, continue at the address where we left off on
+ * the next invocation.
+ *
+ * When faulting pages, the full range must be backed by contiguous VMAs.
+ * Return a failure if all pages cannot be faulted.
+ *
+ * When prefetching, if no VMAs are found, return 0.
+ */
+static int cass_range_fault(struct hmm_range *range, struct mm_struct *mm,
+			    const struct ac_map_opts *m_opts, ulong end)
+{
+	int ret = 0;
+	bool success = false;
+	ulong start = range->start;
+	ulong *pfns = range->hmm_pfns;
+	int flags = m_opts->flags;
+	int page_shift = m_opts->page_shift;
+	struct vm_area_struct *vma;
+#ifdef VMA_ITERATOR
+	VMA_ITERATOR(vmi, mm, start);
+#endif
+
+	vma = find_vma_intersection(mm, range->start, range->end);
+	if (!vma) {
+		if (flags & CXI_MAP_FAULT) {
+			pr_debug("Faulting region not backed by VMA\n");
+			return -EINVAL;
+		}
+
+		return 0;
+	}
+
+	/* When faulting, we expect the full range to be covered by VMA(s) */
+	if (range->default_flags & HMM_PFN_REQ_FAULT)
+		return hmm_range_fault(range);
+
+	for_each_vma(vmi, vma) {
+		if (vma->vm_start >= end)
+			break;
+
+		/* When prefetching, skip over VMAs that don't match
+		 * the requested permissions.
+		 */
+		if ((flags & CXI_MAP_WRITE && !(vma->vm_flags & VM_WRITE)) ||
+		    (flags & CXI_MAP_READ && !(vma->vm_flags & VM_READ))) {
+			continue;
+		}
+
+		if (vma->vm_end < end)
+			range->end = vma->vm_end;
+		else
+			range->end = end;
+
+		if (range->start < vma->vm_start)
+			range->start = vma->vm_start;
+
+		range->hmm_pfns = pfns + ((range->start - start) >> page_shift);
+
+		ret = hmm_range_fault(range);
+		if (ret == -EBUSY || ret == -ENOMEM)
+			return ret;
+
+		if (!ret || success)
+			success = true;
+
+		atu_debug("start:%lx end:%lx len:%lx vm_start:%lx vm_end:%lx vm_flags:%lx ret:%d\n",
+			  range->start, range->end, range->end - range->start,
+			  vma->vm_start, vma->vm_end, vma->vm_flags, ret);
+	}
+
+	return success ? 0 : ret;
+}
+
+/**
+ * cass_mirror_fault() - Fault and mirror an address range
+ *
+ * @m_opts: map options
+ * @pfns: pfns to mirror
+ * @count: number of pages to mirror
+ * @addr: start virtual address to fault
+ * @len: length of address range to fault
+ *
+ * @return: 0 on success or negative error value
+ */
+int cass_mirror_fault(const struct ac_map_opts *m_opts, u64 *pfns, int count,
+		      uintptr_t addr, size_t len)
+{
+	long ret;
+	bool is_huge_page = false;
+	unsigned long timeout;
+	struct hmm_range range = {};
+	u64 end = addr + len;
+	struct cxi_md_priv *md_priv = m_opts->md_priv;
+	struct cass_ac *cac = md_priv->cac;
+	ulong addr_mask = MASK(m_opts->huge_shift);
+	struct mmu_interval_notifier *mn_sub = &m_opts->md_priv->mn_sub;
+	struct mm_struct *mm = mn_sub->mm;
+
+	range.start = addr;
+	range.end = end;
+	range.hmm_pfns = (unsigned long *)pfns;
+	range.pfn_flags_mask = 0;
+	range.notifier = mn_sub;
+
+	if (!(m_opts->flags & CXI_MAP_PREFETCH))
+		range.default_flags = HMM_PFN_REQ_FAULT;
+
+	if (!mn_sub->mm) {
+		pr_debug("Invalid md addr:%lx\n", addr);
+		return -ENOENT;
+	}
+
+	if (!mmget_not_zero(mm)) {
+		pr_debug("mm_user is 0 addr:%lx\n", addr);
+		return -ESRCH;
+	}
+
+	timeout = jiffies + msecs_to_jiffies(HMM_RANGE_DEFAULT_TIMEOUT);
+again:
+	range.notifier_seq = mmu_interval_read_begin(mn_sub);
+	mmap_read_lock(mm);
+
+	ret = cass_vma_write_flag(mm, addr, end, m_opts->flags);
+	if (ret < 0) {
+		/* An -ENOENT indicates there is no VMA when prefetching. */
+		if (ret == -ENOENT)
+			ret = 0;
+
+		goto out_unlock;
+	}
+
+	range.default_flags |= ret ? HMM_PFN_REQ_WRITE : 0;
+
+	ret = cass_range_fault(&range, mm, m_opts, end);
+	mmap_read_unlock(mm);
+	if (ret) {
+		if (ret == -EBUSY && !time_after(jiffies, timeout))
+			goto again;
+
+		goto out;
+	}
+
+	/* ATS mode just needs to fault the pages. */
+	if (cac->flags & CXI_MAP_ATS) {
+		if (mmu_interval_read_retry(mn_sub, range.notifier_seq))
+			goto again;
+
+		ret = count;
+		goto out;
+	}
+
+	mutex_lock(&cac->ac_mutex);
+
+	if (mmu_interval_read_retry(mn_sub, range.notifier_seq)) {
+		mutex_unlock(&cac->ac_mutex);
+		goto again;
+	}
+
+	if (m_opts->is_huge_page && !(addr & addr_mask) &&
+	    (len >= BIT(m_opts->huge_shift)))
+		is_huge_page = true;
+
+	ret = cass_pfns_mirror(md_priv, m_opts, pfns, count, is_huge_page);
+
+	mutex_unlock(&cac->ac_mutex);
+
+	mmput(mm);
+
+	return ret;
+
+out_unlock:
+	mmap_read_unlock(mm);
+out:
+	mmput(mm);
+
+	return ret;
+}
+
+/**
+ * cass_sync_pagetables - Called by the hmm notifier to clear page table
+ *                        entries and invalidate cache entries.
+ *                        mmap_sem is held during this call.
+ *
+ * @mn_sub: MMU interval notifier
+ * @update: update information for callback
+ * @cur_seq:
+ */
+static bool cass_sync_pagetables(struct mmu_interval_notifier *mn_sub,
+				 const struct mmu_notifier_range *update,
+				 unsigned long cur_seq)
+{
+	struct cxi_md_priv *md_priv = container_of(mn_sub, struct cxi_md_priv,
+						   mn_sub);
+	struct cass_dev *hw = container_of(md_priv->cac->lni_priv->dev,
+					   struct cass_dev, cdev);
+	struct cxi_md md = md_priv->md;
+	unsigned long start = update->start;
+	unsigned long end = update->end;
+	u64 va_end = md.va + md.len;
+	u64 s = max_t(u64, md.va, start);
+	u64 e = min_t(u64, va_end, end);
+	u64 offset = s - md.va;
+
+	if (md_priv->flags & CXI_MAP_ATS)
+		return true;
+
+	if (!mmu_notifier_range_blockable(update))
+		return false;
+
+	pr_debug("md:%d va:%llx s:%llx e:%llx update start:%lx end:%lx\n",
+		 md.id, md.va, s, e, start, end);
+
+	mutex_lock(&md_priv->cac->ac_mutex);
+	mmu_interval_set_seq(mn_sub, cur_seq);
+
+	cass_clear_range(md_priv, md.iova + offset, e - s);
+	mutex_unlock(&md_priv->cac->ac_mutex);
+	cass_invalidate_range(md_priv->cac, md.iova + offset, e - s);
+	atomic_inc(&hw->dcpl_nta_mn_inval);
+
+	return true;
+}
+
+static const struct mmu_interval_notifier_ops cass_notifier_ops = {
+	.invalidate = cass_sync_pagetables,
+};
+
+/**
+ * cass_mmu_notifier_insert() - Set up notifier for this descriptor
+ *
+ * @md_priv: Private memory descriptor
+ * @m_opts:  User options
+ *
+ * @return: 0 on success or negative value on error
+ */
+int cass_mmu_notifier_insert(struct cxi_md_priv *md_priv,
+			     const struct ac_map_opts *m_opts)
+{
+	int ret;
+
+	ret = mmu_interval_notifier_insert(&md_priv->mn_sub,
+					   current->mm,
+					   m_opts->va_start,
+					   m_opts->va_len,
+					   &cass_notifier_ops);
+	if (ret)
+		return ret;
+
+	if (m_opts->flags & (CXI_MAP_FAULT | CXI_MAP_PREFETCH)) {
+		ret = cass_mirror_odp(m_opts, md_priv->cac,
+				      m_opts->va_len >> m_opts->page_shift,
+				      m_opts->va_start);
+		if (ret)
+			cass_notifier_cleanup(md_priv);
+	}
+
+	return ret;
+}
+
+int cass_odp_supported(struct cass_dev *hw, u32 flags)
+{
+	if (cass_version(hw, CASSINI_1_0) && !(flags & CXI_MAP_PIN) &&
+	    (flags & CXI_MAP_USER_ADDR)) {
+		cxidev_info(&hw->cdev, "Cassini 1.0 does not support ODP\n");
+		return -EOPNOTSUPP;
+	}
+
+	if (cass_version(hw, CASSINI_1) && (flags & CXI_MAP_ATS) &&
+	    !hw->ats_c1_odp_enable && !ats_c1_override) {
+		cxidev_dbg(&hw->cdev,
+			   "ATS support requires invalidate interface for Cassini 1.x\n");
+		return -EOPNOTSUPP;
+	}
+
+	return 0;
+}
diff --git a/drivers/net/ethernet/hpe/ss1/cass_hni.c b/drivers/net/ethernet/hpe/ss1/cass_hni.c
new file mode 100644
index 000000000000..212bd226a338
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_hni.c
@@ -0,0 +1,370 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2019-2022, 2024-2026 Hewlett Packard Enterprise Development LP */
+
+/* Cassini device handler */
+
+#include <linux/iopoll.h>
+
+#include <linux/hpe/cxi/cxi.h>
+#include <linux/hpe/sbl/sbl.h>
+#include "cass_core.h"
+#include "cass_cable.h"
+
+static unsigned int pause_too_long_timeout = 1000;
+module_param(pause_too_long_timeout, uint, 0444);
+MODULE_PARM_DESC(pause_too_long_timeout,
+		 "Pause too long error timeout in ms, up to 17 min (rounded up to pow 2)");
+
+/* 1ms at a 1GHz clock is 1000000 cycles, so we would need to monitor
+ * bit 20 for a 1ms to 2ms timer.
+ */
+#define PAUSE_MSEC_BIT_OFFSET 20U
+#define RX_CTRL_TIMER_BIT_OFFSET 9U
+#define RX_CTRL_TIMER_BIT_MAX 31
+
+/* Increase pause repeat period to repeat every 156 quantas. With the default
+ * pause quanta configuration, repeat period is ~400 nsecs.
+ */
+#define PAUSE_REPEAT_PERIOD 156U
+
+/* Try to clear a pause. */
+static void pause_timeout_worker(struct work_struct *work)
+{
+	struct cass_dev *hw =
+		container_of(work, struct cass_dev, pause_timeout_work);
+	union c_hni_cfg_pause_rx_ctrl rx_ctrl_cfg;
+	union c_hni_cfg_pause_rx_ctrl old_rx_ctrl_cfg;
+	union c_hni_sts_pause_timeout pause_timeout;
+	void __iomem *csr;
+	unsigned int rc;
+
+	/* Clear pfc_rec_enable to prevent an RX_PAUSE_ERR. */
+	cass_read(hw, C_HNI_CFG_PAUSE_RX_CTRL, &old_rx_ctrl_cfg,
+		  sizeof(old_rx_ctrl_cfg));
+	rx_ctrl_cfg = old_rx_ctrl_cfg;
+	rx_ctrl_cfg.pfc_rec_enable = 0;
+	cass_write(hw, C_HNI_CFG_PAUSE_RX_CTRL, &rx_ctrl_cfg, sizeof(rx_ctrl_cfg));
+
+	/* Wait until pause clears for every PCP, ie bit 3 of each PCP
+	 * is 0.
+	 */
+	csr = cass_csr(hw, C_HNI_STS_PAUSE_TIMEOUT);
+	rc = readq_poll_timeout(csr, pause_timeout.qw,
+				(pause_timeout.qw & 0x88888888ULL) == 0,
+				1, 5000);
+	if (rc)
+		cxidev_warn(&hw->cdev,
+			    "Pause too long not cleared after timeout: %llx\n",
+			    pause_timeout.qw);
+
+	/* Restore pfc_rec_enable */
+	cass_write(hw, C_HNI_CFG_PAUSE_RX_CTRL, &old_rx_ctrl_cfg,
+		   sizeof(old_rx_ctrl_cfg));
+}
+
+static void pause_timeout_cb(struct cass_dev *hw, unsigned int irq,
+			     bool is_ext, unsigned int bitn)
+{
+	queue_work(system_long_wq, &hw->pause_timeout_work);
+}
+
+/* Re-program the HNI and OXE pause quanta when the link is going up,
+ * as they are dependent on the link speed, which may have changed.
+ */
+static const struct quantas {
+	unsigned int speed;
+	union c_hni_cfg_pause_quanta q;
+} c1_quantas[] = {
+	{ .speed = SPEED_50000, .q = { .sub_period = 80, .sub_value = 0x7d000 }},
+	{ .speed = SPEED_100000, .q = { .sub_period = 40, .sub_value = 0x7d000 }},
+	{ .speed = SPEED_200000, .q = { .sub_period = 20, .sub_value = 0x7d000 }},
+	{ .speed = SPEED_400000, .q = { .sub_period = 10, .sub_value = 0x7d000 }},
+	{ }
+}, c2_quantas[] = {
+	{ .speed = SPEED_25000, .q = { .sub_period = 176, .sub_value = 0x7d000 }},
+	{ .speed = SPEED_50000,  .q = { .sub_period = 88, .sub_value = 0x7d000 }},
+	{ .speed = SPEED_100000, .q = { .sub_period = 44, .sub_value = 0x7d000 }},
+	{ .speed = SPEED_200000, .q = { .sub_period = 22, .sub_value = 0x7d000 }},
+	{ .speed = SPEED_400000, .q = { .sub_period = 11, .sub_value = 0x7d000 }},
+	{ }
+};
+
+void update_hni_link_up(struct cass_dev *hw)
+{
+	union c_cq_cfg_fq_thresh_table fq_thresh = {};
+	struct cxi_link_info link_info;
+	const struct quantas *quanta;
+	int i;
+
+	cxi_link_mode_get(&hw->cdev, &link_info);
+
+	/* Update the Pause Quanta. */
+	if (cass_version(hw, CASSINI_1))
+		quanta = c1_quantas;
+	else
+		quanta = c2_quantas;
+
+	while (quanta->speed && quanta->speed != link_info.speed)
+		quanta++;
+
+	if (quanta->speed == 0) {
+		cxidev_warn(&hw->cdev, "Missing pause quanta values for speed %u\n",
+			    link_info.speed);
+	} else {
+		cass_write(hw, C_OXE_CFG_PAUSE_QUANTA, &quanta->q, sizeof(quanta->q));
+		cass_write(hw, C_HNI_CFG_PAUSE_QUANTA, &quanta->q, sizeof(quanta->q));
+	}
+
+	/* and the FQ threshold */
+	if (link_info.speed == SPEED_400000)
+		fq_thresh.thresh = 8 * 1024 * 1024;
+	else
+		fq_thresh.thresh = 4 * 1024 * 1024;
+
+	for (i = 0; i < C_CQ_CFG_FQ_THRESH_TABLE_ENTRIES; i++)
+		cass_write(hw, C_CQ_CFG_FQ_THRESH_TABLE(i),
+			   &fq_thresh, sizeof(fq_thresh));
+}
+
+void cass_hni_init(struct cass_dev *hw)
+{
+	int pause_timeout_bit;
+	union c_hni_cfg_pause_rx_ctrl rx_ctrl;
+	union c_hni_cfg_pause_timing timing;
+
+	/* Clear all default reserved packet buffer space. */
+	cass_clear(hw, C_HNI_CFG_PBUF(0), C_HNI_CFG_PBUF_SIZE);
+
+	if (pause_too_long_timeout) {
+		/* Up align pause too long timeout to a power of 2
+		 * since hardware timeout operates on a specific bit.
+		 */
+		pause_too_long_timeout =
+			roundup_pow_of_two(pause_too_long_timeout);
+
+		/* By HW design, the pause_timeout interrupt is only
+		 * generated after 8 timeouts. Account for that.
+		 */
+		pause_too_long_timeout = max_t(unsigned int,
+					       pause_too_long_timeout / 8, 1);
+
+		pause_timeout_bit = ffs(pause_too_long_timeout) - 1 +
+			PAUSE_MSEC_BIT_OFFSET - RX_CTRL_TIMER_BIT_OFFSET;
+
+		if (pause_timeout_bit > RX_CTRL_TIMER_BIT_MAX) {
+			cxidev_info(&hw->cdev,
+				    "pause_too_long_timeout is too big. Setting to max.\n");
+			pause_timeout_bit = RX_CTRL_TIMER_BIT_MAX;
+		}
+	} else {
+		pause_timeout_bit = 0;
+	}
+
+	cass_read(hw, C_HNI_CFG_PAUSE_RX_CTRL, &rx_ctrl, sizeof(rx_ctrl));
+	rx_ctrl.timer_bit = pause_timeout_bit;
+	cass_write(hw, C_HNI_CFG_PAUSE_RX_CTRL, &rx_ctrl, sizeof(rx_ctrl));
+
+	cass_read(hw, C_HNI_CFG_PAUSE_TIMING, &timing, sizeof(timing));
+	timing.pause_repeat_period = PAUSE_REPEAT_PERIOD;
+	cass_write(hw, C_HNI_CFG_PAUSE_TIMING, &timing, sizeof(timing));
+
+	INIT_WORK(&hw->pause_timeout_work, pause_timeout_worker);
+
+	/* Register pause timeout callback */
+	hw->hni_pause_err.irq = C_HNI_IRQA_MSIX_INT;
+	hw->hni_pause_err.is_ext = false;
+	if (cass_version(hw, CASSINI_1))
+		hw->hni_pause_err.err_flags.c1_hni.pause_timeout = 1;
+	else
+		hw->hni_pause_err.err_flags.c2_hni.pause_timeout = 1;
+
+	hw->hni_pause_err.cb = pause_timeout_cb;
+	cxi_register_hw_errors(hw, &hw->hni_pause_err);
+
+	/* Register uncor callback */
+	hw->hni_pml_uncor_err.irq = C_HNI_PML_IRQA_MSIX_INT;
+	hw->hni_pml_uncor_err.is_ext = false;
+	hw->hni_uncor_err.irq = C_HNI_IRQA_MSIX_INT;
+	hw->hni_uncor_err.is_ext = false;
+	if (cass_version(hw, CASSINI_1)) {
+		hw->hni_pml_uncor_err.err_flags.c1_hni_pml.llr_tx_dp_mbe = 1;
+		hw->hni_uncor_err.err_flags.c1_hni.tx_flit_ucor = 1;
+		hw->hni_uncor_err.err_flags.c1_hni.credit_uflw = 1;
+	} else {
+		hw->hni_pml_uncor_err.err_flags.ss2_port_pml.llr_tx_dp_mbe = 1;
+		hw->hni_uncor_err.err_flags.c2_hni.tx_flit_ucor = 1;
+		hw->hni_uncor_err.err_flags.c2_hni.credit_uflw = 1;
+	}
+
+	hw->hni_pml_uncor_err.cb = uncor_cb;
+	hw->hni_uncor_err.cb = uncor_cb;
+	cxi_register_hw_errors(hw, &hw->hni_pml_uncor_err);
+	cxi_register_hw_errors(hw, &hw->hni_uncor_err);
+}
+
+void cass_hni_fini(struct cass_dev *hw)
+{
+	cxi_unregister_hw_errors(hw, &hw->hni_pause_err);
+	cxi_unregister_hw_errors(hw, &hw->hni_pml_uncor_err);
+	cxi_unregister_hw_errors(hw, &hw->hni_uncor_err);
+	cancel_work_sync(&hw->pause_timeout_work);
+}
+
+/**
+ * cass_cable_scan() - Read cable info from microcontroller
+ *
+ * Read data of the cable headshell and pass it down to the phy
+ *
+ * @hw: the device
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+int cass_cable_scan(struct cass_dev *hw)
+{
+	struct sbl_media_attr attr = SBL_MEDIA_ATTR_INITIALIZER;
+
+	cxidev_dbg(&hw->cdev, "cable scan\n");
+
+	/* This cable scan may be called before hw->port
+	 * is initialized, so check for that first. In this case, a cable scan
+	 * will be run as part of probe, so we can just return for now.
+	 */
+	if (!hw->port)
+		return 0;
+
+	/* Check if a cable is present */
+	switch (hw->uc_platform) {
+	case CUC_BOARD_TYPE_BRAZOS:
+		cxidev_dbg(&hw->cdev, "Platform: BRAZOS\n");
+		if (!cass_is_cable_present(hw)) {
+			cxidev_warn(&hw->cdev, "HSN cable is not plugged\n");
+			cass_link_headshell_remove(hw);
+			return 0;
+		}
+
+		if (cass_parse_heashell_data(hw, &attr, &hw->qsfp_format))
+			return cass_link_headshell_error(hw);
+
+		/* AOCs need to be put into high-power mode */
+		if (attr.media != SBL_LINK_MEDIA_ELECTRICAL)
+			if (cass_headshell_power_up(hw, hw->qsfp_format))
+				return cass_link_headshell_error(hw);
+
+		/* Squirrel away the media info in device struct -
+		 * we will make decisions based off it later
+		 */
+		hw->port->lattr.mattr = attr;
+		return cass_link_headshell_insert(hw, &attr);
+
+	case CUC_BOARD_TYPE_SAWTOOTH:
+		cxidev_dbg(&hw->cdev, "Platform: SAWTOOTH\n");
+		attr.media = SBL_LINK_MEDIA_ELECTRICAL;
+		attr.len = SBL_LINK_LEN_BACKPLANE;
+		attr.info = SBL_MEDIA_INFO_SUPPORTS_BS_200G |
+			SBL_MEDIA_INFO_SUPPORTS_BJ_100G |
+			SBL_MEDIA_INFO_SUPPORTS_CD_100G |
+			SBL_MEDIA_INFO_SUPPORTS_CD_50G;
+
+		/* Squirrel away the media info in device struct -
+		 * we will make decisions based off it later
+		 */
+		hw->port->lattr.mattr = attr;
+
+		return cass_link_media_config(hw, &attr);
+
+	case CUC_BOARD_TYPE_KENNEBEC:
+	case CUC_BOARD_TYPE_SOUHEGAN:
+		cxidev_dbg(&hw->cdev, "Platform: KENNEBEC | SOUHEGAN\n");
+		if (!cass_is_cable_present(hw)) {
+			cxidev_warn(&hw->cdev, "HSN cable is not plugged\n");
+			cass_link_headshell_remove(hw);
+			return 0;
+		}
+		if (cass_parse_heashell_data(hw, &attr, &hw->qsfp_format))
+			return cass_link_headshell_error(hw);
+		return cass_link_headshell_insert(hw, &attr);
+
+	case CUC_BOARD_TYPE_WASHINGTON:
+		cxidev_dbg(&hw->cdev, "Platform: WASHINGTON\n");
+		attr.media = SBL_LINK_MEDIA_ELECTRICAL;
+		attr.len   = SBL_LINK_LEN_BACKPLANE;
+		attr.info  = SBL_MEDIA_INFO_SUPPORTS_BS_200G;
+		return cass_link_media_config(hw, &attr);
+
+	default:
+		cxidev_err(&hw->cdev, "Platform %d is not supported\n",
+			   hw->uc_platform);
+		return -EINVAL;
+	}
+}
+
+/**
+ * cxi_set_max_eth_rxsize() - Configure maximum frame size on the receive side
+ *
+ * @cdev: CXI device
+ * @max_std_size: requested size, up to 9022.
+ */
+int cxi_set_max_eth_rxsize(struct cxi_dev *cdev, unsigned int max_std_size)
+{
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	union c_hni_cfg_max_sizes new_rx;
+
+	if (max_std_size > ETHERNET_MAX_FRAME_SIZE)
+		return -EINVAL;
+
+	/* This is only called by the Ethernet driver, so locking is
+	 * not needed around the CSR.
+	 */
+	cass_read(hw, C_HNI_CFG_MAX_SIZES, &new_rx, sizeof(new_rx));
+	new_rx.max_std_size = max_std_size;
+	cass_write(hw, C_HNI_CFG_MAX_SIZES, &new_rx, sizeof(new_rx));
+
+	/* Store max Ethernet frame size for port configuration. */
+	hw->max_eth_rxsize = max_std_size;
+
+	return 0;
+}
+EXPORT_SYMBOL(cxi_set_max_eth_rxsize);
+/**
+ * cxi_get_max_eth_rxsize_vf() - Fetch the current maximum Ethernet frame size from the PF
+ *
+ * @cdev: VF CXI device
+ *
+ * Returns the maximum Ethernet frame size as reported by the PF, or a negative
+ * errno on failure.
+ */
+static int cxi_get_max_eth_rxsize_vf(struct cxi_dev *cdev)
+{
+	const struct cxi_eth_max_rxsize_get_cmd cmd = {
+		.op = CXI_OP_ETH_MAX_RXSIZE_GET,
+	};
+	struct cxi_eth_get_max_rxsize_resp resp = {};
+	size_t resp_len = sizeof(resp);
+	int rc;
+
+	rc = cxi_send_msg_to_pf(cdev, &cmd, sizeof(cmd), &resp, &resp_len);
+	if (rc)
+		return rc;
+
+	return resp.max_rxsize;
+}
+
+/**
+ * cxi_get_max_eth_rxsize() - Return the current maximum Ethernet frame size
+ *
+ * @cdev: CXI device
+ *
+ * Returns the maximum Ethernet frame size (including layer-2 headers)
+ * currently configured on the device, matching the units used by
+ * cxi_set_max_eth_rxsize().
+ */
+int cxi_get_max_eth_rxsize(struct cxi_dev *cdev)
+{
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+
+	if (!cdev->is_physfn)
+		return cxi_get_max_eth_rxsize_vf(cdev);
+
+	return hw->max_eth_rxsize;
+}
+EXPORT_SYMBOL(cxi_get_max_eth_rxsize);
diff --git a/drivers/net/ethernet/hpe/ss1/cass_ixe.c b/drivers/net/ethernet/hpe/ss1/cass_ixe.c
new file mode 100644
index 000000000000..c52fa70e60a7
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_ixe.c
@@ -0,0 +1,348 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2021 Hewlett Packard Enterprise Development LP */
+
+/* IXE block */
+
+#include <linux/hpe/cxi/cxi.h>
+#include <rdma/ib_pack.h>
+
+#include "cass_core.h"
+
+/* AMO remap to PCIe fetching add is used to remap a single operand NIC AMO
+ * as a PCIe fetch add AMO.
+ */
+static int amo_remap_to_pcie_fadd = C_AMO_OP_SWAP;
+module_param(amo_remap_to_pcie_fadd, int, 0444);
+MODULE_PARM_DESC(amo_remap_to_pcie_fadd,
+		 "Remap NIC AMO operation as a PCIe fetch add operation. "
+		 "The following are the value values.\n"
+		 "AMO_OP_MIN == 0\n"
+		 "AMO_OP_MAX == 1\n"
+		 "AMO_OP_SUM == 2\n"
+		 "AMO_OP_LOR == 4\n"
+		 "AMO_OP_LAND == 5\n"
+		 "AMO_OP_BOR == 6\n"
+		 "AMO_OP_BAND == 7\n"
+		 "AMO_OP_LXOR == 8\n"
+		 "AMO_OP_BXOR == 9\n"
+		 "AMO_OP_SWAP == 10\n"
+		 "-1 disables remapping");
+
+enum {
+	RXE_BTH_BYTES       = 12,
+	RXE_DETH_BYTES      = 8,
+	RXE_IMMDT_BYTES     = 4,
+	RXE_RETH_BYTES      = 16,
+	RXE_AETH_BYTES      = 4,
+	RXE_ATMACK_BYTES    = 8,
+	RXE_ATMETH_BYTES    = 28,
+	RXE_IETH_BYTES      = 4,
+	RXE_RDETH_BYTES     = 4,
+};
+
+/* Length of a whole BTH depending on its opcode, not including the
+ * base BTH itself. Extracted from the rdma_rxe driver's rxe_opcode
+ * array.
+ */
+static const int rxe_op_length[256] = {
+	/* RC */
+	[IB_OPCODE_RC_SEND_LAST_WITH_IMMEDIATE] = RXE_IMMDT_BYTES,
+	[IB_OPCODE_RC_SEND_ONLY_WITH_IMMEDIATE] = RXE_IMMDT_BYTES,
+	[IB_OPCODE_RC_RDMA_WRITE_FIRST] = RXE_RETH_BYTES,
+	[IB_OPCODE_RC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = RXE_IMMDT_BYTES,
+	[IB_OPCODE_RC_RDMA_WRITE_ONLY] = RXE_RETH_BYTES,
+	[IB_OPCODE_RC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = RXE_IMMDT_BYTES +
+		RXE_RETH_BYTES,
+	[IB_OPCODE_RC_RDMA_READ_REQUEST] = RXE_RETH_BYTES,
+	[IB_OPCODE_RC_RDMA_READ_RESPONSE_FIRST] = RXE_AETH_BYTES,
+	[IB_OPCODE_RC_RDMA_READ_RESPONSE_LAST] = RXE_AETH_BYTES,
+	[IB_OPCODE_RC_RDMA_READ_RESPONSE_ONLY] = RXE_AETH_BYTES,
+	[IB_OPCODE_RC_ACKNOWLEDGE] = RXE_AETH_BYTES,
+	[IB_OPCODE_RC_ATOMIC_ACKNOWLEDGE] = RXE_ATMACK_BYTES + RXE_AETH_BYTES,
+	[IB_OPCODE_RC_COMPARE_SWAP] = RXE_ATMETH_BYTES,
+	[IB_OPCODE_RC_FETCH_ADD] = RXE_ATMETH_BYTES,
+	[IB_OPCODE_RC_SEND_LAST_WITH_INVALIDATE] = RXE_IETH_BYTES,
+	[IB_OPCODE_RC_SEND_ONLY_WITH_INVALIDATE] = RXE_IETH_BYTES,
+
+	/* UC */
+	[IB_OPCODE_UC_SEND_LAST_WITH_IMMEDIATE] = RXE_IMMDT_BYTES,
+	[IB_OPCODE_UC_SEND_ONLY_WITH_IMMEDIATE] = RXE_IMMDT_BYTES,
+	[IB_OPCODE_UC_RDMA_WRITE_FIRST] = RXE_RETH_BYTES,
+	[IB_OPCODE_UC_RDMA_WRITE_LAST_WITH_IMMEDIATE] = RXE_IMMDT_BYTES,
+	[IB_OPCODE_UC_RDMA_WRITE_ONLY] = RXE_RETH_BYTES,
+	[IB_OPCODE_UC_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = RXE_IMMDT_BYTES +
+		RXE_RETH_BYTES,
+
+	/* RD */
+	[IB_OPCODE_RD_SEND_FIRST] = RXE_DETH_BYTES + RXE_RDETH_BYTES,
+	[IB_OPCODE_RD_SEND_MIDDLE] = RXE_DETH_BYTES + RXE_RDETH_BYTES,
+	[IB_OPCODE_RD_SEND_LAST] = RXE_DETH_BYTES + RXE_RDETH_BYTES,
+	[IB_OPCODE_RD_SEND_LAST_WITH_IMMEDIATE] = RXE_IMMDT_BYTES +
+		RXE_DETH_BYTES + RXE_RDETH_BYTES,
+	[IB_OPCODE_RD_SEND_ONLY] = RXE_DETH_BYTES + RXE_RDETH_BYTES,
+	[IB_OPCODE_RD_SEND_ONLY_WITH_IMMEDIATE] = RXE_IMMDT_BYTES +
+		RXE_DETH_BYTES + RXE_RDETH_BYTES,
+	[IB_OPCODE_RD_RDMA_WRITE_FIRST] = RXE_RETH_BYTES + RXE_DETH_BYTES +
+		RXE_RDETH_BYTES,
+	[IB_OPCODE_RD_RDMA_WRITE_MIDDLE] = RXE_DETH_BYTES + RXE_RDETH_BYTES,
+	[IB_OPCODE_RD_RDMA_WRITE_LAST] = RXE_DETH_BYTES + RXE_RDETH_BYTES,
+	[IB_OPCODE_RD_RDMA_WRITE_LAST_WITH_IMMEDIATE] = RXE_IMMDT_BYTES +
+		RXE_DETH_BYTES + RXE_RDETH_BYTES,
+	[IB_OPCODE_RD_RDMA_WRITE_ONLY] = RXE_RETH_BYTES + RXE_DETH_BYTES +
+		RXE_RDETH_BYTES,
+	[IB_OPCODE_RD_RDMA_WRITE_ONLY_WITH_IMMEDIATE] = RXE_IMMDT_BYTES +
+		RXE_RETH_BYTES + RXE_DETH_BYTES + RXE_RDETH_BYTES,
+	[IB_OPCODE_RD_RDMA_READ_REQUEST] = RXE_RETH_BYTES + RXE_DETH_BYTES +
+		RXE_RDETH_BYTES,
+	[IB_OPCODE_RD_RDMA_READ_RESPONSE_FIRST] = RXE_AETH_BYTES +
+		RXE_RDETH_BYTES,
+	[IB_OPCODE_RD_RDMA_READ_RESPONSE_MIDDLE] = RXE_RDETH_BYTES,
+	[IB_OPCODE_RD_RDMA_READ_RESPONSE_LAST] = RXE_AETH_BYTES +
+		RXE_RDETH_BYTES,
+	[IB_OPCODE_RD_RDMA_READ_RESPONSE_ONLY] = RXE_AETH_BYTES +
+		RXE_RDETH_BYTES,
+	[IB_OPCODE_RD_ACKNOWLEDGE] = RXE_AETH_BYTES + RXE_RDETH_BYTES,
+	[IB_OPCODE_RD_ATOMIC_ACKNOWLEDGE] = RXE_ATMACK_BYTES + RXE_AETH_BYTES +
+		RXE_RDETH_BYTES,
+	[IB_OPCODE_RD_COMPARE_SWAP] = RXE_ATMETH_BYTES + RXE_DETH_BYTES	+
+		RXE_RDETH_BYTES,
+	[IB_OPCODE_RD_FETCH_ADD] = RXE_ATMETH_BYTES + RXE_DETH_BYTES +
+		RXE_RDETH_BYTES,
+
+	/* UD */
+	[IB_OPCODE_UD_SEND_ONLY] = RXE_DETH_BYTES,
+	[IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE] = RXE_IMMDT_BYTES +
+		RXE_DETH_BYTES,
+};
+
+/* Program BTH opcodes for RXE, using definitions from the rxe driver */
+static void set_bth_opcode(struct cass_dev *hw)
+{
+	unsigned int index;
+	unsigned int offset;
+
+	for (index = 0; index < C_IXE_CFG_BTH_OPCODE_ENTRIES; index++) {
+		union c_ixe_cfg_bth_opcode bth_opcode = {};
+
+		for (offset = 0; offset < 16; offset++) {
+			u64 length;
+
+			length = RXE_BTH_BYTES;
+			length += rxe_op_length[index * 16 + offset];
+			length /= 4;
+
+			bth_opcode.qw |= length << (offset * 4);
+		}
+
+		cass_write(hw, C_IXE_CFG_BTH_OPCODE(index),
+			   &bth_opcode, sizeof(bth_opcode));
+	}
+}
+
+static bool cass_ixe_valid_amo_remap_to_pcie_fadd(int amo_remap)
+{
+	switch (amo_remap) {
+	case -1:
+	case C_AMO_OP_MIN:
+	case C_AMO_OP_MAX:
+	case C_AMO_OP_SUM:
+	case C_AMO_OP_LOR:
+	case C_AMO_OP_LAND:
+	case C_AMO_OP_BOR:
+	case C_AMO_OP_BAND:
+	case C_AMO_OP_LXOR:
+	case C_AMO_OP_BXOR:
+	case C_AMO_OP_SWAP:
+		return true;
+
+	default:
+		return false;
+	}
+}
+
+#define OFFLOAD_UINT32_UINT64_FETCH_NON_FETCH_1OP 0xf
+#define OFFLOAD_INT32_INT64_UINT32_UINT64_FETCH_NON_FETCH_1OP 0xf
+
+int cass_ixe_set_amo_remap_to_pcie_fadd(struct cass_dev *hw, int amo_remap)
+{
+	union c_ixe_cfg_amo_offload amo_offload;
+	union c_ixe_cfg_amo_offload_code_1op amo_offload_code_1op = {};
+	union c_ixe_cfg_amo_offload_en amo_offload_en = {};
+
+	if (!cass_ixe_valid_amo_remap_to_pcie_fadd(amo_remap))
+		return -EINVAL;
+
+	/* Clear current AMO offload configuration. */
+	cass_read(hw, C_IXE_CFG_AMO_OFFLOAD, &amo_offload,
+		  sizeof(amo_offload));
+	amo_offload.base_amo_req = 0;
+	cass_write(hw, C_IXE_CFG_AMO_OFFLOAD, &amo_offload,
+		   sizeof(amo_offload));
+
+	cass_write(hw, C_IXE_CFG_AMO_OFFLOAD_CODE_1OP, &amo_offload_code_1op,
+		   sizeof(amo_offload_code_1op));
+	cass_write(hw, C_IXE_CFG_AMO_OFFLOAD_EN, &amo_offload_en,
+		   sizeof(amo_offload_en));
+
+	switch (amo_remap) {
+	case -1:
+		goto out;
+
+	case C_AMO_OP_MIN:
+		amo_offload_en.op_min =
+			OFFLOAD_UINT32_UINT64_FETCH_NON_FETCH_1OP;
+		break;
+
+	case C_AMO_OP_MAX:
+		amo_offload_en.op_max =
+			OFFLOAD_UINT32_UINT64_FETCH_NON_FETCH_1OP;
+		break;
+
+	case C_AMO_OP_SUM:
+		amo_offload_en.op_sum =
+			OFFLOAD_INT32_INT64_UINT32_UINT64_FETCH_NON_FETCH_1OP;
+		break;
+
+	case C_AMO_OP_LOR:
+		amo_offload_en.op_lor =
+			OFFLOAD_UINT32_UINT64_FETCH_NON_FETCH_1OP;
+		break;
+
+	case C_AMO_OP_LAND:
+		amo_offload_en.op_land =
+			OFFLOAD_UINT32_UINT64_FETCH_NON_FETCH_1OP;
+		break;
+
+	case C_AMO_OP_BOR:
+		amo_offload_en.op_bor =
+			OFFLOAD_UINT32_UINT64_FETCH_NON_FETCH_1OP;
+		break;
+
+	case C_AMO_OP_BAND:
+		amo_offload_en.op_band =
+			OFFLOAD_UINT32_UINT64_FETCH_NON_FETCH_1OP;
+		break;
+
+	case C_AMO_OP_LXOR:
+		amo_offload_en.op_lxor =
+			OFFLOAD_UINT32_UINT64_FETCH_NON_FETCH_1OP;
+		break;
+
+	case C_AMO_OP_BXOR:
+		amo_offload_en.op_bxor =
+			OFFLOAD_UINT32_UINT64_FETCH_NON_FETCH_1OP;
+		break;
+
+	case C_AMO_OP_SWAP:
+		amo_offload_en.op_swap =
+			OFFLOAD_UINT32_UINT64_FETCH_NON_FETCH_1OP;
+		break;
+	}
+
+	cass_write(hw, C_IXE_CFG_AMO_OFFLOAD_EN, &amo_offload_en,
+		   sizeof(amo_offload_en));
+
+out:
+	hw->cdev.prop.amo_remap_to_pcie_fadd = amo_remap;
+
+	return 0;
+}
+
+#define ABORT_MASK_BITS (sizeof(union c_ixe_cfg_ipv6_opt_abort) * 8)
+int cass_ixe_init(struct cass_dev *hw)
+{
+	int i;
+	unsigned int next_header;
+	unsigned int index;
+	unsigned int bit;
+	union c_ixe_cfg_ipv6_opt_abort masks[C_IXE_CFG_IPV6_OPT_ABORT_ENTRIES];
+	static const unsigned int ipv6_extension_headers[] = {
+		IPV6_EH_HOPOPTS,
+		IPV6_EH_ROUTE,
+		IPV6_EH_FRAG,
+		IPV6_EH_ESP,
+		IPV6_EH_AH,
+		IPV6_EH_OPTS,
+		IPV6_EH_MOBILITY,
+		IPV6_EH_HIP,
+		IPV6_EH_SHIM6,
+		IPV6_EH_RSVD1,
+		IPV6_EH_RSVD2,
+	};
+	union c_ixe_cfg_disp_cdt_lim cdt_limits;
+	int ret;
+
+	/* Initially mark all IPv6 next header values as ULP. */
+	for (i = 0; i < ARRAY_SIZE(masks); i++)
+		masks[i].qw = -1;
+
+	/* Mask off IPv6 extension headers next header values. */
+	for (i = 0; i < ARRAY_SIZE(ipv6_extension_headers); i++) {
+		next_header = ipv6_extension_headers[i];
+		index = next_header / ABORT_MASK_BITS;
+		bit = next_header % ABORT_MASK_BITS;
+
+		masks[index].qw &= ~BIT(bit);
+	}
+
+	/* Write the IPv6 next header configuration. */
+	for (i = 0; i < ARRAY_SIZE(masks); i++)
+		cass_write(hw, C_IXE_CFG_IPV6_OPT_ABORT(i), &masks[i],
+			   sizeof(masks[i]));
+
+	if (cass_version(hw, CASSINI_1_0)) {
+		/* Errata 2973 */
+		union c1_pct_cfg_ixe_req_fifo_limits req_limits;
+
+		cass_read(hw, C1_PCT_CFG_IXE_REQ_FIFO_LIMITS, &req_limits,
+			  sizeof(req_limits));
+
+		req_limits.ixe_req_clr2_limit = 1;
+
+		cass_write(hw, C1_PCT_CFG_IXE_REQ_FIFO_LIMITS, &req_limits,
+			   sizeof(req_limits));
+
+		cass_read(hw, C_IXE_CFG_DISP_CDT_LIM, &cdt_limits,
+			  sizeof(cdt_limits));
+		cdt_limits.atu_req_cdts = 3;
+		cass_write(hw, C_IXE_CFG_DISP_CDT_LIM, &cdt_limits,
+			   sizeof(cdt_limits));
+	}
+
+	if (cass_version(hw, CASSINI_2)) {
+		union c2_ixe_cfg_disp_ord ord;
+
+		cass_read(hw, C2_IXE_CFG_DISP_ORD, &ord, sizeof(ord));
+		ord.get_ro_body = 1;
+		ord.get_ro_last = 1;
+		cass_write(hw, C2_IXE_CFG_DISP_ORD, &ord, sizeof(ord));
+
+		cass_read(hw, C_IXE_CFG_DISP_CDT_LIM, &cdt_limits,
+			  sizeof(cdt_limits));
+		cdt_limits.atu_req_cdts = 4;
+		cass_write(hw, C_IXE_CFG_DISP_CDT_LIM, &cdt_limits,
+			   sizeof(cdt_limits));
+	}
+
+	/* RoCE */
+	set_bth_opcode(hw);
+
+	ret = cass_ixe_set_amo_remap_to_pcie_fadd(hw, amo_remap_to_pcie_fadd);
+	if (ret) {
+		pr_err("Failed to remap NIC AMO to PCIe fetch add: %d\n", ret);
+		return ret;
+	}
+
+	hw->ixe_pbuf_rd_err.irq = C_IXE_IRQA_MSIX_INT;
+	hw->ixe_pbuf_rd_err.is_ext = false;
+	hw->ixe_pbuf_rd_err.err_flags.ixe_err_flg.pbuf_rd_err = 1;
+	hw->ixe_pbuf_rd_err.cb = uncor_cb;
+	cxi_register_hw_errors(hw, &hw->ixe_pbuf_rd_err);
+
+	return 0;
+}
+
+void cass_ixe_fini(struct cass_dev *hw)
+{
+	cxi_unregister_hw_errors(hw, &hw->ixe_pbuf_rd_err);
+}
diff --git a/drivers/net/ethernet/hpe/ss1/cass_lmon.c b/drivers/net/ethernet/hpe/ss1/cass_lmon.c
new file mode 100644
index 000000000000..401dd247638a
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_lmon.c
@@ -0,0 +1,573 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Cassini link monitor
+ * Copyright 2020-2024,2025 Hewlett Packard Enterprise Development LP
+ */
+
+#include <linux/iopoll.h>
+#include <linux/hpe/cxi/cxi.h>
+#include <linux/kthread.h>
+#include <linux/hpe/sbl/sbl_mb.h>
+#include <linux/hpe/sbl/sbl.h>
+#include <uapi/ethernet/sbl-abi.h>
+#include <uapi/ethernet/sbl_serdes.h>
+
+#include "cass_core.h"
+
+/*
+ * make sure code is aligned with address map
+ */
+#if (CASS_PCS_NUM_FECL_CNTRS != 8)
+#error fecl counter number mismatch
+#endif
+
+/* FEC monitoring */
+#define CASS_LMON_WAKEUP_INTERVAL                 1000    /* ms */
+#define CASS_LMON_MAX_FEC_WARNINGS                   3
+#define CASS_LMON_MIN_FEC_WINDOW                  1000    /* ms */
+
+/* wakeup rate limiting */
+#define CASS_LMON_MAX_WAKEUPS                       10
+#define CASS_LMON_WAKEUP_DELAY                     100    /* ms */
+#define CASS_LMON_WAKEUP_LIMITER                   500    /* ms */
+#define CASS_LMON_WAKEUP_WINDOW                   1000    /* ms */
+
+/* thread init data */
+struct cass_lmon_data {
+	struct cass_dev *hw;
+	struct completion running;
+};
+
+/*
+ * test to see if link should be up
+ *
+ * This function is called with the port locked
+ */
+static bool cass_lmon_link_should_auto_restart(struct cass_dev *hw)
+{
+	if (kthread_should_stop())
+		return false;
+
+	if (hw->port->link_down_origin == CASS_DOWN_ORIGIN_CONFIG) {
+		/* link has been told to come down */
+		return false;
+	}
+
+	if (!(hw->port->lattr.options & CASS_LINK_OPT_UP_AUTO_RESTART)) {
+		/* auto restart not configured */
+		return false;
+	}
+
+	if (hw->port->lmon_up_pause) {
+		/* auto restart has been paused */
+		return false;
+	}
+
+	/* should auto restart */
+	return true;
+}
+
+/*
+ * test to see if monitor should wake up and do something
+ */
+static bool cass_lmon_wakeup(struct cass_dev *hw)
+{
+	int lmon_dirn;
+	int lstate;
+	bool auto_restart;
+
+	if (kthread_should_stop())
+		return true;
+
+	spin_lock(&hw->port->lock);
+	lmon_dirn = hw->port->lmon_dirn;
+	lstate = hw->port->lstate;
+	auto_restart = cass_lmon_link_should_auto_restart(hw);
+	spin_unlock(&hw->port->lock);
+
+	if (lmon_dirn == CASS_LMON_DIRECTION_RESET) {
+		/* always do reset */
+		return true;
+	} else if (lstate == CASS_LINK_STATUS_ERROR) {
+		/* error can generally only be cleared by a reset */
+		return false;
+	} else if (lstate == CASS_LINK_STATUS_UNCONFIGURED) {
+		/* can't do anything without configuration */
+		return false;
+	} else if ((lmon_dirn == CASS_LMON_DIRECTION_UP &&
+		    lstate != CASS_LINK_STATUS_UP) ||
+		   (lmon_dirn == CASS_LMON_DIRECTION_DOWN &&
+		    (lstate != CASS_LINK_STATUS_DOWN || auto_restart))) {
+		/* if we should be up or down and not, then there is
+		 *  something to do
+		 */
+		return true;
+	}
+
+	return false;
+}
+
+static void cass_lmon_wakeup_limiter_reset(struct cass_dev *hw)
+{
+	spin_lock(&hw->port->lock);
+	hw->port->lmon_wake_cnt = 0;
+	hw->port->lmon_wake_jiffies = jiffies +
+		msecs_to_jiffies(CASS_LMON_WAKEUP_WINDOW);
+	hw->port->lmon_limiter_on = false;
+	spin_unlock(&hw->port->lock);
+}
+
+/*
+ * make sure we are not waking too frequently
+ */
+static void cass_lmon_wakeup_limiter(struct cass_dev *hw)
+{
+	spin_lock(&hw->port->lock);
+	if (time_is_after_jiffies(hw->port->lmon_wake_jiffies)) {
+		if (++hw->port->lmon_wake_cnt < CASS_LMON_MAX_WAKEUPS) {
+			spin_unlock(&hw->port->lock);
+			msleep(CASS_LMON_WAKEUP_DELAY);
+			cxidev_dbg(&hw->cdev, "lmon wakeup limiter - %d\n",
+				   hw->port->lmon_wake_cnt);
+			return;
+		}
+
+		cxidev_dbg(&hw->cdev, "lmon wakeup limiter - sleeping\n");
+		hw->port->lmon_limiter_on = true;
+		spin_unlock(&hw->port->lock);
+		atomic_inc(&hw->port->lmon_counters[lmon_limiter]);
+		msleep(CASS_LMON_WAKEUP_LIMITER);
+		return;
+	}
+	spin_unlock(&hw->port->lock);
+	cass_lmon_wakeup_limiter_reset(hw);
+}
+
+/*
+ * called from thread other than the link monitor
+ */
+int cass_lmon_request_up(struct cass_dev *hw)
+{
+	bool wakeup_lmon = false;
+	int err = 0;
+
+	spin_lock(&hw->port->lock);
+	switch (hw->port->lstate) {
+
+	case CASS_LINK_STATUS_UNKNOWN:
+	case CASS_LINK_STATUS_UNCONFIGURED:
+	case CASS_LINK_STATUS_ERROR:
+		cxidev_err_ratelimited(&hw->cdev,
+				       "lmon: up request failed, wrong state (%s)\n",
+			cass_link_state_str(hw->port->lstate));
+		err = -ESTALE;
+		break;
+
+	case CASS_LINK_STATUS_STARTING:
+	case CASS_LINK_STATUS_UP:
+		/* continue coming up */
+		if (cass_version(hw, CASSINI_1))
+			sbl_base_link_enable_start(hw->sbl, 0);
+		break;
+
+	case CASS_LINK_STATUS_STOPPING:
+	case CASS_LINK_STATUS_DOWN:
+		/* start it coming up */
+		if (cass_version(hw, CASSINI_1))
+			sbl_base_link_enable_start(hw->sbl, 0);
+		hw->port->lmon_dirn = CASS_LMON_DIRECTION_UP;
+		hw->port->link_restart_count = 0;
+		hw->port->link_restart_time_idx = 0;
+		memset(hw->port->link_restart_time_buf, 0, sizeof(hw->port->link_restart_time_buf));
+		wakeup_lmon = true;
+		break;
+
+	case CASS_LINK_STATUS_RESETTING:
+		/* have to wait for this to finish - do nothing */
+		err = -EBUSY;
+		break;
+	}
+	spin_unlock(&hw->port->lock);
+
+	if (wakeup_lmon)
+		wake_up_interruptible(&hw->port->lmon_wq);
+
+	return err;
+}
+
+int cass_lmon_request_down(struct cass_dev *hw)
+{
+	bool wakeup_lmon = false;
+	int err = 0;
+
+	/*
+	 * first change direction
+	 * then, if we need to cancel an ongoing startup, it
+	 * will restarts with the new direction
+	 */
+	spin_lock(&hw->port->lock);
+	switch (hw->port->lstate) {
+
+	case CASS_LINK_STATUS_UNCONFIGURED:
+	case CASS_LINK_STATUS_UNKNOWN:
+	case CASS_LINK_STATUS_ERROR:
+		cxidev_err(&hw->cdev, "lmon: down request failed, wrong state (%s)\n",
+			   cass_link_state_str(hw->port->lstate));
+		err = -ESTALE;
+		break;
+
+	case CASS_LINK_STATUS_STARTING:
+	case CASS_LINK_STATUS_UP:
+		/* start coming down*/
+		hw->port->lmon_dirn = CASS_LMON_DIRECTION_DOWN;
+		wakeup_lmon = true;
+		break;
+
+	case CASS_LINK_STATUS_STOPPING:
+	case CASS_LINK_STATUS_DOWN:
+		/* nothing to do */
+		break;
+
+	case CASS_LINK_STATUS_RESETTING:
+		/* have to wait for this to finish - do nothing */
+		err = -EBUSY;
+		break;
+	}
+
+	/* cancel any starting operation */
+	if (cass_version(hw, CASSINI_1) &&
+	    (hw->port->lstate == CASS_LINK_STATUS_STARTING)) {
+		sbl_base_link_cancel_start(hw->sbl, 0);
+	}
+	spin_unlock(&hw->port->lock);
+
+	if (wakeup_lmon)
+		wake_up_interruptible(&hw->port->lmon_wq);
+
+	return err;
+}
+
+int cass_lmon_request_reset(struct cass_dev *hw)
+{
+	bool wakeup_lmon = false;
+	int err = 0;
+
+	/*
+	 * first change direction
+	 * then, if we need to cancel an ongoing startup, it
+	 * will restarts with the new direction
+	 */
+	spin_lock(&hw->port->lock);
+	switch (hw->port->lstate) {
+
+	case CASS_LINK_STATUS_UNKNOWN:
+		cxidev_err(&hw->cdev, "lmon: down request failed, wrong state (%s)\n",
+			   cass_link_state_str(hw->port->lstate));
+		err = -ESTALE;
+		break;
+
+	case CASS_LINK_STATUS_STARTING:
+	case CASS_LINK_STATUS_UP:
+	case CASS_LINK_STATUS_STOPPING:
+	case CASS_LINK_STATUS_DOWN:
+	case CASS_LINK_STATUS_ERROR:
+	case CASS_LINK_STATUS_UNCONFIGURED:
+	case CASS_LINK_STATUS_RESETTING:
+		/* start reset */
+		hw->port->lmon_dirn = CASS_LMON_DIRECTION_RESET;
+		wakeup_lmon = true;
+		break;
+	}
+
+	/* cancel any starting operation */
+	if (cass_version(hw, CASSINI_1) &&
+	    (hw->port->lstate == CASS_LINK_STATUS_STARTING)) {
+		sbl_base_link_cancel_start(hw->sbl, 0);
+	}
+	spin_unlock(&hw->port->lock);
+
+	if (wakeup_lmon)
+		wake_up_interruptible(&hw->port->lmon_wq);
+
+	return err;
+}
+
+int cass_lmon_get_dirn(struct cass_dev *hw)
+{
+	int dirn;
+
+	spin_lock(&hw->port->lock);
+	dirn = hw->port->lmon_dirn;
+	spin_unlock(&hw->port->lock);
+
+	return dirn;
+}
+
+void cass_lmon_set_dirn(struct cass_dev *hw, int dirn)
+{
+	spin_lock(&hw->port->lock);
+	hw->port->lmon_dirn = dirn;
+	spin_unlock(&hw->port->lock);
+}
+
+bool cass_lmon_get_active(struct cass_dev *hw)
+{
+	bool state;
+
+	spin_lock(&hw->port->lock);
+	state = hw->port->lmon_active;
+	spin_unlock(&hw->port->lock);
+
+	return state;
+}
+
+void cass_lmon_set_active(struct cass_dev *hw, bool state)
+{
+	spin_lock(&hw->port->lock);
+	hw->port->lmon_active = state;
+	spin_unlock(&hw->port->lock);
+}
+
+void cass_lmon_set_up_pause(struct cass_dev *hw, bool state)
+{
+	spin_lock(&hw->port->lock);
+	hw->port->lmon_up_pause = state;
+	spin_unlock(&hw->port->lock);
+	if (!state)
+		wake_up_interruptible(&hw->port->lmon_wq);
+}
+
+bool cass_lmon_get_up_pause(struct cass_dev *hw)
+{
+	bool state;
+
+	spin_lock(&hw->port->lock);
+	state = hw->port->lmon_up_pause;
+	spin_unlock(&hw->port->lock);
+
+	return state;
+}
+
+static int cass_lmon(void *data)
+{
+	struct cass_lmon_data *thrd_data = data;
+	struct cass_dev *hw = thrd_data->hw;
+	long timeout = msecs_to_jiffies(CASS_LMON_WAKEUP_INTERVAL);
+	int down_origin;
+	int status;
+	char base_link_state_str[SBL_BASE_LINK_STATE_STR_LEN];
+
+	cxidev_dbg(&hw->cdev, "lmon starting");
+
+	complete(&thrd_data->running);
+
+	cass_lmon_wakeup_limiter_reset(hw);
+	cass_lmon_set_active(hw, true);
+
+	// FIXME: temp delay before first link up.  Relates to NETCASSINI-6454
+	if (cass_version(hw, CASSINI_2))
+		msleep(5000);
+
+	while (!kthread_should_stop()) {
+
+		while (!cass_lmon_wakeup(hw)) {
+
+			if (cass_lmon_get_active(hw)) {
+				cxidev_dbg(&hw->cdev, "lmon sleeping\n");
+				cass_lmon_set_active(hw, false);
+			}
+
+			status = wait_event_interruptible_timeout(
+							  hw->port->lmon_wq,
+							  cass_lmon_wakeup(hw),
+							  timeout);
+
+			atomic_inc(&hw->port->lmon_counters[lmon_wakeup]);
+
+			if (kthread_should_stop())
+				goto out;
+
+			if (!status) {
+				/* timed out and nothing needing attention */
+				continue;
+			}
+
+			cxidev_dbg(&hw->cdev, "lmon active\n");
+			cass_lmon_set_active(hw, true);
+		}
+
+		atomic_inc(&hw->port->lmon_counters[lmon_active]);
+
+		if (kthread_should_stop())
+			goto out;
+
+		cass_lmon_wakeup_limiter(hw);
+
+		switch (cass_lmon_get_dirn(hw)) {
+
+		case CASS_LMON_DIRECTION_UP:
+
+			if (cass_lmon_get_up_pause(hw)) {
+				cxidev_dbg(&hw->cdev, "lmon up paused\n");
+				break;
+			}
+
+			if (cass_phy_is_headshell_removed(hw))
+				break;
+
+			cxidev_dbg(&hw->cdev, "lmon up action\n");
+
+			hw->link_ops->link_up(hw);
+			break;
+
+		case CASS_LMON_DIRECTION_DOWN:
+			if (cass_version(hw, CASSINI_1)) {
+				down_origin = cass_link_get_down_origin(hw);
+				cass_sbl_counters_down_origin_inc(hw, down_origin);
+				sbl_base_link_state_str(hw->sbl, 0, base_link_state_str,
+							SBL_BASE_LINK_STATE_STR_LEN);
+				cxidev_info(&hw->cdev,
+					    "lmon taking link down (reason %s, bl: %s)\n",
+					    cass_link_down_origin_str(down_origin),
+					    base_link_state_str);
+			}
+
+			hw->link_ops->link_down(hw);
+
+			spin_lock(&hw->port->lock);
+			if (cass_lmon_link_should_auto_restart(hw)) {
+				if (cass_version(hw, CASSINI_1))
+					atomic_inc(&hw->sbl_counters[link_auto_restart]);
+				cxidev_dbg(&hw->cdev,
+					   "lmon auto restarting link up\n");
+				hw->port->lmon_dirn = CASS_LMON_DIRECTION_UP;
+				hw->port->link_restart_count++;
+				hw->port->link_restart_time_buf[hw->port->link_restart_time_idx]
+					= ktime_get_real_seconds();
+				hw->port->link_restart_time_idx++;
+				if (hw->port->link_restart_time_idx >=
+					CASS_SBL_LINK_RESTART_TIME_SIZE)
+					hw->port->link_restart_time_idx = 0;
+			}
+			spin_unlock(&hw->port->lock);
+
+			if (cass_version(hw, CASSINI_2)) {
+				if (cass_lmon_link_should_auto_restart(hw))
+					cass_phy_trigger_machine(hw);
+			}
+
+			break;
+
+		case CASS_LMON_DIRECTION_RESET:
+			cxidev_dbg(&hw->cdev, "lmon reset action\n");
+			hw->link_ops->link_reset(hw);
+			hw->port->lmon_dirn = CASS_LMON_DIRECTION_NONE;
+			break;
+
+		case CASS_LMON_DIRECTION_NONE:
+			/* don't do anything - thread is going to terminate */
+			break;
+		}
+	}
+
+out:
+	return 0;
+}
+
+/**
+ * cass_lmon_start_all() - Starts lmon thread
+ *
+ * @hw: the device
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+int cass_lmon_start_all(struct cass_dev *hw)
+{
+	struct cass_lmon_data thrd_data;
+	struct task_struct *lmon;
+	int err;
+	int i = 0;
+
+	thrd_data.hw = hw;
+
+	init_completion(&thrd_data.running);
+
+	if (hw->port->lmon)
+		return 0;
+
+	lmon = kthread_run(cass_lmon, (void *)&thrd_data, "lmon");
+
+	err = IS_ERR(lmon);
+	if (err) {
+		cxidev_err(&hw->cdev, "lmon %d: failed to start monitor [%d]\n",
+			   i, err);
+		goto out_err;
+	} else {
+		hw->port->lmon = lmon;
+	}
+
+	wait_for_completion(&thrd_data.running);
+	cxidev_dbg(&hw->cdev, "lmon %d: started\n", i);
+
+	return 0;
+
+ out_err:
+	cass_lmon_kill_all(hw);
+	return err;
+
+}
+
+int cass_lmon_stop_all(struct cass_dev *hw)
+{
+	/* TODO add cleanup */
+	cass_lmon_kill_all(hw);
+	return 0;
+}
+
+void cass_lmon_kill_all(struct cass_dev *hw)
+{
+	int err = 0;
+
+	if (!hw->port->lmon)
+		return;
+
+	/*
+	 * cancel any starting ports and stop any more actions
+	 */
+	if (cass_version(hw, CASSINI_1) && (hw->sbl))
+		sbl_base_link_cancel_start(hw->sbl, 0);
+	if (cass_version(hw, CASSINI_2))
+		hw->sl.is_canceled = true;
+	cass_lmon_set_dirn(hw, CASS_LMON_DIRECTION_NONE);
+	wake_up_interruptible(&hw->port->lmon_wq);
+
+	err = kthread_stop(hw->port->lmon);
+	if (err)
+		cxidev_err(&hw->cdev, "thread stop failed [%d]\n", err);
+
+	hw->port->lmon = NULL;
+
+	cxidev_dbg(&hw->cdev, "lmon thread destroyed\n");
+}
+
+/*
+ * Update lmon counters
+ */
+void cass_lmon_counters_init(struct cass_dev *hw)
+{
+	int i;
+
+	hw->port->lmon_counters = kzalloc(sizeof(atomic_t) * CASS_LMON_NUM_COUNTERS, GFP_KERNEL);
+
+	for (i = 0; i < CASS_LMON_NUM_COUNTERS; ++i)
+		atomic_set(&hw->port->lmon_counters[i], 0);
+}
+
+/*
+ * Destroy the port's counter array
+ */
+void cass_lmon_counters_term(struct cass_dev *hw)
+{
+	kfree(hw->port->lmon_counters);
+	hw->port->lmon_counters = NULL;
+}
diff --git a/drivers/net/ethernet/hpe/ss1/cass_lni.c b/drivers/net/ethernet/hpe/ss1/cass_lni.c
new file mode 100644
index 000000000000..bb33bd00f92c
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_lni.c
@@ -0,0 +1,404 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2018, 2024-2026 Hewlett Packard Enterprise Development LP */
+
+/* Cassini NI management */
+
+#include <linux/types.h>
+
+#include "cass_core.h"
+#include "cxi_internal.h"
+#include "cxi_vf_cmd.h"
+#include "cass_ss1_debugfs.h"
+
+unsigned int cxi_lni_get_pe_num(struct cxi_lni_priv *lni)
+{
+	int pe;
+	int xchg;
+
+	/* Round robin across all PEs. */
+	do {
+		pe = atomic_read(&lni->lpe_pe_num);
+		xchg = pe + 1;
+		if (xchg == C_PE_COUNT)
+			xchg = 0;
+	} while (atomic_cmpxchg(&lni->lpe_pe_num, pe, xchg) != pe);
+
+	return pe;
+}
+
+/**
+ * cxi_lni_alloc_vf() - Allocate a logical NI (LNI) for VF
+ *
+ * @dev: CXI device
+ * @svc_id: Service ID of service to be used. May be CXI_DEFAULT_SVC_ID.
+ *
+ * Return: Pointer to allocated LNI on success, ERR_PTR on failure.
+ */
+static struct cxi_lni *cxi_lni_alloc_vf(struct cxi_dev *dev,
+					unsigned int svc_id)
+{
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+	struct cxi_lni_priv_vf *lni_priv_vf;
+	const struct cxi_lni_alloc_cmd lni_alloc_cmd = {
+		.op = CXI_OP_LNI_ALLOC,
+		.svc_id = svc_id,
+	};
+	struct cxi_phys_lac_alloc_cmd lac_alloc_cmd = {
+		.op = CXI_OP_PHYS_LAC_ALLOC,
+		.resp = NULL,
+	};
+	struct cxi_lni_alloc_resp_vf lni_alloc_resp;
+	struct cxi_phys_lac_alloc_resp lac_alloc_resp;
+	size_t resp_len;
+	int rc;
+
+	lni_priv_vf = kzalloc(sizeof(*lni_priv_vf), GFP_KERNEL);
+	if (!lni_priv_vf)
+		return ERR_PTR(-ENOMEM);
+
+	resp_len = sizeof(lni_alloc_resp);
+	rc = cxi_send_msg_to_pf(&hw->cdev, &lni_alloc_cmd, sizeof(lni_alloc_cmd),
+				&lni_alloc_resp, &resp_len);
+	if (rc)
+		goto error_out;
+
+	lni_priv_vf->dev = dev;
+	lni_priv_vf->lni.id = lni_alloc_resp.base.lni;
+	lni_priv_vf->lni.rgid = lni_alloc_resp.rgid;
+
+	/* Allocate Physical LAC for this LNI */
+	resp_len = sizeof(lac_alloc_resp);
+	lac_alloc_cmd.lni = lni_priv_vf->lni.id;
+	rc = cxi_send_msg_to_pf(&hw->cdev, &lac_alloc_cmd, sizeof(lac_alloc_cmd),
+				&lac_alloc_resp, &resp_len);
+	if (rc) {
+		lni_priv_vf->phys_lac = -1;
+		cxi_lni_free(&lni_priv_vf->lni);
+		return ERR_PTR(rc);
+	}
+	lni_priv_vf->phys_lac = lac_alloc_resp.lac;
+
+	return &lni_priv_vf->lni;
+
+error_out:
+	kfree(lni_priv_vf);
+
+	return ERR_PTR(rc);
+}
+
+/**
+ * cxi_lni_alloc_internal() - Allocate a logical NI (LNI) internal function
+ *
+ * @dev: CXI device
+ * @svc_id: Service ID of service to be used. May be CXI_DEFAULT_SVC_ID.
+ * @vf_en: true if this LNI is for a VF
+ * @vf_num: VF number (ignored unless vf_en is true)
+ */
+struct cxi_lni *cxi_lni_alloc_internal(struct cxi_dev *dev, unsigned int svc_id,
+				       bool vf_en, u8 vf_num)
+{
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+	struct cxi_lni_priv *lni_priv;
+	struct cxi_rgroup *rgroup;
+	int rc;
+	int id;
+	int rgid;
+	void *err;
+
+	rc = cxi_dev_find_rgroup_inc_refcount(dev, svc_id, &rgroup);
+	if (rc)
+		return ERR_PTR(-EINVAL);
+
+	/* Ensure service is enabled */
+	if (!cxi_rgroup_is_enabled(rgroup)) {
+		err = ERR_PTR(-EKEYREVOKED);
+		goto dec_svc;
+	}
+
+	/* Verify calling user/group has permission to use this service */
+	if (!cxi_rgroup_valid_user(rgroup)) {
+		err = ERR_PTR(-EPERM);
+		goto dec_svc;
+	}
+
+	rgid = cass_rgid_get(hw, rgroup);
+	if (rgid < 0) {
+		err = ERR_PTR(rgid);
+		goto dec_svc;
+	}
+
+	id = ida_alloc_min(&hw->lni_table, 1, GFP_KERNEL);
+	if (id < 0) {
+		err = ERR_PTR(id);
+		goto put_rgid;
+	}
+
+	lni_priv = kzalloc(sizeof(*lni_priv), GFP_KERNEL);
+	if (!lni_priv) {
+		err = ERR_PTR(-ENOMEM);
+		goto free_lni_id;
+	}
+
+	lni_priv->is_vf = vf_en;
+	if (vf_en) {
+		lni_priv->vf_num = vf_num;
+		lni_priv->phys_ac = hw->vfs[vf_num].phys_ac;
+	} else {
+		lni_priv->phys_ac = ATU_PHYS_AC;
+	}
+
+	lni_priv->rgroup = rgroup;
+	lni_priv->dev = dev;
+	lni_priv->lni.id = id;
+	lni_priv->lni.rgid = rgid;
+	lni_priv->pid = current->pid;
+	atomic_set(&lni_priv->lpe_pe_num, rgid % C_PE_COUNT);
+
+	spin_lock_init(&lni_priv->res_lock);
+	refcount_set(&lni_priv->refcount, 1);
+	mutex_init(&lni_priv->ac_list_mutex);
+
+	INIT_LIST_HEAD(&lni_priv->domain_list);
+	INIT_LIST_HEAD(&lni_priv->eq_list);
+	INIT_LIST_HEAD(&lni_priv->cq_list);
+	INIT_LIST_HEAD(&lni_priv->pt_list);
+	INIT_LIST_HEAD(&lni_priv->ac_list);
+	INIT_LIST_HEAD(&lni_priv->ct_list);
+	INIT_LIST_HEAD(&lni_priv->reserved_pids);
+	INIT_LIST_HEAD(&lni_priv->ct_cleanups_list);
+	INIT_LIST_HEAD(&lni_priv->pt_cleanups_list);
+	INIT_LIST_HEAD(&lni_priv->cq_cleanups_list);
+	INIT_LIST_HEAD(&lni_priv->eq_cleanups_list);
+
+	spin_lock(&hw->lni_lock);
+	list_add_tail(&lni_priv->list, &hw->lni_list);
+	atomic_inc(&hw->stats.lni);
+	spin_unlock(&hw->lni_lock);
+
+	refcount_inc(&hw->refcount);
+
+	lni_debugfs_create(lni_priv->lni.id, hw, lni_priv);
+
+	return &lni_priv->lni;
+
+free_lni_id:
+	ida_free(&hw->lni_table, id);
+put_rgid:
+	cass_rgid_put(hw, rgid);
+dec_svc:
+	cxi_rgroup_dec_refcount(rgroup);
+	return err;
+}
+EXPORT_SYMBOL(cxi_lni_alloc_internal);
+
+/**
+ * cxi_lni_alloc() - Allocate a logical NI (LNI)
+ *
+ * @dev: CXI device
+ * @svc_id: Service ID of service to be used. May be CXI_DEFAULT_SVC_ID.
+ */
+struct cxi_lni *cxi_lni_alloc(struct cxi_dev *dev, unsigned int svc_id)
+{
+	return dev->is_physfn ? cxi_lni_alloc_internal(dev, svc_id, false, 0) :
+				cxi_lni_alloc_vf(dev, svc_id);
+}
+EXPORT_SYMBOL(cxi_lni_alloc);
+
+int cxi_lni_pid_alloc(struct cxi_lni *lni)
+{
+	struct cxi_lni_priv *owner = container_of(lni, struct cxi_lni_priv, lni);
+	struct cass_dev *hw;
+	unsigned int pid;
+	int ret = -ENOSPC;
+
+	if (!owner->dev->is_physfn)
+		return -EOPNOTSUPP;
+	hw = container_of(owner->dev, struct cass_dev, cdev);
+	spin_lock(&hw->pid_pool_lock);
+	for (pid = 0; pid < owner->dev->prop.pid_count; pid++) {
+		if (test_bit(pid, hw->leased_pids) || hw->pid_usecount[pid])
+			continue;
+		set_bit(pid, hw->leased_pids);
+		set_bit(pid, owner->leased_pids);
+		ret = pid;
+		break;
+	}
+	spin_unlock(&hw->pid_pool_lock);
+	return ret;
+}
+EXPORT_SYMBOL_GPL(cxi_lni_pid_alloc);
+
+void cxi_lni_pid_free(struct cxi_lni *lni, unsigned int pid)
+{
+	struct cxi_lni_priv *owner = container_of(lni, struct cxi_lni_priv, lni);
+	struct cass_dev *hw;
+
+	if (!owner->dev->is_physfn)
+		return;
+	hw = container_of(owner->dev, struct cass_dev, cdev);
+	spin_lock(&hw->pid_pool_lock);
+	if (!WARN_ON(pid >= owner->dev->prop.pid_count ||
+		     !test_bit(pid, owner->leased_pids) || hw->pid_usecount[pid])) {
+		clear_bit(pid, owner->leased_pids);
+		clear_bit(pid, hw->leased_pids);
+	}
+	spin_unlock(&hw->pid_pool_lock);
+}
+EXPORT_SYMBOL_GPL(cxi_lni_pid_free);
+
+/* Cleanup of an LNI. Return true if cleanup succeeded.
+ *
+ * If force is true, the LNI will be freed even if the CQs are still
+ * busy. This is only intended for driver unloading.
+ */
+static bool try_cleanup_lni(struct cxi_lni_priv *lni, bool force)
+{
+	struct cxi_dev *dev = lni->dev;
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+
+	/* Cleanup cannot progress until all the CQs have been freed */
+	finalize_cq_cleanups(lni, force);
+	if (!force && !list_empty(&lni->cq_cleanups_list))
+		return false;
+
+	/* Same with the portals */
+	finalize_pt_cleanups(lni, force);
+	if (!force && !list_empty(&lni->pt_cleanups_list))
+		return false;
+
+	finalize_eq_cleanups(lni);
+	finalize_ct_cleanups(lni);
+
+	cass_acs_free(lni);
+
+	cxidev_WARN_ONCE(dev,
+			 !refcount_dec_and_test(&lni->refcount),
+			 "Resource leaks - LNI refcount not zero: %d\n",
+			 refcount_read(&lni->refcount));
+
+	debugfs_remove_recursive(lni->debug_dir);
+
+	cxi_rgroup_dec_refcount(lni->rgroup);
+	refcount_dec(&hw->refcount);
+	atomic_dec(&hw->stats.lni);
+	ida_free(&hw->lni_table, lni->lni.id);
+	cass_rgid_put(hw, lni->lni.rgid);
+
+	return true;
+}
+
+/* Try to cleanup all the pending LNIs.
+ * Returns false if at least one LNI is still pending.
+ *
+ * If force is true, the LNIs will be cleaned up.
+ */
+bool lni_cleanups(struct cass_dev *hw, bool force)
+{
+	struct cxi_lni_priv *lni;
+	struct cxi_lni_priv *tmp;
+	bool done = true;
+
+	mutex_lock(&hw->lni_cleanups_lock);
+
+	list_for_each_entry_safe(lni, tmp, &hw->lni_cleanups_list, list) {
+		if (try_cleanup_lni(lni, force)) {
+			list_del(&lni->list);
+			kfree(lni);
+		} else {
+			done = false;
+		}
+	}
+
+	mutex_unlock(&hw->lni_cleanups_lock);
+
+	return done;
+}
+
+void lni_cleanups_work(struct work_struct *work)
+{
+	struct cass_dev *hw =
+		container_of(work, struct cass_dev, lni_cleanups_work.work);
+
+	/* If cleanup is not complete, reschedule the work. */
+	if (!lni_cleanups(hw, false))
+		mod_delayed_work(system_wq, &hw->lni_cleanups_work, HZ);
+}
+
+/**
+ * cxi_lni_free_vf() - Shutdown and release an LNI for a VF.
+ *
+ * @lni: LNI to release
+ */
+static int cxi_lni_free_vf(struct cxi_lni *lni)
+{
+	struct cxi_lni_priv_vf *lni_priv_vf =
+		container_of(lni, struct cxi_lni_priv_vf, lni);
+	struct cxi_dev *dev = lni_priv_vf->dev;
+	const struct cxi_lni_free_cmd lni_free_cmd = {
+		.op = CXI_OP_LNI_FREE,
+		.lni = lni_priv_vf->lni.id,
+	};
+	const struct cxi_phys_lac_free_cmd lac_free_cmd = {
+		.op = CXI_OP_PHYS_LAC_FREE,
+		.lni = lni_priv_vf->lni.id,
+		.lac = lni_priv_vf->phys_lac,
+	};
+	size_t resp_len;
+	int rc;
+
+	/* Free the physical LAC */
+	if (lni_priv_vf->phys_lac >= 0) {
+		resp_len = 0;
+		cxi_send_msg_to_pf(dev, &lac_free_cmd, sizeof(lac_free_cmd), NULL, &resp_len);
+	}
+
+	/* Free LNI */
+	resp_len = 0;
+	rc = cxi_send_msg_to_pf(dev, &lni_free_cmd, sizeof(lni_free_cmd), NULL, &resp_len);
+	if (rc)
+		return rc;
+
+	kfree(lni_priv_vf);
+
+	return 0;
+}
+
+/**
+ * cxi_lni_free() - Shutdown and release an LNI.
+ *
+ * @lni: LNI to release
+ */
+int cxi_lni_free(struct cxi_lni *lni)
+{
+	struct cxi_lni_priv *lni_priv =
+		container_of(lni, struct cxi_lni_priv, lni);
+	struct cxi_dev *dev = lni_priv->dev;
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+
+	if (!hw->cdev.is_physfn)
+		return cxi_lni_free_vf(lni);
+
+	spin_lock(&hw->lni_lock);
+	list_del(&lni_priv->list);
+	spin_unlock(&hw->lni_lock);
+
+	cxi_domain_lni_cleanup(lni_priv);
+
+	if (hw->cdev.is_physfn) {
+		cass_acs_disable(lni_priv);
+		cxi_inbound_wait(dev);
+	}
+
+	if (try_cleanup_lni(lni_priv, false)) {
+		kfree(lni_priv);
+	} else {
+		mutex_lock(&hw->lni_cleanups_lock);
+		list_add_tail(&lni_priv->list, &hw->lni_cleanups_list);
+		mutex_unlock(&hw->lni_cleanups_lock);
+
+		mod_delayed_work(system_wq, &hw->lni_cleanups_work, HZ);
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(cxi_lni_free);
diff --git a/drivers/net/ethernet/hpe/ss1/cass_odp_decouple.c b/drivers/net/ethernet/hpe/ss1/cass_odp_decouple.c
new file mode 100644
index 000000000000..29711586e535
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_odp_decouple.c
@@ -0,0 +1,599 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2021 Hewlett Packard Enterprise Development LP */
+
+/*
+ * ODP decoupling in software to work around Cassini ERRATA-3260
+ *
+ * Notes:
+ *
+ * 1. We will enter ODP decoupling when an invalidation completion wait
+ *    times out.
+ * 2. Find out the ID of the previous epoch. The completion wait command
+ *    triggers the switch between epochs. We need to know which one is blocked.
+ *    Read C_ATU_STS_AT_EPOCH. The previous epoch x = !CURRENT_EPOCH
+ * 3. If IXE_EPOCH*x*CNTR_NE0 is zero. The completion wait just finished.
+ *    Return from decoupling procedure and continue ODP processing. (return)
+ * 4. If IXE_EPOCH*x*_CNTR_NE0 is one, we need to find out if this epoch
+ *    counter is stuck or continues to decrement. Read repeatedly to see if
+ *    EPOCH*x* is moving. The interval between reads should be around 32
+ *    microseconds.
+ * 5. If EPOCH*x* returns to zero, return from decoupling procedure. (return)
+ * 6. If EPOCH*x* does not change between two reads, we determine that WRQ is
+ *    stuck with ODP at the head of the queue.
+ * 6.1  Get the previous Inbound Epoch. z = !C_ATU_STS_IB_EPOCH.CURRENT_EPOCH
+ * 6.2  Check C_ATU_STS_IB_EPOCH_CNTR.EPOCH*z*
+ *      If it is zero, we are not in the active Inbound wait and ready to
+ *      issue a new InboundWait (step 6.3)
+ *      If it is not zero, InboundWait is in progress. We need to wait for
+ *      this counter to get to zero before we issue a new one (step 6.3).
+ *      This counter may stop decrementing before it gets to zero. If it
+ *      happens, we do not need to issue a new InboundWait and should
+ *      proceed to step #7.
+ * 6.3  Issue an InboundWait and update z = !C_ATU_STS_IB_EPOCH.CURRENT_EPOCH
+ * 6.4  Monitor C_ATU_STS_IB_EPOCH_CNTR.EPOCH*z*
+ *      If it returns to zero, exit this procedure. Check
+ *      C_ATU_STS_IXE_AT_EPOCH_CNTR.EPOCHx. We expect the translation epoch
+ *      to be zero as well so no need for HW decoupling. If the translation
+ *      epoch counter is not zero, return a critical error.
+ *      If the counter stops decrementing, proceed to step #7.
+ * 7. To avoid Cassini ERRATA-3241, make sure EE and OXE epochs are at zero. Read
+ *    C_ATU_STS_AT_EPOCH to check if OXE_EPOCH*x*_CNTR_NE0 and
+ *    EE_EPOCH*x*_CNTR_NE0 are zero. If that is not the case, start pulling
+ *    C_ATU_STS_OXE_AT_EPOCH_CNTR and C_ATU_STS_EE_AT_EPOCH_CNTR, checking
+ *    EPOCH*x*, at 100 microseconds intervals. These counters should decrement
+ *    to zero. Detecting one of the counters being stuck indicates an
+ *    unexpected problem; print a critical error.
+ * 8. At this point, it is safe to enable HW decoupling
+ *    (C_ATU_CFG_ODP_DECOUPLE.ENABLE=1)
+ * 9. Continue reading C_ATU_STS_IXE_AT_EPOCH_CNTR, waiting for EPOCH*x* to
+ *    return to zero. If it does not happen for 100 ms, we have a problem,
+ *    print a critical error to get the node rebooted.
+ * 10.Once EPOCH*x* values for all three clients are zero, disable HW
+ *    decoupling (C_ATU_CFG_ODP_DECOUPLE.ENABLE=0) continue processing
+ *    invalidations. Return from decoupling procedure and continue ODP
+ *    processing. (return)
+ */
+
+#include <linux/iopoll.h>
+#include "cass_core.h"
+
+#define IXE_ECNTR C_ATU_STS_IXE_AT_EPOCH_CNTR
+#define IB_ECNTR C_ATU_STS_IB_EPOCH_CNTR
+
+static int ibw_epoch_wait_us = 50;
+module_param(ibw_epoch_wait_us, int, 0644);
+MODULE_PARM_DESC(ibw_epoch_wait_us,
+		 "Inbound epoch counter decrement wait time");
+
+static int ixe_epoch_wait_us = 32;
+module_param(ixe_epoch_wait_us, int, 0644);
+MODULE_PARM_DESC(ixe_epoch_wait_us,
+		 "Initial IXE epoch counter decrement wait time");
+
+static int epoch_wait_us = 100;
+module_param(epoch_wait_us, int, 0644);
+MODULE_PARM_DESC(epoch_wait_us, "Epoch counter decrement wait time");
+
+static void enable_hw_decoupling(struct cass_dev *hw, bool enable)
+{
+	union c1_atu_cfg_odp_decouple odp_dcpl = {
+		.flush_req_delay = ATU_FLUSH_REQ_DELAY,
+		.enable = enable
+	};
+
+	cass_write(hw, C1_ATU_CFG_ODP_DECOUPLE, &odp_dcpl, sizeof(odp_dcpl));
+}
+
+/* read/clear file operations */
+static int decouple_stats_read(struct seq_file *s, void *unused)
+{
+	int i;
+	long bin;
+	struct timespec64 time;
+	struct cass_dev *hw = s->private;
+
+	seq_printf(s, "completion_wait:%d\n",
+		   atomic_read(&hw->dcpl_comp_wait));
+	seq_printf(s, "md_clear_inval:%d\n",
+		   atomic_read(&hw->dcpl_md_clear_inval));
+	seq_printf(s, "nta_mn_inval:%d\n",
+		   atomic_read(&hw->dcpl_nta_mn_inval));
+	seq_printf(s, "ats_mn_inval:%d\n",
+		   atomic_read(&hw->dcpl_ats_mn_inval));
+	seq_printf(s, "ee_cntr_dec_0:%d\n",
+		   atomic_read(&hw->dcpl_ee_cntr_dec_0));
+	seq_printf(s, "ee_cntr_stuck:%d\n",
+		   atomic_read(&hw->dcpl_ee_cntr_stuck));
+	seq_printf(s, "oxe_cntr_dec_0:%d\n",
+		   atomic_read(&hw->dcpl_oxe_cntr_dec_0));
+	seq_printf(s, "oxe_cntr_stuck:%d\n",
+		   atomic_read(&hw->dcpl_oxe_cntr_stuck));
+	seq_printf(s, "ixe_cntr_0:%d\n",
+		   atomic_read(&hw->dcpl_ixe_cntr_0));
+	seq_printf(s, "ixe_cntr_dec_0:%d\n",
+		   atomic_read(&hw->dcpl_ixe_cntr_dec_0));
+	seq_printf(s, "ixe_cntr_stuck:%d\n",
+		   atomic_read(&hw->dcpl_ixe_cntr_stuck));
+	seq_printf(s, "ibw_cntr_dec_0_62:%d\n",
+		   atomic_read(&hw->dcpl_ibw_cntr_dec_0_62));
+	seq_printf(s, "ibw_cntr_dec_0_62_count:%d\n",
+		   atomic_read(&hw->dcpl_ibw_cntr_dec_0_62_count));
+	seq_printf(s, "ibw_cntr_dec_0_64:%d\n",
+		   atomic_read(&hw->dcpl_ibw_cntr_dec_0_64));
+	seq_printf(s, "ibw_cntr_dec_0_64_count:%d\n",
+		   atomic_read(&hw->dcpl_ibw_cntr_dec_0_64_count));
+	seq_printf(s, "step7:%d\n",
+		   atomic_read(&hw->dcpl_step7));
+	seq_printf(s, "ibw_active_stuck:%d\n",
+		   atomic_read(&hw->dcpl_ibw_active_stuck));
+	seq_printf(s, "ibw_idle_wait:%d\n",
+		   atomic_read(&hw->dcpl_ibw_idle_wait));
+	seq_printf(s, "ibw_cntr_is_0:%d\n",
+		   atomic_read(&hw->dcpl_ibw_cntr_is_0));
+	seq_printf(s, "ibw_issued:%d\n",
+		   atomic_read(&hw->dcpl_ibw_issued));
+	seq_printf(s, "entered:%d\n",
+		   atomic_read(&hw->dcpl_entered));
+	seq_printf(s, "success:%d\n",
+		   atomic_read(&hw->dcpl_success));
+
+	time = ktime_to_timespec64(hw->dcpl_max_time);
+	seq_printf(s, "dcpl_max_time:%lld.%06lds\n",
+		   time.tv_sec,
+		       time.tv_nsec / NSEC_PER_USEC);
+
+	for (i = 0, bin = FIRST_BIN; i < DBINS; i++, bin <<= 1) {
+		time = ktime_to_timespec64(bin);
+		seq_printf(s, "dcpl_time_bin:%lld.%06lds:%d\n",
+			   time.tv_sec, time.tv_nsec / NSEC_PER_USEC,
+			   hw->dcpl_time[i]);
+	}
+
+	time = ktime_to_timespec64(hw->pri_max_md_time);
+	seq_printf(s, "pri_max_md_time:%lld.%06lds\n",
+		   time.tv_sec,
+		       time.tv_nsec / NSEC_PER_USEC);
+
+	for (i = 0, bin = FIRST_MDBIN; i < MDBINS; i++, bin <<= 1) {
+		time = ktime_to_timespec64(bin);
+		seq_printf(s, "pri_md_time_bin:%lld.%06lds:%d\n",
+			   time.tv_sec, time.tv_nsec / NSEC_PER_USEC,
+			   hw->pri_md_time[i]);
+	}
+
+	time = ktime_to_timespec64(hw->pri_max_fault_time);
+	seq_printf(s, "pri_max_fault_time:%lld.%06lds\n",
+		   time.tv_sec,
+		       time.tv_nsec / NSEC_PER_USEC);
+
+	for (i = 0, bin = FIRST_FBIN; i < FBINS; i++, bin <<= 1) {
+		time = ktime_to_timespec64(bin);
+		seq_printf(s, "pri_fault_time_bin:%lld.%06lds:%d\n",
+			   time.tv_sec, time.tv_nsec / NSEC_PER_USEC,
+			   hw->pri_fault_time[i]);
+	}
+
+	return 0;
+}
+
+static ssize_t decouple_stats_write(struct file *f, const char __user *buf,
+				    size_t size, loff_t *pos)
+{
+	int i;
+	struct cass_dev *hw = file_inode(f)->i_private;
+
+	atomic_set(&hw->dcpl_md_clear_inval, 0);
+	atomic_set(&hw->dcpl_nta_mn_inval, 0);
+	atomic_set(&hw->dcpl_ats_mn_inval, 0);
+	atomic_set(&hw->dcpl_comp_wait, 0);
+	atomic_set(&hw->dcpl_entered, 0);
+	atomic_set(&hw->dcpl_ixe_cntr_0, 0);
+	atomic_set(&hw->dcpl_ixe_cntr_dec_0, 0);
+	atomic_set(&hw->dcpl_ee_cntr_dec_0, 0);
+	atomic_set(&hw->dcpl_ee_cntr_stuck, 0);
+	atomic_set(&hw->dcpl_oxe_cntr_dec_0, 0);
+	atomic_set(&hw->dcpl_oxe_cntr_stuck, 0);
+	atomic_set(&hw->dcpl_ixe_cntr_stuck, 0);
+	atomic_set(&hw->dcpl_success, 0);
+	atomic_set(&hw->dcpl_ibw_cntr_dec_0_62, 0);
+	atomic_set(&hw->dcpl_ibw_cntr_dec_0_62_count, 0);
+	atomic_set(&hw->dcpl_ibw_cntr_dec_0_64, 0);
+	atomic_set(&hw->dcpl_ibw_cntr_dec_0_64_count, 0);
+	atomic_set(&hw->dcpl_step7, 0);
+	atomic_set(&hw->dcpl_ibw_active_stuck, 0);
+	atomic_set(&hw->dcpl_ibw_idle_wait, 0);
+	atomic_set(&hw->dcpl_ibw_cntr_is_0, 0);
+	atomic_set(&hw->dcpl_ibw_issued, 0);
+
+	hw->dcpl_max_time = 0;
+	for (i = 0; i < DBINS; i++)
+		hw->dcpl_time[i] = 0;
+
+	hw->pri_max_md_time = 0;
+	for (i = 0; i < MDBINS; i++)
+		hw->pri_md_time[i] = 0;
+	hw->pri_max_fault_time = 0;
+	for (i = 0; i < FBINS; i++)
+		hw->pri_fault_time[i] = 0;
+
+	return size;
+}
+
+static int decouple_stats_read_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, decouple_stats_read, inode->i_private);
+}
+
+const struct file_operations decouple_stats_fops = {
+	.owner = THIS_MODULE,
+	.open = decouple_stats_read_open,
+	.read = seq_read,
+	.write = decouple_stats_write,
+	.llseek  = seq_lseek,
+	.release = single_release,
+};
+
+static ssize_t sw_dcpl_read(struct file *f, char __user *buf, size_t size,
+			    loff_t *pos)
+{
+	char b[3];
+
+	b[0] = odp_sw_decouple ? 'Y' : 'N';
+	b[1] = '\n';
+	b[2] = '\0';
+
+	return simple_read_from_buffer(buf, size, pos, b, 3);
+}
+
+static ssize_t sw_dcpl_write(struct file *f, const char __user *buf,
+			     size_t size, loff_t *pos)
+{
+	int ret;
+	bool user_value;
+	struct cass_dev *hw = file_inode(f)->i_private;
+
+	ret = kstrtobool_from_user(buf, size, &user_value);
+	if (ret)
+		return ret;
+
+	odp_sw_decouple = user_value;
+	enable_hw_decoupling(hw, !odp_sw_decouple);
+
+	return size;
+}
+
+const struct file_operations sw_decouple_fops = {
+	.owner = THIS_MODULE,
+	.read = sw_dcpl_read,
+	.write = sw_dcpl_write,
+	.llseek = default_llseek
+};
+
+static void add_dcpl_time_to_bin(struct cass_dev *hw, ktime_t time)
+{
+	int i;
+	int bin = FIRST_BIN;
+
+	if (ktime_compare(hw->dcpl_max_time, time) < 0)
+		hw->dcpl_max_time = time;
+
+	for (i = 0; i < DBINS; i++, bin <<= 1) {
+		if (time < bin) {
+			hw->dcpl_time[i]++;
+			break;
+		}
+	}
+}
+
+/**
+ * cass_wait_epoch_cntr_dec_zero()
+ *
+ * Wait for one of the c_atu_sts_*_at_epoch_cntr counters to decrement to 0.
+ * The counters all use the same struct.
+ *
+ * @hw: the device
+ * @csr: Address of CSR to poll
+ * @sleep_us: Sleep time in microseconds
+ * @epoch: Which counter (0 or 1) to poll
+ * @loop_count: How many times through the loop. If the count is 0 the first
+ *              time, the count will be zero.
+ * Return: 0 on success, -1 if not decrementing
+ */
+static int cass_wait_epoch_cntr_dec_zero(struct cass_dev *hw, u64 csr,
+					 ulong sleep_us, int epoch,
+					 int *loop_count)
+{
+	int i;
+	int ret = 0;
+	u64 count;
+	u64 last_count = 0xffff;
+	union c_atu_sts_ixe_at_epoch_cntr ecntr;
+
+	for (i = 0; last_count > 0; i++) {
+		cass_read(hw, csr, &ecntr, sizeof(ecntr));
+		count = epoch ? ecntr.epoch1 : ecntr.epoch0;
+
+		if (!count)
+			break;
+
+		if (count >= last_count) {
+			ret = -1;
+			break;
+		}
+
+		last_count = count;
+		usleep_range(sleep_us, sleep_us * 2);
+	};
+
+	*loop_count = i;
+
+	return ret;
+}
+
+/**
+ * ixe_epoch_cntr_0() - Check if IXE epoch counter is zero
+ *
+ * @epoch_sts: Epoch status
+ * @epoch: The current epoch (false for epoch 0, true for epoch 1)
+ * Return: true if zero, false if not zero
+ */
+static bool ixe_epoch_cntr_0(union c_atu_sts_at_epoch *epoch_sts, bool epoch)
+{
+	if (!epoch) {
+		if (!epoch_sts->ixe_epoch0_cntr_ne0)
+			return true;
+	} else {
+		if (!epoch_sts->ixe_epoch1_cntr_ne0)
+			return true;
+	}
+
+	return false;
+}
+
+/**
+ * ibw_epoch_cntr_is_0() - Check if IBW epoch counter is zero
+ *
+ * @hw: the device
+ * @epoch_ret: Return the current_epoch
+ * Return: true if zero, false if not zero
+ */
+static bool ibw_epoch_cntr_is_0(struct cass_dev *hw, bool *epoch_ret)
+{
+	bool epoch;
+	union c_atu_sts_ib_epoch epoch_sts;
+
+	cass_read(hw, C_ATU_STS_IB_EPOCH, &epoch_sts, sizeof(epoch_sts));
+	epoch = !epoch_sts.current_epoch;
+
+	*epoch_ret = epoch;
+
+	if (!epoch) {
+		if (!epoch_sts.epoch0_cntr_ne0)
+			return true;
+	} else {
+		if (!epoch_sts.epoch1_cntr_ne0)
+			return true;
+	}
+
+	return false;
+}
+
+/**
+ * ibw_epoch_cntr_is_stuck() - Check if IBW counter is not decrementing
+ *                             Steps 6.1 and 6.2
+ *
+ * @hw: the device
+ * Return: true if stuck, false if 0 or returned to 0
+ */
+static bool ibw_epoch_cntr_is_stuck(struct cass_dev *hw)
+{
+	int ret;
+	int count;
+	bool ibw_epoch;
+
+	/* Step 6.1 - Get the previous Inbound Epoch */
+	ret = ibw_epoch_cntr_is_0(hw, &ibw_epoch);
+	if (ret)
+		return false;
+
+	/* Step 6.2 - Wait for inbound epoch counter to decrement to zero. */
+	ret = cass_wait_epoch_cntr_dec_zero(hw, IB_ECNTR, ibw_epoch_wait_us,
+					    ibw_epoch, &count);
+	if (!ret) {
+		atomic_inc(&hw->dcpl_ibw_cntr_dec_0_62);
+		atomic_add(count, &hw->dcpl_ibw_cntr_dec_0_62_count);
+		return false;
+	}
+
+	return true;
+}
+
+/**
+ * cass_odp_decouple() - handles spurious translation request due to
+ * bug
+ *
+ * WORKAROUND for Cassini ERRATA-3260
+ * In specific conditions, writes can be acked with a spurious pending
+ * translation request remaining. If not addressed with this function,
+ * then data corruption could occur.
+ *
+ * @hw: the device
+ * Return: 0 on success, negative value on failure
+ */
+int cass_odp_decouple(struct cass_dev *hw)
+{
+	int ret = 0;
+	int count;
+	bool ibw_epoch;
+	bool blocked_epoch;
+	union c_atu_sts_at_epoch at_epoch_sts;
+	union c_atu_sts_ixe_at_epoch_cntr ecntr;
+	struct cass_atu_cq *cq = &hw->atu_cq;
+	ktime_t start = ktime_get_raw();
+	struct sts_idle ibw_idle = {
+		.hw = hw,
+		.ib_wait = true
+	};
+
+	/* Step 1 */
+	atomic_inc(&hw->dcpl_entered);
+
+	/* Step 2 */
+	cass_read(hw, C_ATU_STS_AT_EPOCH, &at_epoch_sts, sizeof(at_epoch_sts));
+	blocked_epoch = !at_epoch_sts.current_epoch;
+
+	/* Step 3 - Check either IXE epoch counter 0 or 1 depending on the
+	 * current epoch.
+	 */
+	if (ixe_epoch_cntr_0(&at_epoch_sts, blocked_epoch)) {
+		atomic_inc(&hw->dcpl_ixe_cntr_0);
+		goto done;
+	}
+
+	/* Step 4/5 - Check if C_ATU_STS_IXE_AT_EPOCH_CNTR is stuck or returns
+	 * to 0.
+	 */
+	ret = cass_wait_epoch_cntr_dec_zero(hw, IXE_ECNTR, ixe_epoch_wait_us,
+					    blocked_epoch, &count);
+	if (!ret) {
+		atomic_inc(&hw->dcpl_ixe_cntr_dec_0);
+		goto done;
+	}
+
+	/* This function may have completed with IBW active so check if it
+	 * still is. Also, inbound wait leaves the inbound_wait_idle inactive
+	 * for some time after it has completed so we need to wait for idle
+	 * before issuing a new inbound wait.
+	 * If IBW is not idle, check if the IBW epoch counter is stuck.
+	 */
+	while (!cass_sts_idle(&ibw_idle)) {
+		if (ibw_epoch_cntr_is_stuck(hw)) {
+			atomic_inc(&hw->dcpl_ibw_active_stuck);
+			goto step_7;
+		}
+		usleep_range(10, 20);
+	}
+
+	/* Determine if another process has issued an inbound wait since the
+	 * lock will be held in that case.
+	 * If we don't get the lock, then cxi_inbound_wait() is in progress.
+	 * If IBW is idle, the c_atu_cfg_inbound_wait may not have been
+	 * written yet or it is just completing and the lock will be released
+	 * soon. We will wait for a not idle status before we can continue to
+	 * step 6.1.
+	 */
+	while (!mutex_trylock(&cq->atu_ib_mutex)) {
+		if (cass_sts_idle(&ibw_idle)) {
+			atomic_inc(&hw->dcpl_ibw_idle_wait);
+			usleep_range(10, 20);
+			continue;
+		}
+
+		/* Step 6.1/6.2 */
+		ret = ibw_epoch_cntr_is_stuck(hw);
+		if (ret)
+			goto step_7;
+
+		atomic_inc(&hw->dcpl_ibw_cntr_is_0);
+	}
+
+	/* Check for idle after we have the lock */
+	if (!cass_sts_idle(&ibw_idle)) {
+		if (ibw_epoch_cntr_is_stuck(hw)) {
+			mutex_unlock(&cq->atu_ib_mutex);
+			goto step_7;
+		}
+	}
+
+	/* Step 6.3 - Issue inbound wait and update current epoch */
+	atomic_inc(&hw->dcpl_ibw_issued);
+	ret = cass_inbound_wait(hw, false);
+	if (ret) {
+		cxidev_crit_once(&hw->cdev, "IBW failed %d\n", ret);
+		mutex_unlock(&cq->atu_ib_mutex);
+		goto done;
+	}
+
+	/* get the new epoch */
+	ibw_epoch_cntr_is_0(hw, &ibw_epoch);
+	mutex_unlock(&cq->atu_ib_mutex);
+
+	/* 6.4  Monitor inbound epoch counter */
+	ret = cass_wait_epoch_cntr_dec_zero(hw, IB_ECNTR, ibw_epoch_wait_us,
+					    ibw_epoch, &count);
+	if (!ret) {
+		atomic_inc(&hw->dcpl_ibw_cntr_dec_0_64);
+		atomic_add(count, &hw->dcpl_ibw_cntr_dec_0_64_count);
+
+		cass_read(hw, C_ATU_STS_AT_EPOCH, &at_epoch_sts,
+			  sizeof(at_epoch_sts));
+		if (blocked_epoch != !at_epoch_sts.current_epoch)
+			cxidev_crit_once(&hw->cdev, "IXE epoch changed\n");
+
+		if (!ixe_epoch_cntr_0(&at_epoch_sts, blocked_epoch))
+			cxidev_crit_once(&hw->cdev, "IXE epoch cntr should be 0\n");
+
+		goto done;
+	}
+
+step_7:
+	/* Step 7 - Check if C_ATU_STS_EE/OXE_AT_EPOCH_CNTR are at 0. */
+	atomic_inc(&hw->dcpl_step7);
+
+	cass_read(hw, C_ATU_STS_AT_EPOCH, &at_epoch_sts, sizeof(at_epoch_sts));
+	if ((!blocked_epoch && at_epoch_sts.ee_epoch0_cntr_ne0) ||
+	    (blocked_epoch && at_epoch_sts.ee_epoch1_cntr_ne0)) {
+		atomic_inc(&hw->dcpl_ee_cntr_dec_0);
+		ret = cass_wait_epoch_cntr_dec_zero(hw,
+						    C_ATU_STS_EE_AT_EPOCH_CNTR, epoch_wait_us,
+				blocked_epoch, &count);
+		if (ret) {
+			cxidev_crit_once(&hw->cdev,
+					 "EE_AT_EPOCH_CNTR did not return to 0\n");
+			atomic_inc(&hw->dcpl_ee_cntr_stuck);
+			ret = -1;
+			goto done;
+		}
+	}
+
+	if ((!blocked_epoch && at_epoch_sts.oxe_epoch0_cntr_ne0) ||
+	    (blocked_epoch && at_epoch_sts.oxe_epoch1_cntr_ne0)) {
+		atomic_inc(&hw->dcpl_oxe_cntr_dec_0);
+		ret = cass_wait_epoch_cntr_dec_zero(hw,
+						    C_ATU_STS_OXE_AT_EPOCH_CNTR,
+				epoch_wait_us, blocked_epoch, &count);
+		if (!ret) {
+			cxidev_crit_once(&hw->cdev,
+					 "OXE_AT_EPOCH_CNTR did not return to 0\n");
+			atomic_inc(&hw->dcpl_oxe_cntr_stuck);
+			ret = -1;
+			goto done;
+		}
+	}
+
+	/* Step 8 - Now we can enable hw decoupling */
+	enable_hw_decoupling(hw, true);
+
+	/* Step 9 - Wait for IXE epoch cntr to return to 0 */
+	ret = cass_wait_epoch_cntr_dec_zero(hw, IXE_ECNTR, epoch_wait_us,
+					    blocked_epoch, &count);
+	if (!ret) {
+		atomic_inc(&hw->dcpl_success);
+	} else {
+		cass_read(hw, IXE_ECNTR, &ecntr,
+			  sizeof(ecntr));
+		cxidev_crit_once(&hw->cdev,
+				 "IXE EPOCH counter not 0 with decoupling enabled epoch:%d epoch0:%x epoch1:%x\n",
+				 blocked_epoch, ecntr.epoch0, ecntr.epoch1);
+		ret = -1;
+		atomic_inc(&hw->dcpl_ixe_cntr_stuck);
+	}
+
+	/* Step 10 - Disable hw decoupling */
+	enable_hw_decoupling(hw, false);
+
+done:
+	add_dcpl_time_to_bin(hw, ktime_get_raw() - start);
+
+	return ret;
+}
diff --git a/drivers/net/ethernet/hpe/ss1/cass_pcie_mon.c b/drivers/net/ethernet/hpe/ss1/cass_pcie_mon.c
new file mode 100644
index 000000000000..5b06427b7804
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_pcie_mon.c
@@ -0,0 +1,288 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2022 Hewlett Packard Enterprise Development LP */
+
+/* Monitoring of vendor specific PCIe counters */
+
+#include "cass_core.h"
+
+#define NUM_LANES 16
+
+/* Options for EVENT_COUNTER_CONTROL_REG register. */
+#define COUNTERS_CLEAR_ONE  (0x01 << 0)
+#define COUNTERS_CLEAR_ALL  (0x03 << 0)
+#define COUNTERS_ENABLE_ALL (0x07 << 2)
+
+struct pcie_cntrs_group {
+	u8 first;
+	u8 last;
+	const char *names[];
+};
+
+static const struct pcie_cntrs_group group_0 = {
+	0, 10,
+	{ "RX Elastic Buffer Overflow Error",
+	  "RX Elastic Buffer Underflow Error",
+	  "Decode Error",
+	  "Disparity Error",
+	  "SKP OS Parity Error",
+	  "SYNC Header Error",
+	  "RX valid de-assertion",
+	  "CTL SKP OS Parity Error",
+	  "1st Retimer Parity Error",
+	  "2nd Retimer Parity Error",
+	  "Margin CRC and Parity Error"
+	}
+};
+
+static const struct pcie_cntrs_group group_1 = {
+	5, 10,
+	{ "Detect EI Infer",
+	  "Receiver Error",
+	  "RX Recovery Request",
+	  "N_FTS Timeout",
+	  "Framing Error",
+	  "Deskew Error"
+	}
+};
+
+static const struct pcie_cntrs_group group_2 = {
+	0, 7,
+	{ "BAD TLP",
+	  "LCRC Error",
+	  "BAD DLLP",
+	  "Replay Number Rollover",
+	  "Replay Timeout",
+	  "RX Nak DLLP",
+	  "TX Nak DLLP",
+	  "Retry LLP"
+	}
+};
+
+static const struct pcie_cntrs_group group_3 = {
+	0, 5,
+	{ "FC Timeout",
+	  "Poisoned TLP",
+	  "ECRC Error",
+	  "Unsupported Request",
+	  "Completer Abort",
+	  "Completion Timeout"
+	}
+};
+
+static const struct pcie_cntrs_group group_4 = {
+	0, 1,
+	{ "EBUF SKP Add",
+	  "EBUF SKP Del"
+	}
+};
+
+static const struct pcie_cntrs_group group_5 = {
+	0, 13,
+	{ "L0 to Recovery Entry",
+	  "L1 to Recovery Entry",
+	  "TX L0s Entry",
+	  "RX L0s Entry",
+	  "ASPM L1 Reject",
+	  "L1 Entry",
+	  "L1 CPM",
+	  "L1.1 Entry",
+	  "L1.2 Entry",
+	  "L1 Short Duration",
+	  "L1.1 Abort",
+	  "L2 Entry",
+	  "Speed Change",
+	  "Link Width Change",
+	}
+};
+
+static const struct pcie_cntrs_group group_6 = {
+	0, 6,
+	{ "TX Ack DLLP",
+	  "TX Update FC DLLP",
+	  "RX ACK DLLP",
+	  "RX Update FC DLLP",
+	  "RX Nullified TLP",
+	  "TX Nullified TLP",
+	  "RX Duplicate TLP"
+	}
+};
+
+static const struct pcie_cntrs_group group_7 = {
+	0, 23,
+	{ "TX Memory Write",
+	  "TX Memory Read",
+	  "TX Configuration Write",
+	  "TX Configuration Read",
+	  "TX IO Write",
+	  "TX IO Read",
+	  "TX Completion w/o data",
+	  "TX Completion w/ data",
+	  "TX Message TLP",
+	  "TX Atomic",
+	  "TX TLP with Prefix",
+	  "RX Memory Write",
+	  "RX Memory Read",
+	  "RX Configuration Write",
+	  "RX Configuration Read",
+	  "RX IO Write",
+	  "RX IO Read",
+	  "RX Completion without data",
+	  "RX Completion w data",
+	  "RX Message TLP",
+	  "RX Atomic",
+	  "RX TLP with Prefix",
+	  "TX CCIX TLP",
+	  "RX CCIX TLP"
+	}
+};
+
+static const struct pcie_cntrs_group *groups[8] = {
+	&group_0, &group_1, &group_2, &group_3,
+	&group_4, &group_5, &group_6, &group_7
+};
+
+/* Enable and clear counters for all lanes. */
+static void enable_pcie_counters(struct cass_dev *hw)
+{
+	unsigned int lane;
+
+	for (lane = 0; lane < NUM_LANES; lane++) {
+		u32 val = lane << 8 | COUNTERS_ENABLE_ALL | COUNTERS_CLEAR_ALL;
+
+		pci_write_config_dword(hw->cdev.pdev,
+				       hw->pcie_mon.event_counter_control, val);
+	}
+}
+
+/* Clear a single lane */
+static void clear_counter_events(struct cass_dev *hw, u8 lane)
+{
+	u32 val = (lane << 8) | COUNTERS_CLEAR_ALL;
+
+	pci_write_config_dword(hw->cdev.pdev,
+			       hw->pcie_mon.event_counter_control, val);
+}
+
+/* Check whether events in a particular group are above an acceptable
+ * threshold.
+ */
+static int check_group(struct cass_dev *hw, u8 group, int first, int last,
+		       unsigned int acceptable)
+{
+	u8 event;
+	int err = 0;
+
+	for (event = first; event <= last; event++) {
+		u32 val = (group << 24) | (event << 16);
+
+		pci_write_config_dword(hw->cdev.pdev,
+				       hw->pcie_mon.event_counter_control, val);
+		pci_read_config_dword(hw->cdev.pdev,
+				      hw->pcie_mon.event_counter_data, &val);
+
+		err += val;
+
+		if (val > acceptable) {
+			const struct pcie_cntrs_group *ginfo = groups[group];
+
+			/* TODO: something that wouldn't spam logs */
+			cxidev_err(&hw->cdev, "PCIe error: %s=%u\n",
+				   ginfo->names[event - ginfo->first], val);
+		}
+	}
+
+	return err;
+}
+
+/* Monitor groups with correctable and uncorrectable errors.
+ */
+static void pcie_monitoring_task(struct work_struct *work)
+{
+	struct cass_dev *hw =
+		container_of(work, struct cass_dev, pcie_mon.task.work);
+
+	/* Uncorrectable errors. None acceptable. */
+	hw->pcie_mon.uncorr_err += check_group(hw, 3, 0, 5, 0);
+
+	/* Correctable errors. */
+	if (hw->pcie_mon.corr_err_min) {
+		hw->pcie_mon.corr_err += check_group(hw, 1, 7, 7,
+						     hw->pcie_mon.corr_err_min);
+		hw->pcie_mon.corr_err += check_group(hw, 2, 0, 7,
+						     hw->pcie_mon.corr_err_min);
+		hw->pcie_mon.corr_err += check_group(hw, 5, 0, 0,
+						     hw->pcie_mon.corr_err_min);
+	}
+
+	clear_counter_events(hw, 0);
+
+	mod_delayed_work(system_wq, &hw->pcie_mon.task, 60 * HZ);
+}
+
+void start_pcie_monitoring(struct cass_dev *hw)
+{
+	int pos;
+
+	/* Get Vendor Specific Information block */
+	pos = 0;
+	while ((pos = pci_find_next_ext_capability(hw->cdev.pdev, pos,
+						   PCI_EXT_CAP_ID_VNDR))) {
+		u32 header;
+
+		pci_read_config_dword(hw->cdev.pdev,
+				      pos + PCI_VNDR_HEADER, &header);
+
+		if (PCI_VNDR_HEADER_ID(header) == 2 &&
+		    PCI_VNDR_HEADER_REV(header) == 4 &&
+		    PCI_VNDR_HEADER_LEN(header) == 0x100) {
+			hw->pcie_mon.event_counter_control = pos + 8;
+			hw->pcie_mon.event_counter_data = pos + 12;
+			break;
+		}
+	}
+
+	if (!hw->pcie_mon.event_counter_control) {
+		cxidev_err(&hw->cdev, "PCIe monitoring is not available\n");
+		return;
+	}
+
+	/* Set the number of acceptable correctable errors per
+	 * minute depending on the link speed.
+	 */
+	switch (hw->pcie_link_speed) {
+	case PCIE_SPEED_2_5GT:
+		hw->pcie_mon.corr_err_min = 5;
+		break;
+	case PCIE_SPEED_5_0GT:
+		hw->pcie_mon.corr_err_min = 10;
+		break;
+	case PCIE_SPEED_8_0GT:
+		hw->pcie_mon.corr_err_min = 15;
+		break;
+	case PCIE_SPEED_16_0GT:
+		hw->pcie_mon.corr_err_min = 31;
+		break;
+	case CASS_SPEED_20_0GT:
+		hw->pcie_mon.corr_err_min = 40;
+		break;
+	case CASS_SPEED_25_0GT:
+		hw->pcie_mon.corr_err_min = 48;
+		break;
+	case CASS_SPEED_32_0GT:
+		hw->pcie_mon.corr_err_min = 61;
+		break;
+	}
+
+	enable_pcie_counters(hw);
+
+	INIT_DELAYED_WORK(&hw->pcie_mon.task, pcie_monitoring_task);
+	mod_delayed_work(system_wq, &hw->pcie_mon.task, 60 * HZ);
+}
+
+void stop_pcie_monitoring(struct cass_dev *hw)
+{
+	if (!hw->pcie_mon.event_counter_control)
+		return;
+
+	cancel_delayed_work_sync(&hw->pcie_mon.task);
+}
diff --git a/drivers/net/ethernet/hpe/ss1/cass_pt.c b/drivers/net/ethernet/hpe/ss1/cass_pt.c
new file mode 100644
index 000000000000..8763255b4459
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_pt.c
@@ -0,0 +1,1255 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2018-2020, 2024-2026 Hewlett Packard Enterprise Development LP */
+
+/* Create and destroy Cassini portal tables */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/hpe/cxi/cxi.h>
+#include <linux/iopoll.h>
+#include <linux/uaccess.h>
+#include <linux/delay.h>
+
+#include "cass_core.h"
+#include "cass_ss1_debugfs.h"
+
+/* Use the last logical endpoint for rendezvous offload. */
+#define RDZV_GET_IDX(pid_granule) ((pid_granule) - 1)
+
+static bool rdzv_get_en_default = true;
+module_param(rdzv_get_en_default, bool, 0444);
+MODULE_PARM_DESC(rdzv_get_en_default, "Hardware rendezvous get enable default");
+
+#define PE_LE_MAX (C_LPE_STS_LIST_ENTRIES_ENTRIES / C_PE_COUNT)
+
+/* By default, all pools share all LEs. Limits are set via use of a service.
+ * Reduce pe_total_les to limit the number of LEs available.
+ */
+unsigned int pe_total_les = PE_LE_MAX;
+module_param(pe_total_les, uint, 0644);
+MODULE_PARM_DESC(pe_total_les, "Maximum number of LEs accessible to a PE");
+
+static void init_le_pools(struct cass_dev *hw)
+{
+	int pe;
+	int pool;
+	union c_lpe_cfg_pe_le_pools le_pool;
+
+	/* Validate module parameters */
+	if (pe_total_les > PE_LE_MAX) {
+		pe_total_les = PE_LE_MAX;
+		cxidev_warn(&hw->cdev, "Total LEs (%u) exceeded maximum (%u).\n",
+			    pe_total_les, PE_LE_MAX);
+	}
+
+	/* Configure LE Pools */
+	for (pe = 0; pe < C_PE_COUNT; pe++) {
+		union c_lpe_cfg_pe_le_shared le_shared = {
+			.num_total = pe_total_les,
+			.num_shared = pe_total_les,
+		};
+
+		cass_write(hw, C_LPE_CFG_PE_LE_SHARED(pe), &le_shared,
+			   sizeof(le_shared));
+
+		for (pool = 0; pool < CASS_NUM_LE_POOLS; pool++) {
+
+			le_pool.max_alloc = pe_total_les;
+			le_pool.num_reserved = 0;
+			cass_config_lpe_reserve_pool(hw, pe, pool, &le_pool);
+
+			cxidev_dbg(&hw->cdev, "pe: %u pool: %u max: %u res: %u\n",
+				   pe, pool, le_pool.max_alloc,
+				   le_pool.num_reserved);
+		}
+
+		cxidev_dbg(&hw->cdev, "pe: %u total: %u shared: %u\n",
+			   pe, pe_total_les, le_shared.num_shared);
+
+		/* Reliquish the core. This takes a long time on the Z1. */
+		if (HW_PLATFORM_Z1(hw))
+			cond_resched();
+	}
+}
+
+/* Do necessary CSR updates to reserve or release(share) LEs */
+void cass_cfg_le_pools(struct cass_dev *hw, int pool_id, int pe,
+		       const struct cxi_limits *les, bool release)
+{
+	int sign = 1;
+	union c_lpe_cfg_pe_le_shared le_shared;
+	union c_lpe_cfg_pe_le_pools le_pool = {
+		.max_alloc = les->max,
+		.num_reserved = les->res,
+	};
+
+	if (release) {
+		le_pool.max_alloc = les->max;
+		le_pool.num_reserved = 0;
+		sign = -1;
+	}
+
+	cass_read(hw, C_LPE_CFG_PE_LE_SHARED(pe), &le_shared,
+		  sizeof(le_shared));
+	le_shared.num_shared -= (les->res * sign);
+
+	/*
+	 * NUM_SHARED should be reduced before
+	 * dedicating entries to pools.
+	 */
+	if (release) {
+		cass_config_lpe_reserve_pool(hw, pe, pool_id, &le_pool);
+		cass_write(hw, C_LPE_CFG_PE_LE_SHARED(pe), &le_shared,
+			   sizeof(le_shared));
+	} else {
+		cass_write(hw, C_LPE_CFG_PE_LE_SHARED(pe), &le_shared,
+			   sizeof(le_shared));
+		cass_config_lpe_reserve_pool(hw, pe, pool_id, &le_pool);
+	}
+}
+
+void cass_pte_set_get_ctrl(struct cass_dev *hw)
+{
+	union c_lpe_cfg_get_ctrl cfg_get_ctrl = {
+		.transaction_type = TRANSACTION_TYPE,
+		.get_en = !!hw->cdev.prop.rdzv_get_en,
+		.dfa_nid = hw->cdev.prop.nid,
+	};
+
+	cfg_get_ctrl.get_index = cxi_build_dfa_ep(0, hw->cdev.prop.pid_bits,
+						  hw->cdev.prop.rdzv_get_idx);
+	cfg_get_ctrl.get_index_ext =
+		cxi_build_dfa_ext(hw->cdev.prop.rdzv_get_idx);
+
+	cass_write(hw, C_LPE_CFG_GET_CTRL, &cfg_get_ctrl,
+		   sizeof(cfg_get_ctrl));
+}
+
+void cass_pte_init(struct cass_dev *hw)
+{
+	const union c_lpe_cfg_initiator_ctrl cfg_initiator_ctrl = {
+		.pid_bits = hw->cdev.prop.pid_bits,
+	};
+
+	hw->cdev.prop.rdzv_get_idx = RDZV_GET_IDX(hw->cdev.prop.pid_granule);
+
+	/*
+	 * Configure CSRs for HW rendezvous offload. The target NIC will build
+	 * the GET DFA by utilizing the source PID within the initiator field
+	 * from rendezvous command. In order for the target NIC to target the
+	 * correct PtlTE, SW must allocate and map a PtlTE at the max PID offset
+	 * value. For example, if number of PIDs equal 512 (9 bits for PID), 8
+	 * bits remain for PID offset. A rendezvous PtlTE needs to be mapped at
+	 * PID offset 0xFF.
+	 */
+	cass_write(hw, C_LPE_CFG_INITIATOR_CTRL, &cfg_initiator_ctrl,
+		   sizeof(cfg_initiator_ctrl));
+
+	hw->cdev.prop.rdzv_get_en = rdzv_get_en_default;
+	cass_pte_set_get_ctrl(hw);
+
+	init_le_pools(hw);
+}
+
+/* Update an MST return code, and return true if the entry is still
+ * valid.
+ */
+static bool mst_rc_update(struct cass_dev *hw,
+			  const union c_mst_cfg_rc_update *mst_update)
+{
+	const void __iomem *csr = cass_csr(hw, C_MST_STS_RC_STS);
+	union c_mst_sts_rc_sts mst_update_sts;
+	int rc;
+
+	mutex_lock(&hw->mst_update_lock);
+
+	cass_write(hw, C_MST_CFG_RC_UPDATE, mst_update, sizeof(*mst_update));
+
+	/* Wait for MST entry update to complete. */
+	rc = readq_poll_timeout(csr, mst_update_sts.qw,
+				mst_update_sts.done == 1, 1, 1000);
+
+	mutex_unlock(&hw->mst_update_lock);
+
+	cxidev_WARN_ONCE(&hw->cdev, rc, "Timeout waiting for MST RC update");
+
+	return mst_update_sts.done == 1 && mst_update_sts.match == 1;
+}
+
+/*
+ * Clean the entries in the MST table that refer to that PT entry.
+ */
+static void pt_mst_cleanup(struct cxi_pte_priv *pt)
+{
+	struct cxi_dev *cdev = pt->lni_priv->dev;
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	const unsigned int ptlte_index = pt->pte.id;
+	int i;
+	union c_mst_cfg_rc_update cfg_rc_update = {
+		.return_code = C_RC_MST_CANCELLED,
+		.portal_vld = 1,
+		.portal_idx = ptlte_index,
+	};
+	union c_mst_sts_num_req mst_sts;
+
+	if (!HW_PLATFORM_NETSIM(hw))
+		cass_read(hw, C_MST_STS_NUM_REQ, &mst_sts, sizeof(mst_sts));
+	else
+		mst_sts.cnt = C_MST_DBG_MST_TABLE_ENTRIES;
+
+	for (i = 0; i < C_MST_DBG_MST_TABLE_ENTRIES && mst_sts.cnt; i++) {
+		/* Read only the 3rd 64 bits word from the entry, for
+		 * the portal_index field.
+		 */
+
+		/* TODO: (TAG_NO_PTE_0) we need to determine whether
+		 * an MST is valid before accessing it.
+		 * Currently, we rely on the pte index to not be 0.
+		 * This prevents lots on unneeded writes to C_MST_CFG_RC_UPDATE.
+		 */
+		struct c_mst_table_simple mst_entry;
+		u64 offset = C_MST_DBG_MST_TABLE(i) + C_MST_TABLE_SIMPLE_OFFSET;
+
+		cass_read(hw, offset, &mst_entry, sizeof(mst_entry));
+
+		if (mst_entry.portal_index != ptlte_index)
+			continue;
+
+		cfg_rc_update.mst_idx = i;
+
+		if (mst_rc_update(hw, &cfg_rc_update))
+			set_bit(i, pt->mst_rc_update);
+
+		mst_sts.cnt--;
+	}
+
+	cass_flush_pci(hw);
+}
+
+#define PE_FREE_MASK_LEN (C_LPE_STS_PE_FREE_MASK_ENTRIES / C_PE_COUNT)
+
+/*
+ * Set the free bit in the corresponding FREE_MASK CSRs.
+ */
+static void cxi_pte_le_mark_free(struct cass_dev *hw, unsigned int le_idx,
+				 unsigned int pe_num)
+{
+	unsigned int fm_idx;
+	unsigned int fm_bit;
+	u64 offset;
+	union c_lpe_sts_pe_free_mask sts_pe_free_mask;
+
+	fm_idx = le_idx % PE_FREE_MASK_LEN;
+	fm_bit = le_idx / PE_FREE_MASK_LEN;
+	sts_pe_free_mask.free_mask = BIT(fm_bit);
+
+	/* All 4 pools are consecutive in memory, so only use pool0
+	 * for the address computation.
+	 */
+	offset = C_LPE_STS_PE_FREE_MASK(pe_num * PE_FREE_MASK_LEN + fm_idx);
+
+	cass_write(hw, offset, &sts_pe_free_mask, sizeof(sts_pe_free_mask));
+}
+
+/* Walk a PtlTE list, and free the entries. The list must be valid. */
+static void cxi_pte_le_free(struct cass_dev *hw,
+			    const struct c_lpe_cfg_ptl_table_ptrs *list,
+			    unsigned int pe_num, unsigned int le_pool)
+{
+	const union c_lpe_msc_le_pool_free le_pool_free = {
+		.free_en = 1,
+		.le_pool = le_pool,
+	};
+	unsigned int le_idx = list->head;
+
+	/* Walk the list entries marking each one as ready to be freed. */
+	while (true) {
+		/* Read only the 6th 64 bits from the entry. */
+		struct c_list_entry_simple le;
+		u64 offset =
+			C_LPE_STS_LIST_ENTRIES(pe_num * PE_LE_MAX + le_idx) +
+			5 * sizeof(u64);
+
+		cass_read(hw, offset, &le, sizeof(le));
+
+		cxi_pte_le_mark_free(hw, le_idx, pe_num);
+
+		/* Tell NIC an entry was freed */
+		cass_write(hw, C_LPE_MSC_LE_POOL_FREE(pe_num),
+			   &le_pool_free, sizeof(le_pool_free));
+
+		if (le.vld) {
+			le_idx = le.addr;
+		} else {
+			WARN_ON_ONCE(list->tail != le_idx);
+			break;
+		}
+	}
+}
+
+/* Clean up resources associated with the PtlTE. */
+static void pt_cleanup(struct cxi_pte_priv *pt)
+{
+	struct cxi_lni_priv *lni = pt->lni_priv;
+	struct cxi_dev *cdev = lni->dev;
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	union c_lpe_cfg_ptl_table ptl_table;
+	int i;
+
+	/* Cleaning Up Portal Table Entries */
+
+	spin_lock(&hw->lpe_shadow_lock);
+	cass_read_pte(hw, pt->pte.id, &ptl_table);
+	spin_unlock(&hw->lpe_shadow_lock);
+
+	/* Walk the various lists in the PtlTE, free LEs, and
+	 * invalidate the list.
+	 */
+	for (i = 0; i < ARRAY_SIZE(ptl_table.l); i++) {
+		struct c_lpe_cfg_ptl_table_ptrs *list = &ptl_table.l[i];
+
+		if (!list->list_vld)
+			continue;
+
+		cxi_pte_le_free(hw, list, ptl_table.pe_num,
+				ptl_table.le_pool);
+	}
+
+	pt_mst_cleanup(pt);
+
+	/* Clear the entire PTE descriptor including list_vld and list
+	 * pointers.
+	 */
+	memset(&ptl_table, 0, sizeof(ptl_table));
+	cass_write(hw, C_LPE_CFG_PTL_TABLE(pt->pte.id),
+		   &ptl_table, sizeof(ptl_table));
+
+	cass_flush_pci(hw);
+}
+
+static struct cxi_pte *cxi_pte_alloc_vf(struct cxi_lni *lni,
+					struct cxi_eq *evtq,
+					const struct cxi_pt_alloc_opts *opts)
+{
+	struct cxi_lni_priv *lni_priv =
+		container_of(lni, struct cxi_lni_priv, lni);
+	const struct cxi_pte_alloc_cmd cmd = {
+		.op = CXI_OP_PTE_ALLOC,
+		.lni_hndl = lni_priv->lni.id,
+		.evtq_hndl = evtq ? evtq->eqn : C_EQ_NONE,
+		.opts = *opts,
+	};
+	struct cxi_pte_alloc_resp resp = {};
+	size_t resp_size = sizeof(resp);
+	int rc;
+	struct cxi_pte_priv *pt_priv;
+
+	pt_priv = kzalloc(sizeof(*pt_priv), GFP_KERNEL);
+	if (!pt_priv)
+		return ERR_PTR(-ENOMEM);
+
+	rc = cxi_send_msg_to_pf(lni_priv->dev, &cmd, sizeof(cmd),
+				&resp, &resp_size);
+	if (rc)
+		goto free_pt;
+
+	pt_priv->lni_priv = lni_priv;
+	pt_priv->pte.id = resp.pte_number;
+
+	if (evtq)
+		pt_priv->eq = container_of(evtq, struct cxi_eq_priv, eq);
+	else
+		pt_priv->eq = NULL;
+
+	return &pt_priv->pte;
+
+free_pt:
+	kfree(pt_priv);
+	return ERR_PTR(rc);
+}
+
+/**
+ * cxi_pte_alloc() - Allocate a portal table entry (PTE)
+ *
+ * @lni: LNI used for PTE allocation
+ * @evtq: Event Queue to associate with the PTE
+ * @opts: Options affecting the PTE
+ *
+ * @return: the PTE or an error pointer
+ */
+struct cxi_pte *cxi_pte_alloc(struct cxi_lni *lni, struct cxi_eq *evtq,
+			      const struct cxi_pt_alloc_opts *opts)
+{
+	struct cxi_lni_priv *lni_priv =
+		container_of(lni, struct cxi_lni_priv, lni);
+	struct cxi_dev *cdev = lni_priv->dev;
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	struct cxi_pte_priv *pt;
+	struct cxi_eq_priv *eq = NULL;
+	int pt_n;
+	int rc;
+	union c_lpe_cfg_ptl_table ptl_table = {
+		.en_event_match = opts->en_event_match,
+		.clr_remote_offset = opts->clr_remote_offset,
+		.en_flowctrl = opts->en_flowctrl,
+		.use_long_event = opts->use_long_event,
+		.lossless = opts->lossless,
+		.en_restricted_unicast_lm = opts->en_restricted_unicast_lm,
+		.use_logical = opts->use_logical,
+		.is_matching = opts->is_matching,
+		.en_match_on_vni = opts->en_match_on_vni,
+		.do_space_check = opts->do_space_check,
+		.en_align_lm = opts->en_align_lm,
+		.en_sw_hw_st_chng = opts->en_sw_hw_st_chng,
+		.ptl_state = opts->ethernet ?
+			C_PTLTE_ETHERNET : C_PTLTE_DISABLED,
+		.signal_invalid = opts->signal_invalid,
+		.signal_underflow = opts->signal_underflow,
+		.signal_overflow = opts->signal_overflow,
+		.signal_inexact = opts->signal_inexact,
+	};
+	bool pt_reuse = false;
+	int count;
+
+	if (!cdev->is_physfn)
+		return cxi_pte_alloc_vf(lni, evtq, opts);
+
+	if (opts->ethernet && !capable(CAP_NET_RAW))
+		return ERR_PTR(-EPERM);
+
+	if (evtq)
+		eq = container_of(evtq, struct cxi_eq_priv, eq);
+
+	/* Prefer a PTE already allocated to this LNI */
+	spin_lock(&lni_priv->res_lock);
+	pt = list_first_entry_or_null(&lni_priv->pt_cleanups_list,
+				      struct cxi_pte_priv, list);
+	if (pt) {
+		list_del(&pt->list);
+		spin_unlock(&lni_priv->res_lock);
+
+		pt_reuse = true;
+		pt_n = pt->pte.id;
+	} else {
+		spin_unlock(&lni_priv->res_lock);
+
+		pt = kzalloc(sizeof(*pt), GFP_KERNEL);
+		if (pt == NULL)
+			return ERR_PTR(-ENOMEM);
+
+		/* Check the associated service to see if this PTE can be
+		 * allocated
+		 */
+		rc = cxi_rgroup_alloc_resource(lni_priv->rgroup,
+					       CXI_RESOURCE_PTLTE);
+		if (rc)
+			goto pt_free;
+
+		/* TODO: Don't allocate PTE 0 until we can determine whether
+		 * an MST entry is valid. See tag TAG_NO_PTE_0 in this file.
+		 */
+		pt_n = ida_alloc_range(&hw->pte_table, 1,
+				       C_LPE_CFG_PTL_TABLE_ENTRIES - 1, GFP_KERNEL);
+		if (pt_n < 0) {
+			rc = pt_n;
+			goto dec_rsrc_use;
+		}
+	}
+
+	pt->lni_priv = lni_priv;
+	pt->eq = eq;
+	pt->pte.id = pt_n;
+	pt->mcast_n = -1;
+	refcount_set(&pt->refcount, 1);
+	bitmap_zero(pt->mst_rc_update, C_MST_DBG_MST_TABLE_ENTRIES);
+
+	if (!ptl_table.is_matching && ptl_table.ptl_state != C_PTLTE_ETHERNET &&
+	    !ptl_table.do_space_check) {
+		ptl_table.do_space_check = true;
+
+		while (true) {
+			count = atomic_read(&hw->plec_count);
+			if (count >= PLEC_SIZE) {
+				cxidev_dbg(cdev, "plec full\n");
+				break;
+			}
+
+			rc = atomic_cmpxchg(&hw->plec_count, count, count + 1);
+			if (rc == count) {
+				pt->plec_enabled = true;
+				ptl_table.do_space_check = false;
+				break;
+			}
+		}
+	}
+
+	/* TODO: Have separate EQs for no rendezvous get events. */
+	if (eq) {
+		ptl_table.eq_handle = eq->eq.eqn;
+		ptl_table.eq_handle_no_rget = eq->eq.eqn;
+	} else {
+		ptl_table.eq_handle = C_EQ_NONE;
+		ptl_table.eq_handle_no_rget = C_EQ_NONE;
+	}
+
+	cass_assign_ptlte_to_rgid(hw, pt->pte.id, lni_priv->lni.rgid);
+
+	ptl_table.pe_num = cxi_lni_get_pe_num(lni_priv);
+	pt->pe_num = ptl_table.pe_num;
+	ptl_table.le_pool = pt->le_pool =
+		cxi_rgroup_le_pool_id(pt->lni_priv->rgroup, pt->pe_num);
+
+	spin_lock(&hw->lpe_shadow_lock);
+	cass_config_pte(hw, pt_n, &ptl_table);
+	spin_unlock(&hw->lpe_shadow_lock);
+
+	spin_lock(&lni_priv->res_lock);
+	list_add_tail(&pt->list, &lni_priv->pt_list);
+	spin_unlock(&lni_priv->res_lock);
+
+	if (!pt_reuse) {
+		atomic_inc(&hw->stats.pt);
+
+		pt_debugfs_create(pt->pte.id, pt, hw, lni_priv);
+		refcount_inc(&lni_priv->refcount);
+	}
+
+	if (eq)
+		refcount_inc(&eq->refcount);
+
+	cass_flush_pci(hw);
+
+	return &pt->pte;
+
+dec_rsrc_use:
+	if (!pt_reuse)
+		cxi_rgroup_free_resource(lni_priv->rgroup, CXI_RESOURCE_PTLTE);
+pt_free:
+	if (pt_reuse) {
+		spin_lock(&lni_priv->res_lock);
+		list_add_tail(&pt->list, &lni_priv->pt_cleanups_list);
+		spin_unlock(&lni_priv->res_lock);
+	} else {
+		kfree(pt);
+	}
+
+	return ERR_PTR(rc);
+}
+EXPORT_SYMBOL(cxi_pte_alloc);
+
+static void cxi_pte_free_vf(struct cxi_pte *pt)
+{
+	struct cxi_pte_priv *pt_priv =
+		container_of(pt, struct cxi_pte_priv, pte);
+	struct cxi_lni_priv *lni_priv = pt_priv->lni_priv;
+	struct cxi_dev *cdev = lni_priv->dev;
+	const struct cxi_pte_free_cmd cmd = {
+		.op = CXI_OP_PTE_FREE,
+		.pte_number = pt_priv->pte.id,
+	};
+	int rc;
+	size_t resp_len = 0;
+
+	rc = cxi_send_msg_to_pf(cdev, &cmd, sizeof(cmd), NULL, &resp_len);
+	if (rc)
+		cxidev_err(cdev, "Failed to free PTE %u on PF: %d\n",
+			   pt_priv->pte.id, rc);
+
+	kfree(pt_priv);
+}
+
+/**
+ * cxi_pte_free() - Release a portal table entry
+ *
+ * @pt: the portal table entry
+ */
+void cxi_pte_free(struct cxi_pte *pt)
+{
+	struct cxi_pte_priv *pt_priv =
+		container_of(pt, struct cxi_pte_priv, pte);
+	struct cxi_lni_priv *lni_priv = pt_priv->lni_priv;
+	struct cxi_dev *cdev = lni_priv->dev;
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	const u64 ptl_state = C_PTLTE_RESET;
+	u64 before;
+	u64 after;
+
+	if (!cdev->is_physfn) {
+		cxi_pte_free_vf(pt);
+		return;
+	}
+
+	cxidev_WARN_ONCE(cdev, !refcount_dec_and_test(&pt_priv->refcount),
+			 "Resource leaks - PT refcount not zero: %d\n",
+			 refcount_read(&pt_priv->refcount));
+
+	cass_assign_ptlte_to_rgid(hw, pt_priv->pte.id, C_RESERVED_RGID);
+
+	/* Set the PtlTE to the Reset state. Only write the last
+	 * 64-bits word, at offset 0x18, as to not overwrite the list
+	 * pointers.
+	 * Repeat as long as PLEC_FREES_CSR increases (Cassini ERRATA-4383).
+	 */
+	do {
+		static const unsigned int offset =
+			offsetof(struct c_lpe_cntrs_group, lpe.plec_frees_csr) /
+			sizeof(u64);
+
+		cass_read(hw, C_LPE_STS_EVENT_CNTS(offset), &before, sizeof(before));
+
+		cass_write(hw, C_LPE_CFG_PTL_TABLE(pt_priv->pte.id) + 0x18,
+			   &ptl_state, sizeof(ptl_state));
+
+		cass_read(hw, C_LPE_STS_EVENT_CNTS(offset), &after, sizeof(after));
+	} while (before != after);
+
+	pt_cleanup(pt_priv);
+
+	if (pt_priv->eq) {
+		refcount_dec(&pt_priv->eq->refcount);
+		pt_priv->eq = NULL;
+	}
+
+	if (pt_priv->plec_enabled) {
+		atomic_dec(&hw->plec_count);
+		pt_priv->plec_enabled = false;
+	}
+
+	spin_lock(&lni_priv->res_lock);
+	list_del(&pt_priv->list);
+	list_add_tail(&pt_priv->list, &lni_priv->pt_cleanups_list);
+	spin_unlock(&lni_priv->res_lock);
+}
+EXPORT_SYMBOL(cxi_pte_free);
+
+/* Check whether an MST entry is valid */
+static bool is_mst_valid(struct cass_dev *hw, unsigned int mst)
+{
+	union c_mst_dbg_match_done match_done = {
+		.mst_idx = mst,
+	};
+
+	spin_lock(&hw->mst_match_done_lock);
+	cass_write(hw, C_MST_DBG_MATCH_DONE, &match_done, sizeof(match_done));
+	cass_read(hw, C_MST_DBG_MATCH_DONE, &match_done, sizeof(match_done));
+	spin_unlock(&hw->mst_match_done_lock);
+
+	return match_done.mst_idx_st == 1;
+}
+
+/* Go through each MST that where the return_code was updated, and
+ * check whether they are now not valid or reused.
+ */
+static bool is_pt_done(struct cass_dev *hw, struct cxi_pte_priv *pt)
+{
+	union c_mst_cfg_rc_update cfg_rc_update = {
+		.return_code = C_RC_MST_CANCELLED,
+		.portal_vld = 1,
+		.portal_idx = pt->pte.id,
+	};
+	unsigned int mst;
+
+	for_each_set_bit(mst, pt->mst_rc_update, C_MST_DBG_MST_TABLE_ENTRIES) {
+		if (is_mst_valid(hw, mst)) {
+			/* MST entry is still valid, but it may have
+			 * been reused for another portal entry.
+			 */
+			cfg_rc_update.mst_idx = mst;
+			if (mst_rc_update(hw, &cfg_rc_update))
+				return false;
+		}
+
+		clear_bit(mst, pt->mst_rc_update);
+	}
+
+	return true;
+}
+
+/* When the LNI closes, the PTEs are ready to be cleaned up and
+ * released.
+ */
+void finalize_pt_cleanups(struct cxi_lni_priv *lni, bool force)
+{
+	struct cxi_dev *cdev = lni->dev;
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	struct cxi_pte_priv *pt;
+	struct cxi_pte_priv *tmp;
+
+	list_for_each_entry_safe(pt, tmp, &lni->pt_cleanups_list, list) {
+		if (!force && !is_pt_done(hw, pt))
+			continue;
+
+		list_del(&pt->list);
+
+		debugfs_remove(pt->lni_dir);
+		debugfs_remove_recursive(pt->debug_dir);
+
+		refcount_dec(&lni->refcount);
+		atomic_dec(&hw->stats.pt);
+		cxi_rgroup_free_resource(lni->rgroup, CXI_RESOURCE_PTLTE);
+		ida_free(&hw->pte_table, pt->pte.id);
+		kfree(pt);
+	}
+}
+
+static int cxi_pte_map_vf(struct cxi_pte *pt, struct cxi_domain *domain,
+			  unsigned int pid_offset, bool is_multicast,
+			  unsigned int *pt_index)
+{
+	struct cxi_pte_priv *pt_priv =
+		container_of(pt, struct cxi_pte_priv, pte);
+	struct cxi_lni_priv *lni_priv = pt_priv->lni_priv;
+	struct cxi_dev *cdev = lni_priv->dev;
+	struct cxi_pte_map_cmd cmd = {
+		.op = CXI_OP_PTE_MAP,
+		.pte_number = pt->id,
+		.domain_hndl = domain->id,
+		.pid_offset = pid_offset,
+		.is_multicast = is_multicast,
+	};
+	struct cxi_pte_map_resp resp = {};
+	size_t resp_size = sizeof(resp);
+	int rc;
+
+	rc = cxi_send_msg_to_pf(cdev, &cmd, sizeof(cmd),
+				&resp, &resp_size);
+	if (rc)
+		return rc;
+
+	*pt_index = resp.pte_index;
+
+	return 0;
+}
+
+/**
+ * cxi_pte_map() - Map a portal entry to a portal index entry
+ *
+ * A portal entry can be mapped several times to a portal index entry.
+ *
+ * @pt: the portal entry
+ * @domain: the domain
+ * @pid_offset: offset of the portal in the domain's PID slice for
+ *   unicast, or the (union cxi_pte_map_offset) uintval field for multicast.
+ * @is_multicast: whether the address is multicast
+ * @pt_index: the allocated portal index entry, to be passed when
+ *   unmapping.
+ *
+ * @return: 0 on success or a negative errno
+ */
+int cxi_pte_map(struct cxi_pte *pt, struct cxi_domain *domain,
+		unsigned int pid_offset, bool is_multicast,
+		unsigned int *pt_index)
+{
+	struct cxi_pte_priv *pt_priv =
+			container_of(pt, struct cxi_pte_priv, pte);
+	struct cxi_domain_priv *domain_priv =
+			container_of(domain, struct cxi_domain_priv, domain);
+	struct cxi_dev *cdev = pt_priv->lni_priv->dev;
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	unsigned int ptl_idx;
+	unsigned int index_ext;
+	union c_rmu_cfg_portal_list rmu_cfg_portal_list = {};
+	int mcast_n;
+	int pti_n;
+	int ret;
+
+	if (!cdev->is_physfn)
+		return cxi_pte_map_vf(pt, domain, pid_offset,
+				      is_multicast, pt_index);
+
+	/* Sanity checks */
+	if (domain_priv->lni_priv != pt_priv->lni_priv)
+		return -EINVAL;
+
+	/* Generate ptl_idx and index_ext */
+	if (is_multicast) {
+		union cxi_pte_map_offset map_offset;
+
+		if (pid_offset >= (1 << (C_DFA_MULTICAST_ID_BITS +
+					 C_DFA_INDEX_EXT_BITS)))
+			return -EINVAL;
+
+		if (pt_priv->mcast_n != -1)
+			return -EINVAL;
+
+		/* structure maps directly to RMU fields.
+		 * | vni | ... | 1:1 | pad:2 | ptl_idx:13    | index_ext:5  |
+		 */
+		map_offset.uintval = pid_offset;
+		ptl_idx = map_offset.mcast_id;
+		index_ext = map_offset.mcast_pte_index;
+	} else {
+		/* pid_offset does not map directly to RMU fields.
+		 * | vni | ... | 0:1 | pad:3 | pid:9      |    pid_offset:8 |
+		 * | vni | ... | 0:1 | pad:3 | ptl_idx:12    | index_ext:5  |
+		 */
+		if (pid_offset >= cdev->prop.pid_granule)
+			return -EINVAL;
+		ptl_idx = cxi_build_dfa_ep(domain->pid, cdev->prop.pid_bits,
+					   pid_offset);
+		index_ext = cxi_build_dfa_ext(pid_offset);
+		if (ptl_idx >= (1 << C_DFA_ENDPOINT_DEFINED_BITS))
+			return -EINVAL;
+	}
+
+	/* Acquire an unused RMU_CFG_PORTAL_LIST slot */
+	pti_n = ida_alloc_max(&hw->pt_index_table, C_RMU_CFG_PORTAL_LIST_ENTRIES - 1,
+			      GFP_KERNEL);
+	if (pti_n < 0)
+		return pti_n;
+
+	if (is_multicast) {
+		/* Prevent re-issue of this mcast_id/index_ext pair */
+		mcast_n = ida_alloc_range(&hw->multicast_table,
+					  pid_offset, pid_offset, GFP_KERNEL);
+		if (mcast_n < 0) {
+			ret = mcast_n;
+			goto rls_pti_n;
+		}
+		pt_priv->mcast_n = mcast_n;
+	}
+
+	refcount_inc(&domain_priv->refcount);
+	refcount_inc(&pt_priv->refcount);
+
+	rmu_cfg_portal_list.index_ext = index_ext;
+	rmu_cfg_portal_list.multicast_id = ptl_idx;
+	rmu_cfg_portal_list.is_multicast = is_multicast;
+	rmu_cfg_portal_list.vni_list_idx =
+				domain_priv->rx_profile->config.rmu_index;
+
+	spin_lock(&hw->rmu_portal_list_lock);
+	cass_config_portal_list(hw, pti_n, pt_priv->pte.id,
+				&rmu_cfg_portal_list);
+	spin_unlock(&hw->rmu_portal_list_lock);
+
+	*pt_index = pti_n;
+
+	return 0;
+rls_pti_n:
+	ida_free(&hw->pt_index_table, pti_n);
+	return ret;
+}
+EXPORT_SYMBOL(cxi_pte_map);
+
+static int cxi_pte_unmap_vf(struct cxi_pte *pt, struct cxi_domain *domain,
+			    int pt_index)
+{
+	struct cxi_pte_priv *pt_priv =
+		container_of(pt, struct cxi_pte_priv, pte);
+	struct cxi_lni_priv *lni_priv = pt_priv->lni_priv;
+	struct cxi_dev *cdev = lni_priv->dev;
+	struct cxi_pte_unmap_cmd cmd = {
+		.op = CXI_OP_PTE_UNMAP,
+		.pte_index = pt_index,
+	};
+	int rc;
+	size_t resp_len = 0;
+
+	rc = cxi_send_msg_to_pf(cdev, &cmd, sizeof(cmd), NULL, &resp_len);
+	if (rc)
+		return rc;
+
+	return 0;
+}
+
+/**
+ * cxi_pte_unmap() - Unmap a portal entry from the index table
+ *
+ * @pt: the portal table entry
+ * @domain: the domain to use
+ * @pt_index: the portal entry index returned by cxi_pte_map()
+ */
+int cxi_pte_unmap(struct cxi_pte *pt, struct cxi_domain *domain, int pt_index)
+{
+	struct cxi_pte_priv *pt_priv =
+			container_of(pt, struct cxi_pte_priv, pte);
+	struct cxi_domain_priv *domain_priv =
+			container_of(domain, struct cxi_domain_priv, domain);
+	struct cxi_dev *cdev = domain_priv->lni_priv->dev;
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+
+	if (!cdev->is_physfn)
+		return cxi_pte_unmap_vf(pt, domain, pt_index);
+
+	cass_invalidate_portal_list(hw, pt_index);
+
+	/* If this was a multicast, release the ID and free the memory */
+	if (pt_priv->mcast_n != -1) {
+		ida_free(&hw->multicast_table, pt_priv->mcast_n);
+		pt_priv->mcast_n = -1;
+	}
+
+	/* Release the pte index value */
+	ida_free(&hw->pt_index_table, pt_index);
+
+	refcount_dec(&pt_priv->refcount);
+	refcount_dec(&domain_priv->refcount);
+
+	return 0;
+}
+EXPORT_SYMBOL(cxi_pte_unmap);
+
+static void cxi_pte_le_invalidate_vf(struct cxi_pte *pt,
+				     unsigned int buffer_id,
+				     enum c_ptl_list list)
+{
+	struct cxi_pte_priv *pt_priv =
+		container_of(pt, struct cxi_pte_priv, pte);
+	struct cxi_lni_priv *lni_priv = pt_priv->lni_priv;
+	struct cxi_dev *cdev = lni_priv->dev;
+	struct cxi_pte_le_invalidate_cmd cmd = {
+		.op = CXI_OP_PTE_LE_INVALIDATE,
+		.pte_index = pt->id,
+		.buffer_id = buffer_id,
+		.list = list,
+	};
+	int rc;
+	size_t resp_len = 0;
+
+	rc = cxi_send_msg_to_pf(cdev, &cmd, sizeof(cmd), NULL, &resp_len);
+	if (rc)
+		cxidev_err(cdev, "Failed to invalidate LE on PTE %u on PF: %d\n",
+			   pt_priv->pte.id, rc);
+}
+
+/**
+ * cxi_pte_le_invalidate() - Invalidate a non-locally managed persistent LE.
+ * @pt: Portal table entry.
+ * @buffer_id: Buffer ID used to identify the LE.
+ * @list: Portal list the LE was appended to.
+ *
+ * Non-locally managed persistent LE invalidation is required due to the LE
+ * unlink not cleaning up all resources.
+ *
+ * If the LE has success and communication events enabled, the PtlTE EQ should
+ * be drained to ensure that no outstanding events exist on the EQ using this
+ * buffer ID, PtlTE, and Ptl list (assuming the PtlTE was configured with an
+ * EQ).
+ *
+ * If a user has enabled matching events for the PtlTE and is correctly counting
+ * the number of match events and target DMA operation events
+ * (Put, Get, etc...), persistent LE invalidation does not need to occur.
+ *
+ * Note: If the PtlTE is configured with a EQ, target DMA operation events may
+ * complete with a RC of C_RC_MST_CANCELLED. These target events should be
+ * ignored by the user.
+ */
+void cxi_pte_le_invalidate(struct cxi_pte *pt, unsigned int buffer_id,
+			   enum c_ptl_list list)
+{
+	struct cxi_pte_priv *pt_priv =
+		container_of(pt, struct cxi_pte_priv, pte);
+	struct cxi_dev *cdev = pt_priv->lni_priv->dev;
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	union c_mst_dbg_mst_table *mst_entry = hw->mst_entries;
+	union c_mst_cfg_rc_update mst_update = {
+		.return_code = C_RC_MST_CANCELLED,
+		.buffer_idx = buffer_id,
+		.portal_idx = pt->id,
+		.ptl_list = list,
+		.ptl_vld = 1,
+		.portal_vld = 1,
+		.buffer_vld = 1,
+	};
+	int i;
+	int rc;
+
+	if (!cdev->is_physfn) {
+		cxi_pte_le_invalidate_vf(pt, buffer_id, list);
+		return;
+	}
+
+	mutex_lock(&hw->mst_table_lock);
+
+	rc = cxi_dmac_xfer(cdev, hw->dmac_pt_id);
+	if (cxidev_WARN_ONCE(cdev, rc, "Unable to get MST table: %d\n", rc)) {
+		mutex_unlock(&hw->mst_table_lock);
+		return;
+	}
+
+	/* Walk all the MST entries cleaning up matching entries. */
+	for (i = 0; i < C_MST_DBG_MST_TABLE_ENTRIES; i++, mst_entry++) {
+		if (mst_entry->portal_index == pt->id &&
+		    mst_entry->ptl_list == list &&
+		    mst_entry->buffer_id == buffer_id) {
+			/* Issue a MST RC update to the NIC. */
+			mst_update.mst_idx = i;
+
+			mst_rc_update(hw, &mst_update);
+		}
+	}
+
+	mutex_unlock(&hw->mst_table_lock);
+}
+EXPORT_SYMBOL(cxi_pte_le_invalidate);
+
+static int cxi_pte_status_vf(struct cxi_pte *pt,
+			     struct cxi_pte_status *status)
+{
+	struct cxi_pte_priv *pt_priv =
+		container_of(pt, struct cxi_pte_priv, pte);
+	struct cxi_lni_priv *lni_priv = pt_priv->lni_priv;
+	struct cxi_dev *cdev = lni_priv->dev;
+	struct cxi_pte_status_cmd cmd = {
+		.op = CXI_OP_PTE_STATUS,
+		.pte_index = pt->id,
+	};
+	struct cxi_pte_status_resp resp = {};
+	size_t resp_size = sizeof(resp);
+	int rc;
+
+	rc = cxi_send_msg_to_pf(cdev, &cmd, sizeof(cmd), &resp, &resp_size);
+	if (rc)
+		return rc;
+
+	*status = resp.status;
+	return 0;
+}
+
+#define ULE_START_OFFSET 24
+
+/**
+ * cxi_pte_status() - Return collection of PTE stats
+ *
+ * @pt: Portal table entry.
+ * @status: Pointer to struct where PTE stats will be written
+ *
+ * status->ule_offsets and status->ule_count are used as inputs. ule_offsets
+ * is an array where ULE information is stored on output. ule_count is the
+ * size in entries of ule_offsets.
+ *
+ * If ule_offsets is set, the PTE unexpected list is walked. The remote
+ * offset field of each ULE is written into ule_offsets (if space is
+ * available). The total number of ULEs found is returned in ule_count. If
+ * ule_offsets is unset, the Unexpected list walk is skipped. This interface
+ * is used to query ULE remote offset information needed for Rendezvous Puts
+ * that are dequeued using a SearchAndDelete command.
+ */
+int cxi_pte_status(struct cxi_pte *pt, struct cxi_pte_status *status)
+{
+	struct cxi_pte_priv *pt_priv =
+		container_of(pt, struct cxi_pte_priv, pte);
+	struct cxi_dev *cdev = pt_priv->lni_priv->dev;
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	union c_lpe_cfg_ptl_table ptl_table;
+	struct c_lpe_cfg_ptl_table_ptrs ule_list;
+	union c_lpe_cfg_pe_le_pools le_pool;
+	union c_lpe_sts_pe_le_alloc le_alloc;
+	size_t ule_count = 0;
+	unsigned int idx;
+
+	if (!cdev->is_physfn)
+		return cxi_pte_status_vf(pt, status);
+
+	spin_lock(&hw->lpe_shadow_lock);
+	cass_read_pte(hw, pt_priv->pte.id, &ptl_table);
+	spin_unlock(&hw->lpe_shadow_lock);
+
+	idx = (pt_priv->pe_num * 16) + pt_priv->le_pool;
+
+	cass_read(hw, C_LPE_CFG_PE_LE_POOLS(idx), &le_pool,
+		  sizeof(le_pool));
+	cass_read(hw, C_LPE_STS_PE_LE_ALLOC(idx), &le_alloc,
+		  sizeof(le_alloc));
+
+	status->drop_count = ptl_table.drop_count;
+	status->state = ptl_table.ptl_state;
+	status->les_reserved = le_pool.num_reserved;
+	status->les_max = le_pool.max_alloc;
+	status->les_allocated = le_alloc.num_allocated;
+	ule_list = ptl_table.l[C_PTL_LIST_UNEXPECTED];
+
+	if (status->ule_offsets && ule_list.list_vld) {
+		unsigned int le_idx = ule_list.head;
+		u64 ule_offset;
+		struct c_ule_entry ule;
+		void *ule_ptr = (void *)&ule + ULE_START_OFFSET;
+
+		if (!user_access_begin(status->ule_offsets,
+				       status->ule_count * sizeof(u64)))
+			return -EFAULT;
+
+		while (true) {
+			/* Read only the last 3 QWs of the ULE */
+			ule_offset = C_LPE_STS_LIST_ENTRIES(pt_priv->pe_num *
+							    PE_LE_MAX +
+							    le_idx) +
+					ULE_START_OFFSET;
+			cass_read(hw, ule_offset, ule_ptr,
+				  sizeof(ule) - ULE_START_OFFSET);
+
+			if (ule_count < status->ule_count) {
+				u64 offset = ule.start_or_offset;
+
+				unsafe_put_user(offset,
+						&status->ule_offsets[ule_count],
+						err_put_user);
+			}
+			ule_count++;
+
+			if (ule.vld) {
+				le_idx = ule.addr;
+			} else {
+				WARN_ON_ONCE(ule_list.tail != le_idx);
+				break;
+			}
+		}
+
+		user_access_end();
+	}
+
+	/* Return the real number of ULEs */
+	status->ule_count = ule_count;
+
+	return 0;
+
+err_put_user:
+	user_access_end();
+
+	return -EFAULT;
+}
+EXPORT_SYMBOL(cxi_pte_status);
+
+/**
+ * cxi_pte_transition_sm() - Transition a disabled PTE to software managed.
+ *
+ * @pt: Portal table entry.
+ * @drop_count: Expected drop_count
+ *
+ * If the PTE is in the disable state, and its drop_count matches,
+ * this will transition it into the software managed state. The
+ * drop_count is reset to 0.
+ *
+ * Returns -EINVAL if the PTE is not disabled, -ETIMEDOUT if the
+ * hardware has issues, -EAGAIN if the drop_count doesn't match, or 0 on
+ * success.
+ */
+int cxi_pte_transition_sm(struct cxi_pte *pt, unsigned int drop_count)
+{
+	struct cxi_pte_priv *pt_priv = container_of(pt, struct cxi_pte_priv, pte);
+	struct cxi_dev *cdev = pt_priv->lni_priv->dev;
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	union c_lpe_sts_cdts_in_use cdts_in_use_mask = {
+		.event_cdts_in_use = ~0,
+		.ixe_mst_cdts_in_use = ~0,
+		.ixe_get_cdts_in_use = ~0,
+		.ixe_put_cdts_in_use = ~0,
+	};
+	union c_lpe_sts_cdts_in_use cdts_in_use;
+	union c_lpe_cfg_cdt_limits cdt_limits;
+	union c_lpe_cfg_ptl_table ptl_table;
+	u8 old_rrq_cdts;
+	int count;
+	int ret;
+
+	if (!cdev->is_physfn)
+		return -EOPNOTSUPP;
+
+	spin_lock(&hw->lpe_shadow_lock);
+	cass_read_pte(hw, pt_priv->pte.id, &ptl_table);
+	spin_unlock(&hw->lpe_shadow_lock);
+
+	if (ptl_table.ptl_state == C_PTLTE_SOFTWARE_MANAGED)
+		return 0;
+
+	if (ptl_table.ptl_state != C_PTLTE_DISABLED)
+		return -EINVAL;
+
+	mutex_lock(&hw->pte_transition_sm_lock);
+
+	/* Stop all LPE requests arbitration before the point where
+	 * the PtlTE RAM is read.
+	 */
+	cass_read(hw, C_LPE_CFG_CDT_LIMITS, &cdt_limits, sizeof(cdt_limits));
+	old_rrq_cdts = cdt_limits.rrq_cdts;
+	cdt_limits.rrq_cdts = 0;
+	cass_write(hw, C_LPE_CFG_CDT_LIMITS, &cdt_limits, sizeof(cdt_limits));
+
+	/* Read stats until load and max are 0 */
+	count = 0;
+	do {
+		static union c_lpe_msc_load_stats_doorbell doorbell = {
+			.doorbell = 1,
+		};
+		union c_lpe_sts_load_stats stats;
+
+		cass_write(hw, C_LPE_MSC_LOAD_STATS_DOORBELL,
+			   &doorbell, sizeof(doorbell));
+
+		cass_read(hw, C_LPE_STS_LOAD_STATS(ptl_table.pe_num),
+			  &stats, sizeof(stats));
+
+		if (stats.max == 0 && stats.load == 0)
+			break;
+
+		count++;
+		if (count >= 250) {
+			ret = -ETIMEDOUT;
+			goto out;
+		}
+
+		usleep_range(5000, 10000);
+	} while (true);
+
+	/* Add the matching PE*_RRQ_CDTS_IN_USE to the mask */
+	switch (ptl_table.pe_num) {
+	case 0:
+		cdts_in_use_mask.pe0_rrq_cdts_in_use = ~0;
+		break;
+	case 1:
+		cdts_in_use_mask.pe1_rrq_cdts_in_use = ~0;
+		break;
+	case 2:
+		cdts_in_use_mask.pe2_rrq_cdts_in_use = ~0;
+		break;
+	case 3:
+		cdts_in_use_mask.pe3_rrq_cdts_in_use = ~0;
+		break;
+	}
+
+	/* Poll until selected fields in C_LPE_STS_CDTS_IN_USE are all
+	 * zeroes.
+	 */
+	ret = readq_poll_timeout(cass_csr(hw, C_LPE_STS_CDTS_IN_USE),
+				 cdts_in_use.qw,
+				 (cdts_in_use.qw & cdts_in_use_mask.qw) == 0,
+				 1, 1000000);
+	if (ret)
+		goto out;
+
+	/* Read the state again since the PE is now quiesced. */
+	spin_lock(&hw->lpe_shadow_lock);
+	cass_read_pte(hw, pt_priv->pte.id, &ptl_table);
+	spin_unlock(&hw->lpe_shadow_lock);
+
+	if (ptl_table.ptl_state == C_PTLTE_SOFTWARE_MANAGED) {
+		ret = 0;
+	} else if (ptl_table.ptl_state != C_PTLTE_DISABLED) {
+		ret = -EINVAL;
+	} else if (drop_count == ptl_table.drop_count) {
+		/* Change the state and drop count. Only write a
+		 * single u64 at offset 0x18, as to not overwrite
+		 * other fields.
+		 */
+		u64 *state_dc = ((u64 *)&ptl_table) + 3;
+
+		ptl_table.ptl_state = C_PTLTE_SOFTWARE_MANAGED;
+		ptl_table.drop_count = 0;
+		cass_write(hw, C_LPE_CFG_PTL_TABLE(pt_priv->pte.id) + 0x18,
+			   state_dc, sizeof(u64));
+
+		ret = 0;
+	} else {
+		ret = -EAGAIN;
+	}
+
+out:
+	cdt_limits.rrq_cdts = old_rrq_cdts;
+	cass_write(hw, C_LPE_CFG_CDT_LIMITS, &cdt_limits, sizeof(cdt_limits));
+
+	mutex_unlock(&hw->pte_transition_sm_lock);
+
+	return ret;
+}
+EXPORT_SYMBOL(cxi_pte_transition_sm);
diff --git a/drivers/net/ethernet/hpe/ss1/cass_ptp.c b/drivers/net/ethernet/hpe/ss1/cass_ptp.c
new file mode 100644
index 000000000000..33afbb064475
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_ptp.c
@@ -0,0 +1,304 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2019 Hewlett Packard Enterprise Development LP */
+
+/* Cassini Precision Time Protocol support */
+
+#include <linux/ptp_clock_kernel.h>
+
+#include "cass_core.h"
+
+#define RTC_NS_WIDTH 30
+#define RTC_MAX_ADJ (RTC_NS_WIDTH / 2)
+#define RTC_FNS_WIDTH 32
+#define RTC_MAX_FNS (1ULL << RTC_FNS_WIDTH)
+
+static void write_rtc(struct cass_dev *hw, const struct timespec64 *ts)
+{
+	union c_mb_cfg_rtc_time rtc;
+	const union c_mb_cfg_rtc rtc_cfg = {
+		.rtc_load = 1,
+		.rtc_enable = 1,
+		.etc_enable = 1,
+	};
+
+	rtc.seconds_47_34 = ts->tv_sec >> 34;
+	rtc.seconds_33_0 = ts->tv_sec & (BIT(34) - 1);
+	rtc.nanoseconds = ts->tv_nsec;
+
+	cass_write(hw, C_MB_CFG_RTC_TIME, &rtc, C_MB_CFG_RTC_TIME_SIZE);
+	cass_write(hw, C_MB_CFG_RTC, &rtc_cfg, sizeof(rtc_cfg));
+}
+
+static void read_current_time(struct cass_dev *hw,
+			      union c_mb_sts_rtc_current_time *rtc)
+{
+	cass_read(hw, C_MB_STS_RTC_CURRENT_TIME, rtc, sizeof(*rtc));
+}
+
+/* Transform a time retrieved with read_current_time(). */
+static void current_time_to_ts(const union c_mb_sts_rtc_current_time *rtc,
+			       struct timespec64 *ts)
+{
+	ts->tv_sec = rtc->seconds_47_34;
+	ts->tv_sec <<= 34;
+	ts->tv_sec |= rtc->seconds_33_0;
+	ts->tv_nsec = rtc->nanoseconds;
+}
+
+static void adjust_rtc(struct cass_dev *hw, s64 delta)
+{
+	const union c_mb_cfg_rtc rtc_cfg = {
+		.rtc_update = 1,
+		.rtc_enable = 1,
+		.etc_enable = 1,
+	};
+	struct timespec64 rtc_ts;
+	struct timespec64 delta_ts;
+
+	if (abs(delta) > RTC_MAX_ADJ) {
+		union c_mb_sts_rtc_current_time rtc;
+
+		read_current_time(hw, &rtc);
+		current_time_to_ts(&rtc, &rtc_ts);
+		delta_ts = ns_to_timespec64(delta);
+		rtc_ts = timespec64_add(rtc_ts, delta_ts);
+		write_rtc(hw, &rtc_ts);
+	} else {
+		union c_mb_cfg_rtc_time rtc = {};
+
+		if (delta > 0)
+			rtc.nanoseconds = delta;
+		else
+			rtc.nanoseconds = BIT(RTC_NS_WIDTH) + delta;
+
+		cass_write(hw, C_MB_CFG_RTC_TIME, &rtc,
+			   C_MB_CFG_RTC_TIME_SIZE);
+		cass_write(hw, C_MB_CFG_RTC, &rtc_cfg, sizeof(rtc_cfg));
+	}
+}
+
+static void adjust_rtc_freq(struct cass_dev *hw, long scaled_ppm)
+{
+	union c_mb_cfg_rtc_inc rtc_inc = {};
+	bool neg_adj;
+	u64 frac_ns;
+	u64 adj_ns;
+
+	if (scaled_ppm < 0) {
+		neg_adj = true;
+		scaled_ppm = -scaled_ppm;
+	} else {
+		neg_adj = false;
+	}
+
+	/* From ptp_clock.c:
+	 *    ppb = scaled_ppm * 10^3 * 2^-16
+	 *
+	 * adj_ns = ppb * 2^32 / clk_hz
+	 *     = scaled_ppm * 10^3 * 2^-16 * 2^32 / clk_hz
+	 *     = scaled_ppm * 65536000 / clk_hz
+	 *     = scaled_ppm << 16 / clk_khz
+	 */
+	if (scaled_ppm) {
+		adj_ns = scaled_ppm;
+		adj_ns <<= 16;
+		if (cass_version(hw, CASSINI_1))
+			adj_ns = div_u64(adj_ns, C1_CLK_FREQ_HZ / 1000);
+		else
+			adj_ns = div_u64(adj_ns, C2_CLK_FREQ_HZ / 1000);
+	} else {
+		adj_ns = 0;
+	}
+
+	/* Set the default value for the clock frequency */
+	if (cass_version(hw, CASSINI_1))
+		frac_ns = RTC_MAX_FNS;	/* i.e. 1ns */
+	else
+		frac_ns = 3904515724; /* 2^32 * 1.0 Ghz / 1.1Ghz */
+
+	/* And adjust it */
+	if (neg_adj)
+		frac_ns -= adj_ns;
+	else
+		frac_ns += adj_ns;
+
+	if (frac_ns >= RTC_MAX_FNS) {
+		rtc_inc.nanoseconds = 1;
+		rtc_inc.fractional_ns = frac_ns - RTC_MAX_FNS;
+	} else {
+		rtc_inc.nanoseconds = 0;
+		rtc_inc.fractional_ns = frac_ns;
+	}
+
+	cass_write(hw, C_MB_CFG_RTC_INC, &rtc_inc, sizeof(rtc_inc));
+
+	/* Perform NOP RTC update so Cassini loads the new RTC_INC value. */
+	adjust_rtc(hw, 0);
+}
+
+/* Initialize the time keeping CSRs before the clock is
+ * started. Hopefully it's close enough to the RTC start that the
+ * small time difference won't matter. RT_OFFSET could be calculated
+ * later to compensate if needed.
+ */
+static void set_elapsed_time(struct cass_dev *hw, const struct timespec64 *ts)
+{
+	struct eltime {
+		unsigned int elapsed_time;
+		unsigned int time_offset_ns;
+		unsigned int rt_offset;
+	} time_init[] = {
+		{ C_ATU_ERR_ELAPSED_TIME, 4, 0 },
+		{ C_CQ_ERR_ELAPSED_TIME, 8, 0 },
+		{ C_EE_ERR_ELAPSED_TIME, 7, C_EE_CFG_RT_OFFSET },
+		{ C_HNI_ERR_ELAPSED_TIME, 12, C_HNI_CFG_RT_OFFSET },
+		{ C_HNI_PML_ERR_ELAPSED_TIME, 13, 0 },
+		{ C_IXE_ERR_ELAPSED_TIME, 17, 0 },
+		{ C_LPE_ERR_ELAPSED_TIME, 11, 0 },
+		{ C_MB_ERR_ELAPSED_TIME, 3, C_MB_CFG_RT_OFFSET },
+		{ C_MST_ERR_ELAPSED_TIME, 13, C_MST_CFG_RT_OFFSET },
+		{ C_OXE_ERR_ELAPSED_TIME, 18, C_OXE_CFG_RT_OFFSET },
+		{ C_PARBS_ERR_ELAPSED_TIME, 9, C_PARBS_CFG_RT_OFFSET },
+		{ C_PCT_ERR_ELAPSED_TIME, 10, 0 },
+		{ C_PI_ERR_ELAPSED_TIME, 6, C_PI_CFG_RT_OFFSET },
+		{ C_PI_IPD_ERR_ELAPSED_TIME, 15, C_PI_IPD_CFG_RT_OFFSET },
+		{ C_RMU_ERR_ELAPSED_TIME, 15, 0 },
+	};
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(time_init); i++) {
+		struct eltime *t = &time_init[i];
+		struct timespec64 offset_ts = *ts;
+		union c_mb_err_elapsed_time err_elapsed_time;
+
+		timespec64_add_ns(&offset_ts, time_init->time_offset_ns);
+		err_elapsed_time.nanoseconds = offset_ts.tv_nsec,
+		err_elapsed_time.seconds = offset_ts.tv_sec,
+
+		cass_write(hw, t->elapsed_time, &err_elapsed_time,
+			   sizeof(err_elapsed_time));
+		if (t->rt_offset)
+			cass_clear(hw, t->rt_offset, C_MB_CFG_RT_OFFSET_SIZE);
+	}
+}
+
+static void init_rtc(struct cass_dev *hw)
+{
+	struct timespec64 ts = {};
+
+	adjust_rtc_freq(hw, 0);
+
+	ktime_get_real_ts64(&ts);
+	set_elapsed_time(hw, &ts);
+	write_rtc(hw, &ts);
+}
+
+static void fini_rtc(struct cass_dev *hw)
+{
+	cass_clear(hw, C_MB_CFG_RTC, C_MB_CFG_RTC_SIZE);
+}
+
+static int cass_ptp_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
+{
+	struct cass_dev *hw = container_of(ptp, struct cass_dev, ptp_info);
+	unsigned long flags;
+
+	spin_lock_irqsave(&hw->rtc_lock, flags);
+	adjust_rtc_freq(hw, scaled_ppm);
+	spin_unlock_irqrestore(&hw->rtc_lock, flags);
+
+	return 0;
+}
+
+static int cass_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
+{
+	struct cass_dev *hw = container_of(ptp, struct cass_dev, ptp_info);
+	unsigned long flags;
+
+	spin_lock_irqsave(&hw->rtc_lock, flags);
+	adjust_rtc(hw, delta);
+	spin_unlock_irqrestore(&hw->rtc_lock, flags);
+
+	return 0;
+}
+
+static int cass_ptp_gettimex64(struct ptp_clock_info *ptp,
+			       struct timespec64 *ts,
+			       struct ptp_system_timestamp *sts)
+{
+	struct cass_dev *hw = container_of(ptp, struct cass_dev, ptp_info);
+	union c_mb_sts_rtc_current_time rtc;
+	unsigned long flags;
+
+	spin_lock_irqsave(&hw->rtc_lock, flags);
+
+	ptp_read_system_prets(sts);
+	read_current_time(hw, &rtc);
+	ptp_read_system_postts(sts);
+
+	spin_unlock_irqrestore(&hw->rtc_lock, flags);
+
+	current_time_to_ts(&rtc, ts);
+
+	return 0;
+}
+
+static int cass_ptp_settime64(struct ptp_clock_info *ptp,
+			      const struct timespec64 *ts)
+{
+	struct cass_dev *hw = container_of(ptp, struct cass_dev, ptp_info);
+	unsigned long flags;
+
+	spin_lock_irqsave(&hw->rtc_lock, flags);
+	write_rtc(hw, ts);
+	spin_unlock_irqrestore(&hw->rtc_lock, flags);
+
+	return 0;
+}
+
+static int cass_ptp_enable(struct ptp_clock_info *ptp,
+			   struct ptp_clock_request *request, int on)
+{
+	return -EOPNOTSUPP;
+}
+
+static int cass_ptp_verify(struct ptp_clock_info *ptp, unsigned int pin,
+			   enum ptp_pin_function func, unsigned int chan)
+{
+	return -EOPNOTSUPP;
+}
+
+static struct ptp_clock_info cass_ptp_info = {
+	.owner		= THIS_MODULE,
+	.name		= "Cassini clock",
+	.max_adj	= RTC_MAX_FNS - 1, /* Max. freq. adj. in  ppb */
+	.adjfine	= cass_ptp_adjfine,
+	.adjtime	= cass_ptp_adjtime,
+	.gettimex64	= cass_ptp_gettimex64,
+	.settime64	= cass_ptp_settime64,
+	.enable		= cass_ptp_enable,
+	.verify		= cass_ptp_verify,
+};
+
+int cass_ptp_init(struct cass_dev *hw)
+{
+	spin_lock_init(&hw->rtc_lock);
+	hw->ptp_info = cass_ptp_info;
+
+	init_rtc(hw);
+
+	hw->ptp_clock = ptp_clock_register(&hw->ptp_info,
+					   &hw->cdev.pdev->dev);
+	if (IS_ERR(hw->ptp_clock)) {
+		fini_rtc(hw);
+		return PTR_ERR(hw->ptp_clock);
+	}
+
+	return 0;
+}
+
+void cass_ptp_fini(struct cass_dev *hw)
+{
+	ptp_clock_unregister(hw->ptp_clock);
+	fini_rtc(hw);
+}
diff --git a/drivers/net/ethernet/hpe/ss1/cass_rgid.c b/drivers/net/ethernet/hpe/ss1/cass_rgid.c
new file mode 100644
index 000000000000..68c8e096b7a9
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_rgid.c
@@ -0,0 +1,293 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2024 Hewlett Packard Enterprise Development LP */
+
+/* Cassini RGID management */
+
+#include <linux/debugfs.h>
+#include <linux/types.h>
+
+#include "cass_core.h"
+
+struct cass_rgid_priv {
+	int lnis;
+	int svc_id;
+	struct ida lac_table;
+	struct idr lcid_table;
+	refcount_t refcount;
+};
+
+/**
+ * cass_rgid_init() - Initialize the RGID array
+ *
+ * @hw: Cassini device
+ */
+void cass_rgid_init(struct cass_dev *hw)
+{
+	xa_init_flags(&hw->rgid_array, XA_FLAGS_ALLOC1);
+	refcount_set(&hw->rgids_refcount, 1);
+}
+
+/**
+ * cass_rgid_fini() - Clean up the RGID array
+ *
+ * @hw: Cassini device
+ */
+void cass_rgid_fini(struct cass_dev *hw)
+{
+	unsigned long id;
+	struct cass_rgid_priv *rgid_priv;
+
+	xa_for_each(&hw->rgid_array, id, rgid_priv)
+		kfree(rgid_priv);
+
+	xa_destroy(&hw->rgid_array);
+}
+
+/**
+ * cass_lac_get() - Get an LAC
+ *
+ * @hw: Cassini device
+ * @id: Value of RGID to get an LAC from
+ * @return: 0 on success or negative error
+ */
+int cass_lac_get(struct cass_dev *hw, int id)
+{
+	struct cass_rgid_priv *rgid_priv = xa_load(&hw->rgid_array, id);
+
+	if (!rgid_priv)
+		return 0;
+
+	return ida_alloc_max(&rgid_priv->lac_table, C_NUM_LACS - 1, GFP_KERNEL);
+}
+
+/**
+ * cass_lac_put() - Free an LAC
+ *
+ * @hw: Cassini device
+ * @id: Value of RGID
+ * @lac: LAC to free
+ */
+void cass_lac_put(struct cass_dev *hw, int id, int lac)
+{
+	struct cass_rgid_priv *rgid_priv = xa_load(&hw->rgid_array, id);
+
+	if (!rgid_priv)
+		return;
+
+	ida_free(&rgid_priv->lac_table, lac);
+}
+
+/**
+ * cass_lcid_get() - Get an LCID
+ *
+ * @hw: Cassini device
+ * @cp_priv: Communication Profile object
+ * @rgid: Value of RGID to get an LCID from
+ * @cp_type: Request LCID 0 for type TRIG_LCID
+ * @return: 0 or positive value on success or negative error
+ */
+int cass_lcid_get(struct cass_dev *hw, struct cxi_cp_priv *cp_priv, int rgid,
+		  enum cxi_trig_cp cp_type)
+	__must_hold(&hw->cp_lock)
+{
+	struct cass_rgid_priv *rgid_priv = xa_load(&hw->rgid_array, rgid);
+
+	if (!rgid_priv)
+		return -ENOENT;
+
+	/* When an TRIG_LCID is requested, return error if it
+	 * cannot be allocated.
+	 */
+	if (cp_type == TRIG_LCID)
+		return idr_alloc(&rgid_priv->lcid_table, cp_priv, 0, 1,
+				   GFP_KERNEL);
+
+	return idr_alloc(&rgid_priv->lcid_table, cp_priv,
+			 (cp_type == NON_TRIG_LCID) ? 1 : 0,
+			 C_COMM_PROF_PER_CQ, GFP_KERNEL);
+}
+
+/**
+ * cass_lcid_put() - Free an LCID
+ *
+ * @hw: Cassini device
+ * @rgid: Value of RGID
+ * @lcid: LCID to free
+ */
+void cass_lcid_put(struct cass_dev *hw, int rgid, int lcid)
+	__must_hold(&hw->cp_lock)
+{
+	struct cass_rgid_priv *rgid_priv = xa_load(&hw->rgid_array, rgid);
+
+	if (!rgid_priv)
+		return;
+
+	idr_remove(&rgid_priv->lcid_table, lcid);
+}
+
+/**
+ * cass_cp_find() - Get the CP accociated with an RGID and LCID
+ *
+ * @hw: Cassini device
+ * @rgid: Value of RGID
+ * @lcid: Value of LCID
+ * @return: CP object on success or NULL on error
+ */
+struct cxi_cp_priv *cass_cp_find(struct cass_dev *hw, int rgid, int lcid)
+{
+	struct cxi_cp_priv *cp_priv;
+	struct cass_rgid_priv *rgid_priv = xa_load(&hw->rgid_array, rgid);
+
+	if (!rgid_priv)
+		return NULL;
+
+	mutex_lock(&hw->cp_lock);
+	cp_priv = idr_find(&rgid_priv->lcid_table, lcid);
+	mutex_unlock(&hw->cp_lock);
+
+	return cp_priv;
+}
+
+/**
+ * cass_cp_rgid_find() - Get the CP associated with an RGID that matches
+ *                       the {vni_pcp,tc,tc_type,lni_id} tuple.
+ *                       Only return a CP with LCID of 0 if requested
+ *                       with TRIG_LCID or ANY_LCID.
+ *
+ * @hw: Cassini device
+ * @lni_priv: the Logical Network Interface
+ * @vni_pcp: VNI of communication profile. If using an ethernet tc
+ *           this argument is treated as PCP.
+ * @tc: Traffic class of the communication profile
+ * @tc_type: Traffic class type of the communication profile
+ * @cp_type: Allow LNIs sharing a CP with lcid 0 only
+ * @return: CP object on success or NULL on error
+ */
+struct cxi_cp_priv *cass_cp_rgid_find(struct cass_dev *hw,
+				      struct cxi_lni_priv *lni_priv,
+				      unsigned int vni_pcp, unsigned int tc,
+				      enum cxi_traffic_class_type tc_type,
+				      enum cxi_trig_cp cp_type)
+{
+	int lcid;
+	struct cxi_cp_priv *cp_priv;
+	bool share_lcid0 = cp_type != NON_TRIG_LCID;
+	struct cass_rgid_priv *rgid_priv = xa_load(&hw->rgid_array,
+						   lni_priv->lni.rgid);
+
+	if (!rgid_priv)
+		return NULL;
+
+	for (lcid = 0; lcid < C_COMM_PROF_PER_CQ; lcid++) {
+		cp_priv = idr_find(&rgid_priv->lcid_table, lcid);
+		if (!cp_priv)
+			continue;
+
+		if (vni_pcp == cp_priv->cp.vni_pcp &&
+		    tc == cp_priv->cp.tc &&
+		    tc_type == cp_priv->cass_cp->tc_type &&
+		    ((share_lcid0 && !lcid) ||
+		     (!share_lcid0 && lcid &&
+		      (lni_priv->lni.id == cp_priv->lni_id)))) {
+			refcount_inc(&cp_priv->refcount);
+
+			return cp_priv;
+		}
+	}
+
+	return NULL;
+}
+
+/**
+ * cass_rgid_get() - Get an RGID from the pool
+ *
+ * @hw: Cassini device
+ * @rgroup: Resource group container
+ * @return: rgid on success or negative error
+ */
+int cass_rgid_get(struct cass_dev *hw, struct cxi_rgroup *rgroup)
+{
+	int ret;
+	u32 id;
+	unsigned long idx;
+	struct cass_rgid_priv *rgidp;
+	struct cass_rgid_priv *rgid_priv;
+	unsigned int lnis_per_rgid = rgroup->attr.lnis_per_rgid;
+
+	rgid_priv = kzalloc(sizeof(*rgid_priv), GFP_KERNEL);
+	if (!rgid_priv)
+		return -ENOMEM;
+
+	xa_lock(&hw->rgid_array);
+
+	xa_for_each(&hw->rgid_array, idx, rgidp) {
+		if ((rgidp->svc_id == rgroup->id) &&
+		    (rgidp->lnis == lnis_per_rgid) &&
+		    (refcount_read(&rgidp->refcount) < rgidp->lnis)) {
+			refcount_inc(&rgidp->refcount);
+			kfree(rgid_priv);
+			id = idx;
+			goto done;
+		}
+	}
+
+	ret = __xa_alloc(&hw->rgid_array, &id, rgid_priv,
+			 XA_LIMIT(1, C_NUM_RGIDS - 1), GFP_KERNEL);
+
+	/* -EBUSY is returned when there is no room */
+	if (ret == -EBUSY)
+		ret = -ENOSPC;
+
+	if (ret)
+		goto unlock_free;
+
+	rgid_priv->svc_id = rgroup->id;
+	rgid_priv->lnis = lnis_per_rgid;
+	refcount_set(&rgid_priv->refcount, 1);
+	ida_init(&rgid_priv->lac_table);
+	idr_init(&rgid_priv->lcid_table);
+	refcount_inc(&hw->rgids_refcount);
+
+done:
+	xa_unlock(&hw->rgid_array);
+
+	return id;
+
+unlock_free:
+	xa_unlock(&hw->rgid_array);
+	kfree(rgid_priv);
+
+	if (ret == -ENOSPC)
+		pr_debug("RGID space exhausted\n");
+	else
+		pr_err("Failed to store id %d ret:%d\n", id, ret);
+
+	return ret;
+}
+
+/**
+ * cass_rgid_put() - Return RGID to the pool
+ *
+ * @hw: Cassini device
+ * @id: Value of RGID
+ */
+void cass_rgid_put(struct cass_dev *hw, int id)
+{
+	struct cass_rgid_priv *rgid_priv;
+
+	xa_lock(&hw->rgid_array);
+
+	rgid_priv = xa_load(&hw->rgid_array, id);
+	if (!rgid_priv) {
+		pr_err("rgid_priv NULL for id:%d\n", id);
+		goto unlock;
+	}
+
+	if (refcount_dec_and_test(&rgid_priv->refcount)) {
+		WARN_ON(__xa_erase(&hw->rgid_array, id) == NULL);
+		refcount_dec(&hw->rgids_refcount);
+		kfree(rgid_priv);
+	}
+unlock:
+	xa_unlock(&hw->rgid_array);
+}
diff --git a/drivers/net/ethernet/hpe/ss1/cass_rgroup.c b/drivers/net/ethernet/hpe/ss1/cass_rgroup.c
new file mode 100644
index 000000000000..840f1d7a2373
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_rgroup.c
@@ -0,0 +1,281 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2024 Hewlett Packard Enterprise Development LP */
+
+/* Resource Group implementation */
+
+#include "cass_core.h"
+
+/**
+ * get_cxi_dev() - type-safe function to get CXI device pointer
+ *                 from Cassini device
+ *
+ * @hw: cass_dev pointer
+ *
+ * Return: Embedded CXI device pointer
+ */
+static struct cxi_dev *get_cxi_dev(struct cass_dev *hw)
+{
+	return &hw->cdev;
+}
+
+void cass_dev_rgroup_init(struct cass_dev *hw)
+{
+	int i;
+
+	spin_lock_init(&hw->rgrp_lock);
+
+	hw->resource_use[CXI_RESOURCE_PTLTE].max = C_NUM_PTLTES;
+	hw->resource_use[CXI_RESOURCE_TXQ].max = C_NUM_TRANSMIT_CQS;
+	hw->resource_use[CXI_RESOURCE_TGQ].max = C_NUM_TARGET_CQS;
+	hw->resource_use[CXI_RESOURCE_EQ].max = EQS_AVAIL;
+	hw->resource_use[CXI_RESOURCE_CT].max = CTS_AVAIL;
+	hw->resource_use[CXI_RESOURCE_PE0_LE].max = pe_total_les;
+	hw->resource_use[CXI_RESOURCE_PE1_LE].max = pe_total_les;
+	hw->resource_use[CXI_RESOURCE_PE2_LE].max = pe_total_les;
+	hw->resource_use[CXI_RESOURCE_PE3_LE].max = pe_total_les;
+	hw->resource_use[CXI_RESOURCE_TLE].max = C_NUM_TLES;
+	/* AC 0 invalid and one reserved for shared physical mappings */
+	hw->resource_use[CXI_RESOURCE_AC].max = ACS_AVAIL;
+
+	/* start with all resources shared */
+	for (i = 0; i < CXI_RESOURCE_MAX; i++) {
+		hw->resource_use[i].in_use = 0;
+		hw->resource_use[i].reserved = 0;
+		hw->resource_use[i].shared_use = 0;
+		hw->resource_use[i].shared = hw->resource_use[i].max;
+	}
+
+	cxi_dev_rgroup_init(get_cxi_dev(hw));
+}
+
+void cass_dev_rgroup_fini(struct cass_dev *hw)
+{
+	cxi_dev_rgroup_fini(get_cxi_dev(hw));
+}
+
+int cass_rgroup_add_resource(struct cxi_rgroup *rgroup,
+			     struct cxi_resource_entry *resource)
+{
+	int rc = 0;
+	struct cass_dev *hw = rgroup->hw;
+	struct cxi_resource_use *r_use = &hw->resource_use[resource->type];
+
+	if (!resource->limits.max && !resource->limits.reserved)
+		return 0;
+
+	spin_lock(&hw->rgrp_lock);
+
+	if (resource->type == CXI_RESOURCE_TLE) {
+		/* Enforce minimum TLEs */
+		if (resource->limits.reserved) {
+			if (resource->limits.reserved < CASS_MIN_POOL_TLES) {
+				pr_debug("%s reserved minimum must be >= %d\n",
+					 cxi_resource_type_to_str(CXI_RESOURCE_TLE),
+					 CASS_MIN_POOL_TLES);
+				rc = -EINVAL;
+				goto unlock;
+			}
+		}
+
+		/* Enforce max and reserved TLEs equal */
+		if (resource->limits.max != resource->limits.reserved) {
+			pr_debug("%s max must equal reserved\n",
+				 cxi_resource_type_to_str(CXI_RESOURCE_TLE));
+			rc = -EINVAL;
+			goto unlock;
+		}
+	}
+
+	if (resource->limits.reserved > r_use->shared) {
+		pr_debug("Error - %s reserved requested (%lu) > shared available (%lu)\n",
+			 cxi_resource_type_to_str(resource->type),
+			 resource->limits.reserved, r_use->shared);
+		rc = -ENOSPC;
+		goto unlock;
+	}
+
+	if (resource->limits.max > r_use->max) {
+		pr_debug("Error - %s max requested (%lu) > max available (%lu)\n",
+			 cxi_resource_type_to_str(resource->type),
+			 resource->limits.max, r_use->max);
+		rc = -ENOSPC;
+		goto unlock;
+	}
+
+	/* resources that need extra configuring */
+	if (resource->type >= CXI_RESOURCE_PE0_LE &&
+	    resource->type <= CXI_RESOURCE_PE3_LE) {
+		int le_pool_id;
+		int pe = resource->type - CXI_RESOURCE_PE0_LE;
+
+		le_pool_id = ida_alloc_range(&hw->le_pool_ids[pe],
+					     DEFAULT_LE_POOL_ID,
+					     CASS_NUM_LE_POOLS - 1, GFP_NOWAIT);
+		if (le_pool_id < 0) {
+			pr_debug("%s pool unavailable.\n",
+				 cxi_resource_type_to_str(resource->type));
+			rc = -EBADR;
+			goto unlock;
+		}
+
+		rgroup->pools.le_pool_id[pe] = le_pool_id;
+	} else if (resource->type == CXI_RESOURCE_TLE) {
+		int tle_pool_id;
+
+		tle_pool_id = ida_alloc_range(&hw->tle_pool_ids,
+					      DEFAULT_TLE_POOL_ID,
+					      C_CQ_CFG_TLE_POOL_ENTRIES - 1,
+					      GFP_NOWAIT);
+		if (tle_pool_id < 0) {
+			pr_debug("%s pool unavailable.\n",
+				 cxi_resource_type_to_str(resource->type));
+			rc = -EBADR;
+			goto unlock;
+		}
+
+		rgroup->pools.tle_pool_id = tle_pool_id;
+	}
+
+	r_use->reserved += resource->limits.reserved;
+	r_use->shared -= resource->limits.reserved;
+
+	pr_debug("type:%s limits.reserved:%ld limits.max:%ld reserved:%ld shared:%ld\n",
+		 cxi_resource_type_to_str(resource->type),
+		 resource->limits.reserved, resource->limits.max,
+		 r_use->reserved, r_use->shared);
+
+	if (resource->type >= CXI_RESOURCE_PE0_LE &&
+	    resource->type <= CXI_RESOURCE_PE3_LE) {
+		int pe = resource->type - CXI_RESOURCE_PE0_LE;
+		struct cxi_limits les = {
+			.max = resource->limits.max,
+			.res = resource->limits.reserved,
+		};
+
+		cass_cfg_le_pools(hw, rgroup->pools.le_pool_id[pe], pe, &les,
+				  false);
+	} else if (resource->type == CXI_RESOURCE_TLE) {
+		struct cxi_limits tles = {
+			.max = resource->limits.max,
+			.res = resource->limits.reserved,
+		};
+
+		cass_cfg_tle_pool(hw, rgroup->pools.tle_pool_id, &tles, false);
+	}
+
+unlock:
+	spin_unlock(&hw->rgrp_lock);
+
+	return rc;
+}
+
+int cass_rgroup_remove_resource(struct cxi_rgroup *rgroup,
+				struct cxi_resource_entry *resource)
+{
+	struct cass_dev *hw = rgroup->hw;
+	struct cxi_resource_use *r_use;
+
+	r_use = &hw->resource_use[resource->type];
+
+	spin_lock(&hw->rgrp_lock);
+
+	r_use->reserved -= resource->limits.reserved;
+	r_use->shared += resource->limits.reserved;
+
+	pr_debug("type:%s limits.reserved:%ld limits.max:%ld reserved:%ld shared:%ld\n",
+		 cxi_resource_type_to_str(resource->type),
+		 resource->limits.reserved, resource->limits.max,
+		 r_use->reserved, r_use->shared);
+
+	if (resource->type >= CXI_RESOURCE_PE0_LE &&
+	    resource->type <= CXI_RESOURCE_PE3_LE) {
+		int pe = resource->type - CXI_RESOURCE_PE0_LE;
+		struct cxi_limits les = {
+			.max = resource->limits.max,
+			.res = resource->limits.reserved,
+		};
+
+		cass_cfg_le_pools(hw, rgroup->pools.le_pool_id[pe], pe, &les,
+				  true);
+		ida_free(&hw->le_pool_ids[pe], rgroup->pools.le_pool_id[pe]);
+		rgroup->pools.le_pool_id[pe] = -1;
+	} else if (resource->type == CXI_RESOURCE_TLE) {
+		struct cxi_limits tles = {
+			.max = resource->limits.max,
+			.res = resource->limits.reserved,
+		};
+
+		cass_cfg_tle_pool(hw, rgroup->pools.tle_pool_id, &tles, true);
+		ida_free(&hw->tle_pool_ids, rgroup->pools.tle_pool_id);
+		rgroup->pools.tle_pool_id = -1;
+	}
+
+	spin_unlock(&hw->rgrp_lock);
+
+	return 0;
+}
+
+void cass_free_resource(struct cxi_rgroup *rgroup,
+			struct cxi_resource_entry *entry)
+{
+	struct cass_dev *hw = rgroup->hw;
+	struct cxi_resource_use *r_use = &hw->resource_use[entry->type];
+
+	spin_lock(&hw->rgrp_lock);
+
+	/* Free from shared space if applicable */
+	if (entry->limits.in_use > entry->limits.reserved)
+		r_use->shared_use--;
+
+	r_use->in_use--;
+	entry->limits.in_use--;
+
+	spin_unlock(&hw->rgrp_lock);
+}
+
+int cass_alloc_resource(struct cxi_rgroup *rgroup,
+			struct cxi_resource_entry *entry)
+{
+	int rc = 0;
+	size_t available;
+	struct cass_dev *hw = rgroup->hw;
+	struct cxi_resource_use *r_use = &hw->resource_use[entry->type];
+
+	spin_lock(&hw->rgrp_lock);
+
+	available = r_use->max - r_use->shared_use;
+
+	if (entry->limits.in_use < entry->limits.reserved) {
+		r_use->in_use++;
+		entry->limits.in_use++;
+	} else if (entry->limits.in_use < entry->limits.max && available) {
+		entry->limits.in_use++;
+		r_use->in_use++;
+		r_use->shared_use++;
+	} else {
+		pr_debug("%s unavailable use:%ld reserved:%ld max:%ld shared_use:%ld\n",
+			 cxi_resource_type_to_str(entry->type),
+			 entry->limits.in_use, entry->limits.reserved,
+			 entry->limits.max, r_use->shared_use);
+		rc = -ENOSPC;
+	}
+
+	spin_unlock(&hw->rgrp_lock);
+
+	return rc;
+}
+
+void cass_get_tle_in_use(struct cxi_rgroup *rgroup,
+			 struct cxi_resource_entry *entry)
+{
+	union c_cq_sts_tle_in_use tle_in_use;
+
+	if (cxi_rgroup_tle_pool_id(rgroup) == -1)
+		return;
+
+	cass_read(rgroup->hw,
+		  C_CQ_STS_TLE_IN_USE(cxi_rgroup_tle_pool_id(rgroup)),
+		  &tle_in_use, sizeof(tle_in_use));
+
+	entry->limits.in_use = tle_in_use.count;
+}
diff --git a/drivers/net/ethernet/hpe/ss1/cass_sbus.c b/drivers/net/ethernet/hpe/ss1/cass_sbus.c
new file mode 100644
index 000000000000..bdce46dc1de7
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_sbus.c
@@ -0,0 +1,172 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2020, 2022, 2024-2026 Hewlett Packard Enterprise Development LP */
+
+/* Cassini SBUS driver */
+
+#include <linux/hpe/cxi/cxi.h>
+#include <linux/iopoll.h>
+
+#include "cass_core.h"
+
+#include <linux/hpe/sbl/sbl.h>
+
+/**
+ * cxi_sbus_op_reset() - Perform an SBus op reset
+ *
+ * Note this doesn't reset the SBus - all it does is clear the MB
+ * accessor registers.
+ *
+ * @cdev: CXI device
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+int cxi_sbus_op_reset(struct cxi_dev *cdev)
+{
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	union c_mb_dbg_cfg_sbus_master cfg = {};
+	union c_mb_dbg_sts_sbus_master sts;
+	int rc;
+
+	if (!cdev->is_physfn)
+		return -EPERM;
+
+	rc = mutex_lock_interruptible(&hw->sbus_mutex);
+	if (rc) {
+		mutex_unlock(&hw->sbus_mutex);
+		return -ERESTARTSYS;
+	}
+
+	/* clear config register */
+	cass_write(hw, C_MB_DBG_CFG_SBUS_MASTER, &cfg, sizeof(cfg));
+
+	/* clear any sticky status bits */
+	cass_read(hw, C_MB_DBG_STS_SBUS_MASTER, &sts, sizeof(sts));
+	if (sts.overrun || sts.write_error) {
+		cass_write(hw, C_MB_DBG_STS_SBUS_MASTER, &sts, sizeof(sts));
+		cass_flush_pci(hw);
+	}
+
+	mutex_unlock(&hw->sbus_mutex);
+
+	return 0;
+}
+EXPORT_SYMBOL(cxi_sbus_op_reset);
+
+/**
+ * cxi_sbus_op() - Perform an SBus operation
+ *
+ * Performs target SBus operation on the single Cassini SBus ring.
+ *
+ * This function will also correct the overrun and write_error
+ * conditions if they happen.
+ *
+ * @cdev: CXI device
+ * @params: command parameters
+ * @rsp_data: pointer to store response data
+ * @result_code: pointer to store result code from SBus request
+ * @overrun: pointer to store request overrun condition
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+int cxi_sbus_op(struct cxi_dev *cdev, const struct cxi_sbus_op_params *params,
+		u32 *rsp_data, u8 *result_code,	u8 *overrun)
+{
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	const union c_mb_dbg_cfg_sbus_master cfg = {
+		.execute = 1,
+		.mode = 1,
+		.command = params->command,
+		.receiver_address = params->rx_addr,
+		.data_address = params->data_addr,
+		.data = params->req_data,
+	};
+	union c_mb_dbg_sts_sbus_master sts;
+	void __iomem *sts_csr = cass_csr(hw, C_MB_DBG_STS_SBUS_MASTER);
+	int rc;
+
+	if (!cdev->is_physfn)
+		return -EPERM;
+
+	if (!rsp_data || !result_code || !overrun)
+		return -EINVAL;
+
+	if (params->timeout == 0 || params->timeout > 5000)
+		return -EINVAL;
+
+	if (params->poll_interval == 0 || params->poll_interval > 1000)
+		return -EINVAL;
+
+	if (params->delay > 100)
+		return -EINVAL;
+
+	cxidev_dbg(cdev, "sbus op: %d, %d, %d %d\n", params->req_data,
+		   params->data_addr, params->rx_addr, params->command);
+
+	rc = mutex_lock_interruptible(&hw->sbus_mutex);
+	if (rc)
+		return -ERESTARTSYS;
+
+	/* Start the operation */
+	cass_write(hw, C_MB_DBG_CFG_SBUS_MASTER, &cfg, sizeof(cfg));
+	cass_flush_pci(hw);
+
+	if (params->delay)
+		udelay(params->delay);
+
+	/* Poll for completion */
+	rc = readq_poll_timeout(sts_csr, sts.qw,
+				sts.rcv_data_valid == 1,
+				(params->poll_interval * USEC_PER_MSEC),
+				(params->timeout * USEC_PER_MSEC));
+	if (rc) {
+		mutex_unlock(&hw->sbus_mutex);
+		return rc;
+	}
+
+	if (sts.overrun || sts.write_error) {
+		cass_write(hw, C_MB_DBG_STS_SBUS_MASTER, &sts, sizeof(sts));
+		cass_flush_pci(hw);
+	}
+
+	mutex_unlock(&hw->sbus_mutex);
+
+	*rsp_data = sts.data;
+	*result_code = sts.result_code;
+	*overrun = sts.overrun;
+
+	return 0;
+}
+EXPORT_SYMBOL(cxi_sbus_op);
+
+/**
+ * cxi_serdes_op() - Perform a SERDES operation
+ *
+ * Passthrough to the SBL driver.
+ *
+ * @cdev: CXI device
+ * @serdes_sel:
+ * @op:
+ * @data:
+ * @timeout:
+ * @flags:
+ * @result:
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+int cxi_serdes_op(struct cxi_dev *cdev, u64 serdes_sel, u64 op, u64 data,
+		  int timeout, unsigned int flags, u16 *result)
+{
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+
+	if (!cdev->is_physfn)
+		return -EPERM;
+
+	if (!cass_version(hw, CASSINI_1)) {
+		cxidev_err(cdev, "%s NOT IMPLEMENTED!\n", __func__);
+		return -ENOTSUPP;
+	}
+
+	return sbl_pml_serdes_op(hw->sbl, 0, serdes_sel, op, data, result,
+				 timeout, flags);
+}
+EXPORT_SYMBOL(cxi_serdes_op);
diff --git a/drivers/net/ethernet/hpe/ss1/cass_svc.c b/drivers/net/ethernet/hpe/ss1/cass_svc.c
new file mode 100644
index 000000000000..b2d91993e070
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_svc.c
@@ -0,0 +1,2011 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2020, 2024-2026 Hewlett Packard Enterprise Development LP */
+
+/* Service Management */
+
+#include <linux/cred.h>
+
+#include "cass_core.h"
+#include "cxi_rxtx_profile.h"
+#include "cxi_rxtx_profile_list.h"
+#include "cass_ss1_debugfs.h"
+#include "cxi_vf_cmd.h"
+
+static bool disable_default_svc = true;
+module_param(disable_default_svc, bool, 0444);
+MODULE_PARM_DESC(disable_default_svc, "Disable the default service.");
+
+static bool default_svc_test_mode;
+module_param(default_svc_test_mode, bool, 0444);
+MODULE_PARM_DESC(default_svc_test_mode,
+		 "Remove all safety rails for default service.");
+
+static int default_svc_num_tles = 512;
+module_param(default_svc_num_tles, int, 0644);
+MODULE_PARM_DESC(default_svc_num_tles,
+		 "Number of reserved TLEs for default service");
+
+static unsigned int default_vnis[CXI_SVC_MAX_VNIS] = {1, 10, 0, 0};
+module_param_array(default_vnis, uint, NULL, 0444);
+MODULE_PARM_DESC(default_vnis,
+		 "Default VNIS. Should be consistent at the fabric level");
+
+static bool enable_rgid_sharing = true;
+module_param(enable_rgid_sharing, bool, 0644);
+MODULE_PARM_DESC(enable_rgid_sharing,
+		 "Allow future CXI service allocations to use RGID sharing.");
+
+static int default_lnis_per_rgid = CXI_DEFAULT_LNIS_PER_RGID;
+module_param(default_lnis_per_rgid, int, 0644);
+MODULE_PARM_DESC(default_lnis_per_rgid, "Number of LNIs per RGID");
+
+static void svc_destroy(struct cass_dev *hw, struct cxi_svc_priv *svc_priv);
+
+static enum cxi_resource_type stype_to_rtype(enum cxi_rsrc_type type, int pe)
+{
+	switch (type) {
+	case CXI_RSRC_TYPE_PTE:
+		return CXI_RESOURCE_PTLTE;
+	case CXI_RSRC_TYPE_TXQ:
+		return CXI_RESOURCE_TXQ;
+	case CXI_RSRC_TYPE_TGQ:
+		return CXI_RESOURCE_TGQ;
+	case CXI_RSRC_TYPE_EQ:
+		return CXI_RESOURCE_EQ;
+	case CXI_RSRC_TYPE_CT:
+		return CXI_RESOURCE_CT;
+	case CXI_RSRC_TYPE_LE:
+		return CXI_RESOURCE_PE0_LE + pe;
+	case CXI_RSRC_TYPE_TLE:
+		return CXI_RESOURCE_TLE;
+	case CXI_RSRC_TYPE_AC:
+		return CXI_RESOURCE_AC;
+	default:
+		return CXI_RESOURCE_MAX;
+	}
+}
+
+static void copy_rsrc_use(struct cxi_dev *dev, struct cxi_rsrc_use *rsrcs,
+			  struct cxi_rgroup *rgroup)
+{
+	int rc;
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+	union c_cq_sts_tle_in_use tle_in_use;
+	int type;
+	enum cxi_resource_type rtype;
+	struct cxi_resource_entry *entry;
+
+	for (type = 0; type < CXI_RSRC_TYPE_MAX; type++) {
+		rtype = stype_to_rtype(type, 0);
+		if (type == CXI_RSRC_TYPE_TLE) {
+			if (cxi_rgroup_tle_pool_id(rgroup) == -1)
+				continue;
+
+			cass_read(hw,
+				  C_CQ_STS_TLE_IN_USE(cxi_rgroup_tle_pool_id(rgroup)),
+				  &tle_in_use, sizeof(tle_in_use));
+			rsrcs->in_use[type] = tle_in_use.count;
+			rsrcs->tle_pool_id = cxi_rgroup_tle_pool_id(rgroup);
+		} else {
+			rc = cxi_rgroup_get_resource_entry(rgroup,
+							   rtype, &entry);
+			if (rc) {
+				rsrcs->in_use[type] = 0;
+				continue;
+			}
+
+			rsrcs->in_use[type] = entry->limits.in_use;
+		}
+	}
+}
+
+void cass_cfg_tle_pool(struct cass_dev *hw, int pool_id,
+		       const struct cxi_limits *tles, bool release)
+{
+	union c_cq_cfg_tle_pool tle_pool;
+
+	if (release) {
+		tle_pool.max_alloc = 0;
+		tle_pool.num_reserved = 0;
+	} else {
+		tle_pool.max_alloc = tles->max;
+		tle_pool.num_reserved = tles->res;
+	}
+	cass_write(hw, C_CQ_CFG_TLE_POOL(pool_id), &tle_pool,
+		   sizeof(tle_pool));
+}
+
+void cass_tle_init(struct cass_dev *hw)
+{
+	int i;
+	union c_cq_cfg_sts_tle_shared tle_shared;
+	union c_cq_cfg_tle_pool tle_pool_cfg = {
+		.max_alloc = 0,
+		.num_reserved = 0,
+	};
+
+	/* Ensure there is no shared space for TLEs */
+	tle_shared.num_shared = 0;
+	cass_write(hw, C_CQ_CFG_STS_TLE_SHARED, &tle_shared,
+		   sizeof(tle_shared));
+
+	/* Disable all pools */
+	for (i = 0; i < C_CQ_CFG_TLE_POOL_ENTRIES; i++)
+		cass_write(hw, C_CQ_CFG_TLE_POOL(i), &tle_pool_cfg,
+			   sizeof(tle_pool_cfg));
+}
+
+static void default_rsrc_limits(struct cxi_rsrc_limits *limits)
+{
+	memset(limits, 0, sizeof(*limits));
+
+	limits->type[CXI_RSRC_TYPE_PTE].max = C_NUM_PTLTES;
+	limits->type[CXI_RSRC_TYPE_TXQ].max = C_NUM_TRANSMIT_CQS;
+	limits->type[CXI_RSRC_TYPE_TGQ].max = C_NUM_TARGET_CQS;
+	limits->type[CXI_RSRC_TYPE_EQ].max = EQS_AVAIL;
+	limits->type[CXI_RSRC_TYPE_CT].max = CTS_AVAIL;
+	limits->type[CXI_RSRC_TYPE_LE].max = pe_total_les;
+	limits->type[CXI_RSRC_TYPE_TLE].max = C_NUM_TLES;
+	limits->type[CXI_RSRC_TYPE_AC].max = ACS_AVAIL;
+}
+
+int cass_svc_init(struct cass_dev *hw)
+{
+	static struct cxi_svc_desc svc_desc = {
+		.resource_limits = true,
+	};
+	int i, svc_id;
+	struct cxi_svc_priv *svc_priv;
+	struct cxi_rsrc_limits limits;
+
+	/* TODO differentiate PF/VF */
+	if (!hw->cdev.is_physfn)
+		return 0;
+
+	default_rsrc_limits(&hw->cdev.prop.rsrcs);
+
+	for (i = 0; i < CXI_RSRC_TYPE_MAX; i++) {
+		/* Set up resource limits for default service */
+		if (i != CXI_RSRC_TYPE_TLE) {
+			limits.type[i].max = hw->cdev.prop.rsrcs.type[i].max;
+			limits.type[i].res = 0;
+		} else {
+			limits.type[i].res = max(CASS_MIN_POOL_TLES,
+						 default_svc_num_tles);
+			limits.type[i].max = limits.type[i].res;
+		}
+	}
+	svc_desc.limits = limits;
+
+	for (i = CXI_TC_DEDICATED_ACCESS; i <= CXI_TC_BEST_EFFORT; ++i)
+		svc_desc.tcs[i] = true;
+
+	if (!default_svc_test_mode) {
+		svc_desc.restricted_vnis = true;
+		svc_desc.num_vld_vnis = 0;
+
+		for (i = 0; i < CXI_SVC_MAX_VNIS; i++) {
+			if (!is_vni_valid(default_vnis[i]))
+				break;
+			svc_desc.num_vld_vnis++;
+			svc_desc.vnis[i] = default_vnis[i];
+		}
+
+		if (!svc_desc.num_vld_vnis)
+			return -EINVAL;
+	}
+
+	mutex_init(&hw->svc_lock);
+	idr_init(&hw->svc_ids);
+	INIT_LIST_HEAD(&hw->svc_list);
+	hw->svc_count = 0;
+
+	/* Create default service. It will get the default ID of
+	 * CXI_DEFAULT_SVC_ID
+	 */
+	svc_id = cxi_svc_alloc(&hw->cdev, &svc_desc, NULL, "default");
+	if (svc_id < 0)
+		return svc_id;
+
+	mutex_lock(&hw->svc_lock);
+	svc_priv = idr_find(&hw->svc_ids, svc_id);
+	mutex_unlock(&hw->svc_lock);
+
+	cxi_rgroup_set_lnis_per_rgid_compat(svc_priv->rgroup, 1);
+
+	svc_service_debugfs_create(hw);
+
+	return 0;
+}
+
+/* Check if a there are enough unused instances of a particular resource */
+static bool rsrc_available(struct cass_dev *hw,
+			   struct cxi_rsrc_limits *limits,
+			   enum cxi_rsrc_type type, int pe,
+			   struct cxi_svc_fail_info *fail_info)
+{
+	u16 shared_avail;
+	enum cxi_resource_type rtype;
+
+	rtype = stype_to_rtype(type, pe);
+	if (rtype >= CXI_RESOURCE_MAX)
+		return false;
+
+	shared_avail = hw->resource_use[rtype].shared;
+
+	/* Always fill out fail_info if a resource was requested so it
+	 * accurately reflects how many of resource X was available.
+	 * If all resources are in fact available, it won't be sent
+	 * back to the user.
+	 */
+	if (fail_info)
+		fail_info->rsrc_avail[type] = shared_avail;
+
+	if (limits->type[type].res > shared_avail)
+		return false;
+
+	return true;
+}
+
+/* Return resource reservations upon destruction of a service
+ * Caller must hold hw->svc_lock.
+ */
+static void free_rsrc(struct cxi_svc_priv *svc_priv,
+		      enum cxi_rsrc_type type)
+{
+	int rc;
+	int pe;
+	enum cxi_resource_type rtype = stype_to_rtype(type, 0);
+
+	if (type == CXI_RSRC_TYPE_LE) {
+		for (pe = 0; pe < C_PE_COUNT; pe++) {
+			rc = cxi_rgroup_delete_resource(svc_priv->rgroup,
+							rtype + pe);
+			if (rc)
+				pr_debug("delete resource %s failed %d\n",
+					 cxi_resource_type_to_str(type + pe),
+					 rc);
+		}
+
+		return;
+	}
+
+	rc = cxi_rgroup_delete_resource(svc_priv->rgroup, rtype);
+	if (rc)
+		pr_debug("delete resource %s failed %d\n",
+			 cxi_rsrc_type_to_str(type), rc);
+}
+
+static void free_rsrcs(struct cxi_svc_priv *svc_priv)
+{
+	int i;
+
+	for (i = 0; i < CXI_RSRC_TYPE_MAX; i++)
+		free_rsrc(svc_priv, i);
+}
+
+static int add_resource(struct cxi_rgroup *rgroup, enum cxi_rsrc_type type,
+			struct cxi_resource_limits *limits)
+{
+	int rc;
+	int pe;
+
+	if (type == CXI_RSRC_TYPE_LE) {
+		for (pe = 0; pe < C_PE_COUNT; pe++) {
+			rc = cxi_rgroup_add_resource(rgroup,
+						     stype_to_rtype(type, pe),
+						     limits);
+			if (rc) {
+				pr_debug("add resource %s PE %d failed\n",
+					 cxi_rsrc_type_to_str(type), pe);
+				return rc;
+			}
+		}
+
+		return rc;
+	}
+
+	rc = cxi_rgroup_add_resource(rgroup,
+				     stype_to_rtype(type, 0), limits);
+	if (rc)
+		pr_debug("add resource %s failed\n",
+			 cxi_rsrc_type_to_str(type));
+
+	return rc;
+}
+
+/* For each resource requested, check if enough of that resource is available.
+ * If they are all available, update the reserved values in the device.
+ * Caller must hold hw->svc_lock.
+ */
+static int reserve_rsrcs(struct cass_dev *hw,
+			 struct cxi_svc_priv *svc_priv,
+			 struct cxi_svc_fail_info *fail_info)
+{
+	int i;
+	int pe;
+	int rc = 0;
+	struct cxi_rgroup *rgroup = svc_priv->rgroup;
+	struct cxi_rsrc_limits *limits = &svc_priv->svc_desc.limits;
+
+	/* Default pool for default svc or when there are no LE limits */
+	if (!svc_priv->svc_desc.resource_limits)
+		default_rsrc_limits(limits);
+
+	for (i = CXI_RSRC_TYPE_PTE; i < CXI_RSRC_TYPE_MAX; i++) {
+		if (!limits->type[i].res && !limits->type[i].max)
+			continue;
+
+		if (i == CXI_RSRC_TYPE_TLE) {
+			if (svc_priv->svc_desc.svc_id != CXI_DEFAULT_SVC_ID) {
+				/* Ensure TLE max/res are at least CASS_MIN_POOL_TLES */
+				if (limits->type[i].res < CASS_MIN_POOL_TLES)
+					limits->type[i].res = CASS_MIN_POOL_TLES;
+				/* Force TLE max/res to be equal */
+				limits->type[i].max = limits->type[i].res;
+			}
+		} else if (i == CXI_RSRC_TYPE_LE) {
+			for (pe = 0; pe < C_PE_COUNT; pe++) {
+				if (!rsrc_available(hw, limits, i, pe,
+						    fail_info)) {
+					pr_debug("resource %s PE %d unavailable\n",
+						 cxi_rsrc_type_to_str(i), pe);
+					rc = -ENOSPC;
+					goto nospace;
+				}
+			}
+		} else if (!rsrc_available(hw, limits, i, 0, fail_info)) {
+			pr_debug("resource %s unavailable\n",
+				 cxi_rsrc_type_to_str(i));
+			rc = -ENOSPC;
+			goto nospace;
+		}
+	}
+
+nospace:
+	if (rc)
+		return rc;
+
+	/* Now reserve resources since needed ones are available */
+	for (i = CXI_RSRC_TYPE_PTE; i < CXI_RSRC_TYPE_MAX; i++) {
+		struct cxi_resource_limits lim = {
+			.reserved = limits->type[i].res,
+			.max = limits->type[i].max
+		};
+
+		if (!lim.reserved && !lim.max)
+			continue;
+
+		rc = add_resource(rgroup, i, &lim);
+		if (rc) {
+			pr_debug("resource %s add_resource failed %d\n",
+				 cxi_rsrc_type_to_str(i), rc);
+
+			if (rc == -EBADR) {
+				if (i == CXI_RSRC_TYPE_TLE)
+					fail_info->no_tle_pools = true;
+
+				if (i == CXI_RSRC_TYPE_LE)
+					fail_info->no_le_pools = true;
+				rc = -ENOSPC;
+			}
+
+			goto err;
+		}
+	}
+
+	return 0;
+
+err:
+	/* Remove any resources we already allocated */
+	for (--i; i >= CXI_RSRC_TYPE_PTE; i--) {
+		if (!limits->type[i].res)
+			continue;
+
+		free_rsrc(svc_priv, i);
+	}
+
+	return rc;
+}
+
+/* Basic sanity checks for user provided service descriptor */
+static int validate_descriptor(struct cass_dev *hw,
+			       const struct cxi_svc_desc *svc_desc)
+{
+	int i;
+
+	if (svc_desc->restricted_vnis) {
+		if (svc_desc->num_vld_vnis > CXI_SVC_MAX_VNIS)
+			return -EINVAL;
+		for (i = 0; i < svc_desc->num_vld_vnis; i++) {
+			if (!is_vni_valid(svc_desc->vnis[i]))
+				return -EINVAL;
+		}
+	}
+
+	if (svc_desc->restricted_members) {
+		for (i = 0; i < CXI_SVC_MAX_MEMBERS; i++) {
+			if (svc_desc->members[i].type < 0 ||
+			    svc_desc->members[i].type >= CXI_SVC_MEMBER_MAX)
+				return -EINVAL;
+		}
+	}
+
+	if (svc_desc->resource_limits) {
+		for (i = 0; i < CXI_RSRC_TYPE_MAX; i++) {
+			if (svc_desc->limits.type[i].max <
+			    svc_desc->limits.type[i].res)
+				return -EINVAL;
+			if (svc_desc->limits.type[i].max >
+			    hw->cdev.prop.rsrcs.type[i].max)
+				return -EINVAL;
+		}
+	}
+
+	return 0;
+}
+
+static enum cxi_ac_type svc_mbr_to_ac_type(enum cxi_svc_member_type type,
+					   bool restricted_members)
+{
+	if (!restricted_members)
+		return CXI_AC_OPEN;
+
+	switch (type) {
+	case CXI_SVC_MEMBER_UID:
+		return CXI_AC_UID;
+	case CXI_SVC_MEMBER_GID:
+		return CXI_AC_GID;
+	case CXI_SVC_MEMBER_NET_NS:
+		return CXI_AC_NETNS;
+	case CXI_SVC_MEMBER_IGNORE:
+		fallthrough;
+	default:
+		return 0;
+	}
+}
+
+static void set_tcs(struct cxi_dev *dev, struct cxi_svc_priv *svc_priv)
+{
+	int i, j;
+	struct cxi_tx_profile *tx_profile;
+	struct cxi_svc_desc *svc_desc = &svc_priv->svc_desc;
+
+	for (i = 0; i < svc_priv->svc_desc.num_vld_vnis; i++) {
+		tx_profile = svc_priv->tx_profile[i];
+
+		for (j = 0; j < CXI_TC_MAX; j++)
+			if (!svc_desc->restricted_tcs || svc_desc->tcs[j])
+				cxi_tx_profile_set_tc(tx_profile, j, true);
+	}
+}
+
+static int alloc_rgroup_ac_entries(struct cxi_dev *dev,
+				   struct cxi_svc_priv *svc_priv)
+{
+	int i;
+	int rc;
+	enum cxi_ac_type type;
+	unsigned int ac_entry_id;
+	union cxi_ac_data ac_data = {};
+	struct cxi_svc_desc *svc_desc = &svc_priv->svc_desc;
+
+	if (!svc_desc->restricted_members)
+		return cxi_rgroup_add_ac_entry(svc_priv->rgroup, CXI_AC_OPEN,
+					       &ac_data, &ac_entry_id);
+
+	for (i = 0; i < CXI_SVC_MAX_MEMBERS; i++) {
+		/* No AC entry for member[].type of CXI_SVC_MEMBER_IGNORE */
+		type = svc_mbr_to_ac_type(svc_desc->members[i].type,
+					  svc_desc->restricted_members);
+		if (!type)
+			continue;
+
+		if (type == CXI_AC_UID)
+			ac_data.uid = svc_desc->members[i].svc_member.uid;
+		else if (type == CXI_AC_GID)
+			ac_data.gid = svc_desc->members[i].svc_member.gid;
+
+		rc = cxi_rgroup_add_ac_entry(svc_priv->rgroup, type, &ac_data,
+					     &ac_entry_id);
+		if (rc)
+			goto cleanup;
+	}
+
+	return 0;
+
+cleanup:
+	cxi_ac_entry_list_destroy(&svc_priv->rgroup->ac_entry_list);
+
+	return rc;
+}
+
+static void remove_profile_ac_entries(struct cxi_dev *dev,
+				      struct cxi_svc_priv *svc_priv)
+{
+	int i;
+	struct cxi_svc_desc *svc_desc = &svc_priv->svc_desc;
+
+	for (i = 0; i < svc_desc->num_vld_vnis; i++) {
+		cxi_tx_profile_remove_ac_entries(svc_priv->tx_profile[i]);
+		cxi_rx_profile_remove_ac_entries(svc_priv->rx_profile[i]);
+	}
+}
+
+/* No AC entry will be allocated for a member[].type of
+ * CXI_SVC_MEMBER_IGNORE.
+ */
+static int alloc_profile_ac_entries(struct cxi_dev *dev,
+				    struct cxi_svc_priv *svc_priv)
+{
+	int i;
+	int j;
+	int rc;
+	enum cxi_ac_type type;
+	unsigned int ac_entry_id;
+	struct cxi_svc_desc *svc_desc = &svc_priv->svc_desc;
+
+	if (!svc_desc->restricted_members) {
+		for (j = 0; j < svc_priv->svc_desc.num_vld_vnis; j++) {
+			rc = cxi_rx_profile_add_ac_entry(svc_priv->rx_profile[j],
+							 CXI_AC_OPEN, 0, 0, 0,
+							 &ac_entry_id);
+			if (rc)
+				goto cleanup;
+
+			rc = cxi_tx_profile_add_ac_entry(svc_priv->tx_profile[j],
+							 CXI_AC_OPEN, 0, 0, 0,
+							 &ac_entry_id);
+			if (rc)
+				goto cleanup;
+		}
+
+		return 0;
+	}
+
+	for (j = 0; j < svc_priv->svc_desc.num_vld_vnis; j++) {
+		for (i = 0; i < CXI_SVC_MAX_MEMBERS; i++) {
+			type = svc_mbr_to_ac_type(svc_desc->members[i].type,
+						  svc_desc->restricted_members);
+			if (!type)
+				continue;
+
+			rc = cxi_rx_profile_add_ac_entry(
+					svc_priv->rx_profile[j], type,
+					svc_desc->members[i].svc_member.uid,
+					svc_desc->members[i].svc_member.gid,
+					0,
+					&ac_entry_id);
+			if (rc)
+				goto cleanup;
+
+			rc = cxi_tx_profile_add_ac_entry(
+					svc_priv->tx_profile[j], type,
+					svc_desc->members[i].svc_member.uid,
+					svc_desc->members[i].svc_member.gid,
+					0,
+					&ac_entry_id);
+			if (rc)
+				goto cleanup;
+		}
+	}
+
+	return 0;
+
+cleanup:
+	remove_profile_ac_entries(dev, svc_priv);
+
+	return rc;
+}
+
+static void release_rxtx_profiles(struct cxi_dev *dev,
+				  struct cxi_svc_priv *svc_priv)
+{
+	int i;
+
+	remove_profile_ac_entries(dev, svc_priv);
+
+	for (i = 0; i < svc_priv->svc_desc.num_vld_vnis; i++) {
+		cxi_rx_profile_dec_refcount(dev, svc_priv->rx_profile[i]);
+		cxi_tx_profile_dec_refcount(dev, svc_priv->tx_profile[i],
+					    true);
+	}
+}
+
+/* Update the Netns in RX/TX profile */
+static int update_profile_netns_entries(struct cxi_dev *dev,
+					struct cxi_svc_priv *svc_priv, unsigned int netns)
+{
+	int j;
+	int rc = 0;
+	union cxi_ac_data data = {};
+	unsigned int ac_entry_id;
+
+	for (j = 0; j < svc_priv->svc_desc.num_vld_vnis; j++) {
+		if (!svc_priv->rx_profile[j] || !svc_priv->tx_profile[j])
+			return -ENODATA;
+
+		data.netns = netns;
+		rc = cxi_rxtx_profile_add_ac_entry(&svc_priv->rx_profile[j]->profile_common,
+						   CXI_AC_NETNS, &data, &ac_entry_id);
+		if (rc)
+			goto cleanup;
+
+		rc = cxi_rxtx_profile_add_ac_entry(&svc_priv->tx_profile[j]->profile_common,
+						   CXI_AC_NETNS, &data, &ac_entry_id);
+		if (rc)
+			goto cleanup;
+	}
+
+	return 0;
+
+cleanup:
+	remove_profile_ac_entries(dev, svc_priv);
+	return rc;
+}
+
+/* Setup up to 4 RX/TX Profiles if restricted_vnis = 1
+ * Otherwise set up a single RX/TX profile for a requested VNI range
+ */
+static int alloc_rxtx_profiles(struct cxi_dev *dev,
+			       struct cxi_svc_priv *svc_priv,
+			       const struct cxi_rxtx_vni_attr *vni_range_attr)
+{
+	int i;
+	int rc;
+	const struct cxi_rxtx_vni_attr *vni_attr;
+	struct cxi_svc_desc *svc_desc = &svc_priv->svc_desc;
+
+	if (!svc_desc->restricted_vnis) {
+		if (!vni_range_attr) {
+			cxidev_err(dev, "vni_range_attr NULL for vni_range\n");
+			return -EINVAL;
+		}
+		svc_priv->svc_desc.num_vld_vnis = 1;
+	}
+
+	for (i = 0; i < svc_priv->svc_desc.num_vld_vnis; i++) {
+		struct cxi_tx_attr tx_attr = {};
+		struct cxi_rx_attr rx_attr = {};
+		struct cxi_rxtx_vni_attr restricted_vni_attr = {
+			.ignore = 0,
+			.match = svc_desc->vnis[i],
+			.name = "",
+		};
+
+		vni_attr = &restricted_vni_attr;
+		if (!svc_desc->restricted_vnis)
+			vni_attr = vni_range_attr;
+
+		tx_attr.vni_attr = *vni_attr;
+		rx_attr.vni_attr = *vni_attr;
+
+		svc_priv->tx_profile[i] = cxi_dev_alloc_tx_profile(dev,
+								   &tx_attr);
+		if (IS_ERR(svc_priv->tx_profile[i])) {
+			rc = PTR_ERR(svc_priv->tx_profile[i]);
+			svc_priv->tx_profile[i] = NULL;
+			goto release_profiles;
+		}
+
+		svc_priv->rx_profile[i] = cxi_dev_alloc_rx_profile(dev,
+								   &rx_attr);
+		if (IS_ERR(svc_priv->rx_profile[i])) {
+			rc = PTR_ERR(svc_priv->rx_profile[i]);
+			svc_priv->rx_profile[i] = NULL;
+			goto release_profiles;
+		}
+	}
+
+	rc = alloc_profile_ac_entries(dev, svc_priv);
+	if (rc)
+		goto release_profiles;
+
+	set_tcs(dev, svc_priv);
+
+	return 0;
+
+release_profiles:
+	release_rxtx_profiles(dev, svc_priv);
+	return rc;
+}
+
+static int svc_enable(struct cxi_dev *dev, struct cxi_svc_priv *svc_priv,
+		      bool enable)
+	__must_hold(&hw->svc_lock)
+{
+	int i;
+	int rc = 0;
+
+	if (enable) {
+		cxi_rgroup_enable(svc_priv->rgroup);
+		svc_priv->svc_desc.enable = 1;
+
+		for (i = 0; i < svc_priv->svc_desc.num_vld_vnis; i++) {
+			rc = cxi_tx_profile_enable(dev,
+						   svc_priv->tx_profile[i]);
+			if (rc)
+				goto disable;
+
+			rc = cxi_rx_profile_enable(dev,
+						   svc_priv->rx_profile[i]);
+			if (rc)
+				goto disable;
+		}
+
+		return 0;
+	}
+
+disable:
+	cxi_rgroup_disable(svc_priv->rgroup);
+	svc_priv->svc_desc.enable = 0;
+
+	for (i = 0; i < svc_priv->svc_desc.num_vld_vnis; i++) {
+		cxi_tx_profile_disable(dev, svc_priv->tx_profile[i]);
+		cxi_rx_profile_disable(dev, svc_priv->rx_profile[i]);
+	}
+
+	return rc;
+}
+
+/**
+ * cxi_svc_alloc() - Allocate a service
+ *
+ * @dev: Cassini Device
+ * @svc_desc: A service descriptor that contains requests for various resources,
+ *            and optionally identifies member processes, tcs, vnis, etc. see
+ *            cxi_svc_desc.
+ * @fail_info: extra information when a failure occurs
+ * @name: name for service
+ *
+ * Return: Service ID on success. Else, negative errno value.
+ */
+int cxi_svc_alloc(struct cxi_dev *dev, const struct cxi_svc_desc *svc_desc,
+		  struct cxi_svc_fail_info *fail_info, char *name)
+{
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+	struct cxi_svc_priv *svc_priv;
+	int rc;
+	struct cxi_rgroup *rgroup;
+	struct cxi_rgroup_attr attr = {
+		.id = svc_desc->svc_id,
+		.cntr_pool_id = svc_desc->cntr_pool_id,
+		.system_service = svc_desc->is_system_svc,
+		.lnis_per_rgid = default_lnis_per_rgid,
+	};
+
+	/* Service allocation is not allowed in VF */
+	if (!dev->is_physfn)
+		return -EPERM;
+
+	rc = validate_descriptor(hw, svc_desc);
+	if (rc)
+		return rc;
+
+	svc_priv = kzalloc(sizeof(*svc_priv), GFP_KERNEL);
+	if (!svc_priv)
+		return -ENOMEM;
+	svc_priv->svc_desc = *svc_desc;
+
+	rgroup = cxi_dev_alloc_rgroup(dev, &attr);
+	if (IS_ERR(rgroup)) {
+		rc = PTR_ERR(rgroup);
+		goto free_svc;
+	}
+
+	svc_priv->rgroup = rgroup;
+	svc_priv->svc_desc.svc_id = cxi_rgroup_id(rgroup);
+
+	rc = idr_alloc(&hw->svc_ids, svc_priv, cxi_rgroup_id(rgroup),
+		       cxi_rgroup_id(rgroup) + 1,
+		       GFP_NOWAIT);
+	if (rc < 0) {
+		cxidev_err(&hw->cdev, "%s Service idr could not be obtained for rgroup ID %d rc:%d\n",
+			   hw->cdev.name, cxi_rgroup_id(rgroup), rc);
+		goto release_rgroup;
+	}
+
+	cxi_rgroup_set_name(rgroup, name);
+
+	if (svc_desc->is_system_svc)
+		cxi_rgroup_set_lnis_per_rgid(svc_priv->rgroup, 1);
+
+	rc = alloc_rgroup_ac_entries(dev, svc_priv);
+	if (rc)
+		goto remove_idr;
+
+	/* If restricted_vnis is set setup profiles now. Otherwise they will
+	 * set up later when a vni range is requested
+	 */
+	if (svc_desc->restricted_vnis) {
+		rc = alloc_rxtx_profiles(dev, svc_priv, NULL);
+		if (rc)
+			goto remove_rgrp_ac_entries;
+	}
+
+	mutex_lock(&hw->svc_lock);
+	rc = reserve_rsrcs(hw, svc_priv, fail_info);
+	if (rc)
+		goto unlock;
+
+	/* SVC is enabled by default for backwards compatibility.
+	 * If disable_default_svc is true, the default service
+	 * will be disabled.
+	 * Setting restricted_vnis = 0 now indicates that a
+	 * VNI range will be set up after the service is enabled.
+	 * Do not enable the svc/rgroup/profiles until then.
+	 */
+	if (((cxi_rgroup_id(rgroup) == CXI_DEFAULT_SVC_ID) &&
+	     disable_default_svc) ||
+	    !svc_desc->restricted_vnis) {
+		svc_priv->svc_desc.enable = 0;
+	} else {
+		rc = svc_enable(dev, svc_priv, true);
+		if (rc)
+			goto free_resources;
+	}
+
+	list_add_tail(&svc_priv->list, &hw->svc_list);
+	hw->svc_count++;
+	mutex_unlock(&hw->svc_lock);
+	refcount_inc(&hw->refcount);
+
+	return cxi_rgroup_id(rgroup);
+
+free_resources:
+	free_rsrcs(svc_priv);
+unlock:
+	mutex_unlock(&hw->svc_lock);
+	if (svc_desc->restricted_vnis)
+		release_rxtx_profiles(dev, svc_priv);
+remove_rgrp_ac_entries:
+	cxi_ac_entry_list_destroy(&svc_priv->rgroup->ac_entry_list);
+remove_idr:
+	idr_remove(&hw->svc_ids, cxi_rgroup_id(rgroup));
+release_rgroup:
+	cxi_rgroup_dec_refcount(rgroup);
+	return rc;
+free_svc:
+	kfree(svc_priv);
+
+	return rc;
+}
+EXPORT_SYMBOL(cxi_svc_alloc);
+
+static void svc_destroy(struct cass_dev *hw, struct cxi_svc_priv *svc_priv)
+{
+	int rc;
+	int svc_id = cxi_rgroup_id(svc_priv->rgroup);
+
+	free_rsrcs(svc_priv);
+
+	release_rxtx_profiles(&hw->cdev, svc_priv);
+
+	rc = cxi_rgroup_dec_refcount(svc_priv->rgroup);
+	if (rc)
+		pr_err("cxi_dev_release_rgroup_by_id failed %d\n", rc);
+
+	idr_remove(&hw->svc_ids, svc_id);
+	list_del(&svc_priv->list);
+	hw->svc_count--;
+
+	refcount_dec(&hw->refcount);
+	kfree(svc_priv);
+}
+
+/**
+ * cxi_svc_destroy() - Destroy a service
+ *
+ * @dev: Cassini Device
+ * @svc_id: Service ID of service to be destroyed.
+ *
+ * Return: 0 on success. Else a negative errno value.
+ */
+int cxi_svc_destroy(struct cxi_dev *dev, u32 svc_id)
+{
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+	struct cxi_svc_priv *svc_priv;
+
+	/* Service allocation is not allowed in VF */
+	if (!dev->is_physfn)
+		return -EPERM;
+
+	/* Don't destroy default svc */
+	if (svc_id == CXI_DEFAULT_SVC_ID)
+		return -EINVAL;
+
+	mutex_lock(&hw->svc_lock);
+
+	svc_priv = idr_find(&hw->svc_ids, svc_id);
+	if (!svc_priv) {
+		mutex_unlock(&hw->svc_lock);
+		return -EINVAL;
+	}
+
+	/* Don't delete if an LNI is still using this SVC */
+	if (cxi_rgroup_refcount(svc_priv->rgroup) > 1) {
+		mutex_unlock(&hw->svc_lock);
+		return -EBUSY;
+	}
+
+	svc_destroy(hw, svc_priv);
+
+	mutex_unlock(&hw->svc_lock);
+
+	return 0;
+}
+EXPORT_SYMBOL(cxi_svc_destroy);
+
+static int cxi_svc_rsrc_list_get_vf(struct cxi_dev *dev, int count,
+				    struct cxi_rsrc_use *rsrc_list)
+{
+	const struct cxi_svc_rsrc_list_get_cmd cmd = {
+		.op = CXI_OP_SVC_RSRC_LIST_GET,
+		.count = count,
+	};
+	struct cxi_svc_rsrc_list_get_resp_vf *resp;
+	size_t resp_len = sizeof(struct cxi_svc_rsrc_list_get_resp_vf) +
+			  count * sizeof(struct cxi_rsrc_use);
+	int rc;
+
+	resp = kzalloc(resp_len, GFP_KERNEL);
+	if (!resp)
+		return -ENOMEM;
+
+	rc = cxi_send_msg_to_pf(dev, &cmd, sizeof(cmd), resp, &resp_len);
+	if (rc)
+		goto free_buf;
+
+	if (count >= resp->base.count)
+		memcpy(rsrc_list, resp->rsrc_list,
+		       resp->base.count * sizeof(struct cxi_rsrc_use));
+	rc = resp->base.count;
+free_buf:
+	kfree(resp);
+	return rc;
+}
+
+/*
+ * cxi_svc_rsrc_list_get - Get per service information on resource usage.
+ *
+ * @dev: Cassini Device
+ * @count: number of services descriptors for which space
+ *         has been allocated. 0 initially, to determine count.
+ * @rsrc_list: destination to land service descriptors
+ *
+ * Return: number of service descriptors
+ * If the specified count is equal to (or greater than) the number of
+ * active service descriptors, they are copied to the provided user
+ * buffer.
+ */
+int cxi_svc_rsrc_list_get(struct cxi_dev *dev, int count,
+			  struct cxi_rsrc_use *rsrc_list)
+{
+
+	int i = 0;
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+	unsigned int rgroup_count;
+	unsigned long index;
+	struct cxi_rgroup *rgroup;
+
+	if (!dev->is_physfn)
+		return cxi_svc_rsrc_list_get_vf(dev, count, rsrc_list);
+
+	mutex_lock(&hw->svc_lock);
+	cxi_dev_lock_rgroup_list(hw);
+
+	rgroup_count = cxi_dev_get_rgroup_count(dev);
+	if (count < rgroup_count) {
+		cxi_dev_unlock_rgroup_list(hw);
+		mutex_unlock(&hw->svc_lock);
+		return rgroup_count;
+	}
+
+	for_each_rgroup(index, rgroup) {
+		if (i >= rgroup_count) {
+			pr_debug("Found more rgroups than expected: %u\n", rgroup_count);
+			break;
+		}
+
+		copy_rsrc_use(dev, &rsrc_list[i], rgroup);
+		rsrc_list[i].svc_id = rgroup->id;
+		i++;
+	}
+
+	cxi_dev_unlock_rgroup_list(hw);
+	mutex_unlock(&hw->svc_lock);
+
+	return i;
+}
+EXPORT_SYMBOL(cxi_svc_rsrc_list_get);
+
+static int cxi_svc_rsrc_get_vf(struct cxi_dev *dev, unsigned int svc_id,
+			       struct cxi_rsrc_use *rsrc_use)
+{
+	const struct cxi_svc_rsrc_get_cmd cmd = {
+		.op = CXI_OP_SVC_RSRC_GET,
+		.svc_id = svc_id,
+	};
+	struct cxi_svc_rsrc_get_resp resp = {};
+	size_t resp_len = sizeof(resp);
+	int rc;
+
+	rc = cxi_send_msg_to_pf(dev, &cmd, sizeof(cmd), &resp, &resp_len);
+	if (rc)
+		return rc;
+
+	*rsrc_use = resp.rsrcs;
+
+	return 0;
+}
+
+/*
+ * cxi_svc_rsrc_get - Get rsrc_use from svc_id
+ *
+ * @dev: Cassini Device
+ * @svc_id: svc_id of the descriptor to find which is equivalent to the
+ *          rgroup ID.
+ * @rsrc_use: destination to land resource usage
+ *
+ * Return: 0 on success or a negative errno
+ */
+int cxi_svc_rsrc_get(struct cxi_dev *dev, unsigned int svc_id,
+		     struct cxi_rsrc_use *rsrc_use)
+{
+	int rc;
+	struct cxi_rgroup *rgroup;
+
+	if (!dev->is_physfn)
+		return cxi_svc_rsrc_get_vf(dev, svc_id, rsrc_use);
+
+	rc = cxi_dev_find_rgroup_inc_refcount(dev, svc_id, &rgroup);
+	if (rc)
+		return -EINVAL;
+
+	copy_rsrc_use(dev, rsrc_use, rgroup);
+	cxi_rgroup_dec_refcount(rgroup);
+
+	return 0;
+}
+EXPORT_SYMBOL(cxi_svc_rsrc_get);
+
+static enum cxi_svc_member_type ac_type_to_svc_mbr(enum cxi_ac_type type)
+{
+	switch (type) {
+	case CXI_AC_UID:
+		return CXI_SVC_MEMBER_UID;
+	case CXI_AC_GID:
+		return CXI_SVC_MEMBER_GID;
+	default:
+		return CXI_SVC_MEMBER_IGNORE;
+	}
+}
+
+static void add_rgroup_ac_entry_to_svc(struct cxi_svc_desc *desc,
+				       struct cxi_rgroup *rgroup)
+{
+	int i;
+	int rc;
+	size_t num_ids;
+	size_t max_ids;
+	unsigned int *ac_entry_ids = NULL;
+	enum cxi_ac_type ac_type;
+	union cxi_ac_data ac_data;
+
+	desc->restricted_members = false;
+
+	rc = cxi_rgroup_get_ac_entry_ids(rgroup, 0, ac_entry_ids, &num_ids);
+	if (rc && rc != -ENOSPC)
+		return;
+
+	ac_entry_ids = kmalloc_array(num_ids, sizeof(*ac_entry_ids),
+				     GFP_ATOMIC);
+	if (!ac_entry_ids)
+		return;
+
+	rc = cxi_rgroup_get_ac_entry_ids(rgroup, num_ids, ac_entry_ids,
+					 &max_ids);
+	if (rc)
+		goto freemem;
+
+	for (i = 0; i < num_ids; i++) {
+		rc = cxi_rgroup_get_ac_entry_data(rgroup, ac_entry_ids[i],
+						  &ac_type, &ac_data);
+		if (rc || ac_type == CXI_AC_OPEN)
+			goto freemem;
+	}
+
+	desc->restricted_members = true;
+	for (i = 0; i < num_ids && i < CXI_SVC_MAX_MEMBERS; i++) {
+		rc = cxi_rgroup_get_ac_entry_data(rgroup, ac_entry_ids[i],
+						  &ac_type, &ac_data);
+		if (rc)
+			continue;
+
+		desc->members[i].type = ac_type_to_svc_mbr(ac_type);
+		desc->members[i].svc_member.uid = ac_data.uid;
+	}
+
+freemem:
+	kfree(ac_entry_ids);
+}
+
+static int cxi_svc_list_get_vf(struct cxi_dev *dev, int count,
+			       struct cxi_svc_desc *svc_list)
+{
+	const struct cxi_svc_list_get_cmd cmd = {
+		.op = CXI_OP_SVC_LIST_GET,
+		.count = count,
+	};
+	struct cxi_svc_list_get_resp_vf *resp;
+	size_t resp_len = sizeof(struct cxi_svc_list_get_resp_vf) +
+			  count * sizeof(struct cxi_svc_desc);
+	int rc;
+
+	resp = kzalloc(resp_len, GFP_KERNEL);
+	if (!resp)
+		return -ENOMEM;
+
+	rc = cxi_send_msg_to_pf(dev, &cmd, sizeof(cmd), resp, &resp_len);
+	if (rc)
+		goto free_buf;
+
+	if (count >= resp->base.count)
+		memcpy(svc_list, resp->svc_list,
+		       resp->base.count * sizeof(struct cxi_svc_desc));
+
+	rc = resp->base.count;
+free_buf:
+	kfree(resp);
+	return rc;
+}
+
+/*
+ * cxi_svc_list_get - Assemble list of active services descriptors
+ *
+ * @dev: Cassini Device
+ * @count: number of services descriptors for which space
+ *         has been allocated. 0 initially, to determine count.
+ * @svc_list: destination to land service descriptors
+ *
+ * Return: number of service descriptors
+ * If the specified count is equal to (or greater than) the number of
+ * active service descriptors, they are copied to the provided user
+ * buffer.
+ */
+int cxi_svc_list_get(struct cxi_dev *dev, int count,
+		     struct cxi_svc_desc *svc_list)
+{
+
+	int i = 0;
+	int ret;
+	enum cxi_resource_type rt;
+	enum cxi_rsrc_type svc_rt;
+	unsigned int rgroup_count;
+	struct cxi_svc_priv *svc_priv;
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+	struct cxi_svc_desc rgroup_svc_desc;
+	unsigned long index;
+	struct cxi_rgroup *rgroup;
+	struct cxi_resource_entry *entry;
+
+	if (!dev->is_physfn)
+		return cxi_svc_list_get_vf(dev, count, svc_list);
+
+	mutex_lock(&hw->svc_lock);
+	cxi_dev_lock_rgroup_list(hw);
+
+	rgroup_count = cxi_dev_get_rgroup_count(dev);
+	if (count < rgroup_count) {
+		cxi_dev_unlock_rgroup_list(hw);
+		mutex_unlock(&hw->svc_lock);
+		return rgroup_count;
+	}
+
+	for_each_rgroup(index, rgroup) {
+		svc_priv = idr_find(&hw->svc_ids, cxi_rgroup_id(rgroup));
+		if (svc_priv) {
+			svc_list[i++] = svc_priv->svc_desc;
+			continue;
+		}
+
+		memset(&rgroup_svc_desc, 0, sizeof(rgroup_svc_desc));
+		rgroup_svc_desc.svc_id = rgroup->id;
+		rgroup_svc_desc.enable = rgroup->state.enabled;
+		rgroup_svc_desc.resource_limits = true;
+		rgroup_svc_desc.is_system_svc =
+					cxi_rgroup_system_service(rgroup);
+		add_rgroup_ac_entry_to_svc(&rgroup_svc_desc, rgroup);
+
+		for (rt = 1, svc_rt = 0; rt < CXI_RESOURCE_MAX; rt++) {
+			ret = cxi_rgroup_get_resource_entry(rgroup, rt,
+							    &entry);
+			if (!ret) {
+				if (svc_rt == CXI_RSRC_TYPE_MAX)
+					break;
+
+				if (rt == CXI_RESOURCE_PE1_LE ||
+				    rt == CXI_RESOURCE_PE2_LE ||
+				    rt == CXI_RESOURCE_PE3_LE)
+					continue;
+
+				rgroup_svc_desc.limits.type[svc_rt].max =
+							entry->limits.max;
+				rgroup_svc_desc.limits.type[svc_rt].res =
+							entry->limits.reserved;
+			}
+			svc_rt++;
+		}
+		svc_list[i++] = rgroup_svc_desc;
+	}
+
+	cxi_dev_unlock_rgroup_list(hw);
+	mutex_unlock(&hw->svc_lock);
+	return i;
+}
+EXPORT_SYMBOL(cxi_svc_list_get);
+
+/* cxi_svc_get_vf - Get svc_desc from svc_id for a VF
+ *
+ * @dev: Cassini Device
+ * @svc_id: svc_id of the descriptor to find which is equivalent to the
+ *          rgroup ID.
+ * @svc_desc: destination to land service descriptor
+ *
+ * Return: 0 on success or a negative errno
+ */
+static int cxi_svc_get_vf(struct cxi_dev *dev, unsigned int svc_id,
+			  struct cxi_svc_desc *svc_desc)
+{
+	const struct cxi_svc_get_cmd cmd = {
+		.op = CXI_OP_SVC_GET,
+		.svc_id = svc_id,
+	};
+	struct cxi_svc_get_resp resp;
+	size_t resp_len = sizeof(resp);
+	int rc;
+
+	rc = cxi_send_msg_to_pf(dev, &cmd, sizeof(cmd), &resp, &resp_len);
+	if (rc)
+		return rc;
+
+	*svc_desc = resp.svc_desc;
+
+	return 0;
+}
+
+/*
+ * cxi_svc_get - Get svc_desc from svc_id
+ *
+ * @dev: Cassini Device
+ * @svc_id: svc_id of the descriptor to find which is equivalent to the
+ *          rgroup ID.
+ * @svc_desc: destination to land service descriptor
+ *
+ * Return: 0 on success or a negative errno
+ */
+int cxi_svc_get(struct cxi_dev *dev, unsigned int svc_id,
+		struct cxi_svc_desc *svc_desc)
+{
+	struct cxi_svc_priv *svc_priv;
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+
+	if (!dev->is_physfn)
+		return cxi_svc_get_vf(dev, svc_id, svc_desc);
+
+	mutex_lock(&hw->svc_lock);
+
+	/* Find priv descriptor */
+	svc_priv = idr_find(&hw->svc_ids, svc_id);
+	if (!svc_priv) {
+		mutex_unlock(&hw->svc_lock);
+		return -EINVAL;
+	}
+
+	*svc_desc = svc_priv->svc_desc;
+	mutex_unlock(&hw->svc_lock);
+
+	return 0;
+}
+EXPORT_SYMBOL(cxi_svc_get);
+
+void cxi_free_resource(struct cxi_dev *dev, struct cxi_svc_priv *svc_priv,
+		       enum cxi_rsrc_type type)
+{
+	return cxi_rgroup_free_resource(svc_priv->rgroup,
+					stype_to_rtype(type, 0));
+}
+
+/* used to allocate ACs, etc. */
+int cxi_alloc_resource(struct cxi_dev *dev, struct cxi_svc_priv *svc_priv,
+		       enum cxi_rsrc_type type)
+{
+	return cxi_rgroup_alloc_resource(svc_priv->rgroup,
+					 stype_to_rtype(type, 0));
+}
+
+/**
+ * cxi_svc_enable() - Enable or Disable a service.
+ *
+ * @dev: Cassini Device
+ * @svc_id: Service ID of the service to be enabled.
+ * @enable: Boolean value indicating whether to enable or disable the service.
+ *
+ * Return: 0 on success or negative errno value.
+ */
+int cxi_svc_enable(struct cxi_dev *dev, unsigned int svc_id, bool enable)
+{
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+	struct cxi_svc_priv *svc_priv;
+	int rc = 0;
+
+	if (!dev->is_physfn)
+		return -EPERM;
+
+	mutex_lock(&hw->svc_lock);
+
+	svc_priv = idr_find(&hw->svc_ids, svc_id);
+	if (!svc_priv) {
+		rc = -EINVAL;
+		cxidev_err(dev, "Invalid service ID: %u\n", svc_id);
+		goto unlock;
+	}
+
+	/* Service must be unused for it to be enabled/disabled. */
+	if (refcount_read(&svc_priv->rgroup->state.refcount) > 1) {
+		rc = -EBUSY;
+		goto unlock;
+	}
+
+	rc = svc_enable(dev, svc_priv, enable);
+unlock:
+	mutex_unlock(&hw->svc_lock);
+	return rc;
+}
+EXPORT_SYMBOL(cxi_svc_enable);
+
+/**
+ * cxi_svc_update() - Modify an existing service.
+ *
+ * @dev: Cassini Device
+ * @svc_desc: A service descriptor that contains requests for various resources,
+ *            and optionally identifies member processes, tcs, vnis, etc. see
+ *            cxi_svc_desc.
+ *
+ * Currently does not honor changes to resource limits in a svc_desc.
+ *
+ * Return: 0 on success. Else, negative errno value.
+ */
+int cxi_svc_update(struct cxi_dev *dev, const struct cxi_svc_desc *svc_desc)
+{
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+	struct cxi_svc_priv *svc_priv;
+	int rc;
+
+	if (!dev->is_physfn)
+		return -EPERM;
+
+	rc = validate_descriptor(hw, svc_desc);
+	if (rc)
+		return rc;
+
+	mutex_lock(&hw->svc_lock);
+
+	/* Find priv descriptor */
+	svc_priv = idr_find(&hw->svc_ids, svc_desc->svc_id);
+	if (!svc_priv) {
+		rc = -EINVAL;
+		goto error;
+	}
+
+	/* Service must be unused for it to be updated. */
+	if (refcount_read(&svc_priv->rgroup->state.refcount) > 1) {
+		rc = -EBUSY;
+		goto error;
+	}
+
+	/* TODO Handle Resource Reservation Changes */
+	if (svc_priv->svc_desc.resource_limits != svc_desc->resource_limits) {
+		rc = -EINVAL;
+		goto error;
+	}
+
+	rc = svc_enable(dev, svc_priv, svc_desc->enable);
+	if (rc)
+		goto error;
+
+	/* Update TCs, VNIs, Members */
+	svc_priv->svc_desc.restricted_members = svc_desc->restricted_members;
+	svc_priv->svc_desc.restricted_vnis = svc_desc->restricted_vnis;
+	svc_priv->svc_desc.num_vld_vnis = svc_desc->num_vld_vnis;
+	svc_priv->svc_desc.restricted_tcs = svc_desc->restricted_tcs;
+	svc_priv->svc_desc.cntr_pool_id = svc_desc->cntr_pool_id;
+	svc_priv->svc_desc.enable = svc_desc->enable;
+
+	memcpy(svc_priv->svc_desc.tcs, svc_desc->tcs, sizeof(svc_desc->tcs));
+	memcpy(svc_priv->svc_desc.vnis, svc_desc->vnis, sizeof(svc_desc->vnis));
+	memcpy(svc_priv->svc_desc.members, svc_desc->members, sizeof(svc_desc->members));
+	// TODO: update TX profile?
+error:
+	mutex_unlock(&hw->svc_lock);
+	return rc;
+}
+EXPORT_SYMBOL(cxi_svc_update);
+
+int cxi_job_tc_bind(struct cxi_dev *dev, unsigned int job_id,
+		    unsigned int svc_id, unsigned int tc,
+		    enum cxi_traffic_class_type tc_type, bool create_tc,
+		    const struct cxi_rsrc_limits *limits,
+		    unsigned int *bound_svc_id, bool *created_tc)
+{
+	struct cxi_svc_desc svc_desc = {};
+	struct cxi_svc_fail_info fail_info = {};
+	int ret;
+
+	if (!dev->is_physfn)
+		return -EPERM;
+	if (!is_vni_valid(job_id))
+		return -EINVAL;
+	if (tc >= CXI_TC_MAX || tc_type >= CXI_TC_TYPE_MAX)
+		return -EINVAL;
+	if (created_tc)
+		*created_tc = false;
+
+	if (create_tc) {
+		ret = cxi_tc_cfg(dev, tc, tc_type);
+		if (ret && ret != -EEXIST)
+			return ret;
+		if (!ret && created_tc)
+			*created_tc = true;
+	} else {
+		ret = cxi_tc_validate(dev, tc, tc_type);
+		if (ret)
+			return ret;
+	}
+
+	svc_desc.svc_id = svc_id;
+	svc_desc.restricted_vnis = true;
+	svc_desc.num_vld_vnis = 1;
+	svc_desc.vnis[0] = job_id;
+	svc_desc.restricted_tcs = true;
+	svc_desc.tcs[tc] = true;
+	svc_desc.resource_limits = true;
+	svc_desc.enable = true;
+	if (limits)
+		svc_desc.limits = *limits;
+
+	ret = cxi_svc_alloc(dev, &svc_desc, &fail_info, "uet-job-tc");
+	if (ret < 0)
+		return ret;
+
+	if (bound_svc_id)
+		*bound_svc_id = ret;
+
+	return 0;
+}
+EXPORT_SYMBOL(cxi_job_tc_bind);
+
+/**
+ * cxi_svc_set_lpr() - Update an existing service to set the LNIs per RGID
+ *
+ * For backwards compatibility, check if service is in use instead of
+ * checking if rgroup is enabled.
+ *
+ * @dev: Cassini Device
+ * @svc_id: Service ID of service to be updated.
+ * @lnis_per_rgid: New value of lnis_per_rgid
+ *
+ * Return: 0 on success or negative errno value.
+ */
+int cxi_svc_set_lpr(struct cxi_dev *dev, unsigned int svc_id,
+		    unsigned int lnis_per_rgid)
+{
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+	struct cxi_svc_priv *svc_priv;
+
+	if (!dev->is_physfn)
+		return -EPERM;
+
+	if (lnis_per_rgid > C_NUM_LACS)
+		return -EINVAL;
+
+	if (!enable_rgid_sharing) {
+		cxidev_warn(dev, "RGID sharing is disabled\n");
+		return 0;
+	}
+
+	mutex_lock(&hw->svc_lock);
+
+	svc_priv = idr_find(&hw->svc_ids, svc_id);
+	if (!svc_priv) {
+		mutex_unlock(&hw->svc_lock);
+		return -EINVAL;
+	}
+
+	/* Service must be unused for it to be updated. */
+	if (cxi_rgroup_refcount(svc_priv->rgroup) > 1) {
+		mutex_unlock(&hw->svc_lock);
+		return -EBUSY;
+	}
+
+	cxi_rgroup_set_lnis_per_rgid_compat(svc_priv->rgroup, lnis_per_rgid);
+
+	mutex_unlock(&hw->svc_lock);
+
+	return 0;
+}
+EXPORT_SYMBOL(cxi_svc_set_lpr);
+
+static int cxi_svc_get_lpr_vf(struct cxi_dev *dev, unsigned int svc_id)
+{
+	const struct cxi_svc_lpr_cmd cmd = {
+		.op = CXI_OP_SVC_GET_LPR,
+		.svc_id = svc_id,
+	};
+	struct cxi_svc_get_value_resp resp = {};
+	size_t resp_len = sizeof(resp);
+	int rc;
+
+	rc = cxi_send_msg_to_pf(dev, &cmd, sizeof(cmd), &resp, &resp_len);
+	if (rc)
+		return rc;
+
+	return resp.value;
+}
+
+/**
+ * cxi_svc_get_lpr() - Get the LNIs per RGID of the indicated service
+ *
+ * @dev: Cassini Device
+ * @svc_id: Service ID of service to be updated.
+ *
+ * Return: lnis_per_rgid on success or negative errno value.
+ */
+int cxi_svc_get_lpr(struct cxi_dev *dev, unsigned int svc_id)
+{
+	struct cxi_rgroup *rgroup;
+	int ret;
+
+	if (!dev->is_physfn)
+		return cxi_svc_get_lpr_vf(dev, svc_id);
+
+	ret = cxi_dev_find_rgroup_inc_refcount(dev, svc_id, &rgroup);
+	if (ret)
+		return -EINVAL;
+
+	ret = cxi_rgroup_lnis_per_rgid(rgroup);
+	cxi_rgroup_dec_refcount(rgroup);
+
+	return ret;
+}
+EXPORT_SYMBOL(cxi_svc_get_lpr);
+
+/**
+ * cxi_svc_set_exclusive_cp() - Set the exclusive_cp bit for a service
+ *
+ * @dev: Cassini Device
+ * @svc_id: Service ID of service to be updated.
+ * @exclusive_cp: New value for exclusive_cp (true or false)
+ *
+ * Return: 0 on success or negative errno value.
+ */
+int cxi_svc_set_exclusive_cp(struct cxi_dev *dev, unsigned int svc_id,
+			     bool exclusive_cp)
+{
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+	struct cxi_svc_priv *svc_priv;
+	int rc;
+
+	if (!dev->is_physfn)
+		return -EPERM;
+
+	mutex_lock(&hw->svc_lock);
+
+	svc_priv = idr_find(&hw->svc_ids, svc_id);
+	if (!svc_priv) {
+		rc = -EINVAL;
+		goto unlock;
+	}
+
+	if (svc_priv->svc_desc.restricted_vnis) {
+		cxidev_err(dev, "Exclusive CP not allowed with restricted VNIs\n");
+		rc = -EINVAL;
+		goto unlock;
+	}
+
+	/* One VNI Range will be allowed, tied to tx_profile 0.
+	 * This call will fail if the svc/tx_profile is already enabled
+	 */
+	if (!svc_priv->tx_profile[0]) {
+		cxidev_err(dev, "tx_profile[0] not initialized for svc_id: %d\n",
+			   svc_id);
+		rc = -EINVAL;
+		goto unlock;
+	}
+
+	rc = cxi_tx_profile_set_exclusive_cp(svc_priv->tx_profile[0],
+					     exclusive_cp);
+	if (rc)
+		cxidev_err(dev, "Failed to set exclusive CP for svc_id: %d rc:%d\n",
+			   svc_id, rc);
+
+unlock:
+	mutex_unlock(&hw->svc_lock);
+	return rc;
+}
+EXPORT_SYMBOL(cxi_svc_set_exclusive_cp);
+
+static int cxi_svc_get_exclusive_cp_vf(struct cxi_dev *dev, unsigned int svc_id)
+{
+	const struct cxi_svc_get_exclusive_cp_cmd cmd = {
+		.op = CXI_OP_SVC_GET_EXCLUSIVE_CP,
+		.svc_id = svc_id,
+	};
+	struct cxi_svc_get_exclusive_cp_resp resp = {};
+	size_t resp_len = sizeof(resp);
+	int rc;
+
+	rc = cxi_send_msg_to_pf(dev, &cmd, sizeof(cmd), &resp, &resp_len);
+	if (rc)
+		return rc;
+
+	return resp.exclusive_cp ? 1 : 0;
+}
+
+/**
+ * cxi_svc_get_exclusive_cp() - Get the exclusive_cp bit for a service
+ *
+ * @dev: Cassini Device
+ * @svc_id: Service ID of service to query.
+ *
+ * Return: 1 if exclusive_cp is set, 0 if not, or negative errno value.
+ */
+int cxi_svc_get_exclusive_cp(struct cxi_dev *dev, unsigned int svc_id)
+{
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+	struct cxi_svc_priv *svc_priv;
+	int rc;
+
+	if (!dev->is_physfn)
+		return cxi_svc_get_exclusive_cp_vf(dev, svc_id);
+
+	mutex_lock(&hw->svc_lock);
+
+	svc_priv = idr_find(&hw->svc_ids, svc_id);
+	if (!svc_priv) {
+		rc = -EINVAL;
+		goto unlock;
+	}
+
+	if (!svc_priv->tx_profile[0]) {
+		rc = -ENOENT;
+		goto unlock;
+	}
+
+	/* Grab the first TX Profile and report its exclusive_cp value */
+	rc = cxi_tx_profile_exclusive_cp(svc_priv->tx_profile[0]);
+unlock:
+	mutex_unlock(&hw->svc_lock);
+
+	return rc;
+}
+EXPORT_SYMBOL(cxi_svc_get_exclusive_cp);
+
+/**
+ * cxi_svc_set_vni_range() - Add TX/RX profiles for a contiguous range of VNIs to a service
+ *
+ * The provided range must be exactly representable as a mask/match pair.
+ * Requirements:
+ *   - The number of values in the range must be a power of two (1, 2, 4, 8, 16, ...).
+ *   - The first value in the range (vni_min) must be a multiple of the range size.
+ *   - The svc must not have the restricted_vnis bit set.
+ *
+ * For example:
+ *   64–127: 64 values, starting value (64) is a multiple of the
+ *           range size (64), so the range is valid.
+ *   32–95 : 64 values, starting value (32) is not a multiple of the
+ *           range size (64), so the range is invalid.
+ *
+ * @dev: Cassini Device
+ * @svc_id: Service ID of service to be updated.
+ * @vni_min: Minimum VNI value (inclusive)
+ * @vni_max: Maximum VNI value (inclusive)
+ *
+ * Return: 0 on success, or negative errno value on failure.
+ */
+int cxi_svc_set_vni_range(struct cxi_dev *dev, unsigned int svc_id,
+			  unsigned int vni_min, unsigned int vni_max)
+{
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+	struct cxi_svc_priv *svc_priv;
+	struct cxi_rxtx_vni_attr vni_attr = {
+		.name = "",
+	};
+	unsigned int range;
+	int rc = 0;
+
+	if (!dev->is_physfn)
+		return -EPERM;
+
+	mutex_lock(&hw->svc_lock);
+
+	svc_priv = idr_find(&hw->svc_ids, svc_id);
+	if (!svc_priv) {
+		rc = -EINVAL;
+		goto unlock_return;
+	}
+
+	/* VNI range is incompatible with distinct VNIs */
+	if (svc_priv->svc_desc.restricted_vnis) {
+		cxidev_err(dev, "Cannot specify distinct VNIs and a VNI range");
+		rc = -EINVAL;
+		goto unlock_return;
+	}
+	if (!is_vni_valid(vni_min)) {
+		cxidev_err(dev, "vni_min %u invalid", vni_min);
+		rc = -EINVAL;
+		goto unlock_return;
+	}
+	if (!is_vni_valid(vni_max)) {
+		cxidev_err(dev, "vni_max %u invalid", vni_max);
+		rc = -EINVAL;
+		goto unlock_return;
+	}
+	if (vni_max < vni_min) {
+		cxidev_err(dev, "vni_max %u is less than vni_min %u",
+			   vni_max, vni_min);
+		rc = -EINVAL;
+		goto unlock_return;
+	}
+
+	range = vni_max - vni_min + 1;
+
+	if (!is_power_of_2(range)) {
+		cxidev_err(dev, "VNI range [%u, %u] is not a power-of-two size",
+			   vni_min, vni_max);
+		rc = -EINVAL;
+		goto unlock_return;
+	}
+	/* Validate the range is aligned */
+	if (vni_min & (range - 1)) {
+		cxidev_err(dev, "VNI range [%u, %u] is not aligned. min (%u) must be a multiple of range size (%u)",
+			   vni_min, vni_max, vni_min, range);
+		rc = -EINVAL;
+		goto unlock_return;
+	}
+
+	vni_attr.match = vni_min;
+	vni_attr.ignore = range - 1;
+
+	rc = alloc_rxtx_profiles(dev, svc_priv, &vni_attr);
+
+unlock_return:
+	mutex_unlock(&hw->svc_lock);
+	return rc;
+}
+EXPORT_SYMBOL(cxi_svc_set_vni_range);
+
+static int cxi_svc_get_vni_range_vf(struct cxi_dev *dev, unsigned int svc_id,
+				    unsigned int *vni_min, unsigned int *vni_max)
+{
+	const struct cxi_svc_vni_range_cmd cmd = {
+		.op = CXI_OP_SVC_GET_VNI_RANGE,
+		.svc_id = svc_id,
+	};
+	struct cxi_svc_get_vni_range_resp resp = {};
+	size_t resp_len = sizeof(resp);
+	int rc;
+
+	rc = cxi_send_msg_to_pf(dev, &cmd, sizeof(cmd), &resp, &resp_len);
+	if (rc)
+		return rc;
+
+	*vni_min = resp.vni_min;
+	*vni_max = resp.vni_max;
+
+	return 0;
+}
+
+/**
+ * cxi_svc_get_vni_range() - Get the VNI range associated with a service
+ *
+ * @dev: Cassini Device
+ * @svc_id: Service ID of service to query.
+ * @vni_min: Pointer to store minimum VNI value (inclusive)
+ * @vni_max: Pointer to store maximum VNI value (inclusive)
+ *
+ * Return: 0 on success, or negative errno value.
+ */
+int cxi_svc_get_vni_range(struct cxi_dev *dev, unsigned int svc_id,
+			  unsigned int *vni_min, unsigned int *vni_max)
+{
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+	struct cxi_svc_priv *svc_priv;
+	struct cxi_tx_attr tx_attr;
+	int rc = 0;
+	struct cxi_rgroup *rgroup;
+
+	if (!dev->is_physfn)
+		return cxi_svc_get_vni_range_vf(dev, svc_id, vni_min, vni_max);
+
+	mutex_lock(&hw->svc_lock);
+
+	svc_priv = idr_find(&hw->svc_ids, svc_id);
+	if (!svc_priv) {
+		rc = cxi_dev_find_rgroup_inc_refcount(dev, svc_id, &rgroup);
+		if (!rc) {
+			/* We don't support getting a VNI range for rgroups */
+			cxi_rgroup_dec_refcount(rgroup);
+			cxidev_dbg(dev, "svc_id %u is a rgroup", svc_id);
+			rc = -EOPNOTSUPP;
+			goto unlock_return;
+		}
+
+		cxidev_err(dev, "svc_id %u not found", svc_id);
+		rc = -EINVAL;
+		goto unlock_return;
+	}
+	if (svc_priv->svc_desc.restricted_vnis) {
+		cxidev_err(dev, "svc_id %u does not have a vni range", svc_id);
+		rc = -EINVAL;
+		goto unlock_return;
+	}
+	if (!svc_priv->svc_desc.num_vld_vnis) {
+		cxidev_err(dev, "svc_id %u has no valid TX/RX profiles", svc_id);
+		rc = -EINVAL;
+		goto unlock_return;
+	}
+
+	if (!svc_priv->tx_profile[0]) {
+		rc = -ENOENT;
+		goto unlock_return;
+	}
+
+	rc = cxi_tx_profile_get_info(dev, svc_priv->tx_profile[0], &tx_attr,
+				     NULL);
+	if (rc) {
+		cxidev_err(dev, "Failed to get TX profile info for svc_id %u",
+			   svc_id);
+		goto unlock_return;
+	}
+
+	*vni_min = tx_attr.vni_attr.match;
+	*vni_max = tx_attr.vni_attr.match + tx_attr.vni_attr.ignore;
+
+unlock_return:
+	mutex_unlock(&hw->svc_lock);
+	return rc;
+}
+EXPORT_SYMBOL(cxi_svc_get_vni_range);
+
+/**
+ * cxi_svc_set_netns() - Set netns Access control to existing service
+ *
+ * @dev: Cassini Device
+ * @svc_id: Service ID of service to be set.
+ * @netns: The Namespace id
+ * * Return:
+ * * 0       - success
+ * * -EEXIST - The service was originally created with a UID or GID,
+ * *           so netns access control cannot be applied
+ * * -EINVAL - The specified service does not exist
+ */
+int cxi_svc_set_netns(struct cxi_dev *dev, unsigned int svc_id, unsigned int netns)
+{
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+	struct cxi_svc_priv *svc_priv;
+	unsigned int ac_entry_id;
+	union cxi_ac_data ac_data = {};
+	struct cxi_ac_entry_list list = {};
+	int rc;
+
+	if (!dev->is_physfn)
+		return -EPERM;
+
+	mutex_lock(&hw->svc_lock);
+	svc_priv = idr_find(&hw->svc_ids, svc_id);
+	if (!svc_priv) {
+		rc = -EINVAL;
+		goto unlock_return;
+	}
+
+	/* Make sure that the ac list is empty.	 */
+	list = svc_priv->rgroup->ac_entry_list;
+	if (!xa_empty(&list.uid.xarray) || !xa_empty(&list.gid.xarray) || list.open_entry) {
+		cxidev_dbg(dev,
+			   "Failed to add netns for svc_id: %u (netns is not supported with uid/gid/open)",
+			   svc_id);
+		rc = -EEXIST;
+		goto unlock_return;
+	}
+
+	ac_data.netns = netns;
+
+	rc = cxi_rgroup_update_ac_entry(svc_priv->rgroup, CXI_AC_NETNS, &ac_data,
+					&ac_entry_id);
+	if (rc)
+		goto unlock_return;
+
+	rc = update_profile_netns_entries(dev, svc_priv, netns);
+	if (rc)
+		goto unlock_return;
+unlock_return:
+	mutex_unlock(&hw->svc_lock);
+	return rc;
+}
+EXPORT_SYMBOL(cxi_svc_set_netns);
+
+static int cxi_svc_get_netns_vf(struct cxi_dev *dev, unsigned int svc_id,
+				unsigned int *netns)
+{
+	const struct cxi_svc_get_netns_cmd cmd = {
+		.op = CXI_OP_SVC_GET_NETNS,
+		.svc_id = svc_id,
+	};
+	struct cxi_svc_get_value_resp resp = {};
+	size_t resp_len = sizeof(resp);
+	int rc;
+
+	rc = cxi_send_msg_to_pf(dev, &cmd, sizeof(cmd), &resp, &resp_len);
+	if (rc)
+		return rc;
+
+	*netns = resp.value;
+
+	return 0;
+}
+
+/**
+ * cxi_svc_get_netns() - Get the network namespace associated with a service
+ *
+ * @dev: Cassini Device
+ * @svc_id: Service ID of service to query.
+ * @netns: Pointer to store namespace ID
+ *
+ * Return: 0 on success, or negative errno value.
+ */
+int cxi_svc_get_netns(struct cxi_dev *dev, unsigned int svc_id,
+		      unsigned int *netns)
+{
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+	struct cxi_svc_priv *svc_priv;
+	union cxi_ac_data ac_data = {};
+	int rc;
+
+	if (!dev->is_physfn)
+		return cxi_svc_get_netns_vf(dev, svc_id, netns);
+
+	mutex_lock(&hw->svc_lock);
+
+	svc_priv = idr_find(&hw->svc_ids, svc_id);
+	if (!svc_priv) {
+		cxidev_dbg(dev, "svc_id %u not found", svc_id);
+		rc = -EINVAL;
+		goto unlock_return;
+	}
+	rc = cxi_ac_entry_list_retrieve_netns(&svc_priv->rgroup->ac_entry_list, &ac_data);
+	if (rc)
+		goto unlock_return;
+
+	*netns = ac_data.netns;
+
+unlock_return:
+	mutex_unlock(&hw->svc_lock);
+	return rc;
+}
+EXPORT_SYMBOL(cxi_svc_get_netns);
+
+void cass_svc_fini(struct cass_dev *hw)
+{
+	struct cxi_svc_priv *svc_priv;
+	struct cxi_svc_priv *tmp;
+
+	if (!hw->cdev.is_physfn)
+		return;
+
+	debugfs_remove(hw->svc_debug);
+	list_for_each_entry_safe(svc_priv, tmp, &hw->svc_list, list)
+		svc_destroy(hw, svc_priv);
+
+	idr_destroy(&hw->svc_ids);
+}
diff --git a/drivers/net/ethernet/hpe/ss1/cass_sysfs.c b/drivers/net/ethernet/hpe/ss1/cass_sysfs.c
new file mode 100644
index 000000000000..ae0da46e774d
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_sysfs.c
@@ -0,0 +1,849 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2022 Hewlett Packard Enterprise Development LP */
+
+#include "cass_core.h"
+
+#define PROP_ATTR_RO(_name) \
+	static struct kobj_attribute dev_attr_##_name = __ATTR_RO(_name)
+
+#define PROP_ATTR_RW(_name) \
+	static struct kobj_attribute dev_attr_##_name = __ATTR_RW(_name)
+
+static ssize_t nic_addr_show(struct kobject *kobj, struct kobj_attribute *kattr,
+			     char *buf)
+{
+	struct cass_dev *hw =
+		container_of(kobj, struct cass_dev, properties_kobj);
+
+	return scnprintf(buf, PAGE_SIZE, "0x%x\n", hw->cdev.prop.nic_addr);
+}
+PROP_ATTR_RO(nic_addr);
+
+static ssize_t nid_show(struct kobject *kobj, struct kobj_attribute *kattr,
+			char *buf)
+{
+	struct cass_dev *hw =
+		container_of(kobj, struct cass_dev, properties_kobj);
+
+	return scnprintf(buf, PAGE_SIZE, "0x%x\n", hw->cdev.prop.nid);
+}
+
+static ssize_t nid_store(struct kobject *kobj, struct kobj_attribute *attr,
+			 const char *buf, size_t count)
+{
+	struct cass_dev *hw = container_of(kobj, struct cass_dev,
+					   properties_kobj);
+	u32 nid;
+
+	if (kstrtoint(buf, 0, &nid) < 0)
+		return -EINVAL;
+
+	cxi_set_nid(&hw->cdev, nid);
+
+	return count;
+}
+PROP_ATTR_RW(nid);
+
+static ssize_t pid_bits_show(struct kobject *kobj, struct kobj_attribute *kattr,
+			     char *buf)
+{
+	struct cass_dev *hw =
+		container_of(kobj, struct cass_dev, properties_kobj);
+
+	return scnprintf(buf, PAGE_SIZE, "%d\n", hw->cdev.prop.pid_bits);
+}
+PROP_ATTR_RO(pid_bits);
+
+static ssize_t system_type_identifier_show(struct kobject *kobj, struct kobj_attribute *kattr,
+					   char *buf)
+{
+	struct cass_dev *hw =
+		container_of(kobj, struct cass_dev, properties_kobj);
+
+	return scnprintf(buf, PAGE_SIZE, "%u\n", hw->cdev.system_type_identifier);
+}
+PROP_ATTR_RO(system_type_identifier);
+
+static ssize_t pid_count_show(struct kobject *kobj,
+			      struct kobj_attribute *kattr,
+			      char *buf)
+{
+	struct cass_dev *hw =
+		container_of(kobj, struct cass_dev, properties_kobj);
+
+	return scnprintf(buf, PAGE_SIZE, "%d\n", hw->cdev.prop.pid_count);
+}
+PROP_ATTR_RO(pid_count);
+
+static ssize_t pid_granule_show(struct kobject *kobj,
+				struct kobj_attribute *kattr,
+				char *buf)
+{
+	struct cass_dev *hw =
+		container_of(kobj, struct cass_dev, properties_kobj);
+
+	return scnprintf(buf, PAGE_SIZE, "%d\n", hw->cdev.prop.pid_granule);
+}
+PROP_ATTR_RO(pid_granule);
+
+static ssize_t min_free_shift_show(struct kobject *kobj,
+				   struct kobj_attribute *kattr,
+				   char *buf)
+{
+	struct cass_dev *hw =
+		container_of(kobj, struct cass_dev, properties_kobj);
+
+	return scnprintf(buf, PAGE_SIZE, "%d\n", hw->cdev.prop.min_free_shift);
+}
+PROP_ATTR_RO(min_free_shift);
+
+static ssize_t rdzv_get_idx_show(struct kobject *kobj,
+				 struct kobj_attribute *kattr,
+				 char *buf)
+{
+	struct cass_dev *hw =
+		container_of(kobj, struct cass_dev, properties_kobj);
+
+	return scnprintf(buf, PAGE_SIZE, "%d\n", hw->cdev.prop.rdzv_get_idx);
+}
+PROP_ATTR_RO(rdzv_get_idx);
+
+static ssize_t num_ptes_show(struct kobject *kobj,
+			     struct kobj_attribute *kattr,
+			     char *buf)
+{
+	struct cass_dev *hw =
+		container_of(kobj, struct cass_dev, properties_kobj);
+
+	return scnprintf(buf, PAGE_SIZE, "%d\n", hw->cdev.prop.rsrcs.ptes.max);
+}
+PROP_ATTR_RO(num_ptes);
+
+static ssize_t num_txqs_show(struct kobject *kobj,
+			     struct kobj_attribute *kattr,
+			     char *buf)
+{
+	struct cass_dev *hw =
+		container_of(kobj, struct cass_dev, properties_kobj);
+
+	return scnprintf(buf, PAGE_SIZE, "%d\n", hw->cdev.prop.rsrcs.txqs.max);
+}
+PROP_ATTR_RO(num_txqs);
+
+static ssize_t num_tgqs_show(struct kobject *kobj,
+			     struct kobj_attribute *kattr,
+			     char *buf)
+{
+	struct cass_dev *hw =
+		container_of(kobj, struct cass_dev, properties_kobj);
+
+	return scnprintf(buf, PAGE_SIZE, "%d\n", hw->cdev.prop.rsrcs.tgqs.max);
+}
+PROP_ATTR_RO(num_tgqs);
+
+static ssize_t num_eqs_show(struct kobject *kobj,
+			    struct kobj_attribute *kattr,
+			    char *buf)
+{
+	struct cass_dev *hw =
+		container_of(kobj, struct cass_dev, properties_kobj);
+
+	return scnprintf(buf, PAGE_SIZE, "%d\n", hw->cdev.prop.rsrcs.eqs.max);
+}
+PROP_ATTR_RO(num_eqs);
+
+static ssize_t num_cts_show(struct kobject *kobj,
+			    struct kobj_attribute *kattr,
+			    char *buf)
+{
+	struct cass_dev *hw =
+		container_of(kobj, struct cass_dev, properties_kobj);
+
+	return scnprintf(buf, PAGE_SIZE, "%d\n", hw->cdev.prop.rsrcs.cts.max);
+}
+PROP_ATTR_RO(num_cts);
+
+static ssize_t num_acs_show(struct kobject *kobj,
+			    struct kobj_attribute *kattr,
+			    char *buf)
+{
+	struct cass_dev *hw =
+		container_of(kobj, struct cass_dev, properties_kobj);
+
+	return scnprintf(buf, PAGE_SIZE, "%d\n", hw->cdev.prop.rsrcs.acs.max);
+}
+PROP_ATTR_RO(num_acs);
+
+static ssize_t num_tles_show(struct kobject *kobj,
+			     struct kobj_attribute *kattr,
+			     char *buf)
+{
+	struct cass_dev *hw =
+		container_of(kobj, struct cass_dev, properties_kobj);
+
+	return scnprintf(buf, PAGE_SIZE, "%d\n", hw->cdev.prop.rsrcs.tles.max);
+}
+PROP_ATTR_RO(num_tles);
+
+static ssize_t num_les_show(struct kobject *kobj,
+			    struct kobj_attribute *kattr,
+			    char *buf)
+{
+	struct cass_dev *hw =
+		container_of(kobj, struct cass_dev, properties_kobj);
+
+	return scnprintf(buf, PAGE_SIZE, "%d\n", hw->cdev.prop.rsrcs.les.max);
+}
+PROP_ATTR_RO(num_les);
+
+static ssize_t rgids_avail_show(struct kobject *kobj,
+				struct kobj_attribute *kattr, char *buf)
+{
+	struct cass_dev *hw = container_of(kobj, struct cass_dev,
+					   properties_kobj);
+
+	return scnprintf(buf, PAGE_SIZE, "%u\n",
+			 C_NUM_RGIDS - refcount_read(&hw->rgids_refcount));
+}
+PROP_ATTR_RO(rgids_avail);
+
+static ssize_t hpc_mtu_show(struct kobject *kobj, struct kobj_attribute *kattr,
+			    char *buf)
+{
+	return scnprintf(buf, PAGE_SIZE, "%u\n", C_MAX_HPC_MTU);
+}
+PROP_ATTR_RO(hpc_mtu);
+
+static ssize_t speed_show(struct kobject *kobj, struct kobj_attribute *kattr,
+			  char *buf)
+{
+	struct cass_dev *hw =
+		container_of(kobj, struct cass_dev, properties_kobj);
+	int speed;
+
+	if (hw->port)
+		cass_sbl_link_mode_to_speed(hw->port->lattr.bl.link_mode, &speed);
+	else
+		speed = 0;
+
+	return scnprintf(buf, PAGE_SIZE, "%d\n", speed);
+}
+PROP_ATTR_RO(speed);
+
+static ssize_t link_show(struct kobject *kobj, struct kobj_attribute *kattr,
+			 char *buf)
+{
+	struct cass_dev *hw =
+		container_of(kobj, struct cass_dev, properties_kobj);
+	int state = hw->phy.state == CASS_PHY_RUNNING;
+
+	return scnprintf(buf, PAGE_SIZE, "%d\n", state);
+}
+PROP_ATTR_RO(link);
+
+static ssize_t rev_show(struct kobject *kobj, struct kobj_attribute *kattr,
+			char *buf)
+{
+	struct cass_dev *hw =
+		container_of(kobj, struct cass_dev, properties_kobj);
+
+	return scnprintf(buf, PAGE_SIZE, "%u\n", hw->cdev.prop.device_rev);
+}
+PROP_ATTR_RO(rev);
+
+static ssize_t proto_show(struct kobject *kobj, struct kobj_attribute *kattr,
+			  char *buf)
+{
+	struct cass_dev *hw =
+		container_of(kobj, struct cass_dev, properties_kobj);
+
+	return scnprintf(buf, PAGE_SIZE, "%u\n", hw->cdev.prop.device_proto);
+}
+PROP_ATTR_RO(proto);
+
+static ssize_t platform_show(struct kobject *kobj, struct kobj_attribute *kattr,
+			     char *buf)
+{
+	struct cass_dev *hw =
+		container_of(kobj, struct cass_dev, properties_kobj);
+
+	return scnprintf(buf, PAGE_SIZE, "%u\n",
+			 hw->cdev.prop.device_platform);
+}
+PROP_ATTR_RO(platform);
+
+static ssize_t cassini_version_show(struct kobject *kobj,
+				    struct kobj_attribute *kattr, char *buf)
+{
+	struct cass_dev *hw =
+		container_of(kobj, struct cass_dev, properties_kobj);
+	const char *str;
+
+	switch (hw->cdev.prop.cassini_version) {
+	case CASSINI_1_0:
+		str = "1.0";
+		break;
+	case CASSINI_1_1:
+		str = "1.1";
+		break;
+	case CASSINI_2_0:
+		str = "2.0";
+		break;
+	default:
+		str = "unknown";
+		break;
+	}
+
+	return scnprintf(buf, PAGE_SIZE, "%s\n", str);
+}
+PROP_ATTR_RO(cassini_version);
+
+static ssize_t uc_nic_show(struct kobject *kobj, struct kobj_attribute *kattr,
+			   char *buf)
+{
+	struct cass_dev *hw =
+		container_of(kobj, struct cass_dev, properties_kobj);
+
+	return scnprintf(buf, PAGE_SIZE, "%u\n", hw->uc_nic);
+}
+PROP_ATTR_RO(uc_nic);
+
+static ssize_t pct_eq_show(struct kobject *kobj, struct kobj_attribute *kattr,
+			   char *buf)
+{
+	struct cass_dev *hw =
+		container_of(kobj, struct cass_dev, properties_kobj);
+
+	return scnprintf(buf, PAGE_SIZE, "%u\n", hw->pct_eq_n);
+}
+PROP_ATTR_RO(pct_eq);
+
+/* This function is similar to the kernel's current_link_speed_show() and
+ * ideally would be merged into it
+ */
+static ssize_t current_esm_link_speed_show(struct kobject *kobj,
+					   struct kobj_attribute *kattr,
+					   char *buf)
+{
+	struct cass_dev *hw =
+		container_of(kobj, struct cass_dev, properties_kobj);
+	const char *speed;
+
+	if (!hw->esm_active)
+		return scnprintf(buf, PAGE_SIZE, "Disabled\n");
+
+	switch (hw->pcie_link_speed) {
+	case CASS_SPEED_2_5GT:
+		speed = "2.5 GT/s";
+		break;
+	case CASS_SPEED_5_0GT:
+		speed = "5.0 GT/s";
+		break;
+	case CASS_SPEED_8_0GT:
+		speed = "8.0 GT/s";
+		break;
+	case CASS_SPEED_16_0GT:
+		speed = "16.0 GT/s";
+		break;
+	case CASS_SPEED_20_0GT:
+		speed = "20.0 GT/s";
+		break;
+	case CASS_SPEED_25_0GT:
+		speed = "25.0 GT/s";
+		break;
+	case CASS_SPEED_32_0GT:
+		speed = "32.0 GT/s";
+		break;
+	default:
+		speed = "Unknown speed";
+		break;
+	}
+
+	return scnprintf(buf, PAGE_SIZE, "%s\n", speed);
+}
+PROP_ATTR_RO(current_esm_link_speed);
+
+static ssize_t rdzv_get_en_show(struct kobject *kobj,
+				struct kobj_attribute *attr, char *buf)
+{
+	struct cass_dev *hw = container_of(kobj, struct cass_dev,
+					   properties_kobj);
+
+	return snprintf(buf, PAGE_SIZE, "%d\n", !!hw->cdev.prop.rdzv_get_en);
+}
+
+static ssize_t rdzv_get_en_store(struct kobject *kobj,
+				 struct kobj_attribute *attr,
+				 const char *buf, size_t count)
+{
+	struct cass_dev *hw = container_of(kobj, struct cass_dev,
+					   properties_kobj);
+	bool flag;
+
+	mutex_lock(&hw->get_ctrl_mutex);
+	if (kstrtobool(buf, &flag) < 0) {
+		mutex_unlock(&hw->get_ctrl_mutex);
+
+		return -EINVAL;
+	}
+	hw->cdev.prop.rdzv_get_en = flag;
+	cass_pte_set_get_ctrl(hw);
+	mutex_unlock(&hw->get_ctrl_mutex);
+
+	return count;
+}
+PROP_ATTR_RW(rdzv_get_en);
+
+static ssize_t amo_remap_to_pcie_fadd_show(struct kobject *kobj,
+					   struct kobj_attribute *attr,
+					   char *buf)
+{
+	struct cass_dev *hw = container_of(kobj, struct cass_dev,
+					   properties_kobj);
+
+	return snprintf(buf, PAGE_SIZE, "%d\n",
+			hw->cdev.prop.amo_remap_to_pcie_fadd);
+}
+
+static ssize_t amo_remap_to_pcie_fadd_store(struct kobject *kobj,
+					    struct kobj_attribute *attr,
+					    const char *buf, size_t count)
+{
+	struct cass_dev *hw = container_of(kobj, struct cass_dev,
+					   properties_kobj);
+	int amo_remap_to_pcie_fadd;
+	int ret;
+
+	ret = kstrtoint(buf, 10, &amo_remap_to_pcie_fadd);
+	if (ret)
+		return ret;
+
+	mutex_lock(&hw->amo_remap_to_pcie_fadd_mutex);
+	ret = cass_ixe_set_amo_remap_to_pcie_fadd(hw, amo_remap_to_pcie_fadd);
+	mutex_unlock(&hw->amo_remap_to_pcie_fadd_mutex);
+
+	if (ret)
+		return ret;
+
+	return count;
+}
+PROP_ATTR_RW(amo_remap_to_pcie_fadd);
+
+static ssize_t pcie_corr_err_show(struct kobject *kobj,
+				  struct kobj_attribute *kattr, char *buf)
+{
+	struct cass_dev *hw =
+		container_of(kobj, struct cass_dev, properties_kobj);
+
+	return scnprintf(buf, PAGE_SIZE, "%llu\n", hw->pcie_mon.corr_err);
+}
+PROP_ATTR_RO(pcie_corr_err);
+
+static ssize_t pcie_uncorr_err_show(struct kobject *kobj,
+				    struct kobj_attribute *kattr, char *buf)
+{
+	struct cass_dev *hw =
+		container_of(kobj, struct cass_dev, properties_kobj);
+
+	return scnprintf(buf, PAGE_SIZE, "%llu\n", hw->pcie_mon.uncorr_err);
+}
+PROP_ATTR_RO(pcie_uncorr_err);
+
+static struct attribute *properties_attrs[] = {
+	&dev_attr_nic_addr.attr,
+	&dev_attr_nid.attr,
+	&dev_attr_pid_bits.attr,
+	&dev_attr_pid_count.attr,
+	&dev_attr_pid_granule.attr,
+	&dev_attr_min_free_shift.attr,
+	&dev_attr_rdzv_get_idx.attr,
+	&dev_attr_hpc_mtu.attr,
+	&dev_attr_speed.attr,
+	&dev_attr_link.attr,
+	&dev_attr_rev.attr,
+	&dev_attr_proto.attr,
+	&dev_attr_platform.attr,
+	&dev_attr_system_type_identifier.attr,
+	&dev_attr_cassini_version.attr,
+	&dev_attr_uc_nic.attr,
+	&dev_attr_num_ptes.attr,
+	&dev_attr_num_txqs.attr,
+	&dev_attr_num_tgqs.attr,
+	&dev_attr_num_eqs.attr,
+	&dev_attr_num_cts.attr,
+	&dev_attr_num_acs.attr,
+	&dev_attr_num_tles.attr,
+	&dev_attr_num_les.attr,
+	&dev_attr_rgids_avail.attr,
+	&dev_attr_pct_eq.attr,
+	&dev_attr_current_esm_link_speed.attr,
+	&dev_attr_rdzv_get_en.attr,
+	&dev_attr_pcie_corr_err.attr,
+	&dev_attr_pcie_uncorr_err.attr,
+	&dev_attr_amo_remap_to_pcie_fadd.attr,
+	NULL,
+};
+ATTRIBUTE_GROUPS(properties);
+
+static struct kobj_type properties_info = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = properties_groups,
+};
+
+/* FRU attributes from the uC. The FRU information is made available
+ * in hw->fru_info[]. Create each entry with the index in that table.
+ */
+#define FRU_ATTR(_name, _idx)						\
+	static ssize_t _name##_show(struct kobject *kobj,		\
+				    struct kobj_attribute *kattr,	\
+				    char *buf)				\
+	{								\
+		struct cass_dev *hw =					\
+			container_of(kobj, struct cass_dev, fru_kobj);	\
+		if (!hw->fru_info_valid)				\
+			uc_cmd_get_fru(hw);				\
+		if (hw->fru_info[_idx])					\
+			return scnprintf(buf, PAGE_SIZE, "%s\n",	\
+					 hw->fru_info[_idx]);		\
+		else							\
+			return 0;					\
+	}								\
+	static struct kobj_attribute dev_attr_##_name = __ATTR_RO(_name)
+
+FRU_ATTR(chassis_type, PLDM_FRU_FIELD_CHASSIS_TYPE);
+FRU_ATTR(model, PLDM_FRU_FIELD_MODEL);
+FRU_ATTR(part_number, PLDM_FRU_FIELD_PART_NUMBER);
+FRU_ATTR(serial_number, PLDM_FRU_FIELD_SERIAL_NUMBER);
+FRU_ATTR(manufacturer, PLDM_FRU_FIELD_MANUFACTURER);
+FRU_ATTR(manufacture_date, PLDM_FRU_FIELD_MANUFACTURE_DATE);
+FRU_ATTR(vendor, PLDM_FRU_FIELD_VENDOR);
+FRU_ATTR(name, PLDM_FRU_FIELD_NAME);
+FRU_ATTR(sku, PLDM_FRU_FIELD_SKU);
+FRU_ATTR(version, PLDM_FRU_FIELD_VERSION);
+FRU_ATTR(asset_tag, PLDM_FRU_FIELD_ASSET_TAG);
+FRU_ATTR(description, PLDM_FRU_FIELD_DESCRIPTION);
+FRU_ATTR(engineering_change_level,
+	 PLDM_FRU_FIELD_ENGINEERING_CHANGE_LEVEL);
+FRU_ATTR(other, PLDM_FRU_FIELD_OTHER);
+FRU_ATTR(vendor_iana, PLDM_FRU_FIELD_VENDOR_IANA);
+
+static struct attribute *fru_attrs[] = {
+	&dev_attr_chassis_type.attr,
+	&dev_attr_model.attr,
+	&dev_attr_part_number.attr,
+	&dev_attr_serial_number.attr,
+	&dev_attr_manufacturer.attr,
+	&dev_attr_manufacture_date.attr,
+	&dev_attr_vendor.attr,
+	&dev_attr_name.attr,
+	&dev_attr_sku.attr,
+	&dev_attr_version.attr,
+	&dev_attr_asset_tag.attr,
+	&dev_attr_description.attr,
+	&dev_attr_engineering_change_level.attr,
+	&dev_attr_other.attr,
+	&dev_attr_vendor_iana.attr,
+
+	NULL,
+};
+ATTRIBUTE_GROUPS(fru);
+
+static struct kobj_type fru_info = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = fru_groups,
+};
+
+#define LINK_RESTART_TIME(_idx)					\
+	static ssize_t time_##_idx##_show(struct kobject *kobj,	\
+		struct kobj_attribute *kattr, char *buf)	\
+	{							\
+		struct cass_dev *hw =				\
+			container_of(kobj, struct cass_dev,	\
+			link_restarts_kobj);			\
+								\
+		return scnprintf(buf, PAGE_SIZE, "%lld\n",	\
+			hw->port->link_restart_time_buf[_idx]);	\
+	}							\
+	PROP_ATTR_RO(time_##_idx)
+
+LINK_RESTART_TIME(0);
+LINK_RESTART_TIME(1);
+LINK_RESTART_TIME(2);
+LINK_RESTART_TIME(3);
+LINK_RESTART_TIME(4);
+LINK_RESTART_TIME(5);
+LINK_RESTART_TIME(6);
+LINK_RESTART_TIME(7);
+LINK_RESTART_TIME(8);
+LINK_RESTART_TIME(9);
+/* NOTE: don't forget to add more buffer entries */
+
+static struct attribute *link_restarts_attrs[] = {
+	&dev_attr_time_0.attr,
+	&dev_attr_time_1.attr,
+	&dev_attr_time_2.attr,
+	&dev_attr_time_3.attr,
+	&dev_attr_time_4.attr,
+	&dev_attr_time_5.attr,
+	&dev_attr_time_6.attr,
+	&dev_attr_time_7.attr,
+	&dev_attr_time_8.attr,
+	&dev_attr_time_9.attr,
+	NULL,
+};
+ATTRIBUTE_GROUPS(link_restarts);
+
+static struct kobj_type link_restarts_info = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = link_restarts_groups,
+};
+
+#define SENSOR_ATTR_RO(_name, _fmt, _field)				\
+	static ssize_t sensor_##_name##_show(struct kobject *kobj,	\
+					     struct kobj_attribute *kattr, \
+					     char *buf)			\
+	{								\
+		struct pldm_sensor *sensor =				\
+			container_of(kobj, struct pldm_sensor, kobj);	\
+									\
+		return scnprintf(buf, PAGE_SIZE, _fmt "\n",		\
+				 sensor->_field);			\
+	}								\
+									\
+	static struct kobj_attribute dev_attr_sensor_##_name = {	\
+		.attr   = { .name = __stringify(_name), .mode = 0444 },	\
+		.show   = sensor_##_name##_show,			\
+	}
+
+SENSOR_ATTR_RO(name, "%s", name);
+SENSOR_ATTR_RO(base_unit, "%u", num.base_unit);
+SENSOR_ATTR_RO(unit_modifier, "%d", num.unit_modifier);
+SENSOR_ATTR_RO(rate_unit, "%u", num.rate_unit);
+
+#define SENSOR_SSD_ATTR_RO(_name, _field)				\
+	static ssize_t sensor_##_name##_show(struct kobject *kobj,	\
+					     struct kobj_attribute *kattr, \
+					     char *buf)			\
+	{								\
+		struct pldm_sensor *sensor =				\
+			container_of(kobj, struct pldm_sensor, kobj);	\
+									\
+		return scnprintf(buf, PAGE_SIZE, "%llu\n",		\
+				 get_pldm_value(sensor, _field));	\
+	}								\
+									\
+	static struct kobj_attribute dev_attr_sensor_##_name = {	\
+		.attr   = { .name = __stringify(_name), .mode = 0444 },	\
+		.show   = sensor_##_name##_show,			\
+	}
+
+SENSOR_SSD_ATTR_RO(range_field_supported, range_field_support);
+SENSOR_SSD_ATTR_RO(nominal_value, nominal_value);
+SENSOR_SSD_ATTR_RO(warning_high, warning_high);
+SENSOR_SSD_ATTR_RO(warning_low, warning_low);
+SENSOR_SSD_ATTR_RO(critical_high, critical_high);
+SENSOR_SSD_ATTR_RO(critical_low, critical_low);
+SENSOR_SSD_ATTR_RO(fatal_high, fatal_high);
+SENSOR_SSD_ATTR_RO(fatal_low, fatal_low);
+
+#define SENSOR_VAL_ATTR_RO(_name, _fmt)					\
+	static ssize_t sensor_##_name##_show(struct kobject *kobj,	\
+					     struct kobj_attribute *kattr, \
+					     char *buf)			\
+	{								\
+		struct pldm_sensor *sensor =				\
+			container_of(kobj, struct pldm_sensor, kobj);	\
+		struct pldm_sensor_reading result;			\
+		int rc;							\
+									\
+		rc = update_sensor(sensor, &result);			\
+		if (rc)							\
+			return rc;					\
+									\
+		return scnprintf(buf, PAGE_SIZE, _fmt "\n", result._name); \
+	}								\
+									\
+	static struct kobj_attribute dev_attr_sensor_##_name = {	\
+		.attr   = { .name = __stringify(_name), .mode = 0400 },	\
+		.show   = sensor_##_name##_show,			\
+	}
+
+SENSOR_VAL_ATTR_RO(operational_state, "%u");
+SENSOR_VAL_ATTR_RO(present_state, "%u");
+SENSOR_VAL_ATTR_RO(previous_state, "%u");
+SENSOR_VAL_ATTR_RO(present_reading, "%lld");
+
+static struct attribute *sensor_attrs[] = {
+	&dev_attr_sensor_name.attr,
+	&dev_attr_sensor_base_unit.attr,
+	&dev_attr_sensor_unit_modifier.attr,
+	&dev_attr_sensor_rate_unit.attr,
+	&dev_attr_sensor_nominal_value.attr,
+	&dev_attr_sensor_range_field_supported.attr,
+	&dev_attr_sensor_warning_high.attr,
+	&dev_attr_sensor_warning_low.attr,
+	&dev_attr_sensor_critical_high.attr,
+	&dev_attr_sensor_critical_low.attr,
+	&dev_attr_sensor_fatal_high.attr,
+	&dev_attr_sensor_fatal_low.attr,
+	&dev_attr_sensor_operational_state.attr,
+	&dev_attr_sensor_present_state.attr,
+	&dev_attr_sensor_previous_state.attr,
+	&dev_attr_sensor_present_reading.attr,
+	NULL,
+};
+ATTRIBUTE_GROUPS(sensor);
+
+static struct kobj_type sensor_settings = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = sensor_groups,
+};
+
+static int create_sensors(struct cass_dev *hw)
+{
+	struct pldm_sensor *sensor;
+	int id;
+	int bad_id;
+	int rc;
+
+	hw->pldm_sensors_kobj =
+		kobject_create_and_add("sensors", &hw->cdev.pdev->dev.kobj);
+	if (!hw->pldm_sensors_kobj)
+		return -ENOMEM;
+
+	idr_for_each_entry(&hw->pldm_sensors, sensor, id) {
+		rc = kobject_init_and_add(&sensor->kobj, &sensor_settings,
+					  hw->pldm_sensors_kobj,
+					  "%u", id);
+		if (rc)
+			goto err;
+	}
+
+	return 0;
+
+err:
+	bad_id = id;
+	idr_for_each_entry(&hw->pldm_sensors, sensor, id) {
+		kobject_put(&sensor->kobj);
+		if (id == bad_id)
+			break;
+	}
+
+	kobject_put(hw->pldm_sensors_kobj);
+
+	return rc;
+}
+
+static void delete_sensors(struct cass_dev *hw)
+{
+	struct pldm_sensor *sensor;
+	int id;
+
+	idr_for_each_entry(&hw->pldm_sensors, sensor, id)
+		kobject_put(&sensor->kobj);
+
+	kobject_put(hw->pldm_sensors_kobj);
+}
+
+static ssize_t ac_filter_disabled_show(struct device *dev,
+				       struct device_attribute *attr, char *buf)
+{
+	struct cass_dev *hw = dev_get_drvdata(dev);
+
+	return snprintf(buf, PAGE_SIZE, "%d\n", hw->ac_filter_disabled);
+}
+
+static ssize_t ac_filter_disabled_store(struct device *dev,
+					struct device_attribute *attr,
+				       const char *buf,
+				       size_t count)
+{
+	struct cass_dev *hw = dev_get_drvdata(dev);
+
+	if (kstrtobool(buf, &hw->ac_filter_disabled) < 0)
+		return -EINVAL;
+
+	return count;
+}
+
+static DEVICE_ATTR_RW(ac_filter_disabled);
+
+static struct attribute *cxi_dev_settings[] = {
+	&dev_attr_ac_filter_disabled.attr,
+	NULL,
+};
+
+static const struct attribute_group cxi_dev_settings_group = {
+	.name = "settings",
+	.attrs = cxi_dev_settings,
+};
+
+int create_sysfs_properties(struct cass_dev *hw)
+{
+	int rc;
+
+	if (!hw->cdev.is_physfn)
+		return 0;
+
+	rc = kobject_init_and_add(&hw->properties_kobj, &properties_info,
+				  &hw->cdev.pdev->dev.kobj,
+				  "properties");
+	if (rc)
+		goto put_properties;
+
+	rc = kobject_init_and_add(&hw->link_restarts_kobj, &link_restarts_info,
+				  &hw->cdev.pdev->dev.kobj,
+				  "link_restarts");
+	if (rc)
+		goto put_link_restarts;
+
+	if (!hw->cdev.is_physfn)
+		return 0;
+
+	rc = kobject_init_and_add(&hw->fru_kobj, &fru_info,
+				  &hw->cdev.pdev->dev.kobj,
+				  "fru");
+	if (rc)
+		goto put_fru;
+
+	rc = sysfs_create_group(&hw->cdev.pdev->dev.kobj,
+				&cxi_dev_settings_group);
+	if (rc)
+		goto put_fru;
+
+	rc = cass_create_tc_sysfs(hw);
+	if (rc)
+		goto remove_sysfs_group;
+
+	rc = create_sensors(hw);
+	if (rc)
+		goto remove_tc;
+
+	return 0;
+
+remove_tc:
+	cass_destroy_tc_sysfs(hw);
+remove_sysfs_group:
+	sysfs_remove_group(&hw->cdev.pdev->dev.kobj, &cxi_dev_settings_group);
+put_fru:
+	kobject_put(&hw->fru_kobj);
+put_link_restarts:
+	kobject_put(&hw->link_restarts_kobj);
+put_properties:
+	kobject_put(&hw->properties_kobj);
+
+	return rc;
+}
+
+void destroy_sysfs_properties(struct cass_dev *hw)
+{
+	if (!hw->cdev.is_physfn)
+		return;
+
+	delete_sensors(hw);
+	cass_destroy_tc_sysfs(hw);
+	sysfs_remove_group(&hw->cdev.pdev->dev.kobj, &cxi_dev_settings_group);
+	kobject_put(&hw->fru_kobj);
+	kobject_put(&hw->link_restarts_kobj);
+	kobject_put(&hw->properties_kobj);
+}
diff --git a/drivers/net/ethernet/hpe/ss1/cass_tc.c b/drivers/net/ethernet/hpe/ss1/cass_tc.c
new file mode 100644
index 000000000000..f057e3dea520
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_tc.c
@@ -0,0 +1,2780 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2020, 2024-2026 Hewlett Packard Enterprise Development LP */
+
+/* Traffic Class (TC) Management */
+#include <linux/lockdep.h>
+
+#include "cass_core.h"
+#include "cass_ss1_debugfs.h"
+
+static unsigned int pfc_buf_skid_space = 65280;
+module_param(pfc_buf_skid_space, uint, 0444);
+MODULE_PARM_DESC(pfc_buf_skid_space,
+		 "PFC buffer skid space (high water threshold) in bytes");
+
+/* PCP that PCT Traffic will use. By default we use the PCP specified
+ * in the QoS Profile.
+ */
+static int pct_control_traffic_pcp = -1;
+module_param(pct_control_traffic_pcp, int, 0444);
+MODULE_PARM_DESC(pct_control_traffic_pcp,
+		 "PCP used for PCT control traffic.\n"
+		 "Values 0-7 are valid\n"
+		 "Value -1 - Use PCP Specified in QoS Profile\n");
+
+/* Prevent (or not) usage of PCT PCP by an RDMA TC */
+static bool disable_user_pct_tc_usage = true;
+module_param(disable_user_pct_tc_usage, bool, 0644);
+MODULE_PARM_DESC(disable_user_pct_tc_usage,
+		 "Prevent users from using traffic class assigned to PCT control traffic");
+
+/* PCT Control Traffic needs a dedicated PCP that is configured to ignore
+ * pause from Rosetta. However if the provided PCP is in use by an RDMA TC
+ * we may disallow use of this RDMA TC. This value will only be set if
+ * an RDMA TC is in fact using the PCP used by PCP.
+ */
+static int pct_control_traffic_tc = -1;
+
+static unsigned int active_qos_profile = 2;
+module_param(active_qos_profile, uint, 0444);
+MODULE_PARM_DESC(active_qos_profile,
+		 "QoS Profile to load. Must match fabric QoS Profile\n"
+		 "1 - HPC\n"
+		 "2 - LL_BE_BD_ET\n"
+		 "3 - LL_BE_BD_ET1_ET2\n");
+
+static const char * const cxi_qos_strs[] = {
+	[CXI_QOS_HPC] = "HPC",
+	[CXI_QOS_LL_BE_BD_ET] = "LL_BE_BD_ET",
+	[CXI_QOS_LL_BE_BD_ET1_ET2] = "LL_BE_BD_ET1_ET2",
+};
+
+static const char * const cxi_tc_strs_lc[] = {
+	[CXI_TC_DEDICATED_ACCESS]	= "dedicated_access",
+	[CXI_TC_LOW_LATENCY]            = "low_latency",
+	[CXI_TC_BULK_DATA]              = "bulk_data",
+	[CXI_TC_BEST_EFFORT]            = "best_effort",
+	[CXI_ETH_SHARED]		= "ethernet_shared",
+	[CXI_ETH_TC1]			= "ethernet1",
+	[CXI_ETH_TC2]			= "ethernet2",
+};
+
+static const char * const cxi_tc_strs_uc[] = {
+	[CXI_TC_DEDICATED_ACCESS]	= "DEDICATED_ACCESS",
+	[CXI_TC_LOW_LATENCY]            = "LOW_LATENCY",
+	[CXI_TC_BULK_DATA]              = "BULK_DATA",
+	[CXI_TC_BEST_EFFORT]            = "BEST_EFFORT",
+	[CXI_ETH_SHARED]		= "ETHERNET_SHARED",
+	[CXI_ETH_TC1]			= "ETHERNET1",
+	[CXI_ETH_TC2]			= "ETHERNET2",
+};
+
+static int cxi_get_tc_req_pcp_vf(struct cxi_dev *cdev, unsigned int tc)
+{
+	struct cxi_eth_tc_req_pcp_get_cmd cmd = {
+		.op = CXI_OP_ETH_TC_REQ_PCP_GET,
+		.tc = tc,
+	};
+	struct cxi_get_tc_req_pcp_resp resp = {};
+	size_t resp_len = sizeof(resp);
+	int rc;
+
+	rc = cxi_send_msg_to_pf(cdev, &cmd, sizeof(cmd), &resp, &resp_len);
+	if (rc)
+		return rc;
+
+	return resp.req_pcp;
+}
+
+/**
+ * cxi_get_tc_req_pcp() - Get the request PCP associated with a TC.
+ * If the TC is not enabled return -1.
+ *
+ * @dev: CXI device
+ * @tc: Traffic Class
+ */
+int cxi_get_tc_req_pcp(struct cxi_dev *dev, unsigned int tc)
+{
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+
+	if (!dev->is_physfn)
+		return cxi_get_tc_req_pcp_vf(dev, tc);
+
+	if (tc >= CXI_ETH_TC_MAX)
+		return -EINVAL;
+
+	if (!hw->qos.tcs_active[tc])
+		return -1;
+
+	if (is_eth_tc(tc))
+		return hw->qos.tcs[tc].eth_settings.pcp;
+	else
+		return hw->qos.tcs[tc].dscp_pcp_settings.req_pcp;
+}
+EXPORT_SYMBOL(cxi_get_tc_req_pcp);
+
+static int cass_tc_get_oxe_bc(struct cass_dev *hw)
+{
+	int bc = hw->next_oxe_bc;
+
+	if (bc >= C_OXE_CFG_BUF_BC_PARAM_ENTRIES)
+		return -ENOSPC;
+
+	hw->next_oxe_bc++;
+
+	return bc;
+}
+
+static int cass_tc_req_oxe_bc_cfg(struct cass_dev *hw, unsigned int spt_rsvd,
+				  unsigned int smt_rsvd, unsigned int sct_rsvd,
+				  unsigned int srb_rsvd, unsigned int pbuf_rsvd)
+{
+	const union c_oxe_cfg_pct_bc_cdt pct_bc_cdt_cfg = {
+		.spt_cdt_rsvd = hw->reduced_pct_tables ? 8 : spt_rsvd,
+		.smt_cdt_rsvd = hw->reduced_pct_tables ? 8 : smt_rsvd,
+		.sct_cdt_rsvd = hw->reduced_pct_tables ? 8 : sct_rsvd,
+		.srb_cdt_rsvd = hw->reduced_pct_tables ? 8 : srb_rsvd,
+	};
+	const union c_oxe_cfg_buf_bc_param buf_bc_param_cfg = {
+		.bc_reserv_buf_cdt = pbuf_rsvd,
+		.bc_max_mtu = DIV_ROUND_UP(PORTALS_MAX_FRAME_SIZE, 256),
+	};
+	int bc;
+
+	bc = cass_tc_get_oxe_bc(hw);
+	if (bc < 0)
+		goto out;
+
+	cass_write(hw, C_OXE_CFG_PCT_BC_CDT(bc), &pct_bc_cdt_cfg,
+		   sizeof(pct_bc_cdt_cfg));
+	cass_write(hw, C_OXE_CFG_BUF_BC_PARAM(bc), &buf_bc_param_cfg,
+		   sizeof(buf_bc_param_cfg));
+
+	if (hw->reduced_pct_tables) {
+		static const union c_oxe_cfg_pct_cdt oxe_cfg_pct_cdt = {
+			.spt_cdt_limit = 208,
+			.smt_cdt_limit = 112,
+			.srb_cdt_limit = 336,
+			.sct_cdt_limit = 112,
+		};
+
+		cass_write(hw, C_OXE_CFG_PCT_CDT, &oxe_cfg_pct_cdt,
+			   sizeof(oxe_cfg_pct_cdt));
+	}
+
+out:
+	return bc;
+}
+
+static int cass_tc_rsp_oxe_bc_cfg(struct cass_dev *hw, unsigned int pbuf_rsvd)
+{
+	const union c_oxe_cfg_pct_bc_cdt pct_bc_cdt_cfg = {
+		.ignore_spt = 1,
+		.ignore_smt = 1,
+		.ignore_sct = 1,
+		.ignore_srb = 1,
+	};
+	const union c_oxe_cfg_buf_bc_param buf_bc_param_cfg = {
+		.bc_reserv_buf_cdt = pbuf_rsvd,
+		.bc_max_mtu = DIV_ROUND_UP(PORTALS_MAX_FRAME_SIZE, 256),
+	};
+	int bc;
+
+	bc = cass_tc_get_oxe_bc(hw);
+	if (bc < 0)
+		goto out;
+
+	cass_write(hw, C_OXE_CFG_PCT_BC_CDT(bc), &pct_bc_cdt_cfg,
+		   sizeof(pct_bc_cdt_cfg));
+	cass_write(hw, C_OXE_CFG_BUF_BC_PARAM(bc), &buf_bc_param_cfg,
+		   sizeof(buf_bc_param_cfg));
+
+out:
+	return bc;
+}
+
+static int cass_tc_eth_oxe_bc_cfg(struct cass_dev *hw, unsigned int spt_rsvd,
+				  unsigned int pbuf_rsvd)
+{
+	const union c_oxe_cfg_pct_bc_cdt pct_bc_cdt_cfg = {
+		.spt_cdt_rsvd = spt_rsvd,
+		.ignore_smt = 1,
+		.ignore_sct = 1,
+		.ignore_srb = 1,
+	};
+	const union c_oxe_cfg_buf_bc_param buf_bc_param_cfg = {
+		.bc_reserv_buf_cdt = pbuf_rsvd,
+		.bc_max_mtu = DIV_ROUND_UP(ETHERNET_MAX_FRAME_SIZE, 256),
+	};
+	int bc;
+
+	bc = cass_tc_get_oxe_bc(hw);
+	if (bc < 0)
+		goto out;
+
+	cass_write(hw, C_OXE_CFG_PCT_BC_CDT(bc), &pct_bc_cdt_cfg,
+		   sizeof(pct_bc_cdt_cfg));
+	cass_write(hw, C_OXE_CFG_BUF_BC_PARAM(bc), &buf_bc_param_cfg,
+		   sizeof(buf_bc_param_cfg));
+
+out:
+	return bc;
+}
+
+static int cass_tc_get_branch_bucket(struct cass_dev *hw)
+{
+	int bucket = hw->next_oxe_branch_bucket;
+
+	if (bucket >= C_OXE_CFG_ARB_BRANCH_ENTRIES)
+		return -ENOSPC;
+
+	hw->next_oxe_branch_bucket++;
+
+	return bucket;
+}
+
+static int cass_tc_get_leaf_bucket(struct cass_dev *hw)
+{
+	int bucket = hw->next_oxe_leaf_bucket;
+
+	if (bucket >= C_OXE_CFG_ARB_LEAF_ENTRIES)
+		return -ENOSPC;
+
+	hw->next_oxe_leaf_bucket++;
+
+	return bucket;
+}
+
+static int cass_tc_oxe_mcu_cfg(struct cass_dev *hw, unsigned int mcu_base,
+			       unsigned int mcu_count, unsigned int pcp,
+			       unsigned int tsc, unsigned int bc,
+			       unsigned int mfs_index)
+{
+	const union c_oxe_cfg_mcu_param mcu_cfg = {
+		.bc_map = bc,
+		.tsc_map = tsc,
+		.pcp_map = pcp,
+		.wdrr_in_sel = mfs_index,
+		.wdrr_out_sel = mfs_index,
+	};
+	int i;
+
+	if (mcu_base >= C_OXE_MCU_COUNT ||
+	    (mcu_base + mcu_count) >  C_OXE_MCU_COUNT)
+		return -EINVAL;
+
+	for (i = 0; i < mcu_count; i++)
+		cass_write(hw, C_OXE_CFG_MCU_PARAM(mcu_base + i), &mcu_cfg,
+			   sizeof(mcu_cfg));
+
+	return 0;
+}
+
+static int cass_tc_oxe_pcp_pause_cfg(struct cass_dev *hw, unsigned int pcp,
+				     unsigned int tsc)
+{
+	union c_oxe_cfg_arb_pcp_mask pcp_mask;
+
+	if (pcp >= C_OXE_CFG_ARB_PCP_MASK_ENTRIES)
+		return -EINVAL;
+
+	cass_read(hw, C_OXE_CFG_ARB_PCP_MASK(pcp), &pcp_mask, sizeof(pcp_mask));
+
+	pcp_mask.tsc_mask |= BIT(tsc);
+
+	cass_write(hw, C_OXE_CFG_ARB_PCP_MASK(pcp), &pcp_mask,
+		   sizeof(pcp_mask));
+
+	return 0;
+}
+
+static void cass_tc_oxe_branch_bucket_cfg(struct cass_dev *hw,
+					  int tc)
+{
+	const struct cass_tc_oxe_settings *oxe_settings =
+		&hw->qos.tcs[tc].oxe_settings;
+	int assured_fill_qty =
+		max_t(int, 1, hw->tsc_fill_qty * oxe_settings->assured_percent / 100);
+	int ceiling_fill_qty =
+		max_t(int, 1, hw->tsc_fill_qty * oxe_settings->ceiling_percent / 100);
+	int branch = hw->qos.tcs[tc].branch;
+	const union c_oxe_cfg_arb_branch branch_cfg = {
+		.pri = oxe_settings->branch_priority,
+		.mfs_in_sel = oxe_settings->mfs_index,
+		.mfs_out_sel = oxe_settings->mfs_index,
+	};
+	const union c_oxe_cfg_arb_branch_out_a branch_out_a_cfg = {
+		.fill_qty = assured_fill_qty,
+		.limit = oxe_settings->bucket_limit,
+	};
+	const union c_oxe_cfg_arb_branch_out_c branch_out_c_cfg = {
+		.fill_qty = ceiling_fill_qty,
+		.limit = oxe_settings->bucket_limit,
+		.enable = 1,
+	};
+	const union c_oxe_cfg_arb_branch_in_a branch_in_a_cfg = {
+		.fill_qty = assured_fill_qty,
+		.limit = oxe_settings->bucket_limit,
+	};
+	const union c_oxe_cfg_arb_branch_in_c branch_in_c_cfg = {
+		.fill_qty = ceiling_fill_qty,
+		.limit = oxe_settings->bucket_limit,
+		.enable = 1,
+	};
+
+	if (branch >= C_OXE_CFG_ARB_BRANCH_ENTRIES)
+		return;
+
+	cass_write(hw, C_OXE_CFG_ARB_BRANCH(branch), &branch_cfg,
+		   sizeof(branch_cfg));
+	cass_write(hw, C_OXE_CFG_ARB_BRANCH_OUT_A(branch), &branch_out_a_cfg,
+		   sizeof(branch_out_a_cfg));
+	cass_write(hw, C_OXE_CFG_ARB_BRANCH_OUT_C(branch), &branch_out_c_cfg,
+		   sizeof(branch_out_c_cfg));
+	cass_write(hw, C_OXE_CFG_ARB_BRANCH_IN_A(branch), &branch_in_a_cfg,
+		   sizeof(branch_in_a_cfg));
+	cass_write(hw, C_OXE_CFG_ARB_BRANCH_IN_C(branch), &branch_in_c_cfg,
+		   sizeof(branch_in_c_cfg));
+}
+
+static void cass_tc_oxe_leaf_bucket_cfg(struct cass_dev *hw,
+					int tc, int leaf, bool req)
+{
+	const struct cass_tc_oxe_settings *oxe_settings =
+		&hw->qos.tcs[tc].oxe_settings;
+	bool is_ethernet = is_eth_tc(tc);
+	int assured_fill_qty = is_ethernet ?
+		max_t(int, 1, hw->tsc_fill_qty * oxe_settings->assured_percent / 100) :
+		1;
+	int ceiling_fill_qty = is_ethernet ?
+		max_t(int, 1, hw->tsc_fill_qty * oxe_settings->ceiling_percent / 100) :
+		hw->tsc_fill_qty;
+	unsigned int priority = req ? oxe_settings->leaf_request_priority :
+				oxe_settings->leaf_response_priority;
+	const union c_oxe_cfg_arb_leaf leaf_cfg = {
+		.pri = priority,
+		.parent = hw->qos.tcs[tc].branch,
+		.enable_in = !is_ethernet,
+		.mfs_in_sel = oxe_settings->mfs_index,
+		.mfs_out_sel = oxe_settings->mfs_index,
+	};
+	const union c_oxe_cfg_arb_leaf_out_a leaf_out_a_cfg = {
+		.fill_qty = assured_fill_qty,
+		.limit = oxe_settings->bucket_limit,
+	};
+	const union c_oxe_cfg_arb_leaf_out_c leaf_out_c_cfg = {
+		.fill_qty = ceiling_fill_qty,
+		.limit = oxe_settings->bucket_limit,
+		.enable = 1,
+	};
+	const union c_oxe_cfg_arb_leaf_in_a leaf_in_a_cfg = {
+		.fill_qty = assured_fill_qty,
+		.limit = oxe_settings->bucket_limit,
+	};
+	const union c_oxe_cfg_arb_leaf_in_c leaf_in_c_cfg = {
+		.fill_qty = ceiling_fill_qty,
+		.limit = oxe_settings->bucket_limit,
+		.enable = 1,
+	};
+
+	cass_write(hw, C_OXE_CFG_ARB_LEAF(leaf), &leaf_cfg, sizeof(leaf_cfg));
+	cass_write(hw, C_OXE_CFG_ARB_LEAF_OUT_A(leaf), &leaf_out_a_cfg,
+		   sizeof(leaf_out_a_cfg));
+	cass_write(hw, C_OXE_CFG_ARB_LEAF_OUT_C(leaf), &leaf_out_c_cfg,
+		   sizeof(leaf_out_c_cfg));
+	cass_write(hw, C_OXE_CFG_ARB_LEAF_IN_A(leaf), &leaf_in_a_cfg,
+		   sizeof(leaf_in_a_cfg));
+	cass_write(hw, C_OXE_CFG_ARB_LEAF_IN_C(leaf), &leaf_in_c_cfg,
+		   sizeof(leaf_in_c_cfg));
+}
+
+/* Configure OXE for RDMA classes */
+static int cass_tc_oxe_cfg(struct cass_dev *hw, enum cxi_traffic_class tc,
+			   unsigned int req_pcp, unsigned int rsp_pcp,
+			   unsigned int cq_mcu_base,
+			   unsigned int cq_mcu_count,
+			   unsigned int lpe_mcu_base,
+			   unsigned int lpe_mcu_count,
+			   unsigned int ixe_mcu_base,
+			   unsigned int ixe_mcu_count,
+			   unsigned int tou_mcu)
+{
+	const struct cass_tc_oxe_settings *oxe_settings =
+		&hw->qos.tcs[tc].oxe_settings;
+	int req_bc;
+	int rsp_bc;
+	int branch_bucket;
+	int req_leaf_bucket;
+	int rsp_leaf_bucket;
+	int ret;
+	int spt_rsvd = oxe_settings->spt_rsvd;
+
+	/* If PCT control traffic needs to be remapped to a different traffic
+	 * class, reuse the response PCP of the remapped traffic class.
+	 */
+	int mcu_pcp = hw->qos.pct_control_pcp;
+
+	/* Calculate SPT reserved back on number of MCUs and ordered packets
+	 * inflight. Only 3 MCUs worth of SPT entries are currently supported
+	 * being reserved.
+	 */
+	if (!spt_rsvd) {
+		spt_rsvd = min_t(int, 3, cq_mcu_count);
+		if (cass_version(hw, CASSINI_2))
+			spt_rsvd *= CASS2_MAX_PACKETS_INFLIGHT;
+		else
+			spt_rsvd *= CASS1_MAX_PACKETS_INFLIGHT;
+	}
+
+	req_bc = cass_tc_req_oxe_bc_cfg(hw, spt_rsvd, oxe_settings->smt_rsvd,
+					oxe_settings->sct_rsvd,
+					oxe_settings->srb_rsvd,
+					oxe_settings->pbuf_rsvd);
+	if (req_bc < 0)
+		return req_bc;
+
+	hw->qos.tcs[tc].req_bc = req_bc;
+
+	rsp_bc = cass_tc_rsp_oxe_bc_cfg(hw, oxe_settings->pbuf_rsvd);
+	if (rsp_bc < 0)
+		return rsp_bc;
+
+	branch_bucket = cass_tc_get_branch_bucket(hw);
+	if (branch_bucket < 0)
+		return branch_bucket;
+
+	hw->qos.tcs[tc].branch = branch_bucket;
+	cass_tc_oxe_branch_bucket_cfg(hw, tc);
+
+	req_leaf_bucket = cass_tc_get_leaf_bucket(hw);
+	if (req_leaf_bucket < 0)
+		return req_leaf_bucket;
+	cass_tc_oxe_leaf_bucket_cfg(hw, tc, req_leaf_bucket, true);
+	hw->qos.tcs[tc].leaf[0] = req_leaf_bucket;
+
+	rsp_leaf_bucket = cass_tc_get_leaf_bucket(hw);
+	if (rsp_leaf_bucket < 0)
+		return rsp_leaf_bucket;
+	cass_tc_oxe_leaf_bucket_cfg(hw, tc, rsp_leaf_bucket, false);
+	hw->qos.tcs[tc].leaf[1] = rsp_leaf_bucket;
+
+	ret = cass_tc_oxe_mcu_cfg(hw, cq_mcu_base, cq_mcu_count, mcu_pcp,
+				  req_leaf_bucket, req_bc,
+				  oxe_settings->mfs_index);
+	if (ret)
+		return ret;
+
+	ret = cass_tc_oxe_mcu_cfg(hw, tou_mcu, 1, mcu_pcp, req_leaf_bucket,
+				  req_bc, oxe_settings->mfs_index);
+	if (ret)
+		return ret;
+
+	ret = cass_tc_oxe_mcu_cfg(hw, lpe_mcu_base, lpe_mcu_count, mcu_pcp,
+				  req_leaf_bucket, req_bc,
+				  oxe_settings->mfs_index);
+	if (ret)
+		return ret;
+
+	ret = cass_tc_oxe_mcu_cfg(hw, ixe_mcu_base, ixe_mcu_count, rsp_pcp,
+				  rsp_leaf_bucket, rsp_bc,
+				  oxe_settings->mfs_index);
+	if (ret)
+		return ret;
+
+	ret = cass_tc_oxe_pcp_pause_cfg(hw, req_pcp, req_leaf_bucket);
+	if (ret)
+		return ret;
+
+	ret = cass_tc_oxe_pcp_pause_cfg(hw, rsp_pcp, rsp_leaf_bucket);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+static int cass_tc_get_cq_tc(struct cass_dev *hw)
+{
+	int tc = hw->next_cq_tc;
+
+	if (tc >= C_CQ_CFG_FQ_RESRV_ENTRIES)
+		return -ENOSPC;
+
+	hw->next_cq_tc++;
+
+	return tc;
+}
+
+static void cass_tc_cq_pfq_cfg(struct cass_dev *hw, unsigned int cq_tc,
+			       unsigned int pfq, unsigned int high_thresh)
+{
+	const union c_cq_cfg_pfq_tc_map tc_map_cfg = {
+		.pfq_tc = cq_tc,
+	};
+	const union c_cq_cfg_pfq_thresh_table thresh_table_cfg = {
+		.high_thresh = high_thresh,
+	};
+
+	cass_write(hw, C_CQ_CFG_PFQ_TC_MAP(pfq), &tc_map_cfg,
+		   sizeof(tc_map_cfg));
+	cass_write(hw, C_CQ_CFG_PFQ_THRESH_TABLE(pfq), &thresh_table_cfg,
+		   sizeof(thresh_table_cfg));
+}
+
+static void cass_tc_cq_fq_cfg(struct cass_dev *hw, unsigned int cq_tc,
+			      unsigned int buf_rsvd)
+{
+	const union c_cq_cfg_fq_resrv fq_resrv_cfg = {
+		.num_reserved = buf_rsvd,
+		.max_alloc = 256,
+	};
+
+	cass_write(hw, C_CQ_CFG_FQ_RESRV(cq_tc), &fq_resrv_cfg,
+		   sizeof(fq_resrv_cfg));
+};
+
+static int cass_tc_get_ocuset(struct cass_dev *hw, unsigned int fq_count)
+{
+	int ocuset = hw->next_cq_ocuset;
+
+	if (hw->next_cq_ocuset >= C_CQ_CFG_OCUSET_OCU_TABLE_ENTRIES ||
+	    (hw->next_cq_ocuset + fq_count) >
+	     C_CQ_CFG_OCUSET_OCU_TABLE_ENTRIES)
+		return -EINVAL;
+
+	hw->next_cq_ocuset += fq_count;
+
+	return ocuset;
+}
+
+static int cass_tc_get_ocu(struct cass_dev *hw, unsigned int ocu_count)
+{
+	int ocu = hw->next_cq_ocu;
+
+	if (hw->next_cq_ocu >= C_CQ_CFG_OCU_TABLE_ENTRIES ||
+	    (hw->next_cq_ocu + ocu_count) > C_CQ_CFG_OCU_TABLE_ENTRIES)
+		return -EINVAL;
+
+	hw->next_cq_ocu += ocu_count;
+
+	return ocu;
+}
+
+static int cass_tc_cq_dynamic_ocuset_cfg(struct cass_dev *hw,
+					 unsigned int ocu_base,
+					 unsigned int ocu_count,
+					 unsigned int fq_count)
+{
+	const union c_cq_cfg_ocuset_ocu_table ocu_table_cfg = {
+		.ocu_base = ocu_base,
+		.ocu_count = ilog2(ocu_count),
+	};
+	const union c_cq_cfg_ocuset_fq_table fq_table_cfg = {
+		.fq_count = min_t(unsigned int, fq_count, 8),
+	};
+	int ocuset;
+
+	ocuset = cass_tc_get_ocuset(hw, fq_table_cfg.fq_count);
+	if (ocuset < 0)
+		return ocuset;
+
+	cass_write(hw, C_CQ_CFG_OCUSET_OCU_TABLE(ocuset), &ocu_table_cfg,
+		   sizeof(ocu_table_cfg));
+	cass_write(hw, C_CQ_CFG_OCUSET_FQ_TABLE(ocuset), &fq_table_cfg,
+		   sizeof(fq_table_cfg));
+
+	return ocuset;
+}
+
+static int cass_tc_cq_static_ocuset_cfg(struct cass_dev *hw,
+					unsigned int ocu_base,
+					unsigned int ocu_count,
+					unsigned int fq_count)
+{
+	const union c_cq_cfg_ocuset_ocu_table ocu_table_cfg = {
+		.ocu_base = ocu_base,
+		.ocu_count = ilog2(ocu_count),
+		.ocu_static = 1,
+	};
+	union c_cq_cfg_ocu_table ocu_cfg = {};
+	int ocuset;
+	int ocu;
+
+	ocuset = cass_tc_get_ocuset(hw, fq_count);
+	if (ocuset < 0)
+		return ocuset;
+
+	cass_write(hw, C_CQ_CFG_OCUSET_OCU_TABLE(ocuset), &ocu_table_cfg,
+		   sizeof(ocu_table_cfg));
+
+	for (ocu = ocu_base; ocu < (ocu_base + ocu_count); ocu++) {
+		ocu_cfg.fq = ocuset + (ocu % fq_count);
+
+		cass_write(hw, C_CQ_CFG_OCU_TABLE(ocu), &ocu_cfg,
+			   sizeof(ocu_cfg));
+	}
+
+	return ocuset;
+}
+
+static int cass_tc_cq_cfg(struct cass_dev *hw, enum cxi_traffic_class tc,
+			  unsigned int *cq_mcu_base,
+			  unsigned int *cq_mcu_count,
+			  unsigned int *cq_tc, bool is_static)
+{
+	const struct cass_tc_cq_settings *cq_settings =
+		&hw->qos.tcs[tc].cq_settings;
+	unsigned int fq_count;
+	unsigned int ocu_count;
+	int ocu_base;
+	int tc_cq;
+	int ocuset;
+
+	fq_count = is_static ? cq_settings->static_fq_count :
+		cq_settings->dynamic_fq_count;
+	if (!fq_count)
+		return -EINVAL;
+
+	ocu_count = is_static ? fq_count : fq_count * 4;
+
+	ocu_base = cass_tc_get_ocu(hw, ocu_count);
+	if (ocu_base < 0)
+		return ocu_base;
+
+	tc_cq = cass_tc_get_cq_tc(hw);
+	if (tc_cq < 0)
+		return tc_cq;
+
+	if (is_static)
+		ocuset = cass_tc_cq_static_ocuset_cfg(hw, ocu_base, ocu_count,
+						      fq_count);
+	else
+		ocuset = cass_tc_cq_dynamic_ocuset_cfg(hw, ocu_base, ocu_count,
+						       fq_count);
+	if (ocuset < 0)
+		return ocuset;
+
+	cass_tc_cq_pfq_cfg(hw, tc_cq, ocuset, cq_settings->pfq_high_thresh);
+	cass_tc_cq_fq_cfg(hw, tc_cq, cq_settings->fq_buf_reserved);
+
+	*cq_mcu_base = ocuset + C_OXE_CQ_MCU_START;
+	*cq_mcu_count = fq_count;
+	*cq_tc = tc_cq;
+
+	return ocuset;
+}
+
+static void cass_tc_get_ixe_wrq(struct cass_dev *hw,
+				unsigned int *wrq_base, unsigned int *wrq_mask)
+{
+	*wrq_base = hw->next_ixe_wrq;
+	*wrq_mask = 3;
+
+	hw->next_ixe_wrq += 4;
+	if (hw->next_ixe_wrq >= 32)
+		hw->next_ixe_wrq = 0;
+}
+
+static void cass_tc_ixe_dscp_pcp_map(struct cass_dev *hw, unsigned int dscp,
+				     unsigned int pcp, unsigned int rsp_dscp)
+{
+	union c_ixe_cfg_dscp_wrq_map wrq_map_cfg;
+	union c_ixe_cfg_dscp_dscp_tc_map tc_map_cfg;
+	unsigned int wrq_base;
+	unsigned int wrq_mask;
+	unsigned int index = dscp / C_IXE_CFG_DSCP_DSCP_TC_MAP_ARRAY_SIZE;
+	unsigned int offset = dscp % C_IXE_CFG_DSCP_DSCP_TC_MAP_ARRAY_SIZE;
+
+	cass_tc_get_ixe_wrq(hw, &wrq_base, &wrq_mask);
+
+	cass_read(hw, C_IXE_CFG_DSCP_WRQ_MAP(dscp), &wrq_map_cfg,
+		  sizeof(wrq_map_cfg));
+
+	wrq_map_cfg.base = wrq_base;
+	wrq_map_cfg.hash_mask = wrq_mask;
+
+	cass_write(hw, C_IXE_CFG_DSCP_WRQ_MAP(dscp), &wrq_map_cfg,
+		   sizeof(wrq_map_cfg));
+
+	cass_read(hw, C_IXE_CFG_DSCP_DSCP_TC_MAP(index), &tc_map_cfg,
+		  sizeof(tc_map_cfg));
+
+	tc_map_cfg.map[offset].dscp = rsp_dscp;
+	tc_map_cfg.map[offset].tc = pcp;
+
+	cass_write(hw, C_IXE_CFG_DSCP_DSCP_TC_MAP(index), &tc_map_cfg,
+		   sizeof(tc_map_cfg));
+}
+
+static int cass_tc_get_ixe_fq(struct cass_dev *hw, unsigned int fq_count)
+{
+	int fq = hw->next_ixe_fq;
+
+	if (hw->next_ixe_fq >= 24 ||
+	    (hw->next_ixe_fq + fq_count) > 24)
+		return -EINVAL;
+
+	hw->next_ixe_fq += fq_count;
+
+	return fq;
+}
+
+static int cass_tc_ixe_fq_cfg(struct cass_dev *hw, enum cxi_traffic_class tc,
+			      unsigned int req_pcp, unsigned int *ixe_mcu_base,
+			      unsigned int *ixe_mcu_count)
+{
+	const struct cass_tc_ixe_settings *ixe_settings =
+		&hw->qos.tcs[tc].ixe_settings;
+	union c_ixe_cfg_tc_fq_map fq_map_cfg = {};
+	union c_ixe_cfg_mp_tc_fq_map mp_fq_map_cfg = {};
+	unsigned int i;
+	int fq_base;
+
+	fq_base = cass_tc_get_ixe_fq(hw, ixe_settings->fq_count);
+	if (fq_base < 0)
+		return fq_base;
+
+	for (i = 0; i < ixe_settings->fq_count; i++)
+		fq_map_cfg.put_resp_mask |= BIT(fq_base + i);
+	fq_map_cfg.get_req_mask = fq_map_cfg.put_resp_mask;
+
+	cass_write(hw, C_IXE_CFG_TC_FQ_MAP(req_pcp), &fq_map_cfg,
+		   sizeof(fq_map_cfg));
+
+	mp_fq_map_cfg.base = fq_base;
+	mp_fq_map_cfg.num_fqs_mask =
+		min_t(unsigned int, 4,
+		      rounddown_pow_of_two(ixe_settings->fq_count)) - 1;
+
+	cass_write(hw, C_IXE_CFG_MP_TC_FQ_MAP(req_pcp), &mp_fq_map_cfg,
+		   sizeof(mp_fq_map_cfg));
+
+	*ixe_mcu_base = fq_base + C_OXE_IXE_MCU_START;
+	*ixe_mcu_count = ixe_settings->fq_count;
+
+	return 0;
+}
+
+static int cass_tc_get_lpe_fq(struct cass_dev *hw, unsigned int fq_count)
+{
+	int fq = hw->next_lpe_fq;
+
+	if (hw->next_lpe_fq >= 16 ||
+	    (hw->next_lpe_fq + fq_count) > 16)
+		return -EINVAL;
+
+	hw->next_lpe_fq += fq_count;
+
+	return fq;
+}
+
+static int cass_tc_lpe_fq_cfg(struct cass_dev *hw, unsigned int req_pcp,
+			      unsigned int fq_count)
+{
+	union c_lpe_cfg_fq_tc_map fq_tc_map_cfg;
+	int fq_base;
+
+	fq_base = cass_tc_get_lpe_fq(hw, fq_count);
+	if (fq_base < 0)
+		return fq_base;
+
+	cass_read(hw, C_LPE_CFG_FQ_TC_MAP, &fq_tc_map_cfg,
+		  sizeof(fq_tc_map_cfg));
+
+	fq_tc_map_cfg.tc[req_pcp].fq_base = fq_base;
+	fq_tc_map_cfg.tc[req_pcp].fq_mask =
+		min_t(unsigned int, 8, rounddown_pow_of_two(fq_count)) - 1;
+
+	cass_write(hw, C_LPE_CFG_FQ_TC_MAP, &fq_tc_map_cfg,
+		   sizeof(fq_tc_map_cfg));
+
+	return fq_base;
+}
+
+static int cass_tc_lpe_cfg(struct cass_dev *hw, enum cxi_traffic_class tc,
+			   unsigned int req_pcp, unsigned int *lpe_mcu_base,
+			   unsigned int *lpe_mcu_count)
+{
+	const struct cass_tc_lpe_settings *lpe_settings =
+		&hw->qos.tcs[tc].lpe_settings;
+	int fq_base;
+
+	fq_base = cass_tc_lpe_fq_cfg(hw, req_pcp, lpe_settings->fq_count);
+	if (fq_base < 0)
+		return fq_base;
+
+	*lpe_mcu_base = fq_base + C_OXE_LPE_MCU_START;
+	*lpe_mcu_count = lpe_settings->fq_count;
+
+	return 0;
+}
+
+static void cass_tc_pct_pcp_cfg(struct cass_dev *hw, unsigned int req_pcp,
+				unsigned int trs_rsvd, unsigned int trs_max,
+				unsigned int tct_rsvd, unsigned int tct_max,
+				unsigned int mst_rsvd, unsigned int mst_max)
+{
+	const union c_pct_cfg_mst_tc_ded_limit mst_ded_limit_cfg = {
+		.ded_limit = mst_rsvd,
+	};
+	const union c_pct_cfg_mst_tc_max_limit mst_max_limit_cfg = {
+		.max_limit = mst_max,
+	};
+	const union c_pct_cfg_tct_tc_ded_limit tct_ded_limit_cfg = {
+		.ded_limit = tct_rsvd,
+	};
+	const union c_pct_cfg_tct_tc_max_limit tct_max_limit_cfg = {
+		.max_limit = tct_max,
+	};
+
+	if (cass_version(hw, CASSINI_1)) {
+		const union c1_pct_cfg_trs_tc_ded_limit trs_ded_limit_cfg = {
+			.ded_limit = trs_rsvd,
+		};
+		const union c1_pct_cfg_trs_tc_max_limit trs_max_limit_cfg = {
+			.max_limit = trs_max,
+		};
+
+		cass_write(hw, C1_PCT_CFG_TRS_TC_DED_LIMIT(req_pcp),
+			   &trs_ded_limit_cfg, sizeof(trs_ded_limit_cfg));
+		cass_write(hw, C1_PCT_CFG_TRS_TC_MAX_LIMIT(req_pcp),
+			   &trs_max_limit_cfg, sizeof(trs_max_limit_cfg));
+	} else {
+		const union c2_pct_cfg_trs_tc_ded_limit trs_ded_limit_cfg = {
+			.ded_limit = trs_rsvd,
+		};
+		const union c2_pct_cfg_trs_tc_max_limit trs_max_limit_cfg = {
+			.max_limit = trs_max,
+		};
+
+		cass_write(hw, C2_PCT_CFG_TRS_TC_DED_LIMIT(req_pcp),
+			   &trs_ded_limit_cfg, sizeof(trs_ded_limit_cfg));
+		cass_write(hw, C2_PCT_CFG_TRS_TC_MAX_LIMIT(req_pcp),
+			   &trs_max_limit_cfg, sizeof(trs_max_limit_cfg));
+	}
+
+	cass_write(hw, C_PCT_CFG_MST_TC_DED_LIMIT(req_pcp), &mst_ded_limit_cfg,
+		   sizeof(mst_ded_limit_cfg));
+	cass_write(hw, C_PCT_CFG_MST_TC_MAX_LIMIT(req_pcp), &mst_max_limit_cfg,
+		   sizeof(mst_max_limit_cfg));
+	cass_write(hw, C_PCT_CFG_TCT_TC_DED_LIMIT(req_pcp), &tct_ded_limit_cfg,
+		   sizeof(tct_ded_limit_cfg));
+	cass_write(hw, C_PCT_CFG_TCT_TC_MAX_LIMIT(req_pcp), &tct_max_limit_cfg,
+		   sizeof(tct_max_limit_cfg));
+}
+
+static void cass_tc_pct_dscp_pcp_map(struct cass_dev *hw, unsigned int req_pcp,
+				     unsigned int rsp_pcp,
+				     unsigned int req_dscp,
+				     unsigned int rsp_dscp)
+{
+	union c_pct_cfg_req_tc_rsp_tc_map req_tc_rsp_tc_map;
+	union c_pct_cfg_req_dscp_rsp_dscp_map req_dscp_rsp_dscp_map;
+	union c_pct_cfg_rsp_dscp_req_tc_map rsp_dscp_req_tc_map;
+	int req_dscp_index = req_dscp / 8;
+	int req_dscp_offset = req_dscp % 8;
+	int rsp_dscp_index = rsp_dscp / 16;
+
+	cass_read(hw, C_PCT_CFG_REQ_TC_RSP_TC_MAP, &req_tc_rsp_tc_map,
+		  sizeof(req_tc_rsp_tc_map));
+
+	/* Map the provided req_pcp to the provided rsp_pcp */
+	switch (req_pcp) {
+	case 0:
+		req_tc_rsp_tc_map.req_tc0 = rsp_pcp;
+		break;
+	case 1:
+		req_tc_rsp_tc_map.req_tc1 = rsp_pcp;
+		break;
+	case 2:
+		req_tc_rsp_tc_map.req_tc2 = rsp_pcp;
+		break;
+	case 3:
+		req_tc_rsp_tc_map.req_tc3 = rsp_pcp;
+		break;
+	case 4:
+		req_tc_rsp_tc_map.req_tc4 = rsp_pcp;
+		break;
+	case 5:
+		req_tc_rsp_tc_map.req_tc5 = rsp_pcp;
+		break;
+	case 6:
+		req_tc_rsp_tc_map.req_tc6 = rsp_pcp;
+		break;
+	default:
+		req_tc_rsp_tc_map.req_tc7 = rsp_pcp;
+		break;
+	}
+
+	cass_write(hw, C_PCT_CFG_REQ_TC_RSP_TC_MAP, &req_tc_rsp_tc_map,
+		   sizeof(req_tc_rsp_tc_map));
+
+	cass_read(hw, C_PCT_CFG_REQ_DSCP_RSP_DSCP_MAP(req_dscp_index),
+		  &req_dscp_rsp_dscp_map, sizeof(req_dscp_rsp_dscp_map));
+
+	req_dscp_rsp_dscp_map.map[req_dscp_offset].rsp_dscp = rsp_dscp;
+
+	cass_write(hw, C_PCT_CFG_REQ_DSCP_RSP_DSCP_MAP(req_dscp_index),
+		   &req_dscp_rsp_dscp_map, sizeof(req_dscp_rsp_dscp_map));
+
+	cass_read(hw, C_PCT_CFG_RSP_DSCP_REQ_TC_MAP(rsp_dscp_index),
+		  &rsp_dscp_req_tc_map, sizeof(rsp_dscp_req_tc_map));
+
+	switch (rsp_dscp % 16) {
+	case 0:
+		rsp_dscp_req_tc_map.dscp0_tc = req_pcp;
+		break;
+	case 1:
+		rsp_dscp_req_tc_map.dscp1_tc = req_pcp;
+		break;
+	case 2:
+		rsp_dscp_req_tc_map.dscp2_tc = req_pcp;
+		break;
+	case 3:
+		rsp_dscp_req_tc_map.dscp3_tc = req_pcp;
+		break;
+	case 4:
+		rsp_dscp_req_tc_map.dscp4_tc = req_pcp;
+		break;
+	case 5:
+		rsp_dscp_req_tc_map.dscp5_tc = req_pcp;
+		break;
+	case 6:
+		rsp_dscp_req_tc_map.dscp6_tc = req_pcp;
+		break;
+	case 7:
+		rsp_dscp_req_tc_map.dscp7_tc = req_pcp;
+		break;
+	case 8:
+		rsp_dscp_req_tc_map.dscp8_tc = req_pcp;
+		break;
+	case 9:
+		rsp_dscp_req_tc_map.dscp9_tc = req_pcp;
+		break;
+	case 10:
+		rsp_dscp_req_tc_map.dscp10_tc = req_pcp;
+		break;
+	case 11:
+		rsp_dscp_req_tc_map.dscp11_tc = req_pcp;
+		break;
+	case 12:
+		rsp_dscp_req_tc_map.dscp12_tc = req_pcp;
+		break;
+	case 13:
+		rsp_dscp_req_tc_map.dscp13_tc = req_pcp;
+		break;
+	case 14:
+		rsp_dscp_req_tc_map.dscp14_tc = req_pcp;
+		break;
+	default:
+		rsp_dscp_req_tc_map.dscp15_tc = req_pcp;
+		break;
+	}
+
+	cass_write(hw, C_PCT_CFG_RSP_DSCP_REQ_TC_MAP(rsp_dscp_index),
+		   &rsp_dscp_req_tc_map, sizeof(rsp_dscp_req_tc_map));
+}
+
+static unsigned int cass_tc_get_pct_shared_trs_limit(struct cass_dev *hw)
+{
+	enum cxi_traffic_class tc;
+	int rsvd = 0;
+
+	for (tc = 0; tc < CXI_MAX_RDMA_TCS; tc++) {
+		if (!hw->qos.tcs_active[tc])
+			continue;
+		rsvd += hw->qos.tcs[tc].pct_settings.trs_rsvd;
+	}
+
+	if (cass_version(hw, CASSINI_1))
+		return max_t(unsigned int, C1_PCT_CFG_TRS_CAM_ENTRIES - rsvd, 0);
+	else
+		return max_t(unsigned int, C2_PCT_CFG_TRS_CAM_ENTRIES - rsvd, 0);
+}
+
+static unsigned int cass_tc_get_pct_shared_mst_limit(struct cass_dev *hw)
+{
+	enum cxi_traffic_class tc;
+	int rsvd = 0;
+
+	for (tc = 0; tc < CXI_MAX_RDMA_TCS; tc++) {
+		if (!hw->qos.tcs_active[tc])
+			continue;
+		rsvd += hw->qos.tcs[tc].pct_settings.mst_rsvd;
+	}
+
+	return max_t(unsigned int, C_MST_DBG_MST_TABLE_ENTRIES - rsvd, 0);
+}
+
+static unsigned int cass_tc_get_pct_shared_tct_limit(struct cass_dev *hw)
+{
+	enum cxi_traffic_class tc;
+	int rsvd = 0;
+
+	for (tc = 0; tc < CXI_MAX_RDMA_TCS; tc++) {
+		if (!hw->qos.tcs_active[tc])
+			continue;
+		rsvd += hw->qos.tcs[tc].pct_settings.tct_rsvd;
+	}
+
+	return max_t(unsigned int, C_PCT_CFG_TCT_RAM_ENTRIES - rsvd, 0);
+}
+
+static void cass_tc_pct_cfg(struct cass_dev *hw, enum cxi_traffic_class tc,
+			    unsigned int req_pcp)
+{
+	const struct cass_tc_pct_settings *pct_settings =
+		&hw->qos.tcs[tc].pct_settings;
+	unsigned int shared_trs_limit = cass_tc_get_pct_shared_trs_limit(hw);
+	unsigned int shared_mst_limit = cass_tc_get_pct_shared_mst_limit(hw);
+	unsigned int shared_tct_limit = cass_tc_get_pct_shared_tct_limit(hw);
+
+	if (hw->reduced_pct_tables) {
+		cass_tc_pct_pcp_cfg(hw, req_pcp, 8,
+				    8 + 64,
+				    8,
+				    8 + 32,
+				    8,
+				    8 + 64);
+	} else {
+		cass_tc_pct_pcp_cfg(hw, req_pcp, pct_settings->trs_rsvd,
+				    pct_settings->trs_rsvd + shared_trs_limit,
+				    pct_settings->tct_rsvd,
+				    pct_settings->tct_rsvd + shared_tct_limit,
+				    pct_settings->mst_rsvd,
+				    pct_settings->mst_rsvd + shared_mst_limit);
+	}
+}
+
+static void cass_tc_pct_global_cfg(struct cass_dev *hw)
+{
+	const union c_pct_cfg_mst_crdt_limits mst_crdt_limits = {
+		.total_limit = hw->reduced_pct_tables ?
+			128 : C_MST_DBG_MST_TABLE_ENTRIES,
+		.shared_limit = hw->reduced_pct_tables ?
+			64 : cass_tc_get_pct_shared_mst_limit(hw),
+	};
+	const union c_pct_cfg_tct_crdt_limits tct_crdt_limits = {
+		.total_limit = hw->reduced_pct_tables ?
+			96 : C_PCT_CFG_TCT_RAM_ENTRIES,
+		.shared_limit = hw->reduced_pct_tables ?
+			32 : cass_tc_get_pct_shared_tct_limit(hw),
+	};
+
+	if (cass_version(hw, CASSINI_1)) {
+		const union c1_pct_cfg_trs_crdt_limits trs_crdt_limits = {
+			.total_limit = C1_PCT_CFG_TRS_CAM_ENTRIES,
+			.shared_limit = cass_tc_get_pct_shared_trs_limit(hw),
+		};
+
+		cass_write(hw, C1_PCT_CFG_TRS_CRDT_LIMITS, &trs_crdt_limits,
+			   sizeof(trs_crdt_limits));
+	} else {
+		const union c2_pct_cfg_trs_crdt_limits trs_crdt_limits = {
+			.total_limit = hw->reduced_pct_tables ?
+				128 : C2_PCT_CFG_TRS_CAM_ENTRIES,
+			.shared_limit = hw->reduced_pct_tables ?
+				64 : cass_tc_get_pct_shared_trs_limit(hw),
+		};
+
+		cass_write(hw, C2_PCT_CFG_TRS_CRDT_LIMITS, &trs_crdt_limits,
+			   sizeof(trs_crdt_limits));
+	}
+
+	cass_write(hw, C_PCT_CFG_MST_CRDT_LIMITS, &mst_crdt_limits,
+		   sizeof(mst_crdt_limits));
+	cass_write(hw, C_PCT_CFG_TCT_CRDT_LIMITS, &tct_crdt_limits,
+		   sizeof(tct_crdt_limits));
+}
+
+#define PFC_BUF_UNITS 64U
+
+#define C1_ETHERNET_PAUSE_RESPONSE_TIME_BYTES (15 * 1024)
+#define C2_ETHERNET_PAUSE_RESPONSE_TIME_BYTES (57 * 1024)
+
+#define C1_MAX_CABLE_LENGTH_BYTES 2560
+#define C2_MAX_CABLE_LENGTH_BYTES (5 * 1024)
+
+#define C1_MAC_LATENCY_BYTES (4 * 1024)
+#define C2_MAC_LATENCY_BYTES (10 * 1024)
+
+#define MAX_PACKET_SIZE (9 * 1024)
+#define STORE_AND_FORWARD_FIFO (9 * 1024)
+
+#define C1_SKID_BUF_SIZE (64 * 1024)
+#define C2_SKID_BUF_SIZE (128 * 1024)
+
+static unsigned int cass_tc_get_pfc_high_water(const struct cass_dev *hw)
+{
+	unsigned int skid_space;
+	unsigned int skid_buf_size;
+
+	if (cass_version(hw, CASSINI_1)) {
+		skid_space = C1_ETHERNET_PAUSE_RESPONSE_TIME_BYTES +
+			C1_MAX_CABLE_LENGTH_BYTES + C1_MAC_LATENCY_BYTES +
+			(2 * MAX_PACKET_SIZE) + STORE_AND_FORWARD_FIFO;
+		skid_buf_size = C1_SKID_BUF_SIZE;
+	} else {
+		skid_space = C2_ETHERNET_PAUSE_RESPONSE_TIME_BYTES +
+			C2_MAX_CABLE_LENGTH_BYTES + C2_MAC_LATENCY_BYTES +
+			(2 * MAX_PACKET_SIZE) + STORE_AND_FORWARD_FIFO;
+		skid_buf_size = C2_SKID_BUF_SIZE;
+	}
+
+	/* NIC-to-NIC needs extra store and forward fifo space. */
+	if (!switch_connected)
+		skid_space += STORE_AND_FORWARD_FIFO;
+
+	/* Only use the user-defined PFC buffer skid space if the requested skid
+	 * space is at least the minimal value.
+	 */
+	if (pfc_buf_skid_space) {
+		if (pfc_buf_skid_space < skid_space)
+			pr_info_once("PFC buf skid space %u too small. Using default %u\n",
+				     pfc_buf_skid_space, skid_space);
+		else if (pfc_buf_skid_space > (skid_buf_size - PFC_BUF_UNITS))
+			pr_info_once("PFC buf skid space %u too large. Using default %u\n",
+				     pfc_buf_skid_space, skid_space);
+		else
+			skid_space = pfc_buf_skid_space;
+	}
+
+	return (skid_buf_size - skid_space) / PFC_BUF_UNITS;
+}
+
+#define HIGH_LOW_WATER_SKID_SPACE_DELTA 4096U
+
+static unsigned int cass_tc_get_pfc_low_water(const struct cass_dev *hw)
+{
+	return max_t(int,
+		     (int)cass_tc_get_pfc_high_water(hw) -
+		     (int)(HIGH_LOW_WATER_SKID_SPACE_DELTA / PFC_BUF_UNITS), 0);
+}
+
+static void cass_tc_hni_pcp_cfg(struct cass_dev *hw, unsigned int pcp,
+				unsigned int pbuf_rsvd,
+				unsigned int max_frame_size)
+{
+	union c_hni_cfg_pbuf cfg_pbuf_cfg;
+
+	/* Since PCP packet buffer space is shared between Portals and Ethernet
+	 * traffic and my be updated twice for Portals and Ethernet
+	 * configuration, always take the max configured value.
+	 */
+	cass_read(hw, C_HNI_CFG_PBUF(pcp), &cfg_pbuf_cfg,
+		  sizeof(cfg_pbuf_cfg));
+
+	cfg_pbuf_cfg.mtu = max_t(unsigned int, cfg_pbuf_cfg.mtu,
+				 DIV_ROUND_UP(max_frame_size, 128));
+	cfg_pbuf_cfg.static_rsvd =
+		max_t(unsigned int, cfg_pbuf_cfg.static_rsvd, pbuf_rsvd);
+
+	cass_write(hw, C_HNI_CFG_PBUF(pcp), &cfg_pbuf_cfg,
+		   sizeof(cfg_pbuf_cfg));
+
+	if (cass_version(hw, CASSINI_1)) {
+		const union c1_hni_cfg_pfc_buf pfc_buf_cfg = {
+			.high_water = cass_tc_get_pfc_high_water(hw),
+			.low_water = cass_tc_get_pfc_low_water(hw),
+		};
+
+		cass_write(hw, C1_HNI_CFG_PFC_BUF(pcp), &pfc_buf_cfg,
+			   sizeof(pfc_buf_cfg));
+	} else {
+		const union c2_hni_cfg_pfc_buf pfc_buf_cfg = {
+			.high_water = cass_tc_get_pfc_high_water(hw),
+			.low_water = cass_tc_get_pfc_low_water(hw),
+		};
+
+		cass_write(hw, C2_HNI_CFG_PFC_BUF(pcp), &pfc_buf_cfg,
+			   sizeof(pfc_buf_cfg));
+	}
+}
+
+static void cass_tc_hni_dscp_pcp_map(struct cass_dev *hw, unsigned int dscp,
+				     unsigned int pcp)
+{
+	const union c_hni_cfg_dscp_pcp dscp_pcp_cfg = {
+		.pcp = pcp,
+	};
+
+	cass_write(hw, C_HNI_CFG_DSCP_PCP(dscp), &dscp_pcp_cfg,
+		   sizeof(dscp_pcp_cfg));
+}
+
+static void cass_tc_enable_tx_pause(struct cass_dev *hw, unsigned int pcp)
+{
+	union c_hni_cfg_pause_tx_ctrl tx_ctrl_cfg;
+
+	cass_read(hw, C_HNI_CFG_PAUSE_TX_CTRL, &tx_ctrl_cfg, sizeof(tx_ctrl_cfg));
+
+	tx_ctrl_cfg.enable_send_pause |= BIT(pcp);
+	tx_ctrl_cfg.pev |= BIT(pcp);
+
+	cass_write(hw, C_HNI_CFG_PAUSE_TX_CTRL, &tx_ctrl_cfg, sizeof(tx_ctrl_cfg));
+}
+
+static void cass_tc_disable_tx_pause(struct cass_dev *hw, unsigned int pcp)
+{
+	union c_hni_cfg_pause_tx_ctrl tx_ctrl_cfg;
+
+	cass_read(hw, C_HNI_CFG_PAUSE_TX_CTRL, &tx_ctrl_cfg, sizeof(tx_ctrl_cfg));
+
+	tx_ctrl_cfg.enable_send_pause &= ~BIT(pcp);
+	tx_ctrl_cfg.pev &= ~BIT(pcp);
+
+	cass_write(hw, C_HNI_CFG_PAUSE_TX_CTRL, &tx_ctrl_cfg, sizeof(tx_ctrl_cfg));
+}
+
+static void cass_tc_enable_rx_pause(struct cass_dev *hw, unsigned int pcp)
+{
+	union c_hni_cfg_pause_rx_ctrl rx_ctrl_cfg;
+
+	cass_read(hw, C_HNI_CFG_PAUSE_RX_CTRL, &rx_ctrl_cfg, sizeof(rx_ctrl_cfg));
+
+	if (pcp == hw->qos.pct_control_pcp) {
+		/* Never enable the receiving of PFC pause if the
+		 * response PCP of a given traffic class is to be used
+		 * for PCT control traffic.  Failure to do this
+		 * results in packet drops and performance issues.
+		 */
+		rx_ctrl_cfg.enable_rec_pause &= ~BIT(pcp);
+	} else {
+		rx_ctrl_cfg.enable_rec_pause |= BIT(pcp);
+	}
+
+	cass_write(hw, C_HNI_CFG_PAUSE_RX_CTRL, &rx_ctrl_cfg, sizeof(rx_ctrl_cfg));
+}
+
+static void cass_tc_disable_rx_pause(struct cass_dev *hw, unsigned int pcp)
+{
+	union c_hni_cfg_pause_rx_ctrl rx_ctrl_cfg;
+
+	cass_read(hw, C_HNI_CFG_PAUSE_RX_CTRL, &rx_ctrl_cfg,
+		  sizeof(rx_ctrl_cfg));
+
+	rx_ctrl_cfg.enable_rec_pause &= ~(1U << pcp);
+
+	cass_write(hw, C_HNI_CFG_PAUSE_RX_CTRL, &rx_ctrl_cfg,
+		   sizeof(rx_ctrl_cfg));
+}
+
+static void cass_tc_enable_pauses(struct cass_dev *hw, unsigned int pcp)
+{
+	cass_tc_enable_tx_pause(hw, pcp);
+	cass_tc_enable_rx_pause(hw, pcp);
+}
+
+void cass_tc_set_tx_pause_all(struct cass_dev *hw, bool enable)
+{
+	int i;
+
+	for (i = 0; i < PCP_COUNT; i++) {
+		if (enable)
+			cass_tc_enable_tx_pause(hw, i);
+		else
+			cass_tc_disable_tx_pause(hw, i);
+	}
+}
+
+void cass_tc_set_rx_pause_all(struct cass_dev *hw, bool enable)
+{
+	int i;
+
+	for (i = 0; i < PCP_COUNT; i++) {
+		if (enable)
+			cass_tc_enable_rx_pause(hw, i);
+		else
+			cass_tc_disable_rx_pause(hw, i);
+	}
+}
+
+void cass_tc_get_hni_pause_cfg(struct cass_dev *hw)
+{
+	u32 pause_type;
+	bool tx_pause;
+	bool rx_pause;
+	union c_hni_cfg_pause_tx_ctrl tx_ctrl_cfg;
+	union c_hni_cfg_pause_rx_ctrl rx_ctrl_cfg;
+
+	cass_read(hw, C_HNI_CFG_PAUSE_TX_CTRL, &tx_ctrl_cfg,
+		  sizeof(tx_ctrl_cfg));
+
+	cass_read(hw, C_HNI_CFG_PAUSE_RX_CTRL, &rx_ctrl_cfg,
+		  sizeof(rx_ctrl_cfg));
+
+	tx_pause = ((tx_ctrl_cfg.enable_pfc_pause && tx_ctrl_cfg.pev) ||
+		    tx_ctrl_cfg.enable_pause) && tx_ctrl_cfg.enable_send_pause;
+
+	rx_pause = (rx_ctrl_cfg.pfc_rec_enable ||
+		    rx_ctrl_cfg.pause_rec_enable) &&
+		   rx_ctrl_cfg.enable_rec_pause;
+
+	if (!tx_ctrl_cfg.enable_pfc_pause && !tx_ctrl_cfg.enable_pause &&
+	    !rx_ctrl_cfg.pfc_rec_enable && !rx_ctrl_cfg.pause_rec_enable)
+		pause_type = CASS_PAUSE_TYPE_NONE;
+	else if (!tx_ctrl_cfg.enable_pfc_pause && tx_ctrl_cfg.enable_pause &&
+		 !rx_ctrl_cfg.pfc_rec_enable && rx_ctrl_cfg.pause_rec_enable)
+		pause_type = CASS_PAUSE_TYPE_GLOBAL;
+	else if (tx_ctrl_cfg.enable_pfc_pause &&
+		 rx_ctrl_cfg.pfc_rec_enable && !rx_ctrl_cfg.pause_rec_enable)
+		pause_type = CASS_PAUSE_TYPE_PFC;
+	else
+		pause_type = CASS_PAUSE_TYPE_INVALID;
+
+	spin_lock(&hw->port->pause_lock);
+	hw->port->pause_type = pause_type;
+	hw->port->tx_pause = tx_pause;
+	hw->port->rx_pause = rx_pause;
+	spin_unlock(&hw->port->pause_lock);
+}
+
+static void cass_tc_hni_cfg(struct cass_dev *hw, enum cxi_traffic_class tc,
+			    unsigned int req_pcp, unsigned int rsp_pcp)
+{
+	const struct cass_tc_hni_settings *hni_settings =
+		&hw->qos.tcs[tc].hni_settings;
+
+	cass_tc_hni_pcp_cfg(hw, req_pcp, hni_settings->pbuf_rsvd,
+			    hni_settings->mfs);
+
+	/* Response PCP is ignored for Ethernet configuration. */
+	if (tc != CXI_TC_ETH)
+		cass_tc_hni_pcp_cfg(hw, rsp_pcp, hni_settings->pbuf_rsvd,
+				    hni_settings->mfs);
+
+	/* TODO: Support disabling pause and global pause. */
+	cass_tc_enable_pauses(hw, req_pcp);
+
+	if (tc != CXI_TC_ETH)
+		cass_tc_enable_pauses(hw, rsp_pcp);
+}
+
+#define C1_RESTRICTED_BC_SPT_RSVD 1500U
+#define RESTRICTED_BC_SMT_RSVD 0U
+#define RESTRICTED_BC_SCT_RSVD 0U
+#define RESTRICTED_BC_SRB_RSVD 39U
+#define RESTRICTED_BC_PBUF_RSVD 39U
+
+/**
+ * cass_tc_init_res_req_oxe_bc() - Initialize global OXE buffer class to be
+ * used for restricted request MCUs.
+ *
+ * @hw: Cassini device
+ *
+ * This buffer class is to be used by all CXI_TC_TYPE_HRP and
+ * CXI_TC_TYPE_RESTRICTED traffic class types.
+ *
+ * This only applies for C1.
+ */
+static int cass_tc_init_res_req_oxe_bc(struct cass_dev *hw)
+{
+	int bc;
+
+	bc = cass_tc_req_oxe_bc_cfg(hw, C1_RESTRICTED_BC_SPT_RSVD,
+				    RESTRICTED_BC_SMT_RSVD,
+				    RESTRICTED_BC_SCT_RSVD,
+				    RESTRICTED_BC_SRB_RSVD,
+				    RESTRICTED_BC_PBUF_RSVD);
+
+	return bc;
+}
+
+/* Set the DSCP DFA mask. */
+static void set_dscp_dfa_mask(struct cass_dev *hw,
+			      int dscp, unsigned int new_mask)
+{
+	union c_pct_cfg_sct_tag_dfa_mask dfa_mask;
+	unsigned int idx = dscp / 4;
+	unsigned int offset = dscp % 4;
+
+	if (dscp == -1)
+		return;
+
+	cass_read(hw, C_PCT_CFG_SCT_TAG_DFA_MASK(idx),
+		  &dfa_mask, sizeof(dfa_mask));
+
+	dfa_mask.dscp[offset].dfa_mask = new_mask;
+
+	cass_write(hw, C_PCT_CFG_SCT_TAG_DFA_MASK(idx),
+		   &dfa_mask, sizeof(dfa_mask));
+
+	if (cass_version(hw, CASSINI_2))
+		cass_write(hw, C2_LPE_CFG_GET_FQ_DFA_MASK(idx),
+			   &dfa_mask, sizeof(dfa_mask));
+}
+
+/**
+ * cass_tc_dscp_pcp_map() - For all traffic classes, map DSCP and PCP values in
+ * hardware.
+ *
+ * @hw: Cassini device
+ */
+static void cass_tc_dscp_pcp_map(struct cass_dev *hw)
+{
+	int i;
+	const struct cass_tc_dscp_pcp_settings *dscp_pcp_settings;
+	const struct qos_profile *prof = &hw->qos;
+
+	/* For each TC program mappings into HW */
+	for (i = 0; i < CXI_MAX_RDMA_TCS; i++) {
+		/* Don't configure inactive TCs */
+		if (!prof->tcs_active[i])
+			continue;
+		dscp_pcp_settings = &prof->tcs[i].dscp_pcp_settings;
+
+		/* IXE Mappings */
+		cass_tc_ixe_dscp_pcp_map(hw, dscp_pcp_settings->res_req_dscp,
+					 dscp_pcp_settings->req_pcp,
+					 dscp_pcp_settings->res_rsp_dscp);
+		cass_tc_ixe_dscp_pcp_map(hw, dscp_pcp_settings->res_rsp_dscp,
+					 dscp_pcp_settings->rsp_pcp, 0);
+		cass_tc_ixe_dscp_pcp_map(hw, dscp_pcp_settings->unres_req_dscp,
+					 dscp_pcp_settings->req_pcp,
+					 dscp_pcp_settings->unres_rsp_dscp);
+		cass_tc_ixe_dscp_pcp_map(hw, dscp_pcp_settings->unres_rsp_dscp,
+					 dscp_pcp_settings->rsp_pcp, 0);
+
+		/* PCT Mapping Restricted Request DSCP */
+		cass_tc_pct_dscp_pcp_map(hw, dscp_pcp_settings->req_pcp,
+					 prof->pct_control_pcp,
+					 dscp_pcp_settings->res_req_dscp,
+					 dscp_pcp_settings->res_rsp_dscp);
+
+		/* PCT Mapping Unrestricted Request DSCP */
+		cass_tc_pct_dscp_pcp_map(hw, dscp_pcp_settings->req_pcp,
+					 prof->pct_control_pcp,
+					 dscp_pcp_settings->unres_req_dscp,
+					 dscp_pcp_settings->unres_rsp_dscp);
+
+		/* HNI Mappings */
+		cass_tc_hni_dscp_pcp_map(hw, dscp_pcp_settings->res_req_dscp,
+					 dscp_pcp_settings->req_pcp);
+		cass_tc_hni_dscp_pcp_map(hw, dscp_pcp_settings->res_rsp_dscp,
+					 dscp_pcp_settings->rsp_pcp);
+		cass_tc_hni_dscp_pcp_map(hw, dscp_pcp_settings->unres_req_dscp,
+					 dscp_pcp_settings->req_pcp);
+		cass_tc_hni_dscp_pcp_map(hw, dscp_pcp_settings->unres_rsp_dscp,
+					 dscp_pcp_settings->rsp_pcp);
+
+		/* Optionally configure TC "Type" CXI_TC_TYPE_HRP. */
+		if (dscp_pcp_settings->hrp_res_req_dscp >= 0) {
+			cass_tc_ixe_dscp_pcp_map(hw,
+						 dscp_pcp_settings->hrp_res_req_dscp,
+						 dscp_pcp_settings->req_pcp,
+						 dscp_pcp_settings->res_rsp_dscp);
+			cass_tc_pct_dscp_pcp_map(hw, dscp_pcp_settings->req_pcp,
+						 prof->pct_control_pcp,
+						 dscp_pcp_settings->hrp_res_req_dscp,
+						 dscp_pcp_settings->res_rsp_dscp);
+			cass_tc_hni_dscp_pcp_map(hw,
+						 dscp_pcp_settings->hrp_res_req_dscp,
+						 dscp_pcp_settings->req_pcp);
+		}
+
+		/* Optionally configure TC "Type" CXI_TC_TYPE_COLL_LEAF. */
+		if (dscp_pcp_settings->coll_leaf_res_req_dscp >= 0) {
+			cass_tc_ixe_dscp_pcp_map(hw,
+						 dscp_pcp_settings->coll_leaf_res_req_dscp,
+						 dscp_pcp_settings->req_pcp,
+						 dscp_pcp_settings->res_rsp_dscp);
+			cass_tc_pct_dscp_pcp_map(hw, dscp_pcp_settings->req_pcp,
+						 prof->pct_control_pcp,
+						 dscp_pcp_settings->coll_leaf_res_req_dscp,
+						 dscp_pcp_settings->res_rsp_dscp);
+			cass_tc_hni_dscp_pcp_map(hw,
+						 dscp_pcp_settings->coll_leaf_res_req_dscp,
+						 dscp_pcp_settings->req_pcp);
+		}
+
+		/* Optionally configure TC "Type" CXI_TC_TYPE_RESTRICTED. */
+		if (dscp_pcp_settings->restricted_unres_req_dscp >= 0) {
+			cass_tc_ixe_dscp_pcp_map(hw,
+						 dscp_pcp_settings->restricted_unres_req_dscp,
+						 dscp_pcp_settings->req_pcp,
+						 dscp_pcp_settings->unres_rsp_dscp);
+			cass_tc_pct_dscp_pcp_map(hw, dscp_pcp_settings->req_pcp,
+						 prof->pct_control_pcp,
+						 dscp_pcp_settings->restricted_unres_req_dscp,
+						 dscp_pcp_settings->unres_rsp_dscp);
+			cass_tc_hni_dscp_pcp_map(hw,
+						 dscp_pcp_settings->restricted_unres_req_dscp,
+						 dscp_pcp_settings->req_pcp);
+		}
+
+		/* Errata 3176. */
+		set_dscp_dfa_mask(hw, dscp_pcp_settings->res_req_dscp, 0xfff);
+		set_dscp_dfa_mask(hw, dscp_pcp_settings->hrp_res_req_dscp,
+				  0xfff);
+		set_dscp_dfa_mask(hw, dscp_pcp_settings->coll_leaf_res_req_dscp,
+				  0xfff);
+	}
+}
+
+static void hrp_enable_mask(struct cass_dev *hw, u64 *dscp_mask, u64 *hrp_mask)
+{
+	struct cass_tc_cfg *tc_cfg;
+
+	*dscp_mask = *hrp_mask = 0;
+	list_for_each_entry(tc_cfg, &hw->tc_list, tc_entry) {
+		*dscp_mask |= BIT(tc_cfg->res_req_dscp);
+		if (tc_cfg->tc_type == CXI_TC_TYPE_HRP)
+			*hrp_mask |= BIT(tc_cfg->res_req_dscp);
+	}
+}
+
+/**
+ * cass_tc_cfg_locked() - Configure a traffic class (TC) definition which can be
+ * used to allocate a communication profile. Called with hw->tc_lock held.
+ *
+ * @hw: Cassini device
+ * @tc: Traffic Class label
+ * @tc_type: Traffic Class type
+ *
+ * @return: 0 on success. Else negative errno value.
+ */
+static int cass_tc_cfg_locked(struct cass_dev *hw, unsigned int tc,
+			      enum cxi_traffic_class_type tc_type)
+	__must_hold(&hw->tc_lock)
+{
+	struct cass_tc_cfg *tc_cfg;
+	unsigned int i;
+	unsigned int req_pcp;
+	unsigned int res_req_dscp;
+	unsigned int res_rsp_dscp;
+	unsigned int unres_req_dscp;
+	unsigned int unres_rsp_dscp;
+	unsigned int rsp_pcp;
+	unsigned int ocuset;
+	unsigned int cq_tc;
+	u64 res_req_dscp_mask;
+	struct cxi_tc *cxi_tc = &hw->qos.tcs[tc];
+	bool eth_tc = is_eth_tc(tc);
+	unsigned int iterations = (tc == CXI_ETH_SHARED) ? PCP_COUNT : 1;
+	u64 dscp_mask = 0;
+	u64 hrp_mask = 0;
+	union c_ixe_cfg_hrp cfg_hrp = {};
+	bool hrp = tc_type == CXI_TC_TYPE_HRP;
+
+	/* runtime debug assert */
+	lockdep_assert_held(&hw->tc_lock);
+
+	if (eth_tc || tc_type == CXI_TC_TYPE_DEFAULT) {
+		ocuset = cxi_tc->default_ocuset;
+		cq_tc = cxi_tc->default_cq_tc;
+	} else {
+		ocuset = cxi_tc->restricted_ocuset;
+		cq_tc = cxi_tc->restricted_cq_tc;
+	}
+
+	/* Common defaults */
+	res_req_dscp = cxi_tc->dscp_pcp_settings.res_req_dscp;
+	res_rsp_dscp = cxi_tc->dscp_pcp_settings.res_rsp_dscp;
+	unres_rsp_dscp = cxi_tc->dscp_pcp_settings.unres_rsp_dscp;
+	req_pcp = cxi_tc->dscp_pcp_settings.req_pcp;
+	rsp_pcp = cxi_tc->dscp_pcp_settings.rsp_pcp;
+
+	/* Changed various fields based on TC Type */
+	if (tc_type == CXI_TC_TYPE_DEFAULT) {
+		unres_req_dscp = cxi_tc->dscp_pcp_settings.unres_req_dscp;
+	} else if (tc_type == CXI_TC_TYPE_RESTRICTED) {
+		unres_req_dscp = cxi_tc->dscp_pcp_settings.restricted_unres_req_dscp;
+	} else if (tc_type == CXI_TC_TYPE_HRP) {
+		res_req_dscp = cxi_tc->dscp_pcp_settings.hrp_res_req_dscp;
+		unres_req_dscp = cxi_tc->dscp_pcp_settings.unres_req_dscp;
+	} else if (tc_type == CXI_TC_TYPE_COLL_LEAF) {
+		res_req_dscp = cxi_tc->dscp_pcp_settings.coll_leaf_res_req_dscp;
+		unres_req_dscp = cxi_tc->dscp_pcp_settings.unres_req_dscp;
+	} else {
+		return -EINVAL;
+	}
+
+	res_req_dscp_mask = BIT(res_req_dscp);
+	/* rdscp must be used exclusively with or without HRP */
+	if (!eth_tc) {
+		hrp_enable_mask(hw, &dscp_mask, &hrp_mask);
+		if (res_req_dscp_mask & dscp_mask) {
+			if (((hrp && !(res_req_dscp_mask & hrp_mask))) ||
+			    (!hrp && (res_req_dscp_mask & hrp_mask))) {
+				return -EINVAL;
+			}
+		}
+	}
+
+	/* Run once for most TC / TC Type Combinations.
+	 * Run multiple times for the Shared Eth Class
+	 */
+	for (i = 0; i < iterations; i++) {
+		/* Skip PCPs not owned by the Shared Eth Class */
+		if (tc == CXI_ETH_SHARED &&
+		    !cxi_tc->eth_settings.tc_pcps[i])
+			continue;
+		/* Use PCP field from settings for non-Shared Eth Classes */
+		if (eth_tc) {
+			if (tc == CXI_ETH_SHARED)
+				req_pcp = i;
+			else
+				req_pcp = cxi_tc->eth_settings.pcp;
+		}
+
+		/* All traffic class configs have a unique traffic class label
+		 * and traffic class type. Should never be configured twice.
+		 */
+		list_for_each_entry(tc_cfg, &hw->tc_list, tc_entry) {
+			if (eth_tc) {
+				if (tc_cfg->tc == tc && tc_cfg->req_pcp == req_pcp &&
+				    tc_cfg->tc_type == tc_type)
+					return -EEXIST;
+			} else {
+				if (tc_cfg->tc == tc && tc_cfg->tc_type == tc_type)
+					return -EEXIST;
+			}
+		}
+
+		tc_cfg = kzalloc(sizeof(*tc_cfg), GFP_KERNEL);
+		if (!tc_cfg)
+			return -ENOMEM;
+
+		list_add_tail(&tc_cfg->tc_entry, &hw->tc_list);
+
+		/* Update mapping for TC Label */
+		tc_cfg->tc = tc;
+		tc_cfg->tc_type = tc_type;
+		tc_cfg->res_req_dscp = res_req_dscp;
+		tc_cfg->unres_req_dscp = unres_req_dscp;
+		tc_cfg->res_rsp_dscp = res_rsp_dscp;
+		tc_cfg->unres_rsp_dscp = unres_rsp_dscp;
+		tc_cfg->req_pcp = req_pcp;
+		tc_cfg->rsp_pcp = rsp_pcp;
+		tc_cfg->ocuset = ocuset;
+		tc_cfg->cq_tc = cq_tc;
+
+		/* For C1 Restricted and HRP Labels, use the global restricted
+		 * buffer class.
+		 * For all other labels, or C2, use the parent TC req_bc
+		 */
+		if (!cass_version(hw, CASSINI_2) &&
+		    (tc_type == CXI_TC_TYPE_RESTRICTED ||
+		     tc_type == CXI_TC_TYPE_HRP))
+			tc_cfg->req_bc = hw->qos.tc_restricted_oxe_req_bc;
+		else
+			tc_cfg->req_bc = cxi_tc->req_bc;
+	}
+
+	/* Configure IXE to not generate responses to requests from HRP DSCPs */
+	if (!eth_tc) {
+		hrp_enable_mask(hw, &dscp_mask, &hrp_mask);
+		cfg_hrp.hrp_enable = hrp_mask;
+		cass_write(hw, C_IXE_CFG_HRP, &cfg_hrp, sizeof(cfg_hrp));
+	}
+
+	return 0;
+}
+
+static int cass_tc_cfg(struct cass_dev *hw, unsigned int tc,
+		       enum cxi_traffic_class_type tc_type)
+{
+	int ret;
+
+	mutex_lock(&hw->tc_lock);
+	ret = cass_tc_cfg_locked(hw, tc, tc_type);
+	mutex_unlock(&hw->tc_lock);
+
+	return ret;
+}
+
+int cxi_tc_cfg(struct cxi_dev *dev, unsigned int tc,
+	       enum cxi_traffic_class_type tc_type)
+{
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+
+	if (!dev->is_physfn)
+		return -EPERM;
+	if (tc >= CXI_TC_MAX || tc_type >= CXI_TC_TYPE_MAX)
+		return -EINVAL;
+
+	return cass_tc_cfg(hw, tc, tc_type);
+}
+EXPORT_SYMBOL(cxi_tc_cfg);
+
+int cxi_tc_validate(struct cxi_dev *dev, unsigned int tc,
+		    enum cxi_traffic_class_type tc_type)
+{
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+	struct cass_tc_cfg tc_cfg;
+
+	if (tc >= CXI_TC_MAX || tc_type >= CXI_TC_TYPE_MAX)
+		return -EINVAL;
+
+	return cass_tc_find(hw, tc, tc_type, 0, &tc_cfg);
+}
+EXPORT_SYMBOL(cxi_tc_validate);
+
+int cxi_tc_clear(struct cxi_dev *dev, unsigned int tc,
+		 enum cxi_traffic_class_type tc_type)
+{
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+	struct cass_tc_cfg *cfg, *tmp;
+	bool found = false;
+
+	if (!dev->is_physfn)
+		return -EPERM;
+	if (tc >= CXI_TC_MAX || tc_type >= CXI_TC_TYPE_MAX)
+		return -EINVAL;
+
+	mutex_lock(&hw->tc_lock);
+	list_for_each_entry_safe(cfg, tmp, &hw->tc_list, tc_entry) {
+		if (cfg->tc != tc || cfg->tc_type != tc_type)
+			continue;
+		list_del(&cfg->tc_entry);
+		kfree(cfg);
+		found = true;
+	}
+	mutex_unlock(&hw->tc_lock);
+
+	return found ? 0 : -ENOENT;
+}
+EXPORT_SYMBOL(cxi_tc_clear);
+
+int cxi_tc_list(struct cxi_dev *dev, struct cxi_tc_info *entries,
+		unsigned int max_entries, unsigned int *count)
+{
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+	struct cass_tc_cfg *cfg;
+	unsigned int index = 0;
+
+	mutex_lock(&hw->tc_lock);
+	list_for_each_entry(cfg, &hw->tc_list, tc_entry) {
+		if (entries && index < max_entries) {
+			entries[index].tc = cfg->tc;
+			entries[index].tc_type = cfg->tc_type;
+			entries[index].res_req_dscp = cfg->res_req_dscp;
+			entries[index].unres_req_dscp = cfg->unres_req_dscp;
+			entries[index].res_rsp_dscp = cfg->res_rsp_dscp;
+			entries[index].unres_rsp_dscp = cfg->unres_rsp_dscp;
+			entries[index].req_pcp = cfg->req_pcp;
+			entries[index].rsp_pcp = cfg->rsp_pcp;
+			entries[index].ocuset = cfg->ocuset;
+			entries[index].cq_tc = cfg->cq_tc;
+			entries[index].req_bc = cfg->req_bc;
+		}
+		index++;
+	}
+	mutex_unlock(&hw->tc_lock);
+
+	if (count)
+		*count = index;
+
+	return 0;
+}
+EXPORT_SYMBOL(cxi_tc_list);
+
+/**
+ * cass_tc_default_type_cfg() - Configure traffic class type CXI_TC_TYPE_DEFAULT
+ * for a given traffic class.
+ *
+ * Each RDMA traffic class MUST have the CXI_TC_TYPE_DEFAULT type configured. This
+ * performs the initial allocation and configuration of required resources which
+ * can later be shared with other traffic class types with the same traffic
+ * class.
+ *
+ * @hw: Cassini device
+ * @tc: Traffic Class to initialize
+ */
+static int cass_tc_default_type_cfg(struct cass_dev *hw,
+				    enum cxi_traffic_class tc)
+{
+	struct cxi_tc *cxi_tc = &hw->qos.tcs[tc];
+	const struct cass_tc_dscp_pcp_settings *dscp_pcp_settings =
+		&cxi_tc->dscp_pcp_settings;
+	unsigned int cq_mcu_base;
+	unsigned int cq_mcu_count;
+	unsigned int ixe_mcu_base;
+	unsigned int ixe_mcu_count;
+	unsigned int lpe_mcu_base;
+	unsigned int lpe_mcu_count;
+	unsigned int tou_mcu;
+	int ret;
+
+	cxi_tc->default_ocuset = cass_tc_cq_cfg(hw, tc, &cq_mcu_base,
+						&cq_mcu_count,
+						&cxi_tc->default_cq_tc,
+						false);
+	if (cxi_tc->default_ocuset < 0)
+		return cxi_tc->default_ocuset;
+
+	tou_mcu = cxi_tc->default_cq_tc + C_OXE_TOU_MCU_START;
+
+	ret = cass_tc_ixe_fq_cfg(hw, tc, dscp_pcp_settings->req_pcp,
+				 &ixe_mcu_base, &ixe_mcu_count);
+	if (ret)
+		return ret;
+
+	ret = cass_tc_lpe_cfg(hw, tc, dscp_pcp_settings->req_pcp,
+			      &lpe_mcu_base, &lpe_mcu_count);
+	if (ret)
+		return ret;
+
+	ret = cass_tc_oxe_cfg(hw, tc, dscp_pcp_settings->req_pcp,
+			      dscp_pcp_settings->rsp_pcp,
+			      cq_mcu_base, cq_mcu_count, lpe_mcu_base,
+			      lpe_mcu_count, ixe_mcu_base, ixe_mcu_count,
+			      tou_mcu);
+	if (ret)
+		return ret;
+
+	cass_tc_pct_cfg(hw, tc, dscp_pcp_settings->req_pcp);
+
+	cass_tc_hni_cfg(hw, tc, dscp_pcp_settings->req_pcp,
+			dscp_pcp_settings->rsp_pcp);
+
+	ret = cass_tc_cfg(hw, tc, CXI_TC_TYPE_DEFAULT);
+
+	return ret;
+}
+
+/**
+ * cass_tc_restricted_cfg() - Configuration of restricted resources needed for
+ * CXI_TC_TYPE_RESTRICTED, CXI_TC_TYPE_HRP, and CXI_TC_TYPE_COLL_LEAF traffic
+ * class types.
+ *
+ * If a traffic class has CXI_TC_TYPE_RESTRICTED, CXI_TC_TYPE_HRP, and
+ * CXI_TC_TYPE_COLL_LEAF disabled, this restricted resource configuration is a
+ * NOOP.
+ *
+ * @hw: Cassini device
+ * @tc: Traffic Class to configure
+ */
+static int cass_tc_restricted_cfg(struct cass_dev *hw,
+				  enum cxi_traffic_class tc)
+{
+	const struct cass_tc_dscp_pcp_settings *dscp_pcp_settings =
+		&hw->qos.tcs[tc].dscp_pcp_settings;
+	const struct cass_tc_oxe_settings *oxe_settings =
+		&hw->qos.tcs[tc].oxe_settings;
+	int ocuset;
+	int ret;
+	unsigned int cq_mcu_base;
+	unsigned int cq_mcu_count;
+	unsigned int cq_tc;
+	unsigned int tou_mcu;
+	unsigned int restricted_bc;
+
+	/* If PCT control traffic needs to be remapped to a different traffic
+	 * class, reuse the response PCP of the remapped traffic class.
+	 */
+	int mcu_pcp = hw->qos.pct_control_pcp;
+
+	/* NOOP if CXI_TC_TYPE_RESTRICTED, CXI_TC_TYPE_HRP, and
+	 * CXI_TC_TYPE_COLL_LEAF are disabled.
+	 */
+	if (dscp_pcp_settings->restricted_unres_req_dscp < 0 &&
+	    dscp_pcp_settings->hrp_res_req_dscp < 0 &&
+	    dscp_pcp_settings->coll_leaf_res_req_dscp < 0)
+		return 0;
+
+	ocuset = cass_tc_cq_cfg(hw, tc, &cq_mcu_base, &cq_mcu_count, &cq_tc,
+				true);
+	if (ocuset < 0)
+		return ocuset;
+
+	tou_mcu = cq_tc + C_OXE_TOU_MCU_START;
+
+	/* For Restricted TC "Type" use the same BC as the parent TC for C2.
+	 * For C1 use the global restricted buffer class.
+	 */
+	restricted_bc = cass_version(hw, CASSINI_2) ?
+			hw->qos.tcs[tc].req_bc :
+			hw->qos.tc_restricted_oxe_req_bc;
+
+	ret = cass_tc_oxe_mcu_cfg(hw, cq_mcu_base, cq_mcu_count, mcu_pcp,
+				  hw->qos.tcs[tc].leaf[0],
+				  restricted_bc,
+				  oxe_settings->mfs_index);
+	if (ret)
+		return ret;
+
+	ret = cass_tc_oxe_mcu_cfg(hw, tou_mcu, 1, mcu_pcp,
+				  hw->qos.tcs[tc].leaf[0],
+				  restricted_bc,
+				  oxe_settings->mfs_index);
+	if (ret)
+		return ret;
+
+	hw->qos.tcs[tc].restricted_ocuset = ocuset;
+	hw->qos.tcs[tc].restricted_cq_tc = cq_tc;
+
+	return 0;
+}
+
+/**
+ * cass_tc_restricted_type_cfg() - Configure traffic class type
+ * CXI_TC_TYPE_RESTRICTED for a given traffic class.
+ *
+ * This traffic class type requires a unique OCUset. The resulting MCU
+ * configuration share the same request traffic shaping and PCP values as the
+ * CXI_TC_TYPE_DEFAULT traffic class type configuration for respective traffic
+ * class. But, all CXI_TC_TYPE_RESTRICTED traffic class configurations will
+ * share the same buffer class regardless of traffic class.
+ *
+ * In addition, the OCUset configured for CXI_TC_TYPE_RESTRICTED is shared with
+ * CXI_TC_TYPE_HRP and CXI_TC_TYPE_COLL_LEAF configurations.
+ *
+ * @hw: Cassini device
+ * @tc: Traffic Class label
+ */
+static int cass_tc_restricted_type_cfg(struct cass_dev *hw,
+				       enum cxi_traffic_class tc)
+{
+	const struct cass_tc_dscp_pcp_settings *dscp_pcp_settings =
+		&hw->qos.tcs[tc].dscp_pcp_settings;
+	int ret;
+
+	if (dscp_pcp_settings->restricted_unres_req_dscp < 0)
+		return 0;
+
+	ret = cass_tc_cfg(hw, tc, CXI_TC_TYPE_RESTRICTED);
+
+	return ret;
+}
+
+/**
+ * cass_tc_hrp_type_cfg() - Configure traffic class type CXI_TC_TYPE_HRP for a
+ * given traffic class.
+ *
+ * This traffic class type requires a unique OCUset. The resulting MCU
+ * configuration share the same request traffic shaping and PCP values as the
+ * CXI_TC_TYPE_DEFAULT traffic class type configuration for respective traffic
+ * class. But, all CXI_TC_TYPE_HRP traffic class configurations will
+ * share the same buffer class regardless of traffic class.
+ *
+ * In addition, the OCUset configured for CXI_TC_TYPE_HRP is shared with
+ * CXI_TC_TYPE_RESTRICTED and CXI_TC_TYPE_COLL_LEAF configurations.
+ *
+ * @hw: Cassini device
+ * @tc: Traffic Class label
+ */
+static int cass_tc_hrp_type_cfg(struct cass_dev *hw, enum cxi_traffic_class tc)
+{
+	const struct cass_tc_dscp_pcp_settings *dscp_pcp_settings =
+		&hw->qos.tcs[tc].dscp_pcp_settings;
+	int ret;
+
+	if (dscp_pcp_settings->hrp_res_req_dscp < 0)
+		return 0;
+
+	ret = cass_tc_cfg(hw, tc, CXI_TC_TYPE_HRP);
+
+	return ret;
+}
+
+/**
+ * cass_tc_coll_leaf_type_cfg() - Configure traffic class type
+ * CXI_TC_TYPE_COLL_LEAF for a given traffic class.
+ *
+ * This traffic class type requires a unique OCUset. The resulting MCU
+ * configuration share the same request traffic shaping and PCP values as the
+ * CXI_TC_TYPE_DEFAULT traffic class type configuration for respective traffic
+ * class. But, all CXI_TC_TYPE_COLL_LEAF traffic class configurations will share
+ * the same buffer class regardless of traffic class.
+ *
+ * In addition, the OCUset configured for CXI_TC_TYPE_COLL_LEAF is shared with
+ * CXI_TC_TYPE_RESTRICTED and CXI_TC_TYPE_HRP configurations.
+ *
+ * @hw: Cassini device
+ * @tc: Traffic Class label
+ */
+static int cass_tc_coll_leaf_type_cfg(struct cass_dev *hw, enum cxi_traffic_class tc)
+{
+	const struct cass_tc_dscp_pcp_settings *dscp_pcp_settings =
+		&hw->qos.tcs[tc].dscp_pcp_settings;
+	int ret;
+
+	if (dscp_pcp_settings->coll_leaf_res_req_dscp < 0)
+		return 0;
+
+	ret = cass_tc_cfg(hw, tc, CXI_TC_TYPE_COLL_LEAF);
+
+	return ret;
+}
+
+static void cass_tc_eth_hni_cfg(struct cass_dev *hw)
+{
+	const union c_hni_cfg_gen cfg_gen = {
+		.default_pcp = hw->qos.untagged_eth_pcp,
+	};
+	int i;
+
+	cass_write(hw, C_HNI_CFG_GEN, &cfg_gen, sizeof(cfg_gen));
+
+	for (i = 0; i < PCP_COUNT; i++)
+		cass_tc_hni_cfg(hw, CXI_TC_ETH, i, 0);
+}
+
+static int cass_tc_eth_oxe_cfg(struct cass_dev *hw,
+			       enum cxi_eth_traffic_class tc,
+			       unsigned int cq_mcu_base,
+			       unsigned int cq_mcu_count, unsigned int req_bc)
+{
+	struct cxi_tc *cxi_tc = &hw->qos.tcs[tc];
+	const struct cass_tc_oxe_settings *oxe_settings =
+		&cxi_tc->oxe_settings;
+	unsigned int leaf = cxi_tc->leaf[0];
+	int ret;
+	int i;
+
+	cass_tc_oxe_leaf_bucket_cfg(hw, tc, leaf, true);
+
+	ret = cass_tc_oxe_mcu_cfg(hw, cq_mcu_base, cq_mcu_count,
+				  hw->qos.untagged_eth_pcp,
+				  leaf, req_bc, oxe_settings->mfs_index);
+	if (ret)
+		return ret;
+
+	/* Configure PCP associated with an Eth TC */
+	if (tc != CXI_ETH_SHARED) {
+		ret = cass_tc_oxe_pcp_pause_cfg(hw, cxi_tc->eth_settings.pcp,
+						leaf);
+		if (ret)
+			return ret;
+	} else {
+		for (i = 0; i < PCP_COUNT; i++) {
+			/* Configure each PCP in the shared class */
+			if (cxi_tc->eth_settings.tc_pcps[i]) {
+				ret = cass_tc_oxe_pcp_pause_cfg(hw, i, leaf);
+				if (ret)
+					return ret;
+			}
+		}
+	}
+
+	return ret;
+}
+
+static int cass_tc_eth_init(struct cass_dev *hw)
+{
+	unsigned int cq_mcu_base;
+	unsigned int cq_mcu_count;
+	unsigned int shared_cq_mcu_base;
+	unsigned int shared_cq_mcu_count;
+	int req_bc;
+	int ret;
+	const struct cass_tc_oxe_settings *oxe_settings =
+		&hw->qos.tcs[CXI_TC_ETH].oxe_settings;
+	struct cxi_tc *cxi_tc;
+	int leaf;
+	int tc;
+	int i;
+	bool pcp_used[PCP_COUNT] =  {};
+
+	/* Get TSC for each Eth TC */
+	for (tc = CXI_TC_MAX; tc < CXI_ETH_TC_MAX; tc++) {
+
+		/* Skip TCs that aren't enabled */
+		if (!hw->qos.tcs_active[tc])
+			continue;
+
+		cxi_tc = &hw->qos.tcs[tc];
+
+		/* Use the head bucket for Ethernet, not a branch. */
+		cxi_tc->branch = 7;
+
+		leaf = cass_tc_get_leaf_bucket(hw);
+		if (leaf < 0)
+			return leaf;
+
+		cxi_tc->leaf[0] = leaf;
+	}
+
+	/* Due to buffer class exhaustion, a single buffer class is shared
+	 * between all Ethernet OXE configurations.
+	 */
+	req_bc = cass_tc_eth_oxe_bc_cfg(hw, oxe_settings->spt_rsvd,
+					oxe_settings->pbuf_rsvd);
+	if (req_bc < 0)
+		return req_bc;
+
+	/* Configure a traffic class configuration using a unique communication
+	 * profile and OCUset for the untagged Ethernet PCP. This will allow
+	 * for all traffic using the untagged Ethernet PCP to have unique
+	 * resources allocated.
+	 */
+	/* Get OCUset for each Eth TC */
+	for (tc = CXI_TC_MAX; tc < CXI_ETH_TC_MAX; tc++) {
+
+		/* Skip TCs that aren't enabled */
+		if (!hw->qos.tcs_active[tc])
+			continue;
+		cxi_tc = &hw->qos.tcs[tc];
+
+		cxi_tc->req_bc = req_bc;
+
+		cxi_tc->default_ocuset = cass_tc_cq_cfg(hw, CXI_TC_ETH,
+							&cq_mcu_base,
+							&cq_mcu_count,
+							&cxi_tc->default_cq_tc, true);
+		if (cxi_tc->default_ocuset < 0)
+			return cxi_tc->default_ocuset;
+
+		/* We will configure the Shared Eth class later */
+		if (tc == CXI_ETH_SHARED) {
+			shared_cq_mcu_base = cq_mcu_base;
+			shared_cq_mcu_count = cq_mcu_count;
+			continue;
+		}
+
+		/* Store info about each PCP that is used. The catch all
+		 * Eth class will be configured to use the rest.
+		 */
+		pcp_used[cxi_tc->eth_settings.pcp] = true;
+
+		ret = cass_tc_eth_oxe_cfg(hw, tc, cq_mcu_base, cq_mcu_count,
+					  req_bc);
+		if (ret)
+			return ret;
+
+		ret = cass_tc_cfg(hw, tc, CXI_TC_TYPE_DEFAULT);
+	}
+
+	/* Configure a catch-all traffic class configuration for all the
+	 * remaining Ethernet PCPs. This will allow for functionality of
+	 * packets using these PCPs at the cost of sharing resources.
+	 * In addition, any pause issued against one of the PCPs within the
+	 * catch-all will impact all PCPs.
+	 */
+
+	/* Determine which PCPs are "Shared" */
+	for (i = 0; i < PCP_COUNT; i++) {
+		if (!pcp_used[i])
+			hw->qos.tcs[CXI_ETH_SHARED].eth_settings.tc_pcps[i] = true;
+	}
+
+	cxi_tc = &hw->qos.tcs[CXI_ETH_SHARED];
+	ret = cass_tc_eth_oxe_cfg(hw, CXI_ETH_SHARED,
+				  shared_cq_mcu_base, shared_cq_mcu_count,
+				  req_bc);
+	if (ret)
+		return ret;
+
+	ret = cass_tc_cfg(hw, CXI_ETH_SHARED, CXI_TC_TYPE_DEFAULT);
+	if (ret)
+		return ret;
+
+	cass_tc_eth_hni_cfg(hw);
+
+	return ret;
+}
+
+int cass_tc_init(struct cass_dev *hw)
+{
+	union c_hni_cfg_pause_tx_ctrl tx_ctrl_cfg;
+	union c_hni_cfg_pause_rx_ctrl rx_ctrl_cfg;
+	int ret;
+	int tc;
+
+	if (!active_qos_profile ||
+	    active_qos_profile > CXI_QOS_NUM_PROF) {
+		pr_err("Invalid active_qos_profile: %d\n",
+		       active_qos_profile);
+		return -EINVAL;
+	}
+	pr_info("QoS Profile: %s\n", cxi_qos_strs[active_qos_profile]);
+
+	/* Choose QoS Profile */
+	hw->qos	= profiles[active_qos_profile];
+	mutex_init(&hw->qos.mutex);
+	for (tc = 0; tc < CXI_ETH_TC_MAX; tc++) {
+		/* Store TC idx for easy access */
+		hw->qos.tcs[tc].tc = tc;
+	}
+
+	/* Update QoS Profile Based on Device Generation */
+	cxi_qos_calculate_limits(&hw->qos, (cass_version(hw, CASSINI_2)));
+
+	/* Use user provided Untagged Eth PCP if applicable */
+	if (untagged_eth_pcp > -1)
+		hw->qos.untagged_eth_pcp = untagged_eth_pcp;
+
+	if (pct_control_traffic_pcp < -1 ||
+	    pct_control_traffic_pcp > 7) {
+		pr_err("Invalid PCT control traffic pcp: %d\n",
+		       pct_control_traffic_pcp);
+		return -EINVAL;
+	}
+
+	if (pct_control_traffic_pcp > -1)
+		hw->qos.pct_control_pcp = pct_control_traffic_pcp;
+
+	/* Check if any RDMA TCs are using the PCT PCP */
+	for (tc = 0; tc < CXI_TC_MAX; tc++) {
+		if (!hw->qos.tcs_active[tc])
+			continue;
+		if (hw->qos.tcs[tc].dscp_pcp_settings.req_pcp == hw->qos.pct_control_pcp ||
+		    hw->qos.tcs[tc].dscp_pcp_settings.rsp_pcp == hw->qos.pct_control_pcp)
+			pct_control_traffic_tc = tc;
+	}
+
+	cass_clear(hw, C_OXE_CFG_ARB_PCP_MASK(0), C_OXE_CFG_ARB_PCP_MASK_SIZE);
+
+	cass_tc_dscp_pcp_map(hw);
+
+	/* Configure for PFC pauses */
+	cass_read(hw, C_HNI_CFG_PAUSE_TX_CTRL, &tx_ctrl_cfg, sizeof(tx_ctrl_cfg));
+	tx_ctrl_cfg.enable_pfc_pause = 1;
+	tx_ctrl_cfg.enable_pause = 0;
+	tx_ctrl_cfg.mac_cntl_opcode = 0x0101;
+	cass_write(hw, C_HNI_CFG_PAUSE_TX_CTRL, &tx_ctrl_cfg, sizeof(tx_ctrl_cfg));
+
+	cass_read(hw, C_HNI_CFG_PAUSE_RX_CTRL, &rx_ctrl_cfg, sizeof(rx_ctrl_cfg));
+	rx_ctrl_cfg.pfc_rec_enable = 1;
+	rx_ctrl_cfg.pause_rec_enable = 0;
+	cass_write(hw, C_HNI_CFG_PAUSE_RX_CTRL, &rx_ctrl_cfg, sizeof(rx_ctrl_cfg));
+
+	/* Setup Global OXE BC for restricted request MCUs for C1 */
+	if (!cass_version(hw, CASSINI_2)) {
+		ret = cass_tc_init_res_req_oxe_bc(hw);
+		if (ret)
+			return ret;
+	}
+
+	for (tc = 0; tc < CXI_MAX_RDMA_TCS; tc++) {
+		/* Don't configure inactive TCs */
+		if (!hw->qos.tcs_active[tc])
+			continue;
+
+		/* Setup CXI_TC_TYPE_DEFAULT for each RDMA TC */
+		ret = cass_tc_default_type_cfg(hw, tc);
+		if (ret)
+			return ret;
+
+		/* Must be run before CXI_TC_TYPE_RESTRICTED and
+		 * CXI_TC_TYPE_HRP configuration.
+		 */
+		ret = cass_tc_restricted_cfg(hw, tc);
+		if (ret)
+			return ret;
+
+		ret = cass_tc_restricted_type_cfg(hw, tc);
+		if (ret)
+			return ret;
+
+		ret = cass_tc_hrp_type_cfg(hw, tc);
+		if (ret)
+			return ret;
+
+		ret = cass_tc_coll_leaf_type_cfg(hw, tc);
+		if (ret)
+			return ret;
+	}
+
+	/* Set up global PCT Credit limits*/
+	cass_tc_pct_global_cfg(hw);
+
+	ret = cass_tc_eth_init(hw);
+	if (ret)
+		return ret;
+
+	return 0;
+}
+
+/* Re-program the ARB CFG CSRs when the link is going up, as they are
+ * dependent on the link speed, which may have changed.
+ *
+ * Matching formula between bandwidth, fill_qty and
+ * fill_rate. bandwidth should be slightly above the real
+ * value.
+ *   FILL_QTY * 16/(FILL_RATE+1) * clock = bandwidth
+ *
+ * For instance, for Cassini 1, if desired bandwidth is
+ * 200Gbps, assuming a FILL_RATE of 9, then FILL_QTY of 16
+ * does the job:
+ *   16 * 16/10 * 1_000_000_000 * 8 = 204_800_000_000
+ *
+ * Current fill_qty for Cassini 1 depending on the link speed, and a
+ * clock speed of 1GHz:
+ *    50: 4  ->  51.2
+ *   100: 8  -> 102.4
+ *   200: 16 -> 204.8
+ *
+ * Current fill_qty for Cassini 2 depending on the link speed, and a
+ * clock speed of 1.1GHz:
+ *    25: 2  ->  28.16
+ *    50: 4  ->  56.32
+ *   100: 8  -> 112.64
+ *   200: 15 -> 211.2
+ *   400: 29 -> 408.32
+ */
+void update_oxe_link_up(struct cass_dev *hw)
+{
+	struct cxi_link_info link_info;
+	int tc;
+
+	cxi_link_mode_get(&hw->cdev, &link_info);
+
+	if (cass_version(hw, CASSINI_1)) {
+		switch (link_info.speed) {
+		case SPEED_50000:
+			hw->tsc_fill_qty = 4;
+			break;
+		case SPEED_100000:
+			hw->tsc_fill_qty = 8;
+			break;
+		case SPEED_200000:
+		default:
+			hw->tsc_fill_qty = 16;
+			break;
+		}
+	} else {
+		switch (link_info.speed) {
+		case SPEED_25000:
+			hw->tsc_fill_qty = 2;
+			break;
+		case SPEED_50000:
+			hw->tsc_fill_qty = 4;
+			break;
+		case SPEED_100000:
+			hw->tsc_fill_qty = 8;
+			break;
+		case SPEED_200000:
+			hw->tsc_fill_qty = 15;
+			break;
+		case SPEED_400000:
+		default:
+			hw->tsc_fill_qty = 29;
+			break;
+		}
+	}
+
+	traffic_shaping_cfg(hw);
+
+	/* Configure BW for each TC */
+	for (tc = 0; tc < CXI_ETH_TC_MAX; tc++) {
+
+		/* CXI_TC_ETH is used for "general" eth config. The specific
+		 * Ethernet classes are the ones that actually will have BW
+		 * settings.
+		 */
+		if (tc == CXI_TC_ETH)
+			continue;
+
+		if (!hw->qos.tcs_active[tc])
+			continue;
+
+		/* Configure Branch specified in TC */
+		cass_tc_oxe_branch_bucket_cfg(hw, tc);
+
+		/* Configure leaf for RDMA and Ethernet */
+		cass_tc_oxe_leaf_bucket_cfg(hw, tc,
+					    hw->qos.tcs[tc].leaf[0], true);
+
+		/* Configure second leaf for RDMA. Not used for Ethernet */
+		if (tc < CXI_TC_ETH)
+			cass_tc_oxe_leaf_bucket_cfg(hw, tc,
+						    hw->qos.tcs[tc].leaf[1],
+						    false);
+	}
+}
+
+/**
+ * cass_tc_find() - Look up Traffic Class definition
+ *
+ * @hw: Cassini device
+ * @tc: Traffic Class label
+ * @tc_type: Traffic Class type
+ * @ethernet_pcp: Ethernet PCP (only valid for CXI_TC_ETH)
+ * @tc_cfg: Traffic Class description values
+ *
+ * @return: 0 on success. -EINVAL if a matching definition was not found.
+ */
+int cass_tc_find(struct cass_dev *hw, enum cxi_traffic_class tc,
+		 enum cxi_traffic_class_type tc_type, u8 ethernet_pcp,
+		 struct cass_tc_cfg *tc_cfg)
+{
+	struct cass_tc_cfg *cfg;
+
+	if (disable_user_pct_tc_usage && pct_control_traffic_tc == tc) {
+		pr_err_once("%s reserved for PCT control traffic\n",
+			    cxi_tc_strs[tc]);
+		return -EINVAL;
+	}
+
+	mutex_lock(&hw->tc_lock);
+	list_for_each_entry(cfg, &hw->tc_list, tc_entry) {
+		if (tc == CXI_TC_ETH) {
+			if (cfg->tc == tc && cfg->tc_type == tc_type &&
+			    cfg->req_pcp == ethernet_pcp) {
+				*tc_cfg = *cfg;
+				mutex_unlock(&hw->tc_lock);
+				return 0;
+			}
+		} else {
+			if (cfg->tc == tc && cfg->tc_type == tc_type) {
+				/* Return config by value */
+				*tc_cfg = *cfg;
+				mutex_unlock(&hw->tc_lock);
+				return 0;
+			}
+		}
+	}
+	mutex_unlock(&hw->tc_lock);
+
+	return -EINVAL;
+}
+
+/**
+ * cass_tc_fini() - Finalize Traffic Classes
+ *
+ * @hw: Cassini device to be finalized
+ */
+void cass_tc_fini(struct cass_dev *hw)
+{
+	struct cass_tc_cfg *tc_cfg;
+
+	/* Remove all TC definitions */
+	while ((tc_cfg = list_first_entry_or_null(&hw->tc_list,
+						  struct cass_tc_cfg,
+						  tc_entry))) {
+		list_del(&tc_cfg->tc_entry);
+		kfree(tc_cfg);
+	}
+}
+
+/*
+ * print out pause state for sysfs diags
+ *
+ */
+int cass_pause_sysfs_sprint(struct cass_dev *hw, char *buf, size_t size)
+{
+	int rc;
+	u32 pause_type;
+
+	spin_lock(&hw->port->pause_lock);
+	pause_type = hw->port->pause_type;
+	spin_unlock(&hw->port->pause_lock);
+
+	rc = scnprintf(buf, size, "%s", cass_pause_type_str(pause_type));
+
+	return rc;
+}
+
+static ssize_t active_qos_profile_show(struct kobject *kobj,
+				       struct kobj_attribute *kattr, char *buf)
+{
+	return scnprintf(buf, PAGE_SIZE, "%s\n",
+			 cxi_qos_strs[active_qos_profile]);
+}
+
+static struct kobj_attribute active_qos_profile_attribute = __ATTR_RO(active_qos_profile);
+
+static ssize_t untagged_eth_pcp_show(struct kobject *kobj,
+				     struct kobj_attribute *kattr, char *buf)
+{
+	struct cass_dev *hw = container_of(kobj, struct cass_dev, tcs_kobj);
+
+	return scnprintf(buf, PAGE_SIZE, "%d\n",
+			 hw->qos.untagged_eth_pcp);
+}
+
+static struct kobj_attribute untagged_eth_pcp_attribute = __ATTR_RO(untagged_eth_pcp);
+
+static ssize_t assured_bw_show(struct kobject *kobj,
+			       struct kobj_attribute *kattr, char *buf)
+{
+	const struct cxi_tc *tc_obj;
+	const struct cass_tc_oxe_settings *oxe_settings;
+
+	tc_obj = container_of(kobj, struct cxi_tc, kobj);
+	oxe_settings = &tc_obj->oxe_settings;
+
+	return scnprintf(buf, PAGE_SIZE, "%d\n",
+			 oxe_settings->assured_percent);
+}
+
+static ssize_t assured_bw_store(struct kobject *kobj,
+				struct kobj_attribute *attr, const char *buf,
+				size_t count)
+{
+	struct cxi_tc *tc_obj;
+	struct qos_profile *qos;
+	struct cass_tc_oxe_settings *oxe_settings;
+	struct cass_dev *hw;
+	int ret, assured;
+	unsigned int tc;
+	unsigned int i;
+	unsigned int sum = 0;
+
+	tc_obj = container_of(kobj, struct cxi_tc, kobj);
+	tc = tc_obj->tc;
+	oxe_settings = &tc_obj->oxe_settings;
+	qos = container_of(tc_obj, struct qos_profile, tcs[tc]);
+	hw = container_of(qos, struct cass_dev, qos);
+
+	/* Validate input */
+	ret = kstrtoint(buf, 10, &assured);
+	if (ret)
+		return ret;
+
+	/* Input range check */
+	if (assured < 0 || assured > 100)
+		return -EINVAL;
+
+	/* Compare to ceiling */
+	if (assured > oxe_settings->ceiling_percent) {
+		pr_err("TC: %s requested assured_bw (%d) cannot be greater than ceiling_bw (%u)\n",
+		       cxi_tc_strs_uc[tc], assured,
+		       oxe_settings->ceiling_percent);
+		return -EINVAL;
+	}
+
+	/* Calculate the sum of current BW Percentages */
+	for (i = 0; i < CXI_ETH_TC_MAX; i++) {
+		/* Not a "real" TC that can have BW */
+		if (i == CXI_TC_ETH)
+			continue;
+		if (!qos->tcs_active[i])
+			continue;
+		if (i == tc)
+			continue;
+		sum += qos->tcs[i].oxe_settings.assured_percent;
+	}
+
+	/* Ensure requested assured value + sum of other BW Percentages
+	 * does not exceed 100
+	 */
+	sum += assured;
+	if (sum > 100) {
+		pr_err("Updating assured_bw for TC: %s to %d would exceed total available bandwidth. (calculated sum: %d)",
+		       cxi_tc_strs_uc[tc], assured, sum);
+		return -EINVAL;
+	}
+
+	mutex_lock(&hw->qos.mutex);
+	oxe_settings->assured_percent = assured;
+
+	/* Reconfigure branch bucket and leaf buckets for req/rsp */
+	cass_tc_oxe_branch_bucket_cfg(hw, tc);
+	cass_tc_oxe_leaf_bucket_cfg(hw, tc, hw->qos.tcs[tc].leaf[0], true);
+	if (tc < CXI_TC_ETH)
+		cass_tc_oxe_leaf_bucket_cfg(hw, tc, hw->qos.tcs[tc].leaf[1],
+					    false);
+	mutex_unlock(&hw->qos.mutex);
+
+	return count;
+}
+
+static struct kobj_attribute assured_bw_attribute = __ATTR_RW(assured_bw);
+
+static ssize_t ceiling_bw_show(struct kobject *kobj,
+			       struct kobj_attribute *kattr, char *buf)
+{
+	const struct cxi_tc *tc_obj;
+	const struct cass_tc_oxe_settings *oxe_settings;
+
+	tc_obj = container_of(kobj, struct cxi_tc, kobj);
+	oxe_settings = &tc_obj->oxe_settings;
+
+	return scnprintf(buf, PAGE_SIZE, "%d\n",
+			 oxe_settings->ceiling_percent);
+}
+
+static ssize_t ceiling_bw_store(struct kobject *kobj,
+				struct kobj_attribute *attr, const char *buf,
+				size_t count)
+{
+	struct cxi_tc *tc_obj;
+	struct qos_profile *qos;
+	struct cass_tc_oxe_settings *oxe_settings;
+	struct cass_dev *hw;
+	int ret, ceiling;
+	unsigned int tc;
+
+	tc_obj = container_of(kobj, struct cxi_tc, kobj);
+	tc = tc_obj->tc;
+	oxe_settings = &tc_obj->oxe_settings;
+	qos = container_of(tc_obj, struct qos_profile, tcs[tc]);
+	hw = container_of(qos, struct cass_dev, qos);
+
+	/* Validate input */
+	ret = kstrtoint(buf, 10, &ceiling);
+	if (ret)
+		return ret;
+
+	if (ceiling < 0 || ceiling > 100)
+		return -EINVAL;
+
+	/* Compare to assured bw */
+	if (ceiling < oxe_settings->assured_percent) {
+		pr_err("TC: %s requested ceiling_bw (%d) cannot be lower than assured_bw (%u)\n",
+		       cxi_tc_strs_uc[tc], ceiling,
+		       oxe_settings->assured_percent);
+		return -EINVAL;
+	}
+
+	mutex_lock(&hw->qos.mutex);
+	oxe_settings->ceiling_percent = ceiling;
+
+	/* Reconfigure branch bucket and leaf buckets for req/rsp */
+	cass_tc_oxe_branch_bucket_cfg(hw, tc);
+	cass_tc_oxe_leaf_bucket_cfg(hw, tc, hw->qos.tcs[tc].leaf[0], true);
+	if (tc < CXI_TC_ETH)
+		cass_tc_oxe_leaf_bucket_cfg(hw, tc, hw->qos.tcs[tc].leaf[1],
+					    false);
+	mutex_unlock(&hw->qos.mutex);
+
+	return count;
+}
+
+static struct kobj_attribute ceiling_bw_attribute = __ATTR_RW(ceiling_bw);
+
+static struct attribute *tc_attrs[] = {
+	&assured_bw_attribute.attr,
+	&ceiling_bw_attribute.attr,
+	NULL,
+};
+ATTRIBUTE_GROUPS(tc);
+
+static struct kobj_type tc_settings = {
+	.sysfs_ops	= &kobj_sysfs_ops,
+	.default_groups = tc_groups,
+};
+
+static struct kobj_type tc_dir = {
+	.sysfs_ops	= &kobj_sysfs_ops,
+};
+
+static struct attribute *tc_top_attrs[] = {
+	&active_qos_profile_attribute.attr,
+	&untagged_eth_pcp_attribute.attr,
+	NULL,
+};
+ATTRIBUTE_GROUPS(tc_top);
+
+static struct kobj_type tc_top_info = {
+	.sysfs_ops = &kobj_sysfs_ops,
+	.default_groups = tc_top_groups,
+};
+
+int cass_create_tc_sysfs(struct cass_dev *hw)
+{
+	int tc, rc, bad_tc;
+
+	/* Create top level directory and files */
+	rc = kobject_init_and_add(&hw->tcs_kobj, &tc_top_info,
+				  &hw->cdev.pdev->dev.kobj,
+				  "traffic_classes");
+	if (rc)
+		goto destroy;
+
+	/* Create directory for each RDMA TC */
+	for (tc = 0; tc < CXI_TC_ETH; tc++) {
+		if (!hw->qos.tcs_active[tc])
+			continue;
+		rc = kobject_init_and_add(&hw->qos.tcs[tc].kobj,
+					  &tc_settings, &hw->tcs_kobj,
+					  "%s", cxi_tc_strs_lc[tc]);
+		if (rc)
+			goto put_rdma_tcs;
+	}
+
+	/* Create top level directory for ETH */
+	rc = kobject_init_and_add(&hw->qos.tcs[CXI_TC_ETH].kobj,
+				  &tc_dir, &hw->tcs_kobj,
+				  "%s", "ethernet");
+	if (rc) {
+		bad_tc = -1;
+		goto put_rdma_tcs;
+	}
+
+	/* Create directory for each Eth TC */
+	for (tc = CXI_TC_MAX; tc < CXI_ETH_TC_MAX; tc++) {
+		if (!hw->qos.tcs_active[tc])
+			continue;
+		rc = kobject_init_and_add(&hw->qos.tcs[tc].kobj,
+					  &tc_settings, &hw->qos.tcs[CXI_TC_ETH].kobj,
+					  "%s", cxi_tc_strs_lc[tc]);
+		if (rc)
+			goto put_eth_tcs;
+	}
+
+	return 0;
+
+put_eth_tcs:
+	bad_tc = tc;
+	for (tc = CXI_TC_MAX; tc < CXI_ETH_TC_MAX; tc++) {
+		if (!hw->qos.tcs_active[tc])
+			continue;
+
+		kobject_put(&hw->qos.tcs[tc].kobj);
+
+		if (tc == bad_tc)
+			break;
+	}
+	bad_tc = -1;
+put_rdma_tcs:
+	bad_tc = tc;
+	for (tc = 0; tc < CXI_MAX_RDMA_TCS; tc++) {
+		if (!hw->qos.tcs_active[tc])
+			continue;
+
+		kobject_put(&hw->qos.tcs[tc].kobj);
+
+		if (tc == bad_tc)
+			break;
+	}
+destroy:
+	kobject_put(&hw->tcs_kobj);
+	return rc;
+}
+
+void cass_destroy_tc_sysfs(struct cass_dev *hw)
+{
+	int tc;
+
+	for (tc = CXI_TC_MAX; tc < CXI_ETH_TC_MAX; tc++) {
+		if (!hw->qos.tcs_active[tc])
+			continue;
+		kobject_put(&hw->qos.tcs[tc].kobj);
+	}
+
+	kobject_put(&hw->qos.tcs[CXI_TC_ETH].kobj);
+
+	for (tc = 0; tc < CXI_TC_ETH; tc++) {
+		if (!hw->qos.tcs_active[tc])
+			continue;
+		kobject_put(&hw->qos.tcs[tc].kobj);
+	}
+	sysfs_remove_file(&hw->tcs_kobj, &active_qos_profile_attribute.attr);
+	kobject_put(&hw->tcs_kobj);
+}
+
+int tc_cfg_show(struct seq_file *s, void *unused)
+{
+	struct cass_dev *hw = s->private;
+	struct cass_tc_cfg *tc_cfg;
+	const char *label;
+
+	seq_printf(s, "Active QoS Profile: %s\n\n",
+		   cxi_qos_strs[active_qos_profile]);
+	seq_printf(s, "%18s%18s%15s%15s%15s%15s%8s%8s%7s%7s\n", "LABEL", "TYPE",
+		   "RES_REQ_DSCP", "UNRES_REQ_DSCP", "RES_RSP_DSCP",
+		   "UNRES_RSP_DSCP", "REQ_PCP", "RSP_PCP", "OCUSET", "BC");
+
+	mutex_lock(&hw->tc_lock);
+	list_for_each_entry(tc_cfg, &hw->tc_list, tc_entry) {
+		if (tc_cfg->tc < 0 || tc_cfg->tc > CXI_ETH_TC_MAX)
+			label = "(invalid)";
+		else
+			label = cxi_tc_strs_uc[tc_cfg->tc];
+		seq_printf(s, "%18s%18s%15d%15d%15d%15d%8d%8d%7d%7d\n",
+			   label, cxi_tc_type_to_str(tc_cfg->tc_type),
+			   tc_cfg->res_req_dscp, tc_cfg->unres_req_dscp,
+			   tc_cfg->res_rsp_dscp, tc_cfg->unres_rsp_dscp,
+			   tc_cfg->req_pcp, tc_cfg->rsp_pcp, tc_cfg->ocuset,
+			   tc_cfg->req_bc);
+	}
+	mutex_unlock(&hw->tc_lock);
+	seq_printf(s, "%18s%18s%15d%15d%15d%15d%8d%8d%7d%7d\n",
+		   "PCT", "N/A", -1, -1, -1, -1,
+		   hw->qos.pct_control_pcp, hw->qos.pct_control_pcp, -1, -1);
+
+	return 0;
+}
diff --git a/drivers/net/ethernet/hpe/ss1/cass_telem.c b/drivers/net/ethernet/hpe/ss1/cass_telem.c
new file mode 100644
index 000000000000..af1838d9d0c3
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_telem.c
@@ -0,0 +1,309 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2020-2021,2024 Hewlett Packard Enterprise Development LP */
+
+/* Cassini Telemetry */
+
+#include <linux/iopoll.h>
+#include <linux/ktime.h>
+
+#include "cass_core.h"
+
+#define CASSINI_TELEMETRY_ITEM_TYPE_UNDEFINED	0
+#define CASSINI_TELEMETRY_ITEM_TYPE_COUNTER	1
+#define CASSINI_TELEMETRY_ITEM_TYPE_UGAUGE	2
+#define CASSINI_TELEMETRY_ITEM_TYPE_SGAUGE	3
+
+/* Telemetry item 0 is never defined. */
+#define C_TELEM_UNDEFINED	0
+
+struct telem_item {
+	u32 offset;
+	u8 lsb;
+	u8 numbits;
+	u8 type;
+};
+
+struct telem_info {
+	u64 total_num_items;
+	u64 valid_num_items;
+	const struct telem_item *items;
+};
+
+#include "cass_telem_tables.h"
+
+static struct telem_info c1 = {
+	.total_num_items = C1_TELEM_TOTAL,
+	.valid_num_items = C1_TELEM_VALID,
+	.items = c1_items,
+};
+
+static struct telem_info c2 = {
+	.total_num_items = C2_TELEM_TOTAL,
+	.valid_num_items = C2_TELEM_VALID,
+	.items = c2_items,
+};
+
+static bool telem_item_defined(const struct telem_info *info, u64 item)
+{
+	return item < info->total_num_items &&
+	       info->items[item].type != CASSINI_TELEMETRY_ITEM_TYPE_UNDEFINED;
+}
+
+static u64 telem_item_extract(const struct telem_item *item, u64 rawval)
+{
+	return (rawval >> item->lsb) & (~0ULL >> (64 - item->numbits));
+}
+
+/**
+ * cxi_telem_get_selected() - get values for supplied telemetry items
+ * @cdev: the device
+ * @items: array indicating which items to retrieve
+ * @data: array to hold the items's values
+ * @count: number of elements in each array (items and data)
+ *
+ * Retrieve the values for the requested telemetry items. Every item must
+ * be defined for this device.
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+int cxi_telem_get_selected(struct cxi_dev *cdev, const unsigned int *items,
+			   u64 *data, unsigned int count)
+{
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	const struct telem_info *info = hw->telemetry.info;
+	unsigned int i;
+
+	if (count == 0 || count > info->valid_num_items)
+		return -EINVAL;
+
+	for (i = 0; i < count; i++)
+		if (!telem_item_defined(info, items[i]))
+			return -EINVAL;
+
+	for (i = 0; i < count; i++) {
+		const struct telem_item *item = &info->items[items[i]];
+		u64 rawval;
+
+		cass_read(hw, item->offset, &rawval, sizeof(rawval));
+		data[i] = telem_item_extract(item, rawval);
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(cxi_telem_get_selected);
+
+/**
+ * cxi_telem_read() - read telemetry items with timestamps
+ * @cdev: the device
+ * @items: item IDs to read, or NULL to read items 0 to @count - 1
+ * @values: receives the value of each item
+ * @timestamps: if not NULL, receives the wall clock time in nanoseconds
+ *              taken right after each item was read
+ * @count: number of entries in each array
+ *
+ * An item that is not defined for this device, including item 0, reads as
+ * zero with a zero timestamp. An item ID past the end of the device's item
+ * space is an error. Items that share a register are read once.
+ *
+ * Return: 0 on success, negative errno on failure
+ */
+int cxi_telem_read(struct cxi_dev *cdev, const u64 *items, u64 *values,
+		   u64 *timestamps, unsigned int count)
+{
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	const struct telem_info *info = hw->telemetry.info;
+	bool have_raw = false;
+	u32 raw_offset = 0;
+	u64 rawval = 0;
+	u64 now = 0;
+	unsigned int i;
+
+	for (i = 0; i < count; i++)
+		if ((items ? items[i] : i) >= info->total_num_items)
+			return -EINVAL;
+
+	for (i = 0; i < count; i++) {
+		u64 id = items ? items[i] : i;
+		const struct telem_item *item = &info->items[id];
+
+		if (item->type == CASSINI_TELEMETRY_ITEM_TYPE_UNDEFINED) {
+			values[i] = 0;
+			if (timestamps)
+				timestamps[i] = 0;
+			continue;
+		}
+
+		if (!have_raw || raw_offset != item->offset) {
+			cass_read(hw, item->offset, &rawval, sizeof(rawval));
+			raw_offset = item->offset;
+			have_raw = true;
+			if (timestamps)
+				now = ktime_get_real_ns();
+		}
+
+		values[i] = telem_item_extract(item, rawval);
+		if (timestamps)
+			timestamps[i] = now;
+	}
+
+	return 0;
+}
+EXPORT_SYMBOL(cxi_telem_read);
+
+/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
+
+/* Toggle all counter group enable and init bits. */
+static int telem_cntr_group_toggle(struct cass_dev *hw, bool enable, bool init)
+{
+	/*
+	 * While the c_*_cfg_event_cnts registers & unions are very
+	 * similar, there are two variants one with and one without
+	 * the warm_rst_disable field, and since each counter group
+	 * defines its own cfg reg & union and may theoretically change
+	 * without corresponding changes in the other groups cfg reg,
+	 * use each group cfg reg independently versus using a single
+	 * u64 (qw) for all.   Let the compiler determine if any
+	 * optimizations may be done.
+	 */
+
+	union c_mb_cfg_event_cnts	cfg_mb;
+	union c_pi_ipd_cfg_event_cnts	cfg_pi_ipd;
+	union c_cq_cfg_event_cnts	cfg_cq;
+	union c_lpe_cfg_event_cnts	cfg_lpe;
+	union c_hni_cfg_event_cnts	cfg_hni;
+
+	cfg_mb.qw	  = 0;
+	cfg_mb.enable	  = enable;
+	cfg_mb.init	  = init;
+
+	cfg_pi_ipd.qw	  = 0;
+	cfg_pi_ipd.enable = enable;
+	cfg_pi_ipd.init	  = init;
+
+	cfg_cq.qw	  = 0;
+	cfg_cq.enable	  = enable;
+	cfg_cq.init	  = init;
+
+	cfg_lpe.qw	  = 0;
+	cfg_lpe.enable	  = enable;
+	cfg_lpe.init	  = init;
+
+	cfg_hni.qw	  = 0;
+	cfg_hni.enable	  = enable;
+	cfg_hni.init	  = init;
+
+	cass_write(hw, C_MB_CFG_EVENT_CNTS,	&cfg_mb,     sizeof(cfg_mb));
+	cass_write(hw, C_PI_IPD_CFG_EVENT_CNTS, &cfg_pi_ipd, sizeof(cfg_pi_ipd));
+	cass_write(hw, C_CQ_CFG_EVENT_CNTS,	&cfg_cq,     sizeof(cfg_cq));
+	cass_write(hw, C_LPE_CFG_EVENT_CNTS,	&cfg_lpe,    sizeof(cfg_lpe));
+	cass_write(hw, C_HNI_CFG_EVENT_CNTS,	&cfg_hni,    sizeof(cfg_hni));
+
+	cass_flush_pci(hw);
+
+	if (!init)
+		return 0;
+
+	if (readq_poll_timeout(cass_csr(hw, C_MB_CFG_EVENT_CNTS),
+			       cfg_mb.qw, cfg_mb.init_done == 1, 1, 1000000)) {
+		cxidev_err(&hw->cdev,
+			   "Telemetry counter group reset failed: %x\n",
+			   C_MB_CFG_EVENT_CNTS);
+		return -1;
+	}
+
+	if (readq_poll_timeout(cass_csr(hw, C_PI_IPD_CFG_EVENT_CNTS),
+			       cfg_pi_ipd.qw,
+			       cfg_pi_ipd.init_done == 1, 1, 1000000)) {
+		cxidev_err(&hw->cdev,
+			   "Telemetry counter group reset failed: %x\n",
+			   C_PI_IPD_CFG_EVENT_CNTS);
+		return -1;
+	}
+
+	if (readq_poll_timeout(cass_csr(hw, C_CQ_CFG_EVENT_CNTS),
+			       cfg_cq.qw, cfg_cq.init_done == 1, 1, 1000000)) {
+		cxidev_err(&hw->cdev,
+			   "Telemetry counter group reset failed: %x\n",
+			   C_CQ_CFG_EVENT_CNTS);
+		return -1;
+	}
+
+	if (readq_poll_timeout(cass_csr(hw, C_LPE_CFG_EVENT_CNTS),
+			       cfg_lpe.qw, cfg_lpe.init_done == 1, 1, 1000000)) {
+		cxidev_err(&hw->cdev,
+			   "Telemetry counter group reset failed: %x\n",
+			   C_LPE_CFG_EVENT_CNTS);
+		return -1;
+	}
+
+	if (readq_poll_timeout(cass_csr(hw, C_HNI_CFG_EVENT_CNTS),
+			       cfg_hni.qw, cfg_hni.init_done == 1, 1, 1000000)) {
+		cxidev_err(&hw->cdev,
+			   "Telemetry counter group reset failed: %x\n",
+			   C_HNI_CFG_EVENT_CNTS);
+		return -1;
+	}
+
+	return 0;
+}
+
+/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
+
+int cass_telem_init(struct cass_dev *hw)
+{
+	int rc;
+
+	if (cass_version(hw, CASSINI_1)) {
+		cxidev_info(&hw->cdev, "telemetry for cassini1\n");
+		hw->telemetry.info = &c1;
+	} else if (cass_version(hw, CASSINI_2)) {
+		cxidev_info(&hw->cdev, "telemetry for cassini2\n");
+		hw->telemetry.info = &c2;
+	} else {
+		cxidev_err(&hw->cdev,
+			   "telemetry: unsupported cassini version = %x\n",
+			   hw->cdev.prop.cassini_version);
+		rc = -EOPNOTSUPP;
+		goto __cass_telem_init_err_ret_rc;
+	}
+
+	if (hw->cdev.is_physfn) {
+		rc = telem_cntr_group_toggle(hw, true, true);
+		if (rc != 0) {
+			cxidev_err(&hw->cdev,
+				   "telem_cntr_group_toggle failed with %d\n", rc);
+			/*
+			 * going to __cass_telem_init_err_cntr_group_toggle to
+			 * have driver try to write disable for the functionality.
+			 */
+			goto __cass_telem_init_err_cntr_group_toggle;
+		}
+	}
+
+	return 0;
+
+__cass_telem_init_err_cntr_group_toggle:
+	if (hw->cdev.is_physfn) {
+		/*
+		 * since the 'init parameter' is false, the following will not fail.
+		 */
+		(void)telem_cntr_group_toggle(hw, false, false);
+	}
+	hw->telemetry.info = NULL;
+
+__cass_telem_init_err_ret_rc:
+	return rc;
+}
+
+void cass_telem_fini(struct cass_dev *hw)
+{
+	if (hw->cdev.is_physfn) {
+		/*
+		 * since the 'init parameter' is false, the following will not fail.
+		 */
+		(void)telem_cntr_group_toggle(hw, false, false);
+	}
+	hw->telemetry.info = NULL;
+}
+
+/* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */
diff --git a/drivers/net/ethernet/hpe/ss1/cass_uc.c b/drivers/net/ethernet/hpe/ss1/cass_uc.c
new file mode 100644
index 000000000000..53dea4a25f82
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cass_uc.c
@@ -0,0 +1,1933 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2019-2021 Hewlett Packard Enterprise Development LP */
+
+/* Communication with embedded µC
+ *
+ * The driver prepares a message with a command and signals the
+ * µC. When the µC has processed the command, it raises
+ * C_PI_ERR_FLG.UC_ATTENTION[0]. The callback the driver has
+ * registered for these bits signals a completion, and the response
+ * can be processed.
+ *
+ * C_PI_ERR_FLG.UC_ATTENTION[1] is used for asynchronous events, like
+ * cable status change.
+ *
+ * The uc_mbox_mutex protects the uc_req and uc_resp buffers, as well
+ * as the communication.
+ */
+
+#include <linux/workqueue.h>
+#include <linux/firmware.h>
+#include <linux/delay.h>
+#include <linux/etherdevice.h>
+#include <linux/iopoll.h>
+
+#include "cass_core.h"
+#include "cass_cable.h"
+#include "cass_ss1_debugfs.h"
+
+/* Reserved DMAC registers for communication.
+ * Range is [FIRST, FIRST+16)
+ */
+#define HOST_TO_UC_FIRST 992
+#define UC_TO_HOST_FIRST 1008
+
+/* When the driver sends several commands in a row, it is possible it
+ * processes a response and starts a new request before the error code
+ * has cleared the uc_attention bit. When that happens, the response
+ * from the uC won't raise a new uc_interrupt and the response will
+ * not be seen, leading to a timeout. Make sure the uC will actually
+ * be able to raise an interrupt before sending the next command.
+ */
+static int wait_for_uc(struct cass_dev *hw)
+{
+	union c_pi_err_flg err_flg;
+	void __iomem *csr;
+	int ret;
+
+	csr = cass_csr(hw, C_PI_ERR_FLG);
+	ret = readq_poll_timeout(csr, err_flg.qw, (err_flg.uc_attention & 1) == 0,
+				 1, 5 * MSEC_PER_SEC);
+
+	cxidev_WARN_ONCE(&hw->cdev, ret, "Timeout waiting for uc_attention to be ack'ed");
+
+	return ret;
+}
+
+/* Common command initialization */
+void uc_prepare_comm(struct cass_dev *hw)
+{
+	/* Clear the uC to host buffer (C_PI_CFG_DMAC_DESC[1008:1023]) */
+	memset(&hw->uc_req, 0, sizeof(hw->uc_req));
+	memset(&hw->uc_resp, 0, sizeof(hw->uc_resp));
+	cass_write(hw, C_PI_CFG_DMAC_DESC(UC_TO_HOST_FIRST),
+		   &hw->uc_resp, sizeof(hw->uc_resp));
+	reinit_completion(&hw->uc_attention0_comp);
+}
+
+/* Signal a new command is ready, and wait for the µC to raise
+ * UC_ATTENTION[0] of C_PI_ERR_FLAG.
+ *
+ * Return 0 if the response is valid, or a negative errno on error.
+ */
+int uc_wait_for_response(struct cass_dev *hw)
+{
+	static const union c_hni_uc_sbr_intr srb_intr = {
+		.send_sbr_dis = 1,
+		.intr = 1,
+	};
+	int rc;
+
+	rc = wait_for_uc(hw);
+	if (rc)
+		return rc;
+
+	hw->uc_req.type = CUC_TYPE_REQ;
+
+	/* Write the request and ring the doorbell */
+	cass_write(hw, C_PI_CFG_DMAC_DESC(HOST_TO_UC_FIRST),
+		   &hw->uc_req, sizeof(hw->uc_req));
+	cass_write(hw, C_HNI_UC_SBR_INTR, &srb_intr, sizeof(srb_intr));
+	cass_flush_pci(hw);
+
+	rc = wait_for_completion_interruptible_timeout(&hw->uc_attention0_comp,
+						       20 * HZ);
+	if (rc == 0)
+		return -ETIMEDOUT;
+	else if (rc < 0)
+		return rc;
+
+	/* Read the response */
+	cass_read(hw, C_PI_CFG_DMAC_DESC(UC_TO_HOST_FIRST),
+		  &hw->uc_resp, sizeof(hw->uc_resp));
+
+	switch (hw->uc_resp.type) {
+	case CUC_TYPE_RSP_SUCCESS:
+		rc = 0;
+		break;
+	case CUC_TYPE_RSP_ERROR: {
+		struct cuc_error_rsp_data *rsp_data =
+			(struct cuc_error_rsp_data *)hw->uc_resp.data;
+		rc = -rsp_data->error;
+		if (rc == 0) {
+			/* Be paranoid for now. Should not happen. */
+			cxidev_warn_once(&hw->cdev, "Got error code 0 from uC\n");
+			rc = -EIO;
+		}
+		break;
+	}
+	default:
+		/* Be paranoid for now. Should not happen. */
+		cxidev_warn_once(&hw->cdev, "Unexpected uC response type %u\n",
+				 hw->uc_resp.type);
+		rc = -EIO;
+	}
+
+	return rc;
+}
+
+/* Get the firmware version for the given target */
+static void uc_cmd_get_fw_version(struct cass_dev *hw, unsigned int fw_target)
+{
+	struct device *dev = &hw->cdev.pdev->dev;
+	struct cuc_get_firmware_version_req *req_data =
+		(struct cuc_get_firmware_version_req *)hw->uc_req.data;
+	int rc;
+
+	if (!hw->uc_present)
+		return;
+
+	if (fw_target >= ARRAY_SIZE(hw->fw_versions))
+		return;
+
+	mutex_lock(&hw->uc_mbox_mutex);
+
+	uc_prepare_comm(hw);
+
+	hw->uc_req.cmd = CUC_CMD_FIRMWARE_VERSION;
+	hw->uc_req.count = 1 + sizeof(*req_data);
+	req_data->nic = CUC_MAC_THIS_NIC;
+	req_data->fw_target = fw_target;
+	req_data->from_flash = 0;
+	req_data->slot = FW_SLOT_ACTIVE;
+
+	rc = uc_wait_for_response(hw);
+	if (rc) {
+		cxidev_err(&hw->cdev,
+			   "uC failed to return FW info for target %d: %d\n",
+			   fw_target, rc);
+		goto done;
+	}
+
+	if (hw->fw_versions[fw_target]) {
+		devm_kfree(dev, hw->fw_versions[fw_target]);
+		hw->fw_versions[fw_target] = NULL;
+	}
+
+	hw->fw_versions[fw_target] =
+		devm_kasprintf(dev, GFP_KERNEL, "%.*s",
+			       hw->uc_resp.count, hw->uc_resp.data);
+
+	/* Target 2 is the main firmware version. */
+	if (fw_target == 2 && hw->fw_versions[fw_target])
+		cxidev_info(&hw->cdev, "uC firmware version %s\n",
+			    hw->fw_versions[fw_target]);
+
+done:
+	mutex_unlock(&hw->uc_mbox_mutex);
+}
+
+/* Get the various uC firmware versions */
+static void uc_cmd_get_fw_versions(struct cass_dev *hw)
+{
+	uc_cmd_get_fw_version(hw, FW_UC_APPLICATION);
+	uc_cmd_get_fw_version(hw, FW_UC_BOOTLOADER);
+	uc_cmd_get_fw_version(hw, FW_QSPI_BLOB);
+	if (cass_version(hw, CASSINI_1))
+		uc_cmd_get_fw_version(hw, FW_OPROM);
+	uc_cmd_get_fw_version(hw, FW_CSR1);
+	uc_cmd_get_fw_version(hw, FW_CSR2);
+	uc_cmd_get_fw_version(hw, FW_SRDS);
+}
+
+/* Get the NIC ID */
+int uc_cmd_get_nic_id(struct cass_dev *hw)
+{
+	const struct cuc_get_nic_id_rsp *rsp_data =
+		(struct cuc_get_nic_id_rsp *)hw->uc_resp.data;
+	int rc;
+
+	if (!hw->uc_present)
+		return -ENOTSUPP;
+
+	mutex_lock(&hw->uc_mbox_mutex);
+
+	uc_prepare_comm(hw);
+
+	hw->uc_req.cmd = CUC_CMD_GET_NIC_ID;
+	hw->uc_req.count = 1;
+
+	rc = uc_wait_for_response(hw);
+	if (!rc)
+		hw->uc_nic = rsp_data->nic;
+	else
+		cxidev_err(&hw->cdev, "uC failed to return the NIC ID: %d\n", rc);
+
+	mutex_unlock(&hw->uc_mbox_mutex);
+
+	return rc;
+}
+
+/* Get the MAC address */
+int uc_cmd_get_mac(struct cass_dev *hw)
+{
+	struct cuc_mac_req_data *req_data =
+		(struct cuc_mac_req_data *)hw->uc_req.data;
+	const struct cuc_mac_rsp_data *rsp_data =
+		(struct cuc_mac_rsp_data *)hw->uc_resp.data;
+	int rc;
+
+	if (!hw->uc_present)
+		return -ENOTSUPP;
+
+	mutex_lock(&hw->uc_mbox_mutex);
+
+	uc_prepare_comm(hw);
+
+	hw->uc_req.cmd = CUC_CMD_GET_MAC;
+	hw->uc_req.count = sizeof(struct cuc_mac_req_data) + 1;
+	req_data->nic = CUC_MAC_THIS_NIC;
+
+	rc = uc_wait_for_response(hw);
+	if (!rc) {
+		ether_addr_copy(hw->default_mac_addr, rsp_data->nic_mac);
+	} else {
+		if (rc == -ENOENT)
+			cxidev_err(&hw->cdev,
+				   "MAC address not yet programmed in uC\n");
+		else
+			cxidev_err(&hw->cdev,
+				   "uC failed to return the MAC info: %d\n",
+				   rc);
+	}
+
+	mutex_unlock(&hw->uc_mbox_mutex);
+
+	return rc;
+}
+
+static void decode_fru_field_info(struct cass_dev *hw,
+				  const struct pldm_fru_field *fru_field)
+{
+	struct device *dev = &hw->cdev.pdev->dev;
+
+	if (fru_field->field_type == 0 ||
+	    fru_field->field_type > PLDM_FRU_FIELD_VENDOR_IANA) {
+		cxidev_info(&hw->cdev, "Unsupported FRU field type %u\n",
+			    fru_field->field_type);
+		return;
+	}
+
+	/* All supported fields are strings except two */
+	if (fru_field->field_type == PLDM_FRU_FIELD_MANUFACTURE_DATE) {
+		hw->fru_info[fru_field->field_type] = devm_kasprintf(
+			dev, GFP_KERNEL, "%04u:%02u:%02u:%02u:%02u:%02u",
+			*(u16 *)&fru_field->value[10], fru_field->value[9],
+			fru_field->value[8], fru_field->value[7],
+			fru_field->value[6], fru_field->value[5]);
+	} else if (fru_field->field_type == PLDM_FRU_FIELD_VENDOR_IANA) {
+		hw->fru_info[fru_field->field_type] = devm_kasprintf(
+			dev, GFP_KERNEL, "%x", *(u32 *)fru_field->value);
+	} else {
+		hw->fru_info[fru_field->field_type] = devm_kasprintf(
+			dev, GFP_KERNEL, "%.*s", fru_field->length,
+			fru_field->value);
+	}
+}
+
+static void decode_fru_info(struct cass_dev *hw)
+{
+	const struct pldm_fru_record *fru;
+	const struct pldm_fru_field *fru_field;
+	int len = hw->uc_resp.count - 1;
+	unsigned int fru_num;
+
+	if (len > CUC_DATA_BYTES) {
+		cxidev_err(&hw->cdev, "uC returned length too big\n");
+		return;
+	}
+
+	len -= sizeof(struct pldm_fru_record);
+	if (len < 0) {
+		cxidev_err(&hw->cdev, "uC returned invalid FRU length\n");
+		return;
+	}
+
+	fru = (struct pldm_fru_record *)hw->uc_resp.data;
+
+	if (fru->record_type != PLDM_FRU_RECORD_GENERAL) {
+		cxidev_err(&hw->cdev, "uC returned unknown record type %x\n",
+			   fru->record_type);
+		return;
+	}
+
+	fru_field = (const struct pldm_fru_field *)fru->field_data;
+	for (fru_num = 0; fru_num < fru->num_fields; fru_num++) {
+		len -= sizeof(struct pldm_fru_field);
+		if (len < 0) {
+			cxidev_err(&hw->cdev,
+				   "uC returned invalid FRU field header length\n");
+			return;
+		}
+		len -= fru_field->length;
+		if (len < 0) {
+			cxidev_err(&hw->cdev,
+				   "uC returned invalid FRU field length\n");
+			return;
+		}
+
+		decode_fru_field_info(hw, fru_field);
+
+		fru_field = (const struct pldm_fru_field *)
+			(((uintptr_t)(fru_field + 1)) + fru_field->length);
+	}
+}
+
+/* Get the FRU information */
+int uc_cmd_get_fru(struct cass_dev *hw)
+{
+	int rc;
+
+	if (HW_PLATFORM_Z1(hw)) {
+		/* Add needed info for libcxi to run. */
+		hw->fru_info[PLDM_FRU_FIELD_DESCRIPTION] =
+			devm_kasprintf(&hw->cdev.pdev->dev, GFP_KERNEL, "Z1");
+		return 0;
+	}
+
+	if (!hw->uc_present)
+		return -ENOTSUPP;
+
+	if (hw->fru_info_valid)
+		return 0;
+
+	mutex_lock(&hw->uc_mbox_mutex);
+
+	uc_prepare_comm(hw);
+
+	hw->uc_req.cmd = CUC_CMD_GET_FRU;
+	hw->uc_req.count = 1;
+
+	rc = uc_wait_for_response(hw);
+	if (!rc) {
+		hw->fru_info_valid = true;
+		decode_fru_info(hw);
+	} else {
+		cxidev_err(&hw->cdev,
+			   "uC failed to return the FRU info: %d\n", rc);
+	}
+
+	mutex_unlock(&hw->uc_mbox_mutex);
+	return rc;
+}
+
+/* Read QSFP eeprom data for a given page */
+int cxi_get_qsfp_data(struct cxi_dev *cdev, u32 offset, u32 len, u32 page, u8 *data)
+{
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	struct cuc_qsfp_read_req_data *req_data =
+		(struct cuc_qsfp_read_req_data *)hw->uc_req.data;
+	const struct cuc_qsfp_read_rsp_data *rsp_data =
+		(struct cuc_qsfp_read_rsp_data *)hw->uc_resp.data;
+	int ret_len = len;
+	int rc;
+
+	if (!hw->uc_present ||
+	    (hw->uc_platform != CUC_BOARD_TYPE_BRAZOS &&
+	     hw->uc_platform != CUC_BOARD_TYPE_KENNEBEC &&
+	     hw->uc_platform != CUC_BOARD_TYPE_SOUHEGAN &&
+	     !HW_PLATFORM_NETSIM(hw)))
+		return -ENOMEDIUM;
+
+	if (hw->uc_i2c_locked)
+		return -EBUSY;
+
+	mutex_lock(&hw->uc_mbox_mutex);
+
+	/* Read up to 128 bytes at a time, since the CUC command can
+	 * only return up to 253 bytes.
+	 */
+	while (len) {
+		u32 to_read = min_t(u32, len, 128);
+
+		uc_prepare_comm(hw);
+
+		hw->uc_req.cmd = CUC_CMD_QSFP_READ;
+		hw->uc_req.count = sizeof(struct cuc_qsfp_read_req_data) + 1;
+		req_data->nic = CUC_MAC_THIS_NIC;
+		req_data->page = page;
+		req_data->addr = offset;
+		req_data->count = to_read;
+
+		rc = uc_wait_for_response(hw);
+		if (!rc) {
+			memcpy(data, rsp_data, to_read);
+		} else {
+			mutex_unlock(&hw->uc_mbox_mutex);
+			cxidev_err(cdev,
+				   "uC failed to read the cable eeprom page %u offset %u length %u: %d\n",
+				   page, offset, to_read, rc);
+			return -EIO;
+		}
+
+		len -= to_read;
+		offset += to_read;
+		data += to_read;
+	}
+
+	mutex_unlock(&hw->uc_mbox_mutex);
+
+	return ret_len;
+}
+EXPORT_SYMBOL(cxi_get_qsfp_data);
+
+/* Read the cable module information. Assume it's a SFF-8436 /
+ * SFF-8636 type, with 256-bytes eeprom pages.
+ */
+#define SFF_8436_STATUS_2_OFFSET           0x02
+#define     CMIS_PAGE_01_PRESENT           BIT(7)
+static void uc_update_cable_info(struct cass_dev *hw)
+{
+	int ret;
+
+	mutex_lock(&hw->qsfp_eeprom_lock);
+	hw->qsfp_eeprom_page_len = 0;
+	mutex_unlock(&hw->qsfp_eeprom_lock);
+
+	ret = cxi_get_qsfp_data(&hw->cdev, 0, ETH_MODULE_SFF_8436_LEN,
+				0, &hw->qsfp_eeprom_page0[0]);
+	if (ret != ETH_MODULE_SFF_8436_LEN)
+		return;
+
+	mutex_lock(&hw->qsfp_eeprom_lock);
+	hw->qsfp_eeprom_page_len = ETH_MODULE_SFF_8436_LEN;
+	mutex_unlock(&hw->qsfp_eeprom_lock);
+
+	if ((hw->qsfp_eeprom_page0[QSFP_IDENTIFIER_OFFSET] >= 0x1E) &&
+	    (hw->qsfp_eeprom_page0[QSFP_IDENTIFIER_OFFSET] <= 0x25)) {
+		if (((hw->qsfp_eeprom_page0[QSFP_REV_CMPL_OFFSET] & 0xF0) == 0x30) ||
+		    ((hw->qsfp_eeprom_page0[QSFP_REV_CMPL_OFFSET] & 0xF0) == 0x40) ||
+		    ((hw->qsfp_eeprom_page0[QSFP_REV_CMPL_OFFSET] & 0xF0) == 0x50)) {
+			if (hw->qsfp_eeprom_page0[SFF_8436_STATUS_2_OFFSET] & CMIS_PAGE_01_PRESENT) {
+				cxidev_dbg(&hw->cdev, "no eeprom page 1\n");
+				return;
+			}
+
+			ret = cxi_get_qsfp_data(&hw->cdev, 0, ETH_MODULE_SFF_8436_LEN,
+						1, &hw->qsfp_eeprom_page1[0]);
+			if (ret != ETH_MODULE_SFF_8436_LEN)
+				cxidev_dbg(&hw->cdev, "couldn't read eeprom page 1: %d\n", ret);
+		}
+	}
+}
+
+/* Write to the QSFP module - CUC_CMD_QSFP_WRITE */
+int uc_cmd_qsfp_write(struct cass_dev *hw, u8 page, u8 addr,
+		      const u8 *data, size_t data_len)
+{
+	struct cuc_qsfp_write_req_data *req_data =
+		(struct cuc_qsfp_write_req_data *)hw->uc_req.data;
+	int rc;
+
+	if (!hw->uc_present)
+		return -EIO;
+
+	if (hw->uc_i2c_locked)
+		return -EBUSY;
+
+	if (data_len > ETH_MODULE_SFF_8436_LEN)
+		return -EINVAL;
+
+	if (addr + data_len > ETH_MODULE_SFF_8436_LEN)
+		return -EINVAL;
+
+	mutex_lock(&hw->uc_mbox_mutex);
+
+	while (data_len) {
+		size_t to_write = data_len;
+		const size_t max_data_size =
+			CUC_DATA_BYTES - sizeof(struct cuc_qsfp_write_req_data);
+
+		/* If the data is too big, write 128 bytes, then the
+		 * remainder in a second request.
+		 */
+		if (to_write > max_data_size)
+			to_write = ETH_MODULE_SFF_8436_LEN / 2;
+
+		uc_prepare_comm(hw);
+
+		hw->uc_req.cmd = CUC_CMD_QSFP_WRITE;
+		hw->uc_req.count = sizeof(struct cuc_qsfp_write_req_data) +
+			to_write + 1;
+		req_data->nic = CUC_MAC_THIS_NIC;
+		req_data->page = page;
+		req_data->addr = addr;
+		req_data->count = to_write;
+		memcpy(req_data->data, data, to_write);
+
+		rc = uc_wait_for_response(hw);
+		if (rc) {
+			mutex_unlock(&hw->uc_mbox_mutex);
+
+			cxidev_err(&hw->cdev,
+				   "uC failed to write QSFP data: %d\n", rc);
+			return rc;
+		}
+
+		data += to_write;
+		data_len -= to_write;
+	}
+
+	mutex_unlock(&hw->uc_mbox_mutex);
+
+	return 0;
+}
+
+/* Return the ISR */
+static u32 uc_cmd_get_intr_locked(struct cass_dev *hw)
+{
+	struct cuc_get_intr_req_data *req_data =
+		(struct cuc_get_intr_req_data *)hw->uc_req.data;
+	const struct cuc_get_intr_rsp_data *rsp_data =
+		(struct cuc_get_intr_rsp_data *)hw->uc_resp.data;
+	int rc;
+	u32 isr;
+
+	uc_prepare_comm(hw);
+
+	hw->uc_req.cmd = CUC_CMD_GET_INTR;
+	hw->uc_req.count = sizeof(*req_data) + 1;
+	req_data->nic = CUC_MAC_THIS_NIC;
+
+	rc = uc_wait_for_response(hw);
+	if (!rc)
+		isr = rsp_data->isr;
+	else
+		isr = 0;
+
+	return isr;
+}
+
+static u32 uc_cmd_get_intr(struct cass_dev *hw)
+{
+	u32 isr;
+
+	mutex_lock(&hw->uc_mbox_mutex);
+	isr = uc_cmd_get_intr_locked(hw);
+	mutex_unlock(&hw->uc_mbox_mutex);
+
+	return isr;
+}
+
+/* CUC_CMD_CLEAR_INTR */
+static void uc_cmd_clear_intr_locked(struct cass_dev *hw, u32 isr)
+{
+	struct cuc_clear_isr_req_data *req_data =
+		(struct cuc_clear_isr_req_data *)hw->uc_req.data;
+	int rc;
+
+	uc_prepare_comm(hw);
+
+	hw->uc_req.cmd = CUC_CMD_CLEAR_ISR;
+	hw->uc_req.count = sizeof(*req_data) + 1;
+
+	req_data->nic = CUC_MAC_THIS_NIC;
+	req_data->isr_clear_bits = isr;
+
+	rc = uc_wait_for_response(hw);
+	if (rc)
+		cxidev_err(&hw->cdev, "Failed to clear the uC interrupt: %d\n", rc);
+}
+
+static void uc_cmd_clear_intr(struct cass_dev *hw, u32 isr)
+{
+	mutex_lock(&hw->uc_mbox_mutex);
+	uc_cmd_clear_intr_locked(hw, isr);
+	mutex_unlock(&hw->uc_mbox_mutex);
+}
+
+/* CUC_CMD_UPDATE_IER */
+void uc_cmd_update_ier(struct cass_dev *hw, u32 set_bits, u32 clear_bits)
+{
+	struct cuc_update_ier_req_data *req_data =
+		(struct cuc_update_ier_req_data *)hw->uc_req.data;
+	int rc;
+
+	if (!hw->uc_present)
+		return;
+
+	mutex_lock(&hw->uc_mbox_mutex);
+
+	uc_prepare_comm(hw);
+
+	hw->uc_req.cmd = CUC_CMD_UPDATE_IER;
+	hw->uc_req.count = sizeof(*req_data) + 1;
+
+	req_data->nic = CUC_MAC_THIS_NIC;
+	req_data->ier_set_bits = set_bits;
+	req_data->ier_clear_bits = clear_bits;
+
+	rc = uc_wait_for_response(hw);
+	if (rc)
+		cxidev_err(&hw->cdev, "Failed to update the uC IER: %d\n", rc);
+
+	mutex_unlock(&hw->uc_mbox_mutex);
+}
+
+void uc_cmd_set_link_leds(struct cass_dev *hw, enum casuc_led_states led_state)
+{
+	struct cuc_set_led_req *req_data =
+		(struct cuc_set_led_req *)hw->uc_req.data;
+	int rc;
+
+	if (!hw->uc_present)
+		return;
+
+	mutex_lock(&hw->uc_mbox_mutex);
+
+	uc_prepare_comm(hw);
+
+	hw->uc_req.cmd = CUC_CMD_SET_LED;
+	hw->uc_req.count = sizeof(*req_data) + 1;
+
+	req_data->nic = CUC_MAC_THIS_NIC;
+	req_data->led = LED_LINK_STATUS;
+	req_data->state = led_state;
+
+	rc = uc_wait_for_response(hw);
+
+	mutex_unlock(&hw->uc_mbox_mutex);
+
+	if (rc)
+		cxidev_err(&hw->cdev, "Failed to set the link LED to %d: %d\n",
+			   led_state, rc);
+}
+
+/**
+ * cxi_program_firmware()
+ *
+ * Flash the uC firmware, reboots it and wait until it's back up. It
+ * is expected that the whole procedure would not last more than 30
+ * seconds.
+ *
+ * @cdev: CXI device
+ * @fw: a firmware returned by request_firmware()
+ *
+ * Returns 0 on success, or a negative errno.
+ *
+ */
+int cxi_program_firmware(struct cxi_dev *cdev, const struct firmware *fw)
+{
+	struct cass_dev *hw = container_of(cdev, struct cass_dev, cdev);
+	struct cuc_firmware_update_start_req *req_start =
+		(struct cuc_firmware_update_start_req *)hw->uc_req.data;
+	struct cuc_firmware_update_download_req *req_download =
+		(struct cuc_firmware_update_download_req *)hw->uc_req.data;
+	struct cuc_firmware_update_status_rsp *status =
+		(struct cuc_firmware_update_status_rsp *)hw->uc_resp.data;
+	size_t len_left;
+	size_t to_send;
+	const u8 *data;
+	int rc;
+	ktime_t timeout;
+
+	if (!hw->uc_present) {
+		cxidev_info(cdev, "uC is not supported\n");
+		return -EIO;
+	}
+
+	if (!capable(CAP_SYS_ADMIN))
+		return -EPERM;
+
+	if (!cdev->is_physfn) {
+		cxidev_err(cdev, "Cannot flash Cassini firmware from a VF\n");
+		return -EINVAL;
+	}
+
+	mutex_lock(&hw->uc_mbox_mutex);
+
+	uc_prepare_comm(hw);
+
+	hw->uc_req.cmd = CUC_CMD_FIRMWARE_UPDATE_START;
+	hw->uc_req.count = 1 + sizeof(*req_start);
+
+	req_start->nic = CUC_MAC_THIS_NIC;
+	req_start->size = fw->size;
+	req_start->slot = FW_SLOT_ACTIVE;
+
+	rc = uc_wait_for_response(hw);
+	if (rc) {
+		cxidev_err(cdev, "Cannot start firmware flashing: %d\n", rc);
+		goto done;
+	}
+
+	/* Upload the firmware by tiny chunks */
+	len_left = fw->size;
+	data = fw->data;
+	while (len_left) {
+		to_send = min_t(size_t, CUC_DATA_BYTES - sizeof(*req_download),
+				len_left);
+
+		uc_prepare_comm(hw);
+
+		hw->uc_req.cmd = CUC_CMD_FIRMWARE_UPDATE_DOWNLOAD;
+		hw->uc_req.count = 1 + sizeof(*req_download) + to_send;
+
+		memcpy(req_download->data, data, to_send);
+		len_left -= to_send;
+		data += to_send;
+
+		rc = uc_wait_for_response(hw);
+		if (rc) {
+			cxidev_err(cdev, "Cannot upload firmware to uC: %d\n",
+				   rc);
+			goto done;
+		}
+	}
+
+	/* Wait until idle. Flashing should not take more than 30
+	 * seconds. Set the timeout to 130 seconds.
+	 */
+	timeout = ktime_add_ms(ktime_get(), 130 * MSEC_PER_SEC);
+	while (1) {
+		uc_prepare_comm(hw);
+
+		hw->uc_req.cmd = CUC_CMD_FIRMWARE_UPDATE_STATUS;
+		hw->uc_req.count = 1;
+
+		rc = uc_wait_for_response(hw);
+		if (rc) {
+			cxidev_err(cdev,
+				   "Cannot get firmware status from uC: %d\n",
+				   rc);
+			goto done;
+		}
+
+		if (status->status & FWU_STATUS_IDLE) {
+			if (status->status != FWU_STATUS_SUCCESS) {
+				cxidev_err(cdev,
+					   "Firmware flashing failed: 0x%x\n",
+					   status->status);
+				rc = -EIO;
+				goto done;
+			} else {
+				cxidev_info(cdev,
+					    "Firmware flashing succeeded\n");
+				break;
+			}
+		}
+
+		if (ktime_after(ktime_get(), timeout)) {
+			cxidev_err(cdev,
+				   "uC took too long to flash the new firmware\n");
+			rc = -EIO;
+			goto done;
+		}
+
+		mdelay(100);
+	}
+
+	/* Clear the reset bit just in case */
+	uc_cmd_clear_intr_locked(hw, ATT1_UC_RESET);
+
+	/* Reset the uC */
+	uc_prepare_comm(hw);
+
+	hw->uc_req.cmd = CUC_CMD_RESET;
+	hw->uc_req.count = 1;
+
+	rc = uc_wait_for_response(hw);
+	if (rc) {
+		cxidev_err(cdev, "uC didn't want to reset after flashing: %d\n",
+			   rc);
+		rc = -EIO;
+		goto done;
+	}
+
+	/* Poll the uC until the reset bit is set. Reset should take
+	 * about 2 seconds, but may take as long as 90 seconds if the partner
+	 * node is flashing the other NIC. Set the timeout to 120 seconds.
+	 */
+	timeout = ktime_add_ms(ktime_get(), 120 * MSEC_PER_SEC);
+	while (1) {
+		u32 isr;
+
+		isr = uc_cmd_get_intr_locked(hw);
+
+		if (isr & ATT1_UC_RESET)
+			break;
+
+		if (ktime_after(ktime_get(), timeout)) {
+			rc = -ETIMEDOUT;
+			cxidev_err(cdev, "uC took too long to reset\n");
+			goto done;
+		}
+
+		mdelay(100);
+	}
+
+	rc = 0;
+
+done:
+	mutex_unlock(&hw->uc_mbox_mutex);
+
+	if (!rc)
+		uc_cmd_get_fw_versions(hw);
+
+	return rc;
+}
+EXPORT_SYMBOL(cxi_program_firmware);
+
+/* Called when one of the C_PI_ERR_FLG.UC_ATTENTION bits was set */
+static void uc_attention_cb(struct cass_dev *hw, unsigned int irq,
+			    bool is_ext, unsigned int bitn)
+{
+	if (bitn == C_PI_ERR_FLG__UC_ATTENTION_0)
+		complete(&hw->uc_attention0_comp);
+
+	if (bitn == C_PI_ERR_FLG__UC_ATTENTION_1)
+		queue_work(hw->uc_attn1_wq, &hw->uc_attn1_work);
+}
+
+static ssize_t show_fw_version(struct kobject *kobj, char *buf,
+			       unsigned int fw_target)
+{
+	struct cass_dev *hw =
+		container_of(kobj, struct cass_dev, uc_kobj);
+	int rc;
+
+	mutex_lock(&hw->uc_mbox_mutex);
+
+	if (hw->fw_versions[fw_target])
+		rc = scnprintf(buf, PAGE_SIZE, "%s\n",
+			       hw->fw_versions[fw_target]);
+	else
+		rc = 0;
+
+	mutex_unlock(&hw->uc_mbox_mutex);
+
+	return rc;
+}
+
+#define FW_VERSION_ATTR(name, target_fw) \
+	static ssize_t name##_show(struct kobject *kobj, \
+				  struct kobj_attribute *kattr, char *buf) \
+	{								\
+		return show_fw_version(kobj, buf, target_fw);		\
+	}								\
+	static struct kobj_attribute dev_attr_##name = __ATTR_RO(name)
+
+FW_VERSION_ATTR(app_version, FW_UC_APPLICATION);
+FW_VERSION_ATTR(bootloader_version, FW_UC_BOOTLOADER);
+FW_VERSION_ATTR(qspi_blob_version, FW_QSPI_BLOB);
+FW_VERSION_ATTR(oprom_version, FW_OPROM);
+FW_VERSION_ATTR(csr1_version, FW_CSR1);
+FW_VERSION_ATTR(csr2_version, FW_CSR2);
+FW_VERSION_ATTR(srds_version, FW_SRDS);
+
+/* Reset the uC through sysfs. As a safety measure, the user must
+ * write '1789' to it.
+ */
+static ssize_t reset_store(struct kobject *kobj, struct kobj_attribute *attr,
+			   const char *buf, size_t len)
+{
+	struct cass_dev *hw =
+		container_of(kobj, struct cass_dev, uc_kobj);
+	int rc;
+	int value;
+
+	rc = kstrtoint(buf, 0, &value);
+	if (rc)
+		return rc;
+
+	if (value != 1789)
+		return -EINVAL;
+
+	if (!hw->uc_present)
+		return 0;
+
+	mutex_lock(&hw->uc_mbox_mutex);
+
+	uc_prepare_comm(hw);
+
+	hw->uc_req.cmd = CUC_CMD_RESET;
+	hw->uc_req.count = 1;
+
+	rc = uc_wait_for_response(hw);
+	if (rc)
+		cxidev_err(&hw->cdev, "uC didn't want to reset: %d\n", rc);
+	else
+		rc = len;
+
+	mutex_unlock(&hw->uc_mbox_mutex);
+
+	return rc;
+}
+
+static struct kobj_attribute dev_attr_reset = __ATTR_WO(reset);
+
+static ssize_t timings_show(struct kobject *kobj,
+			    struct kobj_attribute *kattr, char *buf)
+{
+	struct cass_dev *hw =
+		container_of(kobj, struct cass_dev, uc_kobj);
+	const struct cuc_get_timings_rsp *rsp_data =
+		(struct cuc_get_timings_rsp *)hw->uc_resp.data;
+	int rc;
+	int i;
+
+	if (!hw->uc_present)
+		return -ENODATA;
+
+	mutex_lock(&hw->uc_mbox_mutex);
+
+	uc_prepare_comm(hw);
+
+	hw->uc_req.cmd = CUC_CMD_GET_TIMINGS;
+	hw->uc_req.count = 1;
+
+	rc = uc_wait_for_response(hw);
+	if (rc) {
+		cxidev_err(&hw->cdev, "uC didn't return its timings: %d\n", rc);
+	} else {
+		rc = 0;
+		for (i = 0; i < TIMING_NUM_ENTRIES; i++) {
+			rc += scnprintf(buf + rc, PAGE_SIZE - rc, "%llu ",
+					rsp_data->entries_us[i]);
+		}
+		rc += scnprintf(buf + rc, PAGE_SIZE - rc, "\n");
+	}
+
+	mutex_unlock(&hw->uc_mbox_mutex);
+
+	return rc;
+}
+
+static struct kobj_attribute dev_attr_timings = __ATTR_RO(timings);
+
+static struct attribute *uc_attrs[] = {
+	&dev_attr_app_version.attr,
+	&dev_attr_bootloader_version.attr,
+	&dev_attr_qspi_blob_version.attr,
+	&dev_attr_oprom_version.attr,
+	&dev_attr_csr1_version.attr,
+	&dev_attr_csr2_version.attr,
+	&dev_attr_srds_version.attr,
+	&dev_attr_reset.attr,
+	&dev_attr_timings.attr,
+	NULL,
+};
+ATTRIBUTE_GROUPS(uc);
+
+static struct kobj_type uc_sysfs_entries = {
+	.sysfs_ops      = &kobj_sysfs_ops,
+	.default_groups = uc_groups,
+};
+
+/* Retrieve a PDR given a record handle.
+ * Used for PDR iteration.
+ *
+ * The uC must be locked.
+ */
+static int pldm_get_pdr(struct cass_dev *hw, unsigned int record_handle)
+{
+	struct get_pdr_req *req_data =
+		(struct get_pdr_req *)hw->uc_req.data;
+	int rc;
+
+	if (!hw->uc_present)
+		return -ENOTSUPP;
+
+	uc_prepare_comm(hw);
+
+	hw->uc_req.cmd = CUC_CMD_PLDM;
+	hw->uc_req.count = sizeof(*req_data) + 1;
+
+	req_data->hdr.d = 0;
+	req_data->hdr.rq = 1;
+	req_data->hdr.pldm_type = PLDM_TYPE_PLATFORM_MONITORING_AND_CONTROL;
+	req_data->hdr.hdr_ver = 0;
+	req_data->hdr.pldm_command_code = PLDM_CMD_GET_PDR;
+	req_data->record_handle = record_handle;
+	req_data->data_transfer_handle = 0;
+	req_data->transfer_operation_flag = PLDM_XFER_OP_GET_FIRST_PART;
+	req_data->request_count = CUC_DATA_BYTES - sizeof(struct get_pdr_rsp);
+	req_data->record_change_number = 0;
+
+	rc = uc_wait_for_response(hw);
+
+	return rc;
+}
+
+/* Iterate through the PDR building an IDR tree of supported
+ * sensors.
+ */
+static void iterate_pdr(struct cass_dev *hw)
+{
+	unsigned int record_handle;
+	const struct get_pdr_rsp *rsp_data =
+		(struct get_pdr_rsp *)hw->uc_resp.data;
+	const struct pdr_hdr *pdr_hdr = (struct pdr_hdr *)rsp_data->record_data;
+	int rc;
+	struct pldm_sensor *sensor;
+	unsigned int count = 0;
+
+	mutex_lock(&hw->uc_mbox_mutex);
+
+	/* Get the numerical sensors first */
+	record_handle = 0;
+	do {
+		const struct numeric_sensor_pdr *pdr_sensor =
+			(struct numeric_sensor_pdr *)rsp_data->record_data;
+
+		rc = pldm_get_pdr(hw, record_handle);
+		if (rc)
+			break;
+
+		if (rsp_data->completion_code != PLDM_SUCCESS) {
+			cxidev_err(&hw->cdev,
+				   "Unexpected PLDM completion error: %d\n",
+				   rsp_data->completion_code);
+			break;
+		}
+
+		record_handle = rsp_data->next_record_handle;
+
+		if (pdr_hdr->pdr_type != PLDM_PDR_NUMERIC_SENSOR)
+			continue;
+
+		sensor = kzalloc(sizeof(struct pldm_sensor), GFP_KERNEL);
+		if (!sensor)
+			break;
+
+		sensor->hw = hw;
+		sensor->id = pdr_sensor->sensor_id;
+		sensor->num = *pdr_sensor;
+
+		idr_preload(GFP_KERNEL);
+		rc = idr_alloc(&hw->pldm_sensors, sensor,
+			       sensor->num.sensor_id, sensor->num.sensor_id + 1,
+			       GFP_NOWAIT);
+		idr_preload_end();
+
+		count++;
+	} while (record_handle != 0);
+
+	/* Then get their names */
+	record_handle = 0;
+	do {
+		const struct aux_name_pdr *pdr_name =
+			(struct aux_name_pdr *)rsp_data->record_data;
+		int i;
+
+		rc = pldm_get_pdr(hw, record_handle);
+		if (rc)
+			break;
+
+		if (rsp_data->completion_code != PLDM_SUCCESS) {
+			cxidev_err(&hw->cdev,
+				   "Unexpected PLDM completion error: %d\n",
+				   rsp_data->completion_code);
+			break;
+		}
+
+		record_handle = rsp_data->next_record_handle;
+
+		if (pdr_hdr->pdr_type != PLDM_PDR_SENSOR_AUXILIARY_NAMES)
+			continue;
+
+		sensor = idr_find(&hw->pldm_sensors, pdr_name->sensor_id);
+		if (!sensor)
+			continue;
+
+		if (pdr_name->name_string_count != 1) {
+			cxidev_err(&hw->cdev,
+				   "Unexpected number of strings: %d\n",
+				   pdr_name->name_string_count);
+			continue;
+		}
+
+		/* Name is in big endian UTF-16. Convert to ASCII. */
+		for (i = 0; i < AUX_NAME_MAX; i++) {
+			u16 c = be16_to_cpu((__force __be16)pdr_name->sensor_name[i]);
+
+			if (c == 0)
+				break;
+
+			if (c < ' ' || c > '~')
+				c = '.';
+
+			sensor->name[i] = c;
+		}
+		sensor->name[AUX_NAME_MAX - 1] = 0;
+	} while (record_handle != 0);
+
+	mutex_unlock(&hw->uc_mbox_mutex);
+
+	hw->pldm_sensors_count = count;
+}
+
+/* Read a PLDM sensor, given a sensor ID.
+ *
+ * uc_mbox_mutex must be held.
+ *
+ * Return 0 if the sensor was successfully read.
+ */
+static int pldm_read_sensor(struct cass_dev *hw, unsigned int id,
+			    struct pldm_sensor_reading *result)
+{
+	struct get_sensor_reading_req *req_data =
+		(struct get_sensor_reading_req *)hw->uc_req.data;
+	const struct get_sensor_reading_rsp *rsp_data =
+		(struct get_sensor_reading_rsp *)hw->uc_resp.data;
+	int rc;
+
+	uc_prepare_comm(hw);
+
+	hw->uc_req.cmd = CUC_CMD_PLDM;
+	hw->uc_req.count = sizeof(*req_data) + 1;
+
+	req_data->hdr.d = 0;
+	req_data->hdr.rq = 1;
+	req_data->hdr.pldm_type = PLDM_TYPE_PLATFORM_MONITORING_AND_CONTROL;
+	req_data->hdr.hdr_ver = 0;
+	req_data->hdr.pldm_command_code = PLDM_CMD_GET_SENSOR_READING;
+	req_data->sensor_id = id;
+	req_data->rearm_event_status = 0;
+
+	rc = uc_wait_for_response(hw);
+	if (rc)
+		goto out;
+
+	if (rsp_data->completion_code != PLDM_SUCCESS) {
+		rc = -EIO;
+		goto out;
+	}
+
+	result->operational_state = rsp_data->sensor_operational_state;
+	result->present_state = rsp_data->present_state;
+	result->previous_state = rsp_data->previous_state;
+	rc = 0;
+	switch (rsp_data->sensor_data_size) {
+	case PLDM_DATA_SIZE_UINT8:
+		result->present_reading = rsp_data->present_reading.value_UINT8;
+		break;
+	case PLDM_DATA_SIZE_SINT8:
+		result->present_reading = rsp_data->present_reading.value_SINT8;
+		break;
+	case PLDM_DATA_SIZE_UINT16:
+		result->present_reading = rsp_data->present_reading.value_UINT16;
+		break;
+	case PLDM_DATA_SIZE_SINT16:
+		result->present_reading = rsp_data->present_reading.value_SINT16;
+		break;
+	case PLDM_DATA_SIZE_UINT32:
+		result->present_reading = rsp_data->present_reading.value_UINT32;
+		break;
+	case PLDM_DATA_SIZE_SINT32:
+		result->present_reading = rsp_data->present_reading.value_SINT32;
+		break;
+	default:
+		rc = -EIO;
+	}
+
+out:
+	return rc;
+}
+
+int update_sensor(struct pldm_sensor *sensor,
+		  struct pldm_sensor_reading *result)
+{
+	struct cass_dev *hw = sensor->hw;
+	int rc;
+
+	// TODO: rate limit ?
+	mutex_lock(&hw->uc_mbox_mutex);
+
+	rc = pldm_read_sensor(hw, sensor->id, result);
+
+	mutex_unlock(&hw->uc_mbox_mutex);
+
+	return rc;
+}
+
+static void set_uc_platform(struct cass_dev *hw)
+{
+	const struct cuc_board_info_rsp *rsp_data =
+		(struct cuc_board_info_rsp *)hw->uc_resp.data;
+	u8 board_type;
+	int rc;
+	int resp_len;
+
+	if (HW_PLATFORM_Z1(hw)) {
+		if (!cass_version(hw, CASSINI_1))
+			hw->uc_platform = CUC_BOARD_TYPE_WASHINGTON;
+		else
+			hw->uc_platform = CUC_BOARD_TYPE_SAWTOOTH;
+		return;
+	}
+
+	mutex_lock(&hw->uc_mbox_mutex);
+
+	uc_prepare_comm(hw);
+
+	hw->uc_req.cmd = CUC_CMD_BOARD_INFO;
+	hw->uc_req.count = 1;
+
+	rc = uc_wait_for_response(hw);
+	board_type = rsp_data->board_type;
+	resp_len = hw->uc_resp.count;
+
+	mutex_unlock(&hw->uc_mbox_mutex);
+
+	/* CUC_CMD_BOARD_INFO re-used the CUC_CMD_FW_VERSION command
+	 * number. To ensure that the response is indeed for the
+	 * CUC_CMD_BOARD_INFO command, also check the response size. A
+	 * CUC_CMD_FW_VERSION response would be at least 4 bytes.
+	 */
+	if (rc == 0 && resp_len == (1 + sizeof(struct cuc_board_info_rsp))) {
+		hw->uc_platform = board_type;
+
+		return;
+	}
+
+	/* Older firmwares do not support the BOARD_INFO command, and
+	 * FRU has to be parsed.
+	 */
+
+	if (!hw->fru_info[PLDM_FRU_FIELD_PART_NUMBER]) {
+		cxidev_err(&hw->cdev, "Failed to detect platform from uC!\n");
+		hw->uc_platform = CUC_BOARD_TYPE_UNKNOWN;
+	} else if (!strcmp(hw->fru_info[PLDM_FRU_FIELD_PART_NUMBER],
+			   PCA_SHASTA_SAWTOOTH_PASS_1_PN) ||
+		   !strcmp(hw->fru_info[PLDM_FRU_FIELD_PART_NUMBER],
+			   PCA_SHASTA_SAWTOOTH_PASS_2_PN) ||
+		   !strncmp(hw->fru_info[PLDM_FRU_FIELD_PART_NUMBER],
+			    PCA_SHASTA_SAWTOOTH_PASS_3_PN,
+			    strlen(PCA_SHASTA_SAWTOOTH_PASS_3_PN))) {
+		hw->uc_platform = CUC_BOARD_TYPE_SAWTOOTH;
+	} else if (!strcmp(hw->fru_info[PLDM_FRU_FIELD_PART_NUMBER],
+			   PCA_SHASTA_BRAZOS_PASS_1_PN) ||
+		   !strcmp(hw->fru_info[PLDM_FRU_FIELD_PART_NUMBER],
+			   PCA_SHASTA_BRAZOS_PASS_2_PN) ||
+		   !strcmp(hw->fru_info[PLDM_FRU_FIELD_PART_NUMBER],
+			   PCA_SHASTA_BRAZOS_PASS_3_PN) ||
+		   !strncmp(hw->fru_info[PLDM_FRU_FIELD_PART_NUMBER],
+			    PCA_SHASTA_BRAZOS_PASS_4_PN,
+			    strlen(PCA_SHASTA_BRAZOS_PASS_4_PN))) {
+		hw->uc_platform = CUC_BOARD_TYPE_BRAZOS;
+	} else {
+		hw->uc_platform = CUC_BOARD_TYPE_UNKNOWN;
+	};
+}
+
+static void check_sensor_values(struct cass_dev *hw)
+{
+	struct pldm_sensor *sensor;
+	struct pldm_sensor_reading result;
+	int id;
+	int rc;
+
+	mutex_lock(&hw->uc_mbox_mutex);
+
+	idr_for_each_entry(&hw->pldm_sensors, sensor, id) {
+		unsigned int thresh_mask;
+
+		rc = pldm_read_sensor(hw, id, &result);
+		if (rc)
+			continue;
+
+		if (result.operational_state != PLDM_OPSTATE_ENABLED)
+			continue;
+
+		thresh_mask = get_pldm_value(sensor, supported_thresholds);
+
+		if (((thresh_mask & PLDM_THRESHOLD_LOWER_FATAL_MASK) &&
+		     result.present_reading <= get_pldm_value(sensor, fatal_low)) ||
+		    ((thresh_mask & PLDM_THRESHOLD_UPPER_FATAL_MASK) &&
+		     result.present_reading >= get_pldm_value(sensor, fatal_high))) {
+			cxidev_err(&hw->cdev,
+				   "uC: ATT1_SENSOR_ALERT: sensor '%s' (%d) in fatal state: %lld not in [%lld..%lld]\n",
+				   sensor->name, id,
+				   result.present_reading,
+				   get_pldm_value(sensor, fatal_low),
+				   get_pldm_value(sensor, fatal_high));
+		} else if (((thresh_mask & PLDM_THRESHOLD_LOWER_CRITICAL_MASK) &&
+			  result.present_reading <= get_pldm_value(sensor, critical_low)) ||
+			 ((thresh_mask & PLDM_THRESHOLD_UPPER_CRITICAL_MASK) &&
+			  result.present_reading >= get_pldm_value(sensor, critical_high))) {
+			cxidev_warn(&hw->cdev,
+				    "uC: ATT1_SENSOR_ALERT: sensor '%s' (%d) in critical state: %lld not in [%lld..%lld]\n",
+				    sensor->name, id,
+				    result.present_reading,
+				    get_pldm_value(sensor, critical_low),
+				    get_pldm_value(sensor, critical_high));
+		} else if (((thresh_mask & PLDM_THRESHOLD_LOWER_WARNING_MASK) &&
+			  result.present_reading <= get_pldm_value(sensor, warning_low)) ||
+			 ((thresh_mask & PLDM_THRESHOLD_UPPER_WARNING_MASK) &&
+			  result.present_reading >= get_pldm_value(sensor, warning_high))) {
+			cxidev_warn(&hw->cdev,
+				    "uC: ATT1_SENSOR_ALERT: sensor '%s' (%d) in warning state: %lld not in [%lld..%lld]\n",
+				    sensor->name, id,
+				    result.present_reading,
+				    get_pldm_value(sensor, warning_low),
+				    get_pldm_value(sensor, warning_high));
+		}
+	}
+
+	mutex_unlock(&hw->uc_mbox_mutex);
+}
+
+/* Called when the µC raised C_PI_ERR_FLG.UC_ATTENTION[1]. Retrieve
+ * the status register and act on the bits that are set.
+ */
+static void attn1_worker(struct work_struct *work)
+{
+	struct cass_dev *hw =
+		container_of(work, struct cass_dev, uc_attn1_work);
+	u32 isr;
+
+	/* Get the current interrupt status */
+	isr = uc_cmd_get_intr(hw);
+
+	if (isr & ATT1_UC_RESET)
+		cxidev_info(&hw->cdev, "uC: UC_RESET\n");
+
+	if (isr & ATT1_ASIC_PWR_UP_DONE)
+		cxidev_dbg(&hw->cdev, "uC: ASIC_PWR_UP_DONE\n");
+
+	if (isr & ATT1_ASIC_EPO_TEMPERATURE)
+		cxidev_notice(&hw->cdev, "uC: ASIC_EPO_TEMPERATURE\n");
+
+	/* The ATT1_QSFP_BAD_CABLE event happens every 5
+	 * seconds. Ignore all but the first one.
+	 */
+	if (isr & ATT1_QSFP_BAD_CABLE && !hw->qsfp_bad) {
+		cxidev_warn(&hw->cdev, "Bad cable present\n");
+		hw->qsfp_bad = true;
+	}
+
+	if (isr & ATT1_QSFP_INSERT) {
+		cxidev_info(&hw->cdev, "Cable inserted\n");
+		hw->qsfp_bad = false;
+		uc_update_cable_info(hw);
+		cass_cable_scan(hw);
+		cxi_send_async_event(&hw->cdev, CXI_EVENT_CABLE_INSERTED);
+		cass_phy_trigger_machine(hw);
+	}
+
+	if (isr & ATT1_QSFP_REMOVE) {
+		cxidev_info(&hw->cdev, "Cable removed\n");
+		hw->qsfp_bad = false;
+		mutex_lock(&hw->qsfp_eeprom_lock);
+		hw->qsfp_eeprom_page_len = 0;
+		mutex_unlock(&hw->qsfp_eeprom_lock);
+		cass_cable_scan(hw);
+		cxi_send_async_event(&hw->cdev, CXI_EVENT_CABLE_REMOVED);
+		cass_phy_trigger_machine(hw);
+	}
+
+	if (isr & ATT1_QSFP_EPO_TEMPERATURE) {
+		cxidev_crit(&hw->cdev, "uC: QSFP_EPO_TEMPERATURE\n");
+		hw->qsfp_over_temp = true;
+		cass_link_set_led(hw);
+	}
+
+	if (isr & ATT1_SENSOR_ALERT) {
+		cxidev_info(&hw->cdev, "uC: ATT1_SENSOR_ALERT\n");
+		check_sensor_values(hw);
+	}
+
+	uc_cmd_clear_intr(hw, isr);
+}
+
+/* Conversion table for unit between PLDM and HWMON */
+static const struct {
+	enum sensor_unit pldm_base_unit;
+	enum hwmon_sensor_types hwmon_type;
+	unsigned int hwmon_input;
+} pldm_sensor_to_hwmon[] = {
+	{ PLDM_UNIT_DEGREES_C, hwmon_temp, HWMON_T_INPUT | HWMON_T_LABEL, },
+	{ PLDM_UNIT_VOLTS, hwmon_in, HWMON_I_INPUT | HWMON_I_LABEL, },
+	{ PLDM_UNIT_AMPS, hwmon_curr, HWMON_C_INPUT | HWMON_C_LABEL, },
+	{ PLDM_UNIT_WATTS, hwmon_power, HWMON_P_INPUT | HWMON_P_LABEL, },
+};
+
+static umode_t cxi_hwmon_is_visible(const void *data,
+				    enum hwmon_sensor_types type,
+				    u32 attr, int channel)
+{
+	return 0444;
+}
+
+static int cxi_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
+			  u32 attr, int channel, long *val)
+{
+	struct cass_dev *hw = dev_get_drvdata(dev);
+	struct pldm_sensor_reading result;
+	struct pldm_sensor *sensor;
+	bool is_input = false;
+	bool found = false;
+	int id;
+	int rc;
+
+	idr_for_each_entry(&hw->pldm_sensors, sensor, id) {
+		if (sensor->hwmon.type == type &&
+		    sensor->hwmon.channel == channel) {
+			found = true;
+			break;
+		}
+	}
+
+	if (!found)
+		return -EINVAL;
+
+	switch (type) {
+	case hwmon_temp:
+		switch (attr) {
+		case hwmon_temp_input:
+			is_input = true;
+			break;
+		case hwmon_temp_max:
+			*val = get_pldm_value(sensor, warning_high);
+			break;
+		case hwmon_temp_crit:
+			*val = get_pldm_value(sensor, critical_high);
+			break;
+		default:
+			return -EOPNOTSUPP;
+		}
+		break;
+
+	case hwmon_in:
+		switch (attr) {
+		case hwmon_in_input:
+			is_input = true;
+			break;
+		case hwmon_in_min:
+			*val = get_pldm_value(sensor, warning_low);
+			break;
+		case hwmon_in_max:
+			*val = get_pldm_value(sensor, warning_high);
+			break;
+		case hwmon_in_lcrit:
+			*val = get_pldm_value(sensor, critical_low);
+			break;
+		case hwmon_in_crit:
+			*val = get_pldm_value(sensor, critical_high);
+			break;
+		default:
+			return -EOPNOTSUPP;
+		}
+		break;
+
+	case hwmon_curr:
+		switch (attr) {
+		case hwmon_curr_input:
+			is_input = true;
+			break;
+		case hwmon_curr_max:
+			*val = get_pldm_value(sensor, warning_high);
+			break;
+		case hwmon_curr_crit:
+			*val = get_pldm_value(sensor, critical_high);
+			break;
+		default:
+			return -EOPNOTSUPP;
+		}
+		break;
+
+	case hwmon_power:
+		switch (attr) {
+		case hwmon_power_input:
+			is_input = true;
+			break;
+		case hwmon_power_max:
+			*val = get_pldm_value(sensor, warning_high);
+			break;
+		case hwmon_power_crit:
+			*val = get_pldm_value(sensor, critical_high);
+			break;
+		default:
+			return -EOPNOTSUPP;
+		}
+		break;
+
+	default:
+		return -EOPNOTSUPP;
+	}
+
+	if (is_input) {
+		rc = update_sensor(sensor, &result);
+		if (rc)
+			return rc;
+
+		if (result.operational_state == PLDM_OPSTATE_ENABLED)
+			*val = result.present_reading;
+		else
+			return -ENODATA;
+	}
+
+	*val *= sensor->hwmon.multiplier;
+
+	return 0;
+}
+
+static int cxi_hwmon_read_string(struct device *dev,
+				 enum hwmon_sensor_types type,
+				 u32 attr, int channel, const char **str)
+{
+	struct cass_dev *hw = dev_get_drvdata(dev);
+	struct pldm_sensor *sensor;
+	int id;
+
+	idr_for_each_entry(&hw->pldm_sensors, sensor, id) {
+		if (sensor->hwmon.type == type &&
+		    sensor->hwmon.channel == channel) {
+			*str = sensor->name;
+			return 0;
+		}
+	}
+
+	*str = "NOTFOUND";
+
+	return 0;
+}
+
+static const struct hwmon_ops cxi_hwmon_ops = {
+	.is_visible = cxi_hwmon_is_visible,
+	.read = cxi_hwmon_read,
+	.read_string = cxi_hwmon_read_string,
+};
+
+static const long pldm_multiplier[] = {
+	1000000000,		/* PLDM_MODIFIER_NANO */
+	100000000,
+	10000000,
+	1000000,		/* PLDM_MODIFIER_MICRO */
+	100000,
+	10000,
+	1000,			/* PLDM_MODIFIER_MILLI */
+	100,
+	10,			/* PLDM_MODIFIER_DECI */
+	1,			/* PLDM_MODIFIER_NONE */
+};
+
+static const unsigned int pldm_to_hwmon_temp[PLDM_THRESHOLD_COUNT] = {
+	[PLDM_THRESHOLD_UPPER_WARNING] = HWMON_T_MAX,
+	[PLDM_THRESHOLD_UPPER_CRITICAL] = HWMON_T_CRIT,
+};
+
+static const unsigned int pldm_to_hwmon_in[PLDM_THRESHOLD_COUNT] = {
+	[PLDM_THRESHOLD_UPPER_WARNING] = HWMON_I_MAX,
+	[PLDM_THRESHOLD_LOWER_WARNING] = HWMON_I_MIN,
+	[PLDM_THRESHOLD_LOWER_CRITICAL] = HWMON_I_LCRIT,
+	[PLDM_THRESHOLD_UPPER_CRITICAL] = HWMON_I_CRIT,
+};
+
+static const unsigned int pldm_to_hwmon_curr[PLDM_THRESHOLD_COUNT] = {
+	[PLDM_THRESHOLD_UPPER_WARNING] = HWMON_C_MAX,
+	[PLDM_THRESHOLD_UPPER_CRITICAL] = HWMON_C_CRIT,
+};
+
+static const unsigned int pldm_to_hwmon_power[PLDM_THRESHOLD_COUNT] = {
+	[PLDM_THRESHOLD_UPPER_WARNING] = HWMON_P_MAX,
+	[PLDM_THRESHOLD_UPPER_CRITICAL] = HWMON_P_CRIT,
+};
+
+static void create_sensors_intf(struct cass_dev *hw)
+{
+	unsigned int config_idx = 0;
+	unsigned int sensor_idx = 0;
+	unsigned int sensor_type;
+	unsigned int channel;
+
+	if (hw->pldm_sensors_count > CASS_MAX_SENSORS) {
+		cxidev_WARN_ONCE(&hw->cdev, true, "Too many sensors for hwmon\n");
+		return;
+	}
+
+	/* Enumerate all sensors that can be converted between PLDM
+	 * and HWMON, and build a HWMON device.
+	 */
+	for (sensor_type = 0; sensor_type < ARRAY_SIZE(pldm_sensor_to_hwmon);
+	     sensor_type++) {
+		struct pldm_sensor *sensor;
+		bool present = false;
+		int unit_modifier;
+		int id;
+
+		/* Find whether a sensor of that PLDM type is present */
+		idr_for_each_entry(&hw->pldm_sensors, sensor, id) {
+			if (sensor->num.base_unit !=
+			    pldm_sensor_to_hwmon[sensor_type].pldm_base_unit)
+				continue;
+
+			present = true;
+			break;
+		}
+
+		if (!present)
+			continue;
+
+		hw->hwmon.info[sensor_idx].type =
+			pldm_sensor_to_hwmon[sensor_type].hwmon_type;
+		hw->hwmon.info[sensor_idx].config =
+			(const u32 *)&hw->hwmon.config[config_idx];
+
+		/* Create the config for all sensors of that type */
+		channel = 0;
+		idr_for_each_entry(&hw->pldm_sensors, sensor, id) {
+			unsigned long thresh_mask;
+			unsigned int hwmon_input;
+			unsigned int bit;
+
+			if (sensor->num.base_unit !=
+			    pldm_sensor_to_hwmon[sensor_type].pldm_base_unit)
+				continue;
+
+			sensor->hwmon.type =
+				pldm_sensor_to_hwmon[sensor_type].hwmon_type;
+			sensor->hwmon.channel = channel;
+
+			/* Compute the multiplier to apply to convert
+			 * from PLDM value to hwmon, taking into
+			 * account both the pldm and hwmon
+			 * multipliers.
+			 */
+			unit_modifier = sensor->num.unit_modifier;
+			if (unit_modifier < PLDM_MODIFIER_NANO ||
+			    unit_modifier > PLDM_MODIFIER_NONE)
+				unit_modifier = PLDM_MODIFIER_NONE;
+
+			unit_modifier -= PLDM_MODIFIER_NANO;
+
+			hwmon_input = pldm_sensor_to_hwmon[sensor_type].hwmon_input;
+			thresh_mask = get_pldm_value(sensor, supported_thresholds);
+
+			switch (sensor->hwmon.type) {
+			case hwmon_temp:
+				sensor->hwmon.multiplier = 1000 /
+					pldm_multiplier[unit_modifier];
+
+				for_each_set_bit(bit, &thresh_mask, PLDM_THRESHOLD_COUNT)
+					hwmon_input |= pldm_to_hwmon_temp[bit];
+
+				break;
+			case hwmon_in:
+				sensor->hwmon.multiplier = 1000 /
+					pldm_multiplier[unit_modifier];
+
+				for_each_set_bit(bit, &thresh_mask, PLDM_THRESHOLD_COUNT)
+					hwmon_input |= pldm_to_hwmon_in[bit];
+
+				break;
+			case hwmon_curr:
+				sensor->hwmon.multiplier = 1000 /
+					pldm_multiplier[unit_modifier];
+
+				for_each_set_bit(bit, &thresh_mask, PLDM_THRESHOLD_COUNT)
+					hwmon_input |= pldm_to_hwmon_curr[bit];
+
+				break;
+			case hwmon_power:
+				sensor->hwmon.multiplier = 1000000 /
+					pldm_multiplier[unit_modifier];
+
+				for_each_set_bit(bit, &thresh_mask, PLDM_THRESHOLD_COUNT)
+					hwmon_input |= pldm_to_hwmon_power[bit];
+
+				break;
+			default:
+				sensor->hwmon.multiplier = 1;
+			}
+
+			hw->hwmon.config[config_idx] = hwmon_input;
+
+			config_idx++;
+			channel++;
+		};
+
+		config_idx++;		/* NUL terminator */
+
+		hw->hwmon.all_types[sensor_idx] = &hw->hwmon.info[sensor_idx];
+		sensor_idx++;
+	}
+
+	hw->hwmon.all_types[sensor_idx] = NULL;
+
+	hw->hwmon.chip_info.ops = &cxi_hwmon_ops;
+	hw->hwmon.chip_info.info = hw->hwmon.all_types;
+
+	hw->hwmon.dev = hwmon_device_register_with_info(&hw->cdev.pdev->dev,
+							hw->cdev.name,
+							hw,
+							&hw->hwmon.chip_info,
+							NULL);
+	if (IS_ERR(hw->hwmon.dev)) {
+		dev_err(&hw->cdev.pdev->dev,
+			"Failed to register sensors: %ld\n",
+			PTR_ERR(hw->hwmon.dev));
+		hw->hwmon.dev = NULL;
+	}
+}
+
+static int cass_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
+{
+	struct cass_dev *hw = i2c_get_adapdata(adap);
+	int ret = 0;
+	int i;
+
+	mutex_lock(&hw->uc_mbox_mutex);
+
+	for (i = 0; i < num; i++) {
+		struct i2c_msg *msg = &msgs[i];
+
+		uc_prepare_comm(hw);
+
+		if (msg->flags & I2C_M_RD) {
+			struct cuc_i2c_read_req *req_data =
+				(struct cuc_i2c_read_req *)hw->uc_req.data;
+
+			hw->uc_req.cmd = CUC_CMD_I2C_READ;
+			hw->uc_req.count = 1 + sizeof(*req_data);
+			req_data->bus = QSFP_I2C_BUS_REDIRECT;
+			req_data->addr = msg->addr;
+			req_data->count = msg->len;
+		} else {
+			struct cuc_i2c_write_req *req_data =
+				(struct cuc_i2c_write_req *)hw->uc_req.data;
+
+			hw->uc_req.cmd = CUC_CMD_I2C_WRITE;
+			hw->uc_req.count = 1 + sizeof(*req_data) + msg->len;
+			req_data->bus = QSFP_I2C_BUS_REDIRECT;
+			req_data->addr = msg->addr;
+			req_data->count = msg->len;
+			memcpy(req_data->buf, msg->buf, msg->len);
+		}
+
+		ret = uc_wait_for_response(hw);
+		if (ret) {
+			cxidev_err(&hw->cdev, "uC failed to perform i2c request\n");
+			goto out;
+		}
+
+		if (msg->flags & I2C_M_RD)
+			memcpy(msg->buf, hw->uc_resp.data, msg->len);
+	}
+
+out:
+	mutex_unlock(&hw->uc_mbox_mutex);
+
+	return ret ?: num;
+}
+
+static u32 cass_i2c_func(struct i2c_adapter *adap)
+{
+	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
+}
+
+static const struct i2c_adapter_quirks uc_i2c_quirks = {
+	.max_read_len = CUC_DATA_BYTES - sizeof(struct cuc_i2c_read_req),
+	.max_write_len = CUC_DATA_BYTES - sizeof(struct cuc_i2c_write_req),
+};
+
+static const struct i2c_algorithm cass_i2c_algo = {
+	.master_xfer = cass_i2c_xfer,
+	.functionality = cass_i2c_func,
+};
+
+/* The i2c bus device whose sole purpose is to access the QSFP headshell. */
+static int uc_register_i2c(struct cass_dev *hw)
+{
+	int ret;
+
+	if (!hw->uc_present)
+		return 0;
+
+	if (hw->uc_platform != CUC_BOARD_TYPE_BRAZOS &&
+	    hw->uc_platform != CUC_BOARD_TYPE_KENNEBEC &&
+	    hw->uc_platform != CUC_BOARD_TYPE_SOUHEGAN &&
+	    !HW_PLATFORM_NETSIM(hw))
+		return 0;
+
+	hw->uc_i2c.owner = THIS_MODULE;
+	hw->uc_i2c.algo = &cass_i2c_algo;
+	hw->uc_i2c.timeout = msecs_to_jiffies(1000);
+	hw->uc_i2c.retries = 2;
+	hw->uc_i2c.quirks = &uc_i2c_quirks;
+	hw->uc_i2c.dev.parent = &hw->cdev.pdev->dev;
+	i2c_set_adapdata(&hw->uc_i2c, hw);
+
+	snprintf(hw->uc_i2c.name, sizeof(hw->uc_i2c.name), "%s headshell", hw->cdev.name);
+
+	ret = i2c_add_adapter(&hw->uc_i2c);
+	if (ret) {
+		hw->uc_i2c.algo = NULL;
+		return ret;
+	}
+
+	dev_dbg(&hw->cdev.pdev->dev, "Added i2c controller %d\n", hw->uc_i2c.nr);
+
+	return 0;
+}
+
+static void uc_unregister_i2c(struct cass_dev *hw)
+{
+	if (hw->uc_i2c.algo)
+		i2c_del_adapter(&hw->uc_i2c);
+}
+
+int cass_register_uc(struct cass_dev *hw)
+{
+	int rc;
+
+	mutex_init(&hw->uc_mbox_mutex);
+	init_completion(&hw->uc_attention0_comp);
+	INIT_WORK(&hw->uc_attn1_work, attn1_worker);
+	idr_init(&hw->pldm_sensors);
+
+	rc = cxi_dmac_desc_set_reserve(&hw->cdev, 32, HOST_TO_UC_FIRST, "uc");
+	if (rc < 0) {
+		cxidev_err(&hw->cdev, "Failed to reserve UC DMAC space\n");
+		return rc;
+	}
+	hw->uc_dmac_id = rc;
+
+	hw->uc_attn1_wq = alloc_workqueue("uc_attn1", WQ_UNBOUND, 1);
+	if (!hw->uc_attn1_wq) {
+		cxidev_err(&hw->cdev, "Failed to allocate UC attn1 workqueue\n");
+		rc = -ENOMEM;
+		goto free_dmac_id;
+	}
+
+	/* Create the uC sysfs entries */
+	rc = kobject_init_and_add(&hw->uc_kobj, &uc_sysfs_entries,
+				  &hw->cdev.pdev->dev.kobj,
+				  "uc");
+	if (rc < 0)
+		goto free_wq;
+
+	/* Register callback for C_PI_ERR_FLG.UC_ATTENTION bits */
+	hw->uc_err.irq = C_PI_IRQA_MSIX_INT;
+	hw->uc_err.is_ext = false;
+	hw->uc_err.err_flags.pi.uc_attention = 0b11;
+	hw->uc_err.cb = uc_attention_cb;
+	cxi_register_hw_errors(hw, &hw->uc_err);
+
+	/* Some test platforms do not have a uC */
+	mutex_lock(&hw->uc_mbox_mutex);
+
+	uc_prepare_comm(hw);
+
+	hw->uc_req.cmd = CUC_CMD_PING;
+	hw->uc_req.count = 1;
+
+	rc = uc_wait_for_response(hw);
+
+	hw->uc_present = rc == 0;
+
+	mutex_unlock(&hw->uc_mbox_mutex);
+
+	if (!hw->uc_present)
+		cxidev_err(&hw->cdev, "uC not detected: %d\n", rc);
+
+	uc_cmd_update_ier(hw, HOST_CLEARED_ATT1_INTERRUPTS, 0);
+
+	uc_cmd_get_fw_versions(hw);
+
+	/* Find all sensors, and check whether they are currently
+	 * reporting some error.
+	 */
+	iterate_pdr(hw);
+	check_sensor_values(hw);
+
+	create_sensors_intf(hw);
+
+	uc_cmd_get_fru(hw);
+
+	set_uc_platform(hw);
+
+	uc_update_cable_info(hw);
+
+	uc_register_i2c(hw);
+
+	return 0;
+
+free_wq:
+	kobject_put(&hw->uc_kobj);
+	destroy_workqueue(hw->uc_attn1_wq);
+
+free_dmac_id:
+	cxi_dmac_desc_set_free(&hw->cdev, hw->uc_dmac_id);
+
+	return rc;
+}
+
+void cass_unregister_uc(struct cass_dev *hw)
+{
+	struct pldm_sensor *sensor;
+	int id;
+
+	uc_cmd_update_ier(hw, 0, ATT1_ALL_INTERRUPTS);
+	uc_unregister_i2c(hw);
+	if (hw->hwmon.dev)
+		hwmon_device_unregister(hw->hwmon.dev);
+	kobject_put(&hw->uc_kobj);
+	cxi_dmac_desc_set_free(&hw->cdev, hw->uc_dmac_id);
+	destroy_workqueue(hw->uc_attn1_wq);
+	cxi_unregister_hw_errors(hw, &hw->uc_err);
+	idr_for_each_entry(&hw->pldm_sensors, sensor, id)
+		kfree(sensor);
+	idr_destroy(&hw->pldm_sensors);
+}
diff --git a/drivers/net/ethernet/hpe/ss1/cxi_ac_entry_list.c b/drivers/net/ethernet/hpe/ss1/cxi_ac_entry_list.c
new file mode 100644
index 000000000000..183e11821ce7
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cxi_ac_entry_list.c
@@ -0,0 +1,499 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2020 Hewlett Packard Enterprise Development LP */
+
+/* Access Control Entry lists */
+
+#include "cass_core.h"
+#include "cxi_ac_entry_list.h"
+
+/* **************************************************************** */
+/* Access Control List operations                                   */
+/* **************************************************************** */
+struct cxi_ac_entry {
+	unsigned int       id;
+	enum cxi_ac_type   type;
+	union cxi_ac_data  data;
+};
+
+static const struct xa_limit ac_entry_id_limits  = AC_ENTRY_ID_LIMITS;
+static const uid_t  invalid_uid = (uid_t)-1;
+static const gid_t  invalid_gid = (gid_t)-1;
+static const unsigned int invalid_netns = (unsigned int)-1;
+
+static bool validate_ac_data(cxi_ac_typeset_t ac_type,
+			     const union cxi_ac_data *data)
+{
+	switch (ac_type) {
+	case CXI_AC_UID:
+		return (data->uid != invalid_uid);
+	case CXI_AC_GID:
+		return (data->gid != invalid_gid);
+	case CXI_AC_OPEN:
+		return true;
+	case CXI_AC_NETNS:
+		return (data->netns != invalid_netns);
+	default:
+		return false;
+	}
+}
+
+static int ac_entry_list_insert_entry(struct cxi_ac_entry_list *list,
+				      enum cxi_ac_type type,
+				      const union cxi_ac_data *data,
+				      unsigned int *ac_entry_id)
+{
+	struct cxi_ac_entry   *ac_entry;
+	int    ret;
+
+	ac_entry = kzalloc(sizeof(*ac_entry), AC_ENTRY_GFP_OPTS);
+	if (!ac_entry)
+		return -ENOMEM;
+
+	/* allocate an Id for this entry */
+
+	ret = xa_alloc(&list->id.xarray, &ac_entry->id, ac_entry,
+		       ac_entry_id_limits, AC_ENTRY_GFP_OPTS);
+
+	if (ret)
+		goto free_entry;
+
+	ac_entry->type = type;
+	ac_entry->data = *data;
+	*ac_entry_id   = ac_entry->id;
+
+	/* store the entry in the appropriate xarray */
+
+	switch (ac_entry->type) {
+	case CXI_AC_UID:
+		ret = xa_insert(&list->uid.xarray, ac_entry->data.uid,
+				ac_entry, AC_ENTRY_GFP_OPTS);
+		break;
+	case CXI_AC_GID:
+		ret = xa_insert(&list->gid.xarray, ac_entry->data.gid,
+				ac_entry, AC_ENTRY_GFP_OPTS);
+		break;
+	case CXI_AC_OPEN:
+		xa_lock(&list->id.xarray);
+		if (list->open_entry)
+			ret = -EBUSY;
+		else
+			list->open_entry = ac_entry;
+		xa_unlock(&list->id.xarray);
+		break;
+	case CXI_AC_NETNS:
+		ret = xa_insert(&list->netns.xarray, ac_entry->data.netns,
+				ac_entry, AC_ENTRY_GFP_OPTS);
+		break;
+	default:
+		ret = -EBADR;
+	}
+
+	if (!ret)
+		return 0;
+
+	/* if we failed, we need to deallocate the id */
+
+	xa_erase(&list->id.xarray, ac_entry->id);
+
+free_entry:
+	kfree(ac_entry);
+	return ret;
+}
+
+static int ac_entry_list_delete_entry(struct cxi_ac_entry_list *list,
+				      unsigned int ac_entry_id)
+{
+	struct cxi_ac_entry   *ac_entry;
+	int    ret;
+
+	ac_entry = xa_load(&list->id.xarray, ac_entry_id);
+	ret = xa_err(ac_entry);
+	if (ret)
+		return ret;
+	if (!ac_entry)
+		return -ENODATA;
+
+	switch (ac_entry->type) {
+	case CXI_AC_UID:
+		xa_erase(&list->uid.xarray, ac_entry->data.uid);
+		break;
+	case CXI_AC_GID:
+		xa_erase(&list->gid.xarray, ac_entry->data.gid);
+		break;
+	case CXI_AC_OPEN:
+		list->open_entry = NULL;
+		break;
+	case CXI_AC_NETNS:
+		xa_erase(&list->netns.xarray, ac_entry->data.netns);
+		break;
+	default:
+		ret = -EIO;
+		break;
+	}
+
+	xa_erase(&list->id.xarray, ac_entry_id);
+
+	kfree(ac_entry);
+	return ret;
+}
+
+/**
+ * ac_entry_list_iterate() - call a function on all entries in the list
+ *
+ * @list: list pointer
+ * @operator: function to call with each AC Entry and user_data
+ * @user_data: second argument to operator function
+ *
+ * Return: the first non-zero return value of 'operator' or 0.
+ */
+static int ac_entry_list_iterate(struct cxi_ac_entry_list *list,
+				 int (*operator)(struct cxi_ac_entry *ac_entry,
+						 void *user_data),
+				 void *user_data)
+{
+	struct cxi_ac_entry     *ac_entry;
+	unsigned long           index = ac_entry_id_limits.min;
+
+	xa_for_each(&list->id.xarray, index, ac_entry) {
+		int ret = operator(ac_entry, user_data);
+
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+/**
+ * cxi_ac_entry_list_init() - initialize a list of AC Entries
+ *
+ * @list: address of list
+ */
+void cxi_ac_entry_list_init(struct cxi_ac_entry_list *list)
+{
+	xa_init_flags(&list->id.xarray, AC_ENTRY_ID_XARRAY_FLAGS);
+	xa_init_flags(&list->gid.xarray, AC_ENTRY_GID_XARRAY_FLAGS);
+	xa_init_flags(&list->uid.xarray, AC_ENTRY_UID_XARRAY_FLAGS);
+	xa_init_flags(&list->netns.xarray, AC_ENTRY_NETNS_XARRAY_FLAGS);
+}
+
+/**
+ * cxi_ac_entry_list_purge() - Remove all AC Entries from a list
+ *
+ * @list: address of list
+ */
+void cxi_ac_entry_list_purge(struct cxi_ac_entry_list *list)
+{
+	unsigned long          index = ac_entry_id_limits.min;
+	struct cxi_ac_entry    *ac_entry;
+
+	xa_for_each(&list->id.xarray, index, ac_entry) {
+		ac_entry_list_delete_entry(list, index);
+	}
+}
+
+/**
+ * cxi_ac_entry_list_destroy() - tear down a list of AC Entries.  The
+ *                               list infrastructure is destroyed.
+ *
+ * @list: pointer to list
+ */
+void cxi_ac_entry_list_destroy(struct cxi_ac_entry_list *list)
+{
+	cxi_ac_entry_list_purge(list);
+
+	xa_destroy(&list->id.xarray);
+	xa_destroy(&list->gid.xarray);
+	xa_destroy(&list->uid.xarray);
+	xa_destroy(&list->netns.xarray);
+}
+
+/**
+ * cxi_ac_entry_list_empty() - determine if any AC Entries are present
+ *
+ * @list: list pointer
+ *
+ * Return: true if no entries present, false otherwise
+ */
+bool cxi_ac_entry_list_empty(struct cxi_ac_entry_list *list)
+{
+	return xa_empty(&list->id.xarray);
+}
+
+/**
+ * cxi_ac_entry_list_insert() - allocate an id and add an AC Entry
+ *                              to the list
+ *
+ * @list: list pointer
+ * @ac_type: one of the cxi_ac_type enums
+ * @ac_data: pointer to cxi_ac_data struct
+ * @id: location to store new Id
+ *
+ * Return:
+ * * 0       - success
+ * * -ENOMEM - unable to allocate memory
+ * * -EBUSY  - no free entries available
+ * * -EBADR  - invalid type or data
+ * * -EEXIST - entry with same data exists
+ */
+int cxi_ac_entry_list_insert(struct cxi_ac_entry_list *list,
+			     enum cxi_ac_type ac_type,
+			     const union cxi_ac_data *ac_data,
+			     unsigned int *id)
+{
+	int   ret;
+
+	if (!validate_ac_data(ac_type, ac_data))
+		return -EBADR;
+
+	ret = ac_entry_list_insert_entry(list, ac_type, ac_data, id);
+	switch (ret) {
+	case -EBUSY:   /* translate xarray EBUSY to EEXIST */
+		return -EEXIST;
+	default:
+		return ret;
+	}
+}
+
+/**
+ * cxi_ac_entry_list_delete() - remove an AC Entry from the
+ *                              list by Id
+ *
+ * @list: list pointer
+ * @id: desired AC Entry Id to remove
+ *
+ * Return:
+ * * 0        - success
+ * * -EBADR   - not found with given id
+ */
+int cxi_ac_entry_list_delete(struct cxi_ac_entry_list *list,
+			     unsigned int id)
+{
+	return ac_entry_list_delete_entry(list, id);
+}
+
+/**
+ * cxi_ac_entry_list_retrieve_by_id() - get AC type and data by id
+ *
+ * @list: list pointer
+ * @id: id of ac entry to retrieve
+ * @type: location to store type
+ * @data: location to store data
+ *
+ * Return:
+ * * 0       - success
+ * * -EBADR  - AC Entry with given id not found
+ */
+int cxi_ac_entry_list_retrieve_by_id(struct cxi_ac_entry_list *list,
+				     unsigned int id,
+				     enum cxi_ac_type *type,
+				     union cxi_ac_data *data)
+{
+	struct cxi_ac_entry   *ac_entry;
+
+	ac_entry = xa_load(&list->id.xarray, id);
+	if (!ac_entry)
+		return -EBADR;
+
+	switch (ac_entry->type) {
+	case CXI_AC_UID:
+		data->uid = ac_entry->data.uid;
+		break;
+	case CXI_AC_GID:
+		data->gid = ac_entry->data.gid;
+		break;
+	case CXI_AC_OPEN:
+		break;
+	default:
+		return -EIO;   /* yikes */
+	}
+	*type = ac_entry->type;
+	return 0;
+}
+
+/**
+ * cxi_ac_entry_list_retrieve_by_data() - get an AC Entry ID by type and
+ *                                        data value
+ *
+ * @list: list pointer
+ * @ac_type: type of entry
+ * @ac_data: uid/gid data
+ * @id: location to store id value
+ *
+ * Return:
+ * * 0        - success
+ * * -EBADR   - AC Entry with given type&data not found
+ * * -EINVAL  - invalid ac_type or data
+ */
+int
+cxi_ac_entry_list_retrieve_by_data(struct cxi_ac_entry_list *list,
+				   enum cxi_ac_type ac_type,
+				   const union cxi_ac_data *ac_data,
+				   unsigned int *id)
+{
+	struct cxi_ac_entry   *ac_entry = NULL;
+
+	if (!validate_ac_data(ac_type, ac_data))
+		return -EINVAL;
+
+	switch (ac_type) {
+	case CXI_AC_OPEN:
+		ac_entry = list->open_entry;
+		break;
+	case CXI_AC_UID:
+		ac_entry = xa_load(&list->uid.xarray, ac_data->uid);
+		break;
+	case CXI_AC_GID:
+		ac_entry = xa_load(&list->gid.xarray, ac_data->gid);
+		break;
+	case CXI_AC_NETNS:
+		/* Execute this block only when the user provided a netns AC type.
+		 * Maintains compatibility with older versions.
+		 */
+		if (!xa_empty(&list->netns.xarray))
+			ac_entry = xa_load(&list->netns.xarray, ac_data->netns);
+		break;
+	default:
+		break;
+	}
+
+	if (!ac_entry)
+		return -EBADR;
+
+	*id = ac_entry->id;
+	return 0;
+}
+
+/**
+ * cxi_ac_entry_list_retrieve_by_user() - get an access control entry Id
+ *           which covers the given uid/gid, if any.  There may be more than
+ *           one possible, the priority order is: UID, GID, OPEN.
+ *
+ * @list: the ac_entry_list to search
+ * @uid: user id
+ * @gid: group id
+ * @netns: The Network Namespace id
+ * @desired_types: one of more of the enum cxi_ac_type values (OR'd together)
+ * @id: location to store the id
+ *
+ * Return:
+ * * 0        - success
+ * * -EPERM   - no access control found for uid/gid
+ * * -EBADR   - no valid desired types specified
+ */
+int cxi_ac_entry_list_retrieve_by_user(struct cxi_ac_entry_list *list,
+				       uid_t uid,
+				       gid_t gid,
+				       unsigned int netns,
+				       cxi_ac_typeset_t desired_types,
+				       unsigned int *id)
+{
+	union cxi_ac_data           data = {};
+
+	if ((desired_types & CXI_AC_ANY) == 0)
+		return -EBADR;
+
+	if (desired_types & CXI_AC_UID) {
+		data.uid = uid;
+		if (!cxi_ac_entry_list_retrieve_by_data(list, CXI_AC_UID,
+							&data, id))
+			return 0;
+	}
+
+	if (desired_types & CXI_AC_GID) {
+		data.gid = gid;
+		if (!cxi_ac_entry_list_retrieve_by_data(list, CXI_AC_GID,
+							&data, id))
+			return 0;
+	}
+
+	if (desired_types & CXI_AC_NETNS) {
+		data.netns = netns;
+		if (!cxi_ac_entry_list_retrieve_by_data(list, CXI_AC_NETNS,
+							&data, id))
+			return 0;
+	}
+
+	if (desired_types & CXI_AC_OPEN) {
+		if (!cxi_ac_entry_list_retrieve_by_data(list, CXI_AC_OPEN,
+							&data, id))
+			return 0;
+	}
+
+	return -EPERM;
+}
+
+struct get_ids_data {
+	size_t         max_ids;
+	unsigned int   *ids;
+	size_t         num_ids;
+};
+
+static int get_ids_operator(struct cxi_ac_entry *ac_entry,
+			    void *user_data)
+{
+	struct get_ids_data   *data = user_data;
+
+	if (data->num_ids < data->max_ids) {
+		*data->ids = ac_entry->id;
+		data->ids++;
+	}
+
+	data->num_ids++;
+	return 0;
+}
+
+/**
+ * cxi_ac_entry_list_get_ids() - retrieve the ids of all entries in the list
+ *
+ * @list: the list pointer
+ * @max_ids: the size of the 'ids' array
+ * @ids: location to store ids
+ * @num_ids: location to store actual number of ids copied to list
+ *
+ * Return:
+ * * 0       - success
+ * * -ENOSPC - max_ids is not large enough (num_ids holds required size)
+ */
+int cxi_ac_entry_list_get_ids(struct cxi_ac_entry_list *list,
+			      size_t max_ids,
+			      unsigned int *ids,
+			      size_t *num_ids)
+{
+	struct get_ids_data    data = {
+		.max_ids = max_ids,
+		.ids     = ids,
+		.num_ids = 0,
+	};
+	int    ret;
+
+	ret = ac_entry_list_iterate(list, get_ids_operator, &data);
+	if (ret)
+		return ret;
+
+	*num_ids = data.num_ids;
+
+	return (data.num_ids <= max_ids) ? 0 : -ENOSPC;
+}
+
+/**
+ * cxi_ac_entry_list_retrieve_netns() - Get an AC Entry of type netns
+ *
+ * @list: list pointer
+ * @ac_data: The first netns value found in the list
+ *
+ * Return:
+ * * 0        - success
+ * * -EINVAL  - No netns entry found
+ */
+int cxi_ac_entry_list_retrieve_netns(struct cxi_ac_entry_list *list,  union cxi_ac_data *ac_data)
+{
+	struct cxi_ac_entry *entry;
+	unsigned long index;
+
+	xa_for_each(&list->netns.xarray, index, entry) {
+		ac_data->netns = index;
+		return 0;
+	}
+	return -EINVAL;
+}
diff --git a/drivers/net/ethernet/hpe/ss1/cxi_qos_profiles.c b/drivers/net/ethernet/hpe/ss1/cxi_qos_profiles.c
new file mode 100644
index 000000000000..5f3977c494c4
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cxi_qos_profiles.c
@@ -0,0 +1,722 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/*
+ * Cassini QoS Profiles
+ * Copyright 2023 Hewlett Packard Enterprise Development LP
+ */
+#include "cass_core.h"
+
+#define SRB_MAX_SIZE 2048U
+
+/* Reserve half the SRB space to cover C2 expected bandwidth delay product. The
+ * remainder of the space should be split up between the RDMA traffic classes.
+ */
+#define SRB_SHARED_MAX (SRB_MAX_SIZE / 2)
+
+/* Since low-latency does not need to sustain bandwidth, reserve only a few
+ * MTU sized packets worth of SRB.
+ */
+#define LOW_LATENCY_SRB_RSVD 32U
+
+/* SRB Space Reserved for the Global Restricted BC - C1 Only */
+#define C1_SRB_GLOBAL_RES_BC_RSVD 39U
+
+/* SRB Space Available to Split Between other RDMA TCs */
+#define C1_SRB_RESERVED (SRB_MAX_SIZE - SRB_SHARED_MAX - C1_SRB_GLOBAL_RES_BC_RSVD - LOW_LATENCY_SRB_RSVD)
+#define C2_SRB_RESERVED (SRB_MAX_SIZE - SRB_SHARED_MAX - LOW_LATENCY_SRB_RSVD)
+
+struct qos_profile profiles[CXI_QOS_NUM_PROF] = {
+	/* HPC Profile */
+	[CXI_QOS_HPC] = {
+		/* Shared with low latency */
+		.pct_control_pcp = 5,
+		.untagged_eth_pcp = 6, /* Shared with Eth1 */
+		.tcs_active = {
+			[CXI_TC_DEDICATED_ACCESS] = true,
+			[CXI_TC_LOW_LATENCY] = true,
+			[CXI_TC_BULK_DATA] = true,
+			[CXI_TC_BEST_EFFORT] = true,
+
+			[CXI_ETH_SHARED] = true,
+			[CXI_ETH_TC1] = true,
+		},
+		.tcs = {
+			[CXI_TC_DEDICATED_ACCESS] = {
+				.dscp_pcp_settings = {
+					.req_pcp = 6,
+					.rsp_pcp = 7,
+					.res_rsp_dscp = 13,
+					.unres_rsp_dscp = 15,
+					.res_req_dscp = 12,
+					.unres_req_dscp = 14,
+					.hrp_res_req_dscp = -1,
+					.coll_leaf_res_req_dscp = -1,
+					.restricted_unres_req_dscp = -1,
+				},
+				.ixe_settings = {
+					.fq_count = 10,
+				},
+				.lpe_settings = {
+					.fq_count = 8,
+				},
+				.pct_settings = {
+					.trs_rsvd = 64,
+					.mst_rsvd = 64,
+					.tct_rsvd = 256,
+				},
+				.oxe_settings = {
+					.smt_rsvd = 4,
+					.sct_rsvd = 4,
+					.pbuf_rsvd = 39,
+					.assured_percent = 50,
+					.ceiling_percent = 100,
+					.bucket_limit = DIV_ROUND_UP(4 * PORTALS_MAX_FRAME_SIZE, 1024),
+					.leaf_request_priority = 2,
+					.leaf_response_priority = 1,
+					.branch_priority = 1,
+					.mfs_index = 0,
+				},
+				.cq_settings = {
+					.dynamic_fq_count = 8,
+					.fq_buf_reserved = 32,
+					.pfq_high_thresh = 64,
+				},
+				.hni_settings = {
+					.pbuf_rsvd = 128,
+					.mfs = PORTALS_MAX_FRAME_SIZE,
+				},
+			},
+			[CXI_TC_LOW_LATENCY] = {
+				.dscp_pcp_settings = {
+					.req_pcp = 4,
+					.rsp_pcp = 5,
+					.res_rsp_dscp = 9,
+					.unres_rsp_dscp = 11,
+					.res_req_dscp = 8,
+					.unres_req_dscp = 10,
+					.hrp_res_req_dscp = -1,
+					.coll_leaf_res_req_dscp = -1,
+					.restricted_unres_req_dscp = -1,
+				},
+				.ixe_settings = {
+					.fq_count = 2,
+				},
+				.lpe_settings = {
+
+					.fq_count = 2,
+				},
+				.pct_settings = {
+					.trs_rsvd = 64,
+					.mst_rsvd = 64,
+					.tct_rsvd = 256,
+				},
+				.oxe_settings = {
+					.spt_rsvd = 64,
+					.smt_rsvd = 4,
+					.sct_rsvd = 4,
+					.srb_rsvd = LOW_LATENCY_SRB_RSVD,
+					.pbuf_rsvd = 13,
+					.assured_percent = 15,
+					.ceiling_percent = 30,
+					.bucket_limit = DIV_ROUND_UP(4 * PORTALS_MAX_FRAME_SIZE, 1024),
+					.leaf_request_priority = 7,
+					.leaf_response_priority = 6,
+					.branch_priority = 6,
+					.mfs_index = 0,
+				},
+				.cq_settings = {
+					.dynamic_fq_count = 2,
+					.fq_buf_reserved = 32,
+					.pfq_high_thresh = 64,
+				},
+				.hni_settings = {
+					.pbuf_rsvd = 128,
+					.mfs = PORTALS_MAX_FRAME_SIZE,
+				},
+			},
+			[CXI_TC_BULK_DATA] = {
+				.dscp_pcp_settings = {
+					.req_pcp = 2,
+					.rsp_pcp = 3,
+					.res_rsp_dscp = 5,
+					.unres_rsp_dscp = 7,
+					.res_req_dscp = 4,
+					.unres_req_dscp = 6,
+					.hrp_res_req_dscp = -1,
+					.coll_leaf_res_req_dscp = -1,
+					.restricted_unres_req_dscp = -1,
+				},
+				.ixe_settings = {
+					.fq_count = 4,
+				},
+				.lpe_settings = {
+					.fq_count = 2,
+				},
+				.pct_settings = {
+					.trs_rsvd = 32,
+					.mst_rsvd = 32,
+					.tct_rsvd = 128,
+				},
+				.oxe_settings = {
+					.smt_rsvd = 4,
+					.sct_rsvd = 4,
+					.pbuf_rsvd = 39,
+					.assured_percent = 15,
+					.ceiling_percent = 100,
+					.bucket_limit = DIV_ROUND_UP(2 * PORTALS_MAX_FRAME_SIZE, 1024),
+					.leaf_request_priority = 2,
+					.leaf_response_priority = 1,
+					.branch_priority = 1,
+					.mfs_index = 0,
+				},
+				.cq_settings = {
+					.dynamic_fq_count = 4,
+					.fq_buf_reserved = 32,
+					.pfq_high_thresh = 64,
+				},
+				.hni_settings = {
+					.pbuf_rsvd = 64,
+					.mfs = PORTALS_MAX_FRAME_SIZE,
+				},
+			},
+			[CXI_TC_BEST_EFFORT] = {
+				.dscp_pcp_settings = {
+					.req_pcp = 0,
+					.rsp_pcp = 1,
+					.res_rsp_dscp = 1,
+					.unres_rsp_dscp = 3,
+					.res_req_dscp = 0,
+					.unres_req_dscp = 2,
+					.hrp_res_req_dscp = 50,
+					.coll_leaf_res_req_dscp = 52,
+					.restricted_unres_req_dscp = 30,
+				},
+				.ixe_settings = {
+					.fq_count = 8,
+				},
+				.lpe_settings = {
+					.fq_count = 4,
+				},
+				.pct_settings = {
+					.trs_rsvd = 4,
+					.mst_rsvd = 4,
+					.tct_rsvd = 16,
+				},
+				.oxe_settings = {
+					.smt_rsvd = 4,
+					.sct_rsvd = 4,
+					.pbuf_rsvd = 13,
+					.assured_percent = 10,
+					.ceiling_percent = 100,
+					.bucket_limit = DIV_ROUND_UP(2 * PORTALS_MAX_FRAME_SIZE, 1024),
+					.leaf_request_priority = 2,
+					.leaf_response_priority = 1,
+					.branch_priority = 1,
+					.mfs_index = 0,
+				},
+				.cq_settings = {
+					.dynamic_fq_count = 8,
+					.static_fq_count = 16,
+					.fq_buf_reserved = 32,
+					.pfq_high_thresh = 64,
+				},
+				.hni_settings = {
+					.pbuf_rsvd = 17,
+					.mfs = PORTALS_MAX_FRAME_SIZE,
+				},
+			},
+			[CXI_TC_ETH] = {
+				.oxe_settings = {
+					.spt_rsvd = 30,
+					.pbuf_rsvd = DIV_ROUND_UP(ETHERNET_MAX_FRAME_SIZE, 256),
+				},
+				.cq_settings = {
+					.dynamic_fq_count = 2,
+					.static_fq_count = 2,
+					.fq_buf_reserved = 32,
+					.pfq_high_thresh = 64,
+				},
+				.hni_settings = {
+					.pbuf_rsvd = DIV_ROUND_UP(ETHERNET_MAX_FRAME_SIZE, 128),
+					.mfs = ETHERNET_MAX_FRAME_SIZE,
+				},
+
+			},
+			[CXI_ETH_SHARED] = {
+				.oxe_settings = {
+					.assured_percent = 10,
+					.ceiling_percent = 100,
+					.bucket_limit = DIV_ROUND_UP(2 * ETHERNET_MAX_FRAME_SIZE, 1024),
+					.leaf_request_priority = 1,
+					.branch_priority = 1,
+					.mfs_index = 1,
+				},
+			},
+			[CXI_ETH_TC1] = {
+				.eth_settings = {
+					.pcp =  6,
+				},
+				.oxe_settings = {
+					.assured_percent = 10,
+					.ceiling_percent = 100,
+					.bucket_limit = DIV_ROUND_UP(2 * ETHERNET_MAX_FRAME_SIZE, 1024),
+					.leaf_request_priority = 1,
+					.branch_priority = 1,
+					.mfs_index = 1,
+				},
+
+			},
+		},
+	},
+	[CXI_QOS_LL_BE_BD_ET] = {
+		.pct_control_pcp = 7,
+		.untagged_eth_pcp = 6, /* Shared with Eth1 */
+		.tcs_active = {
+			[CXI_TC_LOW_LATENCY] = true,
+			[CXI_TC_BULK_DATA] = true,
+			[CXI_TC_BEST_EFFORT] = true,
+
+			[CXI_ETH_SHARED] = true,
+			[CXI_ETH_TC1] = true,
+		},
+		.tcs = {
+			[CXI_TC_LOW_LATENCY] = {
+				.dscp_pcp_settings = {
+					.req_pcp = 4,
+					.rsp_pcp = 5,
+					.res_rsp_dscp = 9,
+					.unres_rsp_dscp = 11,
+					.res_req_dscp = 8,
+					.unres_req_dscp = 10,
+					.hrp_res_req_dscp = -1,
+					.coll_leaf_res_req_dscp = 52,
+					.restricted_unres_req_dscp = -1,
+				},
+				.ixe_settings = {
+					.fq_count = 2,
+				},
+				.lpe_settings = {
+
+					.fq_count = 2,
+				},
+				.pct_settings = {
+					.trs_rsvd = 64,
+					.mst_rsvd = 64,
+					.tct_rsvd = 256,
+				},
+				.oxe_settings = {
+					.spt_rsvd = 64,
+					.smt_rsvd = 4,
+					.sct_rsvd = 4,
+					.srb_rsvd = LOW_LATENCY_SRB_RSVD,
+					.pbuf_rsvd = 13,
+					.assured_percent = 2,
+					.ceiling_percent = 5,
+					.bucket_limit = DIV_ROUND_UP(4 * PORTALS_MAX_FRAME_SIZE, 1024),
+					.leaf_request_priority = 7,
+					.leaf_response_priority = 6,
+					.branch_priority = 6,
+					.mfs_index = 0,
+				},
+				.cq_settings = {
+					.dynamic_fq_count = 2,
+					.static_fq_count = 4,
+					.fq_buf_reserved = 32,
+					.pfq_high_thresh = 64,
+				},
+				.hni_settings = {
+					.pbuf_rsvd = 128,
+					.mfs = PORTALS_MAX_FRAME_SIZE,
+				},
+			},
+			[CXI_TC_BULK_DATA] = {
+				.dscp_pcp_settings = {
+					.req_pcp = 2,
+					.rsp_pcp = 3,
+					.res_rsp_dscp = 5,
+					.unres_rsp_dscp = 7,
+					.res_req_dscp = 4,
+					.unres_req_dscp = 6,
+					.hrp_res_req_dscp = -1,
+					.coll_leaf_res_req_dscp = -1,
+					.restricted_unres_req_dscp = -1,
+				},
+				.ixe_settings = {
+					.fq_count = 4,
+				},
+				.lpe_settings = {
+					.fq_count = 2,
+				},
+				.pct_settings = {
+					.trs_rsvd = 32,
+					.mst_rsvd = 32,
+					.tct_rsvd = 128,
+				},
+				.oxe_settings = {
+					.smt_rsvd = 4,
+					.sct_rsvd = 4,
+					.pbuf_rsvd = 39,
+					.assured_percent = 10, /* Fabric: 20 */
+					.ceiling_percent = 100,
+					.bucket_limit = DIV_ROUND_UP(2 * PORTALS_MAX_FRAME_SIZE, 1024),
+					.leaf_request_priority = 2,
+					.leaf_response_priority = 1,
+					.branch_priority = 1,
+					.mfs_index = 0,
+				},
+				.cq_settings = {
+					.dynamic_fq_count = 4,
+					.fq_buf_reserved = 32,
+					.pfq_high_thresh = 64,
+				},
+				.hni_settings = {
+					.pbuf_rsvd = 64,
+					.mfs = PORTALS_MAX_FRAME_SIZE,
+				},
+			},
+			[CXI_TC_BEST_EFFORT] = {
+				.dscp_pcp_settings = {
+					.req_pcp = 0,
+					.rsp_pcp = 1,
+					.res_rsp_dscp = 1,
+					.unres_rsp_dscp = 3,
+					.res_req_dscp = 0,
+					.unres_req_dscp = 2,
+					.hrp_res_req_dscp = 50,
+					.coll_leaf_res_req_dscp = -1,
+					.restricted_unres_req_dscp = 30,
+				},
+				.ixe_settings = {
+					.fq_count = 8,
+				},
+				.lpe_settings = {
+					.fq_count = 4,
+				},
+				.pct_settings = {
+					.trs_rsvd = 4,
+					.mst_rsvd = 4,
+					.tct_rsvd = 16,
+				},
+				.oxe_settings = {
+					.smt_rsvd = 4,
+					.sct_rsvd = 4,
+					.pbuf_rsvd = 13,
+					.assured_percent = 10, /* Fabric: 50 */
+					.ceiling_percent = 100,
+					.bucket_limit = DIV_ROUND_UP(2 * PORTALS_MAX_FRAME_SIZE, 1024),
+					.leaf_request_priority = 2,
+					.leaf_response_priority = 1,
+					.branch_priority = 1,
+					.mfs_index = 0,
+				},
+				.cq_settings = {
+					.dynamic_fq_count = 8,
+					.static_fq_count = 16,
+					.fq_buf_reserved = 32,
+					.pfq_high_thresh = 64,
+				},
+				.hni_settings = {
+					.pbuf_rsvd = 17,
+					.mfs = PORTALS_MAX_FRAME_SIZE,
+				},
+			},
+			[CXI_TC_ETH] = {
+				.oxe_settings = {
+					.spt_rsvd = 30,
+					.pbuf_rsvd = DIV_ROUND_UP(ETHERNET_MAX_FRAME_SIZE, 256),
+				},
+				.cq_settings = {
+					.dynamic_fq_count = 2,
+					.static_fq_count = 2,
+					.fq_buf_reserved = 32,
+					.pfq_high_thresh = 64,
+				},
+				.hni_settings = {
+					.pbuf_rsvd = DIV_ROUND_UP(ETHERNET_MAX_FRAME_SIZE, 128),
+					.mfs = ETHERNET_MAX_FRAME_SIZE,
+				},
+
+			},
+			[CXI_ETH_SHARED] = {
+				.oxe_settings = {
+					.assured_percent = 0,
+					.ceiling_percent = 100,
+					.bucket_limit = DIV_ROUND_UP(2 * ETHERNET_MAX_FRAME_SIZE, 1024),
+					.leaf_request_priority = 2,
+					.branch_priority = 1,
+					.mfs_index = 1,
+				},
+			},
+			[CXI_ETH_TC1] = {
+				.eth_settings = {
+					.pcp =  6,
+				},
+				.oxe_settings = {
+					.assured_percent = 10, /* Fabric: 20 */
+					.ceiling_percent = 100,
+					.bucket_limit = DIV_ROUND_UP(2 * ETHERNET_MAX_FRAME_SIZE, 1024),
+					.leaf_request_priority = 2,
+					.branch_priority = 1,
+					.mfs_index = 1,
+				},
+
+			},
+		},
+	},
+	[CXI_QOS_LL_BE_BD_ET1_ET2] = {
+		.pct_control_pcp = 7,
+		.untagged_eth_pcp = 2, /* Shared with Eth2 */
+		.tcs_active = {
+			[CXI_TC_LOW_LATENCY] = true,
+			[CXI_TC_BULK_DATA] = true,
+			[CXI_TC_BEST_EFFORT] = true,
+
+			[CXI_ETH_SHARED] = true,
+			[CXI_ETH_TC1] = true,
+			[CXI_ETH_TC2] = true,
+		},
+		.tcs = {
+			[CXI_TC_LOW_LATENCY] = {
+				.dscp_pcp_settings = {
+					.req_pcp = 4,
+					.rsp_pcp = 5,
+					.res_rsp_dscp = 40,
+					.unres_rsp_dscp = 41,
+					.res_req_dscp = 32,
+					.unres_req_dscp = 33,
+					.hrp_res_req_dscp = -1,
+					.coll_leaf_res_req_dscp = 52,
+					.restricted_unres_req_dscp = -1,
+				},
+				.ixe_settings = {
+					.fq_count = 2,
+				},
+				.lpe_settings = {
+
+					.fq_count = 2,
+				},
+				.pct_settings = {
+					.trs_rsvd = 64,
+					.mst_rsvd = 64,
+					.tct_rsvd = 256,
+				},
+				.oxe_settings = {
+					.spt_rsvd = 64,
+					.smt_rsvd = 4,
+					.sct_rsvd = 4,
+					.srb_rsvd = LOW_LATENCY_SRB_RSVD,
+					.pbuf_rsvd = 13,
+					.assured_percent = 2,
+					.ceiling_percent = 5,
+					.bucket_limit = DIV_ROUND_UP(4 * PORTALS_MAX_FRAME_SIZE, 1024),
+					.leaf_request_priority = 7,
+					.leaf_response_priority = 6,
+					.branch_priority = 6,
+					.mfs_index = 0,
+				},
+				.cq_settings = {
+					.dynamic_fq_count = 2,
+					.static_fq_count = 4,
+					.fq_buf_reserved = 32,
+					.pfq_high_thresh = 64,
+				},
+				.hni_settings = {
+					.pbuf_rsvd = 128,
+					.mfs = PORTALS_MAX_FRAME_SIZE,
+				},
+			},
+			[CXI_TC_BULK_DATA] = {
+				.dscp_pcp_settings = {
+					.req_pcp = 2,
+					.rsp_pcp = 3,
+					.res_rsp_dscp = 24,
+					.unres_rsp_dscp = 26,
+					.res_req_dscp = 16,
+					.unres_req_dscp = 18,
+					.hrp_res_req_dscp = -1,
+					.coll_leaf_res_req_dscp = -1,
+					.restricted_unres_req_dscp = -1,
+				},
+				.ixe_settings = {
+					.fq_count = 4,
+				},
+				.lpe_settings = {
+					.fq_count = 2,
+				},
+				.pct_settings = {
+					.trs_rsvd = 32,
+					.mst_rsvd = 32,
+					.tct_rsvd = 128,
+				},
+				.oxe_settings = {
+					.smt_rsvd = 4,
+					.sct_rsvd = 4,
+					.pbuf_rsvd = 39,
+					.assured_percent = 10, /* Fabric: 20 */
+					.ceiling_percent = 100,
+					.bucket_limit = DIV_ROUND_UP(2 * PORTALS_MAX_FRAME_SIZE, 1024),
+					.leaf_request_priority = 2,
+					.leaf_response_priority = 1,
+					.branch_priority = 1,
+					.mfs_index = 0,
+				},
+				.cq_settings = {
+					.dynamic_fq_count = 4,
+					.fq_buf_reserved = 32,
+					.pfq_high_thresh = 64,
+				},
+				.hni_settings = {
+					.pbuf_rsvd = 64,
+					.mfs = PORTALS_MAX_FRAME_SIZE,
+				},
+			},
+			[CXI_TC_BEST_EFFORT] = {
+				.dscp_pcp_settings = {
+					.req_pcp = 0,
+					.rsp_pcp = 1,
+					.res_rsp_dscp = 1,
+					.unres_rsp_dscp = 3,
+					.res_req_dscp = 0,
+					.unres_req_dscp = 2,
+					.hrp_res_req_dscp = 7,
+					.coll_leaf_res_req_dscp = -1,
+					.restricted_unres_req_dscp = 30,
+				},
+				.ixe_settings = {
+					.fq_count = 8,
+				},
+				.lpe_settings = {
+					.fq_count = 4,
+				},
+				.pct_settings = {
+					.trs_rsvd = 4,
+					.mst_rsvd = 4,
+					.tct_rsvd = 16,
+				},
+				.oxe_settings = {
+					.smt_rsvd = 4,
+					.sct_rsvd = 4,
+					.pbuf_rsvd = 13,
+					.assured_percent = 10, /* Fabric: 40 */
+					.ceiling_percent = 100,
+					.bucket_limit = DIV_ROUND_UP(2 * PORTALS_MAX_FRAME_SIZE, 1024),
+					.leaf_request_priority = 2,
+					.leaf_response_priority = 1,
+					.branch_priority = 1,
+					.mfs_index = 0,
+				},
+				.cq_settings = {
+					.dynamic_fq_count = 8,
+					.static_fq_count = 16,
+					.fq_buf_reserved = 32,
+					.pfq_high_thresh = 64,
+				},
+				.hni_settings = {
+					.pbuf_rsvd = 17,
+					.mfs = PORTALS_MAX_FRAME_SIZE,
+				},
+			},
+			[CXI_TC_ETH] = {
+				.oxe_settings = {
+					.spt_rsvd = 30,
+					.pbuf_rsvd = DIV_ROUND_UP(ETHERNET_MAX_FRAME_SIZE, 256),
+				},
+				.cq_settings = {
+					.dynamic_fq_count = 2,
+					.static_fq_count = 2,
+					.fq_buf_reserved = 32,
+					.pfq_high_thresh = 64,
+				},
+				.hni_settings = {
+					.pbuf_rsvd = DIV_ROUND_UP(ETHERNET_MAX_FRAME_SIZE, 128),
+					.mfs = ETHERNET_MAX_FRAME_SIZE,
+				},
+
+			},
+			[CXI_ETH_SHARED] = {
+				.oxe_settings = {
+					.assured_percent = 0,
+					.ceiling_percent = 100,
+					.bucket_limit = DIV_ROUND_UP(2 * ETHERNET_MAX_FRAME_SIZE, 1024),
+					.leaf_request_priority = 2,
+					.branch_priority = 1,
+					.mfs_index = 1,
+				},
+			},
+			[CXI_ETH_TC1] = {
+				.eth_settings = {
+					.pcp =  6,
+				},
+				.oxe_settings = {
+					.assured_percent = 10, /* Fabric: 25 */
+					.ceiling_percent = 100,
+					.bucket_limit = DIV_ROUND_UP(2 * ETHERNET_MAX_FRAME_SIZE, 1024),
+					.leaf_request_priority = 2,
+					.branch_priority = 1,
+					.mfs_index = 1,
+				},
+
+			},
+			[CXI_ETH_TC2] = {
+				.eth_settings = {
+					.pcp =  2,
+				},
+				.oxe_settings = {
+					.assured_percent = 10, /* Fabric: 13 */
+					.ceiling_percent = 100,
+					.bucket_limit = DIV_ROUND_UP(2 * ETHERNET_MAX_FRAME_SIZE, 1024),
+					.leaf_request_priority = 2,
+					.branch_priority = 1,
+					.mfs_index = 1,
+				},
+
+			},
+
+		},
+	}
+
+};
+
+/* Handle any non hardcoded QoS limits.
+ * Sharing SRB space for example depends on the number of RDMA TCs
+ * that need to sustain max bandwidth and whether or not a C1/C2 dev is in use.
+ */
+void cxi_qos_calculate_limits(struct qos_profile *qos, bool is_c2)
+{
+	unsigned int tc;
+	unsigned int num_active_tcs = 0;
+	unsigned int srb_rsvd;
+
+	/* Count active TCs that need dynamically calculated SRB.
+	 * LOW_LATENCY has an explicit srb_rsvd value and should not be
+	 * counted or overwritten.
+	 */
+	for (tc = 0; tc < CXI_TC_MAX; tc++) {
+		if (!qos->tcs_active[tc])
+			continue;
+		if (tc == CXI_TC_LOW_LATENCY)
+			continue;
+		num_active_tcs++;
+	}
+
+	/* Each active TC needs to sustain max bandwidth.
+	 * Divide up the non-shared srb space between them.
+	 */
+	if (is_c2)
+		srb_rsvd = C2_SRB_RESERVED / num_active_tcs;
+	else
+		srb_rsvd = C1_SRB_RESERVED / num_active_tcs;
+
+	for (tc = 0; tc < CXI_TC_MAX; tc++) {
+		if (!qos->tcs_active[tc])
+			continue;
+
+		/* Skip LOW_LATENCY TC - it has an explicit srb_rsvd value set
+		 * in the QoS profile.
+		 */
+		if (tc == CXI_TC_LOW_LATENCY)
+			continue;
+
+		qos->tcs[tc].oxe_settings.srb_rsvd = srb_rsvd;
+	}
+}
diff --git a/drivers/net/ethernet/hpe/ss1/cxi_rgroup.c b/drivers/net/ethernet/hpe/ss1/cxi_rgroup.c
new file mode 100644
index 000000000000..fe0e19ab4875
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cxi_rgroup.c
@@ -0,0 +1,1791 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2024 Hewlett Packard Enterprise Development LP */
+
+/* Resource Groups */
+
+#include "cass_core.h"
+#include <linux/sched.h>
+#include <linux/nsproxy.h>
+#include <net/net_namespace.h>
+
+/**
+ * get_cass_dev() - type-safe function to get Cassini device pointer
+ *                  from cxi_dev
+ *
+ * @dev: cxi_dev pointer
+ *
+ * Return: containing Cassini device pointer
+ */
+static struct cass_dev *get_cass_dev(struct cxi_dev *dev)
+{
+	return container_of(dev, struct cass_dev, cdev);
+}
+
+/* **************************************************************** */
+/* Rgroup list operations                                           */
+/* **************************************************************** */
+
+static struct xa_limit   rgroup_id_limits = RGROUP_ID_LIMITS;
+
+/**
+ * cxi_dev_lock_rgroup_list() - take the device lock for rgroups
+ *
+ * @hw: Cassini device
+ */
+void cxi_dev_lock_rgroup_list(struct cass_dev *hw)
+	__acquires(&hw->rgroup_list.xarray.xa_lock)
+{
+	xa_lock_nested(&hw->rgroup_list.xarray, SINGLE_DEPTH_NESTING);
+}
+
+/**
+ * cxi_dev_unlock_rgroup_list() - release the device lock for rgroups
+ *
+ * @hw: Cassini device
+ */
+void cxi_dev_unlock_rgroup_list(struct cass_dev *hw)
+	__releases(&hw->rgroup_list.xarray.xa_lock)
+{
+	xa_unlock(&hw->rgroup_list.xarray);
+}
+
+/**
+ * rgroup_list_insert_rgroup() - Insert Resource Group
+ *                                   into device list
+ *
+ * @list: rgroup list pointer
+ * @rgroup: address of rgroup
+ * @id: location to store ID if successful
+ *
+ * Return:
+ * * 0       - success
+ * * -ENOMEM - memory could not be allocated
+ * * -EBUSY  - no free entries available
+ */
+static int rgroup_list_insert_rgroup(struct cxi_rgroup_list *list,
+				     struct cxi_rgroup *rgroup,
+				     unsigned int *id)
+{
+	if (*id)
+		return xa_insert(&list->xarray, *id, rgroup, RGROUP_GFP_OPTS);
+
+	return xa_alloc(&list->xarray, id, rgroup,
+			rgroup_id_limits, RGROUP_GFP_OPTS);
+}
+
+/**
+ * rgroup_list_retrieve_rgroup() - Get Resource Group pointer from list
+ *                                 by id
+ *
+ * @list: rgroup list pointer
+ * @id: desired id
+ * @rgroup: location to store address of rgroup
+ *
+ * Return:
+ * * 0       - success
+ * * -EBADR  - rgroup with desired id not found
+ */
+static int rgroup_list_retrieve_rgroup(struct cxi_rgroup_list *list,
+				       unsigned int id,
+				       struct cxi_rgroup **rgroup)
+{
+	struct cxi_rgroup   *found_rgroup;
+	int    ret;
+
+	found_rgroup = xa_load(&list->xarray, id);
+
+	if (!found_rgroup)
+		return -EBADR;
+
+	ret = xa_err(found_rgroup);
+	if (ret)
+		return ret;
+
+	*rgroup = found_rgroup;
+	return 0;
+}
+
+/**
+ * rgroup_list_remove_rgroup() - delete rgroup from device list
+ *
+ * @list: rgroup list pointer
+ * @rgroup: rgroup pointer
+ *
+ * Return:
+ * * 0       - success
+ * * -EBADR  - rgroup not in device list
+ */
+static int rgroup_list_remove_rgroup(struct cxi_rgroup_list *list,
+				     struct cxi_rgroup *rgroup)
+	__must_hold(&list->xarray.xa_lock)
+{
+	struct cxi_rgroup   *old_value = __xa_erase(&list->xarray, rgroup->id);
+
+	return (old_value == rgroup) ? 0 : -EBADR;
+}
+
+/**
+ * rgroup_list_iterate() - Call a function on each rgroup in the list
+ *
+ * @list: rgroup list pointer
+ * @operator: the function to call
+ * @user_data: second argument to operator function
+ *
+ * Note: iteration stops on non-zero return from operator()
+ *
+ * Return: first non-zero return value of operator or 0
+ */
+static int rgroup_list_iterate(struct cxi_rgroup_list *list,
+			       int (*operator)(struct cxi_rgroup *rgroup,
+					       void *user_data),
+			       void *user_data)
+{
+	struct cxi_rgroup   *rgroup;
+	unsigned long       index = rgroup_id_limits.min;
+
+	xa_for_each(&list->xarray, index, rgroup) {
+		int ret = (*operator)(rgroup, user_data);
+
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+/* **************************************************************** */
+/* Resource Entry operations                                        */
+/* **************************************************************** */
+
+static struct xa_limit  resource_entry_id_limits = RESOURCE_ENTRY_ID_LIMITS;
+
+/**
+ * resource_entry_list_init() - configure the list of resource entries
+ *
+ * @list: list pointer
+ */
+static void resource_entry_list_init(struct cxi_resource_entry_list *list)
+{
+	xa_init_flags(&list->xarray, RESOURCE_ENTRY_XARRAY_FLAGS);
+}
+
+/**
+ * resource_entry_list_lock() - lock the list
+ *
+ * @list: list pointer
+ */
+static void resource_entry_list_lock(struct cxi_resource_entry_list *list)
+	__acquires(&list->xarray.xa_lock)
+{
+	xa_lock(&list->xarray);
+}
+
+/**
+ * resource_entry_list_unlock() - unlock the list
+ *
+ * @list: list pointer
+ */
+static void resource_entry_list_unlock(struct cxi_resource_entry_list *list)
+	__releases(&list->xarray.xa_lock)
+{
+	xa_unlock(&list->xarray);
+}
+
+/**
+ * resource_entry_list_destroy() - remove all resource entries and free
+ *                                 list
+ *
+ * @rgroup: rgroup pointer
+ */
+static void resource_entry_list_destroy(struct cxi_rgroup *rgroup)
+{
+	struct cxi_resource_entry *resource_entry;
+	unsigned long index = resource_entry_id_limits.min;
+	struct cxi_resource_entry_list *list = &rgroup->resource_entry_list;
+
+	resource_entry_list_lock(list);
+
+	xa_for_each(&list->xarray, index, resource_entry) {
+		cass_rgroup_remove_resource(rgroup, resource_entry);
+		__xa_erase(&list->xarray, resource_entry->type);
+		kfree(resource_entry);
+	}
+
+	resource_entry_list_unlock(list);
+
+	xa_destroy(&list->xarray);
+}
+
+/**
+ * resource_entry_list_retrieve_resource_entry() - Get the Resource Entry
+ *          pointer for a given type from the list, if it exists.
+ *
+ * @list: the list pointer
+ * @type: the type to retrieve
+ * @resource_entry: location to store Resource Entry pointer
+ *
+ * Return:
+ * * 0      - success
+ * * -EBADR  - No Resource Entry with given type found
+ */
+static int
+resource_entry_list_retrieve_resource_entry(struct cxi_resource_entry_list *list,
+					    enum cxi_resource_type type,
+					    struct cxi_resource_entry **resource_entry)
+{
+	*resource_entry = xa_load(&list->xarray, type);
+
+	return (*resource_entry) ? 0 : -EBADR;
+}
+
+/**
+ * resource_entry_list_iterate() - call a function for each entry in the list
+ *
+ * @list: the list pointer
+ * @operator: function to call for each list element
+ * @user_data: second argument to operator function
+ *
+ * Note: iteration is discontinued with a non-zero return from 'operator'.
+ *
+ * Return: first non-zero return from operator or 0.
+ */
+static int
+resource_entry_list_iterate(struct cxi_resource_entry_list *list,
+			    int (*operator)(struct cxi_resource_entry *entry,
+					    void *user_data),
+			    void *user_data)
+{
+	struct cxi_resource_entry   *resource_entry;
+	unsigned long               index = resource_entry_id_limits.min;
+
+	xa_for_each(&list->xarray, index, resource_entry) {
+		int ret = (*operator)(resource_entry, user_data);
+
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+/**
+ * validate_resource_type() - test type and limits for acceptable values
+ *
+ * @type: resource type to validate
+ *
+ * Return: true if recognized type value, false otherwise.
+ */
+static bool validate_resource_type(unsigned int type)
+{
+	switch (type) {
+	case CXI_RESOURCE_PTLTE:
+	case CXI_RESOURCE_TXQ:
+	case CXI_RESOURCE_TGQ:
+	case CXI_RESOURCE_EQ:
+	case CXI_RESOURCE_CT:
+	case CXI_RESOURCE_PE0_LE:
+	case CXI_RESOURCE_PE1_LE:
+	case CXI_RESOURCE_PE2_LE:
+	case CXI_RESOURCE_PE3_LE:
+	case CXI_RESOURCE_TLE:
+	case CXI_RESOURCE_AC:
+		break;
+	default:
+		return false;
+	}
+
+	return true;
+}
+
+static bool validate_resource_limits(const struct cass_dev *hw,
+				     unsigned int type,
+				     const struct cxi_resource_limits *limits)
+{
+	if (!validate_resource_type(type))
+		return false;
+
+	/* TODO: actually validate limits based on type */
+
+	return true;
+}
+
+static bool validate_resource_entry(const struct cxi_resource_entry *entry)
+{
+	return validate_resource_limits(entry->rgroup->hw,
+					entry->type,
+					&entry->limits);
+}
+
+/**
+ * resource_entry_list_add_resource_entry() - add a resource entry to the list
+ *
+ * @list: resource entry list
+ * @entry: pointer to entry to add
+ *
+ * Return:
+ * * 0        - success
+ * * -EEXIST - resource with given type already exists
+ * * -ENOMEM - allocation error
+ */
+static int
+resource_entry_list_add_resource_entry(struct cxi_resource_entry_list *list,
+				       struct cxi_resource_entry *entry)
+{
+	int     ret;
+
+	if (!validate_resource_entry(entry))
+		return -EINVAL;
+
+	ret = xa_insert(&list->xarray, entry->type, entry,
+			RESOURCE_ENTRY_GFP_OPTS);
+
+	switch (ret) {
+	case -EBUSY:
+		return -EEXIST;
+	default:
+		return ret;
+	}
+}
+
+/**
+ * resource_entry_list_delete_resource_entry() - remove a resource entry
+ *                                               from the list
+ *
+ * @list: pointer to list
+ * @resource_entry: pointer to resource entry
+ *
+ * Return:
+ * * 0       - success
+ * * -EBADR  - resource entry not found in list
+ */
+static int
+resource_entry_list_delete_resource_entry(struct cxi_resource_entry_list *list,
+					  struct cxi_resource_entry *resource_entry)
+	__must_hold(&list->xarray.xa_lock)
+{
+	struct cxi_resource_entry    *old;
+	int    ret;
+
+	/* It's possible for the entry to change before the lock
+	 * was taken.  So we need to make sure we delete
+	 * the right one.
+	 */
+
+	old = __xa_erase(&list->xarray, resource_entry->type);
+
+	ret = (old == resource_entry) ? 0 : -EBADR;
+
+	if (ret) {
+		/* If it's changed, we erased the wrong entry, so
+		 * put it back.
+		 */
+		__xa_store(&list->xarray, old->type, old,
+			   RESOURCE_ENTRY_GFP_OPTS);
+	}
+
+	return ret;
+}
+
+/* **************************************************************** */
+/* Rgroup operations                                                */
+/* **************************************************************** */
+
+/**
+ * validate_rgroup_attr() - test attributes for useability
+ *
+ * @dev: CXI device pointer
+ * @attr: pointer to attributes
+ *
+ * Return:
+ * * 0        - success
+ */
+static int validate_rgroup_attr(const struct cxi_dev *dev,
+				const struct cxi_rgroup_attr *attr)
+{
+	/* TODO: really validate attributes */
+
+	return 0;
+}
+
+/**
+ * rgroup_init() - initialize a newly created rgroup
+ *
+ * @dev: CXI device that rgroup belongs to
+ * @rgroup: rgroup pointer
+ * @attr: desired attributes for rgroup
+ *
+ * Return:
+ * * 0       - success
+ * * -EINVAL - invalid dev, rgroup or attr pointer
+ */
+static void rgroup_init(struct cxi_dev *dev,
+			struct cxi_rgroup *rgroup,
+			const struct cxi_rgroup_attr *attr)
+{
+	int i;
+
+	for (i = 0; i < C_PE_COUNT; i++)
+		rgroup->pools.le_pool_id[i] = -1;
+
+	rgroup->pools.tle_pool_id = -1;
+	rgroup->attr.lnis_per_rgid = CXI_DEFAULT_LNIS_PER_RGID;
+
+	if (attr)
+		rgroup->attr = *attr;
+
+	rgroup->hw = get_cass_dev(dev);
+	rgroup->state.enabled = false;
+	refcount_set(&rgroup->state.refcount, 1);
+	resource_entry_list_init(&rgroup->resource_entry_list);
+	cxi_ac_entry_list_init(&rgroup->ac_entry_list);
+}
+
+static int resource_busy(struct cxi_resource_entry *entry,
+			 void *user_data)
+{
+	return (entry->limits.in_use) ? -EBUSY : 0;
+}
+
+/**
+ * rgroup_busy() - determine if any rgroup resources are allocated
+ *
+ * @rgroup: pointer to rgroup
+ *
+ * Return:
+ * * true  - rgroup has resources allocated for it
+ * * false - no resources associated with rgroup
+ */
+static bool rgroup_busy(struct cxi_rgroup *rgroup)
+{
+	return resource_entry_list_iterate(&rgroup->resource_entry_list,
+					   resource_busy, NULL);
+}
+
+/**
+ * find_rgroup_inc_refcount() - retrieve rgroup from device by id
+ *
+ * @dev: CXI device pointer
+ * @id: id of desired Resource Group
+ * @rgroup: location to store rgroup pointer
+ *
+ * Return:
+ * * 0       - success
+ * * -EINVAL - invalid hw or rgroup pointers
+ * * -EBADR  - rgroup with given id not found
+ *
+ * Note: returns rgroup which may be in the process of being
+ * torn down, ie, released.
+ *
+ * Use cxi_dev_find_rgroup_inc_refcount() to get only active rgroups.
+ */
+static int find_rgroup_inc_refcount(struct cxi_dev *dev,
+				    unsigned int id,
+				    struct cxi_rgroup **rgroup)
+{
+	struct cass_dev         *hw          = get_cass_dev(dev);
+	struct cxi_rgroup       *found_rgroup;
+	int    ret = 0;
+
+	cxi_dev_lock_rgroup_list(hw);
+
+	ret = rgroup_list_retrieve_rgroup(&hw->rgroup_list, id, &found_rgroup);
+	if (ret)
+		goto unlock_return;
+
+	if (!refcount_inc_not_zero(&found_rgroup->state.refcount)) {
+		ret = -EBADR;
+		goto unlock_return;
+	}
+
+	*rgroup = found_rgroup;
+
+unlock_return:
+	cxi_dev_unlock_rgroup_list(hw);
+	return ret;
+}
+
+/**
+ * rgroup_destroy() - remove resources associated with rgroup and
+ *                    free memory
+ *
+ * @rgroup: pointer to rgroup
+ */
+static void rgroup_destroy(struct cxi_rgroup *rgroup)
+{
+	cxi_ac_entry_list_destroy(&rgroup->ac_entry_list);
+	resource_entry_list_destroy(rgroup);
+	refcount_dec(&rgroup->hw->refcount);
+	kfree(rgroup);
+}
+
+/**
+ * rgroup_dec_refcount_and_destroy() - release reference to rgroup
+ *
+ * @rgroup: pointer to rgroup
+ *
+ * Return:
+ * * 0       - success
+ * * -EBUSY  - refcount decremented, resources still exist on rgroup
+ * * -EBADR  - rgroup no longer in device list
+ *
+ * Most users will want to use cxi_rgroup_dec_refcount().
+ */
+static int rgroup_dec_refcount_and_destroy(struct cxi_rgroup *rgroup)
+{
+	struct cass_dev   *hw = rgroup->hw;
+	bool   outstanding_refs;
+	int    ret = 0;
+
+	cxi_dev_lock_rgroup_list(hw);
+
+	outstanding_refs = !refcount_dec_and_test(&rgroup->state.refcount);
+
+	if (outstanding_refs || rgroup_busy(rgroup)) {
+		ret = -EBUSY;
+		goto unlock_return;
+	}
+
+	ret = rgroup_list_remove_rgroup(&hw->rgroup_list, rgroup);
+	if (!ret)
+		rgroup_destroy(rgroup);
+
+unlock_return:
+	cxi_dev_unlock_rgroup_list(hw);
+	return ret;
+}
+
+/* **************************************************************** */
+/* Rgroup API                                                       */
+/* **************************************************************** */
+
+/**
+ * cxi_rgroup_is_enabled() - Report Resource group is enabled.
+ *
+ * @rgroup: resource group pointer
+ *
+ * Return:
+ * * true    - Is enabled
+ * * false   - Is disabled
+ */
+bool cxi_rgroup_is_enabled(struct cxi_rgroup *rgroup)
+{
+	return rgroup->state.enabled;
+}
+
+/**
+ * cxi_rgroup_enable() - Mark a Resource group as enabled.
+ *
+ * @rgroup: resource group pointer
+ */
+void cxi_rgroup_enable(struct cxi_rgroup *rgroup)
+{
+	cxi_dev_lock_rgroup_list(rgroup->hw);
+
+	rgroup->state.enabled = true;
+
+	cxi_dev_unlock_rgroup_list(rgroup->hw);
+}
+EXPORT_SYMBOL(cxi_rgroup_enable);
+
+/**
+ * cxi_rgroup_disable() - Mark a Resource group as disabled.
+ *
+ * @rgroup: resource group pointer
+ */
+void cxi_rgroup_disable(struct cxi_rgroup *rgroup)
+{
+	cxi_dev_lock_rgroup_list(rgroup->hw);
+
+	rgroup->state.enabled = false;
+
+	cxi_dev_unlock_rgroup_list(rgroup->hw);
+}
+EXPORT_SYMBOL(cxi_rgroup_disable);
+
+/**
+ * cxi_rgroup_id() - Get the rgroup id
+ *
+ * @rgroup: resource group pointer
+ *
+ * Return: ID of rgroup
+ */
+unsigned int cxi_rgroup_id(const struct cxi_rgroup *rgroup)
+{
+	return rgroup->id;
+}
+EXPORT_SYMBOL(cxi_rgroup_id);
+
+/**
+ * cxi_rgroup_name() - Get the rgroup name
+ *
+ * @rgroup: resource group pointer
+ */
+char *cxi_rgroup_name(struct cxi_rgroup *rgroup)
+{
+	return rgroup->attr.name;
+}
+EXPORT_SYMBOL(cxi_rgroup_name);
+
+/**
+ * cxi_rgroup_le_pool_id() - Get the rgroup le_pool_id at index
+ *
+ * @rgroup: resource group pointer
+ * @index: pool array index
+ *
+ * Return: LE pool id value
+ */
+int cxi_rgroup_le_pool_id(const struct cxi_rgroup *rgroup, int index)
+{
+	return rgroup->pools.le_pool_id[index];
+}
+
+/**
+ * cxi_rgroup_tle_pool_id() - Get the rgroup tle_pool_id
+ *
+ * @rgroup: resource group pointer
+ *
+ * Return: TLE pool id value
+ */
+int cxi_rgroup_tle_pool_id(const struct cxi_rgroup *rgroup)
+{
+	return rgroup->pools.tle_pool_id;
+}
+
+/**
+ * cxi_rgroup_cntr_pool_id() - Get the rgroup cntr_pool_id attribute
+ *
+ * @rgroup: resource group pointer
+ *
+ * Return: cntr_pool_id value
+ */
+unsigned int cxi_rgroup_cntr_pool_id(const struct cxi_rgroup *rgroup)
+{
+	return rgroup->attr.cntr_pool_id;
+}
+
+/**
+ * cxi_rgroup_system_service() - Get the rgroup system_service attribute
+ *
+ * @rgroup: resource group pointer
+ *
+ * Return: system_service value
+ */
+bool cxi_rgroup_system_service(const struct cxi_rgroup *rgroup)
+{
+	return rgroup->attr.system_service;
+}
+
+/**
+ * cxi_rgroup_lnis_per_rgid() - Get the rgroup lnis_per_rgid
+ *
+ * @rgroup: resource group pointer
+ *
+ * Return: the lnis_per_rgid value
+ */
+unsigned int cxi_rgroup_lnis_per_rgid(const struct cxi_rgroup *rgroup)
+{
+	return rgroup->attr.lnis_per_rgid;
+}
+
+/**
+ * cxi_rgroup_refcount() - Get the rgroup refcount
+ *
+ * @rgroup: resource group pointer
+ *
+ * Return: the refcount value
+ */
+int cxi_rgroup_refcount(const struct cxi_rgroup *rgroup)
+{
+	return refcount_read(&rgroup->state.refcount);
+}
+
+/**
+ * cxi_rgroup_set_lnis_per_rgid_compat() - Set the rgroup lnis_per_rgid
+ *
+ * For compatibility with the "old" service api, don't check if rgroup
+ * is enabled.
+ *
+ * @rgroup: resource group pointer
+ * @lnis_per_rgid: Value to set
+ */
+void cxi_rgroup_set_lnis_per_rgid_compat(struct cxi_rgroup *rgroup,
+					 int lnis_per_rgid)
+{
+	rgroup->attr.lnis_per_rgid = lnis_per_rgid;
+}
+
+/**
+ * cxi_rgroup_set_lnis_per_rgid() - Set the rgroup lnis_per_rgid
+ *
+ * @rgroup: resource group pointer
+ * @lnis_per_rgid: Value to set
+ *
+ * Return: 0 - success, -EBUSY if not enabled
+ */
+int cxi_rgroup_set_lnis_per_rgid(struct cxi_rgroup *rgroup, int lnis_per_rgid)
+{
+	if (cxi_rgroup_is_enabled(rgroup))
+		return -EBUSY;
+
+	cxi_rgroup_set_lnis_per_rgid_compat(rgroup, lnis_per_rgid);
+
+	return 0;
+}
+EXPORT_SYMBOL(cxi_rgroup_set_lnis_per_rgid);
+
+/**
+ * cxi_rgroup_set_cntr_pool_id() - Set the rgroup cntr_pool_id
+ *
+ * @rgroup: resource group pointer
+ * @cntr_pool_id: Value to set
+ *
+ * Return: 0 - success, -EBUSY if not enabled
+ */
+int cxi_rgroup_set_cntr_pool_id(struct cxi_rgroup *rgroup, int cntr_pool_id)
+{
+	if (cxi_rgroup_is_enabled(rgroup))
+		return -EBUSY;
+
+	rgroup->attr.cntr_pool_id = cntr_pool_id;
+
+	return 0;
+}
+EXPORT_SYMBOL(cxi_rgroup_set_cntr_pool_id);
+
+/**
+ * cxi_rgroup_set_system_service() - Set the rgroup system_service
+ *
+ * @rgroup: resource group pointer
+ * @system_service: Value to set
+ *
+ * Return: 0 - success, -EBUSY if not enabled
+ */
+int cxi_rgroup_set_system_service(struct cxi_rgroup *rgroup, bool system_service)
+{
+	if (cxi_rgroup_is_enabled(rgroup))
+		return -EBUSY;
+
+	rgroup->attr.system_service = system_service;
+
+	return 0;
+}
+EXPORT_SYMBOL(cxi_rgroup_set_system_service);
+
+/**
+ * cxi_rgroup_set_name() - Set the rgroup name
+ *
+ * @rgroup: resource group pointer
+ * @name: name string
+ *
+ * Return: 0 - success, -EBUSY if not enabled
+ */
+int cxi_rgroup_set_name(struct cxi_rgroup *rgroup, char *name)
+{
+	if (cxi_rgroup_is_enabled(rgroup))
+		return -EBUSY;
+
+	strscpy(rgroup->attr.name, name, ARRAY_SIZE(rgroup->attr.name));
+
+	return 0;
+}
+EXPORT_SYMBOL(cxi_rgroup_set_name);
+
+/**
+ * cxi_rgroup_get_info() - retrieve the attr and state of a resource group
+ *
+ * @rgroup: rgroup pointer
+ * @attr: location to store attributes
+ * @state: location to store state
+ *
+ * Note: attr and/or state may be NULL.
+ */
+void cxi_rgroup_get_info(struct cxi_rgroup *rgroup,
+			 struct cxi_rgroup_attr *attr,
+			 struct cxi_rgroup_state *state)
+{
+	if (attr) {
+		attr->id = rgroup->id;
+		attr->cntr_pool_id   = rgroup->attr.cntr_pool_id;
+		attr->system_service = rgroup->attr.system_service;
+		strscpy(attr->name, rgroup->attr.name, ARRAY_SIZE(attr->name));
+	}
+
+	if (state) {
+		state->enabled  = rgroup->state.enabled;
+		state->refcount = rgroup->state.refcount;
+	}
+}
+EXPORT_SYMBOL(cxi_rgroup_get_info);
+
+/**
+ * cxi_rgroup_valid_user() - Verify user is has permission to use rgroup
+ *
+ * @rgroup: resource group pointer
+ *
+ * Return:
+ * * true if user has permission
+ */
+bool cxi_rgroup_valid_user(struct cxi_rgroup *rgroup)
+{
+	unsigned int ac_entry_id;
+	unsigned int netns = CURRENT_NETNS_ID();
+	uid_t uid = __kuid_val(current_euid());
+	gid_t gid = __kgid_val(current_egid());
+
+	return !cxi_rgroup_get_ac_entry_by_user(rgroup, uid, gid, netns,
+						CXI_AC_ANY, &ac_entry_id);
+}
+
+/**
+ * cxi_rgroup_add_resource() - add a resource to this resource group
+ *
+ * @rgroup: resource group pointer
+ * @type: resource type to add
+ * @limits: parameters of the resource
+ *
+ * Return:
+ * * 0       - success
+ * * -ENOMEM - unable to allocate memory for resources
+ * * -EEXIST - resource already exists within group
+ * * -EBUSY  - rgroup is enabled
+ * * -ENOSPC - No space to add resource
+ * * -EBADR  - Failed to allocate an LE or TLE pool
+ */
+int cxi_rgroup_add_resource(struct cxi_rgroup *rgroup,
+			    enum cxi_resource_type type,
+			    const struct cxi_resource_limits *limits)
+{
+	struct cxi_resource_entry_list   *list = &rgroup->resource_entry_list;
+	struct cxi_resource_entry        *resource_entry;
+	int    ret;
+
+	if (cxi_rgroup_is_enabled(rgroup))
+		return -EBUSY;
+
+	if (!validate_resource_limits(rgroup->hw, type, limits))
+		return -EINVAL;
+
+	/* Allocate a new one */
+	resource_entry = kzalloc(sizeof(*resource_entry),
+				 RESOURCE_ENTRY_GFP_OPTS);
+	if (!resource_entry)
+		return -ENOMEM;
+
+	resource_entry->rgroup = rgroup;
+	resource_entry->type   = type;
+	resource_entry->limits = *limits;
+	resource_entry->limits.in_use = 0;
+
+	/* Try to insert into the list */
+	ret = resource_entry_list_add_resource_entry(list, resource_entry);
+	if (ret) {
+		kfree(resource_entry);
+		return ret;
+	}
+
+	ret = cass_rgroup_add_resource(rgroup, resource_entry);
+	if (!ret)
+		return 0;
+
+	resource_entry_list_lock(list);
+	resource_entry_list_delete_resource_entry(list, resource_entry);
+	resource_entry_list_unlock(list);
+	kfree(resource_entry);
+
+	return ret;
+}
+EXPORT_SYMBOL(cxi_rgroup_add_resource);
+
+void cxi_rgroup_free_resource(struct cxi_rgroup *rgroup,
+			      enum cxi_resource_type type)
+{
+	int rc;
+	struct cxi_resource_entry *entry;
+
+	rc = cxi_rgroup_get_resource_entry(rgroup, type, &entry);
+	if (rc) {
+		pr_warn("Failed to get resource_entry rc:%d\n", rc);
+		return;
+	}
+
+	cass_free_resource(rgroup, entry);
+}
+
+int cxi_rgroup_alloc_resource(struct cxi_rgroup *rgroup,
+			      enum cxi_resource_type type)
+{
+	int rc;
+	struct cxi_resource_entry *entry;
+
+	if (!cxi_rgroup_is_enabled(rgroup))
+		return -EKEYREVOKED;
+
+	rc = cxi_rgroup_get_resource_entry(rgroup, type, &entry);
+	if (rc) {
+		pr_debug("Failed to get resource_entry rc:%d\n", rc);
+		return rc;
+	}
+
+	return cass_alloc_resource(rgroup, entry);
+}
+
+/**
+ * cxi_rgroup_delete_resource() - remove a resource from a group
+ *
+ * @rgroup: resource group pointer
+ * @type: resource type to remove
+ *
+ * Return:
+ * * 0        - success
+ * * -EBUSY   - resource group unavailable
+ * * -ENODATA - resource does not exist within group
+ */
+int cxi_rgroup_delete_resource(struct cxi_rgroup *rgroup,
+			       enum cxi_resource_type type)
+{
+	struct cxi_resource_entry_list  *list = &rgroup->resource_entry_list;
+	struct cxi_resource_entry       *resource_entry;
+	int    ret;
+
+	if (cxi_rgroup_is_enabled(rgroup))
+		return -EBUSY;
+
+	resource_entry_list_lock(list);
+
+	ret = resource_entry_list_retrieve_resource_entry(list, type,
+							  &resource_entry);
+	if (ret || !resource_entry) {
+		ret = -ENODATA;
+		goto unlock_return;
+	}
+
+	ret = cass_rgroup_remove_resource(rgroup, resource_entry);
+	if (ret)
+		goto unlock_return;
+
+	resource_entry_list_delete_resource_entry(list, resource_entry);
+	kfree(resource_entry);
+
+unlock_return:
+	resource_entry_list_unlock(list);
+	return ret;
+}
+EXPORT_SYMBOL(cxi_rgroup_delete_resource);
+
+/**
+ * cxi_rgroup_get_resource_entry() - retrieve a resource entry
+ *
+ * @rgroup: resource group pointer
+ * @type: resource type to retrieve parameters for
+ * @entry: the resource entry
+ *
+ * Returns:
+ * 0: success
+ * * -EINVAL  - bad rgroup pointer
+ * * -EINVAL  - invalid limits value
+ * * -ENOENT  - resource not found within group
+ */
+int cxi_rgroup_get_resource_entry(struct cxi_rgroup *rgroup,
+				  enum cxi_resource_type type,
+				  struct cxi_resource_entry **entry)
+{
+	struct cxi_resource_entry_list *list = &rgroup->resource_entry_list;
+
+	return resource_entry_list_retrieve_resource_entry(list, type, entry);
+}
+
+/**
+ * cxi_rgroup_get_resource() - retrieve limits for a resource
+ *                             The TLE in_use needs to be read from hw.
+ *
+ * @rgroup: resource group pointer
+ * @type: resource type to retrieve parameters for
+ * @limits: location to store resource parameters
+ *
+ * Return:
+ * 0: success
+ * * -ENODATA - resource not found within group
+ */
+int cxi_rgroup_get_resource(struct cxi_rgroup *rgroup,
+			    enum cxi_resource_type type,
+			    struct cxi_resource_limits *limits)
+{
+	struct cxi_resource_entry  *resource_entry;
+	int    ret;
+
+	ret = resource_entry_list_retrieve_resource_entry(&rgroup->resource_entry_list,
+							  type, &resource_entry);
+
+	if (ret || !resource_entry)
+		return -ENODATA;
+
+	if (type == CXI_RESOURCE_TLE)
+		cass_get_tle_in_use(rgroup, resource_entry);
+
+	*limits = resource_entry->limits;
+
+	return 0;
+}
+EXPORT_SYMBOL(cxi_rgroup_get_resource);
+
+struct resource_types_data {
+	size_t         max_types;
+	unsigned int   *types;
+	size_t         num_types;
+};
+
+static int get_types_operator(struct cxi_resource_entry *resource_entry,
+			      void *user_data)
+{
+	struct resource_types_data    *data = user_data;
+
+	if (data->num_types < data->max_types) {
+		*data->types = resource_entry->type;
+		data->types++;
+	}
+
+	data->num_types++;
+	return 0;
+}
+
+/**
+ * cxi_rgroup_get_resource_types() - Retrieve list of resource within a group
+ *
+ * @rgroup: resource group pointer
+ * @max_resources: size of the resource_types array
+ * @resource_types: User allocated array to store type values
+ * @num_resources: On success, number of valid entries in resource_types array
+ * On -ENOSPC, value of max_resources needed to retrieve all values
+ *
+ * Return:
+ * * 0       - success
+ * * -ENOSPC - max_resources is not large enough
+ */
+int cxi_rgroup_get_resource_types(struct cxi_rgroup *rgroup,
+				  size_t max_resources,
+				  enum cxi_resource_type *resource_types,
+				  size_t *num_resources)
+{
+	struct resource_types_data  data = {
+		.max_types = max_resources,
+		.types     = resource_types,
+		.num_types = 0,
+	};
+	int    ret = resource_entry_list_iterate(&rgroup->resource_entry_list,
+						 get_types_operator, &data);
+
+	if (ret)
+		return ret;
+
+	*num_resources = data.num_types;
+	return (*num_resources > max_resources) ? -ENOSPC : 0;
+}
+EXPORT_SYMBOL(cxi_rgroup_get_resource_types);
+
+/**
+ * cxi_rgroup_add_ac_entry() - Add access control entry to resource group
+ *
+ * @rgroup: resource group pointer
+ * @type: type of the access control entry
+ * @data: access control parameters
+ * @ac_entry_id: location to store id of access control entry
+ *
+ * Return:
+ * * 0       - success
+ * * -EBADR  - invalid type value
+ * * -ENOMEM - unable to allocate memory for request
+ * * -EEXIST - access control entry already exists
+ * * -EBUSY  - rgroup is enabled
+ */
+int cxi_rgroup_add_ac_entry(struct cxi_rgroup *rgroup,
+			    enum cxi_ac_type type,
+			    const union cxi_ac_data *data,
+			    unsigned int *ac_entry_id)
+{
+	if (cxi_rgroup_is_enabled(rgroup))
+		return -EBUSY;
+
+	return cxi_ac_entry_list_insert(&rgroup->ac_entry_list,
+					type, data, ac_entry_id);
+}
+EXPORT_SYMBOL(cxi_rgroup_add_ac_entry);
+
+/**
+ * cxi_rgroup_update_ac_entry() - Add a new AC type to resource group
+ *
+ * The new AC type can be added only when rgroup is not enabled
+ *
+ * @rgroup: resource group pointer
+ * @type: type of the access control entry
+ * @data: access control parameters
+ * @ac_entry_id: location to store id of access control entry
+ *
+ * Return:
+ * * 0       - success
+ * * -EBADR  - invalid type value
+ * * -ENOMEM - unable to allocate memory for request
+ * * -EEXIST - access control entry already exists
+ * * -EBUSY  - rgroup is enabled
+ */
+int cxi_rgroup_update_ac_entry(struct cxi_rgroup *rgroup,
+			       enum cxi_ac_type type,
+			       const union cxi_ac_data *data,
+			       unsigned int *ac_entry_id)
+{
+	if (cxi_rgroup_is_enabled(rgroup))
+		return -EBUSY;
+
+	return cxi_ac_entry_list_insert(&rgroup->ac_entry_list,
+					type, data, ac_entry_id);
+}
+EXPORT_SYMBOL(cxi_rgroup_update_ac_entry);
+
+/**
+ * cxi_rgroup_delete_ac_entry() - remove an access control entry from a
+ * resource group
+ *
+ * @rgroup: resource group pointer
+ * @ac_entry_id: id of the access control entry
+ *
+ * Return:
+ * * 0        - success
+ * * -ENODATA - access control entry does not exist
+ * * -EBUSY  - rgroup is enabled
+ */
+int cxi_rgroup_delete_ac_entry(struct cxi_rgroup *rgroup,
+			       unsigned int ac_entry_id)
+{
+	if (cxi_rgroup_is_enabled(rgroup))
+		return -EBUSY;
+
+	return cxi_ac_entry_list_delete(&rgroup->ac_entry_list,
+					ac_entry_id);
+}
+EXPORT_SYMBOL(cxi_rgroup_delete_ac_entry);
+
+/**
+ * cxi_rgroup_get_ac_entry_ids() - retrieve all the access control ids for a
+ * resource group
+ *
+ * @rgroup: resource group pointer
+ * @max_ids: size of the 'ids' array
+ * @ids: User allocated array for storage of access control ids
+ * @num_ids: On success, number of valid id values in the array 'ids'.
+ * On -ENOSPC: value of max_ids required to retrieve all the values.
+ *
+ * Return:
+ * * 0       - success
+ * * -ENOSPC - max_ids is not large enough
+ */
+int cxi_rgroup_get_ac_entry_ids(struct cxi_rgroup *rgroup,
+				size_t max_ids,
+				unsigned int *ids,
+				size_t *num_ids)
+{
+	return cxi_ac_entry_list_get_ids(&rgroup->ac_entry_list,
+					 max_ids, ids, num_ids);
+}
+EXPORT_SYMBOL(cxi_rgroup_get_ac_entry_ids);
+
+/**
+ * cxi_rgroup_get_ac_entry_data() - get the data parameters from
+ *                                  an ac_entry in the resource group
+ *
+ * @rgroup: resource group pointer
+ * @ac_entry_id: id of the access control entry to retrieve
+ * @ac_type: location to store type of entry
+ * @ac_data: location to store access control data
+ *
+ * Return:
+ * * 0        - success
+ * * -ENODATA - access control entry not found
+ */
+int cxi_rgroup_get_ac_entry_data(struct cxi_rgroup *rgroup,
+				 unsigned int ac_entry_id,
+				 enum cxi_ac_type *ac_type,
+				 union cxi_ac_data *ac_data)
+{
+	return cxi_ac_entry_list_retrieve_by_id(&rgroup->ac_entry_list,
+						ac_entry_id, ac_type, ac_data);
+}
+EXPORT_SYMBOL(cxi_rgroup_get_ac_entry_data);
+
+/**
+ * cxi_rgroup_get_ac_entry_id_by_data() - get the id of an ac entry if it exists
+ *                                        in the resource group
+ *
+ * @rgroup: resource group pointer
+ * @ac_type: the type of the entry
+ * @ac_data: the data (uid/gid) of the entry
+ * @ac_entry_id: location to store Id value
+ *
+ * Return:
+ * * 0        - success
+ * * -ENODATA - access control entry not found
+ */
+int cxi_rgroup_get_ac_entry_id_by_data(struct cxi_rgroup *rgroup,
+				       enum cxi_ac_type ac_type,
+				       const union cxi_ac_data *ac_data,
+				       unsigned int *ac_entry_id)
+{
+	return cxi_ac_entry_list_retrieve_by_data(&rgroup->ac_entry_list,
+						  ac_type, ac_data,
+						  ac_entry_id);
+}
+EXPORT_SYMBOL(cxi_rgroup_get_ac_entry_id_by_data);
+
+/**
+ * cxi_rgroup_get_ac_entry_by_user() - get an access control entry which covers the
+ *                                     given uid/gid, if any.  There may be more than
+ *                                     one possible, the priority order is:
+ *                                     OPEN, GID, UID.
+ *
+ * @rgroup: resource group pointer
+ * @uid: user id
+ * @gid: group id
+ * @netns: The Network namespace id
+ * @desired_types: bitset of types to search
+ * @ac_entry_id: location to store the id
+ *
+ * Return:
+ * * 0        - success
+ * * -ENODATA - access control entry not found
+ */
+int cxi_rgroup_get_ac_entry_by_user(struct cxi_rgroup *rgroup,
+				    uid_t uid,
+				    gid_t gid,
+				    unsigned int netns,
+				    cxi_ac_typeset_t desired_types,
+				    unsigned int *ac_entry_id)
+{
+	return cxi_ac_entry_list_retrieve_by_user(&rgroup->ac_entry_list,
+						  uid, gid, netns,
+						  desired_types, ac_entry_id);
+}
+EXPORT_SYMBOL(cxi_rgroup_get_ac_entry_by_user);
+
+/**
+ * cxi_rgroup_inc_refcount() - take a reference to an rgroup
+ *
+ * @rgroup: rgroup pointer
+ */
+void cxi_rgroup_inc_refcount(struct cxi_rgroup *rgroup)
+{
+	refcount_inc(&rgroup->state.refcount);
+}
+
+/**
+ * cxi_rgroup_dec_refcount() - release reference to rgroup
+ *
+ * @rgroup: pointer to rgroup
+ *
+ * Return:
+ * * 0       - success
+ * * -EINVAL - invalid rgroup pointer
+ */
+int cxi_rgroup_dec_refcount(struct cxi_rgroup *rgroup)
+{
+	int    ret = rgroup_dec_refcount_and_destroy(rgroup);
+
+	switch (ret) {
+	case 0:
+	case -EBUSY:
+		return 0;
+	default:
+		return ret;
+	}
+}
+EXPORT_SYMBOL(cxi_rgroup_dec_refcount);
+
+/**
+ * cxi_rgroup_ac_entry_list_destroy() - destroy the rgroup ac_entry_list
+ *
+ * @rgroup: pointer to rgroup
+ */
+void cxi_rgroup_ac_entry_list_destroy(struct cxi_rgroup *rgroup)
+{
+	cxi_ac_entry_list_destroy(&rgroup->ac_entry_list);
+}
+
+/* **************************************************************** */
+/* Device level Rgroup operations                                   */
+/* **************************************************************** */
+
+/**
+ * cxi_dev_rgroup_init() - initialize CXI device rgroup entities
+ *
+ * @dev: CXI device pointer
+ */
+void cxi_dev_rgroup_init(struct cxi_dev *dev)
+{
+	struct cass_dev    *hw = get_cass_dev(dev);
+
+	xa_init_flags(&hw->rgroup_list.xarray, RGROUP_XARRAY_FLAGS);
+}
+
+/**
+ * cxi_dev_rgroup_fini() - destroy rgroup entities in Cassini device
+ *
+ * @dev: cxi device pointer
+ */
+void cxi_dev_rgroup_fini(struct cxi_dev *dev)
+{
+	struct cass_dev    *hw = get_cass_dev(dev);
+	struct cxi_rgroup  *rgroup;
+	unsigned long id;
+
+	cxi_dev_lock_rgroup_list(hw);
+
+	for_each_rgroup(id, rgroup)
+		rgroup_destroy(rgroup);
+
+	cxi_dev_unlock_rgroup_list(hw);
+
+	xa_destroy(&hw->rgroup_list.xarray);
+}
+
+/**
+ * cxi_dev_alloc_rgroup() - Allocate a resource group
+ *
+ * @dev: Cassini Device
+ * @attr: Attributes of the Resource Group Requested
+ *
+ * Return: rgroup object on success. Else, negative errno value.
+ */
+struct cxi_rgroup *cxi_dev_alloc_rgroup(struct cxi_dev *dev,
+					const struct cxi_rgroup_attr *attr)
+{
+	struct cass_dev *hw = get_cass_dev(dev);
+	struct cxi_rgroup *rgroup;
+	int    ret;
+	unsigned int id = attr ? attr->id : 0;
+
+	ret = validate_rgroup_attr(dev, attr);
+	if (ret)
+		return ERR_PTR(ret);
+
+	rgroup = kzalloc(sizeof(struct cxi_rgroup), GFP_KERNEL);
+	if (!rgroup)
+		return ERR_PTR(-ENOMEM);
+
+	ret = rgroup_list_insert_rgroup(&hw->rgroup_list, rgroup, &id);
+	if (ret)
+		goto free_rgroup;
+	rgroup->id = id;
+
+	rgroup_init(dev, rgroup, attr);
+	refcount_inc(&hw->refcount);
+
+	return rgroup;
+
+free_rgroup:
+	kfree(rgroup);
+	return ERR_PTR(ret);
+}
+EXPORT_SYMBOL(cxi_dev_alloc_rgroup);
+
+/**
+ * cxi_dev_find_rgroup_inc_refcount() - retrieve rgroup from device by id
+ *
+ * @dev: CXI device pointer
+ * @id: id of desired Resource Group
+ * @rgroup: location to store rgroup pointer
+ *
+ * Return:
+ * * 0       - success
+ * * -EBADR  - rgroup with given id not found
+ */
+int cxi_dev_find_rgroup_inc_refcount(struct cxi_dev *dev,
+				     unsigned int id,
+				     struct cxi_rgroup **rgroup)
+{
+	struct cxi_rgroup   *found_rgroup;
+	int    ret;
+
+	ret = find_rgroup_inc_refcount(dev, id, &found_rgroup);
+	if (ret)
+		return ret;
+
+	*rgroup = found_rgroup;
+	return 0;
+}
+EXPORT_SYMBOL(cxi_dev_find_rgroup_inc_refcount);
+
+struct rgroup_id_data {
+	size_t         max_ids;
+	unsigned int   *ids;
+	size_t         num_ids;
+};
+
+static int rgroup_id_operator(struct cxi_rgroup *rgroup,
+			      void *user_data)
+{
+	struct rgroup_id_data    *data = user_data;
+
+	if (data->num_ids < data->max_ids) {
+		*data->ids = rgroup->id;
+		data->ids++;
+	}
+	data->num_ids++;
+	return 0;
+}
+
+/**
+ * cxi_dev_get_rgroup_count() - Count the number of valid rgroups associated
+ * with a given device.
+ *
+ * @dev: Cassini Device
+ * Return: number of valid rgroups.
+ */
+unsigned int cxi_dev_get_rgroup_count(struct cxi_dev *dev)
+{
+	struct cxi_rgroup *rgroup;
+	unsigned long index = rgroup_id_limits.min;
+	unsigned int count = 0;
+	struct cass_dev *hw = get_cass_dev(dev);
+
+	for_each_rgroup(index, rgroup)
+		count++;
+
+	return count;
+}
+EXPORT_SYMBOL(cxi_dev_get_rgroup_count);
+
+/**
+ * cxi_dev_get_rgroup_ids() - Retrieve the rgroup ids associated
+ * with a given device.
+ *
+ * @dev: Cassini Device
+ * @max_ids: the size of the rgroup_ids array
+ * @rgroup_ids: User allocated array to store id values
+ * @num_ids: On success, the number of valid ids in the rgroup_ids
+ * array.  On -ENOSPC, the value of max_ids needed to retrieve all
+ * the ids.
+ *
+ * Return: 0 on success.
+ * -ENOSPC: max_ids is not large enough
+ */
+int cxi_dev_get_rgroup_ids(struct cxi_dev *dev,
+			   size_t max_ids,
+			   unsigned int *rgroup_ids,
+			   size_t *num_ids)
+{
+	struct rgroup_id_data    data = {
+		.max_ids = max_ids,
+		.ids     = rgroup_ids,
+		.num_ids = 0,
+	};
+	struct cass_dev     *hw = get_cass_dev(dev);
+	int    ret;
+
+	ret = rgroup_list_iterate(&hw->rgroup_list,
+				  rgroup_id_operator,
+				  &data);
+	if (ret)
+		return ret;
+
+	*num_ids = data.num_ids;
+	return (data.num_ids > max_ids) ? -ENOSPC : 0;
+}
+EXPORT_SYMBOL(cxi_dev_get_rgroup_ids);
+
+/**
+ * cxi_dev_rgroup_get_resource() - Retrieve resource data from an rgroup
+ *
+ * @dev: CXI Device
+ * @rgroup_id: ID of Resource Group
+ * @resource_type: which resource to retrieve
+ * @limits: location to store resource data
+ *
+ * Return:
+ * * 0         - success
+ * * -EBADR    - no such rgroup_id
+ * * -EINVAL   - bad resource type or limits
+ * * -ENODATA  - resource did not exist
+ */
+int cxi_dev_rgroup_get_resource(struct cxi_dev *dev,
+				unsigned int rgroup_id,
+				enum cxi_resource_type resource_type,
+				struct cxi_resource_limits *limits)
+{
+	struct cxi_rgroup   *rgroup;
+	int    ret;
+
+	ret = find_rgroup_inc_refcount(dev, rgroup_id, &rgroup);
+	if (ret)
+		return ret;
+
+	ret = cxi_rgroup_get_resource(rgroup, resource_type, limits);
+
+	cxi_rgroup_dec_refcount(rgroup);
+	return ret;
+}
+EXPORT_SYMBOL(cxi_dev_rgroup_get_resource);
+
+/**
+ * cxi_dev_rgroup_get_resource_types() - Retrieve the list of resource types
+ *                                       associated with an rgroup
+ *
+ * @dev: CXI Device
+ * @rgroup_id: ID of Resource Group
+ * @max_types: size of resource_types array
+ * @resource_types: location to place resource types
+ * @num_types: actual number of valid types in resource_types on success
+ *
+ * Return:
+ * * 0         - success
+ * * -EBADR    - no such rgroup_id
+ * * -ENOSPC   - max_types is not large enough.  num_types hold required value.
+ */
+int cxi_dev_rgroup_get_resource_types(struct cxi_dev *dev,
+				      unsigned int rgroup_id,
+				      size_t max_types,
+				      enum cxi_resource_type *resource_types,
+				      size_t *num_types)
+{
+	struct cxi_rgroup   *rgroup;
+	int    ret;
+
+	ret = find_rgroup_inc_refcount(dev, rgroup_id, &rgroup);
+	if (ret)
+		return ret;
+
+	ret = cxi_rgroup_get_resource_types(rgroup,
+					    max_types,
+					    resource_types,
+					    num_types);
+
+	cxi_rgroup_dec_refcount(rgroup);
+	return ret;
+}
+EXPORT_SYMBOL(cxi_dev_rgroup_get_resource_types);
+
+/**
+ * cxi_dev_rgroup_delete_ac_entry() - Remove an Access Control Entry
+ *                                    from an rgroup
+ *
+ * @dev: CXI Device
+ * @rgroup_id: ID of Resource Group
+ * @ac_entry_id: ID of AC Entry
+ *
+ * Return:
+ * * 0         - success
+ * * -EBADR    - no such rgroup_id
+ * * -ENODATA  - entry did not exist
+ */
+int cxi_dev_rgroup_delete_ac_entry(struct cxi_dev *dev,
+				   unsigned int rgroup_id,
+				   unsigned int ac_entry_id)
+{
+	struct cxi_rgroup   *rgroup;
+	int    ret;
+
+	ret = find_rgroup_inc_refcount(dev, rgroup_id, &rgroup);
+	if (ret)
+		return ret;
+
+	ret = cxi_rgroup_delete_ac_entry(rgroup, ac_entry_id);
+
+	cxi_rgroup_dec_refcount(rgroup);
+	return ret;
+}
+EXPORT_SYMBOL(cxi_dev_rgroup_delete_ac_entry);
+
+/**
+ * cxi_dev_rgroup_get_ac_entry_ids() - Retrieve the list of Access Control
+ *                                     Entry ids from a rgroup
+ *
+ * @dev: CXI Device
+ * @rgroup_id: ID of Resource Group
+ * @max_ids: size of the ac_entry_ids array
+ * @ac_entry_ids: location to store ids
+ * @num_ids: number of valid ids in ac_entry_ids on success
+ *
+ * Return:
+ * * 0         - success
+ * * -EBADR    - no such rgroup_id
+ * * -ENOSPC   - max_ids is not large enough, num_ids holds required size
+ */
+int cxi_dev_rgroup_get_ac_entry_ids(struct cxi_dev *dev,
+				    unsigned int rgroup_id,
+				    size_t max_ids,
+				    unsigned int *ac_entry_ids,
+				    size_t *num_ids)
+{
+	struct cxi_rgroup  *rgroup;
+	int    ret;
+
+	ret = find_rgroup_inc_refcount(dev, rgroup_id, &rgroup);
+	if (ret)
+		return ret;
+
+	ret = cxi_rgroup_get_ac_entry_ids(rgroup, max_ids,
+					  ac_entry_ids, num_ids);
+
+	cxi_rgroup_dec_refcount(rgroup);
+	return ret;
+}
+EXPORT_SYMBOL(cxi_dev_rgroup_get_ac_entry_ids);
+
+/**
+ * cxi_dev_rgroup_get_ac_entry_data() - Retrieve an Access Control
+ *                                      Entry from a rgroup
+ *
+ * @dev: CXI Device
+ * @rgroup_id: ID of Resource Group
+ * @ac_entry_id: which Access Control entry to retrieve
+ * @ac_type: location to store type
+ * @ac_data: location to store data
+ *
+ * Return:
+ * * 0         - success
+ * * -EBADR    - no such rgroup_id
+ * * -ENODATA  - ac_entry_id not found
+ */
+int cxi_dev_rgroup_get_ac_entry_data(struct cxi_dev *dev,
+				     unsigned int rgroup_id,
+				     unsigned int ac_entry_id,
+				     enum cxi_ac_type *ac_type,
+				     union cxi_ac_data *ac_data)
+{
+	struct cxi_rgroup   *rgroup;
+	int    ret;
+
+	ret = find_rgroup_inc_refcount(dev, rgroup_id, &rgroup);
+	if (ret)
+		return ret;
+
+	ret = cxi_rgroup_get_ac_entry_data(rgroup, ac_entry_id,
+					   ac_type, ac_data);
+
+	cxi_rgroup_dec_refcount(rgroup);
+	return ret;
+}
+EXPORT_SYMBOL(cxi_dev_rgroup_get_ac_entry_data);
+
+/**
+ * cxi_dev_rgroup_get_ac_entry_id_by_data() - Retrieve the Access Control
+ *                                            Entry id corresponding to
+ *                                            given AC data
+ *
+ * @dev: CXI Device
+ * @rgroup_id: ID of Resource Group
+ * @ac_type: which type to retrieve
+ * @ac_data: which data to look for
+ * @ac_entry_id: location to store AC Entry ID
+ *
+ * Return:
+ * * 0         - success
+ * * -EBADR    - no such rgroup_id
+ * * -ENODATA  - No entry found with type and data
+ */
+int cxi_dev_rgroup_get_ac_entry_id_by_data(struct cxi_dev *dev,
+					   unsigned int rgroup_id,
+					   enum cxi_ac_type ac_type,
+					   union cxi_ac_data *ac_data,
+					   unsigned int *ac_entry_id)
+{
+	struct cxi_rgroup    *rgroup;
+	int    ret;
+
+	ret = find_rgroup_inc_refcount(dev, rgroup_id, &rgroup);
+	if (ret)
+		return ret;
+
+	ret = cxi_rgroup_get_ac_entry_id_by_data(rgroup, ac_type,
+						 ac_data, ac_entry_id);
+
+	cxi_rgroup_dec_refcount(rgroup);
+	return ret;
+}
+EXPORT_SYMBOL(cxi_dev_rgroup_get_ac_entry_id_by_data);
+
+/**
+ * cxi_dev_rgroup_get_ac_entry_id_by_user() - Retrieve the Access Control
+ *                                            Entry id corresponding to
+ *                                            given uid or gid
+ *
+ * @dev: CXI Device
+ * @rgroup_id: ID of Resource Group
+ * @uid: user id to match
+ * @gid: group id to match
+ * @netns: The network namespace id
+ * @desired_types: which type of AC Entry to search
+ * @ac_entry_id: location to store AC Entry ID if found
+ *
+ * Return:
+ * * 0         - success
+ * * -EBADR    - no such rgroup_id
+ * * -ENODATA  - No entry found of desired type
+ */
+int cxi_dev_rgroup_get_ac_entry_id_by_user(struct cxi_dev *dev,
+					   unsigned int rgroup_id,
+					   uid_t uid,
+					   gid_t gid,
+					   unsigned int netns,
+					   cxi_ac_typeset_t desired_types,
+					   unsigned int *ac_entry_id)
+{
+	struct cxi_rgroup    *rgroup;
+	int    ret;
+
+	ret = find_rgroup_inc_refcount(dev, rgroup_id, &rgroup);
+	if (ret)
+		return ret;
+
+	ret = cxi_rgroup_get_ac_entry_by_user(rgroup, uid, gid, netns,
+					      desired_types,
+					      ac_entry_id);
+
+	cxi_rgroup_dec_refcount(rgroup);
+	return ret;
+}
+EXPORT_SYMBOL(cxi_dev_rgroup_get_ac_entry_id_by_user);
+
+void cxi_rgroup_print_ac_entry_info(struct cxi_rgroup *rgroup,
+				    struct seq_file *s)
+{
+	int i;
+	int rc;
+	size_t num_ids;
+	size_t max_ids;
+	unsigned int *ac_entry_ids = NULL;
+	enum cxi_ac_type ac_type;
+	union cxi_ac_data ac_data;
+
+	rc = cxi_rgroup_get_ac_entry_ids(rgroup, 0, ac_entry_ids, &num_ids);
+	if (rc && rc != -ENOSPC)
+		goto done;
+
+	ac_entry_ids = kmalloc_array(num_ids, sizeof(*ac_entry_ids),
+				     GFP_ATOMIC);
+	if (!ac_entry_ids) {
+		rc = -ENOMEM;
+		goto done;
+	}
+
+	rc = cxi_rgroup_get_ac_entry_ids(rgroup, num_ids, ac_entry_ids,
+					 &max_ids);
+	if (rc)
+		goto freemem;
+
+	seq_puts(s, "  AC-entries: ");
+	for (i = 0; i < num_ids; i++) {
+		rc = cxi_rgroup_get_ac_entry_data(rgroup, ac_entry_ids[i],
+						  &ac_type, &ac_data);
+		if (rc)
+			break;
+
+		seq_printf(s, "ID:%d type:%s uid/gid:%d%s",
+			   ac_entry_ids[i], AC_TYPE(ac_type),
+			   ac_type == CXI_AC_OPEN ? 0 : ac_data.uid,
+			   i < (num_ids - 1) ? ", " : "");
+	}
+	seq_puts(s, "\n");
+
+freemem:
+	kfree(ac_entry_ids);
+done:
+	if (rc)
+		seq_puts(s, "\n");
+}
diff --git a/drivers/net/ethernet/hpe/ss1/cxi_rx_profile.c b/drivers/net/ethernet/hpe/ss1/cxi_rx_profile.c
new file mode 100644
index 000000000000..939f523930b2
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cxi_rx_profile.c
@@ -0,0 +1,833 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright (C) 2024 Hewlett Packard Enterprise Development LP */
+
+/* RX Profile Implementation */
+
+#include "cass_core.h"
+#include "cxi_rxtx_profile.h"
+#include "cxi_rxtx_profile_list.h"
+
+#define RX_PROFILE_GFP_OPTS  (GFP_KERNEL)
+
+static struct cass_dev *get_cass_dev(struct cxi_dev *dev)
+{
+	return container_of(dev, struct cass_dev, cdev);
+}
+
+static void rx_profile_init(struct cxi_rx_profile *rx_profile,
+			    struct cass_dev *hw,
+			    const struct cxi_rx_attr *rx_attr)
+{
+	cxi_rxtx_profile_init(&rx_profile->profile_common,
+			      hw, &rx_attr->vni_attr);
+
+	/* TODO: extract additional parameters */
+}
+
+static void cxi_rx_profile_update_pid_table_locked(
+					struct cxi_rx_profile *rx_profile,
+					int pid, int nbits, bool set)
+{
+	struct cass_dev *hw = get_cass_dev(rx_profile->config.device);
+	int index;
+
+	for (index = pid; index < pid + nbits; index++) {
+		if (set) {
+			if (!test_and_set_bit(index, rx_profile->config.pid_table))
+				hw->pid_usecount[index]++;
+		} else if (test_and_clear_bit(index, rx_profile->config.pid_table)) {
+			hw->pid_usecount[index]--;
+		}
+	}
+}
+
+/**
+ * cxi_rx_profile_update_pid_table() - Set/clear pids from rx profile pid_table
+ *
+ * @rx_profile: RX profile object
+ * @pid: Pid to allocate
+ * @nbits: Number of entries to clear
+ * @set: Set or clear
+ */
+void cxi_rx_profile_update_pid_table(struct cxi_rx_profile *rx_profile, int pid,
+				     int nbits, bool set)
+{
+	struct cass_dev *hw = get_cass_dev(rx_profile->config.device);
+
+	spin_lock(&hw->pid_pool_lock);
+	spin_lock(&rx_profile->config.pid_lock);
+	cxi_rx_profile_update_pid_table_locked(rx_profile, pid, nbits, set);
+	spin_unlock(&rx_profile->config.pid_lock);
+	spin_unlock(&hw->pid_pool_lock);
+}
+
+/**
+ * cxi_rx_profile_andnot_pid_table() - Update rx profile pid_table based on
+ *                                     pids table.
+ *
+ * @pids: pids object
+ * @len: Number of entries to clear.
+ */
+void cxi_rx_profile_andnot_pid_table(struct cxi_reserved_pids *pids,
+				     int len)
+{
+	struct cxi_rx_profile *rx_profile = pids->rx_profile;
+	struct cass_dev *hw = get_cass_dev(rx_profile->config.device);
+	unsigned long pid;
+
+	spin_lock(&hw->pid_pool_lock);
+	spin_lock(&rx_profile->config.pid_lock);
+	for_each_set_bit(pid, pids->table, len)
+		cxi_rx_profile_update_pid_table_locked(rx_profile, pid, 1, false);
+	spin_unlock(&rx_profile->config.pid_lock);
+	spin_unlock(&hw->pid_pool_lock);
+}
+
+/* Return true if the PID is reserved to the LNI. If so, mark the PID as
+ * "allocated" and do some house-keeping.
+ */
+static bool pid_reserved(struct cxi_lni_priv *lni_priv, unsigned int vni,
+			 unsigned int pid)
+{
+	bool match;
+	bool rc = false;
+	struct cxi_reserved_pids *pids;
+	struct cxi_rxtx_vni_attr vni_attr = {.match = vni};
+
+	spin_lock(&lni_priv->res_lock);
+
+	list_for_each_entry(pids, &lni_priv->reserved_pids, entry) {
+		match = vni_overlap(&vni_attr,
+				    &pids->rx_profile->profile_common.vni_attr);
+
+		if (match && test_and_clear_bit(pid, pids->table)) {
+			if (bitmap_empty(pids->table,
+					 lni_priv->dev->prop.pid_count)) {
+				list_del(&pids->entry);
+				cxi_rx_profile_dec_refcount(lni_priv->dev,
+							    pids->rx_profile);
+				kfree(pids);
+			}
+
+			rc = true;
+			break;
+		}
+	}
+
+	spin_unlock(&lni_priv->res_lock);
+
+	return rc;
+}
+
+/**
+ * cxi_rx_profile_alloc_pid() - Allocate or reserve a domain pid
+ *
+ * @lni_priv: the Logical Network Interface
+ * @rx_profile: RX profile object
+ * @pid: Pid to allocate
+ * @vni: Match criteria to find rx profile when finding a reserved pid
+ * @count: size of pid range
+ * @reserve: flag indicates reserving a pid range
+ *
+ * Return:
+ * * new_pid on success
+ * * -ENOSPC, -EEXIST
+ */
+int cxi_rx_profile_alloc_pid(struct cxi_lni_priv *lni_priv,
+			     struct cxi_rx_profile *rx_profile,
+			     int pid, int vni, int count, bool reserve)
+{
+	unsigned long *pid_table = rx_profile->config.pid_table;
+	struct cxi_dev *dev = lni_priv->dev;
+	struct cass_dev *hw = get_cass_dev(dev);
+	int start = (pid == C_PID_ANY) ? 0 : pid;
+	int new_pid = pid;
+	int offset;
+
+	if (!count || count > lni_priv->dev->prop.pid_count)
+		return -EINVAL;
+
+	spin_lock(&hw->pid_pool_lock);
+	spin_lock(&rx_profile->config.pid_lock);
+
+retry:
+	if (reserve || pid == C_PID_ANY) {
+		new_pid = bitmap_find_next_zero_area(pid_table,
+						     dev->prop.pid_count,
+						     start, count, 0);
+		if (pid == C_PID_ANY) {
+			if (new_pid + count > dev->prop.pid_count) {
+				new_pid = -ENOSPC;
+				goto unlock;
+			}
+		} else {
+			if (new_pid >= (pid + count)) {
+				new_pid = -EEXIST;
+				goto unlock;
+			}
+		}
+	} else {
+		if (test_bit(new_pid, pid_table) &&
+		    !pid_reserved(lni_priv, vni, new_pid)) {
+			new_pid = -EEXIST;
+			goto unlock;
+		}
+	}
+	for (offset = 0; offset < count; offset++) {
+		if (!test_bit(new_pid + offset, hw->leased_pids))
+			continue;
+		if (pid != C_PID_ANY &&
+		    test_bit(new_pid + offset, lni_priv->leased_pids))
+			continue;
+		if (pid == C_PID_ANY) {
+			start = new_pid + offset + 1;
+			goto retry;
+		}
+		new_pid = -EEXIST;
+		goto unlock;
+	}
+
+	cxi_rx_profile_update_pid_table_locked(rx_profile, new_pid, count,
+					       true);
+
+unlock:
+	spin_unlock(&rx_profile->config.pid_lock);
+	spin_unlock(&hw->pid_pool_lock);
+
+	return new_pid;
+}
+
+/**
+ * cxi_rx_profile_enable() - Enable a Profile
+ *
+ * @dev: Cassini Device
+ * @rx_profile: Profile to be enabled.
+ *
+ * Return:
+ * * 0       - success
+ * * -ENOSPC
+ */
+int cxi_rx_profile_enable(struct cxi_dev *dev,
+			  struct cxi_rx_profile *rx_profile)
+{
+	int index;
+	struct cass_dev *hw = get_cass_dev(dev);
+	struct cxi_rxtx_vni_attr *attr;
+
+	if (!rx_profile)
+		return -EINVAL;
+
+	if (cxi_rx_profile_is_enabled(rx_profile))
+		return 0;
+
+	attr = &rx_profile->profile_common.vni_attr;
+
+	if (zero_vni(attr)) {
+		pr_debug("Cannot enable profile with invalid VNI\n");
+		return -EINVAL;
+	}
+
+	index = ida_alloc_range(&hw->rmu_index_table, 0,
+				C_RMU_CFG_VNI_LIST_ENTRIES - 1, GFP_KERNEL);
+	if (index < 0)
+		return index;
+
+	cass_config_matching_vni_list(hw, index, attr->match, attr->ignore);
+
+	rx_profile->profile_common.state.enable = true;
+	rx_profile->config.rmu_index = index;
+
+	return 0;
+}
+EXPORT_SYMBOL(cxi_rx_profile_enable);
+
+/**
+ * cxi_rx_profile_disable() - Disable a Profile
+ *
+ * @dev: Cassini Device
+ * @rx_profile: Profile to be disabled.
+ */
+void cxi_rx_profile_disable(struct cxi_dev *dev,
+			    struct cxi_rx_profile *rx_profile)
+{
+	struct cass_dev *hw = get_cass_dev(dev);
+
+	if (!rx_profile)
+		return;
+
+	if (!cxi_rx_profile_is_enabled(rx_profile))
+		return;
+
+	ida_free(&hw->rmu_index_table, rx_profile->config.rmu_index);
+	cass_invalidate_vni_list(hw, rx_profile->config.rmu_index);
+
+	rx_profile->profile_common.state.enable = false;
+}
+EXPORT_SYMBOL(cxi_rx_profile_disable);
+
+/**
+ * cxi_rx_profile_is_enabled() - Report RX profile is enabled
+ *
+ * @rx_profile: Profile object
+ */
+bool cxi_rx_profile_is_enabled(const struct cxi_rx_profile *rx_profile)
+{
+	if (!rx_profile)
+		return false;
+
+	return rx_profile->profile_common.state.enable;
+}
+EXPORT_SYMBOL(cxi_rx_profile_is_enabled);
+
+/**
+ * cxi_dev_set_rx_profile_attr() - Set the RX profile attributes
+ *
+ * @dev: Cassini Device
+ * @rx_profile: RX profile to update
+ * @rx_attr: Attributes of the RX Profile
+ *
+ * Return: 0 on success, or a negative errno value.
+ */
+int cxi_dev_set_rx_profile_attr(struct cxi_dev *dev,
+				struct cxi_rx_profile *rx_profile,
+				const struct cxi_rx_attr *rx_attr)
+{
+	struct cass_dev *hw = get_cass_dev(dev);
+
+	if (rx_profile->profile_common.state.enable)
+		return -EBUSY;
+
+	if (!vni_well_formed(&rx_attr->vni_attr)) {
+		pr_debug("VNI not well formed match:%d ignore:%d\n",
+			 rx_attr->vni_attr.match, rx_attr->vni_attr.ignore);
+		return -EINVAL;
+	}
+
+	if (!unique_vni_space(hw, &hw->rx_profile_list, &rx_attr->vni_attr)) {
+		pr_debug("VNI not unique match:%d ignore:%d\n",
+			 rx_attr->vni_attr.match, rx_attr->vni_attr.ignore);
+		return -EINVAL;
+	}
+
+	rx_profile->profile_common.vni_attr.match = rx_attr->vni_attr.match;
+	rx_profile->profile_common.vni_attr.ignore = rx_attr->vni_attr.ignore;
+
+	if (!rx_attr->vni_attr.name[0])
+		strscpy(rx_profile->profile_common.vni_attr.name,
+			rx_attr->vni_attr.name,
+			ARRAY_SIZE(rx_attr->vni_attr.name));
+
+	return 0;
+}
+EXPORT_SYMBOL(cxi_dev_set_rx_profile_attr);
+
+/**
+ * cxi_dev_alloc_rx_profile() - Allocate a RX Profile
+ *
+ * @dev: Cassini Device
+ * @rx_attr: Attributes of the RX Profile
+ *
+ * Return: rx_profile ptr on success, or a negative errno value.
+ */
+struct cxi_rx_profile *cxi_dev_alloc_rx_profile(struct cxi_dev *dev,
+						const struct cxi_rx_attr *rx_attr)
+{
+	int                    ret = 0;
+	struct cass_dev        *hw = get_cass_dev(dev);
+	struct cxi_rx_profile  *rx_profile;
+
+	if (!zero_vni(&rx_attr->vni_attr) &&
+	    !vni_well_formed(&rx_attr->vni_attr))
+		return ERR_PTR(-EDOM);
+
+	/* Allocate memory */
+	rx_profile = kzalloc(sizeof(*rx_profile), RX_PROFILE_GFP_OPTS);
+	if (!rx_profile)
+		return ERR_PTR(-ENOMEM);
+
+	/* initialize common profile and cassini config members */
+	rx_profile_init(rx_profile, hw, rx_attr);
+	cass_rx_profile_init(hw, rx_profile);
+
+	cxi_rxtx_profile_list_lock(&hw->rx_profile_list);
+
+	/* Configfs needs to allocate a profile without attributes which
+	 * will be updated later.
+	 */
+	if (!zero_vni(&rx_attr->vni_attr)) {
+		ret = cxi_rxtx_profile_list_iterate(&hw->rx_profile_list,
+						    vni_overlap_test,
+						    &rx_profile->profile_common);
+		if (ret)
+			goto unlock_free_return;
+	}
+
+	/* Insert into device list if unique */
+	ret = cxi_rxtx_profile_list_insert(&hw->rx_profile_list,
+					   &rx_profile->profile_common,
+					   &rx_profile->profile_common.id);
+
+	cxi_rxtx_profile_list_unlock(&hw->rx_profile_list);
+
+	if (ret)
+		goto free_return;
+
+	refcount_inc(&hw->refcount);
+
+	return rx_profile;
+
+unlock_free_return:
+
+	cxi_rxtx_profile_list_unlock(&hw->rx_profile_list);
+
+free_return:
+	kfree(rx_profile);
+	return ERR_PTR(ret);
+}
+EXPORT_SYMBOL(cxi_dev_alloc_rx_profile);
+
+/**
+ * cxi_dev_find_rx_profile() - Get RX profile containing a vni
+ *
+ * @dev: Cassini Device
+ * @vni: Match criteria to find rx profile
+ *
+ * Return: rx_profile ptr on success or NULL
+ */
+struct cxi_rx_profile *cxi_dev_find_rx_profile(struct cxi_dev *dev,
+					       u16 vni)
+{
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+	struct cxi_rxtx_profile_list *list = &hw->rx_profile_list;
+	struct cxi_rx_profile *rx_profile = NULL;
+	struct cxi_rxtx_profile *profile;
+	unsigned long index = list->limits->min;
+	uid_t uid = __kuid_val(current_euid());
+	gid_t gid = __kgid_val(current_egid());
+	unsigned int netns = CURRENT_NETNS_ID();
+	unsigned int ac_entry_id;
+	int rc;
+
+	cxi_rxtx_profile_list_lock(list);
+	xa_for_each(&list->xarray, index, profile) {
+		if (!profile->state.enable)
+			continue;
+
+		if ((vni & ~profile->vni_attr.ignore) == profile->vni_attr.match) {
+			rx_profile = container_of(profile,
+						  struct cxi_rx_profile,
+						  profile_common);
+
+			rc = cxi_rxtx_profile_get_ac_entry_id_by_user(
+						&rx_profile->profile_common,
+						uid, gid, netns, CXI_AC_ANY,
+						&ac_entry_id);
+			if (!rc) {
+				refcount_inc(&profile->state.refcount);
+				break;
+			}
+
+			rx_profile = ERR_PTR(rc);
+		}
+	}
+
+	cxi_rxtx_profile_list_unlock(list);
+
+	return rx_profile;
+}
+
+/**
+ * cxi_dev_get_rx_profile - Get an RX profile
+ *
+ * For a given VNI check if an RX profile is already allocated
+ * and return it.
+ * For kernel users (i.e. kcxi), allocate one if not found, add
+ * an AC entry, set the TCs and enable the profile.
+ *
+ * @dev: Cassini Device
+ * @vni: VNI to find
+ *
+ * Return: rx_profile ptr on success, or a negative errno value.
+ */
+struct cxi_rx_profile *cxi_dev_get_rx_profile(struct cxi_dev *dev,
+					      unsigned int vni)
+{
+	int rc;
+	unsigned int ac_entry_id;
+	struct cass_dev *hw = get_cass_dev(dev);
+	struct cxi_rx_profile *rx_profile;
+	unsigned int netns = CURRENT_NETNS_ID();
+	struct cxi_rx_attr rx_attr = {
+		.vni_attr = {
+			.match = vni,
+			.ignore = 0
+		}
+	};
+
+	mutex_lock(&hw->rx_profile_get_lock);
+	rx_profile = cxi_dev_find_rx_profile(dev, vni);
+	if (rx_profile)
+		goto done;
+
+	/* For a non-root user, just report no entry found.*/
+	if (__kuid_val(current_euid())) {
+		rx_profile = ERR_PTR(-ENOENT);
+		goto done;
+	}
+
+	rx_profile = cxi_dev_alloc_rx_profile(dev, &rx_attr);
+	if (IS_ERR(rx_profile))
+		goto done;
+
+	rc = cxi_rx_profile_add_ac_entry(rx_profile, CXI_AC_UID,
+					 __kuid_val(current_euid()), 0,
+					 netns, &ac_entry_id);
+	if (rc) {
+		rx_profile = ERR_PTR(rc);
+		goto done;
+	}
+
+	rc = cxi_rx_profile_enable(dev, rx_profile);
+	if (rc)
+		rx_profile = ERR_PTR(rc);
+
+done:
+	mutex_unlock(&hw->rx_profile_get_lock);
+
+	return rx_profile;
+}
+EXPORT_SYMBOL(cxi_dev_get_rx_profile);
+
+/**
+ * cxi_rx_profile_dec_refcount() - Decrement refcount and cleanup
+ *                                 if last reference
+ *
+ * @dev: Cassini device pointer
+ * @rx_profile: pointer to Profile
+ *
+ */
+int cxi_rx_profile_dec_refcount(struct cxi_dev *dev,
+				struct cxi_rx_profile *rx_profile)
+{
+	struct cass_dev *hw = get_cass_dev(dev);
+	int    ret;
+
+	if (!rx_profile)
+		return 0;
+
+	ret = refcount_dec_and_test(&rx_profile->profile_common.state.refcount);
+	if (!ret)
+		return -EBUSY;
+
+	cxi_rx_profile_disable(dev, rx_profile);
+	cxi_rx_profile_remove_ac_entries(rx_profile);
+	refcount_dec(&hw->refcount);
+	cxi_rxtx_profile_list_remove(&hw->rx_profile_list,
+				     rx_profile->profile_common.id);
+
+	kfree(rx_profile);
+	return 0;
+}
+EXPORT_SYMBOL(cxi_rx_profile_dec_refcount);
+
+/**
+ * cxi_rx_profile_get_info() - Retrieve the attributes and state associated
+ *                             with this Profile
+ *
+ * @dev: Cassini Device
+ * @rx_profile: RX Profile
+ * @rx_attr: location to place attributes
+ * @state: location to put state
+ *
+ * Note: rx_attr and/or state may be NULL.  If both are NULL,
+ * this return value indicates whether the Profile exists
+ * with the given Id value.
+ *
+ * Return:
+ * * 0      - success
+ * * -EBADR - rx_profile_id unknown
+ */
+int cxi_rx_profile_get_info(struct cxi_dev *dev,
+			    struct cxi_rx_profile *rx_profile,
+			    struct cxi_rx_attr *rx_attr,
+			    struct cxi_rxtx_profile_state *state)
+{
+	cxi_rxtx_profile_get_info(&rx_profile->profile_common,
+				  (rx_attr) ? &rx_attr->vni_attr : NULL,
+				  state);
+
+	/* TODO: other rx_attr values */
+
+	return 0;
+}
+EXPORT_SYMBOL(cxi_rx_profile_get_info);
+
+static void print_rx_profile_ac_entry_info(struct cxi_rx_profile *rx_profile,
+					   struct seq_file *s)
+{
+	int i;
+	int rc;
+	size_t num_ids;
+	size_t max_ids;
+	unsigned int *ac_entry_ids = NULL;
+	enum cxi_ac_type ac_type;
+	union cxi_ac_data ac_data;
+
+	rc = cxi_rx_profile_get_ac_entry_ids(rx_profile, 0, ac_entry_ids,
+					     &num_ids);
+	if (rc && rc != -ENOSPC)
+		goto done;
+
+	ac_entry_ids = kmalloc_array(num_ids, sizeof(*ac_entry_ids),
+				     GFP_ATOMIC);
+	if (!ac_entry_ids) {
+		rc = -ENOMEM;
+		goto done;
+	}
+
+	rc = cxi_rx_profile_get_ac_entry_ids(rx_profile, num_ids, ac_entry_ids,
+					     &max_ids);
+	if (rc)
+		goto freemem;
+
+	seq_puts(s, "        AC-entries: ");
+	for (i = 0; i < num_ids; i++) {
+		rc = cxi_rx_profile_get_ac_entry_data(rx_profile,
+						      ac_entry_ids[i],
+						      &ac_type, &ac_data);
+		if (rc)
+			break;
+
+		seq_printf(s, "ID:%d type:%s uid/gid:%d%s",
+			   ac_entry_ids[i], AC_TYPE(ac_type),
+			   ac_type == CXI_AC_OPEN ? 0 : ac_data.uid,
+			   i < (num_ids - 1) ? ", " : "");
+	}
+	seq_puts(s, "\n");
+
+freemem:
+	kfree(ac_entry_ids);
+done:
+	if (rc)
+		seq_puts(s, "\n");
+}
+
+static void print_profile(struct cxi_rx_profile *rx_profile, struct seq_file *s)
+{
+	struct cxi_rxtx_vni_attr vni_attr;
+	struct cxi_rxtx_profile_state state;
+	struct cxi_rxtx_profile *profile = &rx_profile->profile_common;
+
+	cxi_rxtx_profile_get_info(profile, &vni_attr, &state);
+	seq_printf(s, "  ID:%-2d Name:%s VNI:match:%u ignore:%u State:%s refcount:%d\n",
+		   profile->id,
+		   vni_attr.name[0] ? vni_attr.name : "none",
+		   vni_attr.match, vni_attr.ignore,
+		   state.enable ? "enabled" : "disabled",
+		   refcount_read(&state.refcount));
+
+	print_rx_profile_ac_entry_info(rx_profile, s);
+}
+
+/**
+ * cxi_rx_profile_print() - Print the RX profile info
+ *
+ * @s: file ptr
+ *
+ */
+void cxi_rx_profile_print(struct seq_file *s)
+{
+	struct cass_dev *hw = s->private;
+	struct cxi_rxtx_profile_list *list = &hw->rx_profile_list;
+	struct cxi_rx_profile *rx_profile;
+	struct cxi_rxtx_profile *profile;
+	unsigned long index;
+
+	seq_puts(s, "\nRX profiles:\n");
+
+	cxi_rxtx_profile_list_lock(list);
+
+	xa_for_each(&list->xarray, index, profile) {
+		rx_profile = container_of(profile, struct cxi_rx_profile,
+					  profile_common);
+		print_profile(rx_profile, s);
+	}
+
+	cxi_rxtx_profile_list_unlock(list);
+}
+
+/**
+ * cxi_rx_profile_remove_ac_entry() - disable access control to a Profile
+ *                                    by access control id.
+ *
+ * @rx_profile: pointer to Profile
+ * @ac_entry_id: id of AC entry
+ *
+ * Return:
+ * * 0       - success
+ * * -EBADR  - ac entry id unknown
+ */
+int cxi_rx_profile_remove_ac_entry(struct cxi_rx_profile *rx_profile,
+				   unsigned int ac_entry_id)
+{
+	return cxi_rxtx_profile_remove_ac_entry(&rx_profile->profile_common,
+						ac_entry_id);
+}
+EXPORT_SYMBOL(cxi_rx_profile_remove_ac_entry);
+
+/**
+ * cxi_rx_profile_get_ac_entry_ids() - get the list of AC entry ids
+ *                                     associated with a Profile
+ *
+ * @rx_profile: pointer to Profile
+ * @max_ids: size of the ac_entry_ids array
+ * @ac_entry_ids: location to store ids
+ * @num_ids: number of valid ids in ac_entry_ids array on success
+ *
+ * Return:
+ * * 0       - success
+ * * -ENOSPC - max_ids is not large enough.  num_ids holds value required.
+ */
+int cxi_rx_profile_get_ac_entry_ids(struct cxi_rx_profile *rx_profile,
+				    size_t max_ids,
+				    unsigned int *ac_entry_ids,
+				    size_t *num_ids)
+{
+	return cxi_rxtx_profile_get_ac_entry_ids(&rx_profile->profile_common,
+						 max_ids, ac_entry_ids, num_ids);
+}
+EXPORT_SYMBOL(cxi_rx_profile_get_ac_entry_ids);
+
+/**
+ * cxi_rx_profile_get_ac_entry_data() - retrieve the type and data for a
+ *                                      AC entry associated with a Profile
+ *
+ * @rx_profile: pointer to Profile
+ * @ac_entry_id: id of AC entry
+ * @ac_type: location to store AC entry type
+ * @ac_data: location to store AC data
+ *
+ * Return:
+ * * 0       - success
+ * * -EBADR  - AC entry id unknown
+ */
+int cxi_rx_profile_get_ac_entry_data(struct cxi_rx_profile *rx_profile,
+				     unsigned int ac_entry_id,
+				     enum cxi_ac_type *ac_type,
+				     union cxi_ac_data *ac_data)
+{
+	return cxi_rxtx_profile_get_ac_entry_data(&rx_profile->profile_common,
+						  ac_entry_id, ac_type, ac_data);
+}
+EXPORT_SYMBOL(cxi_rx_profile_get_ac_entry_data);
+
+/**
+ * cxi_rx_profile_get_ac_entry_id_by_data() - get the AC entry id associated
+ *                                            with a given VNI entry type and data
+ *
+ * @rx_profile: pointer to Profile
+ * @ac_type: type of AC entry to look for
+ * @ac_data: AC entry data to look for
+ * @ac_entry_id: location to store AC entry id on success
+ *
+ * Return:
+ * * 0        - success
+ * * -ENODATA - AC entry with given type&data not found
+ * * -EBADR   - invalid ac_type
+ */
+int cxi_rx_profile_get_ac_entry_id_by_data(struct cxi_rx_profile *rx_profile,
+					   enum cxi_ac_type ac_type,
+					   const union cxi_ac_data *ac_data,
+					   unsigned int *ac_entry_id)
+{
+	return cxi_rxtx_profile_get_ac_entry_id_by_data(&rx_profile->profile_common,
+							ac_type, ac_data, ac_entry_id);
+}
+EXPORT_SYMBOL(cxi_rx_profile_get_ac_entry_id_by_data);
+
+/**
+ * cxi_rx_profile_get_ac_entry_id_by_user() - retrieve the AC entry associated
+ *                                            with a Profile by user and group
+ *
+ * @rx_profile: pointer to Profile
+ * @uid: user id
+ * @gid: group id
+ * @netns: The Network namespace id
+ * @desired_types: list of enum cxi_ac_type values OR'd together
+ * @ac_entry_id: location to store AC entry id on success
+ *
+ * Return:
+ * * 0       - success
+ * * -EPERM  - no AC entries found for given uid and gid
+ *
+ * Note: multiple AC entries may apply.  The priority of return is
+ * CXI_AC_UID, CXI_AC_GID, CXI_AC_OPEN.
+ */
+int cxi_rx_profile_get_ac_entry_id_by_user(struct cxi_rx_profile *rx_profile,
+					   uid_t uid,
+					   gid_t gid,
+					   unsigned int netns,
+					   cxi_ac_typeset_t desired_types,
+					   unsigned int *ac_entry_id)
+{
+	return cxi_rxtx_profile_get_ac_entry_id_by_user(&rx_profile->profile_common,
+							uid, gid, netns, desired_types,
+							ac_entry_id);
+}
+EXPORT_SYMBOL(cxi_rx_profile_get_ac_entry_id_by_user);
+
+/**
+ * cxi_rx_profile_add_ac_entry() - add an Access Control entry to
+ *                                 an existing Profile
+ *
+ * @rx_profile: RX profile to add AC Entry
+ * @type: type of AC Entry to add
+ * @uid: UID for AC Entry
+ * @gid: GID for AC Entry
+ * @netns: The Network Namespace id
+ * @ac_entry_id: Location to store resulting id
+ *
+ * Return:
+ * * 0       - success
+ * * -EEXIST - AC Entry already exists
+ */
+int cxi_rx_profile_add_ac_entry(struct cxi_rx_profile *rx_profile,
+				enum cxi_ac_type type, uid_t uid, gid_t gid,
+				unsigned int netns, unsigned int *ac_entry_id)
+{
+	union cxi_ac_data data = {};
+
+	switch (type) {
+	case CXI_AC_UID:
+		data.uid = uid;
+		break;
+	case CXI_AC_GID:
+		data.gid = gid;
+		break;
+	case CXI_AC_OPEN:
+		break;
+	case CXI_AC_NETNS:
+		data.netns = netns;
+		break;
+	default:
+		return -EDOM;
+	}
+
+	return cxi_rxtx_profile_add_ac_entry(&rx_profile->profile_common,
+					     type, &data, ac_entry_id);
+}
+EXPORT_SYMBOL(cxi_rx_profile_add_ac_entry);
+
+/**
+ * cxi_rx_profile_remove_ac_entries() - remove Access Control entries
+ *                                      from profile
+ *
+ * @rx_profile: RX profile from which to remove AC entries
+ */
+void cxi_rx_profile_remove_ac_entries(struct cxi_rx_profile *rx_profile)
+{
+	if (!rx_profile)
+		return;
+
+	cxi_ac_entry_list_destroy(&rx_profile->profile_common.ac_entry_list);
+}
diff --git a/drivers/net/ethernet/hpe/ss1/cxi_tx_profile.c b/drivers/net/ethernet/hpe/ss1/cxi_tx_profile.c
new file mode 100644
index 000000000000..4037c389a77d
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cxi_tx_profile.c
@@ -0,0 +1,819 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright (C) 2024 Hewlett Packard Enterprise Development LP */
+
+/* TX Profile Implementation */
+
+#include "cass_core.h"
+#include "cxi_rxtx_profile.h"
+#include "cxi_rxtx_profile_list.h"
+
+#define TX_PROFILE_GFP_OPTS  (GFP_KERNEL)
+
+static struct cass_dev *get_cass_dev(struct cxi_dev *dev)
+{
+	return container_of(dev, struct cass_dev, cdev);
+}
+
+/* initialize common profile and cassini config members */
+static void cass_dev_init_tx_profile(struct cass_dev *hw,
+				     struct cxi_tx_profile *tx_profile,
+				     const struct cxi_tx_attr *tx_attr)
+{
+	cxi_rxtx_profile_init(&tx_profile->profile_common,
+			      hw, &tx_attr->vni_attr);
+	cass_tx_profile_init(hw, tx_profile);
+}
+
+void cxi_dev_init_eth_tx_profile(struct cass_dev *hw)
+{
+	struct cxi_tx_attr tx_attr = {};
+
+	cass_dev_init_tx_profile(hw, &hw->eth_tx_profile, &tx_attr);
+	refcount_inc(&hw->refcount);
+}
+EXPORT_SYMBOL(cxi_dev_init_eth_tx_profile);
+
+/**
+ * cxi_tx_profile_list_destroy() - remove all Profile references from
+ *                                 the TX profile list and free the
+ *                                 underlying resources.
+ *
+ * Take the cp_lock so that the cass_cp_table can be iterated
+ * over to disable the CPs associated with each TX profile.
+ *
+ * @hw: Cassini Device ptr
+ */
+void cxi_tx_profile_list_destroy(struct cass_dev *hw)
+{
+	struct cxi_rxtx_profile *profile;
+	struct cxi_rxtx_profile_list *list = &hw->tx_profile_list;
+	unsigned long index = list->limits->min;
+
+	cass_cp_lock(hw);
+	xa_lock(&list->xarray);
+
+	xa_for_each(&list->xarray, index, profile) {
+		__xa_erase(&list->xarray, index);
+
+		refcount_dec(&profile->state.refcount);
+		cxi_tx_profile_dec_refcount(&hw->cdev,
+					    co_tx_profile(profile),
+					    false);
+	}
+
+	xa_unlock(&list->xarray);
+	cass_cp_unlock(hw);
+
+	xa_destroy(&list->xarray);
+}
+
+/**
+ * cxi_dev_alloc_tx_profile() - Allocate a TX Profile
+ *
+ * @dev: Cassini Device
+ * @tx_attr: TX attributes for the Profile
+ *
+ * Return: tx_profile ptr on success, or a negative errno value.
+ */
+struct cxi_tx_profile *cxi_dev_alloc_tx_profile(struct cxi_dev *dev,
+						const struct cxi_tx_attr *tx_attr)
+{
+	int                    ret = 0;
+	struct cass_dev        *hw = get_cass_dev(dev);
+	struct cxi_tx_profile  *tx_profile;
+
+	if (!zero_vni(&tx_attr->vni_attr) &&
+	    !vni_well_formed(&tx_attr->vni_attr))
+		return ERR_PTR(-EDOM);
+
+	/* Allocate memory */
+	tx_profile = kzalloc(sizeof(*tx_profile), TX_PROFILE_GFP_OPTS);
+	if (!tx_profile)
+		return ERR_PTR(-ENOMEM);
+
+	cass_dev_init_tx_profile(hw, tx_profile, tx_attr);
+
+	cxi_rxtx_profile_list_lock(&hw->tx_profile_list);
+
+	/* make sure the VNI space is unique */
+	ret = cxi_rxtx_profile_list_iterate(&hw->tx_profile_list,
+					    vni_overlap_test,
+					    &tx_profile->profile_common);
+	if (ret)
+		goto unlock_free_return;
+
+	/* Insert into device list if unique */
+	ret = cxi_rxtx_profile_list_insert(&hw->tx_profile_list,
+					   &tx_profile->profile_common,
+					   &tx_profile->profile_common.id);
+
+	cxi_rxtx_profile_list_unlock(&hw->tx_profile_list);
+
+	if (ret)
+		goto free_return;
+
+	refcount_inc(&hw->refcount);
+
+	return tx_profile;
+
+unlock_free_return:
+	cxi_rxtx_profile_list_unlock(&hw->tx_profile_list);
+
+free_return:
+	kfree(tx_profile);
+	return ERR_PTR(ret);
+}
+EXPORT_SYMBOL(cxi_dev_alloc_tx_profile);
+
+/**
+ * cxi_dev_find_tx_profile() - Find the TX profile containing a vni
+ *
+ * @dev: Cassini Device
+ * @vni: Match criteria to find TX profile
+ *
+ * Return: tx_profile ptr on success or NULL
+ */
+struct cxi_tx_profile *cxi_dev_find_tx_profile(struct cxi_dev *dev,
+					       u16 vni)
+{
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+	struct cxi_rxtx_profile_list *list = &hw->tx_profile_list;
+	struct cxi_tx_profile *tx_profile = NULL;
+	struct cxi_rxtx_profile *profile;
+	unsigned int netns = CURRENT_NETNS_ID();
+	unsigned long index = list->limits->min;
+	uid_t uid = __kuid_val(current_euid());
+	gid_t gid = __kgid_val(current_egid());
+	unsigned int ac_entry_id;
+	int rc;
+
+	cxi_rxtx_profile_list_lock(list);
+
+	xa_for_each(&list->xarray, index, profile) {
+		if (!profile->state.enable)
+			continue;
+
+		if ((vni & ~profile->vni_attr.ignore) == profile->vni_attr.match) {
+			tx_profile = container_of(profile,
+						  struct cxi_tx_profile,
+						  profile_common);
+
+			rc = cxi_rxtx_profile_get_ac_entry_id_by_user(
+						&tx_profile->profile_common,
+						uid, gid, netns, CXI_AC_ANY,
+						&ac_entry_id);
+			if (!rc) {
+				refcount_inc(&profile->state.refcount);
+				break;
+			}
+
+			tx_profile = ERR_PTR(rc);
+		}
+	}
+
+	cxi_rxtx_profile_list_unlock(list);
+
+	return tx_profile;
+}
+
+/**
+ * cxi_dev_get_tx_profile - Get a TX profile
+ *
+ * Check if one is already allocated and return it.
+ * For kernel users (i.e. kcxi), allocate one if not found, add
+ * an AC entry, set the TCs and enable the profile.
+ *
+ * @dev: Cassini Device
+ * @vni: VNI to find
+ *
+ * Return: tx_profile ptr on success, or a negative errno value.
+ */
+struct cxi_tx_profile *cxi_dev_get_tx_profile(struct cxi_dev *dev,
+					      unsigned int vni)
+{
+	int i;
+	int rc;
+	unsigned int ac_entry_id;
+	struct cass_dev *hw = get_cass_dev(dev);
+	struct cxi_tx_profile *tx_profile;
+	unsigned int netns;
+	struct cxi_tx_attr tx_attr = {
+		.vni_attr = {
+			.match = vni,
+			.ignore = 0
+		}
+	};
+
+	mutex_lock(&hw->tx_profile_get_lock);
+
+	tx_profile = cxi_dev_find_tx_profile(dev, vni);
+	if (tx_profile)
+		goto done;
+
+	/* For a non-root user, just report no entry found.*/
+	if (__kuid_val(current_euid())) {
+		tx_profile = ERR_PTR(-ENOENT);
+		goto done;
+	}
+
+	tx_profile = cxi_dev_alloc_tx_profile(dev, &tx_attr);
+	if (IS_ERR(tx_profile))
+		goto done;
+
+	netns = CURRENT_NETNS_ID();
+	rc = cxi_tx_profile_add_ac_entry(tx_profile, CXI_AC_UID,
+					 __kuid_val(current_euid()), 0,
+					 netns, &ac_entry_id);
+	if (rc) {
+		tx_profile = ERR_PTR(rc);
+		goto done;
+	}
+
+	/* For backward compatibility to the old service api,
+	 * enable all the TCs.
+	 */
+	for (i = CXI_TC_DEDICATED_ACCESS; i <= CXI_TC_BEST_EFFORT; i++)
+		cxi_tx_profile_set_tc(tx_profile, i, true);
+
+	rc = cxi_tx_profile_enable(dev, tx_profile);
+	if (rc)
+		tx_profile = ERR_PTR(rc);
+
+done:
+	mutex_unlock(&hw->tx_profile_get_lock);
+
+	return tx_profile;
+}
+EXPORT_SYMBOL(cxi_dev_get_tx_profile);
+
+/**
+ * cxi_tx_profile_valid_tc() - Check if a TC is valid for this TX profile
+ *
+ * @tx_profile: Profile to check against
+ * @tc: Traffic Class
+ *
+ * Return:
+ * * true if valid
+ */
+bool cxi_tx_profile_valid_tc(struct cxi_tx_profile *tx_profile, unsigned int tc)
+{
+	if (tc >= CXI_TC_MAX)
+		return false;
+
+	return test_bit(tc, tx_profile->config.tc_table);
+}
+
+/**
+ * cxi_dev_set_tx_profile_attr() - Set the TX profile attributes
+ *
+ * @dev: Cassini Device
+ * @tx_profile: TX profile to update
+ * @tx_attr: Attributes of the TX Profile
+ *
+ * Return: 0 on success, or a negative errno value.
+ */
+int cxi_dev_set_tx_profile_attr(struct cxi_dev *dev,
+				struct cxi_tx_profile *tx_profile,
+				const struct cxi_tx_attr *tx_attr)
+{
+	struct cass_dev *hw = get_cass_dev(dev);
+
+	if (tx_profile->profile_common.state.enable)
+		return -EBUSY;
+
+	if (!vni_well_formed(&tx_attr->vni_attr)) {
+		pr_debug("VNI not well formed match:%d ignore:%d\n",
+			 tx_attr->vni_attr.match, tx_attr->vni_attr.ignore);
+		return -EINVAL;
+	}
+
+	if (!unique_vni_space(hw, &hw->tx_profile_list, &tx_attr->vni_attr)) {
+		pr_debug("VNI not unique match:%d ignore:%d\n",
+			 tx_attr->vni_attr.match, tx_attr->vni_attr.ignore);
+		return -EINVAL;
+	}
+
+	tx_profile->profile_common.vni_attr.match = tx_attr->vni_attr.match;
+	tx_profile->profile_common.vni_attr.ignore = tx_attr->vni_attr.ignore;
+
+	if (!tx_attr->vni_attr.name[0])
+		strscpy(tx_profile->profile_common.vni_attr.name,
+			tx_attr->vni_attr.name,
+			ARRAY_SIZE(tx_attr->vni_attr.name));
+
+	return 0;
+}
+EXPORT_SYMBOL(cxi_dev_set_tx_profile_attr);
+
+/**
+ * cxi_tx_profile_enable() - Enable a Profile
+ *
+ * @dev: Cassini Device
+ * @tx_profile: Profile to be enabled.
+ *
+ * Return:
+ * * 0       - success
+ */
+int cxi_tx_profile_enable(struct cxi_dev *dev,
+			  struct cxi_tx_profile *tx_profile)
+{
+	if (!tx_profile)
+		return -EINVAL;
+
+	if (cxi_tx_profile_is_enabled(tx_profile))
+		return 0;
+
+	if (zero_vni(&tx_profile->profile_common.vni_attr)) {
+		pr_debug("Cannot enable profile with invalid VNI\n");
+		return -EINVAL;
+	}
+
+	// TODO: more hw setup here?
+	tx_profile->profile_common.state.enable = true;
+
+	return 0;
+}
+EXPORT_SYMBOL(cxi_tx_profile_enable);
+
+/**
+ * cxi_tx_profile_disable() - Disable a Profile
+ *
+ * @dev: Cassini Device
+ * @tx_profile: Profile to be disabled.
+ */
+void cxi_tx_profile_disable(struct cxi_dev *dev,
+			    struct cxi_tx_profile *tx_profile)
+{
+	if (!tx_profile)
+		return;
+
+	if (!cxi_tx_profile_is_enabled(tx_profile))
+		return;
+
+	tx_profile->profile_common.state.enable = false;
+	cass_clear_cps(tx_profile);
+}
+EXPORT_SYMBOL(cxi_tx_profile_disable);
+
+/**
+ * cxi_tx_profile_is_enabled() - Report TX profile is enabled
+ *
+ * @tx_profile: Profile object
+ */
+bool cxi_tx_profile_is_enabled(const struct cxi_tx_profile *tx_profile)
+{
+	if (!tx_profile)
+		return false;
+
+	return tx_profile->profile_common.state.enable;
+}
+EXPORT_SYMBOL(cxi_tx_profile_is_enabled);
+
+/**
+ * cxi_tx_profile_dec_refcount() - Decrement refcount and cleanup
+ *                                 if last reference
+ *
+ * @dev: Cassini device pointer
+ * @tx_profile: pointer to Profile
+ * @list_remove: don't remove from tx_profile_list
+ *
+ */
+int cxi_tx_profile_dec_refcount(struct cxi_dev *dev,
+				struct cxi_tx_profile *tx_profile,
+				bool list_remove)
+{
+	struct cass_dev *hw = get_cass_dev(dev);
+	int    ret;
+
+	if (!tx_profile)
+		return 0;
+
+	ret = refcount_dec_and_test(&tx_profile->profile_common.state.refcount);
+	if (!ret)
+		return -EBUSY;
+
+	cxi_tx_profile_disable(dev, tx_profile);
+	cxi_tx_profile_remove_ac_entries(tx_profile);
+
+	refcount_dec(&hw->refcount);
+
+	if (list_remove)
+		cxi_rxtx_profile_list_remove(&hw->tx_profile_list,
+					     tx_profile->profile_common.id);
+
+	kfree(tx_profile);
+	return 0;
+}
+EXPORT_SYMBOL(cxi_tx_profile_dec_refcount);
+
+/**
+ * cxi_dev_get_eth_tx_profile() - Get ethernet TX profile
+ *
+ * @dev: Cassini Device
+ *
+ * Return: tx_profile ethernet ptr
+ */
+struct cxi_tx_profile *cxi_dev_get_eth_tx_profile(struct cxi_dev *dev)
+{
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+
+	refcount_inc(&hw->eth_tx_profile.profile_common.state.refcount);
+	return &hw->eth_tx_profile;
+}
+
+/**
+ * cxi_eth_tx_profile_cleanup() - Clean up the TX profile for ethernet
+ *
+ * @hw: the device
+ */
+void cxi_eth_tx_profile_cleanup(struct cass_dev *hw)
+{
+	cxi_tx_profile_disable(&hw->cdev, &hw->eth_tx_profile);
+	refcount_dec(&hw->refcount);
+}
+EXPORT_SYMBOL(cxi_eth_tx_profile_cleanup);
+
+/**
+ * cxi_tx_profile_get_info() - Retrieve the attributes and state associated
+ *                             with this Profile
+ *
+ * @dev: Cassini Device
+ * @tx_profile: the Profile
+ * @tx_attr: location to place attributes
+ * @state: location to put state
+ *
+ * Note: vni_attr and/or state may be NULL.  If both are NULL,
+ * this return value indicates whether the Profile exists
+ * with the given Id value.
+ *
+ * Return:
+ * * 0      - success
+ * * -ENOENT - No tx_profile
+ * * -EBADR - tx_profile_id unknown
+ */
+int cxi_tx_profile_get_info(struct cxi_dev *dev,
+			    struct cxi_tx_profile *tx_profile,
+			    struct cxi_tx_attr *tx_attr,
+			    struct cxi_rxtx_profile_state *state)
+{
+	if (!tx_profile)
+		return -ENOENT;
+
+	cxi_rxtx_profile_get_info(&tx_profile->profile_common,
+				  &tx_attr->vni_attr, state);
+
+	/* TODO: gather other TX attributes */
+
+	return 0;
+}
+EXPORT_SYMBOL(cxi_tx_profile_get_info);
+
+/**
+ * cxi_tx_profile_set_tc() - Set/clear a traffic class in the TX profile
+ *
+ * @tx_profile: pointer to Profile
+ * @tc: traffic class to add/clear
+ * @set: operation - set true / clear false
+ *
+ * Return:
+ * * 0       - success
+ * * -EINVAL - tc outside of allowed range
+ */
+int cxi_tx_profile_set_tc(struct cxi_tx_profile *tx_profile, int tc, bool set)
+{
+	if (tc < CXI_TC_DEDICATED_ACCESS || tc > CXI_TC_MAX)
+		return -EINVAL;
+
+	spin_lock(&tx_profile->config.lock);
+
+	if (set)
+		set_bit(tc, tx_profile->config.tc_table);
+	else
+		clear_bit(tc, tx_profile->config.tc_table);
+
+	spin_unlock(&tx_profile->config.lock);
+
+	return 0;
+}
+EXPORT_SYMBOL(cxi_tx_profile_set_tc);
+
+static void print_tx_profile_ac_entry_info(struct cxi_tx_profile *tx_profile,
+					   struct seq_file *s)
+{
+	int i;
+	int rc;
+	size_t num_ids;
+	size_t max_ids;
+	unsigned int *ac_entry_ids = NULL;
+	enum cxi_ac_type ac_type;
+	union cxi_ac_data ac_data;
+
+	rc = cxi_tx_profile_get_ac_entry_ids(tx_profile, 0, ac_entry_ids,
+					     &num_ids);
+	if (rc && rc != -ENOSPC)
+		goto done;
+
+	ac_entry_ids = kmalloc_array(num_ids, sizeof(*ac_entry_ids),
+				     GFP_ATOMIC);
+	if (!ac_entry_ids) {
+		rc = -ENOMEM;
+		goto done;
+	}
+
+	rc = cxi_tx_profile_get_ac_entry_ids(tx_profile, num_ids, ac_entry_ids,
+					     &max_ids);
+	if (rc)
+		goto freemem;
+
+	seq_puts(s, "        AC-entries: ");
+	for (i = 0; i < num_ids; i++) {
+		rc = cxi_tx_profile_get_ac_entry_data(tx_profile,
+						      ac_entry_ids[i],
+						      &ac_type, &ac_data);
+		if (rc)
+			break;
+
+		seq_printf(s, "ID:%d type:%s uid/gid:%d%s",
+			   ac_entry_ids[i], AC_TYPE(ac_type),
+			   ac_type == CXI_AC_OPEN ? 0 : ac_data.uid,
+			   i < (num_ids - 1) ? ", " : "");
+	}
+
+freemem:
+	kfree(ac_entry_ids);
+done:
+	if (rc)
+		seq_puts(s, "\n");
+}
+
+static void print_profile(struct cxi_tx_profile *tx_profile, struct seq_file *s)
+{
+	struct cxi_rxtx_vni_attr vni_attr;
+	struct cxi_rxtx_profile_state state;
+	struct cxi_rxtx_profile *profile = &tx_profile->profile_common;
+
+	cxi_rxtx_profile_get_info(profile, &vni_attr, &state);
+	seq_printf(s, "  ID:%-2d Name:%s VNI:match:%u ignore:%u State:%s refcount:%d Exclusive-CP:%d\n",
+		   profile->id,
+		   vni_attr.name[0] ? vni_attr.name : "none",
+		   vni_attr.match, vni_attr.ignore,
+		   state.enable ? "enabled" : "disabled",
+		   refcount_read(&state.refcount),
+		   tx_profile->config.exclusive_cp);
+
+	print_tx_profile_ac_entry_info(tx_profile, s);
+}
+
+/**
+ * cxi_tx_profile_print() - Print the TX profile info
+ *
+ * @s: file ptr
+ *
+ */
+void cxi_tx_profile_print(struct seq_file *s)
+{
+	struct cass_dev *hw = s->private;
+	struct cxi_rxtx_profile_list *list = &hw->tx_profile_list;
+	struct cxi_tx_profile *tx_profile;
+	struct cxi_rxtx_profile *profile;
+	unsigned long index;
+	int tcs;
+	int i;
+
+	seq_puts(s, "\nTX profiles:\n");
+
+	cxi_rxtx_profile_list_lock(list);
+
+	xa_for_each(&list->xarray, index, profile) {
+		tx_profile = container_of(profile, struct cxi_tx_profile,
+					  profile_common);
+		print_profile(tx_profile, s);
+
+		seq_puts(s, "\n        TCs:");
+		for (i = 0, tcs = 0; i < CXI_TC_MAX; i++) {
+			if (test_bit(i, tx_profile->config.tc_table)) {
+				seq_printf(s, "%s%s", tcs ? ", " : "",
+					   cxi_tc_strs[i]);
+				tcs++;
+			}
+		}
+
+		seq_puts(s, "\n");
+	}
+
+	cxi_rxtx_profile_list_unlock(list);
+}
+
+/**
+ * cxi_tx_profile_remove_ac_entry() - disable access control to a Profile
+ *                                    by access control id.
+ *
+ * @tx_profile: pointer to Profile
+ * @ac_entry_id: id of AC entry
+ *
+ * Return:
+ * * 0       - success
+ * * -EBADR  - ac entry id unknown
+ */
+int cxi_tx_profile_remove_ac_entry(struct cxi_tx_profile *tx_profile,
+				   unsigned int ac_entry_id)
+{
+	return cxi_rxtx_profile_remove_ac_entry(&tx_profile->profile_common,
+						ac_entry_id);
+}
+EXPORT_SYMBOL(cxi_tx_profile_remove_ac_entry);
+
+/**
+ * cxi_tx_profile_get_ac_entry_ids() - get the list of AC entry ids
+ *                                     associated with a Profile
+ *
+ * @tx_profile: pointer to Profile
+ * @max_ids: size of the ac_entry_ids array
+ * @ac_entry_ids: location to store ids
+ * @num_ids: number of valid ids in ac_entry_ids array on success
+ *
+ * Return:
+ * * 0       - success
+ * * -ENOSPC - max_ids is not large enough.  num_ids holds value required.
+ */
+int cxi_tx_profile_get_ac_entry_ids(struct cxi_tx_profile *tx_profile,
+				    size_t max_ids,
+				    unsigned int *ac_entry_ids,
+				    size_t *num_ids)
+{
+	return cxi_rxtx_profile_get_ac_entry_ids(&tx_profile->profile_common,
+						 max_ids, ac_entry_ids, num_ids);
+}
+EXPORT_SYMBOL(cxi_tx_profile_get_ac_entry_ids);
+
+/**
+ * cxi_tx_profile_get_ac_entry_data() - retrieve the type and data for a
+ *                                      AC entry associated with a Profile
+ *
+ * @tx_profile: pointer to Profile
+ * @ac_entry_id: id of AC entry
+ * @ac_type: location to store AC entry type
+ * @ac_data: location to store AC data
+ *
+ * Return:
+ * * 0       - success
+ * * -EBADR  - AC entry id unknown
+ */
+int cxi_tx_profile_get_ac_entry_data(struct cxi_tx_profile *tx_profile,
+				     unsigned int ac_entry_id,
+				     enum cxi_ac_type *ac_type,
+				     union cxi_ac_data *ac_data)
+{
+	return cxi_rxtx_profile_get_ac_entry_data(&tx_profile->profile_common,
+						  ac_entry_id, ac_type, ac_data);
+}
+EXPORT_SYMBOL(cxi_tx_profile_get_ac_entry_data);
+
+/**
+ * cxi_tx_profile_get_ac_entry_id_by_data() - get the AC entry id associated
+ *                                            with a given VNI entry type and data
+ *
+ * @tx_profile: pointer to Profile
+ * @ac_type: type of AC entry to look for
+ * @ac_data: AC entry data to look for
+ * @ac_entry_id: location to store AC entry id on success
+ *
+ * Return:
+ * * 0        - success
+ * * -ENODATA - AC entry with given type&data not found
+ * * -EBADR   - invalid ac_type
+ */
+int cxi_tx_profile_get_ac_entry_id_by_data(struct cxi_tx_profile *tx_profile,
+					   enum cxi_ac_type ac_type,
+					   const union cxi_ac_data *ac_data,
+					   unsigned int *ac_entry_id)
+{
+	return cxi_rxtx_profile_get_ac_entry_id_by_data(&tx_profile->profile_common,
+							ac_type, ac_data, ac_entry_id);
+}
+EXPORT_SYMBOL(cxi_tx_profile_get_ac_entry_id_by_data);
+
+/**
+ * cxi_tx_profile_get_ac_entry_id_by_user() - retrieve the AC entry associated
+ *                                            with a Profile by user and group
+ *
+ * @tx_profile: pointer to Profile
+ * @uid: user id
+ * @gid: group id
+ * @netns: The Network Namespace id
+ * @desired_types: OR'd list of enum cxi_ac_type values
+ * @ac_entry_id: location to store AC entry id on success
+ *
+ * Return:
+ * * 0       - success
+ * * -EPERM  - no AC entries found for given uid and gid
+ * * -EBADR  - invalid desired_types
+ *
+ * Note: multiple AC entries may apply.  The priority of return is
+ * CXI_AC_UID, CXI_AC_GID, CXI_AC_OPEN.
+ */
+int cxi_tx_profile_get_ac_entry_id_by_user(struct cxi_tx_profile *tx_profile,
+					   uid_t uid,
+					   gid_t gid,
+					   unsigned int netns,
+					   cxi_ac_typeset_t desired_types,
+					   unsigned int *ac_entry_id)
+{
+	return cxi_rxtx_profile_get_ac_entry_id_by_user(&tx_profile->profile_common,
+							uid, gid, netns, desired_types,
+							ac_entry_id);
+}
+EXPORT_SYMBOL(cxi_tx_profile_get_ac_entry_id_by_user);
+
+/**
+ * cxi_tx_profile_add_ac_entry() - add an Access Control entry to
+ *                                 an existing Profile
+ *
+ * @tx_profile: TX profile to add AC Entry
+ * @type: type of AC Entry to add
+ * @uid: UID for AC Entry
+ * @gid: GID for AC Entry
+ * @netns: The Network Namespace id
+ * @ac_entry_id: Location to store resulting id
+ *
+ * Return:
+ * * 0       - success
+ * * -EEXIST - AC Entry already exists
+ */
+int cxi_tx_profile_add_ac_entry(struct cxi_tx_profile *tx_profile,
+				enum cxi_ac_type type, uid_t uid, gid_t gid,
+				unsigned int netns, unsigned int *ac_entry_id)
+{
+	union cxi_ac_data data = {};
+
+	switch (type) {
+	case CXI_AC_UID:
+		data.uid = uid;
+		break;
+	case CXI_AC_GID:
+		data.gid = gid;
+		break;
+	case CXI_AC_OPEN:
+		break;
+	case CXI_AC_NETNS:
+		data.netns = netns;
+		break;
+	default:
+		return -EDOM;
+	}
+
+	return cxi_rxtx_profile_add_ac_entry(&tx_profile->profile_common,
+					     type, &data, ac_entry_id);
+}
+EXPORT_SYMBOL(cxi_tx_profile_add_ac_entry);
+
+/**
+ * cxi_tx_profile_remove_ac_entries() - remove Access Control entries
+ *                                          from profile
+ *
+ * @tx_profile: TX profile from which to remove AC entries
+ */
+void cxi_tx_profile_remove_ac_entries(struct cxi_tx_profile *tx_profile)
+{
+	if (!tx_profile)
+		return;
+
+	cxi_ac_entry_list_destroy(&tx_profile->profile_common.ac_entry_list);
+}
+EXPORT_SYMBOL(cxi_tx_profile_remove_ac_entries);
+
+/**
+ * cxi_tx_profile_exclusive_cp() - Get tx_profile exclusive CP value
+ *
+ * @tx_profile: pointer to Profile
+ *
+ * Return: exclusive_cp value
+ */
+bool cxi_tx_profile_exclusive_cp(struct cxi_tx_profile *tx_profile)
+{
+	if (!tx_profile)
+		return false;
+
+	return tx_profile->config.exclusive_cp;
+}
+EXPORT_SYMBOL(cxi_tx_profile_exclusive_cp);
+
+/**
+ * cxi_tx_profile_set_exclusive_cp() - Set tx_profile exclusive CP value
+ *
+ * @tx_profile: pointer to Profile
+ * @exclusive_cp: Value to set
+ *
+ * Return: 0 - success, -EBUSY if not enabled
+ */
+int cxi_tx_profile_set_exclusive_cp(struct cxi_tx_profile *tx_profile,
+				    bool exclusive_cp)
+{
+	if (cxi_tx_profile_is_enabled(tx_profile))
+		return -EBUSY;
+
+	tx_profile->config.exclusive_cp = exclusive_cp;
+
+	return 0;
+}
+EXPORT_SYMBOL(cxi_tx_profile_set_exclusive_cp);

-- 
2.56.0


^ permalink raw reply	[flat|nested] 25+ messages in thread
* [PATCH 22/23] net: hpe: ss1: add the Ethernet personality
  2026-10-30 20:58 [PATCH 00/23] Subject: [PATCH net-next 00/23] net/hpe: add HPE Slingshot NIC drivers Doug Ledford
                   ` (20 preceding siblings ...)
  2026-10-30 20:59 ` [PATCH 21/23] net: hpe: ss1: add resource groups, QoS and services Doug Ledford
@ 2026-10-30 20:59 ` Doug Ledford
  2026-10-30 20:59 ` [PATCH 23/23] net: hpe: wire up the Slingshot NIC drivers Doug Ledford
  2026-10-30 22:11 ` [PATCH 00/23] Subject: [PATCH net-next 00/23] net/hpe: add HPE " Jakub Kicinski
  23 siblings, 0 replies; 25+ messages in thread
From: Doug Ledford @ 2026-10-30 20:59 UTC (permalink / raw)
  To: Slingshot Open Source Team, Nathan Chancellor, Nicolas Schier,
	Richard Cochran, Andrew Lunn, David S. Miller, Eric Dumazet,
	Jakub Kicinski, Paolo Abeni, Sumit Semwal, Christian König,
	Guenter Roeck
  Cc: linux-kernel, netdev, linux-kbuild, Doug Ledford, Sandeep Bhoot

Add cxi-eth, the Ethernet netdev personality of the NIC: netdev and
ethtool operations, hardware timestamp configuration through
ndo_hwtstamp_get/set, the RX/TX profile lists and the debugfs
interface.

The driver does not depend on any InfiniBand configuration option; it
defines the RoCE v2 UDP port locally instead of including
rdma/ib_verbs.h.

Known limitation, deferred to V2: this patch carries SR-IOV
virtual-function code (VF-to-PF mailbox requests, mailbox opcodes or VF
resource handling) from an older, incomplete version of the Cassini
SR-IOV support. V2 of this series will include the updated SR-IOV
implementation, so issues in the VF paths should be ignored for now.

checkpatch --strict (100 columns) still reports the following in this
patch. They need coordination with the internal repositories this code
is maintained in and will be fixed in V2:
- WARNING: ENOTSUPP (3), AVOID_BUG (2), SPLIT_STRING (2), BRACES (1),
  MODULE_LICENSE (1)
- CHECK: CAMELCASE (6), COMPARISON_TO_NULL (5), MULTIPLE_ASSIGNMENTS
  (2), BRACES (1), OPEN_ENDED_LINE (1), UNNECESSARY_PARENTHESES (1)

Co-developed-by: Sandeep Bhoot <sandeep.bhoot@hpe.com>
Signed-off-by: Sandeep Bhoot <sandeep.bhoot@hpe.com>
Signed-off-by: Doug Ledford <doug.ledford@hpe.com>
---
 drivers/net/ethernet/hpe/ss1/cxi_eth.c             |  443 ++++
 drivers/net/ethernet/hpe/ss1/cxi_eth_debugfs.c     |  206 ++
 drivers/net/ethernet/hpe/ss1/cxi_eth_ioctl.c       |   44 +
 drivers/net/ethernet/hpe/ss1/cxi_eth_ops.c         | 2367 ++++++++++++++++++++
 drivers/net/ethernet/hpe/ss1/cxi_ethtool.c         |  916 ++++++++
 drivers/net/ethernet/hpe/ss1/cxi_rxtx_profile.c    |  418 ++++
 .../net/ethernet/hpe/ss1/cxi_rxtx_profile_list.c   |  249 ++
 7 files changed, 4643 insertions(+)

diff --git a/drivers/net/ethernet/hpe/ss1/cxi_eth.c b/drivers/net/ethernet/hpe/ss1/cxi_eth.c
new file mode 100644
index 000000000000..f575847120f9
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cxi_eth.c
@@ -0,0 +1,443 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Cray Cassini ethernet driver
+ * © Copyright 2018-2020 Cray Inc
+ * © Copyright 2020-2021 Hewlett Packard Enterprise Development LP
+ */
+
+/* TODO:
+ *
+ * - address all the TODOs
+ * - a lot of error handling
+ * - support PCI device removal (see srcu usage in cxi_user_core.c)
+ * - find a way to cleanly pass the hash types. Modify ethtool?
+ * - add support for RSS contexts
+ */
+
+#include <linux/module.h>
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/pci.h>
+
+#include "cxi_eth.h"
+#include "cxi_eth_debugfs.h"
+
+unsigned int rss_indir_size = 64;
+module_param(rss_indir_size, int, 0444);
+MODULE_PARM_DESC(rss_indir_size, "Size of RSS indirection table");
+
+unsigned int max_rss_queues = 16;
+module_param(max_rss_queues, int, 0444);
+MODULE_PARM_DESC(max_rss_queues, "Maximum number of RSS queues (power of 2)");
+
+unsigned int max_tx_queues = 16;
+module_param(max_tx_queues, int, 0444);
+MODULE_PARM_DESC(max_tx_queues, "Maximum number of TX queues");
+
+unsigned int small_pkts_buf_size = CXI_ETH_1_MB;
+module_param(small_pkts_buf_size, uint, 0444);
+MODULE_PARM_DESC(small_pkts_buf_size, "Size of a small packets buffer (4 KiB to 1 GiB, 4 KiB aligned)");
+
+unsigned int small_pkts_buf_count = 4;
+module_param(small_pkts_buf_count, uint, 0444);
+MODULE_PARM_DESC(small_pkts_buf_count, "Number of small packets buffers (1 to 1024)");
+
+unsigned int large_pkts_buf_count = 1024;
+module_param(large_pkts_buf_count, uint, 0444);
+MODULE_PARM_DESC(large_pkts_buf_count, "Number of large packets buffers (1 to 10000)");
+
+unsigned int buffer_threshold = 256;
+module_param(buffer_threshold, uint, 0444);
+MODULE_PARM_DESC(buffer_threshold, "Ethernet packets with length greater than"
+		 " or equal to this threshold are large packets (0 to 16383)");
+
+unsigned int lpe_cdt_thresh_id = 2;
+module_param(lpe_cdt_thresh_id, uint, 0444);
+MODULE_PARM_DESC(lpe_cdt_thresh_id, "LPE append credit id to use (0 to 3)");
+
+static unsigned int rx_repost_retry_ms = 20;
+module_param(rx_repost_retry_ms, uint, 0444);
+MODULE_PARM_DESC(rx_repost_retry_ms,
+		 "Time to wait before retrying to repost an RX buffer, in ms");
+
+static struct dentry *cxieth_debug_dir;
+unsigned long rx_repost_retry_jiffies;
+
+static int idc_dma_threshold_set(const char *val, const struct kernel_param *kp)
+{
+	unsigned long num;
+	int ret;
+
+	if (!val)
+		return -EINVAL;
+
+	ret = kstrtoul(val, 0, &num);
+	if (ret || num > C_MAX_IDC_PAYLOAD_RES)
+		return -EINVAL;
+
+	*((unsigned int *)kp->arg) = num;
+
+	return 0;
+}
+
+static const struct kernel_param_ops idc_dma_threshold_ops = {
+	.set = idc_dma_threshold_set,
+	.get = param_get_uint,
+};
+
+unsigned int idc_dma_threshold = C_MAX_IDC_PAYLOAD_RES;
+module_param_cb(idc_dma_threshold, &idc_dma_threshold_ops,
+		&idc_dma_threshold, 0644);
+MODULE_PARM_DESC(idc_dma_threshold, "Ethernet packets up to this size will be"
+		 " sent inline. Larger packets will use DMA. (0 to 224)");
+
+/* List of devices registered with this client */
+static LIST_HEAD(dev_list);
+static DEFINE_MUTEX(dev_list_mutex);
+
+static const struct net_device_ops cxi_eth_netdev_ops = {
+	.ndo_open = cxi_eth_open,
+	.ndo_start_xmit = cxi_eth_start_xmit,
+	.ndo_stop = cxi_eth_close,
+	.ndo_set_mac_address = cxi_eth_mac_addr,
+	.ndo_set_rx_mode = cxi_eth_set_rx_mode,
+	.ndo_change_mtu = cxi_change_mtu,
+	.ndo_hwtstamp_get = cxi_eth_hwtstamp_get,
+	.ndo_hwtstamp_set = cxi_eth_hwtstamp_set,
+};
+
+/* Core is adding a new device */
+static int add_device(struct cxi_dev *cxi_dev)
+{
+	struct net_device *ndev;
+	struct cxi_eth *dev;
+	int rc;
+
+	/* Disable Ethernet devices on VF devices for now */
+	if (!cxi_dev->is_physfn)
+		return -ENODEV;
+
+	ndev = alloc_etherdev_mqs(sizeof(struct cxi_eth), max_tx_queues,
+				  max_rss_queues + 1);
+	if (!ndev) {
+		rc = -ENOMEM;
+		goto err;
+	}
+
+	cxi_set_ethernet_threshold(cxi_dev, buffer_threshold);
+	cxi_set_roce_rcv_seg(cxi_dev, false);
+
+	SET_NETDEV_DEV(ndev, &cxi_dev->pdev->dev);
+
+	dev = netdev_priv(ndev);
+
+	dev->txqs = kcalloc(max_tx_queues, sizeof(*dev->txqs), GFP_KERNEL);
+	if (!dev->txqs) {
+		rc = -ENOMEM;
+		goto err_free_ether;
+	}
+
+	dev->rxqs = kcalloc(max_rss_queues + 1, sizeof(*dev->rxqs), GFP_KERNEL);
+	if (!dev->rxqs) {
+		rc = -ENOMEM;
+		goto err_free_txq;
+	}
+
+	dev->ndev = ndev;
+	dev->cxi_dev = cxi_dev;
+	spin_lock_init(&dev->cq_tgt_req_lock);
+	dev->is_c2 = cassini_version(&dev->cxi_dev->prop, CASSINI_2);
+
+	ndev->netdev_ops = &cxi_eth_netdev_ops;
+	ndev->ethtool_ops = &cxi_eth_ethtool_ops;
+	ndev->watchdog_timeo = CXI_ETH_TX_TIMEOUT;
+
+	//ndev->irq = cxi_dev->pdev->irq;
+	ndev->mtu = ETH_DATA_LEN;
+	ndev->min_mtu = ETH_ZLEN;
+	ndev->max_mtu = CXI_ETH_MAX_MTU;
+	ndev->tx_queue_len = TX_QUEUE_LEN_DEFAULT;
+
+	cxi_eth_devinfo(cxi_dev, &dev->eth_info);
+
+	eth_hw_addr_set(ndev, dev->eth_info.default_mac_addr);
+
+	dev->ringparam.rx_max_pending = LARGE_PKTS_BUF_COUNT_MAX;
+	dev->ringparam.rx_mini_max_pending = num_small_packets(SMALL_PKTS_BUF_COUNT_MAX);
+	dev->ringparam.tx_max_pending = CXI_MAX_CQ_COUNT;
+
+	dev->ringparam.rx_pending = large_pkts_buf_count;
+	dev->ringparam.rx_mini_pending = num_small_packets(small_pkts_buf_count);
+	dev->ringparam.tx_pending = min_t(unsigned int, CXI_MAX_CQ_COUNT,
+					  2 * dev->ndev->tx_queue_len);
+
+	/* Used to set min_free to be equal or higher than buffer_threshold. */
+	dev->min_free = roundup_pow_of_two(buffer_threshold) >>
+		dev->eth_info.min_free_shift;
+
+	ndev->hw_features = NETIF_F_HW_CSUM | NETIF_F_GSO | NETIF_F_SG |
+		NETIF_F_GRO | NETIF_F_RXCSUM | NETIF_F_HIGHDMA |
+		NETIF_F_RXHASH;
+
+	ndev->features = ndev->hw_features;
+	ndev->vlan_features = ndev->hw_features;
+	ndev->priv_flags |= IFF_UNICAST_FLT | IFF_LIVE_ADDR_CHANGE;
+
+	rc = netif_set_real_num_queues(ndev,
+				       min_t(unsigned int, 8, max_tx_queues),
+				       min_t(unsigned int, 8, max_rss_queues));
+	if (rc)
+		goto err_free_rxq;
+
+	rc = register_netdev(ndev);
+	if (rc)
+		goto err_free_rxq;
+
+	/* If the SerDes are up, we must report the carrier as on here,
+	 * since we've already missed the link up event which was sent from
+	 * cxi-ss1
+	 */
+	if (cxi_is_link_up(cxi_dev)) {
+		/* Without the off->on transition, the ip link state will go to
+		 * UNKNOWN.
+		 */
+		netif_carrier_off(ndev);
+		netif_carrier_on(ndev);
+	} else {
+		netif_carrier_off(ndev);
+	}
+
+	device_debugfs_create(cxi_dev->name, dev, cxieth_debug_dir);
+
+	mutex_lock(&dev_list_mutex);
+	list_add_tail(&dev->dev_list, &dev_list);
+	mutex_unlock(&dev_list_mutex);
+
+	dev_info(&cxi_dev->pdev->dev, "%s[%s]: Added Ethernet device",
+		 cxi_dev->name, netdev_name(ndev));
+
+	return 0;
+
+err_free_rxq:
+	kfree(dev->rxqs);
+err_free_txq:
+	kfree(dev->txqs);
+err_free_ether:
+	free_netdev(ndev);
+err:
+	dev_err(&cxi_dev->pdev->dev,
+		"%s[]: Failure(%d): Ethernet device not added",
+		 cxi_dev->name, rc);
+	return rc;
+}
+
+/* From a given CXI device, find the ethernet device. Must be locked. */
+static struct cxi_eth *find_eth_device(const struct cxi_dev *cxi_dev)
+{
+	struct cxi_eth *dev;
+
+	list_for_each_entry_reverse(dev, &dev_list, dev_list) {
+		if (dev->cxi_dev == cxi_dev)
+			return dev;
+	}
+
+	return NULL;
+}
+
+static void remove_device(struct cxi_dev *cxi_dev)
+{
+	struct cxi_eth *dev;
+
+	/* Ethernet devices on VF devices are not added for now, so not removed */
+	if (!cxi_dev->is_physfn)
+		return;
+
+	mutex_lock(&dev_list_mutex);
+	dev = find_eth_device(cxi_dev);
+	if (dev)
+		list_del(&dev->dev_list);
+	mutex_unlock(&dev_list_mutex);
+
+	if (!dev) {
+		dev_info(&cxi_dev->pdev->dev,
+			 "%s[]: Failure(NOT FOUND): no Ethernet device to remove",
+			 cxi_dev->name);
+		return;
+	}
+
+	debugfs_remove(dev->debug);
+
+	unregister_netdev(dev->ndev);
+
+	kfree(dev->rxqs);
+	kfree(dev->txqs);
+	free_netdev(dev->ndev);
+
+	dev_info(&cxi_dev->pdev->dev, "%s[]: Removed Ethernet device",
+		 cxi_dev->name);
+}
+
+static void async_event(struct cxi_dev *cxi_dev, enum cxi_async_event event)
+{
+	struct cxi_eth *dev;
+
+	mutex_lock(&dev_list_mutex);
+	dev = find_eth_device(cxi_dev);
+	mutex_unlock(&dev_list_mutex);
+
+	if (!dev)
+		return;
+
+	netdev_dbg(dev->ndev, "got async event %d\n", event);
+
+	switch (event) {
+	case CXI_EVENT_LINK_UP:
+		netif_carrier_on(dev->ndev);
+		break;
+
+	case CXI_EVENT_LINK_DOWN:
+		netif_carrier_off(dev->ndev);
+		break;
+
+	default:
+		break;
+	}
+}
+
+static int cxi_netdev_event(struct notifier_block *this, unsigned long event,
+			    void *ptr)
+{
+	struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
+
+	if (ndev->netdev_ops->ndo_open == &cxi_eth_open &&
+	    event == NETDEV_CHANGENAME) {
+		struct cxi_eth *dev = netdev_priv(ndev);
+
+		cxi_set_eth_name(dev->cxi_dev, netdev_name(ndev));
+	}
+
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block cxi_netdev_notifier = {
+	.notifier_call = cxi_netdev_event,
+};
+
+static struct cxi_client cxiu_client = {
+	.add = add_device,
+	.remove = remove_device,
+	.async_event = async_event,
+};
+
+static int __init init(void)
+{
+	unsigned int new;
+	int ret;
+
+	if (rss_indir_size && (!is_power_of_2(rss_indir_size) ||
+			       rss_indir_size > CXI_ETH_MAX_INDIR_ENTRIES)) {
+		rss_indir_size = min_t(unsigned int,
+				       roundup_pow_of_two(rss_indir_size),
+				       CXI_ETH_MAX_INDIR_ENTRIES);
+		pr_info("Adjusting rss_indir_size to %d\n", rss_indir_size);
+	}
+
+	if (max_rss_queues > CXI_ETH_MAX_RSS_QUEUES ||
+	    !is_power_of_2(max_rss_queues)) {
+		max_rss_queues = min_t(unsigned int,
+				       roundup_pow_of_two(max_rss_queues),
+				       CXI_ETH_MAX_RSS_QUEUES);
+		pr_info("Adjusting max_rss_queues to %d\n", max_rss_queues);
+	}
+
+	if (max_tx_queues > CXI_ETH_MAX_TX_QUEUES) {
+		max_tx_queues = CXI_ETH_MAX_TX_QUEUES;
+		pr_info("Adjusting max_tx_queues to %d\n", max_tx_queues);
+	}
+
+	if (small_pkts_buf_size < PAGE_SIZE) {
+		small_pkts_buf_size = PAGE_SIZE;
+		pr_info("Adjusting small_pkts_buf_size to %u\n",
+			small_pkts_buf_size);
+	} else if (small_pkts_buf_size > CXI_ETH_1_GB) {
+		small_pkts_buf_size = CXI_ETH_1_GB;
+		pr_info("Adjusting small_pkts_buf_size to %u\n",
+			small_pkts_buf_size);
+	} else if ((small_pkts_buf_size % PAGE_SIZE) != 0) {
+		small_pkts_buf_size = roundup(small_pkts_buf_size, PAGE_SIZE);
+		pr_info("Adjusting small_pkts_buf_size to %u\n",
+			small_pkts_buf_size);
+	}
+
+	new = clamp(small_pkts_buf_count,
+		    SMALL_PKTS_BUF_COUNT_MIN, SMALL_PKTS_BUF_COUNT_MAX);
+	if (new != small_pkts_buf_count) {
+		small_pkts_buf_count = new;
+		pr_info("Adjusting small_pkts_buf_count to %u\n",
+			small_pkts_buf_count);
+	}
+
+	new = clamp(large_pkts_buf_count,
+		    LARGE_PKTS_BUF_COUNT_MIN, LARGE_PKTS_BUF_COUNT_MAX);
+	if (new != large_pkts_buf_count) {
+		large_pkts_buf_count = new;
+		pr_info("Adjusting large_pkts_buf_count to %u\n",
+			large_pkts_buf_count);
+	}
+
+	if (!buffer_threshold) {
+		pr_err("buffer_threshold must be nonzero\n");
+		return -EINVAL;
+	}
+	if (buffer_threshold > 16383) {
+		buffer_threshold = 16383;
+		pr_info("Adjusting buffer_threshold to %u\n", buffer_threshold);
+	}
+
+	if (lpe_cdt_thresh_id > 3) {
+		lpe_cdt_thresh_id = 0;
+		pr_info("Resetting lpe_cdt_thresh_id to 0\n");
+	}
+
+	if (rx_repost_retry_ms < 1 || rx_repost_retry_ms > 5000) {
+		rx_repost_retry_ms = 20;
+		pr_info("Resetting rx_repost_retry_ms to 20ms\n");
+	}
+	rx_repost_retry_jiffies = msecs_to_jiffies(rx_repost_retry_ms);
+
+	ret = register_netdevice_notifier(&cxi_netdev_notifier);
+	if (ret) {
+		pr_err("Failed to register netdevice_notifier\n");
+		return -EINVAL;
+	}
+
+	cxieth_debug_dir = device_eth_debugfs_init();
+
+	ret = cxi_register_client(&cxiu_client);
+	if (ret) {
+		pr_err("Couldn't register CXI ethernet driver\n");
+		goto out;
+	}
+
+	return 0;
+
+out:
+	debugfs_remove(cxieth_debug_dir);
+	unregister_netdevice_notifier(&cxi_netdev_notifier);
+
+	return ret;
+}
+
+static void __exit cleanup(void)
+{
+	cxi_unregister_client(&cxiu_client);
+	unregister_netdevice_notifier(&cxi_netdev_notifier);
+	debugfs_remove(cxieth_debug_dir);
+}
+
+module_init(init);
+module_exit(cleanup);
+
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Cray eXascale Interconnect (CXI) Ethernet driver");
+MODULE_AUTHOR("Cray Inc.");
diff --git a/drivers/net/ethernet/hpe/ss1/cxi_eth_debugfs.c b/drivers/net/ethernet/hpe/ss1/cxi_eth_debugfs.c
new file mode 100644
index 000000000000..310a5a6484b9
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cxi_eth_debugfs.c
@@ -0,0 +1,206 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright 2018 Hewlett Packard Enterprise Development LP */
+
+/* cxi-eth debug fs*/
+#include <linux/netdevice.h>
+#include "cxi_eth.h"
+#include "cxi_eth_debugfs.h"
+
+static u64 bucket_times[NB_BUCKETS];
+
+static void dump_rx_queue(struct seq_file *s, const struct rx_queue *rx)
+{
+	const struct bucket *bucket;
+	int i;
+
+	seq_printf(s, "  EQ=%u, PtlTE=%u TGT PRIO CQ=%u\n",
+		   rx->eq->eqn, rx->pt->id, cxi_cq_get_cqn(rx->cq_tgt_prio));
+
+	seq_printf(s, "  Preferred NUMA Node: %u\n", rx->node);
+	seq_printf(s, "  Preferred CPU: %u\n", rx->cpu);
+
+	seq_printf(s, "  list rx_unallocated=%s\n",
+		   list_empty(&rx->rx_unallocated) ? "empty" : "not empty");
+	seq_printf(s, "  list rx_ready=%s\n",
+		   list_empty(&rx->rx_ready) ? "empty" : "not empty");
+	seq_printf(s, "  list rx_in_use=%s\n",
+		   list_empty(&rx->rx_in_use) ? "empty" : "not empty");
+
+	seq_printf(s, "  rx_bufs_count=%u\n", rx->rx_bufs_count);
+	seq_printf(s, "  append_prio=%llu\n", rx->stats.append_prio);
+	seq_printf(s, "  append_req=%llu\n", rx->stats.append_req);
+	seq_printf(s, "  append_failed=%llu\n", rx->stats.append_failed);
+	seq_printf(s, "  unlinked_prio=%llu\n", rx->stats.unlinked_prio);
+	seq_printf(s, "  unlinked_req=%llu\n", rx->stats.unlinked_req);
+	seq_printf(s, "  Last bad RC for dropped fragment: %u\n",
+		   rx->last_bad_frag_drop_rc);
+
+	/* Each bucket */
+	seq_puts(s, "  bucket for napi_schedule\n");
+	bucket = &rx->eth_napi_schedule;
+	if (bucket->min_ts == UINT_MAX)
+		seq_printf(s, "    min_ts=%llu\n", 0ULL);
+	else
+		seq_printf(s, "    min_ts=%llu\n", bucket->min_ts);
+	seq_printf(s, "    max_ts=%llu\n", bucket->max_ts);
+	for (i = 0; i < NB_BUCKETS; i++) {
+		if (i < (NB_BUCKETS - 1))
+			seq_printf(s, "      < %llu ns       %llu\n",
+				   bucket_times[i],
+				   bucket->b[i]);
+		else
+			seq_printf(s, "      higher          %llu\n",
+				   bucket->b[i]);
+	}
+	seq_puts(s, "\n");
+}
+
+static void dump_cq_info(struct seq_file *s, struct cxi_cq *cq)
+{
+	seq_printf(s, "    id: %u\n", cxi_cq_get_cqn(cq));
+	seq_printf(s, "    ptrs: size32=%u, rp32=%llu, hw_rp32=%u, wp32=%llu, hw_wp32=%llu\n",
+		   cq->size32, cq->rp32, cq->status->rd_ptr * 2,
+		   cq->wp32, cq->hw_wp32);
+	seq_printf(s, "    free CQ slots: %d\n", __cxi_cq_free_slots(cq));
+}
+
+static void dump_tx_queue(struct seq_file *s, const struct tx_queue *txq,
+			  struct cxi_eth *dev)
+{
+	struct netdev_queue *dev_queue =
+		netdev_get_tx_queue(txq->dev->ndev, txq->id);
+
+	seq_printf(s, "  EQ=%u\n", txq->eq->eqn);
+	seq_puts(s,   "  eth1 CQ:\n");
+	dump_cq_info(s, txq->eth1_cq);
+	if (dev->eth2_active) {
+		seq_puts(s,   "  eth2 CQ:\n");
+		dump_cq_info(s, txq->eth2_cq);
+	}
+	seq_puts(s,   "  shared CQ:\n");
+	dump_cq_info(s, txq->shared_cq);
+
+	seq_printf(s, "  Preferred NUMA Node: %u\n", txq->node);
+	seq_printf(s, "  Preferred CPU: %u\n", txq->cpu);
+	seq_printf(s, "  polling: %llu\n", txq->stats.polling);
+	seq_printf(s, "  TXQ EQ credits: %d\n", atomic_read(&txq->dma_eq_cdt));
+	seq_printf(s, "  TXQ stopped count for full CQ: %llu\n", txq->stats.stopped);
+	seq_printf(s, "  TXQ stopped for no EQ credits: %llu\n", txq->stats.stopped_eq);
+	seq_printf(s, "  TXQ restarted count: %llu\n", txq->stats.restarted);
+	seq_printf(s, "  TXQ got busy: %llu\n", txq->stats.tx_busy);
+	seq_printf(s, "  idc: %llu\n", txq->stats.idc);
+	seq_printf(s, "  idc_bytes: %llu\n", txq->stats.idc_bytes);
+	seq_printf(s, "  dma: %llu\n", txq->stats.dma);
+	seq_printf(s, "  dma_bytes: %llu\n", txq->stats.dma_bytes);
+	seq_printf(s, "  dma_forced: %llu\n", txq->stats.dma_forced);
+	seq_printf(s, "  force_dma: %u\n", txq->force_dma);
+	seq_printf(s, "  force_dma_interval: %u\n", txq->force_dma_interval);
+	seq_printf(s, "  netdev queue state: 0x%lx\n", dev_queue->state);
+}
+
+static int dump_dev(struct seq_file *s, void *unused)
+{
+	struct cxi_eth *dev = s->private;
+	u64 min_ts = UINT_MAX;
+	u64 max_ts = 0;
+	int i;
+	int j;
+
+	seq_printf(s, "rss_indir_size=%u\n", rss_indir_size);
+	seq_printf(s, "idc_dma_threshold=%u\n", idc_dma_threshold);
+	seq_printf(s, "small_pkts_buf_size=%u\n", small_pkts_buf_size);
+	seq_printf(s, "small_pkts_buf_count=%u\n", small_pkts_buf_count);
+	seq_printf(s, "large_pkts_buf_count=%u\n", large_pkts_buf_count);
+	seq_printf(s, "num rx_pending=%u\n", dev->ringparam.rx_pending);
+	seq_printf(s, "num rx_mini_pending=%u\n", dev->ringparam.rx_mini_pending);
+	seq_printf(s, "num tx_pending=%u\n", dev->ringparam.tx_pending);
+	seq_printf(s, "num_prio_buffers=%u\n", dev->num_prio_buffers);
+	seq_printf(s, "num_req_buffers=%u\n", dev->num_req_buffers);
+
+	if (!dev->is_active)
+		return 0;
+
+	seq_printf(s, "shared TGT REQ CQ=%u\n",
+		   cxi_cq_get_cqn(dev->cq_tgt_req));
+
+	for (i = 0; i < dev->res.rss_queues; i++) {
+		seq_printf(s, "RX queue %u\n", i);
+		dump_rx_queue(s, &dev->rxqs[i]);
+	}
+
+	if (dev->res.rss_queues) {
+		seq_printf(s, "PTP RX queue %u\n", PTP_RX_Q);
+		dump_rx_queue(s, &dev->rxqs[PTP_RX_Q]);
+	}
+
+	for (i = 0; i < dev->cur_txqs; i++) {
+		seq_printf(s, "TX queue %u\n", i);
+		dump_tx_queue(s, &dev->txqs[i], dev);
+	}
+
+	/* Sum all buckets */
+	seq_puts(s, "\n");
+	seq_puts(s, "ALL buckets for RX napi_schedule\n");
+
+	for (i = 0; i < dev->res.rss_queues; i++) {
+		const struct bucket *bucket = &dev->rxqs[i].eth_napi_schedule;
+
+		if (min_ts > bucket->min_ts)
+			min_ts = bucket->min_ts;
+		if (max_ts < bucket->max_ts)
+			max_ts = bucket->max_ts;
+	}
+
+	if (min_ts == UINT_MAX)
+		min_ts = 0;
+
+	seq_printf(s, "    min_ts=%llu\n", min_ts);
+	seq_printf(s, "    max_ts=%llu\n", max_ts);
+
+	for (i = 0; i < NB_BUCKETS; i++) {
+		u64 nb = 0;
+
+		for (j = 0; j < dev->res.rss_queues; j++)
+			nb += dev->rxqs[j].eth_napi_schedule.b[i];
+
+		if (i < (NB_BUCKETS - 1))
+			seq_printf(s, "      < %llu ns       %llu\n",
+				   bucket_times[i],
+				   nb);
+		else
+			seq_printf(s, "      higher          %llu\n",
+				   nb);
+	}
+	seq_puts(s, "\n");
+
+	return 0;
+}
+
+static int dump_dev_debug_dev_open(struct inode *inode, struct file *file)
+{
+	return single_open(file, dump_dev, inode->i_private);
+}
+
+static const struct file_operations cxi_eth_fops = {
+	.owner = THIS_MODULE,
+	.open = dump_dev_debug_dev_open,
+	.read = seq_read,
+	.llseek  = seq_lseek,
+	.release = single_release,
+};
+
+struct dentry *device_eth_debugfs_init(void)
+{
+	int i;
+
+	for (i = 0; i < NB_BUCKETS; i++)
+		bucket_times[i] = 1 << i;
+	return debugfs_create_dir("cxi_eth", NULL);
+}
+
+void device_debugfs_create(char *name, struct cxi_eth *dev,
+			   struct dentry *cxieth_debug_dir)
+{
+	dev->debug = debugfs_create_file(name, 0444, cxieth_debug_dir,
+					 dev, &cxi_eth_fops);
+}
diff --git a/drivers/net/ethernet/hpe/ss1/cxi_eth_ioctl.c b/drivers/net/ethernet/hpe/ss1/cxi_eth_ioctl.c
new file mode 100644
index 000000000000..cd69e2c6fe31
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cxi_eth_ioctl.c
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Cray Cassini ethernet driver - hardware timestamp configuration.
+ * © Copyright 2021 Hewlett Packard Enterprise Development LP
+ */
+
+#include <linux/netdevice.h>
+#include <linux/net_tstamp.h>
+
+#include "cxi_eth.h"
+
+int cxi_eth_hwtstamp_get(struct net_device *ndev,
+			 struct kernel_hwtstamp_config *config)
+{
+	struct cxi_eth *dev = netdev_priv(ndev);
+
+	hwtstamp_config_to_kernel(config, &dev->tstamp_config);
+
+	return 0;
+}
+
+int cxi_eth_hwtstamp_set(struct net_device *ndev,
+			 struct kernel_hwtstamp_config *config,
+			 struct netlink_ext_ack *extack)
+{
+	struct cxi_eth *dev = netdev_priv(ndev);
+	struct hwtstamp_config cfg;
+	int rc;
+
+	hwtstamp_config_from_kernel(&cfg, config);
+
+	rc = cxi_eth_cfg_timestamp(dev->cxi_dev, &cfg);
+	if (rc)
+		return rc;
+
+	dev->tstamp_config = cfg;
+
+	dev->ptp_ts_enabled = cfg.rx_filter == HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
+
+	/* Report the configuration actually applied, e.g. TX forced on. */
+	hwtstamp_config_to_kernel(config, &cfg);
+
+	return 0;
+}
diff --git a/drivers/net/ethernet/hpe/ss1/cxi_eth_ops.c b/drivers/net/ethernet/hpe/ss1/cxi_eth_ops.c
new file mode 100644
index 000000000000..d19a6a27aa23
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cxi_eth_ops.c
@@ -0,0 +1,2367 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Cray Cassini ethernet driver
+ * © Copyright 2018-2020 Cray Inc
+ * © Copyright 2020 Hewlett Packard Enterprise Development LP
+ */
+
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/etherdevice.h>
+#include <linux/if_vlan.h>
+#include <linux/ip.h>
+#include <linux/ipv6.h>
+#include <linux/netdevice.h>
+#include <linux/pci.h>
+#include <linux/tcp.h>
+#include <linux/udp.h>
+#include <linux/vmalloc.h>
+#include <net/ipv6.h>
+
+#include "cxi_eth.h"
+#include "cxi_core.h"
+
+#define ROCE_V2_UDP_DPORT	4791
+
+static unsigned int tx_eq_count;
+module_param(tx_eq_count, uint, 0444);
+MODULE_PARM_DESC(tx_eq_count, "Override the number of entries in transmit event queue");
+
+static int cxi_rx_eth_poll(struct napi_struct *napi, int budget);
+static void rx_eq_cb(void *context);
+
+static void err_eq_cb(void *context)
+{
+	struct cxi_eth *dev = context;
+	const union c_event *event;
+
+	while ((event = cxi_eq_get_event(dev->err_eq))) {
+		switch (event->hdr.event_type) {
+		case C_EVENT_COMMAND_FAILURE:
+			netdev_warn(dev->ndev, "%s CQ %u disabled\n",
+				    event->cmd_fail.is_target ?
+				    "target" : "transmit",
+				    event->cmd_fail.cq_id);
+			break;
+		default:
+			netdev_warn(dev->ndev, "Unhandled event %u, rc %d\n",
+				    event->hdr.event_type,
+				    event->hdr.return_code);
+			print_hex_dump(KERN_INFO,
+				       "cxi eth unexpected tx event: ",
+				       DUMP_PREFIX_ADDRESS, 16, 1, event,
+				       (8 << event->hdr.event_size), false);
+		}
+
+		cxi_eq_ack_events(dev->err_eq);
+	}
+
+	cxi_eq_int_enable(dev->err_eq);
+}
+
+static void cancel_tx_tstamp(struct cxi_eth *dev, struct sk_buff *skb)
+{
+	if (cmpxchg(&dev->tstamp_skb, skb, NULL) == skb)
+		skb_shinfo(skb)->tx_flags &= ~SKBTX_IN_PROGRESS;
+}
+
+static void finalize_tx_tstamp(struct cxi_eth *dev, struct sk_buff *skb)
+{
+	struct skb_shared_hwtstamps tstamps;
+	int rc;
+
+	if (skb != dev->tstamp_skb) {
+		netdev_warn_once(dev->ndev, "skb != dev->tstamp_skb : %p != %p",
+				 skb, dev->tstamp_skb);
+		return;
+	}
+
+	rc = cxi_eth_get_tx_timestamp(dev->cxi_dev, &tstamps);
+	if (!rc)
+		skb_tstamp_tx(skb, &tstamps);
+
+	/* Release timestamp slot */
+	cmpxchg(&dev->tstamp_skb, skb, NULL);
+}
+
+static void unmap_frags(struct device *dma_dev, struct sk_buff *skb)
+{
+	struct cb_data *cb = (struct cb_data *)skb->cb;
+	int i;
+
+	for (i = 0; i < cb->num_frags; i++) {
+		int len;
+
+		if (i < MAX_CB_LEN) {
+			len = cb->dma_len[i];
+		} else {
+			const skb_frag_t *frag = &skb_shinfo(skb)->frags[i - 1];
+
+			len = skb_frag_size(frag);
+		}
+
+		dma_unmap_single(dma_dev, cb->dma_addr[i], len, DMA_TO_DEVICE);
+	}
+}
+
+/* Prepare the segments in the command, mapping them for DMA */
+static int prepare_frags(struct device *dma_dev, struct sk_buff *skb,
+			 struct c_dma_eth_cmd *dma_eth)
+{
+	struct cb_data *cb = (struct cb_data *)skb->cb;
+	int i;
+
+	BUILD_BUG_ON(sizeof(struct cb_data) > sizeof(skb->cb));
+
+	dma_eth->num_segments = 1 + skb_shinfo(skb)->nr_frags;
+
+	if (skb_shinfo(skb)->nr_frags) {
+		unsigned int segnum = 0;
+
+		cb->dma_len[segnum] = dma_eth->len[segnum] = skb_headlen(skb);
+		segnum++;
+
+		for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
+			const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
+
+			dma_eth->len[segnum] = skb_frag_size(frag);
+
+			if (segnum < MAX_CB_LEN)
+				cb->dma_len[segnum] = dma_eth->len[segnum];
+
+			segnum++;
+		}
+	} else {
+		cb->dma_len[0] = skb->len;
+		dma_eth->len[0] = skb->len;
+	}
+
+	cb->num_frags = 0;
+
+	for (i = 0; i < dma_eth->num_segments; i++) {
+		dma_addr_t dma_addr;
+
+		if (i == 0) {
+			dma_addr = dma_map_single(dma_dev, skb->data,
+						  dma_eth->len[i], DMA_TO_DEVICE);
+		} else {
+			const skb_frag_t *frag = &skb_shinfo(skb)->frags[i - 1];
+
+			dma_addr = dma_map_single(dma_dev, skb_frag_address(frag),
+						  dma_eth->len[i], DMA_TO_DEVICE);
+		}
+
+		if (dma_mapping_error(dma_dev, dma_addr)) {
+			unmap_frags(dma_dev, skb);
+			return -ENOMEM;
+		}
+
+		cb->dma_addr[i] = dma_eth->addr[i] = dma_addr;
+		cb->num_frags++;
+	}
+
+	return 0;
+}
+
+/* A packet was sent with a DMA command. Returns the number of EQ
+ * credits to return to the TX queue.
+ */
+static unsigned int eth_complete(struct cxi_eth *dev, struct tx_queue *txq,
+				 const union c_event *event, int budget,
+				 unsigned int *pkts, unsigned int *bytes)
+{
+	struct net_device *ndev = dev->ndev;
+	struct sk_buff *skb;
+	enum c_return_code return_code;
+
+	if (event->hdr.event_size == C_EVENT_SIZE_16_BYTE) {
+		return_code = event->init_short.return_code;
+		skb = (void *)event->init_short.user_ptr;
+	} else {
+		return_code = event->init_long.return_code;
+		skb = (void *)event->init_long.user_ptr;
+	}
+
+	if (skb == NULL) {
+		/* Bad IDC commands will generate a SEND event on error. */
+		if (return_code == C_RC_OK)
+			netdev_warn_once(dev->ndev,
+					 "Successful command with NULL skb\n");
+
+		ndev->stats.tx_dropped++;
+
+		return 0;
+	}
+
+	if (return_code == C_RC_OK) {
+		ndev->stats.tx_packets++;
+		ndev->stats.tx_bytes += skb->len;
+		*pkts += 1;
+		*bytes += skb->len;
+	} else {
+		netdev_err_once(dev->ndev,
+				"DMA command failed to complete: %d\n",
+				return_code);
+		ndev->stats.tx_dropped++;
+	}
+
+	if (skb_shinfo(skb)->tx_flags & SKBTX_IN_PROGRESS)
+		finalize_tx_tstamp(dev, skb);
+
+	unmap_frags(&dev->cxi_dev->pdev->dev, skb);
+
+	napi_consume_skb(skb, budget);
+
+	return 1;
+}
+
+static int cxi_tx_eth_poll(struct napi_struct *napi, int budget)
+{
+	struct tx_queue *txq = container_of(napi, struct tx_queue, napi);
+	struct cxi_eth *dev = txq->dev;
+	struct netdev_queue *dev_queue =
+		netdev_get_tx_queue(dev->ndev, txq->id);
+	const union c_event *event;
+	int work_done = 0;
+	unsigned int event_count = 0;
+	unsigned int pkts = 0;
+	unsigned int bytes = 0;
+	unsigned int cdts = 0;
+
+	txq->stats.polling++;
+
+	while (work_done < budget && (event = cxi_eq_get_event(txq->eq))) {
+		switch (event->hdr.event_type) {
+		case C_EVENT_SEND:
+			cdts += eth_complete(dev, txq, event, budget, &pkts, &bytes);
+			work_done++;
+			break;
+		default:
+			netdev_warn(dev->ndev, "Unhandled event %u, rc %d\n",
+				    event->hdr.event_type,
+				    event->hdr.return_code);
+			print_hex_dump(KERN_INFO,
+				       "cxi eth unexpected tx event: ",
+				       DUMP_PREFIX_ADDRESS, 16, 1, event,
+				       (8 << event->hdr.event_size), false);
+		}
+
+		event_count++;
+		if (event_count == 16) {
+			cxi_eq_int_disable(txq->eq);
+			event_count = 0;
+
+			atomic_add(cdts, &txq->dma_eq_cdt);
+			cdts = 0;
+		}
+	}
+
+	BUG_ON(work_done > budget);
+
+	/* Check to see if the TX queue needs to be re-enabled. */
+	if (netif_tx_queue_stopped(dev_queue)) {
+		if (__cxi_cq_free_slots(txq->shared_cq) >= 16 &&
+		    __cxi_cq_free_slots(txq->eth1_cq) >= 16 &&
+		    (!dev->eth2_active || __cxi_cq_free_slots(txq->eth2_cq) >= 16) &&
+		    atomic_read(&txq->dma_eq_cdt) > 0) {
+			txq->stats.restarted++;
+			netif_tx_wake_queue(dev_queue);
+		}
+	}
+
+	if (pkts)
+		netdev_tx_completed_queue(dev_queue, pkts, bytes);
+
+	if (work_done < budget && napi_complete_done(napi, work_done)) {
+		/* Ack events and re-enable the EQ interrupt. */
+		cxi_eq_int_enable(txq->eq);
+	} else if (event_count) {
+		cxi_eq_int_disable(txq->eq);
+	}
+
+	atomic_add(cdts, &txq->dma_eq_cdt);
+
+	return work_done;
+}
+
+static void tx_eq_cb(void *context)
+{
+	struct tx_queue *tx = context;
+
+	napi_schedule(&tx->napi);
+}
+
+void enable_tx_queue(struct tx_queue *tx)
+{
+	napi_enable(&tx->napi);
+	cxi_eq_int_enable(tx->eq);
+}
+
+void disable_tx_queue(struct tx_queue *tx)
+{
+	cxi_eq_int_disable(tx->eq);
+	napi_disable(&tx->napi);
+}
+
+void free_tx_queue(struct tx_queue *tx)
+{
+	netif_napi_del(&tx->napi);
+
+	tx->untagged_cq = NULL;
+
+	cxi_cq_free(tx->shared_cq);
+	tx->shared_cq = NULL;
+
+	cxi_cq_free(tx->eth1_cq);
+	tx->eth1_cq = NULL;
+
+	if (tx->eth2_cq) {
+		cxi_cq_free(tx->eth2_cq);
+		tx->eth2_cq = NULL;
+	}
+
+	cxi_eq_free(tx->eq);
+	tx->eq = NULL;
+
+	if (is_vmalloc_addr(tx->eq_attr.queue))
+		cxi_unmap(tx->eq_md);
+	kvfree(tx->eq_attr.queue);
+	tx->eq_attr.queue = NULL;
+
+	tx->dev = NULL;
+}
+
+static void cxi_eth_get_node_cpu(struct cxi_eth *dev, unsigned int queue_id,
+				 unsigned int *queue_node,
+				 unsigned int *queue_cpu)
+{
+	int node;
+	int cpu;
+	int cpu_offset;
+	const struct cpumask *cpus;
+	int cpu_count;
+	int num_cpu_nodes = 0;
+	int i;
+
+	/* Figure out how many numa nodes are online and contain
+	 * CPUs. Apparently linux will reorder the nodes so that the
+	 * empty ones are at the end of the list. If it's not the
+	 * case, then further changes will be needed.
+	 */
+	for_each_online_node(node) {
+		cpus = cpumask_of_node(node);
+		if (!cpumask_empty(cpus))
+			num_cpu_nodes++;
+	}
+	if (!num_cpu_nodes || dev_to_node(&dev->cxi_dev->pdev->dev) < 0)
+		goto fallback;
+
+	/* Round robin queues across all the nodes in the system instead of
+	 * overloading 1 node with multiple queues. Favor the local node to
+	 * start with.
+	 */
+	node = (dev_to_node(&dev->cxi_dev->pdev->dev) + queue_id) % num_cpu_nodes;
+	if (!node_online(node)) {
+		/* For sanity, but that shouldn't be possible. */
+		netdev_err(dev->ndev, "Node %u not online. Defaulting to %u\n",
+			   node, dev_to_node(&dev->cxi_dev->pdev->dev));
+		node = dev_to_node(&dev->cxi_dev->pdev->dev);
+	}
+
+	/* If the queue ID exceeds the number of nodes, multiple queues will be
+	 * mapped to the same node. For this case, round robin queues within the
+	 * node.
+	 */
+	cpus = cpumask_of_node(node);
+	if (cpumask_empty(cpus)) {
+		/* For sanity, but that shouldn't be possible. */
+		netdev_err(dev->ndev, "Node %u is empty. Defaulting to all cpus.\n",
+			   node);
+		cpus = cpu_all_mask;
+	}
+
+	cpu_count = 0;
+	for_each_cpu(cpu, cpus) {
+		if (cpu_is_offline(cpu))
+			continue;
+		/* We only care about CPUs which belong to the NUMA node. */
+		if (cpumask_test_cpu(cpu, cpus))
+			cpu_count++;
+	}
+
+	if (!cpu_count)
+		goto fallback;
+	cpu_offset = (queue_id / num_cpu_nodes) % cpu_count;
+	i = 0;
+	for_each_cpu(cpu, cpus) {
+		if (cpu_is_offline(cpu))
+			continue;
+		if (cpumask_test_cpu(cpu, cpus)) {
+			if (i == cpu_offset)
+				break;
+			i++;
+		}
+	}
+
+	if (cpu < nr_cpu_ids)
+		goto out;
+
+fallback:
+	cpu = cpumask_local_spread(queue_id,
+				   dev_to_node(&dev->cxi_dev->pdev->dev));
+out:
+	*queue_node = cpu_to_node(cpu);
+	*queue_cpu = cpu;
+}
+
+int alloc_tx_queue(struct cxi_eth *dev, unsigned int id)
+{
+	struct tx_queue *tx = &dev->txqs[id];
+	struct cxi_cq_alloc_opts cq_alloc_opts = {};
+	struct c_cstate_cmd c_state = {};
+	unsigned int eq_count;
+	int rc;
+
+	memset(tx, 0, sizeof(*tx));
+
+	cxi_eth_get_node_cpu(dev, id, &tx->node, &tx->cpu);
+
+	tx->force_dma_interval = dev->ndev->tx_queue_len / 8;
+	tx->force_dma = tx->force_dma_interval;
+
+	cq_alloc_opts.count = min_t(unsigned int, CXI_MAX_CQ_COUNT,
+				    2 * dev->ndev->tx_queue_len);
+
+	eq_count = tx_eq_count ? tx_eq_count : 4 * cq_alloc_opts.count;
+	tx->eq_attr.queue_len = PAGE_ALIGN(C_EE_CFG_ECB_SIZE * eq_count);
+
+	tx->eq_attr.queue = kvzalloc_node(tx->eq_attr.queue_len, GFP_KERNEL,
+					  tx->node);
+	if (!tx->eq_attr.queue) {
+		rc = -ENOMEM;
+		goto err;
+	}
+
+	/* Keep a 5% margin for IDC send errors if they ever happen. */
+	atomic_set(&tx->dma_eq_cdt, (eq_count * 95) / 100);
+
+	if (is_vmalloc_addr(tx->eq_attr.queue)) {
+		tx->eq_md = cxi_map(dev->lni, (uintptr_t)tx->eq_attr.queue,
+				    tx->eq_attr.queue_len, CXI_MAP_WRITE, NULL);
+		if (IS_ERR(tx->eq_md)) {
+			rc = PTR_ERR(tx->eq_md);
+			goto err_free_eq_buf;
+		}
+	} else {
+		tx->eq_attr.flags = CXI_EQ_PASSTHROUGH;
+	}
+
+	tx->eq_attr.cpu_affinity = tx->cpu;
+	tx->eq = cxi_eq_alloc(dev->lni, tx->eq_md, &tx->eq_attr, tx_eq_cb, tx,
+			      NULL, NULL);
+	if (IS_ERR(tx->eq)) {
+		rc = PTR_ERR(tx->eq);
+		goto err_unmap_eq_buf;
+	}
+
+	cq_alloc_opts.flags = CXI_CQ_IS_TX | CXI_CQ_TX_ETHERNET;
+	cq_alloc_opts.lcid = dev->eth1_cp->lcid;
+	tx->eth1_cq = cxi_cq_alloc(dev->lni, dev->err_eq, &cq_alloc_opts,
+				   tx->node);
+	if (IS_ERR(tx->eth1_cq)) {
+		rc = PTR_ERR(tx->eth1_cq);
+		goto err_free_eq;
+	}
+
+	cq_alloc_opts.lcid = dev->shared_cp->lcid;
+	tx->shared_cq = cxi_cq_alloc(dev->lni, dev->err_eq, &cq_alloc_opts,
+				     tx->node);
+	if (IS_ERR(tx->shared_cq)) {
+		rc = PTR_ERR(tx->shared_cq);
+		goto err_free_eth1_cq;
+	}
+
+	if (dev->eth2_active) {
+		cq_alloc_opts.lcid = dev->eth2_cp->lcid;
+		tx->eth2_cq = cxi_cq_alloc(dev->lni, dev->err_eq,
+					   &cq_alloc_opts, tx->node);
+
+		if (IS_ERR(tx->eth2_cq)) {
+			rc = PTR_ERR(tx->eth2_cq);
+			goto err_free_shared_cq;
+		}
+	}
+
+	/* Add C_STATE command. */
+	c_state.eq = tx->eq->eqn;
+	c_state.restricted = 1;
+	c_state.event_success_disable = 1;
+	c_state.event_send_disable = 1;
+
+	rc = cxi_cq_emit_c_state(tx->eth1_cq, &c_state);
+	if (rc) {
+		netdev_err(dev->ndev, "Command emit failed: %d\n", rc);
+		goto err_free_eth2_cq;
+	}
+
+	cxi_cq_ring(tx->eth1_cq);
+
+	rc = cxi_cq_emit_c_state(tx->shared_cq, &c_state);
+	if (rc) {
+		netdev_err(dev->ndev, "Command emit failed: %d\n", rc);
+		goto err_free_eth2_cq;
+	}
+
+	cxi_cq_ring(tx->shared_cq);
+
+	if (dev->eth2_active) {
+		rc = cxi_cq_emit_c_state(tx->eth2_cq, &c_state);
+		if (rc) {
+			netdev_err(dev->ndev, "Command emit failed: %d\n", rc);
+			goto err_free_eth2_cq;
+		}
+
+		cxi_cq_ring(tx->eth2_cq);
+	}
+
+	/* Determine which tx_queue CQ should be used for untagged traffic */
+	if (dev->cxi_dev->untagged_eth_pcp == dev->eth1_pcp)
+		tx->untagged_cq = tx->eth1_cq;
+	else if (dev->eth2_active &&
+		 dev->cxi_dev->untagged_eth_pcp == dev->eth2_pcp)
+		tx->untagged_cq = tx->eth2_cq;
+	else
+		tx->untagged_cq = tx->shared_cq;
+
+	tx->dev = dev;
+	tx->id = id;
+
+	NETIF_NAPI_ADD_TX(dev->ndev, &tx->napi, cxi_tx_eth_poll);
+
+	return 0;
+
+err_free_eth2_cq:
+	if (dev->eth2_active) {
+		cxi_cq_free(tx->eth2_cq);
+		tx->eth2_cq = NULL;
+	}
+err_free_shared_cq:
+	cxi_cq_free(tx->shared_cq);
+	tx->shared_cq = NULL;
+err_free_eth1_cq:
+	cxi_cq_free(tx->eth1_cq);
+	tx->eth1_cq = NULL;
+err_free_eq:
+	cxi_eq_free(tx->eq);
+	tx->eq = NULL;
+err_unmap_eq_buf:
+	if (is_vmalloc_addr(tx->eq_attr.queue))
+		cxi_unmap(tx->eq_md);
+err_free_eq_buf:
+	kvfree(tx->eq_attr.queue);
+	tx->eq_attr.queue = NULL;
+err:
+	return rc;
+}
+
+/* Free the receive buffers on the ready lists.
+ * TODO: when closing the device, make sure all buffers are back on
+ * the ready lists.
+ */
+static void free_rx_buffers(struct rx_queue *rx)
+{
+	struct cxi_eth *dev = rx->dev;
+	struct rx_buffer *buf;
+
+	/* Move all buffers to the ready list and free them. */
+	list_splice_init(&rx->rx_in_use, &rx->rx_ready);
+
+	while ((buf = list_first_entry_or_null(&rx->rx_ready,
+					       struct rx_buffer, buf_list))) {
+		list_del(&buf->buf_list);
+		list_add_tail(&buf->buf_list, &rx->rx_unallocated);
+
+		if (buf->ptl_list == C_PTL_LIST_PRIORITY) {
+			if (buf->page) {
+				dma_unmap_page(&dev->cxi_dev->pdev->dev,
+					       dma_unmap_addr(buf, mapping),
+				PAGE_SIZE, DMA_FROM_DEVICE);
+
+				for (; buf->posted_count > 0; buf->posted_count--)
+					put_page(buf->page);
+
+				__free_page(buf->page);
+				buf->page = NULL;
+			}
+		} else {
+			cxi_unmap(buf->md);
+			kvfree(buf->data);
+		}
+		buf->data = NULL;
+	}
+}
+
+/* Allocate and map the receive buffers. */
+static int alloc_rx_buffers(struct rx_queue *rx, unsigned int count,
+			    enum c_ptl_list ptl_list)
+{
+	int rc;
+	unsigned int i;
+	struct rx_buffer *buf;
+	unsigned int data_size;
+	struct cxi_eth *dev = rx->dev;
+	int numa_node = dev_to_node(&dev->cxi_dev->pdev->dev);
+
+	if (ptl_list == C_PTL_LIST_PRIORITY)
+		data_size = dev->eth_info.max_segment_size;
+	else
+		data_size = small_pkts_buf_size;
+
+	for (i = 0; i < count; i++) {
+		buf = list_first_entry_or_null(&rx->rx_unallocated,
+					       struct rx_buffer, buf_list);
+		if (!buf)
+			break;
+
+		list_del(&buf->buf_list);
+
+		buf->data_size = data_size;
+
+		if (ptl_list == C_PTL_LIST_REQUEST) {
+			buf->data = kvzalloc_node(buf->data_size, GFP_KERNEL,
+						  numa_node);
+			if (!buf->data)
+				goto out_requeue;
+
+			buf->md = cxi_map(dev->lni, (uintptr_t)buf->data,
+					  buf->data_size, CXI_MAP_WRITE, NULL);
+			if (IS_ERR(buf->md)) {
+				rc = PTR_ERR(buf->md);
+				netdev_err(dev->ndev,
+					   "cxi_map failed: %d\n", rc);
+				kvfree(buf->data);
+				buf->data = NULL;
+				goto out_requeue;
+			}
+		}
+
+		/* Allocated. Enqueue on the corresponding ready list. */
+		buf->ptl_list = ptl_list;
+
+		list_add_tail(&buf->buf_list, &rx->rx_ready);
+
+		if (ptl_list == C_PTL_LIST_PRIORITY)
+			dev->num_prio_buffers++;
+		else
+			dev->num_req_buffers++;
+	}
+
+	return i;
+
+out_requeue:
+	list_add_tail(&buf->buf_list, &rx->rx_unallocated);
+
+	return i;
+}
+
+/* Re-post an RX buffer. The buffer is on the rx_ready list. */
+static int append_rx_buffer(struct rx_queue *rx, struct rx_buffer *buf,
+			    gfp_t gfp)
+{
+	int rc;
+	dma_addr_t mapping;
+	struct page *page;
+	struct cxi_eth *dev = rx->dev;
+	struct c_target_cmd cmd = {
+		.command.opcode = C_CMD_TGT_APPEND,
+		.ptl_list = buf->ptl_list,
+		.ptlte_index = rx->pt->id,
+		.op_put = 1,
+		.no_truncate = 1,
+		.event_link_disable = 1,
+		.length = buf->data_size,
+		.buffer_id = buf->id,
+		.unrestricted_end_ro = 1,
+		.unrestricted_body_ro = 1,
+		.event_unlink_disable = 1,
+	};
+	int i;
+	size_t posted_offset;
+
+	if (buf->ptl_list == C_PTL_LIST_PRIORITY) {
+		cmd.use_once = 1;
+
+		if (buf->page == NULL) {
+			page = alloc_page(gfp);
+			if (!page) {
+				rc = -ENOMEM;
+				goto fail;
+			}
+
+			mapping = dma_map_page(&dev->cxi_dev->pdev->dev, page,
+					       0, PAGE_SIZE,
+					       DMA_FROM_DEVICE);
+			if (dma_mapping_error(&dev->cxi_dev->pdev->dev,
+					      mapping)) {
+				__free_page(page);
+				rc = -EIO;
+				goto fail;
+			}
+			buf->page = page;
+			buf->mapping = mapping;
+		}
+
+		cmd.start = buf->mapping;
+		cmd.lac = dev->phys_lac;
+		buf->cur_offset = 0;
+		buf->posted_count = 0;
+		posted_offset = 0;
+
+		for (i = 0; i < rx->page_chunks; i++) {
+			cmd.start = buf->mapping + posted_offset;
+
+			rc = cxi_cq_emit_target(rx->cq_tgt_prio, &cmd);
+			if (rc)
+				goto fail;
+
+			get_page(buf->page);
+			buf->posted_count++;
+			posted_offset += dev->eth_info.max_segment_size;
+			rx->stats.append_prio++;
+		}
+	} else {
+		cmd.manage_local = 1;
+		cmd.min_free = dev->min_free;
+		cmd.start = buf->md->iova;
+		cmd.lac = buf->md->lac;
+
+		spin_lock_bh(&dev->cq_tgt_req_lock);
+		rc = cxi_cq_emit_target(dev->cq_tgt_req, &cmd);
+		spin_unlock_bh(&dev->cq_tgt_req_lock);
+
+		rx->stats.append_req++;
+	}
+
+fail:
+	if (rc) {
+		netdev_err_once(dev->ndev, "Append failed on list %d: %d\n",
+				buf->ptl_list, rc);
+		rx->stats.append_failed++;
+	} else {
+		list_del(&buf->buf_list);
+		list_add_tail(&buf->buf_list, &rx->rx_in_use);
+	}
+
+	return rc;
+}
+
+/* Append all ready RX buffers to the portal.
+ * Return the number of buffers appended.
+ */
+int post_rx_buffers(struct rx_queue *rx, gfp_t gfp)
+{
+	struct cxi_eth *dev = rx->dev;
+	unsigned int posted = 0;
+	unsigned int count = 0;
+	struct rx_buffer *buf;
+	struct rx_buffer *tmp;
+	int rc = 0;
+
+	list_for_each_entry_safe(buf, tmp, &rx->rx_ready, buf_list) {
+		rc = append_rx_buffer(rx, buf, gfp);
+		if (rc)
+			break;
+
+		/* Ring the CQ regularly */
+		if (buf->ptl_list == C_PTL_LIST_PRIORITY) {
+			posted++;
+			if (posted == 16) {
+				cxi_cq_ring(rx->cq_tgt_prio);
+				posted = 0;
+			}
+		} else {
+			spin_lock_bh(&dev->cq_tgt_req_lock);
+			cxi_cq_ring(dev->cq_tgt_req);
+			spin_unlock_bh(&dev->cq_tgt_req_lock);
+		}
+
+		count++;
+	}
+
+	if (posted)
+		cxi_cq_ring(rx->cq_tgt_prio);
+
+	return rc ? rc : count;
+}
+
+#define EXPECTED_TARGET_EVENT_SIZE (sizeof(struct c_event_target_enet))
+#define MIN_PACKET_SIZE 64U
+size_t get_rxq_eq_buf_size(struct cxi_eth *dev)
+{
+	size_t num_events;
+
+	/* Calculate the maximum number of events which could occur based on
+	 * RX buffer configuration.
+	 */
+	num_events = dev->ringparam.rx_pending +
+		(small_pkts_buf_count * (small_pkts_buf_size / MIN_PACKET_SIZE));
+
+	return ALIGN((num_events * EXPECTED_TARGET_EVENT_SIZE) +
+		     C_EE_CFG_ECB_SIZE, PAGE_SIZE);
+}
+
+/* CXI_CQ_UPDATE_HIGH_FREQ_EMPTY updates the read pointer every 16 slots.
+ * Since a read pointer status update could be missed on CQ wrap, 2 * 16 slots
+ * should be included as overhead.
+ *
+ * In addition, 4 event slots are reserved for status updates. Thus, an
+ * additional 4 slots should be included as overhead.
+ */
+#define TGT_CQ_OVERHEAD_COUNT ((2U * 16U) + 4U)
+
+int alloc_rx_queue(struct cxi_eth *dev, unsigned int id)
+{
+	int i;
+	int rc;
+	static const struct cxi_pt_alloc_opts pt_alloc_opts = {
+		.en_flowctrl = 1, /* TODO: needed for ethernet? */
+		.ethernet = 1,
+		.do_space_check = 1,
+		.lossless = 1,
+	};
+	struct cxi_eq_attr eq_attr = {};
+	struct cxi_cq_alloc_opts cq_alloc_opts = {};
+	struct rx_queue *rx = &dev->rxqs[id];
+	unsigned int prio_bufs;
+
+	memset(rx, 0, sizeof(*rx));
+
+	cxi_eth_get_node_cpu(dev, id, &rx->node, &rx->cpu);
+
+	rx->dev = dev;
+	rx->id = id;
+	rx->last_bad_frag_drop_rc = C_RC_OK;
+	rx->eth_napi_schedule.min_ts = UINT_MAX;
+
+	INIT_LIST_HEAD(&rx->rx_unallocated);
+	INIT_LIST_HEAD(&rx->rx_ready);
+	INIT_LIST_HEAD(&rx->rx_in_use);
+
+	/* Packets landing on priority buffers will be chopped into
+	 * max_segment_size pieces. Since pages are priority buffers, to avoid
+	 * wasting page memory, pages should be chunked in max_segment_size
+	 * pieces and posted.
+	 */
+	rx->page_chunks = PAGE_SIZE / dev->eth_info.max_segment_size;
+
+	/* The number of priority buffers, not pages, is the size of the RX
+	 * ring divided by number of page chunks. If the
+	 * PAGE_SIZE ==  max_segment_size, the number of prio_bufs will equal
+	 * rx_pending.
+	 */
+	prio_bufs = DIV_ROUND_UP(dev->ringparam.rx_pending, rx->page_chunks);
+	rx->rx_bufs_count = prio_bufs + small_pkts_buf_count;
+	rx->rx_bufs = vzalloc(rx->rx_bufs_count * sizeof(*rx->rx_bufs));
+	if (rx->rx_bufs == NULL) {
+		rc = -ENOMEM;
+		goto err;
+	}
+
+	for (i = 0; i < rx->rx_bufs_count; i++) {
+		struct rx_buffer *buf = &rx->rx_bufs[i];
+
+		buf->id = i;
+		list_add_tail(&buf->buf_list, &rx->rx_unallocated);
+	}
+
+	/* Allocate RX buffers */
+	rc = alloc_rx_buffers(rx, prio_bufs, C_PTL_LIST_PRIORITY);
+	if (rc == 0) {
+		netdev_info(dev->ndev, "Cannot allocate RX priority buffers\n");
+		rc = -ENOMEM;
+		goto err_free_rx_bufs;
+	} else if (rc != prio_bufs) {
+		netdev_info(dev->ndev,
+			    "Only allocated %d RX priority buffers out of %u requested\n",
+			    rc, prio_bufs);
+	}
+
+	rc = alloc_rx_buffers(rx, small_pkts_buf_count, C_PTL_LIST_REQUEST);
+	if (rc == 0) {
+		netdev_info(dev->ndev, "Cannot allocate RX request buffers\n");
+		rc = -ENOMEM;
+		goto err_free_buffers;
+	} else if (rc != small_pkts_buf_count) {
+		netdev_info(dev->ndev,
+			    "Only allocated %d RX request buffers out of %d requested\n",
+			    rc, small_pkts_buf_count);
+	}
+
+	cq_alloc_opts.policy = CXI_CQ_UPDATE_HIGH_FREQ_EMPTY;
+	cq_alloc_opts.count = dev->ringparam.rx_pending + TGT_CQ_OVERHEAD_COUNT;
+	cq_alloc_opts.lpe_cdt_thresh_id = lpe_cdt_thresh_id;
+	rx->cq_tgt_prio = cxi_cq_alloc(dev->lni, dev->err_eq, &cq_alloc_opts,
+				       rx->node);
+	if (IS_ERR(rx->cq_tgt_prio)) {
+		rc = PTR_ERR(rx->cq_tgt_prio);
+		goto err_free_buffers;
+	}
+
+	rx->eq_buf_size = get_rxq_eq_buf_size(dev);
+	rx->eq_buf = kvzalloc_node(rx->eq_buf_size, GFP_KERNEL, rx->node);
+	if (!rx->eq_buf) {
+		rc = -ENOMEM;
+		goto err_free_cq;
+	}
+
+	if (is_vmalloc_addr(rx->eq_buf)) {
+		rx->eq_md = cxi_map(dev->lni, (uintptr_t)rx->eq_buf,
+				    rx->eq_buf_size, CXI_MAP_WRITE, NULL);
+		if (IS_ERR(rx->eq_md)) {
+			rc = PTR_ERR(rx->eq_md);
+			goto err_free_eq_buf;
+		}
+	} else {
+		eq_attr.flags = CXI_EQ_PASSTHROUGH;
+	}
+
+	eq_attr.queue = rx->eq_buf;
+	eq_attr.queue_len = rx->eq_buf_size;
+	eq_attr.cpu_affinity = rx->cpu;
+	rx->eq = cxi_eq_alloc(dev->lni, rx->eq_md, &eq_attr, rx_eq_cb, rx, NULL,
+			      NULL);
+	if (IS_ERR(rx->eq)) {
+		rc = PTR_ERR(rx->eq);
+		goto err_unmap_eq_buf;
+	}
+
+	cxi_eq_int_disable(rx->eq);
+
+	/* Create an Ethernet portal */
+	rx->pt = cxi_pte_alloc(dev->lni, rx->eq, &pt_alloc_opts);
+	if (IS_ERR(rx->pt)) {
+		rc = PTR_ERR(rx->pt);
+		goto err_free_eq;
+	}
+
+	NETIF_NAPI_ADD(dev->ndev, &rx->napi, cxi_rx_eth_poll);
+
+	return 0;
+
+err_free_eq:
+	cxi_eq_free(rx->eq);
+err_unmap_eq_buf:
+	if (is_vmalloc_addr(rx->eq_buf))
+		cxi_unmap(rx->eq_md);
+err_free_eq_buf:
+	kvfree(rx->eq_buf);
+err_free_cq:
+	cxi_cq_free(rx->cq_tgt_prio);
+err_free_buffers:
+	free_rx_buffers(rx);
+err_free_rx_bufs:
+	vfree(rx->rx_bufs);
+err:
+	rx->dev = NULL;
+	return rc;
+}
+
+void free_rx_queue(struct rx_queue *rx)
+{
+	if (!rx->dev)
+		return;
+
+	netif_napi_del(&rx->napi);
+
+	cxi_pte_free(rx->pt);
+	rx->pt = NULL;
+	cxi_eq_free(rx->eq);
+	rx->eq = NULL;
+
+	if (is_vmalloc_addr(rx->eq_buf))
+		cxi_unmap(rx->eq_md);
+	kvfree(rx->eq_buf);
+	rx->eq_md = NULL;
+	rx->eq_buf = NULL;
+
+	cxi_cq_free(rx->cq_tgt_prio);
+	rx->cq_tgt_prio = NULL;
+	free_rx_buffers(rx);
+	vfree(rx->rx_bufs);
+	rx->rx_bufs = NULL;
+	rx->dev = NULL;
+}
+
+void enable_rx_queue(struct rx_queue *rx)
+{
+	napi_enable(&rx->napi);
+	cxi_eq_int_enable(rx->eq);
+}
+
+void disable_rx_queue(struct rx_queue *rx)
+{
+	if (!rx->dev)
+		return;
+
+	cxi_eq_int_disable(rx->eq);
+	napi_disable(&rx->napi);
+}
+
+#define DEFAULT_RESERVED_LES 1024U
+
+static unsigned int get_reserved_les(void)
+{
+	int reserved_les;
+	int max_rx_queues = max_rss_queues + 1; // +1 for PTP queue
+	int max_les_per_queue;
+
+	reserved_les = cxi_get_lpe_append_credits(lpe_cdt_thresh_id);
+	if (reserved_les < 0) {
+		pr_err("Failed to get LPE append credits. Used default %u\n",
+		       DEFAULT_RESERVED_LES);
+		return DEFAULT_RESERVED_LES;
+	}
+
+	max_les_per_queue = reserved_les + small_pkts_buf_count;
+
+	/* Each RX queue needs max_les_per_queue. Since the CXI service reserves
+	 * LEs against each LPE pool (4 pools total), the total number of LEs
+	 * needed needs to be divided by 4. cxi_pte_alloc() will then round
+	 * robind across the LPE pools.
+	 */
+	reserved_les = max_les_per_queue * (max_rx_queues / C_PE_COUNT);
+
+	/* Need to account if the number of queues is not a factor of 4. */
+	if (max_rx_queues % C_PE_COUNT)
+		reserved_les += max_les_per_queue;
+
+	return reserved_les;
+}
+
+/* Allocate the hardware resources and some receive buffers */
+int hw_setup(struct cxi_eth *dev)
+{
+	int rc;
+	int lac;
+	struct net_device *ndev = dev->ndev;
+	const struct cxi_rsrc_limits limits = {
+		.acs = {
+			.max = 1,
+			.res = 1,
+		},
+		.eqs = {
+			.max = 1 + max_rss_queues + (max_tx_queues * 2),
+			.res = 1,
+		},
+		.cts = {
+			.max = 0,
+			.res = 0,
+		},
+		.ptes = {
+			.max = 1 + max_rss_queues,
+			.res = 8,
+		},
+		.txqs = {
+			.max = max_tx_queues * 2,
+			.res = 1,
+		},
+		.tgqs = {
+			.max = 1 + 1 + max_rss_queues,
+			.res = 1,
+		},
+		.tles = {
+			.max = 0,
+			.res = 0,
+		},
+		/* Will actually have 4 * res value for les */
+		.les = {
+			.max = MAX_LE_LIMIT,
+			.res = get_reserved_les(),
+		},
+	};
+	struct cxi_svc_desc svc_desc = {
+		.resource_limits = true,
+		.limits = limits,
+		.is_system_svc = true,
+		.restricted_members = true,
+		.restricted_vnis = true,
+		.num_vld_vnis = 0,
+		.enable = true,
+		.members[0] = {
+			.type = CXI_SVC_MEMBER_UID,
+			.svc_member.uid = (current_euid()).val,
+		},
+	};
+	struct cxi_cq_alloc_opts cq_alloc_opts = {};
+	u8 shared_cp_pcp;
+
+	/* Allocate a Service */
+	rc = cxi_svc_alloc(dev->cxi_dev, &svc_desc, NULL, "ethernet-svc");
+	if (rc < 0) {
+		netdev_info(ndev, "Can't reserve resources: %d\n", rc);
+		goto err;
+	}
+	dev->svc_id = rc;
+
+	dev->lni = cxi_lni_alloc(dev->cxi_dev, dev->svc_id);
+	if (IS_ERR(dev->lni)) {
+		rc = PTR_ERR(dev->lni);
+		netdev_info(ndev, "Can't get an LNI: %d\n", rc);
+		goto err_free_svc;
+	}
+
+	lac = cxi_phys_lac_alloc(dev->lni);
+	if (lac < 0) {
+		rc = -EINVAL;
+		netdev_info(ndev, "failed to get a physical LAC: %d\n", rc);
+		goto err_free_ni;
+	}
+	dev->phys_lac = lac;
+
+	/* Store PCPs for all the Eth Classes */
+	dev->eth1_pcp = cxi_get_tc_req_pcp(dev->cxi_dev, CXI_ETH_TC1);
+	if (dev->eth1_pcp < 0) {
+		rc = -EINVAL;
+		goto err_free_ni;
+	}
+
+	/* Determine if Eth2 is active. Eth1 and Shared will always be active */
+	dev->eth2_pcp = cxi_get_tc_req_pcp(dev->cxi_dev, CXI_ETH_TC2);
+	dev->eth2_active = (dev->eth2_pcp >= 0 && dev->eth2_pcp < 8);
+
+	/* The Shared Ethernet Class is configured with all PCPs apart from
+	 * the ones used by Eth1 and Eth2. Use any of them for configuring
+	 * the CP
+	 */
+	for (shared_cp_pcp = 0; shared_cp_pcp <= 7; shared_cp_pcp++) {
+		if (shared_cp_pcp != dev->eth1_pcp &&
+		    (!dev->eth2_active || shared_cp_pcp != dev->eth2_pcp))
+			break;
+	}
+
+	/* Allocate CPs for each Eth TC
+	 * TODO: Support unique communication profiles + CQ + MCUs for each
+	 * PCP. This may not be feasible with the resource needed for each.
+	 */
+	dev->eth1_cp = cxi_trig_cp_alloc(dev->lni, dev->eth1_pcp,
+					 CXI_ETH_TC1, CXI_TC_TYPE_DEFAULT,
+					 NON_TRIG_LCID);
+	if (IS_ERR(dev->eth1_cp)) {
+		rc = PTR_ERR(dev->eth1_cp);
+		netdev_info(ndev, "Can't allocate Eth1 CP: %d\n", rc);
+		goto err_free_lac;
+	}
+
+	dev->shared_cp = cxi_trig_cp_alloc(dev->lni, shared_cp_pcp,
+					   CXI_ETH_SHARED,
+					   CXI_TC_TYPE_DEFAULT, NON_TRIG_LCID);
+	if (IS_ERR(dev->shared_cp)) {
+		rc = PTR_ERR(dev->shared_cp);
+		netdev_info(ndev, "Can't allocate Eth shared CP: %d\n", rc);
+		goto err_free_eth1_cp;
+	}
+
+	if (dev->eth2_active) {
+		dev->eth2_cp = cxi_trig_cp_alloc(dev->lni, dev->eth2_pcp,
+						 CXI_ETH_TC2,
+						 CXI_TC_TYPE_DEFAULT,
+						 NON_TRIG_LCID);
+		if (IS_ERR(dev->eth2_cp)) {
+			rc = PTR_ERR(dev->eth2_cp);
+			netdev_info(ndev, "Can't allocate Eth2 CP: %d\n", rc);
+			goto err_free_shared_cp;
+		}
+	}
+
+	dev->err_eq_attr.queue_len = PAGE_SIZE;
+	dev->err_eq_attr.queue = (void *)
+		__get_free_pages(GFP_KERNEL | __GFP_ZERO,
+				 get_order(dev->err_eq_attr.queue_len));
+	if (!dev->err_eq_attr.queue) {
+		rc = -ENOMEM;
+		netdev_info(ndev, "Can't allocate the EQ buffer: %d\n", rc);
+		goto err_free_eth2_cp;
+	}
+
+	dev->err_eq_attr.flags = CXI_EQ_PASSTHROUGH;
+	dev->err_eq = cxi_eq_alloc(dev->lni, NULL, &dev->err_eq_attr, err_eq_cb,
+				   dev, NULL, NULL);
+	if (IS_ERR(dev->err_eq)) {
+		rc = PTR_ERR(dev->err_eq);
+		netdev_info(ndev, "Can't allocate the EQ: %d\n", rc);
+		goto err_free_err_eq_buf;
+	}
+
+	cq_alloc_opts.policy = CXI_CQ_UPDATE_HIGH_FREQ_EMPTY;
+	cq_alloc_opts.count =
+		(small_pkts_buf_count * (max_rss_queues + 1)) +	TGT_CQ_OVERHEAD_COUNT;
+	dev->cq_tgt_req = cxi_cq_alloc(dev->lni, dev->err_eq, &cq_alloc_opts,
+				       dev_to_node(&dev->cxi_dev->pdev->dev));
+	if (IS_ERR(dev->cq_tgt_req)) {
+		rc = PTR_ERR(dev->cq_tgt_req);
+		netdev_info(ndev, "Can't allocate the target CQ: %d\n", rc);
+		goto err_free_err_eq;
+	}
+
+	/* Configure RXQ zero used for default/catch-all traffic. */
+	rc = alloc_rx_queue(dev, 0);
+	if (rc) {
+		netdev_info(ndev, "Can't allocate the receive queue: %d\n", rc);
+		goto err_free_cq_tgt_req;
+	}
+	dev->res.ptn_def = dev->rxqs[0].pt->id;
+
+	rc = post_rx_buffers(&dev->rxqs[0], GFP_KERNEL);
+	if (rc < 0) {
+		netdev_info(ndev, "Cannot post any RX buffers: %d\n", rc);
+		goto err_free_rx_queue;
+	}
+
+	/* Configure PTP RX queue */
+	rc = alloc_rx_queue(dev, PTP_RX_Q);
+	if (rc) {
+		netdev_info(ndev, "Can't allocate the PTP receive queue: %d\n",
+			    rc);
+		goto err_free_rx_queue;
+	}
+	dev->res.ptn_ptp = dev->rxqs[PTP_RX_Q].pt->id;
+	rc = post_rx_buffers(&dev->rxqs[PTP_RX_Q], GFP_KERNEL);
+	if (rc < 0) {
+		netdev_info(ndev, "Cannot post RX buffers: %d\n", rc);
+		goto err_free_ptp_queue;
+	}
+
+	rc = alloc_tx_queue(dev, 0);
+	if (rc) {
+		netdev_info(ndev, "Can't allocate the transmit queue: %d\n",
+			    rc);
+		goto err_free_ptp_queue;
+	}
+
+	dev->mac_addr = ether_addr_to_u64(ndev->dev_addr);
+	dev->ptp_mac_addr = PTP_L2_MAC;
+
+	cxi_eth_add_mac(dev->cxi_dev, &dev->res, dev->mac_addr,	false);
+
+	enable_rx_queue(&dev->rxqs[0]);
+	enable_rx_queue(&dev->rxqs[PTP_RX_Q]);
+	enable_tx_queue(&dev->txqs[0]);
+
+	dev->res.rss_queues = 1;
+	rc = cxi_set_rx_channels(dev, dev->ndev->real_num_rx_queues);
+	if (rc) {
+		netdev_info(ndev,
+			    "Can't set the number of RX channels to %d: %d\n",
+			    dev->ndev->real_num_rx_queues, rc);
+		goto err_disable_queues;
+	}
+
+	dev->cur_txqs = 1;
+	rc = cxi_set_tx_channels(dev, dev->ndev->real_num_tx_queues);
+	if (rc) {
+		netdev_info(ndev,
+			    "Can't set the number of TX channels to %d: %d\n",
+			    dev->ndev->real_num_tx_queues, rc);
+		goto err_set_rx_queues;
+	}
+
+	cxi_eth_set_rx_mode(ndev);
+	netif_tx_start_all_queues(ndev);
+	dev->is_active = true;
+
+	return 0;
+
+err_set_rx_queues:
+	cxi_set_rx_channels(dev, 1);
+err_disable_queues:
+	disable_tx_queue(&dev->txqs[0]);
+	disable_rx_queue(&dev->rxqs[PTP_RX_Q]);
+	disable_rx_queue(&dev->rxqs[0]);
+	cxi_eth_set_list_invalidate_all(dev->cxi_dev, &dev->res);
+	free_tx_queue(&dev->txqs[0]);
+err_free_ptp_queue:
+	free_rx_queue(&dev->rxqs[PTP_RX_Q]);
+err_free_rx_queue:
+	free_rx_queue(&dev->rxqs[0]);
+err_free_cq_tgt_req:
+	cxi_cq_free(dev->cq_tgt_req);
+err_free_err_eq:
+	cxi_eq_free(dev->err_eq);
+err_free_err_eq_buf:
+	free_pages((unsigned long)dev->err_eq_attr.queue,
+		   get_order(dev->err_eq_attr.queue_len));
+err_free_eth2_cp:
+	if (dev->eth2_active)
+		cxi_cp_free(dev->eth2_cp);
+err_free_shared_cp:
+	cxi_cp_free(dev->shared_cp);
+err_free_eth1_cp:
+	cxi_cp_free(dev->eth1_cp);
+err_free_lac:
+	cxi_phys_lac_free(dev->lni, dev->phys_lac);
+err_free_ni:
+	cxi_lni_free(dev->lni);
+err_free_svc:
+	cxi_svc_destroy(dev->cxi_dev, dev->svc_id);
+err:
+	return rc;
+}
+
+/* Release hardware resources belonging to a device. */
+void hw_cleanup(struct cxi_eth *dev)
+{
+	int i;
+
+	if (!dev->is_active)
+		return;
+
+	netif_tx_stop_all_queues(dev->ndev);
+
+	dev->is_active = false;
+
+	for (i = 0; i < dev->cur_txqs; i++)
+		disable_tx_queue(&dev->txqs[i]);
+
+	/* Disable RSS support and free RX queues. */
+	cxi_eth_clear_indir_table(dev->cxi_dev, &dev->res);
+	for (i = 0; i < dev->res.rss_queues; i++)
+		disable_rx_queue(&dev->rxqs[i]);
+	disable_rx_queue(&dev->rxqs[PTP_RX_Q]);
+
+	cxi_eth_set_list_invalidate_all(dev->cxi_dev, &dev->res);
+
+	for (i = 0; i < dev->cur_txqs; i++)
+		free_tx_queue(&dev->txqs[i]);
+
+	for (i = 0; i < dev->res.rss_queues; i++)
+		free_rx_queue(&dev->rxqs[i]);
+	free_rx_queue(&dev->rxqs[PTP_RX_Q]);
+
+	cxi_cq_free(dev->cq_tgt_req);
+	dev->cq_tgt_req = NULL;
+	cxi_eq_free(dev->err_eq);
+	free_pages((unsigned long)dev->err_eq_attr.queue,
+		   get_order(dev->err_eq_attr.queue_len));
+	dev->err_eq = NULL;
+	if (dev->eth2_active) {
+		cxi_cp_free(dev->eth2_cp);
+		dev->eth2_cp = NULL;
+	}
+	cxi_cp_free(dev->shared_cp);
+	dev->shared_cp = NULL;
+	cxi_cp_free(dev->eth1_cp);
+	dev->eth1_cp = NULL;
+	cxi_phys_lac_free(dev->lni, dev->phys_lac);
+	dev->phys_lac = 0;
+	cxi_lni_free(dev->lni);
+	dev->lni = NULL;
+	cxi_svc_destroy(dev->cxi_dev, dev->svc_id);
+}
+
+static struct sk_buff *eth_rx_copy(struct rx_queue *rx,
+				   struct rx_buffer *buf,
+				   const struct c_event_target_enet *event)
+{
+	struct cxi_eth *dev = rx->dev;
+	struct net_device *ndev = dev->ndev;
+	struct sk_buff *skb;
+	struct page *page;
+	unsigned char *start;
+	u64 buffer_start;
+	u64 offset;
+
+	if (unlikely(!buf->md || !buf->data))
+		return NULL;
+	buffer_start = CXI_VA_TO_IOVA(buf->md, (uintptr_t)buf->data);
+	if (unlikely(event->start < buffer_start))
+		return NULL;
+	offset = event->start - buffer_start;
+	if (unlikely(offset > buf->data_size ||
+		     event->length > buf->data_size - offset))
+		return NULL;
+	start = buf->data + offset;
+
+	if (likely(rx->frag_state == FRAG_NONE && !event->more_frags)) {
+		/* single fragment */
+		skb = napi_alloc_skb(&rx->napi, event->length);
+		if (unlikely(!skb))
+			return NULL;
+
+		__skb_put_data(skb, start, event->length);
+
+		skb->protocol = eth_type_trans(skb, ndev);
+	} else {
+		skb = napi_get_frags(&rx->napi);
+		if (unlikely(!skb))
+			return NULL;
+
+		/* The SKB may already be full, due to the adapter
+		 * being configured to fragment too much.
+		 */
+		if (unlikely(skb_shinfo(skb)->nr_frags == MAX_SKB_FRAGS))
+			return NULL;
+
+		if (rx->frag_state == FRAG_NONE &&
+		    event->length <= skb_availroom(skb)) {
+			__skb_put_data(skb, start, event->length);
+		} else {
+			if (unlikely(event->length > PAGE_SIZE))
+				return NULL;
+			page = alloc_page(GFP_ATOMIC);
+			if (unlikely(!page)) {
+				napi_free_frags(&rx->napi);
+				return NULL;
+			}
+
+			memcpy(page_address(page), start, event->length);
+
+			skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
+					page, 0, event->length, PAGE_SIZE);
+		}
+	}
+
+	return skb;
+}
+
+static struct sk_buff *eth_rx_frags(struct rx_queue *rx,
+				    struct rx_buffer *buf,
+				    const struct c_event_target_enet *event)
+{
+	struct cxi_eth *eth_dev = rx->dev;
+	struct device *dev = &eth_dev->cxi_dev->pdev->dev;
+	struct sk_buff *skb;
+	struct page *page;
+	int frag_len;
+
+	if (unlikely(!buf->page || !buf->posted_count ||
+		     buf->cur_offset >= PAGE_SIZE ||
+		     event->length > PAGE_SIZE - buf->cur_offset ||
+		     event->length > eth_dev->eth_info.max_segment_size))
+		return NULL;
+
+	skb = napi_get_frags(&rx->napi);
+	if (unlikely(!skb))
+		return NULL;
+
+	/* The SKB may already be full, due to the adapter
+	 * being configured to fragment too much.
+	 */
+	if (unlikely(skb_shinfo(skb)->nr_frags == MAX_SKB_FRAGS))
+		return NULL;
+
+	page = buf->page;
+	frag_len = event->length;
+
+	if (rx->frag_state == FRAG_NONE)
+		prefetch(page_address(page));
+
+	skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
+			page, buf->cur_offset, frag_len,
+			eth_dev->eth_info.max_segment_size);
+	dma_sync_single_for_cpu(dev, buf->mapping + buf->cur_offset, frag_len,
+				DMA_FROM_DEVICE);
+
+	buf->cur_offset += eth_dev->eth_info.max_segment_size;
+	buf->posted_count--;
+
+	if (buf->posted_count == 0) {
+		dma_unmap_page(dev, dma_unmap_addr(buf, mapping), PAGE_SIZE,
+			       DMA_FROM_DEVICE);
+		put_page(page);
+		buf->page = NULL;
+	}
+
+	return skb;
+}
+
+/* Check whether the RoCE packet in the SKB has been segmented by
+ * hardware, which also removed its iCRC. Fix the headers if that
+ * happened.
+ */
+static void check_segmented_roce(struct sk_buff *skb)
+{
+	int frag_len;
+	u16 protocol;
+	struct ethhdr *ethhdr;
+	size_t vhdr_size = 0;
+
+	/* heuristic to figure out whether Cassini stripped the iCRC
+	 * from a RoCE packet, following its segmentation.
+	 */
+	if (skb_shinfo(skb)->nr_frags != 1)
+		return;
+
+	ethhdr = (void *)skb->data;
+	protocol = be16_to_cpu(ethhdr->h_proto);
+
+	/* Check for vlan header - we will support at most one vlan header,
+	 * no nested headers, ipv6 extensions, etc.
+	 */
+	if (eth_type_vlan(ethhdr->h_proto)) {
+		struct vlan_ethhdr *veth;
+
+		veth = (struct vlan_ethhdr *)skb->data;
+		protocol = be16_to_cpu(veth->h_vlan_encapsulated_proto);
+		vhdr_size = sizeof(struct vlan_hdr);
+	}
+
+	/* Check length. ETH+IPv4/6+UDP+BTH headers. */
+	if (skb_headlen(skb) < (54 + vhdr_size) || skb_headlen(skb) > (90 + vhdr_size))
+		return;
+
+	frag_len = skb_frag_size(&skb_shinfo(skb)->frags[0]);
+	if (frag_len != 1024 && frag_len != 2048 && frag_len != 4096)
+		return;
+
+	/* Adjust the IP packet by removing the 4 bytes and
+	 * recomputing the IP header checksum.
+	 */
+	switch (protocol) {
+	case ETH_P_IP: {
+		struct udphdr *udph;
+		struct iphdr *iph;
+
+		iph = (void *)skb->data + sizeof(struct ethhdr) + vhdr_size;
+		iph->tot_len = cpu_to_be16(be16_to_cpu(iph->tot_len) - 4);
+		iph->check = 0;
+		iph->check = ip_fast_csum((const void *)iph, iph->ihl);
+
+		udph = (void *)(iph + 1);
+		udph->len = cpu_to_be16(be16_to_cpu(udph->len) - 4);
+	}
+		break;
+
+	case ETH_P_IPV6: {
+		struct udphdr *udph;
+		struct ipv6hdr *ip6h;
+
+		ip6h = (void *)skb->data + sizeof(struct ethhdr) + vhdr_size;
+		ip6h->payload_len =
+			cpu_to_be16(be16_to_cpu(ip6h->payload_len) - 4);
+
+		if (ip6h->nexthdr != NEXTHDR_UDP) {
+			netdev_warn_once(skb->dev,
+					 "Unexpected ipv6 packet format (nexthdr = %d)\n",
+					 ip6h->nexthdr);
+			return;
+		}
+
+		udph = (void *)(ip6h + 1);
+		udph->len = cpu_to_be16(be16_to_cpu(udph->len) - 4);
+	}
+		break;
+
+	default:
+		netdev_warn_once(skb->dev,
+				 "unexpected protocol in RoCE packet: %x\n",
+				 protocol);
+		return;
+	}
+
+	/* TODO. For now, use a bit in the SKB to tell RXE that
+	 * the iCRC is gone, and that the packet is otherwise correct.
+	 */
+	cxi_skb_icrc_gone(skb);
+}
+
+/* Convert from hash type (i.e. C_RSS_HASH_IPV4_UDP) to linux hash
+ * type (i.e. PKT_HASH_TYPE_L4). Only valid if the hash type is not
+ * C_RSS_HASH_NONE.
+ */
+static const u8 rss_hash_type_to_level[C_RSS_HASH_IPV6_FLOW_LABEL + 1] = {
+	[C_RSS_HASH_IPV4] = PKT_HASH_TYPE_L3,
+	[C_RSS_HASH_IPV4_PROTOCOL] = PKT_HASH_TYPE_L3,
+	[C_RSS_HASH_IPV4_FLOW_LABEL] = PKT_HASH_TYPE_L3,
+	[C_RSS_HASH_IPV6] = PKT_HASH_TYPE_L3,
+	[C_RSS_HASH_IPV6_PROTOCOL] = PKT_HASH_TYPE_L3,
+	[C_RSS_HASH_IPV6_FLOW_LABEL] = PKT_HASH_TYPE_L3,
+
+	[C_RSS_HASH_IPV4_TCP] = PKT_HASH_TYPE_L4,
+	[C_RSS_HASH_IPV4_UDP] = PKT_HASH_TYPE_L4,
+	[C_RSS_HASH_IPV4_PROTOCOL_TCP] = PKT_HASH_TYPE_L4,
+	[C_RSS_HASH_IPV4_PROTOCOL_UDP] = PKT_HASH_TYPE_L4,
+	[C_RSS_HASH_IPV4_PROTOCOL_UDP_ROCE] = PKT_HASH_TYPE_L4,
+	[C_RSS_HASH_IPV6_TCP] = PKT_HASH_TYPE_L4,
+	[C_RSS_HASH_IPV6_UDP] = PKT_HASH_TYPE_L4,
+	[C_RSS_HASH_IPV6_PROTOCOL_TCP] = PKT_HASH_TYPE_L4,
+	[C_RSS_HASH_IPV6_PROTOCOL_UDP] = PKT_HASH_TYPE_L4,
+	[C_RSS_HASH_IPV6_PROTOCOL_UDP_ROCE] = PKT_HASH_TYPE_L4,
+};
+
+static void set_rss_hash_value(const struct c_event_target_enet *event,
+			       struct sk_buff *skb)
+{
+	if (event->rss_hash_type == C_RSS_HASH_NONE ||
+	    event->rss_hash_type > C_RSS_HASH_IPV6_FLOW_LABEL)
+		return;
+
+	skb_set_hash(skb, event->rss_hash_value,
+		     rss_hash_type_to_level[event->rss_hash_type]);
+}
+
+/* Process a received packet */
+static bool eth_receive(struct rx_queue *rx,
+			const struct c_event_target_enet *event)
+{
+	struct cxi_eth *dev = rx->dev;
+	struct net_device *ndev = dev->ndev;
+	struct sk_buff *skb = NULL;
+	struct rx_buffer *buf;
+	bool packet_complete = false;
+
+	/* Find the target buffer */
+	if (event->ptlte_index != rx->pt->id) {
+		netdev_err(ndev, "Unknown portal target in RX event (%d instead of %d)\n",
+			   event->ptlte_index, rx->pt->id);
+		return packet_complete;
+	}
+
+	buf = &rx->rx_bufs[event->buffer_id];
+
+	if (unlikely(event->return_code != C_RC_OK ||
+		     (event->is_roce && !event->more_frags &&
+		      !event->roce_icrc_ok) ||
+		     event->parser_err ||
+		     rx->frag_state == FRAG_DROP)) {
+		goto drop;
+	}
+
+	if (event->ptl_list == C_PTL_LIST_PRIORITY)
+		skb = eth_rx_frags(rx, buf, event);
+	else
+		skb = eth_rx_copy(rx, buf, event);
+
+	if (unlikely(!skb))
+		goto drop;
+
+	if (dev->is_c2) {
+		if (event->seg_cnt == 0) {
+			/* It's a new packet */
+			rx->pkt_cnt = event->pkt_cnt;
+			rx->next_seg_cnt = 1;
+
+			/* Free existing incomplete segments if any */
+			if (rx->frag_state != FRAG_NONE) {
+				ndev->stats.rx_dropped++;
+				rx->frag_state = FRAG_NONE;
+				napi_free_frags(&rx->napi);
+			}
+		} else if (event->pkt_cnt != rx->pkt_cnt ||
+			   event->seg_cnt != rx->next_seg_cnt) {
+			goto drop;
+		} else {
+			rx->next_seg_cnt++;
+		}
+	}
+
+	if (event->more_frags == 0) {
+		__be16 csum;
+
+		ndev->stats.rx_packets++;
+		ndev->stats.rx_bytes += skb->len;
+
+		csum = (__force __be16)event->checksum;
+		skb->csum = (__force __wsum)be16_to_cpu(csum);
+		skb->ip_summed = CHECKSUM_COMPLETE;
+
+		/* Cassini ERRATA-3258. This should test event->timestamp, but
+		 * Cassini 1/1.1 doesn't set it.
+		 */
+		if (dev->ptp_ts_enabled &&
+		    event->ptlte_index == dev->res.ptn_ptp) {
+			struct c_ts ts;
+			int rc;
+
+			rc = skb_copy_bits(skb, skb->len - sizeof(ts),
+					   &ts, sizeof(ts));
+			if (rc)
+				goto drop;
+
+			/* Cassini ERRATA-3276. Ignore the timestamp on Cassini 1
+			 * if ns is close to 1s, as RX timestamp can
+			 * be off by one second in that case. No issue
+			 * on Cassini 2.
+			 */
+			if (dev->is_c2 || ts.ns < 999999700)
+				skb_hwtstamps(skb)->hwtstamp =
+					ktime_set(ts.sec, ts.ns);
+
+			pskb_trim(skb, skb->len - sizeof(ts));
+		}
+
+		if (event->is_roce) {
+			if (skb->len <= 64 && !dev->is_c2 &&
+			    (skb_shinfo(skb)->nr_frags == 0))
+				/* Due to a rarely occurring hardware
+				 * bug, iCRC on packets smaller than
+				 * 65 bytes may be passed although
+				 * they are corrupted.  Tell the rxe
+				 * driver to check it again.
+				 */
+				cxi_force_icrc_check(skb);
+			else if (dev->priv_flags & CXI_ETH_PF_ROCE_OPT)
+				check_segmented_roce(skb);
+		}
+
+		skb_record_rx_queue(skb, rx->id);
+
+		if (ndev->features & NETIF_F_RXHASH)
+			set_rss_hash_value(event, skb);
+
+		if (skb_is_nonlinear(skb)) {
+			napi_gro_frags(&rx->napi);
+
+			rx->frag_state = FRAG_NONE;
+		} else {
+			napi_gro_receive(&rx->napi, skb);
+		}
+
+		packet_complete = true;
+	} else {
+		rx->frag_state = FRAG_MORE;
+	}
+
+requeue:
+	if (event->ptl_list == C_PTL_LIST_PRIORITY) {
+		rx->stats.unlinked_prio++;
+
+		if (buf->page == NULL) {
+			list_del(&buf->buf_list);
+			list_add_tail(&buf->buf_list, &rx->rx_ready);
+		}
+	} else if (event->auto_unlinked) {
+		rx->stats.unlinked_req++;
+		list_del(&buf->buf_list);
+		list_add_tail(&buf->buf_list, &rx->rx_ready);
+	}
+
+	return packet_complete;
+
+drop:
+	/* Error on receive, NIC dropped this frag, or driver dropped a previous
+	 * frag, or skb allocation failure
+	 */
+	netdev_dbg(dev->ndev,
+		   "received return_code=%d more=%d state=%d ptl_list=%d roce=%d\n",
+		   event->return_code, event->more_frags, rx->frag_state,
+		   event->ptl_list, event->is_roce);
+
+	if (event->return_code != C_RC_OK)
+		rx->last_bad_frag_drop_rc = event->return_code;
+
+	/* Not always a whole packet, so in theory a single packet
+	 * could be counted several times, one for each segment.
+	 */
+	ndev->stats.rx_dropped++;
+
+	if (rx->frag_state != FRAG_DROP)
+		napi_free_frags(&rx->napi);
+
+	if (event->more_frags)
+		rx->frag_state = FRAG_DROP;
+	else
+		rx->frag_state = FRAG_NONE;
+
+	goto requeue;
+}
+
+/* RX queue interrupt handler. Disable the interrupts for that EQ and
+ * trigger NAPI.
+ */
+static void rx_eq_cb(void *context)
+{
+	struct rx_queue *rx = context;
+
+	rx->time_napi_schedule = ktime_get_raw();
+	napi_schedule(&rx->napi);
+}
+
+static void add_ktime_to_bucket(struct bucket *bucket, u64 ns)
+{
+	int i;
+
+	if (ns > bucket->max_ts)
+		bucket->max_ts = ns;
+	if (ns < bucket->min_ts)
+		bucket->min_ts = ns;
+
+	i = fls(ns + 1);
+	if (i >= NB_BUCKETS)
+		i = NB_BUCKETS - 1;
+
+	bucket->b[i]++;
+}
+
+#define RX_ETH_EQ_UNACKED_MAX 16U
+
+/* NAPI poll function.
+ * Only the receive event will be counted towards the budget.
+ */
+static int cxi_rx_eth_poll(struct napi_struct *napi, int budget)
+{
+	struct rx_queue *rx = container_of(napi, struct rx_queue, napi);
+	struct cxi_eth *dev = rx->dev;
+	const union c_event *event;
+	int work_done = 0;
+	int event_count = 0;
+	bool reschedule = false;
+	bool packet_processed = false;
+	int rc;
+
+	if (rx->time_napi_schedule) {
+		ktime_t enter_ts;
+		u64 time_exec;
+
+		enter_ts = ktime_get_raw();
+		time_exec = ktime_to_ns(ktime_sub(enter_ts,
+						  rx->time_napi_schedule));
+		add_ktime_to_bucket(&rx->eth_napi_schedule, time_exec);
+
+		/* Prevent adding time when the function is re-entered */
+		rx->time_napi_schedule = 0;
+	}
+
+	while (work_done < budget &&
+	       (event = cxi_eq_get_event(rx->eq))) {
+		switch (event->hdr.event_type) {
+		case C_EVENT_LINK:
+			packet_processed = false;
+			netdev_warn(dev->ndev, "LE append failure: %d\n",
+				    event->tgt_long.return_code);
+			break;
+		case C_EVENT_ETHERNET:
+			packet_processed = eth_receive(rx, &event->enet);
+			if (packet_processed)
+				work_done++;
+			break;
+		case C_EVENT_STATE_CHANGE:
+			packet_processed = false;
+			netdev_warn(dev->ndev, "State change (%d, %d, %d)\n",
+				    event->tgt_long.ptlte_index,
+			       event->tgt_long.initiator.state_change.ptlte_state,
+			       event->tgt_long.return_code);
+			break;
+		default:
+			packet_processed = false;
+			netdev_warn(dev->ndev, "Unhandled event %d, rc %d\n",
+				    event->hdr.event_type,
+				    event->hdr.return_code);
+			print_hex_dump(KERN_INFO,
+				       "cxi eth unexpected target event: ",
+				       DUMP_PREFIX_ADDRESS, 16, 1, event,
+				       (8 << event->hdr.event_size), false);
+		}
+
+		event_count++;
+		if ((event_count >= RX_ETH_EQ_UNACKED_MAX) &&
+		    packet_processed) {
+			cxi_eq_int_disable(rx->eq);
+			rc = post_rx_buffers(rx, GFP_ATOMIC);
+			if (rc < 0)
+				reschedule = true;
+
+			event_count = 0;
+		}
+	}
+
+	BUG_ON(work_done > budget);
+
+	/* ACK all EQ space before appending new buffers. */
+	if (event_count)
+		cxi_eq_int_disable(rx->eq);
+
+	if (!list_empty(&rx->rx_ready)) {
+		rc = post_rx_buffers(rx, GFP_ATOMIC);
+		if (rc < 0)
+			reschedule = true;
+	}
+
+	if (work_done < budget && napi_complete_done(napi, work_done)) {
+		/* Only re-enable interrupts if NAPI is not going to be
+		 * rescheduled.
+		 */
+		if (reschedule) {
+			netdev_warn_once(dev->ndev,
+					 "Forcing NAPI reschedule\n");
+			napi_schedule(&rx->napi);
+		} else {
+			cxi_eq_int_enable(rx->eq);
+		}
+	}
+
+	return work_done;
+}
+
+/* Hardware defined RSS hash bit is one less than the corresponding
+ * c_rss_hash_type enum value. This macro should only be used if the
+ * c_rss_hash_type enum value is not C_RSS_HASH_NONE.
+ */
+#define RSS_HASH_BIT(hash_type) ((hash_type) - 1)
+
+int cxi_eth_open(struct net_device *ndev)
+{
+	struct cxi_eth *dev = netdev_priv(ndev);
+	struct hwtstamp_config ts_cfg = {
+		.flags = 0,
+		.tx_type = HWTSTAMP_TX_OFF,
+		.rx_filter = HWTSTAMP_FILTER_NONE,
+	};
+
+	cxi_set_eth_name(dev->cxi_dev, netdev_name(ndev));
+
+	/* The indirection base is always 0 for now, as there is only
+	 * one Ethernet device supported. The driver will need an
+	 * allocation scheme when VFs support Ethernet.
+	 */
+	dev->res.portal_index_indir_base = 0;
+
+	/* Enable some default hash type.
+	 * TODO: remove when ethtool supports them.
+	 */
+	dev->res.hash_types_enabled =
+		BIT(RSS_HASH_BIT(C_RSS_HASH_IPV4_TCP)) |
+		BIT(RSS_HASH_BIT(C_RSS_HASH_IPV4_UDP)) |
+		BIT(RSS_HASH_BIT(C_RSS_HASH_IPV4_PROTOCOL_UDP_ROCE)) |
+		BIT(RSS_HASH_BIT(C_RSS_HASH_IPV6_TCP)) |
+		BIT(RSS_HASH_BIT(C_RSS_HASH_IPV6_UDP)) |
+		BIT(RSS_HASH_BIT(C_RSS_HASH_IPV6_PROTOCOL_UDP_ROCE));
+
+	cxi_eth_cfg_timestamp(dev->cxi_dev, &ts_cfg);
+
+	return hw_setup(dev);
+}
+
+int cxi_eth_close(struct net_device *ndev)
+{
+	struct cxi_eth *dev = netdev_priv(ndev);
+
+	hw_cleanup(dev);
+
+	return 0;
+}
+
+/* Get a flow hash for the commands */
+static u8 get_flow_hash(struct sk_buff *skb)
+{
+	u32 hash = skb_get_hash(skb);
+
+	/* XOR the 4 bytes into one */
+	hash ^= hash >> 16;
+	hash ^= hash >> 8;
+
+	return hash & 0xff;
+}
+
+static void cxi_eth_get_skb_checksum_settings(struct sk_buff *skb,
+					      struct cxi_eth *dev,
+					      enum c_checksum_ctrl *ctrl,
+					      unsigned int *start,
+					      unsigned int *offset)
+{
+	__be16 proto;
+
+	if (skb->ip_summed != CHECKSUM_PARTIAL)
+		goto no_crc;
+
+	*start = skb_checksum_start_offset(skb) / 2;
+	*offset = skb->csum_offset / 2;
+
+	if (eth_type_vlan(skb->protocol))
+		proto = vlan_get_protocol(skb);
+	else
+		proto = skb->protocol;
+
+	if (proto == htons(ETH_P_IP)) {
+		struct iphdr *iph = ip_hdr(skb);
+
+		if (iph->protocol == IPPROTO_UDP) {
+			if ((dev->priv_flags & CXI_ETH_PF_ROCE_OPT) &&
+			    ntohs(udp_hdr(skb)->dest) == ROCE_V2_UDP_DPORT)
+				*ctrl = C_CHECKSUM_CTRL_ROCE;
+			else
+				*ctrl = C_CHECKSUM_CTRL_UDP;
+		} else if (iph->protocol == IPPROTO_TCP) {
+			*ctrl = C_CHECKSUM_CTRL_TCP;
+		}
+	} else if (proto == htons(ETH_P_IPV6)) {
+		struct ipv6hdr *iph = ipv6_hdr(skb);
+
+		if (iph->nexthdr == IPPROTO_UDP) {
+			if ((dev->priv_flags & CXI_ETH_PF_ROCE_OPT) &&
+			    ntohs(udp_hdr(skb)->dest) == ROCE_V2_UDP_DPORT)
+				*ctrl = C_CHECKSUM_CTRL_ROCE;
+			else
+				*ctrl = C_CHECKSUM_CTRL_UDP;
+		} else if (iph->nexthdr == IPPROTO_TCP) {
+			*ctrl = C_CHECKSUM_CTRL_TCP;
+		}
+	} else {
+		netdev_warn_once(dev->ndev,
+				 "Checksum type not supported. Protocol=%u\n",
+				 skb->protocol);
+		goto no_crc;
+	}
+
+	return;
+
+no_crc:
+	*ctrl = C_CHECKSUM_CTRL_NONE;
+	*start = 0;
+	*offset = 0;
+}
+
+/* Emit a packet using an IDC command */
+static netdev_tx_t emit_idc(struct sk_buff *skb, struct tx_queue *txq,
+			    struct cxi_cq *cq)
+{
+	struct c_idc_eth_cmd idc_eth = {
+		.fmt = C_PKT_FORMAT_STD,
+	};
+	struct cxi_eth *dev = txq->dev;
+	struct net_device *ndev = dev->ndev;
+	enum c_checksum_ctrl checksum_ctrl;
+	unsigned int checksum_start;
+	unsigned int checksum_offset;
+	int rc;
+
+	cxi_eth_get_skb_checksum_settings(skb, dev, &checksum_ctrl,
+					  &checksum_start, &checksum_offset);
+
+	idc_eth.checksum_ctrl = checksum_ctrl;
+	idc_eth.checksum_start = checksum_start;
+	idc_eth.checksum_offset = checksum_offset;
+	idc_eth.flow_hash = get_flow_hash(skb);
+
+	skb_tx_timestamp(skb);
+
+	rc = cxi_cq_emit_idc_eth(cq, &idc_eth, skb->data, skb->len);
+	if (rc) {
+		/* Hard error which should never happen. */
+		netdev_err(dev->ndev, "TX queue %u full when queue awake\n",
+			   txq->id);
+		txq->stats.tx_busy++;
+
+		return NETDEV_TX_BUSY;
+	}
+
+	txq->stats.idc++;
+	txq->stats.idc_bytes += skb->len;
+
+	ndev->stats.tx_packets++;
+	ndev->stats.tx_bytes += skb->len;
+
+	dev_kfree_skb(skb);
+
+	return NETDEV_TX_OK;
+}
+
+/* Emit a packet using a DMA command */
+static netdev_tx_t emit_dma(struct sk_buff *skb, struct tx_queue *txq,
+			    struct cxi_cq *cq, unsigned int *bytes)
+{
+	struct cxi_eth *dev = txq->dev;
+	struct device *dma_dev = &dev->cxi_dev->pdev->dev;
+	struct net_device *ndev = dev->ndev;
+	struct c_dma_eth_cmd dma_eth = {
+		.read_lac = txq->dev->phys_lac,
+		.fmt = C_PKT_FORMAT_STD,
+		.checksum_ctrl = C_CHECKSUM_CTRL_NONE,
+		.eq = txq->eq->eqn,
+		.user_ptr = (uintptr_t)skb,
+		.total_len = skb->len,
+	};
+	enum c_checksum_ctrl checksum_ctrl;
+	unsigned int checksum_start;
+	unsigned int checksum_offset;
+	int rc;
+
+	if (skb_shinfo(skb)->nr_frags >= C_MAX_ETH_FRAGS) {
+		if (skb_linearize(skb) ||
+		    skb_shinfo(skb)->nr_frags >= C_MAX_ETH_FRAGS) {
+			netdev_warn(ndev, "skb could not be linearized\n");
+			cancel_tx_tstamp(dev, skb);
+			dev_kfree_skb(skb);
+			ndev->stats.tx_dropped++;
+			return NETDEV_TX_OK;
+		}
+	}
+
+	if (prepare_frags(dma_dev, skb, &dma_eth)) {
+		netdev_warn(ndev, "skb could not be mapped for DMA\n");
+		cancel_tx_tstamp(dev, skb);
+		dev_kfree_skb(skb);
+		ndev->stats.tx_dropped++;
+		return NETDEV_TX_OK;
+	}
+
+	cxi_eth_get_skb_checksum_settings(skb, dev, &checksum_ctrl,
+					  &checksum_start, &checksum_offset);
+
+	dma_eth.checksum_ctrl = checksum_ctrl;
+	dma_eth.checksum_start = checksum_start;
+	dma_eth.checksum_offset = checksum_offset;
+	dma_eth.flow_hash = get_flow_hash(skb);
+
+	skb_tx_timestamp(skb);
+
+	rc = cxi_cq_emit_dma_eth(cq, &dma_eth);
+	if (rc) {
+		/* Hard error which should never happen. */
+		netdev_err(dev->ndev, "TX queue %u full when queue awake\n",
+			   txq->id);
+		txq->stats.tx_busy++;
+
+		unmap_frags(dma_dev, skb);
+		cancel_tx_tstamp(dev, skb);
+
+		return NETDEV_TX_BUSY;
+	}
+
+	atomic_dec(&txq->dma_eq_cdt);
+	txq->stats.dma++;
+	txq->stats.dma_bytes += skb->len;
+
+	*bytes += skb->len;
+	return NETDEV_TX_OK;
+}
+
+/* Check whether an outgoing packet can be timestamped, and reserve
+ * the unique slot if it can.
+ */
+static bool tstamp_xmit(struct cxi_eth *dev, struct sk_buff *skb)
+{
+	struct ethhdr *ethhdr;
+
+	if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)))
+		return false;
+
+	/* Only Ethernet PTP packets are supported. That's what was
+	 * programmed in cxi_eth_cfg_timestamp().
+	 */
+	ethhdr = (struct ethhdr *)skb->data;
+	if (ethhdr->h_proto != htons(PTP_L2_ETHERTYPE))
+		return false;
+
+	if (cmpxchg(&dev->tstamp_skb, NULL, skb))
+		return false;
+
+	skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
+
+	return true;
+}
+
+static void ring_txq(struct tx_queue *txq)
+{
+	cxi_cq_ring(txq->eth1_cq);
+	if (txq->eth2_cq)
+		cxi_cq_ring(txq->eth2_cq);
+	cxi_cq_ring(txq->shared_cq);
+}
+
+netdev_tx_t cxi_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
+{
+	struct cxi_eth *dev = netdev_priv(ndev);
+	unsigned int qid = skb_get_queue_mapping(skb);
+	struct tx_queue *txq = &dev->txqs[qid];
+	struct netdev_queue *dev_queue =
+		netdev_get_tx_queue(dev->ndev, txq->id);
+	unsigned int bytes = 0;
+	netdev_tx_t tx_status;
+	bool kick_cq;
+	bool more = netdev_xmit_more();
+	struct cxi_cq *cq;
+
+	if (eth_type_vlan(skb->protocol)) {
+		/* Tagged traffic. Check PCPs to steer appropriately */
+		struct vlan_ethhdr *veth;
+		unsigned int pcp;
+
+		veth = (struct vlan_ethhdr *)vlan_eth_hdr(skb);
+		pcp = (be16_to_cpu(veth->h_vlan_TCI) & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT;
+
+		if (pcp == dev->cxi_dev->untagged_eth_pcp)
+			cq = txq->untagged_cq;
+		else if (pcp == dev->eth1_pcp)
+			cq = txq->eth1_cq;
+		else if (dev->eth2_active && pcp == dev->eth2_pcp)
+			cq = txq->eth2_cq;
+		else
+			cq = txq->shared_cq;
+	} else {
+		/* Untagged traffic. */
+		cq = txq->untagged_cq;
+	}
+
+	if (tstamp_xmit(dev, skb) || skb_shinfo(skb)->nr_frags ||
+	    skb->len > idc_dma_threshold) {
+		tx_status = emit_dma(skb, txq, cq, &bytes);
+		txq->force_dma = txq->force_dma_interval;
+	} else if (--txq->force_dma == 0) {
+		/* Too many consecutive IDC. Use DMA instead */
+		tx_status = emit_dma(skb, txq, cq, &bytes);
+		txq->force_dma = txq->force_dma_interval;
+		txq->stats.dma_forced++;
+	} else {
+		tx_status = emit_idc(skb, txq, cq);
+	}
+
+	/* Kick CQ if netdev TX queue is ready. */
+	kick_cq = __netdev_tx_sent_queue(dev_queue, bytes, more);
+	if (kick_cq)
+		ring_txq(txq);
+
+	/* Stop TX queue if not enough free slots to emit another SKB
+	 * or NETDEV_TX_BUSY is set. 8 slots, aligned on an 8-slot
+	 * boundary, are required to emit the largest IDC or DMA
+	 * commands. TX queue will be re-enabled as space frees up. If
+	 * the TX queue is to be stopped, the TX queue is always
+	 * kicked in an attempt to free up space.
+	 */
+	if (__cxi_cq_free_slots(cq) < 16 || tx_status == NETDEV_TX_BUSY) {
+		if (!kick_cq)
+			ring_txq(txq);
+		netif_tx_stop_queue(dev_queue);
+		txq->stats.stopped++;
+	} else if (atomic_read(&txq->dma_eq_cdt) <= 0) {
+		/* The EQ is getting full */
+		if (!kick_cq)
+			ring_txq(txq);
+		netif_tx_stop_queue(dev_queue);
+		txq->stats.stopped_eq++;
+	}
+
+	return tx_status;
+}
+
+int cxi_eth_mac_addr(struct net_device *ndev, void *p)
+{
+	struct cxi_eth *dev = netdev_priv(ndev);
+	int rc;
+
+	rc = eth_mac_addr(ndev, p);
+	if (rc)
+		return rc;
+
+	dev->mac_addr = ether_addr_to_u64(ndev->dev_addr);
+	ether_addr_copy(dev->cxi_dev->mac_addr, ndev->dev_addr);
+
+	cxi_eth_set_rx_mode(ndev);
+
+	/* We expect the NID to be configured before the MAC address is set.
+	 * To be backwards compatible, we will attempt to set the NID from the MAC address.
+	 * If the NID was not set, it will be derived from the MAC. Otherwise this will be ignored
+	 */
+	cxi_set_nid_from_mac(dev->cxi_dev, ndev->dev_addr);
+
+	return 0;
+}
+
+/* Program MAC filters.
+ *
+ * Since the ethernet driver is the only thing using the MAC filter
+ * (set_list), we can reset the whole list when entering this
+ * function, and reprogram everything.
+ */
+void cxi_eth_set_rx_mode(struct net_device *ndev)
+{
+	struct cxi_eth *dev = netdev_priv(ndev);
+	struct netdev_hw_addr *ha;
+	int rc;
+
+	/* Invalidate all existing filters. */
+	cxi_eth_set_list_invalidate_all(dev->cxi_dev, &dev->res);
+
+	/* Cassini ERRATA-3258. Workaround timestamp bug. Program the PTP MAC
+	 * address first so all the PTP packets will land on the PTP
+	 * RX queue, even if promiscuous mode is enabled.
+	 */
+	cxi_eth_add_mac(dev->cxi_dev, &dev->res, dev->ptp_mac_addr, true);
+
+	if (ndev->flags & IFF_PROMISC) {
+		/* Listen on everything. */
+		cxi_eth_set_promiscuous(dev->cxi_dev, &dev->res);
+		cxi_eth_set_indir_table(dev->cxi_dev, &dev->res);
+		return;
+	}
+
+	rc = cxi_eth_add_mac(dev->cxi_dev, &dev->res, dev->mac_addr, false);
+	if (rc) {
+		netdev_err(ndev, "Cannot program MAC address\n");
+		return;
+	}
+
+	if (ndev->flags & IFF_BROADCAST) {
+		rc = cxi_eth_add_mac(dev->cxi_dev, &dev->res,
+				     0xffffffffffffULL, false);
+		if (rc) {
+			netdev_err(ndev, "Cannot program broadcast address\n");
+			return;
+		}
+	}
+
+	netdev_for_each_uc_addr(ha, ndev) {
+		netdev_dbg(ndev, "Adding UC addr %pM\n", ha->addr);
+
+		rc = cxi_eth_add_mac(dev->cxi_dev, &dev->res,
+				     ether_addr_to_u64(ha->addr), false);
+		if (rc) {
+			netdev_err(ndev, "Cannot program unicast address\n");
+			return;
+		}
+	}
+
+	if (ndev->flags & IFF_ALLMULTI) {
+		/* Accept all multicasts. */
+		rc = cxi_eth_set_all_multi(dev->cxi_dev, &dev->res);
+		if (rc) {
+			netdev_err(ndev,
+				   "Cannot program all multicast addresses\n");
+			return;
+		}
+	} else if (ndev->flags & IFF_MULTICAST) {
+		netdev_for_each_mc_addr(ha, ndev) {
+			netdev_dbg(ndev, "Adding MC addr %pM\n", ha->addr);
+
+			rc = cxi_eth_add_mac(dev->cxi_dev, &dev->res,
+					     ether_addr_to_u64(ha->addr),
+					     false);
+			if (rc) {
+				netdev_err(ndev,
+					   "Cannot program multicast address\n");
+				return;
+			}
+		}
+	}
+
+	cxi_eth_set_indir_table(dev->cxi_dev, &dev->res);
+}
+
+int cxi_change_mtu(struct net_device *ndev, int new_mtu)
+{
+	struct cxi_eth *dev = netdev_priv(ndev);
+	bool was_running;
+	int rc;
+
+	was_running = netif_running(ndev);
+	if (was_running)
+		hw_cleanup(dev);
+
+	rc = cxi_set_max_eth_rxsize(dev->cxi_dev, new_mtu + VLAN_ETH_HLEN);
+	if (rc)
+		netdev_err(ndev, "Invalid MTU size: %u\n", new_mtu);
+	else
+		ndev->mtu = new_mtu;
+
+	if (was_running) {
+		int rc2;
+
+		rc2 = hw_setup(dev);
+		if (rc2) {
+			netdev_err(ndev,
+				   "Failed to setup resources after an MTU change\n");
+			rc = rc2;
+		}
+	}
+
+	return rc;
+}
diff --git a/drivers/net/ethernet/hpe/ss1/cxi_ethtool.c b/drivers/net/ethernet/hpe/ss1/cxi_ethtool.c
new file mode 100644
index 000000000000..67d8a0d23b90
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cxi_ethtool.c
@@ -0,0 +1,916 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Cassini ethernet driver
+ * Copyright 2018,2022,2024,2026 Hewlett Packard Enterprise Development LP
+ */
+
+#include <linux/netdevice.h>
+#include <linux/etherdevice.h>
+#include <linux/ethtool.h>
+#include <linux/firmware.h>
+#include <uapi/linux/net_tstamp.h>
+
+#include "cxi_eth.h"
+#include "cxi_link.h"
+/*
+ * definitions for CXI_GLOBAL_STATS_LEN, cxi_get_ethtool_stats_set,
+ * and cxi_get_ethtool_stats_name.
+ */
+#include "cxi_ethtool_names.h"
+
+/* Ethtool priv_flags */
+static const char priv_flags_str[PRIV_FLAGS_COUNT][ETH_GSTRING_LEN] = {
+	"internal-loopback",
+	"external-loopback",
+	"llr",
+	"precoding",
+	"ifg-hpc",
+	"roce-opt",
+	"ignore-align",
+	"pml-recovery",
+	"link-train",
+	"remote-fault-recovery",
+	"use-unsupported-cable",
+	"fec_monitor",
+	"auto-lane-degrade",
+	"ignore-media-error",
+	"use-supported-ss200-cable",
+	"los-lol-hide",
+	"r1-link-partner"
+};
+
+/* ethtool ops */
+static void cxi_get_drvinfo(struct net_device *ndev,
+			    struct ethtool_drvinfo *info)
+{
+	struct cxi_eth *dev = netdev_priv(ndev);
+
+	strscpy(info->driver, "cxi_eth", sizeof(info->driver));
+	strscpy(info->version, "0.2", sizeof(info->version));
+	strscpy(info->bus_info, dev_name(ndev->dev.parent),
+		sizeof(info->bus_info));
+	strscpy(info->fw_version, dev->eth_info.fw_version,
+		sizeof(info->fw_version));
+	strscpy(info->erom_version, dev->eth_info.erom_version,
+		sizeof(info->erom_version));
+
+	info->n_priv_flags = PRIV_FLAGS_COUNT;
+}
+
+static int cxi_get_sset_count(struct net_device *ndev, int sset)
+{
+	switch (sset) {
+	case ETH_SS_PRIV_FLAGS:
+		return PRIV_FLAGS_COUNT;
+	case ETH_SS_STATS:
+		return CXI_GLOBAL_STATS_LEN;
+	default:
+		return -EOPNOTSUPP;
+	}
+}
+
+static void cxi_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
+{
+	char *p = data;
+	struct cxi_eth *dev = netdev_priv(ndev);
+	char *dst;
+
+	switch (stringset) {
+	case ETH_SS_PRIV_FLAGS:
+		memcpy(p, priv_flags_str, PRIV_FLAGS_COUNT * ETH_GSTRING_LEN);
+		if (cassini_version(&dev->cxi_dev->prop, CASSINI_1)) {
+			dst = p + 7 * ETH_GSTRING_LEN;
+			memset(dst, 0, ETH_GSTRING_LEN);
+			strscpy(dst, "disable-pml-recovery", ETH_GSTRING_LEN);
+		}
+		break;
+	case ETH_SS_STATS:
+		memcpy(p, cxi_get_ethtool_stats_name, CXI_GLOBAL_STATS_LEN *
+		       ETH_GSTRING_LEN);
+		break;
+
+	}
+}
+
+/* Return the number of RSS queues. */
+static void cxi_get_channels(struct net_device *ndev,
+			     struct ethtool_channels *channels)
+{
+	channels->max_rx = max_rss_queues;
+	channels->max_tx = max_tx_queues;
+	channels->max_combined = 0;
+	channels->max_other = 0;
+	channels->rx_count = ndev->real_num_rx_queues;
+	channels->tx_count = ndev->real_num_tx_queues;
+	channels->other_count = 0;
+	channels->combined_count = 0;
+}
+
+static int cxi_grow_tx_channels(struct cxi_eth *dev,
+				unsigned int num_tx_channels)
+{
+	int i;
+	int rc;
+
+	for (i = dev->cur_txqs; i < num_tx_channels; i++) {
+		rc = alloc_tx_queue(dev, i);
+		if (rc)
+			goto err_free_txqs;
+	}
+
+	for (i = dev->cur_txqs; i < num_tx_channels; i++)
+		enable_tx_queue(&dev->txqs[i]);
+
+	rc = netif_set_real_num_tx_queues(dev->ndev, num_tx_channels);
+	if (rc)
+		goto err_disable_txqs;
+
+	return 0;
+
+err_disable_txqs:
+	for (i = dev->cur_txqs; i < num_tx_channels; i++)
+		disable_tx_queue(&dev->txqs[i]);
+err_free_txqs:
+	while (i > dev->cur_txqs)
+		free_tx_queue(&dev->txqs[--i]);
+
+	return rc;
+}
+
+static int cxi_shrink_tx_channels(struct cxi_eth *dev,
+				  unsigned int num_tx_channels)
+{
+	int i;
+	int rc;
+
+	rc = netif_set_real_num_tx_queues(dev->ndev, num_tx_channels);
+	if (rc)
+		return rc;
+
+	for (i = dev->cur_txqs - 1; i >= num_tx_channels; i--)
+		disable_tx_queue(&dev->txqs[i]);
+
+	for (i = dev->cur_txqs - 1; i >= num_tx_channels; i--)
+		free_tx_queue(&dev->txqs[i]);
+
+	return 0;
+}
+
+int cxi_set_tx_channels(struct cxi_eth *dev, unsigned int num_tx_channels)
+{
+	int rc;
+
+	if (dev->cur_txqs == num_tx_channels)
+		return 0;
+	else if (num_tx_channels < dev->cur_txqs)
+		rc = cxi_shrink_tx_channels(dev, num_tx_channels);
+	else
+		rc = cxi_grow_tx_channels(dev, num_tx_channels);
+
+	if (!rc)
+		dev->cur_txqs = num_tx_channels;
+
+	return rc;
+}
+
+static int cxi_grow_rx_channels(struct cxi_eth *dev,
+				unsigned int num_rx_channels)
+{
+	int rc;
+	int i;
+
+	for (i = dev->res.rss_queues; i < num_rx_channels; i++) {
+		rc = alloc_rx_queue(dev, i);
+		if (rc)
+			goto err_free_rxqs;
+
+		rc = post_rx_buffers(&dev->rxqs[i], GFP_KERNEL);
+		if (rc < 0) {
+			netdev_info(dev->ndev, "Cannot post RX buffers: %d\n",
+				    rc);
+			/* Increment i to free this RXQ. */
+			i++;
+			goto err_free_rxqs;
+		}
+	}
+
+	for (i = dev->res.rss_queues; i < num_rx_channels; i++)
+		enable_rx_queue(&dev->rxqs[i]);
+
+	return 0;
+
+err_free_rxqs:
+	for (i--; i >= dev->res.rss_queues; i--)
+		free_rx_queue(&dev->rxqs[i]);
+
+	return rc;
+}
+
+static void cxi_shrink_rx_channels(struct cxi_eth *dev,
+				   unsigned int num_rx_channels)
+{
+	int i;
+
+	for (i = dev->res.rss_queues - 1; i >= num_rx_channels; i--)
+		disable_rx_queue(&dev->rxqs[i]);
+
+	for (i = dev->res.rss_queues - 1; i >= num_rx_channels; i--)
+		free_rx_queue(&dev->rxqs[i]);
+}
+
+static bool valid_rx_channel_count(unsigned int num_rx_channels)
+{
+	if (!is_power_of_2(num_rx_channels) || num_rx_channels < 1 ||
+	    num_rx_channels > max_rss_queues)
+		return false;
+	return true;
+}
+
+int cxi_set_rx_channels(struct cxi_eth *dev, unsigned int num_rx_channels)
+{
+	unsigned int old_rx_channels = dev->ndev->real_num_rx_queues;
+	int rc;
+	int i;
+
+	if (!valid_rx_channel_count(num_rx_channels))
+		return -EINVAL;
+
+	if (num_rx_channels == dev->res.rss_queues)
+		return 0;
+
+	/* Disable RSS support for all configure MAC addresses/set lists. This
+	 * will temporarily force all traffic to the RXQ 0 which is the
+	 * default/catch-all RX queue.
+	 */
+	cxi_eth_clear_indir_table(dev->cxi_dev, &dev->res);
+
+	rc = netif_set_real_num_rx_queues(dev->ndev, num_rx_channels);
+	if (rc) {
+		cxi_eth_set_indir_table(dev->cxi_dev, &dev->res);
+		goto out;
+	}
+
+	if (num_rx_channels > dev->res.rss_queues) {
+		rc = cxi_grow_rx_channels(dev, num_rx_channels);
+		if (rc) {
+			netif_set_real_num_rx_queues(dev->ndev, old_rx_channels);
+			/* Number of channels have not changed. Re-enable RSS
+			 * and exit.
+			 */
+			cxi_eth_set_indir_table(dev->cxi_dev, &dev->res);
+			goto out;
+		}
+	} else {
+		cxi_shrink_rx_channels(dev, num_rx_channels);
+	}
+
+	dev->res.rss_queues = num_rx_channels;
+	dev->res.rss_indir_size = num_rx_channels > 1 ? rss_indir_size : 0;
+
+	for (i = 0; i < dev->res.rss_queues; i++)
+		dev->res.ptn_rss[i] = dev->rxqs[i].pt->id;
+
+	for (i = 0; i < dev->res.rss_indir_size; i++)
+		dev->res.indir_table[i] =
+			ethtool_rxfh_indir_default(i, dev->res.rss_queues);
+
+	/* Re-enable RSS if number of RX queues is successfully changed. */
+	cxi_eth_set_indir_table(dev->cxi_dev, &dev->res);
+
+out:
+	return rc;
+}
+
+static int cxi_set_channels(struct net_device *ndev,
+			    struct ethtool_channels *ch)
+{
+	struct cxi_eth *dev = netdev_priv(ndev);
+	unsigned int old_tx_channels = dev->cur_txqs;
+	int rc;
+
+	if (ch->combined_count || ch->other_count)
+		return -EINVAL;
+	if (!valid_rx_channel_count(ch->rx_count) || !ch->tx_count ||
+	    ch->tx_count > ndev->num_tx_queues)
+		return -EINVAL;
+
+	/* If interface is not running, update the real TX/RX queue count. The
+	 * real TX/RX queue count is used to initialize TX/RX channels during
+	 * hardware setup.
+	 */
+	if (!netif_running(dev->ndev)) {
+		return netif_set_real_num_queues(ndev, ch->tx_count, ch->rx_count);
+	}
+
+	if (ch->tx_count > old_tx_channels) {
+		rc = cxi_set_tx_channels(dev, ch->tx_count);
+		if (rc)
+			return rc;
+	}
+
+	rc = cxi_set_rx_channels(dev, ch->rx_count);
+	if (rc) {
+		if (ch->tx_count > old_tx_channels)
+			WARN_ON_ONCE(cxi_set_tx_channels(dev, old_tx_channels));
+		return rc;
+	}
+
+	if (ch->tx_count < old_tx_channels)
+		return cxi_set_tx_channels(dev, ch->tx_count);
+	return 0;
+}
+
+static int cxi_get_rxnfc(struct net_device *ndev, struct ethtool_rxnfc *cmd,
+			 u32 *rule_locs)
+{
+	struct cxi_eth *dev = netdev_priv(ndev);
+	int rc;
+
+	switch (cmd->cmd) {
+	case ETHTOOL_GRXRINGS:
+		/* The catch-all queue is always present */
+		cmd->data = dev->res.rss_queues ? : 1;
+		rc = 0;
+		break;
+
+	default:
+		rc = -EOPNOTSUPP;
+		break;
+	}
+
+	return rc;
+}
+
+static u32 cxi_get_rxfh_indir_size(struct net_device *ndev)
+{
+	struct cxi_eth *dev = netdev_priv(ndev);
+
+	return dev->res.rss_indir_size;
+}
+
+static u32 cxi_get_rxfh_key_size(struct net_device *ndev)
+{
+	return CXI_ETH_HASH_KEY_SIZE;
+}
+
+static int cxi_get_rxfh(struct net_device *ndev,
+			struct ethtool_rxfh_param *rxfh)
+{
+	u8 *key = rxfh->key;
+	u8 *hfunc = &rxfh->hfunc;
+	u32 *indir = rxfh->indir;
+
+	struct cxi_eth *dev = netdev_priv(ndev);
+
+	if (hfunc)
+		*hfunc = ETH_RSS_HASH_TOP;
+
+	if (key)
+		cxi_eth_get_hash_key(dev->cxi_dev, key);
+
+	if (indir && dev->res.rss_queues)
+		memcpy(indir, dev->res.indir_table,
+		       dev->res.rss_indir_size * sizeof(u32));
+
+	return 0;
+}
+
+static int cxi_set_rxfh(struct net_device *ndev,
+			struct ethtool_rxfh_param *rxfh,
+			struct netlink_ext_ack *extack)
+{
+	u8 *key = rxfh->key;
+	u8 hfunc = rxfh->hfunc;
+	u32 *indir = rxfh->indir;
+
+	struct cxi_eth *dev = netdev_priv(ndev);
+	int i;
+
+	if (hfunc != ETH_RSS_HASH_NO_CHANGE && hfunc != ETH_RSS_HASH_TOP)
+		return -EINVAL;
+
+	if (key != NULL)
+		return -EINVAL;
+
+	if (indir) {
+		/* Sanity check the table */
+		for (i = 0; i < dev->res.rss_indir_size; i++) {
+			if (indir[i] >= dev->res.rss_queues) {
+				netdev_warn_once(ndev, "Bad new indirection - %d %d\n",
+						 indir[i],
+						 dev->res.rss_queues);
+				return -EINVAL;
+			}
+		}
+
+		memcpy(dev->res.indir_table, indir,
+		       dev->res.rss_indir_size * sizeof(u32));
+		cxi_eth_set_indir_table(dev->cxi_dev, &dev->res);
+	}
+
+	return 0;
+}
+
+static int cxi_get_module_info(struct net_device *ndev,
+			       struct ethtool_modinfo *modinfo)
+{
+	struct cxi_eth *dev = netdev_priv(ndev);
+
+	cxi_eth_devinfo(dev->cxi_dev, &dev->eth_info);
+
+	if (dev->eth_info.qsfp_eeprom_len == 0)
+		return -ENOMEDIUM;
+
+	switch (dev->eth_info.qsfp_eeprom[0]) {
+	case 0xc: /* QSFP */
+	case 0xd: /* QSFP+ */
+		modinfo->type = ETH_MODULE_SFF_8436;
+		modinfo->eeprom_len = ETH_MODULE_SFF_8436_LEN;
+		break;
+	case 0x11: /* QSFP-28 */
+	case 0x1E:
+		modinfo->type = ETH_MODULE_SFF_8636;
+		modinfo->eeprom_len = ETH_MODULE_SFF_8636_LEN;
+		break;
+	default:
+		netdev_err(dev->ndev, "Unsupported transceiver type 0x%x\n",
+			   dev->eth_info.qsfp_eeprom[0]);
+		return -EIO;
+	}
+
+	return 0;
+}
+
+static int cxi_get_module_eeprom(struct net_device *ndev,
+				 struct ethtool_eeprom *eeprom, u8 *data)
+{
+	struct cxi_eth *dev = netdev_priv(ndev);
+	int ret;
+
+	ret = cxi_get_qsfp_data(dev->cxi_dev, eeprom->offset, eeprom->len,
+				0, data);
+
+	if (ret > 0)
+		return 0;
+	else
+		return -EINVAL;
+}
+
+static int cxi_get_module_eeprom_by_page(struct net_device *ndev,
+					 const struct ethtool_module_eeprom *req,
+					 struct netlink_ext_ack *extack)
+{
+	struct cxi_eth *dev = netdev_priv(ndev);
+
+	return cxi_get_qsfp_data(dev->cxi_dev, req->offset, req->length,
+				 req->page, req->data);
+}
+
+static int cxi_flash_device(struct net_device *ndev,
+			    struct ethtool_flash *flash)
+{
+	struct cxi_eth *dev = netdev_priv(ndev);
+	const struct firmware *fw;
+	int rc;
+
+	if (!capable(CAP_SYS_ADMIN))
+		return -EPERM;
+
+	rc = request_firmware(&fw, flash->data, &ndev->dev);
+	if (rc != 0)
+		return rc;
+
+	// TODO? stop adapter
+	rc = cxi_program_firmware(dev->cxi_dev, fw);
+	release_firmware(fw);
+	// TODO? restart adapter
+
+	if (!rc)
+		cxi_eth_devinfo(dev->cxi_dev, &dev->eth_info);
+
+	return rc;
+}
+
+/* Link settings. */
+static int cxi_get_link_ksettings(struct net_device *ndev,
+				  struct ethtool_link_ksettings *s)
+{
+	struct cxi_eth *dev = netdev_priv(ndev);
+	struct cxi_link_info link_info;
+
+	memset(s, 0, sizeof(struct ethtool_link_ksettings));
+
+	cxi_link_mode_get(dev->cxi_dev, &link_info);
+
+	s->base.speed = link_info.speed;
+	s->base.port = link_info.port_type;
+	s->base.duplex = DUPLEX_FULL;
+	s->base.phy_address = 0; /* N/A */
+	s->base.autoneg = link_info.autoneg;
+	s->base.eth_tp_mdix = ETH_TP_MDI;
+	s->base.eth_tp_mdix_ctrl = ETH_TP_MDI;
+
+	ethtool_link_ksettings_add_link_mode(s, supported, Autoneg);
+	ethtool_link_ksettings_add_link_mode(s, supported, FIBRE);
+	ethtool_link_ksettings_add_link_mode(s, supported, TP);
+	ethtool_link_ksettings_add_link_mode(s, supported, Backplane);
+	ethtool_link_ksettings_add_link_mode(s, supported, Pause);
+	if (cassini_version(&dev->cxi_dev->prop, CASSINI_1)) {
+		ethtool_link_ksettings_add_link_mode(s, supported, 50000baseKR_Full);
+		ethtool_link_ksettings_add_link_mode(s, supported, 100000baseCR2_Full);
+		ethtool_link_ksettings_add_link_mode(s, supported, 100000baseCR4_Full);
+		ethtool_link_ksettings_add_link_mode(s, supported, 200000baseCR4_Full);
+		if (s->base.autoneg == AUTONEG_ENABLE)
+			ethtool_link_ksettings_add_link_mode(s, advertising, Autoneg);
+		ethtool_link_ksettings_add_link_mode(s, advertising, Pause);
+		ethtool_link_ksettings_add_link_mode(s, advertising, 50000baseKR_Full);
+		ethtool_link_ksettings_add_link_mode(s, advertising, 100000baseCR2_Full);
+		ethtool_link_ksettings_add_link_mode(s, advertising, 100000baseCR4_Full);
+		ethtool_link_ksettings_add_link_mode(s, advertising, 200000baseCR4_Full);
+	} else if (cassini_version(&dev->cxi_dev->prop, CASSINI_2)) {
+		ethtool_link_ksettings_add_link_mode(s, supported, 100000baseCR2_Full);
+		ethtool_link_ksettings_add_link_mode(s, supported, 200000baseCR4_Full);
+		ethtool_link_ksettings_add_link_mode(s, supported, 400000baseCR4_Full);
+		ethtool_link_ksettings_add_link_mode(s, supported, FEC_RS);
+		if (s->base.autoneg == AUTONEG_ENABLE) {
+			ethtool_link_ksettings_add_link_mode(s, advertising, Autoneg);
+			ethtool_link_ksettings_add_link_mode(s, advertising, 100000baseCR2_Full);
+			ethtool_link_ksettings_add_link_mode(s, advertising, 200000baseCR4_Full);
+			ethtool_link_ksettings_add_link_mode(s, advertising, 400000baseCR4_Full);
+			ethtool_link_ksettings_add_link_mode(s, advertising, FEC_RS);
+		}
+	}
+
+	return 0;
+}
+
+static int
+cxi_set_link_ksettings(struct net_device *ndev,
+		       const struct ethtool_link_ksettings *s)
+{
+	struct cxi_eth *dev = netdev_priv(ndev);
+	struct cxi_link_info link_info;
+
+	cxi_link_mode_get(dev->cxi_dev, &link_info);
+
+	if (s->base.duplex != DUPLEX_UNKNOWN &&
+	    s->base.duplex != DUPLEX_FULL)
+		return -ENOTSUPP;
+
+	if (s->base.eth_tp_mdix != ETH_TP_MDI ||
+	    s->base.eth_tp_mdix_ctrl != ETH_TP_MDI)
+		return -ENOTSUPP;
+
+	if (dev->is_c2 && s->base.autoneg == AUTONEG_ENABLE &&
+	    (link_info.flags & LOOPBACK_MODE) != 0) {
+		netdev_err(ndev,
+			   "autoneg must not be enabled in loopback mode\n");
+		return -EINVAL;
+	}
+
+	link_info.speed = s->base.speed;
+	link_info.autoneg = s->base.autoneg;
+
+	cxi_link_mode_set(dev->cxi_dev, &link_info);
+
+	return 0;
+}
+
+static int cxi_set_priv_flags(struct net_device *ndev, u32 flags)
+{
+	struct cxi_eth *dev = netdev_priv(ndev);
+	struct cxi_link_info link_info;
+	u32 changes;
+	u32 old_flags;
+	u32 debug_flags;
+
+	cxi_link_mode_get(dev->cxi_dev, &link_info);
+	cxi_link_flags_get(dev->cxi_dev, &debug_flags);
+
+	old_flags = dev->priv_flags | link_info.flags | debug_flags;
+
+	changes = flags ^ old_flags;
+
+	if (!changes)
+		return 0;
+
+	if (changes & LOOPBACK_MODE) {
+		u32 loopback_mode = flags & LOOPBACK_MODE;
+
+		if (loopback_mode ==
+		    (CXI_ETH_PF_INTERNAL_LOOPBACK | CXI_ETH_PF_EXTERNAL_LOOPBACK)) {
+			netdev_err(dev->ndev,
+				   "Loopback private flags are mutually exclusive\n");
+			return -EINVAL;
+		}
+	}
+
+	if (changes & flags & LINK_DEBUG_FLAGS &
+	    ~cxi_link_flags_supported(dev->cxi_dev)) {
+		netdev_err(ndev, "Link debug private flag not supported\n");
+		return -EOPNOTSUPP;
+	}
+
+	link_info.flags = flags;
+	cxi_link_mode_set(dev->cxi_dev, &link_info);
+
+	if (changes & CXI_ETH_PF_FEC_MONITOR) {
+		if (flags & CXI_ETH_PF_FEC_MONITOR)
+			dev->priv_flags |= CXI_ETH_PF_FEC_MONITOR;
+		else
+			dev->priv_flags &= ~CXI_ETH_PF_FEC_MONITOR;
+	}
+
+	if (changes & CXI_ETH_PF_ROCE_OPT) {
+		if (flags & CXI_ETH_PF_ROCE_OPT)
+			dev->priv_flags |= CXI_ETH_PF_ROCE_OPT;
+		else
+			dev->priv_flags &= ~CXI_ETH_PF_ROCE_OPT;
+
+		cxi_set_roce_rcv_seg(dev->cxi_dev, flags & CXI_ETH_PF_ROCE_OPT);
+	}
+
+	if (changes & CXI_ETH_PF_IGNORE_ALIGN) {
+		if (flags & CXI_ETH_PF_IGNORE_ALIGN)
+			cxi_link_flags_set(dev->cxi_dev,
+					   0, CXI_ETH_PF_IGNORE_ALIGN);
+		else
+			cxi_link_flags_set(dev->cxi_dev,
+					   CXI_ETH_PF_IGNORE_ALIGN, 0);
+	}
+
+	if (changes & CXI_ETH_PF_PML_REC) {
+		if (flags & CXI_ETH_PF_PML_REC) {
+			dev->priv_flags |= CXI_ETH_PF_PML_REC;
+			cxi_pml_recovery_set(dev->cxi_dev, true);
+		} else {
+			dev->priv_flags &= ~CXI_ETH_PF_PML_REC;
+			cxi_pml_recovery_set(dev->cxi_dev, false);
+		}
+	}
+
+	if (changes & CXI_ETH_PF_REMOTE_FAULT_RECOVERY) {
+		if (flags & CXI_ETH_PF_REMOTE_FAULT_RECOVERY)
+			cxi_link_flags_set(dev->cxi_dev,
+					   0, CXI_ETH_PF_REMOTE_FAULT_RECOVERY);
+		else
+			cxi_link_flags_set(dev->cxi_dev,
+					   CXI_ETH_PF_REMOTE_FAULT_RECOVERY, 0);
+	}
+
+	if (changes & CXI_ETH_PF_USE_UNSUPPORTED_CABLE) {
+		if (flags & CXI_ETH_PF_USE_UNSUPPORTED_CABLE) {
+			dev->priv_flags |= CXI_ETH_PF_USE_UNSUPPORTED_CABLE;
+			cxi_link_use_unsupported_cable(dev->cxi_dev, true);
+		} else {
+			dev->priv_flags &= ~CXI_ETH_PF_USE_UNSUPPORTED_CABLE;
+			cxi_link_use_unsupported_cable(dev->cxi_dev, false);
+		}
+	}
+
+	if (changes & CXI_ETH_PF_USE_SUPPORTED_SS200_CABLE) {
+		if (flags & CXI_ETH_PF_USE_SUPPORTED_SS200_CABLE) {
+			dev->priv_flags |= CXI_ETH_PF_USE_SUPPORTED_SS200_CABLE;
+			cxi_link_use_supported_ss200_cable(dev->cxi_dev, true);
+		} else {
+			dev->priv_flags &= ~CXI_ETH_PF_USE_SUPPORTED_SS200_CABLE;
+			cxi_link_use_supported_ss200_cable(dev->cxi_dev, false);
+		}
+	}
+
+	if (changes & CXI_ETH_PF_IGNORE_MEDIA_ERROR) {
+		if (flags & CXI_ETH_PF_IGNORE_MEDIA_ERROR) {
+			dev->priv_flags |= CXI_ETH_PF_IGNORE_MEDIA_ERROR;
+			cxi_link_ignore_media_error(dev->cxi_dev, true);
+		} else {
+			dev->priv_flags &= ~CXI_ETH_PF_IGNORE_MEDIA_ERROR;
+			cxi_link_ignore_media_error(dev->cxi_dev, false);
+		}
+	}
+
+	if (changes & CXI_ETH_PF_ALD) {
+		if (flags & CXI_ETH_PF_ALD) {
+			dev->priv_flags |= CXI_ETH_PF_ALD;
+			cxi_link_auto_lane_degrade(dev->cxi_dev, true);
+		} else {
+			dev->priv_flags &= ~CXI_ETH_PF_ALD;
+			cxi_link_auto_lane_degrade(dev->cxi_dev, false);
+		}
+	}
+
+	if (changes & CXI_ETH_PF_LOS_LOL_HIDE) {
+		if (flags & CXI_ETH_PF_LOS_LOL_HIDE) {
+			dev->priv_flags |= CXI_ETH_PF_LOS_LOL_HIDE;
+			cxi_link_los_lol_hide(dev->cxi_dev, true);
+		} else {
+			dev->priv_flags &= ~CXI_ETH_PF_LOS_LOL_HIDE;
+			cxi_link_los_lol_hide(dev->cxi_dev, false);
+		}
+	}
+
+	if (changes & CXI_ETH_PF_R1_LINK_PARTNER) {
+		if (flags & CXI_ETH_PF_R1_LINK_PARTNER)
+			dev->priv_flags |= CXI_ETH_PF_R1_LINK_PARTNER;
+		else
+			dev->priv_flags &= ~CXI_ETH_PF_R1_LINK_PARTNER;
+	}
+
+	return 0;
+}
+
+static u32 cxi_get_priv_flags(struct net_device *ndev)
+{
+	struct cxi_eth *dev = netdev_priv(ndev);
+	struct cxi_link_info link_info;
+	u32 debug_flags;
+
+	cxi_link_mode_get(dev->cxi_dev, &link_info);
+	cxi_link_flags_get(dev->cxi_dev, &debug_flags);
+
+	return dev->priv_flags | link_info.flags | debug_flags;
+}
+
+static void cxi_get_ethtool_stats(struct net_device *ndev,
+				  struct ethtool_stats *stats, u64 *data)
+{
+	struct cxi_eth *dev = netdev_priv(ndev);
+	struct cxi_dev *cdev = dev->cxi_dev;
+	int retval;
+	int i;
+
+	retval = cxi_telem_get_selected(cdev, cxi_get_ethtool_stats_set, data,
+					CXI_GLOBAL_STATS_LEN);
+	if (retval != 0)
+		for (i = 0 ; i < CXI_GLOBAL_STATS_LEN ; ++i)
+			data[i] = 0;
+}
+
+static int cxi_get_ts_info(struct net_device *ndev,
+			   struct kernel_ethtool_ts_info *info)
+{
+	struct cxi_eth *dev = netdev_priv(ndev);
+
+	info->so_timestamping =
+		SOF_TIMESTAMPING_RX_SOFTWARE | SOF_TIMESTAMPING_RX_HARDWARE |
+		SOF_TIMESTAMPING_TX_SOFTWARE | SOF_TIMESTAMPING_TX_HARDWARE |
+		SOF_TIMESTAMPING_SOFTWARE | SOF_TIMESTAMPING_RAW_HARDWARE;
+
+	info->phc_index = dev->eth_info.ptp_clock_index;
+
+	info->tx_types = BIT(HWTSTAMP_TX_OFF) | BIT(HWTSTAMP_TX_ON);
+
+	/* The HW only supports PTP Ethernet filter. Timestamp cannot
+	 * be added to PTP UDP packet.
+	 */
+	info->rx_filters = BIT(HWTSTAMP_FILTER_NONE) |
+			   BIT(HWTSTAMP_FILTER_PTP_V2_L2_EVENT);
+
+	return 0;
+}
+
+static void cxi_get_pauseparam(struct net_device *ndev,
+			       struct ethtool_pauseparam *pause)
+{
+	struct cxi_eth *dev = netdev_priv(ndev);
+
+	cxi_eth_get_pause(dev->cxi_dev, pause);
+	pause->autoneg = 0;
+}
+
+static int cxi_set_pauseparam(struct net_device *ndev,
+			      struct ethtool_pauseparam *pause)
+{
+	struct cxi_eth *dev = netdev_priv(ndev);
+
+	if (pause->autoneg != 0)
+		return -EINVAL;
+
+	cxi_eth_set_pause(dev->cxi_dev, pause);
+
+	return 0;
+}
+
+static int cxi_get_fecparam(struct net_device *ndev,
+			    struct ethtool_fecparam *fec)
+{
+	struct cxi_eth *dev = netdev_priv(ndev);
+	struct cxi_link_info link_info;
+
+	cxi_link_mode_get(dev->cxi_dev, &link_info);
+
+	fec->active_fec = link_info.fec_type;
+
+	return 0;
+}
+
+static int cxi_set_fecparam(struct net_device *ndev,
+			    struct ethtool_fecparam *fec)
+{
+	return -ENOTSUPP;
+}
+
+static void cxi_get_ringparam(struct net_device *ndev,
+			      struct ethtool_ringparam *ring,
+			      struct kernel_ethtool_ringparam *kernel_ring,
+			      struct netlink_ext_ack *extack)
+{
+	struct cxi_eth *dev = netdev_priv(ndev);
+
+	*ring = dev->ringparam;
+
+#ifdef ETHTOOL_RING_USE_CQE_SIZE
+	kernel_ring->cqe_size = get_rxq_eq_buf_size(dev) /
+		sizeof(struct c_event_target_enet);
+#endif
+	kernel_ring->rx_buf_len =
+		dev->ringparam.rx_pending * dev->eth_info.max_segment_size +
+		small_pkts_buf_count * small_pkts_buf_size;
+}
+
+static int cxi_set_ringparam(struct net_device *ndev,
+			     struct ethtool_ringparam *ring,
+			     struct kernel_ethtool_ringparam *kernel_ring,
+			     struct netlink_ext_ack *extack)
+{
+	struct cxi_eth *dev = netdev_priv(ndev);
+	int rc = 0;
+
+	if (ring->rx_jumbo_pending)
+		return -EINVAL;
+
+	dev->ringparam.rx_pending = clamp(ring->rx_pending,
+					  LARGE_PKTS_BUF_COUNT_MIN,
+					  LARGE_PKTS_BUF_COUNT_MAX);
+
+	dev->ringparam.rx_mini_pending = num_small_packets(
+		clamp(round_up(ring->rx_mini_pending, 4096) /
+		      (small_pkts_buf_size / buffer_threshold),
+		      SMALL_PKTS_BUF_COUNT_MIN, SMALL_PKTS_BUF_COUNT_MAX));
+
+	dev->ringparam.tx_pending = clamp_t(unsigned int, ring->tx_pending,
+					    1, CXI_MAX_CQ_COUNT);
+
+	if (netif_running(ndev)) {
+		hw_cleanup(dev);
+		rc = hw_setup(dev);
+		if (rc)
+			netdev_err(ndev,
+				   "Failed to restart after ringparam change\n");
+	}
+
+	return rc;
+}
+
+static int cxi_set_phys_id(struct net_device *ndev,
+			   enum ethtool_phys_id_state state)
+{
+	struct cxi_eth *dev = netdev_priv(ndev);
+
+	switch (state) {
+	case ETHTOOL_ID_ACTIVE:
+		cxi_set_led_beacon(dev->cxi_dev, true);
+		return 0;
+
+	case ETHTOOL_ID_INACTIVE:
+		cxi_set_led_beacon(dev->cxi_dev, false);
+		return 0;
+	default:
+		return -EOPNOTSUPP;
+	}
+}
+
+const struct ethtool_ops cxi_eth_ethtool_ops = {
+	.supported_ring_params =
+#ifdef ETHTOOL_RING_USE_CQE_SIZE
+	ETHTOOL_RING_USE_CQE_SIZE |
+#endif
+	ETHTOOL_RING_USE_RX_BUF_LEN,
+	.get_drvinfo	= cxi_get_drvinfo,
+	.get_sset_count	= cxi_get_sset_count,
+	.get_strings	= cxi_get_strings,
+	.get_rxnfc	= cxi_get_rxnfc,
+	.get_channels	= cxi_get_channels,
+	.set_channels	= cxi_set_channels,
+	.get_rxfh_indir_size = cxi_get_rxfh_indir_size,
+	.get_rxfh       = cxi_get_rxfh,
+	.set_rxfh       = cxi_set_rxfh,
+	.get_rxfh_key_size = cxi_get_rxfh_key_size,
+	.get_module_info = cxi_get_module_info,
+	.get_module_eeprom = cxi_get_module_eeprom,
+	.get_module_eeprom_by_page = cxi_get_module_eeprom_by_page,
+	.flash_device   = cxi_flash_device,
+	.get_link	= ethtool_op_get_link,
+	.get_link_ksettings = cxi_get_link_ksettings,
+	.set_link_ksettings = cxi_set_link_ksettings,
+	.get_priv_flags     = cxi_get_priv_flags,
+	.set_priv_flags     = cxi_set_priv_flags,
+	.get_ethtool_stats  = cxi_get_ethtool_stats,
+	.get_ts_info        = cxi_get_ts_info,
+	.set_phys_id        = cxi_set_phys_id,
+	.get_pauseparam     = cxi_get_pauseparam,
+	.set_pauseparam     = cxi_set_pauseparam,
+	.get_fecparam       = cxi_get_fecparam,
+	.set_fecparam       = cxi_set_fecparam,
+	.get_ringparam      = cxi_get_ringparam,
+	.set_ringparam      = cxi_set_ringparam,
+};
diff --git a/drivers/net/ethernet/hpe/ss1/cxi_rxtx_profile.c b/drivers/net/ethernet/hpe/ss1/cxi_rxtx_profile.c
new file mode 100644
index 000000000000..f5c978efd183
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cxi_rxtx_profile.c
@@ -0,0 +1,418 @@
+// SPDX-License-Identifier: GPL-2.0
+/* Copyright (C) 2024 Hewlett Packard Enterprise Development LP */
+
+/* Common parts of RX and TX Profile */
+
+#include "cass_core.h"
+#include "cxi_rxtx_profile.h"
+#include "cxi_rxtx_profile_list.h"
+
+/**
+ * cxi_rxtx_profile_init() - Initialize the common portions
+ *
+ * @rxtx_profile: profile pointer
+ * @hw: Cassini device
+ * @vni_attr: VNI attributes for profile
+ *
+ */
+void cxi_rxtx_profile_init(struct cxi_rxtx_profile *rxtx_profile,
+			   struct cass_dev *hw,
+			   const struct cxi_rxtx_vni_attr *vni_attr)
+{
+	rxtx_profile->vni_attr.match  = vni_attr->match;
+	rxtx_profile->vni_attr.ignore = vni_attr->ignore;
+	strscpy(rxtx_profile->vni_attr.name, vni_attr->name,
+		ARRAY_SIZE(rxtx_profile->vni_attr.name));
+
+	/* Profiles are long lived.  We indicate this by an
+	 * initial reference count of 1, and a release status of false.
+	 *
+	 * The release operation is atomic: it sets the value of
+	 * 'released' to true, and decrements the reference count.
+	 *
+	 * When no references remain, the profile is deleted.
+	 *
+	 * TODO: is revoke still needed?
+	 */
+
+	refcount_set(&rxtx_profile->state.refcount, 1);
+	rxtx_profile->state.enable = false;
+
+	cxi_ac_entry_list_init(&rxtx_profile->ac_entry_list);
+}
+
+/**
+ * cxi_rxtx_profile_destroy() - tear down common portion
+ *
+ * @rxtx_profile: profile pointer
+ */
+void cxi_rxtx_profile_destroy(struct cxi_rxtx_profile *rxtx_profile)
+{
+	/* TODO: make sure these commented functions get */
+	/* implemented in rx and tx profiles... */
+
+	/* cass_vni_entry_disable_hw(vni_entry); */
+	cxi_ac_entry_list_destroy(&rxtx_profile->ac_entry_list);
+}
+
+/**
+ * cxi_rxtx_profile_find_inc_refcount() - Look up RX Profile in the
+ *                                        device list by ID and increment
+ *                                        its refcount.
+ *
+ * @list: profile list
+ * @profile_id: the ID to use for the lookup
+ * @rxtx_profile: location to place rxtx_profile pointer
+ *
+ * Return: 0 on success or error code.
+ *
+ * Note: this function is used internally for cases where we need to
+ * examine a profile even if it is released or revoked.
+ *
+ * Refcount must be decremented when usage is done.
+ */
+int cxi_rxtx_profile_find_inc_refcount(struct cxi_rxtx_profile_list *list,
+				       unsigned int profile_id,
+				       struct cxi_rxtx_profile **rxtx_profile)
+	__must_hold(&list->xarray.xa_lock)
+{
+	struct cxi_rxtx_profile    *profile;
+	int    ret = 0;
+
+	ret = cxi_rxtx_profile_list_retrieve(list, profile_id, &profile);
+	if (ret)
+		goto out;
+
+	if (!refcount_inc_not_zero(&profile->state.refcount)) {
+		ret = -EBADR;
+		goto out;
+	}
+
+	*rxtx_profile = profile;
+
+out:
+	return ret;
+}
+
+/**
+ * cxi_rxtx_profile_release() - Mark a Profile as released.
+ *
+ * No new references can be taken.
+ *
+ * @rxtx_profile: pointer to profile
+ */
+void cxi_rxtx_profile_release(struct cxi_rxtx_profile *rxtx_profile)
+{
+	/* Reduce the reference count.  Note that this function is
+	 * called via pointer to profile, indicating that the caller
+	 * also has a reference to this profile.  Thus the reference
+	 * count after this function returns will be at least 1.
+	 * (Eating the return from cxi_rxtx_profile_dec_refcount() is ok).
+	 */
+	refcount_dec(&rxtx_profile->state.refcount);
+}
+
+/**
+ * cxi_rxtx_profile_revoke() - Revoke the VNI associated with profile.
+ *
+ * RDMA operations for this VNI will fail.  Since the Profile is
+ * essentially dead at this point, 'revoke' implies 'release' as well.
+ *
+ * @rxtx_profile: pointer to profile
+ */
+void cxi_rxtx_profile_revoke(struct cxi_rxtx_profile *rxtx_profile)
+{
+	/* Remove all the Access Control entries associated with
+	 * this Profile.  This ensures it can't be used again.
+	 */
+
+	cxi_ac_entry_list_purge(&rxtx_profile->ac_entry_list);
+
+	/* TODO: this has to be done at the RX or TX layer */
+	/* cass_rx_profile_revoke(rx_profile); */
+
+	cxi_rxtx_profile_release(rxtx_profile);
+}
+
+/**
+ * cxi_rxtx_profile_get_info() - Retrieve the attributes and state associated
+ *                               with this Profile.
+ *
+ * @rxtx_profile: pointer to Profile
+ * @vni_attr: location to place attributes
+ * @state: location to put state
+ *
+ * Note: attr and/or state may be NULL.
+ */
+void cxi_rxtx_profile_get_info(struct cxi_rxtx_profile *rxtx_profile,
+			       struct cxi_rxtx_vni_attr *vni_attr,
+			       struct cxi_rxtx_profile_state *state)
+{
+	if (vni_attr) {
+		vni_attr->ignore   = rxtx_profile->vni_attr.ignore;
+		vni_attr->match    = rxtx_profile->vni_attr.match;
+		strscpy(vni_attr->name, rxtx_profile->vni_attr.name,
+			ARRAY_SIZE(vni_attr->name));
+	}
+
+	if (state) {
+		state->enable = rxtx_profile->state.enable;
+		state->refcount = rxtx_profile->state.refcount;
+	}
+}
+
+/**
+ * cxi_rxtx_profile_add_ac_entry() - add an Access Control entry to
+ *                                   an existing Profile
+ *
+ * @rxtx_profile: pointer to Profile
+ * @ac_type: type of AC Entry to add
+ * @ac_data: UID/GID for AC Entry
+ * @ac_entry_id: location to put AC Entry id on success
+ *
+ * Return:
+ * * 0       - success
+ * * -EBUSY  - AC Entry already exists
+ */
+int cxi_rxtx_profile_add_ac_entry(struct cxi_rxtx_profile *rxtx_profile,
+				  enum cxi_ac_type ac_type,
+				  union cxi_ac_data *ac_data,
+				  unsigned int *ac_entry_id)
+{
+	/* insert will fail with error if data is already present */
+
+	return cxi_ac_entry_list_insert(&rxtx_profile->ac_entry_list, ac_type,
+					ac_data, ac_entry_id);
+}
+
+/**
+ * cxi_rxtx_profile_remove_ac_entry() - disable access control to a Profile
+ *                                      by access control id.
+ *
+ * @rxtx_profile: pointer to profile
+ * @ac_entry_id: id of AC entry
+ *
+ * Return:
+ * * 0       - success
+ * * -EBADR  - ac entry id unknown
+ */
+int cxi_rxtx_profile_remove_ac_entry(struct cxi_rxtx_profile *rxtx_profile,
+				     unsigned int ac_entry_id)
+{
+	return cxi_ac_entry_list_delete(&rxtx_profile->ac_entry_list,
+					ac_entry_id);
+}
+
+/**
+ * cxi_rxtx_profile_get_ac_entry_ids() - get the list of AC entry ids
+ *                                       associated with a Profile
+ *
+ * @rxtx_profile: pointer to Profile
+ * @max_ids: size of the ac_entry_ids array
+ * @ac_entry_ids: location to store ids
+ * @num_ids: number of valid ids in ac_entry_ids array on success
+ *
+ * Return:
+ * * 0       - success
+ * * -ENOSPC - max_ids is not large enough.  num_ids holds value required.
+ */
+int cxi_rxtx_profile_get_ac_entry_ids(struct cxi_rxtx_profile *rxtx_profile,
+				      size_t max_ids,
+				      unsigned int *ac_entry_ids,
+				      size_t *num_ids)
+{
+	return cxi_ac_entry_list_get_ids(&rxtx_profile->ac_entry_list, max_ids,
+					 ac_entry_ids, num_ids);
+}
+
+/**
+ * cxi_rxtx_profile_get_ac_entry_data() - retrieve the type and data for a
+ *                                        AC entry associated with a Profile
+ *
+ * @rxtx_profile: pointer to Profile
+ * @ac_entry_id: id of AC entry
+ * @ac_type: location to store AC entry type
+ * @ac_data: location to store AC data
+ *
+ * Return:
+ * * 0       - success
+ * * -EBADR  - AC entry id unknown
+ */
+int cxi_rxtx_profile_get_ac_entry_data(struct cxi_rxtx_profile *rxtx_profile,
+				       unsigned int ac_entry_id,
+				       enum cxi_ac_type *ac_type,
+				       union cxi_ac_data *ac_data)
+{
+	return cxi_ac_entry_list_retrieve_by_id(&rxtx_profile->ac_entry_list,
+						ac_entry_id, ac_type, ac_data);
+}
+
+/**
+ * cxi_rxtx_profile_get_ac_entry_id_by_data() - get the AC entry id associated
+ *                                              with a Profile for a given
+ *                                              type and data
+ *
+ * @rxtx_profile: pointer to Profile
+ * @ac_type: type of AC entry to look for
+ * @ac_data: AC entry data to look for
+ * @ac_entry_id: location to store AC entry id on success
+ *
+ * Return:
+ * * 0        - success
+ * * -ENODATA - AC entry with given type&data not found
+ * * -EBADR   - invalid ac_type
+ */
+int cxi_rxtx_profile_get_ac_entry_id_by_data(struct cxi_rxtx_profile *rxtx_profile,
+					     enum cxi_ac_type ac_type,
+					     const union cxi_ac_data *ac_data,
+					     unsigned int *ac_entry_id)
+{
+	return cxi_ac_entry_list_retrieve_by_data(&rxtx_profile->ac_entry_list,
+						  ac_type, ac_data, ac_entry_id);
+}
+
+/**
+ * cxi_rxtx_profile_get_ac_entry_id_by_user() - retrieve the AC entry associated
+ *                                              with a Profile by user and group
+ *
+ * @rxtx_profile: pointer to Profile
+ * @uid: user id
+ * @gid: group id
+ * @netns: The Network Namespace id
+ * @desired_types: one or more of the enum cxi_ac_type values OR's together
+ * @ac_entry_id: location to store AC entry id on success
+ *
+ * Return:
+ * * 0       - success
+ * * -EPERM  - no AC entries found for given uid and gid
+ *
+ * Note: multiple AC entries may apply.  The priority of return is
+ * CXI_AC_UID, CXI_AC_GID, CXI_AC_NETNS, CXI_AC_OPEN.
+ */
+int cxi_rxtx_profile_get_ac_entry_id_by_user(struct cxi_rxtx_profile *rxtx_profile,
+					     uid_t uid,
+					     gid_t gid,
+					     unsigned int netns,
+					     cxi_ac_typeset_t desired_types,
+					     unsigned int *ac_entry_id)
+{
+	return cxi_ac_entry_list_retrieve_by_user(&rxtx_profile->ac_entry_list,
+						  uid, gid, netns, desired_types, ac_entry_id);
+}
+
+struct valid_ac_data {
+	uid_t uid;
+	gid_t gid;
+	unsigned int netns;
+};
+
+struct valid_user_data {
+	unsigned int vni;
+	struct valid_ac_data ac_data;
+};
+
+int vni_overlap_test(struct cxi_rxtx_profile *profile1,
+		     void *user_arg)
+{
+	struct cxi_rxtx_profile  *profile2 = user_arg;
+	bool overlap = vni_overlap(&profile1->vni_attr, &profile2->vni_attr);
+
+	/* ignore profiles with 0 VNI */
+	if (zero_vni(&profile1->vni_attr))
+		return 0;
+
+	return overlap ? -EEXIST : 0;
+}
+
+/* Make sure the VNI space is unique */
+bool unique_vni_space(struct cass_dev *hw,
+		      struct cxi_rxtx_profile_list *list,
+		      const struct cxi_rxtx_vni_attr *attr)
+{
+	int rc;
+	struct cxi_rxtx_profile rxtx_prof = {
+		.vni_attr.match = attr->match,
+		.vni_attr.ignore = attr->ignore,
+	};
+
+	cxi_rxtx_profile_list_lock(list);
+
+	rc = cxi_rxtx_profile_list_iterate(list,
+					   vni_overlap_test,
+					   &rxtx_prof);
+
+	cxi_rxtx_profile_list_unlock(list);
+
+	return !rc;
+}
+
+static int valid_vni_operator(struct cxi_rxtx_profile *rxtx_profile,
+			      void *user_data)
+{
+	int rc;
+	bool valid = false;
+	unsigned int ac_entry_id;
+	struct cxi_rxtx_vni_attr vni_attr;
+	struct cxi_rxtx_profile_state state;
+	struct valid_user_data *data = user_data;
+	struct cxi_rxtx_vni_attr user_vni = {
+		.match = data->vni,
+	};
+	struct valid_ac_data ac_data = data->ac_data;
+
+	cxi_rxtx_profile_get_info(rxtx_profile, &vni_attr, &state);
+
+	if (!state.enable)
+		return false;
+
+	/* If there is a vni match, check if user is authorized */
+	if (vni_overlap(&user_vni, &vni_attr)) {
+		rc = cxi_rxtx_profile_get_ac_entry_id_by_user(rxtx_profile,
+							      ac_data.uid,
+							      ac_data.gid,
+							      ac_data.netns,
+							      CXI_AC_ANY,
+							      &ac_entry_id);
+		if (!rc)
+			valid = true;
+	}
+
+	return valid;
+}
+
+/**
+ * cxi_valid_vni() - Check if user has permission to use a VNI by searching
+ *                   for a profile containing the VNI.
+ *
+ * @dev: Cassini Device
+ * @type: TX or RX profile
+ * @vni: VNI to verify
+ *
+ * Return:
+ * * true if VNI is valid
+ */
+bool cxi_valid_vni(struct cxi_dev *dev, enum cxi_profile_type type,
+		   unsigned int vni)
+{
+	struct cxi_rxtx_profile_list *list;
+	bool valid;
+	struct cass_dev *hw = container_of(dev, struct cass_dev, cdev);
+	struct valid_user_data user_data = {
+		.vni = vni,
+		.ac_data = {
+			.uid = __kuid_val(current_euid()),
+			.gid = __kgid_val(current_egid()),
+			.netns = CURRENT_NETNS_ID(),
+		},
+	};
+
+	if (type == CXI_PROF_RX)
+		list = &hw->rx_profile_list;
+	else
+		list = &hw->tx_profile_list;
+
+	cxi_rxtx_profile_list_lock(list);
+	valid = cxi_rxtx_profile_list_iterate(list, valid_vni_operator, &user_data);
+	cxi_rxtx_profile_list_unlock(list);
+	return valid;
+}
diff --git a/drivers/net/ethernet/hpe/ss1/cxi_rxtx_profile_list.c b/drivers/net/ethernet/hpe/ss1/cxi_rxtx_profile_list.c
new file mode 100644
index 000000000000..605f08abe53c
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/cxi_rxtx_profile_list.c
@@ -0,0 +1,249 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/* Copyright (C) 2024 Hewlett Packard Enterprise Development LP */
+
+/* RX Profile and TX Profile List Implementations */
+
+#include "cass_core.h"
+#include "cxi_rxtx_profile_list.h"
+
+/* **************************************************************** */
+/* RXTX Profile List implementation                                 */
+/* **************************************************************** */
+
+/**
+ * cxi_rxtx_profile_list_init() - initialize the Profile list object
+ *
+ * @list: address of list object
+ * @limits: address of index limits struct
+ * @flags: optional flags for xarray
+ * @gfp_opts: memory allocation options for xarray
+ */
+void cxi_rxtx_profile_list_init(struct cxi_rxtx_profile_list *list,
+				struct xa_limit *limits,
+				gfp_t flags,
+				gfp_t gfp_opts)
+{
+	xa_init_flags(&list->xarray, flags);
+
+	list->limits   = limits;
+	list->flags    = flags;
+	list->gfp_opts = gfp_opts;
+}
+
+/**
+ * cxi_rxtx_profile_list_destroy() - remove all Profile references
+ * from the list and free the underlying resources.
+ *
+ * @list: address of list
+ * @cleanup: function to call for additional cleanup processing of each
+ *           profile in the list
+ * @user_arg: second arg to cleanup function
+ */
+void cxi_rxtx_profile_list_destroy(struct cxi_rxtx_profile_list *list,
+				   void (*cleanup)(struct cxi_rxtx_profile *profile,
+						   void *user_arg),
+				   void *user_arg)
+{
+	unsigned long              index;
+	struct cxi_rxtx_profile    *profile;
+
+	index = list->limits->min;
+
+	xa_lock(&list->xarray);
+
+	xa_for_each(&list->xarray, index, profile) {
+		__xa_erase(&list->xarray, index);
+		if (cleanup)
+			cleanup(profile, user_arg);
+	}
+
+	xa_unlock(&list->xarray);
+	xa_destroy(&list->xarray);
+}
+
+/**
+ * cxi_rxtx_profile_list_lock() - lock the list
+ *
+ * @list: address of list
+ */
+void cxi_rxtx_profile_list_lock(struct cxi_rxtx_profile_list *list)
+	__acquires(&list->xarray.xa_lock)
+{
+	xa_lock(&list->xarray);
+}
+
+/**
+ * cxi_rxtx_profile_list_unlock() - unlock the list
+ *
+ * @list: address of list
+ */
+void cxi_rxtx_profile_list_unlock(struct cxi_rxtx_profile_list *list)
+	__releases(&list->xarray.xa_lock)
+{
+	xa_unlock(&list->xarray);
+}
+
+/**
+ * cxi_rxtx_profile_list_insert() - Allocate a free Id and
+ *                                  add a Profile to the list.
+ *
+ * @list: address of list
+ * @profile: address of Profile to add
+ * @profile_id: location to store newly allocated Id on success
+ *
+ * Return:
+ * * 0 - success
+ *
+ * Errors related to memory allocation failures are also possible.
+ */
+int cxi_rxtx_profile_list_insert(struct cxi_rxtx_profile_list *list,
+				 struct cxi_rxtx_profile *profile,
+				 unsigned int *profile_id)
+	__must_hold(&list->xarray.xa_lock)
+{
+	int    ret;
+
+	ret = __xa_alloc(&list->xarray, &profile->id, profile,
+			 *list->limits, list->gfp_opts);
+
+	if (!ret)
+		*profile_id = profile->id;
+
+	return ret;
+}
+
+/**
+ * cxi_rxtx_profile_list_remove() - remove the Profile from the list
+ *
+ * @list: address of list struct
+ * @rxtx_profile_id: index of Profile
+ *
+ * Return: 0 on success
+ * -EBADR: Profile struct is not in list
+ */
+int cxi_rxtx_profile_list_remove(struct cxi_rxtx_profile_list *list,
+				 unsigned int rxtx_profile_id)
+{
+	struct cxi_rxtx_profile   *previous_entry;
+
+	previous_entry = xa_erase(&list->xarray, rxtx_profile_id);
+
+	return previous_entry ? 0 : -EBADR;
+}
+
+/**
+ * cxi_rxtx_profile_list_retrieve() - get the pointer to a Profile by Id
+ *
+ * @list: address of list
+ * @profile_id: Id of desired Profile
+ * @profile: location to place Profile pointer
+ *
+ * Return: 0 on success
+ * -EBADR: Profile with desired Id not found.
+ */
+int cxi_rxtx_profile_list_retrieve(struct cxi_rxtx_profile_list *list,
+				   unsigned int profile_id,
+				   struct cxi_rxtx_profile **profile)
+{
+	struct cxi_rxtx_profile  *my_profile;
+	int    ret;
+
+	my_profile = xa_load(&list->xarray, profile_id);
+	ret = xa_err(my_profile);
+
+	if (ret)
+		return ret;
+
+	*profile = my_profile;
+
+	return my_profile ? 0 : -EBADR;
+}
+
+/**
+ * cxi_rxtx_profile_list_iterate() - walk list and call function on each member.
+ *
+ * @list: address of list
+ * @operator: function to call (see below).
+ * @user_args: other data to pass to operator (see below).
+ *
+ * This iterator calls the function 'operator(profile, user_args)' for each
+ * profile in the list.
+ * Iteration continues as long as the return value of 'operator' is 0.
+ *
+ * The return value of the iterator function is the final return value
+ * of the operator.
+ *
+ * The caller may lock the list during iteration but it is not required.
+ */
+int cxi_rxtx_profile_list_iterate(struct cxi_rxtx_profile_list *list,
+				  int (*operator)(struct cxi_rxtx_profile *profile,
+						  void *user_args),
+				  void *user_args)
+{
+	struct cxi_rxtx_profile    *profile;
+	unsigned long              index;
+
+	index = list->limits->min;
+
+	xa_for_each(&list->xarray, index, profile) {
+		int ret = operator(profile, user_args);
+
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+struct get_ids_data {
+	size_t         max_ids;
+	unsigned int   *ids;
+	size_t         num_ids;
+};
+
+static int get_ids_operator(struct cxi_rxtx_profile *rxtx_profile,
+			    void *user_data)
+{
+	struct get_ids_data   *data = user_data;
+
+	if (data->num_ids < data->max_ids) {
+		*data->ids = rxtx_profile->id;
+		data->ids++;
+	}
+
+	data->num_ids++;
+	return 0;
+}
+
+/**
+ * cxi_rxtx_profile_list_get_ids() - Get a list of the active IDs
+ *
+ * @list: address of list
+ * @max_ids: size of the ids array
+ * @ids: array to put ids in
+ * @num_ids: number of valid IDs in ids
+ *
+ * Return:
+ * * 0       - success
+ * * -ENOSPC - max_ids is not large enough, num_ids hold required value
+ */
+int cxi_rxtx_profile_list_get_ids(struct cxi_rxtx_profile_list *list,
+				  size_t max_ids,
+				  unsigned int *ids,
+				  size_t *num_ids)
+{
+	struct get_ids_data   data = {
+		.max_ids = max_ids,
+		.ids     = ids,
+		.num_ids = 0,
+	};
+	int    ret;
+
+	ret = cxi_rxtx_profile_list_iterate(list, get_ids_operator, &data);
+	if (ret)
+		return ret;
+
+	*num_ids = data.num_ids;
+
+	return (data.num_ids > max_ids) ? -ENOSPC : 0;
+}

-- 
2.56.0


^ permalink raw reply	[flat|nested] 25+ messages in thread
* [PATCH 23/23] net: hpe: wire up the Slingshot NIC drivers
  2026-10-30 20:58 [PATCH 00/23] Subject: [PATCH net-next 00/23] net/hpe: add HPE Slingshot NIC drivers Doug Ledford
                   ` (21 preceding siblings ...)
  2026-10-30 20:59 ` [PATCH 22/23] net: hpe: ss1: add the Ethernet personality Doug Ledford
@ 2026-10-30 20:59 ` Doug Ledford
  2026-10-30 22:11 ` [PATCH 00/23] Subject: [PATCH net-next 00/23] net/hpe: add HPE " Jakub Kicinski
  23 siblings, 0 replies; 25+ messages in thread
From: Doug Ledford @ 2026-10-30 20:59 UTC (permalink / raw)
  To: Slingshot Open Source Team, Nathan Chancellor, Nicolas Schier,
	Richard Cochran, Andrew Lunn, David S. Miller, Eric Dumazet,
	Jakub Kicinski, Paolo Abeni, Sumit Semwal, Christian König,
	Guenter Roeck
  Cc: linux-kernel, netdev, linux-kbuild, Doug Ledford

Hook the SBL, SL and SS1 drivers into the build and add the MAINTAINERS
entry.

 - NET_VENDOR_HPE gates the vendor menu; CONFIG_HPE_SS1 builds cxi-ss1
   (the core driver) and cxi-eth (the Ethernet personality) and
   selects HPE_SBL (cxi-sbl, 200 Gb/s link) and HPE_SL (cxi-sl, 400 Gb/s
   link), because the core driver picks the link layer at run time
   according to the NIC generation
 - the module names keep the cxi- prefix used by the existing user
   space tools and udev rules

checkpatch --strict (100 columns) still reports the following in this
patch. They need coordination with the internal repositories this code
is maintained in and will be fixed in V2:
- WARNING: MAINTAINERS_STYLE (1)

Signed-off-by: Doug Ledford <doug.ledford@hpe.com>
---
 MAINTAINERS                           |   7 ++
 drivers/net/ethernet/Kconfig          |   1 +
 drivers/net/ethernet/Makefile         |   1 +
 drivers/net/ethernet/hpe/Kconfig      |  26 +++++++
 drivers/net/ethernet/hpe/Makefile     |   8 ++
 drivers/net/ethernet/hpe/sbl/Kconfig  |  15 ++++
 drivers/net/ethernet/hpe/sbl/Makefile |  21 +++++
 drivers/net/ethernet/hpe/sl/Kconfig   |  15 ++++
 drivers/net/ethernet/hpe/sl/Makefile  | 140 ++++++++++++++++++++++++++++++++++
 drivers/net/ethernet/hpe/ss1/Kconfig  |  35 +++++++++
 drivers/net/ethernet/hpe/ss1/Makefile |  28 +++++++
 11 files changed, 297 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 7336600952c8..4974717d22c1 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11608,6 +11608,13 @@ S:	Supported
 F:	Documentation/watchdog/hpwdt.rst
 F:	drivers/watchdog/hpwdt.c
 
+HEWLETT PACKARD ENTERPRISE SLINGSHOT NIC DRIVER
+M:	Slingshot Open Source Team <slingshot-os-team@groups.ext.hpe.com>
+L:	netdev@vger.kernel.org
+S:	Supported
+F:	include/linux/hpe
+F:	drivers/net/ethernet/hpe
+
 HEWLETT-PACKARD SMART ARRAY RAID DRIVER (hpsa)
 M:	Don Brace <don.brace@microchip.com>
 L:	storagedev@microchip.com
diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig
index c2b0161d0bec..c6f3c722ca98 100644
--- a/drivers/net/ethernet/Kconfig
+++ b/drivers/net/ethernet/Kconfig
@@ -65,6 +65,7 @@ source "drivers/net/ethernet/freescale/Kconfig"
 source "drivers/net/ethernet/fungible/Kconfig"
 source "drivers/net/ethernet/google/Kconfig"
 source "drivers/net/ethernet/hisilicon/Kconfig"
+source "drivers/net/ethernet/hpe/Kconfig"
 source "drivers/net/ethernet/huawei/Kconfig"
 source "drivers/net/ethernet/i825xx/Kconfig"
 source "drivers/net/ethernet/ibm/Kconfig"
diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile
index a306dae23bcb..65e00a93049b 100644
--- a/drivers/net/ethernet/Makefile
+++ b/drivers/net/ethernet/Makefile
@@ -44,6 +44,7 @@ obj-$(CONFIG_NET_VENDOR_FREESCALE) += freescale/
 obj-$(CONFIG_NET_VENDOR_FUNGIBLE) += fungible/
 obj-$(CONFIG_NET_VENDOR_GOOGLE) += google/
 obj-$(CONFIG_NET_VENDOR_HISILICON) += hisilicon/
+obj-$(CONFIG_NET_VENDOR_HPE) += hpe/
 obj-$(CONFIG_NET_VENDOR_HUAWEI) += huawei/
 obj-$(CONFIG_NET_VENDOR_IBM) += ibm/
 obj-$(CONFIG_NET_VENDOR_INTEL) += intel/
diff --git a/drivers/net/ethernet/hpe/Kconfig b/drivers/net/ethernet/hpe/Kconfig
new file mode 100644
index 000000000000..c43172a62cf6
--- /dev/null
+++ b/drivers/net/ethernet/hpe/Kconfig
@@ -0,0 +1,26 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# HPE/Cray driver configuration
+# Copyright 2025 Hewlett Packard Enterprise Development LP
+
+config NET_VENDOR_HPE
+	bool "Hewlett Packard Enterprise/Cray devices"
+	default n
+	depends on PCI
+	help
+	  If you have a network (Ethernet or RDMA) manufactured by HPE/Cray,
+	  say Y.
+
+	  Note that the answer to this question doesn't directly affect the
+	  kernel: saying N will just cause the configurator to skip all
+	  the questions about HPE cards. If you say Y, you will be asked
+	  for your specific card in the following questions.
+
+if NET_VENDOR_HPE
+
+source "drivers/net/ethernet/hpe/sbl/Kconfig"
+source "drivers/net/ethernet/hpe/sl/Kconfig"
+source "drivers/net/ethernet/hpe/ss1/Kconfig"
+
+
+endif # NET_VENDOR_HPE
diff --git a/drivers/net/ethernet/hpe/Makefile b/drivers/net/ethernet/hpe/Makefile
new file mode 100644
index 000000000000..692886cac9ef
--- /dev/null
+++ b/drivers/net/ethernet/hpe/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Makefile for HPE/Cray device drivers.
+# Copyright 2025 Hewlett Packard Enterprise Development LP
+
+obj-$(CONFIG_HPE_SBL)	+= sbl/
+obj-$(CONFIG_HPE_SL)	+= sl/
+obj-$(CONFIG_HPE_SS1)	+= ss1/
diff --git a/drivers/net/ethernet/hpe/sbl/Kconfig b/drivers/net/ethernet/hpe/sbl/Kconfig
new file mode 100644
index 000000000000..929224e44a43
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sbl/Kconfig
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0
+
+#
+# Slingshot base link module Kconfig
+#
+
+config HPE_SBL
+	tristate "HPE/Cray Slingshot 200Gbs Link Support"
+	depends on HPE_SS1
+	help
+	  Compile the cxi-sbl module, which provides link management support
+	  for Slingshot 200Gbs devices/fabrics.
+
+	  The cxi-ss1 driver automatically enables this driver whenever
+	  it is enabled.
diff --git a/drivers/net/ethernet/hpe/sbl/Makefile b/drivers/net/ethernet/hpe/sbl/Makefile
new file mode 100644
index 000000000000..9f61e04fe7bf
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sbl/Makefile
@@ -0,0 +1,21 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Slingshot base link 200Gbs module
+#
+
+subdir-ccflags-y := -I$(src)
+
+obj-$(CONFIG_HPE_SBL)	:= cxi-sbl.o
+
+# These base modules work for both NIC and Switch parts
+cxi-sbl-$(CONFIG_HPE_SBL)	:= sbl_pml_pcs.o sbl_link.o \
+	sbl_link_an.o sbl_media.o sbl_pml.o sbl_pml_mac.o \
+	sbl_pml_llr.o sbl_timers.o sbl_debug.o sbl_serdes_fn.o \
+	sbl_test.o sbl_sbm_serdes.o sbl_counters.o sbl_fec.o \
+	sbl_serdes.o sbl_inst.o sbl_pml_serdes_op.o sbl_misc.o \
+	sbl_internal.o
+# Everything after here is specific to NICs
+cxi-sbl-$(CONFIG_HPE_SBL)	+= \
+	sbl_pml_pcs_nic.o sbl_module_nic.o sbl_link_nic.o \
+	sbl_media_nic.o sbl_inst_nic.o sbl_sbm_serdes_nic.o \
+	sbl_fec_nic.o sbl_link_an_nic.o sbl_pml_llr_nic.o
diff --git a/drivers/net/ethernet/hpe/sl/Kconfig b/drivers/net/ethernet/hpe/sl/Kconfig
new file mode 100644
index 000000000000..2935fec855f8
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/Kconfig
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0
+
+#
+# Slingshot link 400Gbs module Kconfig
+#
+
+config HPE_SL
+	tristate "HPE/Cray Slingshot 400Gbs Link Support"
+	depends on HPE_SS1
+	help
+	  Compile the cxi-sl module, which provides link management support
+	  for Slingshot 400Gbs devices/fabrics.
+
+	  The cxi-ss1 driver automatically enables this driver whenever
+	  it is enabled.
diff --git a/drivers/net/ethernet/hpe/sl/Makefile b/drivers/net/ethernet/hpe/sl/Makefile
new file mode 100644
index 000000000000..1930da475e59
--- /dev/null
+++ b/drivers/net/ethernet/hpe/sl/Makefile
@@ -0,0 +1,140 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Slingshot base link 400Gbs module makefile
+#
+
+CAS_DEFINES := -DCONFIG_SL_BUILD_NAME="cassini" -DSL_NAME=cxi-sl
+
+subdir-ccflags-y += -I$(src) -I$(src)/nic -I$(src)/core/hw/nic \
+	-I$(src)/log -I$(src)/media -I$(src)/ctrl -I$(src)/sysfs \
+	-I$(src)/core $(CAS_DEFINES)
+
+obj-$(CONFIG_HPE_SL)	:= cxi-sl.o
+
+# These base modules work for both NIC and Switch parts
+cxi-sl-$(CONFIG_HPE_SL)	:= sl_module.o sl_ldev.o sl_lgrp.o sl_link.o \
+	sl_llr.o sl_mac.o sl_media.o sl_fec.o
+cxi-sl-$(CONFIG_HPE_SL)	+= media/sl_media_lgrp.o \
+	media/sl_media_ldev.o \
+	media/sl_media_jack.o \
+	media/data/sl_media_data_ldev.o \
+	media/data/sl_media_data_lgrp.o \
+	media/data/sl_media_data_lgrp_trace.o \
+	media/data/sl_media_data_jack.o \
+	media/data/sl_media_data_cable_db_ops.o \
+	media/base/sl_media_eeprom.o
+cxi-sl-$(CONFIG_HPE_SL)	+= core/sl_core_ldev.o \
+	core/sl_core_lgrp.o \
+	core/sl_core_link.o \
+	core/sl_core_link_an.o \
+	core/sl_core_link_fec.o \
+	core/sl_core_mac.o \
+	core/sl_core_llr.o \
+	core/sl_core_str.o \
+	core/base/sl_core_timer_link.o \
+	core/base/sl_core_timer_llr.o \
+	core/data/sl_core_data_ldev.o \
+	core/data/sl_core_data_lgrp.o \
+	core/data/sl_core_data_lgrp_trace.o \
+	core/data/sl_core_data_link.o \
+	core/data/sl_core_data_llr.o \
+	core/data/sl_core_data_mac.o \
+	core/hw/sl_core_hw_intr.o \
+	core/hw/sl_core_hw_intr_llr.o \
+	core/hw/sl_core_hw_sbus.o \
+	core/hw/sl_core_hw_pmi.o \
+	core/hw/sl_core_hw_sbus_pmi.o \
+	core/hw/sl_core_hw_uc_ram.o \
+	core/hw/sl_core_hw_serdes.o \
+	core/hw/sl_core_hw_serdes_fw.o \
+	core/hw/sl_core_hw_serdes_core.o \
+	core/hw/sl_core_hw_serdes_link.o \
+	core/hw/sl_core_hw_serdes_lane.o \
+	core/hw/sl_core_hw_serdes_lane_tx.o \
+	core/hw/sl_core_hw_serdes_lane_rx.o \
+	core/hw/sl_core_hw_link.o \
+	core/hw/sl_core_hw_an.o \
+	core/hw/sl_core_hw_an_lp.o \
+	core/hw/sl_core_hw_an_up.o \
+	core/hw/sl_core_hw_pcs.o \
+	core/hw/sl_core_hw_mac.o \
+	core/hw/sl_core_hw_llr.o \
+	core/hw/sl_core_hw_reset.o
+
+cxi-sl-$(CONFIG_HPE_SL)	+= ctrl/sl_ctrl_ldev.o \
+	ctrl/sl_ctrl_lgrp.o \
+	ctrl/sl_ctrl_lgrp_notif.o \
+	ctrl/sl_ctrl_link.o \
+	ctrl/sl_ctrl_link_priv.o \
+	ctrl/sl_ctrl_link_fec.o \
+	ctrl/sl_ctrl_link_fec_priv.o \
+	ctrl/sl_ctrl_link_counters.o \
+	ctrl/sl_ctrl_mac.o \
+	ctrl/sl_ctrl_mac_counters.o \
+	ctrl/sl_ctrl_llr.o \
+	ctrl/sl_ctrl_llr_counters.o \
+	ctrl/sl_ctrl_media_counters.o \
+	ctrl/data/sl_ctrl_data_lgrp.o \
+	ctrl/data/sl_ctrl_data_lgrp_trace.o \
+	ctrl/data/sl_ctrl_data_link.o \
+	ctrl/data/sl_ctrl_data_llr.o
+
+cxi-sl-$(CONFIG_HPE_SL)	+= log/sl_log.o \
+	sysfs/sl_sysfs_ldev.o \
+	sysfs/sl_sysfs_lgrp.o \
+	sysfs/sl_sysfs_lgrp_policy.o \
+	sysfs/sl_sysfs_lgrp_config.o \
+	sysfs/sl_sysfs_link.o \
+	sysfs/sl_sysfs_link_policy.o \
+	sysfs/sl_sysfs_link_fec_mon_check.o \
+	sysfs/sl_sysfs_link_fec_up_check.o \
+	sysfs/sl_sysfs_link_config.o \
+	sysfs/sl_sysfs_link_degrade.o \
+	sysfs/sl_sysfs_link_pml_rec.o \
+	sysfs/sl_sysfs_link_caps.o \
+	sysfs/sl_sysfs_link_fec.o \
+	sysfs/sl_sysfs_link_fec_current.o \
+	sysfs/sl_sysfs_link_fec_up.o \
+	sysfs/sl_sysfs_link_fec_down.o \
+	sysfs/sl_sysfs_link_counters.o \
+	sysfs/sl_sysfs_pmi.o \
+	sysfs/sl_sysfs_pmi_rd.o \
+	sysfs/sl_sysfs_pmi_wr.o \
+	sysfs/sl_sysfs_sbus.o \
+	sysfs/sl_sysfs_sbus_rd.o \
+	sysfs/sl_sysfs_sbus_wr.o \
+	sysfs/sl_sysfs_sbus_rst.o \
+	sysfs/sl_sysfs_sbus_pmi.o \
+	sysfs/sl_sysfs_sbus_pmi_rd.o \
+	sysfs/sl_sysfs_sbus_pmi_wr.o \
+	sysfs/sl_sysfs_serdes.o \
+	sysfs/sl_sysfs_serdes_settings.o \
+	sysfs/sl_sysfs_serdes_eye.o \
+	sysfs/sl_sysfs_serdes_lol.o \
+	sysfs/sl_sysfs_serdes_los.o \
+	sysfs/sl_sysfs_serdes_state.o \
+	sysfs/sl_sysfs_serdes_swizzle.o \
+	sysfs/sl_sysfs_llr.o \
+	sysfs/sl_sysfs_llr_config.o \
+	sysfs/sl_sysfs_llr_counters.o \
+	sysfs/sl_sysfs_llr_policy.o \
+	sysfs/sl_sysfs_llr_loop_time.o \
+	sysfs/sl_sysfs_mac.o \
+	sysfs/sl_sysfs_mac_counters.o \
+	sysfs/sl_sysfs_media.o \
+	sysfs/sl_sysfs_media_counters.o
+
+# Everything after here is specific to NICs
+cxi-sl-$(CONFIG_HPE_SL)	+= nic/sl_ldev.o nic/sl_media.o \
+	media/nic/sl_media_io.o media/nic/sl_media_jack.o \
+	media/nic/sl_media_ldev.o \
+	media/data/nic/sl_media_data_ldev.o \
+	media/data/nic/sl_media_data_jack.o \
+	media/data/nic/sl_media_data_jack_emu.o \
+	core/hw/nic/sl_core_hw_fec.o \
+	core/hw/nic/sl_core_hw_llr.o \
+	core/hw/nic/sl_core_hw_an.o \
+	core/hw/nic/sl_core_hw_mac.o \
+	core/hw/nic/sl_core_hw_pcs.o \
+	core/data/nic/sl_core_data_link.o \
+	core/data/nic/sl_core_data_mac.o
diff --git a/drivers/net/ethernet/hpe/ss1/Kconfig b/drivers/net/ethernet/hpe/ss1/Kconfig
new file mode 100644
index 000000000000..d154506749d1
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/Kconfig
@@ -0,0 +1,35 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Kernel config for HPE/Cray Net Cassini Slingshot 200/400Gbs hardware
+# Copyright 2025 Hewlett Packard Enterprise Development LP
+
+config HPE_SS1
+	tristate "HPE/Cray Slingshot 200/400Gbs NIC driver"
+	depends on PCI && ETHERNET && NETDEVICES && INET
+	depends on (ARM64 && CPU_LITTLE_ENDIAN) || X86_64
+	select HPE_SBL
+	select HPE_SL
+	select CONFIGFS_FS
+	select AUXILIARY_BUS
+	help
+	  Core and Ethernet driver for the HPE/Cray Cassini network
+	  interface cards, used with Slingshot 200 and 400 Gbs fabrics.
+
+	  This builds the cxi-ss1 core driver and the cxi-eth Ethernet
+	  personality. The link layer modules cxi-sbl (200 Gbs) and
+	  cxi-sl (400 Gbs) are selected as well. Other drivers, such as
+	  the CXI RDMA driver, attach to cxi-ss1 as auxiliary devices.
+
+	  To compile this driver as modules, choose M here: the modules
+	  will be called cxi-ss1 and cxi-eth. If unsure, say N.
+
+config HPE_SS1_P2P_DMABUF
+	bool "Enable Peer-2-Peer dmabuf support"
+	depends on HPE_SS1 && PCI_P2PDMA
+	help
+	  Enable PCI Peer-2-Peer dmabuf support. This allows the NIC to
+	  DMA directly to and from device memory, such as GPU memory,
+	  that is exported through dma-buf, without staging it in
+	  host memory. It requires a PCI P2P DMA capable platform.
+
+	  If unsure, say N.
diff --git a/drivers/net/ethernet/hpe/ss1/Makefile b/drivers/net/ethernet/hpe/ss1/Makefile
new file mode 100644
index 000000000000..538ac762cff2
--- /dev/null
+++ b/drivers/net/ethernet/hpe/ss1/Makefile
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: GPL-2.0
+#
+# Makefile for HPE/Cray Net Cassini Slingshot version 200/400Gbs hardware
+# Copyright 2025 Hewlett Packard Enterprise Development LP
+
+subdir-ccflags-y += -I$(src)
+
+obj-$(CONFIG_HPE_SS1) += cxi-ss1.o cxi-eth.o
+
+cxi-ss1-objs := cxi_core.o cass_core.o cass_lni.o cass_rmu.o cass_eq.o \
+		cass_cpt.o cass_cq.o cass_pt.o cass_atu.o cass_ct.o \
+		cass_errors.o cass_sriov.o cass_nta.o cass_ptp.o \
+		cass_hni.o cass_eth.o cass_rmu_eth.o cass_ats.o cass_uc.o \
+		cass_hmm.o cxi_qos_profiles.o cass_tc.o cass_svc.o \
+		cass_telem.o cxi_link.o cass_sbl.o cass_sl.o \
+		cass_sl_io.o cass_sysfs.o cass_sbus.o cass_phy.o \
+		cass_dmac.o cass_link.o cass_link_misc.o cass_port_misc.o \
+		cass_lmon.o cass_ixe.o cass_irq.o cass_cable.o \
+		cass_odp_decouple.o cass_ats_inval.o cass_pcie_mon.o \
+		cxi_ac_entry_list.o cass_dev_info.o cxi_rxtx_profile_list.o \
+		cass_rx_tx_profile.o cxi_rxtx_profile.o cxi_config.o \
+		cxi_rx_profile.o cxi_tx_profile.o \
+		cass_rgroup.o cxi_rgroup.o cass_rgid.o cxi_aux_dev.o cass_vf_notif.o \
+		cass_vf.o
+cxi-ss1-$(CONFIG_DEBUG_FS) += cass_ss1_debugfs.o
+cxi-ss1-$(CONFIG_HPE_SS1_P2P_DMABUF) += cass_p2p.o cass_dma_buf.o
+cxi-eth-objs := cxi_eth.o cxi_eth_ops.o cxi_ethtool.o cxi_eth_ioctl.o
+cxi-eth-$(CONFIG_DEBUG_FS) += cxi_eth_debugfs.o

-- 
2.56.0


^ permalink raw reply	[flat|nested] 25+ messages in thread
* Re: [PATCH 00/23] Subject: [PATCH net-next 00/23] net/hpe: add HPE Slingshot NIC drivers
  2026-10-30 20:58 [PATCH 00/23] Subject: [PATCH net-next 00/23] net/hpe: add HPE Slingshot NIC drivers Doug Ledford
                   ` (22 preceding siblings ...)
  2026-10-30 20:59 ` [PATCH 23/23] net: hpe: wire up the Slingshot NIC drivers Doug Ledford
@ 2026-10-30 22:11 ` Jakub Kicinski
  23 siblings, 0 replies; 25+ messages in thread
From: Jakub Kicinski @ 2026-10-30 22:11 UTC (permalink / raw)
  To: Doug Ledford
  Cc: Slingshot Open Source Team, Nathan Chancellor, Nicolas Schier,
	Richard Cochran, Andrew Lunn, David S. Miller, Eric Dumazet,
	Paolo Abeni, Sumit Semwal, Christian König, Guenter Roeck,
	linux-kernel, netdev, linux-kbuild, Sandeep Bhoot, Iraimani P,
	Mamila Santosh

On Fri, 30 Oct 2026 13:58:56 -0700 Doug Ledford wrote:
>  416 files changed, 185137 insertions(+)

🤣️
-- 
pw-bot: cr

^ permalink raw reply	[flat|nested] 25+ messages in thread
end of thread, other threads:[~2026-10-30 22:11 UTC | newest]

Thread overview: 25+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2026-10-30 20:58 [PATCH 00/23] Subject: [PATCH net-next 00/23] net/hpe: add HPE Slingshot NIC drivers Doug Ledford
2026-10-30 20:58 ` [PATCH 01/23] net: hpe: ss1: add the Cassini headers Doug Ledford
2026-10-30 20:58 ` [PATCH 02/23] net: hpe: sbl: add the Slingshot Base Link headers Doug Ledford
2026-10-30 20:58 ` [PATCH 03/23] net: hpe: sbl: add the core instance and configuration layer Doug Ledford
2026-10-30 20:59 ` [PATCH 04/23] net: hpe: sbl: add the SerDes layer Doug Ledford
2026-10-30 20:59 ` [PATCH 05/23] net: hpe: sbl: add the PML link layer Doug Ledford
2026-10-30 20:59 ` [PATCH 06/23] net: hpe: sbl: add link state management Doug Ledford
2026-10-30 20:59 ` [PATCH 07/23] net: hpe: sbl: add the SBM serial bus layer Doug Ledford
2026-10-30 20:59 ` [PATCH 08/23] net: hpe: sbl: add media, FEC and counter support Doug Ledford
2026-10-30 20:59 ` [PATCH 09/23] net: hpe: sl: add the Slingshot Link headers Doug Ledford
2026-10-30 20:59 ` [PATCH 10/23] net: hpe: sl: add the module entry points Doug Ledford
2026-10-30 20:59 ` [PATCH 11/23] net: hpe: sl: add the core link state machines Doug Ledford
2026-10-30 20:59 ` [PATCH 12/23] net: hpe: sl: add the control layer Doug Ledford
2026-10-30 20:59 ` [PATCH 13/23] net: hpe: sl: add media and cable handling Doug Ledford
2026-10-30 20:59 ` [PATCH 14/23] net: hpe: sl: add the sysfs interface Doug Ledford
2026-10-30 20:59 ` [PATCH 15/23] net: hpe: sl: add the NIC binding and logging helpers Doug Ledford
2026-10-30 20:59 ` [PATCH 16/23] net: hpe: ss1: add the Cassini core device layer Doug Ledford
2026-10-30 20:59 ` [PATCH 17/23] net: hpe: ss1: add the datapath and memory translation layers Doug Ledford
2026-10-30 20:59 ` [PATCH 18/23] net: hpe: ss1: add the link layer glue Doug Ledford
2026-10-30 20:59 ` [PATCH 19/23] net: hpe: ss1: add SR-IOV support Doug Ledford
2026-10-30 20:59 ` [PATCH 20/23] net: hpe: ss1: add the CXI core interfaces Doug Ledford
2026-10-30 20:59 ` [PATCH 21/23] net: hpe: ss1: add resource groups, QoS and services Doug Ledford
2026-10-30 20:59 ` [PATCH 22/23] net: hpe: ss1: add the Ethernet personality Doug Ledford
2026-10-30 20:59 ` [PATCH 23/23] net: hpe: wire up the Slingshot NIC drivers Doug Ledford
2026-10-30 22:11 ` [PATCH 00/23] Subject: [PATCH net-next 00/23] net/hpe: add HPE " Jakub Kicinski

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