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From: Rob Clark <robin.clark@oss.qualcomm.com>
To: dri-devel@lists.freedesktop.org
Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org,
	Alexander Koskovich <akoskovich@pm.me>,
	Jie Zhang <jie.zhang@oss.qualcomm.com>,
	Akhil P Oommen <akhilpo@oss.qualcomm.com>,
	Bhaskar Reddy Valluru <bvalluru@qti.qualcomm.com>,
	Rob Clark <robin.clark@oss.qualcomm.com>,
	Sean Paul <sean@poorly.run>,
	Konrad Dybcio <konradybcio@kernel.org>,
	Dmitry Baryshkov <lumag@kernel.org>,
	Abhinav Kumar <abhinav.kumar@linux.dev>,
	Jessica Zhang <jesszhan0024@gmail.com>,
	Marijn Suijten <marijn.suijten@somainline.org>,
	David Airlie <airlied@gmail.com>, Simona Vetter <simona@ffwll.ch>,
	linux-kernel@vger.kernel.org (open list)
Subject: [PATCH v4 09/19] drm/msm: Rename sysprof_setup()
Date: Fri, 30 Oct 2026 14:18:11 -0700	[thread overview]
Message-ID: <20261030211928.45761-10-robin.clark@oss.qualcomm.com> (raw)
In-Reply-To: <20261030211928.45761-1-robin.clark@oss.qualcomm.com>

We'll need this for other non-sysprof related things, so give it a
better name.

It keeps the behavior of implicit force_on when sysprof is active, to
avoid accidentially re-enabling IFPC when sysprof is active.  That isn't
a problem yet (PERFCNTR_CONFIG is not intended to be used with SYSPROF),
but it will be for future users.

Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
---
 drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 17 +++++++++++++----
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c |  6 +++---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.h |  2 +-
 drivers/gpu/drm/msm/msm_gpu.h         |  2 +-
 drivers/gpu/drm/msm/msm_perfcntr.c    |  8 ++++----
 drivers/gpu/drm/msm/msm_submitqueue.c |  4 ++--
 6 files changed, 24 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
index 662f09bec9d5..f3ec78226ed3 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c
@@ -2128,13 +2128,22 @@ static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev,
 	return irq;
 }
 
-void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu, bool force_on)
+/**
+ * a6xx_gmu_ifpc_update - Update IFPC inhibit OOB request
+ * @gpu: the gpu device
+ * @force_on: whether to force GPU on (disable IFPC)
+ *
+ * Update IFPC OOB request, if force_on is true, set an OOB request to
+ * force the GPU on (disable IFPC), if false drop the OOB request.
+ */
+void a6xx_gmu_ifpc_update(struct msm_gpu *gpu, bool force_on)
 {
-	bool sysprof = msm_gpu_sysprof_no_ifpc(gpu) || force_on;
 	struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
 	struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
 	struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
 
+	force_on |= msm_gpu_sysprof_no_ifpc(gpu);
+
 	/* Nothing to do if GPU is suspended. We will handle this during GMU resume */
 	if (!pm_runtime_get_if_active(&gpu->pdev->dev))
 		return;
@@ -2145,9 +2154,9 @@ void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu, bool force_on)
 	 * 'Perfcounter select' register values are lost during IFPC collapse. To avoid that,
 	 * use the currently unused perfcounter oob vote to block IFPC when sysprof is active
 	 */
-	if (sysprof && !test_and_set_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status))
+	if (force_on && !test_and_set_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status))
 		a6xx_gmu_set_oob(gmu, GMU_OOB_PERFCOUNTER_SET);
-	else if (!sysprof && test_and_clear_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status))
+	else if (!force_on && test_and_clear_bit(GMU_STATUS_OOB_PERF_SET, &gmu->status))
 		a6xx_gmu_clear_oob(gmu, GMU_OOB_PERFCOUNTER_SET);
 
 	mutex_unlock(&gmu->lock);
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 09d76cdf059f..70c0024bdef4 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -2851,7 +2851,7 @@ const struct adreno_gpu_funcs a6xx_gpu_funcs = {
 		.create_private_vm = a6xx_create_private_vm,
 		.get_rptr = a6xx_get_rptr,
 		.progress = a6xx_progress,
-		.sysprof_setup = a6xx_gmu_sysprof_setup,
+		.ifpc_update = a6xx_gmu_ifpc_update,
 		.perfcntr_configure = a6xx_perfcntr_configure,
 	},
 	.init = a6xx_gpu_init,
@@ -2922,7 +2922,7 @@ const struct adreno_gpu_funcs a7xx_gpu_funcs = {
 		.create_private_vm = a6xx_create_private_vm,
 		.get_rptr = a6xx_get_rptr,
 		.progress = a6xx_progress,
-		.sysprof_setup = a6xx_gmu_sysprof_setup,
+		.ifpc_update = a6xx_gmu_ifpc_update,
 		.perfcntr_configure = a6xx_perfcntr_configure,
 	},
 	.init = a6xx_gpu_init,
@@ -2953,7 +2953,7 @@ const struct adreno_gpu_funcs a8xx_gpu_funcs = {
 		.create_private_vm = a6xx_create_private_vm,
 		.get_rptr = a6xx_get_rptr,
 		.progress = a8xx_progress,
-		.sysprof_setup = a6xx_gmu_sysprof_setup,
+		.ifpc_update = a6xx_gmu_ifpc_update,
 		.perfcntr_configure = a6xx_perfcntr_configure,
 		.perfcntr_flush = a8xx_perfcntr_flush,
 	},
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
index c49301be504b..639e63c29f4b 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h
@@ -298,7 +298,7 @@ void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
 int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node);
 int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node);
 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu);
-void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu, bool force_on);
+void a6xx_gmu_ifpc_update(struct msm_gpu *gpu, bool force_on);
 
 void a6xx_preempt_init(struct msm_gpu *gpu);
 void a6xx_preempt_hw_init(struct msm_gpu *gpu);
diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
index d27d54bdb7a7..2e1b1bea37ce 100644
--- a/drivers/gpu/drm/msm/msm_gpu.h
+++ b/drivers/gpu/drm/msm/msm_gpu.h
@@ -93,7 +93,7 @@ struct msm_gpu_funcs {
 	 * for cmdstream that is buffered in this FIFO upstream of the CP fw.
 	 */
 	bool (*progress)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
-	void (*sysprof_setup)(struct msm_gpu *gpu, bool force_on);
+	void (*ifpc_update)(struct msm_gpu *gpu, bool force_on);
 
 	/* Configure perfcntr SELect regs: */
 	void (*perfcntr_configure)(struct msm_gpu *gpu, struct msm_ringbuffer *ring,
diff --git a/drivers/gpu/drm/msm/msm_perfcntr.c b/drivers/gpu/drm/msm/msm_perfcntr.c
index ce65b1160955..7b4a6e49d3a7 100644
--- a/drivers/gpu/drm/msm/msm_perfcntr.c
+++ b/drivers/gpu/drm/msm/msm_perfcntr.c
@@ -259,8 +259,8 @@ sample_worker(struct kthread_work *work)
 	}
 
 	/* Inhibit IFPC while accessing registers: */
-	if (gpu->funcs->sysprof_setup)
-		gpu->funcs->sysprof_setup(gpu, true);
+	if (gpu->funcs->ifpc_update)
+		gpu->funcs->ifpc_update(gpu, true);
 
 	if (gpu->funcs->perfcntr_flush)
 		gpu->funcs->perfcntr_flush(gpu);
@@ -297,8 +297,8 @@ sample_worker(struct kthread_work *work)
 	}
 
 	/* Re-enable IFPC: */
-	if (gpu->funcs->sysprof_setup)
-		gpu->funcs->sysprof_setup(gpu, false);
+	if (gpu->funcs->ifpc_update)
+		gpu->funcs->ifpc_update(gpu, false);
 
 	smp_store_release(&stream->fifo.head, head);
 	wake_up_all(&stream->poll_wq);
diff --git a/drivers/gpu/drm/msm/msm_submitqueue.c b/drivers/gpu/drm/msm/msm_submitqueue.c
index d307cdd17d90..43103b054ee7 100644
--- a/drivers/gpu/drm/msm/msm_submitqueue.c
+++ b/drivers/gpu/drm/msm/msm_submitqueue.c
@@ -43,8 +43,8 @@ int msm_context_set_sysprof(struct msm_context *ctx, struct msm_gpu *gpu, int sy
 	}
 
 	/* Some gpu families require additional setup for sysprof */
-	if (gpu->funcs->sysprof_setup)
-		gpu->funcs->sysprof_setup(gpu, false);
+	if (gpu->funcs->ifpc_update)
+		gpu->funcs->ifpc_update(gpu, false);
 
 	ctx->sysprof = sysprof;
 
-- 
2.56.0


  parent reply	other threads:[~2026-10-30 21:19 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-30 21:18 [PATCH v4 00/19] drm/msm/a8xx: GPU state capture support Rob Clark
2026-10-30 21:18 ` [PATCH v4 01/19] drm/msm: Import adreno_snapshot.h Rob Clark
2026-10-30 21:18 ` [PATCH v4 02/19] drm/msm/a8xx: Export aperture helpers Rob Clark
2026-10-30 21:18 ` [PATCH v4 03/19] drm/msm/a8xx: Add a8xx_aperture_acquire_raw() Rob Clark
2026-10-30 21:18 ` [PATCH v4 04/19] drm/msm/a8xx: Export slice helper Rob Clark
2026-10-30 21:18 ` [PATCH v4 05/19] drm/msm/a8xx: Add missing a850 ifpc reglist entries Rob Clark
2026-10-30 21:18 ` [PATCH v4 06/19] drm/msm/a8xx: Allow nonctx reglist to include GMU regs Rob Clark
2026-10-30 21:18 ` [PATCH v4 07/19] drm/msm/a8xx: Stop getting GMEM_PROTECT from nonctx list Rob Clark
2026-10-30 21:18 ` [PATCH v4 08/19] drm/msm/adreno: Fix PROTECT span length Rob Clark
2026-10-30 21:18 ` Rob Clark [this message]
2026-10-30 21:18 ` [PATCH v4 10/19] drm/msm: Add cleanup help for disabling IFPC Rob Clark
2026-10-30 21:18 ` [PATCH v4 11/19] drm/msm/debugfs: Use cleanup.h for gpu state dump Rob Clark
2026-10-30 21:18 ` [PATCH v4 12/19] drm/msm: Inhibit IFPC for state snapshot Rob Clark
2026-10-30 21:18 ` [PATCH v4 13/19] drm/msm/adreno: add temporary __maybe_unused Rob Clark
2026-10-30 21:18 ` [PATCH v4 14/19] drm/msm/a8xx: Import generated headers Rob Clark
2026-10-30 21:18 ` [PATCH v4 15/19] drm/msm/a8xx: devcoredump state capture support Rob Clark
2026-10-30 21:18 ` [PATCH v4 16/19] drm/msm/a8xx: Add all CP_PROTECT_PIPE to pwrup reglist Rob Clark
2026-10-30 21:18 ` [PATCH v4 17/19] drm/msm/a8xx: Use CP_PROTECT_PIPE regs Rob Clark
2026-10-30 21:18 ` [PATCH v4 18/19] drm/msm/a8xx: Switch to generated protect regs Rob Clark
2026-10-30 21:18 ` [PATCH v4 19/19] drm/msm/adreno: Remove temporary __maybe_unused Rob Clark

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