mirror of https://lore.kernel.org/lkml/
 help / color / mirror / Atom feed
* [PATCH v2] irqchip/qcom-pdc: Handle ESPIs in qcom,pdc-ranges
@ 2026-11-02 15:45 Konrad Dybcio
  0 siblings, 0 replies; only message in thread
From: Konrad Dybcio @ 2026-11-02 15:45 UTC (permalink / raw)
  To: Thomas Gleixner, Radu Rendec, Stephen Boyd, Marc Zyngier, Lina Iyer
  Cc: linux-arm-msm, linux-kernel, Abel Vesa, Konrad Dybcio

From: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

The qcom,pdc-ranges property maps GIC interrupts to PDC output pins.
That data is then subsequently used by irq_domain to resolve into the
interrupt parent (which again, is always GIC).

The code that handles this hardcodes parent_fwspec.param[0] = 0
(GIC_SPI). Make that conditional to prevent this warning at boot:

GICv3: SPI 4115 out of range (use ESPI?)

Fixes: 81ef8bf88065 ("irqchip/qcom-pdc: Add irqdomain for wakeup capable GPIOs")
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
---
Changes in v2:
- Drop the arm-specific header, replace with an 4096 literal
- Link to v1: https://patch.msgid.link/20261022-topic-pdc_map_espi-v1-1-7c481a42bac5@oss.qualcomm.com

To: Thomas Gleixner <tglx@kernel.org>
To: Radu Rendec <radu@rendec.net>
To: Stephen Boyd <swboyd@chromium.org>
To: Lina Iyer <ilina@codeaurora.org>
To: Marc Zyngier <maz@kernel.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
---
 drivers/irqchip/qcom-pdc.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c
index 29025a212ece..6c2a2d13629c 100644
--- a/drivers/irqchip/qcom-pdc.c
+++ b/drivers/irqchip/qcom-pdc.c
@@ -21,6 +21,7 @@
 #include <linux/slab.h>
 #include <linux/types.h>
 #include <linux/firmware/qcom/qcom_scm.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
 
 #define PDC_MAX_IRQS			256
 #define IRQ_ENABLE_BANK_MAX		BITS_TO_BYTES(PDC_MAX_IRQS)
@@ -597,8 +598,14 @@ static int qcom_pdc_alloc(struct irq_domain *domain, unsigned int virq,
 
 	parent_fwspec.fwnode      = domain->parent->fwnode;
 	parent_fwspec.param_count = 3;
-	parent_fwspec.param[0]    = 0;
-	parent_fwspec.param[1]    = pin_to_hwirq(region, hwirq);
+	/* GIC ESPIs start at 4096 */
+	if (pin_to_hwirq(region, hwirq) >= 4096) {
+		parent_fwspec.param[0] = GIC_ESPI;
+		parent_fwspec.param[1] = pin_to_hwirq(region, hwirq) - 4096;
+	} else {
+		parent_fwspec.param[0] = GIC_SPI;
+		parent_fwspec.param[1] = pin_to_hwirq(region, hwirq);
+	}
 	parent_fwspec.param[2]    = type;
 
 	return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &parent_fwspec);

---
base-commit: 2efb7a11f1aa4d2dc285fe2680cca22cb9f72f64
change-id: 20261022-topic-pdc_map_espi-43d4300dd856

Best regards,
--  
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>


^ permalink raw reply	[flat|nested] only message in thread

only message in thread, other threads:[~2026-11-02 15:45 UTC | newest]

Thread overview: (only message) (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2026-11-02 15:45 [PATCH v2] irqchip/qcom-pdc: Handle ESPIs in qcom,pdc-ranges Konrad Dybcio

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox

all inboxes | Powered by JetHome®