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From: Jenhao Chen <jenhaochen@google.com>
To: Nick Terrell <terrelln@fb.com>, David Sterba <dsterba@suse.com>
Cc: linux-kernel@vger.kernel.org, Minchan Kim <minchan@kernel.org>,
	 Martin Liu <liumartin@google.com>, Ben Wei <benwei@google.com>,
	 Jenhao Chen <jenhaochen@google.com>
Subject: [PATCH v2] zstd: Use shift mask in BIT_getMiddleBits() on arm64
Date: Mon,  2 Nov 2026 02:34:12 +0000	[thread overview]
Message-ID: <20261102023412.701888-1-jenhaochen@google.com> (raw)
In-Reply-To: <20261030121633.258612-1-jenhaochen@google.com>

In ZSTD_decodeSequence(), ZSTD_updateFseStateWithDInfo() calls
BIT_readBits() -> BIT_lookBits() -> BIT_getMiddleBits() three times per
decoded sequence (for literal length, match length, and offset FSE
states). However, BIT_getMiddleBits() only enables the branchless
register shift-and-mask path on x86_64, falling back to a BIT_mask[]
lookup table load on arm64.

Enable the shift-and-mask path in BIT_getMiddleBits() on __aarch64__ so
the mask is computed directly in registers instead of loading from
BIT_mask[]. On arm64 at -O2, this eliminates three table loads per
decoded sequence, shrinks zstd decompression .text by 212 bytes, and
improves decompression throughput by 1-3%.

Signed-off-by: Jenhao Chen <jenhaochen@google.com>
---
Changes in v2:
- Drop the Makefile -O3 change, which triggered an undefined
  __divsi3_table reference in zstd_compress.ko on nios2-linux-gcc
  (reported by kernel test robot <lkp@intel.com>) and previously caused
  stack frame size warnings on parisc (commit 7416cdc9b9c1).
- Update the commit message with isolated -O2 numbers for the
  BIT_getMiddleBits() shift-mask change alone.
- Link to v1: https://lore.kernel.org/r/20261030121633.258612-1-jenhaochen@google.com/

 lib/zstd/common/bitstream.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/lib/zstd/common/bitstream.h b/lib/zstd/common/bitstream.h
index 86439da0eea76..01e69ab7053b4 100644
--- a/lib/zstd/common/bitstream.h
+++ b/lib/zstd/common/bitstream.h
@@ -299,7 +299,7 @@ FORCE_INLINE_TEMPLATE BitContainerType BIT_getMiddleBits(BitContainerType bitCon
      * such cpus old (pre-Haswell, 2013) and their performance is not of that
      * importance.
      */
-#if defined(__x86_64__) || defined(_M_X64)
+#if defined(__x86_64__) || defined(_M_X64) || defined(__aarch64__)
     return (bitContainer >> (start & regMask)) & ((((U64)1) << nbBits) - 1);
 #else
     return (bitContainer >> (start & regMask)) & BIT_mask[nbBits];
-- 
2.56.0.317.g454f8302e1-goog

      parent reply	other threads:[~2026-11-02  2:34 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-30 12:16 [PATCH] zstd: Build with -O3 and use shift mask " Jenhao Chen
2026-11-01  5:05 ` kernel test robot
2026-11-02  2:34 ` Jenhao Chen [this message]

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