[PATCH v3 00/10] PCI: tegra194: Fix EP and Root Port corner cases

[Manikanta Maddireddy <mmaddireddy@nvidia.com>]

This series fixes a set of independent Tegra194/Tegra234 PCIe controller
issues found while testing Root Port and Endpoint flows.

The Root Port fixes tighten probe/remove and suspend/resume error handling:
propagate optional GPIO failures, check reset deassertion, avoid skipping
cleanup when no link came up, and enable the optional core monitor clock
only after link setup and final core clock rate selection.

The Endpoint fixes cover PERST# IRQ suspend handling, PHY/PLL error
unwinds, capability checks before programming optional PCIe extended
capabilities, hiding Tegra234 EP L1.2 advertisement for the documented
hardware limitation, and rejecting invalid MSI interrupt number zero.

The patches are ordered from low-level error handling toward Endpoint
capability checks and MSI validation. MSI-X enablement, MSI-X doorbell
changes and fixed MSI-X table handling are deferred; MSI-X remains
disabled in the Tegra EPC features.

Changes in v3:
- Rebase onto the current PCI main-based stack after the DWC register-field
  cleanup series. Patches 1-8 and 10 have no code changes from v2.
- Rework patch 9 and rename it to "Enable core monitor clock after link
  setup". Set the core clock rate to 500 MHz before enabling it, program
  the controller, train the link, select the negotiated-speed core rate,
  and then enable the monitor clock.
- Propagate initial and negotiated core rate-setting errors and monitor
  enable failures. Keep monitor operations out of the host initialization
  callback and DLF retry path, and release the monitor during remove,
  suspend and shutdown without a separate reference-state flag.
- Expand patch 9's explanation of the Boot and Power Management Processor
  (BPMP) firmware voltage requirement and false frequency-monitor faults
  during rate transitions.
- Retain Frank Li's Reviewed-by tags from v2 on unchanged patches 1-8
  and 10.

Changes in v2:
- Expand the PERST# suspend-race explanation to describe how an IRQ thread
  can enable the endpoint after the original state check. Explain how
  disable_irq() drains that thread and preserves the existing suspend
  policy, and add a synchronization comment.
- Split the MSI-only zero check out of the former MSI/MSI-X patch, with a
  focused title and commit message. Treat it as defensive validation and
  omit the Fixes tag from that patch.
- Drop all MSI-X changes and the fixed MSI-X table patch (v1 patch 11),
  reducing the series from eleven patches to ten.
- Adapt register names to the preceding DWC register-field cleanup series.

Validation reported with v2:
- ARM64 compilation of the Tegra driver passed.
- Checkpatch and whitespace checks passed.
- Tegra PCIe EP link up with pci-epf-test driver.
- pci_endpoint_test
  - pci_ep_bar.BAR0.BAR_TEST
  - pci_ep_basic.CONSECUTIVE_BAR_TEST
  - pci_ep_basic.LEGACY_IRQ_TEST
  - pci_ep_basic.MSI_TEST
  - pci_ep_data_transfer.memcpy.READ_TEST
  - pci_ep_data_transfer.memcpy.WRITE_TEST
  - pci_ep_data_transfer.memcpy.COPY_TEST

v2: https://lore.kernel.org/linux-pci/20261021061349.1265704-1-mmaddireddy@nvidia.com/

v1: https://lore.kernel.org/linux-pci/20260923072237.1139013-1-mmaddireddy@nvidia.com/

Manikanta Maddireddy (10):
  PCI: tegra194: Propagate REFCLK select GPIO errors
  PCI: tegra194: Check core reset deassertion
  PCI: tegra194: Fix Endpoint PERST# IRQ suspend race
  PCI: tegra194: Do not skip no-link Root Port remove cleanup
  PCI: tegra194: Check for 16 GT/s capability before programming
  PCI: tegra194: Check for L1SS capability before programming
  PCI: tegra194: Always disable Tegra234 Endpoint L1.2
  PCI: tegra194: Guard Endpoint PLL-off error path
  PCI: tegra194: Enable core monitor clock after link setup
  PCI: tegra194: Reject zero MSI interrupt number

 drivers/pci/controller/dwc/pcie-tegra194.c | 239 +++++++++++++--------
 1 file changed, 151 insertions(+), 88 deletions(-)


base-commit: d447e8cfe376cc0cc4db8266d01356d0b3ebb695
-- 
2.34.1