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From: Alexandre Courbot <acourbot@nvidia.com>
To: Danilo Krummrich <dakr@kernel.org>,
	Alice Ryhl <aliceryhl@google.com>,
	 David Airlie <airlied@gmail.com>,
	Simona Vetter <simona@ffwll.ch>
Cc: John Hubbard <jhubbard@nvidia.com>,
	 Alistair Popple <apopple@nvidia.com>,
	Timur Tabi <ttabi@nvidia.com>,
	 Eliot Courtney <ecourtney@nvidia.com>,
	Zhi Wang <zhiw@nvidia.com>,
	 nova-gpu@lists.linux.dev, rust-for-linux@vger.kernel.org,
	 linux-kernel@vger.kernel.org,
	Alexandre Courbot <acourbot@nvidia.com>
Subject: [PATCH 6/7] gpu: nova-core: falcon: allow DMA transfers to read from a framebuffer address
Date: Tue, 03 Nov 2026 19:22:44 +0900	[thread overview]
Message-ID: <20261103-r000-fw-v1-6-e3d38fc130e3@nvidia.com> (raw)
In-Reply-To: <20261103-r000-fw-v1-0-e3d38fc130e3@nvidia.com>

The r000 boot protocol has a load-and-execute event in which GSP-RM asks
the driver to load a Heavy-Secured binary from framebuffer memory into
the GSP falcon's memory by DMA in order to run it.

Nova-core's falcon DMA loading method currently only supports loading
from a DMA object that the driver had allocated, so there is no way to
copy an image from framebuffer memory that an event supplied.

Address this by making the source of a falcon DMA transfer an enum,
which can be either a DMA object, or a GPU framebuffer address.

The framebuffer address source has no user yet, but will be used by the
r000 boot protocol.

Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
---
 drivers/gpu/nova-core/falcon.rs | 65 +++++++++++++++++++++++++++++------------
 1 file changed, 46 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon.rs
index f48f2eabab0f..fb43d0ed2821 100644
--- a/drivers/gpu/nova-core/falcon.rs
+++ b/drivers/gpu/nova-core/falcon.rs
@@ -136,6 +136,15 @@ pub(crate) enum FalconMem {
     Dmem { tag: bool },
 }
 
+/// Where a falcon DMA transfer reads from.
+pub(crate) enum FalconDmaSource<'a> {
+    /// A DMA object in system memory.
+    Sysmem(&'a Coherent<'a, [u8]>),
+    /// GPU framebuffer memory at physical address `base`.
+    #[expect(dead_code)]
+    Framebuffer { base: u64 },
+}
+
 bounded_enum! {
     /// Defines the Framebuffer Interface (FBIF) aperture type.
     /// This determines the memory type for external memory access during a DMA transfer, which is
@@ -510,13 +519,11 @@ pub(crate) fn pio_load<F: FalconFirmware<Target = E> + FalconPioLoadable>(
         Ok(())
     }
 
-    /// Perform a DMA write according to `load_offsets` from `dma_obj` into the falcon's
+    /// Perform a DMA write according to `load_offsets` from `src` into the falcon's
     /// `target_mem`.
-    ///
-    /// `sec` is set if the loaded firmware is expected to run in secure mode.
     fn dma_wr(
         &self,
-        dma_obj: &Coherent<'_, [u8]>,
+        src: FalconDmaSource<'_>,
         target_mem: FalconMem,
         load_offsets: FalconDmaLoadTarget,
     ) -> Result {
@@ -529,21 +536,37 @@ fn dma_wr(
         // For IMEM, we want to use the start offset as a virtual address tag for each page, since
         // code addresses in the firmware (and the boot vector) are virtual.
         //
-        // For DMEM, the start offset is folded into the DMA address.
-        let (src_start, dma_start, tag_dmem) = match target_mem {
-            FalconMem::ImemSecure | FalconMem::ImemNonSecure => (load_offsets.src_start, 0, false),
-            FalconMem::Dmem { tag } => (0, usize::from_safe_cast(load_offsets.src_start), tag),
-        };
+        // For DMEM in a DMA object, the start offset is folded into the DMA address. For DMEM at a
+        // framebuffer address, the DMA engine adds it to the address.
+        let (src_start, dma_address, tag_dmem) = match src {
+            FalconDmaSource::Sysmem(dma_obj) => {
+                let (src_start, dma_start, tag_dmem) = match target_mem {
+                    FalconMem::ImemSecure | FalconMem::ImemNonSecure => {
+                        (load_offsets.src_start, 0, false)
+                    }
+                    FalconMem::Dmem { tag } => {
+                        (0, usize::from_safe_cast(load_offsets.src_start), tag)
+                    }
+                };
 
-        let dma_address = {
-            // Upper limit of transfer is `(num_transfers * DMA_LEN) + load_offsets.src_start`.
-            let dma_end = num_transfers
-                .checked_mul(DMA_LEN)
-                .and_then(|size| size.checked_add(load_offsets.src_start))
-                .map(usize::from_safe_cast)
-                .ok_or(EOVERFLOW)?;
+                // Upper limit of transfer is `(num_transfers * DMA_LEN) + load_offsets.src_start`.
+                let dma_end = num_transfers
+                    .checked_mul(DMA_LEN)
+                    .and_then(|size| size.checked_add(load_offsets.src_start))
+                    .map(usize::from_safe_cast)
+                    .ok_or(EOVERFLOW)?;
 
-            io_project!(dma_obj, [try: dma_start..dma_end]).dma_address()
+                (
+                    src_start,
+                    io_project!(dma_obj, [try: dma_start..dma_end]).dma_address(),
+                    tag_dmem,
+                )
+            }
+            FalconDmaSource::Framebuffer { base } => (
+                load_offsets.src_start,
+                base,
+                matches!(target_mem, FalconMem::Dmem { tag: true }),
+            ),
         };
 
         if dma_address % DmaAddress::from(DMA_LEN) > 0 {
@@ -626,9 +649,13 @@ fn dma_load<F: FalconFirmware<Target = E> + FalconDmaLoadable>(&self, fw: &F) ->
                     .with_mem_type(FalconFbifMemType::Physical)
             });
 
-        self.dma_wr(&dma_obj, FalconMem::ImemSecure, fw.imem_sec_load_params())?;
         self.dma_wr(
-            &dma_obj,
+            FalconDmaSource::Sysmem(&dma_obj),
+            FalconMem::ImemSecure,
+            fw.imem_sec_load_params(),
+        )?;
+        self.dma_wr(
+            FalconDmaSource::Sysmem(&dma_obj),
             FalconMem::Dmem { tag: false },
             fw.dmem_load_params(),
         )?;

-- 
2.56.0


  parent reply	other threads:[~2026-11-03 10:23 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-03 10:22 [PATCH 0/7] gpu: nova-core: generic bootloader and falcon DMA changes for r000 Alexandre Courbot
2026-11-03 10:22 ` [PATCH 1/7] gpu: nova-core: separate the generic falcon bootloader from FWSEC Alexandre Courbot
2026-11-03 10:22 ` [PATCH 2/7] gpu: nova-core: place the generic bootloader at the top of IMEM Alexandre Courbot
2026-11-03 10:22 ` [PATCH 3/7] gpu: nova-core: move the bootloader DMEM descriptor out of FWSEC Alexandre Courbot
2026-11-03 10:22 ` [PATCH 4/7] gpu: nova-core: run the generic bootloader from its own type Alexandre Courbot
2026-11-03 10:22 ` [PATCH 5/7] gpu: nova-core: falcon: allow DMEM DMA transfers to request tagging Alexandre Courbot
2026-11-03 10:22 ` Alexandre Courbot [this message]
2026-11-03 10:22 ` [PATCH 7/7] gpu: nova-core: falcon: check the per-block DMA offsets for overflow Alexandre Courbot

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