From: Shawn Guo <shengchao.guo@oss.qualcomm.com>
To: Bjorn Andersson <andersson@kernel.org>
Cc: Konrad Dybcio <konradybcio@kernel.org>,
Abel Vesa <abelvesa@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Bartosz Golaszewski <brgl@kernel.org>,
Dhruvin Rajpura <dhruvin.rajpura@oss.qualcomm.com>,
devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-kernel@vger.kernel.org,
Shawn Guo <shengchao.guo@oss.qualcomm.com>
Subject: [PATCH RFC v2 1/2] arm64: dts: qcom: nord-ride-embedded: Add PMIC ADC thermistor channels
Date: Tue, 3 Nov 2026 21:54:44 +0800 [thread overview]
Message-ID: <20261103135445.2049110-2-shengchao.guo@oss.qualcomm.com> (raw)
In-Reply-To: <20261103135445.2049110-1-shengchao.guo@oss.qualcomm.com>
From: Dhruvin Rajpura <dhruvin.rajpura@oss.qualcomm.com>
The PMAU0102 (Kai_MV) ADC5 Gen3 controllers only expose the
REF_GND/1P25VREF/DIE_TEMP calibration channels, so no board thermistor
feeds the thermal framework.
On Nord Ride, three Kai AMUX pins are wired to thermistors: Kai
instance E's AMUX1 (SDRAM3 THERM) and Kai instance I's AMUX1/AMUX2
(SDRAM1 THERM, UFS THERM). The remaining Kai AMUX pins monitor voltage
rails.
Mark all Kai ADCs as thermal sensor providers in the PMIC dtsi, as it
is a PMIC capability, and describe the thermistor channels with
qcom,adc-tm and their thermal zones in the board DT, since the wiring
is board specific.
Signed-off-by: Dhruvin Rajpura <dhruvin.rajpura@oss.qualcomm.com>
Signed-off-by: Shawn Guo <shengchao.guo@oss.qualcomm.com>
---
.../boot/dts/qcom/nord-ride-embedded.dts | 84 +++++++++++++++++++
arch/arm64/boot/dts/qcom/pmau0102-nord.dtsi | 8 ++
2 files changed, 92 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/nord-ride-embedded.dts b/arch/arm64/boot/dts/qcom/nord-ride-embedded.dts
index 49635695f832..550cd7fe0ac1 100644
--- a/arch/arm64/boot/dts/qcom/nord-ride-embedded.dts
+++ b/arch/arm64/boot/dts/qcom/nord-ride-embedded.dts
@@ -53,6 +53,62 @@ bi_tcxo_ao_div2: bi-tcxo-ao-div2-clk {
clock-div = <2>;
};
};
+
+ thermal-zones {
+ sdram3_thermal: sdram3-thermal {
+ thermal-sensors = <&pmau0102_e_adc ADC5_GEN3_AMUX1_THM_100K_PU(4)>;
+
+ trips {
+ trip0 {
+ temperature = <70000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ trip1 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+
+ sdram1_thermal: sdram1-thermal {
+ thermal-sensors = <&pmau0102_i_adc ADC5_GEN3_AMUX1_THM_100K_PU(8)>;
+
+ trips {
+ trip0 {
+ temperature = <70000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ trip1 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+
+ ufs_thermal: ufs-thermal {
+ thermal-sensors = <&pmau0102_i_adc ADC5_GEN3_AMUX2_THM_100K_PU(8)>;
+
+ trips {
+ trip0 {
+ temperature = <70000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+
+ trip1 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "hot";
+ };
+ };
+ };
+ };
};
&apps_rsc {
@@ -366,6 +422,34 @@ vreg_l3l_1p8: ldo3 {
};
};
+&pmau0102_e_adc {
+ channel@444 {
+ reg = <ADC5_GEN3_AMUX1_THM_100K_PU(4)>;
+ label = "pmau0102_e_sdram3_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,adc-tm;
+ };
+};
+
+&pmau0102_i_adc {
+ channel@844 {
+ reg = <ADC5_GEN3_AMUX1_THM_100K_PU(8)>;
+ label = "pmau0102_i_sdram1_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,adc-tm;
+ };
+
+ channel@845 {
+ reg = <ADC5_GEN3_AMUX2_THM_100K_PU(8)>;
+ label = "pmau0102_i_ufs_therm";
+ qcom,ratiometric;
+ qcom,hw-settle-time = <200>;
+ qcom,adc-tm;
+ };
+};
+
&qupv3_0 {
firmware-name = "qcom/nord/qupv3fw.elf";
diff --git a/arch/arm64/boot/dts/qcom/pmau0102-nord.dtsi b/arch/arm64/boot/dts/qcom/pmau0102-nord.dtsi
index 47ea145f4abb..26c4d126a23b 100644
--- a/arch/arm64/boot/dts/qcom/pmau0102-nord.dtsi
+++ b/arch/arm64/boot/dts/qcom/pmau0102-nord.dtsi
@@ -31,6 +31,7 @@ pmau0102_e_adc: adc@7200 {
#size-cells = <0>;
interrupts-extended = <&spmi_bus 0x4 0x72 0x1 IRQ_TYPE_EDGE_RISING>;
#io-channel-cells = <1>;
+ #thermal-sensor-cells = <1>;
channel@400 {
reg = <ADC5_GEN3_REF_GND(4)>;
@@ -84,6 +85,7 @@ pmau0102_f_adc: adc@7200 {
#size-cells = <0>;
interrupts-extended = <&spmi_bus 0x5 0x72 0x1 IRQ_TYPE_EDGE_RISING>;
#io-channel-cells = <1>;
+ #thermal-sensor-cells = <1>;
channel@500 {
reg = <ADC5_GEN3_REF_GND(5)>;
@@ -137,6 +139,7 @@ pmau0102_g_adc: adc@7200 {
#size-cells = <0>;
interrupts-extended = <&spmi_bus 0x6 0x72 0x1 IRQ_TYPE_EDGE_RISING>;
#io-channel-cells = <1>;
+ #thermal-sensor-cells = <1>;
channel@600 {
reg = <ADC5_GEN3_REF_GND(6)>;
@@ -190,6 +193,7 @@ pmau0102_h_adc: adc@7200 {
#size-cells = <0>;
interrupts-extended = <&spmi_bus 0x7 0x72 0x1 IRQ_TYPE_EDGE_RISING>;
#io-channel-cells = <1>;
+ #thermal-sensor-cells = <1>;
channel@700 {
reg = <ADC5_GEN3_REF_GND(7)>;
@@ -243,6 +247,7 @@ pmau0102_i_adc: adc@7200 {
#size-cells = <0>;
interrupts-extended = <&spmi_bus 0x8 0x72 0x1 IRQ_TYPE_EDGE_RISING>;
#io-channel-cells = <1>;
+ #thermal-sensor-cells = <1>;
channel@800 {
reg = <ADC5_GEN3_REF_GND(8)>;
@@ -296,6 +301,7 @@ pmau0102_j_adc: adc@7200 {
#size-cells = <0>;
interrupts-extended = <&spmi_bus 0x9 0x72 0x1 IRQ_TYPE_EDGE_RISING>;
#io-channel-cells = <1>;
+ #thermal-sensor-cells = <1>;
channel@900 {
reg = <ADC5_GEN3_REF_GND(9)>;
@@ -349,6 +355,7 @@ pmau0102_k_adc: adc@7200 {
#size-cells = <0>;
interrupts-extended = <&spmi_bus 0xa 0x72 0x1 IRQ_TYPE_EDGE_RISING>;
#io-channel-cells = <1>;
+ #thermal-sensor-cells = <1>;
channel@a00 {
reg = <ADC5_GEN3_REF_GND(0xa)>;
@@ -402,6 +409,7 @@ pmau0102_l_adc: adc@7200 {
#size-cells = <0>;
interrupts-extended = <&spmi_bus 0xb 0x72 0x1 IRQ_TYPE_EDGE_RISING>;
#io-channel-cells = <1>;
+ #thermal-sensor-cells = <1>;
channel@b00 {
reg = <ADC5_GEN3_REF_GND(0xb)>;
--
2.43.0
next prev parent reply other threads:[~2026-11-03 13:55 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-03 13:54 [PATCH RFC v2 0/2] arm64: dts: qcom: nord: Add ADC-TM " Shawn Guo
2026-11-03 13:54 ` Shawn Guo [this message]
2026-11-03 13:54 ` [PATCH RFC v2 2/2] arm64: dts: qcom: nord-rrd: Add PMIC ADC " Shawn Guo
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