From: Lee Jones <lee@kernel.org>
To: lee@kernel.org, "James Tai" <james.tai@realtek.com>,
"Yu-Chun Lin" <eleanor.lin@realtek.com>,
"Andreas Färber" <afaerber@suse.com>,
"Linus Walleij" <linusw@kernel.org>,
"Tzuyi Chang" <tychang@realtek.com>,
linux-arm-kernel@lists.infradead.org,
linux-realtek-soc@lists.infradead.org,
linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: stable@vger.kernel.org
Subject: [PATCH 06/10] pinctrl: realtek: Fix bit shift when configuring RTD_HIGH_VIL
Date: Tue, 3 Nov 2026 21:29:11 +0000 [thread overview]
Message-ID: <20261103213002.1673560-7-lee@kernel.org> (raw)
In-Reply-To: <20261103213002.1673560-1-lee@kernel.org>
In rtd_pconf_parse_conf(), the RTD_HIGH_VIL case prepares mask as
BIT(hvil_off) for regmap_update_bits(), but sets val = 1 without
shifting it to hvil_off. Whenever hvil_off is non-zero,
regmap_update_bits() masks val with BIT(hvil_off) and clears the high
VIL bit instead of setting it.
Set val to BIT(hvil_off) so that the target bit is set as intended.
Fixes: dcc9334435b0 ("pinctrl: realtek: add support for slew rate, input voltage and high VIL")
Closes: https://sashiko.dev/#/bug/linux-e7077311-3f30-4b77-844b-1447519d0c84
Cc: stable@vger.kernel.org
Signed-off-by: Lee Jones <lee@kernel.org>
---
drivers/pinctrl/realtek/pinctrl-rtd.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pinctrl/realtek/pinctrl-rtd.c b/drivers/pinctrl/realtek/pinctrl-rtd.c
index 2b877099ec85..72773600303b 100644
--- a/drivers/pinctrl/realtek/pinctrl-rtd.c
+++ b/drivers/pinctrl/realtek/pinctrl-rtd.c
@@ -473,7 +473,7 @@ static int rtd_pconf_parse_conf(struct rtd_pinctrl *data,
hvil_off = config_desc->base_bit + config_desc->hvil_offset;
reg_off = config_desc->reg_offset;
mask = BIT(hvil_off);
- val = 1;
+ val = BIT(hvil_off);
break;
case RTD_DRIVE_STRENGTH_P:
--
2.56.0.385.gac671c819a-goog
next prev parent reply other threads:[~2026-11-03 21:30 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-03 21:29 [PATCH 00/10] pinctrl: Fix out-of-bounds accesses, divide-by-zero, and error handling Lee Jones
2026-11-03 21:29 ` [PATCH 01/10] pinctrl: sunxi: Fix out-of-bounds irq_bank index when first bank has no IRQs Lee Jones
2026-11-03 21:29 ` [PATCH 02/10] pinctrl: tegra186: Fix out-of-bounds register bank index for AON drive groups Lee Jones
2026-11-03 21:29 ` [PATCH 03/10] pinctrl: ingenic: Fix element type of x1600_sfc_funcs array Lee Jones
2026-11-03 22:00 ` H. Nikolaus Schaller
2026-11-03 21:29 ` [PATCH 04/10] pinctrl: mediatek: mt7981: Add missing entries to mt7981_ant_sel_funcs Lee Jones
2026-11-03 21:29 ` [PATCH 05/10] pinctrl: realtek: Prevent out-of-bounds access in rtd_pinctrl_find_config() Lee Jones
2026-11-03 21:29 ` Lee Jones [this message]
2026-11-03 21:29 ` [PATCH 07/10] pinctrl: realtek: Initialise omitted offset fields to NA in config macros Lee Jones
2026-11-03 21:29 ` [PATCH 08/10] pinctrl: mediatek: Clean up partially initialised hw->eint on error Lee Jones
2026-11-03 21:29 ` [PATCH 09/10] pinctrl: mediatek: Prevent divide-by-zero for pins with fixed drive strength Lee Jones
2026-11-03 21:29 ` [PATCH 10/10] pinctrl: qcom: Check qcom_scm_io_readl() return value in msm_gpio_irq_set_type() Lee Jones
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