* [PATCH v2 1/2] media: rppx1: Move register definitions to header
@ 2026-10-27 17:40 Barnabás Pőcze
2026-10-27 17:40 ` [PATCH v2 2/2] media: rppx1: Update shadowed registers Barnabás Pőcze
2026-11-04 10:17 ` [PATCH v2 1/2] media: rppx1: Move register definitions to header Niklas Söderlund
0 siblings, 2 replies; 4+ messages in thread
From: Barnabás Pőcze @ 2026-10-27 17:40 UTC (permalink / raw)
To: Jacopo Mondi, Jai Luthra, Niklas Söderlund, Mauro Carvalho Chehab
Cc: linux-media, linux-kernel, Barnabás Pőcze
Some definitions will be subsequently used outside of `rppx1.c`,
so move the register definitions into `rppx1.h`.
Signed-off-by: Barnabás Pőcze <barnabas.pocze+renesas@ideasonboard.com>
---
.../media/platform/dreamchip/rppx1/rppx1.c | 92 -------------------
.../media/platform/dreamchip/rppx1/rppx1.h | 92 +++++++++++++++++++
2 files changed, 92 insertions(+), 92 deletions(-)
diff --git a/drivers/media/platform/dreamchip/rppx1/rppx1.c b/drivers/media/platform/dreamchip/rppx1/rppx1.c
index c502be7979146..c03dd061783a5 100644
--- a/drivers/media/platform/dreamchip/rppx1/rppx1.c
+++ b/drivers/media/platform/dreamchip/rppx1/rppx1.c
@@ -14,98 +14,6 @@
#include "rppx1.h"
-/* RPP_HDR Base Addresses */
-#define RPPX1_HDRREGS_BASE 0x0000
-#define RPPX1_HDR_IRQ_BASE 0x0200
-#define RPPX1_RPP_OUT_BASE 0x0800
-#define RPPX1_RPP_RMAP_BASE 0x0c00
-#define RPPX1_RPP_RMAP_MEAS_BASE 0x1000
-#define RPPX1_RPP_MAIN_PRE1_BASE 0x2000
-#define RPPX1_RPP_MAIN_PRE2_BASE 0x4000
-#define RPPX1_RPP_MAIN_POST_BASE 0xa000
-#define RPPX1_RPP_MVOUT_BASE 0xc000
-#define RPPX1_RPP_FUSA_BASE 0xf000
-
-#define RPPX1_RPP_HDRREGS_VERSION_REG (RPPX1_HDRREGS_BASE + 0x0000)
-
-#define RPPX1_RPP_HDR_UPD_REG (RPPX1_HDRREGS_BASE + 0x0004)
-#define RPPX1_RPP_HDR_UPD_REGS_GEN_CFG_UPD BIT(1)
-#define RPPX1_RPP_HDR_UPD_REGS_CFG_UPD BIT(0)
-
-#define RPPX1_RESERVED_3_REG (RPPX1_HDRREGS_BASE + 0x0008)
-
-#define RPPX1_RPP_HDR_INFORM_ENABLE_REG (RPPX1_HDRREGS_BASE + 0x000c)
-#define RPPX1_RPP_HDR_INFORM_ENABLE_ENABLE 1
-#define RPPX1_RPP_HDR_INFORM_ENABLE_DISABLE 0
-
-#define RPPX1_RPP_HDR_OUT_IF_ON_REG (RPPX1_HDRREGS_BASE + 0x0010)
-#define RPPX1_RPP_HDR_OUT_IF_OFF_REG (RPPX1_HDRREGS_BASE + 0x0014)
-
-#define RPPX1_RPP_HDR_SAFETY_ACCESS_PROTECTION_REG (RPPX1_HDRREGS_BASE + 0x0018)
-#define RPPX1_RPP_HDR_SAFETY_ACCESS_PROTECTION_ENABLE 1
-#define RPPX1_RPP_HDR_SAFETY_ACCESS_PROTECTION_DISABLE 0
-
-#define RPPX1_RPP_ISM (RPPX1_HDR_IRQ_BASE + 0x00)
-#define RPPX1_RPP_RIS (RPPX1_HDR_IRQ_BASE + 0x04)
-#define RPPX1_RPP_MIS (RPPX1_HDR_IRQ_BASE + 0x08)
-#define RPPX1_RPP_ISC (RPPX1_HDR_IRQ_BASE + 0x0c)
-
-/* RPP_OUT/MV_OUT Pipelines - Base Addresses */
-#define RPPX1_GAMMA_OUT_BASE 0x0000 /* HV, MV */
-#define RPPX1_IS_BASE 0x00c0 /* HV, MV */
-#define RPPX1_CSM_BASE 0x0100 /* HV, MV */
-#define RPPX1_OUT_IF_BASE 0x0200 /* HV, MV */
-#define RPPX1_RPP_OUTREGS_BASE 0x02c0 /* HV, MV */
-#define RPPX1_LUV_BASE 0x0300 /* MV */
-
-/* PRE1/PRE2/POST Pipelines - Base Addresses */
-#define RPPX1_ACQ_BASE 0x0080 /* PRE1, PRE2 */
-#define RPPX1_BLS_BASE 0x0100 /* PRE1, PRE2 */
-#define RPPX1_GAMMA_IN_BASE 0x0200 /* PRE1, PRE2 */
-#define RPPX1_LSC_BASE 0x0400 /* PRE1, PRE2 */
-#define RPPX1_AWB_GAIN_BASE 0x0500 /* PRE1, PRE2, POST */
-#define RPPX1_DPCC_BASE 0x0600 /* PRE1, PRE2 */
-#define RPPX1_DPF_BASE 0x0700 /* PRE1, PRE2 */
-#define RPPX1_FILT_BASE 0x0800 /* POST */
-#define RPPX1_CAC_BASE 0x0880 /* POST */
-#define RPPX1_CCOR_BASE 0x0900 /* POST */
-#define RPPX1_HIST_BASE 0x0a00 /* PRE1, PRE2, POST */
-#define RPPX1_HIST256_BASE 0x0b00 /* PRE1 */
-#define RPPX1_EXM_BASE 0x0c00 /* PRE1, PRE2 */
-#define RPPX1_LTM_BASE 0x1000 /* POST */
-#define RPPX1_LTM_MEAS_BASE 0x1200 /* POST */
-#define RPPX1_WBMEAS_BASE 0x1700 /* POST */
-#define RPPX1_BDRGB_BASE 0x1800 /* POST */
-#define RPPX1_SHRP_BASE 0x1a00 /* POST */
-
-/* Functional Safety Module Base Addresses */
-#define RPPX1_FMU_BASE 0x0100
-
-#define RPPX1_RPP_HDR_FMU_FSM_REG (RPPX1_RPP_FUSA_BASE + RPPX1_FMU_BASE + 0x00)
-#define RPPX1_RPP_HDR_FMU_FSM_FSM_IRQM_FAULT BIT(23)
-#define RPPX1_RPP_HDR_FMU_FSM_PRE2_SIZE_FAULT BIT(20)
-#define RPPX1_RPP_HDR_FMU_FSM_PRE2_TIME_FAULT BIT(19)
-#define RPPX1_RPP_HDR_FMU_FSM_PRE1_SIZE_FAULT BIT(18)
-#define RPPX1_RPP_HDR_FMU_FSM_PRE1_TIME_FAULT BIT(17)
-#define RPPX1_RPP_HDR_FMU_FSM_SIZE_FAULT BIT(16)
-#define RPPX1_RPP_HDR_FMU_FSM_TIME_FAULT BIT(15)
-#define RPPX1_RPP_HDR_FMU_FSM_MV_OUT_SIZE_FAULT BIT(14)
-#define RPPX1_RPP_HDR_FMU_FSM_MV_OUT_TIME_FAULT BIT(13)
-#define RPPX1_RPP_HDR_FMU_FSM_HV_OUT_SIZE_FAULT BIT(12)
-#define RPPX1_RPP_HDR_FMU_FSM_HV_OUT_TIME_FAULT BIT(11)
-#define RPPX1_RPP_HDR_FMU_FSM_MV_OUT_SIZE_ERR BIT(10)
-#define RPPX1_RPP_HDR_FMU_FSM_IS_OUT_SIZE_ERR BIT(9)
-#define RPPX1_RPP_HDR_FMU_FSM_PRE2_FIFO_OVFLW BIT(7)
-#define RPPX1_RPP_HDR_FMU_FSM_PRE1_FIFO_OVFLW BIT(6)
-#define RPPX1_RPP_HDR_FMU_FSM_PRE1_INFORM_SIZE BIT(5)
-#define RPPX1_RPP_HDR_FMU_FSM_PRE1_OUTFORM_SIZE BIT(4)
-#define RPPX1_RPP_HDR_FMU_FSM_PRE2_INFORM_SIZE BIT(3)
-#define RPPX1_RPP_HDR_FMU_FSM_PRE2_OUTFORM_SIZE BIT(2)
-
-#define RPPX1_RPP_HDR_FMU_RFS_REG (RPPX1_RPP_FUSA_BASE + RPPX1_FMU_BASE + 0x04)
-#define RPPX1_RPP_HDR_FMU_MFS_REG (RPPX1_RPP_FUSA_BASE + RPPX1_FMU_BASE + 0x08)
-#define RPPX1_RPP_HDR_FMU_FSC_REG (RPPX1_RPP_FUSA_BASE + RPPX1_FMU_BASE + 0x0c)
-
void rppx1_write(struct rppx1 *rpp, u32 offset, u32 value)
{
iowrite32(value, rpp->base + offset);
diff --git a/drivers/media/platform/dreamchip/rppx1/rppx1.h b/drivers/media/platform/dreamchip/rppx1/rppx1.h
index 3bf3955afbaed..825499f8f709c 100644
--- a/drivers/media/platform/dreamchip/rppx1/rppx1.h
+++ b/drivers/media/platform/dreamchip/rppx1/rppx1.h
@@ -13,6 +13,98 @@
#include "rpp_module.h"
+/* RPP_HDR Base Addresses */
+#define RPPX1_HDRREGS_BASE 0x0000
+#define RPPX1_HDR_IRQ_BASE 0x0200
+#define RPPX1_RPP_OUT_BASE 0x0800
+#define RPPX1_RPP_RMAP_BASE 0x0c00
+#define RPPX1_RPP_RMAP_MEAS_BASE 0x1000
+#define RPPX1_RPP_MAIN_PRE1_BASE 0x2000
+#define RPPX1_RPP_MAIN_PRE2_BASE 0x4000
+#define RPPX1_RPP_MAIN_POST_BASE 0xa000
+#define RPPX1_RPP_MVOUT_BASE 0xc000
+#define RPPX1_RPP_FUSA_BASE 0xf000
+
+#define RPPX1_RPP_HDRREGS_VERSION_REG (RPPX1_HDRREGS_BASE + 0x0000)
+
+#define RPPX1_RPP_HDR_UPD_REG (RPPX1_HDRREGS_BASE + 0x0004)
+#define RPPX1_RPP_HDR_UPD_REGS_GEN_CFG_UPD BIT(1)
+#define RPPX1_RPP_HDR_UPD_REGS_CFG_UPD BIT(0)
+
+#define RPPX1_RESERVED_3_REG (RPPX1_HDRREGS_BASE + 0x0008)
+
+#define RPPX1_RPP_HDR_INFORM_ENABLE_REG (RPPX1_HDRREGS_BASE + 0x000c)
+#define RPPX1_RPP_HDR_INFORM_ENABLE_ENABLE 1
+#define RPPX1_RPP_HDR_INFORM_ENABLE_DISABLE 0
+
+#define RPPX1_RPP_HDR_OUT_IF_ON_REG (RPPX1_HDRREGS_BASE + 0x0010)
+#define RPPX1_RPP_HDR_OUT_IF_OFF_REG (RPPX1_HDRREGS_BASE + 0x0014)
+
+#define RPPX1_RPP_HDR_SAFETY_ACCESS_PROTECTION_REG (RPPX1_HDRREGS_BASE + 0x0018)
+#define RPPX1_RPP_HDR_SAFETY_ACCESS_PROTECTION_ENABLE 1
+#define RPPX1_RPP_HDR_SAFETY_ACCESS_PROTECTION_DISABLE 0
+
+#define RPPX1_RPP_ISM (RPPX1_HDR_IRQ_BASE + 0x00)
+#define RPPX1_RPP_RIS (RPPX1_HDR_IRQ_BASE + 0x04)
+#define RPPX1_RPP_MIS (RPPX1_HDR_IRQ_BASE + 0x08)
+#define RPPX1_RPP_ISC (RPPX1_HDR_IRQ_BASE + 0x0c)
+
+/* RPP_OUT/MV_OUT Pipelines - Base Addresses */
+#define RPPX1_GAMMA_OUT_BASE 0x0000 /* HV, MV */
+#define RPPX1_IS_BASE 0x00c0 /* HV, MV */
+#define RPPX1_CSM_BASE 0x0100 /* HV, MV */
+#define RPPX1_OUT_IF_BASE 0x0200 /* HV, MV */
+#define RPPX1_RPP_OUTREGS_BASE 0x02c0 /* HV, MV */
+#define RPPX1_LUV_BASE 0x0300 /* MV */
+
+/* PRE1/PRE2/POST Pipelines - Base Addresses */
+#define RPPX1_ACQ_BASE 0x0080 /* PRE1, PRE2 */
+#define RPPX1_BLS_BASE 0x0100 /* PRE1, PRE2 */
+#define RPPX1_GAMMA_IN_BASE 0x0200 /* PRE1, PRE2 */
+#define RPPX1_LSC_BASE 0x0400 /* PRE1, PRE2 */
+#define RPPX1_AWB_GAIN_BASE 0x0500 /* PRE1, PRE2, POST */
+#define RPPX1_DPCC_BASE 0x0600 /* PRE1, PRE2 */
+#define RPPX1_DPF_BASE 0x0700 /* PRE1, PRE2 */
+#define RPPX1_FILT_BASE 0x0800 /* POST */
+#define RPPX1_CAC_BASE 0x0880 /* POST */
+#define RPPX1_CCOR_BASE 0x0900 /* POST */
+#define RPPX1_HIST_BASE 0x0a00 /* PRE1, PRE2, POST */
+#define RPPX1_HIST256_BASE 0x0b00 /* PRE1 */
+#define RPPX1_EXM_BASE 0x0c00 /* PRE1, PRE2 */
+#define RPPX1_LTM_BASE 0x1000 /* POST */
+#define RPPX1_LTM_MEAS_BASE 0x1200 /* POST */
+#define RPPX1_WBMEAS_BASE 0x1700 /* POST */
+#define RPPX1_BDRGB_BASE 0x1800 /* POST */
+#define RPPX1_SHRP_BASE 0x1a00 /* POST */
+
+/* Functional Safety Module Base Addresses */
+#define RPPX1_FMU_BASE 0x0100
+
+#define RPPX1_RPP_HDR_FMU_FSM_REG (RPPX1_RPP_FUSA_BASE + RPPX1_FMU_BASE + 0x00)
+#define RPPX1_RPP_HDR_FMU_FSM_FSM_IRQM_FAULT BIT(23)
+#define RPPX1_RPP_HDR_FMU_FSM_PRE2_SIZE_FAULT BIT(20)
+#define RPPX1_RPP_HDR_FMU_FSM_PRE2_TIME_FAULT BIT(19)
+#define RPPX1_RPP_HDR_FMU_FSM_PRE1_SIZE_FAULT BIT(18)
+#define RPPX1_RPP_HDR_FMU_FSM_PRE1_TIME_FAULT BIT(17)
+#define RPPX1_RPP_HDR_FMU_FSM_SIZE_FAULT BIT(16)
+#define RPPX1_RPP_HDR_FMU_FSM_TIME_FAULT BIT(15)
+#define RPPX1_RPP_HDR_FMU_FSM_MV_OUT_SIZE_FAULT BIT(14)
+#define RPPX1_RPP_HDR_FMU_FSM_MV_OUT_TIME_FAULT BIT(13)
+#define RPPX1_RPP_HDR_FMU_FSM_HV_OUT_SIZE_FAULT BIT(12)
+#define RPPX1_RPP_HDR_FMU_FSM_HV_OUT_TIME_FAULT BIT(11)
+#define RPPX1_RPP_HDR_FMU_FSM_MV_OUT_SIZE_ERR BIT(10)
+#define RPPX1_RPP_HDR_FMU_FSM_IS_OUT_SIZE_ERR BIT(9)
+#define RPPX1_RPP_HDR_FMU_FSM_PRE2_FIFO_OVFLW BIT(7)
+#define RPPX1_RPP_HDR_FMU_FSM_PRE1_FIFO_OVFLW BIT(6)
+#define RPPX1_RPP_HDR_FMU_FSM_PRE1_INFORM_SIZE BIT(5)
+#define RPPX1_RPP_HDR_FMU_FSM_PRE1_OUTFORM_SIZE BIT(4)
+#define RPPX1_RPP_HDR_FMU_FSM_PRE2_INFORM_SIZE BIT(3)
+#define RPPX1_RPP_HDR_FMU_FSM_PRE2_OUTFORM_SIZE BIT(2)
+
+#define RPPX1_RPP_HDR_FMU_RFS_REG (RPPX1_RPP_FUSA_BASE + RPPX1_FMU_BASE + 0x04)
+#define RPPX1_RPP_HDR_FMU_MFS_REG (RPPX1_RPP_FUSA_BASE + RPPX1_FMU_BASE + 0x08)
+#define RPPX1_RPP_HDR_FMU_FSC_REG (RPPX1_RPP_FUSA_BASE + RPPX1_FMU_BASE + 0x0c)
+
#define RPPX1_IRQ_ID_256HIST BIT(27)
#define RPPX1_IRQ_ID_PRE2_DPCC BIT(25)
#define RPPX1_IRQ_ID_PRE1_DPCC BIT(24)
--
2.56.0
^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH v2 2/2] media: rppx1: Update shadowed registers
2026-10-27 17:40 [PATCH v2 1/2] media: rppx1: Move register definitions to header Barnabás Pőcze
@ 2026-10-27 17:40 ` Barnabás Pőcze
2026-11-04 10:19 ` Niklas Söderlund
2026-11-04 10:17 ` [PATCH v2 1/2] media: rppx1: Move register definitions to header Niklas Söderlund
1 sibling, 1 reply; 4+ messages in thread
From: Barnabás Pőcze @ 2026-10-27 17:40 UTC (permalink / raw)
To: Jacopo Mondi, Jai Luthra, Niklas Söderlund, Mauro Carvalho Chehab
Cc: linux-media, linux-kernel, Barnabás Pőcze
Certain registers are shadowed and changes to those must be explicly
applied. Updating the shadowed registers after a frame is complete can
be done by writing `RPPX1_RPP_HDR_UPD_REGS_GEN_CFG_UPD` to the
`RPPX1_RPP_HDR_UPD_REG` register.
This is already done in `rppx1_start()`, but this auto-update feature
is documented as "self reset at picture end". Therefore setting it
at start will only auto-update the registers once, after the first
frame.
For example, this causes that the LSC module cannot be toggled after
the first frame. This behaviour can be tested by reading the first
bit of `LSC_STATUS_REG`, which will show the same value after the
first frame regardless of what was last written to `LSC_CTRL_REG`.
Fix this by unconditionall triggering an auto-update when a parameter
buffer is processed in `rppx1_params()`.
Signed-off-by: Barnabás Pőcze <barnabas.pocze+renesas@ideasonboard.com>
---
drivers/media/platform/dreamchip/rppx1/rpp_params.c | 3 +++
drivers/media/platform/dreamchip/rppx1/rppx1.c | 3 ---
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/media/platform/dreamchip/rppx1/rpp_params.c b/drivers/media/platform/dreamchip/rppx1/rpp_params.c
index a75a27a8afd09..cbc9847ba5be6 100644
--- a/drivers/media/platform/dreamchip/rppx1/rpp_params.c
+++ b/drivers/media/platform/dreamchip/rppx1/rpp_params.c
@@ -110,6 +110,9 @@ int rppx1_params(struct rppx1 *rpp, struct vb2_buffer *vb, size_t max_size,
}
}
+ /* Trigger update of shadowed registers after frame is done. */
+ write(priv, RPPX1_RPP_HDR_UPD_REG, RPPX1_RPP_HDR_UPD_REGS_GEN_CFG_UPD);
+
return 0;
}
EXPORT_SYMBOL_GPL(rppx1_params);
diff --git a/drivers/media/platform/dreamchip/rppx1/rppx1.c b/drivers/media/platform/dreamchip/rppx1/rppx1.c
index c03dd061783a5..a3c923a57d922 100644
--- a/drivers/media/platform/dreamchip/rppx1/rppx1.c
+++ b/drivers/media/platform/dreamchip/rppx1/rppx1.c
@@ -257,9 +257,6 @@ int rppx1_start(struct rppx1 *rpp,
/* Immediate commit update for shadows. */
rppx1_write(rpp, RPPX1_RPP_HDR_UPD_REG, RPPX1_RPP_HDR_UPD_REGS_CFG_UPD);
- /* Then for operation update shadows with picture synchronization. */
- rppx1_write(rpp, RPPX1_RPP_HDR_UPD_REG, RPPX1_RPP_HDR_UPD_REGS_GEN_CFG_UPD);
-
/* Clear any pending interrupts. */
rppx1_interrupt(rpp, NULL);
--
2.56.0
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v2 1/2] media: rppx1: Move register definitions to header
2026-10-27 17:40 [PATCH v2 1/2] media: rppx1: Move register definitions to header Barnabás Pőcze
2026-10-27 17:40 ` [PATCH v2 2/2] media: rppx1: Update shadowed registers Barnabás Pőcze
@ 2026-11-04 10:17 ` Niklas Söderlund
1 sibling, 0 replies; 4+ messages in thread
From: Niklas Söderlund @ 2026-11-04 10:17 UTC (permalink / raw)
To: Barnabás Pőcze
Cc: Jacopo Mondi, Jai Luthra, Mauro Carvalho Chehab, linux-media,
linux-kernel
Hi Barnabás,
Thanks for your patch.
On 2026-10-27 18:40:13 +0100, Barnabás Pőcze wrote:
> Some definitions will be subsequently used outside of `rppx1.c`,
> so move the register definitions into `rppx1.h`.
>
> Signed-off-by: Barnabás Pőcze <barnabas.pocze+renesas@ideasonboard.com>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
> ---
> .../media/platform/dreamchip/rppx1/rppx1.c | 92 -------------------
> .../media/platform/dreamchip/rppx1/rppx1.h | 92 +++++++++++++++++++
> 2 files changed, 92 insertions(+), 92 deletions(-)
>
> diff --git a/drivers/media/platform/dreamchip/rppx1/rppx1.c b/drivers/media/platform/dreamchip/rppx1/rppx1.c
> index c502be7979146..c03dd061783a5 100644
> --- a/drivers/media/platform/dreamchip/rppx1/rppx1.c
> +++ b/drivers/media/platform/dreamchip/rppx1/rppx1.c
> @@ -14,98 +14,6 @@
>
> #include "rppx1.h"
>
> -/* RPP_HDR Base Addresses */
> -#define RPPX1_HDRREGS_BASE 0x0000
> -#define RPPX1_HDR_IRQ_BASE 0x0200
> -#define RPPX1_RPP_OUT_BASE 0x0800
> -#define RPPX1_RPP_RMAP_BASE 0x0c00
> -#define RPPX1_RPP_RMAP_MEAS_BASE 0x1000
> -#define RPPX1_RPP_MAIN_PRE1_BASE 0x2000
> -#define RPPX1_RPP_MAIN_PRE2_BASE 0x4000
> -#define RPPX1_RPP_MAIN_POST_BASE 0xa000
> -#define RPPX1_RPP_MVOUT_BASE 0xc000
> -#define RPPX1_RPP_FUSA_BASE 0xf000
> -
> -#define RPPX1_RPP_HDRREGS_VERSION_REG (RPPX1_HDRREGS_BASE + 0x0000)
> -
> -#define RPPX1_RPP_HDR_UPD_REG (RPPX1_HDRREGS_BASE + 0x0004)
> -#define RPPX1_RPP_HDR_UPD_REGS_GEN_CFG_UPD BIT(1)
> -#define RPPX1_RPP_HDR_UPD_REGS_CFG_UPD BIT(0)
> -
> -#define RPPX1_RESERVED_3_REG (RPPX1_HDRREGS_BASE + 0x0008)
> -
> -#define RPPX1_RPP_HDR_INFORM_ENABLE_REG (RPPX1_HDRREGS_BASE + 0x000c)
> -#define RPPX1_RPP_HDR_INFORM_ENABLE_ENABLE 1
> -#define RPPX1_RPP_HDR_INFORM_ENABLE_DISABLE 0
> -
> -#define RPPX1_RPP_HDR_OUT_IF_ON_REG (RPPX1_HDRREGS_BASE + 0x0010)
> -#define RPPX1_RPP_HDR_OUT_IF_OFF_REG (RPPX1_HDRREGS_BASE + 0x0014)
> -
> -#define RPPX1_RPP_HDR_SAFETY_ACCESS_PROTECTION_REG (RPPX1_HDRREGS_BASE + 0x0018)
> -#define RPPX1_RPP_HDR_SAFETY_ACCESS_PROTECTION_ENABLE 1
> -#define RPPX1_RPP_HDR_SAFETY_ACCESS_PROTECTION_DISABLE 0
> -
> -#define RPPX1_RPP_ISM (RPPX1_HDR_IRQ_BASE + 0x00)
> -#define RPPX1_RPP_RIS (RPPX1_HDR_IRQ_BASE + 0x04)
> -#define RPPX1_RPP_MIS (RPPX1_HDR_IRQ_BASE + 0x08)
> -#define RPPX1_RPP_ISC (RPPX1_HDR_IRQ_BASE + 0x0c)
> -
> -/* RPP_OUT/MV_OUT Pipelines - Base Addresses */
> -#define RPPX1_GAMMA_OUT_BASE 0x0000 /* HV, MV */
> -#define RPPX1_IS_BASE 0x00c0 /* HV, MV */
> -#define RPPX1_CSM_BASE 0x0100 /* HV, MV */
> -#define RPPX1_OUT_IF_BASE 0x0200 /* HV, MV */
> -#define RPPX1_RPP_OUTREGS_BASE 0x02c0 /* HV, MV */
> -#define RPPX1_LUV_BASE 0x0300 /* MV */
> -
> -/* PRE1/PRE2/POST Pipelines - Base Addresses */
> -#define RPPX1_ACQ_BASE 0x0080 /* PRE1, PRE2 */
> -#define RPPX1_BLS_BASE 0x0100 /* PRE1, PRE2 */
> -#define RPPX1_GAMMA_IN_BASE 0x0200 /* PRE1, PRE2 */
> -#define RPPX1_LSC_BASE 0x0400 /* PRE1, PRE2 */
> -#define RPPX1_AWB_GAIN_BASE 0x0500 /* PRE1, PRE2, POST */
> -#define RPPX1_DPCC_BASE 0x0600 /* PRE1, PRE2 */
> -#define RPPX1_DPF_BASE 0x0700 /* PRE1, PRE2 */
> -#define RPPX1_FILT_BASE 0x0800 /* POST */
> -#define RPPX1_CAC_BASE 0x0880 /* POST */
> -#define RPPX1_CCOR_BASE 0x0900 /* POST */
> -#define RPPX1_HIST_BASE 0x0a00 /* PRE1, PRE2, POST */
> -#define RPPX1_HIST256_BASE 0x0b00 /* PRE1 */
> -#define RPPX1_EXM_BASE 0x0c00 /* PRE1, PRE2 */
> -#define RPPX1_LTM_BASE 0x1000 /* POST */
> -#define RPPX1_LTM_MEAS_BASE 0x1200 /* POST */
> -#define RPPX1_WBMEAS_BASE 0x1700 /* POST */
> -#define RPPX1_BDRGB_BASE 0x1800 /* POST */
> -#define RPPX1_SHRP_BASE 0x1a00 /* POST */
> -
> -/* Functional Safety Module Base Addresses */
> -#define RPPX1_FMU_BASE 0x0100
> -
> -#define RPPX1_RPP_HDR_FMU_FSM_REG (RPPX1_RPP_FUSA_BASE + RPPX1_FMU_BASE + 0x00)
> -#define RPPX1_RPP_HDR_FMU_FSM_FSM_IRQM_FAULT BIT(23)
> -#define RPPX1_RPP_HDR_FMU_FSM_PRE2_SIZE_FAULT BIT(20)
> -#define RPPX1_RPP_HDR_FMU_FSM_PRE2_TIME_FAULT BIT(19)
> -#define RPPX1_RPP_HDR_FMU_FSM_PRE1_SIZE_FAULT BIT(18)
> -#define RPPX1_RPP_HDR_FMU_FSM_PRE1_TIME_FAULT BIT(17)
> -#define RPPX1_RPP_HDR_FMU_FSM_SIZE_FAULT BIT(16)
> -#define RPPX1_RPP_HDR_FMU_FSM_TIME_FAULT BIT(15)
> -#define RPPX1_RPP_HDR_FMU_FSM_MV_OUT_SIZE_FAULT BIT(14)
> -#define RPPX1_RPP_HDR_FMU_FSM_MV_OUT_TIME_FAULT BIT(13)
> -#define RPPX1_RPP_HDR_FMU_FSM_HV_OUT_SIZE_FAULT BIT(12)
> -#define RPPX1_RPP_HDR_FMU_FSM_HV_OUT_TIME_FAULT BIT(11)
> -#define RPPX1_RPP_HDR_FMU_FSM_MV_OUT_SIZE_ERR BIT(10)
> -#define RPPX1_RPP_HDR_FMU_FSM_IS_OUT_SIZE_ERR BIT(9)
> -#define RPPX1_RPP_HDR_FMU_FSM_PRE2_FIFO_OVFLW BIT(7)
> -#define RPPX1_RPP_HDR_FMU_FSM_PRE1_FIFO_OVFLW BIT(6)
> -#define RPPX1_RPP_HDR_FMU_FSM_PRE1_INFORM_SIZE BIT(5)
> -#define RPPX1_RPP_HDR_FMU_FSM_PRE1_OUTFORM_SIZE BIT(4)
> -#define RPPX1_RPP_HDR_FMU_FSM_PRE2_INFORM_SIZE BIT(3)
> -#define RPPX1_RPP_HDR_FMU_FSM_PRE2_OUTFORM_SIZE BIT(2)
> -
> -#define RPPX1_RPP_HDR_FMU_RFS_REG (RPPX1_RPP_FUSA_BASE + RPPX1_FMU_BASE + 0x04)
> -#define RPPX1_RPP_HDR_FMU_MFS_REG (RPPX1_RPP_FUSA_BASE + RPPX1_FMU_BASE + 0x08)
> -#define RPPX1_RPP_HDR_FMU_FSC_REG (RPPX1_RPP_FUSA_BASE + RPPX1_FMU_BASE + 0x0c)
> -
> void rppx1_write(struct rppx1 *rpp, u32 offset, u32 value)
> {
> iowrite32(value, rpp->base + offset);
> diff --git a/drivers/media/platform/dreamchip/rppx1/rppx1.h b/drivers/media/platform/dreamchip/rppx1/rppx1.h
> index 3bf3955afbaed..825499f8f709c 100644
> --- a/drivers/media/platform/dreamchip/rppx1/rppx1.h
> +++ b/drivers/media/platform/dreamchip/rppx1/rppx1.h
> @@ -13,6 +13,98 @@
>
> #include "rpp_module.h"
>
> +/* RPP_HDR Base Addresses */
> +#define RPPX1_HDRREGS_BASE 0x0000
> +#define RPPX1_HDR_IRQ_BASE 0x0200
> +#define RPPX1_RPP_OUT_BASE 0x0800
> +#define RPPX1_RPP_RMAP_BASE 0x0c00
> +#define RPPX1_RPP_RMAP_MEAS_BASE 0x1000
> +#define RPPX1_RPP_MAIN_PRE1_BASE 0x2000
> +#define RPPX1_RPP_MAIN_PRE2_BASE 0x4000
> +#define RPPX1_RPP_MAIN_POST_BASE 0xa000
> +#define RPPX1_RPP_MVOUT_BASE 0xc000
> +#define RPPX1_RPP_FUSA_BASE 0xf000
> +
> +#define RPPX1_RPP_HDRREGS_VERSION_REG (RPPX1_HDRREGS_BASE + 0x0000)
> +
> +#define RPPX1_RPP_HDR_UPD_REG (RPPX1_HDRREGS_BASE + 0x0004)
> +#define RPPX1_RPP_HDR_UPD_REGS_GEN_CFG_UPD BIT(1)
> +#define RPPX1_RPP_HDR_UPD_REGS_CFG_UPD BIT(0)
> +
> +#define RPPX1_RESERVED_3_REG (RPPX1_HDRREGS_BASE + 0x0008)
> +
> +#define RPPX1_RPP_HDR_INFORM_ENABLE_REG (RPPX1_HDRREGS_BASE + 0x000c)
> +#define RPPX1_RPP_HDR_INFORM_ENABLE_ENABLE 1
> +#define RPPX1_RPP_HDR_INFORM_ENABLE_DISABLE 0
> +
> +#define RPPX1_RPP_HDR_OUT_IF_ON_REG (RPPX1_HDRREGS_BASE + 0x0010)
> +#define RPPX1_RPP_HDR_OUT_IF_OFF_REG (RPPX1_HDRREGS_BASE + 0x0014)
> +
> +#define RPPX1_RPP_HDR_SAFETY_ACCESS_PROTECTION_REG (RPPX1_HDRREGS_BASE + 0x0018)
> +#define RPPX1_RPP_HDR_SAFETY_ACCESS_PROTECTION_ENABLE 1
> +#define RPPX1_RPP_HDR_SAFETY_ACCESS_PROTECTION_DISABLE 0
> +
> +#define RPPX1_RPP_ISM (RPPX1_HDR_IRQ_BASE + 0x00)
> +#define RPPX1_RPP_RIS (RPPX1_HDR_IRQ_BASE + 0x04)
> +#define RPPX1_RPP_MIS (RPPX1_HDR_IRQ_BASE + 0x08)
> +#define RPPX1_RPP_ISC (RPPX1_HDR_IRQ_BASE + 0x0c)
> +
> +/* RPP_OUT/MV_OUT Pipelines - Base Addresses */
> +#define RPPX1_GAMMA_OUT_BASE 0x0000 /* HV, MV */
> +#define RPPX1_IS_BASE 0x00c0 /* HV, MV */
> +#define RPPX1_CSM_BASE 0x0100 /* HV, MV */
> +#define RPPX1_OUT_IF_BASE 0x0200 /* HV, MV */
> +#define RPPX1_RPP_OUTREGS_BASE 0x02c0 /* HV, MV */
> +#define RPPX1_LUV_BASE 0x0300 /* MV */
> +
> +/* PRE1/PRE2/POST Pipelines - Base Addresses */
> +#define RPPX1_ACQ_BASE 0x0080 /* PRE1, PRE2 */
> +#define RPPX1_BLS_BASE 0x0100 /* PRE1, PRE2 */
> +#define RPPX1_GAMMA_IN_BASE 0x0200 /* PRE1, PRE2 */
> +#define RPPX1_LSC_BASE 0x0400 /* PRE1, PRE2 */
> +#define RPPX1_AWB_GAIN_BASE 0x0500 /* PRE1, PRE2, POST */
> +#define RPPX1_DPCC_BASE 0x0600 /* PRE1, PRE2 */
> +#define RPPX1_DPF_BASE 0x0700 /* PRE1, PRE2 */
> +#define RPPX1_FILT_BASE 0x0800 /* POST */
> +#define RPPX1_CAC_BASE 0x0880 /* POST */
> +#define RPPX1_CCOR_BASE 0x0900 /* POST */
> +#define RPPX1_HIST_BASE 0x0a00 /* PRE1, PRE2, POST */
> +#define RPPX1_HIST256_BASE 0x0b00 /* PRE1 */
> +#define RPPX1_EXM_BASE 0x0c00 /* PRE1, PRE2 */
> +#define RPPX1_LTM_BASE 0x1000 /* POST */
> +#define RPPX1_LTM_MEAS_BASE 0x1200 /* POST */
> +#define RPPX1_WBMEAS_BASE 0x1700 /* POST */
> +#define RPPX1_BDRGB_BASE 0x1800 /* POST */
> +#define RPPX1_SHRP_BASE 0x1a00 /* POST */
> +
> +/* Functional Safety Module Base Addresses */
> +#define RPPX1_FMU_BASE 0x0100
> +
> +#define RPPX1_RPP_HDR_FMU_FSM_REG (RPPX1_RPP_FUSA_BASE + RPPX1_FMU_BASE + 0x00)
> +#define RPPX1_RPP_HDR_FMU_FSM_FSM_IRQM_FAULT BIT(23)
> +#define RPPX1_RPP_HDR_FMU_FSM_PRE2_SIZE_FAULT BIT(20)
> +#define RPPX1_RPP_HDR_FMU_FSM_PRE2_TIME_FAULT BIT(19)
> +#define RPPX1_RPP_HDR_FMU_FSM_PRE1_SIZE_FAULT BIT(18)
> +#define RPPX1_RPP_HDR_FMU_FSM_PRE1_TIME_FAULT BIT(17)
> +#define RPPX1_RPP_HDR_FMU_FSM_SIZE_FAULT BIT(16)
> +#define RPPX1_RPP_HDR_FMU_FSM_TIME_FAULT BIT(15)
> +#define RPPX1_RPP_HDR_FMU_FSM_MV_OUT_SIZE_FAULT BIT(14)
> +#define RPPX1_RPP_HDR_FMU_FSM_MV_OUT_TIME_FAULT BIT(13)
> +#define RPPX1_RPP_HDR_FMU_FSM_HV_OUT_SIZE_FAULT BIT(12)
> +#define RPPX1_RPP_HDR_FMU_FSM_HV_OUT_TIME_FAULT BIT(11)
> +#define RPPX1_RPP_HDR_FMU_FSM_MV_OUT_SIZE_ERR BIT(10)
> +#define RPPX1_RPP_HDR_FMU_FSM_IS_OUT_SIZE_ERR BIT(9)
> +#define RPPX1_RPP_HDR_FMU_FSM_PRE2_FIFO_OVFLW BIT(7)
> +#define RPPX1_RPP_HDR_FMU_FSM_PRE1_FIFO_OVFLW BIT(6)
> +#define RPPX1_RPP_HDR_FMU_FSM_PRE1_INFORM_SIZE BIT(5)
> +#define RPPX1_RPP_HDR_FMU_FSM_PRE1_OUTFORM_SIZE BIT(4)
> +#define RPPX1_RPP_HDR_FMU_FSM_PRE2_INFORM_SIZE BIT(3)
> +#define RPPX1_RPP_HDR_FMU_FSM_PRE2_OUTFORM_SIZE BIT(2)
> +
> +#define RPPX1_RPP_HDR_FMU_RFS_REG (RPPX1_RPP_FUSA_BASE + RPPX1_FMU_BASE + 0x04)
> +#define RPPX1_RPP_HDR_FMU_MFS_REG (RPPX1_RPP_FUSA_BASE + RPPX1_FMU_BASE + 0x08)
> +#define RPPX1_RPP_HDR_FMU_FSC_REG (RPPX1_RPP_FUSA_BASE + RPPX1_FMU_BASE + 0x0c)
> +
> #define RPPX1_IRQ_ID_256HIST BIT(27)
> #define RPPX1_IRQ_ID_PRE2_DPCC BIT(25)
> #define RPPX1_IRQ_ID_PRE1_DPCC BIT(24)
> --
> 2.56.0
>
--
Kind Regards,
Niklas Söderlund
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH v2 2/2] media: rppx1: Update shadowed registers
2026-10-27 17:40 ` [PATCH v2 2/2] media: rppx1: Update shadowed registers Barnabás Pőcze
@ 2026-11-04 10:19 ` Niklas Söderlund
0 siblings, 0 replies; 4+ messages in thread
From: Niklas Söderlund @ 2026-11-04 10:19 UTC (permalink / raw)
To: Barnabás Pőcze
Cc: Jacopo Mondi, Jai Luthra, Mauro Carvalho Chehab, linux-media,
linux-kernel
Hi Barnabás,
Thanks for your work.
On 2026-10-27 18:40:14 +0100, Barnabás Pőcze wrote:
> Certain registers are shadowed and changes to those must be explicly
> applied. Updating the shadowed registers after a frame is complete can
> be done by writing `RPPX1_RPP_HDR_UPD_REGS_GEN_CFG_UPD` to the
> `RPPX1_RPP_HDR_UPD_REG` register.
>
> This is already done in `rppx1_start()`, but this auto-update feature
> is documented as "self reset at picture end". Therefore setting it
> at start will only auto-update the registers once, after the first
> frame.
>
> For example, this causes that the LSC module cannot be toggled after
> the first frame. This behaviour can be tested by reading the first
> bit of `LSC_STATUS_REG`, which will show the same value after the
> first frame regardless of what was last written to `LSC_CTRL_REG`.
>
> Fix this by unconditionall triggering an auto-update when a parameter
> buffer is processed in `rppx1_params()`.
>
> Signed-off-by: Barnabás Pőcze <barnabas.pocze+renesas@ideasonboard.com>
Looks good.
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
> ---
> drivers/media/platform/dreamchip/rppx1/rpp_params.c | 3 +++
> drivers/media/platform/dreamchip/rppx1/rppx1.c | 3 ---
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/media/platform/dreamchip/rppx1/rpp_params.c b/drivers/media/platform/dreamchip/rppx1/rpp_params.c
> index a75a27a8afd09..cbc9847ba5be6 100644
> --- a/drivers/media/platform/dreamchip/rppx1/rpp_params.c
> +++ b/drivers/media/platform/dreamchip/rppx1/rpp_params.c
> @@ -110,6 +110,9 @@ int rppx1_params(struct rppx1 *rpp, struct vb2_buffer *vb, size_t max_size,
> }
> }
>
> + /* Trigger update of shadowed registers after frame is done. */
> + write(priv, RPPX1_RPP_HDR_UPD_REG, RPPX1_RPP_HDR_UPD_REGS_GEN_CFG_UPD);
> +
> return 0;
> }
> EXPORT_SYMBOL_GPL(rppx1_params);
> diff --git a/drivers/media/platform/dreamchip/rppx1/rppx1.c b/drivers/media/platform/dreamchip/rppx1/rppx1.c
> index c03dd061783a5..a3c923a57d922 100644
> --- a/drivers/media/platform/dreamchip/rppx1/rppx1.c
> +++ b/drivers/media/platform/dreamchip/rppx1/rppx1.c
> @@ -257,9 +257,6 @@ int rppx1_start(struct rppx1 *rpp,
> /* Immediate commit update for shadows. */
> rppx1_write(rpp, RPPX1_RPP_HDR_UPD_REG, RPPX1_RPP_HDR_UPD_REGS_CFG_UPD);
>
> - /* Then for operation update shadows with picture synchronization. */
> - rppx1_write(rpp, RPPX1_RPP_HDR_UPD_REG, RPPX1_RPP_HDR_UPD_REGS_GEN_CFG_UPD);
> -
> /* Clear any pending interrupts. */
> rppx1_interrupt(rpp, NULL);
>
> --
> 2.56.0
>
--
Kind Regards,
Niklas Söderlund
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2026-11-04 10:19 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2026-10-27 17:40 [PATCH v2 1/2] media: rppx1: Move register definitions to header Barnabás Pőcze
2026-10-27 17:40 ` [PATCH v2 2/2] media: rppx1: Update shadowed registers Barnabás Pőcze
2026-11-04 10:19 ` Niklas Söderlund
2026-11-04 10:17 ` [PATCH v2 1/2] media: rppx1: Move register definitions to header Niklas Söderlund
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