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From: Jelly Jia <Jelly.Jia@cixtech.com>
To: vkoul@kernel.org, robh@kernel.org, krzk+dt@kernel.org,
	conor+dt@kernel.org, robin.murphy@arm.com
Cc: devicetree@vger.kernel.org, Frank.Li@kernel.org,
	cix-kernel-upstream@cixtech.com, dmaengine@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, Jelly.Jia@cixtech.com
Subject: [PATCH v5 0/5] dmaengine: arm-dma350: Add slave support and Sky1 integration
Date: Wed,  4 Nov 2026 20:44:06 +0800	[thread overview]
Message-ID: <20261104124411.296640-1-Jelly.Jia@cixtech.com> (raw)

Hello,

This series adds scatter-gather and cyclic slave transfer support to the
Arm DMA-350 driver, then describes the clock, reset and DMA address view
of the CIX Sky1 FCH integration.

Patch 1 fixes the source-trigger bit. Patch 2 adds peripheral transfers
with descriptor-owned resource mappings, coherent linked commands and
hardware-based residue reporting. Patches 3 and 4 document and handle
optional integration clocks and resets. Patch 5 describes the FCH DMA
address windows and adds its bus clock.

The controller nodes use arm,dma-350. The driver changes use standard
integration resources and introduce no CIX-specific register programming.
The companion AUDSS interrupt-path series builds on this one and manages
the AUDSS interrupt gates in the CRU driver.

Changes since v4:
- Allow slave configuration updates while descriptors exist, and take a
  locked configuration snapshot when preparing transfers. (Sashiko.)
- Derive cyclic residue from the hardware link pointer rather than a
  software period count. Retry changed samples and retain cached residue
  when a usable sample is not obtained. (Sashiko.)
- Stop advertising undefined bus widths; validate trigger support and
  transfer widths per channel and report per-channel capabilities.
  (Sashiko.)
- Remove the stopping flag and always poll STOPCMD during synchronization.
  Serialize IRQ status sampling, acknowledgement and descriptor selection
  under the channel lock. (Sashiko.)
- After dmaengine_terminate_async(), the DMAengine API requires clients to
  call dmaengine_synchronize() before issuing new transfers. The start path
  continues to rely on that requirement. (Sashiko.)
- Rebase onto Linux 7.4-rc1 and regenerate DTS context on the clean base.
  Keep patch 1 unchanged and retain Frank's Reviewed-by.

Link: https://lore.kernel.org/r/20261023093017.3248454-1-Jelly.Jia@cixtech.com

Signed-off-by: Jelly Jia <Jelly.Jia@cixtech.com>

Jelly Jia (5):
  dmaengine: arm-dma350: Fix source trigger bit
  dmaengine: arm-dma350: Add slave and cyclic transfer support
  dt-bindings: dma: arm,dma-350: Document optional clocks and resets
  dmaengine: arm-dma350: Support integration clocks and resets
  arm64: dts: cix: Describe the Sky1 FCH DMA-350 integration

 .../devicetree/bindings/dma/arm,dma-350.yaml  |  16 +-
 arch/arm64/boot/dts/cix/sky1.dtsi             |  36 +-
 drivers/dma/arm-dma350.c                      | 821 +++++++++++++++++-
 3 files changed, 828 insertions(+), 45 deletions(-)


base-commit: 6628e7d4c6b25c8d18f1345e3a20d21829aae7e4
-- 
2.54.0


             reply	other threads:[~2026-11-04 12:50 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-04 12:44 Jelly Jia [this message]
2026-11-04 12:44 ` [PATCH v5 1/5] dmaengine: arm-dma350: Fix source trigger bit Jelly Jia
2026-11-04 12:44 ` [PATCH v5 2/5] dmaengine: arm-dma350: Add slave and cyclic transfer support Jelly Jia
2026-11-04 12:44 ` [PATCH v5 3/5] dt-bindings: dma: arm,dma-350: Document optional clocks and resets Jelly Jia
2026-11-04 19:34   ` Frank Li
2026-11-04 12:44 ` [PATCH v5 4/5] dmaengine: arm-dma350: Support integration " Jelly Jia
2026-11-04 19:37   ` Frank Li
2026-11-04 12:44 ` [PATCH v5 5/5] arm64: dts: cix: Describe the Sky1 FCH DMA-350 integration Jelly Jia

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