* [PATCH 1/7] dt-bindings: power: st: add STM32MP PM domain binding
2026-11-04 13:55 [PATCH 0/7] arm64: dts: st: add STM32MP2 power domains Patrick Delaunay
@ 2026-11-04 13:55 ` Patrick Delaunay
2026-11-04 13:55 ` [PATCH 2/7] pmdomain: st: add STM32MP power domain Patrick Delaunay
` (5 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Patrick Delaunay @ 2026-11-04 13:55 UTC (permalink / raw)
To: Patrick Delaunay, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Maxime Coquelin, Alexandre Torgue
Cc: Linux STM32, devicetree, linux-arm-kernel, linux-kernel
Add binding documentation for the power domains found on
STMicroelectronics STM32MP SoCs.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
---
.../bindings/power/st,stm32mp-pm-domain.yaml | 46 +++++++++++++++++++
1 file changed, 46 insertions(+)
create mode 100644 Documentation/devicetree/bindings/power/st,stm32mp-pm-domain.yaml
diff --git a/Documentation/devicetree/bindings/power/st,stm32mp-pm-domain.yaml b/Documentation/devicetree/bindings/power/st,stm32mp-pm-domain.yaml
new file mode 100644
index 000000000000..4ab477fb4499
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/st,stm32mp-pm-domain.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/power/st,stm32mp-pm-domain.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: STM32MP generic power domain
+
+maintainers:
+ - Patrick Delaunay <patrick.delaunay@foss.st.com>
+
+allOf:
+ - $ref: /schemas/power/power-domain.yaml#
+
+description: |
+ The STM32MP SoCs contain a D1 domain which defines the devices assigned to
+ Cortex A cluster, the devices in this domain are functional only when this
+ cluster is not in low power modes (Stop modes) with clock OFF.
+
+ This PM domain node represents this dependency, based on PM framework and
+ without wake-up path support.
+
+properties:
+ compatible:
+ const: st,stm32mp-pm-domain
+
+ '#power-domain-cells':
+ const: 0
+
+ power-domains:
+ maxItems: 1
+
+additionalProperties: false
+
+required:
+ - compatible
+ - '#power-domain-cells'
+ - power-domains
+
+examples:
+ - |
+ power-domain-d1 {
+ compatible = "st,stm32mp-pm-domain";
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ };
--
2.43.0
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 2/7] pmdomain: st: add STM32MP power domain
2026-11-04 13:55 [PATCH 0/7] arm64: dts: st: add STM32MP2 power domains Patrick Delaunay
2026-11-04 13:55 ` [PATCH 1/7] dt-bindings: power: st: add STM32MP PM domain binding Patrick Delaunay
@ 2026-11-04 13:55 ` Patrick Delaunay
2026-11-04 13:55 ` [PATCH 3/7] MAINTAINERS: add entry for ST STM32 power domain driver Patrick Delaunay
` (4 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Patrick Delaunay @ 2026-11-04 13:55 UTC (permalink / raw)
To: Ulf Hansson, Patrick Delaunay, Maxime Coquelin, Alexandre Torgue
Cc: Linux STM32, linux-arm-kernel, linux-kernel, linux-pm
Add a generic PM domain for the STM32MP D1 domain, using the PM
framework to manage attached devices.
Make D1 a subdomain of the PSCI cluster domain, so active devices keep
the Cortex-A35 cluster in Run1. Do not set GENPD_FLAG_ACTIVE_WAKEUP on
D1: system wakeups are handled by EXTI1 through the RET_PD PSCI domain.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
---
drivers/pmdomain/st/Kconfig | 14 +++
drivers/pmdomain/st/Makefile | 1 +
drivers/pmdomain/st/stm32mp-pm-domain.c | 128 ++++++++++++++++++++++++
3 files changed, 143 insertions(+)
create mode 100644 drivers/pmdomain/st/stm32mp-pm-domain.c
diff --git a/drivers/pmdomain/st/Kconfig b/drivers/pmdomain/st/Kconfig
index a77a70211f61..da8a54d44158 100644
--- a/drivers/pmdomain/st/Kconfig
+++ b/drivers/pmdomain/st/Kconfig
@@ -1,4 +1,18 @@
# SPDX-License-Identifier: GPL-2.0-only
+
+config STM32MP_PM_DOMAIN
+ tristate "STM32MP PM domain"
+ depends on ARCH_STM32 || COMPILE_TEST
+ select PM_GENERIC_DOMAINS
+ default y
+ help
+ Enable support for the STM32MP Power Management (PM) domain driver.
+ This driver implements a generic PM domain for STM32MP SoCs, allowing
+ the kernel to manage power domains for various hardware blocks using
+ the generic power management framework. It is typically used to
+ control the power state of devices and peripherals on STM32MP
+ platforms. If unsure, say Y.
+
config UX500_PM_DOMAIN
bool "ST-Ericsson ux500 Power Domain"
depends on ARCH_U8500 || COMPILE_TEST
diff --git a/drivers/pmdomain/st/Makefile b/drivers/pmdomain/st/Makefile
index 6d8b617eb834..0e8131b7fe9d 100644
--- a/drivers/pmdomain/st/Makefile
+++ b/drivers/pmdomain/st/Makefile
@@ -1,2 +1,3 @@
# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_STM32MP_PM_DOMAIN) += stm32mp-pm-domain.o
obj-$(CONFIG_UX500_PM_DOMAIN) += ste-ux500-pm-domain.o
diff --git a/drivers/pmdomain/st/stm32mp-pm-domain.c b/drivers/pmdomain/st/stm32mp-pm-domain.c
new file mode 100644
index 000000000000..1a6393840f56
--- /dev/null
+++ b/drivers/pmdomain/st/stm32mp-pm-domain.c
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Implements PM domain using the generic PM domain for STM32MP SoC.
+ *
+ * Copyright (C) STMicroelectronics 2026
+ * Author(s): Patrick Delaunay <patrick.delaunay@foss.st.com>
+ */
+
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_runtime.h>
+
+struct stm32mp_pm_subdomain_link {
+ struct generic_pm_domain *domain;
+ struct generic_pm_domain *subdomain;
+};
+
+static void stm32mp_pm_domain_genpd_remove(void *data)
+{
+ struct generic_pm_domain *genpd = data;
+
+ pm_genpd_remove(genpd);
+}
+
+static void stm32mp_pm_domain_release_subdomain(void *data)
+{
+ struct stm32mp_pm_subdomain_link *link = data;
+
+ pm_genpd_remove_subdomain(link->domain, link->subdomain);
+}
+
+static void stm32mp_pm_domain_release_genpd_provider(void *data)
+{
+ struct device_node *np = data;
+
+ of_genpd_del_provider(np);
+}
+
+static int stm32mp_pm_domain_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ struct generic_pm_domain *pd;
+ struct stm32mp_pm_subdomain_link *link;
+ int ret;
+
+ if (!np)
+ return -ENODEV;
+
+ /* The OF node must specify us as a power-domain provider. */
+ if (!of_property_present(np, "#power-domain-cells")) {
+ dev_warn(dev, "%pOF lacks #power-domain-cells\n", np);
+ return 0;
+ }
+
+ pd = devm_kzalloc(dev, sizeof(*pd), GFP_KERNEL);
+ if (!pd)
+ return -ENOMEM;
+
+ pd->name = dev_name(dev);
+
+ /*
+ * Domain based only on PM clk framework, no GENPD_FLAG_ACTIVE_WAKEUP
+ * support, the wake-up path is handled by interrupt driver with its
+ * power domain. GENPD_FLAG_NO_STAY_ON as domain no required sync state,
+ * domain allow low power modes even if devices are not probed
+ */
+ pd->flags = GENPD_FLAG_PM_CLK | GENPD_FLAG_IRQ_SAFE | GENPD_FLAG_NO_STAY_ON;
+
+ ret = pm_genpd_init(pd, NULL, false);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to init power domain\n");
+
+ ret = devm_add_action_or_reset(dev, stm32mp_pm_domain_genpd_remove, pd);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to add action\n");
+
+ link = devm_kzalloc(dev, sizeof(*link), GFP_KERNEL);
+ if (!link)
+ return -ENOMEM;
+ link->domain = pd_to_genpd(dev->pm_domain);
+ link->subdomain = pd;
+
+ ret = pm_genpd_add_subdomain(link->domain, link->subdomain);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to add subdomain\n");
+
+ ret = devm_add_action_or_reset(dev, stm32mp_pm_domain_release_subdomain, link);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to add action\n");
+
+ ret = of_genpd_add_provider_simple(np, pd);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to add power domain provider\n");
+
+ ret = devm_add_action_or_reset(dev, stm32mp_pm_domain_release_genpd_provider, np);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to add action\n");
+
+ ret = devm_pm_runtime_enable(dev);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to enable pm-runtime\n");
+
+ return 0;
+}
+
+static const struct of_device_id stm32mp_pm_domain_matches[] = {
+ { .compatible = "st,stm32mp-pm-domain", },
+ { }
+};
+MODULE_DEVICE_TABLE(of, stm32mp_pm_domain_matches);
+
+static struct platform_driver stm32mp_pm_domain_driver = {
+ .driver = {
+ .name = "stm32mp_pm_domain",
+ .of_match_table = stm32mp_pm_domain_matches,
+ },
+ .probe = stm32mp_pm_domain_probe,
+};
+
+module_platform_driver(stm32mp_pm_domain_driver);
+
+MODULE_AUTHOR("Patrick Delaunay <patrick.delaunay@foss.st.com>");
+MODULE_DESCRIPTION("ST STM32MP power domain driver");
+MODULE_LICENSE("GPL");
--
2.43.0
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 3/7] MAINTAINERS: add entry for ST STM32 power domain driver
2026-11-04 13:55 [PATCH 0/7] arm64: dts: st: add STM32MP2 power domains Patrick Delaunay
2026-11-04 13:55 ` [PATCH 1/7] dt-bindings: power: st: add STM32MP PM domain binding Patrick Delaunay
2026-11-04 13:55 ` [PATCH 2/7] pmdomain: st: add STM32MP power domain Patrick Delaunay
@ 2026-11-04 13:55 ` Patrick Delaunay
2026-11-04 16:41 ` Patrick Delaunay
2026-11-04 13:55 ` [PATCH 4/7] arm64: dts: st: add D1 domain for STM32MP25 family Patrick Delaunay
` (3 subsequent siblings)
6 siblings, 1 reply; 9+ messages in thread
From: Patrick Delaunay @ 2026-11-04 13:55 UTC (permalink / raw)
To: nobody; +Cc: Linux STM32, Patrick Delaunay, linux-kernel
Add myself as maintainer of STM32MP power domain driver.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
---
MAINTAINERS | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 93abbb315065..8644100ca909 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -26571,6 +26571,13 @@ F: drivers/pinctrl/stm32/
F: include/dt-bindings/pinctrl/stm32-pinfunc.h
X: drivers/pinctrl/stm32/pinctrl-stm32-hdp.c
+ST STM32 POWER DOMAIN DRIVER
+M: Patrick Delaunay <patrick.delaunay@foss.st.com>
+L: linux-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers)
+S: Maintained
+F: Documentation/devicetree/bindings/power/st,stm32mp-pm-domain.yaml
+F: drivers/pmdomain/st/stm32mp-pm-domain.c
+
ST STM32 SPI DRIVER
M: Alain Volmat <alain.volmat@foss.st.com>
L: linux-spi@vger.kernel.org
--
2.43.0
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 3/7] MAINTAINERS: add entry for ST STM32 power domain driver
2026-11-04 13:55 ` [PATCH 3/7] MAINTAINERS: add entry for ST STM32 power domain driver Patrick Delaunay
@ 2026-11-04 16:41 ` Patrick Delaunay
0 siblings, 0 replies; 9+ messages in thread
From: Patrick Delaunay @ 2026-11-04 16:41 UTC (permalink / raw)
To: Alexandre Torgue; +Cc: Linux STM32, Patrick Delaunay, linux-kernel
Add myself as maintainer of STM32MP power domain driver.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
---
MAINTAINERS | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 93abbb315065..8644100ca909 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -26571,6 +26571,13 @@ F: drivers/pinctrl/stm32/
F: include/dt-bindings/pinctrl/stm32-pinfunc.h
X: drivers/pinctrl/stm32/pinctrl-stm32-hdp.c
+ST STM32 POWER DOMAIN DRIVER
+M: Patrick Delaunay <patrick.delaunay@foss.st.com>
+L: linux-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers)
+S: Maintained
+F: Documentation/devicetree/bindings/power/st,stm32mp-pm-domain.yaml
+F: drivers/pmdomain/st/stm32mp-pm-domain.c
+
ST STM32 SPI DRIVER
M: Alain Volmat <alain.volmat@foss.st.com>
L: linux-spi@vger.kernel.org
--
2.43.0
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH 4/7] arm64: dts: st: add D1 domain for STM32MP25 family
2026-11-04 13:55 [PATCH 0/7] arm64: dts: st: add STM32MP2 power domains Patrick Delaunay
` (2 preceding siblings ...)
2026-11-04 13:55 ` [PATCH 3/7] MAINTAINERS: add entry for ST STM32 power domain driver Patrick Delaunay
@ 2026-11-04 13:55 ` Patrick Delaunay
2026-11-04 13:55 ` [PATCH 5/7] arm64: dts: st: fix power-domain labels DT coding style in STM32MP25 Patrick Delaunay
` (2 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Patrick Delaunay @ 2026-11-04 13:55 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
Alexandre Torgue
Cc: Linux STM32, Patrick Delaunay, devicetree, linux-arm-kernel,
linux-kernel
Add the D1 power domain for devices that require the Cortex-A35
cluster to remain in Run1. Keep S2Idle wake-up handling on the
EXTI1/RET_PD path.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
---
arch/arm64/boot/dts/st/stm32mp251.dtsi | 110 +++++++++++++++----------
arch/arm64/boot/dts/st/stm32mp253.dtsi | 3 +-
arch/arm64/boot/dts/st/stm32mp255.dtsi | 2 +-
3 files changed, 69 insertions(+), 46 deletions(-)
diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi
index bf1542818be2..d5204d88344f 100644
--- a/arch/arm64/boot/dts/st/stm32mp251.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi
@@ -152,6 +152,12 @@ v2m0: v2m@48090000 {
};
};
+ d1_pd: power-domain-d1 {
+ compatible = "st,stm32mp-pm-domain";
+ #power-domain-cells = <0>;
+ power-domains = <&CLUSTER_PD>;
+ };
+
psci {
compatible = "arm,psci-1.0";
method = "smc";
@@ -209,6 +215,7 @@ hpdma: dma-controller@40400000 {
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scmi_clk CK_SCMI_HPDMA1>;
+ power-domains = <&RET_PD>;
#dma-cells = <3>;
};
@@ -232,6 +239,7 @@ hpdma2: dma-controller@40410000 {
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scmi_clk CK_SCMI_HPDMA2>;
+ power-domains = <&RET_PD>;
#dma-cells = <3>;
};
@@ -255,6 +263,7 @@ hpdma3: dma-controller@40420000 {
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scmi_clk CK_SCMI_HPDMA3>;
+ power-domains = <&RET_PD>;
#dma-cells = <3>;
};
@@ -273,7 +282,7 @@ ommanager: ommanager@40500000 {
<&scmi_reset RST_SCMI_OSPI2>;
reset-names = "omm", "ospi1", "ospi2";
access-controllers = <&rifsc 111>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
#address-cells = <2>;
#size-cells = <1>;
st,syscfg-amcr = <&syscfg 0x2c00 0x7>;
@@ -290,7 +299,7 @@ ospi1: spi@0 {
resets = <&scmi_reset RST_SCMI_OSPI1>,
<&scmi_reset RST_SCMI_OSPI1DLL>;
access-controllers = <&rifsc 74>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
st,syscfg-dlyb = <&syscfg 0x1000>;
status = "disabled";
};
@@ -306,7 +315,7 @@ ospi2: spi@1 {
resets = <&scmi_reset RST_SCMI_OSPI2>,
<&scmi_reset RST_SCMI_OSPI2DLL>;
access-controllers = <&rifsc 75>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
st,syscfg-dlyb = <&syscfg 0x1400>;
status = "disabled";
};
@@ -330,7 +339,7 @@ timers2: timer@40000000 {
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 1>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
status = "disabled";
counter {
@@ -361,7 +370,7 @@ timers3: timer@40010000 {
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 2>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
status = "disabled";
counter {
@@ -392,7 +401,7 @@ timers4: timer@40020000 {
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 3>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
status = "disabled";
counter {
@@ -423,7 +432,7 @@ timers5: timer@40030000 {
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 4>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
status = "disabled";
counter {
@@ -454,7 +463,7 @@ timers6: timer@40040000 {
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 5>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
status = "disabled";
counter {
@@ -479,7 +488,7 @@ timers7: timer@40050000 {
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 6>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
status = "disabled";
counter {
@@ -504,7 +513,7 @@ timers12: timer@40060000 {
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 10>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
status = "disabled";
counter {
@@ -535,7 +544,7 @@ timers13: timer@40070000 {
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 11>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
status = "disabled";
counter {
@@ -566,7 +575,7 @@ timers14: timer@40080000 {
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 12>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
status = "disabled";
counter {
@@ -686,7 +695,7 @@ spi2: spi@400b0000 {
<&hpdma 52 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 23>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -717,7 +726,7 @@ spi3: spi@400c0000 {
<&hpdma 54 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 24>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -744,6 +753,7 @@ usart2: serial@400e0000 {
<&hpdma 12 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 32>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -756,6 +766,7 @@ usart3: serial@400f0000 {
<&hpdma 14 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 33>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -768,6 +779,7 @@ uart4: serial@40100000 {
<&hpdma 16 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 34>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -780,6 +792,7 @@ uart5: serial@40110000 {
<&hpdma 18 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 35>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -796,7 +809,7 @@ i2c1: i2c@40120000 {
<&hpdma 28 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 41>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
i2c-analog-filter;
wakeup-source;
status = "disabled";
@@ -815,7 +828,7 @@ i2c2: i2c@40130000 {
<&hpdma 31 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 42>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
i2c-analog-filter;
wakeup-source;
status = "disabled";
@@ -834,7 +847,7 @@ i2c3: i2c@40140000 {
<&hpdma 34 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 43>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
i2c-analog-filter;
wakeup-source;
status = "disabled";
@@ -853,7 +866,7 @@ i2c4: i2c@40150000 {
<&hpdma 37 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 44>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
i2c-analog-filter;
wakeup-source;
status = "disabled";
@@ -872,7 +885,7 @@ i2c5: i2c@40160000 {
<&hpdma 40 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 45>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
i2c-analog-filter;
wakeup-source;
status = "disabled";
@@ -891,7 +904,7 @@ i2c6: i2c@40170000 {
<&hpdma 43 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 46>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
i2c-analog-filter;
wakeup-source;
status = "disabled";
@@ -910,7 +923,7 @@ i2c7: i2c@40180000 {
<&hpdma 46 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 47>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
i2c-analog-filter;
wakeup-source;
status = "disabled";
@@ -926,7 +939,7 @@ timers10: timer@401c0000 {
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 8>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
status = "disabled";
counter {
@@ -957,7 +970,7 @@ timers11: timer@401d0000 {
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 9>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
status = "disabled";
counter {
@@ -991,7 +1004,7 @@ timers1: timer@40200000 {
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 0>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
status = "disabled";
counter {
@@ -1025,7 +1038,7 @@ timers8: timer@40210000 {
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 7>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
status = "disabled";
counter {
@@ -1055,6 +1068,7 @@ usart6: serial@40220000 {
<&hpdma 20 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 36>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -1085,7 +1099,7 @@ spi1: spi@40230000 {
<&hpdma 50 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 22>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -1101,7 +1115,7 @@ spi4: spi@40240000 {
<&hpdma 56 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 25>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -1115,7 +1129,7 @@ timers15: timer@40250000 {
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 13>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
status = "disabled";
counter {
@@ -1146,7 +1160,7 @@ timers16: timer@40260000 {
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 14>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
status = "disabled";
counter {
@@ -1177,7 +1191,7 @@ timers17: timer@40270000 {
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 15>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
status = "disabled";
counter {
@@ -1210,7 +1224,7 @@ spi5: spi@40280000 {
<&hpdma 58 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 26>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -1325,6 +1339,7 @@ uart9: serial@402c0000 {
<&hpdma 26 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 39>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -1341,7 +1356,7 @@ timers20: timer@40320000 {
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 16>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
status = "disabled";
counter {
@@ -1371,6 +1386,7 @@ usart1: serial@40330000 {
<&hpdma 10 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 31>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -1420,7 +1436,7 @@ spi6: spi@40350000 {
<&hpdma 60 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 27>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -1436,7 +1452,7 @@ spi7: spi@40360000 {
<&hpdma 62 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 28>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -1449,6 +1465,7 @@ uart7: serial@40370000 {
<&hpdma 22 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 37>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -1461,6 +1478,7 @@ uart8: serial@40380000 {
<&hpdma 24 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 38>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -1474,7 +1492,7 @@ dcmi: dcmi@404a0000 {
dmas = <&hpdma 137 0x60 0x00003012>;
dma-names = "tx";
access-controllers = <&rifsc 88>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -1500,7 +1518,7 @@ spi8: spi@46020000 {
<&hpdma 172 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 29>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -1517,7 +1535,7 @@ i2c8: i2c@46040000 {
<&hpdma 169 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 48>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
i2c-analog-filter;
wakeup-source;
status = "disabled";
@@ -1649,7 +1667,7 @@ csi: csi@48020000 {
<&rcc CK_KER_CSIPHY>;
clock-names = "pclk", "txesc", "csi2phy";
access-controllers = <&rifsc 86>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -1661,7 +1679,7 @@ dcmipp: dcmipp@48030000 {
clocks = <&rcc CK_BUS_DCMIPP>, <&rcc CK_KER_CSI>;
clock-names = "kclk", "mclk";
access-controllers = <&rifsc 87>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -1674,7 +1692,7 @@ combophy: phy@480c0000 {
resets = <&rcc USB3PCIEPHY_R>;
reset-names = "phy";
access-controllers = <&rifsc 67>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
wakeup-source;
interrupts-extended = <&exti1 45 IRQ_TYPE_EDGE_FALLING>;
status = "disabled";
@@ -1692,7 +1710,7 @@ sdmmc1: mmc@48220000 {
cap-mmc-highspeed;
max-frequency = <120000000>;
access-controllers = <&rifsc 76>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -1708,7 +1726,7 @@ sdmmc2: mmc@48230000 {
cap-mmc-highspeed;
max-frequency = <166000000>;
access-controllers = <&rifsc 77>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -1724,6 +1742,7 @@ sdmmc3: mmc@48240000 {
cap-mmc-highspeed;
max-frequency = <166000000>;
access-controllers = <&rifsc 78>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -1753,6 +1772,7 @@ ethernet1: ethernet@482c0000 {
snps,tso;
st,syscon = <&syscfg 0x3000>;
access-controllers = <&rifsc 60>;
+ power-domains = <&d1_pd>;
status = "disabled";
mtl_rx_setup_1: rx-queues-config {
@@ -1784,6 +1804,7 @@ usbh_ohci: usb@482e0000 {
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb2_phy1>;
phy-names = "usb";
+ power-domains = <&d1_pd>;
resets = <&rcc USBH_R>;
status = "disabled";
};
@@ -1797,6 +1818,7 @@ usbh_ehci: usb@482f0000 {
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb2_phy1>;
phy-names = "usb";
+ power-domains = <&d1_pd>;
resets = <&rcc USBH_R>;
status = "disabled";
};
@@ -1828,7 +1850,7 @@ pcie_ep: pcie-ep@48400000 {
resets = <&rcc PCIE_R>;
phys = <&combophy PHY_TYPE_PCIE>;
access-controllers = <&rifsc 68>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -1854,7 +1876,7 @@ pcie_rc: pcie@48400000 {
resets = <&rcc PCIE_R>;
msi-parent = <&v2m0>;
access-controllers = <&rifsc 68>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
status = "disabled";
pcie@0,0 {
diff --git a/arch/arm64/boot/dts/st/stm32mp253.dtsi b/arch/arm64/boot/dts/st/stm32mp253.dtsi
index 19b3e55a4414..8562f13e5284 100644
--- a/arch/arm64/boot/dts/st/stm32mp253.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp253.dtsi
@@ -56,7 +56,7 @@ m_can1: can@402d0000 {
resets = <&rcc FDCAN_R>;
bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>;
access-controllers = <&rifsc 56>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -86,6 +86,7 @@ ethernet2: ethernet@482d0000 {
snps,tso;
st,syscon = <&syscfg 0x3400>;
access-controllers = <&rifsc 61>;
+ power-domains = <&d1_pd>;
status = "disabled";
mtl_rx_setup_2: rx-queues-config {
diff --git a/arch/arm64/boot/dts/st/stm32mp255.dtsi b/arch/arm64/boot/dts/st/stm32mp255.dtsi
index 7a598f53a2a0..003024eb2fc7 100644
--- a/arch/arm64/boot/dts/st/stm32mp255.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp255.dtsi
@@ -20,7 +20,7 @@ lvds: lvds@48060000 {
clock-names = "pclk", "ref";
resets = <&rcc LVDS_R>;
access-controllers = <&rifsc 84>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
--
2.43.0
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 5/7] arm64: dts: st: fix power-domain labels DT coding style in STM32MP25
2026-11-04 13:55 [PATCH 0/7] arm64: dts: st: add STM32MP2 power domains Patrick Delaunay
` (3 preceding siblings ...)
2026-11-04 13:55 ` [PATCH 4/7] arm64: dts: st: add D1 domain for STM32MP25 family Patrick Delaunay
@ 2026-11-04 13:55 ` Patrick Delaunay
2026-11-04 13:55 ` [PATCH 6/7] arm64: dts: st: add D1 domain for STM32MP23 family Patrick Delaunay
2026-11-04 13:55 ` [PATCH 7/7] arm64: dts: st: add power domains for STM32MP21 family Patrick Delaunay
6 siblings, 0 replies; 9+ messages in thread
From: Patrick Delaunay @ 2026-11-04 13:55 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
Alexandre Torgue
Cc: Linux STM32, Patrick Delaunay, devicetree, linux-arm-kernel,
linux-kernel
Update STM32MP25 power domain labels to comply with the Device Tree
coding style requirement that labels use only lowercase letters,
digits and underscore.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
---
arch/arm64/boot/dts/st/stm32mp251.dtsi | 24 ++++++++++++------------
arch/arm64/boot/dts/st/stm32mp253.dtsi | 6 +++---
2 files changed, 15 insertions(+), 15 deletions(-)
diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/st/stm32mp251.dtsi
index d5204d88344f..43b4edfa07fc 100644
--- a/arch/arm64/boot/dts/st/stm32mp251.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi
@@ -22,7 +22,7 @@ cpu0: cpu@0 {
device_type = "cpu";
reg = <0>;
enable-method = "psci";
- power-domains = <&CPU_PD0>;
+ power-domains = <&cpu0_pd>;
power-domain-names = "psci";
};
@@ -155,25 +155,25 @@ v2m0: v2m@48090000 {
d1_pd: power-domain-d1 {
compatible = "st,stm32mp-pm-domain";
#power-domain-cells = <0>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&cluster_pd>;
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
- CPU_PD0: power-domain-cpu0 {
+ cpu0_pd: power-domain-cpu0 {
#power-domain-cells = <0>;
domain-idle-states = <&cpu_sleep>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&cluster_pd>;
};
- CLUSTER_PD: power-domain-cluster {
+ cluster_pd: power-domain-cluster {
#power-domain-cells = <0>;
- power-domains = <&RET_PD>;
+ power-domains = <&ret_pd>;
};
- RET_PD: power-domain-retention {
+ ret_pd: power-domain-retention {
#power-domain-cells = <0>;
};
};
@@ -215,7 +215,7 @@ hpdma: dma-controller@40400000 {
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scmi_clk CK_SCMI_HPDMA1>;
- power-domains = <&RET_PD>;
+ power-domains = <&ret_pd>;
#dma-cells = <3>;
};
@@ -239,7 +239,7 @@ hpdma2: dma-controller@40410000 {
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scmi_clk CK_SCMI_HPDMA2>;
- power-domains = <&RET_PD>;
+ power-domains = <&ret_pd>;
#dma-cells = <3>;
};
@@ -263,7 +263,7 @@ hpdma3: dma-controller@40420000 {
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scmi_clk CK_SCMI_HPDMA3>;
- power-domains = <&RET_PD>;
+ power-domains = <&ret_pd>;
#dma-cells = <3>;
};
@@ -605,7 +605,7 @@ lptimer1: timer@40090000 {
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 17>;
- power-domains = <&RET_PD>;
+ power-domains = <&ret_pd>;
wakeup-source;
status = "disabled";
@@ -641,7 +641,7 @@ lptimer2: timer@400a0000 {
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 18>;
- power-domains = <&RET_PD>;
+ power-domains = <&ret_pd>;
wakeup-source;
status = "disabled";
diff --git a/arch/arm64/boot/dts/st/stm32mp253.dtsi b/arch/arm64/boot/dts/st/stm32mp253.dtsi
index 8562f13e5284..7df1031b7e91 100644
--- a/arch/arm64/boot/dts/st/stm32mp253.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp253.dtsi
@@ -12,7 +12,7 @@ cpu1: cpu@1 {
device_type = "cpu";
reg = <1>;
enable-method = "psci";
- power-domains = <&CPU_PD1>;
+ power-domains = <&cpu1_pd>;
power-domain-names = "psci";
};
};
@@ -24,10 +24,10 @@ arm-pmu {
};
psci {
- CPU_PD1: power-domain-cpu1 {
+ cpu1_pd: power-domain-cpu1 {
#power-domain-cells = <0>;
domain-idle-states = <&cpu_sleep>;
- power-domains = <&CLUSTER_PD>;
+ power-domains = <&cluster_pd>;
};
};
--
2.43.0
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 6/7] arm64: dts: st: add D1 domain for STM32MP23 family
2026-11-04 13:55 [PATCH 0/7] arm64: dts: st: add STM32MP2 power domains Patrick Delaunay
` (4 preceding siblings ...)
2026-11-04 13:55 ` [PATCH 5/7] arm64: dts: st: fix power-domain labels DT coding style in STM32MP25 Patrick Delaunay
@ 2026-11-04 13:55 ` Patrick Delaunay
2026-11-04 13:55 ` [PATCH 7/7] arm64: dts: st: add power domains for STM32MP21 family Patrick Delaunay
6 siblings, 0 replies; 9+ messages in thread
From: Patrick Delaunay @ 2026-11-04 13:55 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
Alexandre Torgue
Cc: Linux STM32, Patrick Delaunay, devicetree, linux-arm-kernel,
linux-kernel
Add the D1 power domain for devices that require the Cortex-A35
cluster to remain in Run1. Keep S2Idle wake-up handling on the
EXTI1/ret_pd path.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
---
arch/arm64/boot/dts/st/stm32mp231.dtsi | 54 ++++++++++++++++++--------
arch/arm64/boot/dts/st/stm32mp233.dtsi | 1 +
arch/arm64/boot/dts/st/stm32mp235.dtsi | 2 +-
3 files changed, 40 insertions(+), 17 deletions(-)
diff --git a/arch/arm64/boot/dts/st/stm32mp231.dtsi b/arch/arm64/boot/dts/st/stm32mp231.dtsi
index 27231e140fbb..4075a9cf1d36 100644
--- a/arch/arm64/boot/dts/st/stm32mp231.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp231.dtsi
@@ -130,6 +130,12 @@ scmi_vdda18adc: regulator@7 {
};
};
+ d1_pd: power-domain-d1 {
+ compatible = "st,stm32mp-pm-domain";
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ };
+
psci {
compatible = "arm,psci-1.0";
method = "smc";
@@ -187,6 +193,7 @@ hpdma: dma-controller@40400000 {
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scmi_clk CK_SCMI_HPDMA1>;
+ power-domains = <&ret_pd>;
#dma-cells = <3>;
};
@@ -210,6 +217,7 @@ hpdma2: dma-controller@40410000 {
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scmi_clk CK_SCMI_HPDMA2>;
+ power-domains = <&ret_pd>;
#dma-cells = <3>;
};
@@ -233,6 +241,7 @@ hpdma3: dma-controller@40420000 {
<GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&scmi_clk CK_SCMI_HPDMA3>;
+ power-domains = <&ret_pd>;
#dma-cells = <3>;
};
@@ -251,7 +260,7 @@ ommanager: ommanager@40500000 {
<&scmi_reset RST_SCMI_OSPI2>;
reset-names = "omm", "ospi1", "ospi2";
access-controllers = <&rifsc 111>;
- power-domains = <&cluster_pd>;
+ power-domains = <&d1_pd>;
#address-cells = <2>;
#size-cells = <1>;
st,syscfg-amcr = <&syscfg 0x2c00 0x7>;
@@ -268,7 +277,7 @@ ospi1: spi@0 {
resets = <&scmi_reset RST_SCMI_OSPI1>,
<&scmi_reset RST_SCMI_OSPI1DLL>;
access-controllers = <&rifsc 74>;
- power-domains = <&cluster_pd>;
+ power-domains = <&d1_pd>;
st,syscfg-dlyb = <&syscfg 0x1000>;
status = "disabled";
};
@@ -284,7 +293,7 @@ ospi2: spi@1 {
resets = <&scmi_reset RST_SCMI_OSPI2>,
<&scmi_reset RST_SCMI_OSPI2DLL>;
access-controllers = <&rifsc 75>;
- power-domains = <&cluster_pd>;
+ power-domains = <&d1_pd>;
st,syscfg-dlyb = <&syscfg 0x1400>;
status = "disabled";
};
@@ -325,7 +334,7 @@ spi2: spi@400b0000 {
<&hpdma 52 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 23>;
- power-domains = <&cluster_pd>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -356,7 +365,7 @@ spi3: spi@400c0000 {
<&hpdma 54 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 24>;
- power-domains = <&cluster_pd>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -383,6 +392,7 @@ usart2: serial@400e0000 {
<&hpdma 12 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 32>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -395,6 +405,7 @@ usart3: serial@400f0000 {
<&hpdma 14 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 33>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -407,6 +418,7 @@ uart4: serial@40100000 {
<&hpdma 16 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 34>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -419,6 +431,7 @@ uart5: serial@40110000 {
<&hpdma 18 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 35>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -435,7 +448,7 @@ i2c1: i2c@40120000 {
<&hpdma 28 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 41>;
- power-domains = <&cluster_pd>;
+ power-domains = <&d1_pd>;
i2c-analog-filter;
wakeup-source;
status = "disabled";
@@ -454,7 +467,7 @@ i2c2: i2c@40130000 {
<&hpdma 31 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 42>;
- power-domains = <&cluster_pd>;
+ power-domains = <&d1_pd>;
i2c-analog-filter;
wakeup-source;
status = "disabled";
@@ -473,7 +486,7 @@ i2c7: i2c@40180000 {
<&hpdma 46 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 47>;
- power-domains = <&cluster_pd>;
+ power-domains = <&d1_pd>;
i2c-analog-filter;
wakeup-source;
status = "disabled";
@@ -488,6 +501,7 @@ usart6: serial@40220000 {
<&hpdma 20 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 36>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -518,7 +532,7 @@ spi1: spi@40230000 {
<&hpdma 50 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 22>;
- power-domains = <&cluster_pd>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -534,7 +548,7 @@ spi4: spi@40240000 {
<&hpdma 56 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 25>;
- power-domains = <&cluster_pd>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -550,7 +564,7 @@ spi5: spi@40280000 {
<&hpdma 58 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 26>;
- power-domains = <&cluster_pd>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -665,6 +679,7 @@ usart1: serial@40330000 {
<&hpdma 10 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 31>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -711,6 +726,7 @@ uart7: serial@40370000 {
<&hpdma 22 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 37>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -724,7 +740,7 @@ dcmi: dcmi@404a0000 {
dmas = <&hpdma 137 0x60 0x00003012>;
dma-names = "tx";
access-controllers = <&rifsc 88>;
- power-domains = <&cluster_pd>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -750,6 +766,7 @@ spi8: spi@46020000 {
<&hpdma 172 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 29>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -766,7 +783,7 @@ i2c8: i2c@46040000 {
<&hpdma 169 0x20 0x3021>;
dma-names = "rx", "tx";
access-controllers = <&rifsc 48>;
- power-domains = <&cluster_pd>;
+ power-domains = <&d1_pd>;
i2c-analog-filter;
wakeup-source;
status = "disabled";
@@ -781,7 +798,7 @@ csi: csi@48020000 {
<&rcc CK_KER_CSIPHY>;
clock-names = "pclk", "txesc", "csi2phy";
access-controllers = <&rifsc 86>;
- power-domains = <&cluster_pd>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -793,7 +810,7 @@ dcmipp: dcmipp@48030000 {
clocks = <&rcc CK_BUS_DCMIPP>, <&rcc CK_KER_CSI>;
clock-names = "kclk", "mclk";
access-controllers = <&rifsc 87>;
- power-domains = <&cluster_pd>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -809,7 +826,7 @@ sdmmc1: mmc@48220000 {
cap-mmc-highspeed;
max-frequency = <120000000>;
access-controllers = <&rifsc 76>;
- power-domains = <&cluster_pd>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -825,6 +842,7 @@ sdmmc2: mmc@48230000 {
cap-mmc-highspeed;
max-frequency = <166000000>;
access-controllers = <&rifsc 77>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -840,6 +858,7 @@ sdmmc3: mmc@48240000 {
cap-mmc-highspeed;
max-frequency = <166000000>;
access-controllers = <&rifsc 78>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
@@ -869,6 +888,7 @@ ethernet1: ethernet@482c0000 {
snps,tso;
st,syscon = <&syscfg 0x3000>;
access-controllers = <&rifsc 60>;
+ power-domains = <&d1_pd>;
status = "disabled";
mtl_rx_setup_1: rx-queues-config {
@@ -900,6 +920,7 @@ usbh_ohci: usb@482e0000 {
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb2_phy1>;
phy-names = "usb";
+ power-domains = <&d1_pd>;
resets = <&rcc USBH_R>;
status = "disabled";
};
@@ -913,6 +934,7 @@ usbh_ehci: usb@482f0000 {
interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb2_phy1>;
phy-names = "usb";
+ power-domains = <&d1_pd>;
resets = <&rcc USBH_R>;
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/st/stm32mp233.dtsi b/arch/arm64/boot/dts/st/stm32mp233.dtsi
index cebefd99906f..3fa91f7f2762 100644
--- a/arch/arm64/boot/dts/st/stm32mp233.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp233.dtsi
@@ -70,6 +70,7 @@ ethernet2: ethernet@482d0000 {
snps,tso;
st,syscon = <&syscfg 0x3400>;
access-controllers = <&rifsc 61>;
+ power-domains = <&d1_pd>;
status = "disabled";
mtl_rx_setup_2: rx-queues-config {
diff --git a/arch/arm64/boot/dts/st/stm32mp235.dtsi b/arch/arm64/boot/dts/st/stm32mp235.dtsi
index 7a87c344a4fe..561b12ba74eb 100644
--- a/arch/arm64/boot/dts/st/stm32mp235.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp235.dtsi
@@ -20,7 +20,7 @@ lvds: lvds@48060000 {
clock-names = "pclk", "ref";
resets = <&rcc LVDS_R>;
access-controllers = <&rifsc 84>;
- power-domains = <&cluster_pd>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
--
2.43.0
^ permalink raw reply [flat|nested] 9+ messages in thread* [PATCH 7/7] arm64: dts: st: add power domains for STM32MP21 family
2026-11-04 13:55 [PATCH 0/7] arm64: dts: st: add STM32MP2 power domains Patrick Delaunay
` (5 preceding siblings ...)
2026-11-04 13:55 ` [PATCH 6/7] arm64: dts: st: add D1 domain for STM32MP23 family Patrick Delaunay
@ 2026-11-04 13:55 ` Patrick Delaunay
6 siblings, 0 replies; 9+ messages in thread
From: Patrick Delaunay @ 2026-11-04 13:55 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
Alexandre Torgue
Cc: Linux STM32, Patrick Delaunay, devicetree, linux-arm-kernel,
linux-kernel
Add the PSCI power domain for STM32MP21 family on CPU and cluster,
and the D1 power domain for devices that require the Cortex-A35
cluster to remain in Run1. The wake-up handling is only managed
by the PSCI power domain with EXTI.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
---
arch/arm64/boot/dts/st/stm32mp211.dtsi | 37 ++++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/arch/arm64/boot/dts/st/stm32mp211.dtsi b/arch/arm64/boot/dts/st/stm32mp211.dtsi
index 4bfd58b26b51..aad7c87dc8ca 100644
--- a/arch/arm64/boot/dts/st/stm32mp211.dtsi
+++ b/arch/arm64/boot/dts/st/stm32mp211.dtsi
@@ -18,6 +18,21 @@ cpu0: cpu@0 {
reg = <0>;
device_type = "cpu";
enable-method = "psci";
+ power-domains = <&cpu0_pd>;
+ power-domain-names = "psci";
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ cpu_sleep: cpu-sleep {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x00000002>;
+ local-timer-stop;
+ entry-latency-us = <150>;
+ exit-latency-us = <200>;
+ min-residency-us = <1000>;
+ };
};
};
@@ -70,9 +85,30 @@ scmi_reset: protocol@16 {
};
};
+ d1_pd: power-domain-d1 {
+ compatible = "st,stm32mp-pm-domain";
+ #power-domain-cells = <0>;
+ power-domains = <&cluster_pd>;
+ };
+
psci {
compatible = "arm,psci-1.0";
method = "smc";
+
+ cpu0_pd: power-domain-cpu0 {
+ #power-domain-cells = <0>;
+ domain-idle-states = <&cpu_sleep>;
+ power-domains = <&cluster_pd>;
+ };
+
+ cluster_pd: power-domain-cluster {
+ #power-domain-cells = <0>;
+ power-domains = <&ret_pd>;
+ };
+
+ ret_pd: power-domain-retention {
+ #power-domain-cells = <0>;
+ };
};
timer {
@@ -108,6 +144,7 @@ usart2: serial@400e0000 {
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&ck_flexgen_08>;
access-controllers = <&rifsc 32>;
+ power-domains = <&d1_pd>;
status = "disabled";
};
};
--
2.43.0
^ permalink raw reply [flat|nested] 9+ messages in thread