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* [PATCH v2 0/7] x86-32 CPU configuration cleanups
@ 2026-11-05 16:34 Arnd Bergmann
  2026-11-05 16:34 ` [PATCH 1/7] x86: remove AMD Élan remnants Arnd Bergmann
                   ` (6 more replies)
  0 siblings, 7 replies; 8+ messages in thread
From: Arnd Bergmann @ 2026-11-05 16:34 UTC (permalink / raw)
  To: Ingo Molnar
  Cc: Arnd Bergmann, Richard Weinberger, Anton Ivanov, Johannes Berg,
	Thomas Gleixner, Borislav Petkov, Dave Hansen, H. Peter Anvin,
	Peter Zijlstra, Will Deacon, Boqun Feng, Gary Guo, Yury Norov,
	Rasmus Villemoes, Boris Ostrovsky, Alexander Usyskin,
	Tony Nguyen, Przemek Kitszel, x86, linux-kernel, linux-um

From: Arnd Bergmann <arnd@arndb.de>

Hi Ingo,

Here are some follow-ups to your x86-32 CPU level changes based on
patches I did last year but rebased onto current mainline.

The first three just drop code that is no longer relevant now that Élan
is gone and all CPUs support both TSC and CX8.

The other four patches change the CPU configuration to be more like
x86-64 and other architectures where all kernels are expected to be
generic by default.  I did keep the distinction between i586 and i686
class, but everything else is now just an optimization, building e.g. for
CONFIG_MATOM will still run on all other i686 class CPUs, and picking
any i586-class option will work on everything.

Changes since v1:
 https://lore.kernel.org/all/20260522141959.1071595-1-arnd@kernel.org/

 - rebase to 7.4-rc1
 - drop ts5500 removal patch that was merged [Sean Young]
 - reorder patches for cache line size [Juergen Gross]
  
	Arnd

Arnd Bergmann (7):
  x86: remove AMD Élan remnants
  x86: make TSC usage unconditional
  x86: make CX8 usage unconditional
  x86: require minimum 64 byte cache lines
  x86: remove dependencies on CONFIG_M... CPU options
  x86: remove dependencies on per-CPU options
  x86: simplify 32-bit instruction set selection

 Documentation/virt/kvm/x86/timekeeping.rst |   1 -
 arch/um/include/asm/asm-prototypes.h       |   4 -
 arch/x86/Kconfig.cpu                       |  42 ++---
 arch/x86/Kconfig.cpufeatures               |  14 +-
 arch/x86/Makefile_32.cpu                   |  16 +-
 arch/x86/events/msr.c                      |   5 -
 arch/x86/include/asm/asm-prototypes.h      |   4 -
 arch/x86/include/asm/atomic64_32.h         |  15 --
 arch/x86/include/asm/bitops.h              |   4 +-
 arch/x86/include/asm/cmpxchg_32.h          |  76 +-------
 arch/x86/include/asm/debugreg.h            |  10 +-
 arch/x86/include/asm/percpu.h              |  14 +-
 arch/x86/include/asm/ptrace.h              |   6 +-
 arch/x86/include/asm/timex.h               |   2 -
 arch/x86/include/asm/tsc.h                 |   2 -
 arch/x86/include/asm/vermagic.h            |  36 +---
 arch/x86/kernel/apic/apic.c                |  23 +--
 arch/x86/kernel/apic/io_apic.c             |  22 +--
 arch/x86/kernel/cpu/amd.c                  |  20 ---
 arch/x86/kernel/cpu/centaur.c              |   2 -
 arch/x86/kernel/cpu/common.c               |   4 +-
 arch/x86/kernel/cpu/proc.c                 |  15 +-
 arch/x86/kernel/i8253.c                    |   3 -
 arch/x86/kernel/tsc.c                      |  18 +-
 arch/x86/lib/Makefile                      |   4 -
 arch/x86/lib/atomic64_386_32.S             | 195 ---------------------
 arch/x86/lib/cmpxchg8b_emu.S               |  97 ----------
 arch/x86/lib/kaslr.c                       |  20 +--
 arch/x86/um/Kconfig                        |   2 +-
 arch/x86/um/Makefile                       |   3 +-
 arch/x86/xen/Kconfig                       |   1 -
 arch/x86/xen/time.c                        |   2 -
 drivers/misc/mei/Kconfig                   |   2 +-
 drivers/net/ethernet/intel/igc/igc_ptp.c   |   4 +-
 drivers/ptp/Kconfig                        |   2 +-
 lib/atomic64_test.c                        |   7 +-
 tools/power/cpupower/debug/kernel/Makefile |   5 +-
 37 files changed, 72 insertions(+), 630 deletions(-)
 delete mode 100644 arch/x86/lib/atomic64_386_32.S
 delete mode 100644 arch/x86/lib/cmpxchg8b_emu.S

-- 
2.53.0

Cc: Richard Weinberger <richard@nod.at>
Cc: Anton Ivanov <anton.ivanov@cambridgegreys.com>
Cc: Johannes Berg <johannes@sipsolutions.net>
Cc: Thomas Gleixner <tglx@kernel.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will@kernel.org>
Cc: Boqun Feng <boqun@kernel.org>
Cc: Gary Guo <gary@garyguo.net>
Cc: Yury Norov <yury.norov@gmail.com>
Cc: Rasmus Villemoes <linux@rasmusvillemoes.dk>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Cc: Alexander Usyskin <alexander.usyskin@intel.com>
Cc: Tony Nguyen <anthony.l.nguyen@intel.com>
Cc: Przemek Kitszel <przemyslaw.kitszel@intel.com>
Cc: x86@kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-um@lists.infradead.org

^ permalink raw reply	[flat|nested] 8+ messages in thread
* [PATCH 1/7] x86: remove AMD Élan remnants
  2026-11-05 16:34 [PATCH v2 0/7] x86-32 CPU configuration cleanups Arnd Bergmann
@ 2026-11-05 16:34 ` Arnd Bergmann
  2026-11-05 16:34 ` [PATCH 2/7] x86: make TSC usage unconditional Arnd Bergmann
                   ` (5 subsequent siblings)
  6 siblings, 0 replies; 8+ messages in thread
From: Arnd Bergmann @ 2026-11-05 16:34 UTC (permalink / raw)
  To: Ingo Molnar
  Cc: Arnd Bergmann, Richard Weinberger, Anton Ivanov, Johannes Berg,
	Thomas Gleixner, Borislav Petkov, Dave Hansen, H. Peter Anvin,
	Peter Zijlstra, Will Deacon, Boqun Feng, Gary Guo, Yury Norov,
	Rasmus Villemoes, Boris Ostrovsky, Alexander Usyskin,
	Tony Nguyen, Przemek Kitszel, x86, linux-kernel, linux-um

From: Arnd Bergmann <arnd@arndb.de>

There is one more leftover line in Kconfig and the detection for
AMD Generation 4 CPUs (5k86 and Élan) that can now get removed
following the increase of the minimum CPU level to 586TSC.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
 arch/x86/Kconfig.cpu      |  1 -
 arch/x86/kernel/cpu/amd.c | 20 --------------------
 2 files changed, 21 deletions(-)

diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
index 6e7a366f0798..5b67a4567434 100644
--- a/arch/x86/Kconfig.cpu
+++ b/arch/x86/Kconfig.cpu
@@ -32,7 +32,6 @@ choice
 	  - "Athlon" for the AMD K7 family (Athlon/Duron/Thunderbird).
 	  - "Crusoe" for the Transmeta Crusoe series.
 	  - "Efficeon" for the Transmeta Efficeon series.
-	  - "AMD Elan" for the 32-bit AMD Elan embedded CPU.
 	  - "GeodeGX1" for Geode GX1 (Cyrix MediaGX).
 	  - "Geode GX/LX" For AMD Geode GX and LX processors.
 	  - "CyrixIII/VIA C3" for VIA Cyrix III or VIA C3.
diff --git a/arch/x86/kernel/cpu/amd.c b/arch/x86/kernel/cpu/amd.c
index 3972966cb023..cd468e47b68a 100644
--- a/arch/x86/kernel/cpu/amd.c
+++ b/arch/x86/kernel/cpu/amd.c
@@ -91,25 +91,6 @@ __asm__(".text\n"
 	"vide: ret\n");
 #endif
 
-static void init_amd_k5(struct cpuinfo_x86 *c)
-{
-#ifdef CONFIG_X86_32
-/*
- * General Systems BIOSen alias the cpu frequency registers
- * of the Elan at 0x000df000. Unfortunately, one of the Linux
- * drivers subsequently pokes it, and changes the CPU speed.
- * Workaround : Remove the unneeded alias.
- */
-#define CBAR		(0xfffc) /* Configuration Base Address  (32-bit) */
-#define CBAR_ENB	(0x80000000)
-#define CBAR_KEY	(0X000000CB)
-	if (c->x86_model == 9 || c->x86_model == 10) {
-		if (inl(CBAR) & CBAR_ENB)
-			outl(0 | CBAR_KEY, CBAR);
-	}
-#endif
-}
-
 static void init_amd_k6(struct cpuinfo_x86 *c)
 {
 #ifdef CONFIG_X86_32
@@ -1073,7 +1054,6 @@ static void init_amd(struct cpuinfo_x86 *c)
 		clear_cpu_cap(c, X86_FEATURE_MCE);
 
 	switch (c->x86) {
-	case 4:    init_amd_k5(c); break;
 	case 5:    init_amd_k6(c); break;
 	case 6:	   init_amd_k7(c); break;
 	case 0xf:  init_amd_k8(c); break;
-- 
2.53.0


^ permalink raw reply	[flat|nested] 8+ messages in thread
* [PATCH 2/7] x86: make TSC usage unconditional
  2026-11-05 16:34 [PATCH v2 0/7] x86-32 CPU configuration cleanups Arnd Bergmann
  2026-11-05 16:34 ` [PATCH 1/7] x86: remove AMD Élan remnants Arnd Bergmann
@ 2026-11-05 16:34 ` Arnd Bergmann
  2026-11-05 16:34 ` [PATCH 3/7] x86: make CX8 " Arnd Bergmann
                   ` (4 subsequent siblings)
  6 siblings, 0 replies; 8+ messages in thread
From: Arnd Bergmann @ 2026-11-05 16:34 UTC (permalink / raw)
  To: Ingo Molnar
  Cc: Arnd Bergmann, Richard Weinberger, Anton Ivanov, Johannes Berg,
	Thomas Gleixner, Borislav Petkov, Dave Hansen, H. Peter Anvin,
	Peter Zijlstra, Will Deacon, Boqun Feng, Gary Guo, Yury Norov,
	Rasmus Villemoes, Boris Ostrovsky, Alexander Usyskin,
	Tony Nguyen, Przemek Kitszel, x86, linux-kernel, linux-um

From: Arnd Bergmann <arnd@arndb.de>

There are multiple levels of functionality of the TSC that are checked
for: built into the kernel, present in the CPU, reliable and probably
more.

Since the TSC-less CPUs are no longer supported in the kernel,
remove all checks for CONFIG_TSC and X86_FEATURE_TSC and assume
it's always there. Unfortunately the tsc_clocksource_reliable
checks are still required though.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
 Documentation/virt/kvm/x86/timekeeping.rst |  1 -
 arch/x86/Kconfig.cpu                       |  3 ---
 arch/x86/events/msr.c                      |  5 -----
 arch/x86/include/asm/timex.h               |  2 --
 arch/x86/include/asm/tsc.h                 |  2 --
 arch/x86/kernel/apic/apic.c                | 23 +++++++++-------------
 arch/x86/kernel/apic/io_apic.c             | 22 +--------------------
 arch/x86/kernel/cpu/centaur.c              |  2 --
 arch/x86/kernel/cpu/common.c               |  4 +---
 arch/x86/kernel/cpu/proc.c                 | 15 ++++++--------
 arch/x86/kernel/i8253.c                    |  3 ---
 arch/x86/kernel/tsc.c                      | 16 ++-------------
 arch/x86/lib/kaslr.c                       | 20 ++++---------------
 arch/x86/xen/time.c                        |  2 --
 drivers/net/ethernet/intel/igc/igc_ptp.c   |  4 ++--
 drivers/ptp/Kconfig                        |  2 +-
 tools/power/cpupower/debug/kernel/Makefile |  5 +----
 17 files changed, 27 insertions(+), 104 deletions(-)

diff --git a/Documentation/virt/kvm/x86/timekeeping.rst b/Documentation/virt/kvm/x86/timekeeping.rst
index 21ae7efa29ba..e8519451000d 100644
--- a/Documentation/virt/kvm/x86/timekeeping.rst
+++ b/Documentation/virt/kvm/x86/timekeeping.rst
@@ -471,7 +471,6 @@ The following feature bits are used by Linux to signal various TSC attributes,
 but they can only be taken to be meaningful for UP or single node systems.
 
 =========================	=======================================
-X86_FEATURE_TSC			The TSC is available in hardware
 X86_FEATURE_RDTSCP		The RDTSCP instruction is available
 X86_FEATURE_CONSTANT_TSC	The TSC rate is unchanged with P-states
 X86_FEATURE_NONSTOP_TSC		The TSC does not stop in C-states
diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
index 5b67a4567434..f2c1f544f5f9 100644
--- a/arch/x86/Kconfig.cpu
+++ b/arch/x86/Kconfig.cpu
@@ -270,9 +270,6 @@ config X86_USE_PPRO_CHECKSUM
 	def_bool y
 	depends on MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MEFFICEON || MGEODE_LX || MATOM
 
-config X86_TSC
-	def_bool y
-
 config X86_HAVE_PAE
 	def_bool y
 	depends on MCRUSOE || MEFFICEON || MCYRIXIII || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC7 || MATOM || X86_64
diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c
index 76d6418c5055..130f1a8c8800 100644
--- a/arch/x86/events/msr.c
+++ b/arch/x86/events/msr.c
@@ -229,11 +229,6 @@ static struct pmu pmu_msr = {
 
 static int __init msr_init(void)
 {
-	if (!boot_cpu_has(X86_FEATURE_TSC)) {
-		pr_cont("no MSR PMU driver.\n");
-		return 0;
-	}
-
 	msr_mask = perf_msr_probe(msr, PERF_MSR_EVENT_MAX, true, NULL);
 
 	perf_pmu_register(&pmu_msr, "msr", -1);
diff --git a/arch/x86/include/asm/timex.h b/arch/x86/include/asm/timex.h
index f397072cf294..a4770765b34d 100644
--- a/arch/x86/include/asm/timex.h
+++ b/arch/x86/include/asm/timex.h
@@ -7,8 +7,6 @@
 
 static inline unsigned long random_get_entropy(void)
 {
-	if (!cpu_feature_enabled(X86_FEATURE_TSC))
-		return random_get_entropy_fallback();
 	return rdtsc();
 }
 #define random_get_entropy random_get_entropy
diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h
index 4d2d2f21ff06..88d9d2a22152 100644
--- a/arch/x86/include/asm/tsc.h
+++ b/arch/x86/include/asm/tsc.h
@@ -76,8 +76,6 @@ extern void disable_TSC(void);
 
 static inline cycles_t get_cycles(void)
 {
-	if (!cpu_feature_enabled(X86_FEATURE_TSC))
-		return 0;
 	return rdtsc();
 }
 #define get_cycles get_cycles
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 90025451ace2..31c890618762 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -666,8 +666,7 @@ static void __init lapic_cal_handler(struct clock_event_device *dev)
 	long tapic = apic_read(APIC_TMCCT);
 	u32 pm = acpi_pm_read_early();
 
-	if (boot_cpu_has(X86_FEATURE_TSC))
-		tsc = rdtsc();
+	tsc = rdtsc();
 
 	switch (lapic_cal_loops++) {
 	case 0:
@@ -727,13 +726,11 @@ calibrate_by_pmtimer(u32 deltapm, long *delta, long *deltatsc)
 	*delta = (long)res;
 
 	/* Correct the tsc counter value */
-	if (boot_cpu_has(X86_FEATURE_TSC)) {
-		res = (((u64)(*deltatsc)) * pm_100ms);
-		do_div(res, deltapm);
-		apic_pr_verbose("TSC delta adjusted to PM-Timer: %lu (%ld)\n",
-				(unsigned long)res, *deltatsc);
-		*deltatsc = (long)res;
-	}
+	res = (((u64)(*deltatsc)) * pm_100ms);
+	do_div(res, deltapm);
+	apic_pr_verbose("TSC delta adjusted to PM-Timer: %lu (%ld)\n",
+			(unsigned long)res, *deltatsc);
+	*deltatsc = (long)res;
 
 	return 0;
 }
@@ -902,12 +899,10 @@ static int __init calibrate_APIC_clock(void)
 	apic_pr_verbose("..... mult: %u\n", lapic_clockevent.mult);
 	apic_pr_verbose("..... calibration result: %u\n", lapic_timer_period);
 
-	if (boot_cpu_has(X86_FEATURE_TSC)) {
-		delta_tsc_khz = (deltatsc * HZ) / (1000 * LAPIC_CAL_LOOPS);
+	delta_tsc_khz = (deltatsc * HZ) / (1000 * LAPIC_CAL_LOOPS);
 
-		apic_pr_verbose("..... CPU clock speed is %ld.%03ld MHz.\n",
-				delta_tsc_khz / 1000, delta_tsc_khz % 1000);
-	}
+	apic_pr_verbose("..... CPU clock speed is %ld.%03ld MHz.\n",
+			delta_tsc_khz / 1000, delta_tsc_khz % 1000);
 
 	bus_khz = (long)lapic_timer_period * HZ / 1000;
 	apic_pr_verbose("..... host bus clock speed is %ld.%03ld MHz.\n",
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index 7d7175d01228..b3c5ff599fda 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -1491,23 +1491,6 @@ static void __init delay_with_tsc(void)
 	} while ((now - start) < 40000000000ULL / HZ &&	time_before_eq(jiffies, end));
 }
 
-static void __init delay_without_tsc(void)
-{
-	unsigned long end = jiffies + 4;
-	int band = 1;
-
-	/*
-	 * We don't know any frequency yet, but waiting for
-	 * 40940000000/HZ cycles is safe:
-	 * 4 GHz == 10 jiffies
-	 * 1 GHz == 40 jiffies
-	 * 1 << 1 + 1 << 2 +...+ 1 << 11 = 4094
-	 */
-	do {
-		__delay(((1U << band++) * 10000000UL) / HZ);
-	} while (band < 12 && time_before_eq(jiffies, end));
-}
-
 /*
  * There is a nasty bug in some older SMP boards, their mptable lies
  * about the timer IRQ. We do the following to work around the situation:
@@ -1524,10 +1507,7 @@ static int __init timer_irq_works(void)
 		return 1;
 
 	local_irq_enable();
-	if (boot_cpu_has(X86_FEATURE_TSC))
-		delay_with_tsc();
-	else
-		delay_without_tsc();
+	delay_with_tsc();
 
 	/*
 	 * Expect a few ticks at least, to be sure some possible
diff --git a/arch/x86/kernel/cpu/centaur.c b/arch/x86/kernel/cpu/centaur.c
index 513fa1f640f9..f66ca8335af9 100644
--- a/arch/x86/kernel/cpu/centaur.c
+++ b/arch/x86/kernel/cpu/centaur.c
@@ -140,8 +140,6 @@ static void init_centaur(struct cpuinfo_x86 *c)
 			name = "C6";
 			fcr_set = ECX8|DSMC|EDCTLB|EMMX|ERETSTK;
 			fcr_clr = DPDC;
-			pr_notice("Disabling bugged TSC.\n");
-			clear_cpu_cap(c, X86_FEATURE_TSC);
 			break;
 		case 8:
 			switch (c->x86_stepping) {
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 9bd50c68cd7e..355bcbfdf2dd 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -2478,9 +2478,7 @@ void cpu_init(void)
 #endif
 	pr_debug("Initializing CPU#%d\n", cpu);
 
-	if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) ||
-	    boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE))
-		cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
+	cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
 
 	if (IS_ENABLED(CONFIG_X86_64)) {
 		loadsegment(fs, 0);
diff --git a/arch/x86/kernel/cpu/proc.c b/arch/x86/kernel/cpu/proc.c
index 6571d432cbe3..8086c39c2922 100644
--- a/arch/x86/kernel/cpu/proc.c
+++ b/arch/x86/kernel/cpu/proc.c
@@ -64,7 +64,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
 {
 	struct cpuinfo_x86 *c = v;
 	unsigned int cpu;
-	int i;
+	int freq, i;
 
 	cpu = c->cpu_index;
 	seq_printf(m, "processor\t: %u\n"
@@ -85,14 +85,11 @@ static int show_cpuinfo(struct seq_file *m, void *v)
 	if (c->microcode)
 		seq_printf(m, "microcode\t: 0x%x\n", c->microcode);
 
-	if (cpu_has(c, X86_FEATURE_TSC)) {
-		int freq = arch_freq_get_on_cpu(cpu);
-
-		if (freq < 0)
-			seq_puts(m, "cpu MHz\t\t: Unknown\n");
-		else
-			seq_printf(m, "cpu MHz\t\t: %u.%03u\n", freq / 1000, (freq % 1000));
-	}
+	freq = arch_freq_get_on_cpu(cpu);
+	if (freq < 0)
+		seq_puts(m, "cpu MHz\t\t: Unknown\n");
+	else
+		seq_printf(m, "cpu MHz\t\t: %u.%03u\n", freq / 1000, (freq % 1000));
 
 	/* Cache size */
 	if (c->x86_cache_size)
diff --git a/arch/x86/kernel/i8253.c b/arch/x86/kernel/i8253.c
index 0b991035f127..0c91426e4a08 100644
--- a/arch/x86/kernel/i8253.c
+++ b/arch/x86/kernel/i8253.c
@@ -31,9 +31,6 @@ struct clock_event_device *global_clock_event;
  */
 static bool __init use_pit(void)
 {
-	if (!boot_cpu_has(X86_FEATURE_TSC))
-		return true;
-
 	/* This also returns true when APIC is disabled */
 	return apic_needs_pit();
 }
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index 723347e2cf7f..02269dcbde1f 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -929,9 +929,6 @@ void recalibrate_cpu_khz(void)
 #ifndef CONFIG_SMP
 	unsigned long cpu_khz_old = cpu_khz;
 
-	if (!boot_cpu_has(X86_FEATURE_TSC))
-		return;
-
 	cpu_khz = x86_platform.calibrate_cpu();
 	tsc_khz = x86_platform.calibrate_tsc();
 	if (tsc_khz == 0)
@@ -1046,8 +1043,6 @@ static struct notifier_block time_cpufreq_notifier_block = {
 
 static int __init cpufreq_register_tsc_scaling(void)
 {
-	if (!boot_cpu_has(X86_FEATURE_TSC))
-		return 0;
 	if (boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
 		return 0;
 	cpufreq_register_notifier(&time_cpufreq_notifier_block,
@@ -1253,7 +1248,7 @@ static void __init check_system_tsc_reliable(void)
  */
 int unsynchronized_tsc(void)
 {
-	if (!boot_cpu_has(X86_FEATURE_TSC) || tsc_unstable)
+	if (tsc_unstable)
 		return 1;
 
 #ifdef CONFIG_SMP
@@ -1403,7 +1398,7 @@ static void tsc_refine_calibration_work(struct work_struct *work)
 
 static int __init init_tsc_clocksource(void)
 {
-	if (!boot_cpu_has(X86_FEATURE_TSC) || !tsc_khz)
+	if (!tsc_khz)
 		return 0;
 
 	if (tsc_unstable) {
@@ -1502,8 +1497,6 @@ static void __init tsc_enable_sched_clock(void)
 
 void __init tsc_early_init(void)
 {
-	if (!boot_cpu_has(X86_FEATURE_TSC))
-		return;
 	/* Don't change UV TSC multi-chassis synchronization */
 	if (is_early_uv_system())
 		return;
@@ -1517,11 +1510,6 @@ void __init tsc_early_init(void)
 
 void __init tsc_init(void)
 {
-	if (!cpu_feature_enabled(X86_FEATURE_TSC)) {
-		setup_clear_cpu_cap(X86_FEATURE_TSC_DEADLINE_TIMER);
-		return;
-	}
-
 	/*
 	 * native_calibrate_cpu_early can only calibrate using methods that are
 	 * available early in boot.
diff --git a/arch/x86/lib/kaslr.c b/arch/x86/lib/kaslr.c
index 8c7cd115b484..9984eeeb1a7c 100644
--- a/arch/x86/lib/kaslr.c
+++ b/arch/x86/lib/kaslr.c
@@ -54,7 +54,6 @@ unsigned long kaslr_get_random_long(const char *purpose)
 	const unsigned long mix_const = 0x3f39e593UL;
 #endif
 	unsigned long raw, random = get_boot_seed();
-	bool use_i8254 = true;
 
 	if (purpose) {
 		debug_putstr(purpose);
@@ -66,24 +65,13 @@ unsigned long kaslr_get_random_long(const char *purpose)
 			debug_putstr(" RDRAND");
 		if (rdrand_long(&raw)) {
 			random ^= raw;
-			use_i8254 = false;
 		}
 	}
 
-	if (has_cpuflag(X86_FEATURE_TSC)) {
-		if (purpose)
-			debug_putstr(" RDTSC");
-		raw = rdtsc();
-
-		random ^= raw;
-		use_i8254 = false;
-	}
-
-	if (use_i8254) {
-		if (purpose)
-			debug_putstr(" i8254");
-		random ^= i8254();
-	}
+	if (purpose)
+		debug_putstr(" RDTSC");
+	raw = rdtsc();
+	random ^= raw;
 
 	/* Circular multiply for better bit diffusion */
 	asm(_ASM_MUL "%3"
diff --git a/arch/x86/xen/time.c b/arch/x86/xen/time.c
index 5c7822254a01..b29c94bfce35 100644
--- a/arch/x86/xen/time.c
+++ b/arch/x86/xen/time.c
@@ -541,8 +541,6 @@ static void __init xen_time_init(void)
 	xen_read_wallclock(&tp);
 	do_settimeofday64(&tp);
 
-	setup_force_cpu_cap(X86_FEATURE_TSC);
-
 	/*
 	 * We check ahead on the primary time info if this
 	 * bit is supported hence speeding up Xen clocksource.
diff --git a/drivers/net/ethernet/intel/igc/igc_ptp.c b/drivers/net/ethernet/intel/igc/igc_ptp.c
index b40aba9ab685..3736bd800a5d 100644
--- a/drivers/net/ethernet/intel/igc/igc_ptp.c
+++ b/drivers/net/ethernet/intel/igc/igc_ptp.c
@@ -947,7 +947,7 @@ int igc_ptp_hwtstamp_get(struct net_device *netdev,
  */
 static bool igc_is_crosststamp_supported(struct igc_adapter *adapter)
 {
-	if (!IS_ENABLED(CONFIG_X86_TSC))
+	if (!IS_ENABLED(CONFIG_X86))
 		return false;
 
 	/* FIXME: it was noticed that enabling support for PCIe PTM in
@@ -965,7 +965,7 @@ static bool igc_is_crosststamp_supported(struct igc_adapter *adapter)
 
 static struct system_counterval_t igc_device_tstamp_to_system(u64 tstamp)
 {
-#if IS_ENABLED(CONFIG_X86_TSC) && !defined(CONFIG_UML)
+#if IS_ENABLED(CONFIG_X86) && !defined(CONFIG_UML)
 	return (struct system_counterval_t) {
 		.cs_id		= CSID_X86_ART,
 		.cycles		= tstamp,
diff --git a/drivers/ptp/Kconfig b/drivers/ptp/Kconfig
index feb50f8cc406..52845a1de7fa 100644
--- a/drivers/ptp/Kconfig
+++ b/drivers/ptp/Kconfig
@@ -134,7 +134,7 @@ config PTP_1588_CLOCK_KVM
 
 config PTP_1588_CLOCK_VMCLOCK
 	tristate "Virtual machine PTP clock"
-	depends on X86_TSC || ARM_ARCH_TIMER
+	depends on X86 || ARM_ARCH_TIMER
 	depends on PTP_1588_CLOCK && ARCH_SUPPORTS_INT128
 	default PTP_1588_CLOCK_KVM
 	help
diff --git a/tools/power/cpupower/debug/kernel/Makefile b/tools/power/cpupower/debug/kernel/Makefile
index 7b5c43684be1..89954bba1453 100644
--- a/tools/power/cpupower/debug/kernel/Makefile
+++ b/tools/power/cpupower/debug/kernel/Makefile
@@ -1,12 +1,9 @@
 # SPDX-License-Identifier: GPL-2.0
-obj-m	:=
+obj-m	:= cpufreq-test_tsc.o
 
 KDIR	:= /lib/modules/$(shell uname -r)/build
 KMISC   := /lib/modules/$(shell uname -r)/cpufrequtils/
 
-ifeq ("$(CONFIG_X86_TSC)", "y")
-  obj-m	 += cpufreq-test_tsc.o
-endif
 
 default:
 	$(MAKE) -C $(KDIR) M=$(CURDIR)
-- 
2.53.0


^ permalink raw reply	[flat|nested] 8+ messages in thread
* [PATCH 3/7] x86: make CX8 usage unconditional
  2026-11-05 16:34 [PATCH v2 0/7] x86-32 CPU configuration cleanups Arnd Bergmann
  2026-11-05 16:34 ` [PATCH 1/7] x86: remove AMD Élan remnants Arnd Bergmann
  2026-11-05 16:34 ` [PATCH 2/7] x86: make TSC usage unconditional Arnd Bergmann
@ 2026-11-05 16:34 ` Arnd Bergmann
  2026-11-05 16:34 ` [PATCH 4/7] x86: require minimum 64 byte cache lines Arnd Bergmann
                   ` (3 subsequent siblings)
  6 siblings, 0 replies; 8+ messages in thread
From: Arnd Bergmann @ 2026-11-05 16:34 UTC (permalink / raw)
  To: Ingo Molnar
  Cc: Arnd Bergmann, Richard Weinberger, Anton Ivanov, Johannes Berg,
	Thomas Gleixner, Borislav Petkov, Dave Hansen, H. Peter Anvin,
	Peter Zijlstra, Will Deacon, Boqun Feng, Gary Guo, Yury Norov,
	Rasmus Villemoes, Boris Ostrovsky, Alexander Usyskin,
	Tony Nguyen, Przemek Kitszel, x86, linux-kernel, linux-um

From: Arnd Bergmann <arnd@arndb.de>

All supported CPUs now provide the cmpxchg8b instruction, so remove
all compile-time and runtime checks for its presence and the fallback
implementation, to assume it just works.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
 arch/um/include/asm/asm-prototypes.h  |   4 -
 arch/x86/Kconfig.cpu                  |   3 -
 arch/x86/Kconfig.cpufeatures          |   6 +-
 arch/x86/include/asm/asm-prototypes.h |   4 -
 arch/x86/include/asm/atomic64_32.h    |  15 --
 arch/x86/include/asm/cmpxchg_32.h     |  76 +---------
 arch/x86/include/asm/percpu.h         |  14 +-
 arch/x86/lib/Makefile                 |   4 -
 arch/x86/lib/atomic64_386_32.S        | 195 --------------------------
 arch/x86/lib/cmpxchg8b_emu.S          |  97 -------------
 arch/x86/um/Kconfig                   |   2 +-
 arch/x86/um/Makefile                  |   3 +-
 lib/atomic64_test.c                   |   7 +-
 13 files changed, 13 insertions(+), 417 deletions(-)
 delete mode 100644 arch/x86/lib/atomic64_386_32.S
 delete mode 100644 arch/x86/lib/cmpxchg8b_emu.S

diff --git a/arch/um/include/asm/asm-prototypes.h b/arch/um/include/asm/asm-prototypes.h
index 408b31d59127..b446eec98ed8 100644
--- a/arch/um/include/asm/asm-prototypes.h
+++ b/arch/um/include/asm/asm-prototypes.h
@@ -1,6 +1,2 @@
 #include <asm-generic/asm-prototypes.h>
 #include <asm/checksum.h>
-
-#ifdef CONFIG_UML_X86
-extern void cmpxchg8b_emu(void);
-#endif
diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
index f2c1f544f5f9..832e4bd9f6e0 100644
--- a/arch/x86/Kconfig.cpu
+++ b/arch/x86/Kconfig.cpu
@@ -274,9 +274,6 @@ config X86_HAVE_PAE
 	def_bool y
 	depends on MCRUSOE || MEFFICEON || MCYRIXIII || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC7 || MATOM || X86_64
 
-config X86_CX8
-	def_bool y
-
 # this should be set for all -march=.. options where the compiler
 # generates cmov.
 config X86_CMOV
diff --git a/arch/x86/Kconfig.cpufeatures b/arch/x86/Kconfig.cpufeatures
index 09833c88f9ff..e0f2ff65377d 100644
--- a/arch/x86/Kconfig.cpufeatures
+++ b/arch/x86/Kconfig.cpufeatures
@@ -40,9 +40,6 @@ config X86_REQUIRED_FEATURE_NOPL
 	def_bool y
 	depends on X86_64
 
-config X86_REQUIRED_FEATURE_CX8
-	def_bool y
-
 # this should be set for all -march=.. options where the compiler
 # generates cmov.
 config X86_REQUIRED_FEATURE_CMOV
@@ -59,6 +56,9 @@ config X86_REQUIRED_FEATURE_SYSFAST32
 	def_bool y
 	depends on X86_64 && !X86_FRED
 
+config X86_REQUIRED_FEATURE_CX8
+	def_bool y
+
 config X86_REQUIRED_FEATURE_CPUID
 	def_bool y
 	depends on X86_64
diff --git a/arch/x86/include/asm/asm-prototypes.h b/arch/x86/include/asm/asm-prototypes.h
index 11c6fecc3ad7..6ec680a36dea 100644
--- a/arch/x86/include/asm/asm-prototypes.h
+++ b/arch/x86/include/asm/asm-prototypes.h
@@ -16,10 +16,6 @@
 #include <asm/gsseg.h>
 #include <asm/nospec-branch.h>
 
-#ifndef CONFIG_X86_CX8
-extern void cmpxchg8b_emu(void);
-#endif
-
 #ifdef CONFIG_STACKPROTECTOR
 extern unsigned long __ref_stack_chk_guard;
 #endif
diff --git a/arch/x86/include/asm/atomic64_32.h b/arch/x86/include/asm/atomic64_32.h
index ab838205c1c6..e3da5d0094c4 100644
--- a/arch/x86/include/asm/atomic64_32.h
+++ b/arch/x86/include/asm/atomic64_32.h
@@ -48,7 +48,6 @@ static __always_inline s64 arch_atomic64_read_nonatomic(const atomic64_t *v)
 	ATOMIC64_EXPORT(atomic64_##sym)
 #endif
 
-#ifdef CONFIG_X86_CX8
 #define __alternative_atomic64(f, g, out, in, clobbers...)		\
 	asm volatile("call %c[func]"					\
 		     : ALT_OUTPUT_SP(out) \
@@ -57,20 +56,6 @@ static __always_inline s64 arch_atomic64_read_nonatomic(const atomic64_t *v)
 		     : clobbers)
 
 #define ATOMIC64_DECL(sym) ATOMIC64_DECL_ONE(sym##_cx8)
-#else
-#define __alternative_atomic64(f, g, out, in, clobbers...)		\
-	alternative_call(atomic64_##f##_386, atomic64_##g##_cx8,	\
-			 X86_FEATURE_CX8, ASM_OUTPUT(out),		\
-			 ASM_INPUT(in), clobbers)
-
-#define ATOMIC64_DECL(sym) ATOMIC64_DECL_ONE(sym##_cx8); \
-	ATOMIC64_DECL_ONE(sym##_386)
-
-ATOMIC64_DECL_ONE(add_386);
-ATOMIC64_DECL_ONE(sub_386);
-ATOMIC64_DECL_ONE(inc_386);
-ATOMIC64_DECL_ONE(dec_386);
-#endif
 
 #define alternative_atomic64(f, out, in, clobbers...) \
 	__alternative_atomic64(f, f, ASM_OUTPUT(out), ASM_INPUT(in), clobbers)
diff --git a/arch/x86/include/asm/cmpxchg_32.h b/arch/x86/include/asm/cmpxchg_32.h
index e85c221ed1c9..1019c4bce620 100644
--- a/arch/x86/include/asm/cmpxchg_32.h
+++ b/arch/x86/include/asm/cmpxchg_32.h
@@ -68,8 +68,6 @@ static __always_inline bool __try_cmpxchg64_local(volatile u64 *ptr, u64 *oldp,
 	return __arch_try_cmpxchg64(ptr, oldp, new,);
 }
 
-#ifdef CONFIG_X86_CX8
-
 #define arch_cmpxchg64 __cmpxchg64
 
 #define arch_cmpxchg64_local __cmpxchg64_local
@@ -78,78 +76,6 @@ static __always_inline bool __try_cmpxchg64_local(volatile u64 *ptr, u64 *oldp,
 
 #define arch_try_cmpxchg64_local __try_cmpxchg64_local
 
-#else
-
-/*
- * Building a kernel capable running on 80386 and 80486. It may be necessary
- * to simulate the cmpxchg8b on the 80386 and 80486 CPU.
- */
-
-#define __arch_cmpxchg64_emu(_ptr, _old, _new, _lock_loc, _lock)	\
-({									\
-	union __u64_halves o = { .full = (_old), },			\
-			   n = { .full = (_new), };			\
-									\
-	asm_inline volatile(						\
-		ALTERNATIVE(_lock_loc					\
-			    "call cmpxchg8b_emu",			\
-			    _lock "cmpxchg8b %a[ptr]", X86_FEATURE_CX8)	\
-		: ALT_OUTPUT_SP("+a" (o.low), "+d" (o.high))		\
-		: "b" (n.low), "c" (n.high),				\
-		  [ptr] "S" (_ptr)					\
-		: "memory");						\
-									\
-	o.full;								\
-})
-
-static __always_inline u64 arch_cmpxchg64(volatile u64 *ptr, u64 old, u64 new)
-{
-	return __arch_cmpxchg64_emu(ptr, old, new, , "lock ");
-}
-#define arch_cmpxchg64 arch_cmpxchg64
-
-static __always_inline u64 arch_cmpxchg64_local(volatile u64 *ptr, u64 old, u64 new)
-{
-	return __arch_cmpxchg64_emu(ptr, old, new, ,);
-}
-#define arch_cmpxchg64_local arch_cmpxchg64_local
-
-#define __arch_try_cmpxchg64_emu(_ptr, _oldp, _new, _lock_loc, _lock)	\
-({									\
-	union __u64_halves o = { .full = *(_oldp), },			\
-			   n = { .full = (_new), };			\
-	bool ret;							\
-									\
-	asm_inline volatile(						\
-		ALTERNATIVE(_lock_loc					\
-			    "call cmpxchg8b_emu",			\
-			    _lock "cmpxchg8b %a[ptr]", X86_FEATURE_CX8) \
-		: ALT_OUTPUT_SP("=@ccz" (ret),				\
-				"+a" (o.low), "+d" (o.high))		\
-		: "b" (n.low), "c" (n.high),				\
-		  [ptr] "S" (_ptr)					\
-		: "memory");						\
-									\
-	if (unlikely(!ret))						\
-		*(_oldp) = o.full;					\
-									\
-	likely(ret);							\
-})
-
-static __always_inline bool arch_try_cmpxchg64(volatile u64 *ptr, u64 *oldp, u64 new)
-{
-	return __arch_try_cmpxchg64_emu(ptr, oldp, new, , "lock ");
-}
-#define arch_try_cmpxchg64 arch_try_cmpxchg64
-
-static __always_inline bool arch_try_cmpxchg64_local(volatile u64 *ptr, u64 *oldp, u64 new)
-{
-	return __arch_try_cmpxchg64_emu(ptr, oldp, new, ,);
-}
-#define arch_try_cmpxchg64_local arch_try_cmpxchg64_local
-
-#endif
-
-#define system_has_cmpxchg64()		boot_cpu_has(X86_FEATURE_CX8)
+#define system_has_cmpxchg64()		true
 
 #endif /* _ASM_X86_CMPXCHG_32_H */
diff --git a/arch/x86/include/asm/percpu.h b/arch/x86/include/asm/percpu.h
index cef9a4ca9841..539abf94828d 100644
--- a/arch/x86/include/asm/percpu.h
+++ b/arch/x86/include/asm/percpu.h
@@ -330,11 +330,9 @@ do {									\
 	old__.var = _oval;						\
 	new__.var = _nval;						\
 									\
-	asm_inline qual (						\
-		ALTERNATIVE("call this_cpu_cmpxchg8b_emu",		\
-			    "cmpxchg8b " __percpu_arg([var]), X86_FEATURE_CX8) \
-		: ALT_OUTPUT_SP([var] "+m" (__my_cpu_var(_var)),	\
-				"+a" (old__.low), "+d" (old__.high))	\
+	asm_inline qual ("cmpxchg8b " __percpu_arg([var])		\
+		: [var] "+m" (__my_cpu_var(_var)),			\
+				"+a" (old__.low), "+d" (old__.high)	\
 		: "b" (new__.low), "c" (new__.high),			\
 		  "S" (&(_var))						\
 		: "memory");						\
@@ -359,10 +357,8 @@ do {									\
 	old__.var = *_oval;						\
 	new__.var = _nval;						\
 									\
-	asm_inline qual (						\
-		ALTERNATIVE("call this_cpu_cmpxchg8b_emu",		\
-			    "cmpxchg8b " __percpu_arg([var]), X86_FEATURE_CX8) \
-		: ALT_OUTPUT_SP("=@ccz" (success),			\
+	asm_inline qual ("cmpxchg8b " __percpu_arg([var])		\
+		: "=@ccz" (success),					\
 				[var] "+m" (__my_cpu_var(_var)),	\
 				"+a" (old__.low), "+d" (old__.high))	\
 		: "b" (new__.low), "c" (new__.high),			\
diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile
index 2dba7f83ef97..210af275f468 100644
--- a/arch/x86/lib/Makefile
+++ b/arch/x86/lib/Makefile
@@ -48,10 +48,6 @@ ifeq ($(CONFIG_X86_32),y)
         lib-y += strstr_32.o
         lib-y += string_32.o
         lib-y += memmove_32.o
-        lib-y += cmpxchg8b_emu.o
-ifneq ($(CONFIG_X86_CX8),y)
-        lib-y += atomic64_386_32.o
-endif
 else
 ifneq ($(CONFIG_GENERIC_CSUM),y)
         lib-y += csum-partial_64.o csum-copy_64.o csum-wrappers_64.o
diff --git a/arch/x86/lib/atomic64_386_32.S b/arch/x86/lib/atomic64_386_32.S
deleted file mode 100644
index e768815e58ae..000000000000
--- a/arch/x86/lib/atomic64_386_32.S
+++ /dev/null
@@ -1,195 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * atomic64_t for 386/486
- *
- * Copyright © 2010  Luca Barbieri
- */
-
-#include <linux/linkage.h>
-#include <asm/alternative.h>
-
-/* if you want SMP support, implement these with real spinlocks */
-.macro IRQ_SAVE reg
-	pushfl
-	cli
-.endm
-
-.macro IRQ_RESTORE reg
-	popfl
-.endm
-
-#define BEGIN_IRQ_SAVE(op) \
-.macro endp; \
-SYM_FUNC_END(atomic64_##op##_386); \
-.purgem endp; \
-.endm; \
-SYM_FUNC_START(atomic64_##op##_386); \
-	IRQ_SAVE v;
-
-#define ENDP endp
-
-#define RET_IRQ_RESTORE \
-	IRQ_RESTORE v; \
-	RET
-
-#define v %ecx
-BEGIN_IRQ_SAVE(read)
-	movl  (v), %eax
-	movl 4(v), %edx
-	RET_IRQ_RESTORE
-ENDP
-#undef v
-
-#define v %esi
-BEGIN_IRQ_SAVE(set)
-	movl %ebx,  (v)
-	movl %ecx, 4(v)
-	RET_IRQ_RESTORE
-ENDP
-#undef v
-
-#define v  %esi
-BEGIN_IRQ_SAVE(xchg)
-	movl  (v), %eax
-	movl 4(v), %edx
-	movl %ebx,  (v)
-	movl %ecx, 4(v)
-	RET_IRQ_RESTORE
-ENDP
-#undef v
-
-#define v %ecx
-BEGIN_IRQ_SAVE(add)
-	addl %eax,  (v)
-	adcl %edx, 4(v)
-	RET_IRQ_RESTORE
-ENDP
-#undef v
-
-#define v %ecx
-BEGIN_IRQ_SAVE(add_return)
-	addl  (v), %eax
-	adcl 4(v), %edx
-	movl %eax,  (v)
-	movl %edx, 4(v)
-	RET_IRQ_RESTORE
-ENDP
-#undef v
-
-#define v %ecx
-BEGIN_IRQ_SAVE(sub)
-	subl %eax,  (v)
-	sbbl %edx, 4(v)
-	RET_IRQ_RESTORE
-ENDP
-#undef v
-
-#define v %ecx
-BEGIN_IRQ_SAVE(sub_return)
-	negl %edx
-	negl %eax
-	sbbl $0, %edx
-	addl  (v), %eax
-	adcl 4(v), %edx
-	movl %eax,  (v)
-	movl %edx, 4(v)
-	RET_IRQ_RESTORE
-ENDP
-#undef v
-
-#define v %esi
-BEGIN_IRQ_SAVE(inc)
-	addl $1,  (v)
-	adcl $0, 4(v)
-	RET_IRQ_RESTORE
-ENDP
-#undef v
-
-#define v %esi
-BEGIN_IRQ_SAVE(inc_return)
-	movl  (v), %eax
-	movl 4(v), %edx
-	addl $1, %eax
-	adcl $0, %edx
-	movl %eax,  (v)
-	movl %edx, 4(v)
-	RET_IRQ_RESTORE
-ENDP
-#undef v
-
-#define v %esi
-BEGIN_IRQ_SAVE(dec)
-	subl $1,  (v)
-	sbbl $0, 4(v)
-	RET_IRQ_RESTORE
-ENDP
-#undef v
-
-#define v %esi
-BEGIN_IRQ_SAVE(dec_return)
-	movl  (v), %eax
-	movl 4(v), %edx
-	subl $1, %eax
-	sbbl $0, %edx
-	movl %eax,  (v)
-	movl %edx, 4(v)
-	RET_IRQ_RESTORE
-ENDP
-#undef v
-
-#define v %esi
-BEGIN_IRQ_SAVE(add_unless)
-	addl %eax, %ecx
-	adcl %edx, %edi
-	addl  (v), %eax
-	adcl 4(v), %edx
-	cmpl %eax, %ecx
-	je 3f
-1:
-	movl %eax,  (v)
-	movl %edx, 4(v)
-	movl $1, %eax
-2:
-	RET_IRQ_RESTORE
-3:
-	cmpl %edx, %edi
-	jne 1b
-	xorl %eax, %eax
-	jmp 2b
-ENDP
-#undef v
-
-#define v %esi
-BEGIN_IRQ_SAVE(inc_not_zero)
-	movl  (v), %eax
-	movl 4(v), %edx
-	testl %eax, %eax
-	je 3f
-1:
-	addl $1, %eax
-	adcl $0, %edx
-	movl %eax,  (v)
-	movl %edx, 4(v)
-	movl $1, %eax
-2:
-	RET_IRQ_RESTORE
-3:
-	testl %edx, %edx
-	jne 1b
-	jmp 2b
-ENDP
-#undef v
-
-#define v %esi
-BEGIN_IRQ_SAVE(dec_if_positive)
-	movl  (v), %eax
-	movl 4(v), %edx
-	subl $1, %eax
-	sbbl $0, %edx
-	js 1f
-	movl %eax,  (v)
-	movl %edx, 4(v)
-1:
-	RET_IRQ_RESTORE
-ENDP
-#undef v
diff --git a/arch/x86/lib/cmpxchg8b_emu.S b/arch/x86/lib/cmpxchg8b_emu.S
deleted file mode 100644
index d4bb24347ff8..000000000000
--- a/arch/x86/lib/cmpxchg8b_emu.S
+++ /dev/null
@@ -1,97 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#include <linux/export.h>
-#include <linux/linkage.h>
-#include <asm/percpu.h>
-#include <asm/processor-flags.h>
-
-.text
-
-#ifndef CONFIG_X86_CX8
-
-/*
- * Emulate 'cmpxchg8b (%esi)' on UP
- *
- * Inputs:
- * %esi : memory location to compare
- * %eax : low 32 bits of old value
- * %edx : high 32 bits of old value
- * %ebx : low 32 bits of new value
- * %ecx : high 32 bits of new value
- */
-SYM_FUNC_START(cmpxchg8b_emu)
-
-	pushfl
-	cli
-
-	cmpl	(%esi), %eax
-	jne	.Lnot_same
-	cmpl	4(%esi), %edx
-	jne	.Lnot_same
-
-	movl	%ebx, (%esi)
-	movl	%ecx, 4(%esi)
-
-	orl	$X86_EFLAGS_ZF, (%esp)
-
-	popfl
-	RET
-
-.Lnot_same:
-	movl	(%esi), %eax
-	movl	4(%esi), %edx
-
-	andl	$(~X86_EFLAGS_ZF), (%esp)
-
-	popfl
-	RET
-
-SYM_FUNC_END(cmpxchg8b_emu)
-EXPORT_SYMBOL(cmpxchg8b_emu)
-
-#endif
-
-#ifndef CONFIG_UML
-
-/*
- * Emulate 'cmpxchg8b %fs:(%rsi)'
- *
- * Inputs:
- * %esi : memory location to compare
- * %eax : low 32 bits of old value
- * %edx : high 32 bits of old value
- * %ebx : low 32 bits of new value
- * %ecx : high 32 bits of new value
- *
- * Notably this is not LOCK prefixed and is not safe against NMIs
- */
-SYM_FUNC_START(this_cpu_cmpxchg8b_emu)
-
-	pushfl
-	cli
-
-	cmpl	__percpu (%esi), %eax
-	jne	.Lnot_same2
-	cmpl	__percpu 4(%esi), %edx
-	jne	.Lnot_same2
-
-	movl	%ebx, __percpu (%esi)
-	movl	%ecx, __percpu 4(%esi)
-
-	orl	$X86_EFLAGS_ZF, (%esp)
-
-	popfl
-	RET
-
-.Lnot_same2:
-	movl	__percpu (%esi), %eax
-	movl	__percpu 4(%esi), %edx
-
-	andl	$(~X86_EFLAGS_ZF), (%esp)
-
-	popfl
-	RET
-
-SYM_FUNC_END(this_cpu_cmpxchg8b_emu)
-
-#endif
diff --git a/arch/x86/um/Kconfig b/arch/x86/um/Kconfig
index 44b12e45f9a0..5b78440a78b9 100644
--- a/arch/x86/um/Kconfig
+++ b/arch/x86/um/Kconfig
@@ -13,7 +13,7 @@ config UML_X86
 	select ARCH_USE_QUEUED_SPINLOCKS
 	select DCACHE_WORD_ACCESS
 	select HAVE_EFFICIENT_UNALIGNED_ACCESS
-	select UML_SUBARCH_SUPPORTS_SMP if X86_CX8
+	select UML_SUBARCH_SUPPORTS_SMP
 
 config 64BIT
 	bool "64-bit kernel" if "$(SUBARCH)" = "x86"
diff --git a/arch/x86/um/Makefile b/arch/x86/um/Makefile
index 100b68f601f9..716da7b1e3e9 100644
--- a/arch/x86/um/Makefile
+++ b/arch/x86/um/Makefile
@@ -19,8 +19,7 @@ ifeq ($(CONFIG_X86_32),y)
 
 obj-y += syscalls_32.o
 
-subarch-y = ../lib/string_32.o ../lib/atomic64_32.o ../lib/atomic64_cx8_32.o
-subarch-y += ../lib/cmpxchg8b_emu.o ../lib/atomic64_386_32.o
+subarch-y = ../lib/string_32.o ../lib/atomic64_32.o
 subarch-y += ../lib/checksum_32.o
 subarch-y += ../kernel/sys_ia32.o
 
diff --git a/lib/atomic64_test.c b/lib/atomic64_test.c
index d726068358c7..37af41df3e6a 100644
--- a/lib/atomic64_test.c
+++ b/lib/atomic64_test.c
@@ -251,15 +251,12 @@ static __init int test_atomics_init(void)
 	test_atomic64();
 
 #ifdef CONFIG_X86
-	pr_info("passed for %s platform %s CX8 and %s SSE\n",
+	pr_info("passed for %s platform %s SSE\n",
 #ifdef CONFIG_X86_64
 		"x86-64",
-#elif defined(CONFIG_X86_CX8)
-		"i586+",
 #else
-		"i386+",
+		"i586+",
 #endif
-	       boot_cpu_has(X86_FEATURE_CX8) ? "with" : "without",
 	       boot_cpu_has(X86_FEATURE_XMM) ? "with" : "without");
 #else
 	pr_info("passed\n");
-- 
2.53.0


^ permalink raw reply	[flat|nested] 8+ messages in thread
* [PATCH 4/7] x86: require minimum 64 byte cache lines
  2026-11-05 16:34 [PATCH v2 0/7] x86-32 CPU configuration cleanups Arnd Bergmann
                   ` (2 preceding siblings ...)
  2026-11-05 16:34 ` [PATCH 3/7] x86: make CX8 " Arnd Bergmann
@ 2026-11-05 16:34 ` Arnd Bergmann
  2026-11-05 16:34 ` [PATCH 5/7] x86: remove dependencies on CONFIG_M... CPU options Arnd Bergmann
                   ` (2 subsequent siblings)
  6 siblings, 0 replies; 8+ messages in thread
From: Arnd Bergmann @ 2026-11-05 16:34 UTC (permalink / raw)
  To: Ingo Molnar
  Cc: Arnd Bergmann, Richard Weinberger, Anton Ivanov, Johannes Berg,
	Thomas Gleixner, Borislav Petkov, Dave Hansen, H. Peter Anvin,
	Peter Zijlstra, Will Deacon, Boqun Feng, Gary Guo, Yury Norov,
	Rasmus Villemoes, Boris Ostrovsky, Alexander Usyskin,
	Tony Nguyen, Przemek Kitszel, x86, linux-kernel, linux-um

From: Arnd Bergmann <arnd@arndb.de>

Later x86-32 CPUs like Pentium-M, K7 and Atom use 64 byte cache lines
and are incompatible with kernels built for smaller values of
X86_L1_CACHE_SHIFT.

Pentium-4 CPUs have 128 byte cache lines but are compatible with
cache operations that expect the lines to be 64 bytes.

Older CPUs have smaller cache lines of 16 or 32 bytes but work
correctly when X86_L1_CACHE_SHIFT is set to a larger value.

Remove the per-CPU tuning and always build for 64 or 128 byte
cache lines that work correctly in any CPU.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
 arch/x86/Kconfig.cpu | 8 +++-----
 1 file changed, 3 insertions(+), 5 deletions(-)

diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
index 832e4bd9f6e0..382c9023c855 100644
--- a/arch/x86/Kconfig.cpu
+++ b/arch/x86/Kconfig.cpu
@@ -180,8 +180,8 @@ config MVIAC7
 	bool "VIA C7"
 	depends on X86_32
 	help
-	  Select this for a VIA C7.  Selecting this uses the correct cache
-	  shift and tells gcc to treat the CPU as a 686.
+	  Select this for a VIA C7.  Selecting this tells gcc to treat the
+	  CPU as a 686.
 
 config MATOM
 	bool "Intel Atom"
@@ -250,9 +250,7 @@ config X86_INTERNODE_CACHE_SHIFT
 config X86_L1_CACHE_SHIFT
 	int
 	default "7" if MPENTIUM4
-	default "6" if MK7 || MPENTIUMM || MATOM || MVIAC7 || X86_GENERIC || X86_64
-	default "4" if MGEODEGX1
-	default "5" if MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MVIAC3_2 || MGEODE_LX
+	default "6"
 
 config X86_F00F_BUG
 	def_bool y
-- 
2.53.0


^ permalink raw reply	[flat|nested] 8+ messages in thread
* [PATCH 5/7] x86: remove dependencies on CONFIG_M... CPU options
  2026-11-05 16:34 [PATCH v2 0/7] x86-32 CPU configuration cleanups Arnd Bergmann
                   ` (3 preceding siblings ...)
  2026-11-05 16:34 ` [PATCH 4/7] x86: require minimum 64 byte cache lines Arnd Bergmann
@ 2026-11-05 16:34 ` Arnd Bergmann
  2026-11-05 16:34 ` [PATCH 6/7] x86: remove dependencies on per-CPU options Arnd Bergmann
  2026-11-05 16:34 ` [PATCH 7/7] x86: simplify 32-bit instruction set selection Arnd Bergmann
  6 siblings, 0 replies; 8+ messages in thread
From: Arnd Bergmann @ 2026-11-05 16:34 UTC (permalink / raw)
  To: Ingo Molnar
  Cc: Arnd Bergmann, Richard Weinberger, Anton Ivanov, Johannes Berg,
	Thomas Gleixner, Borislav Petkov, Dave Hansen, H. Peter Anvin,
	Peter Zijlstra, Will Deacon, Boqun Feng, Gary Guo, Yury Norov,
	Rasmus Villemoes, Boris Ostrovsky, Alexander Usyskin,
	Tony Nguyen, Przemek Kitszel, x86, linux-kernel, linux-um

From: Arnd Bergmann <arnd@arndb.de>

CPU specific features should generally be controlled by
CPU_SUP_xxx options rather than CONFIG_Mxxx, to allow
generic kernels to be built that work with all of them.

Replace the few options that don't follow this scheme
with checks on either CPU_SUP_xxx or X86_PAE by itself.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
 arch/x86/kernel/tsc.c    | 2 +-
 arch/x86/xen/Kconfig     | 1 -
 drivers/misc/mei/Kconfig | 2 +-
 3 files changed, 2 insertions(+), 3 deletions(-)

diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index 02269dcbde1f..d8b79d1151da 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -1212,7 +1212,7 @@ static void __init tsc_disable_clocksource_watchdog(void)
 
 static void __init check_system_tsc_reliable(void)
 {
-#if defined(CONFIG_MGEODEGX1) || defined(CONFIG_MGEODE_LX) || defined(CONFIG_X86_GENERIC)
+#if defined(CONFIG_CPU_SUP_CYRIX_32)
 	if (is_geode_lx()) {
 		/* RTSC counts during suspend */
 #define RTSC_SUSP 0x100
diff --git a/arch/x86/xen/Kconfig b/arch/x86/xen/Kconfig
index 609e79942fcb..0655ddd6fd39 100644
--- a/arch/x86/xen/Kconfig
+++ b/arch/x86/xen/Kconfig
@@ -10,7 +10,6 @@ config XEN
 	select X86_HV_CALLBACK_VECTOR
 	select HIBERNATE_CALLBACKS
 	depends on X86_64 || (X86_32 && X86_PAE)
-	depends on X86_64 || (X86_GENERIC || MPENTIUM4 || MATOM)
 	depends on X86_LOCAL_APIC
 	help
 	  This is the Linux Xen port.  Enabling this will allow the
diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig
index 2d1bc5b4d11b..faa451584002 100644
--- a/drivers/misc/mei/Kconfig
+++ b/drivers/misc/mei/Kconfig
@@ -4,7 +4,7 @@ config INTEL_MEI
 	tristate "Intel Management Engine Interface"
 	depends on PCI
 	depends on X86 || DRM_XE!=n || COMPILE_TEST
-	default X86_64 || MATOM
+	default X86_64 || CPU_SUP_INTEL
 	help
 	  The Intel Management Engine (Intel ME) provides Manageability,
 	  Security and Media services for system containing Intel chipsets.
-- 
2.53.0


^ permalink raw reply	[flat|nested] 8+ messages in thread
* [PATCH 6/7] x86: remove dependencies on per-CPU options
  2026-11-05 16:34 [PATCH v2 0/7] x86-32 CPU configuration cleanups Arnd Bergmann
                   ` (4 preceding siblings ...)
  2026-11-05 16:34 ` [PATCH 5/7] x86: remove dependencies on CONFIG_M... CPU options Arnd Bergmann
@ 2026-11-05 16:34 ` Arnd Bergmann
  2026-11-05 16:34 ` [PATCH 7/7] x86: simplify 32-bit instruction set selection Arnd Bergmann
  6 siblings, 0 replies; 8+ messages in thread
From: Arnd Bergmann @ 2026-11-05 16:34 UTC (permalink / raw)
  To: Ingo Molnar
  Cc: Arnd Bergmann, Richard Weinberger, Anton Ivanov, Johannes Berg,
	Thomas Gleixner, Borislav Petkov, Dave Hansen, H. Peter Anvin,
	Peter Zijlstra, Will Deacon, Boqun Feng, Gary Guo, Yury Norov,
	Rasmus Villemoes, Boris Ostrovsky, Alexander Usyskin,
	Tony Nguyen, Przemek Kitszel, x86, linux-kernel, linux-um

From: Arnd Bergmann <arnd@arndb.de>

A few CPU feature options are defined in terms of CONFIG_Mxxx
CPU selection options.

This conflicts with the idea of CONFIG_X86_GENERIC allowing
one to build a kernel that works with multiple slightly
incompatible CPUs.

As a simplification, change all of these to be enabled in terms
of either 586-class or 686-class builds.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
 arch/x86/Kconfig.cpu            | 14 ++++----------
 arch/x86/Kconfig.cpufeatures    |  8 +-------
 arch/x86/include/asm/bitops.h   |  4 ++--
 arch/x86/include/asm/debugreg.h | 10 ++++------
 arch/x86/include/asm/ptrace.h   |  6 +-----
 5 files changed, 12 insertions(+), 30 deletions(-)

diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
index 382c9023c855..21026e0cb569 100644
--- a/arch/x86/Kconfig.cpu
+++ b/arch/x86/Kconfig.cpu
@@ -253,8 +253,7 @@ config X86_L1_CACHE_SHIFT
 	default "6"
 
 config X86_F00F_BUG
-	def_bool y
-	depends on M586MMX || M586TSC || M586
+	def_bool X86_MINIMUM_CPU_FAMILY=5 && CPU_SUP_INTEL
 
 config X86_ALIGNMENT_16
 	def_bool y
@@ -272,12 +271,6 @@ config X86_HAVE_PAE
 	def_bool y
 	depends on MCRUSOE || MEFFICEON || MCYRIXIII || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC7 || MATOM || X86_64
 
-# this should be set for all -march=.. options where the compiler
-# generates cmov.
-config X86_CMOV
-	def_bool y
-	depends on (MK7 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || MATOM || MGEODE_LX || X86_64)
-
 config X86_MINIMUM_CPU_FAMILY
 	int
 	default "64" if X86_64
@@ -286,7 +279,8 @@ config X86_MINIMUM_CPU_FAMILY
 
 config X86_DEBUGCTLMSR
 	def_bool y
-	depends on !(MK6 || MCYRIXIII || M586MMX || M586TSC || M586) && !UML
+	depends on !UML
+	depends on X86_MINIMUM_CPU_FAMILY=6
 
 config IA32_FEAT_CTL
 	def_bool y
@@ -318,7 +312,7 @@ config CPU_SUP_INTEL
 config CPU_SUP_CYRIX_32
 	default y
 	bool "Support Cyrix processors" if PROCESSOR_SELECT
-	depends on M586 || M586TSC || M586MMX || (EXPERT && !64BIT)
+	depends on X86_MINIMUM_CPU_FAMILY=5
 	help
 	  This enables detection, tunings and quirks for Cyrix processors
 
diff --git a/arch/x86/Kconfig.cpufeatures b/arch/x86/Kconfig.cpufeatures
index e0f2ff65377d..a0a1e838014d 100644
--- a/arch/x86/Kconfig.cpufeatures
+++ b/arch/x86/Kconfig.cpufeatures
@@ -44,13 +44,7 @@ config X86_REQUIRED_FEATURE_NOPL
 # generates cmov.
 config X86_REQUIRED_FEATURE_CMOV
 	def_bool y
-	depends on X86_CMOV
-
-# this should be set for all -march= options where the compiler
-# generates movbe.
-config X86_REQUIRED_FEATURE_MOVBE
-	def_bool y
-	depends on MATOM
+	depends on X86_MINIMUM_CPU_FAMILY >= 6
 
 config X86_REQUIRED_FEATURE_SYSFAST32
 	def_bool y
diff --git a/arch/x86/include/asm/bitops.h b/arch/x86/include/asm/bitops.h
index c2ce213f2b9b..f65872f67820 100644
--- a/arch/x86/include/asm/bitops.h
+++ b/arch/x86/include/asm/bitops.h
@@ -312,7 +312,7 @@ static __always_inline __attribute_const__ int variable_ffs(int x)
 	asm("bsfl %1,%0"
 	    : "=r" (r)
 	    : ASM_INPUT_RM (x), "0" (-1));
-#elif defined(CONFIG_X86_CMOV)
+#elif CONFIG_X86_MINIMUM_CPU_FAMILY >= 6
 	asm("bsfl %1,%0\n\t"
 	    "cmovzl %2,%0"
 	    : "=&r" (r) : "rm" (x), "r" (-1));
@@ -369,7 +369,7 @@ static __always_inline __attribute_const__ int fls(unsigned int x)
 	asm("bsrl %1,%0"
 	    : "=r" (r)
 	    : ASM_INPUT_RM (x), "0" (-1));
-#elif defined(CONFIG_X86_CMOV)
+#elif CONFIG_X86_MINIMUM_CPU_FAMILY >= 6
 	asm("bsrl %1,%0\n\t"
 	    "cmovzl %2,%0"
 	    : "=&r" (r) : "rm" (x), "rm" (-1));
diff --git a/arch/x86/include/asm/debugreg.h b/arch/x86/include/asm/debugreg.h
index 854d82b88ff4..90989e95cb8a 100644
--- a/arch/x86/include/asm/debugreg.h
+++ b/arch/x86/include/asm/debugreg.h
@@ -176,10 +176,9 @@ static inline unsigned long get_debugctlmsr(void)
 {
 	unsigned long debugctlmsr = 0;
 
-#ifndef CONFIG_X86_DEBUGCTLMSR
-	if (boot_cpu_data.x86 < 6)
+	if (CONFIG_X86_MINIMUM_CPU_FAMILY < 6 || boot_cpu_data.x86 < 6)
 		return 0;
-#endif
+
 	rdmsrq(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
 
 	return debugctlmsr;
@@ -187,10 +186,9 @@ static inline unsigned long get_debugctlmsr(void)
 
 static inline void update_debugctlmsr(unsigned long debugctlmsr)
 {
-#ifndef CONFIG_X86_DEBUGCTLMSR
-	if (boot_cpu_data.x86 < 6)
+	if (CONFIG_X86_MINIMUM_CPU_FAMILY < 6 || boot_cpu_data.x86 < 6)
 		return;
-#endif
+
 	wrmsrq(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
 }
 
diff --git a/arch/x86/include/asm/ptrace.h b/arch/x86/include/asm/ptrace.h
index 7bb7bd90355d..b1d881229fab 100644
--- a/arch/x86/include/asm/ptrace.h
+++ b/arch/x86/include/asm/ptrace.h
@@ -449,11 +449,7 @@ static inline unsigned long regs_get_kernel_argument(struct pt_regs *regs,
 }
 
 #define arch_has_single_step()	(1)
-#ifdef CONFIG_X86_DEBUGCTLMSR
-#define arch_has_block_step()	(1)
-#else
-#define arch_has_block_step()	(boot_cpu_data.x86 >= 6)
-#endif
+#define arch_has_block_step()	((CONFIG_X86_MINIMUM_CPU_FAMILY >= 6) || (boot_cpu_data.x86 >= 6))
 
 #define ARCH_HAS_USER_SINGLE_STEP_REPORT
 
-- 
2.53.0


^ permalink raw reply	[flat|nested] 8+ messages in thread
* [PATCH 7/7] x86: simplify 32-bit instruction set selection
  2026-11-05 16:34 [PATCH v2 0/7] x86-32 CPU configuration cleanups Arnd Bergmann
                   ` (5 preceding siblings ...)
  2026-11-05 16:34 ` [PATCH 6/7] x86: remove dependencies on per-CPU options Arnd Bergmann
@ 2026-11-05 16:34 ` Arnd Bergmann
  6 siblings, 0 replies; 8+ messages in thread
From: Arnd Bergmann @ 2026-11-05 16:34 UTC (permalink / raw)
  To: Ingo Molnar
  Cc: Arnd Bergmann, Richard Weinberger, Anton Ivanov, Johannes Berg,
	Thomas Gleixner, Borislav Petkov, Dave Hansen, H. Peter Anvin,
	Peter Zijlstra, Will Deacon, Boqun Feng, Gary Guo, Yury Norov,
	Rasmus Villemoes, Boris Ostrovsky, Alexander Usyskin,
	Tony Nguyen, Przemek Kitszel, x86, linux-kernel, linux-um

From: Arnd Bergmann <arnd@arndb.de>

The -march= compiler flags select both instruction set and tuning for
a particular CPU, which works well when building a kernel that can only
run on this one type, but has some counterintuitive effects because it
is not always clear which models are compatible.

E.g. building for Geode LX results in a kernel that can work on all on
all 686-class CPUs but crashes on CPUs without the CMOV instructions.
Building a kernel for 686 could work on Geode LX and Crusoe but fails
because of the CPU generation check that detects these as 585-class.
Similarly, building for Intel Atom produces a 32-bit kernel that uses
the MOVBE instructions and does not work on any other 32-bit CPU or
even 64-bit CPUs before Haswell/Excavator.

Change the CPU selection to build everything with either -march=i586
or -march=i686 and make the specific options only change the -mtune=
parameter where this was previously handled by -march=. Note that
the only -mtune= options that gcc or clang understand for x86-32
are i486, pentium, pentiumpro, pentium4, atom, geode, k6 and athlon,
the other ten are just aliases for one of them.

Selecting any 586-class configuration option now produces a kernel that
works on every supported CPU, while selecting a 686-class configuration
works on all 686-class CPUs but no 586-class ones.

Consequently, the vermagic.h logic can be simplified to just these
two cases.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
 arch/x86/Kconfig.cpu            | 13 +++++-------
 arch/x86/Makefile_32.cpu        | 16 +++++++--------
 arch/x86/include/asm/vermagic.h | 36 ++-------------------------------
 3 files changed, 15 insertions(+), 50 deletions(-)

diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
index 21026e0cb569..121881c4d076 100644
--- a/arch/x86/Kconfig.cpu
+++ b/arch/x86/Kconfig.cpu
@@ -6,9 +6,9 @@ choice
 	default M686
 	help
 	  This is the processor type of your CPU. This information is
-	  used for optimizing purposes. In order to compile a kernel
-	  that can run on all supported x86 CPU types (albeit not
-	  optimally fast), you can specify "586" here.
+	  used to pick between i586-class and i686-class processors,
+	  as well as to optimize for a particular microarchitecture
+	  within the two classes.
 
 	  Note that the 386 and 486 is no longer supported, this includes
 	  AMD/Cyrix/Intel 386DX/DXL/SL/SLC/SX, Cyrix/TI 486DLC/DLC2,
@@ -164,16 +164,13 @@ config MCYRIXIII
 	  treat this chip as a generic 586. Whilst the CPU is 686 class,
 	  it lacks the cmov extension which gcc assumes is present when
 	  generating 686 code.
-	  Note that Nehemiah (Model 9) and above will not boot with this
-	  kernel due to them lacking the 3DNow! instructions used in earlier
-	  incarnations of the CPU.
 
 config MVIAC3_2
 	bool "VIA C3-2 (Nehemiah)"
 	depends on X86_32
 	help
-	  Select this for a VIA C3 "Nehemiah". Selecting this enables usage
-	  of SSE and tells gcc to treat the CPU as a 686.
+	  Select this for a VIA C3 "Nehemiah". Selecting tells gcc to treat
+	  the CPU as a 686.
 	  Note, this kernel will not boot on older (pre model 9) C3s.
 
 config MVIAC7
diff --git a/arch/x86/Makefile_32.cpu b/arch/x86/Makefile_32.cpu
index c5aa169b596d..1735a5f95d33 100644
--- a/arch/x86/Makefile_32.cpu
+++ b/arch/x86/Makefile_32.cpu
@@ -11,26 +11,26 @@ align		:= -falign-functions=0 -falign-jumps=0 -falign-loops=0
 endif
 
 cflags-$(CONFIG_M586TSC)	+= -march=i586
-cflags-$(CONFIG_M586MMX)	+= -march=pentium-mmx
+cflags-$(CONFIG_M586MMX)	+= -march=i586
 cflags-$(CONFIG_M686)		+= -march=i686
 cflags-$(CONFIG_MPENTIUMII)	+= -march=i686 $(call tune,pentium2)
 cflags-$(CONFIG_MPENTIUMIII)	+= -march=i686 $(call tune,pentium3)
 cflags-$(CONFIG_MPENTIUMM)	+= -march=i686 $(call tune,pentium3)
 cflags-$(CONFIG_MPENTIUM4)	+= -march=i686 $(call tune,pentium4)
-cflags-$(CONFIG_MK6)		+= -march=k6
+cflags-$(CONFIG_MK6)		+= -march=i586 $(call tune,k6)
 # Please note, that patches that add -march=athlon-xp and friends are pointless.
 # They make zero difference whatsosever to performance at this time.
-cflags-$(CONFIG_MK7)		+= -march=athlon
+cflags-$(CONFIG_MK7)		+= -march=i686 $(call tune,athlon)
 cflags-$(CONFIG_MCRUSOE)	+= -march=i686 $(align)
 cflags-$(CONFIG_MEFFICEON)	+= -march=i686 $(call tune,pentium3) $(align)
-cflags-$(CONFIG_MCYRIXIII)	+= $(call cc-option,-march=c3,-march=i486) $(align)
-cflags-$(CONFIG_MVIAC3_2)	+= $(call cc-option,-march=c3-2,-march=i686)
+cflags-$(CONFIG_MCYRIXIII)	+= -march=i586 $(call tune,i486) $(align)
+cflags-$(CONFIG_MVIAC3_2)	+= -march=i686
 cflags-$(CONFIG_MVIAC7)		+= -march=i686
-cflags-$(CONFIG_MATOM)		+= -march=atom
+cflags-$(CONFIG_MATOM)		+= -march=i686 $(call tune,atom)
 
 # Geode GX1 support
-cflags-$(CONFIG_MGEODEGX1)	+= -march=pentium-mmx
-cflags-$(CONFIG_MGEODE_LX)	+= $(call cc-option,-march=geode,-march=pentium-mmx)
+cflags-$(CONFIG_MGEODEGX1)	+= -march=i586 $(call tune,geode)
+cflags-$(CONFIG_MGEODE_LX)	+= -march=i586 $(call tune,geode)
 # add at the end to overwrite eventual tuning options from earlier
 # cpu entries
 cflags-$(CONFIG_X86_GENERIC) 	+= $(call tune,generic,$(call tune,i686))
diff --git a/arch/x86/include/asm/vermagic.h b/arch/x86/include/asm/vermagic.h
index e26061df0c9b..5323ed585bc9 100644
--- a/arch/x86/include/asm/vermagic.h
+++ b/arch/x86/include/asm/vermagic.h
@@ -5,42 +5,10 @@
 
 #ifdef CONFIG_X86_64
 /* X86_64 does not define MODULE_PROC_FAMILY */
-#elif defined CONFIG_M586TSC
-#define MODULE_PROC_FAMILY "586TSC "
-#elif defined CONFIG_M586MMX
-#define MODULE_PROC_FAMILY "586MMX "
-#elif defined CONFIG_MATOM
-#define MODULE_PROC_FAMILY "ATOM "
-#elif defined CONFIG_M686
+#elif CONFIG_X86_MINIMUM_CPU_FAMILY == 6
 #define MODULE_PROC_FAMILY "686 "
-#elif defined CONFIG_MPENTIUMII
-#define MODULE_PROC_FAMILY "PENTIUMII "
-#elif defined CONFIG_MPENTIUMIII
-#define MODULE_PROC_FAMILY "PENTIUMIII "
-#elif defined CONFIG_MPENTIUMM
-#define MODULE_PROC_FAMILY "PENTIUMM "
-#elif defined CONFIG_MPENTIUM4
-#define MODULE_PROC_FAMILY "PENTIUM4 "
-#elif defined CONFIG_MK6
-#define MODULE_PROC_FAMILY "K6 "
-#elif defined CONFIG_MK7
-#define MODULE_PROC_FAMILY "K7 "
-#elif defined CONFIG_MCRUSOE
-#define MODULE_PROC_FAMILY "CRUSOE "
-#elif defined CONFIG_MEFFICEON
-#define MODULE_PROC_FAMILY "EFFICEON "
-#elif defined CONFIG_MCYRIXIII
-#define MODULE_PROC_FAMILY "CYRIXIII "
-#elif defined CONFIG_MVIAC3_2
-#define MODULE_PROC_FAMILY "VIAC3-2 "
-#elif defined CONFIG_MVIAC7
-#define MODULE_PROC_FAMILY "VIAC7 "
-#elif defined CONFIG_MGEODEGX1
-#define MODULE_PROC_FAMILY "GEODEGX1 "
-#elif defined CONFIG_MGEODE_LX
-#define MODULE_PROC_FAMILY "GEODE "
 #else
-#error unknown processor family
+#define MODULE_PROC_FAMILY "586 "
 #endif
 
 #ifdef CONFIG_X86_32
-- 
2.53.0


^ permalink raw reply	[flat|nested] 8+ messages in thread
end of thread, other threads:[~2026-11-05 16:35 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2026-11-05 16:34 [PATCH v2 0/7] x86-32 CPU configuration cleanups Arnd Bergmann
2026-11-05 16:34 ` [PATCH 1/7] x86: remove AMD Élan remnants Arnd Bergmann
2026-11-05 16:34 ` [PATCH 2/7] x86: make TSC usage unconditional Arnd Bergmann
2026-11-05 16:34 ` [PATCH 3/7] x86: make CX8 " Arnd Bergmann
2026-11-05 16:34 ` [PATCH 4/7] x86: require minimum 64 byte cache lines Arnd Bergmann
2026-11-05 16:34 ` [PATCH 5/7] x86: remove dependencies on CONFIG_M... CPU options Arnd Bergmann
2026-11-05 16:34 ` [PATCH 6/7] x86: remove dependencies on per-CPU options Arnd Bergmann
2026-11-05 16:34 ` [PATCH 7/7] x86: simplify 32-bit instruction set selection Arnd Bergmann

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