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From: Bjorn Helgaas <helgaas@kernel.org>
To: 廖煊 <liaoxuan@open-hieco.net>
Cc: kbusch <kbusch@kernel.org>, axboe <axboe@kernel.dk>,
	hch <hch@lst.de>, sagi <sagi@grimberg.me>,
	linux-nvme <linux-nvme@lists.infradead.org>,
	linux-kernel <linux-kernel@vger.kernel.org>,
	"default avatarZheng Tan" <tanzheng@kylinos.cn>,
	"Ilpo Järvinen" <ilpo.jarvinen@linux.intel.com>
Subject: Re: 回复:[PATCH 1/3] nvme: Add adaptive PCIe link rate switching function
Date: Thu, 5 Nov 2026 13:22:28 -0600	[thread overview]
Message-ID: <20261105192228.GA1550766@bhelgaas> (raw)
In-Reply-To: <5453bf57-fd19-458b-a723-bc7ab99c2479.liaoxuan@open-hieco.net>

On Thu, Nov 05, 2026 at 02:30:13PM +0800, 廖煊 wrote:
> Hi Bjorn,
> Thank you for the review and for the question.
> 
> The reason for restricting this feature to Hygon platforms is that the
> PCIe link retraining time varies across different CPU platforms.
> 
> In this patch, the I/O threshold for downgrading/upgrading the link rate
> is derived based on this retraining time. Currently, it is hardcoded as
> 100us in nvme_calc_speed_threshold(), which is the validated value for
> Hygon. Since we have only verified this timing parameter on Hygon platforms,
> we added the restriction to avoid potential performance regressions on
> other platforms where the retraining time might be different.

Seems suspect to hard-code platform parameters like this, but if you
must, at least add a comment to the effect that this depends on the
platform and the current value is for platform X.

  reply	other threads:[~2026-11-05 19:22 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <cover.1790134954.git.liaoxuan@open-hieco.net>
2026-11-03  6:25 ` [PATCH " Liao Xuan
2026-11-03 18:23   ` Bjorn Helgaas
2026-11-05  6:30     ` 回复:[PATCH " 廖煊
2026-11-05 19:22       ` Bjorn Helgaas [this message]
2026-11-06  3:39         ` 回复:回复:[PATCH " 廖煊
2026-11-03 19:08   ` [PATCH " Keith Busch
2026-11-05  5:50     ` 回复:[PATCH " 廖煊
2026-11-05 19:57       ` Keith Busch

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