[PATCH 00/25] riscv: add support for the Metanoia MT2824 SoC and MT5824 EVB

["Benoît Monin" <benoit.monin@bootlin.com>]

Hi all,

This series adds initial upstream support for the Metanoia MT2824 SoC
and its MT5824 evaluation board.

The MT2824 is a dual-core RISC-V SoC built on Andes AX45MP cores. It
integrates two 8250-compatible UARTs, the Andes PLIC/PLICSW/PLMT interrupt
and timer blocks, the AX45MP L2 cache controller, a simple reset controller
and a system reboot controller, the ATCWDT200 watchdog, one QSPI and eight
ATCSPI200 SPI controllers, a Synopsys DWC MSHC 2.00a eMMC/SD controller,
and a Synopsys DWC2 USB2 host controller with a reset-only USB2 PHY.

The series is organised as:

- patches 1-14 add the device tree bindings, the Metanoia vendor prefix,
  the RISC-V board schema and the SoC block compatibles
- patch 15 adds ARCH_METANOIA and selects the AX45MP errata
- patches 16-23 add the reset, SPI, watchdog, MMC, PHY and USB changes
  needed to build and probe on this SoC
- patch 24 adds the MT2824 SoC and MT5824 EVB device trees
- patch 25 adds the MAINTAINERS entry

The ATCSPI200 driver gains optional interrupt support for PIO transfers:
when the controller IRQ is wired, the FIFOs and the end of transfer
are serviced from the handler, with a fallback to polling when no IRQ
is available.

The DWC MSHC controller on the evaluation board is wired to either an
SD slot or an eMMC through a board jumper that the SoC cannot read. In
the absence of a fixed card type in the device tree, the driver probes
the eMMC first at 1.8 V and falls back to the SD slot at 3.3 V. The
controller also needs custom tuning and HS400 PHY DLL handling, which
is why it has its own sdhci_ops.

The MT2824 SoC contains other controllers not yet exposed (I2C, GPIO,
pinctrl, Ethernet, DSP, ...). This first series allows accessing the
evaluation board via its serial console, and all its storage options
(SPI-NOR, eMMC, SD card). The watchdog and the USB port are also
available.

The driver changes do not depend on the DTS at build time and are gated
on the new compatible strings. For merge ordering, the DTS depends on the
ARCH_METANOIA Kconfig entry (patch 15) and on the binding compatibles
being accepted. The patches can therefore go through their respective
subsystem trees, with the Kconfig, DTS and MAINTAINERS patches going
through the RISC-V tree once the driver and binding patches have landed.

The series is based on v7.4-rc1.

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
Benoît Monin (25):
      dt-bindings: vendor-prefixes: add Metanoia Communications
      dt-bindings: riscv: add Metanoia SoC-based boards
      dt-bindings: reset: add Metanoia MT2824
      dt-bindings: power: reset: add Metanoia MT2824 reboot
      dt-bindings: phy: add Metanoia USB2 PHY
      dt-bindings: cache: andestech,ax45mp-cache: add MT2824 compatible
      dt-bindings: interrupt-controller: sifive,plic-1.0.0: add Metanoia MT2824
      dt-bindings: interrupt-controller: andestech,plicsw: add Metanoia MT2824
      dt-bindings: timer: andestech,plmt0: add Metanoia MT2824
      dt-bindings: mmc: snps,dwcmshc-sdhci: add Metanoia MT2824
      dt-bindings: spi: andestech,ae350-spi: make DMA and interrupts optional
      dt-bindings: spi: andestech,ae350-spi: add Metanoia MT2824
      dt-bindings: usb: dwc2: add Metanoia MT2824
      dt-bindings: watchdog: andestech,ae350-wdt: add Metanoia MT2824
      riscv: add ARCH_METANOIA Kconfig entry
      reset: simple: add Metanoia MT2824 support
      spi: atcspi200: add optional interrupt support
      spi: atcspi200: allow building for Metanoia SoCs
      watchdog: atcwdt200: allow building for Metanoia SoCs
      mmc: sdhci-of-dwcmshc: add MT2824 support
      mmc: sdhci-of-dwcmshc: add MT2824 tuning and HS400 support
      phy: metanoia: add USB2 PHY driver
      usb: dwc2: add support for Metanoia MT2824
      riscv: add Metanoia MT2824 SoC and MT5824 EVB support
      MAINTAINERS: add RISC-V Metanoia SoC support

 .../bindings/cache/andestech,ax45mp-cache.yaml     |   1 +
 .../interrupt-controller/andestech,plicsw.yaml     |   1 +
 .../interrupt-controller/sifive,plic-1.0.0.yaml    |   1 +
 .../bindings/mmc/snps,dwcmshc-sdhci.yaml           |   1 +
 .../devicetree/bindings/phy/metanoia,usb2-phy.yaml |  43 ++
 .../bindings/power/reset/metanoia,reboot.yaml      |  34 +
 .../devicetree/bindings/reset/metanoia,reset.yaml  |  40 ++
 .../devicetree/bindings/riscv/metanoia.yaml        |  25 +
 .../bindings/spi/andestech,ae350-spi.yaml          |   9 +-
 .../devicetree/bindings/timer/andestech,plmt0.yaml |   1 +
 Documentation/devicetree/bindings/usb/dwc2.yaml    |   1 +
 .../devicetree/bindings/vendor-prefixes.yaml       |   2 +
 .../bindings/watchdog/andestech,ae350-wdt.yaml     |   1 +
 MAINTAINERS                                        |  11 +
 arch/riscv/Kconfig.socs                            |   8 +
 arch/riscv/boot/dts/Makefile                       |   1 +
 arch/riscv/boot/dts/metanoia/Makefile              |   2 +
 arch/riscv/boot/dts/metanoia/mt2824.dtsi           | 330 ++++++++++
 arch/riscv/boot/dts/metanoia/mt5824-evb.dts        |  81 +++
 drivers/mmc/host/Kconfig                           |   1 +
 drivers/mmc/host/sdhci-of-dwcmshc.c                | 704 +++++++++++++++++++++
 drivers/phy/Kconfig                                |   1 +
 drivers/phy/Makefile                               |   1 +
 drivers/phy/metanoia/Kconfig                       |  16 +
 drivers/phy/metanoia/Makefile                      |   3 +
 drivers/phy/metanoia/phy-usb2.c                    |  88 +++
 drivers/reset/Kconfig                              |   2 +-
 drivers/reset/reset-simple.c                       |   1 +
 drivers/spi/Kconfig                                |   2 +-
 drivers/spi/spi-atcspi200.c                        | 255 +++++++-
 drivers/usb/dwc2/params.c                          |  13 +
 drivers/watchdog/Kconfig                           |   2 +-
 32 files changed, 1667 insertions(+), 15 deletions(-)
---
base-commit: 6628e7d4c6b25c8d18f1345e3a20d21829aae7e4
change-id: 20261016-mt2824-32a77a241798

Best regards,
--  
Benoît Monin, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com