From: Rosen Penev <rosenp@gmail.com>
To: netdev@vger.kernel.org
Cc: Chris Snook <chris.snook@gmail.com>,
Andrew Lunn <andrew+netdev@lunn.ch>,
"David S. Miller" <davem@davemloft.net>,
Eric Dumazet <edumazet@kernel.org>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Russell King <linux@armlinux.org.uk>,
Oleksij Rempel <o.rempel@pengutronix.de>,
linux-kernel@vger.kernel.org (open list)
Subject: [PATCH net] net: ag71xx: let both QCA9550 MACs use MII, RGMII and SGMII
Date: Fri, 6 Nov 2026 14:16:07 -0800 [thread overview]
Message-ID: <20261106221607.16215-1-rosenp@gmail.com> (raw)
The GE0_SGMII bit of the QCA955x ETH_CFG register selects which GMAC
gets the SerDes (QCA9558 datasheet, 10.8.1): when it is clear, GMAC0
connects as RGMII/MII and GMAC1 as SGMII, and when it is set, the other
way around. The driver only allows the second layout, with SGMII on
GMAC0 and RGMII/MII on GMAC1, but boards like the TP-Link Archer C7
use the first one, with GMAC0 on RGMII.
Allow MII, RGMII and SGMII on both MACs.
Tested on Archer C7 v2. RGMII on port 0 of the switch works.
Fixes: 0767ec042897 ("net: ag71xx: extend link validation to support other SoCs")
Signed-off-by: Rosen Penev <rosenp@gmail.com>
---
drivers/net/ethernet/atheros/ag71xx.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/net/ethernet/atheros/ag71xx.c b/drivers/net/ethernet/atheros/ag71xx.c
index 16434a7139bc..b2d78819a0a2 100644
--- a/drivers/net/ethernet/atheros/ag71xx.c
+++ b/drivers/net/ethernet/atheros/ag71xx.c
@@ -1079,7 +1079,7 @@ static int ag71xx_phylink_setup(struct ag71xx *ag)
if ((ag71xx_is(ag, AR9330) && ag->mac_idx == 0) ||
ag71xx_is(ag, AR9340) ||
ag71xx_is(ag, QCA9530) ||
- (ag71xx_is(ag, QCA9550) && ag->mac_idx == 1))
+ ag71xx_is(ag, QCA9550))
__set_bit(PHY_INTERFACE_MODE_MII,
ag->phylink_config.supported_interfaces);
@@ -1089,7 +1089,7 @@ static int ag71xx_phylink_setup(struct ag71xx *ag)
__set_bit(PHY_INTERFACE_MODE_GMII,
ag->phylink_config.supported_interfaces);
- if (ag71xx_is(ag, QCA9550) && ag->mac_idx == 0)
+ if (ag71xx_is(ag, QCA9550))
__set_bit(PHY_INTERFACE_MODE_SGMII,
ag->phylink_config.supported_interfaces);
@@ -1098,7 +1098,7 @@ static int ag71xx_phylink_setup(struct ag71xx *ag)
ag->phylink_config.supported_interfaces);
if ((ag71xx_is(ag, AR9340) && ag->mac_idx == 0) ||
- (ag71xx_is(ag, QCA9550) && ag->mac_idx == 1))
+ ag71xx_is(ag, QCA9550))
__set_bit(PHY_INTERFACE_MODE_RGMII,
ag->phylink_config.supported_interfaces);
--
2.56.0
reply other threads:[~2026-11-06 22:16 UTC|newest]
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