From: Shan-Chun Hung <shanchun1218@gmail.com>
To: ychuang3@nuvoton.com, schung@nuvoton.com, vkoul@kernel.org,
Frank.Li@kernel.org, robh@kernel.org, krzk+dt@kernel.org,
conor+dt@kernel.org, kees@kernel.org, gustavoars@kernel.org,
linux-arm-kernel@lists.infradead.org, dmaengine@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-hardening@vger.kernel.org
Cc: Shan-Chun Hung <shanchun1218@gmail.com>
Subject: [PATCH v2 1/2] dt-bindings: dma: nuvoton,ma35d1-pdma: Document MA35D1 PDMA controller
Date: Mon, 9 Nov 2026 13:28:59 +0800 [thread overview]
Message-ID: <20261109052900.2960473-2-shanchun1218@gmail.com> (raw)
In-Reply-To: <20261109052900.2960473-1-shanchun1218@gmail.com>
Add binding for Nuvoton MA35D1 PDMA controller.
Signed-off-by: Shan-Chun Hung <shanchun1218@gmail.com>
---
.../bindings/dma/nuvoton,ma35d1-pdma.yaml | 71 +++++++++++++++++++
1 file changed, 71 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/nuvoton,ma35d1-pdma.yaml
diff --git a/Documentation/devicetree/bindings/dma/nuvoton,ma35d1-pdma.yaml b/Documentation/devicetree/bindings/dma/nuvoton,ma35d1-pdma.yaml
new file mode 100644
index 000000000000..d05971662a5d
--- /dev/null
+++ b/Documentation/devicetree/bindings/dma/nuvoton,ma35d1-pdma.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/dma/nuvoton,ma35d1-pdma.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Nuvoton MA35D1 PDMA controller
+
+description:
+ The MA35D1 SoC has four Peripheral DMA (PDMA) controllers. Each controller
+ has 10 channels and performs memory-to-memory, memory-to-peripheral and
+ peripheral-to-memory transfers.
+
+maintainers:
+ - Shan-Chun Hung <shanchun1218@gmail.com>
+
+allOf:
+ - $ref: dma-controller.yaml#
+
+properties:
+ compatible:
+ const: nuvoton,ma35d1-pdma
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ "#dma-cells":
+ const: 2
+ description:
+ The first cell is the PDMA channel number. The second cell is the
+ peripheral request source number, as listed in the reference manual.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - interrupts
+ - "#dma-cells"
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/nuvoton,ma35d1-clk.h>
+ #include <dt-bindings/reset/nuvoton,ma35d1-reset.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ dma-controller@40080000 {
+ compatible = "nuvoton,ma35d1-pdma";
+ reg = <0x0 0x40080000 0x0 0x2000>;
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk PDMA0_GATE>;
+ resets = <&sys MA35D1_RESET_PDMA0>;
+ #dma-cells = <2>;
+ };
+ };
+
+...
--
2.25.1
next prev parent reply other threads:[~2026-11-09 5:29 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-09 5:28 [PATCH v2 0/2] dmaengine: ma35d1-pdma: Add MA35D1 PDMA driver Shan-Chun Hung
2026-11-09 5:28 ` Shan-Chun Hung [this message]
2026-11-09 5:29 ` [PATCH v2 2/2] " Shan-Chun Hung
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