From: Troy Mitchell <troy.mitchell@linux.dev>
To: "Anup Patel" <anup@brainfault.org>,
"Thomas Gleixner" <tglx@kernel.org>,
"Radu Rendec" <radu@rendec.net>, "Paul Walmsley" <pjw@kernel.org>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Alexandre Ghiti" <alex@ghiti.fr>,
"Björn Töpel" <bjorn@rivosinc.com>
Cc: Anup Patel <apatel@ventanamicro.com>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
Troy Mitchell <troy.mitchell@linux.dev>
Subject: [PATCH v2 2/2] irqchip/riscv-aplic: Apply pending affinity changes for level MSI sources
Date: Tue, 10 Nov 2026 12:06:30 +0000 [thread overview]
Message-ID: <20261110-aplic-affinity-fix-v2-2-6c143b8b4e8c@linux.dev> (raw)
In-Reply-To: <20261110-aplic-affinity-fix-v2-0-6c143b8b4e8c@linux.dev>
IMSIC rejects an affinity change with -EBUSY while a previous vector
move is still in flight, and the IRQ core then records the new mask as
pending. The change is applied by irq_move_irq() in the IMSIC irq_ack
callback, but level-triggered APLIC MSI interrupts are handled by
handle_fasteoi_irq(), which never calls irq_ack.
The pending change is therefore never applied. While it is pending,
later affinity changes only update the pending mask, so the interrupt
stays on its old CPU.
Use handle_fasteoi_ack_irq() for level-triggered sources. It acks the
interrupt before invoking the handler, so a pending affinity change is
applied on the next interrupt, and the EOI retrigger then targets the
new CPU.
Fixes: 58d868b67a9a ("RISC-V: Select CONFIG_GENERIC_PENDING_IRQ")
Signed-off-by: Troy Mitchell <troy.mitchell@linux.dev>
---
drivers/irqchip/Kconfig | 1 +
drivers/irqchip/irq-riscv-aplic-msi.c | 7 +++++--
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index 136bab41f801..a639a0c2f3d2 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -645,6 +645,7 @@ config RISCV_APLIC_MSI
bool
depends on RISCV_APLIC
select GENERIC_MSI_IRQ
+ select IRQ_FASTEOI_HIERARCHY_HANDLERS
default RISCV_APLIC
config RISCV_IMSIC
diff --git a/drivers/irqchip/irq-riscv-aplic-msi.c b/drivers/irqchip/irq-riscv-aplic-msi.c
index 44f0df83f93e..0e71b427da34 100644
--- a/drivers/irqchip/irq-riscv-aplic-msi.c
+++ b/drivers/irqchip/irq-riscv-aplic-msi.c
@@ -75,13 +75,16 @@ static int aplic_msi_irq_set_type(struct irq_data *d, unsigned int type)
* acknowledged before the handler runs. The edge flow handler also
* replays an interrupt which arrives while the previous one is
* still being handled on another CPU after an affinity change.
+ *
+ * Level-triggered sources use the fasteoi flow, but still need the
+ * ack so that the IMSIC parent applies deferred affinity changes.
*/
if (type & IRQ_TYPE_EDGE_BOTH)
irq_set_chip_handler_name_locked(d, irq_data_get_irq_chip(d),
handle_edge_irq, "edge");
else
irq_set_chip_handler_name_locked(d, irq_data_get_irq_chip(d),
- handle_fasteoi_irq, "fasteoi");
+ handle_fasteoi_ack_irq, "fasteoi");
/*
* Updating sourcecfg register for level-triggered interrupts
@@ -181,7 +184,7 @@ static const struct msi_domain_template aplic_msi_template = {
.info = {
.bus_token = DOMAIN_BUS_WIRED_TO_MSI,
.flags = MSI_FLAG_USE_DEV_FWNODE,
- .handler = handle_fasteoi_irq,
+ .handler = handle_fasteoi_ack_irq,
.handler_name = "fasteoi",
},
};
--
2.56.0
prev parent reply other threads:[~2026-11-10 12:06 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-10 12:06 [PATCH v2 0/2] irqchip/riscv-aplic: Use trigger specific flow handlers in MSI mode Troy Mitchell
2026-11-10 12:06 ` [PATCH v2 1/2] irqchip/riscv-aplic: Use handle_edge_irq() for edge-triggered MSI sources Troy Mitchell
2026-11-10 12:06 ` Troy Mitchell [this message]
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