[PATCH v3 0/2] serial: 8250_of: RS-485 on Microchip Core16550

[PATCH v3 0/2] serial: 8250_of: RS-485 on Microchip Core16550

[Kohei Otsuka via B4 Relay]

Core16550 is a 16550-compatible UART soft IP for Microchip FPGAs. We use
four of them in the fabric of a PolarFire SoC Icicle Kit as RS-485
ports, described as "ns16550a" with linux,rs485-enabled-at-boot-time.
With RS-485 enabled, RTS (the transceiver's driver enable) goes high at
the start of the first transmission and never drops, and the port stops
receiving. Core16550, like the original 16550A, raises no interrupt on
TEMT, so __stop_tx() waits for one forever unless the port has
UART_CAP_NOTEMT, which 8250_of never sets.

Testing, on a PolarFire SoC Icicle Kit with four Core16550 instances
on FIC3 (PCLK 50 MHz), linux-mchp 6.18.17 with this series applied
and the ports described as "microchip,core16550-rtl-v3",
115200 8N1, against USB-RS485 (2-wire, half duplex) and USB-RS422
(4-wire) converters:
- All four ports transmit and receive correctly with both converters.
- On RS-485, each port keeps receiving after transmitting, across
  repeated request/response exchanges in both directions.
- Without the series, RTS stays high after the first transmission and
  nothing more is received.

This series was prepared with the help of an AI coding assistant
(Claude, Anthropic): the analysis of __stop_tx(), both patches and
these messages. I reviewed and tested the result and take
responsibility for it.

Link: https://github.com/linux4microchip/meta-mchp/issues/5

Signed-off-by: Kohei Otsuka <kohei@spacemachines.com>
---
Changes in v3:
- dt-bindings: drop the ns16550a fallback, as the generic driver leaves
  RTS asserted in RS-485 mode (Conor)
- 8250_of: match microchip,core16550-rtl-v3 directly, as a PORT_16550A,
  and retitle the patch to match
- Link to v2: https://patch.msgid.link/20261109-core16550-rs485-v2-0-a15933c7b907@spacemachines.com

Changes in v2:
- dt-bindings: rename the compatible to microchip,core16550-rtl-v3,
  following the -rtl-vN convention of Microchip's other fabric cores
  (Conor)
- dt-bindings: explain in the commit message why ns16550a remains a
  valid fallback (Conor)
- 8250_of: match microchip,core16550-rtl-v3
- Dropped Krzysztof's Acked-by on 1/2, as the compatible changed
- Link to v1: https://patch.msgid.link/20261103-core16550-rs485-v1-0-6d15ebe1e5b9@spacemachines.com

To: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
To: Jiri Slaby <jirislaby@kernel.org>
To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
To: Lubomir Rintel <lkundrak@v3.sk>
To: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-serial@vger.kernel.org

---
Kohei Otsuka (2):
      dt-bindings: serial: 8250: add Microchip Core16550
      serial: 8250_of: add Microchip Core16550

 Documentation/devicetree/bindings/serial/8250.yaml |  1 +
 drivers/tty/serial/8250/8250_of.c                  | 12 ++++++++++++
 2 files changed, 13 insertions(+)
---
base-commit: c339f4010dea8b0d754f84ace70cd1b089878ef8
change-id: 20261103-core16550-rs485-505af0ffaeeb

Best regards,
--  
Kohei Otsuka <kohei@spacemachines.com>

[PATCH v3 1/2] dt-bindings: serial: 8250: add Microchip Core16550

[Kohei Otsuka via B4 Relay]

From: Kohei Otsuka <kohei@spacemachines.com>

Core16550 is a 16550-compatible UART soft IP core for Microchip FPGAs,
including the fabric of PolarFire SoC. Its registers follow the 16550A,
but it raises no interrupt on TEMT. A driver that knows only ns16550a
waits for one in software RS-485 mode (em485), so RTS stays asserted
after the first frame and the port stops receiving. ns16550a is
therefore not a valid fallback.

Add microchip,core16550-rtl-v3 as a compatible of its own. As for
Microchip's other FPGA fabric cores, the -rtl-v3 suffix is the major
RTL version of the IP, Core16550 3.x.

Link: https://github.com/linux4microchip/meta-mchp/issues/5
Signed-off-by: Kohei Otsuka <kohei@spacemachines.com>
---
 Documentation/devicetree/bindings/serial/8250.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml
index 50d5c977afa3..d9ee14f7b694 100644
--- a/Documentation/devicetree/bindings/serial/8250.yaml
+++ b/Documentation/devicetree/bindings/serial/8250.yaml
@@ -111,6 +111,7 @@ properties:
           - aspeed,ast2400-vuart
           - aspeed,ast2500-vuart
           - intel,xscale-uart
+          - microchip,core16550-rtl-v3
           - mrvl,pxa-uart
           - nuvoton,npcm750-uart
           - nuvoton,wpcm450-uart

-- 
2.53.0

Re: [PATCH v3 1/2] dt-bindings: serial: 8250: add Microchip Core16550

[Conor Dooley]

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On Tue, Nov 10, 2026 at 09:06:48AM +1100, Kohei Otsuka via B4 Relay wrote:
> From: Kohei Otsuka <kohei@spacemachines.com>
> 
> Core16550 is a 16550-compatible UART soft IP core for Microchip FPGAs,
> including the fabric of PolarFire SoC. Its registers follow the 16550A,
> but it raises no interrupt on TEMT. A driver that knows only ns16550a
> waits for one in software RS-485 mode (em485), so RTS stays asserted
> after the first frame and the port stops receiving. ns16550a is
> therefore not a valid fallback.
> 
> Add microchip,core16550-rtl-v3 as a compatible of its own. As for
> Microchip's other FPGA fabric cores, the -rtl-v3 suffix is the major
> RTL version of the IP, Core16550 3.x.
> 
> Link: https://github.com/linux4microchip/meta-mchp/issues/5
> Signed-off-by: Kohei Otsuka <kohei@spacemachines.com>

With both dt-binding maintainer and microchip fpga hats on:
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable

Thanks,
Conor.

> ---
>  Documentation/devicetree/bindings/serial/8250.yaml | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml
> index 50d5c977afa3..d9ee14f7b694 100644
> --- a/Documentation/devicetree/bindings/serial/8250.yaml
> +++ b/Documentation/devicetree/bindings/serial/8250.yaml
> @@ -111,6 +111,7 @@ properties:
>            - aspeed,ast2400-vuart
>            - aspeed,ast2500-vuart
>            - intel,xscale-uart
> +          - microchip,core16550-rtl-v3
>            - mrvl,pxa-uart
>            - nuvoton,npcm750-uart
>            - nuvoton,wpcm450-uart
> 
> -- 
> 2.53.0
> 
> 
> 

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[PATCH v3 2/2] serial: 8250_of: add Microchip Core16550

[Kohei Otsuka via B4 Relay]

From: Kohei Otsuka <kohei@spacemachines.com>

Core16550, a 16550-compatible UART for Microchip FPGAs, interrupts on
THRE but not on TEMT. When the last character moves from the FIFO into
the shift register, the THRE interrupt calls __stop_tx(), which finds
TEMT clear and, without UART_CAP_NOTEMT, returns to wait for a TEMT
interrupt that never comes. RTS, and with it the RS-485 driver enable,
then stays asserted after the frame, and receive interrupts, disabled
for the half-duplex transmission, stay off.

Match "microchip,core16550-rtl-v3" as a PORT_16550A, and set
UART_CAP_NOTEMT for it, so em485 drops RTS from its stop timer one
frame time (plus 1/7) after THRE, as it does for DesignWare UARTs.

Set UART_CAP_FIFO as well: with the capabilities already non-zero,
serial8250_do_startup() no longer fills in the PORT_16550A default,
and without UART_CAP_FIFO serial8250_clear_fifos() does nothing, so
the RX FIFO is not flushed at the end of a half-duplex transmission.

Link: https://github.com/linux4microchip/meta-mchp/issues/5
Signed-off-by: Kohei Otsuka <kohei@spacemachines.com>
---
 drivers/tty/serial/8250/8250_of.c | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/drivers/tty/serial/8250/8250_of.c b/drivers/tty/serial/8250/8250_of.c
index b41ca604083f..9d92668d7772 100644
--- a/drivers/tty/serial/8250/8250_of.c
+++ b/drivers/tty/serial/8250/8250_of.c
@@ -278,6 +278,16 @@ static int of_platform_serial_probe(struct platform_device *ofdev)
 	if (port8250.port.fifosize)
 		port8250.capabilities = UART_CAP_FIFO;
 
+	/*
+	 * Core16550 has no TEMT interrupt: without UART_CAP_NOTEMT the em485
+	 * code waits for one after the last THRE interrupt and never drops RTS.
+	 * Set UART_CAP_FIFO too, because a non-zero value stops
+	 * serial8250_do_startup() filling in the PORT_16550A default.
+	 */
+	if (of_device_is_compatible(ofdev->dev.of_node,
+				    "microchip,core16550-rtl-v3"))
+		port8250.capabilities |= UART_CAP_FIFO | UART_CAP_NOTEMT;
+
 	/* Check for TX FIFO threshold & set tx_loadsz */
 	if ((of_property_read_u32(ofdev->dev.of_node, "tx-threshold",
 				  &tx_threshold) == 0) &&
@@ -398,6 +408,8 @@ static const struct of_device_id of_platform_serial_table[] = {
 		.data = (void *)PORT_16550A_FSL64, },
 	{ .compatible = "mediatek,mtk-btif",
 		.data = (void *)PORT_MTK_BTIF, },
+	{ .compatible = "microchip,core16550-rtl-v3",
+		.data = (void *)PORT_16550A, },
 	{ .compatible = "mrvl,mmp-uart",
 		.data = (void *)PORT_XSCALE, },
 	{ .compatible = "ti,da830-uart", .data = (void *)PORT_DA830, },

-- 
2.53.0